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rtl-llm
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chisel-verilog-pairs

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Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File PMP.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Cat, log2Ceil} import org.chipsalliance.cde.config._ import freechips.rocketchip.tile._ import freechips.rocketchip.util._ class PMPConfig extends Bundle { val l = Bool() val res = UInt(2.W) val a = UInt(2.W) val x = Bool() val w = Bool() val r = Bool() } object PMP { def lgAlign = 2 def apply(reg: PMPReg): PMP = { val pmp = Wire(new PMP()(reg.p)) pmp.cfg := reg.cfg pmp.addr := reg.addr pmp.mask := pmp.computeMask pmp } } class PMPReg(implicit p: Parameters) extends CoreBundle()(p) { val cfg = new PMPConfig val addr = UInt((paddrBits - PMP.lgAlign).W) def reset(): Unit = { cfg.a := 0.U cfg.l := 0.U } def readAddr = if (pmpGranularity.log2 == PMP.lgAlign) addr else { val mask = ((BigInt(1) << (pmpGranularity.log2 - PMP.lgAlign)) - 1).U Mux(napot, addr \| (mask >> 1), ~(~addr \| mask)) } def napot = cfg.a(1) def torNotNAPOT = cfg.a(0) def tor = !napot && torNotNAPOT def cfgLocked = cfg.l def addrLocked(next: PMPReg) = cfgLocked \|\| next.cfgLocked && next.tor } class PMP(implicit p: Parameters) extends PMPReg { val mask = UInt(paddrBits.W) import PMP._ def computeMask = { val base = Cat(addr, cfg.a(0)) \| ((pmpGranularity - 1).U >> lgAlign) Cat(base & ~(base + 1.U), ((1 << lgAlign) - 1).U) } private def comparand = ~(~(addr << lgAlign) \| (pmpGranularity - 1).U) private def pow2Match(x: UInt, lgSize: UInt, lgMaxSize: Int) = { def eval(a: UInt, b: UInt, m: UInt) = ((a ^ b) & ~m) === 0.U if (lgMaxSize <= pmpGranularity.log2) { eval(x, comparand, mask) } else { // break up the circuit; the MSB part will be CSE'd val lsbMask = mask \| UIntToOH1(lgSize, lgMaxSize) val msbMatch = eval(x >> lgMaxSize, comparand >> lgMaxSize, mask >> lgMaxSize) val lsbMatch = eval(x(lgMaxSize-1, 0), comparand(lgMaxSize-1, 0), lsbMask(lgMaxSize-1, 0)) msbMatch && lsbMatch } } private def boundMatch(x: UInt, lsbMask: UInt, lgMaxSize: Int) = { if (lgMaxSize <= pmpGranularity.log2) { x < comparand } else { // break up the circuit; the MSB part will be CSE'd val msbsLess = (x >> lgMaxSize) < (comparand >> lgMaxSize) val msbsEqual = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U val lsbsLess = (x(lgMaxSize-1, 0) \| lsbMask) < comparand(lgMaxSize-1, 0) msbsLess \|\| (msbsEqual && lsbsLess) } } private def lowerBoundMatch(x: UInt, lgSize: UInt, lgMaxSize: Int) = !boundMatch(x, UIntToOH1(lgSize, lgMaxSize), lgMaxSize) private def upperBoundMatch(x: UInt, lgMaxSize: Int) = boundMatch(x, 0.U, lgMaxSize) private def rangeMatch(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP) = prev.lowerBoundMatch(x, lgSize, lgMaxSize) && upperBoundMatch(x, lgMaxSize) private def pow2Homogeneous(x: UInt, pgLevel: UInt) = { val maskHomogeneous = pgLevelMap { idxBits => if (idxBits > paddrBits) false.B else mask(idxBits - 1) } (pgLevel) maskHomogeneous \|\| (pgLevelMap { idxBits => ((x ^ comparand) >> idxBits) =/= 0.U } (pgLevel)) } private def pgLevelMap[T](f: Int => T) = (0 until pgLevels).map { i => f(pgIdxBits + (pgLevels - 1 - i) pgLevelBits) } private def rangeHomogeneous(x: UInt, pgLevel: UInt, prev: PMP) = { val beginsAfterLower = !(x < prev.comparand) val beginsAfterUpper = !(x < comparand) val pgMask = pgLevelMap { idxBits => (((BigInt(1) << paddrBits) - (BigInt(1) << idxBits)) max 0).U } (pgLevel) val endsBeforeLower = (x & pgMask) < (prev.comparand & pgMask) val endsBeforeUpper = (x & pgMask) < (comparand & pgMask) endsBeforeLower \|\| beginsAfterUpper \|\| (beginsAfterLower && endsBeforeUpper) } // returns whether this PMP completely contains, or contains none of, a page def homogeneous(x: UInt, pgLevel: UInt, prev: PMP): Bool = Mux(napot, pow2Homogeneous(x, pgLevel), !torNotNAPOT \|\| rangeHomogeneous(x, pgLevel, prev)) // returns whether this matching PMP fully contains the access def aligned(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = if (lgMaxSize <= pmpGranularity.log2) true.B else { val lsbMask = UIntToOH1(lgSize, lgMaxSize) val straddlesLowerBound = ((x >> lgMaxSize) ^ (prev.comparand >> lgMaxSize)) === 0.U && (prev.comparand(lgMaxSize-1, 0) & ~x(lgMaxSize-1, 0)) =/= 0.U val straddlesUpperBound = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U && (comparand(lgMaxSize-1, 0) & (x(lgMaxSize-1, 0) \| lsbMask)) =/= 0.U val rangeAligned = !(straddlesLowerBound \|\| straddlesUpperBound) val pow2Aligned = (lsbMask & ~mask(lgMaxSize-1, 0)) === 0.U Mux(napot, pow2Aligned, rangeAligned) } // returns whether this PMP matches at least one byte of the access def hit(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = Mux(napot, pow2Match(x, lgSize, lgMaxSize), torNotNAPOT && rangeMatch(x, lgSize, lgMaxSize, prev)) } class PMPHomogeneityChecker(pmps: Seq[PMP])(implicit p: Parameters) { def apply(addr: UInt, pgLevel: UInt): Bool = { pmps.foldLeft((true.B, 0.U.asTypeOf(new PMP))) { case ((h, prev), pmp) => (h && pmp.homogeneous(addr, pgLevel, prev), pmp) }._1 } } class PMPChecker(lgMaxSize: Int)(implicit val p: Parameters) extends Module with HasCoreParameters { override def desiredName = s"PMPChecker_s${lgMaxSize}" val io = IO(new Bundle { val prv = Input(UInt(PRV.SZ.W)) val pmp = Input(Vec(nPMPs, new PMP)) val addr = Input(UInt(paddrBits.W)) val size = Input(UInt(log2Ceil(lgMaxSize + 1).W)) val r = Output(Bool()) val w = Output(Bool()) val x = Output(Bool()) }) val default = if (io.pmp.isEmpty) true.B else io.prv > PRV.S.U val pmp0 = WireInit(0.U.asTypeOf(new PMP)) pmp0.cfg.r := default pmp0.cfg.w := default pmp0.cfg.x := default val res = (io.pmp zip (pmp0 +: io.pmp)).reverse.foldLeft(pmp0) { case (prev, (pmp, prevPMP)) => val hit = pmp.hit(io.addr, io.size, lgMaxSize, prevPMP) val ignore = default && !pmp.cfg.l val aligned = pmp.aligned(io.addr, io.size, lgMaxSize, prevPMP) for ((name, idx) <- Seq("no", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) property.cover(pmp.cfg.a === idx.U, s"The cfg access is set to ${name} access ", "Cover PMP access mode setting") property.cover(pmp.cfg.l === 0x1.U, s"The cfg lock is set to high ", "Cover PMP lock mode setting") // Not including Write and no Read permission as the combination is reserved for ((name, idx) <- Seq("no", "RO", "", "RW", "X", "RX", "", "RWX").zipWithIndex; if name.nonEmpty) property.cover((Cat(pmp.cfg.x, pmp.cfg.w, pmp.cfg.r) === idx.U), s"The permission is set to ${name} access ", "Cover PMP access permission setting") for ((name, idx) <- Seq("", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) { property.cover(!ignore && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode ", "Cover PMP access") property.cover(pmp.cfg.l && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode with lock bit high", "Cover PMP access with lock bit") } val cur = WireInit(pmp) cur.cfg.r := aligned && (pmp.cfg.r \|\| ignore) cur.cfg.w := aligned && (pmp.cfg.w \|\| ignore) cur.cfg.x := aligned && (pmp.cfg.x \|\| ignore) Mux(hit, cur, prev) } io.r := res.cfg.r io.w := res.cfg.w io.x := res.cfg.x }	module PMPChecker_s2_7( // @[PMP.scala:143:7] input clock, // @[PMP.scala:143:7] input reset, // @[PMP.scala:143:7] input [1:0] io_prv, // @[PMP.scala:146:14] input io_pmp_0_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_0_cfg_a, // @[PMP.scala:146:14] input io_pmp_0_cfg_x, // @[PMP.scala:146:14] input io_pmp_0_cfg_w, // @[PMP.scala:146:14] input io_pmp_0_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_0_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_0_mask, // @[PMP.scala:146:14] input io_pmp_1_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_1_cfg_a, // @[PMP.scala:146:14] input io_pmp_1_cfg_x, // @[PMP.scala:146:14] input io_pmp_1_cfg_w, // @[PMP.scala:146:14] input io_pmp_1_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_1_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_1_mask, // @[PMP.scala:146:14] input io_pmp_2_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_2_cfg_a, // @[PMP.scala:146:14] input io_pmp_2_cfg_x, // @[PMP.scala:146:14] input io_pmp_2_cfg_w, // @[PMP.scala:146:14] input io_pmp_2_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_2_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_2_mask, // @[PMP.scala:146:14] input io_pmp_3_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_3_cfg_a, // @[PMP.scala:146:14] input io_pmp_3_cfg_x, // @[PMP.scala:146:14] input io_pmp_3_cfg_w, // @[PMP.scala:146:14] input io_pmp_3_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_3_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_3_mask, // @[PMP.scala:146:14] input io_pmp_4_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_4_cfg_a, // @[PMP.scala:146:14] input io_pmp_4_cfg_x, // @[PMP.scala:146:14] input io_pmp_4_cfg_w, // @[PMP.scala:146:14] input io_pmp_4_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_4_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_4_mask, // @[PMP.scala:146:14] input io_pmp_5_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_5_cfg_a, // @[PMP.scala:146:14] input io_pmp_5_cfg_x, // @[PMP.scala:146:14] input io_pmp_5_cfg_w, // @[PMP.scala:146:14] input io_pmp_5_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_5_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_5_mask, // @[PMP.scala:146:14] input io_pmp_6_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_6_cfg_a, // @[PMP.scala:146:14] input io_pmp_6_cfg_x, // @[PMP.scala:146:14] input io_pmp_6_cfg_w, // @[PMP.scala:146:14] input io_pmp_6_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_6_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_6_mask, // @[PMP.scala:146:14] input io_pmp_7_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_7_cfg_a, // @[PMP.scala:146:14] input io_pmp_7_cfg_x, // @[PMP.scala:146:14] input io_pmp_7_cfg_w, // @[PMP.scala:146:14] input io_pmp_7_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_7_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_7_mask, // @[PMP.scala:146:14] input [31:0] io_addr, // @[PMP.scala:146:14] output io_r, // @[PMP.scala:146:14] output io_w, // @[PMP.scala:146:14] output io_x // @[PMP.scala:146:14] ); wire [1:0] io_prv_0 = io_prv; // @[PMP.scala:143:7] wire io_pmp_0_cfg_l_0 = io_pmp_0_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_0_cfg_a_0 = io_pmp_0_cfg_a; // @[PMP.scala:143:7] wire io_pmp_0_cfg_x_0 = io_pmp_0_cfg_x; // @[PMP.scala:143:7] wire io_pmp_0_cfg_w_0 = io_pmp_0_cfg_w; // @[PMP.scala:143:7] wire io_pmp_0_cfg_r_0 = io_pmp_0_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_0_addr_0 = io_pmp_0_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_0_mask_0 = io_pmp_0_mask; // @[PMP.scala:143:7] wire io_pmp_1_cfg_l_0 = io_pmp_1_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_1_cfg_a_0 = io_pmp_1_cfg_a; // @[PMP.scala:143:7] wire io_pmp_1_cfg_x_0 = io_pmp_1_cfg_x; // @[PMP.scala:143:7] wire io_pmp_1_cfg_w_0 = io_pmp_1_cfg_w; // @[PMP.scala:143:7] wire io_pmp_1_cfg_r_0 = io_pmp_1_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_1_addr_0 = io_pmp_1_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_1_mask_0 = io_pmp_1_mask; // @[PMP.scala:143:7] wire io_pmp_2_cfg_l_0 = io_pmp_2_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_2_cfg_a_0 = io_pmp_2_cfg_a; // @[PMP.scala:143:7] wire io_pmp_2_cfg_x_0 = io_pmp_2_cfg_x; // @[PMP.scala:143:7] wire io_pmp_2_cfg_w_0 = io_pmp_2_cfg_w; // @[PMP.scala:143:7] wire io_pmp_2_cfg_r_0 = io_pmp_2_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_2_addr_0 = io_pmp_2_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_2_mask_0 = io_pmp_2_mask; // @[PMP.scala:143:7] wire io_pmp_3_cfg_l_0 = io_pmp_3_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_3_cfg_a_0 = io_pmp_3_cfg_a; // @[PMP.scala:143:7] wire io_pmp_3_cfg_x_0 = io_pmp_3_cfg_x; // @[PMP.scala:143:7] wire io_pmp_3_cfg_w_0 = io_pmp_3_cfg_w; // @[PMP.scala:143:7] wire io_pmp_3_cfg_r_0 = io_pmp_3_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_3_addr_0 = io_pmp_3_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_3_mask_0 = io_pmp_3_mask; // @[PMP.scala:143:7] wire io_pmp_4_cfg_l_0 = io_pmp_4_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_4_cfg_a_0 = io_pmp_4_cfg_a; // @[PMP.scala:143:7] wire io_pmp_4_cfg_x_0 = io_pmp_4_cfg_x; // @[PMP.scala:143:7] wire io_pmp_4_cfg_w_0 = io_pmp_4_cfg_w; // @[PMP.scala:143:7] wire io_pmp_4_cfg_r_0 = io_pmp_4_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_4_addr_0 = io_pmp_4_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_4_mask_0 = io_pmp_4_mask; // @[PMP.scala:143:7] wire io_pmp_5_cfg_l_0 = io_pmp_5_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_5_cfg_a_0 = io_pmp_5_cfg_a; // @[PMP.scala:143:7] wire io_pmp_5_cfg_x_0 = io_pmp_5_cfg_x; // @[PMP.scala:143:7] wire io_pmp_5_cfg_w_0 = io_pmp_5_cfg_w; // @[PMP.scala:143:7] wire io_pmp_5_cfg_r_0 = io_pmp_5_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_5_addr_0 = io_pmp_5_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_5_mask_0 = io_pmp_5_mask; // @[PMP.scala:143:7] wire io_pmp_6_cfg_l_0 = io_pmp_6_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_6_cfg_a_0 = io_pmp_6_cfg_a; // @[PMP.scala:143:7] wire io_pmp_6_cfg_x_0 = io_pmp_6_cfg_x; // @[PMP.scala:143:7] wire io_pmp_6_cfg_w_0 = io_pmp_6_cfg_w; // @[PMP.scala:143:7] wire io_pmp_6_cfg_r_0 = io_pmp_6_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_6_addr_0 = io_pmp_6_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_6_mask_0 = io_pmp_6_mask; // @[PMP.scala:143:7] wire io_pmp_7_cfg_l_0 = io_pmp_7_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_7_cfg_a_0 = io_pmp_7_cfg_a; // @[PMP.scala:143:7] wire io_pmp_7_cfg_x_0 = io_pmp_7_cfg_x; // @[PMP.scala:143:7] wire io_pmp_7_cfg_w_0 = io_pmp_7_cfg_w; // @[PMP.scala:143:7] wire io_pmp_7_cfg_r_0 = io_pmp_7_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_7_addr_0 = io_pmp_7_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_7_mask_0 = io_pmp_7_mask; // @[PMP.scala:143:7] wire [31:0] io_addr_0 = io_addr; // @[PMP.scala:143:7] wire [29:0] _pmp0_WIRE_addr = 30'h0; // @[PMP.scala:157:35] wire [29:0] pmp0_addr = 30'h0; // @[PMP.scala:157:22] wire [4:0] _res_hit_T_10 = 5'hC; // @[package.scala:243:71] wire [4:0] _res_hit_T_36 = 5'hC; // @[package.scala:243:71] wire [4:0] _res_hit_T_62 = 5'hC; // @[package.scala:243:71] wire [4:0] _res_hit_T_88 = 5'hC; // @[package.scala:243:71] wire [4:0] _res_hit_T_114 = 5'hC; // @[package.scala:243:71] wire [4:0] _res_hit_T_140 = 5'hC; // @[package.scala:243:71] wire [4:0] _res_hit_T_166 = 5'hC; // @[package.scala:243:71] wire [4:0] _res_hit_T_192 = 5'hC; // @[package.scala:243:71] wire [1:0] _res_hit_T_12 = 2'h3; // @[package.scala:243:46] wire [1:0] _res_hit_T_38 = 2'h3; // @[package.scala:243:46] wire [1:0] _res_hit_T_64 = 2'h3; // @[package.scala:243:46] wire [1:0] _res_hit_T_90 = 2'h3; // @[package.scala:243:46] wire [1:0] _res_hit_T_116 = 2'h3; // @[package.scala:243:46] wire [1:0] _res_hit_T_142 = 2'h3; // @[package.scala:243:46] wire [1:0] _res_hit_T_168 = 2'h3; // @[package.scala:243:46] wire [1:0] _res_hit_T_194 = 2'h3; // @[package.scala:243:46] wire [31:0] _res_hit_T_196 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_197 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _pmp0_WIRE_mask = 32'h0; // @[PMP.scala:157:35] wire [31:0] pmp0_mask = 32'h0; // @[PMP.scala:157:22] wire [31:0] _res_hit_T_195 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_198 = 32'h0; // @[PMP.scala:60:27] wire _pmp0_WIRE_cfg_l = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_x = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_w = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_r = 1'h0; // @[PMP.scala:157:35] wire pmp0_cfg_l = 1'h0; // @[PMP.scala:157:22] wire _res_hit_T_199 = 1'h0; // @[PMP.scala:77:9] wire _res_hit_T_200 = 1'h1; // @[PMP.scala:88:5] wire [1:0] io_size = 2'h2; // @[PMP.scala:143:7] wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] _pmp0_WIRE_cfg_res = 2'h0; // @[PMP.scala:157:35] wire [1:0] _pmp0_WIRE_cfg_a = 2'h0; // @[PMP.scala:157:35] wire [1:0] pmp0_cfg_res = 2'h0; // @[PMP.scala:157:22] wire [1:0] pmp0_cfg_a = 2'h0; // @[PMP.scala:157:22] wire [1:0] _res_hit_T_11 = 2'h0; // @[package.scala:243:76] wire [1:0] res_cur_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_44_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] _res_hit_T_37 = 2'h0; // @[package.scala:243:76] wire [1:0] res_cur_1_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_89_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] _res_hit_T_63 = 2'h0; // @[package.scala:243:76] wire [1:0] res_cur_2_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_134_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] _res_hit_T_89 = 2'h0; // @[package.scala:243:76] wire [1:0] res_cur_3_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_179_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] _res_hit_T_115 = 2'h0; // @[package.scala:243:76] wire [1:0] res_cur_4_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_224_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] _res_hit_T_141 = 2'h0; // @[package.scala:243:76] wire [1:0] res_cur_5_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_269_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] _res_hit_T_167 = 2'h0; // @[package.scala:243:76] wire [1:0] res_cur_6_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_314_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] _res_hit_T_193 = 2'h0; // @[package.scala:243:76] wire [1:0] res_cur_7_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] res_cfg_res = 2'h0; // @[PMP.scala:185:8] wire _res_T_319 = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_7_cfg_l = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_7_cfg_a = io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_7_addr = io_pmp_0_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_7_mask = io_pmp_0_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_274 = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_6_cfg_l = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_6_cfg_a = io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_6_addr = io_pmp_1_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_6_mask = io_pmp_1_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_229 = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_5_cfg_l = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_5_cfg_a = io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_5_addr = io_pmp_2_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_5_mask = io_pmp_2_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_184 = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_4_cfg_l = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_4_cfg_a = io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_4_addr = io_pmp_3_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_4_mask = io_pmp_3_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_139 = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_3_cfg_l = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_3_cfg_a = io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_3_addr = io_pmp_4_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_3_mask = io_pmp_4_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_94 = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_2_cfg_l = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_2_cfg_a = io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_2_addr = io_pmp_5_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_2_mask = io_pmp_5_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_49 = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_1_cfg_l = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_1_cfg_a = io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_1_addr = io_pmp_6_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_1_mask = io_pmp_6_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_4 = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_cfg_l = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_cfg_a = io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_addr = io_pmp_7_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_mask = io_pmp_7_mask_0; // @[PMP.scala:143:7, :181:23] wire res_cfg_r; // @[PMP.scala:185:8] wire res_cfg_w; // @[PMP.scala:185:8] wire res_cfg_x; // @[PMP.scala:185:8] wire io_r_0; // @[PMP.scala:143:7] wire io_w_0; // @[PMP.scala:143:7] wire io_x_0; // @[PMP.scala:143:7] wire default_0 = io_prv_0[1]; // @[PMP.scala:143:7, :156:56] wire pmp0_cfg_x = default_0; // @[PMP.scala:156:56, :157:22] wire pmp0_cfg_w = default_0; // @[PMP.scala:156:56, :157:22] wire pmp0_cfg_r = default_0; // @[PMP.scala:156:56, :157:22] wire _res_hit_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [31:0] _GEN = {io_pmp_7_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_T_1; // @[PMP.scala:60:36] assign _res_hit_T_1 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_19; // @[PMP.scala:60:36] assign _res_hit_T_19 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_2 = ~_res_hit_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_3 = {_res_hit_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_4 = ~_res_hit_T_3; // @[PMP.scala:60:{27,48}] wire [31:0] _res_hit_T_5 = io_addr_0 ^ _res_hit_T_4; // @[PMP.scala:60:27, :63:47, :143:7] wire [31:0] _res_hit_T_6 = ~io_pmp_7_mask_0; // @[PMP.scala:63:54, :143:7] wire [31:0] _res_hit_T_7 = _res_hit_T_5 & _res_hit_T_6; // @[PMP.scala:63:{47,52,54}] wire _res_hit_T_8 = _res_hit_T_7 == 32'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_9 = io_pmp_7_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_0 = {io_pmp_6_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_T_13; // @[PMP.scala:60:36] assign _res_hit_T_13 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_27; // @[PMP.scala:60:36] assign _res_hit_T_27 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_45; // @[PMP.scala:60:36] assign _res_hit_T_45 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_14 = ~_res_hit_T_13; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_15 = {_res_hit_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_16 = ~_res_hit_T_15; // @[PMP.scala:60:{27,48}] wire _res_hit_T_17 = io_addr_0 < _res_hit_T_16; // @[PMP.scala:60:27, :77:9, :143:7] wire _res_hit_T_18 = ~_res_hit_T_17; // @[PMP.scala:77:9, :88:5] wire [31:0] _res_hit_T_20 = ~_res_hit_T_19; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_21 = {_res_hit_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_22 = ~_res_hit_T_21; // @[PMP.scala:60:{27,48}] wire _res_hit_T_23 = io_addr_0 < _res_hit_T_22; // @[PMP.scala:60:27, :77:9, :143:7] wire _res_hit_T_24 = _res_hit_T_18 & _res_hit_T_23; // @[PMP.scala:77:9, :88:5, :94:48] wire _res_hit_T_25 = _res_hit_T_9 & _res_hit_T_24; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit = _res_hit_T ? _res_hit_T_8 : _res_hit_T_25; // @[PMP.scala:45:20, :63:58, :132:{8,61}] wire _res_ignore_T = ~io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore = default_0 & _res_ignore_T; // @[PMP.scala:156:56, :164:{26,29}] wire _res_T = io_pmp_7_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_1 = io_pmp_7_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_1; // @[PMP.scala:168:32] assign _res_T_1 = _GEN_1; // @[PMP.scala:168:32] wire _res_T_20; // @[PMP.scala:177:61] assign _res_T_20 = _GEN_1; // @[PMP.scala:168:32, :177:61] wire _res_T_24; // @[PMP.scala:178:63] assign _res_T_24 = _GEN_1; // @[PMP.scala:168:32, :178:63] wire _GEN_2 = io_pmp_7_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_2; // @[PMP.scala:168:32] assign _res_T_2 = _GEN_2; // @[PMP.scala:168:32] wire _res_T_29; // @[PMP.scala:177:61] assign _res_T_29 = _GEN_2; // @[PMP.scala:168:32, :177:61] wire _res_T_33; // @[PMP.scala:178:63] assign _res_T_33 = _GEN_2; // @[PMP.scala:168:32, :178:63] wire _res_T_3 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_3 = {io_pmp_7_cfg_x_0, io_pmp_7_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi; // @[PMP.scala:174:26] assign res_hi = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_1; // @[PMP.scala:174:26] assign res_hi_1 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_2; // @[PMP.scala:174:26] assign res_hi_2 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_3; // @[PMP.scala:174:26] assign res_hi_3 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_4; // @[PMP.scala:174:26] assign res_hi_4 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_5; // @[PMP.scala:174:26] assign res_hi_5 = _GEN_3; // @[PMP.scala:174:26] wire [2:0] _res_T_5 = {res_hi, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_6 = _res_T_5 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_7 = {res_hi_1, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_8 = _res_T_7 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_9 = {res_hi_2, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_10 = _res_T_9 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_11 = {res_hi_3, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_12 = _res_T_11 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_13 = {res_hi_4, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_14 = _res_T_13 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_15 = {res_hi_5, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_16 = &_res_T_15; // @[PMP.scala:174:{26,60}] wire _res_T_17 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_18 = _res_T_17 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_19 = _res_T_18; // @[PMP.scala:177:{30,37}] wire _res_T_21 = _res_T_19 & _res_T_20; // @[PMP.scala:177:{37,48,61}] wire _GEN_4 = io_pmp_7_cfg_l_0 & res_hit; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_22; // @[PMP.scala:178:32] assign _res_T_22 = _GEN_4; // @[PMP.scala:178:32] wire _res_T_31; // @[PMP.scala:178:32] assign _res_T_31 = _GEN_4; // @[PMP.scala:178:32] wire _res_T_40; // @[PMP.scala:178:32] assign _res_T_40 = _GEN_4; // @[PMP.scala:178:32] wire _res_T_23 = _res_T_22; // @[PMP.scala:178:{32,39}] wire _res_T_25 = _res_T_23 & _res_T_24; // @[PMP.scala:178:{39,50,63}] wire _res_T_26 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_27 = _res_T_26 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_28 = _res_T_27; // @[PMP.scala:177:{30,37}] wire _res_T_30 = _res_T_28 & _res_T_29; // @[PMP.scala:177:{37,48,61}] wire _res_T_32 = _res_T_31; // @[PMP.scala:178:{32,39}] wire _res_T_34 = _res_T_32 & _res_T_33; // @[PMP.scala:178:{39,50,63}] wire _res_T_35 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_36 = _res_T_35 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_37 = _res_T_36; // @[PMP.scala:177:{30,37}] wire _res_T_38 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_39 = _res_T_37 & _res_T_38; // @[PMP.scala:177:{37,48,61}] wire _res_T_41 = _res_T_40; // @[PMP.scala:178:{32,39}] wire _res_T_42 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_43 = _res_T_41 & _res_T_42; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_1; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_1; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_1; // @[PMP.scala:182:26] wire res_cur_cfg_x; // @[PMP.scala:181:23] wire res_cur_cfg_w; // @[PMP.scala:181:23] wire res_cur_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T = io_pmp_7_cfg_r_0 \| res_ignore; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_1 = _res_cur_cfg_r_T; // @[PMP.scala:182:{26,40}] assign res_cur_cfg_r = _res_cur_cfg_r_T_1; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T = io_pmp_7_cfg_w_0 \| res_ignore; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_1 = _res_cur_cfg_w_T; // @[PMP.scala:183:{26,40}] assign res_cur_cfg_w = _res_cur_cfg_w_T_1; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T = io_pmp_7_cfg_x_0 \| res_ignore; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_1 = _res_cur_cfg_x_T; // @[PMP.scala:184:{26,40}] assign res_cur_cfg_x = _res_cur_cfg_x_T_1; // @[PMP.scala:181:23, :184:26] wire _res_T_44_cfg_l = res_hit & res_cur_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_44_cfg_a = res_hit ? res_cur_cfg_a : 2'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_44_cfg_x = res_hit ? res_cur_cfg_x : pmp0_cfg_x; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire _res_T_44_cfg_w = res_hit ? res_cur_cfg_w : pmp0_cfg_w; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire _res_T_44_cfg_r = res_hit ? res_cur_cfg_r : pmp0_cfg_r; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire [29:0] _res_T_44_addr = res_hit ? res_cur_addr : 30'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_44_mask = res_hit ? res_cur_mask : 32'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_26 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [31:0] _res_hit_T_28 = ~_res_hit_T_27; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_29 = {_res_hit_T_28[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_30 = ~_res_hit_T_29; // @[PMP.scala:60:{27,48}] wire [31:0] _res_hit_T_31 = io_addr_0 ^ _res_hit_T_30; // @[PMP.scala:60:27, :63:47, :143:7] wire [31:0] _res_hit_T_32 = ~io_pmp_6_mask_0; // @[PMP.scala:63:54, :143:7] wire [31:0] _res_hit_T_33 = _res_hit_T_31 & _res_hit_T_32; // @[PMP.scala:63:{47,52,54}] wire _res_hit_T_34 = _res_hit_T_33 == 32'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_35 = io_pmp_6_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_5 = {io_pmp_5_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_T_39; // @[PMP.scala:60:36] assign _res_hit_T_39 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_53; // @[PMP.scala:60:36] assign _res_hit_T_53 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_71; // @[PMP.scala:60:36] assign _res_hit_T_71 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_40 = ~_res_hit_T_39; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_41 = {_res_hit_T_40[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_42 = ~_res_hit_T_41; // @[PMP.scala:60:{27,48}] wire _res_hit_T_43 = io_addr_0 < _res_hit_T_42; // @[PMP.scala:60:27, :77:9, :143:7] wire _res_hit_T_44 = ~_res_hit_T_43; // @[PMP.scala:77:9, :88:5] wire [31:0] _res_hit_T_46 = ~_res_hit_T_45; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_47 = {_res_hit_T_46[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_48 = ~_res_hit_T_47; // @[PMP.scala:60:{27,48}] wire _res_hit_T_49 = io_addr_0 < _res_hit_T_48; // @[PMP.scala:60:27, :77:9, :143:7] wire _res_hit_T_50 = _res_hit_T_44 & _res_hit_T_49; // @[PMP.scala:77:9, :88:5, :94:48] wire _res_hit_T_51 = _res_hit_T_35 & _res_hit_T_50; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_1 = _res_hit_T_26 ? _res_hit_T_34 : _res_hit_T_51; // @[PMP.scala:45:20, :63:58, :132:{8,61}] wire _res_ignore_T_1 = ~io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_1 = default_0 & _res_ignore_T_1; // @[PMP.scala:156:56, :164:{26,29}] wire _res_T_45 = io_pmp_6_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_6 = io_pmp_6_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_46; // @[PMP.scala:168:32] assign _res_T_46 = _GEN_6; // @[PMP.scala:168:32] wire _res_T_65; // @[PMP.scala:177:61] assign _res_T_65 = _GEN_6; // @[PMP.scala:168:32, :177:61] wire _res_T_69; // @[PMP.scala:178:63] assign _res_T_69 = _GEN_6; // @[PMP.scala:168:32, :178:63] wire _GEN_7 = io_pmp_6_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_47; // @[PMP.scala:168:32] assign _res_T_47 = _GEN_7; // @[PMP.scala:168:32] wire _res_T_74; // @[PMP.scala:177:61] assign _res_T_74 = _GEN_7; // @[PMP.scala:168:32, :177:61] wire _res_T_78; // @[PMP.scala:178:63] assign _res_T_78 = _GEN_7; // @[PMP.scala:168:32, :178:63] wire _res_T_48 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_8 = {io_pmp_6_cfg_x_0, io_pmp_6_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_6; // @[PMP.scala:174:26] assign res_hi_6 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_7; // @[PMP.scala:174:26] assign res_hi_7 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_8; // @[PMP.scala:174:26] assign res_hi_8 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_9; // @[PMP.scala:174:26] assign res_hi_9 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_10; // @[PMP.scala:174:26] assign res_hi_10 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_11; // @[PMP.scala:174:26] assign res_hi_11 = _GEN_8; // @[PMP.scala:174:26] wire [2:0] _res_T_50 = {res_hi_6, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_51 = _res_T_50 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_52 = {res_hi_7, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_53 = _res_T_52 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_54 = {res_hi_8, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_55 = _res_T_54 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_56 = {res_hi_9, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_57 = _res_T_56 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_58 = {res_hi_10, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_59 = _res_T_58 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_60 = {res_hi_11, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_61 = &_res_T_60; // @[PMP.scala:174:{26,60}] wire _res_T_62 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_63 = _res_T_62 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_64 = _res_T_63; // @[PMP.scala:177:{30,37}] wire _res_T_66 = _res_T_64 & _res_T_65; // @[PMP.scala:177:{37,48,61}] wire _GEN_9 = io_pmp_6_cfg_l_0 & res_hit_1; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_67; // @[PMP.scala:178:32] assign _res_T_67 = _GEN_9; // @[PMP.scala:178:32] wire _res_T_76; // @[PMP.scala:178:32] assign _res_T_76 = _GEN_9; // @[PMP.scala:178:32] wire _res_T_85; // @[PMP.scala:178:32] assign _res_T_85 = _GEN_9; // @[PMP.scala:178:32] wire _res_T_68 = _res_T_67; // @[PMP.scala:178:{32,39}] wire _res_T_70 = _res_T_68 & _res_T_69; // @[PMP.scala:178:{39,50,63}] wire _res_T_71 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_72 = _res_T_71 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_73 = _res_T_72; // @[PMP.scala:177:{30,37}] wire _res_T_75 = _res_T_73 & _res_T_74; // @[PMP.scala:177:{37,48,61}] wire _res_T_77 = _res_T_76; // @[PMP.scala:178:{32,39}] wire _res_T_79 = _res_T_77 & _res_T_78; // @[PMP.scala:178:{39,50,63}] wire _res_T_80 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_81 = _res_T_80 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_82 = _res_T_81; // @[PMP.scala:177:{30,37}] wire _res_T_83 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_84 = _res_T_82 & _res_T_83; // @[PMP.scala:177:{37,48,61}] wire _res_T_86 = _res_T_85; // @[PMP.scala:178:{32,39}] wire _res_T_87 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_88 = _res_T_86 & _res_T_87; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_3; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_3; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_3; // @[PMP.scala:182:26] wire res_cur_1_cfg_x; // @[PMP.scala:181:23] wire res_cur_1_cfg_w; // @[PMP.scala:181:23] wire res_cur_1_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_2 = io_pmp_6_cfg_r_0 \| res_ignore_1; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_3 = _res_cur_cfg_r_T_2; // @[PMP.scala:182:{26,40}] assign res_cur_1_cfg_r = _res_cur_cfg_r_T_3; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_2 = io_pmp_6_cfg_w_0 \| res_ignore_1; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_3 = _res_cur_cfg_w_T_2; // @[PMP.scala:183:{26,40}] assign res_cur_1_cfg_w = _res_cur_cfg_w_T_3; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_2 = io_pmp_6_cfg_x_0 \| res_ignore_1; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_3 = _res_cur_cfg_x_T_2; // @[PMP.scala:184:{26,40}] assign res_cur_1_cfg_x = _res_cur_cfg_x_T_3; // @[PMP.scala:181:23, :184:26] wire _res_T_89_cfg_l = res_hit_1 ? res_cur_1_cfg_l : _res_T_44_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_89_cfg_a = res_hit_1 ? res_cur_1_cfg_a : _res_T_44_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_x = res_hit_1 ? res_cur_1_cfg_x : _res_T_44_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_w = res_hit_1 ? res_cur_1_cfg_w : _res_T_44_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_r = res_hit_1 ? res_cur_1_cfg_r : _res_T_44_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_89_addr = res_hit_1 ? res_cur_1_addr : _res_T_44_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_89_mask = res_hit_1 ? res_cur_1_mask : _res_T_44_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_52 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [31:0] _res_hit_T_54 = ~_res_hit_T_53; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_55 = {_res_hit_T_54[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_56 = ~_res_hit_T_55; // @[PMP.scala:60:{27,48}] wire [31:0] _res_hit_T_57 = io_addr_0 ^ _res_hit_T_56; // @[PMP.scala:60:27, :63:47, :143:7] wire [31:0] _res_hit_T_58 = ~io_pmp_5_mask_0; // @[PMP.scala:63:54, :143:7] wire [31:0] _res_hit_T_59 = _res_hit_T_57 & _res_hit_T_58; // @[PMP.scala:63:{47,52,54}] wire _res_hit_T_60 = _res_hit_T_59 == 32'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_61 = io_pmp_5_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_10 = {io_pmp_4_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_T_65; // @[PMP.scala:60:36] assign _res_hit_T_65 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_79; // @[PMP.scala:60:36] assign _res_hit_T_79 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_97; // @[PMP.scala:60:36] assign _res_hit_T_97 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_66 = ~_res_hit_T_65; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_67 = {_res_hit_T_66[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_68 = ~_res_hit_T_67; // @[PMP.scala:60:{27,48}] wire _res_hit_T_69 = io_addr_0 < _res_hit_T_68; // @[PMP.scala:60:27, :77:9, :143:7] wire _res_hit_T_70 = ~_res_hit_T_69; // @[PMP.scala:77:9, :88:5] wire [31:0] _res_hit_T_72 = ~_res_hit_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_73 = {_res_hit_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_74 = ~_res_hit_T_73; // @[PMP.scala:60:{27,48}] wire _res_hit_T_75 = io_addr_0 < _res_hit_T_74; // @[PMP.scala:60:27, :77:9, :143:7] wire _res_hit_T_76 = _res_hit_T_70 & _res_hit_T_75; // @[PMP.scala:77:9, :88:5, :94:48] wire _res_hit_T_77 = _res_hit_T_61 & _res_hit_T_76; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_2 = _res_hit_T_52 ? _res_hit_T_60 : _res_hit_T_77; // @[PMP.scala:45:20, :63:58, :132:{8,61}] wire _res_ignore_T_2 = ~io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_2 = default_0 & _res_ignore_T_2; // @[PMP.scala:156:56, :164:{26,29}] wire _res_T_90 = io_pmp_5_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_11 = io_pmp_5_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_91; // @[PMP.scala:168:32] assign _res_T_91 = _GEN_11; // @[PMP.scala:168:32] wire _res_T_110; // @[PMP.scala:177:61] assign _res_T_110 = _GEN_11; // @[PMP.scala:168:32, :177:61] wire _res_T_114; // @[PMP.scala:178:63] assign _res_T_114 = _GEN_11; // @[PMP.scala:168:32, :178:63] wire _GEN_12 = io_pmp_5_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_92; // @[PMP.scala:168:32] assign _res_T_92 = _GEN_12; // @[PMP.scala:168:32] wire _res_T_119; // @[PMP.scala:177:61] assign _res_T_119 = _GEN_12; // @[PMP.scala:168:32, :177:61] wire _res_T_123; // @[PMP.scala:178:63] assign _res_T_123 = _GEN_12; // @[PMP.scala:168:32, :178:63] wire _res_T_93 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_13 = {io_pmp_5_cfg_x_0, io_pmp_5_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_12; // @[PMP.scala:174:26] assign res_hi_12 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_13; // @[PMP.scala:174:26] assign res_hi_13 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_14; // @[PMP.scala:174:26] assign res_hi_14 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_15; // @[PMP.scala:174:26] assign res_hi_15 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_16; // @[PMP.scala:174:26] assign res_hi_16 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_17; // @[PMP.scala:174:26] assign res_hi_17 = _GEN_13; // @[PMP.scala:174:26] wire [2:0] _res_T_95 = {res_hi_12, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_96 = _res_T_95 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_97 = {res_hi_13, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_98 = _res_T_97 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_99 = {res_hi_14, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_100 = _res_T_99 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_101 = {res_hi_15, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_102 = _res_T_101 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_103 = {res_hi_16, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_104 = _res_T_103 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_105 = {res_hi_17, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_106 = &_res_T_105; // @[PMP.scala:174:{26,60}] wire _res_T_107 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_108 = _res_T_107 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_109 = _res_T_108; // @[PMP.scala:177:{30,37}] wire _res_T_111 = _res_T_109 & _res_T_110; // @[PMP.scala:177:{37,48,61}] wire _GEN_14 = io_pmp_5_cfg_l_0 & res_hit_2; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_112; // @[PMP.scala:178:32] assign _res_T_112 = _GEN_14; // @[PMP.scala:178:32] wire _res_T_121; // @[PMP.scala:178:32] assign _res_T_121 = _GEN_14; // @[PMP.scala:178:32] wire _res_T_130; // @[PMP.scala:178:32] assign _res_T_130 = _GEN_14; // @[PMP.scala:178:32] wire _res_T_113 = _res_T_112; // @[PMP.scala:178:{32,39}] wire _res_T_115 = _res_T_113 & _res_T_114; // @[PMP.scala:178:{39,50,63}] wire _res_T_116 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_117 = _res_T_116 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_118 = _res_T_117; // @[PMP.scala:177:{30,37}] wire _res_T_120 = _res_T_118 & _res_T_119; // @[PMP.scala:177:{37,48,61}] wire _res_T_122 = _res_T_121; // @[PMP.scala:178:{32,39}] wire _res_T_124 = _res_T_122 & _res_T_123; // @[PMP.scala:178:{39,50,63}] wire _res_T_125 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_126 = _res_T_125 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_127 = _res_T_126; // @[PMP.scala:177:{30,37}] wire _res_T_128 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_129 = _res_T_127 & _res_T_128; // @[PMP.scala:177:{37,48,61}] wire _res_T_131 = _res_T_130; // @[PMP.scala:178:{32,39}] wire _res_T_132 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_133 = _res_T_131 & _res_T_132; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_5; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_5; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_5; // @[PMP.scala:182:26] wire res_cur_2_cfg_x; // @[PMP.scala:181:23] wire res_cur_2_cfg_w; // @[PMP.scala:181:23] wire res_cur_2_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_4 = io_pmp_5_cfg_r_0 \| res_ignore_2; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_5 = _res_cur_cfg_r_T_4; // @[PMP.scala:182:{26,40}] assign res_cur_2_cfg_r = _res_cur_cfg_r_T_5; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_4 = io_pmp_5_cfg_w_0 \| res_ignore_2; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_5 = _res_cur_cfg_w_T_4; // @[PMP.scala:183:{26,40}] assign res_cur_2_cfg_w = _res_cur_cfg_w_T_5; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_4 = io_pmp_5_cfg_x_0 \| res_ignore_2; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_5 = _res_cur_cfg_x_T_4; // @[PMP.scala:184:{26,40}] assign res_cur_2_cfg_x = _res_cur_cfg_x_T_5; // @[PMP.scala:181:23, :184:26] wire _res_T_134_cfg_l = res_hit_2 ? res_cur_2_cfg_l : _res_T_89_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_134_cfg_a = res_hit_2 ? res_cur_2_cfg_a : _res_T_89_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_x = res_hit_2 ? res_cur_2_cfg_x : _res_T_89_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_w = res_hit_2 ? res_cur_2_cfg_w : _res_T_89_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_r = res_hit_2 ? res_cur_2_cfg_r : _res_T_89_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_134_addr = res_hit_2 ? res_cur_2_addr : _res_T_89_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_134_mask = res_hit_2 ? res_cur_2_mask : _res_T_89_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_78 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [31:0] _res_hit_T_80 = ~_res_hit_T_79; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_81 = {_res_hit_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_82 = ~_res_hit_T_81; // @[PMP.scala:60:{27,48}] wire [31:0] _res_hit_T_83 = io_addr_0 ^ _res_hit_T_82; // @[PMP.scala:60:27, :63:47, :143:7] wire [31:0] _res_hit_T_84 = ~io_pmp_4_mask_0; // @[PMP.scala:63:54, :143:7] wire [31:0] _res_hit_T_85 = _res_hit_T_83 & _res_hit_T_84; // @[PMP.scala:63:{47,52,54}] wire _res_hit_T_86 = _res_hit_T_85 == 32'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_87 = io_pmp_4_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_15 = {io_pmp_3_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_T_91; // @[PMP.scala:60:36] assign _res_hit_T_91 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_105; // @[PMP.scala:60:36] assign _res_hit_T_105 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_123; // @[PMP.scala:60:36] assign _res_hit_T_123 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_92 = ~_res_hit_T_91; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_93 = {_res_hit_T_92[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_94 = ~_res_hit_T_93; // @[PMP.scala:60:{27,48}] wire _res_hit_T_95 = io_addr_0 < _res_hit_T_94; // @[PMP.scala:60:27, :77:9, :143:7] wire _res_hit_T_96 = ~_res_hit_T_95; // @[PMP.scala:77:9, :88:5] wire [31:0] _res_hit_T_98 = ~_res_hit_T_97; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_99 = {_res_hit_T_98[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_100 = ~_res_hit_T_99; // @[PMP.scala:60:{27,48}] wire _res_hit_T_101 = io_addr_0 < _res_hit_T_100; // @[PMP.scala:60:27, :77:9, :143:7] wire _res_hit_T_102 = _res_hit_T_96 & _res_hit_T_101; // @[PMP.scala:77:9, :88:5, :94:48] wire _res_hit_T_103 = _res_hit_T_87 & _res_hit_T_102; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_3 = _res_hit_T_78 ? _res_hit_T_86 : _res_hit_T_103; // @[PMP.scala:45:20, :63:58, :132:{8,61}] wire _res_ignore_T_3 = ~io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_3 = default_0 & _res_ignore_T_3; // @[PMP.scala:156:56, :164:{26,29}] wire _res_T_135 = io_pmp_4_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_16 = io_pmp_4_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_136; // @[PMP.scala:168:32] assign _res_T_136 = _GEN_16; // @[PMP.scala:168:32] wire _res_T_155; // @[PMP.scala:177:61] assign _res_T_155 = _GEN_16; // @[PMP.scala:168:32, :177:61] wire _res_T_159; // @[PMP.scala:178:63] assign _res_T_159 = _GEN_16; // @[PMP.scala:168:32, :178:63] wire _GEN_17 = io_pmp_4_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_137; // @[PMP.scala:168:32] assign _res_T_137 = _GEN_17; // @[PMP.scala:168:32] wire _res_T_164; // @[PMP.scala:177:61] assign _res_T_164 = _GEN_17; // @[PMP.scala:168:32, :177:61] wire _res_T_168; // @[PMP.scala:178:63] assign _res_T_168 = _GEN_17; // @[PMP.scala:168:32, :178:63] wire _res_T_138 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_18 = {io_pmp_4_cfg_x_0, io_pmp_4_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_18; // @[PMP.scala:174:26] assign res_hi_18 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_19; // @[PMP.scala:174:26] assign res_hi_19 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_20; // @[PMP.scala:174:26] assign res_hi_20 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_21; // @[PMP.scala:174:26] assign res_hi_21 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_22; // @[PMP.scala:174:26] assign res_hi_22 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_23; // @[PMP.scala:174:26] assign res_hi_23 = _GEN_18; // @[PMP.scala:174:26] wire [2:0] _res_T_140 = {res_hi_18, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_141 = _res_T_140 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_142 = {res_hi_19, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_143 = _res_T_142 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_144 = {res_hi_20, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_145 = _res_T_144 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_146 = {res_hi_21, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_147 = _res_T_146 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_148 = {res_hi_22, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_149 = _res_T_148 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_150 = {res_hi_23, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_151 = &_res_T_150; // @[PMP.scala:174:{26,60}] wire _res_T_152 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_153 = _res_T_152 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_154 = _res_T_153; // @[PMP.scala:177:{30,37}] wire _res_T_156 = _res_T_154 & _res_T_155; // @[PMP.scala:177:{37,48,61}] wire _GEN_19 = io_pmp_4_cfg_l_0 & res_hit_3; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_157; // @[PMP.scala:178:32] assign _res_T_157 = _GEN_19; // @[PMP.scala:178:32] wire _res_T_166; // @[PMP.scala:178:32] assign _res_T_166 = _GEN_19; // @[PMP.scala:178:32] wire _res_T_175; // @[PMP.scala:178:32] assign _res_T_175 = _GEN_19; // @[PMP.scala:178:32] wire _res_T_158 = _res_T_157; // @[PMP.scala:178:{32,39}] wire _res_T_160 = _res_T_158 & _res_T_159; // @[PMP.scala:178:{39,50,63}] wire _res_T_161 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_162 = _res_T_161 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_163 = _res_T_162; // @[PMP.scala:177:{30,37}] wire _res_T_165 = _res_T_163 & _res_T_164; // @[PMP.scala:177:{37,48,61}] wire _res_T_167 = _res_T_166; // @[PMP.scala:178:{32,39}] wire _res_T_169 = _res_T_167 & _res_T_168; // @[PMP.scala:178:{39,50,63}] wire _res_T_170 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_171 = _res_T_170 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_172 = _res_T_171; // @[PMP.scala:177:{30,37}] wire _res_T_173 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_174 = _res_T_172 & _res_T_173; // @[PMP.scala:177:{37,48,61}] wire _res_T_176 = _res_T_175; // @[PMP.scala:178:{32,39}] wire _res_T_177 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_178 = _res_T_176 & _res_T_177; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_7; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_7; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_7; // @[PMP.scala:182:26] wire res_cur_3_cfg_x; // @[PMP.scala:181:23] wire res_cur_3_cfg_w; // @[PMP.scala:181:23] wire res_cur_3_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_6 = io_pmp_4_cfg_r_0 \| res_ignore_3; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_7 = _res_cur_cfg_r_T_6; // @[PMP.scala:182:{26,40}] assign res_cur_3_cfg_r = _res_cur_cfg_r_T_7; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_6 = io_pmp_4_cfg_w_0 \| res_ignore_3; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_7 = _res_cur_cfg_w_T_6; // @[PMP.scala:183:{26,40}] assign res_cur_3_cfg_w = _res_cur_cfg_w_T_7; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_6 = io_pmp_4_cfg_x_0 \| res_ignore_3; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_7 = _res_cur_cfg_x_T_6; // @[PMP.scala:184:{26,40}] assign res_cur_3_cfg_x = _res_cur_cfg_x_T_7; // @[PMP.scala:181:23, :184:26] wire _res_T_179_cfg_l = res_hit_3 ? res_cur_3_cfg_l : _res_T_134_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_179_cfg_a = res_hit_3 ? res_cur_3_cfg_a : _res_T_134_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_x = res_hit_3 ? res_cur_3_cfg_x : _res_T_134_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_w = res_hit_3 ? res_cur_3_cfg_w : _res_T_134_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_r = res_hit_3 ? res_cur_3_cfg_r : _res_T_134_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_179_addr = res_hit_3 ? res_cur_3_addr : _res_T_134_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_179_mask = res_hit_3 ? res_cur_3_mask : _res_T_134_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_104 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [31:0] _res_hit_T_106 = ~_res_hit_T_105; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_107 = {_res_hit_T_106[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_108 = ~_res_hit_T_107; // @[PMP.scala:60:{27,48}] wire [31:0] _res_hit_T_109 = io_addr_0 ^ _res_hit_T_108; // @[PMP.scala:60:27, :63:47, :143:7] wire [31:0] _res_hit_T_110 = ~io_pmp_3_mask_0; // @[PMP.scala:63:54, :143:7] wire [31:0] _res_hit_T_111 = _res_hit_T_109 & _res_hit_T_110; // @[PMP.scala:63:{47,52,54}] wire _res_hit_T_112 = _res_hit_T_111 == 32'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_113 = io_pmp_3_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_20 = {io_pmp_2_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_T_117; // @[PMP.scala:60:36] assign _res_hit_T_117 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_131; // @[PMP.scala:60:36] assign _res_hit_T_131 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_149; // @[PMP.scala:60:36] assign _res_hit_T_149 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_118 = ~_res_hit_T_117; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_119 = {_res_hit_T_118[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_120 = ~_res_hit_T_119; // @[PMP.scala:60:{27,48}] wire _res_hit_T_121 = io_addr_0 < _res_hit_T_120; // @[PMP.scala:60:27, :77:9, :143:7] wire _res_hit_T_122 = ~_res_hit_T_121; // @[PMP.scala:77:9, :88:5] wire [31:0] _res_hit_T_124 = ~_res_hit_T_123; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_125 = {_res_hit_T_124[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_126 = ~_res_hit_T_125; // @[PMP.scala:60:{27,48}] wire _res_hit_T_127 = io_addr_0 < _res_hit_T_126; // @[PMP.scala:60:27, :77:9, :143:7] wire _res_hit_T_128 = _res_hit_T_122 & _res_hit_T_127; // @[PMP.scala:77:9, :88:5, :94:48] wire _res_hit_T_129 = _res_hit_T_113 & _res_hit_T_128; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_4 = _res_hit_T_104 ? _res_hit_T_112 : _res_hit_T_129; // @[PMP.scala:45:20, :63:58, :132:{8,61}] wire _res_ignore_T_4 = ~io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_4 = default_0 & _res_ignore_T_4; // @[PMP.scala:156:56, :164:{26,29}] wire _res_T_180 = io_pmp_3_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_21 = io_pmp_3_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_181; // @[PMP.scala:168:32] assign _res_T_181 = _GEN_21; // @[PMP.scala:168:32] wire _res_T_200; // @[PMP.scala:177:61] assign _res_T_200 = _GEN_21; // @[PMP.scala:168:32, :177:61] wire _res_T_204; // @[PMP.scala:178:63] assign _res_T_204 = _GEN_21; // @[PMP.scala:168:32, :178:63] wire _GEN_22 = io_pmp_3_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_182; // @[PMP.scala:168:32] assign _res_T_182 = _GEN_22; // @[PMP.scala:168:32] wire _res_T_209; // @[PMP.scala:177:61] assign _res_T_209 = _GEN_22; // @[PMP.scala:168:32, :177:61] wire _res_T_213; // @[PMP.scala:178:63] assign _res_T_213 = _GEN_22; // @[PMP.scala:168:32, :178:63] wire _res_T_183 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_23 = {io_pmp_3_cfg_x_0, io_pmp_3_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_24; // @[PMP.scala:174:26] assign res_hi_24 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_25; // @[PMP.scala:174:26] assign res_hi_25 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_26; // @[PMP.scala:174:26] assign res_hi_26 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_27; // @[PMP.scala:174:26] assign res_hi_27 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_28; // @[PMP.scala:174:26] assign res_hi_28 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_29; // @[PMP.scala:174:26] assign res_hi_29 = _GEN_23; // @[PMP.scala:174:26] wire [2:0] _res_T_185 = {res_hi_24, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_186 = _res_T_185 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_187 = {res_hi_25, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_188 = _res_T_187 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_189 = {res_hi_26, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_190 = _res_T_189 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_191 = {res_hi_27, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_192 = _res_T_191 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_193 = {res_hi_28, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_194 = _res_T_193 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_195 = {res_hi_29, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_196 = &_res_T_195; // @[PMP.scala:174:{26,60}] wire _res_T_197 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_198 = _res_T_197 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_199 = _res_T_198; // @[PMP.scala:177:{30,37}] wire _res_T_201 = _res_T_199 & _res_T_200; // @[PMP.scala:177:{37,48,61}] wire _GEN_24 = io_pmp_3_cfg_l_0 & res_hit_4; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_202; // @[PMP.scala:178:32] assign _res_T_202 = _GEN_24; // @[PMP.scala:178:32] wire _res_T_211; // @[PMP.scala:178:32] assign _res_T_211 = _GEN_24; // @[PMP.scala:178:32] wire _res_T_220; // @[PMP.scala:178:32] assign _res_T_220 = _GEN_24; // @[PMP.scala:178:32] wire _res_T_203 = _res_T_202; // @[PMP.scala:178:{32,39}] wire _res_T_205 = _res_T_203 & _res_T_204; // @[PMP.scala:178:{39,50,63}] wire _res_T_206 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_207 = _res_T_206 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_208 = _res_T_207; // @[PMP.scala:177:{30,37}] wire _res_T_210 = _res_T_208 & _res_T_209; // @[PMP.scala:177:{37,48,61}] wire _res_T_212 = _res_T_211; // @[PMP.scala:178:{32,39}] wire _res_T_214 = _res_T_212 & _res_T_213; // @[PMP.scala:178:{39,50,63}] wire _res_T_215 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_216 = _res_T_215 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_217 = _res_T_216; // @[PMP.scala:177:{30,37}] wire _res_T_218 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_219 = _res_T_217 & _res_T_218; // @[PMP.scala:177:{37,48,61}] wire _res_T_221 = _res_T_220; // @[PMP.scala:178:{32,39}] wire _res_T_222 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_223 = _res_T_221 & _res_T_222; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_9; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_9; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_9; // @[PMP.scala:182:26] wire res_cur_4_cfg_x; // @[PMP.scala:181:23] wire res_cur_4_cfg_w; // @[PMP.scala:181:23] wire res_cur_4_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_8 = io_pmp_3_cfg_r_0 \| res_ignore_4; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_9 = _res_cur_cfg_r_T_8; // @[PMP.scala:182:{26,40}] assign res_cur_4_cfg_r = _res_cur_cfg_r_T_9; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_8 = io_pmp_3_cfg_w_0 \| res_ignore_4; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_9 = _res_cur_cfg_w_T_8; // @[PMP.scala:183:{26,40}] assign res_cur_4_cfg_w = _res_cur_cfg_w_T_9; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_8 = io_pmp_3_cfg_x_0 \| res_ignore_4; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_9 = _res_cur_cfg_x_T_8; // @[PMP.scala:184:{26,40}] assign res_cur_4_cfg_x = _res_cur_cfg_x_T_9; // @[PMP.scala:181:23, :184:26] wire _res_T_224_cfg_l = res_hit_4 ? res_cur_4_cfg_l : _res_T_179_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_224_cfg_a = res_hit_4 ? res_cur_4_cfg_a : _res_T_179_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_x = res_hit_4 ? res_cur_4_cfg_x : _res_T_179_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_w = res_hit_4 ? res_cur_4_cfg_w : _res_T_179_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_r = res_hit_4 ? res_cur_4_cfg_r : _res_T_179_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_224_addr = res_hit_4 ? res_cur_4_addr : _res_T_179_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_224_mask = res_hit_4 ? res_cur_4_mask : _res_T_179_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_130 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [31:0] _res_hit_T_132 = ~_res_hit_T_131; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_133 = {_res_hit_T_132[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_134 = ~_res_hit_T_133; // @[PMP.scala:60:{27,48}] wire [31:0] _res_hit_T_135 = io_addr_0 ^ _res_hit_T_134; // @[PMP.scala:60:27, :63:47, :143:7] wire [31:0] _res_hit_T_136 = ~io_pmp_2_mask_0; // @[PMP.scala:63:54, :143:7] wire [31:0] _res_hit_T_137 = _res_hit_T_135 & _res_hit_T_136; // @[PMP.scala:63:{47,52,54}] wire _res_hit_T_138 = _res_hit_T_137 == 32'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_139 = io_pmp_2_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_25 = {io_pmp_1_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_T_143; // @[PMP.scala:60:36] assign _res_hit_T_143 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_157; // @[PMP.scala:60:36] assign _res_hit_T_157 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_175; // @[PMP.scala:60:36] assign _res_hit_T_175 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_144 = ~_res_hit_T_143; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_145 = {_res_hit_T_144[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_146 = ~_res_hit_T_145; // @[PMP.scala:60:{27,48}] wire _res_hit_T_147 = io_addr_0 < _res_hit_T_146; // @[PMP.scala:60:27, :77:9, :143:7] wire _res_hit_T_148 = ~_res_hit_T_147; // @[PMP.scala:77:9, :88:5] wire [31:0] _res_hit_T_150 = ~_res_hit_T_149; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_151 = {_res_hit_T_150[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_152 = ~_res_hit_T_151; // @[PMP.scala:60:{27,48}] wire _res_hit_T_153 = io_addr_0 < _res_hit_T_152; // @[PMP.scala:60:27, :77:9, :143:7] wire _res_hit_T_154 = _res_hit_T_148 & _res_hit_T_153; // @[PMP.scala:77:9, :88:5, :94:48] wire _res_hit_T_155 = _res_hit_T_139 & _res_hit_T_154; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_5 = _res_hit_T_130 ? _res_hit_T_138 : _res_hit_T_155; // @[PMP.scala:45:20, :63:58, :132:{8,61}] wire _res_ignore_T_5 = ~io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_5 = default_0 & _res_ignore_T_5; // @[PMP.scala:156:56, :164:{26,29}] wire _res_T_225 = io_pmp_2_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_26 = io_pmp_2_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_226; // @[PMP.scala:168:32] assign _res_T_226 = _GEN_26; // @[PMP.scala:168:32] wire _res_T_245; // @[PMP.scala:177:61] assign _res_T_245 = _GEN_26; // @[PMP.scala:168:32, :177:61] wire _res_T_249; // @[PMP.scala:178:63] assign _res_T_249 = _GEN_26; // @[PMP.scala:168:32, :178:63] wire _GEN_27 = io_pmp_2_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_227; // @[PMP.scala:168:32] assign _res_T_227 = _GEN_27; // @[PMP.scala:168:32] wire _res_T_254; // @[PMP.scala:177:61] assign _res_T_254 = _GEN_27; // @[PMP.scala:168:32, :177:61] wire _res_T_258; // @[PMP.scala:178:63] assign _res_T_258 = _GEN_27; // @[PMP.scala:168:32, :178:63] wire _res_T_228 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_28 = {io_pmp_2_cfg_x_0, io_pmp_2_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_30; // @[PMP.scala:174:26] assign res_hi_30 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_31; // @[PMP.scala:174:26] assign res_hi_31 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_32; // @[PMP.scala:174:26] assign res_hi_32 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_33; // @[PMP.scala:174:26] assign res_hi_33 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_34; // @[PMP.scala:174:26] assign res_hi_34 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_35; // @[PMP.scala:174:26] assign res_hi_35 = _GEN_28; // @[PMP.scala:174:26] wire [2:0] _res_T_230 = {res_hi_30, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_231 = _res_T_230 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_232 = {res_hi_31, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_233 = _res_T_232 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_234 = {res_hi_32, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_235 = _res_T_234 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_236 = {res_hi_33, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_237 = _res_T_236 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_238 = {res_hi_34, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_239 = _res_T_238 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_240 = {res_hi_35, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_241 = &_res_T_240; // @[PMP.scala:174:{26,60}] wire _res_T_242 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_243 = _res_T_242 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_244 = _res_T_243; // @[PMP.scala:177:{30,37}] wire _res_T_246 = _res_T_244 & _res_T_245; // @[PMP.scala:177:{37,48,61}] wire _GEN_29 = io_pmp_2_cfg_l_0 & res_hit_5; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_247; // @[PMP.scala:178:32] assign _res_T_247 = _GEN_29; // @[PMP.scala:178:32] wire _res_T_256; // @[PMP.scala:178:32] assign _res_T_256 = _GEN_29; // @[PMP.scala:178:32] wire _res_T_265; // @[PMP.scala:178:32] assign _res_T_265 = _GEN_29; // @[PMP.scala:178:32] wire _res_T_248 = _res_T_247; // @[PMP.scala:178:{32,39}] wire _res_T_250 = _res_T_248 & _res_T_249; // @[PMP.scala:178:{39,50,63}] wire _res_T_251 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_252 = _res_T_251 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_253 = _res_T_252; // @[PMP.scala:177:{30,37}] wire _res_T_255 = _res_T_253 & _res_T_254; // @[PMP.scala:177:{37,48,61}] wire _res_T_257 = _res_T_256; // @[PMP.scala:178:{32,39}] wire _res_T_259 = _res_T_257 & _res_T_258; // @[PMP.scala:178:{39,50,63}] wire _res_T_260 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_261 = _res_T_260 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_262 = _res_T_261; // @[PMP.scala:177:{30,37}] wire _res_T_263 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_264 = _res_T_262 & _res_T_263; // @[PMP.scala:177:{37,48,61}] wire _res_T_266 = _res_T_265; // @[PMP.scala:178:{32,39}] wire _res_T_267 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_268 = _res_T_266 & _res_T_267; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_11; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_11; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_11; // @[PMP.scala:182:26] wire res_cur_5_cfg_x; // @[PMP.scala:181:23] wire res_cur_5_cfg_w; // @[PMP.scala:181:23] wire res_cur_5_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_10 = io_pmp_2_cfg_r_0 \| res_ignore_5; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_11 = _res_cur_cfg_r_T_10; // @[PMP.scala:182:{26,40}] assign res_cur_5_cfg_r = _res_cur_cfg_r_T_11; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_10 = io_pmp_2_cfg_w_0 \| res_ignore_5; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_11 = _res_cur_cfg_w_T_10; // @[PMP.scala:183:{26,40}] assign res_cur_5_cfg_w = _res_cur_cfg_w_T_11; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_10 = io_pmp_2_cfg_x_0 \| res_ignore_5; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_11 = _res_cur_cfg_x_T_10; // @[PMP.scala:184:{26,40}] assign res_cur_5_cfg_x = _res_cur_cfg_x_T_11; // @[PMP.scala:181:23, :184:26] wire _res_T_269_cfg_l = res_hit_5 ? res_cur_5_cfg_l : _res_T_224_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_269_cfg_a = res_hit_5 ? res_cur_5_cfg_a : _res_T_224_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_x = res_hit_5 ? res_cur_5_cfg_x : _res_T_224_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_w = res_hit_5 ? res_cur_5_cfg_w : _res_T_224_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_r = res_hit_5 ? res_cur_5_cfg_r : _res_T_224_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_269_addr = res_hit_5 ? res_cur_5_addr : _res_T_224_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_269_mask = res_hit_5 ? res_cur_5_mask : _res_T_224_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_156 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [31:0] _res_hit_T_158 = ~_res_hit_T_157; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_159 = {_res_hit_T_158[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_160 = ~_res_hit_T_159; // @[PMP.scala:60:{27,48}] wire [31:0] _res_hit_T_161 = io_addr_0 ^ _res_hit_T_160; // @[PMP.scala:60:27, :63:47, :143:7] wire [31:0] _res_hit_T_162 = ~io_pmp_1_mask_0; // @[PMP.scala:63:54, :143:7] wire [31:0] _res_hit_T_163 = _res_hit_T_161 & _res_hit_T_162; // @[PMP.scala:63:{47,52,54}] wire _res_hit_T_164 = _res_hit_T_163 == 32'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_165 = io_pmp_1_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_30 = {io_pmp_0_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_T_169; // @[PMP.scala:60:36] assign _res_hit_T_169 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_183; // @[PMP.scala:60:36] assign _res_hit_T_183 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_201; // @[PMP.scala:60:36] assign _res_hit_T_201 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_170 = ~_res_hit_T_169; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_171 = {_res_hit_T_170[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_172 = ~_res_hit_T_171; // @[PMP.scala:60:{27,48}] wire _res_hit_T_173 = io_addr_0 < _res_hit_T_172; // @[PMP.scala:60:27, :77:9, :143:7] wire _res_hit_T_174 = ~_res_hit_T_173; // @[PMP.scala:77:9, :88:5] wire [31:0] _res_hit_T_176 = ~_res_hit_T_175; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_177 = {_res_hit_T_176[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_178 = ~_res_hit_T_177; // @[PMP.scala:60:{27,48}] wire _res_hit_T_179 = io_addr_0 < _res_hit_T_178; // @[PMP.scala:60:27, :77:9, :143:7] wire _res_hit_T_180 = _res_hit_T_174 & _res_hit_T_179; // @[PMP.scala:77:9, :88:5, :94:48] wire _res_hit_T_181 = _res_hit_T_165 & _res_hit_T_180; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_6 = _res_hit_T_156 ? _res_hit_T_164 : _res_hit_T_181; // @[PMP.scala:45:20, :63:58, :132:{8,61}] wire _res_ignore_T_6 = ~io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_6 = default_0 & _res_ignore_T_6; // @[PMP.scala:156:56, :164:{26,29}] wire _res_T_270 = io_pmp_1_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_31 = io_pmp_1_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_271; // @[PMP.scala:168:32] assign _res_T_271 = _GEN_31; // @[PMP.scala:168:32] wire _res_T_290; // @[PMP.scala:177:61] assign _res_T_290 = _GEN_31; // @[PMP.scala:168:32, :177:61] wire _res_T_294; // @[PMP.scala:178:63] assign _res_T_294 = _GEN_31; // @[PMP.scala:168:32, :178:63] wire _GEN_32 = io_pmp_1_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_272; // @[PMP.scala:168:32] assign _res_T_272 = _GEN_32; // @[PMP.scala:168:32] wire _res_T_299; // @[PMP.scala:177:61] assign _res_T_299 = _GEN_32; // @[PMP.scala:168:32, :177:61] wire _res_T_303; // @[PMP.scala:178:63] assign _res_T_303 = _GEN_32; // @[PMP.scala:168:32, :178:63] wire _res_T_273 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_33 = {io_pmp_1_cfg_x_0, io_pmp_1_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_36; // @[PMP.scala:174:26] assign res_hi_36 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_37; // @[PMP.scala:174:26] assign res_hi_37 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_38; // @[PMP.scala:174:26] assign res_hi_38 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_39; // @[PMP.scala:174:26] assign res_hi_39 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_40; // @[PMP.scala:174:26] assign res_hi_40 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_41; // @[PMP.scala:174:26] assign res_hi_41 = _GEN_33; // @[PMP.scala:174:26] wire [2:0] _res_T_275 = {res_hi_36, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_276 = _res_T_275 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_277 = {res_hi_37, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_278 = _res_T_277 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_279 = {res_hi_38, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_280 = _res_T_279 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_281 = {res_hi_39, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_282 = _res_T_281 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_283 = {res_hi_40, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_284 = _res_T_283 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_285 = {res_hi_41, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_286 = &_res_T_285; // @[PMP.scala:174:{26,60}] wire _res_T_287 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_288 = _res_T_287 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_289 = _res_T_288; // @[PMP.scala:177:{30,37}] wire _res_T_291 = _res_T_289 & _res_T_290; // @[PMP.scala:177:{37,48,61}] wire _GEN_34 = io_pmp_1_cfg_l_0 & res_hit_6; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_292; // @[PMP.scala:178:32] assign _res_T_292 = _GEN_34; // @[PMP.scala:178:32] wire _res_T_301; // @[PMP.scala:178:32] assign _res_T_301 = _GEN_34; // @[PMP.scala:178:32] wire _res_T_310; // @[PMP.scala:178:32] assign _res_T_310 = _GEN_34; // @[PMP.scala:178:32] wire _res_T_293 = _res_T_292; // @[PMP.scala:178:{32,39}] wire _res_T_295 = _res_T_293 & _res_T_294; // @[PMP.scala:178:{39,50,63}] wire _res_T_296 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_297 = _res_T_296 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_298 = _res_T_297; // @[PMP.scala:177:{30,37}] wire _res_T_300 = _res_T_298 & _res_T_299; // @[PMP.scala:177:{37,48,61}] wire _res_T_302 = _res_T_301; // @[PMP.scala:178:{32,39}] wire _res_T_304 = _res_T_302 & _res_T_303; // @[PMP.scala:178:{39,50,63}] wire _res_T_305 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_306 = _res_T_305 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_307 = _res_T_306; // @[PMP.scala:177:{30,37}] wire _res_T_308 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_309 = _res_T_307 & _res_T_308; // @[PMP.scala:177:{37,48,61}] wire _res_T_311 = _res_T_310; // @[PMP.scala:178:{32,39}] wire _res_T_312 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_313 = _res_T_311 & _res_T_312; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_13; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_13; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_13; // @[PMP.scala:182:26] wire res_cur_6_cfg_x; // @[PMP.scala:181:23] wire res_cur_6_cfg_w; // @[PMP.scala:181:23] wire res_cur_6_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_12 = io_pmp_1_cfg_r_0 \| res_ignore_6; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_13 = _res_cur_cfg_r_T_12; // @[PMP.scala:182:{26,40}] assign res_cur_6_cfg_r = _res_cur_cfg_r_T_13; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_12 = io_pmp_1_cfg_w_0 \| res_ignore_6; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_13 = _res_cur_cfg_w_T_12; // @[PMP.scala:183:{26,40}] assign res_cur_6_cfg_w = _res_cur_cfg_w_T_13; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_12 = io_pmp_1_cfg_x_0 \| res_ignore_6; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_13 = _res_cur_cfg_x_T_12; // @[PMP.scala:184:{26,40}] assign res_cur_6_cfg_x = _res_cur_cfg_x_T_13; // @[PMP.scala:181:23, :184:26] wire _res_T_314_cfg_l = res_hit_6 ? res_cur_6_cfg_l : _res_T_269_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_314_cfg_a = res_hit_6 ? res_cur_6_cfg_a : _res_T_269_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_x = res_hit_6 ? res_cur_6_cfg_x : _res_T_269_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_w = res_hit_6 ? res_cur_6_cfg_w : _res_T_269_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_r = res_hit_6 ? res_cur_6_cfg_r : _res_T_269_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_314_addr = res_hit_6 ? res_cur_6_addr : _res_T_269_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_314_mask = res_hit_6 ? res_cur_6_mask : _res_T_269_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_182 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [31:0] _res_hit_T_184 = ~_res_hit_T_183; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_185 = {_res_hit_T_184[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_186 = ~_res_hit_T_185; // @[PMP.scala:60:{27,48}] wire [31:0] _res_hit_T_187 = io_addr_0 ^ _res_hit_T_186; // @[PMP.scala:60:27, :63:47, :143:7] wire [31:0] _res_hit_T_188 = ~io_pmp_0_mask_0; // @[PMP.scala:63:54, :143:7] wire [31:0] _res_hit_T_189 = _res_hit_T_187 & _res_hit_T_188; // @[PMP.scala:63:{47,52,54}] wire _res_hit_T_190 = _res_hit_T_189 == 32'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_191 = io_pmp_0_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _res_hit_T_202 = ~_res_hit_T_201; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_203 = {_res_hit_T_202[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_204 = ~_res_hit_T_203; // @[PMP.scala:60:{27,48}] wire _res_hit_T_205 = io_addr_0 < _res_hit_T_204; // @[PMP.scala:60:27, :77:9, :143:7] wire _res_hit_T_206 = _res_hit_T_205; // @[PMP.scala:77:9, :94:48] wire _res_hit_T_207 = _res_hit_T_191 & _res_hit_T_206; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_7 = _res_hit_T_182 ? _res_hit_T_190 : _res_hit_T_207; // @[PMP.scala:45:20, :63:58, :132:{8,61}] wire _res_ignore_T_7 = ~io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_7 = default_0 & _res_ignore_T_7; // @[PMP.scala:156:56, :164:{26,29}] wire _res_T_315 = io_pmp_0_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_35 = io_pmp_0_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_316; // @[PMP.scala:168:32] assign _res_T_316 = _GEN_35; // @[PMP.scala:168:32] wire _res_T_335; // @[PMP.scala:177:61] assign _res_T_335 = _GEN_35; // @[PMP.scala:168:32, :177:61] wire _res_T_339; // @[PMP.scala:178:63] assign _res_T_339 = _GEN_35; // @[PMP.scala:168:32, :178:63] wire _GEN_36 = io_pmp_0_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_317; // @[PMP.scala:168:32] assign _res_T_317 = _GEN_36; // @[PMP.scala:168:32] wire _res_T_344; // @[PMP.scala:177:61] assign _res_T_344 = _GEN_36; // @[PMP.scala:168:32, :177:61] wire _res_T_348; // @[PMP.scala:178:63] assign _res_T_348 = _GEN_36; // @[PMP.scala:168:32, :178:63] wire _res_T_318 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_37 = {io_pmp_0_cfg_x_0, io_pmp_0_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_42; // @[PMP.scala:174:26] assign res_hi_42 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_43; // @[PMP.scala:174:26] assign res_hi_43 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_44; // @[PMP.scala:174:26] assign res_hi_44 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_45; // @[PMP.scala:174:26] assign res_hi_45 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_46; // @[PMP.scala:174:26] assign res_hi_46 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_47; // @[PMP.scala:174:26] assign res_hi_47 = _GEN_37; // @[PMP.scala:174:26] wire [2:0] _res_T_320 = {res_hi_42, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_321 = _res_T_320 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_322 = {res_hi_43, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_323 = _res_T_322 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_324 = {res_hi_44, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_325 = _res_T_324 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_326 = {res_hi_45, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_327 = _res_T_326 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_328 = {res_hi_46, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_329 = _res_T_328 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_330 = {res_hi_47, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_331 = &_res_T_330; // @[PMP.scala:174:{26,60}] wire _res_T_332 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_333 = _res_T_332 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_334 = _res_T_333; // @[PMP.scala:177:{30,37}] wire _res_T_336 = _res_T_334 & _res_T_335; // @[PMP.scala:177:{37,48,61}] wire _GEN_38 = io_pmp_0_cfg_l_0 & res_hit_7; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_337; // @[PMP.scala:178:32] assign _res_T_337 = _GEN_38; // @[PMP.scala:178:32] wire _res_T_346; // @[PMP.scala:178:32] assign _res_T_346 = _GEN_38; // @[PMP.scala:178:32] wire _res_T_355; // @[PMP.scala:178:32] assign _res_T_355 = _GEN_38; // @[PMP.scala:178:32] wire _res_T_338 = _res_T_337; // @[PMP.scala:178:{32,39}] wire _res_T_340 = _res_T_338 & _res_T_339; // @[PMP.scala:178:{39,50,63}] wire _res_T_341 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_342 = _res_T_341 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_343 = _res_T_342; // @[PMP.scala:177:{30,37}] wire _res_T_345 = _res_T_343 & _res_T_344; // @[PMP.scala:177:{37,48,61}] wire _res_T_347 = _res_T_346; // @[PMP.scala:178:{32,39}] wire _res_T_349 = _res_T_347 & _res_T_348; // @[PMP.scala:178:{39,50,63}] wire _res_T_350 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_351 = _res_T_350 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_352 = _res_T_351; // @[PMP.scala:177:{30,37}] wire _res_T_353 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_354 = _res_T_352 & _res_T_353; // @[PMP.scala:177:{37,48,61}] wire _res_T_356 = _res_T_355; // @[PMP.scala:178:{32,39}] wire _res_T_357 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_358 = _res_T_356 & _res_T_357; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_15; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_15; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_15; // @[PMP.scala:182:26] wire res_cur_7_cfg_x; // @[PMP.scala:181:23] wire res_cur_7_cfg_w; // @[PMP.scala:181:23] wire res_cur_7_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_14 = io_pmp_0_cfg_r_0 \| res_ignore_7; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_15 = _res_cur_cfg_r_T_14; // @[PMP.scala:182:{26,40}] assign res_cur_7_cfg_r = _res_cur_cfg_r_T_15; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_14 = io_pmp_0_cfg_w_0 \| res_ignore_7; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_15 = _res_cur_cfg_w_T_14; // @[PMP.scala:183:{26,40}] assign res_cur_7_cfg_w = _res_cur_cfg_w_T_15; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_14 = io_pmp_0_cfg_x_0 \| res_ignore_7; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_15 = _res_cur_cfg_x_T_14; // @[PMP.scala:184:{26,40}] assign res_cur_7_cfg_x = _res_cur_cfg_x_T_15; // @[PMP.scala:181:23, :184:26] wire res_cfg_l = res_hit_7 ? res_cur_7_cfg_l : _res_T_314_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] res_cfg_a = res_hit_7 ? res_cur_7_cfg_a : _res_T_314_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_x = res_hit_7 ? res_cur_7_cfg_x : _res_T_314_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_w = res_hit_7 ? res_cur_7_cfg_w : _res_T_314_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_r = res_hit_7 ? res_cur_7_cfg_r : _res_T_314_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] res_addr = res_hit_7 ? res_cur_7_addr : _res_T_314_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] res_mask = res_hit_7 ? res_cur_7_mask : _res_T_314_mask; // @[PMP.scala:132:8, :181:23, :185:8] assign io_x_0 = res_cfg_x; // @[PMP.scala:143:7, :185:8] assign io_w_0 = res_cfg_w; // @[PMP.scala:143:7, :185:8] assign io_r_0 = res_cfg_r; // @[PMP.scala:143:7, :185:8] assign io_r = io_r_0; // @[PMP.scala:143:7] assign io_w = io_w_0; // @[PMP.scala:143:7] assign io_x = io_x_0; // @[PMP.scala:143:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_293( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_19( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [13:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire io_in_d_bits_denied = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_wo_ready_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_wo_ready_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_4_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_5_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_35 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [13:0] _is_aligned_T = {2'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 14'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_37 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_38 = _source_ok_T_37 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_44 = _source_ok_T_43 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire _source_ok_T_63 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire _source_ok_T_64 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire _source_ok_T_65 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_68 = _source_ok_T_67 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_69 = _source_ok_T_68 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_70 = _source_ok_T_69 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_71 = _source_ok_T_70 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_71 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1110 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1110; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1110; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [13:0] address; // @[Monitor.scala:391:22] wire _T_1183 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1183; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1183; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1183; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [519:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1036 = _T_1110 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1036 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1036 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1036 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1036 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1036 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1082 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1082 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1051 = _T_1183 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1051 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1051 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1051 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [519:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1154 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1154 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1136 = _T_1183 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1136 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1136 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1136 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module MacUnit_134( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }	module OptimizationBarrier_TLBEntryData_82( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry / case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic / val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U \| in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } / Write request logic / // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) \| usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U \| in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) / Read/write response logic / val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied \|\| out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B / Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. / def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } / ReservableListBuffer logic, and associated classes. / class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /* Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. / abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /* A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index / class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) \| validSet used := (used & ~usedClr) \| usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) \| dataIsPresentSet / Reservation logic signals / val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) / Response logic signals / val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) / Reservation logic / reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } / Response logic / // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } / Response unwind logic / // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent \|\| isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind \|\| (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind \|\| (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready \|\| !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire \|\| unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /* Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) \| usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }	module dataMems_53( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File Fragmenter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} import scala.math.min import freechips.rocketchip.util.DataToAugmentedData object EarlyAck { sealed trait T case object AllPuts extends T case object PutFulls extends T case object None extends T } // minSize: minimum size of transfers supported by all outward managers // maxSize: maximum size of transfers supported after the Fragmenter is applied // alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager) // earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat // holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst // nameSuffix: appends a suffix to the module name // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize") require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize") require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize") val fragmentBits = log2Ceil(maxSize / minSize) val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0 val toggleBits = 1 val addedBits = fragmentBits + toggleBits + fullBits def expandTransfer(x: TransferSizes, op: String) = if (!x) x else { // validate that we can apply the fragmenter correctly require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})") TransferSizes(x.min, maxSize) } private def noChangeRequired = minSize == maxSize private def shrinkTransfer(x: TransferSizes) = if (!alwaysMin) x else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none private def mapManager(m: TLSlaveParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"), supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"), supportsHint = expandTransfer(m.supportsHint, "Hint")) val node = new TLAdapterNode( // We require that all the responses are mutually FIFO // Thus we need to compact all of the masters into one big master clientFn = { c => (if (noChangeRequired) c else c.v2copy( masters = Seq(TLMasterParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => if (noChangeRequired) { out <> in } else { // All managers must share a common FIFO domain (responses might end up interleaved) val manager = edgeOut.manager val managers = manager.managers val beatBytes = manager.beatBytes val fifoId = managers(0).fifoId require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _)) require (!manager.anySupportAcquireB \|\| !edgeOut.client.anySupportProbe, s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region") require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses") // We can't support devices which are cached on both sides of us require (!edgeOut.manager.anySupportAcquireB \|\| !edgeIn.client.anySupportProbe) // We can't support denied because we reassemble fragments require (!edgeOut.manager.mayDenyGet \|\| holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true") require (!edgeOut.manager.mayDenyPut \|\| earlyAck == EarlyAck.None) /* The Fragmenter is a bit tricky, because there are 5 sizes in play: * max size -- the maximum transfer size possible * orig size -- the original pre-fragmenter size * frag size -- the modified post-fragmenter size * min size -- the threshold below which frag=orig * beat size -- the amount transfered on any given beat * * The relationships are as follows: * max >= orig >= frag * max > min >= beat * It IS possible that orig <= min (then frag=orig; ie: no fragmentation) * * The fragment# (sent via TL.source) is measured in multiples of min size. * Meanwhile, to track the progress, counters measure in multiples of beat size. * * Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16. * * in.A out.A (frag#) out.D (frag#) in.D gen# ack# * get64 get16 6 ackD16 6 ackD64 12 15 * ackD16 6 ackD64 14 * ackD16 6 ackD64 13 * ackD16 6 ackD64 12 * get16 4 ackD16 4 ackD64 8 11 * ackD16 4 ackD64 10 * ackD16 4 ackD64 9 * ackD16 4 ackD64 8 * get16 2 ackD16 2 ackD64 4 7 * ackD16 2 ackD64 6 * ackD16 2 ackD64 5 * ackD16 2 ackD64 4 * get16 0 ackD16 0 ackD64 0 3 * ackD16 0 ackD64 2 * ackD16 0 ackD64 1 * ackD16 0 ackD64 0 * * get8 get8 0 ackD8 0 ackD8 0 1 * ackD8 0 ackD8 0 * * get4 get4 0 ackD4 0 ackD4 0 0 * get1 get1 0 ackD1 0 ackD1 0 0 * * put64 put16 6 15 * put64 put16 6 14 * put64 put16 6 13 * put64 put16 6 ack16 6 12 12 * put64 put16 4 11 * put64 put16 4 10 * put64 put16 4 9 * put64 put16 4 ack16 4 8 8 * put64 put16 2 7 * put64 put16 2 6 * put64 put16 2 5 * put64 put16 2 ack16 2 4 4 * put64 put16 0 3 * put64 put16 0 2 * put64 put16 0 1 * put64 put16 0 ack16 0 ack64 0 0 * * put8 put8 0 1 * put8 put8 0 ack8 0 ack8 0 0 * * put4 put4 0 ack4 0 ack4 0 0 * put1 put1 0 ack1 0 ack1 0 0 / val counterBits = log2Up(maxSize/beatBytes) val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize) // Consider the following waveform for two 4-beat bursts: // ---A----A------------ // -------D-----DDD-DDDD // Under TL rules, the second A can use the same source as the first A, // because the source is released for reuse on the first response beat. // // However, if we fragment the requests, it looks like this: // ---3210-3210--------- // -------3-----210-3210 // ... now we've broken the rules because 210 are twice inflight. // // This phenomenon means we can have essentially 2maxSize/minSize-1 // fragmented transactions in flight per original transaction source. // // To keep the source unique, we encode the beat counter in the low // bits of the source. To solve the overlap, we use a toggle bit. // Whatever toggle bit the D is reassembling, A will use the opposite. // First, handle the return path val acknum = RegInit(0.U(counterBits.W)) val dOrig = Reg(UInt()) val dToggle = RegInit(false.B) val dFragnum = out.d.bits.source(fragmentBits-1, 0) val dFirst = acknum === 0.U val dLast = dFragnum === 0.U // only for AccessAck (!Data) val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1) val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize)) val dHasData = edgeOut.hasData(out.d.bits) // calculate new acknum val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes) val acknum_size = dsizeOH1 >> log2Ceil(beatBytes) assert (!out.d.valid \|\| (acknum_fragment & acknum_size) === 0.U) val dFirst_acknum = acknum_fragment \| Mux(dHasData, acknum_size, 0.U) val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes)) // calculate the original size val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) \| dsizeOH1) when (out.d.fire) { acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement) when (dFirst) { dOrig := dFirst_size dToggle := out.d.bits.source(fragmentBits) } } // Swallow up non-data ack fragments val doEarlyAck = earlyAck match { case EarlyAck.AllPuts => true.B case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1) case EarlyAck.None => false.B } val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast) out.d.ready := in.d.ready \|\| drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged in.d.bits.source := out.d.bits.source >> addedBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig) if (edgeOut.manager.mayDenyPut) { val r_denied = Reg(Bool()) val d_denied = (!dFirst && r_denied) \|\| out.d.bits.denied when (out.d.fire) { r_denied := d_denied } in.d.bits.denied := d_denied } if (edgeOut.manager.mayDenyGet) { // Take denied only from the first beat and hold that value val d_denied = out.d.bits.denied holdUnless dFirst when (dHasData) { in.d.bits.denied := d_denied in.d.bits.corrupt := d_denied \|\| out.d.bits.corrupt } } // What maximum transfer sizes do downstream devices support? val maxArithmetics = managers.map(_.supportsArithmetic.max) val maxLogicals = managers.map(_.supportsLogical.max) val maxGets = managers.map(_.supportsGet.max) val maxPutFulls = managers.map(_.supportsPutFull.max) val maxPutPartials = managers.map(_.supportsPutPartial.max) val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0) // We assume that the request is valid => size 0 is impossible val lgMinSize = log2Ceil(minSize).U val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) // Make the request repeatable val repeater = Module(new Repeater(in.a.bits)) repeater.io.enq <> in.a val in_a = repeater.io.deq // If this is infront of a single manager, these become constants val find = manager.findFast(edgeIn.address(in_a.bits)) val maxLgArithmetic = Mux1H(find, maxLgArithmetics) val maxLgLogical = Mux1H(find, maxLgLogicals) val maxLgGet = Mux1H(find, maxLgGets) val maxLgPutFull = Mux1H(find, maxLgPutFulls) val maxLgPutPartial = Mux1H(find, maxLgPutPartials) val maxLgHint = Mux1H(find, maxLgHints) val limit = if (alwaysMin) lgMinSize else MuxLookup(in_a.bits.opcode, lgMinSize)(Array( TLMessages.PutFullData -> maxLgPutFull, TLMessages.PutPartialData -> maxLgPutPartial, TLMessages.ArithmeticData -> maxLgArithmetic, TLMessages.LogicalData -> maxLgLogical, TLMessages.Get -> maxLgGet, TLMessages.Hint -> maxLgHint)) val aOrig = in_a.bits.size val aFrag = Mux(aOrig > limit, limit, aOrig) val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize)) val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize)) val aHasData = edgeIn.hasData(in_a.bits) val aMask = Mux(aHasData, 0.U, aFragOH1) val gennum = RegInit(0.U(counterBits.W)) val aFirst = gennum === 0.U val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U) val new_gennum = ~(~old_gennum1 \| (aMask >> log2Ceil(beatBytes))) // ~(~x\|y) is width safe val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) \| (aFragOH1 >> log2Ceil(minSize))) val aLast = aFragnum === 0.U val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst)) val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None when (out.a.fire) { gennum := new_gennum } repeater.io.repeat := !aHasData && aFragnum =/= 0.U out.a <> in_a out.a.bits.address := in_a.bits.address \| ~(old_gennum1 << log2Ceil(beatBytes) \| ~aOrigOH1 \| aFragOH1 \| (minSize-1).U) out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum)) out.a.bits.size := aFrag // Optimize away some of the Repeater's registers assert (!repeater.io.full \|\| !aHasData) out.a.bits.data := in.a.bits.data val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full \|\| in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFragmenter { def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { if (minSize <= maxSize) { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix)) fragmenter.node } else { TLEphemeralNode()(ValName("no_fragmenter")) } } def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix) def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) (ram.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.1) := TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLFragmenter(ramBeatBytes, maxSize/2) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module TLInterconnectCoupler_cbus_to_l2_ctrl( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] input auto_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire tlOut_d_valid; // @[MixedNode.scala:542:17] wire tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] tlOut_d_bits_data; // @[MixedNode.scala:542:17] wire tlOut_d_bits_denied; // @[MixedNode.scala:542:17] wire tlOut_d_bits_sink; // @[MixedNode.scala:542:17] wire [7:0] tlOut_d_bits_source; // @[MixedNode.scala:542:17] wire [2:0] tlOut_d_bits_size; // @[MixedNode.scala:542:17] wire [1:0] tlOut_d_bits_param; // @[MixedNode.scala:542:17] wire [2:0] tlOut_d_bits_opcode; // @[MixedNode.scala:542:17] wire tlOut_a_ready; // @[MixedNode.scala:542:17] wire _fragmenter_auto_anon_out_a_valid; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_auto_anon_out_a_bits_opcode; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_auto_anon_out_a_bits_param; // @[Fragmenter.scala:345:34] wire [1:0] _fragmenter_auto_anon_out_a_bits_size; // @[Fragmenter.scala:345:34] wire [11:0] _fragmenter_auto_anon_out_a_bits_source; // @[Fragmenter.scala:345:34] wire [25:0] _fragmenter_auto_anon_out_a_bits_address; // @[Fragmenter.scala:345:34] wire [7:0] _fragmenter_auto_anon_out_a_bits_mask; // @[Fragmenter.scala:345:34] wire [63:0] _fragmenter_auto_anon_out_a_bits_data; // @[Fragmenter.scala:345:34] wire _fragmenter_auto_anon_out_a_bits_corrupt; // @[Fragmenter.scala:345:34] wire _fragmenter_auto_anon_out_d_ready; // @[Fragmenter.scala:345:34] wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28] wire [11:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28] wire auto_buffer_out_a_ready_0 = auto_buffer_out_a_ready; // @[LazyModuleImp.scala:138:7] wire auto_buffer_out_d_valid_0 = auto_buffer_out_d_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_buffer_out_d_bits_opcode_0 = auto_buffer_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] auto_buffer_out_d_bits_size_0 = auto_buffer_out_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [11:0] auto_buffer_out_d_bits_source_0 = auto_buffer_out_d_bits_source; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_buffer_out_d_bits_data_0 = auto_buffer_out_d_bits_data; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [25:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[LazyModuleImp.scala:138:7] wire auto_buffer_out_d_bits_sink = 1'h0; // @[Buffer.scala:75:28] wire auto_buffer_out_d_bits_denied = 1'h0; // @[Buffer.scala:75:28] wire auto_buffer_out_d_bits_corrupt = 1'h0; // @[Buffer.scala:75:28] wire [1:0] auto_buffer_out_d_bits_param = 2'h0; // @[Buffer.scala:75:28] wire tlIn_a_ready; // @[MixedNode.scala:551:17] wire tlIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17] wire [2:0] tlIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17] wire [2:0] tlIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17] wire [2:0] tlIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17] wire [7:0] tlIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17] wire [25:0] tlIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17] wire [7:0] tlIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17] wire [63:0] tlIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17] wire tlIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17] wire tlIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17] wire tlIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] tlIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] tlIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] tlIn_d_bits_size; // @[MixedNode.scala:551:17] wire [7:0] tlIn_d_bits_source; // @[MixedNode.scala:551:17] wire tlIn_d_bits_sink; // @[MixedNode.scala:551:17] wire tlIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] tlIn_d_bits_data; // @[MixedNode.scala:551:17] wire tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [2:0] auto_buffer_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_buffer_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7] wire [1:0] auto_buffer_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7] wire [11:0] auto_buffer_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7] wire [25:0] auto_buffer_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_buffer_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_buffer_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7] wire auto_buffer_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] wire auto_buffer_out_a_valid_0; // @[LazyModuleImp.scala:138:7] wire auto_buffer_out_d_ready_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7] wire [1:0] auto_tl_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7] assign tlIn_a_ready = tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_valid = tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_opcode = tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_param = tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_size = tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_source = tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_sink = tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_denied = tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_data = tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] tlOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] tlOut_a_bits_size; // @[MixedNode.scala:542:17] wire [7:0] tlOut_a_bits_source; // @[MixedNode.scala:542:17] wire [25:0] tlOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] tlOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] tlOut_a_bits_data; // @[MixedNode.scala:542:17] wire tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign tlIn_d_bits_corrupt = tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire tlOut_a_valid; // @[MixedNode.scala:542:17] wire tlOut_d_ready; // @[MixedNode.scala:542:17] assign auto_tl_in_a_ready_0 = tlIn_a_ready; // @[MixedNode.scala:551:17] assign tlOut_a_valid = tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_opcode = tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_param = tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_size = tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_source = tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_address = tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_mask = tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_data = tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_corrupt = tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign tlOut_d_ready = tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_tl_in_d_valid_0 = tlIn_d_valid; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_opcode_0 = tlIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_param_0 = tlIn_d_bits_param; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_size_0 = tlIn_d_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_source_0 = tlIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_sink_0 = tlIn_d_bits_sink; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_denied_0 = tlIn_d_bits_denied; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_data_0 = tlIn_d_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_corrupt_0 = tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17] TLBuffer_a26d64s12k1z2u buffer ( // @[Buffer.scala:75:28] .clock (clock), .reset (reset), .auto_in_a_ready (_buffer_auto_in_a_ready), .auto_in_a_valid (_fragmenter_auto_anon_out_a_valid), // @[Fragmenter.scala:345:34] .auto_in_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode), // @[Fragmenter.scala:345:34] .auto_in_a_bits_param (_fragmenter_auto_anon_out_a_bits_param), // @[Fragmenter.scala:345:34] .auto_in_a_bits_size (_fragmenter_auto_anon_out_a_bits_size), // @[Fragmenter.scala:345:34] .auto_in_a_bits_source (_fragmenter_auto_anon_out_a_bits_source), // @[Fragmenter.scala:345:34] .auto_in_a_bits_address (_fragmenter_auto_anon_out_a_bits_address), // @[Fragmenter.scala:345:34] .auto_in_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask), // @[Fragmenter.scala:345:34] .auto_in_a_bits_data (_fragmenter_auto_anon_out_a_bits_data), // @[Fragmenter.scala:345:34] .auto_in_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt), // @[Fragmenter.scala:345:34] .auto_in_d_ready (_fragmenter_auto_anon_out_d_ready), // @[Fragmenter.scala:345:34] .auto_in_d_valid (_buffer_auto_in_d_valid), .auto_in_d_bits_opcode (_buffer_auto_in_d_bits_opcode), .auto_in_d_bits_param (_buffer_auto_in_d_bits_param), .auto_in_d_bits_size (_buffer_auto_in_d_bits_size), .auto_in_d_bits_source (_buffer_auto_in_d_bits_source), .auto_in_d_bits_sink (_buffer_auto_in_d_bits_sink), .auto_in_d_bits_denied (_buffer_auto_in_d_bits_denied), .auto_in_d_bits_data (_buffer_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt), .auto_out_a_ready (auto_buffer_out_a_ready_0), // @[LazyModuleImp.scala:138:7] .auto_out_a_valid (auto_buffer_out_a_valid_0), .auto_out_a_bits_opcode (auto_buffer_out_a_bits_opcode_0), .auto_out_a_bits_param (auto_buffer_out_a_bits_param_0), .auto_out_a_bits_size (auto_buffer_out_a_bits_size_0), .auto_out_a_bits_source (auto_buffer_out_a_bits_source_0), .auto_out_a_bits_address (auto_buffer_out_a_bits_address_0), .auto_out_a_bits_mask (auto_buffer_out_a_bits_mask_0), .auto_out_a_bits_data (auto_buffer_out_a_bits_data_0), .auto_out_a_bits_corrupt (auto_buffer_out_a_bits_corrupt_0), .auto_out_d_ready (auto_buffer_out_d_ready_0), .auto_out_d_valid (auto_buffer_out_d_valid_0), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_opcode (auto_buffer_out_d_bits_opcode_0), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_size (auto_buffer_out_d_bits_size_0), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_source (auto_buffer_out_d_bits_source_0), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_data (auto_buffer_out_d_bits_data_0) // @[LazyModuleImp.scala:138:7] ); // @[Buffer.scala:75:28] TLFragmenter_LLCCtrl fragmenter ( // @[Fragmenter.scala:345:34] .clock (clock), .reset (reset), .auto_anon_in_a_ready (tlOut_a_ready), .auto_anon_in_a_valid (tlOut_a_valid), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_opcode (tlOut_a_bits_opcode), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_param (tlOut_a_bits_param), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_size (tlOut_a_bits_size), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_source (tlOut_a_bits_source), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_address (tlOut_a_bits_address), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_mask (tlOut_a_bits_mask), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_data (tlOut_a_bits_data), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_corrupt (tlOut_a_bits_corrupt), // @[MixedNode.scala:542:17] .auto_anon_in_d_ready (tlOut_d_ready), // @[MixedNode.scala:542:17] .auto_anon_in_d_valid (tlOut_d_valid), .auto_anon_in_d_bits_opcode (tlOut_d_bits_opcode), .auto_anon_in_d_bits_param (tlOut_d_bits_param), .auto_anon_in_d_bits_size (tlOut_d_bits_size), .auto_anon_in_d_bits_source (tlOut_d_bits_source), .auto_anon_in_d_bits_sink (tlOut_d_bits_sink), .auto_anon_in_d_bits_denied (tlOut_d_bits_denied), .auto_anon_in_d_bits_data (tlOut_d_bits_data), .auto_anon_in_d_bits_corrupt (tlOut_d_bits_corrupt), .auto_anon_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28] .auto_anon_out_a_valid (_fragmenter_auto_anon_out_a_valid), .auto_anon_out_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (_fragmenter_auto_anon_out_a_bits_param), .auto_anon_out_a_bits_size (_fragmenter_auto_anon_out_a_bits_size), .auto_anon_out_a_bits_source (_fragmenter_auto_anon_out_a_bits_source), .auto_anon_out_a_bits_address (_fragmenter_auto_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (_fragmenter_auto_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (_fragmenter_auto_anon_out_d_ready), .auto_anon_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_opcode (_buffer_auto_in_d_bits_opcode), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_param (_buffer_auto_in_d_bits_param), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_size (_buffer_auto_in_d_bits_size), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_source (_buffer_auto_in_d_bits_source), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_sink (_buffer_auto_in_d_bits_sink), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_denied (_buffer_auto_in_d_bits_denied), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt) // @[Buffer.scala:75:28] ); // @[Fragmenter.scala:345:34] assign auto_buffer_out_a_valid = auto_buffer_out_a_valid_0; // @[LazyModuleImp.scala:138:7] assign auto_buffer_out_a_bits_opcode = auto_buffer_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7] assign auto_buffer_out_a_bits_param = auto_buffer_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7] assign auto_buffer_out_a_bits_size = auto_buffer_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7] assign auto_buffer_out_a_bits_source = auto_buffer_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7] assign auto_buffer_out_a_bits_address = auto_buffer_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7] assign auto_buffer_out_a_bits_mask = auto_buffer_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7] assign auto_buffer_out_a_bits_data = auto_buffer_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7] assign auto_buffer_out_a_bits_corrupt = auto_buffer_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] assign auto_buffer_out_d_ready = auto_buffer_out_d_ready_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_opcode = auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_param = auto_tl_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_sink = auto_tl_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_denied = auto_tl_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_data = auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_corrupt = auto_tl_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Metadata.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.constants.MemoryOpConstants import freechips.rocketchip.util._ object ClientStates { val width = 2 def Nothing = 0.U(width.W) def Branch = 1.U(width.W) def Trunk = 2.U(width.W) def Dirty = 3.U(width.W) def hasReadPermission(state: UInt): Bool = state > Nothing def hasWritePermission(state: UInt): Bool = state > Branch } object MemoryOpCategories extends MemoryOpConstants { def wr = Cat(true.B, true.B) // Op actually writes def wi = Cat(false.B, true.B) // Future op will write def rd = Cat(false.B, false.B) // Op only reads def categorize(cmd: UInt): UInt = { val cat = Cat(isWrite(cmd), isWriteIntent(cmd)) //assert(cat.isOneOf(wr,wi,rd), "Could not categorize command.") cat } } /* Stores the client-side coherence information, * such as permissions on the data and whether the data is dirty. * Its API can be used to make TileLink messages in response to * memory operations, cache control oeprations, or Probe messages. / class ClientMetadata extends Bundle { /* Actual state information stored in this bundle / val state = UInt(ClientStates.width.W) /* Metadata equality / def ===(rhs: UInt): Bool = state === rhs def ===(rhs: ClientMetadata): Bool = state === rhs.state def =/=(rhs: ClientMetadata): Bool = !this.===(rhs) /* Is the block's data present in this cache / def isValid(dummy: Int = 0): Bool = state > ClientStates.Nothing /* Determine whether this cmd misses, and the new state (on hit) or param to be sent (on miss) / private def growStarter(cmd: UInt): (Bool, UInt) = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) MuxTLookup(Cat(c, state), (false.B, 0.U), Seq( //(effect, am now) -> (was a hit, next) Cat(rd, Dirty) -> (true.B, Dirty), Cat(rd, Trunk) -> (true.B, Trunk), Cat(rd, Branch) -> (true.B, Branch), Cat(wi, Dirty) -> (true.B, Dirty), Cat(wi, Trunk) -> (true.B, Trunk), Cat(wr, Dirty) -> (true.B, Dirty), Cat(wr, Trunk) -> (true.B, Dirty), //(effect, am now) -> (was a miss, param) Cat(rd, Nothing) -> (false.B, NtoB), Cat(wi, Branch) -> (false.B, BtoT), Cat(wi, Nothing) -> (false.B, NtoT), Cat(wr, Branch) -> (false.B, BtoT), Cat(wr, Nothing) -> (false.B, NtoT))) } /* Determine what state to go to after miss based on Grant param * For now, doesn't depend on state (which may have been Probed). / private def growFinisher(cmd: UInt, param: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) //assert(c === rd \|\| param === toT, "Client was expecting trunk permissions.") MuxLookup(Cat(c, param), Nothing)(Seq( //(effect param) -> (next) Cat(rd, toB) -> Branch, Cat(rd, toT) -> Trunk, Cat(wi, toT) -> Trunk, Cat(wr, toT) -> Dirty)) } /* Does this cache have permissions on this block sufficient to perform op, * and what to do next (Acquire message param or updated metadata). / def onAccess(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = growStarter(cmd) (r._1, r._2, ClientMetadata(r._2)) } /* Does a secondary miss on the block require another Acquire message / def onSecondaryAccess(first_cmd: UInt, second_cmd: UInt): (Bool, Bool, UInt, ClientMetadata, UInt) = { import MemoryOpCategories._ val r1 = growStarter(first_cmd) val r2 = growStarter(second_cmd) val needs_second_acq = isWriteIntent(second_cmd) && !isWriteIntent(first_cmd) val hit_again = r1._1 && r2._1 val dirties = categorize(second_cmd) === wr val biggest_grow_param = Mux(dirties, r2._2, r1._2) val dirtiest_state = ClientMetadata(biggest_grow_param) val dirtiest_cmd = Mux(dirties, second_cmd, first_cmd) (needs_second_acq, hit_again, biggest_grow_param, dirtiest_state, dirtiest_cmd) } /* Metadata change on a returned Grant / def onGrant(cmd: UInt, param: UInt): ClientMetadata = ClientMetadata(growFinisher(cmd, param)) /* Determine what state to go to based on Probe param / private def shrinkHelper(param: UInt): (Bool, UInt, UInt) = { import ClientStates._ import TLPermissions._ MuxTLookup(Cat(param, state), (false.B, 0.U, 0.U), Seq( //(wanted, am now) -> (hasDirtyData resp, next) Cat(toT, Dirty) -> (true.B, TtoT, Trunk), Cat(toT, Trunk) -> (false.B, TtoT, Trunk), Cat(toT, Branch) -> (false.B, BtoB, Branch), Cat(toT, Nothing) -> (false.B, NtoN, Nothing), Cat(toB, Dirty) -> (true.B, TtoB, Branch), Cat(toB, Trunk) -> (false.B, TtoB, Branch), // Policy: Don't notify on clean downgrade Cat(toB, Branch) -> (false.B, BtoB, Branch), Cat(toB, Nothing) -> (false.B, NtoN, Nothing), Cat(toN, Dirty) -> (true.B, TtoN, Nothing), Cat(toN, Trunk) -> (false.B, TtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Branch) -> (false.B, BtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Nothing) -> (false.B, NtoN, Nothing))) } /* Translate cache control cmds into Probe param / private def cmdToPermCap(cmd: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ MuxLookup(cmd, toN)(Seq( M_FLUSH -> toN, M_PRODUCE -> toB, M_CLEAN -> toT)) } def onCacheControl(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(cmdToPermCap(cmd)) (r._1, r._2, ClientMetadata(r._3)) } def onProbe(param: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(param) (r._1, r._2, ClientMetadata(r._3)) } } /* Factories for ClientMetadata, including on reset / object ClientMetadata { def apply(perm: UInt) = { val meta = Wire(new ClientMetadata) meta.state := perm meta } def onReset = ClientMetadata(ClientStates.Nothing) def maximum = ClientMetadata(ClientStates.Dirty) } File Replacement.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import freechips.rocketchip.util.property.cover abstract class ReplacementPolicy { def nBits: Int def perSet: Boolean def way: UInt def miss: Unit def hit: Unit def access(touch_way: UInt): Unit def access(touch_ways: Seq[Valid[UInt]]): Unit def state_read: UInt def get_next_state(state: UInt, touch_way: UInt): UInt def get_next_state(state: UInt, touch_ways: Seq[Valid[UInt]]): UInt = { touch_ways.foldLeft(state)((prev, touch_way) => Mux(touch_way.valid, get_next_state(prev, touch_way.bits), prev)) } def get_replace_way(state: UInt): UInt } object ReplacementPolicy { def fromString(s: String, n_ways: Int): ReplacementPolicy = s.toLowerCase match { case "random" => new RandomReplacement(n_ways) case "lru" => new TrueLRU(n_ways) case "plru" => new PseudoLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } } class RandomReplacement(n_ways: Int) extends ReplacementPolicy { private val replace = Wire(Bool()) replace := false.B def nBits = 16 def perSet = false private val lfsr = LFSR(nBits, replace) def state_read = WireDefault(lfsr) def way = Random(n_ways, lfsr) def miss = replace := true.B def hit = {} def access(touch_way: UInt) = {} def access(touch_ways: Seq[Valid[UInt]]) = {} def get_next_state(state: UInt, touch_way: UInt) = 0.U //DontCare def get_replace_way(state: UInt) = way } abstract class SeqReplacementPolicy { def access(set: UInt): Unit def update(valid: Bool, hit: Bool, set: UInt, way: UInt): Unit def way: UInt } abstract class SetAssocReplacementPolicy { def access(set: UInt, touch_way: UInt): Unit def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]): Unit def way(set: UInt): UInt } class SeqRandom(n_ways: Int) extends SeqReplacementPolicy { val logic = new RandomReplacement(n_ways) def access(set: UInt) = { } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { when (valid && !hit) { logic.miss } } def way = logic.way } class TrueLRU(n_ways: Int) extends ReplacementPolicy { // True LRU replacement policy, using a triangular matrix to track which sets are more recently used than others. // The matrix is packed into a single UInt (or Bits). Example 4-way (6-bits): // [5] - 3 more recent than 2 // [4] - 3 more recent than 1 // [3] - 2 more recent than 1 // [2] - 3 more recent than 0 // [1] - 2 more recent than 0 // [0] - 1 more recent than 0 def nBits = (n_ways (n_ways-1)) / 2 def perSet = true private val state_reg = RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) private def extractMRUVec(state: UInt): Seq[UInt] = { // Extract per-way information about which higher-indexed ways are more recently used val moreRecentVec = Wire(Vec(n_ways-1, UInt(n_ways.W))) var lsb = 0 for (i <- 0 until n_ways-1) { moreRecentVec(i) := Cat(state(lsb+n_ways-i-2,lsb), 0.U((i+1).W)) lsb = lsb + (n_ways - i - 1) } moreRecentVec } def get_next_state(state: UInt, touch_way: UInt): UInt = { val nextState = Wire(Vec(n_ways-1, UInt(n_ways.W))) val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix val wayDec = UIntToOH(touch_way, n_ways) // Compute next value of triangular matrix // set the touched way as more recent than every other way nextState.zipWithIndex.map { case (e, i) => e := Mux(i.U === touch_way, 0.U(n_ways.W), moreRecentVec(i) \| wayDec) } nextState.zipWithIndex.tail.foldLeft((nextState.head.apply(n_ways-1,1),0)) { case ((pe,pi),(ce,ci)) => (Cat(ce.apply(n_ways-1,ci+1), pe), ci) }._1 } def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"LRU_UpdateCount$i", s"LRU Update $i simultaneous") } } def get_replace_way(state: UInt): UInt = { val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix // For each way, determine if all other ways are more recent val mruWayDec = (0 until n_ways).map { i => val upperMoreRecent = (if (i == n_ways-1) true.B else moreRecentVec(i).apply(n_ways-1,i+1).andR) val lowerMoreRecent = (if (i == 0) true.B else moreRecentVec.map(e => !e(i)).reduce(_ && _)) upperMoreRecent && lowerMoreRecent } OHToUInt(mruWayDec) } def way = get_replace_way(state_reg) def miss = access(way) def hit = {} @deprecated("replace 'replace' with 'way' from abstract class ReplacementPolicy","Rocket Chip 2020.05") def replace: UInt = way } class PseudoLRU(n_ways: Int) extends ReplacementPolicy { // Pseudo-LRU tree algorithm: https://en.wikipedia.org/wiki/Pseudo-LRU#Tree-PLRU // // // - bits storage example for 4-way PLRU binary tree: // bit[2]: ways 3+2 older than ways 1+0 // / \ // bit[1]: way 3 older than way 2 bit[0]: way 1 older than way 0 // // // - bits storage example for 3-way PLRU binary tree: // bit[1]: way 2 older than ways 1+0 // \ // bit[0]: way 1 older than way 0 // // // - bits storage example for 8-way PLRU binary tree: // bit[6]: ways 7-4 older than ways 3-0 // / \ // bit[5]: ways 7+6 > 5+4 bit[2]: ways 3+2 > 1+0 // / \ / \ // bit[4]: way 7>6 bit[3]: way 5>4 bit[1]: way 3>2 bit[0]: way 1>0 def nBits = n_ways - 1 def perSet = true private val state_reg = if (nBits == 0) Reg(UInt(0.W)) else RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"PLRU_UpdateCount$i", s"PLRU Update $i simultaneous") } } /** @param state state_reg bits for this sub-tree * @param touch_way touched way encoded value bits for this sub-tree * @param tree_nways number of ways in this sub-tree / def get_next_state(state: UInt, touch_way: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") require(touch_way.getWidth == (log2Ceil(tree_nways) max 1), s"wrong encoded way width ${touch_way.getWidth} for $tree_nways ways") if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val set_left_older = !touch_way(log2Ceil(tree_nways)-1) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(set_left_older, Mux(set_left_older, left_subtree_state, // if setting left sub-tree as older, do NOT recurse into left sub-tree get_next_state(left_subtree_state, touch_way.extract(log2Ceil(left_nways)-1,0), left_nways)), // recurse left if newer Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(set_left_older, Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so set the single state bit opposite of the lsb of the touched way encoded value !touch_way(0) } else { // tree_nways <= 1 // we are at an empty node in an empty tree for 1 way, so return single zero bit for Chisel (no zero-width wires) 0.U(1.W) } } def get_next_state(state: UInt, touch_way: UInt): UInt = { val touch_way_sized = if (touch_way.getWidth < log2Ceil(n_ways)) touch_way.padTo (log2Ceil(n_ways)) else touch_way.extract(log2Ceil(n_ways)-1,0) get_next_state(state, touch_way_sized, n_ways) } /* @param state state_reg bits for this sub-tree * @param tree_nways number of ways in this sub-tree / def get_replace_way(state: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") // this algorithm recursively descends the binary tree, filling in the way-to-replace encoded value from msb to lsb if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val left_subtree_older = state(tree_nways-2) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, recurse left, else recurse right get_replace_way(left_subtree_state, left_nways), // recurse left get_replace_way(right_subtree_state, right_nways))) // recurse right } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, return and do not recurse right 0.U(1.W), get_replace_way(right_subtree_state, right_nways))) // recurse right } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so just return the single state bit as lsb of the way-to-replace encoded value state(0) } else { // tree_nways <= 1 // we are at an empty node in an unbalanced tree for non-power-of-2 ways, so return single zero bit as lsb of the way-to-replace encoded value 0.U(1.W) } } def get_replace_way(state: UInt): UInt = get_replace_way(state, n_ways) def way = get_replace_way(state_reg) def miss = access(way) def hit = {} } class SeqPLRU(n_sets: Int, n_ways: Int) extends SeqReplacementPolicy { val logic = new PseudoLRU(n_ways) val state = SyncReadMem(n_sets, UInt(logic.nBits.W)) val current_state = Wire(UInt(logic.nBits.W)) val next_state = Wire(UInt(logic.nBits.W)) val plru_way = logic.get_replace_way(current_state) def access(set: UInt) = { current_state := state.read(set) } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { val update_way = Mux(hit, way, plru_way) next_state := logic.get_next_state(current_state, update_way) when (valid) { state.write(set, next_state) } } def way = plru_way } class SetAssocLRU(n_sets: Int, n_ways: Int, policy: String) extends SetAssocReplacementPolicy { val logic = policy.toLowerCase match { case "plru" => new PseudoLRU(n_ways) case "lru" => new TrueLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } val state_vec = if (logic.nBits == 0) Reg(Vec(n_sets, UInt(logic.nBits.W))) // Work around elaboration error on following line else RegInit(VecInit(Seq.fill(n_sets)(0.U(logic.nBits.W)))) def access(set: UInt, touch_way: UInt) = { state_vec(set) := logic.get_next_state(state_vec(set), touch_way) } def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]) = { require(sets.size == touch_ways.size, "internal consistency check: should be same number of simultaneous updates for sets and touch_ways") for (set <- 0 until n_sets) { val set_touch_ways = (sets zip touch_ways).map { case (touch_set, touch_way) => Pipe(touch_way.valid && (touch_set === set.U), touch_way.bits, 0)} when (set_touch_ways.map(_.valid).orR) { state_vec(set) := logic.get_next_state(state_vec(set), set_touch_ways) } } } def way(set: UInt) = logic.get_replace_way(state_vec(set)) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class PLRUTest(n_ways: Int, timeout: Int = 500) extends UnitTest(timeout) { val plru = new PseudoLRU(n_ways) // step io.finished := RegNext(true.B, false.B) val get_replace_ways = (0 until (1 << (n_ways-1))).map(state => plru.get_replace_way(state = state.U((n_ways-1).W))) val get_next_states = (0 until (1 << (n_ways-1))).map(state => (0 until n_ways).map(way => plru.get_next_state (state = state.U((n_ways-1).W), touch_way = way.U(log2Ceil(n_ways).W)))) n_ways match { case 2 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_next_states(0)(0) === 1.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=1 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 0.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=0 actual=%d", get_next_states(0)(1)) assert(get_next_states(1)(0) === 1.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=1 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 0.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=0 actual=%d", get_next_states(1)(1)) } case 3 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=2 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=2 actual=%d", get_replace_ways(3)) assert(get_next_states(0)(0) === 3.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=3 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 2.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=2 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 0.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=0 actual=%d", get_next_states(0)(2)) assert(get_next_states(1)(0) === 3.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=3 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 2.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=2 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 1.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=1 actual=%d", get_next_states(1)(2)) assert(get_next_states(2)(0) === 3.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=3 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 2.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=2 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 0.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=0 actual=%d", get_next_states(2)(2)) assert(get_next_states(3)(0) === 3.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=3 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 2.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=2 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 1.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=1 actual=%d", get_next_states(3)(2)) } case 4 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=0 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=1 actual=%d", get_replace_ways(3)) assert(get_replace_ways(4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=4: expected=2 actual=%d", get_replace_ways(4)) assert(get_replace_ways(5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=5: expected=2 actual=%d", get_replace_ways(5)) assert(get_replace_ways(6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=6: expected=3 actual=%d", get_replace_ways(6)) assert(get_replace_ways(7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=7: expected=3 actual=%d", get_replace_ways(7)) assert(get_next_states(0)(0) === 5.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=5 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 4.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=4 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 2.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=2 actual=%d", get_next_states(0)(2)) assert(get_next_states(0)(3) === 0.U(plru.nBits.W), s"get_next_state state=0 way=3: expected=0 actual=%d", get_next_states(0)(3)) assert(get_next_states(1)(0) === 5.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=5 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 4.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=4 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 3.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=3 actual=%d", get_next_states(1)(2)) assert(get_next_states(1)(3) === 1.U(plru.nBits.W), s"get_next_state state=1 way=3: expected=1 actual=%d", get_next_states(1)(3)) assert(get_next_states(2)(0) === 7.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=7 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 6.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=6 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 2.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=2 actual=%d", get_next_states(2)(2)) assert(get_next_states(2)(3) === 0.U(plru.nBits.W), s"get_next_state state=2 way=3: expected=0 actual=%d", get_next_states(2)(3)) assert(get_next_states(3)(0) === 7.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=7 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 6.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=6 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 3.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=3 actual=%d", get_next_states(3)(2)) assert(get_next_states(3)(3) === 1.U(plru.nBits.W), s"get_next_state state=3 way=3: expected=1 actual=%d", get_next_states(3)(3)) assert(get_next_states(4)(0) === 5.U(plru.nBits.W), s"get_next_state state=4 way=0: expected=5 actual=%d", get_next_states(4)(0)) assert(get_next_states(4)(1) === 4.U(plru.nBits.W), s"get_next_state state=4 way=1: expected=4 actual=%d", get_next_states(4)(1)) assert(get_next_states(4)(2) === 2.U(plru.nBits.W), s"get_next_state state=4 way=2: expected=2 actual=%d", get_next_states(4)(2)) assert(get_next_states(4)(3) === 0.U(plru.nBits.W), s"get_next_state state=4 way=3: expected=0 actual=%d", get_next_states(4)(3)) assert(get_next_states(5)(0) === 5.U(plru.nBits.W), s"get_next_state state=5 way=0: expected=5 actual=%d", get_next_states(5)(0)) assert(get_next_states(5)(1) === 4.U(plru.nBits.W), s"get_next_state state=5 way=1: expected=4 actual=%d", get_next_states(5)(1)) assert(get_next_states(5)(2) === 3.U(plru.nBits.W), s"get_next_state state=5 way=2: expected=3 actual=%d", get_next_states(5)(2)) assert(get_next_states(5)(3) === 1.U(plru.nBits.W), s"get_next_state state=5 way=3: expected=1 actual=%d", get_next_states(5)(3)) assert(get_next_states(6)(0) === 7.U(plru.nBits.W), s"get_next_state state=6 way=0: expected=7 actual=%d", get_next_states(6)(0)) assert(get_next_states(6)(1) === 6.U(plru.nBits.W), s"get_next_state state=6 way=1: expected=6 actual=%d", get_next_states(6)(1)) assert(get_next_states(6)(2) === 2.U(plru.nBits.W), s"get_next_state state=6 way=2: expected=2 actual=%d", get_next_states(6)(2)) assert(get_next_states(6)(3) === 0.U(plru.nBits.W), s"get_next_state state=6 way=3: expected=0 actual=%d", get_next_states(6)(3)) assert(get_next_states(7)(0) === 7.U(plru.nBits.W), s"get_next_state state=7 way=0: expected=7 actual=%d", get_next_states(7)(0)) assert(get_next_states(7)(1) === 6.U(plru.nBits.W), s"get_next_state state=7 way=5: expected=6 actual=%d", get_next_states(7)(1)) assert(get_next_states(7)(2) === 3.U(plru.nBits.W), s"get_next_state state=7 way=2: expected=3 actual=%d", get_next_states(7)(2)) assert(get_next_states(7)(3) === 1.U(plru.nBits.W), s"get_next_state state=7 way=3: expected=1 actual=%d", get_next_states(7)(3)) } case 5 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=4 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=4 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=4 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=4 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=4 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=4 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=4 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=4 actual=%d", get_replace_ways(15)) assert(get_next_states( 0)(0) === 13.U(plru.nBits.W), s"get_next_state state=00 way=0: expected=13 actual=%d", get_next_states( 0)(0)) assert(get_next_states( 0)(1) === 12.U(plru.nBits.W), s"get_next_state state=00 way=1: expected=12 actual=%d", get_next_states( 0)(1)) assert(get_next_states( 0)(2) === 10.U(plru.nBits.W), s"get_next_state state=00 way=2: expected=10 actual=%d", get_next_states( 0)(2)) assert(get_next_states( 0)(3) === 8.U(plru.nBits.W), s"get_next_state state=00 way=3: expected=08 actual=%d", get_next_states( 0)(3)) assert(get_next_states( 0)(4) === 0.U(plru.nBits.W), s"get_next_state state=00 way=4: expected=00 actual=%d", get_next_states( 0)(4)) assert(get_next_states( 1)(0) === 13.U(plru.nBits.W), s"get_next_state state=01 way=0: expected=13 actual=%d", get_next_states( 1)(0)) assert(get_next_states( 1)(1) === 12.U(plru.nBits.W), s"get_next_state state=01 way=1: expected=12 actual=%d", get_next_states( 1)(1)) assert(get_next_states( 1)(2) === 11.U(plru.nBits.W), s"get_next_state state=01 way=2: expected=11 actual=%d", get_next_states( 1)(2)) assert(get_next_states( 1)(3) === 9.U(plru.nBits.W), s"get_next_state state=01 way=3: expected=09 actual=%d", get_next_states( 1)(3)) assert(get_next_states( 1)(4) === 1.U(plru.nBits.W), s"get_next_state state=01 way=4: expected=01 actual=%d", get_next_states( 1)(4)) assert(get_next_states( 2)(0) === 15.U(plru.nBits.W), s"get_next_state state=02 way=0: expected=15 actual=%d", get_next_states( 2)(0)) assert(get_next_states( 2)(1) === 14.U(plru.nBits.W), s"get_next_state state=02 way=1: expected=14 actual=%d", get_next_states( 2)(1)) assert(get_next_states( 2)(2) === 10.U(plru.nBits.W), s"get_next_state state=02 way=2: expected=10 actual=%d", get_next_states( 2)(2)) assert(get_next_states( 2)(3) === 8.U(plru.nBits.W), s"get_next_state state=02 way=3: expected=08 actual=%d", get_next_states( 2)(3)) assert(get_next_states( 2)(4) === 2.U(plru.nBits.W), s"get_next_state state=02 way=4: expected=02 actual=%d", get_next_states( 2)(4)) assert(get_next_states( 3)(0) === 15.U(plru.nBits.W), s"get_next_state state=03 way=0: expected=15 actual=%d", get_next_states( 3)(0)) assert(get_next_states( 3)(1) === 14.U(plru.nBits.W), s"get_next_state state=03 way=1: expected=14 actual=%d", get_next_states( 3)(1)) assert(get_next_states( 3)(2) === 11.U(plru.nBits.W), s"get_next_state state=03 way=2: expected=11 actual=%d", get_next_states( 3)(2)) assert(get_next_states( 3)(3) === 9.U(plru.nBits.W), s"get_next_state state=03 way=3: expected=09 actual=%d", get_next_states( 3)(3)) assert(get_next_states( 3)(4) === 3.U(plru.nBits.W), s"get_next_state state=03 way=4: expected=03 actual=%d", get_next_states( 3)(4)) assert(get_next_states( 4)(0) === 13.U(plru.nBits.W), s"get_next_state state=04 way=0: expected=13 actual=%d", get_next_states( 4)(0)) assert(get_next_states( 4)(1) === 12.U(plru.nBits.W), s"get_next_state state=04 way=1: expected=12 actual=%d", get_next_states( 4)(1)) assert(get_next_states( 4)(2) === 10.U(plru.nBits.W), s"get_next_state state=04 way=2: expected=10 actual=%d", get_next_states( 4)(2)) assert(get_next_states( 4)(3) === 8.U(plru.nBits.W), s"get_next_state state=04 way=3: expected=08 actual=%d", get_next_states( 4)(3)) assert(get_next_states( 4)(4) === 4.U(plru.nBits.W), s"get_next_state state=04 way=4: expected=04 actual=%d", get_next_states( 4)(4)) assert(get_next_states( 5)(0) === 13.U(plru.nBits.W), s"get_next_state state=05 way=0: expected=13 actual=%d", get_next_states( 5)(0)) assert(get_next_states( 5)(1) === 12.U(plru.nBits.W), s"get_next_state state=05 way=1: expected=12 actual=%d", get_next_states( 5)(1)) assert(get_next_states( 5)(2) === 11.U(plru.nBits.W), s"get_next_state state=05 way=2: expected=11 actual=%d", get_next_states( 5)(2)) assert(get_next_states( 5)(3) === 9.U(plru.nBits.W), s"get_next_state state=05 way=3: expected=09 actual=%d", get_next_states( 5)(3)) assert(get_next_states( 5)(4) === 5.U(plru.nBits.W), s"get_next_state state=05 way=4: expected=05 actual=%d", get_next_states( 5)(4)) assert(get_next_states( 6)(0) === 15.U(plru.nBits.W), s"get_next_state state=06 way=0: expected=15 actual=%d", get_next_states( 6)(0)) assert(get_next_states( 6)(1) === 14.U(plru.nBits.W), s"get_next_state state=06 way=1: expected=14 actual=%d", get_next_states( 6)(1)) assert(get_next_states( 6)(2) === 10.U(plru.nBits.W), s"get_next_state state=06 way=2: expected=10 actual=%d", get_next_states( 6)(2)) assert(get_next_states( 6)(3) === 8.U(plru.nBits.W), s"get_next_state state=06 way=3: expected=08 actual=%d", get_next_states( 6)(3)) assert(get_next_states( 6)(4) === 6.U(plru.nBits.W), s"get_next_state state=06 way=4: expected=06 actual=%d", get_next_states( 6)(4)) assert(get_next_states( 7)(0) === 15.U(plru.nBits.W), s"get_next_state state=07 way=0: expected=15 actual=%d", get_next_states( 7)(0)) assert(get_next_states( 7)(1) === 14.U(plru.nBits.W), s"get_next_state state=07 way=5: expected=14 actual=%d", get_next_states( 7)(1)) assert(get_next_states( 7)(2) === 11.U(plru.nBits.W), s"get_next_state state=07 way=2: expected=11 actual=%d", get_next_states( 7)(2)) assert(get_next_states( 7)(3) === 9.U(plru.nBits.W), s"get_next_state state=07 way=3: expected=09 actual=%d", get_next_states( 7)(3)) assert(get_next_states( 7)(4) === 7.U(plru.nBits.W), s"get_next_state state=07 way=4: expected=07 actual=%d", get_next_states( 7)(4)) assert(get_next_states( 8)(0) === 13.U(plru.nBits.W), s"get_next_state state=08 way=0: expected=13 actual=%d", get_next_states( 8)(0)) assert(get_next_states( 8)(1) === 12.U(plru.nBits.W), s"get_next_state state=08 way=1: expected=12 actual=%d", get_next_states( 8)(1)) assert(get_next_states( 8)(2) === 10.U(plru.nBits.W), s"get_next_state state=08 way=2: expected=10 actual=%d", get_next_states( 8)(2)) assert(get_next_states( 8)(3) === 8.U(plru.nBits.W), s"get_next_state state=08 way=3: expected=08 actual=%d", get_next_states( 8)(3)) assert(get_next_states( 8)(4) === 0.U(plru.nBits.W), s"get_next_state state=08 way=4: expected=00 actual=%d", get_next_states( 8)(4)) assert(get_next_states( 9)(0) === 13.U(plru.nBits.W), s"get_next_state state=09 way=0: expected=13 actual=%d", get_next_states( 9)(0)) assert(get_next_states( 9)(1) === 12.U(plru.nBits.W), s"get_next_state state=09 way=1: expected=12 actual=%d", get_next_states( 9)(1)) assert(get_next_states( 9)(2) === 11.U(plru.nBits.W), s"get_next_state state=09 way=2: expected=11 actual=%d", get_next_states( 9)(2)) assert(get_next_states( 9)(3) === 9.U(plru.nBits.W), s"get_next_state state=09 way=3: expected=09 actual=%d", get_next_states( 9)(3)) assert(get_next_states( 9)(4) === 1.U(plru.nBits.W), s"get_next_state state=09 way=4: expected=01 actual=%d", get_next_states( 9)(4)) assert(get_next_states(10)(0) === 15.U(plru.nBits.W), s"get_next_state state=10 way=0: expected=15 actual=%d", get_next_states(10)(0)) assert(get_next_states(10)(1) === 14.U(plru.nBits.W), s"get_next_state state=10 way=1: expected=14 actual=%d", get_next_states(10)(1)) assert(get_next_states(10)(2) === 10.U(plru.nBits.W), s"get_next_state state=10 way=2: expected=10 actual=%d", get_next_states(10)(2)) assert(get_next_states(10)(3) === 8.U(plru.nBits.W), s"get_next_state state=10 way=3: expected=08 actual=%d", get_next_states(10)(3)) assert(get_next_states(10)(4) === 2.U(plru.nBits.W), s"get_next_state state=10 way=4: expected=02 actual=%d", get_next_states(10)(4)) assert(get_next_states(11)(0) === 15.U(plru.nBits.W), s"get_next_state state=11 way=0: expected=15 actual=%d", get_next_states(11)(0)) assert(get_next_states(11)(1) === 14.U(plru.nBits.W), s"get_next_state state=11 way=1: expected=14 actual=%d", get_next_states(11)(1)) assert(get_next_states(11)(2) === 11.U(plru.nBits.W), s"get_next_state state=11 way=2: expected=11 actual=%d", get_next_states(11)(2)) assert(get_next_states(11)(3) === 9.U(plru.nBits.W), s"get_next_state state=11 way=3: expected=09 actual=%d", get_next_states(11)(3)) assert(get_next_states(11)(4) === 3.U(plru.nBits.W), s"get_next_state state=11 way=4: expected=03 actual=%d", get_next_states(11)(4)) assert(get_next_states(12)(0) === 13.U(plru.nBits.W), s"get_next_state state=12 way=0: expected=13 actual=%d", get_next_states(12)(0)) assert(get_next_states(12)(1) === 12.U(plru.nBits.W), s"get_next_state state=12 way=1: expected=12 actual=%d", get_next_states(12)(1)) assert(get_next_states(12)(2) === 10.U(plru.nBits.W), s"get_next_state state=12 way=2: expected=10 actual=%d", get_next_states(12)(2)) assert(get_next_states(12)(3) === 8.U(plru.nBits.W), s"get_next_state state=12 way=3: expected=08 actual=%d", get_next_states(12)(3)) assert(get_next_states(12)(4) === 4.U(plru.nBits.W), s"get_next_state state=12 way=4: expected=04 actual=%d", get_next_states(12)(4)) assert(get_next_states(13)(0) === 13.U(plru.nBits.W), s"get_next_state state=13 way=0: expected=13 actual=%d", get_next_states(13)(0)) assert(get_next_states(13)(1) === 12.U(plru.nBits.W), s"get_next_state state=13 way=1: expected=12 actual=%d", get_next_states(13)(1)) assert(get_next_states(13)(2) === 11.U(plru.nBits.W), s"get_next_state state=13 way=2: expected=11 actual=%d", get_next_states(13)(2)) assert(get_next_states(13)(3) === 9.U(plru.nBits.W), s"get_next_state state=13 way=3: expected=09 actual=%d", get_next_states(13)(3)) assert(get_next_states(13)(4) === 5.U(plru.nBits.W), s"get_next_state state=13 way=4: expected=05 actual=%d", get_next_states(13)(4)) assert(get_next_states(14)(0) === 15.U(plru.nBits.W), s"get_next_state state=14 way=0: expected=15 actual=%d", get_next_states(14)(0)) assert(get_next_states(14)(1) === 14.U(plru.nBits.W), s"get_next_state state=14 way=1: expected=14 actual=%d", get_next_states(14)(1)) assert(get_next_states(14)(2) === 10.U(plru.nBits.W), s"get_next_state state=14 way=2: expected=10 actual=%d", get_next_states(14)(2)) assert(get_next_states(14)(3) === 8.U(plru.nBits.W), s"get_next_state state=14 way=3: expected=08 actual=%d", get_next_states(14)(3)) assert(get_next_states(14)(4) === 6.U(plru.nBits.W), s"get_next_state state=14 way=4: expected=06 actual=%d", get_next_states(14)(4)) assert(get_next_states(15)(0) === 15.U(plru.nBits.W), s"get_next_state state=15 way=0: expected=15 actual=%d", get_next_states(15)(0)) assert(get_next_states(15)(1) === 14.U(plru.nBits.W), s"get_next_state state=15 way=5: expected=14 actual=%d", get_next_states(15)(1)) assert(get_next_states(15)(2) === 11.U(plru.nBits.W), s"get_next_state state=15 way=2: expected=11 actual=%d", get_next_states(15)(2)) assert(get_next_states(15)(3) === 9.U(plru.nBits.W), s"get_next_state state=15 way=3: expected=09 actual=%d", get_next_states(15)(3)) assert(get_next_states(15)(4) === 7.U(plru.nBits.W), s"get_next_state state=15 way=4: expected=07 actual=%d", get_next_states(15)(4)) } case 6 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=0 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=1 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=0 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=1 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=2 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=2 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=3 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=3 actual=%d", get_replace_ways(15)) assert(get_replace_ways(16) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=16: expected=4 actual=%d", get_replace_ways(16)) assert(get_replace_ways(17) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=17: expected=4 actual=%d", get_replace_ways(17)) assert(get_replace_ways(18) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=18: expected=4 actual=%d", get_replace_ways(18)) assert(get_replace_ways(19) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=19: expected=4 actual=%d", get_replace_ways(19)) assert(get_replace_ways(20) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=20: expected=4 actual=%d", get_replace_ways(20)) assert(get_replace_ways(21) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=21: expected=4 actual=%d", get_replace_ways(21)) assert(get_replace_ways(22) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=22: expected=4 actual=%d", get_replace_ways(22)) assert(get_replace_ways(23) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=23: expected=4 actual=%d", get_replace_ways(23)) assert(get_replace_ways(24) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=24: expected=5 actual=%d", get_replace_ways(24)) assert(get_replace_ways(25) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=25: expected=5 actual=%d", get_replace_ways(25)) assert(get_replace_ways(26) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=26: expected=5 actual=%d", get_replace_ways(26)) assert(get_replace_ways(27) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=27: expected=5 actual=%d", get_replace_ways(27)) assert(get_replace_ways(28) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=28: expected=5 actual=%d", get_replace_ways(28)) assert(get_replace_ways(29) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=29: expected=5 actual=%d", get_replace_ways(29)) assert(get_replace_ways(30) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=30: expected=5 actual=%d", get_replace_ways(30)) assert(get_replace_ways(31) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=31: expected=5 actual=%d", get_replace_ways(31)) } case _ => throw new IllegalArgumentException(s"no test pattern found for n_ways=$n_ways") } } File HellaCache.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3.{dontTouch, _} import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.AMBAProtField import freechips.rocketchip.diplomacy.{IdRange, TransferSizes, RegionType} import freechips.rocketchip.tile.{L1CacheParams, HasL1CacheParameters, HasCoreParameters, CoreBundle, HasNonDiplomaticTileParameters, BaseTile, HasTileParameters} import freechips.rocketchip.tilelink.{TLMasterParameters, TLClientNode, TLMasterPortParameters, TLEdgeOut, TLWidthWidget, TLFIFOFixer, ClientMetadata} import freechips.rocketchip.util.{Code, RandomReplacement, ParameterizedBundle} import freechips.rocketchip.util.{BooleanToAugmentedBoolean, IntToAugmentedInt} import scala.collection.mutable.ListBuffer case class DCacheParams( nSets: Int = 64, nWays: Int = 4, rowBits: Int = 64, subWordBits: Option[Int] = None, replacementPolicy: String = "random", nTLBSets: Int = 1, nTLBWays: Int = 32, nTLBBasePageSectors: Int = 4, nTLBSuperpages: Int = 4, tagECC: Option[String] = None, dataECC: Option[String] = None, dataECCBytes: Int = 1, nMSHRs: Int = 1, nSDQ: Int = 17, nRPQ: Int = 16, nMMIOs: Int = 1, blockBytes: Int = 64, separateUncachedResp: Boolean = false, acquireBeforeRelease: Boolean = false, pipelineWayMux: Boolean = false, clockGate: Boolean = false, scratch: Option[BigInt] = None) extends L1CacheParams { def tagCode: Code = Code.fromString(tagECC) def dataCode: Code = Code.fromString(dataECC) def dataScratchpadBytes: Int = scratch.map(_ => nSetsblockBytes).getOrElse(0) def replacement = new RandomReplacement(nWays) def silentDrop: Boolean = !acquireBeforeRelease require((!scratch.isDefined \|\| nWays == 1), "Scratchpad only allowed in direct-mapped cache.") require((!scratch.isDefined \|\| nMSHRs == 0), "Scratchpad only allowed in blocking cache.") if (scratch.isEmpty) require(isPow2(nSets), s"nSets($nSets) must be pow2") } trait HasL1HellaCacheParameters extends HasL1CacheParameters with HasCoreParameters { val cacheParams = tileParams.dcache.get val cfg = cacheParams def wordBits = coreDataBits def wordBytes = coreDataBytes def subWordBits = cacheParams.subWordBits.getOrElse(wordBits) def subWordBytes = subWordBits / 8 def wordOffBits = log2Up(wordBytes) def beatBytes = cacheBlockBytes / cacheDataBeats def beatWords = beatBytes / wordBytes def beatOffBits = log2Up(beatBytes) def idxMSB = untagBits-1 def idxLSB = blockOffBits def offsetmsb = idxLSB-1 def offsetlsb = wordOffBits def rowWords = rowBits/wordBits def doNarrowRead = coreDataBits * nWays % rowBits == 0 def eccBytes = cacheParams.dataECCBytes val eccBits = cacheParams.dataECCBytes * 8 val encBits = cacheParams.dataCode.width(eccBits) val encWordBits = encBits * (wordBits / eccBits) def encDataBits = cacheParams.dataCode.width(coreDataBits) // NBDCache only def encRowBits = encDataBitsrowWords def lrscCycles = coreParams.lrscCycles // ISA requires 16-insn LRSC sequences to succeed def lrscBackoff = 3 // disallow LRSC reacquisition briefly def blockProbeAfterGrantCycles = 8 // give the processor some time to issue a request after a grant def nIOMSHRs = cacheParams.nMMIOs def maxUncachedInFlight = cacheParams.nMMIOs def dataScratchpadSize = cacheParams.dataScratchpadBytes require(rowBits >= coreDataBits, s"rowBits($rowBits) < coreDataBits($coreDataBits)") if (!usingDataScratchpad) require(rowBits == cacheDataBits, s"rowBits($rowBits) != cacheDataBits($cacheDataBits)") // would need offset addr for puts if data width < xlen require(xLen <= cacheDataBits, s"xLen($xLen) > cacheDataBits($cacheDataBits)") } abstract class L1HellaCacheModule(implicit val p: Parameters) extends Module with HasL1HellaCacheParameters abstract class L1HellaCacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p) with HasL1HellaCacheParameters /* Bundle definitions for HellaCache interfaces / trait HasCoreMemOp extends HasL1HellaCacheParameters { val addr = UInt(coreMaxAddrBits.W) val idx = (usingVM && untagBits > pgIdxBits).option(UInt(coreMaxAddrBits.W)) val tag = UInt((coreParams.dcacheReqTagBits + log2Ceil(dcacheArbPorts)).W) val cmd = UInt(M_SZ.W) val size = UInt(log2Ceil(coreDataBytes.log2 + 1).W) val signed = Bool() val dprv = UInt(PRV.SZ.W) val dv = Bool() } trait HasCoreData extends HasCoreParameters { val data = UInt(coreDataBits.W) val mask = UInt(coreDataBytes.W) } class HellaCacheReqInternal(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp { val phys = Bool() val no_resp = Bool() // The dcache may omit generating a response for this request val no_alloc = Bool() val no_xcpt = Bool() } class HellaCacheReq(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasCoreData class HellaCacheResp(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp with HasCoreData { val replay = Bool() val has_data = Bool() val data_word_bypass = UInt(coreDataBits.W) val data_raw = UInt(coreDataBits.W) val store_data = UInt(coreDataBits.W) } class AlignmentExceptions extends Bundle { val ld = Bool() val st = Bool() } class HellaCacheExceptions extends Bundle { val ma = new AlignmentExceptions val pf = new AlignmentExceptions val gf = new AlignmentExceptions val ae = new AlignmentExceptions } class HellaCacheWriteData(implicit p: Parameters) extends CoreBundle()(p) with HasCoreData class HellaCachePerfEvents extends Bundle { val acquire = Bool() val release = Bool() val grant = Bool() val tlbMiss = Bool() val blocked = Bool() val canAcceptStoreThenLoad = Bool() val canAcceptStoreThenRMW = Bool() val canAcceptLoadThenLoad = Bool() val storeBufferEmptyAfterLoad = Bool() val storeBufferEmptyAfterStore = Bool() } // interface between D$ and processor/DTLB class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) { val req = Decoupled(new HellaCacheReq) val s1_kill = Output(Bool()) // kill previous cycle's req val s1_data = Output(new HellaCacheWriteData()) // data for previous cycle's req val s2_nack = Input(Bool()) // req from two cycles ago is rejected val s2_nack_cause_raw = Input(Bool()) // reason for nack is store-load RAW hazard (performance hint) val s2_kill = Output(Bool()) // kill req from two cycles ago val s2_uncached = Input(Bool()) // advisory signal that the access is MMIO val s2_paddr = Input(UInt(paddrBits.W)) // translated address val resp = Flipped(Valid(new HellaCacheResp)) val replay_next = Input(Bool()) val s2_xcpt = Input(new HellaCacheExceptions) val s2_gpa = Input(UInt(vaddrBitsExtended.W)) val s2_gpa_is_pte = Input(Bool()) val uncached_resp = tileParams.dcache.get.separateUncachedResp.option(Flipped(Decoupled(new HellaCacheResp))) val ordered = Input(Bool()) val store_pending = Input(Bool()) // there is a store in a store buffer somewhere val perf = Input(new HellaCachePerfEvents()) val keep_clock_enabled = Output(Bool()) // should D$ avoid clock-gating itself? val clock_enabled = Input(Bool()) // is D$ currently being clocked? } /* Base classes for Diplomatic TL2 HellaCaches / abstract class HellaCache(tileId: Int)(implicit p: Parameters) extends LazyModule with HasNonDiplomaticTileParameters { protected val cfg = tileParams.dcache.get protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache", sourceId = IdRange(0, 1 max cfg.nMSHRs), supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes)))) protected def mmioClientParameters = Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache MMIO", sourceId = IdRange(firstMMIO, firstMMIO + cfg.nMMIOs), requestFifo = true)) def firstMMIO = (cacheClientParameters.map(_.sourceId.end) :+ 0).max val node = TLClientNode(Seq(TLMasterPortParameters.v1( clients = cacheClientParameters ++ mmioClientParameters, minLatency = 1, requestFields = tileParams.core.useVM.option(Seq()).getOrElse(Seq(AMBAProtField()))))) val hartIdSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val mmioAddressPrefixSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val module: HellaCacheModule def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireB \|\| !m.executable \|\| m.regionType >= RegionType.TRACKED \|\| m.regionType <= RegionType.IDEMPOTENT) def canSupportCFlushLine = !usingVM \|\| cfg.blockBytes cfg.nSets <= (1 << pgIdxBits) require(!tileParams.core.haveCFlush \|\| cfg.scratch.isEmpty, "CFLUSH_D_L1 instruction requires a D$") } class HellaCacheBundle(implicit p: Parameters) extends CoreBundle()(p) { val cpu = Flipped(new HellaCacheIO) val ptw = new TLBPTWIO() val errors = new DCacheErrors val tlb_port = new DCacheTLBPort } class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer) with HasL1HellaCacheParameters { implicit val edge: TLEdgeOut = outer.node.edges.out(0) val (tl_out, _) = outer.node.out(0) val io = IO(new HellaCacheBundle) val io_hartid = outer.hartIdSinkNodeOpt.map(_.bundle) val io_mmio_address_prefix = outer.mmioAddressPrefixSinkNodeOpt.map(_.bundle) dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some signals dontTouch(io.cpu.s1_data) require(rowBits == edge.bundle.dataBits) private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile) fifoManagers.foreach { m => require (m.fifoId == fifoManagers.head.fifoId, s"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees\n"+ s"${m.nodePath.map(_.name)}\nversus\n${fifoManagers.head.nodePath.map(_.name)}") } } /** Support overriding which HellaCache is instantiated / case object BuildHellaCache extends Field[BaseTile => Parameters => HellaCache](HellaCacheFactory.apply) object HellaCacheFactory { def apply(tile: BaseTile)(p: Parameters): HellaCache = { if (tile.tileParams.dcache.get.nMSHRs == 0) new DCache(tile.tileId, tile.crossing)(p) else new NonBlockingDCache(tile.tileId)(p) } } /* Mix-ins for constructing tiles that have a HellaCache / trait HasHellaCache { this: BaseTile => val module: HasHellaCacheModule implicit val p: Parameters var nDCachePorts = 0 lazy val dcache: HellaCache = LazyModule(p(BuildHellaCache)(this)(p)) tlMasterXbar.node := TLWidthWidget(tileParams.dcache.get.rowBits/8) := dcache.node dcache.hartIdSinkNodeOpt.map { _ := hartIdNexusNode } dcache.mmioAddressPrefixSinkNodeOpt.map { _ := mmioAddressPrefixNexusNode } InModuleBody { dcache.module.io.tlb_port := DontCare } } trait HasHellaCacheModule { val outer: HasHellaCache with HasTileParameters implicit val p: Parameters val dcachePorts = ListBuffer[HellaCacheIO]() val dcacheArb = Module(new HellaCacheArbiter(outer.nDCachePorts)(outer.p)) outer.dcache.module.io.cpu <> dcacheArb.io.mem } /* Metadata array used for all HellaCaches / class L1Metadata(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val coh = new ClientMetadata val tag = UInt(tagBits.W) } object L1Metadata { def apply(tag: Bits, coh: ClientMetadata)(implicit p: Parameters) = { val meta = Wire(new L1Metadata) meta.tag := tag meta.coh := coh meta } } class L1MetaReadReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val idx = UInt(idxBits.W) val way_en = UInt(nWays.W) val tag = UInt(tagBits.W) } class L1MetaWriteReq(implicit p: Parameters) extends L1MetaReadReq()(p) { val data = new L1Metadata } class L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters) extends L1HellaCacheModule()(p) { val rstVal = onReset() val io = IO(new Bundle { val read = Flipped(Decoupled(new L1MetaReadReq)) val write = Flipped(Decoupled(new L1MetaWriteReq)) val resp = Output(Vec(nWays, rstVal.cloneType)) }) val rst_cnt = RegInit(0.U(log2Up(nSets+1).W)) val rst = rst_cnt < nSets.U val waddr = Mux(rst, rst_cnt, io.write.bits.idx) val wdata = Mux(rst, rstVal, io.write.bits.data).asUInt val wmask = Mux(rst \|\| (nWays == 1).B, (-1).S, io.write.bits.way_en.asSInt).asBools val rmask = Mux(rst \|\| (nWays == 1).B, (-1).S, io.read.bits.way_en.asSInt).asBools when (rst) { rst_cnt := rst_cnt+1.U } val metabits = rstVal.getWidth val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(metabits.W))) val wen = rst \|\| io.write.valid when (wen) { tag_array.write(waddr, VecInit.fill(nWays)(wdata), wmask) } io.resp := tag_array.read(io.read.bits.idx, io.read.fire).map(_.asTypeOf(chiselTypeOf(rstVal))) io.read.ready := !wen // so really this could be a 6T RAM io.write.ready := !rst } File ECC.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR abstract class Decoding { def uncorrected: UInt def corrected: UInt def correctable: Bool def uncorrectable: Bool // If true, correctable should be ignored def error = correctable \|\| uncorrectable } abstract class Code { def canDetect: Boolean def canCorrect: Boolean def width(w0: Int): Int /* Takes the unencoded width and returns a list of indices indicating which * bits of the encoded value will be used for ecc / def eccIndices(width: Int): Seq[Int] /* Encode x to a codeword suitable for decode. * If poison is true, the decoded value will report uncorrectable * error despite uncorrected == corrected == x. / def encode(x: UInt, poison: Bool = false.B): UInt def decode(x: UInt): Decoding /* Copy the bits in x to the right bit positions in an encoded word, * so that x === decode(swizzle(x)).uncorrected; but don't generate * the other code bits, so decode(swizzle(x)).error might be true. * For codes for which this operation is not trivial, throw an * UnsupportedOperationException. / def swizzle(x: UInt): UInt } class IdentityCode extends Code { def canDetect = false def canCorrect = false def width(w0: Int) = w0 def eccIndices(width: Int) = Seq.empty[Int] def encode(x: UInt, poison: Bool = false.B) = { require (poison.isLit && poison.litValue == 0, "IdentityCode can not be poisoned") x } def swizzle(x: UInt) = x def decode(y: UInt) = new Decoding { def uncorrected = y def corrected = y def correctable = false.B def uncorrectable = false.B } } class ParityCode extends Code { def canDetect = true def canCorrect = false def width(w0: Int) = w0+1 def eccIndices(w0: Int) = Seq(w0) def encode(x: UInt, poison: Bool = false.B) = Cat(x.xorR ^ poison, x) def swizzle(x: UInt) = Cat(false.B, x) def decode(y: UInt) = new Decoding { val uncorrected = y(y.getWidth-2,0) val corrected = uncorrected val correctable = false.B val uncorrectable = y.xorR } } class SECCode extends Code { def canDetect = true def canCorrect = true // SEC codes may or may not be poisonous depending on the length // If the code is perfect, every non-codeword is correctable def poisonous(n: Int) = !isPow2(n+1) def width(k: Int) = { val m = log2Floor(k) + 1 k + m + (if((1 << m) < m+k+1) 1 else 0) } def eccIndices(w0: Int) = { (0 until width(w0)).collect { case i if i >= w0 => i } } def swizzle(x: UInt) = { val k = x.getWidth val n = width(k) Cat(0.U((n-k).W), x) } // An (n=16, k=11) Hamming code is naturally encoded as: // PPxPxxxPxxxxxxxP where P are parity bits and x are data // Indexes typically start at 1, because then the P are on powers of two // In systematic coding, you put all the data in the front: // xxxxxxxxxxxPPPPP // Indexes typically start at 0, because Computer Science // For sanity when reading SRAMs, you want systematic form. private def impl(n: Int, k: Int) = { require (n >= 3 && k >= 1 && !isPow2(n)) val hamm2sys = IndexedSeq.tabulate(n+1) { i => if (i == 0) { n / undefined / } else if (isPow2(i)) { k + log2Ceil(i) } else { i - 1 - log2Ceil(i) } } val sys2hamm = hamm2sys.zipWithIndex.sortBy(_._1).map(_._2).toIndexedSeq def syndrome(j: Int) = { val bit = 1 << j ("b" + Seq.tabulate(n) { i => if ((sys2hamm(i) & bit) != 0) "1" else "0" }.reverse.mkString).U } (hamm2sys, sys2hamm, syndrome _) } def encode(x: UInt, poison: Bool = false.B) = { val k = x.getWidth val n = width(k) val (_, _, syndrome) = impl(n, k) require ((poison.isLit && poison.litValue == 0) \|\| poisonous(n), s"SEC code of length ${n} cannot be poisoned") / By setting the entire syndrome on poison, the corrected bit falls off the end of the code / val syndromeUInt = VecInit.tabulate(n-k) { j => (syndrome(j)(k-1, 0) & x).xorR ^ poison }.asUInt Cat(syndromeUInt, x) } def decode(y: UInt) = new Decoding { val n = y.getWidth val k = n - log2Ceil(n) val (_, sys2hamm, syndrome) = impl(n, k) val syndromeUInt = VecInit.tabulate(n-k) { j => (syndrome(j) & y).xorR }.asUInt val hammBadBitOH = UIntToOH(syndromeUInt, n+1) val sysBadBitOH = VecInit.tabulate(k) { i => hammBadBitOH(sys2hamm(i)) }.asUInt val uncorrected = y(k-1, 0) val corrected = uncorrected ^ sysBadBitOH val correctable = syndromeUInt.orR val uncorrectable = if (poisonous(n)) { syndromeUInt > n.U } else { false.B } } } class SECDEDCode extends Code { def canDetect = true def canCorrect = true private val sec = new SECCode private val par = new ParityCode def width(k: Int) = sec.width(k)+1 def eccIndices(w0: Int) = { (0 until width(w0)).collect { case i if i >= w0 => i } } def encode(x: UInt, poison: Bool = false.B) = { // toggling two bits ensures the error is uncorrectable // to ensure corrected == uncorrected, we pick one redundant // bit from SEC (the highest); correcting it does not affect // corrected == uncorrected. the second toggled bit is the // parity bit, which also does not appear in the decoding val toggle_lo = Cat(poison.asUInt, poison.asUInt) val toggle_hi = toggle_lo << (sec.width(x.getWidth)-1) par.encode(sec.encode(x)) ^ toggle_hi } def swizzle(x: UInt) = par.swizzle(sec.swizzle(x)) def decode(x: UInt) = new Decoding { val secdec = sec.decode(x(x.getWidth-2,0)) val pardec = par.decode(x) val uncorrected = secdec.uncorrected val corrected = secdec.corrected val correctable = pardec.uncorrectable val uncorrectable = !pardec.uncorrectable && secdec.correctable } } object ErrGen { // generate a 1-bit error with approximate probability 2^-f def apply(width: Int, f: Int): UInt = { require(width > 0 && f >= 0 && log2Up(width) + f <= 16) UIntToOH(LFSR(16)(log2Up(width)+f-1,0))(width-1,0) } def apply(x: UInt, f: Int): UInt = x ^ apply(x.getWidth, f) } trait CanHaveErrors extends Bundle { val correctable: Option[ValidIO[UInt]] val uncorrectable: Option[ValidIO[UInt]] } case class ECCParams( bytes: Int = 1, code: Code = new IdentityCode, notifyErrors: Boolean = false, ) object Code { def fromString(s: Option[String]): Code = fromString(s.getOrElse("none")) def fromString(s: String): Code = s.toLowerCase match { case "none" => new IdentityCode case "identity" => new IdentityCode case "parity" => new ParityCode case "sec" => new SECCode case "secded" => new SECDEDCode case _ => throw new IllegalArgumentException("Unknown ECC type") } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class ECCTest(k: Int, timeout: Int = 500000) extends UnitTest(timeout) { val code = new SECDEDCode val n = code.width(k) // Brute force the decode space val test = RegInit(0.U((n+1).W)) val last = test(n) test := test + !last io.finished := RegNext(last, false.B) // Confirm the decoding matches the encoding val decoded = code.decode(test(n-1, 0)) val recoded = code.encode(decoded.corrected) val distance = PopCount(recoded ^ test) // Count the cases val correct = RegInit(0.U(n.W)) val correctable = RegInit(0.U(n.W)) val uncorrectable = RegInit(0.U(n.W)) when (!last) { when (decoded.uncorrectable) { assert (distance >= 2.U) // uncorrectable uncorrectable := uncorrectable + 1.U } .elsewhen (decoded.correctable) { assert (distance(0)) // correctable => odd bit errors correctable := correctable + 1.U } .otherwise { assert (distance === 0.U) // correct assert (decoded.uncorrected === decoded.corrected) correct := correct + 1.U } } // Expected number of each case val nCodes = BigInt(1) << n val nCorrect = BigInt(1) << k val nCorrectable = nCodes / 2 val nUncorrectable = nCodes - nCorrectable - nCorrect when (last) { assert (correct === nCorrect.U) assert (correctable === nCorrectable.U) assert (uncorrectable === nUncorrectable.U) } } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) \|\| isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR \|\| cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) \|\| isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR \|\| cmd === M_PWR \|\| cmd === M_XSC \|\| isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) \|\| cmd === M_PFW \|\| cmd === M_XLR } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File TLB.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.diplomacy.RegionType import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile.{CoreModule, CoreBundle} import freechips.rocketchip.tilelink._ import freechips.rocketchip.util.{OptimizationBarrier, SetAssocLRU, PseudoLRU, PopCountAtLeast, property} import freechips.rocketchip.util.BooleanToAugmentedBoolean import freechips.rocketchip.util.IntToAugmentedInt import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.UIntIsOneOf import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.SeqBoolBitwiseOps case object ASIdBits extends Field[Int](0) case object VMIdBits extends Field[Int](0) /* =SFENCE= * rs1 rs2 * {{{ * 0 0 -> flush All * 0 1 -> flush by ASID * 1 1 -> flush by ADDR * 1 0 -> flush by ADDR and ASID * }}} * {{{ * If rs1=x0 and rs2=x0, the fence orders all reads and writes made to any level of the page tables, for all address spaces. * If rs1=x0 and rs2!=x0, the fence orders all reads and writes made to any level of the page tables, but only for the address space identified by integer register rs2. Accesses to global mappings (see Section 4.3.1) are not ordered. * If rs1!=x0 and rs2=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for all address spaces. * If rs1!=x0 and rs2!=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for the address space identified by integer register rs2. Accesses to global mappings are not ordered. * }}} / class SFenceReq(implicit p: Parameters) extends CoreBundle()(p) { val rs1 = Bool() val rs2 = Bool() val addr = UInt(vaddrBits.W) val asid = UInt((asIdBits max 1).W) // TODO zero-width val hv = Bool() val hg = Bool() } class TLBReq(lgMaxSize: Int)(implicit p: Parameters) extends CoreBundle()(p) { /* request address from CPU. / val vaddr = UInt(vaddrBitsExtended.W) /* don't lookup TLB, bypass vaddr as paddr / val passthrough = Bool() /* granularity / val size = UInt(log2Ceil(lgMaxSize + 1).W) /* memory command. / val cmd = Bits(M_SZ.W) val prv = UInt(PRV.SZ.W) /* virtualization mode / val v = Bool() } class TLBExceptions extends Bundle { val ld = Bool() val st = Bool() val inst = Bool() } class TLBResp(lgMaxSize: Int = 3)(implicit p: Parameters) extends CoreBundle()(p) { // lookup responses val miss = Bool() /* physical address / val paddr = UInt(paddrBits.W) val gpa = UInt(vaddrBitsExtended.W) val gpa_is_pte = Bool() /* page fault exception / val pf = new TLBExceptions /* guest page fault exception / val gf = new TLBExceptions /* access exception / val ae = new TLBExceptions /* misaligned access exception / val ma = new TLBExceptions /* if this address is cacheable / val cacheable = Bool() /* if caches must allocate this address / val must_alloc = Bool() /* if this address is prefetchable for caches/ val prefetchable = Bool() /* size/cmd of request that generated this response/ val size = UInt(log2Ceil(lgMaxSize + 1).W) val cmd = UInt(M_SZ.W) } class TLBEntryData(implicit p: Parameters) extends CoreBundle()(p) { val ppn = UInt(ppnBits.W) /* pte.u user / val u = Bool() /* pte.g global / val g = Bool() /* access exception. * D$ -> PTW -> TLB AE * Alignment failed. / val ae_ptw = Bool() val ae_final = Bool() val ae_stage2 = Bool() /* page fault / val pf = Bool() /* guest page fault / val gf = Bool() /* supervisor write / val sw = Bool() /* supervisor execute / val sx = Bool() /* supervisor read / val sr = Bool() /* hypervisor write / val hw = Bool() /* hypervisor excute / val hx = Bool() /* hypervisor read / val hr = Bool() /* prot_w / val pw = Bool() /* prot_x / val px = Bool() /* prot_r / val pr = Bool() /* PutPartial / val ppp = Bool() /* AMO logical / val pal = Bool() /* AMO arithmetic / val paa = Bool() /* get/put effects / val eff = Bool() /* cacheable / val c = Bool() /* fragmented_superpage support / val fragmented_superpage = Bool() } /* basic cell for TLB data / class TLBEntry(val nSectors: Int, val superpage: Boolean, val superpageOnly: Boolean)(implicit p: Parameters) extends CoreBundle()(p) { require(nSectors == 1 \|\| !superpage) require(!superpageOnly \|\| superpage) val level = UInt(log2Ceil(pgLevels).W) /* use vpn as tag / val tag_vpn = UInt(vpnBits.W) /* tag in vitualization mode / val tag_v = Bool() /* entry data / val data = Vec(nSectors, UInt(new TLBEntryData().getWidth.W)) /* valid bit / val valid = Vec(nSectors, Bool()) /* returns all entry data in this entry / def entry_data = data.map(_.asTypeOf(new TLBEntryData)) /* returns the index of sector / private def sectorIdx(vpn: UInt) = vpn.extract(nSectors.log2-1, 0) /* returns the entry data matched with this vpn/ def getData(vpn: UInt) = OptimizationBarrier(data(sectorIdx(vpn)).asTypeOf(new TLBEntryData)) /* returns whether a sector hits / def sectorHit(vpn: UInt, virtual: Bool) = valid.orR && sectorTagMatch(vpn, virtual) /* returns whether tag matches vpn / def sectorTagMatch(vpn: UInt, virtual: Bool) = (((tag_vpn ^ vpn) >> nSectors.log2) === 0.U) && (tag_v === virtual) /* returns hit signal / def hit(vpn: UInt, virtual: Bool): Bool = { if (superpage && usingVM) { var tagMatch = valid.head && (tag_v === virtual) for (j <- 0 until pgLevels) { val base = (pgLevels - 1 - j) pgLevelBits val n = pgLevelBits + (if (j == 0) hypervisorExtraAddrBits else 0) val ignore = level < j.U \|\| (superpageOnly && j == pgLevels - 1).B tagMatch = tagMatch && (ignore \|\| (tag_vpn ^ vpn)(base + n - 1, base) === 0.U) } tagMatch } else { val idx = sectorIdx(vpn) valid(idx) && sectorTagMatch(vpn, virtual) } } /** returns the ppn of the input TLBEntryData / def ppn(vpn: UInt, data: TLBEntryData) = { val supervisorVPNBits = pgLevels pgLevelBits if (superpage && usingVM) { var res = data.ppn >> pgLevelBits(pgLevels - 1) for (j <- 1 until pgLevels) { val ignore = level < j.U \|\| (superpageOnly && j == pgLevels - 1).B res = Cat(res, (Mux(ignore, vpn, 0.U) \| data.ppn)(supervisorVPNBits - jpgLevelBits - 1, supervisorVPNBits - (j + 1)pgLevelBits)) } res } else { data.ppn } } /* does the refill * * find the target entry with vpn tag * and replace the target entry with the input entry data / def insert(vpn: UInt, virtual: Bool, level: UInt, entry: TLBEntryData): Unit = { this.tag_vpn := vpn this.tag_v := virtual this.level := level.extract(log2Ceil(pgLevels - superpageOnly.toInt)-1, 0) val idx = sectorIdx(vpn) valid(idx) := true.B data(idx) := entry.asUInt } def invalidate(): Unit = { valid.foreach(_ := false.B) } def invalidate(virtual: Bool): Unit = { for ((v, e) <- valid zip entry_data) when (tag_v === virtual) { v := false.B } } def invalidateVPN(vpn: UInt, virtual: Bool): Unit = { if (superpage) { when (hit(vpn, virtual)) { invalidate() } } else { when (sectorTagMatch(vpn, virtual)) { for (((v, e), i) <- (valid zip entry_data).zipWithIndex) when (tag_v === virtual && i.U === sectorIdx(vpn)) { v := false.B } } } // For fragmented superpage mappings, we assume the worst (largest) // case, and zap entries whose most-significant VPNs match when (((tag_vpn ^ vpn) >> (pgLevelBits (pgLevels - 1))) === 0.U) { for ((v, e) <- valid zip entry_data) when (tag_v === virtual && e.fragmented_superpage) { v := false.B } } } def invalidateNonGlobal(virtual: Bool): Unit = { for ((v, e) <- valid zip entry_data) when (tag_v === virtual && !e.g) { v := false.B } } } /** TLB config * * @param nSets the number of sets of PTE, follow [[ICacheParams.nSets]] * @param nWays the total number of wayss of PTE, follow [[ICacheParams.nWays]] * @param nSectors the number of ways in a single PTE TLBEntry * @param nSuperpageEntries the number of SuperpageEntries / case class TLBConfig( nSets: Int, nWays: Int, nSectors: Int = 4, nSuperpageEntries: Int = 4) /* =Overview= * [[TLB]] is a TLB template which contains PMA logic and PMP checker. * * TLB caches PTE and accelerates the address translation process. * When tlb miss happens, ask PTW(L2TLB) for Page Table Walk. * Perform PMP and PMA check during the translation and throw exception if there were any. * * ==Cache Structure== * - Sectored Entry (PTE) * - set-associative or direct-mapped * - nsets = [[TLBConfig.nSets]] * - nways = [[TLBConfig.nWays]] / [[TLBConfig.nSectors]] * - PTEEntry( sectors = [[TLBConfig.nSectors]] ) * - LRU(if set-associative) * * - Superpage Entry(superpage PTE) * - fully associative * - nsets = [[TLBConfig.nSuperpageEntries]] * - PTEEntry(sectors = 1) * - PseudoLRU * * - Special Entry(PTE across PMP) * - nsets = 1 * - PTEEntry(sectors = 1) * * ==Address structure== * {{{ * \|vaddr \| * \|ppn/vpn \| pgIndex \| * \| \| \| * \| \|nSets \|nSector \| \|}}} * * ==State Machine== * {{{ * s_ready: ready to accept request from CPU. * s_request: when L1TLB(this) miss, send request to PTW(L2TLB), . * s_wait: wait for PTW to refill L1TLB. * s_wait_invalidate: L1TLB is waiting for respond from PTW, but L1TLB will invalidate respond from PTW.}}} * * ==PMP== * pmp check * - special_entry: always check * - other entry: check on refill * * ==Note== * PMA consume diplomacy parameter generate physical memory address checking logic * * Boom use Rocket ITLB, and its own DTLB. * * Accelerators:{{{ * sha3: DTLB * gemmini: DTLB * hwacha: DTLB2+ITLB}}} @param instruction true for ITLB, false for DTLB * @param lgMaxSize @todo seems granularity * @param cfg [[TLBConfig]] * @param edge collect SoC metadata. / class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { override def desiredName = if (instruction) "ITLB" else "DTLB" val io = IO(new Bundle { /* request from Core / val req = Flipped(Decoupled(new TLBReq(lgMaxSize))) /* response to Core / val resp = Output(new TLBResp(lgMaxSize)) /* SFence Input / val sfence = Flipped(Valid(new SFenceReq)) /* IO to PTW / val ptw = new TLBPTWIO /* suppress a TLB refill, one cycle after a miss / val kill = Input(Bool()) }) io.ptw.customCSRs := DontCare val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) val vpn = io.req.bits.vaddr(vaddrBits-1, pgIdxBits) /* index for sectored_Entry / val memIdx = vpn.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2) /* TLB Entry / val sectored_entries = Reg(Vec(cfg.nSets, Vec(cfg.nWays / cfg.nSectors, new TLBEntry(cfg.nSectors, false, false)))) /* Superpage Entry / val superpage_entries = Reg(Vec(cfg.nSuperpageEntries, new TLBEntry(1, true, true))) /* Special Entry * * If PMP granularity is less than page size, thus need additional "special" entry manage PMP. / val special_entry = (!pageGranularityPMPs).option(Reg(new TLBEntry(1, true, false))) def ordinary_entries = sectored_entries(memIdx) ++ superpage_entries def all_entries = ordinary_entries ++ special_entry def all_real_entries = sectored_entries.flatten ++ superpage_entries ++ special_entry val s_ready :: s_request :: s_wait :: s_wait_invalidate :: Nil = Enum(4) val state = RegInit(s_ready) // use vpn as refill_tag val r_refill_tag = Reg(UInt(vpnBits.W)) val r_superpage_repl_addr = Reg(UInt(log2Ceil(superpage_entries.size).W)) val r_sectored_repl_addr = Reg(UInt(log2Ceil(sectored_entries.head.size).W)) val r_sectored_hit = Reg(Valid(UInt(log2Ceil(sectored_entries.head.size).W))) val r_superpage_hit = Reg(Valid(UInt(log2Ceil(superpage_entries.size).W))) val r_vstage1_en = Reg(Bool()) val r_stage2_en = Reg(Bool()) val r_need_gpa = Reg(Bool()) val r_gpa_valid = Reg(Bool()) val r_gpa = Reg(UInt(vaddrBits.W)) val r_gpa_vpn = Reg(UInt(vpnBits.W)) val r_gpa_is_pte = Reg(Bool()) /* privilege mode / val priv = io.req.bits.prv val priv_v = usingHypervisor.B && io.req.bits.v val priv_s = priv(0) // user mode and supervisor mode val priv_uses_vm = priv <= PRV.S.U val satp = Mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) val stage1_en = usingVM.B && satp.mode(satp.mode.getWidth-1) /* VS-stage translation enable / val vstage1_en = usingHypervisor.B && priv_v && io.ptw.vsatp.mode(io.ptw.vsatp.mode.getWidth-1) /* G-stage translation enable / val stage2_en = usingHypervisor.B && priv_v && io.ptw.hgatp.mode(io.ptw.hgatp.mode.getWidth-1) /* Enable Virtual Memory when: * 1. statically configured * 1. satp highest bits enabled * i. RV32: * - 0 -> Bare * - 1 -> SV32 * i. RV64: * - 0000 -> Bare * - 1000 -> SV39 * - 1001 -> SV48 * - 1010 -> SV57 * - 1011 -> SV64 * 1. In virtualization mode, vsatp highest bits enabled * 1. priv mode in U and S. * 1. in H & M mode, disable VM. * 1. no passthrough(micro-arch defined.) * * @see RV-priv spec 4.1.11 Supervisor Address Translation and Protection (satp) Register * @see RV-priv spec 8.2.18 Virtual Supervisor Address Translation and Protection Register (vsatp) / val vm_enabled = (stage1_en \|\| stage2_en) && priv_uses_vm && !io.req.bits.passthrough // flush guest entries on vsatp.MODE Bare <-> SvXX transitions val v_entries_use_stage1 = RegInit(false.B) val vsatp_mode_mismatch = priv_v && (vstage1_en =/= v_entries_use_stage1) && !io.req.bits.passthrough // share a single physical memory attribute checker (unshare if critical path) val refill_ppn = io.ptw.resp.bits.pte.ppn(ppnBits-1, 0) /* refill signal / val do_refill = usingVM.B && io.ptw.resp.valid /* sfence invalidate refill / val invalidate_refill = state.isOneOf(s_request / don't care /, s_wait_invalidate) \|\| io.sfence.valid // PMP val mpu_ppn = Mux(do_refill, refill_ppn, Mux(vm_enabled && special_entry.nonEmpty.B, special_entry.map(e => e.ppn(vpn, e.getData(vpn))).getOrElse(0.U), io.req.bits.vaddr >> pgIdxBits)) val mpu_physaddr = Cat(mpu_ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) val mpu_priv = Mux[UInt](usingVM.B && (do_refill \|\| io.req.bits.passthrough / PTW /), PRV.S.U, Cat(io.ptw.status.debug, priv)) val pmp = Module(new PMPChecker(lgMaxSize)) pmp.io.addr := mpu_physaddr pmp.io.size := io.req.bits.size pmp.io.pmp := (io.ptw.pmp: Seq[PMP]) pmp.io.prv := mpu_priv val pma = Module(new PMAChecker(edge.manager)(p)) pma.io.paddr := mpu_physaddr // todo: using DataScratchpad doesn't support cacheable. val cacheable = pma.io.resp.cacheable && (instruction \|\| !usingDataScratchpad).B val homogeneous = TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), BigInt(1) << pgIdxBits, 1 << lgMaxSize)(mpu_physaddr).homogeneous // In M mode, if access DM address(debug module program buffer) val deny_access_to_debug = mpu_priv <= PRV.M.U && p(DebugModuleKey).map(dmp => dmp.address.contains(mpu_physaddr)).getOrElse(false.B) val prot_r = pma.io.resp.r && !deny_access_to_debug && pmp.io.r val prot_w = pma.io.resp.w && !deny_access_to_debug && pmp.io.w val prot_pp = pma.io.resp.pp val prot_al = pma.io.resp.al val prot_aa = pma.io.resp.aa val prot_x = pma.io.resp.x && !deny_access_to_debug && pmp.io.x val prot_eff = pma.io.resp.eff // hit check val sector_hits = sectored_entries(memIdx).map(_.sectorHit(vpn, priv_v)) val superpage_hits = superpage_entries.map(_.hit(vpn, priv_v)) val hitsVec = all_entries.map(vm_enabled && _.hit(vpn, priv_v)) val real_hits = hitsVec.asUInt val hits = Cat(!vm_enabled, real_hits) // use ptw response to refill // permission bit arrays when (do_refill) { val pte = io.ptw.resp.bits.pte val refill_v = r_vstage1_en \|\| r_stage2_en val newEntry = Wire(new TLBEntryData) newEntry.ppn := pte.ppn newEntry.c := cacheable newEntry.u := pte.u newEntry.g := pte.g && pte.v newEntry.ae_ptw := io.ptw.resp.bits.ae_ptw newEntry.ae_final := io.ptw.resp.bits.ae_final newEntry.ae_stage2 := io.ptw.resp.bits.ae_final && io.ptw.resp.bits.gpa_is_pte && r_stage2_en newEntry.pf := io.ptw.resp.bits.pf newEntry.gf := io.ptw.resp.bits.gf newEntry.hr := io.ptw.resp.bits.hr newEntry.hw := io.ptw.resp.bits.hw newEntry.hx := io.ptw.resp.bits.hx newEntry.sr := pte.sr() newEntry.sw := pte.sw() newEntry.sx := pte.sx() newEntry.pr := prot_r newEntry.pw := prot_w newEntry.px := prot_x newEntry.ppp := prot_pp newEntry.pal := prot_al newEntry.paa := prot_aa newEntry.eff := prot_eff newEntry.fragmented_superpage := io.ptw.resp.bits.fragmented_superpage // refill special_entry when (special_entry.nonEmpty.B && !io.ptw.resp.bits.homogeneous) { special_entry.foreach(_.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry)) }.elsewhen (io.ptw.resp.bits.level < (pgLevels-1).U) { val waddr = Mux(r_superpage_hit.valid && usingHypervisor.B, r_superpage_hit.bits, r_superpage_repl_addr) for ((e, i) <- superpage_entries.zipWithIndex) when (r_superpage_repl_addr === i.U) { e.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry) when (invalidate_refill) { e.invalidate() } } // refill sectored_hit }.otherwise { val r_memIdx = r_refill_tag.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2) val waddr = Mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) for ((e, i) <- sectored_entries(r_memIdx).zipWithIndex) when (waddr === i.U) { when (!r_sectored_hit.valid) { e.invalidate() } e.insert(r_refill_tag, refill_v, 0.U, newEntry) when (invalidate_refill) { e.invalidate() } } } r_gpa_valid := io.ptw.resp.bits.gpa.valid r_gpa := io.ptw.resp.bits.gpa.bits r_gpa_is_pte := io.ptw.resp.bits.gpa_is_pte } // get all entries data. val entries = all_entries.map(_.getData(vpn)) val normal_entries = entries.take(ordinary_entries.size) // parallel query PPN from [[all_entries]], if VM not enabled return VPN instead val ppn = Mux1H(hitsVec :+ !vm_enabled, (all_entries zip entries).map{ case (entry, data) => entry.ppn(vpn, data) } :+ vpn(ppnBits-1, 0)) val nPhysicalEntries = 1 + special_entry.size // generally PTW misaligned load exception. val ptw_ae_array = Cat(false.B, entries.map(_.ae_ptw).asUInt) val final_ae_array = Cat(false.B, entries.map(_.ae_final).asUInt) val ptw_pf_array = Cat(false.B, entries.map(_.pf).asUInt) val ptw_gf_array = Cat(false.B, entries.map(_.gf).asUInt) val sum = Mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) // if in hypervisor/machine mode, cannot read/write user entries. // if in superviosr/user mode, "If the SUM bit in the sstatus register is set, supervisor mode software may also access pages with U=1.(from spec)" val priv_rw_ok = Mux(!priv_s \|\| sum, entries.map(_.u).asUInt, 0.U) \| Mux(priv_s, ~entries.map(_.u).asUInt, 0.U) // if in hypervisor/machine mode, other than user pages, all pages are executable. // if in superviosr/user mode, only user page can execute. val priv_x_ok = Mux(priv_s, ~entries.map(_.u).asUInt, entries.map(_.u).asUInt) val stage1_bypass = Fill(entries.size, usingHypervisor.B) & (Fill(entries.size, !stage1_en) \| entries.map(_.ae_stage2).asUInt) val mxr = io.ptw.status.mxr \| Mux(priv_v, io.ptw.gstatus.mxr, false.B) // "The vsstatus field MXR, which makes execute-only pages readable, only overrides VS-stage page protection.(from spec)" val r_array = Cat(true.B, (priv_rw_ok & (entries.map(_.sr).asUInt \| Mux(mxr, entries.map(_.sx).asUInt, 0.U))) \| stage1_bypass) val w_array = Cat(true.B, (priv_rw_ok & entries.map(_.sw).asUInt) \| stage1_bypass) val x_array = Cat(true.B, (priv_x_ok & entries.map(_.sx).asUInt) \| stage1_bypass) val stage2_bypass = Fill(entries.size, !stage2_en) val hr_array = Cat(true.B, entries.map(_.hr).asUInt \| Mux(io.ptw.status.mxr, entries.map(_.hx).asUInt, 0.U) \| stage2_bypass) val hw_array = Cat(true.B, entries.map(_.hw).asUInt \| stage2_bypass) val hx_array = Cat(true.B, entries.map(_.hx).asUInt \| stage2_bypass) // These array is for each TLB entries. // user mode can read: PMA OK, TLB OK, AE OK val pr_array = Cat(Fill(nPhysicalEntries, prot_r), normal_entries.map(_.pr).asUInt) & ~(ptw_ae_array \| final_ae_array) // user mode can write: PMA OK, TLB OK, AE OK val pw_array = Cat(Fill(nPhysicalEntries, prot_w), normal_entries.map(_.pw).asUInt) & ~(ptw_ae_array \| final_ae_array) // user mode can write: PMA OK, TLB OK, AE OK val px_array = Cat(Fill(nPhysicalEntries, prot_x), normal_entries.map(_.px).asUInt) & ~(ptw_ae_array \| final_ae_array) // put effect val eff_array = Cat(Fill(nPhysicalEntries, prot_eff), normal_entries.map(_.eff).asUInt) // cacheable val c_array = Cat(Fill(nPhysicalEntries, cacheable), normal_entries.map(_.c).asUInt) // put partial val ppp_array = Cat(Fill(nPhysicalEntries, prot_pp), normal_entries.map(_.ppp).asUInt) // atomic arithmetic val paa_array = Cat(Fill(nPhysicalEntries, prot_aa), normal_entries.map(_.paa).asUInt) // atomic logic val pal_array = Cat(Fill(nPhysicalEntries, prot_al), normal_entries.map(_.pal).asUInt) val ppp_array_if_cached = ppp_array \| c_array val paa_array_if_cached = paa_array \| (if(usingAtomicsInCache) c_array else 0.U) val pal_array_if_cached = pal_array \| (if(usingAtomicsInCache) c_array else 0.U) val prefetchable_array = Cat((cacheable && homogeneous) << (nPhysicalEntries-1), normal_entries.map(_.c).asUInt) // vaddr misaligned: vaddr[1:0]=b00 val misaligned = (io.req.bits.vaddr & (UIntToOH(io.req.bits.size) - 1.U)).orR def badVA(guestPA: Boolean): Bool = { val additionalPgLevels = (if (guestPA) io.ptw.hgatp else satp).additionalPgLevels val extraBits = if (guestPA) hypervisorExtraAddrBits else 0 val signed = !guestPA val nPgLevelChoices = pgLevels - minPgLevels + 1 val minVAddrBits = pgIdxBits + minPgLevels pgLevelBits + extraBits (for (i <- 0 until nPgLevelChoices) yield { val mask = ((BigInt(1) << vaddrBitsExtended) - (BigInt(1) << (minVAddrBits + i * pgLevelBits - signed.toInt))).U val maskedVAddr = io.req.bits.vaddr & mask additionalPgLevels === i.U && !(maskedVAddr === 0.U \|\| signed.B && maskedVAddr === mask) }).orR } val bad_gpa = if (!usingHypervisor) false.B else vm_enabled && !stage1_en && badVA(true) val bad_va = if (!usingVM \|\| (minPgLevels == pgLevels && vaddrBits == vaddrBitsExtended)) false.B else vm_enabled && stage1_en && badVA(false) val cmd_lrsc = usingAtomics.B && io.req.bits.cmd.isOneOf(M_XLR, M_XSC) val cmd_amo_logical = usingAtomics.B && isAMOLogical(io.req.bits.cmd) val cmd_amo_arithmetic = usingAtomics.B && isAMOArithmetic(io.req.bits.cmd) val cmd_put_partial = io.req.bits.cmd === M_PWR val cmd_read = isRead(io.req.bits.cmd) val cmd_readx = usingHypervisor.B && io.req.bits.cmd === M_HLVX val cmd_write = isWrite(io.req.bits.cmd) val cmd_write_perms = cmd_write \|\| io.req.bits.cmd.isOneOf(M_FLUSH_ALL, M_WOK) // not a write, but needs write permissions val lrscAllowed = Mux((usingDataScratchpad \|\| usingAtomicsOnlyForIO).B, 0.U, c_array) val ae_array = Mux(misaligned, eff_array, 0.U) \| Mux(cmd_lrsc, ~lrscAllowed, 0.U) // access exception needs SoC information from PMA val ae_ld_array = Mux(cmd_read, ae_array \| ~pr_array, 0.U) val ae_st_array = Mux(cmd_write_perms, ae_array \| ~pw_array, 0.U) \| Mux(cmd_put_partial, ~ppp_array_if_cached, 0.U) \| Mux(cmd_amo_logical, ~pal_array_if_cached, 0.U) \| Mux(cmd_amo_arithmetic, ~paa_array_if_cached, 0.U) val must_alloc_array = Mux(cmd_put_partial, ~ppp_array, 0.U) \| Mux(cmd_amo_logical, ~pal_array, 0.U) \| Mux(cmd_amo_arithmetic, ~paa_array, 0.U) \| Mux(cmd_lrsc, ~0.U(pal_array.getWidth.W), 0.U) val pf_ld_array = Mux(cmd_read, ((~Mux(cmd_readx, x_array, r_array) & ~ptw_ae_array) \| ptw_pf_array) & ~ptw_gf_array, 0.U) val pf_st_array = Mux(cmd_write_perms, ((~w_array & ~ptw_ae_array) \| ptw_pf_array) & ~ptw_gf_array, 0.U) val pf_inst_array = ((~x_array & ~ptw_ae_array) \| ptw_pf_array) & ~ptw_gf_array val gf_ld_array = Mux(priv_v && cmd_read, (~Mux(cmd_readx, hx_array, hr_array) \| ptw_gf_array) & ~ptw_ae_array, 0.U) val gf_st_array = Mux(priv_v && cmd_write_perms, (~hw_array \| ptw_gf_array) & ~ptw_ae_array, 0.U) val gf_inst_array = Mux(priv_v, (~hx_array \| ptw_gf_array) & ~ptw_ae_array, 0.U) val gpa_hits = { val need_gpa_mask = if (instruction) gf_inst_array else gf_ld_array \| gf_st_array val hit_mask = Fill(ordinary_entries.size, r_gpa_valid && r_gpa_vpn === vpn) \| Fill(all_entries.size, !vstage1_en) hit_mask \| ~need_gpa_mask(all_entries.size-1, 0) } val tlb_hit_if_not_gpa_miss = real_hits.orR val tlb_hit = (real_hits & gpa_hits).orR // leads to s_request val tlb_miss = vm_enabled && !vsatp_mode_mismatch && !bad_va && !tlb_hit val sectored_plru = new SetAssocLRU(cfg.nSets, sectored_entries.head.size, "plru") val superpage_plru = new PseudoLRU(superpage_entries.size) when (io.req.valid && vm_enabled) { // replace when (sector_hits.orR) { sectored_plru.access(memIdx, OHToUInt(sector_hits)) } when (superpage_hits.orR) { superpage_plru.access(OHToUInt(superpage_hits)) } } // Superpages create the possibility that two entries in the TLB may match. // This corresponds to a software bug, but we can't return complete garbage; // we must return either the old translation or the new translation. This // isn't compatible with the Mux1H approach. So, flush the TLB and report // a miss on duplicate entries. val multipleHits = PopCountAtLeast(real_hits, 2) // only pull up req.ready when this is s_ready state. io.req.ready := state === s_ready // page fault io.resp.pf.ld := (bad_va && cmd_read) \|\| (pf_ld_array & hits).orR io.resp.pf.st := (bad_va && cmd_write_perms) \|\| (pf_st_array & hits).orR io.resp.pf.inst := bad_va \|\| (pf_inst_array & hits).orR // guest page fault io.resp.gf.ld := (bad_gpa && cmd_read) \|\| (gf_ld_array & hits).orR io.resp.gf.st := (bad_gpa && cmd_write_perms) \|\| (gf_st_array & hits).orR io.resp.gf.inst := bad_gpa \|\| (gf_inst_array & hits).orR // access exception io.resp.ae.ld := (ae_ld_array & hits).orR io.resp.ae.st := (ae_st_array & hits).orR io.resp.ae.inst := (~px_array & hits).orR // misaligned io.resp.ma.ld := misaligned && cmd_read io.resp.ma.st := misaligned && cmd_write io.resp.ma.inst := false.B // this is up to the pipeline to figure out io.resp.cacheable := (c_array & hits).orR io.resp.must_alloc := (must_alloc_array & hits).orR io.resp.prefetchable := (prefetchable_array & hits).orR && edge.manager.managers.forall(m => !m.supportsAcquireB \|\| m.supportsHint).B io.resp.miss := do_refill \|\| vsatp_mode_mismatch \|\| tlb_miss \|\| multipleHits io.resp.paddr := Cat(ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) io.resp.size := io.req.bits.size io.resp.cmd := io.req.bits.cmd io.resp.gpa_is_pte := vstage1_en && r_gpa_is_pte io.resp.gpa := { val page = Mux(!vstage1_en, Cat(bad_gpa, vpn), r_gpa >> pgIdxBits) val offset = Mux(io.resp.gpa_is_pte, r_gpa(pgIdxBits-1, 0), io.req.bits.vaddr(pgIdxBits-1, 0)) Cat(page, offset) } io.ptw.req.valid := state === s_request io.ptw.req.bits.valid := !io.kill io.ptw.req.bits.bits.addr := r_refill_tag io.ptw.req.bits.bits.vstage1 := r_vstage1_en io.ptw.req.bits.bits.stage2 := r_stage2_en io.ptw.req.bits.bits.need_gpa := r_need_gpa if (usingVM) { when(io.ptw.req.fire && io.ptw.req.bits.valid) { r_gpa_valid := false.B r_gpa_vpn := r_refill_tag } val sfence = io.sfence.valid // this is [[s_ready]] // handle miss/hit at the first cycle. // if miss, request PTW(L2TLB). when (io.req.fire && tlb_miss) { state := s_request r_refill_tag := vpn r_need_gpa := tlb_hit_if_not_gpa_miss r_vstage1_en := vstage1_en r_stage2_en := stage2_en r_superpage_repl_addr := replacementEntry(superpage_entries, superpage_plru.way) r_sectored_repl_addr := replacementEntry(sectored_entries(memIdx), sectored_plru.way(memIdx)) r_sectored_hit.valid := sector_hits.orR r_sectored_hit.bits := OHToUInt(sector_hits) r_superpage_hit.valid := superpage_hits.orR r_superpage_hit.bits := OHToUInt(superpage_hits) } // Handle SFENCE.VMA when send request to PTW. // SFENCE.VMA io.ptw.req.ready kill // ? ? 1 // 0 0 0 // 0 1 0 -> s_wait // 1 0 0 -> s_wait_invalidate // 1 0 0 -> s_ready when (state === s_request) { // SFENCE.VMA will kill TLB entries based on rs1 and rs2. It will take 1 cycle. when (sfence) { state := s_ready } // here should be io.ptw.req.fire, but assert(io.ptw.req.ready === true.B) // fire -> s_wait when (io.ptw.req.ready) { state := Mux(sfence, s_wait_invalidate, s_wait) } // If CPU kills request(frontend.s2_redirect) when (io.kill) { state := s_ready } } // sfence in refill will results in invalidate when (state === s_wait && sfence) { state := s_wait_invalidate } // after CPU acquire response, go back to s_ready. when (io.ptw.resp.valid) { state := s_ready } // SFENCE processing logic. when (sfence) { assert(!io.sfence.bits.rs1 \|\| (io.sfence.bits.addr >> pgIdxBits) === vpn) for (e <- all_real_entries) { val hv = usingHypervisor.B && io.sfence.bits.hv val hg = usingHypervisor.B && io.sfence.bits.hg when (!hg && io.sfence.bits.rs1) { e.invalidateVPN(vpn, hv) } .elsewhen (!hg && io.sfence.bits.rs2) { e.invalidateNonGlobal(hv) } .otherwise { e.invalidate(hv \|\| hg) } } } when(io.req.fire && vsatp_mode_mismatch) { all_real_entries.foreach(_.invalidate(true.B)) v_entries_use_stage1 := vstage1_en } when (multipleHits \|\| reset.asBool) { all_real_entries.foreach(_.invalidate()) } ccover(io.ptw.req.fire, "MISS", "TLB miss") ccover(io.ptw.req.valid && !io.ptw.req.ready, "PTW_STALL", "TLB miss, but PTW busy") ccover(state === s_wait_invalidate, "SFENCE_DURING_REFILL", "flush TLB during TLB refill") ccover(sfence && !io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_ALL", "flush TLB") ccover(sfence && !io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_ASID", "flush TLB ASID") ccover(sfence && io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_LINE", "flush TLB line") ccover(sfence && io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_LINE_ASID", "flush TLB line/ASID") ccover(multipleHits, "MULTIPLE_HITS", "Two matching translations in TLB") } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"${if (instruction) "I" else "D"}TLB_$label", "MemorySystem;;" + desc) /** Decides which entry to be replaced * * If there is a invalid entry, replace it with priorityencoder; * if not, replace the alt entry * * @return mask for TLBEntry replacement / def replacementEntry(set: Seq[TLBEntry], alt: UInt) = { val valids = set.map(_.valid.orR).asUInt Mux(valids.andR, alt, PriorityEncoder(~valids)) } } File TLBPermissions.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes, RegionType, AddressDecoder} import freechips.rocketchip.tilelink.TLManagerParameters case class TLBPermissions( homogeneous: Bool, // if false, the below are undefined r: Bool, // readable w: Bool, // writeable x: Bool, // executable c: Bool, // cacheable a: Bool, // arithmetic ops l: Bool) // logical ops object TLBPageLookup { private case class TLBFixedPermissions( e: Boolean, // get-/put-effects r: Boolean, // readable w: Boolean, // writeable x: Boolean, // executable c: Boolean, // cacheable a: Boolean, // arithmetic ops l: Boolean) { // logical ops val useful = r \|\| w \|\| x \|\| c \|\| a \|\| l } private def groupRegions(managers: Seq[TLManagerParameters]): Map[TLBFixedPermissions, Seq[AddressSet]] = { val permissions = managers.map { m => (m.address, TLBFixedPermissions( e = Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains m.regionType, r = m.supportsGet \|\| m.supportsAcquireB, // if cached, never uses Get w = m.supportsPutFull \|\| m.supportsAcquireT, // if cached, never uses Put x = m.executable, c = m.supportsAcquireB, a = m.supportsArithmetic, l = m.supportsLogical)) } permissions .filter(_._2.useful) // get rid of no-permission devices .groupBy(_._2) // group by permission type .mapValues(seq => AddressSet.unify(seq.flatMap(_._1))) // coalesce same-permission regions .toMap } // Unmapped memory is considered to be inhomogeneous def apply(managers: Seq[TLManagerParameters], xLen: Int, cacheBlockBytes: Int, pageSize: BigInt, maxRequestBytes: Int): UInt => TLBPermissions = { require (isPow2(xLen) && xLen >= 8) require (isPow2(cacheBlockBytes) && cacheBlockBytes >= xLen/8) require (isPow2(pageSize) && pageSize >= cacheBlockBytes) val xferSizes = TransferSizes(cacheBlockBytes, cacheBlockBytes) val allSizes = TransferSizes(1, maxRequestBytes) val amoSizes = TransferSizes(4, xLen/8) val permissions = managers.foreach { m => require (!m.supportsGet \|\| m.supportsGet .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsGet} Get, but must support ${allSizes}") require (!m.supportsPutFull \|\| m.supportsPutFull .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutFull} PutFull, but must support ${allSizes}") require (!m.supportsPutPartial \|\| m.supportsPutPartial.contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutPartial} PutPartial, but must support ${allSizes}") require (!m.supportsAcquireB \|\| m.supportsAcquireB .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireB} AcquireB, but must support ${xferSizes}") require (!m.supportsAcquireT \|\| m.supportsAcquireT .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireT} AcquireT, but must support ${xferSizes}") require (!m.supportsLogical \|\| m.supportsLogical .contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsLogical} Logical, but must support ${amoSizes}") require (!m.supportsArithmetic \|\| m.supportsArithmetic.contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsArithmetic} Arithmetic, but must support ${amoSizes}") require (!(m.supportsAcquireB && m.supportsPutFull && !m.supportsAcquireT), s"Memory region '${m.name}' supports AcquireB (cached read) and PutFull (un-cached write) but not AcquireT (cached write)") } val grouped = groupRegions(managers) .mapValues(_.filter(_.alignment >= pageSize)) // discard any region that's not big enough def lowCostProperty(prop: TLBFixedPermissions => Boolean): UInt => Bool = { val (yesm, nom) = grouped.partition { case (k, eq) => prop(k) } val (yes, no) = (yesm.values.flatten.toList, nom.values.flatten.toList) // Find the minimal bits needed to distinguish between yes and no val decisionMask = AddressDecoder(Seq(yes, no)) def simplify(x: Seq[AddressSet]) = AddressSet.unify(x.map(_.widen(~decisionMask)).distinct) val (yesf, nof) = (simplify(yes), simplify(no)) if (yesf.size < no.size) { (x: UInt) => yesf.map(_.contains(x)).foldLeft(false.B)(_ \|\| _) } else { (x: UInt) => !nof.map(_.contains(x)).foldLeft(false.B)(_ \|\| _) } } // Derive simplified property circuits (don't care when !homo) val rfn = lowCostProperty(_.r) val wfn = lowCostProperty(_.w) val xfn = lowCostProperty(_.x) val cfn = lowCostProperty(_.c) val afn = lowCostProperty(_.a) val lfn = lowCostProperty(_.l) val homo = AddressSet.unify(grouped.values.flatten.toList) (x: UInt) => TLBPermissions( homogeneous = homo.map(_.contains(x)).foldLeft(false.B)(_ \|\| _), r = rfn(x), w = wfn(x), x = xfn(x), c = cfn(x), a = afn(x), l = lfn(x)) } // Are all pageSize intervals of mapped regions homogeneous? def homogeneous(managers: Seq[TLManagerParameters], pageSize: BigInt): Boolean = { groupRegions(managers).values.forall(_.forall(_.alignment >= pageSize)) } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File PTW.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Arbiter, Cat, Decoupled, Enum, Mux1H, OHToUInt, PopCount, PriorityEncoder, PriorityEncoderOH, RegEnable, UIntToOH, Valid, is, isPow2, log2Ceil, switch} import chisel3.withClock import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ListBuffer /* PTE request from TLB to PTW * * TLB send a PTE request to PTW when L1TLB miss / class PTWReq(implicit p: Parameters) extends CoreBundle()(p) { val addr = UInt(vpnBits.W) val need_gpa = Bool() val vstage1 = Bool() val stage2 = Bool() } /* PTE info from L2TLB to TLB * * containing: target PTE, exceptions, two-satge tanslation info / class PTWResp(implicit p: Parameters) extends CoreBundle()(p) { /* ptw access exception / val ae_ptw = Bool() /* final access exception / val ae_final = Bool() /* page fault / val pf = Bool() /* guest page fault / val gf = Bool() /* hypervisor read / val hr = Bool() /* hypervisor write / val hw = Bool() /* hypervisor execute / val hx = Bool() /* PTE to refill L1TLB * * source: L2TLB / val pte = new PTE /* pte pglevel / val level = UInt(log2Ceil(pgLevels).W) /* fragmented_superpage support / val fragmented_superpage = Bool() /* homogeneous for both pma and pmp / val homogeneous = Bool() val gpa = Valid(UInt(vaddrBits.W)) val gpa_is_pte = Bool() } /* IO between TLB and PTW * * PTW receives : * - PTE request * - CSRs info * - pmp results from PMP(in TLB) / class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val req = Decoupled(Valid(new PTWReq)) val resp = Flipped(Valid(new PTWResp)) val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val customCSRs = Flipped(coreParams.customCSRs) } /* PTW performance statistics / class PTWPerfEvents extends Bundle { val l2miss = Bool() val l2hit = Bool() val pte_miss = Bool() val pte_hit = Bool() } /* Datapath IO between PTW and Core * * PTW receives CSRs info, pmp checks, sfence instruction info * * PTW sends its performance statistics to core / class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val sfence = Flipped(Valid(new SFenceReq)) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val perf = Output(new PTWPerfEvents()) val customCSRs = Flipped(coreParams.customCSRs) /* enable clock generated by ptw / val clock_enabled = Output(Bool()) } /* PTE template for transmission * * contains useful methods to check PTE attributes * @see RV-priv spec 4.3.1 for pgae table entry format / class PTE(implicit p: Parameters) extends CoreBundle()(p) { val reserved_for_future = UInt(10.W) val ppn = UInt(44.W) val reserved_for_software = Bits(2.W) /* dirty bit / val d = Bool() /* access bit / val a = Bool() /* global mapping / val g = Bool() /* user mode accessible / val u = Bool() /* whether the page is executable / val x = Bool() /* whether the page is writable / val w = Bool() /* whether the page is readable / val r = Bool() /* valid bit / val v = Bool() /* return true if find a pointer to next level page table / def table(dummy: Int = 0) = v && !r && !w && !x && !d && !a && !u && reserved_for_future === 0.U /* return true if find a leaf PTE / def leaf(dummy: Int = 0) = v && (r \|\| (x && !w)) && a /* user read / def ur(dummy: Int = 0) = sr() && u /* user write/ def uw(dummy: Int = 0) = sw() && u /* user execute / def ux(dummy: Int = 0) = sx() && u /* supervisor read / def sr(dummy: Int = 0) = leaf() && r /* supervisor write / def sw(dummy: Int = 0) = leaf() && w && d /* supervisor execute / def sx(dummy: Int = 0) = leaf() && x /* full permission: writable and executable in user mode / def isFullPerm(dummy: Int = 0) = uw() && ux() } /* L2TLB PTE template * * contains tag bits * @param nSets number of sets in L2TLB * @see RV-priv spec 4.3.1 for page table entry format / class L2TLBEntry(nSets: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val idxBits = log2Ceil(nSets) val tagBits = maxSVAddrBits - pgIdxBits - idxBits + (if (usingHypervisor) 1 else 0) val tag = UInt(tagBits.W) val ppn = UInt(ppnBits.W) /* dirty bit / val d = Bool() /* access bit / val a = Bool() /* user mode accessible / val u = Bool() /* whether the page is executable / val x = Bool() /* whether the page is writable / val w = Bool() /* whether the page is readable / val r = Bool() } /* PTW contains L2TLB, and performs page table walk for high level TLB, and cache queries from L1 TLBs(I$, D$, RoCC) * * It performs hierarchy page table query to mem for the desired leaf PTE and cache them in l2tlb. * Besides leaf PTEs, it also caches non-leaf PTEs in pte_cache to accerlerate the process. * * ==Structure== * - l2tlb : for leaf PTEs * - set-associative (configurable with [[CoreParams.nL2TLBEntries]]and [[CoreParams.nL2TLBWays]])) * - PLRU * - pte_cache: for non-leaf PTEs * - set-associative * - LRU * - s2_pte_cache: for non-leaf PTEs in 2-stage translation * - set-associative * - PLRU * * l2tlb Pipeline: 3 stage * {{{ * stage 0 : read * stage 1 : decode * stage 2 : hit check * }}} * ==State Machine== * s_ready: ready to reveive request from TLB * s_req: request mem; pte_cache hit judge * s_wait1: deal with l2tlb error * s_wait2: final hit judge * s_wait3: receive mem response * s_fragment_superpage: for superpage PTE * * @note l2tlb hit happens in s_req or s_wait1 * @see RV-priv spec 4.3-4.6 for Virtual-Memory System * @see RV-priv spec 8.5 for Two-Stage Address Translation * @todo details in two-stage translation / class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { /* to n TLB / val requestor = Flipped(Vec(n, new TLBPTWIO)) /* to HellaCache / val mem = new HellaCacheIO /* to Core * * contains CSRs info and performance statistics / val dpath = new DatapathPTWIO }) val s_ready :: s_req :: s_wait1 :: s_dummy1 :: s_wait2 :: s_wait3 :: s_dummy2 :: s_fragment_superpage :: Nil = Enum(8) val state = RegInit(s_ready) val l2_refill_wire = Wire(Bool()) /* Arbiter to arbite request from n TLB / val arb = Module(new Arbiter(Valid(new PTWReq), n)) // use TLB req as arbitor's input arb.io.in <> io.requestor.map(_.req) // receive req only when s_ready and not in refill arb.io.out.ready := (state === s_ready) && !l2_refill_wire val resp_valid = RegNext(VecInit(Seq.fill(io.requestor.size)(false.B))) val clock_en = state =/= s_ready \|\| l2_refill_wire \|\| arb.io.out.valid \|\| io.dpath.sfence.valid \|\| io.dpath.customCSRs.disableDCacheClockGate io.dpath.clock_enabled := usingVM.B && clock_en val gated_clock = if (!usingVM \|\| !tileParams.dcache.get.clockGate) clock else ClockGate(clock, clock_en, "ptw_clock_gate") withClock (gated_clock) { // entering gated-clock domain val invalidated = Reg(Bool()) /* current PTE level * {{{ * 0 <= count <= pgLevel-1 * count = pgLevel - 1 : leaf PTE * count < pgLevel - 1 : non-leaf PTE * }}} / val count = Reg(UInt(log2Ceil(pgLevels).W)) val resp_ae_ptw = Reg(Bool()) val resp_ae_final = Reg(Bool()) val resp_pf = Reg(Bool()) val resp_gf = Reg(Bool()) val resp_hr = Reg(Bool()) val resp_hw = Reg(Bool()) val resp_hx = Reg(Bool()) val resp_fragmented_superpage = Reg(Bool()) /* tlb request / val r_req = Reg(new PTWReq) /* current selected way in arbitor / val r_req_dest = Reg(Bits()) // to respond to L1TLB : l2_hit // to construct mem.req.addr val r_pte = Reg(new PTE) val r_hgatp = Reg(new PTBR) // 2-stage pageLevel val aux_count = Reg(UInt(log2Ceil(pgLevels).W)) /* pte for 2-stage translation / val aux_pte = Reg(new PTE) val gpa_pgoff = Reg(UInt(pgIdxBits.W)) // only valid in resp_gf case val stage2 = Reg(Bool()) val stage2_final = Reg(Bool()) val satp = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr) val r_hgatp_initial_count = pgLevels.U - minPgLevels.U - r_hgatp.additionalPgLevels /* 2-stage translation both enable / val do_both_stages = r_req.vstage1 && r_req.stage2 val max_count = count max aux_count val vpn = Mux(r_req.vstage1 && stage2, aux_pte.ppn, r_req.addr) val mem_resp_valid = RegNext(io.mem.resp.valid) val mem_resp_data = RegNext(io.mem.resp.bits.data) io.mem.uncached_resp.map { resp => assert(!(resp.valid && io.mem.resp.valid)) resp.ready := true.B when (resp.valid) { mem_resp_valid := true.B mem_resp_data := resp.bits.data } } // construct pte from mem.resp val (pte, invalid_paddr, invalid_gpa) = { val tmp = mem_resp_data.asTypeOf(new PTE()) val res = WireDefault(tmp) res.ppn := Mux(do_both_stages && !stage2, tmp.ppn(vpnBits.min(tmp.ppn.getWidth)-1, 0), tmp.ppn(ppnBits-1, 0)) when (tmp.r \|\| tmp.w \|\| tmp.x) { // for superpage mappings, make sure PPN LSBs are zero for (i <- 0 until pgLevels-1) when (count <= i.U && tmp.ppn((pgLevels-1-i)pgLevelBits-1, (pgLevels-2-i)pgLevelBits) =/= 0.U) { res.v := false.B } } (res, Mux(do_both_stages && !stage2, (tmp.ppn >> vpnBits) =/= 0.U, (tmp.ppn >> ppnBits) =/= 0.U), do_both_stages && !stage2 && checkInvalidHypervisorGPA(r_hgatp, tmp.ppn)) } // find non-leaf PTE, need traverse val traverse = pte.table() && !invalid_paddr && !invalid_gpa && count < (pgLevels-1).U /* address send to mem for enquerry / val pte_addr = if (!usingVM) 0.U else { val vpn_idxs = (0 until pgLevels).map { i => val width = pgLevelBits + (if (i <= pgLevels - minPgLevels) hypervisorExtraAddrBits else 0) (vpn >> (pgLevels - i - 1) pgLevelBits)(width - 1, 0) } val mask = Mux(stage2 && count === r_hgatp_initial_count, ((1 << (hypervisorExtraAddrBits + pgLevelBits)) - 1).U, ((1 << pgLevelBits) - 1).U) val vpn_idx = vpn_idxs(count) & mask val raw_pte_addr = ((r_pte.ppn << pgLevelBits) \| vpn_idx) << log2Ceil(xLen / 8) val size = if (usingHypervisor) vaddrBits else paddrBits //use r_pte.ppn as page table base address //use vpn slice as offset raw_pte_addr.apply(size.min(raw_pte_addr.getWidth) - 1, 0) } /** stage2_pte_cache input addr / val stage2_pte_cache_addr = if (!usingHypervisor) 0.U else { val vpn_idxs = (0 until pgLevels - 1).map { i => (r_req.addr >> (pgLevels - i - 1) pgLevelBits)(pgLevelBits - 1, 0) } val vpn_idx = vpn_idxs(aux_count) val raw_s2_pte_cache_addr = Cat(aux_pte.ppn, vpn_idx) << log2Ceil(xLen / 8) raw_s2_pte_cache_addr(vaddrBits.min(raw_s2_pte_cache_addr.getWidth) - 1, 0) } def makeFragmentedSuperpagePPN(ppn: UInt): Seq[UInt] = { (pgLevels-1 until 0 by -1).map(i => Cat(ppn >> (pgLevelBitsi), r_req.addr(((pgLevelBitsi) min vpnBits)-1, 0).padTo(pgLevelBitsi))) } /* PTECache caches non-leaf PTE * @param s2 true: 2-stage address translation / def makePTECache(s2: Boolean): (Bool, UInt) = if (coreParams.nPTECacheEntries == 0) { (false.B, 0.U) } else { val plru = new PseudoLRU(coreParams.nPTECacheEntries) val valid = RegInit(0.U(coreParams.nPTECacheEntries.W)) val tags = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor) 1 + vaddrBits else paddrBits).W))) // not include full pte, only ppn val data = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor && s2) vpnBits else ppnBits).W))) val can_hit = if (s2) count === r_hgatp_initial_count && aux_count < (pgLevels-1).U && r_req.vstage1 && stage2 && !stage2_final else count < (pgLevels-1).U && Mux(r_req.vstage1, stage2, !r_req.stage2) val can_refill = if (s2) do_both_stages && !stage2 && !stage2_final else can_hit val tag = if (s2) Cat(true.B, stage2_pte_cache_addr.padTo(vaddrBits)) else Cat(r_req.vstage1, pte_addr.padTo(if (usingHypervisor) vaddrBits else paddrBits)) val hits = tags.map(_ === tag).asUInt & valid val hit = hits.orR && can_hit // refill with mem response when (mem_resp_valid && traverse && can_refill && !hits.orR && !invalidated) { val r = Mux(valid.andR, plru.way, PriorityEncoder(~valid)) valid := valid \| UIntToOH(r) tags(r) := tag data(r) := pte.ppn plru.access(r) } // replace when (hit && state === s_req) { plru.access(OHToUInt(hits)) } when (io.dpath.sfence.valid && (!io.dpath.sfence.bits.rs1 \|\| usingHypervisor.B && io.dpath.sfence.bits.hg)) { valid := 0.U } val lcount = if (s2) aux_count else count for (i <- 0 until pgLevels-1) { ccover(hit && state === s_req && lcount === i.U, s"PTE_CACHE_HIT_L$i", s"PTE cache hit, level $i") } (hit, Mux1H(hits, data)) } // generate pte_cache val (pte_cache_hit, pte_cache_data) = makePTECache(false) // generate pte_cache with 2-stage translation val (stage2_pte_cache_hit, stage2_pte_cache_data) = makePTECache(true) // pte_cache hit or 2-stage pte_cache hit val pte_hit = RegNext(false.B) io.dpath.perf.pte_miss := false.B io.dpath.perf.pte_hit := pte_hit && (state === s_req) && !io.dpath.perf.l2hit assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss \|\| io.dpath.perf.pte_hit)), "PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event") // l2_refill happens when find the leaf pte val l2_refill = RegNext(false.B) l2_refill_wire := l2_refill io.dpath.perf.l2miss := false.B io.dpath.perf.l2hit := false.B // l2tlb val (l2_hit, l2_error, l2_pte, l2_tlb_ram) = if (coreParams.nL2TLBEntries == 0) (false.B, false.B, WireDefault(0.U.asTypeOf(new PTE)), None) else { val code = new ParityCode require(isPow2(coreParams.nL2TLBEntries)) require(isPow2(coreParams.nL2TLBWays)) require(coreParams.nL2TLBEntries >= coreParams.nL2TLBWays) val nL2TLBSets = coreParams.nL2TLBEntries / coreParams.nL2TLBWays require(isPow2(nL2TLBSets)) val idxBits = log2Ceil(nL2TLBSets) val l2_plru = new SetAssocLRU(nL2TLBSets, coreParams.nL2TLBWays, "plru") val ram = DescribedSRAM( name = "l2_tlb_ram", desc = "L2 TLB", size = nL2TLBSets, data = Vec(coreParams.nL2TLBWays, UInt(code.width(new L2TLBEntry(nL2TLBSets).getWidth).W)) ) val g = Reg(Vec(coreParams.nL2TLBWays, UInt(nL2TLBSets.W))) val valid = RegInit(VecInit(Seq.fill(coreParams.nL2TLBWays)(0.U(nL2TLBSets.W)))) // use r_req to construct tag val (r_tag, r_idx) = Split(Cat(r_req.vstage1, r_req.addr(maxSVAddrBits-pgIdxBits-1, 0)), idxBits) /* the valid vec for the selected set(including n ways) / val r_valid_vec = valid.map(_(r_idx)).asUInt val r_valid_vec_q = Reg(UInt(coreParams.nL2TLBWays.W)) val r_l2_plru_way = Reg(UInt(log2Ceil(coreParams.nL2TLBWays max 1).W)) r_valid_vec_q := r_valid_vec // replacement way r_l2_plru_way := (if (coreParams.nL2TLBWays > 1) l2_plru.way(r_idx) else 0.U) // refill with r_pte(leaf pte) when (l2_refill && !invalidated) { val entry = Wire(new L2TLBEntry(nL2TLBSets)) entry.ppn := r_pte.ppn entry.d := r_pte.d entry.a := r_pte.a entry.u := r_pte.u entry.x := r_pte.x entry.w := r_pte.w entry.r := r_pte.r entry.tag := r_tag // if all the way are valid, use plru to select one way to be replaced, // otherwise use PriorityEncoderOH to select one val wmask = if (coreParams.nL2TLBWays > 1) Mux(r_valid_vec_q.andR, UIntToOH(r_l2_plru_way, coreParams.nL2TLBWays), PriorityEncoderOH(~r_valid_vec_q)) else 1.U(1.W) ram.write(r_idx, VecInit(Seq.fill(coreParams.nL2TLBWays)(code.encode(entry.asUInt))), wmask.asBools) val mask = UIntToOH(r_idx) for (way <- 0 until coreParams.nL2TLBWays) { when (wmask(way)) { valid(way) := valid(way) \| mask g(way) := Mux(r_pte.g, g(way) \| mask, g(way) & ~mask) } } } // sfence happens when (io.dpath.sfence.valid) { val hg = usingHypervisor.B && io.dpath.sfence.bits.hg for (way <- 0 until coreParams.nL2TLBWays) { valid(way) := Mux(!hg && io.dpath.sfence.bits.rs1, valid(way) & ~UIntToOH(io.dpath.sfence.bits.addr(idxBits+pgIdxBits-1, pgIdxBits)), Mux(!hg && io.dpath.sfence.bits.rs2, valid(way) & g(way), 0.U)) } } val s0_valid = !l2_refill && arb.io.out.fire val s0_suitable = arb.io.out.bits.bits.vstage1 === arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.need_gpa val s1_valid = RegNext(s0_valid && s0_suitable && arb.io.out.bits.valid) val s2_valid = RegNext(s1_valid) // read from tlb idx val s1_rdata = ram.read(arb.io.out.bits.bits.addr(idxBits-1, 0), s0_valid) val s2_rdata = s1_rdata.map(s1_rdway => code.decode(RegEnable(s1_rdway, s1_valid))) val s2_valid_vec = RegEnable(r_valid_vec, s1_valid) val s2_g_vec = RegEnable(VecInit(g.map(_(r_idx))), s1_valid) val s2_error = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && s2_rdata(way).error).orR when (s2_valid && s2_error) { valid.foreach { _ := 0.U }} // decode val s2_entry_vec = s2_rdata.map(_.uncorrected.asTypeOf(new L2TLBEntry(nL2TLBSets))) val s2_hit_vec = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && (r_tag === s2_entry_vec(way).tag)) val s2_hit = s2_valid && s2_hit_vec.orR io.dpath.perf.l2miss := s2_valid && !(s2_hit_vec.orR) io.dpath.perf.l2hit := s2_hit when (s2_hit) { l2_plru.access(r_idx, OHToUInt(s2_hit_vec)) assert((PopCount(s2_hit_vec) === 1.U) \|\| s2_error, "L2 TLB multi-hit") } val s2_pte = Wire(new PTE) val s2_hit_entry = Mux1H(s2_hit_vec, s2_entry_vec) s2_pte.ppn := s2_hit_entry.ppn s2_pte.d := s2_hit_entry.d s2_pte.a := s2_hit_entry.a s2_pte.g := Mux1H(s2_hit_vec, s2_g_vec) s2_pte.u := s2_hit_entry.u s2_pte.x := s2_hit_entry.x s2_pte.w := s2_hit_entry.w s2_pte.r := s2_hit_entry.r s2_pte.v := true.B s2_pte.reserved_for_future := 0.U s2_pte.reserved_for_software := 0.U for (way <- 0 until coreParams.nL2TLBWays) { ccover(s2_hit && s2_hit_vec(way), s"L2_TLB_HIT_WAY$way", s"L2 TLB hit way$way") } (s2_hit, s2_error, s2_pte, Some(ram)) } // if SFENCE occurs during walk, don't refill PTE cache or L2 TLB until next walk invalidated := io.dpath.sfence.valid \|\| (invalidated && state =/= s_ready) // mem request io.mem.keep_clock_enabled := false.B io.mem.req.valid := state === s_req \|\| state === s_dummy1 io.mem.req.bits.phys := true.B io.mem.req.bits.cmd := M_XRD io.mem.req.bits.size := log2Ceil(xLen/8).U io.mem.req.bits.signed := false.B io.mem.req.bits.addr := pte_addr io.mem.req.bits.idx.foreach(_ := pte_addr) io.mem.req.bits.dprv := PRV.S.U // PTW accesses are S-mode by definition io.mem.req.bits.dv := do_both_stages && !stage2 io.mem.req.bits.tag := DontCare io.mem.req.bits.no_resp := false.B io.mem.req.bits.no_alloc := DontCare io.mem.req.bits.no_xcpt := DontCare io.mem.req.bits.data := DontCare io.mem.req.bits.mask := DontCare io.mem.s1_kill := l2_hit \|\| (state =/= s_wait1) \|\| resp_gf io.mem.s1_data := DontCare io.mem.s2_kill := false.B val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) require(!usingHypervisor \|\| pageGranularityPMPs, s"hypervisor requires pmpGranularity >= ${1<<pgIdxBits}") val pmaPgLevelHomogeneous = (0 until pgLevels) map { i => val pgSize = BigInt(1) << (pgIdxBits + ((pgLevels - 1 - i) pgLevelBits)) if (pageGranularityPMPs && i == pgLevels - 1) { require(TLBPageLookup.homogeneous(edge.manager.managers, pgSize), s"All memory regions must be $pgSize-byte aligned") true.B } else { TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), pgSize, xLen/8)(r_pte.ppn << pgIdxBits).homogeneous } } val pmaHomogeneous = pmaPgLevelHomogeneous(count) val pmpHomogeneous = new PMPHomogeneityChecker(io.dpath.pmp).apply(r_pte.ppn << pgIdxBits, count) val homogeneous = pmaHomogeneous && pmpHomogeneous // response to tlb for (i <- 0 until io.requestor.size) { io.requestor(i).resp.valid := resp_valid(i) io.requestor(i).resp.bits.ae_ptw := resp_ae_ptw io.requestor(i).resp.bits.ae_final := resp_ae_final io.requestor(i).resp.bits.pf := resp_pf io.requestor(i).resp.bits.gf := resp_gf io.requestor(i).resp.bits.hr := resp_hr io.requestor(i).resp.bits.hw := resp_hw io.requestor(i).resp.bits.hx := resp_hx io.requestor(i).resp.bits.pte := r_pte io.requestor(i).resp.bits.level := max_count io.requestor(i).resp.bits.homogeneous := homogeneous \|\| pageGranularityPMPs.B io.requestor(i).resp.bits.fragmented_superpage := resp_fragmented_superpage && pageGranularityPMPs.B io.requestor(i).resp.bits.gpa.valid := r_req.need_gpa io.requestor(i).resp.bits.gpa.bits := Cat(Mux(!stage2_final \|\| !r_req.vstage1 \|\| aux_count === (pgLevels - 1).U, aux_pte.ppn, makeFragmentedSuperpagePPN(aux_pte.ppn)(aux_count)), gpa_pgoff) io.requestor(i).resp.bits.gpa_is_pte := !stage2_final io.requestor(i).ptbr := io.dpath.ptbr io.requestor(i).hgatp := io.dpath.hgatp io.requestor(i).vsatp := io.dpath.vsatp io.requestor(i).customCSRs <> io.dpath.customCSRs io.requestor(i).status := io.dpath.status io.requestor(i).hstatus := io.dpath.hstatus io.requestor(i).gstatus := io.dpath.gstatus io.requestor(i).pmp := io.dpath.pmp } // control state machine val next_state = WireDefault(state) state := OptimizationBarrier(next_state) val do_switch = WireDefault(false.B) switch (state) { is (s_ready) { when (arb.io.out.fire) { val satp_initial_count = pgLevels.U - minPgLevels.U - satp.additionalPgLevels val vsatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.vsatp.additionalPgLevels val hgatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.hgatp.additionalPgLevels val aux_ppn = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr) r_req := arb.io.out.bits.bits r_req_dest := arb.io.chosen next_state := Mux(arb.io.out.bits.valid, s_req, s_ready) stage2 := arb.io.out.bits.bits.stage2 stage2_final := arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.vstage1 count := Mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count) aux_count := Mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, 0.U) aux_pte.ppn := aux_ppn aux_pte.reserved_for_future := 0.U resp_ae_ptw := false.B resp_ae_final := false.B resp_pf := false.B resp_gf := checkInvalidHypervisorGPA(io.dpath.hgatp, aux_ppn) && arb.io.out.bits.bits.stage2 resp_hr := true.B resp_hw := true.B resp_hx := true.B resp_fragmented_superpage := false.B r_hgatp := io.dpath.hgatp assert(!arb.io.out.bits.bits.need_gpa \|\| arb.io.out.bits.bits.stage2) } } is (s_req) { when(stage2 && count === r_hgatp_initial_count) { gpa_pgoff := Mux(aux_count === (pgLevels-1).U, r_req.addr << (xLen/8).log2, stage2_pte_cache_addr) } // pte_cache hit when (stage2_pte_cache_hit) { aux_count := aux_count + 1.U aux_pte.ppn := stage2_pte_cache_data aux_pte.reserved_for_future := 0.U pte_hit := true.B }.elsewhen (pte_cache_hit) { count := count + 1.U pte_hit := true.B }.otherwise { next_state := Mux(io.mem.req.ready, s_wait1, s_req) } when(resp_gf) { next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_wait1) { // This Mux is for the l2_error case; the l2_hit && !l2_error case is overriden below next_state := Mux(l2_hit, s_req, s_wait2) } is (s_wait2) { next_state := s_wait3 io.dpath.perf.pte_miss := count < (pgLevels-1).U when (io.mem.s2_xcpt.ae.ld) { resp_ae_ptw := true.B next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_fragment_superpage) { next_state := s_ready resp_valid(r_req_dest) := true.B when (!homogeneous) { count := (pgLevels-1).U resp_fragmented_superpage := true.B } when (do_both_stages) { resp_fragmented_superpage := true.B } } } val merged_pte = { val superpage_masks = (0 until pgLevels).map(i => ((BigInt(1) << pte.ppn.getWidth) - (BigInt(1) << (pgLevels-1-i)pgLevelBits)).U) val superpage_mask = superpage_masks(Mux(stage2_final, max_count, (pgLevels-1).U)) val stage1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)pgLevelBits), aux_pte.ppn((pgLevels-i-1)pgLevelBits-1,0))) :+ pte.ppn val stage1_ppn = stage1_ppns(count) makePTE(stage1_ppn & superpage_mask, aux_pte) } r_pte := OptimizationBarrier( // l2tlb hit->find a leaf PTE(l2_pte), respond to L1TLB Mux(l2_hit && !l2_error && !resp_gf, l2_pte, // S2 PTE cache hit -> proceed to the next level of walking, update the r_pte with hgatp Mux(state === s_req && stage2_pte_cache_hit, makeHypervisorRootPTE(r_hgatp, stage2_pte_cache_data, l2_pte), // pte cache hit->find a non-leaf PTE(pte_cache),continue to request mem Mux(state === s_req && pte_cache_hit, makePTE(pte_cache_data, l2_pte), // 2-stage translation Mux(do_switch, makeHypervisorRootPTE(r_hgatp, pte.ppn, r_pte), // when mem respond, store mem.resp.pte Mux(mem_resp_valid, Mux(!traverse && r_req.vstage1 && stage2, merged_pte, pte), // fragment_superpage Mux(state === s_fragment_superpage && !homogeneous && count =/= (pgLevels - 1).U, makePTE(makeFragmentedSuperpagePPN(r_pte.ppn)(count), r_pte), // when tlb request come->request mem, use root address in satp(or vsatp,hgatp) Mux(arb.io.out.fire, Mux(arb.io.out.bits.bits.stage2, makeHypervisorRootPTE(io.dpath.hgatp, io.dpath.vsatp.ppn, r_pte), makePTE(satp.ppn, r_pte)), r_pte)))))))) when (l2_hit && !l2_error && !resp_gf) { assert(state === s_req \|\| state === s_wait1) next_state := s_ready resp_valid(r_req_dest) := true.B count := (pgLevels-1).U } when (mem_resp_valid) { assert(state === s_wait3) next_state := s_req when (traverse) { when (do_both_stages && !stage2) { do_switch := true.B } count := count + 1.U }.otherwise { val gf = (stage2 && !stage2_final && !pte.ur()) \|\| (pte.leaf() && pte.reserved_for_future === 0.U && invalid_gpa) val ae = pte.v && invalid_paddr val pf = pte.v && pte.reserved_for_future =/= 0.U val success = pte.v && !ae && !pf && !gf when (do_both_stages && !stage2_final && success) { when (stage2) { stage2 := false.B count := aux_count }.otherwise { stage2_final := true.B do_switch := true.B } }.otherwise { // find a leaf pte, start l2 refill l2_refill := success && count === (pgLevels-1).U && !r_req.need_gpa && (!r_req.vstage1 && !r_req.stage2 \|\| do_both_stages && aux_count === (pgLevels-1).U && pte.isFullPerm()) count := max_count when (pageGranularityPMPs.B && !(count === (pgLevels-1).U && (!do_both_stages \|\| aux_count === (pgLevels-1).U))) { next_state := s_fragment_superpage }.otherwise { next_state := s_ready resp_valid(r_req_dest) := true.B } resp_ae_ptw := ae && count < (pgLevels-1).U && pte.table() resp_ae_final := ae && pte.leaf() resp_pf := pf && !stage2 resp_gf := gf \|\| (pf && stage2) resp_hr := !stage2 \|\| (!pf && !gf && pte.ur()) resp_hw := !stage2 \|\| (!pf && !gf && pte.uw()) resp_hx := !stage2 \|\| (!pf && !gf && pte.ux()) } } } when (io.mem.s2_nack) { assert(state === s_wait2) next_state := s_req } when (do_switch) { aux_count := Mux(traverse, count + 1.U, count) count := r_hgatp_initial_count aux_pte := Mux(traverse, pte, { val s1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)pgLevelBits), r_req.addr(((pgLevels-i-1)pgLevelBits min vpnBits)-1,0).padTo((pgLevels-i-1)pgLevelBits))) :+ pte.ppn makePTE(s1_ppns(count), pte) }) stage2 := true.B } for (i <- 0 until pgLevels) { val leaf = mem_resp_valid && !traverse && count === i.U ccover(leaf && pte.v && !invalid_paddr && !invalid_gpa && pte.reserved_for_future === 0.U, s"L$i", s"successful page-table access, level $i") ccover(leaf && pte.v && invalid_paddr, s"L${i}_BAD_PPN_MSB", s"PPN too large, level $i") ccover(leaf && pte.v && invalid_gpa, s"L${i}_BAD_GPA_MSB", s"GPA too large, level $i") ccover(leaf && pte.v && pte.reserved_for_future =/= 0.U, s"L${i}_BAD_RSV_MSB", s"reserved MSBs set, level $i") ccover(leaf && !mem_resp_data(0), s"L${i}_INVALID_PTE", s"page not present, level $i") if (i != pgLevels-1) ccover(leaf && !pte.v && mem_resp_data(0), s"L${i}_BAD_PPN_LSB", s"PPN LSBs not zero, level $i") } ccover(mem_resp_valid && count === (pgLevels-1).U && pte.table(), s"TOO_DEEP", s"page table too deep") ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access") ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table") } // leaving gated-clock domain private def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = if (usingVM) property.cover(cond, s"PTW_$label", "MemorySystem;;" + desc) /** Relace PTE.ppn with ppn / private def makePTE(ppn: UInt, default: PTE) = { val pte = WireDefault(default) pte.ppn := ppn pte } /* use hgatp and vpn to construct a new ppn / private def makeHypervisorRootPTE(hgatp: PTBR, vpn: UInt, default: PTE) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> (pgLevels-i)pgLevelBits)) val lsbs = WireDefault(UInt(maxHypervisorExtraAddrBits.W), idxs(count)) val pte = WireDefault(default) pte.ppn := Cat(hgatp.ppn >> maxHypervisorExtraAddrBits, lsbs) pte } /** use hgatp and vpn to check for gpa out of range / private def checkInvalidHypervisorGPA(hgatp: PTBR, vpn: UInt) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> ((pgLevels-i)pgLevelBits)+maxHypervisorExtraAddrBits)) idxs.extract(count) =/= 0.U } } /** Mix-ins for constructing tiles that might have a PTW / trait CanHavePTW extends HasTileParameters with HasHellaCache { this: BaseTile => val module: CanHavePTWModule var nPTWPorts = 1 nDCachePorts += usingPTW.toInt } trait CanHavePTWModule extends HasHellaCacheModule { val outer: CanHavePTW val ptwPorts = ListBuffer(outer.dcache.module.io.ptw) val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p)) ptw.io.mem <> DontCare if (outer.usingPTW) { dcachePorts += ptw.io.mem } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File DCache.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.amba.AMBAProt import freechips.rocketchip.diplomacy.{BufferParams} import freechips.rocketchip.prci.{ClockCrossingType, RationalCrossing, SynchronousCrossing, AsynchronousCrossing, CreditedCrossing} import freechips.rocketchip.tile.{CoreBundle, LookupByHartId} import freechips.rocketchip.tilelink.{TLFIFOFixer,ClientMetadata, TLBundleA, TLAtomics, TLBundleB, TLPermissions} import freechips.rocketchip.tilelink.TLMessages.{AccessAck, HintAck, AccessAckData, Grant, GrantData, ReleaseAck} import freechips.rocketchip.util.{CanHaveErrors, ClockGate, IdentityCode, ReplacementPolicy, DescribedSRAM, property} import freechips.rocketchip.util.BooleanToAugmentedBoolean import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.UIntIsOneOf import freechips.rocketchip.util.IntToAugmentedInt import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.SeqBoolBitwiseOps // TODO: delete this trait once deduplication is smart enough to avoid globally inlining matching circuits trait InlineInstance { self: chisel3.experimental.BaseModule => chisel3.experimental.annotate( new chisel3.experimental.ChiselAnnotation { def toFirrtl: firrtl.annotations.Annotation = firrtl.passes.InlineAnnotation(self.toNamed) } ) } class DCacheErrors(implicit p: Parameters) extends L1HellaCacheBundle()(p) with CanHaveErrors { val correctable = (cacheParams.tagCode.canCorrect \|\| cacheParams.dataCode.canCorrect).option(Valid(UInt(paddrBits.W))) val uncorrectable = (cacheParams.tagCode.canDetect \|\| cacheParams.dataCode.canDetect).option(Valid(UInt(paddrBits.W))) val bus = Valid(UInt(paddrBits.W)) } class DCacheDataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val addr = UInt(untagBits.W) val write = Bool() val wdata = UInt((encBits rowBytes / eccBytes).W) val wordMask = UInt((rowBytes / subWordBytes).W) val eccMask = UInt((wordBytes / eccBytes).W) val way_en = UInt(nWays.W) } class DCacheDataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) { val io = IO(new Bundle { val req = Flipped(Valid(new DCacheDataReq)) val resp = Output(Vec(nWays, UInt((req.bits.wdata.getWidth).W))) }) require(rowBits % subWordBits == 0, "rowBits must be a multiple of subWordBits") val eccMask = if (eccBits == subWordBits) Seq(true.B) else io.req.bits.eccMask.asBools val wMask = if (nWays == 1) eccMask else (0 until nWays).flatMap(i => eccMask.map(_ && io.req.bits.way_en(i))) val wWords = io.req.bits.wdata.grouped(encBits * (subWordBits / eccBits)) val addr = io.req.bits.addr >> rowOffBits val data_arrays = Seq.tabulate(rowBits / subWordBits) { i => DescribedSRAM( name = s"${tileParams.baseName}_dcache_data_arrays_${i}", desc = "DCache Data Array", size = nSets * cacheBlockBytes / rowBytes, data = Vec(nWays * (subWordBits / eccBits), UInt(encBits.W)) ) } val rdata = for ((array , i) <- data_arrays.zipWithIndex) yield { val valid = io.req.valid && ((data_arrays.size == 1).B \|\| io.req.bits.wordMask(i)) when (valid && io.req.bits.write) { val wMaskSlice = (0 until wMask.size).filter(j => i % (wordBits/subWordBits) == (j % (wordBytes/eccBytes)) / (subWordBytes/eccBytes)).map(wMask(_)) val wData = wWords(i).grouped(encBits) array.write(addr, VecInit((0 until nWays).flatMap(i => wData)), wMaskSlice) } val data = array.read(addr, valid && !io.req.bits.write) data.grouped(subWordBits / eccBits).map(_.asUInt).toSeq } (io.resp zip rdata.transpose).foreach { case (resp, data) => resp := data.asUInt } } class DCacheMetadataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val write = Bool() val addr = UInt(vaddrBitsExtended.W) val idx = UInt(idxBits.W) val way_en = UInt(nWays.W) val data = UInt(cacheParams.tagCode.width(new L1Metadata().getWidth).W) } class DCache(staticIdForMetadataUseOnly: Int, val crossing: ClockCrossingType)(implicit p: Parameters) extends HellaCache(staticIdForMetadataUseOnly)(p) { override lazy val module = new DCacheModule(this) } class DCacheTLBPort(implicit p: Parameters) extends CoreBundle()(p) { val req = Flipped(Decoupled(new TLBReq(coreDataBytes.log2))) val s1_resp = Output(new TLBResp(coreDataBytes.log2)) val s2_kill = Input(Bool()) } class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { val tECC = cacheParams.tagCode val dECC = cacheParams.dataCode require(subWordBits % eccBits == 0, "subWordBits must be a multiple of eccBits") require(eccBytes == 1 \|\| !dECC.isInstanceOf[IdentityCode]) require(cacheParams.silentDrop \|\| cacheParams.acquireBeforeRelease, "!silentDrop requires acquireBeforeRelease") val usingRMW = eccBytes > 1 \|\| usingAtomicsInCache val mmioOffset = outer.firstMMIO edge.manager.requireFifo(TLFIFOFixer.allVolatile) // TileLink pipelining MMIO requests val clock_en_reg = Reg(Bool()) io.cpu.clock_enabled := clock_en_reg val gated_clock = if (!cacheParams.clockGate) clock else ClockGate(clock, clock_en_reg, "dcache_clock_gate") class DCacheModuleImpl { // entering gated-clock domain val tlb = Module(new TLB(false, log2Ceil(coreDataBytes), TLBConfig(nTLBSets, nTLBWays, cacheParams.nTLBBasePageSectors, cacheParams.nTLBSuperpages))) val pma_checker = Module(new TLB(false, log2Ceil(coreDataBytes), TLBConfig(nTLBSets, nTLBWays, cacheParams.nTLBBasePageSectors, cacheParams.nTLBSuperpages)) with InlineInstance) // tags val replacer = ReplacementPolicy.fromString(cacheParams.replacementPolicy, nWays) /** Metadata Arbiter: * 0: Tag update on reset * 1: Tag update on ECC error * 2: Tag update on hit * 3: Tag update on refill * 4: Tag update on release * 5: Tag update on flush * 6: Tag update on probe * 7: Tag update on CPU request / val metaArb = Module(new Arbiter(new DCacheMetadataReq, 8) with InlineInstance) val tag_array = DescribedSRAM( name = s"${tileParams.baseName}_dcache_tag_array", desc = "DCache Tag Array", size = nSets, data = Vec(nWays, chiselTypeOf(metaArb.io.out.bits.data)) ) // data val data = Module(new DCacheDataArray) /* Data Arbiter * 0: data from pending store buffer * 1: data from TL-D refill * 2: release to TL-A * 3: hit path to CPU / val dataArb = Module(new Arbiter(new DCacheDataReq, 4) with InlineInstance) dataArb.io.in.tail.foreach(_.bits.wdata := dataArb.io.in.head.bits.wdata) // tie off write ports by default data.io.req.bits <> dataArb.io.out.bits data.io.req.valid := dataArb.io.out.valid dataArb.io.out.ready := true.B metaArb.io.out.ready := clock_en_reg val tl_out_a = Wire(chiselTypeOf(tl_out.a)) tl_out.a <> { val a_queue_depth = outer.crossing match { case RationalCrossing(_) => // TODO make this depend on the actual ratio? if (cacheParams.separateUncachedResp) (maxUncachedInFlight + 1) / 2 else 2 min maxUncachedInFlight-1 case SynchronousCrossing(BufferParams.none) => 1 // Need some buffering to guarantee livelock freedom case SynchronousCrossing(_) => 0 // Adequate buffering within the crossing case _: AsynchronousCrossing => 0 // Adequate buffering within the crossing case _: CreditedCrossing => 0 // Adequate buffering within the crossing } Queue(tl_out_a, a_queue_depth, flow = true) } val (tl_out_c, release_queue_empty) = if (cacheParams.acquireBeforeRelease) { val q = Module(new Queue(chiselTypeOf(tl_out.c.bits), cacheDataBeats, flow = true)) tl_out.c <> q.io.deq (q.io.enq, q.io.count === 0.U) } else { (tl_out.c, true.B) } val s1_valid = RegNext(io.cpu.req.fire, false.B) val s1_probe = RegNext(tl_out.b.fire, false.B) val probe_bits = RegEnable(tl_out.b.bits, tl_out.b.fire) // TODO has data now :( val s1_nack = WireDefault(false.B) val s1_valid_masked = s1_valid && !io.cpu.s1_kill val s1_valid_not_nacked = s1_valid && !s1_nack val s1_tlb_req_valid = RegNext(io.tlb_port.req.fire, false.B) val s2_tlb_req_valid = RegNext(s1_tlb_req_valid, false.B) val s0_clk_en = metaArb.io.out.valid && !metaArb.io.out.bits.write val s0_req = WireInit(io.cpu.req.bits) s0_req.addr := Cat(metaArb.io.out.bits.addr >> blockOffBits, io.cpu.req.bits.addr(blockOffBits-1,0)) s0_req.idx.foreach(_ := Cat(metaArb.io.out.bits.idx, s0_req.addr(blockOffBits-1, 0))) when (!metaArb.io.in(7).ready) { s0_req.phys := true.B } val s1_req = RegEnable(s0_req, s0_clk_en) val s1_vaddr = Cat(s1_req.idx.getOrElse(s1_req.addr) >> tagLSB, s1_req.addr(tagLSB-1, 0)) val s0_tlb_req = WireInit(io.tlb_port.req.bits) when (!io.tlb_port.req.fire) { s0_tlb_req.passthrough := s0_req.phys s0_tlb_req.vaddr := s0_req.addr s0_tlb_req.size := s0_req.size s0_tlb_req.cmd := s0_req.cmd s0_tlb_req.prv := s0_req.dprv s0_tlb_req.v := s0_req.dv } val s1_tlb_req = RegEnable(s0_tlb_req, s0_clk_en \|\| io.tlb_port.req.valid) val s1_read = isRead(s1_req.cmd) val s1_write = isWrite(s1_req.cmd) val s1_readwrite = s1_read \|\| s1_write val s1_sfence = s1_req.cmd === M_SFENCE \|\| s1_req.cmd === M_HFENCEV \|\| s1_req.cmd === M_HFENCEG val s1_flush_line = s1_req.cmd === M_FLUSH_ALL && s1_req.size(0) val s1_flush_valid = Reg(Bool()) val s1_waw_hazard = Wire(Bool()) val s_ready :: s_voluntary_writeback :: s_probe_rep_dirty :: s_probe_rep_clean :: s_probe_retry :: s_probe_rep_miss :: s_voluntary_write_meta :: s_probe_write_meta :: s_dummy :: s_voluntary_release :: Nil = Enum(10) val supports_flush = outer.flushOnFenceI \|\| coreParams.haveCFlush val flushed = RegInit(true.B) val flushing = RegInit(false.B) val flushing_req = Reg(chiselTypeOf(s1_req)) val cached_grant_wait = RegInit(false.B) val resetting = RegInit(false.B) val flushCounter = RegInit((nSets (nWays-1)).U(log2Ceil(nSets * nWays).W)) val release_ack_wait = RegInit(false.B) val release_ack_addr = Reg(UInt(paddrBits.W)) val release_state = RegInit(s_ready) val refill_way = Reg(UInt()) val any_pstore_valid = Wire(Bool()) val inWriteback = release_state.isOneOf(s_voluntary_writeback, s_probe_rep_dirty) val releaseWay = Wire(UInt()) io.cpu.req.ready := (release_state === s_ready) && !cached_grant_wait && !s1_nack // I/O MSHRs val uncachedInFlight = RegInit(VecInit(Seq.fill(maxUncachedInFlight)(false.B))) val uncachedReqs = Reg(Vec(maxUncachedInFlight, new HellaCacheReq)) val uncachedResp = WireInit(new HellaCacheReq, DontCare) // hit initiation path val s0_read = isRead(io.cpu.req.bits.cmd) dataArb.io.in(3).valid := io.cpu.req.valid && likelyNeedsRead(io.cpu.req.bits) dataArb.io.in(3).bits := dataArb.io.in(1).bits dataArb.io.in(3).bits.write := false.B dataArb.io.in(3).bits.addr := Cat(io.cpu.req.bits.idx.getOrElse(io.cpu.req.bits.addr) >> tagLSB, io.cpu.req.bits.addr(tagLSB-1, 0)) dataArb.io.in(3).bits.wordMask := { val mask = (subWordBytes.log2 until rowOffBits).foldLeft(1.U) { case (in, i) => val upper_mask = Mux((i >= wordBytes.log2).B \|\| io.cpu.req.bits.size <= i.U, 0.U, ((BigInt(1) << (1 << (i - subWordBytes.log2)))-1).U) val upper = Mux(io.cpu.req.bits.addr(i), in, 0.U) \| upper_mask val lower = Mux(io.cpu.req.bits.addr(i), 0.U, in) upper ## lower } Fill(subWordBytes / eccBytes, mask) } dataArb.io.in(3).bits.eccMask := ~0.U((wordBytes / eccBytes).W) dataArb.io.in(3).bits.way_en := ~0.U(nWays.W) when (!dataArb.io.in(3).ready && s0_read) { io.cpu.req.ready := false.B } val s1_did_read = RegEnable(dataArb.io.in(3).ready && (io.cpu.req.valid && needsRead(io.cpu.req.bits)), s0_clk_en) val s1_read_mask = RegEnable(dataArb.io.in(3).bits.wordMask, s0_clk_en) metaArb.io.in(7).valid := io.cpu.req.valid metaArb.io.in(7).bits.write := false.B metaArb.io.in(7).bits.idx := dataArb.io.in(3).bits.addr(idxMSB, idxLSB) metaArb.io.in(7).bits.addr := io.cpu.req.bits.addr metaArb.io.in(7).bits.way_en := metaArb.io.in(4).bits.way_en metaArb.io.in(7).bits.data := metaArb.io.in(4).bits.data when (!metaArb.io.in(7).ready) { io.cpu.req.ready := false.B } // address translation val s1_cmd_uses_tlb = s1_readwrite \|\| s1_flush_line \|\| s1_req.cmd === M_WOK io.ptw <> tlb.io.ptw tlb.io.kill := io.cpu.s2_kill \|\| s2_tlb_req_valid && io.tlb_port.s2_kill tlb.io.req.valid := s1_tlb_req_valid \|\| s1_valid && !io.cpu.s1_kill && s1_cmd_uses_tlb tlb.io.req.bits := s1_tlb_req when (!tlb.io.req.ready && !tlb.io.ptw.resp.valid && !io.cpu.req.bits.phys) { io.cpu.req.ready := false.B } when (!s1_tlb_req_valid && s1_valid && s1_cmd_uses_tlb && tlb.io.resp.miss) { s1_nack := true.B } tlb.io.sfence.valid := s1_valid && !io.cpu.s1_kill && s1_sfence tlb.io.sfence.bits.rs1 := s1_req.size(0) tlb.io.sfence.bits.rs2 := s1_req.size(1) tlb.io.sfence.bits.asid := io.cpu.s1_data.data tlb.io.sfence.bits.addr := s1_req.addr tlb.io.sfence.bits.hv := s1_req.cmd === M_HFENCEV tlb.io.sfence.bits.hg := s1_req.cmd === M_HFENCEG io.tlb_port.req.ready := clock_en_reg io.tlb_port.s1_resp := tlb.io.resp when (s1_tlb_req_valid && s1_valid && !(s1_req.phys && s1_req.no_xcpt)) { s1_nack := true.B } pma_checker.io <> DontCare pma_checker.io.req.bits.passthrough := true.B pma_checker.io.req.bits.vaddr := s1_req.addr pma_checker.io.req.bits.size := s1_req.size pma_checker.io.req.bits.cmd := s1_req.cmd pma_checker.io.req.bits.prv := s1_req.dprv pma_checker.io.req.bits.v := s1_req.dv val s1_paddr = Cat(Mux(s1_tlb_req_valid, s1_req.addr(paddrBits-1, pgIdxBits), tlb.io.resp.paddr >> pgIdxBits), s1_req.addr(pgIdxBits-1, 0)) val s1_victim_way = Wire(UInt()) val (s1_hit_way, s1_hit_state, s1_meta) = if (usingDataScratchpad) { val baseAddr = p(LookupByHartId)(_.dcache.flatMap(_.scratch.map(_.U)), io_hartid.get) \| io_mmio_address_prefix.get val inScratchpad = s1_paddr >= baseAddr && s1_paddr < baseAddr + (nSets * cacheBlockBytes).U val hitState = Mux(inScratchpad, ClientMetadata.maximum, ClientMetadata.onReset) val dummyMeta = L1Metadata(0.U, ClientMetadata.onReset) (inScratchpad, hitState, Seq(tECC.encode(dummyMeta.asUInt))) } else { val metaReq = metaArb.io.out val metaIdx = metaReq.bits.idx when (metaReq.valid && metaReq.bits.write) { val wmask = if (nWays == 1) Seq(true.B) else metaReq.bits.way_en.asBools tag_array.write(metaIdx, VecInit(Seq.fill(nWays)(metaReq.bits.data)), wmask) } val s1_meta = tag_array.read(metaIdx, metaReq.valid && !metaReq.bits.write) val s1_meta_uncorrected = s1_meta.map(tECC.decode(_).uncorrected.asTypeOf(new L1Metadata)) val s1_tag = s1_paddr >> tagLSB val s1_meta_hit_way = s1_meta_uncorrected.map(r => r.coh.isValid() && r.tag === s1_tag).asUInt val s1_meta_hit_state = ( s1_meta_uncorrected.map(r => Mux(r.tag === s1_tag && !s1_flush_valid, r.coh.asUInt, 0.U)) .reduce (_\|_)).asTypeOf(chiselTypeOf(ClientMetadata.onReset)) (s1_meta_hit_way, s1_meta_hit_state, s1_meta) } val s1_data_way = WireDefault(if (nWays == 1) 1.U else Mux(inWriteback, releaseWay, s1_hit_way)) val tl_d_data_encoded = Wire(chiselTypeOf(encodeData(tl_out.d.bits.data, false.B))) val s1_all_data_ways = VecInit(data.io.resp ++ (!cacheParams.separateUncachedResp).option(tl_d_data_encoded)) val s1_mask_xwr = new StoreGen(s1_req.size, s1_req.addr, 0.U, wordBytes).mask val s1_mask = Mux(s1_req.cmd === M_PWR, io.cpu.s1_data.mask, s1_mask_xwr) // for partial writes, s1_data.mask must be a subset of s1_mask_xwr assert(!(s1_valid_masked && s1_req.cmd === M_PWR) \|\| (s1_mask_xwr \| ~io.cpu.s1_data.mask).andR) val s2_valid = RegNext(s1_valid_masked && !s1_sfence, init=false.B) val s2_valid_no_xcpt = s2_valid && !io.cpu.s2_xcpt.asUInt.orR val s2_probe = RegNext(s1_probe, init=false.B) val releaseInFlight = s1_probe \|\| s2_probe \|\| release_state =/= s_ready val s2_not_nacked_in_s1 = RegNext(!s1_nack) val s2_valid_not_nacked_in_s1 = s2_valid && s2_not_nacked_in_s1 val s2_valid_masked = s2_valid_no_xcpt && s2_not_nacked_in_s1 val s2_valid_not_killed = s2_valid_masked && !io.cpu.s2_kill val s2_req = Reg(chiselTypeOf(io.cpu.req.bits)) val s2_cmd_flush_all = s2_req.cmd === M_FLUSH_ALL && !s2_req.size(0) val s2_cmd_flush_line = s2_req.cmd === M_FLUSH_ALL && s2_req.size(0) val s2_tlb_xcpt = Reg(chiselTypeOf(tlb.io.resp)) val s2_pma = Reg(chiselTypeOf(tlb.io.resp)) val s2_uncached_resp_addr = Reg(chiselTypeOf(s2_req.addr)) // should be DCE'd in synthesis when (s1_valid_not_nacked \|\| s1_flush_valid) { s2_req := s1_req s2_req.addr := s1_paddr s2_tlb_xcpt := tlb.io.resp s2_pma := Mux(s1_tlb_req_valid, pma_checker.io.resp, tlb.io.resp) } val s2_vaddr = Cat(RegEnable(s1_vaddr, s1_valid_not_nacked \|\| s1_flush_valid) >> tagLSB, s2_req.addr(tagLSB-1, 0)) val s2_read = isRead(s2_req.cmd) val s2_write = isWrite(s2_req.cmd) val s2_readwrite = s2_read \|\| s2_write val s2_flush_valid_pre_tag_ecc = RegNext(s1_flush_valid) val s1_meta_decoded = s1_meta.map(tECC.decode(_)) val s1_meta_clk_en = s1_valid_not_nacked \|\| s1_flush_valid \|\| s1_probe val s2_meta_correctable_errors = s1_meta_decoded.map(m => RegEnable(m.correctable, s1_meta_clk_en)).asUInt val s2_meta_uncorrectable_errors = s1_meta_decoded.map(m => RegEnable(m.uncorrectable, s1_meta_clk_en)).asUInt val s2_meta_error_uncorrectable = s2_meta_uncorrectable_errors.orR val s2_meta_corrected = s1_meta_decoded.map(m => RegEnable(m.corrected, s1_meta_clk_en).asTypeOf(new L1Metadata)) val s2_meta_error = (s2_meta_uncorrectable_errors \| s2_meta_correctable_errors).orR val s2_flush_valid = s2_flush_valid_pre_tag_ecc && !s2_meta_error val s2_data = { val wordsPerRow = rowBits / subWordBits val en = s1_valid \|\| inWriteback \|\| io.cpu.replay_next val word_en = Mux(inWriteback, Fill(wordsPerRow, 1.U), Mux(s1_did_read, s1_read_mask, 0.U)) val s1_way_words = s1_all_data_ways.map(_.grouped(dECC.width(eccBits) * (subWordBits / eccBits))) if (cacheParams.pipelineWayMux) { val s1_word_en = Mux(io.cpu.replay_next, 0.U, word_en) (for (i <- 0 until wordsPerRow) yield { val s2_way_en = RegEnable(Mux(s1_word_en(i), s1_data_way, 0.U), en) val s2_way_words = (0 until nWays).map(j => RegEnable(s1_way_words(j)(i), en && word_en(i))) (0 until nWays).map(j => Mux(s2_way_en(j), s2_way_words(j), 0.U)).reduce(_\|_) }).asUInt } else { val s1_word_en = Mux(!io.cpu.replay_next, word_en, UIntToOH(uncachedResp.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)), wordsPerRow)) (for (i <- 0 until wordsPerRow) yield { RegEnable(Mux1H(Mux(s1_word_en(i), s1_data_way, 0.U), s1_way_words.map(_(i))), en) }).asUInt } } val s2_probe_way = RegEnable(s1_hit_way, s1_probe) val s2_probe_state = RegEnable(s1_hit_state, s1_probe) val s2_hit_way = RegEnable(s1_hit_way, s1_valid_not_nacked) val s2_hit_state = RegEnable(s1_hit_state, s1_valid_not_nacked \|\| s1_flush_valid) val s2_waw_hazard = RegEnable(s1_waw_hazard, s1_valid_not_nacked) val s2_store_merge = Wire(Bool()) val s2_hit_valid = s2_hit_state.isValid() val (s2_hit, s2_grow_param, s2_new_hit_state) = s2_hit_state.onAccess(s2_req.cmd) val s2_data_decoded = decodeData(s2_data) val s2_word_idx = s2_req.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)) val s2_data_error = s2_data_decoded.map(_.error).orR val s2_data_error_uncorrectable = s2_data_decoded.map(_.uncorrectable).orR val s2_data_corrected = (s2_data_decoded.map(_.corrected): Seq[UInt]).asUInt val s2_data_uncorrected = (s2_data_decoded.map(_.uncorrected): Seq[UInt]).asUInt val s2_valid_hit_maybe_flush_pre_data_ecc_and_waw = s2_valid_masked && !s2_meta_error && s2_hit val s2_no_alloc_hazard = if (!usingVM \|\| pgIdxBits >= untagBits) false.B else { // make sure that any in-flight non-allocating accesses are ordered before // any allocating accesses. this can only happen if aliasing is possible. val any_no_alloc_in_flight = Reg(Bool()) when (!uncachedInFlight.asUInt.orR) { any_no_alloc_in_flight := false.B } when (s2_valid && s2_req.no_alloc) { any_no_alloc_in_flight := true.B } val s1_need_check = any_no_alloc_in_flight \|\| s2_valid && s2_req.no_alloc val concerns = (uncachedInFlight zip uncachedReqs) :+ (s2_valid && s2_req.no_alloc, s2_req) val s1_uncached_hits = concerns.map { c => val concern_wmask = new StoreGen(c._2.size, c._2.addr, 0.U, wordBytes).mask val addr_match = (c._2.addr ^ s1_paddr)(pgIdxBits+pgLevelBits-1, wordBytes.log2) === 0.U val mask_match = (concern_wmask & s1_mask_xwr).orR \|\| c._2.cmd === M_PWR \|\| s1_req.cmd === M_PWR val cmd_match = isWrite(c._2.cmd) \|\| isWrite(s1_req.cmd) c._1 && s1_need_check && cmd_match && addr_match && mask_match } val s2_uncached_hits = RegEnable(s1_uncached_hits.asUInt, s1_valid_not_nacked) s2_uncached_hits.orR } val s2_valid_hit_pre_data_ecc_and_waw = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw && s2_readwrite && !s2_no_alloc_hazard val s2_valid_flush_line = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw && s2_cmd_flush_line val s2_valid_hit_pre_data_ecc = s2_valid_hit_pre_data_ecc_and_waw && (!s2_waw_hazard \|\| s2_store_merge) val s2_valid_data_error = s2_valid_hit_pre_data_ecc_and_waw && s2_data_error val s2_valid_hit = s2_valid_hit_pre_data_ecc && !s2_data_error val s2_valid_miss = s2_valid_masked && s2_readwrite && !s2_meta_error && !s2_hit val s2_uncached = !s2_pma.cacheable \|\| s2_req.no_alloc && !s2_pma.must_alloc && !s2_hit_valid val s2_valid_cached_miss = s2_valid_miss && !s2_uncached && !uncachedInFlight.asUInt.orR dontTouch(s2_valid_cached_miss) val s2_want_victimize = (!usingDataScratchpad).B && (s2_valid_cached_miss \|\| s2_valid_flush_line \|\| s2_valid_data_error \|\| s2_flush_valid) val s2_cannot_victimize = !s2_flush_valid && io.cpu.s2_kill val s2_victimize = s2_want_victimize && !s2_cannot_victimize val s2_valid_uncached_pending = s2_valid_miss && s2_uncached && !uncachedInFlight.asUInt.andR val s2_victim_way = UIntToOH(RegEnable(s1_victim_way, s1_valid_not_nacked \|\| s1_flush_valid)) val s2_victim_or_hit_way = Mux(s2_hit_valid, s2_hit_way, s2_victim_way) val s2_victim_tag = Mux(s2_valid_data_error \|\| s2_valid_flush_line, s2_req.addr(paddrBits-1, tagLSB), Mux1H(s2_victim_way, s2_meta_corrected).tag) val s2_victim_state = Mux(s2_hit_valid, s2_hit_state, Mux1H(s2_victim_way, s2_meta_corrected).coh) val (s2_prb_ack_data, s2_report_param, probeNewCoh)= s2_probe_state.onProbe(probe_bits.param) val (s2_victim_dirty, s2_shrink_param, voluntaryNewCoh) = s2_victim_state.onCacheControl(M_FLUSH) dontTouch(s2_victim_dirty) val s2_update_meta = s2_hit_state =/= s2_new_hit_state val s2_dont_nack_uncached = s2_valid_uncached_pending && tl_out_a.ready val s2_dont_nack_misc = s2_valid_masked && !s2_meta_error && (supports_flush.B && s2_cmd_flush_all && flushed && !flushing \|\| supports_flush.B && s2_cmd_flush_line && !s2_hit \|\| s2_req.cmd === M_WOK) io.cpu.s2_nack := s2_valid_no_xcpt && !s2_dont_nack_uncached && !s2_dont_nack_misc && !s2_valid_hit when (io.cpu.s2_nack \|\| (s2_valid_hit_pre_data_ecc_and_waw && s2_update_meta)) { s1_nack := true.B } // tag updates on ECC errors val s2_first_meta_corrected = PriorityMux(s2_meta_correctable_errors, s2_meta_corrected) metaArb.io.in(1).valid := s2_meta_error && (s2_valid_masked \|\| s2_flush_valid_pre_tag_ecc \|\| s2_probe) metaArb.io.in(1).bits.write := true.B metaArb.io.in(1).bits.way_en := s2_meta_uncorrectable_errors \| Mux(s2_meta_error_uncorrectable, 0.U, PriorityEncoderOH(s2_meta_correctable_errors)) metaArb.io.in(1).bits.idx := Mux(s2_probe, probeIdx(probe_bits), s2_vaddr(idxMSB, idxLSB)) metaArb.io.in(1).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, metaArb.io.in(1).bits.idx << blockOffBits) metaArb.io.in(1).bits.data := tECC.encode { val new_meta = WireDefault(s2_first_meta_corrected) when (s2_meta_error_uncorrectable) { new_meta.coh := ClientMetadata.onReset } new_meta.asUInt } // tag updates on hit metaArb.io.in(2).valid := s2_valid_hit_pre_data_ecc_and_waw && s2_update_meta metaArb.io.in(2).bits.write := !io.cpu.s2_kill metaArb.io.in(2).bits.way_en := s2_victim_or_hit_way metaArb.io.in(2).bits.idx := s2_vaddr(idxMSB, idxLSB) metaArb.io.in(2).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, s2_vaddr(idxMSB, 0)) metaArb.io.in(2).bits.data := tECC.encode(L1Metadata(s2_req.addr >> tagLSB, s2_new_hit_state).asUInt) // load reservations and TL error reporting val s2_lr = (usingAtomics && !usingDataScratchpad).B && s2_req.cmd === M_XLR val s2_sc = (usingAtomics && !usingDataScratchpad).B && s2_req.cmd === M_XSC val lrscCount = RegInit(0.U) val lrscValid = lrscCount > lrscBackoff.U val lrscBackingOff = lrscCount > 0.U && !lrscValid val lrscAddr = Reg(UInt()) val lrscAddrMatch = lrscAddr === (s2_req.addr >> blockOffBits) val s2_sc_fail = s2_sc && !(lrscValid && lrscAddrMatch) when ((s2_valid_hit && s2_lr && !cached_grant_wait \|\| s2_valid_cached_miss) && !io.cpu.s2_kill) { lrscCount := Mux(s2_hit, (lrscCycles - 1).U, 0.U) lrscAddr := s2_req.addr >> blockOffBits } when (lrscCount > 0.U) { lrscCount := lrscCount - 1.U } when (s2_valid_not_killed && lrscValid) { lrscCount := lrscBackoff.U } when (s1_probe) { lrscCount := 0.U } // don't perform data correction if it might clobber a recent store val s2_correct = s2_data_error && !any_pstore_valid && !RegNext(any_pstore_valid \|\| s2_valid) && usingDataScratchpad.B // pending store buffer val s2_valid_correct = s2_valid_hit_pre_data_ecc_and_waw && s2_correct && !io.cpu.s2_kill def s2_store_valid_pre_kill = s2_valid_hit && s2_write && !s2_sc_fail def s2_store_valid = s2_store_valid_pre_kill && !io.cpu.s2_kill val pstore1_cmd = RegEnable(s1_req.cmd, s1_valid_not_nacked && s1_write) val pstore1_addr = RegEnable(s1_vaddr, s1_valid_not_nacked && s1_write) val pstore1_data = RegEnable(io.cpu.s1_data.data, s1_valid_not_nacked && s1_write) val pstore1_way = RegEnable(s1_hit_way, s1_valid_not_nacked && s1_write) val pstore1_mask = RegEnable(s1_mask, s1_valid_not_nacked && s1_write) val pstore1_storegen_data = WireDefault(pstore1_data) val pstore1_rmw = usingRMW.B && RegEnable(needsRead(s1_req), s1_valid_not_nacked && s1_write) val pstore1_merge_likely = s2_valid_not_nacked_in_s1 && s2_write && s2_store_merge val pstore1_merge = s2_store_valid && s2_store_merge val pstore2_valid = RegInit(false.B) val pstore_drain_opportunistic = !(io.cpu.req.valid && likelyNeedsRead(io.cpu.req.bits)) && !(s1_valid && s1_waw_hazard) val pstore_drain_on_miss = releaseInFlight \|\| RegNext(io.cpu.s2_nack) val pstore1_held = RegInit(false.B) val pstore1_valid_likely = s2_valid && s2_write \|\| pstore1_held def pstore1_valid_not_rmw(s2_kill: Bool) = s2_valid_hit_pre_data_ecc && s2_write && !s2_kill \|\| pstore1_held val pstore1_valid = s2_store_valid \|\| pstore1_held any_pstore_valid := pstore1_held \|\| pstore2_valid val pstore_drain_structural = pstore1_valid_likely && pstore2_valid && ((s1_valid && s1_write) \|\| pstore1_rmw) assert(pstore1_rmw \|\| pstore1_valid_not_rmw(io.cpu.s2_kill) === pstore1_valid) ccover(pstore_drain_structural, "STORE_STRUCTURAL_HAZARD", "D$ read-modify-write structural hazard") ccover(pstore1_valid && pstore_drain_on_miss, "STORE_DRAIN_ON_MISS", "D$ store buffer drain on miss") ccover(s1_valid_not_nacked && s1_waw_hazard, "WAW_HAZARD", "D$ write-after-write hazard") def should_pstore_drain(truly: Bool) = { val s2_kill = truly && io.cpu.s2_kill !pstore1_merge_likely && (usingRMW.B && pstore_drain_structural \|\| (((pstore1_valid_not_rmw(s2_kill) && !pstore1_rmw) \|\| pstore2_valid) && (pstore_drain_opportunistic \|\| pstore_drain_on_miss))) } val pstore_drain = should_pstore_drain(true.B) pstore1_held := (s2_store_valid && !s2_store_merge \|\| pstore1_held) && pstore2_valid && !pstore_drain val advance_pstore1 = (pstore1_valid \|\| s2_valid_correct) && (pstore2_valid === pstore_drain) pstore2_valid := pstore2_valid && !pstore_drain \|\| advance_pstore1 val pstore2_addr = RegEnable(Mux(s2_correct, s2_vaddr, pstore1_addr), advance_pstore1) val pstore2_way = RegEnable(Mux(s2_correct, s2_hit_way, pstore1_way), advance_pstore1) val pstore2_storegen_data = { for (i <- 0 until wordBytes) yield RegEnable(pstore1_storegen_data(8(i+1)-1, 8i), advance_pstore1 \|\| pstore1_merge && pstore1_mask(i)) }.asUInt val pstore2_storegen_mask = { val mask = Reg(UInt(wordBytes.W)) when (advance_pstore1 \|\| pstore1_merge) { val mergedMask = pstore1_mask \| Mux(pstore1_merge, mask, 0.U) mask := ~Mux(s2_correct, 0.U, ~mergedMask) } mask } s2_store_merge := (if (eccBytes == 1) false.B else { ccover(pstore1_merge, "STORE_MERGED", "D$ store merged") // only merge stores to ECC granules that are already stored-to, to avoid // WAW hazards val wordMatch = (eccMask(pstore2_storegen_mask) \| ~eccMask(pstore1_mask)).andR val idxMatch = s2_vaddr(untagBits-1, log2Ceil(wordBytes)) === pstore2_addr(untagBits-1, log2Ceil(wordBytes)) val tagMatch = (s2_hit_way & pstore2_way).orR pstore2_valid && wordMatch && idxMatch && tagMatch }) dataArb.io.in(0).valid := should_pstore_drain(false.B) dataArb.io.in(0).bits.write := pstore_drain dataArb.io.in(0).bits.addr := Mux(pstore2_valid, pstore2_addr, pstore1_addr) dataArb.io.in(0).bits.way_en := Mux(pstore2_valid, pstore2_way, pstore1_way) dataArb.io.in(0).bits.wdata := encodeData(Fill(rowWords, Mux(pstore2_valid, pstore2_storegen_data, pstore1_data)), false.B) dataArb.io.in(0).bits.wordMask := { val eccMask = dataArb.io.in(0).bits.eccMask.asBools.grouped(subWordBytes/eccBytes).map(_.orR).toSeq.asUInt val wordMask = UIntToOH(Mux(pstore2_valid, pstore2_addr, pstore1_addr).extract(rowOffBits-1, wordBytes.log2)) FillInterleaved(wordBytes/subWordBytes, wordMask) & Fill(rowBytes/wordBytes, eccMask) } dataArb.io.in(0).bits.eccMask := eccMask(Mux(pstore2_valid, pstore2_storegen_mask, pstore1_mask)) // store->load RAW hazard detection def s1Depends(addr: UInt, mask: UInt) = addr(idxMSB, wordOffBits) === s1_vaddr(idxMSB, wordOffBits) && Mux(s1_write, (eccByteMask(mask) & eccByteMask(s1_mask_xwr)).orR, (mask & s1_mask_xwr).orR) val s1_hazard = (pstore1_valid_likely && s1Depends(pstore1_addr, pstore1_mask)) \|\| (pstore2_valid && s1Depends(pstore2_addr, pstore2_storegen_mask)) val s1_raw_hazard = s1_read && s1_hazard s1_waw_hazard := (if (eccBytes == 1) false.B else { ccover(s1_valid_not_nacked && s1_waw_hazard, "WAW_HAZARD", "D$ write-after-write hazard") s1_write && (s1_hazard \|\| needsRead(s1_req) && !s1_did_read) }) when (s1_valid && s1_raw_hazard) { s1_nack := true.B } // performance hints to processor io.cpu.s2_nack_cause_raw := RegNext(s1_raw_hazard) \|\| !(!s2_waw_hazard \|\| s2_store_merge) // Prepare a TileLink request message that initiates a transaction val a_source = PriorityEncoder(~uncachedInFlight.asUInt << mmioOffset) // skip the MSHR val acquire_address = (s2_req.addr >> idxLSB) << idxLSB val access_address = s2_req.addr val a_size = s2_req.size val a_data = Fill(beatWords, pstore1_data) val a_mask = pstore1_mask << (access_address.extract(beatBytes.log2-1, wordBytes.log2) << 3) val get = edge.Get(a_source, access_address, a_size)._2 val put = edge.Put(a_source, access_address, a_size, a_data)._2 val putpartial = edge.Put(a_source, access_address, a_size, a_data, a_mask)._2 val atomics = if (edge.manager.anySupportLogical) { MuxLookup(s2_req.cmd, WireDefault(0.U.asTypeOf(new TLBundleA(edge.bundle))))(Array( M_XA_SWAP -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.SWAP)._2, M_XA_XOR -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.XOR) ._2, M_XA_OR -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.OR) ._2, M_XA_AND -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.AND) ._2, M_XA_ADD -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.ADD)._2, M_XA_MIN -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MIN)._2, M_XA_MAX -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MAX)._2, M_XA_MINU -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MINU)._2, M_XA_MAXU -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MAXU)._2)) } else { // If no managers support atomics, assert fail if processor asks for them assert (!(tl_out_a.valid && s2_read && s2_write && s2_uncached)) WireDefault(new TLBundleA(edge.bundle), DontCare) } tl_out_a.valid := !io.cpu.s2_kill && (s2_valid_uncached_pending \|\| (s2_valid_cached_miss && !(release_ack_wait && (s2_req.addr ^ release_ack_addr)(((pgIdxBits + pgLevelBits) min paddrBits) - 1, idxLSB) === 0.U) && (cacheParams.acquireBeforeRelease.B && !release_ack_wait && release_queue_empty \|\| !s2_victim_dirty))) tl_out_a.bits := Mux(!s2_uncached, acquire(s2_vaddr, s2_req.addr, s2_grow_param), Mux(!s2_write, get, Mux(s2_req.cmd === M_PWR, putpartial, Mux(!s2_read, put, atomics)))) // Drive APROT Bits tl_out_a.bits.user.lift(AMBAProt).foreach { x => val user_bit_cacheable = s2_pma.cacheable x.privileged := s2_req.dprv === PRV.M.U \|\| user_bit_cacheable // if the address is cacheable, enable outer caches x.bufferable := user_bit_cacheable x.modifiable := user_bit_cacheable x.readalloc := user_bit_cacheable x.writealloc := user_bit_cacheable // Following are always tied off x.fetch := false.B x.secure := true.B } // Set pending bits for outstanding TileLink transaction val a_sel = UIntToOH(a_source, maxUncachedInFlight+mmioOffset) >> mmioOffset when (tl_out_a.fire) { when (s2_uncached) { (a_sel.asBools zip (uncachedInFlight zip uncachedReqs)) foreach { case (s, (f, r)) => when (s) { f := true.B r := s2_req r.cmd := Mux(s2_write, Mux(s2_req.cmd === M_PWR, M_PWR, M_XWR), M_XRD) } } }.otherwise { cached_grant_wait := true.B refill_way := s2_victim_or_hit_way } } // grant val (d_first, d_last, d_done, d_address_inc) = edge.addr_inc(tl_out.d) val (d_opc, grantIsUncached, grantIsUncachedData) = { val uncachedGrantOpcodesSansData = Seq(AccessAck, HintAck) val uncachedGrantOpcodesWithData = Seq(AccessAckData) val uncachedGrantOpcodes = uncachedGrantOpcodesWithData ++ uncachedGrantOpcodesSansData val whole_opc = tl_out.d.bits.opcode if (usingDataScratchpad) { assert(!tl_out.d.valid \|\| whole_opc.isOneOf(uncachedGrantOpcodes)) // the only valid TL-D messages are uncached, so we can do some pruning val opc = whole_opc(uncachedGrantOpcodes.map(_.getWidth).max - 1, 0) val data = DecodeLogic(opc, uncachedGrantOpcodesWithData, uncachedGrantOpcodesSansData) (opc, true.B, data) } else { (whole_opc, whole_opc.isOneOf(uncachedGrantOpcodes), whole_opc.isOneOf(uncachedGrantOpcodesWithData)) } } tl_d_data_encoded := encodeData(tl_out.d.bits.data, tl_out.d.bits.corrupt && !io.ptw.customCSRs.suppressCorruptOnGrantData && !grantIsUncached) val grantIsCached = d_opc.isOneOf(Grant, GrantData) val grantIsVoluntary = d_opc === ReleaseAck // Clears a different pending bit val grantIsRefill = d_opc === GrantData // Writes the data array val grantInProgress = RegInit(false.B) val blockProbeAfterGrantCount = RegInit(0.U) when (blockProbeAfterGrantCount > 0.U) { blockProbeAfterGrantCount := blockProbeAfterGrantCount - 1.U } val canAcceptCachedGrant = !release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta, s_voluntary_release) tl_out.d.ready := Mux(grantIsCached, (!d_first \|\| tl_out.e.ready) && canAcceptCachedGrant, true.B) val uncachedRespIdxOH = UIntToOH(tl_out.d.bits.source, maxUncachedInFlight+mmioOffset) >> mmioOffset uncachedResp := Mux1H(uncachedRespIdxOH, uncachedReqs) when (tl_out.d.fire) { when (grantIsCached) { grantInProgress := true.B assert(cached_grant_wait, "A GrantData was unexpected by the dcache.") when(d_last) { cached_grant_wait := false.B grantInProgress := false.B blockProbeAfterGrantCount := (blockProbeAfterGrantCycles - 1).U replacer.miss } } .elsewhen (grantIsUncached) { (uncachedRespIdxOH.asBools zip uncachedInFlight) foreach { case (s, f) => when (s && d_last) { assert(f, "An AccessAck was unexpected by the dcache.") // TODO must handle Ack coming back on same cycle! f := false.B } } when (grantIsUncachedData) { if (!cacheParams.separateUncachedResp) { if (!cacheParams.pipelineWayMux) s1_data_way := 1.U << nWays s2_req.cmd := M_XRD s2_req.size := uncachedResp.size s2_req.signed := uncachedResp.signed s2_req.tag := uncachedResp.tag s2_req.addr := { require(rowOffBits >= beatOffBits) val dontCareBits = s1_paddr >> rowOffBits << rowOffBits dontCareBits \| uncachedResp.addr(beatOffBits-1, 0) } s2_uncached_resp_addr := uncachedResp.addr } } } .elsewhen (grantIsVoluntary) { assert(release_ack_wait, "A ReleaseAck was unexpected by the dcache.") // TODO should handle Ack coming back on same cycle! release_ack_wait := false.B } } // Finish TileLink transaction by issuing a GrantAck tl_out.e.valid := tl_out.d.valid && d_first && grantIsCached && canAcceptCachedGrant tl_out.e.bits := edge.GrantAck(tl_out.d.bits) assert(tl_out.e.fire === (tl_out.d.fire && d_first && grantIsCached)) // data refill // note this ready-valid signaling ignores E-channel backpressure, which // benignly means the data RAM might occasionally be redundantly written dataArb.io.in(1).valid := tl_out.d.valid && grantIsRefill && canAcceptCachedGrant when (grantIsRefill && !dataArb.io.in(1).ready) { tl_out.e.valid := false.B tl_out.d.ready := false.B } if (!usingDataScratchpad) { dataArb.io.in(1).bits.write := true.B dataArb.io.in(1).bits.addr := (s2_vaddr >> idxLSB) << idxLSB \| d_address_inc dataArb.io.in(1).bits.way_en := refill_way dataArb.io.in(1).bits.wdata := tl_d_data_encoded dataArb.io.in(1).bits.wordMask := ~0.U((rowBytes / subWordBytes).W) dataArb.io.in(1).bits.eccMask := ~0.U((wordBytes / eccBytes).W) } else { dataArb.io.in(1).bits := dataArb.io.in(0).bits } // tag updates on refill // ignore backpressure from metaArb, which can only be caused by tag ECC // errors on hit-under-miss. failing to write the new tag will leave the // line invalid, so we'll simply request the line again later. metaArb.io.in(3).valid := grantIsCached && d_done && !tl_out.d.bits.denied metaArb.io.in(3).bits.write := true.B metaArb.io.in(3).bits.way_en := refill_way metaArb.io.in(3).bits.idx := s2_vaddr(idxMSB, idxLSB) metaArb.io.in(3).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, s2_vaddr(idxMSB, 0)) metaArb.io.in(3).bits.data := tECC.encode(L1Metadata(s2_req.addr >> tagLSB, s2_hit_state.onGrant(s2_req.cmd, tl_out.d.bits.param)).asUInt) if (!cacheParams.separateUncachedResp) { // don't accept uncached grants if there's a structural hazard on s2_data... val blockUncachedGrant = Reg(Bool()) blockUncachedGrant := dataArb.io.out.valid when (grantIsUncachedData && (blockUncachedGrant \|\| s1_valid)) { tl_out.d.ready := false.B // ...but insert bubble to guarantee grant's eventual forward progress when (tl_out.d.valid) { io.cpu.req.ready := false.B dataArb.io.in(1).valid := true.B dataArb.io.in(1).bits.write := false.B blockUncachedGrant := !dataArb.io.in(1).ready } } } ccover(tl_out.d.valid && !tl_out.d.ready, "BLOCK_D", "D$ D-channel blocked") // Handle an incoming TileLink Probe message val block_probe_for_core_progress = blockProbeAfterGrantCount > 0.U \|\| lrscValid val block_probe_for_pending_release_ack = release_ack_wait && (tl_out.b.bits.address ^ release_ack_addr)(((pgIdxBits + pgLevelBits) min paddrBits) - 1, idxLSB) === 0.U val block_probe_for_ordering = releaseInFlight \|\| block_probe_for_pending_release_ack \|\| grantInProgress metaArb.io.in(6).valid := tl_out.b.valid && (!block_probe_for_core_progress \|\| lrscBackingOff) tl_out.b.ready := metaArb.io.in(6).ready && !(block_probe_for_core_progress \|\| block_probe_for_ordering \|\| s1_valid \|\| s2_valid) metaArb.io.in(6).bits.write := false.B metaArb.io.in(6).bits.idx := probeIdx(tl_out.b.bits) metaArb.io.in(6).bits.addr := Cat(io.cpu.req.bits.addr >> paddrBits, tl_out.b.bits.address) metaArb.io.in(6).bits.way_en := metaArb.io.in(4).bits.way_en metaArb.io.in(6).bits.data := metaArb.io.in(4).bits.data // replacement policy s1_victim_way := (if (replacer.perSet && nWays > 1) { val repl_array = Mem(nSets, UInt(replacer.nBits.W)) val s1_repl_idx = s1_req.addr(idxBits+blockOffBits-1, blockOffBits) val s2_repl_idx = s2_vaddr(idxBits+blockOffBits-1, blockOffBits) val s2_repl_state = Reg(UInt(replacer.nBits.W)) val s2_new_repl_state = replacer.get_next_state(s2_repl_state, OHToUInt(s2_hit_way)) val s2_repl_wen = s2_valid_masked && s2_hit_way.orR && s2_repl_state =/= s2_new_repl_state val s1_repl_state = Mux(s2_repl_wen && s2_repl_idx === s1_repl_idx, s2_new_repl_state, repl_array(s1_repl_idx)) when (s1_valid_not_nacked) { s2_repl_state := s1_repl_state } val waddr = Mux(resetting, flushCounter(idxBits-1, 0), s2_repl_idx) val wdata = Mux(resetting, 0.U, s2_new_repl_state) val wen = resetting \|\| s2_repl_wen when (wen) { repl_array(waddr) := wdata } replacer.get_replace_way(s1_repl_state) } else { replacer.way }) // release val (c_first, c_last, releaseDone, c_count) = edge.count(tl_out_c) val releaseRejected = Wire(Bool()) val s1_release_data_valid = RegNext(dataArb.io.in(2).fire) val s2_release_data_valid = RegNext(s1_release_data_valid && !releaseRejected) releaseRejected := s2_release_data_valid && !tl_out_c.fire val releaseDataBeat = Cat(0.U, c_count) + Mux(releaseRejected, 0.U, s1_release_data_valid + Cat(0.U, s2_release_data_valid)) val nackResponseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = TLPermissions.NtoN) val cleanReleaseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = s2_report_param) val dirtyReleaseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = s2_report_param, data = 0.U) tl_out_c.valid := (s2_release_data_valid \|\| (!cacheParams.silentDrop.B && release_state === s_voluntary_release)) && !(c_first && release_ack_wait) tl_out_c.bits := nackResponseMessage val newCoh = WireDefault(probeNewCoh) releaseWay := s2_probe_way if (!usingDataScratchpad) { when (s2_victimize) { assert(s2_valid_flush_line \|\| s2_flush_valid \|\| io.cpu.s2_nack) val discard_line = s2_valid_flush_line && s2_req.size(1) \|\| s2_flush_valid && flushing_req.size(1) release_state := Mux(s2_victim_dirty && !discard_line, s_voluntary_writeback, Mux(!cacheParams.silentDrop.B && !release_ack_wait && release_queue_empty && s2_victim_state.isValid() && (s2_valid_flush_line \|\| s2_flush_valid \|\| s2_readwrite && !s2_hit_valid), s_voluntary_release, s_voluntary_write_meta)) probe_bits := addressToProbe(s2_vaddr, Cat(s2_victim_tag, s2_req.addr(tagLSB-1, idxLSB)) << idxLSB) } when (s2_probe) { val probeNack = WireDefault(true.B) when (s2_meta_error) { release_state := s_probe_retry }.elsewhen (s2_prb_ack_data) { release_state := s_probe_rep_dirty }.elsewhen (s2_probe_state.isValid()) { tl_out_c.valid := true.B tl_out_c.bits := cleanReleaseMessage release_state := Mux(releaseDone, s_probe_write_meta, s_probe_rep_clean) }.otherwise { tl_out_c.valid := true.B probeNack := !releaseDone release_state := Mux(releaseDone, s_ready, s_probe_rep_miss) } when (probeNack) { s1_nack := true.B } } when (release_state === s_probe_retry) { metaArb.io.in(6).valid := true.B metaArb.io.in(6).bits.idx := probeIdx(probe_bits) metaArb.io.in(6).bits.addr := Cat(io.cpu.req.bits.addr >> paddrBits, probe_bits.address) when (metaArb.io.in(6).ready) { release_state := s_ready s1_probe := true.B } } when (release_state === s_probe_rep_miss) { tl_out_c.valid := true.B when (releaseDone) { release_state := s_ready } } when (release_state === s_probe_rep_clean) { tl_out_c.valid := true.B tl_out_c.bits := cleanReleaseMessage when (releaseDone) { release_state := s_probe_write_meta } } when (release_state === s_probe_rep_dirty) { tl_out_c.bits := dirtyReleaseMessage when (releaseDone) { release_state := s_probe_write_meta } } when (release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta, s_voluntary_release)) { when (release_state === s_voluntary_release) { tl_out_c.bits := edge.Release(fromSource = 0.U, toAddress = 0.U, lgSize = lgCacheBlockBytes.U, shrinkPermissions = s2_shrink_param)._2 }.otherwise { tl_out_c.bits := edge.Release(fromSource = 0.U, toAddress = 0.U, lgSize = lgCacheBlockBytes.U, shrinkPermissions = s2_shrink_param, data = 0.U)._2 } newCoh := voluntaryNewCoh releaseWay := s2_victim_or_hit_way when (releaseDone) { release_state := s_voluntary_write_meta } when (tl_out_c.fire && c_first) { release_ack_wait := true.B release_ack_addr := probe_bits.address } } tl_out_c.bits.source := probe_bits.source tl_out_c.bits.address := probe_bits.address tl_out_c.bits.data := s2_data_corrected tl_out_c.bits.corrupt := inWriteback && s2_data_error_uncorrectable } tl_out_c.bits.user.lift(AMBAProt).foreach { x => x.fetch := false.B x.secure := true.B x.privileged := true.B x.bufferable := true.B x.modifiable := true.B x.readalloc := true.B x.writealloc := true.B } dataArb.io.in(2).valid := inWriteback && releaseDataBeat < refillCycles.U dataArb.io.in(2).bits := dataArb.io.in(1).bits dataArb.io.in(2).bits.write := false.B dataArb.io.in(2).bits.addr := (probeIdx(probe_bits) << blockOffBits) \| (releaseDataBeat(log2Up(refillCycles)-1,0) << rowOffBits) dataArb.io.in(2).bits.wordMask := ~0.U((rowBytes / subWordBytes).W) dataArb.io.in(2).bits.eccMask := ~0.U((wordBytes / eccBytes).W) dataArb.io.in(2).bits.way_en := ~0.U(nWays.W) metaArb.io.in(4).valid := release_state.isOneOf(s_voluntary_write_meta, s_probe_write_meta) metaArb.io.in(4).bits.write := true.B metaArb.io.in(4).bits.way_en := releaseWay metaArb.io.in(4).bits.idx := probeIdx(probe_bits) metaArb.io.in(4).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, probe_bits.address(idxMSB, 0)) metaArb.io.in(4).bits.data := tECC.encode(L1Metadata(tl_out_c.bits.address >> tagLSB, newCoh).asUInt) when (metaArb.io.in(4).fire) { release_state := s_ready } // cached response (io.cpu.resp.bits: Data).waiveAll :<>= (s2_req: Data).waiveAll io.cpu.resp.bits.has_data := s2_read io.cpu.resp.bits.replay := false.B io.cpu.s2_uncached := s2_uncached && !s2_hit io.cpu.s2_paddr := s2_req.addr io.cpu.s2_gpa := s2_tlb_xcpt.gpa io.cpu.s2_gpa_is_pte := s2_tlb_xcpt.gpa_is_pte // report whether there are any outstanding accesses. disregard any // slave-port accesses, since they don't affect local memory ordering. val s1_isSlavePortAccess = s1_req.no_xcpt val s2_isSlavePortAccess = s2_req.no_xcpt io.cpu.ordered := !(s1_valid && !s1_isSlavePortAccess \|\| s2_valid && !s2_isSlavePortAccess \|\| cached_grant_wait \|\| uncachedInFlight.asUInt.orR) io.cpu.store_pending := (cached_grant_wait && isWrite(s2_req.cmd)) \|\| uncachedInFlight.asUInt.orR val s1_xcpt_valid = tlb.io.req.valid && !s1_isSlavePortAccess && !s1_nack io.cpu.s2_xcpt := Mux(RegNext(s1_xcpt_valid), s2_tlb_xcpt, 0.U.asTypeOf(s2_tlb_xcpt)) if (usingDataScratchpad) { assert(!(s2_valid_masked && s2_req.cmd.isOneOf(M_XLR, M_XSC))) } else { ccover(tl_out.b.valid && !tl_out.b.ready, "BLOCK_B", "D$ B-channel blocked") } // uncached response val s1_uncached_data_word = { val word_idx = uncachedResp.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)) val words = tl_out.d.bits.data.grouped(wordBits) words(word_idx) } val s2_uncached_data_word = RegEnable(s1_uncached_data_word, io.cpu.replay_next) val doUncachedResp = RegNext(io.cpu.replay_next) io.cpu.resp.valid := (s2_valid_hit_pre_data_ecc \|\| doUncachedResp) && !s2_data_error io.cpu.replay_next := tl_out.d.fire && grantIsUncachedData && !cacheParams.separateUncachedResp.B when (doUncachedResp) { assert(!s2_valid_hit) io.cpu.resp.bits.replay := true.B io.cpu.resp.bits.addr := s2_uncached_resp_addr } io.cpu.uncached_resp.map { resp => resp.valid := tl_out.d.valid && grantIsUncachedData resp.bits.tag := uncachedResp.tag resp.bits.size := uncachedResp.size resp.bits.signed := uncachedResp.signed resp.bits.data := new LoadGen(uncachedResp.size, uncachedResp.signed, uncachedResp.addr, s1_uncached_data_word, false.B, wordBytes).data resp.bits.data_raw := s1_uncached_data_word when (grantIsUncachedData && !resp.ready) { tl_out.d.ready := false.B } } // load data subword mux/sign extension val s2_data_word = (0 until rowBits by wordBits).map(i => s2_data_uncorrected(wordBits+i-1,i)).reduce(_\|_) val s2_data_word_corrected = (0 until rowBits by wordBits).map(i => s2_data_corrected(wordBits+i-1,i)).reduce(_\|_) val s2_data_word_possibly_uncached = Mux(cacheParams.pipelineWayMux.B && doUncachedResp, s2_uncached_data_word, 0.U) \| s2_data_word val loadgen = new LoadGen(s2_req.size, s2_req.signed, s2_req.addr, s2_data_word_possibly_uncached, s2_sc, wordBytes) io.cpu.resp.bits.data := loadgen.data \| s2_sc_fail io.cpu.resp.bits.data_word_bypass := loadgen.wordData io.cpu.resp.bits.data_raw := s2_data_word io.cpu.resp.bits.store_data := pstore1_data // AMOs if (usingRMW) { val amoalus = (0 until coreDataBits / xLen).map { i => val amoalu = Module(new AMOALU(xLen)) amoalu.io.mask := pstore1_mask >> (i * xBytes) amoalu.io.cmd := (if (usingAtomicsInCache) pstore1_cmd else M_XWR) amoalu.io.lhs := s2_data_word >> (i * xLen) amoalu.io.rhs := pstore1_data >> (i * xLen) amoalu } pstore1_storegen_data := (if (!usingDataScratchpad) amoalus.map(_.io.out).asUInt else { val mask = FillInterleaved(8, Mux(s2_correct, 0.U, pstore1_mask)) amoalus.map(_.io.out_unmasked).asUInt & mask \| s2_data_word_corrected & ~mask }) } else if (!usingAtomics) { assert(!(s1_valid_masked && s1_read && s1_write), "unsupported D$ operation") } if (coreParams.useVector) { edge.manager.managers.foreach { m => // Statically ensure that no-allocate accesses are permitted. // We could consider turning some of these into dynamic PMA checks. require(!m.supportsAcquireB \|\| m.supportsGet, "With a vector unit, cacheable memory must support Get") require(!m.supportsAcquireT \|\| m.supportsPutPartial, "With a vector unit, cacheable memory must support PutPartial") } } // flushes if (!usingDataScratchpad) when (RegNext(reset.asBool)) { resetting := true.B } val flushCounterNext = flushCounter +& 1.U val flushDone = (flushCounterNext >> log2Ceil(nSets)) === nWays.U val flushCounterWrap = flushCounterNext(log2Ceil(nSets)-1, 0) ccover(s2_valid_masked && s2_cmd_flush_all && s2_meta_error, "TAG_ECC_ERROR_DURING_FENCE_I", "D$ ECC error in tag array during cache flush") ccover(s2_valid_masked && s2_cmd_flush_all && s2_data_error, "DATA_ECC_ERROR_DURING_FENCE_I", "D$ ECC error in data array during cache flush") s1_flush_valid := metaArb.io.in(5).fire && !s1_flush_valid && !s2_flush_valid_pre_tag_ecc && release_state === s_ready && !release_ack_wait metaArb.io.in(5).valid := flushing && !flushed metaArb.io.in(5).bits.write := false.B metaArb.io.in(5).bits.idx := flushCounter(idxBits-1, 0) metaArb.io.in(5).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, metaArb.io.in(5).bits.idx << blockOffBits) metaArb.io.in(5).bits.way_en := metaArb.io.in(4).bits.way_en metaArb.io.in(5).bits.data := metaArb.io.in(4).bits.data // Only flush D$ on FENCE.I if some cached executable regions are untracked. if (supports_flush) { when (s2_valid_masked && s2_cmd_flush_all) { when (!flushed && !io.cpu.s2_kill && !release_ack_wait && !uncachedInFlight.asUInt.orR) { flushing := true.B flushing_req := s2_req } } when (tl_out_a.fire && !s2_uncached) { flushed := false.B } when (flushing) { s1_victim_way := flushCounter >> log2Up(nSets) when (s2_flush_valid) { flushCounter := flushCounterNext when (flushDone) { flushed := true.B if (!isPow2(nWays)) flushCounter := flushCounterWrap } } when (flushed && release_state === s_ready && !release_ack_wait) { flushing := false.B } } } metaArb.io.in(0).valid := resetting metaArb.io.in(0).bits := metaArb.io.in(5).bits metaArb.io.in(0).bits.write := true.B metaArb.io.in(0).bits.way_en := ~0.U(nWays.W) metaArb.io.in(0).bits.data := tECC.encode(L1Metadata(0.U, ClientMetadata.onReset).asUInt) when (resetting) { flushCounter := flushCounterNext when (flushDone) { resetting := false.B if (!isPow2(nWays)) flushCounter := flushCounterWrap } } // gate the clock clock_en_reg := !cacheParams.clockGate.B \|\| io.ptw.customCSRs.disableDCacheClockGate \|\| io.cpu.keep_clock_enabled \|\| metaArb.io.out.valid \|\| // subsumes resetting \|\| flushing s1_probe \|\| s2_probe \|\| s1_valid \|\| s2_valid \|\| io.tlb_port.req.valid \|\| s1_tlb_req_valid \|\| s2_tlb_req_valid \|\| pstore1_held \|\| pstore2_valid \|\| release_state =/= s_ready \|\| release_ack_wait \|\| !release_queue_empty \|\| !tlb.io.req.ready \|\| cached_grant_wait \|\| uncachedInFlight.asUInt.orR \|\| lrscCount > 0.U \|\| blockProbeAfterGrantCount > 0.U // performance events io.cpu.perf.acquire := edge.done(tl_out_a) io.cpu.perf.release := edge.done(tl_out_c) io.cpu.perf.grant := tl_out.d.valid && d_last io.cpu.perf.tlbMiss := io.ptw.req.fire io.cpu.perf.storeBufferEmptyAfterLoad := !( (s1_valid && s1_write) \|\| ((s2_valid && s2_write && !s2_waw_hazard) \|\| pstore1_held) \|\| pstore2_valid) io.cpu.perf.storeBufferEmptyAfterStore := !( (s1_valid && s1_write) \|\| (s2_valid && s2_write && pstore1_rmw) \|\| ((s2_valid && s2_write && !s2_waw_hazard \|\| pstore1_held) && pstore2_valid)) io.cpu.perf.canAcceptStoreThenLoad := !( ((s2_valid && s2_write && pstore1_rmw) && (s1_valid && s1_write && !s1_waw_hazard)) \|\| (pstore2_valid && pstore1_valid_likely && (s1_valid && s1_write))) io.cpu.perf.canAcceptStoreThenRMW := io.cpu.perf.canAcceptStoreThenLoad && !pstore2_valid io.cpu.perf.canAcceptLoadThenLoad := !((s1_valid && s1_write && needsRead(s1_req)) && ((s2_valid && s2_write && !s2_waw_hazard \|\| pstore1_held) \|\| pstore2_valid)) io.cpu.perf.blocked := { // stop reporting blocked just before unblocking to avoid overly conservative stalling val beatsBeforeEnd = outer.crossing match { case SynchronousCrossing(_) => 2 case RationalCrossing(_) => 1 // assumes 1 < ratio <= 2; need more bookkeeping for optimal handling of >2 case _: AsynchronousCrossing => 1 // likewise case _: CreditedCrossing => 1 // likewise } val near_end_of_refill = if (cacheBlockBytes / beatBytes <= beatsBeforeEnd) tl_out.d.valid else { val refill_count = RegInit(0.U((cacheBlockBytes / beatBytes).log2.W)) when (tl_out.d.fire && grantIsRefill) { refill_count := refill_count + 1.U } refill_count >= (cacheBlockBytes / beatBytes - beatsBeforeEnd).U } cached_grant_wait && !near_end_of_refill } // report errors val (data_error, data_error_uncorrectable, data_error_addr) = if (usingDataScratchpad) (s2_valid_data_error, s2_data_error_uncorrectable, s2_req.addr) else { (RegNext(tl_out_c.fire && inWriteback && s2_data_error), RegNext(s2_data_error_uncorrectable), probe_bits.address) // This is stable for a cycle after tl_out_c.fire, so don't need a register } { val error_addr = Mux(metaArb.io.in(1).valid, Cat(s2_first_meta_corrected.tag, metaArb.io.in(1).bits.addr(tagLSB-1, idxLSB)), data_error_addr >> idxLSB) << idxLSB io.errors.uncorrectable.foreach { u => u.valid := metaArb.io.in(1).valid && s2_meta_error_uncorrectable \|\| data_error && data_error_uncorrectable u.bits := error_addr } io.errors.correctable.foreach { c => c.valid := metaArb.io.in(1).valid \|\| data_error c.bits := error_addr io.errors.uncorrectable.foreach { u => when (u.valid) { c.valid := false.B } } } io.errors.bus.valid := tl_out.d.fire && (tl_out.d.bits.denied \|\| tl_out.d.bits.corrupt) io.errors.bus.bits := Mux(grantIsCached, s2_req.addr >> idxLSB << idxLSB, 0.U) ccoverNotScratchpad(io.errors.bus.valid && grantIsCached, "D_ERROR_CACHED", "D$ D-channel error, cached") ccover(io.errors.bus.valid && !grantIsCached, "D_ERROR_UNCACHED", "D$ D-channel error, uncached") } if (usingDataScratchpad) { val data_error_cover = Seq( property.CoverBoolean(!data_error, Seq("no_data_error")), property.CoverBoolean(data_error && !data_error_uncorrectable, Seq("data_correctable_error")), property.CoverBoolean(data_error && data_error_uncorrectable, Seq("data_uncorrectable_error"))) val request_source = Seq( property.CoverBoolean(s2_isSlavePortAccess, Seq("from_TL")), property.CoverBoolean(!s2_isSlavePortAccess, Seq("from_CPU"))) property.cover(new property.CrossProperty( Seq(data_error_cover, request_source), Seq(), "MemorySystem;;Scratchpad Memory Bit Flip Cross Covers")) } else { val data_error_type = Seq( property.CoverBoolean(!s2_valid_data_error, Seq("no_data_error")), property.CoverBoolean(s2_valid_data_error && !s2_data_error_uncorrectable, Seq("data_correctable_error")), property.CoverBoolean(s2_valid_data_error && s2_data_error_uncorrectable, Seq("data_uncorrectable_error"))) val data_error_dirty = Seq( property.CoverBoolean(!s2_victim_dirty, Seq("data_clean")), property.CoverBoolean(s2_victim_dirty, Seq("data_dirty"))) val request_source = if (supports_flush) { Seq( property.CoverBoolean(!flushing, Seq("access")), property.CoverBoolean(flushing, Seq("during_flush"))) } else { Seq(property.CoverBoolean(true.B, Seq("never_flush"))) } val tag_error_cover = Seq( property.CoverBoolean( !s2_meta_error, Seq("no_tag_error")), property.CoverBoolean( s2_meta_error && !s2_meta_error_uncorrectable, Seq("tag_correctable_error")), property.CoverBoolean( s2_meta_error && s2_meta_error_uncorrectable, Seq("tag_uncorrectable_error"))) property.cover(new property.CrossProperty( Seq(data_error_type, data_error_dirty, request_source, tag_error_cover), Seq(), "MemorySystem;;Cache Memory Bit Flip Cross Covers")) } } // leaving gated-clock domain val dcacheImpl = withClock (gated_clock) { new DCacheModuleImpl } def encodeData(x: UInt, poison: Bool) = x.grouped(eccBits).map(dECC.encode(_, if (dECC.canDetect) poison else false.B)).asUInt def dummyEncodeData(x: UInt) = x.grouped(eccBits).map(dECC.swizzle(_)).asUInt def decodeData(x: UInt) = x.grouped(dECC.width(eccBits)).map(dECC.decode(_)) def eccMask(byteMask: UInt) = byteMask.grouped(eccBytes).map(_.orR).asUInt def eccByteMask(byteMask: UInt) = FillInterleaved(eccBytes, eccMask(byteMask)) def likelyNeedsRead(req: HellaCacheReq) = { val res = !req.cmd.isOneOf(M_XWR, M_PFW) \|\| req.size < log2Ceil(eccBytes).U assert(!needsRead(req) \|\| res) res } def needsRead(req: HellaCacheReq) = isRead(req.cmd) \|\| (isWrite(req.cmd) && (req.cmd === M_PWR \|\| req.size < log2Ceil(eccBytes).U)) def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"DCACHE_$label", "MemorySystem;;" + desc) def ccoverNotScratchpad(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = if (!usingDataScratchpad) ccover(cond, label, desc) require(!usingVM \|\| tagLSB <= pgIdxBits, s"D$$ set size must not exceed ${1<<(pgIdxBits-10)} KiB; got ${(nSets * cacheBlockBytes)>>10} KiB") def tagLSB: Int = untagBits def probeIdx(b: TLBundleB): UInt = b.address(idxMSB, idxLSB) def addressToProbe(vaddr: UInt, paddr: UInt): TLBundleB = { val res = Wire(new TLBundleB(edge.bundle)) res :#= DontCare res.address := paddr res.source := (mmioOffset - 1).U res } def acquire(vaddr: UInt, paddr: UInt, param: UInt): TLBundleA = { if (!edge.manager.anySupportAcquireB) WireDefault(0.U.asTypeOf(new TLBundleA(edge.bundle))) else edge.AcquireBlock(0.U, paddr >> lgCacheBlockBytes << lgCacheBlockBytes, lgCacheBlockBytes.U, param)._2 } } File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File AMOALU.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) { val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W)) size := typ val dat_padded = dat.pad(maxSize8) def misaligned: Bool = (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR def mask = { var res = 1.U for (i <- 0 until log2Up(maxSize)) { val upper = Mux(addr(i), res, 0.U) \| Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U) val lower = Mux(addr(i), 0.U, res) res = Cat(upper, lower) } res } protected def genData(i: Int): UInt = if (i >= log2Up(maxSize)) dat_padded else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1)) def data = genData(0) def wordData = genData(2) } class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { private val size = new StoreGen(typ, addr, dat, maxSize).size private def genData(logMinSize: Int): UInt = { var res = dat for (i <- log2Up(maxSize)-1 to logMinSize by -1) { val pos = 8 << i val shifted = Mux(addr(i), res(2pos-1,pos), res(pos-1,0)) val doZero = (i == 0).B && zero val zeroed = Mux(doZero, 0.U, shifted) res = Cat(Mux(size === i.U \|\| doZero, Fill(8maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed) } res } def wordData = genData(2) def data = genData(0) } class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module { val minXLen = 32 val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _) val io = IO(new Bundle { val mask = Input(UInt((operandBits / 8).W)) val cmd = Input(UInt(M_SZ.W)) val lhs = Input(UInt(operandBits.W)) val rhs = Input(UInt(operandBits.W)) val out = Output(UInt(operandBits.W)) val out_unmasked = Output(UInt(operandBits.W)) }) val max = io.cmd === M_XA_MAX \|\| io.cmd === M_XA_MAXU val min = io.cmd === M_XA_MIN \|\| io.cmd === M_XA_MINU val add = io.cmd === M_XA_ADD val logic_and = io.cmd === M_XA_OR \|\| io.cmd === M_XA_AND val logic_xor = io.cmd === M_XA_XOR \|\| io.cmd === M_XA_OR val adder_out = { // partition the carry chain to support sub-xLen addition val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_\|_) (io.lhs & mask) + (io.rhs & mask) } val less = { // break up the comparator so the lower parts will be CSE'd def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = { if (n == minXLen) x(n-1, 0) < y(n-1, 0) else x(n-1, n/2) < y(n-1, n/2) \|\| x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2) } def isLess(x: UInt, y: UInt, n: Int): Bool = { val signed = { val mask = M_XA_MIN ^ M_XA_MINU (io.cmd & mask) === (M_XA_MIN & mask) } Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1))) } PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w)))) } val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs) val logic = Mux(logic_and, io.lhs & io.rhs, 0.U) \| Mux(logic_xor, io.lhs ^ io.rhs, 0.U) val out = Mux(add, adder_out, Mux(logic_and \|\| logic_xor, logic, minmax)) val wmask = FillInterleaved(8, io.mask) io.out := wmask & out \| ~wmask & io.lhs io.out_unmasked := out }	module DCache_1( // @[DCache.scala:101:7] input clock, // @[DCache.scala:101:7] input reset, // @[DCache.scala:101:7] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] output io_cpu_req_ready, // @[HellaCache.scala:243:14] input io_cpu_req_valid, // @[HellaCache.scala:243:14] input [39:0] io_cpu_req_bits_addr, // @[HellaCache.scala:243:14] input [6:0] io_cpu_req_bits_tag, // @[HellaCache.scala:243:14] input [4:0] io_cpu_req_bits_cmd, // @[HellaCache.scala:243:14] input [1:0] io_cpu_req_bits_size, // @[HellaCache.scala:243:14] input io_cpu_req_bits_signed, // @[HellaCache.scala:243:14] input [1:0] io_cpu_req_bits_dprv, // @[HellaCache.scala:243:14] input io_cpu_req_bits_dv, // @[HellaCache.scala:243:14] input io_cpu_req_bits_phys, // @[HellaCache.scala:243:14] input io_cpu_req_bits_no_resp, // @[HellaCache.scala:243:14] input io_cpu_s1_kill, // @[HellaCache.scala:243:14] input [63:0] io_cpu_s1_data_data, // @[HellaCache.scala:243:14] input [7:0] io_cpu_s1_data_mask, // @[HellaCache.scala:243:14] output io_cpu_s2_nack, // @[HellaCache.scala:243:14] output io_cpu_s2_nack_cause_raw, // @[HellaCache.scala:243:14] output io_cpu_s2_uncached, // @[HellaCache.scala:243:14] output [31:0] io_cpu_s2_paddr, // @[HellaCache.scala:243:14] output io_cpu_resp_valid, // @[HellaCache.scala:243:14] output [39:0] io_cpu_resp_bits_addr, // @[HellaCache.scala:243:14] output [6:0] io_cpu_resp_bits_tag, // @[HellaCache.scala:243:14] output [4:0] io_cpu_resp_bits_cmd, // @[HellaCache.scala:243:14] output [1:0] io_cpu_resp_bits_size, // @[HellaCache.scala:243:14] output io_cpu_resp_bits_signed, // @[HellaCache.scala:243:14] output [1:0] io_cpu_resp_bits_dprv, // @[HellaCache.scala:243:14] output io_cpu_resp_bits_dv, // @[HellaCache.scala:243:14] output [63:0] io_cpu_resp_bits_data, // @[HellaCache.scala:243:14] output [7:0] io_cpu_resp_bits_mask, // @[HellaCache.scala:243:14] output io_cpu_resp_bits_replay, // @[HellaCache.scala:243:14] output io_cpu_resp_bits_has_data, // @[HellaCache.scala:243:14] output [63:0] io_cpu_resp_bits_data_word_bypass, // @[HellaCache.scala:243:14] output [63:0] io_cpu_resp_bits_data_raw, // @[HellaCache.scala:243:14] output [63:0] io_cpu_resp_bits_store_data, // @[HellaCache.scala:243:14] output io_cpu_replay_next, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_ma_ld, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_ma_st, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_pf_ld, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_pf_st, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_ae_ld, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_ae_st, // @[HellaCache.scala:243:14] output [39:0] io_cpu_s2_gpa, // @[HellaCache.scala:243:14] output io_cpu_ordered, // @[HellaCache.scala:243:14] output io_cpu_store_pending, // @[HellaCache.scala:243:14] output io_cpu_perf_acquire, // @[HellaCache.scala:243:14] output io_cpu_perf_release, // @[HellaCache.scala:243:14] output io_cpu_perf_grant, // @[HellaCache.scala:243:14] output io_cpu_perf_tlbMiss, // @[HellaCache.scala:243:14] output io_cpu_perf_blocked, // @[HellaCache.scala:243:14] output io_cpu_perf_canAcceptStoreThenLoad, // @[HellaCache.scala:243:14] output io_cpu_perf_canAcceptStoreThenRMW, // @[HellaCache.scala:243:14] output io_cpu_perf_canAcceptLoadThenLoad, // @[HellaCache.scala:243:14] output io_cpu_perf_storeBufferEmptyAfterLoad, // @[HellaCache.scala:243:14] output io_cpu_perf_storeBufferEmptyAfterStore, // @[HellaCache.scala:243:14] input io_cpu_keep_clock_enabled, // @[HellaCache.scala:243:14] input io_ptw_req_ready, // @[HellaCache.scala:243:14] output io_ptw_req_valid, // @[HellaCache.scala:243:14] output [26:0] io_ptw_req_bits_bits_addr, // @[HellaCache.scala:243:14] output io_ptw_req_bits_bits_need_gpa, // @[HellaCache.scala:243:14] input io_ptw_resp_valid, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_ae_ptw, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_ae_final, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pf, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_gf, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_hr, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_hw, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_hx, // @[HellaCache.scala:243:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[HellaCache.scala:243:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[HellaCache.scala:243:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_d, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_a, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_g, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_u, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_x, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_w, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_r, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_v, // @[HellaCache.scala:243:14] input [1:0] io_ptw_resp_bits_level, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_homogeneous, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_gpa_valid, // @[HellaCache.scala:243:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_gpa_is_pte, // @[HellaCache.scala:243:14] input [3:0] io_ptw_ptbr_mode, // @[HellaCache.scala:243:14] input [43:0] io_ptw_ptbr_ppn, // @[HellaCache.scala:243:14] input io_ptw_status_debug, // @[HellaCache.scala:243:14] input io_ptw_status_cease, // @[HellaCache.scala:243:14] input io_ptw_status_wfi, // @[HellaCache.scala:243:14] input [31:0] io_ptw_status_isa, // @[HellaCache.scala:243:14] input [1:0] io_ptw_status_dprv, // @[HellaCache.scala:243:14] input io_ptw_status_dv, // @[HellaCache.scala:243:14] input [1:0] io_ptw_status_prv, // @[HellaCache.scala:243:14] input io_ptw_status_v, // @[HellaCache.scala:243:14] input io_ptw_status_sd, // @[HellaCache.scala:243:14] input io_ptw_status_mpv, // @[HellaCache.scala:243:14] input io_ptw_status_gva, // @[HellaCache.scala:243:14] input io_ptw_status_tsr, // @[HellaCache.scala:243:14] input io_ptw_status_tw, // @[HellaCache.scala:243:14] input io_ptw_status_tvm, // @[HellaCache.scala:243:14] input io_ptw_status_mxr, // @[HellaCache.scala:243:14] input io_ptw_status_sum, // @[HellaCache.scala:243:14] input io_ptw_status_mprv, // @[HellaCache.scala:243:14] input [1:0] io_ptw_status_fs, // @[HellaCache.scala:243:14] input [1:0] io_ptw_status_mpp, // @[HellaCache.scala:243:14] input io_ptw_status_spp, // @[HellaCache.scala:243:14] input io_ptw_status_mpie, // @[HellaCache.scala:243:14] input io_ptw_status_spie, // @[HellaCache.scala:243:14] input io_ptw_status_mie, // @[HellaCache.scala:243:14] input io_ptw_status_sie, // @[HellaCache.scala:243:14] input io_ptw_hstatus_spvp, // @[HellaCache.scala:243:14] input io_ptw_hstatus_spv, // @[HellaCache.scala:243:14] input io_ptw_hstatus_gva, // @[HellaCache.scala:243:14] input io_ptw_gstatus_debug, // @[HellaCache.scala:243:14] input io_ptw_gstatus_cease, // @[HellaCache.scala:243:14] input io_ptw_gstatus_wfi, // @[HellaCache.scala:243:14] input [31:0] io_ptw_gstatus_isa, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_dprv, // @[HellaCache.scala:243:14] input io_ptw_gstatus_dv, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_prv, // @[HellaCache.scala:243:14] input io_ptw_gstatus_v, // @[HellaCache.scala:243:14] input io_ptw_gstatus_sd, // @[HellaCache.scala:243:14] input [22:0] io_ptw_gstatus_zero2, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mpv, // @[HellaCache.scala:243:14] input io_ptw_gstatus_gva, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mbe, // @[HellaCache.scala:243:14] input io_ptw_gstatus_sbe, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_sxl, // @[HellaCache.scala:243:14] input [7:0] io_ptw_gstatus_zero1, // @[HellaCache.scala:243:14] input io_ptw_gstatus_tsr, // @[HellaCache.scala:243:14] input io_ptw_gstatus_tw, // @[HellaCache.scala:243:14] input io_ptw_gstatus_tvm, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mxr, // @[HellaCache.scala:243:14] input io_ptw_gstatus_sum, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mprv, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_fs, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_mpp, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_vs, // @[HellaCache.scala:243:14] input io_ptw_gstatus_spp, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mpie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_ube, // @[HellaCache.scala:243:14] input io_ptw_gstatus_spie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_upie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_hie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_sie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_uie, // @[HellaCache.scala:243:14] input io_ptw_pmp_0_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_0_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_0_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_0_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_0_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_0_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_1_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_1_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_1_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_1_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_1_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_1_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_2_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_2_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_2_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_2_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_2_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_2_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_3_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_3_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_3_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_3_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_3_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_3_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_4_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_4_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_4_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_4_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_4_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_4_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_5_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_5_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_5_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_5_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_5_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_5_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_6_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_6_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_6_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_6_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_6_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_6_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_7_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_7_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_7_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_7_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_7_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_7_mask, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_0_ren, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_0_wen, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_1_ren, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_1_wen, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_2_ren, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_2_wen, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_3_ren, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_3_wen, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_3_value // @[HellaCache.scala:243:14] ); wire [19:0] s2_meta_corrected_7_tag; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_7_coh_state; // @[DCache.scala:361:99] wire [63:0] s1_all_data_ways_7; // @[DCache.scala:325:33] wire [63:0] s1_all_data_ways_6; // @[DCache.scala:325:33] wire [63:0] s1_all_data_ways_5; // @[DCache.scala:325:33] wire [63:0] s1_all_data_ways_4; // @[DCache.scala:325:33] wire [63:0] s1_all_data_ways_3; // @[DCache.scala:325:33] wire [63:0] s1_all_data_ways_2; // @[DCache.scala:325:33] wire [63:0] s1_all_data_ways_1; // @[DCache.scala:325:33] wire [63:0] s1_all_data_ways_0; // @[DCache.scala:325:33] wire rockettile_dcache_tag_array_MPORT_en; // @[DCache.scala:310:27] wire s0_req_phys; // @[DCache.scala:192:24] wire [39:0] s0_req_addr; // @[DCache.scala:192:24] wire tl_out_a_valid; // @[DCache.scala:159:22] wire [63:0] tl_out_a_bits_data; // @[DCache.scala:159:22] wire [7:0] tl_out_a_bits_mask; // @[DCache.scala:159:22] wire [31:0] tl_out_a_bits_address; // @[DCache.scala:159:22] wire tl_out_a_bits_source; // @[DCache.scala:159:22] wire [3:0] tl_out_a_bits_size; // @[DCache.scala:159:22] wire [2:0] tl_out_a_bits_param; // @[DCache.scala:159:22] wire [2:0] tl_out_a_bits_opcode; // @[DCache.scala:159:22] wire [5:0] metaArb_io_out_bits_idx; // @[DCache.scala:135:28] wire metaArb_io_in_0_valid; // @[DCache.scala:135:28] wire [4:0] pma_checker_io_req_bits_cmd; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_req_bits_size; // @[DCache.scala:120:32] wire [175:0] _rockettile_dcache_tag_array_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire _lfsr_prng_io_out_0; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_1; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_2; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_3; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_4; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_5; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_6; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_7; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_8; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_9; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_10; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_11; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_12; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_13; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_14; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_15; // @[PRNG.scala:91:22] wire [19:0] _pma_checker_entries_barrier_12_io_y_ppn; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_hr; // @[package.scala:267:25] wire [19:0] _pma_checker_entries_barrier_11_io_y_ppn; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_c; // @[package.scala:267:25] wire [19:0] _pma_checker_entries_barrier_10_io_y_ppn; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_c; // @[package.scala:267:25] wire [19:0] _pma_checker_entries_barrier_9_io_y_ppn; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_c; // @[package.scala:267:25] wire [19:0] _pma_checker_entries_barrier_8_io_y_ppn; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_c; // @[package.scala:267:25] wire _pma_checker_pma_io_resp_r; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_w; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_pp; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_al; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_aa; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_x; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_eff; // @[TLB.scala:422:19] wire [19:0] _pma_checker_mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25] wire _tlb_io_req_ready; // @[DCache.scala:119:19] wire _tlb_io_resp_miss; // @[DCache.scala:119:19] wire [31:0] _tlb_io_resp_paddr; // @[DCache.scala:119:19] wire [39:0] _tlb_io_resp_gpa; // @[DCache.scala:119:19] wire _tlb_io_resp_pf_ld; // @[DCache.scala:119:19] wire _tlb_io_resp_pf_st; // @[DCache.scala:119:19] wire _tlb_io_resp_pf_inst; // @[DCache.scala:119:19] wire _tlb_io_resp_ae_ld; // @[DCache.scala:119:19] wire _tlb_io_resp_ae_st; // @[DCache.scala:119:19] wire _tlb_io_resp_ae_inst; // @[DCache.scala:119:19] wire _tlb_io_resp_ma_ld; // @[DCache.scala:119:19] wire _tlb_io_resp_ma_st; // @[DCache.scala:119:19] wire _tlb_io_resp_cacheable; // @[DCache.scala:119:19] wire _tlb_io_resp_must_alloc; // @[DCache.scala:119:19] wire _tlb_io_resp_prefetchable; // @[DCache.scala:119:19] wire [1:0] _tlb_io_resp_size; // @[DCache.scala:119:19] wire [4:0] _tlb_io_resp_cmd; // @[DCache.scala:119:19] wire auto_out_a_ready_0 = auto_out_a_ready; // @[DCache.scala:101:7] wire auto_out_b_valid_0 = auto_out_b_valid; // @[DCache.scala:101:7] wire [2:0] auto_out_b_bits_opcode_0 = auto_out_b_bits_opcode; // @[DCache.scala:101:7] wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[DCache.scala:101:7] wire [3:0] auto_out_b_bits_size_0 = auto_out_b_bits_size; // @[DCache.scala:101:7] wire auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[DCache.scala:101:7] wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[DCache.scala:101:7] wire [7:0] auto_out_b_bits_mask_0 = auto_out_b_bits_mask; // @[DCache.scala:101:7] wire [63:0] auto_out_b_bits_data_0 = auto_out_b_bits_data; // @[DCache.scala:101:7] wire auto_out_b_bits_corrupt_0 = auto_out_b_bits_corrupt; // @[DCache.scala:101:7] wire auto_out_c_ready_0 = auto_out_c_ready; // @[DCache.scala:101:7] wire auto_out_d_valid_0 = auto_out_d_valid; // @[DCache.scala:101:7] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[DCache.scala:101:7] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[DCache.scala:101:7] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[DCache.scala:101:7] wire auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[DCache.scala:101:7] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[DCache.scala:101:7] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[DCache.scala:101:7] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[DCache.scala:101:7] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[DCache.scala:101:7] wire auto_out_e_ready_0 = auto_out_e_ready; // @[DCache.scala:101:7] wire io_cpu_req_valid_0 = io_cpu_req_valid; // @[DCache.scala:101:7] wire [39:0] io_cpu_req_bits_addr_0 = io_cpu_req_bits_addr; // @[DCache.scala:101:7] wire [6:0] io_cpu_req_bits_tag_0 = io_cpu_req_bits_tag; // @[DCache.scala:101:7] wire [4:0] io_cpu_req_bits_cmd_0 = io_cpu_req_bits_cmd; // @[DCache.scala:101:7] wire [1:0] io_cpu_req_bits_size_0 = io_cpu_req_bits_size; // @[DCache.scala:101:7] wire io_cpu_req_bits_signed_0 = io_cpu_req_bits_signed; // @[DCache.scala:101:7] wire [1:0] io_cpu_req_bits_dprv_0 = io_cpu_req_bits_dprv; // @[DCache.scala:101:7] wire io_cpu_req_bits_dv_0 = io_cpu_req_bits_dv; // @[DCache.scala:101:7] wire io_cpu_req_bits_phys_0 = io_cpu_req_bits_phys; // @[DCache.scala:101:7] wire io_cpu_req_bits_no_resp_0 = io_cpu_req_bits_no_resp; // @[DCache.scala:101:7] wire io_cpu_s1_kill_0 = io_cpu_s1_kill; // @[DCache.scala:101:7] wire [63:0] io_cpu_s1_data_data_0 = io_cpu_s1_data_data; // @[DCache.scala:101:7] wire [7:0] io_cpu_s1_data_mask_0 = io_cpu_s1_data_mask; // @[DCache.scala:101:7] wire io_cpu_keep_clock_enabled_0 = io_cpu_keep_clock_enabled; // @[DCache.scala:101:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[DCache.scala:101:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[DCache.scala:101:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[DCache.scala:101:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[DCache.scala:101:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[DCache.scala:101:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[DCache.scala:101:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[DCache.scala:101:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[DCache.scala:101:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[DCache.scala:101:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[DCache.scala:101:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[DCache.scala:101:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[DCache.scala:101:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[DCache.scala:101:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[DCache.scala:101:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[DCache.scala:101:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[DCache.scala:101:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[DCache.scala:101:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[DCache.scala:101:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[DCache.scala:101:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[DCache.scala:101:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[DCache.scala:101:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[DCache.scala:101:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[DCache.scala:101:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[DCache.scala:101:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[DCache.scala:101:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[DCache.scala:101:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[DCache.scala:101:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[DCache.scala:101:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[DCache.scala:101:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[DCache.scala:101:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[DCache.scala:101:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[DCache.scala:101:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[DCache.scala:101:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[DCache.scala:101:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[DCache.scala:101:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[DCache.scala:101:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[DCache.scala:101:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[DCache.scala:101:7] wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[DCache.scala:101:7] wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[DCache.scala:101:7] wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[DCache.scala:101:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[DCache.scala:101:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[DCache.scala:101:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[DCache.scala:101:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[DCache.scala:101:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[DCache.scala:101:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[DCache.scala:101:7] wire io_ptw_gstatus_sd_0 = io_ptw_gstatus_sd; // @[DCache.scala:101:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[DCache.scala:101:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[DCache.scala:101:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[DCache.scala:101:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[DCache.scala:101:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[DCache.scala:101:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[DCache.scala:101:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[DCache.scala:101:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[DCache.scala:101:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[DCache.scala:101:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[DCache.scala:101:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[DCache.scala:101:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[DCache.scala:101:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[DCache.scala:101:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[DCache.scala:101:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[DCache.scala:101:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[DCache.scala:101:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[DCache.scala:101:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[DCache.scala:101:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[DCache.scala:101:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[DCache.scala:101:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[DCache.scala:101:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[DCache.scala:101:7] wire _dataArb_io_in_3_valid_T_55 = reset; // @[DCache.scala:1186:11] wire _pstore_drain_opportunistic_T_55 = reset; // @[DCache.scala:1186:11] wire auto_out_a_bits_corrupt = 1'h0; // @[DCache.scala:101:7] wire auto_out_c_bits_corrupt = 1'h0; // @[DCache.scala:101:7] wire io_cpu_req_bits_no_alloc = 1'h0; // @[DCache.scala:101:7] wire io_cpu_req_bits_no_xcpt = 1'h0; // @[DCache.scala:101:7] wire io_cpu_s2_kill = 1'h0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_gf_ld = 1'h0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_gf_st = 1'h0; // @[DCache.scala:101:7] wire io_cpu_s2_gpa_is_pte = 1'h0; // @[DCache.scala:101:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[DCache.scala:101:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[DCache.scala:101:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_mbe = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_sbe = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_ube = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_upie = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_hie = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_uie = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_vtw = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_hu = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[DCache.scala:101:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_req_valid = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_req_bits_passthrough = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_req_bits_v = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_gpa_is_pte = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_gf_ld = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_gf_st = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_gf_inst = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ma_inst = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s2_kill = 1'h0; // @[DCache.scala:101:7] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire pma_checker_io_req_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_miss = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_gpa_is_pte = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_gf_ld = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_gf_st = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_gf_inst = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_ma_inst = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_rs1 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_rs2 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_asid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_hv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_hg = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_ready = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_bits_bits_need_gpa = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_bits_bits_vstage1 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_bits_bits_stage2 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_ae_ptw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_ae_final = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pf = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_gf = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_hr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_hw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_hx = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_d = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_a = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_g = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_u = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_v = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_homogeneous = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_gpa_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_gpa_is_pte = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_debug = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_cease = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_wfi = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_dv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_v = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sd = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mpv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_gva = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sd_rv32 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_tsr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_tw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_tvm = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mxr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sum = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mprv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_spp = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mpie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_ube = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_spie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_upie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_hie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_uie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_vtsr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_vtw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_vtvm = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_hu = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_spvp = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_spv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_gva = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_vsbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_debug = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_cease = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_wfi = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_dv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_v = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sd = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mpv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_gva = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sd_rv32 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_tsr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_tw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_tvm = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mxr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sum = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mprv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_spp = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mpie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_ube = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_spie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_upie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_hie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_uie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_0_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_0_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_0_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_0_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_1_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_1_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_1_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_1_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_2_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_2_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_2_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_2_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_3_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_3_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_3_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_3_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_4_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_4_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_4_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_4_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_5_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_5_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_5_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_5_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_6_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_6_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_6_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_6_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_7_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_7_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_7_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_7_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_0_set = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_1_set = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_2_ren = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_2_wen = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_2_set = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_3_ren = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_3_wen = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_3_set = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_kill = 1'h0; // @[DCache.scala:120:32] wire pma_checker_priv_v = 1'h0; // @[TLB.scala:369:34] wire pma_checker__stage1_en_T = 1'h0; // @[TLB.scala:374:41] wire pma_checker_stage1_en = 1'h0; // @[TLB.scala:374:29] wire pma_checker__vstage1_en_T = 1'h0; // @[TLB.scala:376:38] wire pma_checker__vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68] wire pma_checker_vstage1_en = 1'h0; // @[TLB.scala:376:48] wire pma_checker__stage2_en_T = 1'h0; // @[TLB.scala:378:38] wire pma_checker__stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68] wire pma_checker_stage2_en = 1'h0; // @[TLB.scala:378:48] wire pma_checker__vm_enabled_T = 1'h0; // @[TLB.scala:399:31] wire pma_checker__vm_enabled_T_1 = 1'h0; // @[TLB.scala:399:45] wire pma_checker__vm_enabled_T_2 = 1'h0; // @[TLB.scala:399:64] wire pma_checker_vm_enabled = 1'h0; // @[TLB.scala:399:61] wire pma_checker__vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52] wire pma_checker__vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37] wire pma_checker__vsatp_mode_mismatch_T_2 = 1'h0; // @[TLB.scala:403:81] wire pma_checker_vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78] wire pma_checker_do_refill = 1'h0; // @[TLB.scala:408:29] wire pma_checker__invalidate_refill_T = 1'h0; // @[package.scala:16:47] wire pma_checker__invalidate_refill_T_1 = 1'h0; // @[package.scala:16:47] wire pma_checker__invalidate_refill_T_2 = 1'h0; // @[package.scala:81:59] wire pma_checker_invalidate_refill = 1'h0; // @[TLB.scala:410:88] wire pma_checker__mpu_ppn_T = 1'h0; // @[TLB.scala:413:32] wire pma_checker_prot_r = 1'h0; // @[TLB.scala:429:55] wire pma_checker_prot_w = 1'h0; // @[TLB.scala:430:55] wire pma_checker_prot_x = 1'h0; // @[TLB.scala:434:55] wire pma_checker__sector_hits_T = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_1 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_2 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_0 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_8 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_9 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_10 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_1 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_16 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_17 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_18 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_2 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_24 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_25 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_26 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_3 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_32 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_33 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_34 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_4 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_40 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_41 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_42 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_5 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_48 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_49 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_50 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_6 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_56 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_57 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_58 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_7 = 1'h0; // @[TLB.scala:172:55] wire pma_checker_superpage_hits_tagMatch = 1'h0; // @[TLB.scala:178:33] wire pma_checker__superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_4 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__superpage_hits_T_9 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_0 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_tagMatch_1 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__superpage_hits_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_18 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__superpage_hits_T_23 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_1 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_tagMatch_2 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__superpage_hits_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_32 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__superpage_hits_T_37 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_2 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_tagMatch_3 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__superpage_hits_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_46 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__superpage_hits_T_51 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_3 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_5 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_0 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_11 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_1 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_17 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_2 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_23 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_3 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_29 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_4 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_35 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_5 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_41 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_6 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_47 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_7 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_hitsVec_tagMatch = 1'h0; // @[TLB.scala:178:33] wire pma_checker__hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore = 1'h0; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_52 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_57 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_62 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_hitsVec_8 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_hitsVec_tagMatch_1 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_67 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_72 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_77 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_hitsVec_9 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_hitsVec_tagMatch_2 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__hitsVec_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_82 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_87 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_92 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_hitsVec_10 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_hitsVec_tagMatch_3 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__hitsVec_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_97 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_102 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_107 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_hitsVec_11 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_hitsVec_tagMatch_4 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__hitsVec_ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_12 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_112 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_117 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_122 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_hitsVec_12 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_refill_v = 1'h0; // @[TLB.scala:448:33] wire pma_checker_newEntry_u = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_g = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_ae_ptw = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_ae_final = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_pf = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_gf = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_sw = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_sx = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_sr = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_hw = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_hx = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_hr = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_pw = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_px = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_pr = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24] wire pma_checker__newEntry_g_T = 1'h0; // @[TLB.scala:453:25] wire pma_checker__newEntry_ae_stage2_T = 1'h0; // @[TLB.scala:456:53] wire pma_checker__newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84] wire pma_checker__newEntry_sr_T_1 = 1'h0; // @[PTW.scala:141:44] wire pma_checker__newEntry_sr_T_2 = 1'h0; // @[PTW.scala:141:38] wire pma_checker__newEntry_sr_T_3 = 1'h0; // @[PTW.scala:141:32] wire pma_checker__newEntry_sr_T_4 = 1'h0; // @[PTW.scala:141:52] wire pma_checker__newEntry_sr_T_5 = 1'h0; // @[PTW.scala:149:35] wire pma_checker__newEntry_sw_T_1 = 1'h0; // @[PTW.scala:141:44] wire pma_checker__newEntry_sw_T_2 = 1'h0; // @[PTW.scala:141:38] wire pma_checker__newEntry_sw_T_3 = 1'h0; // @[PTW.scala:141:32] wire pma_checker__newEntry_sw_T_4 = 1'h0; // @[PTW.scala:141:52] wire pma_checker__newEntry_sw_T_5 = 1'h0; // @[PTW.scala:151:35] wire pma_checker__newEntry_sw_T_6 = 1'h0; // @[PTW.scala:151:40] wire pma_checker__newEntry_sx_T_1 = 1'h0; // @[PTW.scala:141:44] wire pma_checker__newEntry_sx_T_2 = 1'h0; // @[PTW.scala:141:38] wire pma_checker__newEntry_sx_T_3 = 1'h0; // @[PTW.scala:141:32] wire pma_checker__newEntry_sx_T_4 = 1'h0; // @[PTW.scala:141:52] wire pma_checker__newEntry_sx_T_5 = 1'h0; // @[PTW.scala:153:35] wire pma_checker__waddr_T = 1'h0; // @[TLB.scala:477:45] wire pma_checker__superpage_entries_0_level_T = 1'h0; // @[package.scala:163:13] wire pma_checker__superpage_entries_1_level_T = 1'h0; // @[package.scala:163:13] wire pma_checker__superpage_entries_2_level_T = 1'h0; // @[package.scala:163:13] wire pma_checker__superpage_entries_3_level_T = 1'h0; // @[package.scala:163:13] wire pma_checker_sum = 1'h0; // @[TLB.scala:510:16] wire pma_checker__mxr_T = 1'h0; // @[TLB.scala:518:36] wire pma_checker_mxr = 1'h0; // @[TLB.scala:518:31] wire pma_checker__bad_va_T = 1'h0; // @[TLB.scala:568:21] wire pma_checker_bad_va = 1'h0; // @[TLB.scala:568:34] wire pma_checker_cmd_readx = 1'h0; // @[TLB.scala:575:37] wire pma_checker__gf_ld_array_T = 1'h0; // @[TLB.scala:600:32] wire pma_checker__gf_st_array_T = 1'h0; // @[TLB.scala:601:32] wire pma_checker__gpa_hits_hit_mask_T_1 = 1'h0; // @[TLB.scala:606:60] wire pma_checker_tlb_hit_if_not_gpa_miss = 1'h0; // @[TLB.scala:610:43] wire pma_checker_tlb_hit = 1'h0; // @[TLB.scala:611:40] wire pma_checker__tlb_miss_T_1 = 1'h0; // @[TLB.scala:613:29] wire pma_checker__tlb_miss_T_3 = 1'h0; // @[TLB.scala:613:53] wire pma_checker_tlb_miss = 1'h0; // @[TLB.scala:613:64] wire pma_checker__state_vec_0_set_left_older_T = 1'h0; // @[Replacement.scala:196:43] wire pma_checker__state_vec_0_set_left_older_T_1 = 1'h0; // @[Replacement.scala:196:43] wire pma_checker_state_vec_0_left_subtree_state_1 = 1'h0; // @[package.scala:163:13] wire pma_checker_state_vec_0_right_subtree_state_1 = 1'h0; // @[Replacement.scala:198:38] wire pma_checker__state_vec_0_T_1 = 1'h0; // @[package.scala:163:13] wire pma_checker__state_vec_0_T_2 = 1'h0; // @[Replacement.scala:218:17] wire pma_checker__state_vec_0_T_4 = 1'h0; // @[Replacement.scala:203:16] wire pma_checker__state_vec_0_T_5 = 1'h0; // @[Replacement.scala:207:62] wire pma_checker__state_vec_0_T_6 = 1'h0; // @[Replacement.scala:218:17] wire pma_checker__state_vec_0_set_left_older_T_2 = 1'h0; // @[Replacement.scala:196:43] wire pma_checker_state_vec_0_left_subtree_state_2 = 1'h0; // @[package.scala:163:13] wire pma_checker_state_vec_0_right_subtree_state_2 = 1'h0; // @[Replacement.scala:198:38] wire pma_checker__state_vec_0_T_12 = 1'h0; // @[package.scala:163:13] wire pma_checker__state_vec_0_T_13 = 1'h0; // @[Replacement.scala:218:17] wire pma_checker__state_vec_0_T_15 = 1'h0; // @[Replacement.scala:203:16] wire pma_checker__state_vec_0_T_16 = 1'h0; // @[Replacement.scala:207:62] wire pma_checker__state_vec_0_T_17 = 1'h0; // @[Replacement.scala:218:17] wire pma_checker__state_reg_set_left_older_T = 1'h0; // @[Replacement.scala:196:43] wire pma_checker_state_reg_left_subtree_state = 1'h0; // @[package.scala:163:13] wire pma_checker_state_reg_right_subtree_state = 1'h0; // @[Replacement.scala:198:38] wire pma_checker__state_reg_T = 1'h0; // @[package.scala:163:13] wire pma_checker__state_reg_T_1 = 1'h0; // @[Replacement.scala:218:17] wire pma_checker__state_reg_T_3 = 1'h0; // @[Replacement.scala:203:16] wire pma_checker__state_reg_T_4 = 1'h0; // @[Replacement.scala:207:62] wire pma_checker__state_reg_T_5 = 1'h0; // @[Replacement.scala:218:17] wire pma_checker__multipleHits_T_2 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_4 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_1 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_5 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_rightOne_1 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_7 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_leftOne_2 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_8 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_9 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_leftTwo = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_11 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_3 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_13 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_4 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_14 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne_2 = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_rightOne_3 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_16 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_1 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_rightOne_4 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_17 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_18 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_2 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_leftOne_5 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_19 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_20 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_leftTwo_1 = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_23 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_6 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_25 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_7 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_26 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne_5 = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_rightOne_6 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_28 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_3 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_leftOne_8 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_29 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_30 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_leftTwo_2 = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_33 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_9 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_34 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne_7 = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_leftOne_10 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_36 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_leftTwo_3 = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_38 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_11 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_39 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne_8 = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_rightOne_9 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_41 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_4 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_rightOne_10 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_42 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_43 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_5 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_rightOne_11 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_44 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_45 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_6 = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_46 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_47 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_48 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits = 1'h0; // @[Misc.scala:183:49] wire pma_checker__io_resp_pf_ld_T = 1'h0; // @[TLB.scala:633:28] wire pma_checker__io_resp_pf_st_T = 1'h0; // @[TLB.scala:634:28] wire pma_checker__io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29] wire pma_checker__io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66] wire pma_checker__io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42] wire pma_checker__io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29] wire pma_checker__io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73] wire pma_checker__io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49] wire pma_checker__io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56] wire pma_checker__io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30] wire pma_checker__io_resp_miss_T = 1'h0; // @[TLB.scala:651:29] wire pma_checker__io_resp_miss_T_1 = 1'h0; // @[TLB.scala:651:52] wire pma_checker__io_resp_miss_T_2 = 1'h0; // @[TLB.scala:651:64] wire pma_checker__io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36] wire pma_checker__io_ptw_req_valid_T = 1'h0; // @[TLB.scala:662:29] wire pma_checker_r_superpage_repl_addr_left_subtree_older = 1'h0; // @[Replacement.scala:243:38] wire pma_checker_r_superpage_repl_addr_left_subtree_state = 1'h0; // @[package.scala:163:13] wire pma_checker_r_superpage_repl_addr_right_subtree_state = 1'h0; // @[Replacement.scala:245:38] wire pma_checker__r_superpage_repl_addr_T = 1'h0; // @[Replacement.scala:262:12] wire pma_checker__r_superpage_repl_addr_T_1 = 1'h0; // @[Replacement.scala:262:12] wire pma_checker__r_superpage_repl_addr_T_2 = 1'h0; // @[Replacement.scala:250:16] wire pma_checker__r_superpage_repl_addr_T_4 = 1'h0; // @[TLB.scala:757:16] wire pma_checker_r_sectored_repl_addr_left_subtree_older = 1'h0; // @[Replacement.scala:243:38] wire pma_checker_r_sectored_repl_addr_left_subtree_older_1 = 1'h0; // @[Replacement.scala:243:38] wire pma_checker_r_sectored_repl_addr_left_subtree_state_1 = 1'h0; // @[package.scala:163:13] wire pma_checker_r_sectored_repl_addr_right_subtree_state_1 = 1'h0; // @[Replacement.scala:245:38] wire pma_checker__r_sectored_repl_addr_T = 1'h0; // @[Replacement.scala:262:12] wire pma_checker__r_sectored_repl_addr_T_1 = 1'h0; // @[Replacement.scala:262:12] wire pma_checker__r_sectored_repl_addr_T_2 = 1'h0; // @[Replacement.scala:250:16] wire pma_checker_r_sectored_repl_addr_left_subtree_older_2 = 1'h0; // @[Replacement.scala:243:38] wire pma_checker_r_sectored_repl_addr_left_subtree_state_2 = 1'h0; // @[package.scala:163:13] wire pma_checker_r_sectored_repl_addr_right_subtree_state_2 = 1'h0; // @[Replacement.scala:245:38] wire pma_checker__r_sectored_repl_addr_T_4 = 1'h0; // @[Replacement.scala:262:12] wire pma_checker__r_sectored_repl_addr_T_5 = 1'h0; // @[Replacement.scala:262:12] wire pma_checker__r_sectored_repl_addr_T_6 = 1'h0; // @[Replacement.scala:250:16] wire pma_checker__r_sectored_repl_addr_valids_T = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_1 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_2 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_3 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_4 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_5 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_6 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_7 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_8 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_9 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_10 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_11 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_12 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_13 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_14 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_15 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_16 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_17 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_18 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_19 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_20 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_21 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_22 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_23 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_T_10 = 1'h0; // @[TLB.scala:757:16] wire pma_checker__r_sectored_hit_valid_T = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_valid_T_1 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_valid_T_2 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_valid_T_3 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_valid_T_4 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_valid_T_5 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_valid_T_6 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_bits_T_1 = 1'h0; // @[OneHot.scala:32:14] wire pma_checker__r_sectored_hit_bits_T_3 = 1'h0; // @[OneHot.scala:32:14] wire pma_checker__r_sectored_hit_bits_T_5 = 1'h0; // @[CircuitMath.scala:28:8] wire pma_checker__r_superpage_hit_valid_T = 1'h0; // @[package.scala:81:59] wire pma_checker__r_superpage_hit_valid_T_1 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_superpage_hit_valid_T_2 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_superpage_hit_bits_T_1 = 1'h0; // @[OneHot.scala:32:14] wire pma_checker__r_superpage_hit_bits_T_3 = 1'h0; // @[CircuitMath.scala:28:8] wire pma_checker_hv = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_1 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_1 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_2 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_2 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_3 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_3 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_4 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_4 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_5 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_5 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_6 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_6 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_7 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_7 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_8 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_8 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_tagMatch = 1'h0; // @[TLB.scala:178:33] wire pma_checker__ignore_T = 1'h0; // @[TLB.scala:182:28] wire pma_checker_ignore = 1'h0; // @[TLB.scala:182:34] wire pma_checker_hv_9 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_9 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_tagMatch_1 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire pma_checker_hv_10 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_10 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_tagMatch_2 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire pma_checker_hv_11 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_11 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_tagMatch_3 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire pma_checker_hv_12 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_12 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_tagMatch_4 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_ignore_12 = 1'h0; // @[TLB.scala:182:34] wire metaArb_io_in_1_valid = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_5_valid = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_5_bits_write = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_6_bits_write = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_7_bits_write = 1'h0; // @[DCache.scala:135:28] wire dataArb_io_in_2_bits_write = 1'h0; // @[DCache.scala:152:28] wire dataArb_io_in_3_bits_write = 1'h0; // @[DCache.scala:152:28] wire tl_out_a_bits_corrupt = 1'h0; // @[DCache.scala:159:22] wire nodeOut_a_deq_bits_corrupt = 1'h0; // @[Decoupled.scala:356:21] wire _s1_tlb_req_valid_T = 1'h0; // @[Decoupled.scala:51:35] wire s0_req_no_alloc = 1'h0; // @[DCache.scala:192:24] wire s0_req_no_xcpt = 1'h0; // @[DCache.scala:192:24] wire s1_waw_hazard = 1'h0; // @[DCache.scala:216:27] wire _uncachedInFlight_WIRE_0 = 1'h0; // @[DCache.scala:236:41] wire _dataArb_io_in_3_valid_res_T_4 = 1'h0; // @[DCache.scala:1185:58] wire _dataArb_io_in_3_valid_T_49 = 1'h0; // @[DCache.scala:1191:57] wire _s1_did_read_T_49 = 1'h0; // @[DCache.scala:1191:57] wire _tlb_io_kill_T = 1'h0; // @[DCache.scala:272:53] wire _tlb_io_kill_T_1 = 1'h0; // @[DCache.scala:272:33] wire _s2_pma_T_gpa_is_pte = 1'h0; // @[DCache.scala:349:18] wire _s2_pma_T_gf_ld = 1'h0; // @[DCache.scala:349:18] wire _s2_pma_T_gf_st = 1'h0; // @[DCache.scala:349:18] wire _s2_pma_T_gf_inst = 1'h0; // @[DCache.scala:349:18] wire _s2_pma_T_ma_inst = 1'h0; // @[DCache.scala:349:18] wire s2_meta_error_uncorrectable = 1'h0; // @[DCache.scala:360:66] wire s2_meta_error = 1'h0; // @[DCache.scala:362:83] wire s2_store_merge = 1'h0; // @[DCache.scala:388:28] wire _r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _s2_data_error_T = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_1 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_2 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_3 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_4 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_5 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_6 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_7 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_8 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_9 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_10 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_11 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_12 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_13 = 1'h0; // @[package.scala:81:59] wire s2_data_error = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_1 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_2 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_3 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_4 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_5 = 1'h0; // @[package.scala:81:59] wire s2_data_error_uncorrectable = 1'h0; // @[package.scala:81:59] wire s2_valid_data_error = 1'h0; // @[DCache.scala:421:63] wire s2_cannot_victimize = 1'h0; // @[DCache.scala:428:45] wire _r_T_73 = 1'h0; // @[Misc.scala:38:9] wire _r_T_77 = 1'h0; // @[Misc.scala:38:9] wire _r_T_81 = 1'h0; // @[Misc.scala:38:9] wire _r_T_119 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_121 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_137 = 1'h0; // @[Misc.scala:38:9] wire _r_T_141 = 1'h0; // @[Misc.scala:38:9] wire _r_T_145 = 1'h0; // @[Misc.scala:38:9] wire _s2_dont_nack_misc_T_2 = 1'h0; // @[DCache.scala:442:23] wire _s2_dont_nack_misc_T_3 = 1'h0; // @[DCache.scala:442:43] wire _s2_dont_nack_misc_T_5 = 1'h0; // @[DCache.scala:442:54] wire _s2_dont_nack_misc_T_6 = 1'h0; // @[DCache.scala:443:23] wire _s2_dont_nack_misc_T_8 = 1'h0; // @[DCache.scala:443:44] wire _s2_dont_nack_misc_T_9 = 1'h0; // @[DCache.scala:442:67] wire _s2_first_meta_corrected_T = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_1 = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_2 = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_3 = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_4 = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_5 = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_6 = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_7 = 1'h0; // @[Mux.scala:52:83] wire _metaArb_io_in_1_valid_T_2 = 1'h0; // @[DCache.scala:450:43] wire _metaArb_io_in_1_bits_way_en_T = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_1 = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_2 = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_3 = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_4 = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_5 = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_6 = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_7 = 1'h0; // @[OneHot.scala:85:71] wire _s2_correct_T_1 = 1'h0; // @[DCache.scala:487:34] wire _s2_correct_T_4 = 1'h0; // @[DCache.scala:487:55] wire s2_correct = 1'h0; // @[DCache.scala:487:97] wire _s2_valid_correct_T = 1'h0; // @[DCache.scala:489:60] wire s2_valid_correct = 1'h0; // @[DCache.scala:489:74] wire _pstore1_rmw_T_49 = 1'h0; // @[DCache.scala:1191:57] wire pstore1_merge_likely = 1'h0; // @[DCache.scala:499:68] wire pstore1_merge = 1'h0; // @[DCache.scala:500:38] wire _pstore_drain_opportunistic_res_T_4 = 1'h0; // @[DCache.scala:1185:58] wire _pstore_drain_opportunistic_T_49 = 1'h0; // @[DCache.scala:1191:57] wire _pstore_drain_opportunistic_T_60 = 1'h0; // @[DCache.scala:502:106] wire pstore_drain_s2_kill = 1'h0; // @[DCache.scala:515:25] wire _pstore2_storegen_data_T_2 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_6 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_10 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_14 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_18 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_22 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_26 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_30 = 1'h0; // @[DCache.scala:528:95] wire dataArb_io_in_0_valid_s2_kill = 1'h0; // @[DCache.scala:515:25] wire _dataArb_io_in_0_bits_wordMask_T_1 = 1'h0; // @[DCache.scala:555:20] wire _io_cpu_s2_nack_cause_raw_T_2 = 1'h0; // @[DCache.scala:574:57] wire get_corrupt = 1'h0; // @[Edges.scala:460:17] wire _put_legal_T_62 = 1'h0; // @[Parameters.scala:684:29] wire _put_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire put_corrupt = 1'h0; // @[Edges.scala:480:17] wire _putpartial_legal_T_62 = 1'h0; // @[Parameters.scala:684:29] wire _putpartial_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire putpartial_corrupt = 1'h0; // @[Edges.scala:500:17] wire _atomics_WIRE_source = 1'h0; // @[DCache.scala:587:51] wire _atomics_WIRE_corrupt = 1'h0; // @[DCache.scala:587:51] wire _atomics_WIRE_1_source = 1'h0; // @[DCache.scala:587:38] wire _atomics_WIRE_1_corrupt = 1'h0; // @[DCache.scala:587:38] wire _atomics_legal_T_46 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_52 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_corrupt = 1'h0; // @[Edges.scala:534:17] wire _atomics_legal_T_100 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_106 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_1_corrupt = 1'h0; // @[Edges.scala:534:17] wire _atomics_legal_T_154 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_160 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_2_corrupt = 1'h0; // @[Edges.scala:534:17] wire _atomics_legal_T_208 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_214 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_3_corrupt = 1'h0; // @[Edges.scala:534:17] wire _atomics_legal_T_262 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_268 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_4_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_legal_T_316 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_322 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_5_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_legal_T_370 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_376 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_6_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_legal_T_424 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_430 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_7_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_legal_T_478 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_484 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_8_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_T_1_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_3_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_5_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_7_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_9_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_11_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_13_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_15_corrupt = 1'h0; // @[DCache.scala:587:81] wire atomics_corrupt = 1'h0; // @[DCache.scala:587:81] wire _tl_out_a_valid_T_8 = 1'h0; // @[DCache.scala:607:44] wire _tl_out_a_valid_T_9 = 1'h0; // @[DCache.scala:607:65] wire _tl_out_a_bits_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _tl_out_a_bits_legal_T_18 = 1'h0; // @[Parameters.scala:684:54] wire _tl_out_a_bits_legal_T_33 = 1'h0; // @[Parameters.scala:686:26] wire tl_out_a_bits_a_source = 1'h0; // @[Edges.scala:346:17] wire tl_out_a_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17] wire tl_out_a_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _tl_out_a_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_T_6_corrupt = 1'h0; // @[DCache.scala:611:8] wire _tl_out_a_bits_T_7_corrupt = 1'h0; // @[DCache.scala:610:8] wire _tl_out_a_bits_T_8_corrupt = 1'h0; // @[DCache.scala:609:8] wire _tl_out_a_bits_T_9_corrupt = 1'h0; // @[DCache.scala:608:23] wire nackResponseMessage_corrupt = 1'h0; // @[Edges.scala:416:17] wire cleanReleaseMessage_corrupt = 1'h0; // @[Edges.scala:416:17] wire dirtyReleaseMessage_corrupt = 1'h0; // @[Edges.scala:433:17] wire _nodeOut_c_valid_T = 1'h0; // @[DCache.scala:810:48] wire _nodeOut_c_valid_T_2 = 1'h0; // @[DCache.scala:810:74] wire _discard_line_T_2 = 1'h0; // @[DCache.scala:818:102] wire _release_state_T_2 = 1'h0; // @[DCache.scala:820:28] wire _release_state_T_4 = 1'h0; // @[DCache.scala:820:54] wire _release_state_T_5 = 1'h0; // @[DCache.scala:820:75] wire _release_state_T_7 = 1'h0; // @[DCache.scala:820:98] wire _release_state_T_12 = 1'h0; // @[DCache.scala:820:127] wire probe_bits_res_source = 1'h0; // @[DCache.scala:1202:19] wire probe_bits_res_corrupt = 1'h0; // @[DCache.scala:1202:19] wire _nodeOut_c_bits_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _nodeOut_c_bits_legal_T_1 = 1'h0; // @[Parameters.scala:137:31] wire _nodeOut_c_bits_legal_T_10 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_15 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_18 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_c_bits_legal_T_25 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_30 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_31 = 1'h0; // @[Parameters.scala:685:42] wire _nodeOut_c_bits_legal_T_32 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_c_bits_legal_T_33 = 1'h0; // @[Parameters.scala:686:26] wire nodeOut_c_bits_legal = 1'h0; // @[Parameters.scala:686:26] wire nodeOut_c_bits_c_source = 1'h0; // @[Edges.scala:380:17] wire nodeOut_c_bits_c_corrupt = 1'h0; // @[Edges.scala:380:17] wire _nodeOut_c_bits_legal_T_34 = 1'h0; // @[Parameters.scala:684:29] wire _nodeOut_c_bits_legal_T_35 = 1'h0; // @[Parameters.scala:137:31] wire _nodeOut_c_bits_legal_T_44 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_49 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_52 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_c_bits_legal_T_59 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_64 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_65 = 1'h0; // @[Parameters.scala:685:42] wire _nodeOut_c_bits_legal_T_66 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_c_bits_legal_T_67 = 1'h0; // @[Parameters.scala:686:26] wire nodeOut_c_bits_legal_1 = 1'h0; // @[Parameters.scala:686:26] wire nodeOut_c_bits_c_1_source = 1'h0; // @[Edges.scala:396:17] wire nodeOut_c_bits_c_1_corrupt = 1'h0; // @[Edges.scala:396:17] wire _nodeOut_c_bits_corrupt_T = 1'h0; // @[DCache.scala:887:42] wire _io_cpu_s2_xcpt_WIRE_miss = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_gpa_is_pte = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_pf_ld = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_pf_st = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_pf_inst = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_gf_ld = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_gf_st = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_gf_inst = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ae_ld = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ae_st = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ae_inst = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ma_ld = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ma_st = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ma_inst = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_cacheable = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_must_alloc = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_prefetchable = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_T_gpa_is_pte = 1'h0; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_gf_ld = 1'h0; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_gf_st = 1'h0; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_gf_inst = 1'h0; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_ma_inst = 1'h0; // @[DCache.scala:933:24] wire _s2_data_word_possibly_uncached_T = 1'h0; // @[DCache.scala:972:73] wire io_cpu_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_cpu_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_cpu_resp_bits_data_word_bypass_doZero = 1'h0; // @[AMOALU.scala:43:31] wire _s1_flush_valid_T = 1'h0; // @[Decoupled.scala:51:35] wire _s1_flush_valid_T_2 = 1'h0; // @[DCache.scala:1014:43] wire _s1_flush_valid_T_4 = 1'h0; // @[DCache.scala:1014:62] wire _s1_flush_valid_T_6 = 1'h0; // @[DCache.scala:1014:93] wire _s1_flush_valid_T_8 = 1'h0; // @[DCache.scala:1014:122] wire _metaArb_io_in_5_valid_T = 1'h0; // @[DCache.scala:1015:41] wire _metaArb_io_in_5_valid_T_1 = 1'h0; // @[DCache.scala:1015:38] wire _clock_en_reg_T_17 = 1'h0; // @[DCache.scala:1070:25] wire _io_cpu_perf_canAcceptLoadThenLoad_T_50 = 1'h0; // @[DCache.scala:1191:57] wire io_cpu_clock_enabled = 1'h1; // @[DCache.scala:101:7] wire io_ptw_req_bits_valid = 1'h1; // @[DCache.scala:101:7] wire io_tlb_port_req_ready = 1'h1; // @[DCache.scala:101:7] wire pma_checker_io_req_ready = 1'h1; // @[DCache.scala:120:32] wire pma_checker_io_req_bits_passthrough = 1'h1; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_bits_valid = 1'h1; // @[DCache.scala:120:32] wire pma_checker__mpu_ppn_ignore_T = 1'h1; // @[TLB.scala:197:28] wire pma_checker_mpu_ppn_ignore = 1'h1; // @[TLB.scala:197:34] wire pma_checker__mpu_ppn_ignore_T_1 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_mpu_ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__mpu_priv_T = 1'h1; // @[TLB.scala:415:52] wire pma_checker__mpu_priv_T_1 = 1'h1; // @[TLB.scala:415:38] wire pma_checker__homogeneous_T_59 = 1'h1; // @[TLBPermissions.scala:87:22] wire pma_checker__deny_access_to_debug_T = 1'h1; // @[TLB.scala:428:39] wire pma_checker__sector_hits_T_6 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_14 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_22 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_30 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_38 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_46 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_54 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_62 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__superpage_hits_tagMatch_T = 1'h1; // @[TLB.scala:178:43] wire pma_checker__superpage_hits_ignore_T_1 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__superpage_hits_ignore_T_2 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__superpage_hits_tagMatch_T_1 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__superpage_hits_ignore_T_4 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__superpage_hits_ignore_T_5 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_27 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__superpage_hits_tagMatch_T_2 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__superpage_hits_ignore_T_7 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__superpage_hits_ignore_T_8 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_41 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__superpage_hits_tagMatch_T_3 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__superpage_hits_ignore_T_10 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__superpage_hits_ignore_T_11 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_55 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hitsVec_T_3 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_9 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_15 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_21 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_27 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_33 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_39 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_45 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_tagMatch_T = 1'h1; // @[TLB.scala:178:43] wire pma_checker__hitsVec_ignore_T_1 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__hitsVec_ignore_T_2 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_61 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hitsVec_tagMatch_T_1 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__hitsVec_ignore_T_4 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__hitsVec_ignore_T_5 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_76 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hitsVec_tagMatch_T_2 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__hitsVec_ignore_T_7 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__hitsVec_ignore_T_8 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_91 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hitsVec_tagMatch_T_3 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__hitsVec_ignore_T_10 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__hitsVec_ignore_T_11 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_106 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hitsVec_tagMatch_T_4 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__hitsVec_ignore_T_13 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_13 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_116 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hitsVec_ignore_T_14 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_14 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_121 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hits_T = 1'h1; // @[TLB.scala:442:18] wire pma_checker__newEntry_sr_T = 1'h1; // @[PTW.scala:141:47] wire pma_checker__newEntry_sw_T = 1'h1; // @[PTW.scala:141:47] wire pma_checker__newEntry_sx_T = 1'h1; // @[PTW.scala:141:47] wire pma_checker__ppn_T = 1'h1; // @[TLB.scala:502:30] wire pma_checker__ppn_ignore_T = 1'h1; // @[TLB.scala:197:28] wire pma_checker__ppn_ignore_T_1 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__ppn_ignore_T_2 = 1'h1; // @[TLB.scala:197:28] wire pma_checker__ppn_ignore_T_3 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_ppn_ignore_3 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__ppn_ignore_T_4 = 1'h1; // @[TLB.scala:197:28] wire pma_checker__ppn_ignore_T_5 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_ppn_ignore_5 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__ppn_ignore_T_6 = 1'h1; // @[TLB.scala:197:28] wire pma_checker__ppn_ignore_T_7 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_ppn_ignore_7 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__ppn_ignore_T_8 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_ppn_ignore_8 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__ppn_ignore_T_9 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_ppn_ignore_9 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__stage1_bypass_T_1 = 1'h1; // @[TLB.scala:517:83] wire pma_checker__stage2_bypass_T = 1'h1; // @[TLB.scala:523:42] wire pma_checker__bad_va_T_1 = 1'h1; // @[TLB.scala:560:26] wire pma_checker__gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107] wire pma_checker__tlb_miss_T = 1'h1; // @[TLB.scala:613:32] wire pma_checker__tlb_miss_T_2 = 1'h1; // @[TLB.scala:613:56] wire pma_checker__tlb_miss_T_4 = 1'h1; // @[TLB.scala:613:67] wire pma_checker_state_vec_0_set_left_older = 1'h1; // @[Replacement.scala:196:33] wire pma_checker_state_vec_0_set_left_older_1 = 1'h1; // @[Replacement.scala:196:33] wire pma_checker__state_vec_0_T_3 = 1'h1; // @[Replacement.scala:218:7] wire pma_checker__state_vec_0_T_7 = 1'h1; // @[Replacement.scala:218:7] wire pma_checker__state_vec_0_T_8 = 1'h1; // @[Replacement.scala:206:16] wire pma_checker_state_vec_0_set_left_older_2 = 1'h1; // @[Replacement.scala:196:33] wire pma_checker__state_vec_0_T_14 = 1'h1; // @[Replacement.scala:218:7] wire pma_checker__state_vec_0_T_18 = 1'h1; // @[Replacement.scala:218:7] wire pma_checker__state_vec_0_T_19 = 1'h1; // @[Replacement.scala:206:16] wire pma_checker_state_reg_set_left_older = 1'h1; // @[Replacement.scala:196:33] wire pma_checker__state_reg_T_2 = 1'h1; // @[Replacement.scala:218:7] wire pma_checker__state_reg_T_6 = 1'h1; // @[Replacement.scala:218:7] wire pma_checker__state_reg_T_7 = 1'h1; // @[Replacement.scala:206:16] wire pma_checker__io_req_ready_T = 1'h1; // @[TLB.scala:631:25] wire pma_checker__io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20] wire pma_checker__io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28] wire pma_checker__r_superpage_repl_addr_T_6 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_superpage_repl_addr_T_7 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_superpage_repl_addr_T_8 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_superpage_repl_addr_T_9 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_12 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_13 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_14 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_15 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_16 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_17 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_18 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_19 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__tagMatch_T = 1'h1; // @[TLB.scala:178:43] wire pma_checker__ignore_T_1 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__ignore_T_2 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__tagMatch_T_1 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__ignore_T_4 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__ignore_T_5 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__tagMatch_T_2 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__ignore_T_7 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__ignore_T_8 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__tagMatch_T_3 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__ignore_T_10 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__ignore_T_11 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__tagMatch_T_4 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__ignore_T_13 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_ignore_13 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__ignore_T_14 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_ignore_14 = 1'h1; // @[TLB.scala:182:34] wire metaArb_io_in_0_ready = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_0_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_1_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_2_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_3_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_4_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_out_ready = 1'h1; // @[DCache.scala:135:28] wire metaArb__io_in_0_ready_T = 1'h1; // @[Arbiter.scala:153:19] wire dataArb_io_in_0_ready = 1'h1; // @[DCache.scala:152:28] wire dataArb_io_in_1_bits_wordMask = 1'h1; // @[DCache.scala:152:28] wire dataArb_io_in_2_bits_wordMask = 1'h1; // @[DCache.scala:152:28] wire dataArb_io_in_3_bits_wordMask = 1'h1; // @[DCache.scala:152:28] wire dataArb_io_out_ready = 1'h1; // @[DCache.scala:152:28] wire dataArb__io_in_0_ready_T = 1'h1; // @[Arbiter.scala:153:19] wire _s2_valid_not_killed_T = 1'h1; // @[DCache.scala:338:48] wire _s2_flush_valid_T = 1'h1; // @[DCache.scala:363:54] wire _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T = 1'h1; // @[DCache.scala:397:74] wire _s2_valid_hit_pre_data_ecc_and_waw_T_1 = 1'h1; // @[DCache.scala:418:108] wire _s2_valid_hit_pre_data_ecc_T = 1'h1; // @[DCache.scala:420:73] wire _s2_valid_hit_pre_data_ecc_T_1 = 1'h1; // @[DCache.scala:420:88] wire _s2_valid_hit_T = 1'h1; // @[DCache.scala:422:51] wire _s2_valid_miss_T_1 = 1'h1; // @[DCache.scala:423:58] wire _s2_victimize_T = 1'h1; // @[DCache.scala:429:43] wire _r_T_117 = 1'h1; // @[Metadata.scala:140:24] wire _s2_dont_nack_misc_T = 1'h1; // @[DCache.scala:441:46] wire _s2_dont_nack_misc_T_4 = 1'h1; // @[DCache.scala:442:57] wire _metaArb_io_in_2_bits_write_T = 1'h1; // @[DCache.scala:463:34] wire _s2_valid_correct_T_1 = 1'h1; // @[DCache.scala:489:77] wire _pstore1_merge_T_3 = 1'h1; // @[DCache.scala:491:51] wire _pstore_drain_opportunistic_T_61 = 1'h1; // @[DCache.scala:502:95] wire _pstore1_valid_T_3 = 1'h1; // @[DCache.scala:491:51] wire _pstore_drain_T = 1'h1; // @[DCache.scala:516:5] wire _pstore_drain_T_3 = 1'h1; // @[DCache.scala:506:87] wire _pstore1_held_T_3 = 1'h1; // @[DCache.scala:491:51] wire _pstore1_held_T_5 = 1'h1; // @[DCache.scala:521:38] wire _dataArb_io_in_0_valid_T = 1'h1; // @[DCache.scala:516:5] wire _dataArb_io_in_0_valid_T_3 = 1'h1; // @[DCache.scala:506:87] wire _dataArb_io_in_0_bits_wordMask_T = 1'h1; // @[DCache.scala:555:20] wire _io_cpu_s2_nack_cause_raw_T = 1'h1; // @[DCache.scala:574:59] wire _io_cpu_s2_nack_cause_raw_T_1 = 1'h1; // @[DCache.scala:574:74] wire _get_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _get_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _putpartial_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _putpartial_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _putpartial_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _putpartial_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _putpartial_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _putpartial_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _putpartial_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _putpartial_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_54 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_55 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_56 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_57 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_108 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_109 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_110 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_111 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_162 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_163 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_164 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_165 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_216 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_217 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_218 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_219 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_270 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_271 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_272 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_273 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_324 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_325 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_326 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_327 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_378 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_379 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_380 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_381 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_432 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_433 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_434 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_435 = 1'h1; // @[Parameters.scala:684:29] wire _tl_out_a_valid_T = 1'h1; // @[DCache.scala:603:21] wire _tl_out_a_bits_legal_T_19 = 1'h1; // @[Parameters.scala:91:44] wire _tl_out_a_bits_legal_T_20 = 1'h1; // @[Parameters.scala:684:29] wire tl_out_a_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire tl_out_a_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire tl_out_a_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire tl_out_a_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire _dataArb_io_in_1_bits_wordMask_T = 1'h1; // @[DCache.scala:731:39] wire _nodeOut_c_bits_legal_T_5 = 1'h1; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_16 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_c_bits_legal_T_17 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_c_bits_legal_T_19 = 1'h1; // @[Parameters.scala:91:44] wire _nodeOut_c_bits_legal_T_20 = 1'h1; // @[Parameters.scala:684:29] wire _nodeOut_c_bits_legal_T_39 = 1'h1; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_50 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_c_bits_legal_T_51 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_c_bits_legal_T_53 = 1'h1; // @[Parameters.scala:91:44] wire _nodeOut_c_bits_legal_T_54 = 1'h1; // @[Parameters.scala:684:29] wire _dataArb_io_in_2_bits_wordMask_T = 1'h1; // @[DCache.scala:904:37] wire _io_cpu_ordered_T = 1'h1; // @[DCache.scala:929:35] wire _s1_xcpt_valid_T = 1'h1; // @[DCache.scala:932:43] wire _io_cpu_resp_valid_T_1 = 1'h1; // @[DCache.scala:949:73] wire _io_cpu_replay_next_T_2 = 1'h1; // @[DCache.scala:950:65] wire _clock_en_reg_T = 1'h1; // @[DCache.scala:1060:19] wire _clock_en_reg_T_2 = 1'h1; // @[DCache.scala:1060:44] wire _clock_en_reg_T_3 = 1'h1; // @[DCache.scala:1061:46] wire _clock_en_reg_T_4 = 1'h1; // @[DCache.scala:1062:31] wire _clock_en_reg_T_5 = 1'h1; // @[DCache.scala:1063:26] wire _clock_en_reg_T_6 = 1'h1; // @[DCache.scala:1064:14] wire _clock_en_reg_T_7 = 1'h1; // @[DCache.scala:1064:26] wire _clock_en_reg_T_8 = 1'h1; // @[DCache.scala:1065:14] wire _clock_en_reg_T_9 = 1'h1; // @[DCache.scala:1065:26] wire _clock_en_reg_T_10 = 1'h1; // @[DCache.scala:1066:27] wire _clock_en_reg_T_11 = 1'h1; // @[DCache.scala:1067:22] wire _clock_en_reg_T_12 = 1'h1; // @[DCache.scala:1067:42] wire _clock_en_reg_T_13 = 1'h1; // @[DCache.scala:1068:18] wire _clock_en_reg_T_15 = 1'h1; // @[DCache.scala:1068:35] wire _clock_en_reg_T_16 = 1'h1; // @[DCache.scala:1069:31] wire _clock_en_reg_T_18 = 1'h1; // @[DCache.scala:1070:22] wire _clock_en_reg_T_20 = 1'h1; // @[DCache.scala:1070:46] wire _clock_en_reg_T_21 = 1'h1; // @[DCache.scala:1071:23] wire _clock_en_reg_T_23 = 1'h1; // @[DCache.scala:1072:23] wire _clock_en_reg_T_25 = 1'h1; // @[DCache.scala:1072:54] wire _clock_en_reg_T_27 = 1'h1; // @[DCache.scala:1073:21] wire _io_cpu_perf_storeBufferEmptyAfterLoad_T_2 = 1'h1; // @[DCache.scala:1082:31] wire _io_cpu_perf_storeBufferEmptyAfterStore_T_5 = 1'h1; // @[DCache.scala:1087:31] wire _io_cpu_perf_canAcceptStoreThenLoad_T_3 = 1'h1; // @[DCache.scala:1089:72] wire _io_cpu_perf_canAcceptLoadThenLoad_T_56 = 1'h1; // @[DCache.scala:1092:115] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[DCache.scala:101:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[DCache.scala:101:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[DCache.scala:101:7] wire [15:0] pma_checker_io_ptw_ptbr_asid = 16'h0; // @[DCache.scala:120:32] wire [15:0] pma_checker_io_ptw_hgatp_asid = 16'h0; // @[DCache.scala:120:32] wire [15:0] pma_checker_io_ptw_vsatp_asid = 16'h0; // @[DCache.scala:120:32] wire [15:0] pma_checker_satp_asid = 16'h0; // @[TLB.scala:373:17] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[DCache.scala:101:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[DCache.scala:101:7] wire [3:0] pma_checker_io_ptw_ptbr_mode = 4'h0; // @[DCache.scala:120:32] wire [3:0] pma_checker_io_ptw_hgatp_mode = 4'h0; // @[DCache.scala:120:32] wire [3:0] pma_checker_io_ptw_vsatp_mode = 4'h0; // @[DCache.scala:120:32] wire [3:0] pma_checker_satp_mode = 4'h0; // @[TLB.scala:373:17] wire [3:0] pma_checker_real_hits_hi_hi = 4'h0; // @[package.scala:45:27] wire [3:0] pma_checker_lo = 4'h0; // @[OneHot.scala:21:45] wire [3:0] pma_checker_hi = 4'h0; // @[OneHot.scala:21:45] wire [3:0] pma_checker_hi_1 = 4'h0; // @[OneHot.scala:30:18] wire [3:0] pma_checker_lo_1 = 4'h0; // @[OneHot.scala:31:18] wire [3:0] pma_checker__multipleHits_T_31 = 4'h0; // @[Misc.scala:182:39] wire [3:0] pma_checker_r_superpage_repl_addr_valids = 4'h0; // @[package.scala:45:27] wire [3:0] pma_checker_r_sectored_repl_addr_valids_lo = 4'h0; // @[package.scala:45:27] wire [3:0] pma_checker_r_sectored_repl_addr_valids_hi = 4'h0; // @[package.scala:45:27] wire [3:0] pma_checker_r_sectored_hit_bits_lo = 4'h0; // @[OneHot.scala:21:45] wire [3:0] pma_checker_r_sectored_hit_bits_hi = 4'h0; // @[OneHot.scala:21:45] wire [3:0] pma_checker_r_sectored_hit_bits_hi_1 = 4'h0; // @[OneHot.scala:30:18] wire [3:0] pma_checker_r_sectored_hit_bits_lo_1 = 4'h0; // @[OneHot.scala:31:18] wire [3:0] pma_checker__r_sectored_hit_bits_T_2 = 4'h0; // @[OneHot.scala:32:28] wire [3:0] pma_checker__r_superpage_hit_bits_T = 4'h0; // @[OneHot.scala:21:45] wire [3:0] s2_meta_correctable_errors_lo = 4'h0; // @[package.scala:45:27] wire [3:0] s2_meta_correctable_errors_hi = 4'h0; // @[package.scala:45:27] wire [3:0] s2_meta_uncorrectable_errors_lo = 4'h0; // @[package.scala:45:27] wire [3:0] s2_meta_uncorrectable_errors_hi = 4'h0; // @[package.scala:45:27] wire [3:0] _r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r_T_63 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _r_T_127 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _a_mask_T = 4'h0; // @[DCache.scala:582:90] wire [3:0] _atomics_WIRE_size = 4'h0; // @[DCache.scala:587:51] wire [3:0] _atomics_WIRE_1_size = 4'h0; // @[DCache.scala:587:38] wire [3:0] _metaArb_io_in_3_bits_data_T_5 = 4'h0; // @[Metadata.scala:87:10] wire [3:0] probe_bits_res_size = 4'h0; // @[DCache.scala:1202:19] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[DCache.scala:101:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[DCache.scala:101:7] wire [43:0] pma_checker_io_ptw_resp_bits_pte_ppn = 44'h0; // @[DCache.scala:120:32] wire [43:0] pma_checker_io_ptw_ptbr_ppn = 44'h0; // @[DCache.scala:120:32] wire [43:0] pma_checker_io_ptw_hgatp_ppn = 44'h0; // @[DCache.scala:120:32] wire [43:0] pma_checker_io_ptw_vsatp_ppn = 44'h0; // @[DCache.scala:120:32] wire [43:0] pma_checker_satp_ppn = 44'h0; // @[TLB.scala:373:17] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[DCache.scala:101:7] wire [22:0] pma_checker_io_ptw_status_zero2 = 23'h0; // @[DCache.scala:120:32] wire [22:0] pma_checker_io_ptw_gstatus_zero2 = 23'h0; // @[DCache.scala:120:32] wire [7:0] io_cpu_req_bits_mask = 8'h0; // @[DCache.scala:101:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[DCache.scala:101:7] wire [7:0] pma_checker_io_ptw_status_zero1 = 8'h0; // @[DCache.scala:120:32] wire [7:0] pma_checker_io_ptw_gstatus_zero1 = 8'h0; // @[DCache.scala:120:32] wire [7:0] pma_checker_r_sectored_repl_addr_valids = 8'h0; // @[package.scala:45:27] wire [7:0] pma_checker__r_sectored_hit_bits_T = 8'h0; // @[OneHot.scala:21:45] wire [7:0] metaArb_io_in_1_bits_way_en = 8'h0; // @[DCache.scala:135:28] wire [7:0] s0_req_mask = 8'h0; // @[DCache.scala:192:24] wire [7:0] s2_meta_correctable_errors = 8'h0; // @[package.scala:45:27] wire [7:0] s2_meta_uncorrectable_errors = 8'h0; // @[package.scala:45:27] wire [7:0] _s2_meta_error_T = 8'h0; // @[DCache.scala:362:53] wire [7:0] _metaArb_io_in_1_bits_way_en_T_8 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_9 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_10 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_11 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_12 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_13 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_14 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_15 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_16 = 8'h0; // @[DCache.scala:452:69] wire [7:0] _metaArb_io_in_1_bits_way_en_T_17 = 8'h0; // @[DCache.scala:452:64] wire [7:0] _pstore2_storegen_mask_mergedMask_T = 8'h0; // @[DCache.scala:533:42] wire [7:0] _atomics_WIRE_mask = 8'h0; // @[DCache.scala:587:51] wire [7:0] _atomics_WIRE_1_mask = 8'h0; // @[DCache.scala:587:38] wire [7:0] probe_bits_res_mask = 8'h0; // @[DCache.scala:1202:19] wire [1:0] io_ptw_status_xs = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_tlb_port_req_bits_size = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_tlb_port_req_bits_prv = 2'h0; // @[DCache.scala:101:7] wire [1:0] pma_checker_io_ptw_resp_bits_pte_reserved_for_software = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_resp_bits_level = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_dprv = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_prv = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_sxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_uxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_xs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_fs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_mpp = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_vs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_hstatus_vsxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_hstatus_zero3 = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_hstatus_zero2 = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_dprv = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_prv = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_sxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_uxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_xs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_fs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_mpp = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_vs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_0_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_0_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_1_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_1_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_2_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_2_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_3_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_3_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_4_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_4_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_5_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_5_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_6_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_6_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_7_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_7_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_real_hits_lo_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_real_hits_lo_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_real_hits_hi_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_real_hits_hi_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_real_hits_hi_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker__special_entry_level_T = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_special_entry_data_0_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_special_entry_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_special_entry_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_special_entry_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_special_entry_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_waddr = 2'h0; // @[TLB.scala:477:22] wire [1:0] pma_checker_superpage_entries_0_data_0_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_0_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_1 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_1_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_2 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_2_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_3 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_3_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_4 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_4_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_5 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_5_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_6 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_6_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_7 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_7_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker__pr_array_T = 2'h0; // @[TLB.scala:529:26] wire [1:0] pma_checker__pw_array_T = 2'h0; // @[TLB.scala:531:26] wire [1:0] pma_checker__px_array_T = 2'h0; // @[TLB.scala:533:26] wire [1:0] pma_checker_lo_lo = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_lo_hi = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_hi_lo = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_hi_hi = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_hi_2 = 2'h0; // @[OneHot.scala:30:18] wire [1:0] pma_checker_lo_2 = 2'h0; // @[OneHot.scala:31:18] wire [1:0] pma_checker__state_vec_0_T = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker__state_vec_0_T_11 = 2'h0; // @[Replacement.scala:207:62] wire [1:0] pma_checker_lo_3 = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_hi_3 = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_hi_4 = 2'h0; // @[OneHot.scala:30:18] wire [1:0] pma_checker_lo_4 = 2'h0; // @[OneHot.scala:31:18] wire [1:0] pma_checker_state_reg_touch_way_sized = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker__multipleHits_T_3 = 2'h0; // @[Misc.scala:182:39] wire [1:0] pma_checker__multipleHits_T_12 = 2'h0; // @[Misc.scala:182:39] wire [1:0] pma_checker__multipleHits_T_24 = 2'h0; // @[Misc.scala:182:39] wire [1:0] pma_checker__multipleHits_T_32 = 2'h0; // @[Misc.scala:181:37] wire [1:0] pma_checker__multipleHits_T_37 = 2'h0; // @[Misc.scala:182:39] wire [1:0] pma_checker__r_superpage_repl_addr_T_3 = 2'h0; // @[Replacement.scala:249:12] wire [1:0] pma_checker_r_superpage_repl_addr_valids_lo = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_r_superpage_repl_addr_valids_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker__r_superpage_repl_addr_T_12 = 2'h0; // @[Mux.scala:50:70] wire [1:0] pma_checker__r_superpage_repl_addr_T_13 = 2'h0; // @[TLB.scala:757:8] wire [1:0] pma_checker__r_sectored_repl_addr_T_3 = 2'h0; // @[Replacement.scala:249:12] wire [1:0] pma_checker__r_sectored_repl_addr_T_7 = 2'h0; // @[Replacement.scala:249:12] wire [1:0] pma_checker__r_sectored_repl_addr_T_8 = 2'h0; // @[Replacement.scala:250:16] wire [1:0] pma_checker_r_sectored_repl_addr_valids_lo_lo = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_r_sectored_repl_addr_valids_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_r_sectored_repl_addr_valids_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_r_sectored_repl_addr_valids_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_r_sectored_hit_bits_lo_lo = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_r_sectored_hit_bits_lo_hi = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_r_sectored_hit_bits_hi_lo = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_r_sectored_hit_bits_hi_hi = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_r_sectored_hit_bits_hi_2 = 2'h0; // @[OneHot.scala:30:18] wire [1:0] pma_checker_r_sectored_hit_bits_lo_2 = 2'h0; // @[OneHot.scala:31:18] wire [1:0] pma_checker__r_sectored_hit_bits_T_4 = 2'h0; // @[OneHot.scala:32:28] wire [1:0] pma_checker__r_sectored_hit_bits_T_6 = 2'h0; // @[OneHot.scala:32:10] wire [1:0] pma_checker_r_superpage_hit_bits_lo = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_r_superpage_hit_bits_hi = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_r_superpage_hit_bits_hi_1 = 2'h0; // @[OneHot.scala:30:18] wire [1:0] pma_checker_r_superpage_hit_bits_lo_1 = 2'h0; // @[OneHot.scala:31:18] wire [1:0] pma_checker__r_superpage_hit_bits_T_2 = 2'h0; // @[OneHot.scala:32:28] wire [1:0] pma_checker__r_superpage_hit_bits_T_4 = 2'h0; // @[OneHot.scala:32:10] wire [1:0] s1_meta_hit_state_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _s2_valid_no_xcpt_T_1 = 2'h0; // @[DCache.scala:332:54] wire [1:0] s2_meta_correctable_errors_lo_lo = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_correctable_errors_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_correctable_errors_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_correctable_errors_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_uncorrectable_errors_lo_lo = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_uncorrectable_errors_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_uncorrectable_errors_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_uncorrectable_errors_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] _r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_75 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_79 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_83 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_87 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_91 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_139 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_143 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_147 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_151 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_155 = 2'h0; // @[Misc.scala:38:63] wire [1:0] metaArb_io_in_1_bits_data_new_meta_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _metaArb_io_in_3_bits_data_T_2 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _metaArb_io_in_3_bits_data_T_4 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] probe_bits_res_param = 2'h0; // @[DCache.scala:1202:19] wire [1:0] _nodeOut_c_bits_legal_T_2 = 2'h0; // @[Parameters.scala:137:41] wire [1:0] _nodeOut_c_bits_legal_T_36 = 2'h0; // @[Parameters.scala:137:41] wire [1:0] _io_cpu_s2_xcpt_WIRE_size = 2'h0; // @[DCache.scala:933:74] wire [1:0] metaArb_io_in_0_bits_data_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] metaArb_io_in_0_bits_data_meta_1_coh_state = 2'h0; // @[HellaCache.scala:305:20] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[DCache.scala:101:7] wire [29:0] pma_checker_io_ptw_hstatus_zero6 = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_0_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_1_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_2_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_3_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_4_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_5_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_6_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_7_addr = 30'h0; // @[DCache.scala:120:32] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[DCache.scala:101:7] wire [8:0] pma_checker_io_ptw_hstatus_zero5 = 9'h0; // @[DCache.scala:120:32] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[DCache.scala:101:7] wire [5:0] pma_checker_io_ptw_hstatus_vgein = 6'h0; // @[DCache.scala:120:32] wire [5:0] pma_checker_real_hits_lo = 6'h0; // @[package.scala:45:27] wire [5:0] pma_checker_special_entry_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_0_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_1_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_2_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_3_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_0_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_1_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_2_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_3_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_4_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_5_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_6_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_7_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker__multipleHits_T = 6'h0; // @[Misc.scala:181:37] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[DCache.scala:101:7] wire [4:0] io_tlb_port_req_bits_cmd = 5'h0; // @[DCache.scala:101:7] wire [4:0] pma_checker_io_ptw_hstatus_zero1 = 5'h0; // @[DCache.scala:120:32] wire [4:0] _io_cpu_s2_xcpt_WIRE_cmd = 5'h0; // @[DCache.scala:933:74] wire [7:0] pma_checker__r_sectored_repl_addr_T_11 = 8'hFF; // @[TLB.scala:757:43] wire [7:0] metaArb_io_in_0_bits_way_en = 8'hFF; // @[DCache.scala:135:28] wire [7:0] dataArb_io_in_1_bits_eccMask = 8'hFF; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_2_bits_eccMask = 8'hFF; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_2_bits_way_en = 8'hFF; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_3_bits_eccMask = 8'hFF; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_3_bits_way_en = 8'hFF; // @[DCache.scala:152:28] wire [7:0] _dataArb_io_in_3_bits_wordMask_T = 8'hFF; // @[DCache.scala:254:9] wire [7:0] _dataArb_io_in_3_bits_eccMask_T = 8'hFF; // @[DCache.scala:256:36] wire [7:0] _dataArb_io_in_3_bits_way_en_T = 8'hFF; // @[DCache.scala:257:35] wire [7:0] tl_out_a_bits_a_mask = 8'hFF; // @[Edges.scala:346:17] wire [7:0] _tl_out_a_bits_a_mask_T = 8'hFF; // @[Misc.scala:222:10] wire [7:0] _dataArb_io_in_1_bits_eccMask_T = 8'hFF; // @[DCache.scala:732:38] wire [7:0] _dataArb_io_in_2_bits_eccMask_T = 8'hFF; // @[DCache.scala:905:36] wire [7:0] _dataArb_io_in_2_bits_way_en_T = 8'hFF; // @[DCache.scala:906:35] wire [7:0] _metaArb_io_in_0_bits_way_en_T = 8'hFF; // @[DCache.scala:1049:35] wire [2:0] pma_checker__r_sectored_repl_addr_T_20 = 3'h6; // @[Mux.scala:50:70] wire [2:0] tl_out_a_bits_a_opcode = 3'h6; // @[Edges.scala:346:17] wire [2:0] _tl_out_a_bits_a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34] wire [2:0] nodeOut_c_bits_c_opcode = 3'h6; // @[Edges.scala:380:17] wire [2:0] pma_checker_real_hits_lo_lo = 3'h0; // @[package.scala:45:27] wire [2:0] pma_checker_real_hits_lo_hi = 3'h0; // @[package.scala:45:27] wire [2:0] pma_checker_real_hits_hi_lo = 3'h0; // @[package.scala:45:27] wire [2:0] pma_checker_special_entry_data_0_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_special_entry_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_special_entry_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_special_entry_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_waddr_1 = 3'h0; // @[TLB.scala:485:22] wire [2:0] pma_checker_sectored_entries_0_0_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_state_vec_0_touch_way_sized = 3'h0; // @[package.scala:163:13] wire [2:0] pma_checker_state_vec_0_left_subtree_state = 3'h0; // @[package.scala:163:13] wire [2:0] pma_checker_state_vec_0_right_subtree_state = 3'h0; // @[Replacement.scala:198:38] wire [2:0] pma_checker__state_vec_0_T_10 = 3'h0; // @[Replacement.scala:203:16] wire [2:0] pma_checker__multipleHits_T_1 = 3'h0; // @[Misc.scala:181:37] wire [2:0] pma_checker__multipleHits_T_10 = 3'h0; // @[Misc.scala:182:39] wire [2:0] pma_checker__multipleHits_T_22 = 3'h0; // @[Misc.scala:181:37] wire [2:0] pma_checker_r_sectored_repl_addr_left_subtree_state = 3'h0; // @[package.scala:163:13] wire [2:0] pma_checker_r_sectored_repl_addr_right_subtree_state = 3'h0; // @[Replacement.scala:245:38] wire [2:0] pma_checker__r_sectored_repl_addr_T_9 = 3'h0; // @[Replacement.scala:249:12] wire [2:0] pma_checker__r_sectored_repl_addr_T_26 = 3'h0; // @[Mux.scala:50:70] wire [2:0] pma_checker__r_sectored_repl_addr_T_27 = 3'h0; // @[TLB.scala:757:8] wire [2:0] pma_checker__r_sectored_hit_bits_T_7 = 3'h0; // @[OneHot.scala:32:10] wire [2:0] get_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] put_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] put_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] putpartial_param = 3'h0; // @[Edges.scala:500:17] wire [2:0] _atomics_WIRE_opcode = 3'h0; // @[DCache.scala:587:51] wire [2:0] _atomics_WIRE_param = 3'h0; // @[DCache.scala:587:51] wire [2:0] _atomics_WIRE_1_opcode = 3'h0; // @[DCache.scala:587:38] wire [2:0] _atomics_WIRE_1_param = 3'h0; // @[DCache.scala:587:38] wire [2:0] atomics_a_1_param = 3'h0; // @[Edges.scala:534:17] wire [2:0] atomics_a_5_param = 3'h0; // @[Edges.scala:517:17] wire [2:0] probe_bits_res_opcode = 3'h0; // @[DCache.scala:1202:19] wire [2:0] pma_checker__state_vec_0_T_9 = 3'h5; // @[Replacement.scala:202:12] wire [2:0] pma_checker__state_vec_0_T_20 = 3'h5; // @[Replacement.scala:202:12] wire [2:0] pma_checker__state_vec_0_T_21 = 3'h5; // @[Replacement.scala:206:16] wire [2:0] pma_checker__state_reg_T_8 = 3'h5; // @[Replacement.scala:202:12] wire [2:0] pma_checker__r_sectored_repl_addr_T_21 = 3'h5; // @[Mux.scala:50:70] wire [2:0] tl_out_a_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [2:0] nackResponseMessage_param = 3'h5; // @[Edges.scala:416:17] wire [2:0] dirtyReleaseMessage_opcode = 3'h5; // @[Edges.scala:433:17] wire [2:0] pma_checker__r_sectored_repl_addr_T_22 = 3'h4; // @[Mux.scala:50:70] wire [2:0] get_opcode = 3'h4; // @[Edges.scala:460:17] wire [2:0] atomics_a_4_param = 3'h4; // @[Edges.scala:517:17] wire [2:0] _tl_out_a_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] nackResponseMessage_opcode = 3'h4; // @[Edges.scala:416:17] wire [2:0] cleanReleaseMessage_opcode = 3'h4; // @[Edges.scala:416:17] wire [1:0] pma_checker__r_superpage_repl_addr_T_11 = 2'h1; // @[Mux.scala:50:70] wire [1:0] _r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] dataArb_io_in_0_bits_wordMask_wordMask = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _dataArb_io_in_0_bits_wordMask_T_2 = 2'h1; // @[DCache.scala:555:20] wire [1:0] _metaArb_io_in_3_bits_data_T_6 = 2'h1; // @[Metadata.scala:25:15] wire [3:0] pma_checker__r_superpage_repl_addr_T_5 = 4'hF; // @[TLB.scala:757:43] wire [3:0] _r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] tl_out_a_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] tl_out_a_bits_a_mask_hi = 4'hF; // @[Misc.scala:222:10] wire [1:0] io_ptw_status_sxl = 2'h2; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[DCache.scala:101:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[DCache.scala:101:7] wire [1:0] pma_checker_state_vec_0_hi = 2'h2; // @[Replacement.scala:202:12] wire [1:0] pma_checker_state_vec_0_hi_1 = 2'h2; // @[Replacement.scala:202:12] wire [1:0] pma_checker_state_reg_hi = 2'h2; // @[Replacement.scala:202:12] wire [1:0] pma_checker__r_superpage_repl_addr_T_10 = 2'h2; // @[Mux.scala:50:70] wire [1:0] pma_checker__state_T = 2'h2; // @[TLB.scala:704:45] wire [1:0] _r_T_118 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_120 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_122 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] tl_out_a_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [2:0] pma_checker__r_sectored_repl_addr_T_23 = 3'h3; // @[Mux.scala:50:70] wire [2:0] atomics_a_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_param = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_1_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_2_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_3_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_8_param = 3'h3; // @[Edges.scala:517:17] wire [2:0] pma_checker__r_sectored_repl_addr_T_24 = 3'h2; // @[Mux.scala:50:70] wire [2:0] atomics_a_3_param = 3'h2; // @[Edges.scala:534:17] wire [2:0] atomics_a_4_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_5_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_6_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_param = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_8_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] pma_checker_mpu_priv = 3'h1; // @[TLB.scala:415:27] wire [2:0] pma_checker__r_sectored_repl_addr_T_25 = 3'h1; // @[Mux.scala:50:70] wire [2:0] putpartial_opcode = 3'h1; // @[Edges.scala:500:17] wire [2:0] atomics_a_2_param = 3'h1; // @[Edges.scala:534:17] wire [2:0] atomics_a_6_param = 3'h1; // @[Edges.scala:517:17] wire [3:0] pma_checker_state_vec_0_hi_2 = 4'h8; // @[Replacement.scala:202:12] wire [3:0] _r_T_71 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _r_T_135 = 4'h8; // @[Metadata.scala:133:10] wire [11:0] pma_checker__gpa_hits_hit_mask_T_2 = 12'h0; // @[TLB.scala:606:24] wire [11:0] pma_checker__io_resp_gpa_offset_T = 12'h0; // @[TLB.scala:658:47] wire [26:0] pma_checker_io_ptw_req_bits_bits_addr = 27'h0; // @[DCache.scala:120:32] wire [26:0] pma_checker__io_resp_gpa_page_T_2 = 27'h0; // @[TLB.scala:657:58] wire [6:0] pma_checker__state_vec_0_T_22 = 7'h45; // @[Replacement.scala:202:12] wire [63:0] io_cpu_req_bits_data = 64'h0; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[DCache.scala:101:7] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_0_value = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_1_value = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_2_wdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_2_value = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_3_wdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_3_value = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] s0_req_data = 64'h0; // @[DCache.scala:192:24] wire [63:0] get_data = 64'h0; // @[Edges.scala:460:17] wire [63:0] _atomics_WIRE_data = 64'h0; // @[DCache.scala:587:51] wire [63:0] _atomics_WIRE_1_data = 64'h0; // @[DCache.scala:587:38] wire [63:0] tl_out_a_bits_a_data = 64'h0; // @[Edges.scala:346:17] wire [63:0] nackResponseMessage_data = 64'h0; // @[Edges.scala:416:17] wire [63:0] cleanReleaseMessage_data = 64'h0; // @[Edges.scala:416:17] wire [63:0] dirtyReleaseMessage_data = 64'h0; // @[Edges.scala:433:17] wire [63:0] probe_bits_res_data = 64'h0; // @[DCache.scala:1202:19] wire [63:0] nodeOut_c_bits_c_data = 64'h0; // @[Edges.scala:380:17] wire [63:0] nodeOut_c_bits_c_1_data = 64'h0; // @[Edges.scala:396:17] wire [63:0] _s2_data_word_possibly_uncached_T_1 = 64'h0; // @[DCache.scala:972:43] wire [38:0] pma_checker_io_sfence_bits_addr = 39'h0; // @[DCache.scala:120:32] wire [38:0] pma_checker_io_ptw_resp_bits_gpa_bits = 39'h0; // @[DCache.scala:120:32] wire [39:0] io_tlb_port_req_bits_vaddr = 40'h0; // @[DCache.scala:101:7] wire [39:0] _io_cpu_s2_xcpt_WIRE_gpa = 40'h0; // @[DCache.scala:933:74] wire [21:0] pma_checker_special_entry_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_superpage_entries_0_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_superpage_entries_1_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_superpage_entries_2_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_superpage_entries_3_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_0_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_1_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_2_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_3_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_4_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_5_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_6_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_7_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] metaArb_io_in_0_bits_data = 22'h0; // @[DCache.scala:135:28] wire [21:0] _metaArb_io_in_0_bits_data_T = 22'h0; // @[DCache.scala:1050:85] wire [19:0] pma_checker_refill_ppn = 20'h0; // @[TLB.scala:406:44] wire [19:0] pma_checker_newEntry_ppn = 20'h0; // @[TLB.scala:449:24] wire [19:0] pma_checker__ppn_T_42 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_43 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_44 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_45 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_46 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_47 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_48 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_49 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_50 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_51 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_52 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_53 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_54 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_56 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_57 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_58 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_59 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_60 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_61 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_62 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_63 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_64 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_65 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_66 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_67 = 20'h0; // @[Mux.scala:30:73] wire [19:0] metaArb_io_in_0_bits_data_meta_1_tag = 20'h0; // @[HellaCache.scala:305:20] wire [31:0] pma_checker_io_ptw_status_isa = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_gstatus_isa = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_0_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_1_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_2_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_3_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_4_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_5_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_6_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_7_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] _atomics_WIRE_address = 32'h0; // @[DCache.scala:587:51] wire [31:0] _atomics_WIRE_1_address = 32'h0; // @[DCache.scala:587:38] wire [31:0] nodeOut_c_bits_c_address = 32'h0; // @[Edges.scala:380:17] wire [31:0] nodeOut_c_bits_c_1_address = 32'h0; // @[Edges.scala:396:17] wire [31:0] _io_cpu_s2_xcpt_WIRE_paddr = 32'h0; // @[DCache.scala:933:74] wire [3:0] _r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r_T_65 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _r_T_129 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] tl_out_a_bits_a_size = 4'h6; // @[Edges.scala:346:17] wire [3:0] _release_state_T_13 = 4'h6; // @[DCache.scala:820:27] wire [3:0] nodeOut_c_bits_c_size = 4'h6; // @[Edges.scala:380:17] wire [3:0] nodeOut_c_bits_c_1_size = 4'h6; // @[Edges.scala:396:17] wire [2:0] nodeOut_c_bits_c_1_opcode = 3'h7; // @[Edges.scala:396:17] wire [32:0] _nodeOut_c_bits_legal_T_27 = 33'h80000000; // @[Parameters.scala:137:41] wire [32:0] _nodeOut_c_bits_legal_T_28 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_29 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_61 = 33'h80000000; // @[Parameters.scala:137:41] wire [32:0] _nodeOut_c_bits_legal_T_62 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_63 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_23 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_24 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_57 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_58 = 33'h8000000; // @[Parameters.scala:137:46] wire [28:0] _nodeOut_c_bits_legal_T_22 = 29'h8000000; // @[Parameters.scala:137:41] wire [28:0] _nodeOut_c_bits_legal_T_56 = 29'h8000000; // @[Parameters.scala:137:41] wire [32:0] _nodeOut_c_bits_legal_T_13 = 33'hC000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_14 = 33'hC000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_47 = 33'hC000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_48 = 33'hC000000; // @[Parameters.scala:137:46] wire [28:0] _nodeOut_c_bits_legal_T_12 = 29'hC000000; // @[Parameters.scala:137:41] wire [28:0] _nodeOut_c_bits_legal_T_46 = 29'hC000000; // @[Parameters.scala:137:41] wire [32:0] _nodeOut_c_bits_legal_T_8 = 33'h10000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_9 = 33'h10000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_42 = 33'h10000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_43 = 33'h10000; // @[Parameters.scala:137:46] wire [17:0] _nodeOut_c_bits_legal_T_7 = 18'h10000; // @[Parameters.scala:137:41] wire [17:0] _nodeOut_c_bits_legal_T_41 = 18'h10000; // @[Parameters.scala:137:41] wire [32:0] _nodeOut_c_bits_legal_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_4 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_37 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_38 = 33'h0; // @[Parameters.scala:137:46] wire [3:0] _r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _metaArb_io_in_3_bits_data_T_9 = 4'hC; // @[Metadata.scala:89:10] wire [1:0] _r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] tl_out_a_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] tl_out_a_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] tl_out_a_bits_a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] tl_out_a_bits_a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _metaArb_io_in_3_bits_data_T_8 = 2'h3; // @[Metadata.scala:24:15] wire [3:0] _r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r_T_67 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _r_T_131 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _tl_out_a_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _metaArb_io_in_3_bits_data_T_7 = 4'h4; // @[Metadata.scala:88:10] wire [3:0] _r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_62 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _r_T_126 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _metaArb_io_in_3_bits_data_T_3 = 4'h1; // @[Metadata.scala:86:10] wire [8:0] _s1_data_way_T_1 = 9'h100; // @[DCache.scala:694:32] wire [3:0] _r_T_70 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_134 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_69 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_133 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_68 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _r_T_132 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r_T_66 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_130 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r_T_64 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_128 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_61 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_125 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_60 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_124 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [13:0] pma_checker__gf_ld_array_T_2 = 14'h0; // @[TLB.scala:600:46] wire [13:0] pma_checker_gf_ld_array = 14'h0; // @[TLB.scala:600:24] wire [13:0] pma_checker__gf_st_array_T_1 = 14'h0; // @[TLB.scala:601:53] wire [13:0] pma_checker_gf_st_array = 14'h0; // @[TLB.scala:601:24] wire [13:0] pma_checker__gf_inst_array_T = 14'h0; // @[TLB.scala:602:36] wire [13:0] pma_checker_gf_inst_array = 14'h0; // @[TLB.scala:602:26] wire [13:0] pma_checker_gpa_hits_need_gpa_mask = 14'h0; // @[TLB.scala:605:73] wire [13:0] pma_checker__io_resp_gf_ld_T_1 = 14'h0; // @[TLB.scala:637:58] wire [13:0] pma_checker__io_resp_gf_st_T_1 = 14'h0; // @[TLB.scala:638:65] wire [13:0] pma_checker__io_resp_gf_inst_T = 14'h0; // @[TLB.scala:639:48] wire [6:0] pma_checker_real_hits_hi = 7'h0; // @[package.scala:45:27] wire [6:0] pma_checker__state_vec_WIRE_0 = 7'h0; // @[Replacement.scala:305:25] wire [6:0] pma_checker__multipleHits_T_21 = 7'h0; // @[Misc.scala:182:39] wire [12:0] pma_checker_real_hits = 13'h0; // @[package.scala:45:27] wire [12:0] pma_checker__stage1_bypass_T = 13'h0; // @[TLB.scala:517:27] wire [12:0] pma_checker_stage1_bypass = 13'h0; // @[TLB.scala:517:61] wire [12:0] pma_checker__r_array_T_2 = 13'h0; // @[TLB.scala:520:74] wire [12:0] pma_checker__hr_array_T_2 = 13'h0; // @[TLB.scala:524:60] wire [12:0] pma_checker__gpa_hits_T = 13'h0; // @[TLB.scala:607:30] wire [12:0] pma_checker__tlb_hit_T = 13'h0; // @[TLB.scala:611:28] wire [12:0] pma_checker__stage1_bypass_T_2 = 13'h1FFF; // @[TLB.scala:517:68] wire [12:0] pma_checker__stage1_bypass_T_4 = 13'h1FFF; // @[TLB.scala:517:95] wire [12:0] pma_checker_stage2_bypass = 13'h1FFF; // @[TLB.scala:523:27] wire [12:0] pma_checker__hr_array_T_4 = 13'h1FFF; // @[TLB.scala:524:111] wire [12:0] pma_checker__hw_array_T_1 = 13'h1FFF; // @[TLB.scala:525:55] wire [12:0] pma_checker__hx_array_T_1 = 13'h1FFF; // @[TLB.scala:526:55] wire [12:0] pma_checker__gpa_hits_hit_mask_T_4 = 13'h1FFF; // @[TLB.scala:606:88] wire [12:0] pma_checker_gpa_hits_hit_mask = 13'h1FFF; // @[TLB.scala:606:82] wire [12:0] pma_checker__gpa_hits_T_1 = 13'h1FFF; // @[TLB.scala:607:16] wire [12:0] pma_checker_gpa_hits = 13'h1FFF; // @[TLB.scala:607:14] wire [13:0] pma_checker_hr_array = 14'h3FFF; // @[TLB.scala:524:21] wire [13:0] pma_checker_hw_array = 14'h3FFF; // @[TLB.scala:525:21] wire [13:0] pma_checker_hx_array = 14'h3FFF; // @[TLB.scala:526:21] wire [13:0] pma_checker__must_alloc_array_T_8 = 14'h3FFF; // @[TLB.scala:596:19] wire [13:0] pma_checker__gf_ld_array_T_1 = 14'h3FFF; // @[TLB.scala:600:50] wire [30:0] pma_checker_special_entry_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_superpage_entries_0_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_superpage_entries_1_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_superpage_entries_2_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_superpage_entries_3_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_0_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_1_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_2_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_3_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_4_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_5_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_6_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_7_data_hi = 31'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_special_entry_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_superpage_entries_0_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_superpage_entries_1_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_superpage_entries_2_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_superpage_entries_3_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_0_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_1_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_2_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_3_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_4_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_5_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_6_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_7_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_special_entry_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_superpage_entries_0_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_superpage_entries_1_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_superpage_entries_2_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_superpage_entries_3_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_0_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_1_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_2_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_3_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_4_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_5_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_6_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_7_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [13:0] pma_checker_hits = 14'h2000; // @[TLB.scala:442:17] wire [9:0] pma_checker_io_ptw_resp_bits_pte_reserved_for_future = 10'h0; // @[DCache.scala:120:32] wire [31:0] _nodeOut_c_bits_legal_T_26 = 32'h80000000; // @[Parameters.scala:137:31] wire [31:0] _nodeOut_c_bits_legal_T_60 = 32'h80000000; // @[Parameters.scala:137:31] wire [27:0] _nodeOut_c_bits_legal_T_11 = 28'hC000000; // @[Parameters.scala:137:31] wire [27:0] _nodeOut_c_bits_legal_T_45 = 28'hC000000; // @[Parameters.scala:137:31] wire [27:0] _nodeOut_c_bits_legal_T_21 = 28'h8000000; // @[Parameters.scala:137:31] wire [27:0] _nodeOut_c_bits_legal_T_55 = 28'h8000000; // @[Parameters.scala:137:31] wire [16:0] _nodeOut_c_bits_legal_T_6 = 17'h10000; // @[Parameters.scala:137:31] wire [16:0] _nodeOut_c_bits_legal_T_40 = 17'h10000; // @[Parameters.scala:137:31] wire [41:0] pma_checker__mpu_ppn_WIRE_1 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_1 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_3 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_5 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_7 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_9 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_11 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_13 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_15 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_17 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_19 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_21 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_23 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_25 = 42'h0; // @[TLB.scala:170:77] wire nodeOut_a_ready = auto_out_a_ready_0; // @[DCache.scala:101:7] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[DCache.scala:101:7] wire [2:0] nodeOut_b_bits_opcode = auto_out_b_bits_opcode_0; // @[DCache.scala:101:7] wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[DCache.scala:101:7] wire [3:0] nodeOut_b_bits_size = auto_out_b_bits_size_0; // @[DCache.scala:101:7] wire nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[DCache.scala:101:7] wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[DCache.scala:101:7] wire [7:0] nodeOut_b_bits_mask = auto_out_b_bits_mask_0; // @[DCache.scala:101:7] wire [63:0] nodeOut_b_bits_data = auto_out_b_bits_data_0; // @[DCache.scala:101:7] wire nodeOut_b_bits_corrupt = auto_out_b_bits_corrupt_0; // @[DCache.scala:101:7] wire nodeOut_c_ready = auto_out_c_ready_0; // @[DCache.scala:101:7] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[DCache.scala:101:7] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[DCache.scala:101:7] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[DCache.scala:101:7] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[DCache.scala:101:7] wire nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[DCache.scala:101:7] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[DCache.scala:101:7] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[DCache.scala:101:7] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[DCache.scala:101:7] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[DCache.scala:101:7] wire nodeOut_e_ready = auto_out_e_ready_0; // @[DCache.scala:101:7] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire metaArb_io_in_7_valid = io_cpu_req_valid_0; // @[DCache.scala:101:7, :135:28] wire [39:0] metaArb_io_in_7_bits_addr = io_cpu_req_bits_addr_0; // @[DCache.scala:101:7, :135:28] wire [6:0] s0_req_tag = io_cpu_req_bits_tag_0; // @[DCache.scala:101:7, :192:24] wire [4:0] s0_req_cmd = io_cpu_req_bits_cmd_0; // @[DCache.scala:101:7, :192:24] wire [1:0] s0_req_size = io_cpu_req_bits_size_0; // @[DCache.scala:101:7, :192:24] wire s0_req_signed = io_cpu_req_bits_signed_0; // @[DCache.scala:101:7, :192:24] wire [1:0] s0_req_dprv = io_cpu_req_bits_dprv_0; // @[DCache.scala:101:7, :192:24] wire s0_req_dv = io_cpu_req_bits_dv_0; // @[DCache.scala:101:7, :192:24] wire s0_req_no_resp = io_cpu_req_bits_no_resp_0; // @[DCache.scala:101:7, :192:24] wire _io_cpu_s2_nack_T_5; // @[DCache.scala:445:86] wire _io_cpu_s2_nack_cause_raw_T_3; // @[DCache.scala:574:54] wire _io_cpu_s2_uncached_T_1; // @[DCache.scala:920:37] wire _io_cpu_resp_valid_T_2; // @[DCache.scala:949:70] wire [63:0] _io_cpu_resp_bits_data_T_24; // @[DCache.scala:974:41] wire s2_read; // @[Consts.scala:89:68] wire [63:0] _io_cpu_resp_bits_data_word_bypass_T_7; // @[AMOALU.scala:45:16] wire [63:0] s2_data_word; // @[DCache.scala:970:80] wire _io_cpu_replay_next_T_3; // @[DCache.scala:950:62] wire _io_cpu_s2_xcpt_T_ma_ld; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_ma_st; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_pf_ld; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_pf_st; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_ae_ld; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_ae_st; // @[DCache.scala:933:24] wire _io_cpu_ordered_T_8; // @[DCache.scala:929:21] wire _io_cpu_store_pending_T_25; // @[DCache.scala:930:70] wire io_cpu_perf_acquire_done; // @[Edges.scala:233:22] wire io_cpu_perf_release_done; // @[Edges.scala:233:22] wire _io_cpu_perf_grant_T; // @[DCache.scala:1078:39] wire _io_cpu_perf_tlbMiss_T; // @[Decoupled.scala:51:35] wire _io_cpu_perf_blocked_T_1; // @[DCache.scala:1106:23] wire _io_cpu_perf_canAcceptStoreThenLoad_T_10; // @[DCache.scala:1088:41] wire _io_cpu_perf_canAcceptStoreThenRMW_T_1; // @[DCache.scala:1091:75] wire _io_cpu_perf_canAcceptLoadThenLoad_T_61; // @[DCache.scala:1092:40] wire _io_cpu_perf_storeBufferEmptyAfterLoad_T_7; // @[DCache.scala:1080:44] wire _io_cpu_perf_storeBufferEmptyAfterStore_T_10; // @[DCache.scala:1084:45] wire _io_errors_bus_valid_T_2; // @[DCache.scala:1129:42] wire [2:0] auto_out_a_bits_opcode_0; // @[DCache.scala:101:7] wire [2:0] auto_out_a_bits_param_0; // @[DCache.scala:101:7] wire [3:0] auto_out_a_bits_size_0; // @[DCache.scala:101:7] wire auto_out_a_bits_source_0; // @[DCache.scala:101:7] wire [31:0] auto_out_a_bits_address_0; // @[DCache.scala:101:7] wire [7:0] auto_out_a_bits_mask_0; // @[DCache.scala:101:7] wire [63:0] auto_out_a_bits_data_0; // @[DCache.scala:101:7] wire auto_out_a_valid_0; // @[DCache.scala:101:7] wire auto_out_b_ready_0; // @[DCache.scala:101:7] wire [2:0] auto_out_c_bits_opcode_0; // @[DCache.scala:101:7] wire [2:0] auto_out_c_bits_param_0; // @[DCache.scala:101:7] wire [3:0] auto_out_c_bits_size_0; // @[DCache.scala:101:7] wire auto_out_c_bits_source_0; // @[DCache.scala:101:7] wire [31:0] auto_out_c_bits_address_0; // @[DCache.scala:101:7] wire [63:0] auto_out_c_bits_data_0; // @[DCache.scala:101:7] wire auto_out_c_valid_0; // @[DCache.scala:101:7] wire auto_out_d_ready_0; // @[DCache.scala:101:7] wire [2:0] auto_out_e_bits_sink_0; // @[DCache.scala:101:7] wire auto_out_e_valid_0; // @[DCache.scala:101:7] wire io_cpu_req_ready_0; // @[DCache.scala:101:7] wire [39:0] io_cpu_resp_bits_addr_0; // @[DCache.scala:101:7] wire [6:0] io_cpu_resp_bits_tag_0; // @[DCache.scala:101:7] wire [4:0] io_cpu_resp_bits_cmd_0; // @[DCache.scala:101:7] wire [1:0] io_cpu_resp_bits_size_0; // @[DCache.scala:101:7] wire io_cpu_resp_bits_signed_0; // @[DCache.scala:101:7] wire [1:0] io_cpu_resp_bits_dprv_0; // @[DCache.scala:101:7] wire io_cpu_resp_bits_dv_0; // @[DCache.scala:101:7] wire [63:0] io_cpu_resp_bits_data_0; // @[DCache.scala:101:7] wire [7:0] io_cpu_resp_bits_mask_0; // @[DCache.scala:101:7] wire io_cpu_resp_bits_replay_0; // @[DCache.scala:101:7] wire io_cpu_resp_bits_has_data_0; // @[DCache.scala:101:7] wire [63:0] io_cpu_resp_bits_data_word_bypass_0; // @[DCache.scala:101:7] wire [63:0] io_cpu_resp_bits_data_raw_0; // @[DCache.scala:101:7] wire [63:0] io_cpu_resp_bits_store_data_0; // @[DCache.scala:101:7] wire io_cpu_resp_valid_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_ma_ld_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_ma_st_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_pf_ld_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_pf_st_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_ae_ld_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_ae_st_0; // @[DCache.scala:101:7] wire io_cpu_perf_acquire_0; // @[DCache.scala:101:7] wire io_cpu_perf_release_0; // @[DCache.scala:101:7] wire io_cpu_perf_grant_0; // @[DCache.scala:101:7] wire io_cpu_perf_tlbMiss_0; // @[DCache.scala:101:7] wire io_cpu_perf_blocked_0; // @[DCache.scala:101:7] wire io_cpu_perf_canAcceptStoreThenLoad_0; // @[DCache.scala:101:7] wire io_cpu_perf_canAcceptStoreThenRMW_0; // @[DCache.scala:101:7] wire io_cpu_perf_canAcceptLoadThenLoad_0; // @[DCache.scala:101:7] wire io_cpu_perf_storeBufferEmptyAfterLoad_0; // @[DCache.scala:101:7] wire io_cpu_perf_storeBufferEmptyAfterStore_0; // @[DCache.scala:101:7] wire io_cpu_s2_nack_0; // @[DCache.scala:101:7] wire io_cpu_s2_nack_cause_raw_0; // @[DCache.scala:101:7] wire io_cpu_s2_uncached_0; // @[DCache.scala:101:7] wire [31:0] io_cpu_s2_paddr_0; // @[DCache.scala:101:7] wire io_cpu_replay_next_0; // @[DCache.scala:101:7] wire [39:0] io_cpu_s2_gpa_0; // @[DCache.scala:101:7] wire io_cpu_ordered_0; // @[DCache.scala:101:7] wire io_cpu_store_pending_0; // @[DCache.scala:101:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[DCache.scala:101:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[DCache.scala:101:7] wire io_ptw_req_valid_0; // @[DCache.scala:101:7] wire io_errors_bus_valid; // @[DCache.scala:101:7] wire [31:0] io_errors_bus_bits; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_pf_ld; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_pf_st; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_pf_inst; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ae_ld; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ae_st; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ae_inst; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ma_ld; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ma_st; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_miss; // @[DCache.scala:101:7] wire [31:0] io_tlb_port_s1_resp_paddr; // @[DCache.scala:101:7] wire [39:0] io_tlb_port_s1_resp_gpa; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_cacheable; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_must_alloc; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_prefetchable; // @[DCache.scala:101:7] wire [1:0] io_tlb_port_s1_resp_size; // @[DCache.scala:101:7] wire [4:0] io_tlb_port_s1_resp_cmd; // @[DCache.scala:101:7] wire nodeOut_a_deq_ready = nodeOut_a_ready; // @[Decoupled.scala:356:21] wire nodeOut_a_deq_valid; // @[Decoupled.scala:356:21] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[DCache.scala:101:7] wire [2:0] nodeOut_a_deq_bits_opcode; // @[Decoupled.scala:356:21] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[DCache.scala:101:7] wire [2:0] nodeOut_a_deq_bits_param; // @[Decoupled.scala:356:21] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[DCache.scala:101:7] wire [3:0] nodeOut_a_deq_bits_size; // @[Decoupled.scala:356:21] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[DCache.scala:101:7] wire nodeOut_a_deq_bits_source; // @[Decoupled.scala:356:21] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[DCache.scala:101:7] wire [31:0] nodeOut_a_deq_bits_address; // @[Decoupled.scala:356:21] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[DCache.scala:101:7] wire [7:0] nodeOut_a_deq_bits_mask; // @[Decoupled.scala:356:21] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[DCache.scala:101:7] wire [63:0] nodeOut_a_deq_bits_data; // @[Decoupled.scala:356:21] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[DCache.scala:101:7] wire _nodeOut_b_ready_T_4; // @[DCache.scala:770:44] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[DCache.scala:101:7] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[DCache.scala:101:7] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[DCache.scala:101:7] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[DCache.scala:101:7] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[DCache.scala:101:7] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[DCache.scala:101:7] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[DCache.scala:101:7] wire [63:0] s2_data_corrected; // @[package.scala:45:27] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[DCache.scala:101:7] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[DCache.scala:101:7] wire uncachedRespIdxOH_shiftAmount = nodeOut_d_bits_source; // @[OneHot.scala:64:49] wire [2:0] nodeOut_e_bits_e_sink = nodeOut_d_bits_sink; // @[Edges.scala:451:17] wire [63:0] s1_uncached_data_word = nodeOut_d_bits_data; // @[package.scala:211:50] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[DCache.scala:101:7] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[DCache.scala:101:7] wire [1:0] pma_checker_io_resp_size = pma_checker_io_req_bits_size; // @[DCache.scala:120:32] wire [4:0] pma_checker_io_resp_cmd = pma_checker_io_req_bits_cmd; // @[DCache.scala:120:32] wire [31:0] pma_checker__io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [39:0] pma_checker__io_resp_gpa_T; // @[TLB.scala:659:8] wire pma_checker__io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire pma_checker__io_resp_pf_st_T_3; // @[TLB.scala:634:48] wire pma_checker__io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire pma_checker__io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire pma_checker__io_resp_ae_st_T_1; // @[TLB.scala:642:41] wire pma_checker__io_resp_ae_inst_T_2; // @[TLB.scala:643:41] wire pma_checker__io_resp_ma_ld_T; // @[TLB.scala:645:31] wire pma_checker__io_resp_ma_st_T; // @[TLB.scala:646:31] wire pma_checker__io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire pma_checker__io_resp_must_alloc_T_1; // @[TLB.scala:649:51] wire pma_checker__io_resp_prefetchable_T_2; // @[TLB.scala:650:59] wire [39:0] pma_checker_io_req_bits_vaddr; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_req_bits_prv; // @[DCache.scala:120:32] wire pma_checker_io_req_bits_v; // @[DCache.scala:120:32] wire pma_checker_io_resp_pf_ld; // @[DCache.scala:120:32] wire pma_checker_io_resp_pf_st; // @[DCache.scala:120:32] wire pma_checker_io_resp_pf_inst; // @[DCache.scala:120:32] wire pma_checker_io_resp_ae_ld; // @[DCache.scala:120:32] wire pma_checker_io_resp_ae_st; // @[DCache.scala:120:32] wire pma_checker_io_resp_ae_inst; // @[DCache.scala:120:32] wire pma_checker_io_resp_ma_ld; // @[DCache.scala:120:32] wire pma_checker_io_resp_ma_st; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_resp_paddr; // @[DCache.scala:120:32] wire [39:0] pma_checker_io_resp_gpa; // @[DCache.scala:120:32] wire pma_checker_io_resp_cacheable; // @[DCache.scala:120:32] wire pma_checker_io_resp_must_alloc; // @[DCache.scala:120:32] wire pma_checker_io_resp_prefetchable; // @[DCache.scala:120:32] wire [26:0] pma_checker_vpn = pma_checker_io_req_bits_vaddr[38:12]; // @[TLB.scala:335:30] wire [26:0] pma_checker__mpu_ppn_T_24 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__mpu_ppn_T_28 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__sector_hits_T_3 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_11 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_19 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_27 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_35 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_43 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_51 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_59 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__superpage_hits_T = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_5 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_10 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_14 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_19 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_24 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_28 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_33 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_38 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_42 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_47 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_52 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_6 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_12 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_18 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_24 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_30 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_36 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_42 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_48 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_53 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_58 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_63 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_68 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_73 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_78 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_83 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_88 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_93 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_98 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_103 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_108 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_113 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_118 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__ppn_T_5 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__ppn_T_13 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__ppn_T_21 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__ppn_T_29 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__ppn_T_33 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__ppn_T_37 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire pma_checker_priv_s = pma_checker_io_req_bits_prv[0]; // @[TLB.scala:370:20] wire pma_checker_priv_uses_vm = ~(pma_checker_io_req_bits_prv[1]); // @[TLB.scala:372:27] wire [19:0] pma_checker__mpu_ppn_T_23; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_22; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_21; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_20; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_19; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_18; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_17; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_16; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_15; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_14; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_13; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_12; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_11; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_10; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_9; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_8; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_7; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_6; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_5; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_4; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_3; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_2; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_1; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_1 = pma_checker__mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_fragmented_superpage = pma_checker__mpu_ppn_T_1; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_2 = pma_checker__mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_c = pma_checker__mpu_ppn_T_2; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_3 = pma_checker__mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_eff = pma_checker__mpu_ppn_T_3; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_4 = pma_checker__mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_paa = pma_checker__mpu_ppn_T_4; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_5 = pma_checker__mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_pal = pma_checker__mpu_ppn_T_5; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_6 = pma_checker__mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_ppp = pma_checker__mpu_ppn_T_6; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_7 = pma_checker__mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_pr = pma_checker__mpu_ppn_T_7; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_8 = pma_checker__mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_px = pma_checker__mpu_ppn_T_8; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_9 = pma_checker__mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_pw = pma_checker__mpu_ppn_T_9; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_10 = pma_checker__mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_hr = pma_checker__mpu_ppn_T_10; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_11 = pma_checker__mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_hx = pma_checker__mpu_ppn_T_11; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_12 = pma_checker__mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_hw = pma_checker__mpu_ppn_T_12; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_13 = pma_checker__mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_sr = pma_checker__mpu_ppn_T_13; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_14 = pma_checker__mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_sx = pma_checker__mpu_ppn_T_14; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_15 = pma_checker__mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_sw = pma_checker__mpu_ppn_T_15; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_16 = pma_checker__mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_gf = pma_checker__mpu_ppn_T_16; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_17 = pma_checker__mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_pf = pma_checker__mpu_ppn_T_17; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_18 = pma_checker__mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_ae_stage2 = pma_checker__mpu_ppn_T_18; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_19 = pma_checker__mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_ae_final = pma_checker__mpu_ppn_T_19; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_20 = pma_checker__mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_ae_ptw = pma_checker__mpu_ppn_T_20; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_21 = pma_checker__mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_g = pma_checker__mpu_ppn_T_21; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_22 = pma_checker__mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_u = pma_checker__mpu_ppn_T_22; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_23 = pma_checker__mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__mpu_ppn_WIRE_ppn = pma_checker__mpu_ppn_T_23; // @[TLB.scala:170:77] wire [1:0] pma_checker_mpu_ppn_res = _pma_checker_mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25] wire [26:0] pma_checker__mpu_ppn_T_25 = {pma_checker__mpu_ppn_T_24[26:20], pma_checker__mpu_ppn_T_24[19:0] \| _pma_checker_mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__mpu_ppn_T_26 = pma_checker__mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] pma_checker__mpu_ppn_T_27 = {pma_checker_mpu_ppn_res, pma_checker__mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}] wire [26:0] pma_checker__mpu_ppn_T_29 = {pma_checker__mpu_ppn_T_28[26:20], pma_checker__mpu_ppn_T_28[19:0] \| _pma_checker_mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__mpu_ppn_T_30 = pma_checker__mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] pma_checker__mpu_ppn_T_31 = {pma_checker__mpu_ppn_T_27, pma_checker__mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}] wire [27:0] pma_checker__mpu_ppn_T_32 = pma_checker_io_req_bits_vaddr[39:12]; // @[TLB.scala:413:146] wire [27:0] pma_checker__mpu_ppn_T_33 = pma_checker__mpu_ppn_T_32; // @[TLB.scala:413:{20,146}] wire [27:0] pma_checker_mpu_ppn = pma_checker__mpu_ppn_T_33; // @[TLB.scala:412:20, :413:20] wire [11:0] pma_checker__mpu_physaddr_T = pma_checker_io_req_bits_vaddr[11:0]; // @[TLB.scala:414:52] wire [11:0] pma_checker__io_resp_paddr_T = pma_checker_io_req_bits_vaddr[11:0]; // @[TLB.scala:414:52, :652:46] wire [11:0] pma_checker__io_resp_gpa_offset_T_1 = pma_checker_io_req_bits_vaddr[11:0]; // @[TLB.scala:414:52, :658:82] wire [39:0] pma_checker_mpu_physaddr = {pma_checker_mpu_ppn, pma_checker__mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}] wire [39:0] pma_checker__homogeneous_T = pma_checker_mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] pma_checker__homogeneous_T_67 = pma_checker_mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] pma_checker__deny_access_to_debug_T_1 = pma_checker_mpu_physaddr; // @[TLB.scala:414:25] wire [2:0] pma_checker__mpu_priv_T_2 = {1'h0, pma_checker_io_req_bits_prv}; // @[TLB.scala:415:103] wire pma_checker_cacheable; // @[TLB.scala:425:41] wire pma_checker_newEntry_c = pma_checker_cacheable; // @[TLB.scala:425:41, :449:24] wire [40:0] pma_checker__homogeneous_T_1 = {1'h0, pma_checker__homogeneous_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_2 = pma_checker__homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_3 = pma_checker__homogeneous_T_2; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_4 = pma_checker__homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_50 = pma_checker__homogeneous_T_4; // @[TLBPermissions.scala:101:65] wire [39:0] _GEN = {pma_checker_mpu_physaddr[39:14], pma_checker_mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25] wire [39:0] pma_checker__homogeneous_T_5; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_5 = _GEN; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_72; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_72 = _GEN; // @[Parameters.scala:137:31] wire [40:0] pma_checker__homogeneous_T_6 = {1'h0, pma_checker__homogeneous_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_7 = pma_checker__homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_8 = pma_checker__homogeneous_T_7; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_9 = pma_checker__homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_0 = {pma_checker_mpu_physaddr[39:17], pma_checker_mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25] wire [39:0] pma_checker__homogeneous_T_10; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_10 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_60; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_60 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_77; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_77 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_109; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_109 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_116; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_116 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] pma_checker__homogeneous_T_11 = {1'h0, pma_checker__homogeneous_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_12 = pma_checker__homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_13 = pma_checker__homogeneous_T_12; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_14 = pma_checker__homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] pma_checker__homogeneous_T_15 = {pma_checker_mpu_physaddr[39:21], pma_checker_mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25] wire [40:0] pma_checker__homogeneous_T_16 = {1'h0, pma_checker__homogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_17 = pma_checker__homogeneous_T_16 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_18 = pma_checker__homogeneous_T_17; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_19 = pma_checker__homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] pma_checker__homogeneous_T_20 = {pma_checker_mpu_physaddr[39:26], pma_checker_mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25] wire [40:0] pma_checker__homogeneous_T_21 = {1'h0, pma_checker__homogeneous_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_22 = pma_checker__homogeneous_T_21 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_23 = pma_checker__homogeneous_T_22; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_24 = pma_checker__homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] pma_checker__homogeneous_T_25 = {pma_checker_mpu_physaddr[39:26], pma_checker_mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25] wire [40:0] pma_checker__homogeneous_T_26 = {1'h0, pma_checker__homogeneous_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_27 = pma_checker__homogeneous_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_28 = pma_checker__homogeneous_T_27; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_29 = pma_checker__homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {pma_checker_mpu_physaddr[39:28], pma_checker_mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25] wire [39:0] pma_checker__homogeneous_T_30; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_30 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_82; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_82 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_97; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_97 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] pma_checker__homogeneous_T_31 = {1'h0, pma_checker__homogeneous_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_32 = pma_checker__homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_33 = pma_checker__homogeneous_T_32; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_34 = pma_checker__homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] pma_checker__homogeneous_T_35 = {pma_checker_mpu_physaddr[39:28], pma_checker_mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25] wire [40:0] pma_checker__homogeneous_T_36 = {1'h0, pma_checker__homogeneous_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_37 = pma_checker__homogeneous_T_36 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_38 = pma_checker__homogeneous_T_37; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_39 = pma_checker__homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] pma_checker__homogeneous_T_40 = {pma_checker_mpu_physaddr[39:29], pma_checker_mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25] wire [40:0] pma_checker__homogeneous_T_41 = {1'h0, pma_checker__homogeneous_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_42 = pma_checker__homogeneous_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_43 = pma_checker__homogeneous_T_42; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_44 = pma_checker__homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {pma_checker_mpu_physaddr[39:32], pma_checker_mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15] wire [39:0] pma_checker__homogeneous_T_45; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_45 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_87; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_87 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_102; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_102 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] pma_checker__homogeneous_T_46 = {1'h0, pma_checker__homogeneous_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_47 = pma_checker__homogeneous_T_46 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_48 = pma_checker__homogeneous_T_47; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_49 = pma_checker__homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_51 = pma_checker__homogeneous_T_50 \| pma_checker__homogeneous_T_9; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_52 = pma_checker__homogeneous_T_51 \| pma_checker__homogeneous_T_14; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_53 = pma_checker__homogeneous_T_52 \| pma_checker__homogeneous_T_19; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_54 = pma_checker__homogeneous_T_53 \| pma_checker__homogeneous_T_24; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_55 = pma_checker__homogeneous_T_54 \| pma_checker__homogeneous_T_29; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_56 = pma_checker__homogeneous_T_55 \| pma_checker__homogeneous_T_34; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_57 = pma_checker__homogeneous_T_56 \| pma_checker__homogeneous_T_39; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_58 = pma_checker__homogeneous_T_57 \| pma_checker__homogeneous_T_44; // @[TLBPermissions.scala:101:65] wire pma_checker_homogeneous = pma_checker__homogeneous_T_58 \| pma_checker__homogeneous_T_49; // @[TLBPermissions.scala:101:65] wire [40:0] pma_checker__homogeneous_T_61 = {1'h0, pma_checker__homogeneous_T_60}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_62 = pma_checker__homogeneous_T_61 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_63 = pma_checker__homogeneous_T_62; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_64 = pma_checker__homogeneous_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_65 = pma_checker__homogeneous_T_64; // @[TLBPermissions.scala:87:66] wire pma_checker__homogeneous_T_66 = ~pma_checker__homogeneous_T_65; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] pma_checker__homogeneous_T_68 = {1'h0, pma_checker__homogeneous_T_67}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_69 = pma_checker__homogeneous_T_68 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_70 = pma_checker__homogeneous_T_69; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_71 = pma_checker__homogeneous_T_70 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_92 = pma_checker__homogeneous_T_71; // @[TLBPermissions.scala:85:66] wire [40:0] pma_checker__homogeneous_T_73 = {1'h0, pma_checker__homogeneous_T_72}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_74 = pma_checker__homogeneous_T_73 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_75 = pma_checker__homogeneous_T_74; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_76 = pma_checker__homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] pma_checker__homogeneous_T_78 = {1'h0, pma_checker__homogeneous_T_77}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_79 = pma_checker__homogeneous_T_78 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_80 = pma_checker__homogeneous_T_79; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_81 = pma_checker__homogeneous_T_80 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] pma_checker__homogeneous_T_83 = {1'h0, pma_checker__homogeneous_T_82}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_84 = pma_checker__homogeneous_T_83 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_85 = pma_checker__homogeneous_T_84; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_86 = pma_checker__homogeneous_T_85 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] pma_checker__homogeneous_T_88 = {1'h0, pma_checker__homogeneous_T_87}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_89 = pma_checker__homogeneous_T_88 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_90 = pma_checker__homogeneous_T_89; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_91 = pma_checker__homogeneous_T_90 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_93 = pma_checker__homogeneous_T_92 \| pma_checker__homogeneous_T_76; // @[TLBPermissions.scala:85:66] wire pma_checker__homogeneous_T_94 = pma_checker__homogeneous_T_93 \| pma_checker__homogeneous_T_81; // @[TLBPermissions.scala:85:66] wire pma_checker__homogeneous_T_95 = pma_checker__homogeneous_T_94 \| pma_checker__homogeneous_T_86; // @[TLBPermissions.scala:85:66] wire pma_checker__homogeneous_T_96 = pma_checker__homogeneous_T_95 \| pma_checker__homogeneous_T_91; // @[TLBPermissions.scala:85:66] wire [40:0] pma_checker__homogeneous_T_98 = {1'h0, pma_checker__homogeneous_T_97}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_99 = pma_checker__homogeneous_T_98 & 41'h8E000000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_100 = pma_checker__homogeneous_T_99; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_101 = pma_checker__homogeneous_T_100 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_107 = pma_checker__homogeneous_T_101; // @[TLBPermissions.scala:85:66] wire [40:0] pma_checker__homogeneous_T_103 = {1'h0, pma_checker__homogeneous_T_102}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_104 = pma_checker__homogeneous_T_103 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_105 = pma_checker__homogeneous_T_104; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_106 = pma_checker__homogeneous_T_105 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_108 = pma_checker__homogeneous_T_107 \| pma_checker__homogeneous_T_106; // @[TLBPermissions.scala:85:66] wire [40:0] pma_checker__homogeneous_T_110 = {1'h0, pma_checker__homogeneous_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_111 = pma_checker__homogeneous_T_110 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_112 = pma_checker__homogeneous_T_111; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_113 = pma_checker__homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_114 = pma_checker__homogeneous_T_113; // @[TLBPermissions.scala:87:66] wire pma_checker__homogeneous_T_115 = ~pma_checker__homogeneous_T_114; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] pma_checker__homogeneous_T_117 = {1'h0, pma_checker__homogeneous_T_116}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_118 = pma_checker__homogeneous_T_117 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_119 = pma_checker__homogeneous_T_118; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_120 = pma_checker__homogeneous_T_119 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_121 = pma_checker__homogeneous_T_120; // @[TLBPermissions.scala:87:66] wire pma_checker__homogeneous_T_122 = ~pma_checker__homogeneous_T_121; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] pma_checker__deny_access_to_debug_T_2 = {1'h0, pma_checker__deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__deny_access_to_debug_T_3 = pma_checker__deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__deny_access_to_debug_T_4 = pma_checker__deny_access_to_debug_T_3; // @[Parameters.scala:137:46] wire pma_checker__deny_access_to_debug_T_5 = pma_checker__deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker_deny_access_to_debug = pma_checker__deny_access_to_debug_T_5; // @[TLB.scala:428:50] wire pma_checker__prot_r_T = ~pma_checker_deny_access_to_debug; // @[TLB.scala:428:50, :429:33] wire pma_checker__prot_r_T_1 = _pma_checker_pma_io_resp_r & pma_checker__prot_r_T; // @[TLB.scala:422:19, :429:{30,33}] wire pma_checker__prot_w_T = ~pma_checker_deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33] wire pma_checker__prot_w_T_1 = _pma_checker_pma_io_resp_w & pma_checker__prot_w_T; // @[TLB.scala:422:19, :430:{30,33}] wire pma_checker__prot_x_T = ~pma_checker_deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33] wire pma_checker__prot_x_T_1 = _pma_checker_pma_io_resp_x & pma_checker__prot_x_T; // @[TLB.scala:422:19, :434:{30,33}] wire [24:0] pma_checker__sector_hits_T_4 = pma_checker__sector_hits_T_3[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_5 = pma_checker__sector_hits_T_4 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_7 = pma_checker__sector_hits_T_5 & pma_checker__sector_hits_T_6; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_12 = pma_checker__sector_hits_T_11[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_13 = pma_checker__sector_hits_T_12 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_15 = pma_checker__sector_hits_T_13 & pma_checker__sector_hits_T_14; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_20 = pma_checker__sector_hits_T_19[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_21 = pma_checker__sector_hits_T_20 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_23 = pma_checker__sector_hits_T_21 & pma_checker__sector_hits_T_22; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_28 = pma_checker__sector_hits_T_27[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_29 = pma_checker__sector_hits_T_28 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_31 = pma_checker__sector_hits_T_29 & pma_checker__sector_hits_T_30; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_36 = pma_checker__sector_hits_T_35[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_37 = pma_checker__sector_hits_T_36 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_39 = pma_checker__sector_hits_T_37 & pma_checker__sector_hits_T_38; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_44 = pma_checker__sector_hits_T_43[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_45 = pma_checker__sector_hits_T_44 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_47 = pma_checker__sector_hits_T_45 & pma_checker__sector_hits_T_46; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_52 = pma_checker__sector_hits_T_51[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_53 = pma_checker__sector_hits_T_52 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_55 = pma_checker__sector_hits_T_53 & pma_checker__sector_hits_T_54; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_60 = pma_checker__sector_hits_T_59[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_61 = pma_checker__sector_hits_T_60 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_63 = pma_checker__sector_hits_T_61 & pma_checker__sector_hits_T_62; // @[TLB.scala:174:{86,95,105}] wire [8:0] pma_checker__superpage_hits_T_1 = pma_checker__superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_2 = pma_checker__superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_3 = pma_checker__superpage_hits_T_2; // @[TLB.scala:183:{40,79}] wire pma_checker_superpage_hits_ignore_1 = pma_checker__superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__superpage_hits_T_6 = pma_checker__superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_7 = pma_checker__superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_8 = pma_checker_superpage_hits_ignore_1 \| pma_checker__superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__superpage_hits_T_11 = pma_checker__superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_12 = pma_checker__superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__superpage_hits_T_15 = pma_checker__superpage_hits_T_14[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_16 = pma_checker__superpage_hits_T_15 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_17 = pma_checker__superpage_hits_T_16; // @[TLB.scala:183:{40,79}] wire pma_checker_superpage_hits_ignore_4 = pma_checker__superpage_hits_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__superpage_hits_T_20 = pma_checker__superpage_hits_T_19[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_21 = pma_checker__superpage_hits_T_20 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_22 = pma_checker_superpage_hits_ignore_4 \| pma_checker__superpage_hits_T_21; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__superpage_hits_T_25 = pma_checker__superpage_hits_T_24[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_26 = pma_checker__superpage_hits_T_25 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__superpage_hits_T_29 = pma_checker__superpage_hits_T_28[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_30 = pma_checker__superpage_hits_T_29 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_31 = pma_checker__superpage_hits_T_30; // @[TLB.scala:183:{40,79}] wire pma_checker_superpage_hits_ignore_7 = pma_checker__superpage_hits_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__superpage_hits_T_34 = pma_checker__superpage_hits_T_33[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_35 = pma_checker__superpage_hits_T_34 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_36 = pma_checker_superpage_hits_ignore_7 \| pma_checker__superpage_hits_T_35; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__superpage_hits_T_39 = pma_checker__superpage_hits_T_38[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_40 = pma_checker__superpage_hits_T_39 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__superpage_hits_T_43 = pma_checker__superpage_hits_T_42[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_44 = pma_checker__superpage_hits_T_43 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_45 = pma_checker__superpage_hits_T_44; // @[TLB.scala:183:{40,79}] wire pma_checker_superpage_hits_ignore_10 = pma_checker__superpage_hits_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__superpage_hits_T_48 = pma_checker__superpage_hits_T_47[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_49 = pma_checker__superpage_hits_T_48 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_50 = pma_checker_superpage_hits_ignore_10 \| pma_checker__superpage_hits_T_49; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__superpage_hits_T_53 = pma_checker__superpage_hits_T_52[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_54 = pma_checker__superpage_hits_T_53 == 9'h0; // @[TLB.scala:183:{58,79}] wire [1:0] pma_checker_hitsVec_idx = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_1 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_2 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_3 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_4 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_5 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_6 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_7 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_24 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_48 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_72 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_96 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_120 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_144 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_168 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [24:0] pma_checker__hitsVec_T_1 = pma_checker__hitsVec_T[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_2 = pma_checker__hitsVec_T_1 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_4 = pma_checker__hitsVec_T_2 & pma_checker__hitsVec_T_3; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_7 = pma_checker__hitsVec_T_6[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_8 = pma_checker__hitsVec_T_7 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_10 = pma_checker__hitsVec_T_8 & pma_checker__hitsVec_T_9; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_13 = pma_checker__hitsVec_T_12[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_14 = pma_checker__hitsVec_T_13 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_16 = pma_checker__hitsVec_T_14 & pma_checker__hitsVec_T_15; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_19 = pma_checker__hitsVec_T_18[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_20 = pma_checker__hitsVec_T_19 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_22 = pma_checker__hitsVec_T_20 & pma_checker__hitsVec_T_21; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_25 = pma_checker__hitsVec_T_24[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_26 = pma_checker__hitsVec_T_25 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_28 = pma_checker__hitsVec_T_26 & pma_checker__hitsVec_T_27; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_31 = pma_checker__hitsVec_T_30[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_32 = pma_checker__hitsVec_T_31 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_34 = pma_checker__hitsVec_T_32 & pma_checker__hitsVec_T_33; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_37 = pma_checker__hitsVec_T_36[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_38 = pma_checker__hitsVec_T_37 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_40 = pma_checker__hitsVec_T_38 & pma_checker__hitsVec_T_39; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_43 = pma_checker__hitsVec_T_42[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_44 = pma_checker__hitsVec_T_43 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_46 = pma_checker__hitsVec_T_44 & pma_checker__hitsVec_T_45; // @[TLB.scala:174:{86,95,105}] wire [8:0] pma_checker__hitsVec_T_49 = pma_checker__hitsVec_T_48[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_50 = pma_checker__hitsVec_T_49 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_51 = pma_checker__hitsVec_T_50; // @[TLB.scala:183:{40,79}] wire pma_checker_hitsVec_ignore_1 = pma_checker__hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__hitsVec_T_54 = pma_checker__hitsVec_T_53[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_55 = pma_checker__hitsVec_T_54 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_56 = pma_checker_hitsVec_ignore_1 \| pma_checker__hitsVec_T_55; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__hitsVec_T_59 = pma_checker__hitsVec_T_58[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_60 = pma_checker__hitsVec_T_59 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__hitsVec_T_64 = pma_checker__hitsVec_T_63[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_65 = pma_checker__hitsVec_T_64 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_66 = pma_checker__hitsVec_T_65; // @[TLB.scala:183:{40,79}] wire pma_checker_hitsVec_ignore_4 = pma_checker__hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__hitsVec_T_69 = pma_checker__hitsVec_T_68[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_70 = pma_checker__hitsVec_T_69 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_71 = pma_checker_hitsVec_ignore_4 \| pma_checker__hitsVec_T_70; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__hitsVec_T_74 = pma_checker__hitsVec_T_73[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_75 = pma_checker__hitsVec_T_74 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__hitsVec_T_79 = pma_checker__hitsVec_T_78[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_80 = pma_checker__hitsVec_T_79 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_81 = pma_checker__hitsVec_T_80; // @[TLB.scala:183:{40,79}] wire pma_checker_hitsVec_ignore_7 = pma_checker__hitsVec_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__hitsVec_T_84 = pma_checker__hitsVec_T_83[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_85 = pma_checker__hitsVec_T_84 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_86 = pma_checker_hitsVec_ignore_7 \| pma_checker__hitsVec_T_85; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__hitsVec_T_89 = pma_checker__hitsVec_T_88[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_90 = pma_checker__hitsVec_T_89 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__hitsVec_T_94 = pma_checker__hitsVec_T_93[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_95 = pma_checker__hitsVec_T_94 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_96 = pma_checker__hitsVec_T_95; // @[TLB.scala:183:{40,79}] wire pma_checker_hitsVec_ignore_10 = pma_checker__hitsVec_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__hitsVec_T_99 = pma_checker__hitsVec_T_98[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_100 = pma_checker__hitsVec_T_99 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_101 = pma_checker_hitsVec_ignore_10 \| pma_checker__hitsVec_T_100; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__hitsVec_T_104 = pma_checker__hitsVec_T_103[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_105 = pma_checker__hitsVec_T_104 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__hitsVec_T_109 = pma_checker__hitsVec_T_108[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_110 = pma_checker__hitsVec_T_109 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_111 = pma_checker__hitsVec_T_110; // @[TLB.scala:183:{40,79}] wire [8:0] pma_checker__hitsVec_T_114 = pma_checker__hitsVec_T_113[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_115 = pma_checker__hitsVec_T_114 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__hitsVec_T_119 = pma_checker__hitsVec_T_118[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_120 = pma_checker__hitsVec_T_119 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker_newEntry_ppp; // @[TLB.scala:449:24] wire pma_checker_newEntry_pal; // @[TLB.scala:449:24] wire pma_checker_newEntry_paa; // @[TLB.scala:449:24] wire pma_checker_newEntry_eff; // @[TLB.scala:449:24] wire [1:0] _GEN_3 = {pma_checker_newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24] wire [1:0] pma_checker_special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_special_entry_data_0_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_0_data_0_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_1_data_0_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_2_data_0_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_3_data_0_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_0_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_1_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_2_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_3_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_4_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_5_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_6_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_7_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] _GEN_4 = {pma_checker_newEntry_pal, pma_checker_newEntry_paa}; // @[TLB.scala:217:24, :449:24] wire [1:0] pma_checker_special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_special_entry_data_0_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_1_data_0_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_2_data_0_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_3_data_0_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_0_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_1_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_2_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_3_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_4_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_5_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_6_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_7_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [2:0] pma_checker_special_entry_data_0_lo_lo_hi = {pma_checker_special_entry_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_special_entry_data_0_lo_lo = {pma_checker_special_entry_data_0_lo_lo_hi, pma_checker_special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] _GEN_5 = {2'h0, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] pma_checker_special_entry_data_0_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_special_entry_data_0_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_0_data_0_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_1_data_0_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_2_data_0_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_3_data_0_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_0_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_1_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_2_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_3_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_4_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_5_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_6_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_7_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [5:0] pma_checker_special_entry_data_0_lo_hi = {3'h0, pma_checker_special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_special_entry_data_0_lo = {pma_checker_special_entry_data_0_lo_hi, pma_checker_special_entry_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__special_entry_data_0_T = {31'h0, pma_checker_special_entry_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_lo_lo_hi = {pma_checker_superpage_entries_0_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_superpage_entries_0_data_0_lo_lo = {pma_checker_superpage_entries_0_data_0_lo_lo_hi, pma_checker_superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_0_data_0_lo_hi = {3'h0, pma_checker_superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_superpage_entries_0_data_0_lo = {pma_checker_superpage_entries_0_data_0_lo_hi, pma_checker_superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__superpage_entries_0_data_0_T = {31'h0, pma_checker_superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_lo_lo_hi = {pma_checker_superpage_entries_1_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_superpage_entries_1_data_0_lo_lo = {pma_checker_superpage_entries_1_data_0_lo_lo_hi, pma_checker_superpage_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_1_data_0_lo_hi = {3'h0, pma_checker_superpage_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_superpage_entries_1_data_0_lo = {pma_checker_superpage_entries_1_data_0_lo_hi, pma_checker_superpage_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__superpage_entries_1_data_0_T = {31'h0, pma_checker_superpage_entries_1_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_lo_lo_hi = {pma_checker_superpage_entries_2_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_superpage_entries_2_data_0_lo_lo = {pma_checker_superpage_entries_2_data_0_lo_lo_hi, pma_checker_superpage_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_2_data_0_lo_hi = {3'h0, pma_checker_superpage_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_superpage_entries_2_data_0_lo = {pma_checker_superpage_entries_2_data_0_lo_hi, pma_checker_superpage_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__superpage_entries_2_data_0_T = {31'h0, pma_checker_superpage_entries_2_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_lo_lo_hi = {pma_checker_superpage_entries_3_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_superpage_entries_3_data_0_lo_lo = {pma_checker_superpage_entries_3_data_0_lo_lo_hi, pma_checker_superpage_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_3_data_0_lo_hi = {3'h0, pma_checker_superpage_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_superpage_entries_3_data_0_lo = {pma_checker_superpage_entries_3_data_0_lo_hi, pma_checker_superpage_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__superpage_entries_3_data_0_T = {31'h0, pma_checker_superpage_entries_3_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_lo_lo_hi = {pma_checker_sectored_entries_0_0_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_0_data_lo_lo = {pma_checker_sectored_entries_0_0_data_lo_lo_hi, pma_checker_sectored_entries_0_0_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_0_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_0_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_0_data_lo = {pma_checker_sectored_entries_0_0_data_lo_hi, pma_checker_sectored_entries_0_0_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_0_data_T = {31'h0, pma_checker_sectored_entries_0_0_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_lo_lo_hi = {pma_checker_sectored_entries_0_1_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_1_data_lo_lo = {pma_checker_sectored_entries_0_1_data_lo_lo_hi, pma_checker_sectored_entries_0_1_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_1_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_1_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_1_data_lo = {pma_checker_sectored_entries_0_1_data_lo_hi, pma_checker_sectored_entries_0_1_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_1_data_T = {31'h0, pma_checker_sectored_entries_0_1_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_lo_lo_hi = {pma_checker_sectored_entries_0_2_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_2_data_lo_lo = {pma_checker_sectored_entries_0_2_data_lo_lo_hi, pma_checker_sectored_entries_0_2_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_2_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_2_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_2_data_lo = {pma_checker_sectored_entries_0_2_data_lo_hi, pma_checker_sectored_entries_0_2_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_2_data_T = {31'h0, pma_checker_sectored_entries_0_2_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_lo_lo_hi = {pma_checker_sectored_entries_0_3_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_3_data_lo_lo = {pma_checker_sectored_entries_0_3_data_lo_lo_hi, pma_checker_sectored_entries_0_3_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_3_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_3_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_3_data_lo = {pma_checker_sectored_entries_0_3_data_lo_hi, pma_checker_sectored_entries_0_3_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_3_data_T = {31'h0, pma_checker_sectored_entries_0_3_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_lo_lo_hi = {pma_checker_sectored_entries_0_4_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_4_data_lo_lo = {pma_checker_sectored_entries_0_4_data_lo_lo_hi, pma_checker_sectored_entries_0_4_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_4_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_4_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_4_data_lo = {pma_checker_sectored_entries_0_4_data_lo_hi, pma_checker_sectored_entries_0_4_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_4_data_T = {31'h0, pma_checker_sectored_entries_0_4_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_lo_lo_hi = {pma_checker_sectored_entries_0_5_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_5_data_lo_lo = {pma_checker_sectored_entries_0_5_data_lo_lo_hi, pma_checker_sectored_entries_0_5_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_5_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_5_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_5_data_lo = {pma_checker_sectored_entries_0_5_data_lo_hi, pma_checker_sectored_entries_0_5_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_5_data_T = {31'h0, pma_checker_sectored_entries_0_5_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_lo_lo_hi = {pma_checker_sectored_entries_0_6_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_6_data_lo_lo = {pma_checker_sectored_entries_0_6_data_lo_lo_hi, pma_checker_sectored_entries_0_6_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_6_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_6_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_6_data_lo = {pma_checker_sectored_entries_0_6_data_lo_hi, pma_checker_sectored_entries_0_6_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_6_data_T = {31'h0, pma_checker_sectored_entries_0_6_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_lo_lo_hi = {pma_checker_sectored_entries_0_7_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_7_data_lo_lo = {pma_checker_sectored_entries_0_7_data_lo_lo_hi, pma_checker_sectored_entries_0_7_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_7_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_7_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_7_data_lo = {pma_checker_sectored_entries_0_7_data_lo_hi, pma_checker_sectored_entries_0_7_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_7_data_T = {31'h0, pma_checker_sectored_entries_0_7_data_lo}; // @[TLB.scala:217:24] wire [19:0] pma_checker__entries_T_23; // @[TLB.scala:170:77] wire pma_checker__entries_T_22; // @[TLB.scala:170:77] wire pma_checker__entries_T_21; // @[TLB.scala:170:77] wire pma_checker__entries_T_20; // @[TLB.scala:170:77] wire pma_checker__entries_T_19; // @[TLB.scala:170:77] wire pma_checker__entries_T_18; // @[TLB.scala:170:77] wire pma_checker__entries_T_17; // @[TLB.scala:170:77] wire pma_checker__entries_T_16; // @[TLB.scala:170:77] wire pma_checker__entries_T_15; // @[TLB.scala:170:77] wire pma_checker__entries_T_14; // @[TLB.scala:170:77] wire pma_checker__entries_T_13; // @[TLB.scala:170:77] wire pma_checker__entries_T_12; // @[TLB.scala:170:77] wire pma_checker__entries_T_11; // @[TLB.scala:170:77] wire pma_checker__entries_T_10; // @[TLB.scala:170:77] wire pma_checker__entries_T_9; // @[TLB.scala:170:77] wire pma_checker__entries_T_8; // @[TLB.scala:170:77] wire pma_checker__entries_T_7; // @[TLB.scala:170:77] wire pma_checker__entries_T_6; // @[TLB.scala:170:77] wire pma_checker__entries_T_5; // @[TLB.scala:170:77] wire pma_checker__entries_T_4; // @[TLB.scala:170:77] wire pma_checker__entries_T_3; // @[TLB.scala:170:77] wire pma_checker__entries_T_2; // @[TLB.scala:170:77] wire pma_checker__entries_T_1; // @[TLB.scala:170:77] assign pma_checker__entries_T_1 = pma_checker__entries_WIRE_1[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_fragmented_superpage = pma_checker__entries_T_1; // @[TLB.scala:170:77] assign pma_checker__entries_T_2 = pma_checker__entries_WIRE_1[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_c = pma_checker__entries_T_2; // @[TLB.scala:170:77] assign pma_checker__entries_T_3 = pma_checker__entries_WIRE_1[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_eff = pma_checker__entries_T_3; // @[TLB.scala:170:77] assign pma_checker__entries_T_4 = pma_checker__entries_WIRE_1[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_paa = pma_checker__entries_T_4; // @[TLB.scala:170:77] assign pma_checker__entries_T_5 = pma_checker__entries_WIRE_1[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_pal = pma_checker__entries_T_5; // @[TLB.scala:170:77] assign pma_checker__entries_T_6 = pma_checker__entries_WIRE_1[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_ppp = pma_checker__entries_T_6; // @[TLB.scala:170:77] assign pma_checker__entries_T_7 = pma_checker__entries_WIRE_1[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_pr = pma_checker__entries_T_7; // @[TLB.scala:170:77] assign pma_checker__entries_T_8 = pma_checker__entries_WIRE_1[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_px = pma_checker__entries_T_8; // @[TLB.scala:170:77] assign pma_checker__entries_T_9 = pma_checker__entries_WIRE_1[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_pw = pma_checker__entries_T_9; // @[TLB.scala:170:77] assign pma_checker__entries_T_10 = pma_checker__entries_WIRE_1[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_hr = pma_checker__entries_T_10; // @[TLB.scala:170:77] assign pma_checker__entries_T_11 = pma_checker__entries_WIRE_1[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_hx = pma_checker__entries_T_11; // @[TLB.scala:170:77] assign pma_checker__entries_T_12 = pma_checker__entries_WIRE_1[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_hw = pma_checker__entries_T_12; // @[TLB.scala:170:77] assign pma_checker__entries_T_13 = pma_checker__entries_WIRE_1[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_sr = pma_checker__entries_T_13; // @[TLB.scala:170:77] assign pma_checker__entries_T_14 = pma_checker__entries_WIRE_1[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_sx = pma_checker__entries_T_14; // @[TLB.scala:170:77] assign pma_checker__entries_T_15 = pma_checker__entries_WIRE_1[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_sw = pma_checker__entries_T_15; // @[TLB.scala:170:77] assign pma_checker__entries_T_16 = pma_checker__entries_WIRE_1[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_gf = pma_checker__entries_T_16; // @[TLB.scala:170:77] assign pma_checker__entries_T_17 = pma_checker__entries_WIRE_1[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_pf = pma_checker__entries_T_17; // @[TLB.scala:170:77] assign pma_checker__entries_T_18 = pma_checker__entries_WIRE_1[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_ae_stage2 = pma_checker__entries_T_18; // @[TLB.scala:170:77] assign pma_checker__entries_T_19 = pma_checker__entries_WIRE_1[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_ae_final = pma_checker__entries_T_19; // @[TLB.scala:170:77] assign pma_checker__entries_T_20 = pma_checker__entries_WIRE_1[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_ae_ptw = pma_checker__entries_T_20; // @[TLB.scala:170:77] assign pma_checker__entries_T_21 = pma_checker__entries_WIRE_1[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_g = pma_checker__entries_T_21; // @[TLB.scala:170:77] assign pma_checker__entries_T_22 = pma_checker__entries_WIRE_1[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_u = pma_checker__entries_T_22; // @[TLB.scala:170:77] assign pma_checker__entries_T_23 = pma_checker__entries_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_ppn = pma_checker__entries_T_23; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_47; // @[TLB.scala:170:77] wire pma_checker__entries_T_46; // @[TLB.scala:170:77] wire pma_checker__entries_T_45; // @[TLB.scala:170:77] wire pma_checker__entries_T_44; // @[TLB.scala:170:77] wire pma_checker__entries_T_43; // @[TLB.scala:170:77] wire pma_checker__entries_T_42; // @[TLB.scala:170:77] wire pma_checker__entries_T_41; // @[TLB.scala:170:77] wire pma_checker__entries_T_40; // @[TLB.scala:170:77] wire pma_checker__entries_T_39; // @[TLB.scala:170:77] wire pma_checker__entries_T_38; // @[TLB.scala:170:77] wire pma_checker__entries_T_37; // @[TLB.scala:170:77] wire pma_checker__entries_T_36; // @[TLB.scala:170:77] wire pma_checker__entries_T_35; // @[TLB.scala:170:77] wire pma_checker__entries_T_34; // @[TLB.scala:170:77] wire pma_checker__entries_T_33; // @[TLB.scala:170:77] wire pma_checker__entries_T_32; // @[TLB.scala:170:77] wire pma_checker__entries_T_31; // @[TLB.scala:170:77] wire pma_checker__entries_T_30; // @[TLB.scala:170:77] wire pma_checker__entries_T_29; // @[TLB.scala:170:77] wire pma_checker__entries_T_28; // @[TLB.scala:170:77] wire pma_checker__entries_T_27; // @[TLB.scala:170:77] wire pma_checker__entries_T_26; // @[TLB.scala:170:77] wire pma_checker__entries_T_25; // @[TLB.scala:170:77] assign pma_checker__entries_T_25 = pma_checker__entries_WIRE_3[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_fragmented_superpage = pma_checker__entries_T_25; // @[TLB.scala:170:77] assign pma_checker__entries_T_26 = pma_checker__entries_WIRE_3[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_c = pma_checker__entries_T_26; // @[TLB.scala:170:77] assign pma_checker__entries_T_27 = pma_checker__entries_WIRE_3[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_eff = pma_checker__entries_T_27; // @[TLB.scala:170:77] assign pma_checker__entries_T_28 = pma_checker__entries_WIRE_3[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_paa = pma_checker__entries_T_28; // @[TLB.scala:170:77] assign pma_checker__entries_T_29 = pma_checker__entries_WIRE_3[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_pal = pma_checker__entries_T_29; // @[TLB.scala:170:77] assign pma_checker__entries_T_30 = pma_checker__entries_WIRE_3[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_ppp = pma_checker__entries_T_30; // @[TLB.scala:170:77] assign pma_checker__entries_T_31 = pma_checker__entries_WIRE_3[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_pr = pma_checker__entries_T_31; // @[TLB.scala:170:77] assign pma_checker__entries_T_32 = pma_checker__entries_WIRE_3[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_px = pma_checker__entries_T_32; // @[TLB.scala:170:77] assign pma_checker__entries_T_33 = pma_checker__entries_WIRE_3[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_pw = pma_checker__entries_T_33; // @[TLB.scala:170:77] assign pma_checker__entries_T_34 = pma_checker__entries_WIRE_3[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_hr = pma_checker__entries_T_34; // @[TLB.scala:170:77] assign pma_checker__entries_T_35 = pma_checker__entries_WIRE_3[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_hx = pma_checker__entries_T_35; // @[TLB.scala:170:77] assign pma_checker__entries_T_36 = pma_checker__entries_WIRE_3[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_hw = pma_checker__entries_T_36; // @[TLB.scala:170:77] assign pma_checker__entries_T_37 = pma_checker__entries_WIRE_3[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_sr = pma_checker__entries_T_37; // @[TLB.scala:170:77] assign pma_checker__entries_T_38 = pma_checker__entries_WIRE_3[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_sx = pma_checker__entries_T_38; // @[TLB.scala:170:77] assign pma_checker__entries_T_39 = pma_checker__entries_WIRE_3[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_sw = pma_checker__entries_T_39; // @[TLB.scala:170:77] assign pma_checker__entries_T_40 = pma_checker__entries_WIRE_3[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_gf = pma_checker__entries_T_40; // @[TLB.scala:170:77] assign pma_checker__entries_T_41 = pma_checker__entries_WIRE_3[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_pf = pma_checker__entries_T_41; // @[TLB.scala:170:77] assign pma_checker__entries_T_42 = pma_checker__entries_WIRE_3[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_ae_stage2 = pma_checker__entries_T_42; // @[TLB.scala:170:77] assign pma_checker__entries_T_43 = pma_checker__entries_WIRE_3[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_ae_final = pma_checker__entries_T_43; // @[TLB.scala:170:77] assign pma_checker__entries_T_44 = pma_checker__entries_WIRE_3[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_ae_ptw = pma_checker__entries_T_44; // @[TLB.scala:170:77] assign pma_checker__entries_T_45 = pma_checker__entries_WIRE_3[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_g = pma_checker__entries_T_45; // @[TLB.scala:170:77] assign pma_checker__entries_T_46 = pma_checker__entries_WIRE_3[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_u = pma_checker__entries_T_46; // @[TLB.scala:170:77] assign pma_checker__entries_T_47 = pma_checker__entries_WIRE_3[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_2_ppn = pma_checker__entries_T_47; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_71; // @[TLB.scala:170:77] wire pma_checker__entries_T_70; // @[TLB.scala:170:77] wire pma_checker__entries_T_69; // @[TLB.scala:170:77] wire pma_checker__entries_T_68; // @[TLB.scala:170:77] wire pma_checker__entries_T_67; // @[TLB.scala:170:77] wire pma_checker__entries_T_66; // @[TLB.scala:170:77] wire pma_checker__entries_T_65; // @[TLB.scala:170:77] wire pma_checker__entries_T_64; // @[TLB.scala:170:77] wire pma_checker__entries_T_63; // @[TLB.scala:170:77] wire pma_checker__entries_T_62; // @[TLB.scala:170:77] wire pma_checker__entries_T_61; // @[TLB.scala:170:77] wire pma_checker__entries_T_60; // @[TLB.scala:170:77] wire pma_checker__entries_T_59; // @[TLB.scala:170:77] wire pma_checker__entries_T_58; // @[TLB.scala:170:77] wire pma_checker__entries_T_57; // @[TLB.scala:170:77] wire pma_checker__entries_T_56; // @[TLB.scala:170:77] wire pma_checker__entries_T_55; // @[TLB.scala:170:77] wire pma_checker__entries_T_54; // @[TLB.scala:170:77] wire pma_checker__entries_T_53; // @[TLB.scala:170:77] wire pma_checker__entries_T_52; // @[TLB.scala:170:77] wire pma_checker__entries_T_51; // @[TLB.scala:170:77] wire pma_checker__entries_T_50; // @[TLB.scala:170:77] wire pma_checker__entries_T_49; // @[TLB.scala:170:77] assign pma_checker__entries_T_49 = pma_checker__entries_WIRE_5[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_fragmented_superpage = pma_checker__entries_T_49; // @[TLB.scala:170:77] assign pma_checker__entries_T_50 = pma_checker__entries_WIRE_5[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_c = pma_checker__entries_T_50; // @[TLB.scala:170:77] assign pma_checker__entries_T_51 = pma_checker__entries_WIRE_5[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_eff = pma_checker__entries_T_51; // @[TLB.scala:170:77] assign pma_checker__entries_T_52 = pma_checker__entries_WIRE_5[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_paa = pma_checker__entries_T_52; // @[TLB.scala:170:77] assign pma_checker__entries_T_53 = pma_checker__entries_WIRE_5[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_pal = pma_checker__entries_T_53; // @[TLB.scala:170:77] assign pma_checker__entries_T_54 = pma_checker__entries_WIRE_5[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_ppp = pma_checker__entries_T_54; // @[TLB.scala:170:77] assign pma_checker__entries_T_55 = pma_checker__entries_WIRE_5[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_pr = pma_checker__entries_T_55; // @[TLB.scala:170:77] assign pma_checker__entries_T_56 = pma_checker__entries_WIRE_5[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_px = pma_checker__entries_T_56; // @[TLB.scala:170:77] assign pma_checker__entries_T_57 = pma_checker__entries_WIRE_5[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_pw = pma_checker__entries_T_57; // @[TLB.scala:170:77] assign pma_checker__entries_T_58 = pma_checker__entries_WIRE_5[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_hr = pma_checker__entries_T_58; // @[TLB.scala:170:77] assign pma_checker__entries_T_59 = pma_checker__entries_WIRE_5[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_hx = pma_checker__entries_T_59; // @[TLB.scala:170:77] assign pma_checker__entries_T_60 = pma_checker__entries_WIRE_5[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_hw = pma_checker__entries_T_60; // @[TLB.scala:170:77] assign pma_checker__entries_T_61 = pma_checker__entries_WIRE_5[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_sr = pma_checker__entries_T_61; // @[TLB.scala:170:77] assign pma_checker__entries_T_62 = pma_checker__entries_WIRE_5[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_sx = pma_checker__entries_T_62; // @[TLB.scala:170:77] assign pma_checker__entries_T_63 = pma_checker__entries_WIRE_5[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_sw = pma_checker__entries_T_63; // @[TLB.scala:170:77] assign pma_checker__entries_T_64 = pma_checker__entries_WIRE_5[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_gf = pma_checker__entries_T_64; // @[TLB.scala:170:77] assign pma_checker__entries_T_65 = pma_checker__entries_WIRE_5[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_pf = pma_checker__entries_T_65; // @[TLB.scala:170:77] assign pma_checker__entries_T_66 = pma_checker__entries_WIRE_5[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_ae_stage2 = pma_checker__entries_T_66; // @[TLB.scala:170:77] assign pma_checker__entries_T_67 = pma_checker__entries_WIRE_5[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_ae_final = pma_checker__entries_T_67; // @[TLB.scala:170:77] assign pma_checker__entries_T_68 = pma_checker__entries_WIRE_5[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_ae_ptw = pma_checker__entries_T_68; // @[TLB.scala:170:77] assign pma_checker__entries_T_69 = pma_checker__entries_WIRE_5[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_g = pma_checker__entries_T_69; // @[TLB.scala:170:77] assign pma_checker__entries_T_70 = pma_checker__entries_WIRE_5[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_u = pma_checker__entries_T_70; // @[TLB.scala:170:77] assign pma_checker__entries_T_71 = pma_checker__entries_WIRE_5[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_4_ppn = pma_checker__entries_T_71; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_95; // @[TLB.scala:170:77] wire pma_checker__entries_T_94; // @[TLB.scala:170:77] wire pma_checker__entries_T_93; // @[TLB.scala:170:77] wire pma_checker__entries_T_92; // @[TLB.scala:170:77] wire pma_checker__entries_T_91; // @[TLB.scala:170:77] wire pma_checker__entries_T_90; // @[TLB.scala:170:77] wire pma_checker__entries_T_89; // @[TLB.scala:170:77] wire pma_checker__entries_T_88; // @[TLB.scala:170:77] wire pma_checker__entries_T_87; // @[TLB.scala:170:77] wire pma_checker__entries_T_86; // @[TLB.scala:170:77] wire pma_checker__entries_T_85; // @[TLB.scala:170:77] wire pma_checker__entries_T_84; // @[TLB.scala:170:77] wire pma_checker__entries_T_83; // @[TLB.scala:170:77] wire pma_checker__entries_T_82; // @[TLB.scala:170:77] wire pma_checker__entries_T_81; // @[TLB.scala:170:77] wire pma_checker__entries_T_80; // @[TLB.scala:170:77] wire pma_checker__entries_T_79; // @[TLB.scala:170:77] wire pma_checker__entries_T_78; // @[TLB.scala:170:77] wire pma_checker__entries_T_77; // @[TLB.scala:170:77] wire pma_checker__entries_T_76; // @[TLB.scala:170:77] wire pma_checker__entries_T_75; // @[TLB.scala:170:77] wire pma_checker__entries_T_74; // @[TLB.scala:170:77] wire pma_checker__entries_T_73; // @[TLB.scala:170:77] assign pma_checker__entries_T_73 = pma_checker__entries_WIRE_7[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_fragmented_superpage = pma_checker__entries_T_73; // @[TLB.scala:170:77] assign pma_checker__entries_T_74 = pma_checker__entries_WIRE_7[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_c = pma_checker__entries_T_74; // @[TLB.scala:170:77] assign pma_checker__entries_T_75 = pma_checker__entries_WIRE_7[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_eff = pma_checker__entries_T_75; // @[TLB.scala:170:77] assign pma_checker__entries_T_76 = pma_checker__entries_WIRE_7[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_paa = pma_checker__entries_T_76; // @[TLB.scala:170:77] assign pma_checker__entries_T_77 = pma_checker__entries_WIRE_7[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_pal = pma_checker__entries_T_77; // @[TLB.scala:170:77] assign pma_checker__entries_T_78 = pma_checker__entries_WIRE_7[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_ppp = pma_checker__entries_T_78; // @[TLB.scala:170:77] assign pma_checker__entries_T_79 = pma_checker__entries_WIRE_7[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_pr = pma_checker__entries_T_79; // @[TLB.scala:170:77] assign pma_checker__entries_T_80 = pma_checker__entries_WIRE_7[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_px = pma_checker__entries_T_80; // @[TLB.scala:170:77] assign pma_checker__entries_T_81 = pma_checker__entries_WIRE_7[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_pw = pma_checker__entries_T_81; // @[TLB.scala:170:77] assign pma_checker__entries_T_82 = pma_checker__entries_WIRE_7[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_hr = pma_checker__entries_T_82; // @[TLB.scala:170:77] assign pma_checker__entries_T_83 = pma_checker__entries_WIRE_7[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_hx = pma_checker__entries_T_83; // @[TLB.scala:170:77] assign pma_checker__entries_T_84 = pma_checker__entries_WIRE_7[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_hw = pma_checker__entries_T_84; // @[TLB.scala:170:77] assign pma_checker__entries_T_85 = pma_checker__entries_WIRE_7[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_sr = pma_checker__entries_T_85; // @[TLB.scala:170:77] assign pma_checker__entries_T_86 = pma_checker__entries_WIRE_7[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_sx = pma_checker__entries_T_86; // @[TLB.scala:170:77] assign pma_checker__entries_T_87 = pma_checker__entries_WIRE_7[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_sw = pma_checker__entries_T_87; // @[TLB.scala:170:77] assign pma_checker__entries_T_88 = pma_checker__entries_WIRE_7[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_gf = pma_checker__entries_T_88; // @[TLB.scala:170:77] assign pma_checker__entries_T_89 = pma_checker__entries_WIRE_7[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_pf = pma_checker__entries_T_89; // @[TLB.scala:170:77] assign pma_checker__entries_T_90 = pma_checker__entries_WIRE_7[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_ae_stage2 = pma_checker__entries_T_90; // @[TLB.scala:170:77] assign pma_checker__entries_T_91 = pma_checker__entries_WIRE_7[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_ae_final = pma_checker__entries_T_91; // @[TLB.scala:170:77] assign pma_checker__entries_T_92 = pma_checker__entries_WIRE_7[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_ae_ptw = pma_checker__entries_T_92; // @[TLB.scala:170:77] assign pma_checker__entries_T_93 = pma_checker__entries_WIRE_7[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_g = pma_checker__entries_T_93; // @[TLB.scala:170:77] assign pma_checker__entries_T_94 = pma_checker__entries_WIRE_7[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_u = pma_checker__entries_T_94; // @[TLB.scala:170:77] assign pma_checker__entries_T_95 = pma_checker__entries_WIRE_7[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_6_ppn = pma_checker__entries_T_95; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_119; // @[TLB.scala:170:77] wire pma_checker__entries_T_118; // @[TLB.scala:170:77] wire pma_checker__entries_T_117; // @[TLB.scala:170:77] wire pma_checker__entries_T_116; // @[TLB.scala:170:77] wire pma_checker__entries_T_115; // @[TLB.scala:170:77] wire pma_checker__entries_T_114; // @[TLB.scala:170:77] wire pma_checker__entries_T_113; // @[TLB.scala:170:77] wire pma_checker__entries_T_112; // @[TLB.scala:170:77] wire pma_checker__entries_T_111; // @[TLB.scala:170:77] wire pma_checker__entries_T_110; // @[TLB.scala:170:77] wire pma_checker__entries_T_109; // @[TLB.scala:170:77] wire pma_checker__entries_T_108; // @[TLB.scala:170:77] wire pma_checker__entries_T_107; // @[TLB.scala:170:77] wire pma_checker__entries_T_106; // @[TLB.scala:170:77] wire pma_checker__entries_T_105; // @[TLB.scala:170:77] wire pma_checker__entries_T_104; // @[TLB.scala:170:77] wire pma_checker__entries_T_103; // @[TLB.scala:170:77] wire pma_checker__entries_T_102; // @[TLB.scala:170:77] wire pma_checker__entries_T_101; // @[TLB.scala:170:77] wire pma_checker__entries_T_100; // @[TLB.scala:170:77] wire pma_checker__entries_T_99; // @[TLB.scala:170:77] wire pma_checker__entries_T_98; // @[TLB.scala:170:77] wire pma_checker__entries_T_97; // @[TLB.scala:170:77] assign pma_checker__entries_T_97 = pma_checker__entries_WIRE_9[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_fragmented_superpage = pma_checker__entries_T_97; // @[TLB.scala:170:77] assign pma_checker__entries_T_98 = pma_checker__entries_WIRE_9[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_c = pma_checker__entries_T_98; // @[TLB.scala:170:77] assign pma_checker__entries_T_99 = pma_checker__entries_WIRE_9[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_eff = pma_checker__entries_T_99; // @[TLB.scala:170:77] assign pma_checker__entries_T_100 = pma_checker__entries_WIRE_9[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_paa = pma_checker__entries_T_100; // @[TLB.scala:170:77] assign pma_checker__entries_T_101 = pma_checker__entries_WIRE_9[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_pal = pma_checker__entries_T_101; // @[TLB.scala:170:77] assign pma_checker__entries_T_102 = pma_checker__entries_WIRE_9[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_ppp = pma_checker__entries_T_102; // @[TLB.scala:170:77] assign pma_checker__entries_T_103 = pma_checker__entries_WIRE_9[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_pr = pma_checker__entries_T_103; // @[TLB.scala:170:77] assign pma_checker__entries_T_104 = pma_checker__entries_WIRE_9[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_px = pma_checker__entries_T_104; // @[TLB.scala:170:77] assign pma_checker__entries_T_105 = pma_checker__entries_WIRE_9[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_pw = pma_checker__entries_T_105; // @[TLB.scala:170:77] assign pma_checker__entries_T_106 = pma_checker__entries_WIRE_9[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_hr = pma_checker__entries_T_106; // @[TLB.scala:170:77] assign pma_checker__entries_T_107 = pma_checker__entries_WIRE_9[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_hx = pma_checker__entries_T_107; // @[TLB.scala:170:77] assign pma_checker__entries_T_108 = pma_checker__entries_WIRE_9[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_hw = pma_checker__entries_T_108; // @[TLB.scala:170:77] assign pma_checker__entries_T_109 = pma_checker__entries_WIRE_9[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_sr = pma_checker__entries_T_109; // @[TLB.scala:170:77] assign pma_checker__entries_T_110 = pma_checker__entries_WIRE_9[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_sx = pma_checker__entries_T_110; // @[TLB.scala:170:77] assign pma_checker__entries_T_111 = pma_checker__entries_WIRE_9[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_sw = pma_checker__entries_T_111; // @[TLB.scala:170:77] assign pma_checker__entries_T_112 = pma_checker__entries_WIRE_9[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_gf = pma_checker__entries_T_112; // @[TLB.scala:170:77] assign pma_checker__entries_T_113 = pma_checker__entries_WIRE_9[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_pf = pma_checker__entries_T_113; // @[TLB.scala:170:77] assign pma_checker__entries_T_114 = pma_checker__entries_WIRE_9[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_ae_stage2 = pma_checker__entries_T_114; // @[TLB.scala:170:77] assign pma_checker__entries_T_115 = pma_checker__entries_WIRE_9[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_ae_final = pma_checker__entries_T_115; // @[TLB.scala:170:77] assign pma_checker__entries_T_116 = pma_checker__entries_WIRE_9[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_ae_ptw = pma_checker__entries_T_116; // @[TLB.scala:170:77] assign pma_checker__entries_T_117 = pma_checker__entries_WIRE_9[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_g = pma_checker__entries_T_117; // @[TLB.scala:170:77] assign pma_checker__entries_T_118 = pma_checker__entries_WIRE_9[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_u = pma_checker__entries_T_118; // @[TLB.scala:170:77] assign pma_checker__entries_T_119 = pma_checker__entries_WIRE_9[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_8_ppn = pma_checker__entries_T_119; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_143; // @[TLB.scala:170:77] wire pma_checker__entries_T_142; // @[TLB.scala:170:77] wire pma_checker__entries_T_141; // @[TLB.scala:170:77] wire pma_checker__entries_T_140; // @[TLB.scala:170:77] wire pma_checker__entries_T_139; // @[TLB.scala:170:77] wire pma_checker__entries_T_138; // @[TLB.scala:170:77] wire pma_checker__entries_T_137; // @[TLB.scala:170:77] wire pma_checker__entries_T_136; // @[TLB.scala:170:77] wire pma_checker__entries_T_135; // @[TLB.scala:170:77] wire pma_checker__entries_T_134; // @[TLB.scala:170:77] wire pma_checker__entries_T_133; // @[TLB.scala:170:77] wire pma_checker__entries_T_132; // @[TLB.scala:170:77] wire pma_checker__entries_T_131; // @[TLB.scala:170:77] wire pma_checker__entries_T_130; // @[TLB.scala:170:77] wire pma_checker__entries_T_129; // @[TLB.scala:170:77] wire pma_checker__entries_T_128; // @[TLB.scala:170:77] wire pma_checker__entries_T_127; // @[TLB.scala:170:77] wire pma_checker__entries_T_126; // @[TLB.scala:170:77] wire pma_checker__entries_T_125; // @[TLB.scala:170:77] wire pma_checker__entries_T_124; // @[TLB.scala:170:77] wire pma_checker__entries_T_123; // @[TLB.scala:170:77] wire pma_checker__entries_T_122; // @[TLB.scala:170:77] wire pma_checker__entries_T_121; // @[TLB.scala:170:77] assign pma_checker__entries_T_121 = pma_checker__entries_WIRE_11[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_fragmented_superpage = pma_checker__entries_T_121; // @[TLB.scala:170:77] assign pma_checker__entries_T_122 = pma_checker__entries_WIRE_11[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_c = pma_checker__entries_T_122; // @[TLB.scala:170:77] assign pma_checker__entries_T_123 = pma_checker__entries_WIRE_11[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_eff = pma_checker__entries_T_123; // @[TLB.scala:170:77] assign pma_checker__entries_T_124 = pma_checker__entries_WIRE_11[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_paa = pma_checker__entries_T_124; // @[TLB.scala:170:77] assign pma_checker__entries_T_125 = pma_checker__entries_WIRE_11[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_pal = pma_checker__entries_T_125; // @[TLB.scala:170:77] assign pma_checker__entries_T_126 = pma_checker__entries_WIRE_11[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_ppp = pma_checker__entries_T_126; // @[TLB.scala:170:77] assign pma_checker__entries_T_127 = pma_checker__entries_WIRE_11[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_pr = pma_checker__entries_T_127; // @[TLB.scala:170:77] assign pma_checker__entries_T_128 = pma_checker__entries_WIRE_11[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_px = pma_checker__entries_T_128; // @[TLB.scala:170:77] assign pma_checker__entries_T_129 = pma_checker__entries_WIRE_11[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_pw = pma_checker__entries_T_129; // @[TLB.scala:170:77] assign pma_checker__entries_T_130 = pma_checker__entries_WIRE_11[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_hr = pma_checker__entries_T_130; // @[TLB.scala:170:77] assign pma_checker__entries_T_131 = pma_checker__entries_WIRE_11[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_hx = pma_checker__entries_T_131; // @[TLB.scala:170:77] assign pma_checker__entries_T_132 = pma_checker__entries_WIRE_11[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_hw = pma_checker__entries_T_132; // @[TLB.scala:170:77] assign pma_checker__entries_T_133 = pma_checker__entries_WIRE_11[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_sr = pma_checker__entries_T_133; // @[TLB.scala:170:77] assign pma_checker__entries_T_134 = pma_checker__entries_WIRE_11[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_sx = pma_checker__entries_T_134; // @[TLB.scala:170:77] assign pma_checker__entries_T_135 = pma_checker__entries_WIRE_11[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_sw = pma_checker__entries_T_135; // @[TLB.scala:170:77] assign pma_checker__entries_T_136 = pma_checker__entries_WIRE_11[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_gf = pma_checker__entries_T_136; // @[TLB.scala:170:77] assign pma_checker__entries_T_137 = pma_checker__entries_WIRE_11[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_pf = pma_checker__entries_T_137; // @[TLB.scala:170:77] assign pma_checker__entries_T_138 = pma_checker__entries_WIRE_11[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_ae_stage2 = pma_checker__entries_T_138; // @[TLB.scala:170:77] assign pma_checker__entries_T_139 = pma_checker__entries_WIRE_11[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_ae_final = pma_checker__entries_T_139; // @[TLB.scala:170:77] assign pma_checker__entries_T_140 = pma_checker__entries_WIRE_11[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_ae_ptw = pma_checker__entries_T_140; // @[TLB.scala:170:77] assign pma_checker__entries_T_141 = pma_checker__entries_WIRE_11[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_g = pma_checker__entries_T_141; // @[TLB.scala:170:77] assign pma_checker__entries_T_142 = pma_checker__entries_WIRE_11[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_u = pma_checker__entries_T_142; // @[TLB.scala:170:77] assign pma_checker__entries_T_143 = pma_checker__entries_WIRE_11[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_10_ppn = pma_checker__entries_T_143; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_167; // @[TLB.scala:170:77] wire pma_checker__entries_T_166; // @[TLB.scala:170:77] wire pma_checker__entries_T_165; // @[TLB.scala:170:77] wire pma_checker__entries_T_164; // @[TLB.scala:170:77] wire pma_checker__entries_T_163; // @[TLB.scala:170:77] wire pma_checker__entries_T_162; // @[TLB.scala:170:77] wire pma_checker__entries_T_161; // @[TLB.scala:170:77] wire pma_checker__entries_T_160; // @[TLB.scala:170:77] wire pma_checker__entries_T_159; // @[TLB.scala:170:77] wire pma_checker__entries_T_158; // @[TLB.scala:170:77] wire pma_checker__entries_T_157; // @[TLB.scala:170:77] wire pma_checker__entries_T_156; // @[TLB.scala:170:77] wire pma_checker__entries_T_155; // @[TLB.scala:170:77] wire pma_checker__entries_T_154; // @[TLB.scala:170:77] wire pma_checker__entries_T_153; // @[TLB.scala:170:77] wire pma_checker__entries_T_152; // @[TLB.scala:170:77] wire pma_checker__entries_T_151; // @[TLB.scala:170:77] wire pma_checker__entries_T_150; // @[TLB.scala:170:77] wire pma_checker__entries_T_149; // @[TLB.scala:170:77] wire pma_checker__entries_T_148; // @[TLB.scala:170:77] wire pma_checker__entries_T_147; // @[TLB.scala:170:77] wire pma_checker__entries_T_146; // @[TLB.scala:170:77] wire pma_checker__entries_T_145; // @[TLB.scala:170:77] assign pma_checker__entries_T_145 = pma_checker__entries_WIRE_13[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_fragmented_superpage = pma_checker__entries_T_145; // @[TLB.scala:170:77] assign pma_checker__entries_T_146 = pma_checker__entries_WIRE_13[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_c = pma_checker__entries_T_146; // @[TLB.scala:170:77] assign pma_checker__entries_T_147 = pma_checker__entries_WIRE_13[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_eff = pma_checker__entries_T_147; // @[TLB.scala:170:77] assign pma_checker__entries_T_148 = pma_checker__entries_WIRE_13[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_paa = pma_checker__entries_T_148; // @[TLB.scala:170:77] assign pma_checker__entries_T_149 = pma_checker__entries_WIRE_13[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_pal = pma_checker__entries_T_149; // @[TLB.scala:170:77] assign pma_checker__entries_T_150 = pma_checker__entries_WIRE_13[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_ppp = pma_checker__entries_T_150; // @[TLB.scala:170:77] assign pma_checker__entries_T_151 = pma_checker__entries_WIRE_13[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_pr = pma_checker__entries_T_151; // @[TLB.scala:170:77] assign pma_checker__entries_T_152 = pma_checker__entries_WIRE_13[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_px = pma_checker__entries_T_152; // @[TLB.scala:170:77] assign pma_checker__entries_T_153 = pma_checker__entries_WIRE_13[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_pw = pma_checker__entries_T_153; // @[TLB.scala:170:77] assign pma_checker__entries_T_154 = pma_checker__entries_WIRE_13[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_hr = pma_checker__entries_T_154; // @[TLB.scala:170:77] assign pma_checker__entries_T_155 = pma_checker__entries_WIRE_13[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_hx = pma_checker__entries_T_155; // @[TLB.scala:170:77] assign pma_checker__entries_T_156 = pma_checker__entries_WIRE_13[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_hw = pma_checker__entries_T_156; // @[TLB.scala:170:77] assign pma_checker__entries_T_157 = pma_checker__entries_WIRE_13[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_sr = pma_checker__entries_T_157; // @[TLB.scala:170:77] assign pma_checker__entries_T_158 = pma_checker__entries_WIRE_13[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_sx = pma_checker__entries_T_158; // @[TLB.scala:170:77] assign pma_checker__entries_T_159 = pma_checker__entries_WIRE_13[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_sw = pma_checker__entries_T_159; // @[TLB.scala:170:77] assign pma_checker__entries_T_160 = pma_checker__entries_WIRE_13[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_gf = pma_checker__entries_T_160; // @[TLB.scala:170:77] assign pma_checker__entries_T_161 = pma_checker__entries_WIRE_13[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_pf = pma_checker__entries_T_161; // @[TLB.scala:170:77] assign pma_checker__entries_T_162 = pma_checker__entries_WIRE_13[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_ae_stage2 = pma_checker__entries_T_162; // @[TLB.scala:170:77] assign pma_checker__entries_T_163 = pma_checker__entries_WIRE_13[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_ae_final = pma_checker__entries_T_163; // @[TLB.scala:170:77] assign pma_checker__entries_T_164 = pma_checker__entries_WIRE_13[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_ae_ptw = pma_checker__entries_T_164; // @[TLB.scala:170:77] assign pma_checker__entries_T_165 = pma_checker__entries_WIRE_13[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_g = pma_checker__entries_T_165; // @[TLB.scala:170:77] assign pma_checker__entries_T_166 = pma_checker__entries_WIRE_13[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_u = pma_checker__entries_T_166; // @[TLB.scala:170:77] assign pma_checker__entries_T_167 = pma_checker__entries_WIRE_13[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_12_ppn = pma_checker__entries_T_167; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_191; // @[TLB.scala:170:77] wire pma_checker__entries_T_190; // @[TLB.scala:170:77] wire pma_checker__entries_T_189; // @[TLB.scala:170:77] wire pma_checker__entries_T_188; // @[TLB.scala:170:77] wire pma_checker__entries_T_187; // @[TLB.scala:170:77] wire pma_checker__entries_T_186; // @[TLB.scala:170:77] wire pma_checker__entries_T_185; // @[TLB.scala:170:77] wire pma_checker__entries_T_184; // @[TLB.scala:170:77] wire pma_checker__entries_T_183; // @[TLB.scala:170:77] wire pma_checker__entries_T_182; // @[TLB.scala:170:77] wire pma_checker__entries_T_181; // @[TLB.scala:170:77] wire pma_checker__entries_T_180; // @[TLB.scala:170:77] wire pma_checker__entries_T_179; // @[TLB.scala:170:77] wire pma_checker__entries_T_178; // @[TLB.scala:170:77] wire pma_checker__entries_T_177; // @[TLB.scala:170:77] wire pma_checker__entries_T_176; // @[TLB.scala:170:77] wire pma_checker__entries_T_175; // @[TLB.scala:170:77] wire pma_checker__entries_T_174; // @[TLB.scala:170:77] wire pma_checker__entries_T_173; // @[TLB.scala:170:77] wire pma_checker__entries_T_172; // @[TLB.scala:170:77] wire pma_checker__entries_T_171; // @[TLB.scala:170:77] wire pma_checker__entries_T_170; // @[TLB.scala:170:77] wire pma_checker__entries_T_169; // @[TLB.scala:170:77] assign pma_checker__entries_T_169 = pma_checker__entries_WIRE_15[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_fragmented_superpage = pma_checker__entries_T_169; // @[TLB.scala:170:77] assign pma_checker__entries_T_170 = pma_checker__entries_WIRE_15[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_c = pma_checker__entries_T_170; // @[TLB.scala:170:77] assign pma_checker__entries_T_171 = pma_checker__entries_WIRE_15[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_eff = pma_checker__entries_T_171; // @[TLB.scala:170:77] assign pma_checker__entries_T_172 = pma_checker__entries_WIRE_15[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_paa = pma_checker__entries_T_172; // @[TLB.scala:170:77] assign pma_checker__entries_T_173 = pma_checker__entries_WIRE_15[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_pal = pma_checker__entries_T_173; // @[TLB.scala:170:77] assign pma_checker__entries_T_174 = pma_checker__entries_WIRE_15[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_ppp = pma_checker__entries_T_174; // @[TLB.scala:170:77] assign pma_checker__entries_T_175 = pma_checker__entries_WIRE_15[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_pr = pma_checker__entries_T_175; // @[TLB.scala:170:77] assign pma_checker__entries_T_176 = pma_checker__entries_WIRE_15[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_px = pma_checker__entries_T_176; // @[TLB.scala:170:77] assign pma_checker__entries_T_177 = pma_checker__entries_WIRE_15[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_pw = pma_checker__entries_T_177; // @[TLB.scala:170:77] assign pma_checker__entries_T_178 = pma_checker__entries_WIRE_15[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_hr = pma_checker__entries_T_178; // @[TLB.scala:170:77] assign pma_checker__entries_T_179 = pma_checker__entries_WIRE_15[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_hx = pma_checker__entries_T_179; // @[TLB.scala:170:77] assign pma_checker__entries_T_180 = pma_checker__entries_WIRE_15[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_hw = pma_checker__entries_T_180; // @[TLB.scala:170:77] assign pma_checker__entries_T_181 = pma_checker__entries_WIRE_15[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_sr = pma_checker__entries_T_181; // @[TLB.scala:170:77] assign pma_checker__entries_T_182 = pma_checker__entries_WIRE_15[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_sx = pma_checker__entries_T_182; // @[TLB.scala:170:77] assign pma_checker__entries_T_183 = pma_checker__entries_WIRE_15[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_sw = pma_checker__entries_T_183; // @[TLB.scala:170:77] assign pma_checker__entries_T_184 = pma_checker__entries_WIRE_15[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_gf = pma_checker__entries_T_184; // @[TLB.scala:170:77] assign pma_checker__entries_T_185 = pma_checker__entries_WIRE_15[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_pf = pma_checker__entries_T_185; // @[TLB.scala:170:77] assign pma_checker__entries_T_186 = pma_checker__entries_WIRE_15[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_ae_stage2 = pma_checker__entries_T_186; // @[TLB.scala:170:77] assign pma_checker__entries_T_187 = pma_checker__entries_WIRE_15[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_ae_final = pma_checker__entries_T_187; // @[TLB.scala:170:77] assign pma_checker__entries_T_188 = pma_checker__entries_WIRE_15[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_ae_ptw = pma_checker__entries_T_188; // @[TLB.scala:170:77] assign pma_checker__entries_T_189 = pma_checker__entries_WIRE_15[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_g = pma_checker__entries_T_189; // @[TLB.scala:170:77] assign pma_checker__entries_T_190 = pma_checker__entries_WIRE_15[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_u = pma_checker__entries_T_190; // @[TLB.scala:170:77] assign pma_checker__entries_T_191 = pma_checker__entries_WIRE_15[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_14_ppn = pma_checker__entries_T_191; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_214; // @[TLB.scala:170:77] wire pma_checker__entries_T_213; // @[TLB.scala:170:77] wire pma_checker__entries_T_212; // @[TLB.scala:170:77] wire pma_checker__entries_T_211; // @[TLB.scala:170:77] wire pma_checker__entries_T_210; // @[TLB.scala:170:77] wire pma_checker__entries_T_209; // @[TLB.scala:170:77] wire pma_checker__entries_T_208; // @[TLB.scala:170:77] wire pma_checker__entries_T_207; // @[TLB.scala:170:77] wire pma_checker__entries_T_206; // @[TLB.scala:170:77] wire pma_checker__entries_T_205; // @[TLB.scala:170:77] wire pma_checker__entries_T_204; // @[TLB.scala:170:77] wire pma_checker__entries_T_203; // @[TLB.scala:170:77] wire pma_checker__entries_T_202; // @[TLB.scala:170:77] wire pma_checker__entries_T_201; // @[TLB.scala:170:77] wire pma_checker__entries_T_200; // @[TLB.scala:170:77] wire pma_checker__entries_T_199; // @[TLB.scala:170:77] wire pma_checker__entries_T_198; // @[TLB.scala:170:77] wire pma_checker__entries_T_197; // @[TLB.scala:170:77] wire pma_checker__entries_T_196; // @[TLB.scala:170:77] wire pma_checker__entries_T_195; // @[TLB.scala:170:77] wire pma_checker__entries_T_194; // @[TLB.scala:170:77] wire pma_checker__entries_T_193; // @[TLB.scala:170:77] wire pma_checker__entries_T_192; // @[TLB.scala:170:77] assign pma_checker__entries_T_192 = pma_checker__entries_WIRE_17[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_fragmented_superpage = pma_checker__entries_T_192; // @[TLB.scala:170:77] assign pma_checker__entries_T_193 = pma_checker__entries_WIRE_17[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_c = pma_checker__entries_T_193; // @[TLB.scala:170:77] assign pma_checker__entries_T_194 = pma_checker__entries_WIRE_17[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_eff = pma_checker__entries_T_194; // @[TLB.scala:170:77] assign pma_checker__entries_T_195 = pma_checker__entries_WIRE_17[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_paa = pma_checker__entries_T_195; // @[TLB.scala:170:77] assign pma_checker__entries_T_196 = pma_checker__entries_WIRE_17[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_pal = pma_checker__entries_T_196; // @[TLB.scala:170:77] assign pma_checker__entries_T_197 = pma_checker__entries_WIRE_17[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_ppp = pma_checker__entries_T_197; // @[TLB.scala:170:77] assign pma_checker__entries_T_198 = pma_checker__entries_WIRE_17[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_pr = pma_checker__entries_T_198; // @[TLB.scala:170:77] assign pma_checker__entries_T_199 = pma_checker__entries_WIRE_17[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_px = pma_checker__entries_T_199; // @[TLB.scala:170:77] assign pma_checker__entries_T_200 = pma_checker__entries_WIRE_17[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_pw = pma_checker__entries_T_200; // @[TLB.scala:170:77] assign pma_checker__entries_T_201 = pma_checker__entries_WIRE_17[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_hr = pma_checker__entries_T_201; // @[TLB.scala:170:77] assign pma_checker__entries_T_202 = pma_checker__entries_WIRE_17[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_hx = pma_checker__entries_T_202; // @[TLB.scala:170:77] assign pma_checker__entries_T_203 = pma_checker__entries_WIRE_17[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_hw = pma_checker__entries_T_203; // @[TLB.scala:170:77] assign pma_checker__entries_T_204 = pma_checker__entries_WIRE_17[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_sr = pma_checker__entries_T_204; // @[TLB.scala:170:77] assign pma_checker__entries_T_205 = pma_checker__entries_WIRE_17[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_sx = pma_checker__entries_T_205; // @[TLB.scala:170:77] assign pma_checker__entries_T_206 = pma_checker__entries_WIRE_17[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_sw = pma_checker__entries_T_206; // @[TLB.scala:170:77] assign pma_checker__entries_T_207 = pma_checker__entries_WIRE_17[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_gf = pma_checker__entries_T_207; // @[TLB.scala:170:77] assign pma_checker__entries_T_208 = pma_checker__entries_WIRE_17[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_pf = pma_checker__entries_T_208; // @[TLB.scala:170:77] assign pma_checker__entries_T_209 = pma_checker__entries_WIRE_17[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_ae_stage2 = pma_checker__entries_T_209; // @[TLB.scala:170:77] assign pma_checker__entries_T_210 = pma_checker__entries_WIRE_17[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_ae_final = pma_checker__entries_T_210; // @[TLB.scala:170:77] assign pma_checker__entries_T_211 = pma_checker__entries_WIRE_17[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_ae_ptw = pma_checker__entries_T_211; // @[TLB.scala:170:77] assign pma_checker__entries_T_212 = pma_checker__entries_WIRE_17[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_g = pma_checker__entries_T_212; // @[TLB.scala:170:77] assign pma_checker__entries_T_213 = pma_checker__entries_WIRE_17[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_u = pma_checker__entries_T_213; // @[TLB.scala:170:77] assign pma_checker__entries_T_214 = pma_checker__entries_WIRE_17[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_16_ppn = pma_checker__entries_T_214; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_237; // @[TLB.scala:170:77] wire pma_checker__entries_T_236; // @[TLB.scala:170:77] wire pma_checker__entries_T_235; // @[TLB.scala:170:77] wire pma_checker__entries_T_234; // @[TLB.scala:170:77] wire pma_checker__entries_T_233; // @[TLB.scala:170:77] wire pma_checker__entries_T_232; // @[TLB.scala:170:77] wire pma_checker__entries_T_231; // @[TLB.scala:170:77] wire pma_checker__entries_T_230; // @[TLB.scala:170:77] wire pma_checker__entries_T_229; // @[TLB.scala:170:77] wire pma_checker__entries_T_228; // @[TLB.scala:170:77] wire pma_checker__entries_T_227; // @[TLB.scala:170:77] wire pma_checker__entries_T_226; // @[TLB.scala:170:77] wire pma_checker__entries_T_225; // @[TLB.scala:170:77] wire pma_checker__entries_T_224; // @[TLB.scala:170:77] wire pma_checker__entries_T_223; // @[TLB.scala:170:77] wire pma_checker__entries_T_222; // @[TLB.scala:170:77] wire pma_checker__entries_T_221; // @[TLB.scala:170:77] wire pma_checker__entries_T_220; // @[TLB.scala:170:77] wire pma_checker__entries_T_219; // @[TLB.scala:170:77] wire pma_checker__entries_T_218; // @[TLB.scala:170:77] wire pma_checker__entries_T_217; // @[TLB.scala:170:77] wire pma_checker__entries_T_216; // @[TLB.scala:170:77] wire pma_checker__entries_T_215; // @[TLB.scala:170:77] assign pma_checker__entries_T_215 = pma_checker__entries_WIRE_19[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_fragmented_superpage = pma_checker__entries_T_215; // @[TLB.scala:170:77] assign pma_checker__entries_T_216 = pma_checker__entries_WIRE_19[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_c = pma_checker__entries_T_216; // @[TLB.scala:170:77] assign pma_checker__entries_T_217 = pma_checker__entries_WIRE_19[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_eff = pma_checker__entries_T_217; // @[TLB.scala:170:77] assign pma_checker__entries_T_218 = pma_checker__entries_WIRE_19[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_paa = pma_checker__entries_T_218; // @[TLB.scala:170:77] assign pma_checker__entries_T_219 = pma_checker__entries_WIRE_19[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_pal = pma_checker__entries_T_219; // @[TLB.scala:170:77] assign pma_checker__entries_T_220 = pma_checker__entries_WIRE_19[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_ppp = pma_checker__entries_T_220; // @[TLB.scala:170:77] assign pma_checker__entries_T_221 = pma_checker__entries_WIRE_19[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_pr = pma_checker__entries_T_221; // @[TLB.scala:170:77] assign pma_checker__entries_T_222 = pma_checker__entries_WIRE_19[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_px = pma_checker__entries_T_222; // @[TLB.scala:170:77] assign pma_checker__entries_T_223 = pma_checker__entries_WIRE_19[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_pw = pma_checker__entries_T_223; // @[TLB.scala:170:77] assign pma_checker__entries_T_224 = pma_checker__entries_WIRE_19[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_hr = pma_checker__entries_T_224; // @[TLB.scala:170:77] assign pma_checker__entries_T_225 = pma_checker__entries_WIRE_19[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_hx = pma_checker__entries_T_225; // @[TLB.scala:170:77] assign pma_checker__entries_T_226 = pma_checker__entries_WIRE_19[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_hw = pma_checker__entries_T_226; // @[TLB.scala:170:77] assign pma_checker__entries_T_227 = pma_checker__entries_WIRE_19[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_sr = pma_checker__entries_T_227; // @[TLB.scala:170:77] assign pma_checker__entries_T_228 = pma_checker__entries_WIRE_19[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_sx = pma_checker__entries_T_228; // @[TLB.scala:170:77] assign pma_checker__entries_T_229 = pma_checker__entries_WIRE_19[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_sw = pma_checker__entries_T_229; // @[TLB.scala:170:77] assign pma_checker__entries_T_230 = pma_checker__entries_WIRE_19[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_gf = pma_checker__entries_T_230; // @[TLB.scala:170:77] assign pma_checker__entries_T_231 = pma_checker__entries_WIRE_19[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_pf = pma_checker__entries_T_231; // @[TLB.scala:170:77] assign pma_checker__entries_T_232 = pma_checker__entries_WIRE_19[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_ae_stage2 = pma_checker__entries_T_232; // @[TLB.scala:170:77] assign pma_checker__entries_T_233 = pma_checker__entries_WIRE_19[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_ae_final = pma_checker__entries_T_233; // @[TLB.scala:170:77] assign pma_checker__entries_T_234 = pma_checker__entries_WIRE_19[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_ae_ptw = pma_checker__entries_T_234; // @[TLB.scala:170:77] assign pma_checker__entries_T_235 = pma_checker__entries_WIRE_19[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_g = pma_checker__entries_T_235; // @[TLB.scala:170:77] assign pma_checker__entries_T_236 = pma_checker__entries_WIRE_19[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_u = pma_checker__entries_T_236; // @[TLB.scala:170:77] assign pma_checker__entries_T_237 = pma_checker__entries_WIRE_19[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_18_ppn = pma_checker__entries_T_237; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_260; // @[TLB.scala:170:77] wire pma_checker__entries_T_259; // @[TLB.scala:170:77] wire pma_checker__entries_T_258; // @[TLB.scala:170:77] wire pma_checker__entries_T_257; // @[TLB.scala:170:77] wire pma_checker__entries_T_256; // @[TLB.scala:170:77] wire pma_checker__entries_T_255; // @[TLB.scala:170:77] wire pma_checker__entries_T_254; // @[TLB.scala:170:77] wire pma_checker__entries_T_253; // @[TLB.scala:170:77] wire pma_checker__entries_T_252; // @[TLB.scala:170:77] wire pma_checker__entries_T_251; // @[TLB.scala:170:77] wire pma_checker__entries_T_250; // @[TLB.scala:170:77] wire pma_checker__entries_T_249; // @[TLB.scala:170:77] wire pma_checker__entries_T_248; // @[TLB.scala:170:77] wire pma_checker__entries_T_247; // @[TLB.scala:170:77] wire pma_checker__entries_T_246; // @[TLB.scala:170:77] wire pma_checker__entries_T_245; // @[TLB.scala:170:77] wire pma_checker__entries_T_244; // @[TLB.scala:170:77] wire pma_checker__entries_T_243; // @[TLB.scala:170:77] wire pma_checker__entries_T_242; // @[TLB.scala:170:77] wire pma_checker__entries_T_241; // @[TLB.scala:170:77] wire pma_checker__entries_T_240; // @[TLB.scala:170:77] wire pma_checker__entries_T_239; // @[TLB.scala:170:77] wire pma_checker__entries_T_238; // @[TLB.scala:170:77] assign pma_checker__entries_T_238 = pma_checker__entries_WIRE_21[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_fragmented_superpage = pma_checker__entries_T_238; // @[TLB.scala:170:77] assign pma_checker__entries_T_239 = pma_checker__entries_WIRE_21[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_c = pma_checker__entries_T_239; // @[TLB.scala:170:77] assign pma_checker__entries_T_240 = pma_checker__entries_WIRE_21[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_eff = pma_checker__entries_T_240; // @[TLB.scala:170:77] assign pma_checker__entries_T_241 = pma_checker__entries_WIRE_21[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_paa = pma_checker__entries_T_241; // @[TLB.scala:170:77] assign pma_checker__entries_T_242 = pma_checker__entries_WIRE_21[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_pal = pma_checker__entries_T_242; // @[TLB.scala:170:77] assign pma_checker__entries_T_243 = pma_checker__entries_WIRE_21[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_ppp = pma_checker__entries_T_243; // @[TLB.scala:170:77] assign pma_checker__entries_T_244 = pma_checker__entries_WIRE_21[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_pr = pma_checker__entries_T_244; // @[TLB.scala:170:77] assign pma_checker__entries_T_245 = pma_checker__entries_WIRE_21[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_px = pma_checker__entries_T_245; // @[TLB.scala:170:77] assign pma_checker__entries_T_246 = pma_checker__entries_WIRE_21[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_pw = pma_checker__entries_T_246; // @[TLB.scala:170:77] assign pma_checker__entries_T_247 = pma_checker__entries_WIRE_21[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_hr = pma_checker__entries_T_247; // @[TLB.scala:170:77] assign pma_checker__entries_T_248 = pma_checker__entries_WIRE_21[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_hx = pma_checker__entries_T_248; // @[TLB.scala:170:77] assign pma_checker__entries_T_249 = pma_checker__entries_WIRE_21[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_hw = pma_checker__entries_T_249; // @[TLB.scala:170:77] assign pma_checker__entries_T_250 = pma_checker__entries_WIRE_21[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_sr = pma_checker__entries_T_250; // @[TLB.scala:170:77] assign pma_checker__entries_T_251 = pma_checker__entries_WIRE_21[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_sx = pma_checker__entries_T_251; // @[TLB.scala:170:77] assign pma_checker__entries_T_252 = pma_checker__entries_WIRE_21[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_sw = pma_checker__entries_T_252; // @[TLB.scala:170:77] assign pma_checker__entries_T_253 = pma_checker__entries_WIRE_21[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_gf = pma_checker__entries_T_253; // @[TLB.scala:170:77] assign pma_checker__entries_T_254 = pma_checker__entries_WIRE_21[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_pf = pma_checker__entries_T_254; // @[TLB.scala:170:77] assign pma_checker__entries_T_255 = pma_checker__entries_WIRE_21[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_ae_stage2 = pma_checker__entries_T_255; // @[TLB.scala:170:77] assign pma_checker__entries_T_256 = pma_checker__entries_WIRE_21[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_ae_final = pma_checker__entries_T_256; // @[TLB.scala:170:77] assign pma_checker__entries_T_257 = pma_checker__entries_WIRE_21[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_ae_ptw = pma_checker__entries_T_257; // @[TLB.scala:170:77] assign pma_checker__entries_T_258 = pma_checker__entries_WIRE_21[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_g = pma_checker__entries_T_258; // @[TLB.scala:170:77] assign pma_checker__entries_T_259 = pma_checker__entries_WIRE_21[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_u = pma_checker__entries_T_259; // @[TLB.scala:170:77] assign pma_checker__entries_T_260 = pma_checker__entries_WIRE_21[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_20_ppn = pma_checker__entries_T_260; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_283; // @[TLB.scala:170:77] wire pma_checker__entries_T_282; // @[TLB.scala:170:77] wire pma_checker__entries_T_281; // @[TLB.scala:170:77] wire pma_checker__entries_T_280; // @[TLB.scala:170:77] wire pma_checker__entries_T_279; // @[TLB.scala:170:77] wire pma_checker__entries_T_278; // @[TLB.scala:170:77] wire pma_checker__entries_T_277; // @[TLB.scala:170:77] wire pma_checker__entries_T_276; // @[TLB.scala:170:77] wire pma_checker__entries_T_275; // @[TLB.scala:170:77] wire pma_checker__entries_T_274; // @[TLB.scala:170:77] wire pma_checker__entries_T_273; // @[TLB.scala:170:77] wire pma_checker__entries_T_272; // @[TLB.scala:170:77] wire pma_checker__entries_T_271; // @[TLB.scala:170:77] wire pma_checker__entries_T_270; // @[TLB.scala:170:77] wire pma_checker__entries_T_269; // @[TLB.scala:170:77] wire pma_checker__entries_T_268; // @[TLB.scala:170:77] wire pma_checker__entries_T_267; // @[TLB.scala:170:77] wire pma_checker__entries_T_266; // @[TLB.scala:170:77] wire pma_checker__entries_T_265; // @[TLB.scala:170:77] wire pma_checker__entries_T_264; // @[TLB.scala:170:77] wire pma_checker__entries_T_263; // @[TLB.scala:170:77] wire pma_checker__entries_T_262; // @[TLB.scala:170:77] wire pma_checker__entries_T_261; // @[TLB.scala:170:77] assign pma_checker__entries_T_261 = pma_checker__entries_WIRE_23[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_fragmented_superpage = pma_checker__entries_T_261; // @[TLB.scala:170:77] assign pma_checker__entries_T_262 = pma_checker__entries_WIRE_23[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_c = pma_checker__entries_T_262; // @[TLB.scala:170:77] assign pma_checker__entries_T_263 = pma_checker__entries_WIRE_23[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_eff = pma_checker__entries_T_263; // @[TLB.scala:170:77] assign pma_checker__entries_T_264 = pma_checker__entries_WIRE_23[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_paa = pma_checker__entries_T_264; // @[TLB.scala:170:77] assign pma_checker__entries_T_265 = pma_checker__entries_WIRE_23[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_pal = pma_checker__entries_T_265; // @[TLB.scala:170:77] assign pma_checker__entries_T_266 = pma_checker__entries_WIRE_23[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_ppp = pma_checker__entries_T_266; // @[TLB.scala:170:77] assign pma_checker__entries_T_267 = pma_checker__entries_WIRE_23[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_pr = pma_checker__entries_T_267; // @[TLB.scala:170:77] assign pma_checker__entries_T_268 = pma_checker__entries_WIRE_23[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_px = pma_checker__entries_T_268; // @[TLB.scala:170:77] assign pma_checker__entries_T_269 = pma_checker__entries_WIRE_23[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_pw = pma_checker__entries_T_269; // @[TLB.scala:170:77] assign pma_checker__entries_T_270 = pma_checker__entries_WIRE_23[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_hr = pma_checker__entries_T_270; // @[TLB.scala:170:77] assign pma_checker__entries_T_271 = pma_checker__entries_WIRE_23[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_hx = pma_checker__entries_T_271; // @[TLB.scala:170:77] assign pma_checker__entries_T_272 = pma_checker__entries_WIRE_23[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_hw = pma_checker__entries_T_272; // @[TLB.scala:170:77] assign pma_checker__entries_T_273 = pma_checker__entries_WIRE_23[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_sr = pma_checker__entries_T_273; // @[TLB.scala:170:77] assign pma_checker__entries_T_274 = pma_checker__entries_WIRE_23[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_sx = pma_checker__entries_T_274; // @[TLB.scala:170:77] assign pma_checker__entries_T_275 = pma_checker__entries_WIRE_23[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_sw = pma_checker__entries_T_275; // @[TLB.scala:170:77] assign pma_checker__entries_T_276 = pma_checker__entries_WIRE_23[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_gf = pma_checker__entries_T_276; // @[TLB.scala:170:77] assign pma_checker__entries_T_277 = pma_checker__entries_WIRE_23[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_pf = pma_checker__entries_T_277; // @[TLB.scala:170:77] assign pma_checker__entries_T_278 = pma_checker__entries_WIRE_23[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_ae_stage2 = pma_checker__entries_T_278; // @[TLB.scala:170:77] assign pma_checker__entries_T_279 = pma_checker__entries_WIRE_23[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_ae_final = pma_checker__entries_T_279; // @[TLB.scala:170:77] assign pma_checker__entries_T_280 = pma_checker__entries_WIRE_23[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_ae_ptw = pma_checker__entries_T_280; // @[TLB.scala:170:77] assign pma_checker__entries_T_281 = pma_checker__entries_WIRE_23[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_g = pma_checker__entries_T_281; // @[TLB.scala:170:77] assign pma_checker__entries_T_282 = pma_checker__entries_WIRE_23[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_u = pma_checker__entries_T_282; // @[TLB.scala:170:77] assign pma_checker__entries_T_283 = pma_checker__entries_WIRE_23[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_22_ppn = pma_checker__entries_T_283; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_306; // @[TLB.scala:170:77] wire pma_checker__entries_T_305; // @[TLB.scala:170:77] wire pma_checker__entries_T_304; // @[TLB.scala:170:77] wire pma_checker__entries_T_303; // @[TLB.scala:170:77] wire pma_checker__entries_T_302; // @[TLB.scala:170:77] wire pma_checker__entries_T_301; // @[TLB.scala:170:77] wire pma_checker__entries_T_300; // @[TLB.scala:170:77] wire pma_checker__entries_T_299; // @[TLB.scala:170:77] wire pma_checker__entries_T_298; // @[TLB.scala:170:77] wire pma_checker__entries_T_297; // @[TLB.scala:170:77] wire pma_checker__entries_T_296; // @[TLB.scala:170:77] wire pma_checker__entries_T_295; // @[TLB.scala:170:77] wire pma_checker__entries_T_294; // @[TLB.scala:170:77] wire pma_checker__entries_T_293; // @[TLB.scala:170:77] wire pma_checker__entries_T_292; // @[TLB.scala:170:77] wire pma_checker__entries_T_291; // @[TLB.scala:170:77] wire pma_checker__entries_T_290; // @[TLB.scala:170:77] wire pma_checker__entries_T_289; // @[TLB.scala:170:77] wire pma_checker__entries_T_288; // @[TLB.scala:170:77] wire pma_checker__entries_T_287; // @[TLB.scala:170:77] wire pma_checker__entries_T_286; // @[TLB.scala:170:77] wire pma_checker__entries_T_285; // @[TLB.scala:170:77] wire pma_checker__entries_T_284; // @[TLB.scala:170:77] assign pma_checker__entries_T_284 = pma_checker__entries_WIRE_25[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_fragmented_superpage = pma_checker__entries_T_284; // @[TLB.scala:170:77] assign pma_checker__entries_T_285 = pma_checker__entries_WIRE_25[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_c = pma_checker__entries_T_285; // @[TLB.scala:170:77] assign pma_checker__entries_T_286 = pma_checker__entries_WIRE_25[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_eff = pma_checker__entries_T_286; // @[TLB.scala:170:77] assign pma_checker__entries_T_287 = pma_checker__entries_WIRE_25[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_paa = pma_checker__entries_T_287; // @[TLB.scala:170:77] assign pma_checker__entries_T_288 = pma_checker__entries_WIRE_25[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_pal = pma_checker__entries_T_288; // @[TLB.scala:170:77] assign pma_checker__entries_T_289 = pma_checker__entries_WIRE_25[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_ppp = pma_checker__entries_T_289; // @[TLB.scala:170:77] assign pma_checker__entries_T_290 = pma_checker__entries_WIRE_25[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_pr = pma_checker__entries_T_290; // @[TLB.scala:170:77] assign pma_checker__entries_T_291 = pma_checker__entries_WIRE_25[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_px = pma_checker__entries_T_291; // @[TLB.scala:170:77] assign pma_checker__entries_T_292 = pma_checker__entries_WIRE_25[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_pw = pma_checker__entries_T_292; // @[TLB.scala:170:77] assign pma_checker__entries_T_293 = pma_checker__entries_WIRE_25[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_hr = pma_checker__entries_T_293; // @[TLB.scala:170:77] assign pma_checker__entries_T_294 = pma_checker__entries_WIRE_25[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_hx = pma_checker__entries_T_294; // @[TLB.scala:170:77] assign pma_checker__entries_T_295 = pma_checker__entries_WIRE_25[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_hw = pma_checker__entries_T_295; // @[TLB.scala:170:77] assign pma_checker__entries_T_296 = pma_checker__entries_WIRE_25[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_sr = pma_checker__entries_T_296; // @[TLB.scala:170:77] assign pma_checker__entries_T_297 = pma_checker__entries_WIRE_25[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_sx = pma_checker__entries_T_297; // @[TLB.scala:170:77] assign pma_checker__entries_T_298 = pma_checker__entries_WIRE_25[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_sw = pma_checker__entries_T_298; // @[TLB.scala:170:77] assign pma_checker__entries_T_299 = pma_checker__entries_WIRE_25[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_gf = pma_checker__entries_T_299; // @[TLB.scala:170:77] assign pma_checker__entries_T_300 = pma_checker__entries_WIRE_25[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_pf = pma_checker__entries_T_300; // @[TLB.scala:170:77] assign pma_checker__entries_T_301 = pma_checker__entries_WIRE_25[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_ae_stage2 = pma_checker__entries_T_301; // @[TLB.scala:170:77] assign pma_checker__entries_T_302 = pma_checker__entries_WIRE_25[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_ae_final = pma_checker__entries_T_302; // @[TLB.scala:170:77] assign pma_checker__entries_T_303 = pma_checker__entries_WIRE_25[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_ae_ptw = pma_checker__entries_T_303; // @[TLB.scala:170:77] assign pma_checker__entries_T_304 = pma_checker__entries_WIRE_25[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_g = pma_checker__entries_T_304; // @[TLB.scala:170:77] assign pma_checker__entries_T_305 = pma_checker__entries_WIRE_25[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_u = pma_checker__entries_T_305; // @[TLB.scala:170:77] assign pma_checker__entries_T_306 = pma_checker__entries_WIRE_25[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_24_ppn = pma_checker__entries_T_306; // @[TLB.scala:170:77] wire [1:0] pma_checker_ppn_res = _pma_checker_entries_barrier_8_io_y_ppn[19:18]; // @[package.scala:267:25] wire pma_checker_ppn_ignore = pma_checker__ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] pma_checker__ppn_T_1 = pma_checker_ppn_ignore ? pma_checker_vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] pma_checker__ppn_T_2 = {pma_checker__ppn_T_1[26:20], pma_checker__ppn_T_1[19:0] \| _pma_checker_entries_barrier_8_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_3 = pma_checker__ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] pma_checker__ppn_T_4 = {pma_checker_ppn_res, pma_checker__ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}] wire [26:0] pma_checker__ppn_T_6 = {pma_checker__ppn_T_5[26:20], pma_checker__ppn_T_5[19:0] \| _pma_checker_entries_barrier_8_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_7 = pma_checker__ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] pma_checker__ppn_T_8 = {pma_checker__ppn_T_4, pma_checker__ppn_T_7}; // @[TLB.scala:198:{18,58}] wire [1:0] pma_checker_ppn_res_1 = _pma_checker_entries_barrier_9_io_y_ppn[19:18]; // @[package.scala:267:25] wire pma_checker_ppn_ignore_2 = pma_checker__ppn_ignore_T_2; // @[TLB.scala:197:{28,34}] wire [26:0] pma_checker__ppn_T_9 = pma_checker_ppn_ignore_2 ? pma_checker_vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] pma_checker__ppn_T_10 = {pma_checker__ppn_T_9[26:20], pma_checker__ppn_T_9[19:0] \| _pma_checker_entries_barrier_9_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_11 = pma_checker__ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] pma_checker__ppn_T_12 = {pma_checker_ppn_res_1, pma_checker__ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}] wire [26:0] pma_checker__ppn_T_14 = {pma_checker__ppn_T_13[26:20], pma_checker__ppn_T_13[19:0] \| _pma_checker_entries_barrier_9_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_15 = pma_checker__ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] pma_checker__ppn_T_16 = {pma_checker__ppn_T_12, pma_checker__ppn_T_15}; // @[TLB.scala:198:{18,58}] wire [1:0] pma_checker_ppn_res_2 = _pma_checker_entries_barrier_10_io_y_ppn[19:18]; // @[package.scala:267:25] wire pma_checker_ppn_ignore_4 = pma_checker__ppn_ignore_T_4; // @[TLB.scala:197:{28,34}] wire [26:0] pma_checker__ppn_T_17 = pma_checker_ppn_ignore_4 ? pma_checker_vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] pma_checker__ppn_T_18 = {pma_checker__ppn_T_17[26:20], pma_checker__ppn_T_17[19:0] \| _pma_checker_entries_barrier_10_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_19 = pma_checker__ppn_T_18[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] pma_checker__ppn_T_20 = {pma_checker_ppn_res_2, pma_checker__ppn_T_19}; // @[TLB.scala:195:26, :198:{18,58}] wire [26:0] pma_checker__ppn_T_22 = {pma_checker__ppn_T_21[26:20], pma_checker__ppn_T_21[19:0] \| _pma_checker_entries_barrier_10_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_23 = pma_checker__ppn_T_22[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] pma_checker__ppn_T_24 = {pma_checker__ppn_T_20, pma_checker__ppn_T_23}; // @[TLB.scala:198:{18,58}] wire [1:0] pma_checker_ppn_res_3 = _pma_checker_entries_barrier_11_io_y_ppn[19:18]; // @[package.scala:267:25] wire pma_checker_ppn_ignore_6 = pma_checker__ppn_ignore_T_6; // @[TLB.scala:197:{28,34}] wire [26:0] pma_checker__ppn_T_25 = pma_checker_ppn_ignore_6 ? pma_checker_vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] pma_checker__ppn_T_26 = {pma_checker__ppn_T_25[26:20], pma_checker__ppn_T_25[19:0] \| _pma_checker_entries_barrier_11_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_27 = pma_checker__ppn_T_26[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] pma_checker__ppn_T_28 = {pma_checker_ppn_res_3, pma_checker__ppn_T_27}; // @[TLB.scala:195:26, :198:{18,58}] wire [26:0] pma_checker__ppn_T_30 = {pma_checker__ppn_T_29[26:20], pma_checker__ppn_T_29[19:0] \| _pma_checker_entries_barrier_11_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_31 = pma_checker__ppn_T_30[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] pma_checker__ppn_T_32 = {pma_checker__ppn_T_28, pma_checker__ppn_T_31}; // @[TLB.scala:198:{18,58}] wire [1:0] pma_checker_ppn_res_4 = _pma_checker_entries_barrier_12_io_y_ppn[19:18]; // @[package.scala:267:25] wire [26:0] pma_checker__ppn_T_34 = {pma_checker__ppn_T_33[26:20], pma_checker__ppn_T_33[19:0] \| _pma_checker_entries_barrier_12_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_35 = pma_checker__ppn_T_34[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] pma_checker__ppn_T_36 = {pma_checker_ppn_res_4, pma_checker__ppn_T_35}; // @[TLB.scala:195:26, :198:{18,58}] wire [26:0] pma_checker__ppn_T_38 = {pma_checker__ppn_T_37[26:20], pma_checker__ppn_T_37[19:0] \| _pma_checker_entries_barrier_12_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_39 = pma_checker__ppn_T_38[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] pma_checker__ppn_T_40 = {pma_checker__ppn_T_36, pma_checker__ppn_T_39}; // @[TLB.scala:198:{18,58}] wire [19:0] pma_checker__ppn_T_41 = pma_checker_vpn[19:0]; // @[TLB.scala:335:30, :502:125] wire [19:0] pma_checker__ppn_T_55 = pma_checker__ppn_T_41; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_68 = pma_checker__ppn_T_55; // @[Mux.scala:30:73] wire [19:0] pma_checker_ppn = pma_checker__ppn_T_68; // @[Mux.scala:30:73] wire [1:0] pma_checker_ptw_ae_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ae_ptw, _pma_checker_entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_ae_array_lo_lo = {pma_checker_ptw_ae_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_ae_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ae_ptw, _pma_checker_entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_ae_array_lo_hi = {pma_checker_ptw_ae_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ptw_ae_array_lo = {pma_checker_ptw_ae_array_lo_hi, pma_checker_ptw_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_ae_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ae_ptw, _pma_checker_entries_barrier_7_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_ae_array_hi_lo = {pma_checker_ptw_ae_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_ae_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_ae_ptw, _pma_checker_entries_barrier_9_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_ae_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_ae_ptw, _pma_checker_entries_barrier_11_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_ptw_ae_array_hi_hi = {pma_checker_ptw_ae_array_hi_hi_hi, pma_checker_ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_ptw_ae_array_hi = {pma_checker_ptw_ae_array_hi_hi, pma_checker_ptw_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__ptw_ae_array_T = {pma_checker_ptw_ae_array_hi, pma_checker_ptw_ae_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_ptw_ae_array = {1'h0, pma_checker__ptw_ae_array_T}; // @[package.scala:45:27] wire [1:0] pma_checker_final_ae_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ae_final, _pma_checker_entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_final_ae_array_lo_lo = {pma_checker_final_ae_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_final_ae_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ae_final, _pma_checker_entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_final_ae_array_lo_hi = {pma_checker_final_ae_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_final_ae_array_lo = {pma_checker_final_ae_array_lo_hi, pma_checker_final_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_final_ae_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ae_final, _pma_checker_entries_barrier_7_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_final_ae_array_hi_lo = {pma_checker_final_ae_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_final_ae_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_ae_final, _pma_checker_entries_barrier_9_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_final_ae_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_ae_final, _pma_checker_entries_barrier_11_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_final_ae_array_hi_hi = {pma_checker_final_ae_array_hi_hi_hi, pma_checker_final_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_final_ae_array_hi = {pma_checker_final_ae_array_hi_hi, pma_checker_final_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__final_ae_array_T = {pma_checker_final_ae_array_hi, pma_checker_final_ae_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_final_ae_array = {1'h0, pma_checker__final_ae_array_T}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_pf_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pf, _pma_checker_entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_pf_array_lo_lo = {pma_checker_ptw_pf_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_pf_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pf, _pma_checker_entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_pf_array_lo_hi = {pma_checker_ptw_pf_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ptw_pf_array_lo = {pma_checker_ptw_pf_array_lo_hi, pma_checker_ptw_pf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_pf_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pf, _pma_checker_entries_barrier_7_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_pf_array_hi_lo = {pma_checker_ptw_pf_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_pf_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_pf, _pma_checker_entries_barrier_9_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_pf_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_pf, _pma_checker_entries_barrier_11_io_y_pf}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_ptw_pf_array_hi_hi = {pma_checker_ptw_pf_array_hi_hi_hi, pma_checker_ptw_pf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_ptw_pf_array_hi = {pma_checker_ptw_pf_array_hi_hi, pma_checker_ptw_pf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__ptw_pf_array_T = {pma_checker_ptw_pf_array_hi, pma_checker_ptw_pf_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_ptw_pf_array = {1'h0, pma_checker__ptw_pf_array_T}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_gf_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_gf, _pma_checker_entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_gf_array_lo_lo = {pma_checker_ptw_gf_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_gf_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_gf, _pma_checker_entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_gf_array_lo_hi = {pma_checker_ptw_gf_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ptw_gf_array_lo = {pma_checker_ptw_gf_array_lo_hi, pma_checker_ptw_gf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_gf_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_gf, _pma_checker_entries_barrier_7_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_gf_array_hi_lo = {pma_checker_ptw_gf_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_gf_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_gf, _pma_checker_entries_barrier_9_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_gf_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_gf, _pma_checker_entries_barrier_11_io_y_gf}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_ptw_gf_array_hi_hi = {pma_checker_ptw_gf_array_hi_hi_hi, pma_checker_ptw_gf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_ptw_gf_array_hi = {pma_checker_ptw_gf_array_hi_hi, pma_checker_ptw_gf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__ptw_gf_array_T = {pma_checker_ptw_gf_array_hi, pma_checker_ptw_gf_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_ptw_gf_array = {1'h0, pma_checker__ptw_gf_array_T}; // @[package.scala:45:27] wire [13:0] pma_checker__gf_ld_array_T_3 = pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :600:82] wire [13:0] pma_checker__gf_st_array_T_2 = pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :601:63] wire [13:0] pma_checker__gf_inst_array_T_1 = pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :602:46] wire pma_checker__priv_rw_ok_T = ~pma_checker_priv_s; // @[TLB.scala:370:20, :513:24] wire pma_checker__priv_rw_ok_T_1 = pma_checker__priv_rw_ok_T; // @[TLB.scala:513:{24,32}] wire [1:0] _GEN_6 = {_pma_checker_entries_barrier_2_io_y_u, _pma_checker_entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_lo_lo_hi = _GEN_6; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_lo_lo_hi_1 = _GEN_6; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_priv_x_ok_lo_lo_hi = _GEN_6; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_lo_lo_hi_1 = _GEN_6; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_lo_lo = {pma_checker_priv_rw_ok_lo_lo_hi, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_7 = {_pma_checker_entries_barrier_5_io_y_u, _pma_checker_entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_lo_hi_hi = _GEN_7; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_lo_hi_hi_1 = _GEN_7; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_priv_x_ok_lo_hi_hi = _GEN_7; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_lo_hi_hi_1 = _GEN_7; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_lo_hi = {pma_checker_priv_rw_ok_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_priv_rw_ok_lo = {pma_checker_priv_rw_ok_lo_hi, pma_checker_priv_rw_ok_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_8 = {_pma_checker_entries_barrier_8_io_y_u, _pma_checker_entries_barrier_7_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_lo_hi = _GEN_8; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_lo_hi_1 = _GEN_8; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_lo_hi = _GEN_8; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_lo_hi_1 = _GEN_8; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_hi_lo = {pma_checker_priv_rw_ok_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_9 = {_pma_checker_entries_barrier_10_io_y_u, _pma_checker_entries_barrier_9_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_hi_hi_lo; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_hi_lo = _GEN_9; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_hi_lo_1 = _GEN_9; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_hi_lo; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_hi_lo = _GEN_9; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_hi_lo_1 = _GEN_9; // @[package.scala:45:27] wire [1:0] _GEN_10 = {_pma_checker_entries_barrier_12_io_y_u, _pma_checker_entries_barrier_11_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_hi_hi = _GEN_10; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_hi_hi_1 = _GEN_10; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_hi_hi = _GEN_10; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_hi_hi_1 = _GEN_10; // @[package.scala:45:27] wire [3:0] pma_checker_priv_rw_ok_hi_hi = {pma_checker_priv_rw_ok_hi_hi_hi, pma_checker_priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_priv_rw_ok_hi = {pma_checker_priv_rw_ok_hi_hi, pma_checker_priv_rw_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_2 = {pma_checker_priv_rw_ok_hi, pma_checker_priv_rw_ok_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_3 = pma_checker__priv_rw_ok_T_1 ? pma_checker__priv_rw_ok_T_2 : 13'h0; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_lo_lo_1 = {pma_checker_priv_rw_ok_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_priv_rw_ok_lo_hi_1 = {pma_checker_priv_rw_ok_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_priv_rw_ok_lo_1 = {pma_checker_priv_rw_ok_lo_hi_1, pma_checker_priv_rw_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_hi_lo_1 = {pma_checker_priv_rw_ok_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_priv_rw_ok_hi_hi_1 = {pma_checker_priv_rw_ok_hi_hi_hi_1, pma_checker_priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] pma_checker_priv_rw_ok_hi_1 = {pma_checker_priv_rw_ok_hi_hi_1, pma_checker_priv_rw_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_4 = {pma_checker_priv_rw_ok_hi_1, pma_checker_priv_rw_ok_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_5 = ~pma_checker__priv_rw_ok_T_4; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_6 = pma_checker_priv_s ? pma_checker__priv_rw_ok_T_5 : 13'h0; // @[TLB.scala:370:20, :513:{75,84}] wire [12:0] pma_checker_priv_rw_ok = pma_checker__priv_rw_ok_T_3 \| pma_checker__priv_rw_ok_T_6; // @[TLB.scala:513:{23,70,75}] wire [2:0] pma_checker_priv_x_ok_lo_lo = {pma_checker_priv_x_ok_lo_lo_hi, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_priv_x_ok_lo_hi = {pma_checker_priv_x_ok_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_priv_x_ok_lo = {pma_checker_priv_x_ok_lo_hi, pma_checker_priv_x_ok_lo_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_priv_x_ok_hi_lo = {pma_checker_priv_x_ok_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_priv_x_ok_hi_hi = {pma_checker_priv_x_ok_hi_hi_hi, pma_checker_priv_x_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_priv_x_ok_hi = {pma_checker_priv_x_ok_hi_hi, pma_checker_priv_x_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_x_ok_T = {pma_checker_priv_x_ok_hi, pma_checker_priv_x_ok_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_x_ok_T_1 = ~pma_checker__priv_x_ok_T; // @[package.scala:45:27] wire [2:0] pma_checker_priv_x_ok_lo_lo_1 = {pma_checker_priv_x_ok_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_priv_x_ok_lo_hi_1 = {pma_checker_priv_x_ok_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_priv_x_ok_lo_1 = {pma_checker_priv_x_ok_lo_hi_1, pma_checker_priv_x_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] pma_checker_priv_x_ok_hi_lo_1 = {pma_checker_priv_x_ok_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_priv_x_ok_hi_hi_1 = {pma_checker_priv_x_ok_hi_hi_hi_1, pma_checker_priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] pma_checker_priv_x_ok_hi_1 = {pma_checker_priv_x_ok_hi_hi_1, pma_checker_priv_x_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_x_ok_T_2 = {pma_checker_priv_x_ok_hi_1, pma_checker_priv_x_ok_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker_priv_x_ok = pma_checker_priv_s ? pma_checker__priv_x_ok_T_1 : pma_checker__priv_x_ok_T_2; // @[package.scala:45:27] wire [1:0] pma_checker_stage1_bypass_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ae_stage2, _pma_checker_entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_stage1_bypass_lo_lo = {pma_checker_stage1_bypass_lo_lo_hi, _pma_checker_entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_stage1_bypass_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ae_stage2, _pma_checker_entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_stage1_bypass_lo_hi = {pma_checker_stage1_bypass_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_stage1_bypass_lo = {pma_checker_stage1_bypass_lo_hi, pma_checker_stage1_bypass_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_stage1_bypass_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ae_stage2, _pma_checker_entries_barrier_7_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_stage1_bypass_hi_lo = {pma_checker_stage1_bypass_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_stage1_bypass_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_ae_stage2, _pma_checker_entries_barrier_9_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_stage1_bypass_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_ae_stage2, _pma_checker_entries_barrier_11_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_stage1_bypass_hi_hi = {pma_checker_stage1_bypass_hi_hi_hi, pma_checker_stage1_bypass_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_stage1_bypass_hi = {pma_checker_stage1_bypass_hi_hi, pma_checker_stage1_bypass_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__stage1_bypass_T_3 = {pma_checker_stage1_bypass_hi, pma_checker_stage1_bypass_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_r_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_sr, _pma_checker_entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_r_array_lo_lo = {pma_checker_r_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_sr, _pma_checker_entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_r_array_lo_hi = {pma_checker_r_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_r_array_lo = {pma_checker_r_array_lo_hi, pma_checker_r_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_r_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_sr, _pma_checker_entries_barrier_7_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_r_array_hi_lo = {pma_checker_r_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_sr, _pma_checker_entries_barrier_9_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_sr, _pma_checker_entries_barrier_11_io_y_sr}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_r_array_hi_hi = {pma_checker_r_array_hi_hi_hi, pma_checker_r_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_r_array_hi = {pma_checker_r_array_hi_hi, pma_checker_r_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__r_array_T = {pma_checker_r_array_hi, pma_checker_r_array_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__r_array_T_3 = pma_checker__r_array_T; // @[package.scala:45:27] wire [1:0] _GEN_11 = {_pma_checker_entries_barrier_2_io_y_sx, _pma_checker_entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_lo_lo_hi_1; // @[package.scala:45:27] assign pma_checker_r_array_lo_lo_hi_1 = _GEN_11; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_x_array_lo_lo_hi = _GEN_11; // @[package.scala:45:27] wire [2:0] pma_checker_r_array_lo_lo_1 = {pma_checker_r_array_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_12 = {_pma_checker_entries_barrier_5_io_y_sx, _pma_checker_entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_lo_hi_hi_1; // @[package.scala:45:27] assign pma_checker_r_array_lo_hi_hi_1 = _GEN_12; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_x_array_lo_hi_hi = _GEN_12; // @[package.scala:45:27] wire [2:0] pma_checker_r_array_lo_hi_1 = {pma_checker_r_array_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_r_array_lo_1 = {pma_checker_r_array_lo_hi_1, pma_checker_r_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_13 = {_pma_checker_entries_barrier_8_io_y_sx, _pma_checker_entries_barrier_7_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_lo_hi_1; // @[package.scala:45:27] assign pma_checker_r_array_hi_lo_hi_1 = _GEN_13; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_x_array_hi_lo_hi = _GEN_13; // @[package.scala:45:27] wire [2:0] pma_checker_r_array_hi_lo_1 = {pma_checker_r_array_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_14 = {_pma_checker_entries_barrier_10_io_y_sx, _pma_checker_entries_barrier_9_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_hi_lo_1; // @[package.scala:45:27] assign pma_checker_r_array_hi_hi_lo_1 = _GEN_14; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_hi_hi_lo; // @[package.scala:45:27] assign pma_checker_x_array_hi_hi_lo = _GEN_14; // @[package.scala:45:27] wire [1:0] _GEN_15 = {_pma_checker_entries_barrier_12_io_y_sx, _pma_checker_entries_barrier_11_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_hi_hi_1; // @[package.scala:45:27] assign pma_checker_r_array_hi_hi_hi_1 = _GEN_15; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_x_array_hi_hi_hi = _GEN_15; // @[package.scala:45:27] wire [3:0] pma_checker_r_array_hi_hi_1 = {pma_checker_r_array_hi_hi_hi_1, pma_checker_r_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] pma_checker_r_array_hi_1 = {pma_checker_r_array_hi_hi_1, pma_checker_r_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__r_array_T_1 = {pma_checker_r_array_hi_1, pma_checker_r_array_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__r_array_T_4 = pma_checker_priv_rw_ok & pma_checker__r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}] wire [12:0] pma_checker__r_array_T_5 = pma_checker__r_array_T_4; // @[TLB.scala:520:{41,113}] wire [13:0] pma_checker_r_array = {1'h1, pma_checker__r_array_T_5}; // @[TLB.scala:520:{20,113}] wire [13:0] pma_checker__pf_ld_array_T = pma_checker_r_array; // @[TLB.scala:520:20, :597:41] wire [1:0] pma_checker_w_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_sw, _pma_checker_entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_w_array_lo_lo = {pma_checker_w_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_w_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_sw, _pma_checker_entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_w_array_lo_hi = {pma_checker_w_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_w_array_lo = {pma_checker_w_array_lo_hi, pma_checker_w_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_w_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_sw, _pma_checker_entries_barrier_7_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_w_array_hi_lo = {pma_checker_w_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_w_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_sw, _pma_checker_entries_barrier_9_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_w_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_sw, _pma_checker_entries_barrier_11_io_y_sw}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_w_array_hi_hi = {pma_checker_w_array_hi_hi_hi, pma_checker_w_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_w_array_hi = {pma_checker_w_array_hi_hi, pma_checker_w_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__w_array_T = {pma_checker_w_array_hi, pma_checker_w_array_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__w_array_T_1 = pma_checker_priv_rw_ok & pma_checker__w_array_T; // @[package.scala:45:27] wire [12:0] pma_checker__w_array_T_2 = pma_checker__w_array_T_1; // @[TLB.scala:521:{41,69}] wire [13:0] pma_checker_w_array = {1'h1, pma_checker__w_array_T_2}; // @[TLB.scala:521:{20,69}] wire [2:0] pma_checker_x_array_lo_lo = {pma_checker_x_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_x_array_lo_hi = {pma_checker_x_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_x_array_lo = {pma_checker_x_array_lo_hi, pma_checker_x_array_lo_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_x_array_hi_lo = {pma_checker_x_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_x_array_hi_hi = {pma_checker_x_array_hi_hi_hi, pma_checker_x_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_x_array_hi = {pma_checker_x_array_hi_hi, pma_checker_x_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__x_array_T = {pma_checker_x_array_hi, pma_checker_x_array_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__x_array_T_1 = pma_checker_priv_x_ok & pma_checker__x_array_T; // @[package.scala:45:27] wire [12:0] pma_checker__x_array_T_2 = pma_checker__x_array_T_1; // @[TLB.scala:522:{40,68}] wire [13:0] pma_checker_x_array = {1'h1, pma_checker__x_array_T_2}; // @[TLB.scala:522:{20,68}] wire [1:0] pma_checker_hr_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_hr, _pma_checker_entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hr_array_lo_lo = {pma_checker_hr_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_hr, _pma_checker_entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hr_array_lo_hi = {pma_checker_hr_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_hr_array_lo = {pma_checker_hr_array_lo_hi, pma_checker_hr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_hr_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_hr, _pma_checker_entries_barrier_7_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hr_array_hi_lo = {pma_checker_hr_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_hr, _pma_checker_entries_barrier_9_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_hr, _pma_checker_entries_barrier_11_io_y_hr}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_hr_array_hi_hi = {pma_checker_hr_array_hi_hi_hi, pma_checker_hr_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_hr_array_hi = {pma_checker_hr_array_hi_hi, pma_checker_hr_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__hr_array_T = {pma_checker_hr_array_hi, pma_checker_hr_array_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__hr_array_T_3 = pma_checker__hr_array_T; // @[package.scala:45:27] wire [1:0] _GEN_16 = {_pma_checker_entries_barrier_2_io_y_hx, _pma_checker_entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_lo_lo_hi_1; // @[package.scala:45:27] assign pma_checker_hr_array_lo_lo_hi_1 = _GEN_16; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_hx_array_lo_lo_hi = _GEN_16; // @[package.scala:45:27] wire [2:0] pma_checker_hr_array_lo_lo_1 = {pma_checker_hr_array_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_17 = {_pma_checker_entries_barrier_5_io_y_hx, _pma_checker_entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_lo_hi_hi_1; // @[package.scala:45:27] assign pma_checker_hr_array_lo_hi_hi_1 = _GEN_17; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_hx_array_lo_hi_hi = _GEN_17; // @[package.scala:45:27] wire [2:0] pma_checker_hr_array_lo_hi_1 = {pma_checker_hr_array_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_hr_array_lo_1 = {pma_checker_hr_array_lo_hi_1, pma_checker_hr_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_18 = {_pma_checker_entries_barrier_8_io_y_hx, _pma_checker_entries_barrier_7_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_lo_hi_1; // @[package.scala:45:27] assign pma_checker_hr_array_hi_lo_hi_1 = _GEN_18; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_hx_array_hi_lo_hi = _GEN_18; // @[package.scala:45:27] wire [2:0] pma_checker_hr_array_hi_lo_1 = {pma_checker_hr_array_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_19 = {_pma_checker_entries_barrier_10_io_y_hx, _pma_checker_entries_barrier_9_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_hi_lo_1; // @[package.scala:45:27] assign pma_checker_hr_array_hi_hi_lo_1 = _GEN_19; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_hi_hi_lo; // @[package.scala:45:27] assign pma_checker_hx_array_hi_hi_lo = _GEN_19; // @[package.scala:45:27] wire [1:0] _GEN_20 = {_pma_checker_entries_barrier_12_io_y_hx, _pma_checker_entries_barrier_11_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_hi_hi_1; // @[package.scala:45:27] assign pma_checker_hr_array_hi_hi_hi_1 = _GEN_20; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_hx_array_hi_hi_hi = _GEN_20; // @[package.scala:45:27] wire [3:0] pma_checker_hr_array_hi_hi_1 = {pma_checker_hr_array_hi_hi_hi_1, pma_checker_hr_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] pma_checker_hr_array_hi_1 = {pma_checker_hr_array_hi_hi_1, pma_checker_hr_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__hr_array_T_1 = {pma_checker_hr_array_hi_1, pma_checker_hr_array_lo_1}; // @[package.scala:45:27] wire [1:0] pma_checker_hw_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_hw, _pma_checker_entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hw_array_lo_lo = {pma_checker_hw_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hw_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_hw, _pma_checker_entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hw_array_lo_hi = {pma_checker_hw_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_hw_array_lo = {pma_checker_hw_array_lo_hi, pma_checker_hw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_hw_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_hw, _pma_checker_entries_barrier_7_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hw_array_hi_lo = {pma_checker_hw_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hw_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_hw, _pma_checker_entries_barrier_9_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hw_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_hw, _pma_checker_entries_barrier_11_io_y_hw}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_hw_array_hi_hi = {pma_checker_hw_array_hi_hi_hi, pma_checker_hw_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_hw_array_hi = {pma_checker_hw_array_hi_hi, pma_checker_hw_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__hw_array_T = {pma_checker_hw_array_hi, pma_checker_hw_array_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_hx_array_lo_lo = {pma_checker_hx_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hx_array_lo_hi = {pma_checker_hx_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_hx_array_lo = {pma_checker_hx_array_lo_hi, pma_checker_hx_array_lo_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_hx_array_hi_lo = {pma_checker_hx_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_hx_array_hi_hi = {pma_checker_hx_array_hi_hi_hi, pma_checker_hx_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_hx_array_hi = {pma_checker_hx_array_hi_hi, pma_checker_hx_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__hx_array_T = {pma_checker_hx_array_hi, pma_checker_hx_array_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_pr_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pr, _pma_checker_entries_barrier_1_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pr_array_lo_lo = {pma_checker_pr_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pr_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pr, _pma_checker_entries_barrier_4_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pr_array_lo_hi = {pma_checker_pr_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pr_array_lo = {pma_checker_pr_array_lo_hi, pma_checker_pr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_pr_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pr, _pma_checker_entries_barrier_7_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pr_array_hi_lo = {pma_checker_pr_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pr_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_pr, _pma_checker_entries_barrier_10_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pr_array_hi_hi = {pma_checker_pr_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pr_array_hi = {pma_checker_pr_array_hi_hi, pma_checker_pr_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__pr_array_T_1 = {pma_checker_pr_array_hi, pma_checker_pr_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker__pr_array_T_2 = {2'h0, pma_checker__pr_array_T_1}; // @[package.scala:45:27] wire [13:0] _GEN_21 = pma_checker_ptw_ae_array \| pma_checker_final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104] wire [13:0] pma_checker__pr_array_T_3; // @[TLB.scala:529:104] assign pma_checker__pr_array_T_3 = _GEN_21; // @[TLB.scala:529:104] wire [13:0] pma_checker__pw_array_T_3; // @[TLB.scala:531:104] assign pma_checker__pw_array_T_3 = _GEN_21; // @[TLB.scala:529:104, :531:104] wire [13:0] pma_checker__px_array_T_3; // @[TLB.scala:533:104] assign pma_checker__px_array_T_3 = _GEN_21; // @[TLB.scala:529:104, :533:104] wire [13:0] pma_checker__pr_array_T_4 = ~pma_checker__pr_array_T_3; // @[TLB.scala:529:{89,104}] wire [13:0] pma_checker_pr_array = pma_checker__pr_array_T_2 & pma_checker__pr_array_T_4; // @[TLB.scala:529:{21,87,89}] wire [1:0] pma_checker_pw_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pw, _pma_checker_entries_barrier_1_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pw_array_lo_lo = {pma_checker_pw_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pw_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pw, _pma_checker_entries_barrier_4_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pw_array_lo_hi = {pma_checker_pw_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pw_array_lo = {pma_checker_pw_array_lo_hi, pma_checker_pw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_pw_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pw, _pma_checker_entries_barrier_7_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pw_array_hi_lo = {pma_checker_pw_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pw_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_pw, _pma_checker_entries_barrier_10_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pw_array_hi_hi = {pma_checker_pw_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pw_array_hi = {pma_checker_pw_array_hi_hi, pma_checker_pw_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__pw_array_T_1 = {pma_checker_pw_array_hi, pma_checker_pw_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker__pw_array_T_2 = {2'h0, pma_checker__pw_array_T_1}; // @[package.scala:45:27] wire [13:0] pma_checker__pw_array_T_4 = ~pma_checker__pw_array_T_3; // @[TLB.scala:531:{89,104}] wire [13:0] pma_checker_pw_array = pma_checker__pw_array_T_2 & pma_checker__pw_array_T_4; // @[TLB.scala:531:{21,87,89}] wire [1:0] pma_checker_px_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_px, _pma_checker_entries_barrier_1_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_px_array_lo_lo = {pma_checker_px_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_px_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_px, _pma_checker_entries_barrier_4_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_px_array_lo_hi = {pma_checker_px_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_px_array_lo = {pma_checker_px_array_lo_hi, pma_checker_px_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_px_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_px, _pma_checker_entries_barrier_7_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_px_array_hi_lo = {pma_checker_px_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_px_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_px, _pma_checker_entries_barrier_10_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_px_array_hi_hi = {pma_checker_px_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_px_array_hi = {pma_checker_px_array_hi_hi, pma_checker_px_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__px_array_T_1 = {pma_checker_px_array_hi, pma_checker_px_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker__px_array_T_2 = {2'h0, pma_checker__px_array_T_1}; // @[package.scala:45:27] wire [13:0] pma_checker__px_array_T_4 = ~pma_checker__px_array_T_3; // @[TLB.scala:533:{89,104}] wire [13:0] pma_checker_px_array = pma_checker__px_array_T_2 & pma_checker__px_array_T_4; // @[TLB.scala:533:{21,87,89}] wire [1:0] pma_checker__eff_array_T = {2{_pma_checker_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27] wire [1:0] pma_checker_eff_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_eff, _pma_checker_entries_barrier_1_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_eff_array_lo_lo = {pma_checker_eff_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_eff_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_eff, _pma_checker_entries_barrier_4_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_eff_array_lo_hi = {pma_checker_eff_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_eff_array_lo = {pma_checker_eff_array_lo_hi, pma_checker_eff_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_eff_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_eff, _pma_checker_entries_barrier_7_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_eff_array_hi_lo = {pma_checker_eff_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_eff_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_eff, _pma_checker_entries_barrier_10_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_eff_array_hi_hi = {pma_checker_eff_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_eff_array_hi = {pma_checker_eff_array_hi_hi, pma_checker_eff_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__eff_array_T_1 = {pma_checker_eff_array_hi, pma_checker_eff_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_eff_array = {pma_checker__eff_array_T, pma_checker__eff_array_T_1}; // @[package.scala:45:27] wire [1:0] pma_checker__c_array_T = {2{pma_checker_cacheable}}; // @[TLB.scala:425:41, :537:25] wire [1:0] _GEN_22 = {_pma_checker_entries_barrier_2_io_y_c, _pma_checker_entries_barrier_1_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_c_array_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_c_array_lo_lo_hi = _GEN_22; // @[package.scala:45:27] wire [1:0] pma_checker_prefetchable_array_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_prefetchable_array_lo_lo_hi = _GEN_22; // @[package.scala:45:27] wire [2:0] pma_checker_c_array_lo_lo = {pma_checker_c_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_23 = {_pma_checker_entries_barrier_5_io_y_c, _pma_checker_entries_barrier_4_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_c_array_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_c_array_lo_hi_hi = _GEN_23; // @[package.scala:45:27] wire [1:0] pma_checker_prefetchable_array_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_prefetchable_array_lo_hi_hi = _GEN_23; // @[package.scala:45:27] wire [2:0] pma_checker_c_array_lo_hi = {pma_checker_c_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_c_array_lo = {pma_checker_c_array_lo_hi, pma_checker_c_array_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_24 = {_pma_checker_entries_barrier_8_io_y_c, _pma_checker_entries_barrier_7_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_c_array_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_c_array_hi_lo_hi = _GEN_24; // @[package.scala:45:27] wire [1:0] pma_checker_prefetchable_array_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_prefetchable_array_hi_lo_hi = _GEN_24; // @[package.scala:45:27] wire [2:0] pma_checker_c_array_hi_lo = {pma_checker_c_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_25 = {_pma_checker_entries_barrier_11_io_y_c, _pma_checker_entries_barrier_10_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_c_array_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_c_array_hi_hi_hi = _GEN_25; // @[package.scala:45:27] wire [1:0] pma_checker_prefetchable_array_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_prefetchable_array_hi_hi_hi = _GEN_25; // @[package.scala:45:27] wire [2:0] pma_checker_c_array_hi_hi = {pma_checker_c_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_c_array_hi = {pma_checker_c_array_hi_hi, pma_checker_c_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__c_array_T_1 = {pma_checker_c_array_hi, pma_checker_c_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_c_array = {pma_checker__c_array_T, pma_checker__c_array_T_1}; // @[package.scala:45:27] wire [13:0] pma_checker_lrscAllowed = pma_checker_c_array; // @[TLB.scala:537:20, :580:24] wire [1:0] pma_checker__ppp_array_T = {2{_pma_checker_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27] wire [1:0] pma_checker_ppp_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ppp, _pma_checker_entries_barrier_1_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ppp_array_lo_lo = {pma_checker_ppp_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ppp_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ppp, _pma_checker_entries_barrier_4_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ppp_array_lo_hi = {pma_checker_ppp_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ppp_array_lo = {pma_checker_ppp_array_lo_hi, pma_checker_ppp_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_ppp_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ppp, _pma_checker_entries_barrier_7_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ppp_array_hi_lo = {pma_checker_ppp_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ppp_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_ppp, _pma_checker_entries_barrier_10_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ppp_array_hi_hi = {pma_checker_ppp_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ppp_array_hi = {pma_checker_ppp_array_hi_hi, pma_checker_ppp_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__ppp_array_T_1 = {pma_checker_ppp_array_hi, pma_checker_ppp_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_ppp_array = {pma_checker__ppp_array_T, pma_checker__ppp_array_T_1}; // @[package.scala:45:27] wire [1:0] pma_checker__paa_array_T = {2{_pma_checker_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27] wire [1:0] pma_checker_paa_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_paa, _pma_checker_entries_barrier_1_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_paa_array_lo_lo = {pma_checker_paa_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_paa_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_paa, _pma_checker_entries_barrier_4_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_paa_array_lo_hi = {pma_checker_paa_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_paa_array_lo = {pma_checker_paa_array_lo_hi, pma_checker_paa_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_paa_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_paa, _pma_checker_entries_barrier_7_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_paa_array_hi_lo = {pma_checker_paa_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_paa_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_paa, _pma_checker_entries_barrier_10_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_paa_array_hi_hi = {pma_checker_paa_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_paa_array_hi = {pma_checker_paa_array_hi_hi, pma_checker_paa_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__paa_array_T_1 = {pma_checker_paa_array_hi, pma_checker_paa_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_paa_array = {pma_checker__paa_array_T, pma_checker__paa_array_T_1}; // @[package.scala:45:27] wire [1:0] pma_checker__pal_array_T = {2{_pma_checker_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27] wire [1:0] pma_checker_pal_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pal, _pma_checker_entries_barrier_1_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pal_array_lo_lo = {pma_checker_pal_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pal_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pal, _pma_checker_entries_barrier_4_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pal_array_lo_hi = {pma_checker_pal_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pal_array_lo = {pma_checker_pal_array_lo_hi, pma_checker_pal_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_pal_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pal, _pma_checker_entries_barrier_7_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pal_array_hi_lo = {pma_checker_pal_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pal_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_pal, _pma_checker_entries_barrier_10_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pal_array_hi_hi = {pma_checker_pal_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pal_array_hi = {pma_checker_pal_array_hi_hi, pma_checker_pal_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__pal_array_T_1 = {pma_checker_pal_array_hi, pma_checker_pal_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_pal_array = {pma_checker__pal_array_T, pma_checker__pal_array_T_1}; // @[package.scala:45:27] wire [13:0] pma_checker_ppp_array_if_cached = pma_checker_ppp_array \| pma_checker_c_array; // @[TLB.scala:537:20, :539:22, :544:39] wire [13:0] pma_checker_paa_array_if_cached = pma_checker_paa_array \| pma_checker_c_array; // @[TLB.scala:537:20, :541:22, :545:39] wire [13:0] pma_checker_pal_array_if_cached = pma_checker_pal_array \| pma_checker_c_array; // @[TLB.scala:537:20, :543:22, :546:39] wire pma_checker__prefetchable_array_T = pma_checker_cacheable & pma_checker_homogeneous; // @[TLBPermissions.scala:101:65] wire [1:0] pma_checker__prefetchable_array_T_1 = {pma_checker__prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}] wire [2:0] pma_checker_prefetchable_array_lo_lo = {pma_checker_prefetchable_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_prefetchable_array_lo_hi = {pma_checker_prefetchable_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_prefetchable_array_lo = {pma_checker_prefetchable_array_lo_hi, pma_checker_prefetchable_array_lo_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_prefetchable_array_hi_lo = {pma_checker_prefetchable_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_prefetchable_array_hi_hi = {pma_checker_prefetchable_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_prefetchable_array_hi = {pma_checker_prefetchable_array_hi_hi, pma_checker_prefetchable_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__prefetchable_array_T_2 = {pma_checker_prefetchable_array_hi, pma_checker_prefetchable_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_prefetchable_array = {pma_checker__prefetchable_array_T_1, pma_checker__prefetchable_array_T_2}; // @[package.scala:45:27] wire [3:0] pma_checker__misaligned_T = 4'h1 << pma_checker_io_req_bits_size; // @[OneHot.scala:58:35] wire [4:0] pma_checker__misaligned_T_1 = {1'h0, pma_checker__misaligned_T} - 5'h1; // @[OneHot.scala:58:35] wire [3:0] pma_checker__misaligned_T_2 = pma_checker__misaligned_T_1[3:0]; // @[TLB.scala:550:69] wire [39:0] pma_checker__misaligned_T_3 = {36'h0, pma_checker_io_req_bits_vaddr[3:0] & pma_checker__misaligned_T_2}; // @[TLB.scala:550:{39,69}] wire pma_checker_misaligned = \|pma_checker__misaligned_T_3; // @[TLB.scala:550:{39,77}] wire [39:0] pma_checker_bad_va_maskedVAddr = pma_checker_io_req_bits_vaddr & 40'hC000000000; // @[TLB.scala:559:43] wire pma_checker__bad_va_T_2 = pma_checker_bad_va_maskedVAddr == 40'h0; // @[TLB.scala:559:43, :560:51] wire pma_checker__bad_va_T_3 = pma_checker_bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86] wire pma_checker__bad_va_T_4 = pma_checker__bad_va_T_3; // @[TLB.scala:560:{71,86}] wire pma_checker__bad_va_T_5 = pma_checker__bad_va_T_2 \| pma_checker__bad_va_T_4; // @[TLB.scala:560:{51,59,71}] wire pma_checker__bad_va_T_6 = ~pma_checker__bad_va_T_5; // @[TLB.scala:560:{37,59}] wire pma_checker__bad_va_T_7 = pma_checker__bad_va_T_6; // @[TLB.scala:560:{34,37}] wire _GEN_26 = pma_checker_io_req_bits_cmd == 5'h6; // @[package.scala:16:47] wire pma_checker__cmd_lrsc_T; // @[package.scala:16:47] assign pma_checker__cmd_lrsc_T = _GEN_26; // @[package.scala:16:47] wire pma_checker__cmd_read_T_2; // @[package.scala:16:47] assign pma_checker__cmd_read_T_2 = _GEN_26; // @[package.scala:16:47] wire _GEN_27 = pma_checker_io_req_bits_cmd == 5'h7; // @[package.scala:16:47] wire pma_checker__cmd_lrsc_T_1; // @[package.scala:16:47] assign pma_checker__cmd_lrsc_T_1 = _GEN_27; // @[package.scala:16:47] wire pma_checker__cmd_read_T_3; // @[package.scala:16:47] assign pma_checker__cmd_read_T_3 = _GEN_27; // @[package.scala:16:47] wire pma_checker__cmd_write_T_3; // @[Consts.scala:90:66] assign pma_checker__cmd_write_T_3 = _GEN_27; // @[package.scala:16:47] wire pma_checker__cmd_lrsc_T_2 = pma_checker__cmd_lrsc_T \| pma_checker__cmd_lrsc_T_1; // @[package.scala:16:47, :81:59] wire pma_checker_cmd_lrsc = pma_checker__cmd_lrsc_T_2; // @[package.scala:81:59] wire _GEN_28 = pma_checker_io_req_bits_cmd == 5'h4; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T; // @[package.scala:16:47] assign pma_checker__cmd_amo_logical_T = _GEN_28; // @[package.scala:16:47] wire pma_checker__cmd_read_T_7; // @[package.scala:16:47] assign pma_checker__cmd_read_T_7 = _GEN_28; // @[package.scala:16:47] wire pma_checker__cmd_write_T_5; // @[package.scala:16:47] assign pma_checker__cmd_write_T_5 = _GEN_28; // @[package.scala:16:47] wire _GEN_29 = pma_checker_io_req_bits_cmd == 5'h9; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T_1; // @[package.scala:16:47] assign pma_checker__cmd_amo_logical_T_1 = _GEN_29; // @[package.scala:16:47] wire pma_checker__cmd_read_T_8; // @[package.scala:16:47] assign pma_checker__cmd_read_T_8 = _GEN_29; // @[package.scala:16:47] wire pma_checker__cmd_write_T_6; // @[package.scala:16:47] assign pma_checker__cmd_write_T_6 = _GEN_29; // @[package.scala:16:47] wire _GEN_30 = pma_checker_io_req_bits_cmd == 5'hA; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T_2; // @[package.scala:16:47] assign pma_checker__cmd_amo_logical_T_2 = _GEN_30; // @[package.scala:16:47] wire pma_checker__cmd_read_T_9; // @[package.scala:16:47] assign pma_checker__cmd_read_T_9 = _GEN_30; // @[package.scala:16:47] wire pma_checker__cmd_write_T_7; // @[package.scala:16:47] assign pma_checker__cmd_write_T_7 = _GEN_30; // @[package.scala:16:47] wire _GEN_31 = pma_checker_io_req_bits_cmd == 5'hB; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T_3; // @[package.scala:16:47] assign pma_checker__cmd_amo_logical_T_3 = _GEN_31; // @[package.scala:16:47] wire pma_checker__cmd_read_T_10; // @[package.scala:16:47] assign pma_checker__cmd_read_T_10 = _GEN_31; // @[package.scala:16:47] wire pma_checker__cmd_write_T_8; // @[package.scala:16:47] assign pma_checker__cmd_write_T_8 = _GEN_31; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T_4 = pma_checker__cmd_amo_logical_T \| pma_checker__cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_logical_T_5 = pma_checker__cmd_amo_logical_T_4 \| pma_checker__cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_logical_T_6 = pma_checker__cmd_amo_logical_T_5 \| pma_checker__cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59] wire pma_checker_cmd_amo_logical = pma_checker__cmd_amo_logical_T_6; // @[package.scala:81:59] wire _GEN_32 = pma_checker_io_req_bits_cmd == 5'h8; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T = _GEN_32; // @[package.scala:16:47] wire pma_checker__cmd_read_T_14; // @[package.scala:16:47] assign pma_checker__cmd_read_T_14 = _GEN_32; // @[package.scala:16:47] wire pma_checker__cmd_write_T_12; // @[package.scala:16:47] assign pma_checker__cmd_write_T_12 = _GEN_32; // @[package.scala:16:47] wire _GEN_33 = pma_checker_io_req_bits_cmd == 5'hC; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_1; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T_1 = _GEN_33; // @[package.scala:16:47] wire pma_checker__cmd_read_T_15; // @[package.scala:16:47] assign pma_checker__cmd_read_T_15 = _GEN_33; // @[package.scala:16:47] wire pma_checker__cmd_write_T_13; // @[package.scala:16:47] assign pma_checker__cmd_write_T_13 = _GEN_33; // @[package.scala:16:47] wire _GEN_34 = pma_checker_io_req_bits_cmd == 5'hD; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_2; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T_2 = _GEN_34; // @[package.scala:16:47] wire pma_checker__cmd_read_T_16; // @[package.scala:16:47] assign pma_checker__cmd_read_T_16 = _GEN_34; // @[package.scala:16:47] wire pma_checker__cmd_write_T_14; // @[package.scala:16:47] assign pma_checker__cmd_write_T_14 = _GEN_34; // @[package.scala:16:47] wire _GEN_35 = pma_checker_io_req_bits_cmd == 5'hE; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_3; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T_3 = _GEN_35; // @[package.scala:16:47] wire pma_checker__cmd_read_T_17; // @[package.scala:16:47] assign pma_checker__cmd_read_T_17 = _GEN_35; // @[package.scala:16:47] wire pma_checker__cmd_write_T_15; // @[package.scala:16:47] assign pma_checker__cmd_write_T_15 = _GEN_35; // @[package.scala:16:47] wire _GEN_36 = pma_checker_io_req_bits_cmd == 5'hF; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_4; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T_4 = _GEN_36; // @[package.scala:16:47] wire pma_checker__cmd_read_T_18; // @[package.scala:16:47] assign pma_checker__cmd_read_T_18 = _GEN_36; // @[package.scala:16:47] wire pma_checker__cmd_write_T_16; // @[package.scala:16:47] assign pma_checker__cmd_write_T_16 = _GEN_36; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_5 = pma_checker__cmd_amo_arithmetic_T \| pma_checker__cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_arithmetic_T_6 = pma_checker__cmd_amo_arithmetic_T_5 \| pma_checker__cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_arithmetic_T_7 = pma_checker__cmd_amo_arithmetic_T_6 \| pma_checker__cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_arithmetic_T_8 = pma_checker__cmd_amo_arithmetic_T_7 \| pma_checker__cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59] wire pma_checker_cmd_amo_arithmetic = pma_checker__cmd_amo_arithmetic_T_8; // @[package.scala:81:59] wire _GEN_37 = pma_checker_io_req_bits_cmd == 5'h11; // @[TLB.scala:573:41] wire pma_checker_cmd_put_partial; // @[TLB.scala:573:41] assign pma_checker_cmd_put_partial = _GEN_37; // @[TLB.scala:573:41] wire pma_checker__cmd_write_T_1; // @[Consts.scala:90:49] assign pma_checker__cmd_write_T_1 = _GEN_37; // @[TLB.scala:573:41] wire pma_checker__cmd_read_T = pma_checker_io_req_bits_cmd == 5'h0; // @[package.scala:16:47] wire _GEN_38 = pma_checker_io_req_bits_cmd == 5'h10; // @[package.scala:16:47] wire pma_checker__cmd_read_T_1; // @[package.scala:16:47] assign pma_checker__cmd_read_T_1 = _GEN_38; // @[package.scala:16:47] wire pma_checker__cmd_readx_T; // @[TLB.scala:575:56] assign pma_checker__cmd_readx_T = _GEN_38; // @[package.scala:16:47] wire pma_checker__cmd_read_T_4 = pma_checker__cmd_read_T \| pma_checker__cmd_read_T_1; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_5 = pma_checker__cmd_read_T_4 \| pma_checker__cmd_read_T_2; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_6 = pma_checker__cmd_read_T_5 \| pma_checker__cmd_read_T_3; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_11 = pma_checker__cmd_read_T_7 \| pma_checker__cmd_read_T_8; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_12 = pma_checker__cmd_read_T_11 \| pma_checker__cmd_read_T_9; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_13 = pma_checker__cmd_read_T_12 \| pma_checker__cmd_read_T_10; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_19 = pma_checker__cmd_read_T_14 \| pma_checker__cmd_read_T_15; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_20 = pma_checker__cmd_read_T_19 \| pma_checker__cmd_read_T_16; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_21 = pma_checker__cmd_read_T_20 \| pma_checker__cmd_read_T_17; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_22 = pma_checker__cmd_read_T_21 \| pma_checker__cmd_read_T_18; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_23 = pma_checker__cmd_read_T_13 \| pma_checker__cmd_read_T_22; // @[package.scala:81:59] wire pma_checker_cmd_read = pma_checker__cmd_read_T_6 \| pma_checker__cmd_read_T_23; // @[package.scala:81:59] wire pma_checker__cmd_write_T = pma_checker_io_req_bits_cmd == 5'h1; // @[DCache.scala:120:32] wire pma_checker__cmd_write_T_2 = pma_checker__cmd_write_T \| pma_checker__cmd_write_T_1; // @[Consts.scala:90:{32,42,49}] wire pma_checker__cmd_write_T_4 = pma_checker__cmd_write_T_2 \| pma_checker__cmd_write_T_3; // @[Consts.scala:90:{42,59,66}] wire pma_checker__cmd_write_T_9 = pma_checker__cmd_write_T_5 \| pma_checker__cmd_write_T_6; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_10 = pma_checker__cmd_write_T_9 \| pma_checker__cmd_write_T_7; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_11 = pma_checker__cmd_write_T_10 \| pma_checker__cmd_write_T_8; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_17 = pma_checker__cmd_write_T_12 \| pma_checker__cmd_write_T_13; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_18 = pma_checker__cmd_write_T_17 \| pma_checker__cmd_write_T_14; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_19 = pma_checker__cmd_write_T_18 \| pma_checker__cmd_write_T_15; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_20 = pma_checker__cmd_write_T_19 \| pma_checker__cmd_write_T_16; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_21 = pma_checker__cmd_write_T_11 \| pma_checker__cmd_write_T_20; // @[package.scala:81:59] wire pma_checker_cmd_write = pma_checker__cmd_write_T_4 \| pma_checker__cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire pma_checker__cmd_write_perms_T = pma_checker_io_req_bits_cmd == 5'h5; // @[package.scala:16:47] wire pma_checker__cmd_write_perms_T_1 = pma_checker_io_req_bits_cmd == 5'h17; // @[package.scala:16:47] wire pma_checker__cmd_write_perms_T_2 = pma_checker__cmd_write_perms_T \| pma_checker__cmd_write_perms_T_1; // @[package.scala:16:47, :81:59] wire pma_checker_cmd_write_perms = pma_checker_cmd_write \| pma_checker__cmd_write_perms_T_2; // @[package.scala:81:59] wire [13:0] pma_checker__ae_array_T = pma_checker_misaligned ? pma_checker_eff_array : 14'h0; // @[TLB.scala:535:22, :550:77, :582:8] wire [13:0] pma_checker__ae_array_T_1 = ~pma_checker_lrscAllowed; // @[TLB.scala:580:24, :583:19] wire [13:0] pma_checker__ae_array_T_2 = pma_checker_cmd_lrsc ? pma_checker__ae_array_T_1 : 14'h0; // @[TLB.scala:570:33, :583:{8,19}] wire [13:0] pma_checker_ae_array = pma_checker__ae_array_T \| pma_checker__ae_array_T_2; // @[TLB.scala:582:{8,37}, :583:8] wire [13:0] pma_checker__ae_ld_array_T = ~pma_checker_pr_array; // @[TLB.scala:529:87, :586:46] wire [13:0] pma_checker__ae_ld_array_T_1 = pma_checker_ae_array \| pma_checker__ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}] wire [13:0] pma_checker_ae_ld_array = pma_checker_cmd_read ? pma_checker__ae_ld_array_T_1 : 14'h0; // @[TLB.scala:586:{24,44}] wire [13:0] pma_checker__ae_st_array_T = ~pma_checker_pw_array; // @[TLB.scala:531:87, :588:37] wire [13:0] pma_checker__ae_st_array_T_1 = pma_checker_ae_array \| pma_checker__ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}] wire [13:0] pma_checker__ae_st_array_T_2 = pma_checker_cmd_write_perms ? pma_checker__ae_st_array_T_1 : 14'h0; // @[TLB.scala:577:35, :588:{8,35}] wire [13:0] pma_checker__ae_st_array_T_3 = ~pma_checker_ppp_array_if_cached; // @[TLB.scala:544:39, :589:26] wire [13:0] pma_checker__ae_st_array_T_4 = pma_checker_cmd_put_partial ? pma_checker__ae_st_array_T_3 : 14'h0; // @[TLB.scala:573:41, :589:{8,26}] wire [13:0] pma_checker__ae_st_array_T_5 = pma_checker__ae_st_array_T_2 \| pma_checker__ae_st_array_T_4; // @[TLB.scala:588:{8,53}, :589:8] wire [13:0] pma_checker__ae_st_array_T_6 = ~pma_checker_pal_array_if_cached; // @[TLB.scala:546:39, :590:26] wire [13:0] pma_checker__ae_st_array_T_7 = pma_checker_cmd_amo_logical ? pma_checker__ae_st_array_T_6 : 14'h0; // @[TLB.scala:571:40, :590:{8,26}] wire [13:0] pma_checker__ae_st_array_T_8 = pma_checker__ae_st_array_T_5 \| pma_checker__ae_st_array_T_7; // @[TLB.scala:588:53, :589:53, :590:8] wire [13:0] pma_checker__ae_st_array_T_9 = ~pma_checker_paa_array_if_cached; // @[TLB.scala:545:39, :591:29] wire [13:0] pma_checker__ae_st_array_T_10 = pma_checker_cmd_amo_arithmetic ? pma_checker__ae_st_array_T_9 : 14'h0; // @[TLB.scala:572:43, :591:{8,29}] wire [13:0] pma_checker_ae_st_array = pma_checker__ae_st_array_T_8 \| pma_checker__ae_st_array_T_10; // @[TLB.scala:589:53, :590:53, :591:8] wire [13:0] pma_checker__must_alloc_array_T = ~pma_checker_ppp_array; // @[TLB.scala:539:22, :593:26] wire [13:0] pma_checker__must_alloc_array_T_1 = pma_checker_cmd_put_partial ? pma_checker__must_alloc_array_T : 14'h0; // @[TLB.scala:573:41, :593:{8,26}] wire [13:0] pma_checker__must_alloc_array_T_2 = ~pma_checker_pal_array; // @[TLB.scala:543:22, :594:26] wire [13:0] pma_checker__must_alloc_array_T_3 = pma_checker_cmd_amo_logical ? pma_checker__must_alloc_array_T_2 : 14'h0; // @[TLB.scala:571:40, :594:{8,26}] wire [13:0] pma_checker__must_alloc_array_T_4 = pma_checker__must_alloc_array_T_1 \| pma_checker__must_alloc_array_T_3; // @[TLB.scala:593:{8,43}, :594:8] wire [13:0] pma_checker__must_alloc_array_T_5 = ~pma_checker_paa_array; // @[TLB.scala:541:22, :595:29] wire [13:0] pma_checker__must_alloc_array_T_6 = pma_checker_cmd_amo_arithmetic ? pma_checker__must_alloc_array_T_5 : 14'h0; // @[TLB.scala:572:43, :595:{8,29}] wire [13:0] pma_checker__must_alloc_array_T_7 = pma_checker__must_alloc_array_T_4 \| pma_checker__must_alloc_array_T_6; // @[TLB.scala:593:43, :594:43, :595:8] wire [13:0] pma_checker__must_alloc_array_T_9 = {14{pma_checker_cmd_lrsc}}; // @[TLB.scala:570:33, :596:8] wire [13:0] pma_checker_must_alloc_array = pma_checker__must_alloc_array_T_7 \| pma_checker__must_alloc_array_T_9; // @[TLB.scala:594:43, :595:46, :596:8] wire [13:0] pma_checker__pf_ld_array_T_1 = ~pma_checker__pf_ld_array_T; // @[TLB.scala:597:{37,41}] wire [13:0] pma_checker__pf_ld_array_T_2 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73] wire [13:0] pma_checker__pf_ld_array_T_3 = pma_checker__pf_ld_array_T_1 & pma_checker__pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}] wire [13:0] pma_checker__pf_ld_array_T_4 = pma_checker__pf_ld_array_T_3 \| pma_checker_ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}] wire [13:0] pma_checker__pf_ld_array_T_5 = ~pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :597:106] wire [13:0] pma_checker__pf_ld_array_T_6 = pma_checker__pf_ld_array_T_4 & pma_checker__pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}] wire [13:0] pma_checker_pf_ld_array = pma_checker_cmd_read ? pma_checker__pf_ld_array_T_6 : 14'h0; // @[TLB.scala:597:{24,104}] wire [13:0] pma_checker__pf_st_array_T = ~pma_checker_w_array; // @[TLB.scala:521:20, :598:44] wire [13:0] pma_checker__pf_st_array_T_1 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55] wire [13:0] pma_checker__pf_st_array_T_2 = pma_checker__pf_st_array_T & pma_checker__pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}] wire [13:0] pma_checker__pf_st_array_T_3 = pma_checker__pf_st_array_T_2 \| pma_checker_ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}] wire [13:0] pma_checker__pf_st_array_T_4 = ~pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88] wire [13:0] pma_checker__pf_st_array_T_5 = pma_checker__pf_st_array_T_3 & pma_checker__pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}] wire [13:0] pma_checker_pf_st_array = pma_checker_cmd_write_perms ? pma_checker__pf_st_array_T_5 : 14'h0; // @[TLB.scala:577:35, :598:{24,86}] wire [13:0] pma_checker__pf_inst_array_T = ~pma_checker_x_array; // @[TLB.scala:522:20, :599:25] wire [13:0] pma_checker__pf_inst_array_T_1 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36] wire [13:0] pma_checker__pf_inst_array_T_2 = pma_checker__pf_inst_array_T & pma_checker__pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}] wire [13:0] pma_checker__pf_inst_array_T_3 = pma_checker__pf_inst_array_T_2 \| pma_checker_ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}] wire [13:0] pma_checker__pf_inst_array_T_4 = ~pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69] wire [13:0] pma_checker_pf_inst_array = pma_checker__pf_inst_array_T_3 & pma_checker__pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}] wire [13:0] pma_checker__gf_ld_array_T_4 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100] wire [13:0] pma_checker__gf_ld_array_T_5 = pma_checker__gf_ld_array_T_3 & pma_checker__gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}] wire [13:0] pma_checker__gf_st_array_T_3 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81] wire [13:0] pma_checker__gf_st_array_T_4 = pma_checker__gf_st_array_T_2 & pma_checker__gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}] wire [13:0] pma_checker__gf_inst_array_T_2 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64] wire [13:0] pma_checker__gf_inst_array_T_3 = pma_checker__gf_inst_array_T_1 & pma_checker__gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}] wire pma_checker__gpa_hits_hit_mask_T = pma_checker_vpn == 27'h0; // @[TLB.scala:335:30, :606:73] wire [13:0] pma_checker__io_resp_pf_ld_T_1 = pma_checker_pf_ld_array & 14'h2000; // @[TLB.scala:597:24, :633:57] wire pma_checker__io_resp_pf_ld_T_2 = \|pma_checker__io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}] assign pma_checker__io_resp_pf_ld_T_3 = pma_checker__io_resp_pf_ld_T_2; // @[TLB.scala:633:{41,65}] assign pma_checker_io_resp_pf_ld = pma_checker__io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire [13:0] pma_checker__io_resp_pf_st_T_1 = pma_checker_pf_st_array & 14'h2000; // @[TLB.scala:598:24, :634:64] wire pma_checker__io_resp_pf_st_T_2 = \|pma_checker__io_resp_pf_st_T_1; // @[TLB.scala:634:{64,72}] assign pma_checker__io_resp_pf_st_T_3 = pma_checker__io_resp_pf_st_T_2; // @[TLB.scala:634:{48,72}] assign pma_checker_io_resp_pf_st = pma_checker__io_resp_pf_st_T_3; // @[TLB.scala:634:48] wire [13:0] pma_checker__io_resp_pf_inst_T = pma_checker_pf_inst_array & 14'h2000; // @[TLB.scala:599:67, :635:47] wire pma_checker__io_resp_pf_inst_T_1 = \|pma_checker__io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}] assign pma_checker__io_resp_pf_inst_T_2 = pma_checker__io_resp_pf_inst_T_1; // @[TLB.scala:635:{29,55}] assign pma_checker_io_resp_pf_inst = pma_checker__io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire [13:0] pma_checker__io_resp_ae_ld_T = pma_checker_ae_ld_array & 14'h2000; // @[TLB.scala:586:24, :641:33] assign pma_checker__io_resp_ae_ld_T_1 = \|pma_checker__io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}] assign pma_checker_io_resp_ae_ld = pma_checker__io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire [13:0] pma_checker__io_resp_ae_st_T = pma_checker_ae_st_array & 14'h2000; // @[TLB.scala:590:53, :642:33] assign pma_checker__io_resp_ae_st_T_1 = \|pma_checker__io_resp_ae_st_T; // @[TLB.scala:642:{33,41}] assign pma_checker_io_resp_ae_st = pma_checker__io_resp_ae_st_T_1; // @[TLB.scala:642:41] wire [13:0] pma_checker__io_resp_ae_inst_T = ~pma_checker_px_array; // @[TLB.scala:533:87, :643:23] wire [13:0] pma_checker__io_resp_ae_inst_T_1 = pma_checker__io_resp_ae_inst_T & 14'h2000; // @[TLB.scala:643:{23,33}] assign pma_checker__io_resp_ae_inst_T_2 = \|pma_checker__io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}] assign pma_checker_io_resp_ae_inst = pma_checker__io_resp_ae_inst_T_2; // @[TLB.scala:643:41] assign pma_checker__io_resp_ma_ld_T = pma_checker_misaligned & pma_checker_cmd_read; // @[TLB.scala:550:77, :645:31] assign pma_checker_io_resp_ma_ld = pma_checker__io_resp_ma_ld_T; // @[TLB.scala:645:31] assign pma_checker__io_resp_ma_st_T = pma_checker_misaligned & pma_checker_cmd_write; // @[TLB.scala:550:77, :646:31] assign pma_checker_io_resp_ma_st = pma_checker__io_resp_ma_st_T; // @[TLB.scala:646:31] wire [13:0] pma_checker__io_resp_cacheable_T = pma_checker_c_array & 14'h2000; // @[TLB.scala:537:20, :648:33] assign pma_checker__io_resp_cacheable_T_1 = \|pma_checker__io_resp_cacheable_T; // @[TLB.scala:648:{33,41}] assign pma_checker_io_resp_cacheable = pma_checker__io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire [13:0] pma_checker__io_resp_must_alloc_T = pma_checker_must_alloc_array & 14'h2000; // @[TLB.scala:595:46, :649:43] assign pma_checker__io_resp_must_alloc_T_1 = \|pma_checker__io_resp_must_alloc_T; // @[TLB.scala:649:{43,51}] assign pma_checker_io_resp_must_alloc = pma_checker__io_resp_must_alloc_T_1; // @[TLB.scala:649:51] wire [13:0] pma_checker__io_resp_prefetchable_T = pma_checker_prefetchable_array & 14'h2000; // @[TLB.scala:547:31, :650:47] wire pma_checker__io_resp_prefetchable_T_1 = \|pma_checker__io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}] assign pma_checker__io_resp_prefetchable_T_2 = pma_checker__io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}] assign pma_checker_io_resp_prefetchable = pma_checker__io_resp_prefetchable_T_2; // @[TLB.scala:650:59] assign pma_checker__io_resp_paddr_T_1 = {pma_checker_ppn, pma_checker__io_resp_paddr_T}; // @[Mux.scala:30:73] assign pma_checker_io_resp_paddr = pma_checker__io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [27:0] pma_checker__io_resp_gpa_page_T_1 = {1'h0, pma_checker_vpn}; // @[TLB.scala:335:30, :657:36] wire [27:0] pma_checker_io_resp_gpa_page = pma_checker__io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}] wire [11:0] pma_checker_io_resp_gpa_offset = pma_checker__io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}] assign pma_checker__io_resp_gpa_T = {pma_checker_io_resp_gpa_page, pma_checker_io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8] assign pma_checker_io_resp_gpa = pma_checker__io_resp_gpa_T; // @[TLB.scala:659:8] wire pma_checker_ignore_1 = pma_checker__ignore_T_1; // @[TLB.scala:182:{28,34}] wire pma_checker_ignore_4 = pma_checker__ignore_T_4; // @[TLB.scala:182:{28,34}] wire pma_checker_ignore_7 = pma_checker__ignore_T_7; // @[TLB.scala:182:{28,34}] wire pma_checker_ignore_10 = pma_checker__ignore_T_10; // @[TLB.scala:182:{28,34}] wire replace; // @[Replacement.scala:37:29] wire [1:0] lfsr_lo_lo_lo = {_lfsr_prng_io_out_1, _lfsr_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_lo_lo_hi = {_lfsr_prng_io_out_3, _lfsr_prng_io_out_2}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_lo_lo = {lfsr_lo_lo_hi, lfsr_lo_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] lfsr_lo_hi_lo = {_lfsr_prng_io_out_5, _lfsr_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_lo_hi_hi = {_lfsr_prng_io_out_7, _lfsr_prng_io_out_6}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_lo_hi = {lfsr_lo_hi_hi, lfsr_lo_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] lfsr_lo = {lfsr_lo_hi, lfsr_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] lfsr_hi_lo_lo = {_lfsr_prng_io_out_9, _lfsr_prng_io_out_8}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_hi_lo_hi = {_lfsr_prng_io_out_11, _lfsr_prng_io_out_10}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_hi_lo = {lfsr_hi_lo_hi, lfsr_hi_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] lfsr_hi_hi_lo = {_lfsr_prng_io_out_13, _lfsr_prng_io_out_12}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_hi_hi_hi = {_lfsr_prng_io_out_15, _lfsr_prng_io_out_14}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_hi_hi = {lfsr_hi_hi_hi, lfsr_hi_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] lfsr_hi = {lfsr_hi_hi, lfsr_hi_lo}; // @[PRNG.scala:95:17] wire [15:0] lfsr = {lfsr_hi, lfsr_lo}; // @[PRNG.scala:95:17] wire metaArb__grant_T = metaArb_io_in_0_valid; // @[Arbiter.scala:45:68] wire [39:0] _metaArb_io_in_5_bits_addr_T_2; // @[DCache.scala:1018:36] wire [5:0] _metaArb_io_in_5_bits_idx_T; // @[DCache.scala:1017:44] wire metaArb__io_in_1_ready_T; // @[Arbiter.scala:153:19] wire [39:0] _metaArb_io_in_1_bits_addr_T_2; // @[DCache.scala:454:36] wire [5:0] _metaArb_io_in_1_bits_idx_T_2; // @[DCache.scala:453:35] wire [21:0] _metaArb_io_in_1_bits_data_T; // @[DCache.scala:458:14] wire metaArb__io_in_2_ready_T; // @[Arbiter.scala:153:19] wire _metaArb_io_in_2_valid_T; // @[DCache.scala:462:63] wire [39:0] _metaArb_io_in_2_bits_addr_T_2; // @[DCache.scala:466:36] wire [5:0] _metaArb_io_in_2_bits_idx_T; // @[DCache.scala:465:40] wire [7:0] s2_victim_or_hit_way; // @[DCache.scala:432:33] wire [21:0] _metaArb_io_in_2_bits_data_T_1; // @[DCache.scala:467:97] wire metaArb__io_in_3_ready_T; // @[Arbiter.scala:153:19] wire _metaArb_io_in_3_valid_T_2; // @[DCache.scala:741:53] wire [39:0] _metaArb_io_in_3_bits_addr_T_2; // @[DCache.scala:745:36] wire [5:0] _metaArb_io_in_3_bits_idx_T; // @[DCache.scala:744:40] wire [21:0] _metaArb_io_in_3_bits_data_T_18; // @[DCache.scala:746:134] wire metaArb__io_in_4_ready_T; // @[Arbiter.scala:153:19] wire _metaArb_io_in_4_valid_T_2; // @[package.scala:81:59] wire [39:0] _metaArb_io_in_4_bits_addr_T_2; // @[DCache.scala:912:36] wire [5:0] _metaArb_io_in_4_bits_idx_T; // @[DCache.scala:1200:47] wire [7:0] releaseWay; // @[DCache.scala:232:24] wire [21:0] _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:913:97] wire metaArb__io_in_5_ready_T; // @[Arbiter.scala:153:19] wire metaArb__io_in_6_ready_T; // @[Arbiter.scala:153:19] wire metaArb__io_in_7_ready_T; // @[Arbiter.scala:153:19] wire [5:0] _metaArb_io_in_7_bits_idx_T; // @[DCache.scala:263:58] wire metaArb__io_out_valid_T_1; // @[Arbiter.scala:154:31] wire [5:0] _s1_meta_WIRE = metaArb_io_out_bits_idx; // @[DCache.scala:135:28, :314:35] wire [39:0] metaArb_io_in_0_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_0_bits_idx; // @[DCache.scala:135:28] wire [39:0] metaArb_io_in_1_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_1_bits_idx; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_1_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_1_ready; // @[DCache.scala:135:28] wire [39:0] metaArb_io_in_2_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_2_bits_idx; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_2_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_2_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_2_ready; // @[DCache.scala:135:28] wire metaArb_io_in_2_valid; // @[DCache.scala:135:28] wire [39:0] metaArb_io_in_3_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_3_bits_idx; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_3_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_3_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_3_ready; // @[DCache.scala:135:28] wire metaArb_io_in_3_valid; // @[DCache.scala:135:28] wire [39:0] metaArb_io_in_4_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_4_bits_idx; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_4_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_4_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_4_ready; // @[DCache.scala:135:28] wire metaArb_io_in_4_valid; // @[DCache.scala:135:28] wire [39:0] metaArb_io_in_5_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_5_bits_idx; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_5_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_5_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_5_ready; // @[DCache.scala:135:28] wire [39:0] metaArb_io_in_6_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_6_bits_idx; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_6_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_6_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_6_ready; // @[DCache.scala:135:28] wire metaArb_io_in_6_valid; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_7_bits_idx; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_7_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_7_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_7_ready; // @[DCache.scala:135:28] wire metaArb_io_out_bits_write; // @[DCache.scala:135:28] wire [39:0] metaArb_io_out_bits_addr; // @[DCache.scala:135:28] wire [7:0] metaArb_io_out_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_out_bits_data; // @[DCache.scala:135:28] wire metaArb_io_out_valid; // @[DCache.scala:135:28] wire [2:0] metaArb_io_chosen; // @[DCache.scala:135:28] assign metaArb_io_chosen = metaArb_io_in_0_valid ? 3'h0 : metaArb_io_in_2_valid ? 3'h2 : metaArb_io_in_3_valid ? 3'h3 : metaArb_io_in_4_valid ? 3'h4 : {2'h3, ~metaArb_io_in_6_valid}; // @[Arbiter.scala:142:13, :145:26, :146:17] assign metaArb_io_out_bits_write = metaArb_io_in_0_valid \| metaArb_io_in_2_valid \| metaArb_io_in_3_valid \| metaArb_io_in_4_valid; // @[Arbiter.scala:145:26, :147:19] assign metaArb_io_out_bits_addr = metaArb_io_in_0_valid ? metaArb_io_in_0_bits_addr : metaArb_io_in_2_valid ? metaArb_io_in_2_bits_addr : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_addr : metaArb_io_in_4_valid ? metaArb_io_in_4_bits_addr : metaArb_io_in_6_valid ? metaArb_io_in_6_bits_addr : metaArb_io_in_7_bits_addr; // @[Arbiter.scala:143:15, :145:26, :147:19] assign metaArb_io_out_bits_idx = metaArb_io_in_0_valid ? metaArb_io_in_0_bits_idx : metaArb_io_in_2_valid ? metaArb_io_in_2_bits_idx : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_idx : metaArb_io_in_4_valid ? metaArb_io_in_4_bits_idx : metaArb_io_in_6_valid ? metaArb_io_in_6_bits_idx : metaArb_io_in_7_bits_idx; // @[Arbiter.scala:143:15, :145:26, :147:19] assign metaArb_io_out_bits_way_en = metaArb_io_in_0_valid ? 8'hFF : metaArb_io_in_2_valid ? metaArb_io_in_2_bits_way_en : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_way_en : metaArb_io_in_4_valid ? metaArb_io_in_4_bits_way_en : metaArb_io_in_6_valid ? metaArb_io_in_6_bits_way_en : metaArb_io_in_7_bits_way_en; // @[Arbiter.scala:143:15, :145:26, :147:19] assign metaArb_io_out_bits_data = metaArb_io_in_0_valid ? 22'h0 : metaArb_io_in_2_valid ? metaArb_io_in_2_bits_data : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_data : metaArb_io_in_4_valid ? metaArb_io_in_4_bits_data : metaArb_io_in_6_valid ? metaArb_io_in_6_bits_data : metaArb_io_in_7_bits_data; // @[Arbiter.scala:143:15, :145:26, :147:19] wire metaArb__grant_T_1 = metaArb__grant_T \| metaArb_io_in_2_valid; // @[Arbiter.scala:45:68] wire metaArb__grant_T_2 = metaArb__grant_T_1 \| metaArb_io_in_3_valid; // @[Arbiter.scala:45:68] wire metaArb__grant_T_3 = metaArb__grant_T_2 \| metaArb_io_in_4_valid; // @[Arbiter.scala:45:68] wire metaArb__grant_T_4 = metaArb__grant_T_3; // @[Arbiter.scala:45:68] wire metaArb__grant_T_5 = metaArb__grant_T_4 \| metaArb_io_in_6_valid; // @[Arbiter.scala:45:68] wire metaArb_grant_1 = ~metaArb_io_in_0_valid; // @[Arbiter.scala:45:78] assign metaArb__io_in_1_ready_T = metaArb_grant_1; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_2 = ~metaArb__grant_T; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_2_ready_T = metaArb_grant_2; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_3 = ~metaArb__grant_T_1; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_3_ready_T = metaArb_grant_3; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_4 = ~metaArb__grant_T_2; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_4_ready_T = metaArb_grant_4; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_5 = ~metaArb__grant_T_3; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_5_ready_T = metaArb_grant_5; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_6 = ~metaArb__grant_T_4; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_6_ready_T = metaArb_grant_6; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_7 = ~metaArb__grant_T_5; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_7_ready_T = metaArb_grant_7; // @[Arbiter.scala:45:78, :153:19] assign metaArb_io_in_1_ready = metaArb__io_in_1_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_2_ready = metaArb__io_in_2_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_3_ready = metaArb__io_in_3_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_4_ready = metaArb__io_in_4_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_5_ready = metaArb__io_in_5_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_6_ready = metaArb__io_in_6_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_7_ready = metaArb__io_in_7_ready_T; // @[Arbiter.scala:153:19] wire metaArb__io_out_valid_T = ~metaArb_grant_7; // @[Arbiter.scala:45:78, :154:19] assign metaArb__io_out_valid_T_1 = metaArb__io_out_valid_T \| metaArb_io_in_7_valid; // @[Arbiter.scala:154:{19,31}] assign metaArb_io_out_valid = metaArb__io_out_valid_T_1; // @[Arbiter.scala:154:31] wire _s1_meta_T_1; // @[DCache.scala:314:59] wire wmask_0; // @[DCache.scala:311:74] wire wmask_1; // @[DCache.scala:311:74] wire wmask_2; // @[DCache.scala:311:74] wire wmask_3; // @[DCache.scala:311:74] wire wmask_4; // @[DCache.scala:311:74] wire wmask_5; // @[DCache.scala:311:74] wire wmask_6; // @[DCache.scala:311:74] wire wmask_7; // @[DCache.scala:311:74] wire [21:0] _s1_meta_uncorrected_WIRE = _rockettile_dcache_tag_array_RW0_rdata[21:0]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_1 = _rockettile_dcache_tag_array_RW0_rdata[43:22]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_2 = _rockettile_dcache_tag_array_RW0_rdata[65:44]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_3 = _rockettile_dcache_tag_array_RW0_rdata[87:66]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_4 = _rockettile_dcache_tag_array_RW0_rdata[109:88]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_5 = _rockettile_dcache_tag_array_RW0_rdata[131:110]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_6 = _rockettile_dcache_tag_array_RW0_rdata[153:132]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_7 = _rockettile_dcache_tag_array_RW0_rdata[175:154]; // @[DescribedSRAM.scala:17:26] wire _dataArb_io_in_0_valid_T_12; // @[DCache.scala:516:27] wire pstore_drain; // @[DCache.scala:516:27] wire [63:0] _dataArb_io_in_0_bits_wdata_T_9; // @[package.scala:45:27] wire [7:0] _dataArb_io_in_0_bits_eccMask_T_17; // @[package.scala:45:27] wire [7:0] _dataArb_io_in_0_bits_way_en_T; // @[DCache.scala:550:38] wire dataArb__io_in_1_ready_T; // @[Arbiter.scala:153:19] wire [63:0] tl_d_data_encoded; // @[DCache.scala:324:31] wire dataArb__io_in_2_ready_T; // @[Arbiter.scala:153:19] wire _dataArb_io_in_2_valid_T_1; // @[DCache.scala:900:41] wire [11:0] _dataArb_io_in_2_bits_addr_T_4; // @[DCache.scala:903:72] wire dataArb__io_in_3_ready_T; // @[Arbiter.scala:153:19] wire _dataArb_io_in_3_valid_T_58; // @[DCache.scala:242:46] wire dataArb__io_out_valid_T_1; // @[Arbiter.scala:154:31] wire [11:0] dataArb_io_in_0_bits_addr; // @[DCache.scala:152:28] wire dataArb_io_in_0_bits_write; // @[DCache.scala:152:28] wire [63:0] dataArb_io_in_0_bits_wdata; // @[DCache.scala:152:28] wire dataArb_io_in_0_bits_wordMask; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_0_bits_eccMask; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_0_bits_way_en; // @[DCache.scala:152:28] wire dataArb_io_in_0_valid; // @[DCache.scala:152:28] wire [11:0] dataArb_io_in_1_bits_addr; // @[DCache.scala:152:28] wire dataArb_io_in_1_bits_write; // @[DCache.scala:152:28] wire [63:0] dataArb_io_in_1_bits_wdata; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_1_bits_way_en; // @[DCache.scala:152:28] wire dataArb_io_in_1_ready; // @[DCache.scala:152:28] wire dataArb_io_in_1_valid; // @[DCache.scala:152:28] wire [11:0] dataArb_io_in_2_bits_addr; // @[DCache.scala:152:28] wire [63:0] dataArb_io_in_2_bits_wdata; // @[DCache.scala:152:28] wire dataArb_io_in_2_ready; // @[DCache.scala:152:28] wire dataArb_io_in_2_valid; // @[DCache.scala:152:28] wire [11:0] dataArb_io_in_3_bits_addr; // @[DCache.scala:152:28] wire [63:0] dataArb_io_in_3_bits_wdata; // @[DCache.scala:152:28] wire dataArb_io_in_3_ready; // @[DCache.scala:152:28] wire dataArb_io_in_3_valid; // @[DCache.scala:152:28] wire [11:0] dataArb_io_out_bits_addr; // @[DCache.scala:152:28] wire dataArb_io_out_bits_write; // @[DCache.scala:152:28] wire [63:0] dataArb_io_out_bits_wdata; // @[DCache.scala:152:28] wire dataArb_io_out_bits_wordMask; // @[DCache.scala:152:28] wire [7:0] dataArb_io_out_bits_eccMask; // @[DCache.scala:152:28] wire [7:0] dataArb_io_out_bits_way_en; // @[DCache.scala:152:28] wire dataArb_io_out_valid; // @[DCache.scala:152:28] wire [1:0] dataArb_io_chosen; // @[DCache.scala:152:28] assign dataArb_io_chosen = dataArb_io_in_0_valid ? 2'h0 : dataArb_io_in_1_valid ? 2'h1 : {1'h1, ~dataArb_io_in_2_valid}; // @[Arbiter.scala:142:13, :145:26, :146:17] assign dataArb_io_out_bits_addr = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_addr : dataArb_io_in_1_valid ? dataArb_io_in_1_bits_addr : dataArb_io_in_2_valid ? dataArb_io_in_2_bits_addr : dataArb_io_in_3_bits_addr; // @[Arbiter.scala:143:15, :145:26, :147:19] assign dataArb_io_out_bits_write = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_write : dataArb_io_in_1_valid & dataArb_io_in_1_bits_write; // @[Arbiter.scala:145:26, :147:19] assign dataArb_io_out_bits_wdata = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_wdata : dataArb_io_in_1_valid ? dataArb_io_in_1_bits_wdata : dataArb_io_in_2_valid ? dataArb_io_in_2_bits_wdata : dataArb_io_in_3_bits_wdata; // @[Arbiter.scala:143:15, :145:26, :147:19] assign dataArb_io_out_bits_wordMask = ~dataArb_io_in_0_valid \| dataArb_io_in_0_bits_wordMask; // @[Arbiter.scala:145:26, :147:19] assign dataArb_io_out_bits_eccMask = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_eccMask : 8'hFF; // @[Arbiter.scala:145:26, :147:19] assign dataArb_io_out_bits_way_en = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_way_en : dataArb_io_in_1_valid ? dataArb_io_in_1_bits_way_en : 8'hFF; // @[Arbiter.scala:145:26, :147:19] wire dataArb__grant_T = dataArb_io_in_0_valid \| dataArb_io_in_1_valid; // @[Arbiter.scala:45:68] wire dataArb__grant_T_1 = dataArb__grant_T \| dataArb_io_in_2_valid; // @[Arbiter.scala:45:68] wire dataArb_grant_1 = ~dataArb_io_in_0_valid; // @[Arbiter.scala:45:78] assign dataArb__io_in_1_ready_T = dataArb_grant_1; // @[Arbiter.scala:45:78, :153:19] wire dataArb_grant_2 = ~dataArb__grant_T; // @[Arbiter.scala:45:{68,78}] assign dataArb__io_in_2_ready_T = dataArb_grant_2; // @[Arbiter.scala:45:78, :153:19] wire dataArb_grant_3 = ~dataArb__grant_T_1; // @[Arbiter.scala:45:{68,78}] assign dataArb__io_in_3_ready_T = dataArb_grant_3; // @[Arbiter.scala:45:78, :153:19] assign dataArb_io_in_1_ready = dataArb__io_in_1_ready_T; // @[Arbiter.scala:153:19] assign dataArb_io_in_2_ready = dataArb__io_in_2_ready_T; // @[Arbiter.scala:153:19] assign dataArb_io_in_3_ready = dataArb__io_in_3_ready_T; // @[Arbiter.scala:153:19] wire dataArb__io_out_valid_T = ~dataArb_grant_3; // @[Arbiter.scala:45:78, :154:19] assign dataArb__io_out_valid_T_1 = dataArb__io_out_valid_T \| dataArb_io_in_3_valid; // @[Arbiter.scala:154:{19,31}] assign dataArb_io_out_valid = dataArb__io_out_valid_T_1; // @[Arbiter.scala:154:31] wire _tl_out_a_valid_T_14; // @[DCache.scala:603:37] assign nodeOut_a_deq_valid = tl_out_a_valid; // @[Decoupled.scala:356:21] wire [2:0] _tl_out_a_bits_T_9_opcode; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_opcode = tl_out_a_bits_opcode; // @[Decoupled.scala:356:21] wire [2:0] _tl_out_a_bits_T_9_param; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_param = tl_out_a_bits_param; // @[Decoupled.scala:356:21] wire [3:0] _tl_out_a_bits_T_9_size; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_size = tl_out_a_bits_size; // @[Decoupled.scala:356:21] wire _tl_out_a_bits_T_9_source; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_source = tl_out_a_bits_source; // @[Decoupled.scala:356:21] wire [31:0] _tl_out_a_bits_T_9_address; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_address = tl_out_a_bits_address; // @[Decoupled.scala:356:21] wire [7:0] _tl_out_a_bits_T_9_mask; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_mask = tl_out_a_bits_mask; // @[Decoupled.scala:356:21] wire [63:0] _tl_out_a_bits_T_9_data; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_data = tl_out_a_bits_data; // @[Decoupled.scala:356:21] wire tl_out_a_ready; // @[DCache.scala:159:22] assign tl_out_a_ready = nodeOut_a_deq_ready; // @[Decoupled.scala:356:21] assign nodeOut_a_valid = nodeOut_a_deq_valid; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_opcode = nodeOut_a_deq_bits_opcode; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_param = nodeOut_a_deq_bits_param; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_size = nodeOut_a_deq_bits_size; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_source = nodeOut_a_deq_bits_source; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_address = nodeOut_a_deq_bits_address; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_mask = nodeOut_a_deq_bits_mask; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_data = nodeOut_a_deq_bits_data; // @[Decoupled.scala:356:21] wire _s1_valid_T = io_cpu_req_ready_0 & io_cpu_req_valid_0; // @[Decoupled.scala:51:35] reg s1_valid; // @[DCache.scala:182:25] wire _io_cpu_ordered_T_1 = s1_valid; // @[DCache.scala:182:25, :929:32] wire _GEN_39 = nodeOut_b_ready & nodeOut_b_valid; // @[Decoupled.scala:51:35] wire _s1_probe_T; // @[Decoupled.scala:51:35] assign _s1_probe_T = _GEN_39; // @[Decoupled.scala:51:35] wire _probe_bits_T; // @[Decoupled.scala:51:35] assign _probe_bits_T = _GEN_39; // @[Decoupled.scala:51:35] reg s1_probe; // @[DCache.scala:183:25] reg [2:0] probe_bits_opcode; // @[DCache.scala:184:29] reg [1:0] probe_bits_param; // @[DCache.scala:184:29] reg [3:0] probe_bits_size; // @[DCache.scala:184:29] wire [3:0] nackResponseMessage_size = probe_bits_size; // @[Edges.scala:416:17] wire [3:0] cleanReleaseMessage_size = probe_bits_size; // @[Edges.scala:416:17] wire [3:0] dirtyReleaseMessage_size = probe_bits_size; // @[Edges.scala:433:17] reg probe_bits_source; // @[DCache.scala:184:29] assign nodeOut_c_bits_source = probe_bits_source; // @[DCache.scala:184:29] wire nackResponseMessage_source = probe_bits_source; // @[Edges.scala:416:17] wire cleanReleaseMessage_source = probe_bits_source; // @[Edges.scala:416:17] wire dirtyReleaseMessage_source = probe_bits_source; // @[Edges.scala:433:17] reg [31:0] probe_bits_address; // @[DCache.scala:184:29] assign nodeOut_c_bits_address = probe_bits_address; // @[DCache.scala:184:29] wire [31:0] nackResponseMessage_address = probe_bits_address; // @[Edges.scala:416:17] wire [31:0] cleanReleaseMessage_address = probe_bits_address; // @[Edges.scala:416:17] wire [31:0] dirtyReleaseMessage_address = probe_bits_address; // @[Edges.scala:433:17] reg [7:0] probe_bits_mask; // @[DCache.scala:184:29] reg [63:0] probe_bits_data; // @[DCache.scala:184:29] reg probe_bits_corrupt; // @[DCache.scala:184:29] wire s1_nack; // @[DCache.scala:185:28] wire _s1_valid_masked_T = ~io_cpu_s1_kill_0; // @[DCache.scala:101:7, :186:37] wire s1_valid_masked = s1_valid & _s1_valid_masked_T; // @[DCache.scala:182:25, :186:{34,37}] wire _s1_valid_not_nacked_T = ~s1_nack; // @[DCache.scala:185:28, :187:41] wire s1_valid_not_nacked = s1_valid & _s1_valid_not_nacked_T; // @[DCache.scala:182:25, :187:{38,41}] wire _s0_clk_en_T = ~metaArb_io_out_bits_write; // @[DCache.scala:135:28, :190:43] wire s0_clk_en = metaArb_io_out_valid & _s0_clk_en_T; // @[DCache.scala:135:28, :190:{40,43}] wire _s1_tlb_req_T = s0_clk_en; // @[DCache.scala:190:40, :208:52] wire [39:0] _s0_req_addr_T_2; // @[DCache.scala:193:21] wire [39:0] s0_tlb_req_vaddr = s0_req_addr; // @[DCache.scala:192:24, :199:28] wire [4:0] s0_tlb_req_cmd = s0_req_cmd; // @[DCache.scala:192:24, :199:28] wire [1:0] s0_tlb_req_size = s0_req_size; // @[DCache.scala:192:24, :199:28] wire [1:0] s0_tlb_req_prv = s0_req_dprv; // @[DCache.scala:192:24, :199:28] wire s0_tlb_req_v = s0_req_dv; // @[DCache.scala:192:24, :199:28] wire s0_tlb_req_passthrough = s0_req_phys; // @[DCache.scala:192:24, :199:28] wire [33:0] _s0_req_addr_T = metaArb_io_out_bits_addr[39:6]; // @[DCache.scala:135:28, :193:47] wire [5:0] _s0_req_addr_T_1 = io_cpu_req_bits_addr_0[5:0]; // @[DCache.scala:101:7, :193:84] assign _s0_req_addr_T_2 = {_s0_req_addr_T, _s0_req_addr_T_1}; // @[DCache.scala:193:{21,47,84}] assign s0_req_addr = _s0_req_addr_T_2; // @[DCache.scala:192:24, :193:21] assign s0_req_phys = ~metaArb_io_in_7_ready \| io_cpu_req_bits_phys_0; // @[DCache.scala:101:7, :135:28, :192:24, :195:{9,34,48}] reg [39:0] s1_req_addr; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_vaddr = s1_req_addr; // @[DCache.scala:120:32, :196:25] reg [6:0] s1_req_tag; // @[DCache.scala:196:25] reg [4:0] s1_req_cmd; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_cmd = s1_req_cmd; // @[DCache.scala:120:32, :196:25] reg [1:0] s1_req_size; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_size = s1_req_size; // @[DCache.scala:120:32, :196:25] wire [1:0] s1_mask_xwr_size = s1_req_size; // @[DCache.scala:196:25] reg s1_req_signed; // @[DCache.scala:196:25] reg [1:0] s1_req_dprv; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_prv = s1_req_dprv; // @[DCache.scala:120:32, :196:25] reg s1_req_dv; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_v = s1_req_dv; // @[DCache.scala:120:32, :196:25] reg s1_req_phys; // @[DCache.scala:196:25] reg s1_req_no_resp; // @[DCache.scala:196:25] wire [27:0] _s1_vaddr_T = s1_req_addr[39:12]; // @[DCache.scala:196:25, :197:56] wire [11:0] _s1_vaddr_T_1 = s1_req_addr[11:0]; // @[DCache.scala:196:25, :197:78] wire [11:0] _s1_paddr_T_3 = s1_req_addr[11:0]; // @[DCache.scala:196:25, :197:78, :298:125] wire [39:0] s1_vaddr = {_s1_vaddr_T, _s1_vaddr_T_1}; // @[DCache.scala:197:{21,56,78}] reg [39:0] s1_tlb_req_vaddr; // @[DCache.scala:208:29] reg s1_tlb_req_passthrough; // @[DCache.scala:208:29] reg [1:0] s1_tlb_req_size; // @[DCache.scala:208:29] reg [4:0] s1_tlb_req_cmd; // @[DCache.scala:208:29] reg [1:0] s1_tlb_req_prv; // @[DCache.scala:208:29] reg s1_tlb_req_v; // @[DCache.scala:208:29] wire _GEN_40 = s1_req_cmd == 5'h0; // @[package.scala:16:47] wire _s1_read_T; // @[package.scala:16:47] assign _s1_read_T = _GEN_40; // @[package.scala:16:47] wire _pstore1_rmw_T; // @[package.scala:16:47] assign _pstore1_rmw_T = _GEN_40; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_1; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_1 = _GEN_40; // @[package.scala:16:47] wire _GEN_41 = s1_req_cmd == 5'h10; // @[package.scala:16:47] wire _s1_read_T_1; // @[package.scala:16:47] assign _s1_read_T_1 = _GEN_41; // @[package.scala:16:47] wire _pstore1_rmw_T_1; // @[package.scala:16:47] assign _pstore1_rmw_T_1 = _GEN_41; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_2; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_2 = _GEN_41; // @[package.scala:16:47] wire _GEN_42 = s1_req_cmd == 5'h6; // @[package.scala:16:47] wire _s1_read_T_2; // @[package.scala:16:47] assign _s1_read_T_2 = _GEN_42; // @[package.scala:16:47] wire _pstore1_rmw_T_2; // @[package.scala:16:47] assign _pstore1_rmw_T_2 = _GEN_42; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_3; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_3 = _GEN_42; // @[package.scala:16:47] wire _GEN_43 = s1_req_cmd == 5'h7; // @[package.scala:16:47] wire _s1_read_T_3; // @[package.scala:16:47] assign _s1_read_T_3 = _GEN_43; // @[package.scala:16:47] wire _s1_write_T_3; // @[Consts.scala:90:66] assign _s1_write_T_3 = _GEN_43; // @[package.scala:16:47] wire _pstore1_rmw_T_3; // @[package.scala:16:47] assign _pstore1_rmw_T_3 = _GEN_43; // @[package.scala:16:47] wire _pstore1_rmw_T_28; // @[Consts.scala:90:66] assign _pstore1_rmw_T_28 = _GEN_43; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_4; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_4 = _GEN_43; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_29; // @[Consts.scala:90:66] assign _io_cpu_perf_canAcceptLoadThenLoad_T_29 = _GEN_43; // @[package.scala:16:47] wire _s1_read_T_4 = _s1_read_T \| _s1_read_T_1; // @[package.scala:16:47, :81:59] wire _s1_read_T_5 = _s1_read_T_4 \| _s1_read_T_2; // @[package.scala:16:47, :81:59] wire _s1_read_T_6 = _s1_read_T_5 \| _s1_read_T_3; // @[package.scala:16:47, :81:59] wire _GEN_44 = s1_req_cmd == 5'h4; // @[package.scala:16:47] wire _s1_read_T_7; // @[package.scala:16:47] assign _s1_read_T_7 = _GEN_44; // @[package.scala:16:47] wire _s1_write_T_5; // @[package.scala:16:47] assign _s1_write_T_5 = _GEN_44; // @[package.scala:16:47] wire _pstore1_rmw_T_7; // @[package.scala:16:47] assign _pstore1_rmw_T_7 = _GEN_44; // @[package.scala:16:47] wire _pstore1_rmw_T_30; // @[package.scala:16:47] assign _pstore1_rmw_T_30 = _GEN_44; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_8; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_8 = _GEN_44; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_31; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_31 = _GEN_44; // @[package.scala:16:47] wire _GEN_45 = s1_req_cmd == 5'h9; // @[package.scala:16:47] wire _s1_read_T_8; // @[package.scala:16:47] assign _s1_read_T_8 = _GEN_45; // @[package.scala:16:47] wire _s1_write_T_6; // @[package.scala:16:47] assign _s1_write_T_6 = _GEN_45; // @[package.scala:16:47] wire _pstore1_rmw_T_8; // @[package.scala:16:47] assign _pstore1_rmw_T_8 = _GEN_45; // @[package.scala:16:47] wire _pstore1_rmw_T_31; // @[package.scala:16:47] assign _pstore1_rmw_T_31 = _GEN_45; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_9; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_9 = _GEN_45; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_32; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_32 = _GEN_45; // @[package.scala:16:47] wire _GEN_46 = s1_req_cmd == 5'hA; // @[package.scala:16:47] wire _s1_read_T_9; // @[package.scala:16:47] assign _s1_read_T_9 = _GEN_46; // @[package.scala:16:47] wire _s1_write_T_7; // @[package.scala:16:47] assign _s1_write_T_7 = _GEN_46; // @[package.scala:16:47] wire _pstore1_rmw_T_9; // @[package.scala:16:47] assign _pstore1_rmw_T_9 = _GEN_46; // @[package.scala:16:47] wire _pstore1_rmw_T_32; // @[package.scala:16:47] assign _pstore1_rmw_T_32 = _GEN_46; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_10; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_10 = _GEN_46; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_33; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_33 = _GEN_46; // @[package.scala:16:47] wire _GEN_47 = s1_req_cmd == 5'hB; // @[package.scala:16:47] wire _s1_read_T_10; // @[package.scala:16:47] assign _s1_read_T_10 = _GEN_47; // @[package.scala:16:47] wire _s1_write_T_8; // @[package.scala:16:47] assign _s1_write_T_8 = _GEN_47; // @[package.scala:16:47] wire _pstore1_rmw_T_10; // @[package.scala:16:47] assign _pstore1_rmw_T_10 = _GEN_47; // @[package.scala:16:47] wire _pstore1_rmw_T_33; // @[package.scala:16:47] assign _pstore1_rmw_T_33 = _GEN_47; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_11; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_11 = _GEN_47; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_34; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_34 = _GEN_47; // @[package.scala:16:47] wire _s1_read_T_11 = _s1_read_T_7 \| _s1_read_T_8; // @[package.scala:16:47, :81:59] wire _s1_read_T_12 = _s1_read_T_11 \| _s1_read_T_9; // @[package.scala:16:47, :81:59] wire _s1_read_T_13 = _s1_read_T_12 \| _s1_read_T_10; // @[package.scala:16:47, :81:59] wire _GEN_48 = s1_req_cmd == 5'h8; // @[package.scala:16:47] wire _s1_read_T_14; // @[package.scala:16:47] assign _s1_read_T_14 = _GEN_48; // @[package.scala:16:47] wire _s1_write_T_12; // @[package.scala:16:47] assign _s1_write_T_12 = _GEN_48; // @[package.scala:16:47] wire _pstore1_rmw_T_14; // @[package.scala:16:47] assign _pstore1_rmw_T_14 = _GEN_48; // @[package.scala:16:47] wire _pstore1_rmw_T_37; // @[package.scala:16:47] assign _pstore1_rmw_T_37 = _GEN_48; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_15; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_15 = _GEN_48; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_38; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_38 = _GEN_48; // @[package.scala:16:47] wire _GEN_49 = s1_req_cmd == 5'hC; // @[package.scala:16:47] wire _s1_read_T_15; // @[package.scala:16:47] assign _s1_read_T_15 = _GEN_49; // @[package.scala:16:47] wire _s1_write_T_13; // @[package.scala:16:47] assign _s1_write_T_13 = _GEN_49; // @[package.scala:16:47] wire _pstore1_rmw_T_15; // @[package.scala:16:47] assign _pstore1_rmw_T_15 = _GEN_49; // @[package.scala:16:47] wire _pstore1_rmw_T_38; // @[package.scala:16:47] assign _pstore1_rmw_T_38 = _GEN_49; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_16; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_16 = _GEN_49; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_39; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_39 = _GEN_49; // @[package.scala:16:47] wire _GEN_50 = s1_req_cmd == 5'hD; // @[package.scala:16:47] wire _s1_read_T_16; // @[package.scala:16:47] assign _s1_read_T_16 = _GEN_50; // @[package.scala:16:47] wire _s1_write_T_14; // @[package.scala:16:47] assign _s1_write_T_14 = _GEN_50; // @[package.scala:16:47] wire _pstore1_rmw_T_16; // @[package.scala:16:47] assign _pstore1_rmw_T_16 = _GEN_50; // @[package.scala:16:47] wire _pstore1_rmw_T_39; // @[package.scala:16:47] assign _pstore1_rmw_T_39 = _GEN_50; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_17; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_17 = _GEN_50; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_40; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_40 = _GEN_50; // @[package.scala:16:47] wire _GEN_51 = s1_req_cmd == 5'hE; // @[package.scala:16:47] wire _s1_read_T_17; // @[package.scala:16:47] assign _s1_read_T_17 = _GEN_51; // @[package.scala:16:47] wire _s1_write_T_15; // @[package.scala:16:47] assign _s1_write_T_15 = _GEN_51; // @[package.scala:16:47] wire _pstore1_rmw_T_17; // @[package.scala:16:47] assign _pstore1_rmw_T_17 = _GEN_51; // @[package.scala:16:47] wire _pstore1_rmw_T_40; // @[package.scala:16:47] assign _pstore1_rmw_T_40 = _GEN_51; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_18; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_18 = _GEN_51; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_41; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_41 = _GEN_51; // @[package.scala:16:47] wire _GEN_52 = s1_req_cmd == 5'hF; // @[package.scala:16:47] wire _s1_read_T_18; // @[package.scala:16:47] assign _s1_read_T_18 = _GEN_52; // @[package.scala:16:47] wire _s1_write_T_16; // @[package.scala:16:47] assign _s1_write_T_16 = _GEN_52; // @[package.scala:16:47] wire _pstore1_rmw_T_18; // @[package.scala:16:47] assign _pstore1_rmw_T_18 = _GEN_52; // @[package.scala:16:47] wire _pstore1_rmw_T_41; // @[package.scala:16:47] assign _pstore1_rmw_T_41 = _GEN_52; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_19; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_19 = _GEN_52; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_42; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_42 = _GEN_52; // @[package.scala:16:47] wire _s1_read_T_19 = _s1_read_T_14 \| _s1_read_T_15; // @[package.scala:16:47, :81:59] wire _s1_read_T_20 = _s1_read_T_19 \| _s1_read_T_16; // @[package.scala:16:47, :81:59] wire _s1_read_T_21 = _s1_read_T_20 \| _s1_read_T_17; // @[package.scala:16:47, :81:59] wire _s1_read_T_22 = _s1_read_T_21 \| _s1_read_T_18; // @[package.scala:16:47, :81:59] wire _s1_read_T_23 = _s1_read_T_13 \| _s1_read_T_22; // @[package.scala:81:59] wire s1_read = _s1_read_T_6 \| _s1_read_T_23; // @[package.scala:81:59] wire _GEN_53 = s1_req_cmd == 5'h1; // @[DCache.scala:196:25] wire _s1_write_T; // @[Consts.scala:90:32] assign _s1_write_T = _GEN_53; // @[Consts.scala:90:32] wire _pstore1_rmw_T_25; // @[Consts.scala:90:32] assign _pstore1_rmw_T_25 = _GEN_53; // @[Consts.scala:90:32] wire _io_cpu_perf_canAcceptLoadThenLoad_T_26; // @[Consts.scala:90:32] assign _io_cpu_perf_canAcceptLoadThenLoad_T_26 = _GEN_53; // @[Consts.scala:90:32] wire _T_20 = s1_req_cmd == 5'h11; // @[DCache.scala:196:25] wire _s1_write_T_1; // @[Consts.scala:90:49] assign _s1_write_T_1 = _T_20; // @[Consts.scala:90:49] wire _s1_mask_T; // @[DCache.scala:327:32] assign _s1_mask_T = _T_20; // @[DCache.scala:327:32] wire _pstore1_rmw_T_26; // @[Consts.scala:90:49] assign _pstore1_rmw_T_26 = _T_20; // @[Consts.scala:90:49] wire _pstore1_rmw_T_48; // @[DCache.scala:1191:35] assign _pstore1_rmw_T_48 = _T_20; // @[DCache.scala:1191:35] wire _io_cpu_perf_canAcceptLoadThenLoad_T_27; // @[Consts.scala:90:49] assign _io_cpu_perf_canAcceptLoadThenLoad_T_27 = _T_20; // @[Consts.scala:90:49] wire _io_cpu_perf_canAcceptLoadThenLoad_T_49; // @[DCache.scala:1191:35] assign _io_cpu_perf_canAcceptLoadThenLoad_T_49 = _T_20; // @[DCache.scala:1191:35] wire _s1_write_T_2 = _s1_write_T \| _s1_write_T_1; // @[Consts.scala:90:{32,42,49}] wire _s1_write_T_4 = _s1_write_T_2 \| _s1_write_T_3; // @[Consts.scala:90:{42,59,66}] wire _s1_write_T_9 = _s1_write_T_5 \| _s1_write_T_6; // @[package.scala:16:47, :81:59] wire _s1_write_T_10 = _s1_write_T_9 \| _s1_write_T_7; // @[package.scala:16:47, :81:59] wire _s1_write_T_11 = _s1_write_T_10 \| _s1_write_T_8; // @[package.scala:16:47, :81:59] wire _s1_write_T_17 = _s1_write_T_12 \| _s1_write_T_13; // @[package.scala:16:47, :81:59] wire _s1_write_T_18 = _s1_write_T_17 \| _s1_write_T_14; // @[package.scala:16:47, :81:59] wire _s1_write_T_19 = _s1_write_T_18 \| _s1_write_T_15; // @[package.scala:16:47, :81:59] wire _s1_write_T_20 = _s1_write_T_19 \| _s1_write_T_16; // @[package.scala:16:47, :81:59] wire _s1_write_T_21 = _s1_write_T_11 \| _s1_write_T_20; // @[package.scala:81:59] wire s1_write = _s1_write_T_4 \| _s1_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire s1_readwrite = s1_read \| s1_write; // @[DCache.scala:212:30] wire _s1_sfence_T = s1_req_cmd == 5'h14; // @[DCache.scala:196:25, :213:30] wire _GEN_54 = s1_req_cmd == 5'h15; // @[DCache.scala:196:25, :213:57] wire _s1_sfence_T_1; // @[DCache.scala:213:57] assign _s1_sfence_T_1 = _GEN_54; // @[DCache.scala:213:57] wire _tlb_io_sfence_bits_hv_T; // @[DCache.scala:283:39] assign _tlb_io_sfence_bits_hv_T = _GEN_54; // @[DCache.scala:213:57, :283:39] wire _s1_sfence_T_2 = _s1_sfence_T \| _s1_sfence_T_1; // @[DCache.scala:213:{30,43,57}] wire _GEN_55 = s1_req_cmd == 5'h16; // @[DCache.scala:196:25, :213:85] wire _s1_sfence_T_3; // @[DCache.scala:213:85] assign _s1_sfence_T_3 = _GEN_55; // @[DCache.scala:213:85] wire _tlb_io_sfence_bits_hg_T; // @[DCache.scala:284:39] assign _tlb_io_sfence_bits_hg_T = _GEN_55; // @[DCache.scala:213:85, :284:39] wire s1_sfence = _s1_sfence_T_2 \| _s1_sfence_T_3; // @[DCache.scala:213:{43,71,85}] wire _s1_flush_line_T = s1_req_cmd == 5'h5; // @[DCache.scala:196:25, :214:34] wire _s1_flush_line_T_1 = s1_req_size[0]; // @[DCache.scala:196:25, :214:64] wire _tlb_io_sfence_bits_rs1_T = s1_req_size[0]; // @[DCache.scala:196:25, :214:64, :279:40] wire s1_flush_line = _s1_flush_line_T & _s1_flush_line_T_1; // @[DCache.scala:214:{34,50,64}] reg s1_flush_valid; // @[DCache.scala:215:27] reg cached_grant_wait; // @[DCache.scala:223:34] reg resetting; // @[DCache.scala:224:26] assign metaArb_io_in_0_valid = resetting; // @[DCache.scala:135:28, :224:26] reg [8:0] flushCounter; // @[DCache.scala:225:29] reg release_ack_wait; // @[DCache.scala:226:33] reg [31:0] release_ack_addr; // @[DCache.scala:227:29] reg [3:0] release_state; // @[DCache.scala:228:30] reg [7:0] refill_way; // @[DCache.scala:229:23] assign metaArb_io_in_3_bits_way_en = refill_way; // @[DCache.scala:135:28, :229:23] assign dataArb_io_in_1_bits_way_en = refill_way; // @[DCache.scala:152:28, :229:23] wire _any_pstore_valid_T; // @[DCache.scala:508:36] wire any_pstore_valid; // @[DCache.scala:230:30] wire _T_106 = release_state == 4'h1; // @[package.scala:16:47] wire _inWriteback_T; // @[package.scala:16:47] assign _inWriteback_T = _T_106; // @[package.scala:16:47] wire _canAcceptCachedGrant_T; // @[package.scala:16:47] assign _canAcceptCachedGrant_T = _T_106; // @[package.scala:16:47] wire _inWriteback_T_1 = release_state == 4'h2; // @[package.scala:16:47] wire inWriteback = _inWriteback_T \| _inWriteback_T_1; // @[package.scala:16:47, :81:59] assign metaArb_io_in_4_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24] assign metaArb_io_in_5_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24] assign metaArb_io_in_6_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24] assign metaArb_io_in_7_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24] wire _io_cpu_req_ready_T = ~(\|release_state); // @[DCache.scala:228:30, :233:38] wire _io_cpu_req_ready_T_1 = ~cached_grant_wait; // @[DCache.scala:223:34, :233:54] wire _io_cpu_req_ready_T_2 = _io_cpu_req_ready_T & _io_cpu_req_ready_T_1; // @[DCache.scala:233:{38,51,54}] wire _io_cpu_req_ready_T_3 = ~s1_nack; // @[DCache.scala:185:28, :187:41, :233:76] wire _io_cpu_req_ready_T_4 = _io_cpu_req_ready_T_2 & _io_cpu_req_ready_T_3; // @[DCache.scala:233:{51,73,76}] reg uncachedInFlight_0; // @[DCache.scala:236:33] wire _s2_valid_cached_miss_T_2 = uncachedInFlight_0; // @[DCache.scala:236:33, :425:88] wire _s2_valid_uncached_pending_T_1 = uncachedInFlight_0; // @[DCache.scala:236:33, :430:92] wire _io_cpu_ordered_T_6 = uncachedInFlight_0; // @[DCache.scala:236:33, :929:142] wire _io_cpu_store_pending_T_24 = uncachedInFlight_0; // @[DCache.scala:236:33, :930:97] wire _clock_en_reg_T_22 = uncachedInFlight_0; // @[DCache.scala:236:33, :1072:50] reg [39:0] uncachedReqs_0_addr; // @[DCache.scala:237:25] wire [39:0] uncachedResp_addr = uncachedReqs_0_addr; // @[DCache.scala:237:25, :238:30] reg [6:0] uncachedReqs_0_tag; // @[DCache.scala:237:25] wire [6:0] uncachedResp_tag = uncachedReqs_0_tag; // @[DCache.scala:237:25, :238:30] reg [4:0] uncachedReqs_0_cmd; // @[DCache.scala:237:25] wire [4:0] uncachedResp_cmd = uncachedReqs_0_cmd; // @[DCache.scala:237:25, :238:30] reg [1:0] uncachedReqs_0_size; // @[DCache.scala:237:25] wire [1:0] uncachedResp_size = uncachedReqs_0_size; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_signed; // @[DCache.scala:237:25] wire uncachedResp_signed = uncachedReqs_0_signed; // @[DCache.scala:237:25, :238:30] reg [1:0] uncachedReqs_0_dprv; // @[DCache.scala:237:25] wire [1:0] uncachedResp_dprv = uncachedReqs_0_dprv; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_dv; // @[DCache.scala:237:25] wire uncachedResp_dv = uncachedReqs_0_dv; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_phys; // @[DCache.scala:237:25] wire uncachedResp_phys = uncachedReqs_0_phys; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_no_resp; // @[DCache.scala:237:25] wire uncachedResp_no_resp = uncachedReqs_0_no_resp; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_no_alloc; // @[DCache.scala:237:25] wire uncachedResp_no_alloc = uncachedReqs_0_no_alloc; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_no_xcpt; // @[DCache.scala:237:25] wire uncachedResp_no_xcpt = uncachedReqs_0_no_xcpt; // @[DCache.scala:237:25, :238:30] reg [63:0] uncachedReqs_0_data; // @[DCache.scala:237:25] wire [63:0] uncachedResp_data = uncachedReqs_0_data; // @[DCache.scala:237:25, :238:30] reg [7:0] uncachedReqs_0_mask; // @[DCache.scala:237:25] wire [7:0] uncachedResp_mask = uncachedReqs_0_mask; // @[DCache.scala:237:25, :238:30] wire _GEN_56 = io_cpu_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47] wire _s0_read_T; // @[package.scala:16:47] assign _s0_read_T = _GEN_56; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T = _GEN_56; // @[package.scala:16:47] wire _s1_did_read_T; // @[package.scala:16:47] assign _s1_did_read_T = _GEN_56; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T = _GEN_56; // @[package.scala:16:47] wire _GEN_57 = io_cpu_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47] wire _s0_read_T_1; // @[package.scala:16:47] assign _s0_read_T_1 = _GEN_57; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_1; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_1 = _GEN_57; // @[package.scala:16:47] wire _s1_did_read_T_1; // @[package.scala:16:47] assign _s1_did_read_T_1 = _GEN_57; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_1; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_1 = _GEN_57; // @[package.scala:16:47] wire _GEN_58 = io_cpu_req_bits_cmd_0 == 5'h6; // @[package.scala:16:47] wire _s0_read_T_2; // @[package.scala:16:47] assign _s0_read_T_2 = _GEN_58; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_2; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_2 = _GEN_58; // @[package.scala:16:47] wire _s1_did_read_T_2; // @[package.scala:16:47] assign _s1_did_read_T_2 = _GEN_58; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_2; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_2 = _GEN_58; // @[package.scala:16:47] wire _GEN_59 = io_cpu_req_bits_cmd_0 == 5'h7; // @[package.scala:16:47] wire _s0_read_T_3; // @[package.scala:16:47] assign _s0_read_T_3 = _GEN_59; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_3; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_3 = _GEN_59; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_28; // @[Consts.scala:90:66] assign _dataArb_io_in_3_valid_T_28 = _GEN_59; // @[package.scala:16:47] wire _s1_did_read_T_3; // @[package.scala:16:47] assign _s1_did_read_T_3 = _GEN_59; // @[package.scala:16:47] wire _s1_did_read_T_28; // @[Consts.scala:90:66] assign _s1_did_read_T_28 = _GEN_59; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_3; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_3 = _GEN_59; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_28; // @[Consts.scala:90:66] assign _pstore_drain_opportunistic_T_28 = _GEN_59; // @[package.scala:16:47] wire _s0_read_T_4 = _s0_read_T \| _s0_read_T_1; // @[package.scala:16:47, :81:59] wire _s0_read_T_5 = _s0_read_T_4 \| _s0_read_T_2; // @[package.scala:16:47, :81:59] wire _s0_read_T_6 = _s0_read_T_5 \| _s0_read_T_3; // @[package.scala:16:47, :81:59] wire _GEN_60 = io_cpu_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47] wire _s0_read_T_7; // @[package.scala:16:47] assign _s0_read_T_7 = _GEN_60; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_7; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_7 = _GEN_60; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_30; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_30 = _GEN_60; // @[package.scala:16:47] wire _s1_did_read_T_7; // @[package.scala:16:47] assign _s1_did_read_T_7 = _GEN_60; // @[package.scala:16:47] wire _s1_did_read_T_30; // @[package.scala:16:47] assign _s1_did_read_T_30 = _GEN_60; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_7; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_7 = _GEN_60; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_30; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_30 = _GEN_60; // @[package.scala:16:47] wire _GEN_61 = io_cpu_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47] wire _s0_read_T_8; // @[package.scala:16:47] assign _s0_read_T_8 = _GEN_61; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_8; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_8 = _GEN_61; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_31; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_31 = _GEN_61; // @[package.scala:16:47] wire _s1_did_read_T_8; // @[package.scala:16:47] assign _s1_did_read_T_8 = _GEN_61; // @[package.scala:16:47] wire _s1_did_read_T_31; // @[package.scala:16:47] assign _s1_did_read_T_31 = _GEN_61; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_8; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_8 = _GEN_61; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_31; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_31 = _GEN_61; // @[package.scala:16:47] wire _GEN_62 = io_cpu_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47] wire _s0_read_T_9; // @[package.scala:16:47] assign _s0_read_T_9 = _GEN_62; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_9; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_9 = _GEN_62; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_32; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_32 = _GEN_62; // @[package.scala:16:47] wire _s1_did_read_T_9; // @[package.scala:16:47] assign _s1_did_read_T_9 = _GEN_62; // @[package.scala:16:47] wire _s1_did_read_T_32; // @[package.scala:16:47] assign _s1_did_read_T_32 = _GEN_62; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_9; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_9 = _GEN_62; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_32; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_32 = _GEN_62; // @[package.scala:16:47] wire _GEN_63 = io_cpu_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47] wire _s0_read_T_10; // @[package.scala:16:47] assign _s0_read_T_10 = _GEN_63; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_10; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_10 = _GEN_63; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_33; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_33 = _GEN_63; // @[package.scala:16:47] wire _s1_did_read_T_10; // @[package.scala:16:47] assign _s1_did_read_T_10 = _GEN_63; // @[package.scala:16:47] wire _s1_did_read_T_33; // @[package.scala:16:47] assign _s1_did_read_T_33 = _GEN_63; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_10; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_10 = _GEN_63; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_33; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_33 = _GEN_63; // @[package.scala:16:47] wire _s0_read_T_11 = _s0_read_T_7 \| _s0_read_T_8; // @[package.scala:16:47, :81:59] wire _s0_read_T_12 = _s0_read_T_11 \| _s0_read_T_9; // @[package.scala:16:47, :81:59] wire _s0_read_T_13 = _s0_read_T_12 \| _s0_read_T_10; // @[package.scala:16:47, :81:59] wire _GEN_64 = io_cpu_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47] wire _s0_read_T_14; // @[package.scala:16:47] assign _s0_read_T_14 = _GEN_64; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_14; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_14 = _GEN_64; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_37; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_37 = _GEN_64; // @[package.scala:16:47] wire _s1_did_read_T_14; // @[package.scala:16:47] assign _s1_did_read_T_14 = _GEN_64; // @[package.scala:16:47] wire _s1_did_read_T_37; // @[package.scala:16:47] assign _s1_did_read_T_37 = _GEN_64; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_14; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_14 = _GEN_64; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_37; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_37 = _GEN_64; // @[package.scala:16:47] wire _GEN_65 = io_cpu_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47] wire _s0_read_T_15; // @[package.scala:16:47] assign _s0_read_T_15 = _GEN_65; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_15; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_15 = _GEN_65; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_38; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_38 = _GEN_65; // @[package.scala:16:47] wire _s1_did_read_T_15; // @[package.scala:16:47] assign _s1_did_read_T_15 = _GEN_65; // @[package.scala:16:47] wire _s1_did_read_T_38; // @[package.scala:16:47] assign _s1_did_read_T_38 = _GEN_65; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_15; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_15 = _GEN_65; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_38; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_38 = _GEN_65; // @[package.scala:16:47] wire _GEN_66 = io_cpu_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47] wire _s0_read_T_16; // @[package.scala:16:47] assign _s0_read_T_16 = _GEN_66; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_16; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_16 = _GEN_66; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_39; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_39 = _GEN_66; // @[package.scala:16:47] wire _s1_did_read_T_16; // @[package.scala:16:47] assign _s1_did_read_T_16 = _GEN_66; // @[package.scala:16:47] wire _s1_did_read_T_39; // @[package.scala:16:47] assign _s1_did_read_T_39 = _GEN_66; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_16; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_16 = _GEN_66; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_39; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_39 = _GEN_66; // @[package.scala:16:47] wire _GEN_67 = io_cpu_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47] wire _s0_read_T_17; // @[package.scala:16:47] assign _s0_read_T_17 = _GEN_67; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_17; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_17 = _GEN_67; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_40; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_40 = _GEN_67; // @[package.scala:16:47] wire _s1_did_read_T_17; // @[package.scala:16:47] assign _s1_did_read_T_17 = _GEN_67; // @[package.scala:16:47] wire _s1_did_read_T_40; // @[package.scala:16:47] assign _s1_did_read_T_40 = _GEN_67; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_17; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_17 = _GEN_67; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_40; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_40 = _GEN_67; // @[package.scala:16:47] wire _GEN_68 = io_cpu_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47] wire _s0_read_T_18; // @[package.scala:16:47] assign _s0_read_T_18 = _GEN_68; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_18; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_18 = _GEN_68; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_41; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_41 = _GEN_68; // @[package.scala:16:47] wire _s1_did_read_T_18; // @[package.scala:16:47] assign _s1_did_read_T_18 = _GEN_68; // @[package.scala:16:47] wire _s1_did_read_T_41; // @[package.scala:16:47] assign _s1_did_read_T_41 = _GEN_68; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_18; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_18 = _GEN_68; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_41; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_41 = _GEN_68; // @[package.scala:16:47] wire _s0_read_T_19 = _s0_read_T_14 \| _s0_read_T_15; // @[package.scala:16:47, :81:59] wire _s0_read_T_20 = _s0_read_T_19 \| _s0_read_T_16; // @[package.scala:16:47, :81:59] wire _s0_read_T_21 = _s0_read_T_20 \| _s0_read_T_17; // @[package.scala:16:47, :81:59] wire _s0_read_T_22 = _s0_read_T_21 \| _s0_read_T_18; // @[package.scala:16:47, :81:59] wire _s0_read_T_23 = _s0_read_T_13 \| _s0_read_T_22; // @[package.scala:81:59] wire s0_read = _s0_read_T_6 \| _s0_read_T_23; // @[package.scala:81:59] wire _GEN_69 = io_cpu_req_bits_cmd_0 == 5'h1; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_res_T; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_res_T = _GEN_69; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_25; // @[Consts.scala:90:32] assign _dataArb_io_in_3_valid_T_25 = _GEN_69; // @[package.scala:16:47] wire _s1_did_read_T_25; // @[Consts.scala:90:32] assign _s1_did_read_T_25 = _GEN_69; // @[package.scala:16:47] wire _pstore_drain_opportunistic_res_T; // @[package.scala:16:47] assign _pstore_drain_opportunistic_res_T = _GEN_69; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_25; // @[Consts.scala:90:32] assign _pstore_drain_opportunistic_T_25 = _GEN_69; // @[package.scala:16:47] wire _GEN_70 = io_cpu_req_bits_cmd_0 == 5'h3; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_res_T_1; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_res_T_1 = _GEN_70; // @[package.scala:16:47] wire _pstore_drain_opportunistic_res_T_1; // @[package.scala:16:47] assign _pstore_drain_opportunistic_res_T_1 = _GEN_70; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_res_T_2 = _dataArb_io_in_3_valid_res_T \| _dataArb_io_in_3_valid_res_T_1; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_res_T_3 = ~_dataArb_io_in_3_valid_res_T_2; // @[package.scala:81:59] wire dataArb_io_in_3_valid_res = _dataArb_io_in_3_valid_res_T_3; // @[DCache.scala:1185:{15,46}] wire _dataArb_io_in_3_valid_T_4 = _dataArb_io_in_3_valid_T \| _dataArb_io_in_3_valid_T_1; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_5 = _dataArb_io_in_3_valid_T_4 \| _dataArb_io_in_3_valid_T_2; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_6 = _dataArb_io_in_3_valid_T_5 \| _dataArb_io_in_3_valid_T_3; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_11 = _dataArb_io_in_3_valid_T_7 \| _dataArb_io_in_3_valid_T_8; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_12 = _dataArb_io_in_3_valid_T_11 \| _dataArb_io_in_3_valid_T_9; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_13 = _dataArb_io_in_3_valid_T_12 \| _dataArb_io_in_3_valid_T_10; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_19 = _dataArb_io_in_3_valid_T_14 \| _dataArb_io_in_3_valid_T_15; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_20 = _dataArb_io_in_3_valid_T_19 \| _dataArb_io_in_3_valid_T_16; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_21 = _dataArb_io_in_3_valid_T_20 \| _dataArb_io_in_3_valid_T_17; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_22 = _dataArb_io_in_3_valid_T_21 \| _dataArb_io_in_3_valid_T_18; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_23 = _dataArb_io_in_3_valid_T_13 \| _dataArb_io_in_3_valid_T_22; // @[package.scala:81:59] wire _dataArb_io_in_3_valid_T_24 = _dataArb_io_in_3_valid_T_6 \| _dataArb_io_in_3_valid_T_23; // @[package.scala:81:59] wire _GEN_71 = io_cpu_req_bits_cmd_0 == 5'h11; // @[DCache.scala:101:7] wire _dataArb_io_in_3_valid_T_26; // @[Consts.scala:90:49] assign _dataArb_io_in_3_valid_T_26 = _GEN_71; // @[Consts.scala:90:49] wire _dataArb_io_in_3_valid_T_48; // @[DCache.scala:1191:35] assign _dataArb_io_in_3_valid_T_48 = _GEN_71; // @[DCache.scala:1191:35] wire _s1_did_read_T_26; // @[Consts.scala:90:49] assign _s1_did_read_T_26 = _GEN_71; // @[Consts.scala:90:49] wire _s1_did_read_T_48; // @[DCache.scala:1191:35] assign _s1_did_read_T_48 = _GEN_71; // @[DCache.scala:1191:35] wire _pstore_drain_opportunistic_T_26; // @[Consts.scala:90:49] assign _pstore_drain_opportunistic_T_26 = _GEN_71; // @[Consts.scala:90:49] wire _pstore_drain_opportunistic_T_48; // @[DCache.scala:1191:35] assign _pstore_drain_opportunistic_T_48 = _GEN_71; // @[DCache.scala:1191:35] wire _dataArb_io_in_3_valid_T_27 = _dataArb_io_in_3_valid_T_25 \| _dataArb_io_in_3_valid_T_26; // @[Consts.scala:90:{32,42,49}] wire _dataArb_io_in_3_valid_T_29 = _dataArb_io_in_3_valid_T_27 \| _dataArb_io_in_3_valid_T_28; // @[Consts.scala:90:{42,59,66}] wire _dataArb_io_in_3_valid_T_34 = _dataArb_io_in_3_valid_T_30 \| _dataArb_io_in_3_valid_T_31; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_35 = _dataArb_io_in_3_valid_T_34 \| _dataArb_io_in_3_valid_T_32; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_36 = _dataArb_io_in_3_valid_T_35 \| _dataArb_io_in_3_valid_T_33; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_42 = _dataArb_io_in_3_valid_T_37 \| _dataArb_io_in_3_valid_T_38; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_43 = _dataArb_io_in_3_valid_T_42 \| _dataArb_io_in_3_valid_T_39; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_44 = _dataArb_io_in_3_valid_T_43 \| _dataArb_io_in_3_valid_T_40; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_45 = _dataArb_io_in_3_valid_T_44 \| _dataArb_io_in_3_valid_T_41; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_46 = _dataArb_io_in_3_valid_T_36 \| _dataArb_io_in_3_valid_T_45; // @[package.scala:81:59] wire _dataArb_io_in_3_valid_T_47 = _dataArb_io_in_3_valid_T_29 \| _dataArb_io_in_3_valid_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _dataArb_io_in_3_valid_T_50 = _dataArb_io_in_3_valid_T_48; // @[DCache.scala:1191:{35,45}] wire _dataArb_io_in_3_valid_T_51 = _dataArb_io_in_3_valid_T_47 & _dataArb_io_in_3_valid_T_50; // @[DCache.scala:1191:{23,45}] wire _dataArb_io_in_3_valid_T_52 = _dataArb_io_in_3_valid_T_24 \| _dataArb_io_in_3_valid_T_51; // @[DCache.scala:1190:21, :1191:23] wire _dataArb_io_in_3_valid_T_53 = ~_dataArb_io_in_3_valid_T_52; // @[DCache.scala:1186:12, :1190:21] wire _dataArb_io_in_3_valid_T_54 = _dataArb_io_in_3_valid_T_53 \| dataArb_io_in_3_valid_res; // @[DCache.scala:1185:46, :1186:{12,28}] wire _dataArb_io_in_3_valid_T_56 = ~_dataArb_io_in_3_valid_T_55; // @[DCache.scala:1186:11] wire _dataArb_io_in_3_valid_T_57 = ~_dataArb_io_in_3_valid_T_54; // @[DCache.scala:1186:{11,28}] assign _dataArb_io_in_3_valid_T_58 = io_cpu_req_valid_0 & dataArb_io_in_3_valid_res; // @[DCache.scala:101:7, :242:46, :1185:46] assign dataArb_io_in_3_valid = _dataArb_io_in_3_valid_T_58; // @[DCache.scala:152:28, :242:46] wire [27:0] _dataArb_io_in_3_bits_addr_T = io_cpu_req_bits_addr_0[39:12]; // @[DCache.scala:101:7, :245:89] wire [27:0] _metaArb_io_in_1_bits_addr_T = io_cpu_req_bits_addr_0[39:12]; // @[DCache.scala:101:7, :245:89, :454:58] wire [27:0] _metaArb_io_in_2_bits_addr_T = io_cpu_req_bits_addr_0[39:12]; // @[DCache.scala:101:7, :245:89, :466:58] wire [27:0] _metaArb_io_in_3_bits_addr_T = io_cpu_req_bits_addr_0[39:12]; // @[DCache.scala:101:7, :245:89, :745:58] wire [27:0] _metaArb_io_in_4_bits_addr_T = io_cpu_req_bits_addr_0[39:12]; // @[DCache.scala:101:7, :245:89, :912:58] wire [27:0] _metaArb_io_in_5_bits_addr_T = io_cpu_req_bits_addr_0[39:12]; // @[DCache.scala:101:7, :245:89, :1018:58] wire [11:0] _dataArb_io_in_3_bits_addr_T_1 = io_cpu_req_bits_addr_0[11:0]; // @[DCache.scala:101:7, :245:120] wire [39:0] _dataArb_io_in_3_bits_addr_T_2 = {_dataArb_io_in_3_bits_addr_T, _dataArb_io_in_3_bits_addr_T_1}; // @[DCache.scala:245:{36,89,120}] assign dataArb_io_in_3_bits_addr = _dataArb_io_in_3_bits_addr_T_2[11:0]; // @[DCache.scala:152:28, :245:{30,36}] wire _T_4 = ~dataArb_io_in_3_ready & s0_read; // @[DCache.scala:152:28, :258:{9,33}] wire _s1_did_read_T_4 = _s1_did_read_T \| _s1_did_read_T_1; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_5 = _s1_did_read_T_4 \| _s1_did_read_T_2; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_6 = _s1_did_read_T_5 \| _s1_did_read_T_3; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_11 = _s1_did_read_T_7 \| _s1_did_read_T_8; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_12 = _s1_did_read_T_11 \| _s1_did_read_T_9; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_13 = _s1_did_read_T_12 \| _s1_did_read_T_10; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_19 = _s1_did_read_T_14 \| _s1_did_read_T_15; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_20 = _s1_did_read_T_19 \| _s1_did_read_T_16; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_21 = _s1_did_read_T_20 \| _s1_did_read_T_17; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_22 = _s1_did_read_T_21 \| _s1_did_read_T_18; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_23 = _s1_did_read_T_13 \| _s1_did_read_T_22; // @[package.scala:81:59] wire _s1_did_read_T_24 = _s1_did_read_T_6 \| _s1_did_read_T_23; // @[package.scala:81:59] wire _s1_did_read_T_27 = _s1_did_read_T_25 \| _s1_did_read_T_26; // @[Consts.scala:90:{32,42,49}] wire _s1_did_read_T_29 = _s1_did_read_T_27 \| _s1_did_read_T_28; // @[Consts.scala:90:{42,59,66}] wire _s1_did_read_T_34 = _s1_did_read_T_30 \| _s1_did_read_T_31; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_35 = _s1_did_read_T_34 \| _s1_did_read_T_32; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_36 = _s1_did_read_T_35 \| _s1_did_read_T_33; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_42 = _s1_did_read_T_37 \| _s1_did_read_T_38; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_43 = _s1_did_read_T_42 \| _s1_did_read_T_39; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_44 = _s1_did_read_T_43 \| _s1_did_read_T_40; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_45 = _s1_did_read_T_44 \| _s1_did_read_T_41; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_46 = _s1_did_read_T_36 \| _s1_did_read_T_45; // @[package.scala:81:59] wire _s1_did_read_T_47 = _s1_did_read_T_29 \| _s1_did_read_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _s1_did_read_T_50 = _s1_did_read_T_48; // @[DCache.scala:1191:{35,45}] wire _s1_did_read_T_51 = _s1_did_read_T_47 & _s1_did_read_T_50; // @[DCache.scala:1191:{23,45}] wire _s1_did_read_T_52 = _s1_did_read_T_24 \| _s1_did_read_T_51; // @[DCache.scala:1190:21, :1191:23] wire _s1_did_read_T_53 = io_cpu_req_valid_0 & _s1_did_read_T_52; // @[DCache.scala:101:7, :259:75, :1190:21] wire _s1_did_read_T_54 = dataArb_io_in_3_ready & _s1_did_read_T_53; // @[DCache.scala:152:28, :259:{54,75}] reg s1_did_read; // @[DCache.scala:259:30] wire _s2_data_word_en_T = s1_did_read; // @[DCache.scala:259:30, :367:63] assign _metaArb_io_in_7_bits_idx_T = _dataArb_io_in_3_bits_addr_T_2[11:6]; // @[DCache.scala:245:36, :263:58] assign metaArb_io_in_7_bits_idx = _metaArb_io_in_7_bits_idx_T; // @[DCache.scala:135:28, :263:58] wire _s1_cmd_uses_tlb_T = s1_readwrite \| s1_flush_line; // @[DCache.scala:212:30, :214:50, :270:38] wire _s1_cmd_uses_tlb_T_1 = s1_req_cmd == 5'h17; // @[DCache.scala:196:25, :270:69] wire s1_cmd_uses_tlb = _s1_cmd_uses_tlb_T \| _s1_cmd_uses_tlb_T_1; // @[DCache.scala:270:{38,55,69}] wire _tlb_io_req_valid_T = ~io_cpu_s1_kill_0; // @[DCache.scala:101:7, :186:37, :273:55] wire _tlb_io_req_valid_T_1 = s1_valid & _tlb_io_req_valid_T; // @[DCache.scala:182:25, :273:{52,55}] wire _tlb_io_req_valid_T_2 = _tlb_io_req_valid_T_1 & s1_cmd_uses_tlb; // @[DCache.scala:270:55, :273:{52,71}] wire _tlb_io_req_valid_T_3 = _tlb_io_req_valid_T_2; // @[DCache.scala:273:{40,71}] wire _s1_xcpt_valid_T_1 = _tlb_io_req_valid_T_3; // @[DCache.scala:273:40, :932:40] wire _T_10 = ~_tlb_io_req_ready & ~io_ptw_resp_valid_0 & ~io_cpu_req_bits_phys_0; // @[DCache.scala:101:7, :119:19, :275:{9,27,30,53,56}] wire _T_14 = s1_valid & s1_cmd_uses_tlb & _tlb_io_resp_miss; // @[DCache.scala:119:19, :182:25, :270:55, :276:{39,58}] wire _tlb_io_sfence_valid_T = ~io_cpu_s1_kill_0; // @[DCache.scala:101:7, :186:37, :278:38] wire _tlb_io_sfence_valid_T_1 = s1_valid & _tlb_io_sfence_valid_T; // @[DCache.scala:182:25, :278:{35,38}] wire _tlb_io_sfence_valid_T_2 = _tlb_io_sfence_valid_T_1 & s1_sfence; // @[DCache.scala:213:71, :278:{35,54}] wire _tlb_io_sfence_bits_rs2_T = s1_req_size[1]; // @[DCache.scala:196:25, :280:40] wire [19:0] _s1_paddr_T = s1_req_addr[31:12]; // @[DCache.scala:196:25, :298:55] wire [19:0] _s1_paddr_T_1 = _tlb_io_resp_paddr[31:12]; // @[DCache.scala:119:19, :298:99] wire [19:0] _s1_paddr_T_2 = _s1_paddr_T_1; // @[DCache.scala:298:{25,99}] wire [31:0] s1_paddr = {_s1_paddr_T_2, _s1_paddr_T_3}; // @[DCache.scala:298:{21,25,125}] wire [2:0] _s1_victim_way_T; // @[package.scala:163:13] wire [2:0] s1_victim_way; // @[DCache.scala:299:27] assign rockettile_dcache_tag_array_MPORT_en = metaArb_io_out_valid & metaArb_io_out_bits_write; // @[DCache.scala:135:28, :310:27] assign wmask_0 = metaArb_io_out_bits_way_en[0]; // @[DCache.scala:135:28, :311:74] assign wmask_1 = metaArb_io_out_bits_way_en[1]; // @[DCache.scala:135:28, :311:74] assign wmask_2 = metaArb_io_out_bits_way_en[2]; // @[DCache.scala:135:28, :311:74] assign wmask_3 = metaArb_io_out_bits_way_en[3]; // @[DCache.scala:135:28, :311:74] assign wmask_4 = metaArb_io_out_bits_way_en[4]; // @[DCache.scala:135:28, :311:74] assign wmask_5 = metaArb_io_out_bits_way_en[5]; // @[DCache.scala:135:28, :311:74] assign wmask_6 = metaArb_io_out_bits_way_en[6]; // @[DCache.scala:135:28, :311:74] assign wmask_7 = metaArb_io_out_bits_way_en[7]; // @[DCache.scala:135:28, :311:74] wire _s1_meta_T = ~metaArb_io_out_bits_write; // @[DCache.scala:135:28, :190:43, :314:62] assign _s1_meta_T_1 = metaArb_io_out_valid & _s1_meta_T; // @[DCache.scala:135:28, :314:{59,62}] wire [1:0] _s1_meta_uncorrected_T_1; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_0_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_0_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T = _s1_meta_uncorrected_WIRE[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_0_tag = _s1_meta_uncorrected_T; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_1 = _s1_meta_uncorrected_WIRE[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_0_coh_state = _s1_meta_uncorrected_T_1; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_3; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_2; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_1_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_1_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_2 = _s1_meta_uncorrected_WIRE_1[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_1_tag = _s1_meta_uncorrected_T_2; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_3 = _s1_meta_uncorrected_WIRE_1[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_1_coh_state = _s1_meta_uncorrected_T_3; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_5; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_4; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_2_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_2_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_4 = _s1_meta_uncorrected_WIRE_2[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_2_tag = _s1_meta_uncorrected_T_4; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_5 = _s1_meta_uncorrected_WIRE_2[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_2_coh_state = _s1_meta_uncorrected_T_5; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_7; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_6; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_3_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_3_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_6 = _s1_meta_uncorrected_WIRE_3[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_3_tag = _s1_meta_uncorrected_T_6; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_7 = _s1_meta_uncorrected_WIRE_3[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_3_coh_state = _s1_meta_uncorrected_T_7; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_9; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_8; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_4_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_4_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_8 = _s1_meta_uncorrected_WIRE_4[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_4_tag = _s1_meta_uncorrected_T_8; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_9 = _s1_meta_uncorrected_WIRE_4[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_4_coh_state = _s1_meta_uncorrected_T_9; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_11; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_10; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_5_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_5_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_10 = _s1_meta_uncorrected_WIRE_5[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_5_tag = _s1_meta_uncorrected_T_10; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_11 = _s1_meta_uncorrected_WIRE_5[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_5_coh_state = _s1_meta_uncorrected_T_11; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_13; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_12; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_6_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_6_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_12 = _s1_meta_uncorrected_WIRE_6[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_6_tag = _s1_meta_uncorrected_T_12; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_13 = _s1_meta_uncorrected_WIRE_6[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_6_coh_state = _s1_meta_uncorrected_T_13; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_15; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_14; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_7_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_7_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_14 = _s1_meta_uncorrected_WIRE_7[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_7_tag = _s1_meta_uncorrected_T_14; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_15 = _s1_meta_uncorrected_WIRE_7[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_7_coh_state = _s1_meta_uncorrected_T_15; // @[DCache.scala:315:80] wire [19:0] s1_tag = s1_paddr[31:12]; // @[DCache.scala:298:21, :316:29] wire _s1_meta_hit_way_T = \|s1_meta_uncorrected_0_coh_state; // @[Metadata.scala:50:45] wire _GEN_72 = s1_meta_uncorrected_0_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_1; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_1 = _GEN_72; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T = _GEN_72; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_2 = _s1_meta_hit_way_T & _s1_meta_hit_way_T_1; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_3 = \|s1_meta_uncorrected_1_coh_state; // @[Metadata.scala:50:45] wire _GEN_73 = s1_meta_uncorrected_1_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_4; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_4 = _GEN_73; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_4; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_4 = _GEN_73; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_5 = _s1_meta_hit_way_T_3 & _s1_meta_hit_way_T_4; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_6 = \|s1_meta_uncorrected_2_coh_state; // @[Metadata.scala:50:45] wire _GEN_74 = s1_meta_uncorrected_2_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_7; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_7 = _GEN_74; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_8; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_8 = _GEN_74; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_8 = _s1_meta_hit_way_T_6 & _s1_meta_hit_way_T_7; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_9 = \|s1_meta_uncorrected_3_coh_state; // @[Metadata.scala:50:45] wire _GEN_75 = s1_meta_uncorrected_3_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_10; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_10 = _GEN_75; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_12; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_12 = _GEN_75; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_11 = _s1_meta_hit_way_T_9 & _s1_meta_hit_way_T_10; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_12 = \|s1_meta_uncorrected_4_coh_state; // @[Metadata.scala:50:45] wire _GEN_76 = s1_meta_uncorrected_4_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_13; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_13 = _GEN_76; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_16; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_16 = _GEN_76; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_14 = _s1_meta_hit_way_T_12 & _s1_meta_hit_way_T_13; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_15 = \|s1_meta_uncorrected_5_coh_state; // @[Metadata.scala:50:45] wire _GEN_77 = s1_meta_uncorrected_5_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_16; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_16 = _GEN_77; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_20; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_20 = _GEN_77; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_17 = _s1_meta_hit_way_T_15 & _s1_meta_hit_way_T_16; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_18 = \|s1_meta_uncorrected_6_coh_state; // @[Metadata.scala:50:45] wire _GEN_78 = s1_meta_uncorrected_6_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_19; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_19 = _GEN_78; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_24; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_24 = _GEN_78; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_20 = _s1_meta_hit_way_T_18 & _s1_meta_hit_way_T_19; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_21 = \|s1_meta_uncorrected_7_coh_state; // @[Metadata.scala:50:45] wire _GEN_79 = s1_meta_uncorrected_7_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_22; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_22 = _GEN_79; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_28; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_28 = _GEN_79; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_23 = _s1_meta_hit_way_T_21 & _s1_meta_hit_way_T_22; // @[Metadata.scala:50:45] wire [1:0] s1_meta_hit_way_lo_lo = {_s1_meta_hit_way_T_5, _s1_meta_hit_way_T_2}; // @[package.scala:45:27] wire [1:0] s1_meta_hit_way_lo_hi = {_s1_meta_hit_way_T_11, _s1_meta_hit_way_T_8}; // @[package.scala:45:27] wire [3:0] s1_meta_hit_way_lo = {s1_meta_hit_way_lo_hi, s1_meta_hit_way_lo_lo}; // @[package.scala:45:27] wire [1:0] s1_meta_hit_way_hi_lo = {_s1_meta_hit_way_T_17, _s1_meta_hit_way_T_14}; // @[package.scala:45:27] wire [1:0] s1_meta_hit_way_hi_hi = {_s1_meta_hit_way_T_23, _s1_meta_hit_way_T_20}; // @[package.scala:45:27] wire [3:0] s1_meta_hit_way_hi = {s1_meta_hit_way_hi_hi, s1_meta_hit_way_hi_lo}; // @[package.scala:45:27] wire [7:0] s1_hit_way = {s1_meta_hit_way_hi, s1_meta_hit_way_lo}; // @[package.scala:45:27] wire _s1_meta_hit_state_T_1 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_2 = _s1_meta_hit_state_T & _s1_meta_hit_state_T_1; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_3 = _s1_meta_hit_state_T_2 ? s1_meta_uncorrected_0_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_5 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_6 = _s1_meta_hit_state_T_4 & _s1_meta_hit_state_T_5; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_7 = _s1_meta_hit_state_T_6 ? s1_meta_uncorrected_1_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_9 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_10 = _s1_meta_hit_state_T_8 & _s1_meta_hit_state_T_9; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_11 = _s1_meta_hit_state_T_10 ? s1_meta_uncorrected_2_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_13 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_14 = _s1_meta_hit_state_T_12 & _s1_meta_hit_state_T_13; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_15 = _s1_meta_hit_state_T_14 ? s1_meta_uncorrected_3_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_17 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_18 = _s1_meta_hit_state_T_16 & _s1_meta_hit_state_T_17; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_19 = _s1_meta_hit_state_T_18 ? s1_meta_uncorrected_4_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_21 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_22 = _s1_meta_hit_state_T_20 & _s1_meta_hit_state_T_21; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_23 = _s1_meta_hit_state_T_22 ? s1_meta_uncorrected_5_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_25 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_26 = _s1_meta_hit_state_T_24 & _s1_meta_hit_state_T_25; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_27 = _s1_meta_hit_state_T_26 ? s1_meta_uncorrected_6_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_29 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_30 = _s1_meta_hit_state_T_28 & _s1_meta_hit_state_T_29; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_31 = _s1_meta_hit_state_T_30 ? s1_meta_uncorrected_7_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire [1:0] _s1_meta_hit_state_T_32 = _s1_meta_hit_state_T_3 \| _s1_meta_hit_state_T_7; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_T_33 = _s1_meta_hit_state_T_32 \| _s1_meta_hit_state_T_11; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_T_34 = _s1_meta_hit_state_T_33 \| _s1_meta_hit_state_T_15; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_T_35 = _s1_meta_hit_state_T_34 \| _s1_meta_hit_state_T_19; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_T_36 = _s1_meta_hit_state_T_35 \| _s1_meta_hit_state_T_23; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_T_37 = _s1_meta_hit_state_T_36 \| _s1_meta_hit_state_T_27; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_T_38 = _s1_meta_hit_state_T_37 \| _s1_meta_hit_state_T_31; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_WIRE = _s1_meta_hit_state_T_38; // @[DCache.scala:320:{19,32}] wire [1:0] _s1_meta_hit_state_T_39; // @[DCache.scala:320:32] wire [1:0] s1_hit_state_state; // @[DCache.scala:320:32] assign _s1_meta_hit_state_T_39 = _s1_meta_hit_state_WIRE; // @[DCache.scala:320:32] assign s1_hit_state_state = _s1_meta_hit_state_T_39; // @[DCache.scala:320:32] wire [7:0] _s1_data_way_T = inWriteback ? releaseWay : s1_hit_way; // @[package.scala:45:27, :81:59] wire [8:0] s1_data_way; // @[DCache.scala:323:32] wire [7:0] _tl_d_data_encoded_T = nodeOut_d_bits_data[7:0]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_14 = nodeOut_d_bits_data[7:0]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_1 = nodeOut_d_bits_data[15:8]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_15 = nodeOut_d_bits_data[15:8]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_2 = nodeOut_d_bits_data[23:16]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_16 = nodeOut_d_bits_data[23:16]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_3 = nodeOut_d_bits_data[31:24]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_17 = nodeOut_d_bits_data[31:24]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_4 = nodeOut_d_bits_data[39:32]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_18 = nodeOut_d_bits_data[39:32]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_5 = nodeOut_d_bits_data[47:40]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_19 = nodeOut_d_bits_data[47:40]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_6 = nodeOut_d_bits_data[55:48]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_20 = nodeOut_d_bits_data[55:48]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_7 = nodeOut_d_bits_data[63:56]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_21 = nodeOut_d_bits_data[63:56]; // @[package.scala:211:50] wire [15:0] tl_d_data_encoded_lo_lo = {_tl_d_data_encoded_T_1, _tl_d_data_encoded_T}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_lo_hi = {_tl_d_data_encoded_T_3, _tl_d_data_encoded_T_2}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_lo = {tl_d_data_encoded_lo_hi, tl_d_data_encoded_lo_lo}; // @[package.scala:45:27] wire [15:0] tl_d_data_encoded_hi_lo = {_tl_d_data_encoded_T_5, _tl_d_data_encoded_T_4}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_hi_hi = {_tl_d_data_encoded_T_7, _tl_d_data_encoded_T_6}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_hi = {tl_d_data_encoded_hi_hi, tl_d_data_encoded_hi_lo}; // @[package.scala:45:27] wire [63:0] _tl_d_data_encoded_T_8 = {tl_d_data_encoded_hi, tl_d_data_encoded_lo}; // @[package.scala:45:27] wire [63:0] _tl_d_data_encoded_T_22; // @[package.scala:45:27] assign dataArb_io_in_1_bits_wdata = tl_d_data_encoded; // @[DCache.scala:152:28, :324:31] assign dataArb_io_in_2_bits_wdata = tl_d_data_encoded; // @[DCache.scala:152:28, :324:31] assign dataArb_io_in_3_bits_wdata = tl_d_data_encoded; // @[DCache.scala:152:28, :324:31] wire [63:0] s1_all_data_ways_8 = tl_d_data_encoded; // @[DCache.scala:324:31, :325:33] wire [63:0] s2_data_s1_way_words_0_0 = s1_all_data_ways_0; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_1_0 = s1_all_data_ways_1; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_2_0 = s1_all_data_ways_2; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_3_0 = s1_all_data_ways_3; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_4_0 = s1_all_data_ways_4; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_5_0 = s1_all_data_ways_5; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_6_0 = s1_all_data_ways_6; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_7_0 = s1_all_data_ways_7; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_8_0 = s1_all_data_ways_8; // @[package.scala:211:50] wire _s1_mask_xwr_upper_T = s1_req_addr[0]; // @[DCache.scala:196:25] wire _s1_mask_xwr_lower_T = s1_req_addr[0]; // @[DCache.scala:196:25] wire _s1_mask_xwr_upper_T_1 = _s1_mask_xwr_upper_T; // @[AMOALU.scala:20:{22,27}] wire _s1_mask_xwr_upper_T_2 = \|s1_mask_xwr_size; // @[AMOALU.scala:11:18, :20:53] wire _s1_mask_xwr_upper_T_3 = _s1_mask_xwr_upper_T_2; // @[AMOALU.scala:20:{47,53}] wire s1_mask_xwr_upper = _s1_mask_xwr_upper_T_1 \| _s1_mask_xwr_upper_T_3; // @[AMOALU.scala:20:{22,42,47}] wire s1_mask_xwr_lower = ~_s1_mask_xwr_lower_T; // @[AMOALU.scala:21:{22,27}] wire [1:0] _s1_mask_xwr_T = {s1_mask_xwr_upper, s1_mask_xwr_lower}; // @[AMOALU.scala:20:42, :21:22, :22:16] wire _s1_mask_xwr_upper_T_4 = s1_req_addr[1]; // @[DCache.scala:196:25] wire _s1_mask_xwr_lower_T_1 = s1_req_addr[1]; // @[DCache.scala:196:25] wire [1:0] _s1_mask_xwr_upper_T_5 = _s1_mask_xwr_upper_T_4 ? _s1_mask_xwr_T : 2'h0; // @[AMOALU.scala:20:{22,27}, :22:16] wire _s1_mask_xwr_upper_T_6 = s1_mask_xwr_size[1]; // @[AMOALU.scala:11:18, :20:53] wire [1:0] _s1_mask_xwr_upper_T_7 = {2{_s1_mask_xwr_upper_T_6}}; // @[AMOALU.scala:20:{47,53}] wire [1:0] s1_mask_xwr_upper_1 = _s1_mask_xwr_upper_T_5 \| _s1_mask_xwr_upper_T_7; // @[AMOALU.scala:20:{22,42,47}] wire [1:0] s1_mask_xwr_lower_1 = _s1_mask_xwr_lower_T_1 ? 2'h0 : _s1_mask_xwr_T; // @[AMOALU.scala:21:{22,27}, :22:16] wire [3:0] _s1_mask_xwr_T_1 = {s1_mask_xwr_upper_1, s1_mask_xwr_lower_1}; // @[AMOALU.scala:20:42, :21:22, :22:16] wire _s1_mask_xwr_upper_T_8 = s1_req_addr[2]; // @[DCache.scala:196:25] wire _s1_mask_xwr_lower_T_2 = s1_req_addr[2]; // @[DCache.scala:196:25] wire [3:0] _s1_mask_xwr_upper_T_9 = _s1_mask_xwr_upper_T_8 ? _s1_mask_xwr_T_1 : 4'h0; // @[AMOALU.scala:20:{22,27}, :22:16] wire _s1_mask_xwr_upper_T_10 = &s1_mask_xwr_size; // @[AMOALU.scala:11:18, :20:53] wire [3:0] _s1_mask_xwr_upper_T_11 = {4{_s1_mask_xwr_upper_T_10}}; // @[AMOALU.scala:20:{47,53}] wire [3:0] s1_mask_xwr_upper_2 = _s1_mask_xwr_upper_T_9 \| _s1_mask_xwr_upper_T_11; // @[AMOALU.scala:20:{22,42,47}] wire [3:0] s1_mask_xwr_lower_2 = _s1_mask_xwr_lower_T_2 ? 4'h0 : _s1_mask_xwr_T_1; // @[AMOALU.scala:21:{22,27}, :22:16] wire [7:0] s1_mask_xwr = {s1_mask_xwr_upper_2, s1_mask_xwr_lower_2}; // @[AMOALU.scala:20:42, :21:22, :22:16] wire [7:0] s1_mask = _s1_mask_T ? io_cpu_s1_data_mask_0 : s1_mask_xwr; // @[DCache.scala:101:7, :327:{20,32}] wire _s2_valid_T = ~s1_sfence; // @[DCache.scala:213:71, :331:45] wire _s2_valid_T_1 = s1_valid_masked & _s2_valid_T; // @[DCache.scala:186:34, :331:{42,45}] reg s2_valid; // @[DCache.scala:331:25] wire [1:0] _s2_valid_no_xcpt_T = {io_cpu_s2_xcpt_ae_ld_0, io_cpu_s2_xcpt_ae_st_0}; // @[DCache.scala:101:7, :332:54] wire [1:0] _s2_valid_no_xcpt_T_2 = {io_cpu_s2_xcpt_pf_ld_0, io_cpu_s2_xcpt_pf_st_0}; // @[DCache.scala:101:7, :332:54] wire [1:0] _s2_valid_no_xcpt_T_3 = {io_cpu_s2_xcpt_ma_ld_0, io_cpu_s2_xcpt_ma_st_0}; // @[DCache.scala:101:7, :332:54] wire [3:0] s2_valid_no_xcpt_lo = {2'h0, _s2_valid_no_xcpt_T}; // @[DCache.scala:332:54] wire [3:0] s2_valid_no_xcpt_hi = {_s2_valid_no_xcpt_T_3, _s2_valid_no_xcpt_T_2}; // @[DCache.scala:332:54] wire [7:0] _s2_valid_no_xcpt_T_4 = {s2_valid_no_xcpt_hi, s2_valid_no_xcpt_lo}; // @[DCache.scala:332:54] wire _s2_valid_no_xcpt_T_5 = \|_s2_valid_no_xcpt_T_4; // @[DCache.scala:332:{54,61}] wire _s2_valid_no_xcpt_T_6 = ~_s2_valid_no_xcpt_T_5; // @[DCache.scala:332:{38,61}] wire s2_valid_no_xcpt = s2_valid & _s2_valid_no_xcpt_T_6; // @[DCache.scala:331:25, :332:{35,38}] reg s2_probe; // @[DCache.scala:333:25] wire _releaseInFlight_T = s1_probe \| s2_probe; // @[DCache.scala:183:25, :333:25, :334:34] wire _releaseInFlight_T_1 = \|release_state; // @[DCache.scala:228:30, :233:38, :334:63] wire releaseInFlight = _releaseInFlight_T \| _releaseInFlight_T_1; // @[DCache.scala:334:{34,46,63}] wire _s2_not_nacked_in_s1_T = ~s1_nack; // @[DCache.scala:185:28, :187:41, :335:37] reg s2_not_nacked_in_s1; // @[DCache.scala:335:36] wire s2_valid_not_nacked_in_s1 = s2_valid & s2_not_nacked_in_s1; // @[DCache.scala:331:25, :335:36, :336:44] wire s2_valid_masked = s2_valid_no_xcpt & s2_not_nacked_in_s1; // @[DCache.scala:332:35, :335:36, :337:42] wire s2_valid_not_killed = s2_valid_masked; // @[DCache.scala:337:42, :338:45] wire _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T_1 = s2_valid_masked; // @[DCache.scala:337:42, :397:71] wire _s2_dont_nack_misc_T_1 = s2_valid_masked; // @[DCache.scala:337:42, :441:43] reg [39:0] s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_14 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _put_legal_T_14 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _putpartial_legal_T_14 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_4 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_58 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_112 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_166 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_220 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_274 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_328 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_382 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_436 = s2_req_addr; // @[DCache.scala:339:19] reg [6:0] s2_req_tag; // @[DCache.scala:339:19] assign io_cpu_resp_bits_tag_0 = s2_req_tag; // @[DCache.scala:101:7, :339:19] reg [4:0] s2_req_cmd; // @[DCache.scala:339:19] assign io_cpu_resp_bits_cmd_0 = s2_req_cmd; // @[DCache.scala:101:7, :339:19] reg [1:0] s2_req_size; // @[DCache.scala:339:19] assign io_cpu_resp_bits_size_0 = s2_req_size; // @[DCache.scala:101:7, :339:19] wire [1:0] size = s2_req_size; // @[DCache.scala:339:19] reg s2_req_signed; // @[DCache.scala:339:19] assign io_cpu_resp_bits_signed_0 = s2_req_signed; // @[DCache.scala:101:7, :339:19] reg [1:0] s2_req_dprv; // @[DCache.scala:339:19] assign io_cpu_resp_bits_dprv_0 = s2_req_dprv; // @[DCache.scala:101:7, :339:19] reg s2_req_dv; // @[DCache.scala:339:19] assign io_cpu_resp_bits_dv_0 = s2_req_dv; // @[DCache.scala:101:7, :339:19] reg s2_req_phys; // @[DCache.scala:339:19] reg s2_req_no_resp; // @[DCache.scala:339:19] reg s2_req_no_alloc; // @[DCache.scala:339:19] reg s2_req_no_xcpt; // @[DCache.scala:339:19] reg [63:0] s2_req_data; // @[DCache.scala:339:19] reg [7:0] s2_req_mask; // @[DCache.scala:339:19] assign io_cpu_resp_bits_mask_0 = s2_req_mask; // @[DCache.scala:101:7, :339:19] wire _GEN_80 = s2_req_cmd == 5'h5; // @[DCache.scala:339:19, :340:37] wire _s2_cmd_flush_all_T; // @[DCache.scala:340:37] assign _s2_cmd_flush_all_T = _GEN_80; // @[DCache.scala:340:37] wire _s2_cmd_flush_line_T; // @[DCache.scala:341:38] assign _s2_cmd_flush_line_T = _GEN_80; // @[DCache.scala:340:37, :341:38] wire _s2_cmd_flush_all_T_1 = s2_req_size[0]; // @[DCache.scala:339:19, :340:68] wire _s2_cmd_flush_line_T_1 = s2_req_size[0]; // @[DCache.scala:339:19, :340:68, :341:68] wire _s2_cmd_flush_all_T_2 = ~_s2_cmd_flush_all_T_1; // @[DCache.scala:340:{56,68}] wire s2_cmd_flush_all = _s2_cmd_flush_all_T & _s2_cmd_flush_all_T_2; // @[DCache.scala:340:{37,53,56}] wire s2_cmd_flush_line = _s2_cmd_flush_line_T & _s2_cmd_flush_line_T_1; // @[DCache.scala:341:{38,54,68}] reg s2_tlb_xcpt_miss; // @[DCache.scala:342:24] reg [31:0] s2_tlb_xcpt_paddr; // @[DCache.scala:342:24] reg [39:0] s2_tlb_xcpt_gpa; // @[DCache.scala:342:24] assign io_cpu_s2_gpa_0 = s2_tlb_xcpt_gpa; // @[DCache.scala:101:7, :342:24] reg s2_tlb_xcpt_pf_ld; // @[DCache.scala:342:24] reg s2_tlb_xcpt_pf_st; // @[DCache.scala:342:24] reg s2_tlb_xcpt_pf_inst; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ae_ld; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ae_st; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ae_inst; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ma_ld; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ma_st; // @[DCache.scala:342:24] reg s2_tlb_xcpt_cacheable; // @[DCache.scala:342:24] reg s2_tlb_xcpt_must_alloc; // @[DCache.scala:342:24] reg s2_tlb_xcpt_prefetchable; // @[DCache.scala:342:24] reg [1:0] s2_tlb_xcpt_size; // @[DCache.scala:342:24] reg [4:0] s2_tlb_xcpt_cmd; // @[DCache.scala:342:24] reg s2_pma_miss; // @[DCache.scala:343:19] reg [31:0] s2_pma_paddr; // @[DCache.scala:343:19] reg [39:0] s2_pma_gpa; // @[DCache.scala:343:19] reg s2_pma_pf_ld; // @[DCache.scala:343:19] reg s2_pma_pf_st; // @[DCache.scala:343:19] reg s2_pma_pf_inst; // @[DCache.scala:343:19] reg s2_pma_ae_ld; // @[DCache.scala:343:19] reg s2_pma_ae_st; // @[DCache.scala:343:19] reg s2_pma_ae_inst; // @[DCache.scala:343:19] reg s2_pma_ma_ld; // @[DCache.scala:343:19] reg s2_pma_ma_st; // @[DCache.scala:343:19] reg s2_pma_cacheable; // @[DCache.scala:343:19] reg s2_pma_must_alloc; // @[DCache.scala:343:19] reg s2_pma_prefetchable; // @[DCache.scala:343:19] reg [1:0] s2_pma_size; // @[DCache.scala:343:19] reg [4:0] s2_pma_cmd; // @[DCache.scala:343:19] reg [39:0] s2_uncached_resp_addr; // @[DCache.scala:344:34] wire _T_30 = s1_valid_not_nacked \| s1_flush_valid; // @[DCache.scala:187:38, :215:27, :345:29] wire _s2_vaddr_T; // @[DCache.scala:351:62] assign _s2_vaddr_T = _T_30; // @[DCache.scala:345:29, :351:62] wire _s1_meta_clk_en_T; // @[DCache.scala:357:44] assign _s1_meta_clk_en_T = _T_30; // @[DCache.scala:345:29, :357:44] wire _s2_hit_state_T; // @[DCache.scala:386:66] assign _s2_hit_state_T = _T_30; // @[DCache.scala:345:29, :386:66] wire _s2_victim_way_T; // @[DCache.scala:431:77] assign _s2_victim_way_T = _T_30; // @[DCache.scala:345:29, :431:77] reg [39:0] s2_vaddr_r; // @[DCache.scala:351:31] wire [27:0] _s2_vaddr_T_1 = s2_vaddr_r[39:12]; // @[DCache.scala:351:{31,81}] wire [11:0] _s2_vaddr_T_2 = s2_req_addr[11:0]; // @[DCache.scala:339:19, :351:103] wire [39:0] s2_vaddr = {_s2_vaddr_T_1, _s2_vaddr_T_2}; // @[DCache.scala:351:{21,81,103}] wire _s2_read_T = s2_req_cmd == 5'h0; // @[package.scala:16:47] wire _s2_read_T_1 = s2_req_cmd == 5'h10; // @[package.scala:16:47] wire _GEN_81 = s2_req_cmd == 5'h6; // @[package.scala:16:47] wire _s2_read_T_2; // @[package.scala:16:47] assign _s2_read_T_2 = _GEN_81; // @[package.scala:16:47] wire _r_c_cat_T_48; // @[Consts.scala:91:71] assign _r_c_cat_T_48 = _GEN_81; // @[package.scala:16:47] wire _s2_lr_T; // @[DCache.scala:470:70] assign _s2_lr_T = _GEN_81; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_48; // @[Consts.scala:91:71] assign _metaArb_io_in_3_bits_data_c_cat_T_48 = _GEN_81; // @[package.scala:16:47] wire _GEN_82 = s2_req_cmd == 5'h7; // @[package.scala:16:47] wire _s2_read_T_3; // @[package.scala:16:47] assign _s2_read_T_3 = _GEN_82; // @[package.scala:16:47] wire _s2_write_T_3; // @[Consts.scala:90:66] assign _s2_write_T_3 = _GEN_82; // @[package.scala:16:47] wire _r_c_cat_T_3; // @[Consts.scala:90:66] assign _r_c_cat_T_3 = _GEN_82; // @[package.scala:16:47] wire _r_c_cat_T_26; // @[Consts.scala:90:66] assign _r_c_cat_T_26 = _GEN_82; // @[package.scala:16:47] wire _s2_sc_T; // @[DCache.scala:471:70] assign _s2_sc_T = _GEN_82; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_3; // @[Consts.scala:90:66] assign _metaArb_io_in_3_bits_data_c_cat_T_3 = _GEN_82; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_26; // @[Consts.scala:90:66] assign _metaArb_io_in_3_bits_data_c_cat_T_26 = _GEN_82; // @[package.scala:16:47] wire _io_cpu_store_pending_T_3; // @[Consts.scala:90:66] assign _io_cpu_store_pending_T_3 = _GEN_82; // @[package.scala:16:47] wire _s2_read_T_4 = _s2_read_T \| _s2_read_T_1; // @[package.scala:16:47, :81:59] wire _s2_read_T_5 = _s2_read_T_4 \| _s2_read_T_2; // @[package.scala:16:47, :81:59] wire _s2_read_T_6 = _s2_read_T_5 \| _s2_read_T_3; // @[package.scala:16:47, :81:59] wire _GEN_83 = s2_req_cmd == 5'h4; // @[package.scala:16:47] wire _s2_read_T_7; // @[package.scala:16:47] assign _s2_read_T_7 = _GEN_83; // @[package.scala:16:47] wire _s2_write_T_5; // @[package.scala:16:47] assign _s2_write_T_5 = _GEN_83; // @[package.scala:16:47] wire _r_c_cat_T_5; // @[package.scala:16:47] assign _r_c_cat_T_5 = _GEN_83; // @[package.scala:16:47] wire _r_c_cat_T_28; // @[package.scala:16:47] assign _r_c_cat_T_28 = _GEN_83; // @[package.scala:16:47] wire _atomics_T; // @[DCache.scala:587:81] assign _atomics_T = _GEN_83; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_5; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_5 = _GEN_83; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_28; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_28 = _GEN_83; // @[package.scala:16:47] wire _io_cpu_store_pending_T_5; // @[package.scala:16:47] assign _io_cpu_store_pending_T_5 = _GEN_83; // @[package.scala:16:47] wire _GEN_84 = s2_req_cmd == 5'h9; // @[package.scala:16:47] wire _s2_read_T_8; // @[package.scala:16:47] assign _s2_read_T_8 = _GEN_84; // @[package.scala:16:47] wire _s2_write_T_6; // @[package.scala:16:47] assign _s2_write_T_6 = _GEN_84; // @[package.scala:16:47] wire _r_c_cat_T_6; // @[package.scala:16:47] assign _r_c_cat_T_6 = _GEN_84; // @[package.scala:16:47] wire _r_c_cat_T_29; // @[package.scala:16:47] assign _r_c_cat_T_29 = _GEN_84; // @[package.scala:16:47] wire _atomics_T_2; // @[DCache.scala:587:81] assign _atomics_T_2 = _GEN_84; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_6; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_6 = _GEN_84; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_29; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_29 = _GEN_84; // @[package.scala:16:47] wire _io_cpu_store_pending_T_6; // @[package.scala:16:47] assign _io_cpu_store_pending_T_6 = _GEN_84; // @[package.scala:16:47] wire _GEN_85 = s2_req_cmd == 5'hA; // @[package.scala:16:47] wire _s2_read_T_9; // @[package.scala:16:47] assign _s2_read_T_9 = _GEN_85; // @[package.scala:16:47] wire _s2_write_T_7; // @[package.scala:16:47] assign _s2_write_T_7 = _GEN_85; // @[package.scala:16:47] wire _r_c_cat_T_7; // @[package.scala:16:47] assign _r_c_cat_T_7 = _GEN_85; // @[package.scala:16:47] wire _r_c_cat_T_30; // @[package.scala:16:47] assign _r_c_cat_T_30 = _GEN_85; // @[package.scala:16:47] wire _atomics_T_4; // @[DCache.scala:587:81] assign _atomics_T_4 = _GEN_85; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_7; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_7 = _GEN_85; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_30; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_30 = _GEN_85; // @[package.scala:16:47] wire _io_cpu_store_pending_T_7; // @[package.scala:16:47] assign _io_cpu_store_pending_T_7 = _GEN_85; // @[package.scala:16:47] wire _GEN_86 = s2_req_cmd == 5'hB; // @[package.scala:16:47] wire _s2_read_T_10; // @[package.scala:16:47] assign _s2_read_T_10 = _GEN_86; // @[package.scala:16:47] wire _s2_write_T_8; // @[package.scala:16:47] assign _s2_write_T_8 = _GEN_86; // @[package.scala:16:47] wire _r_c_cat_T_8; // @[package.scala:16:47] assign _r_c_cat_T_8 = _GEN_86; // @[package.scala:16:47] wire _r_c_cat_T_31; // @[package.scala:16:47] assign _r_c_cat_T_31 = _GEN_86; // @[package.scala:16:47] wire _atomics_T_6; // @[DCache.scala:587:81] assign _atomics_T_6 = _GEN_86; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_8; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_8 = _GEN_86; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_31; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_31 = _GEN_86; // @[package.scala:16:47] wire _io_cpu_store_pending_T_8; // @[package.scala:16:47] assign _io_cpu_store_pending_T_8 = _GEN_86; // @[package.scala:16:47] wire _s2_read_T_11 = _s2_read_T_7 \| _s2_read_T_8; // @[package.scala:16:47, :81:59] wire _s2_read_T_12 = _s2_read_T_11 \| _s2_read_T_9; // @[package.scala:16:47, :81:59] wire _s2_read_T_13 = _s2_read_T_12 \| _s2_read_T_10; // @[package.scala:16:47, :81:59] wire _GEN_87 = s2_req_cmd == 5'h8; // @[package.scala:16:47] wire _s2_read_T_14; // @[package.scala:16:47] assign _s2_read_T_14 = _GEN_87; // @[package.scala:16:47] wire _s2_write_T_12; // @[package.scala:16:47] assign _s2_write_T_12 = _GEN_87; // @[package.scala:16:47] wire _r_c_cat_T_12; // @[package.scala:16:47] assign _r_c_cat_T_12 = _GEN_87; // @[package.scala:16:47] wire _r_c_cat_T_35; // @[package.scala:16:47] assign _r_c_cat_T_35 = _GEN_87; // @[package.scala:16:47] wire _atomics_T_8; // @[DCache.scala:587:81] assign _atomics_T_8 = _GEN_87; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_12; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_12 = _GEN_87; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_35; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_35 = _GEN_87; // @[package.scala:16:47] wire _io_cpu_store_pending_T_12; // @[package.scala:16:47] assign _io_cpu_store_pending_T_12 = _GEN_87; // @[package.scala:16:47] wire _GEN_88 = s2_req_cmd == 5'hC; // @[package.scala:16:47] wire _s2_read_T_15; // @[package.scala:16:47] assign _s2_read_T_15 = _GEN_88; // @[package.scala:16:47] wire _s2_write_T_13; // @[package.scala:16:47] assign _s2_write_T_13 = _GEN_88; // @[package.scala:16:47] wire _r_c_cat_T_13; // @[package.scala:16:47] assign _r_c_cat_T_13 = _GEN_88; // @[package.scala:16:47] wire _r_c_cat_T_36; // @[package.scala:16:47] assign _r_c_cat_T_36 = _GEN_88; // @[package.scala:16:47] wire _atomics_T_10; // @[DCache.scala:587:81] assign _atomics_T_10 = _GEN_88; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_13; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_13 = _GEN_88; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_36; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_36 = _GEN_88; // @[package.scala:16:47] wire _io_cpu_store_pending_T_13; // @[package.scala:16:47] assign _io_cpu_store_pending_T_13 = _GEN_88; // @[package.scala:16:47] wire _GEN_89 = s2_req_cmd == 5'hD; // @[package.scala:16:47] wire _s2_read_T_16; // @[package.scala:16:47] assign _s2_read_T_16 = _GEN_89; // @[package.scala:16:47] wire _s2_write_T_14; // @[package.scala:16:47] assign _s2_write_T_14 = _GEN_89; // @[package.scala:16:47] wire _r_c_cat_T_14; // @[package.scala:16:47] assign _r_c_cat_T_14 = _GEN_89; // @[package.scala:16:47] wire _r_c_cat_T_37; // @[package.scala:16:47] assign _r_c_cat_T_37 = _GEN_89; // @[package.scala:16:47] wire _atomics_T_12; // @[DCache.scala:587:81] assign _atomics_T_12 = _GEN_89; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_14; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_14 = _GEN_89; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_37; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_37 = _GEN_89; // @[package.scala:16:47] wire _io_cpu_store_pending_T_14; // @[package.scala:16:47] assign _io_cpu_store_pending_T_14 = _GEN_89; // @[package.scala:16:47] wire _GEN_90 = s2_req_cmd == 5'hE; // @[package.scala:16:47] wire _s2_read_T_17; // @[package.scala:16:47] assign _s2_read_T_17 = _GEN_90; // @[package.scala:16:47] wire _s2_write_T_15; // @[package.scala:16:47] assign _s2_write_T_15 = _GEN_90; // @[package.scala:16:47] wire _r_c_cat_T_15; // @[package.scala:16:47] assign _r_c_cat_T_15 = _GEN_90; // @[package.scala:16:47] wire _r_c_cat_T_38; // @[package.scala:16:47] assign _r_c_cat_T_38 = _GEN_90; // @[package.scala:16:47] wire _atomics_T_14; // @[DCache.scala:587:81] assign _atomics_T_14 = _GEN_90; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_15; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_15 = _GEN_90; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_38; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_38 = _GEN_90; // @[package.scala:16:47] wire _io_cpu_store_pending_T_15; // @[package.scala:16:47] assign _io_cpu_store_pending_T_15 = _GEN_90; // @[package.scala:16:47] wire _GEN_91 = s2_req_cmd == 5'hF; // @[package.scala:16:47] wire _s2_read_T_18; // @[package.scala:16:47] assign _s2_read_T_18 = _GEN_91; // @[package.scala:16:47] wire _s2_write_T_16; // @[package.scala:16:47] assign _s2_write_T_16 = _GEN_91; // @[package.scala:16:47] wire _r_c_cat_T_16; // @[package.scala:16:47] assign _r_c_cat_T_16 = _GEN_91; // @[package.scala:16:47] wire _r_c_cat_T_39; // @[package.scala:16:47] assign _r_c_cat_T_39 = _GEN_91; // @[package.scala:16:47] wire _atomics_T_16; // @[DCache.scala:587:81] assign _atomics_T_16 = _GEN_91; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_16; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_16 = _GEN_91; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_39; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_39 = _GEN_91; // @[package.scala:16:47] wire _io_cpu_store_pending_T_16; // @[package.scala:16:47] assign _io_cpu_store_pending_T_16 = _GEN_91; // @[package.scala:16:47] wire _s2_read_T_19 = _s2_read_T_14 \| _s2_read_T_15; // @[package.scala:16:47, :81:59] wire _s2_read_T_20 = _s2_read_T_19 \| _s2_read_T_16; // @[package.scala:16:47, :81:59] wire _s2_read_T_21 = _s2_read_T_20 \| _s2_read_T_17; // @[package.scala:16:47, :81:59] wire _s2_read_T_22 = _s2_read_T_21 \| _s2_read_T_18; // @[package.scala:16:47, :81:59] wire _s2_read_T_23 = _s2_read_T_13 \| _s2_read_T_22; // @[package.scala:81:59] assign s2_read = _s2_read_T_6 \| _s2_read_T_23; // @[package.scala:81:59] assign io_cpu_resp_bits_has_data_0 = s2_read; // @[DCache.scala:101:7] wire _GEN_92 = s2_req_cmd == 5'h1; // @[DCache.scala:339:19] wire _s2_write_T; // @[Consts.scala:90:32] assign _s2_write_T = _GEN_92; // @[Consts.scala:90:32] wire _r_c_cat_T; // @[Consts.scala:90:32] assign _r_c_cat_T = _GEN_92; // @[Consts.scala:90:32] wire _r_c_cat_T_23; // @[Consts.scala:90:32] assign _r_c_cat_T_23 = _GEN_92; // @[Consts.scala:90:32] wire _metaArb_io_in_3_bits_data_c_cat_T; // @[Consts.scala:90:32] assign _metaArb_io_in_3_bits_data_c_cat_T = _GEN_92; // @[Consts.scala:90:32] wire _metaArb_io_in_3_bits_data_c_cat_T_23; // @[Consts.scala:90:32] assign _metaArb_io_in_3_bits_data_c_cat_T_23 = _GEN_92; // @[Consts.scala:90:32] wire _io_cpu_store_pending_T; // @[Consts.scala:90:32] assign _io_cpu_store_pending_T = _GEN_92; // @[Consts.scala:90:32] wire _GEN_93 = s2_req_cmd == 5'h11; // @[DCache.scala:339:19] wire _s2_write_T_1; // @[Consts.scala:90:49] assign _s2_write_T_1 = _GEN_93; // @[Consts.scala:90:49] wire _r_c_cat_T_1; // @[Consts.scala:90:49] assign _r_c_cat_T_1 = _GEN_93; // @[Consts.scala:90:49] wire _r_c_cat_T_24; // @[Consts.scala:90:49] assign _r_c_cat_T_24 = _GEN_93; // @[Consts.scala:90:49] wire _tl_out_a_bits_T_4; // @[DCache.scala:610:20] assign _tl_out_a_bits_T_4 = _GEN_93; // @[DCache.scala:610:20] wire _uncachedReqs_0_cmd_T; // @[DCache.scala:637:49] assign _uncachedReqs_0_cmd_T = _GEN_93; // @[DCache.scala:637:49] wire _metaArb_io_in_3_bits_data_c_cat_T_1; // @[Consts.scala:90:49] assign _metaArb_io_in_3_bits_data_c_cat_T_1 = _GEN_93; // @[Consts.scala:90:49] wire _metaArb_io_in_3_bits_data_c_cat_T_24; // @[Consts.scala:90:49] assign _metaArb_io_in_3_bits_data_c_cat_T_24 = _GEN_93; // @[Consts.scala:90:49] wire _io_cpu_store_pending_T_1; // @[Consts.scala:90:49] assign _io_cpu_store_pending_T_1 = _GEN_93; // @[Consts.scala:90:49] wire _s2_write_T_2 = _s2_write_T \| _s2_write_T_1; // @[Consts.scala:90:{32,42,49}] wire _s2_write_T_4 = _s2_write_T_2 \| _s2_write_T_3; // @[Consts.scala:90:{42,59,66}] wire _s2_write_T_9 = _s2_write_T_5 \| _s2_write_T_6; // @[package.scala:16:47, :81:59] wire _s2_write_T_10 = _s2_write_T_9 \| _s2_write_T_7; // @[package.scala:16:47, :81:59] wire _s2_write_T_11 = _s2_write_T_10 \| _s2_write_T_8; // @[package.scala:16:47, :81:59] wire _s2_write_T_17 = _s2_write_T_12 \| _s2_write_T_13; // @[package.scala:16:47, :81:59] wire _s2_write_T_18 = _s2_write_T_17 \| _s2_write_T_14; // @[package.scala:16:47, :81:59] wire _s2_write_T_19 = _s2_write_T_18 \| _s2_write_T_15; // @[package.scala:16:47, :81:59] wire _s2_write_T_20 = _s2_write_T_19 \| _s2_write_T_16; // @[package.scala:16:47, :81:59] wire _s2_write_T_21 = _s2_write_T_11 \| _s2_write_T_20; // @[package.scala:81:59] wire s2_write = _s2_write_T_4 \| _s2_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire s2_readwrite = s2_read \| s2_write; // @[DCache.scala:354:30] reg s2_flush_valid_pre_tag_ecc; // @[DCache.scala:355:43] wire s2_flush_valid = s2_flush_valid_pre_tag_ecc; // @[DCache.scala:355:43, :363:51] wire s1_meta_clk_en = _s1_meta_clk_en_T \| s1_probe; // @[DCache.scala:183:25, :357:{44,62}] reg [21:0] s2_meta_corrected_r; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE = s2_meta_corrected_r; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_1; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_0_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_0_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T = _s2_meta_corrected_WIRE[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_0_tag = _s2_meta_corrected_T; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_1 = _s2_meta_corrected_WIRE[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_0_coh_state = _s2_meta_corrected_T_1; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_1; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_1 = s2_meta_corrected_r_1; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_3; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_2; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_1_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_1_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_2 = _s2_meta_corrected_WIRE_1[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_1_tag = _s2_meta_corrected_T_2; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_3 = _s2_meta_corrected_WIRE_1[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_1_coh_state = _s2_meta_corrected_T_3; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_2; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_2 = s2_meta_corrected_r_2; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_5; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_4; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_2_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_2_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_4 = _s2_meta_corrected_WIRE_2[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_2_tag = _s2_meta_corrected_T_4; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_5 = _s2_meta_corrected_WIRE_2[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_2_coh_state = _s2_meta_corrected_T_5; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_3; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_3 = s2_meta_corrected_r_3; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_7; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_6; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_3_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_3_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_6 = _s2_meta_corrected_WIRE_3[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_3_tag = _s2_meta_corrected_T_6; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_7 = _s2_meta_corrected_WIRE_3[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_3_coh_state = _s2_meta_corrected_T_7; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_4; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_4 = s2_meta_corrected_r_4; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_9; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_8; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_4_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_4_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_8 = _s2_meta_corrected_WIRE_4[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_4_tag = _s2_meta_corrected_T_8; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_9 = _s2_meta_corrected_WIRE_4[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_4_coh_state = _s2_meta_corrected_T_9; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_5; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_5 = s2_meta_corrected_r_5; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_11; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_10; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_5_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_5_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_10 = _s2_meta_corrected_WIRE_5[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_5_tag = _s2_meta_corrected_T_10; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_11 = _s2_meta_corrected_WIRE_5[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_5_coh_state = _s2_meta_corrected_T_11; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_6; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_6 = s2_meta_corrected_r_6; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_13; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_12; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_6_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_6_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_12 = _s2_meta_corrected_WIRE_6[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_6_tag = _s2_meta_corrected_T_12; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_13 = _s2_meta_corrected_WIRE_6[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_6_coh_state = _s2_meta_corrected_T_13; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_7; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_7 = s2_meta_corrected_r_7; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_15; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_14; // @[DCache.scala:361:99] wire [1:0] _s2_first_meta_corrected_T_8_coh_state = s2_meta_corrected_7_coh_state; // @[Mux.scala:50:70] wire [19:0] _s2_first_meta_corrected_T_8_tag = s2_meta_corrected_7_tag; // @[Mux.scala:50:70] assign _s2_meta_corrected_T_14 = _s2_meta_corrected_WIRE_7[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_7_tag = _s2_meta_corrected_T_14; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_15 = _s2_meta_corrected_WIRE_7[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_7_coh_state = _s2_meta_corrected_T_15; // @[DCache.scala:361:99] wire _s2_data_en_T = s1_valid \| inWriteback; // @[package.scala:81:59] wire s2_data_en = _s2_data_en_T \| io_cpu_replay_next_0; // @[DCache.scala:101:7, :366:{23,38}] wire s2_data_word_en = inWriteback \| _s2_data_word_en_T; // @[package.scala:81:59] wire _s2_data_s1_word_en_T = ~io_cpu_replay_next_0; // @[DCache.scala:101:7, :377:28] wire s2_data_s1_word_en = ~_s2_data_s1_word_en_T \| s2_data_word_en; // @[DCache.scala:367:22, :377:{27,28}] wire _s2_data_T = s2_data_s1_word_en; // @[DCache.scala:377:27, :379:39] wire [8:0] _s2_data_T_1 = _s2_data_T ? s1_data_way : 9'h0; // @[DCache.scala:323:32, :379:{28,39}] wire _s2_data_T_2 = _s2_data_T_1[0]; // @[Mux.scala:32:36] wire _s2_data_T_3 = _s2_data_T_1[1]; // @[Mux.scala:32:36] wire _s2_data_T_4 = _s2_data_T_1[2]; // @[Mux.scala:32:36] wire _s2_data_T_5 = _s2_data_T_1[3]; // @[Mux.scala:32:36] wire _s2_data_T_6 = _s2_data_T_1[4]; // @[Mux.scala:32:36] wire _s2_data_T_7 = _s2_data_T_1[5]; // @[Mux.scala:32:36] wire _s2_data_T_8 = _s2_data_T_1[6]; // @[Mux.scala:32:36] wire _s2_data_T_9 = _s2_data_T_1[7]; // @[Mux.scala:32:36] wire _s2_data_T_10 = _s2_data_T_1[8]; // @[Mux.scala:32:36] wire [63:0] _s2_data_T_11 = _s2_data_T_2 ? s2_data_s1_way_words_0_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_12 = _s2_data_T_3 ? s2_data_s1_way_words_1_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_13 = _s2_data_T_4 ? s2_data_s1_way_words_2_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_14 = _s2_data_T_5 ? s2_data_s1_way_words_3_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_15 = _s2_data_T_6 ? s2_data_s1_way_words_4_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_16 = _s2_data_T_7 ? s2_data_s1_way_words_5_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_17 = _s2_data_T_8 ? s2_data_s1_way_words_6_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_18 = _s2_data_T_9 ? s2_data_s1_way_words_7_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_19 = _s2_data_T_10 ? s2_data_s1_way_words_8_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_20 = _s2_data_T_11 \| _s2_data_T_12; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_21 = _s2_data_T_20 \| _s2_data_T_13; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_22 = _s2_data_T_21 \| _s2_data_T_14; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_23 = _s2_data_T_22 \| _s2_data_T_15; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_24 = _s2_data_T_23 \| _s2_data_T_16; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_25 = _s2_data_T_24 \| _s2_data_T_17; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_26 = _s2_data_T_25 \| _s2_data_T_18; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_27 = _s2_data_T_26 \| _s2_data_T_19; // @[Mux.scala:30:73] wire [63:0] _s2_data_WIRE = _s2_data_T_27; // @[Mux.scala:30:73] reg [63:0] s2_data; // @[DCache.scala:379:18] reg [7:0] s2_probe_way; // @[DCache.scala:383:31] reg [1:0] s2_probe_state_state; // @[DCache.scala:384:33] reg [7:0] s2_hit_way; // @[DCache.scala:385:29] reg [1:0] s2_hit_state_state; // @[DCache.scala:386:31] wire s2_hit_valid = \|s2_hit_state_state; // @[Metadata.scala:50:45] wire _r_c_cat_T_2 = _r_c_cat_T \| _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_4 = _r_c_cat_T_2 \| _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_9 = _r_c_cat_T_5 \| _r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_10 = _r_c_cat_T_9 \| _r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_11 = _r_c_cat_T_10 \| _r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_17 = _r_c_cat_T_12 \| _r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_18 = _r_c_cat_T_17 \| _r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_19 = _r_c_cat_T_18 \| _r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_20 = _r_c_cat_T_19 \| _r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_21 = _r_c_cat_T_11 \| _r_c_cat_T_20; // @[package.scala:81:59] wire _r_c_cat_T_22 = _r_c_cat_T_4 \| _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_25 = _r_c_cat_T_23 \| _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_27 = _r_c_cat_T_25 \| _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_32 = _r_c_cat_T_28 \| _r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_33 = _r_c_cat_T_32 \| _r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_34 = _r_c_cat_T_33 \| _r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_40 = _r_c_cat_T_35 \| _r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_41 = _r_c_cat_T_40 \| _r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_42 = _r_c_cat_T_41 \| _r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_43 = _r_c_cat_T_42 \| _r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_44 = _r_c_cat_T_34 \| _r_c_cat_T_43; // @[package.scala:81:59] wire _r_c_cat_T_45 = _r_c_cat_T_27 \| _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_94 = s2_req_cmd == 5'h3; // @[DCache.scala:339:19] wire _r_c_cat_T_46; // @[Consts.scala:91:54] assign _r_c_cat_T_46 = _GEN_94; // @[Consts.scala:91:54] wire _metaArb_io_in_3_bits_data_c_cat_T_46; // @[Consts.scala:91:54] assign _metaArb_io_in_3_bits_data_c_cat_T_46 = _GEN_94; // @[Consts.scala:91:54] wire _r_c_cat_T_47 = _r_c_cat_T_45 \| _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_49 = _r_c_cat_T_47 \| _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r_T = {r_c, s2_hit_state_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_25 = _r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_27 = {1'h0, _r_T_25}; // @[Misc.scala:35:36, :49:20] wire _r_T_28 = _r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_30 = _r_T_28 ? 2'h2 : _r_T_27; // @[Misc.scala:35:36, :49:20] wire _r_T_31 = _r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_33 = _r_T_31 ? 2'h1 : _r_T_30; // @[Misc.scala:35:36, :49:20] wire _r_T_34 = _r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_36 = _r_T_34 ? 2'h2 : _r_T_33; // @[Misc.scala:35:36, :49:20] wire _r_T_37 = _r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_39 = _r_T_37 ? 2'h0 : _r_T_36; // @[Misc.scala:35:36, :49:20] wire _r_T_40 = _r_T == 4'hE; // @[Misc.scala:49:20] wire _r_T_41 = _r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_42 = _r_T_40 ? 2'h3 : _r_T_39; // @[Misc.scala:35:36, :49:20] wire _r_T_43 = &_r_T; // @[Misc.scala:49:20] wire _r_T_44 = _r_T_43 \| _r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_45 = _r_T_43 ? 2'h3 : _r_T_42; // @[Misc.scala:35:36, :49:20] wire _r_T_46 = _r_T == 4'h6; // @[Misc.scala:49:20] wire _r_T_47 = _r_T_46 \| _r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_48 = _r_T_46 ? 2'h2 : _r_T_45; // @[Misc.scala:35:36, :49:20] wire _r_T_49 = _r_T == 4'h7; // @[Misc.scala:49:20] wire _r_T_50 = _r_T_49 \| _r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_51 = _r_T_49 ? 2'h3 : _r_T_48; // @[Misc.scala:35:36, :49:20] wire _r_T_52 = _r_T == 4'h1; // @[Misc.scala:49:20] wire _r_T_53 = _r_T_52 \| _r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_54 = _r_T_52 ? 2'h1 : _r_T_51; // @[Misc.scala:35:36, :49:20] wire _r_T_55 = _r_T == 4'h2; // @[Misc.scala:49:20] wire _r_T_56 = _r_T_55 \| _r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_57 = _r_T_55 ? 2'h2 : _r_T_54; // @[Misc.scala:35:36, :49:20] wire _r_T_58 = _r_T == 4'h3; // @[Misc.scala:49:20] wire s2_hit = _r_T_58 \| _r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] s2_grow_param = _r_T_58 ? 2'h3 : _r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] s2_new_hit_state_state = s2_grow_param; // @[Misc.scala:35:36] wire [1:0] metaArb_io_in_2_bits_data_meta_coh_state = s2_new_hit_state_state; // @[Metadata.scala:160:20] wire [15:0] s2_data_corrected_lo_lo = s2_data[15:0]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_lo_lo = s2_data[15:0]; // @[package.scala:45:27] wire [15:0] s2_data_corrected_lo_hi = s2_data[31:16]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_lo_hi = s2_data[31:16]; // @[package.scala:45:27] wire [31:0] s2_data_corrected_lo = {s2_data_corrected_lo_hi, s2_data_corrected_lo_lo}; // @[package.scala:45:27] wire [15:0] s2_data_corrected_hi_lo = s2_data[47:32]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_hi_lo = s2_data[47:32]; // @[package.scala:45:27] wire [15:0] s2_data_corrected_hi_hi = s2_data[63:48]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_hi_hi = s2_data[63:48]; // @[package.scala:45:27] wire [31:0] s2_data_corrected_hi = {s2_data_corrected_hi_hi, s2_data_corrected_hi_lo}; // @[package.scala:45:27] assign s2_data_corrected = {s2_data_corrected_hi, s2_data_corrected_lo}; // @[package.scala:45:27] assign nodeOut_c_bits_data = s2_data_corrected; // @[package.scala:45:27] wire [63:0] s2_data_word_corrected = s2_data_corrected; // @[package.scala:45:27] wire [31:0] s2_data_uncorrected_lo = {s2_data_uncorrected_lo_hi, s2_data_uncorrected_lo_lo}; // @[package.scala:45:27] wire [31:0] s2_data_uncorrected_hi = {s2_data_uncorrected_hi_hi, s2_data_uncorrected_hi_lo}; // @[package.scala:45:27] wire [63:0] s2_data_uncorrected = {s2_data_uncorrected_hi, s2_data_uncorrected_lo}; // @[package.scala:45:27] assign s2_data_word = s2_data_uncorrected; // @[package.scala:45:27] wire s2_valid_hit_maybe_flush_pre_data_ecc_and_waw = _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T_1 & s2_hit; // @[Misc.scala:35:9] wire _s2_valid_hit_pre_data_ecc_and_waw_T = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw & s2_readwrite; // @[DCache.scala:354:30, :397:89, :418:89] wire s2_valid_hit_pre_data_ecc_and_waw = _s2_valid_hit_pre_data_ecc_and_waw_T; // @[DCache.scala:418:{89,105}] wire s2_valid_hit_pre_data_ecc = s2_valid_hit_pre_data_ecc_and_waw; // @[DCache.scala:418:105, :420:69] wire s2_valid_flush_line = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw & s2_cmd_flush_line; // @[DCache.scala:341:54, :397:89, :419:75] wire _s2_victim_tag_T = s2_valid_flush_line; // @[DCache.scala:419:75, :433:47] wire s2_valid_hit = s2_valid_hit_pre_data_ecc; // @[DCache.scala:420:69, :422:48] wire _s2_valid_miss_T = s2_valid_masked & s2_readwrite; // @[DCache.scala:337:42, :354:30, :423:39] wire _s2_valid_miss_T_2 = _s2_valid_miss_T; // @[DCache.scala:423:{39,55}] wire _s2_valid_miss_T_3 = ~s2_hit; // @[Misc.scala:35:9] wire s2_valid_miss = _s2_valid_miss_T_2 & _s2_valid_miss_T_3; // @[DCache.scala:423:{55,73,76}] wire _s2_uncached_T = ~s2_pma_cacheable; // @[DCache.scala:343:19, :424:21] wire _s2_uncached_T_1 = ~s2_pma_must_alloc; // @[DCache.scala:343:19, :424:61] wire _s2_uncached_T_2 = s2_req_no_alloc & _s2_uncached_T_1; // @[DCache.scala:339:19, :424:{58,61}] wire _s2_uncached_T_3 = ~s2_hit_valid; // @[Metadata.scala:50:45] wire _s2_uncached_T_4 = _s2_uncached_T_2 & _s2_uncached_T_3; // @[DCache.scala:424:{58,80,83}] wire s2_uncached = _s2_uncached_T \| _s2_uncached_T_4; // @[DCache.scala:424:{21,39,80}] wire _s2_valid_cached_miss_T = ~s2_uncached; // @[DCache.scala:424:39, :425:47] wire _s2_valid_cached_miss_T_1 = s2_valid_miss & _s2_valid_cached_miss_T; // @[DCache.scala:423:73, :425:{44,47}] wire _s2_valid_cached_miss_T_3 = ~_s2_valid_cached_miss_T_2; // @[DCache.scala:425:{63,88}] wire s2_valid_cached_miss = _s2_valid_cached_miss_T_1 & _s2_valid_cached_miss_T_3; // @[DCache.scala:425:{44,60,63}] wire _s2_want_victimize_T = s2_valid_cached_miss \| s2_valid_flush_line; // @[DCache.scala:419:75, :425:60, :427:77] wire _s2_want_victimize_T_1 = _s2_want_victimize_T; // @[DCache.scala:427:{77,100}] wire _s2_want_victimize_T_2 = _s2_want_victimize_T_1 \| s2_flush_valid; // @[DCache.scala:363:51, :427:{100,123}] wire s2_want_victimize = _s2_want_victimize_T_2; // @[DCache.scala:427:{52,123}] wire s2_victimize = s2_want_victimize; // @[DCache.scala:427:52, :429:40] wire _s2_cannot_victimize_T = ~s2_flush_valid; // @[DCache.scala:363:51, :428:29] wire _s2_valid_uncached_pending_T = s2_valid_miss & s2_uncached; // @[DCache.scala:423:73, :424:39, :430:49] wire _s2_valid_uncached_pending_T_2 = ~_s2_valid_uncached_pending_T_1; // @[DCache.scala:430:{67,92}] wire s2_valid_uncached_pending = _s2_valid_uncached_pending_T & _s2_valid_uncached_pending_T_2; // @[DCache.scala:430:{49,64,67}] reg [2:0] s2_victim_way_r; // @[DCache.scala:431:41] wire [7:0] s2_victim_way = 8'h1 << s2_victim_way_r; // @[OneHot.scala:58:35] assign s2_victim_or_hit_way = s2_hit_valid ? s2_hit_way : s2_victim_way; // @[OneHot.scala:58:35] assign metaArb_io_in_2_bits_way_en = s2_victim_or_hit_way; // @[DCache.scala:135:28, :432:33] wire [19:0] _s2_victim_tag_T_1 = s2_req_addr[31:12]; // @[DCache.scala:339:19, :433:82] wire _s2_victim_tag_T_2 = s2_victim_way[0]; // @[OneHot.scala:58:35] wire _s2_victim_state_T = s2_victim_way[0]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_3 = s2_victim_way[1]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_1 = s2_victim_way[1]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_4 = s2_victim_way[2]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_2 = s2_victim_way[2]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_5 = s2_victim_way[3]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_3 = s2_victim_way[3]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_6 = s2_victim_way[4]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_4 = s2_victim_way[4]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_7 = s2_victim_way[5]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_5 = s2_victim_way[5]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_8 = s2_victim_way[6]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_6 = s2_victim_way[6]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_9 = s2_victim_way[7]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_7 = s2_victim_way[7]; // @[OneHot.scala:58:35] wire [1:0] _s2_victim_tag_WIRE_2_state; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_WIRE_1; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_10 = _s2_victim_tag_T_2 ? s2_meta_corrected_0_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_11 = _s2_victim_tag_T_3 ? s2_meta_corrected_1_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_12 = _s2_victim_tag_T_4 ? s2_meta_corrected_2_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_13 = _s2_victim_tag_T_5 ? s2_meta_corrected_3_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_14 = _s2_victim_tag_T_6 ? s2_meta_corrected_4_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_15 = _s2_victim_tag_T_7 ? s2_meta_corrected_5_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_16 = _s2_victim_tag_T_8 ? s2_meta_corrected_6_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_17 = _s2_victim_tag_T_9 ? s2_meta_corrected_7_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_18 = _s2_victim_tag_T_10 \| _s2_victim_tag_T_11; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_19 = _s2_victim_tag_T_18 \| _s2_victim_tag_T_12; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_20 = _s2_victim_tag_T_19 \| _s2_victim_tag_T_13; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_21 = _s2_victim_tag_T_20 \| _s2_victim_tag_T_14; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_22 = _s2_victim_tag_T_21 \| _s2_victim_tag_T_15; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_23 = _s2_victim_tag_T_22 \| _s2_victim_tag_T_16; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_24 = _s2_victim_tag_T_23 \| _s2_victim_tag_T_17; // @[Mux.scala:30:73] assign _s2_victim_tag_WIRE_1 = _s2_victim_tag_T_24; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_WIRE_tag = _s2_victim_tag_WIRE_1; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_WIRE_3; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_WIRE_coh_state = _s2_victim_tag_WIRE_2_state; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_25 = _s2_victim_tag_T_2 ? s2_meta_corrected_0_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_26 = _s2_victim_tag_T_3 ? s2_meta_corrected_1_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_27 = _s2_victim_tag_T_4 ? s2_meta_corrected_2_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_28 = _s2_victim_tag_T_5 ? s2_meta_corrected_3_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_29 = _s2_victim_tag_T_6 ? s2_meta_corrected_4_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_30 = _s2_victim_tag_T_7 ? s2_meta_corrected_5_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_31 = _s2_victim_tag_T_8 ? s2_meta_corrected_6_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_32 = _s2_victim_tag_T_9 ? s2_meta_corrected_7_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_33 = _s2_victim_tag_T_25 \| _s2_victim_tag_T_26; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_34 = _s2_victim_tag_T_33 \| _s2_victim_tag_T_27; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_35 = _s2_victim_tag_T_34 \| _s2_victim_tag_T_28; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_36 = _s2_victim_tag_T_35 \| _s2_victim_tag_T_29; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_37 = _s2_victim_tag_T_36 \| _s2_victim_tag_T_30; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_38 = _s2_victim_tag_T_37 \| _s2_victim_tag_T_31; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_39 = _s2_victim_tag_T_38 \| _s2_victim_tag_T_32; // @[Mux.scala:30:73] assign _s2_victim_tag_WIRE_3 = _s2_victim_tag_T_39; // @[Mux.scala:30:73] assign _s2_victim_tag_WIRE_2_state = _s2_victim_tag_WIRE_3; // @[Mux.scala:30:73] wire [19:0] s2_victim_tag = _s2_victim_tag_T ? _s2_victim_tag_T_1 : _s2_victim_tag_WIRE_tag; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_WIRE_2_state; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_WIRE_1; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_8 = _s2_victim_state_T ? s2_meta_corrected_0_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_9 = _s2_victim_state_T_1 ? s2_meta_corrected_1_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_10 = _s2_victim_state_T_2 ? s2_meta_corrected_2_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_11 = _s2_victim_state_T_3 ? s2_meta_corrected_3_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_12 = _s2_victim_state_T_4 ? s2_meta_corrected_4_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_13 = _s2_victim_state_T_5 ? s2_meta_corrected_5_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_14 = _s2_victim_state_T_6 ? s2_meta_corrected_6_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_15 = _s2_victim_state_T_7 ? s2_meta_corrected_7_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_16 = _s2_victim_state_T_8 \| _s2_victim_state_T_9; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_17 = _s2_victim_state_T_16 \| _s2_victim_state_T_10; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_18 = _s2_victim_state_T_17 \| _s2_victim_state_T_11; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_19 = _s2_victim_state_T_18 \| _s2_victim_state_T_12; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_20 = _s2_victim_state_T_19 \| _s2_victim_state_T_13; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_21 = _s2_victim_state_T_20 \| _s2_victim_state_T_14; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_22 = _s2_victim_state_T_21 \| _s2_victim_state_T_15; // @[Mux.scala:30:73] assign _s2_victim_state_WIRE_1 = _s2_victim_state_T_22; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_WIRE_tag = _s2_victim_state_WIRE_1; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_WIRE_3; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_WIRE_coh_state = _s2_victim_state_WIRE_2_state; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_23 = _s2_victim_state_T ? s2_meta_corrected_0_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_24 = _s2_victim_state_T_1 ? s2_meta_corrected_1_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_25 = _s2_victim_state_T_2 ? s2_meta_corrected_2_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_26 = _s2_victim_state_T_3 ? s2_meta_corrected_3_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_27 = _s2_victim_state_T_4 ? s2_meta_corrected_4_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_28 = _s2_victim_state_T_5 ? s2_meta_corrected_5_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_29 = _s2_victim_state_T_6 ? s2_meta_corrected_6_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_30 = _s2_victim_state_T_7 ? s2_meta_corrected_7_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_31 = _s2_victim_state_T_23 \| _s2_victim_state_T_24; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_32 = _s2_victim_state_T_31 \| _s2_victim_state_T_25; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_33 = _s2_victim_state_T_32 \| _s2_victim_state_T_26; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_34 = _s2_victim_state_T_33 \| _s2_victim_state_T_27; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_35 = _s2_victim_state_T_34 \| _s2_victim_state_T_28; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_36 = _s2_victim_state_T_35 \| _s2_victim_state_T_29; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_37 = _s2_victim_state_T_36 \| _s2_victim_state_T_30; // @[Mux.scala:30:73] assign _s2_victim_state_WIRE_3 = _s2_victim_state_T_37; // @[Mux.scala:30:73] assign _s2_victim_state_WIRE_2_state = _s2_victim_state_WIRE_3; // @[Mux.scala:30:73] wire [1:0] s2_victim_state_state = s2_hit_valid ? s2_hit_state_state : _s2_victim_state_WIRE_coh_state; // @[Mux.scala:30:73] wire [3:0] _r_T_59 = {probe_bits_param, s2_probe_state_state}; // @[Metadata.scala:120:19] wire _r_T_72 = _r_T_59 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_74 = _r_T_72 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_76 = _r_T_59 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_78 = _r_T_76 ? 3'h2 : _r_T_74; // @[Misc.scala:38:36, :56:20] wire _r_T_80 = _r_T_59 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_82 = _r_T_80 ? 3'h1 : _r_T_78; // @[Misc.scala:38:36, :56:20] wire _r_T_84 = _r_T_59 == 4'hB; // @[Misc.scala:56:20] wire _r_T_85 = _r_T_84; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_86 = _r_T_84 ? 3'h1 : _r_T_82; // @[Misc.scala:38:36, :56:20] wire _r_T_88 = _r_T_59 == 4'h4; // @[Misc.scala:56:20] wire _r_T_89 = ~_r_T_88 & _r_T_85; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_90 = _r_T_88 ? 3'h5 : _r_T_86; // @[Misc.scala:38:36, :56:20] wire _r_T_92 = _r_T_59 == 4'h5; // @[Misc.scala:56:20] wire _r_T_93 = ~_r_T_92 & _r_T_89; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_94 = _r_T_92 ? 3'h4 : _r_T_90; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_95 = {1'h0, _r_T_92}; // @[Misc.scala:38:63, :56:20] wire _r_T_96 = _r_T_59 == 4'h6; // @[Misc.scala:56:20] wire _r_T_97 = ~_r_T_96 & _r_T_93; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_98 = _r_T_96 ? 3'h0 : _r_T_94; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_99 = _r_T_96 ? 2'h1 : _r_T_95; // @[Misc.scala:38:63, :56:20] wire _r_T_100 = _r_T_59 == 4'h7; // @[Misc.scala:56:20] wire _r_T_101 = _r_T_100 \| _r_T_97; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_102 = _r_T_100 ? 3'h0 : _r_T_98; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_103 = _r_T_100 ? 2'h1 : _r_T_99; // @[Misc.scala:38:63, :56:20] wire _r_T_104 = _r_T_59 == 4'h0; // @[Misc.scala:56:20] wire _r_T_105 = ~_r_T_104 & _r_T_101; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_106 = _r_T_104 ? 3'h5 : _r_T_102; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_107 = _r_T_104 ? 2'h0 : _r_T_103; // @[Misc.scala:38:63, :56:20] wire _r_T_108 = _r_T_59 == 4'h1; // @[Misc.scala:56:20] wire _r_T_109 = ~_r_T_108 & _r_T_105; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_110 = _r_T_108 ? 3'h4 : _r_T_106; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_111 = _r_T_108 ? 2'h1 : _r_T_107; // @[Misc.scala:38:63, :56:20] wire _r_T_112 = _r_T_59 == 4'h2; // @[Misc.scala:56:20] wire _r_T_113 = ~_r_T_112 & _r_T_109; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_114 = _r_T_112 ? 3'h3 : _r_T_110; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_115 = _r_T_112 ? 2'h2 : _r_T_111; // @[Misc.scala:38:63, :56:20] wire _r_T_116 = _r_T_59 == 4'h3; // @[Misc.scala:56:20] wire s2_prb_ack_data = _r_T_116 \| _r_T_113; // @[Misc.scala:38:9, :56:20] wire [2:0] s2_report_param = _r_T_116 ? 3'h3 : _r_T_114; // @[Misc.scala:38:36, :56:20] wire [2:0] cleanReleaseMessage_param = s2_report_param; // @[Misc.scala:38:36] wire [2:0] dirtyReleaseMessage_param = s2_report_param; // @[Misc.scala:38:36] wire [1:0] r_3 = _r_T_116 ? 2'h2 : _r_T_115; // @[Misc.scala:38:63, :56:20] wire [1:0] probeNewCoh_state = r_3; // @[Misc.scala:38:63] wire [3:0] _r_T_123 = {2'h2, s2_victim_state_state}; // @[Metadata.scala:120:19] wire _r_T_136 = _r_T_123 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_138 = _r_T_136 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_140 = _r_T_123 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_142 = _r_T_140 ? 3'h2 : _r_T_138; // @[Misc.scala:38:36, :56:20] wire _r_T_144 = _r_T_123 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_146 = _r_T_144 ? 3'h1 : _r_T_142; // @[Misc.scala:38:36, :56:20] wire _r_T_148 = _r_T_123 == 4'hB; // @[Misc.scala:56:20] wire _r_T_149 = _r_T_148; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_150 = _r_T_148 ? 3'h1 : _r_T_146; // @[Misc.scala:38:36, :56:20] wire _r_T_152 = _r_T_123 == 4'h4; // @[Misc.scala:56:20] wire _r_T_153 = ~_r_T_152 & _r_T_149; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_154 = _r_T_152 ? 3'h5 : _r_T_150; // @[Misc.scala:38:36, :56:20] wire _r_T_156 = _r_T_123 == 4'h5; // @[Misc.scala:56:20] wire _r_T_157 = ~_r_T_156 & _r_T_153; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_158 = _r_T_156 ? 3'h4 : _r_T_154; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_159 = {1'h0, _r_T_156}; // @[Misc.scala:38:63, :56:20] wire _r_T_160 = _r_T_123 == 4'h6; // @[Misc.scala:56:20] wire _r_T_161 = ~_r_T_160 & _r_T_157; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_162 = _r_T_160 ? 3'h0 : _r_T_158; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_163 = _r_T_160 ? 2'h1 : _r_T_159; // @[Misc.scala:38:63, :56:20] wire _r_T_164 = _r_T_123 == 4'h7; // @[Misc.scala:56:20] wire _r_T_165 = _r_T_164 \| _r_T_161; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_166 = _r_T_164 ? 3'h0 : _r_T_162; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_167 = _r_T_164 ? 2'h1 : _r_T_163; // @[Misc.scala:38:63, :56:20] wire _r_T_168 = _r_T_123 == 4'h0; // @[Misc.scala:56:20] wire _r_T_169 = ~_r_T_168 & _r_T_165; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_170 = _r_T_168 ? 3'h5 : _r_T_166; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_171 = _r_T_168 ? 2'h0 : _r_T_167; // @[Misc.scala:38:63, :56:20] wire _r_T_172 = _r_T_123 == 4'h1; // @[Misc.scala:56:20] wire _r_T_173 = ~_r_T_172 & _r_T_169; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_174 = _r_T_172 ? 3'h4 : _r_T_170; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_175 = _r_T_172 ? 2'h1 : _r_T_171; // @[Misc.scala:38:63, :56:20] wire _r_T_176 = _r_T_123 == 4'h2; // @[Misc.scala:56:20] wire _r_T_177 = ~_r_T_176 & _r_T_173; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_178 = _r_T_176 ? 3'h3 : _r_T_174; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_179 = _r_T_176 ? 2'h2 : _r_T_175; // @[Misc.scala:38:63, :56:20] wire _r_T_180 = _r_T_123 == 4'h3; // @[Misc.scala:56:20] wire s2_victim_dirty = _r_T_180 \| _r_T_177; // @[Misc.scala:38:9, :56:20] wire [2:0] s2_shrink_param = _r_T_180 ? 3'h3 : _r_T_178; // @[Misc.scala:38:36, :56:20] wire [2:0] nodeOut_c_bits_c_param = s2_shrink_param; // @[Misc.scala:38:36] wire [2:0] nodeOut_c_bits_c_1_param = s2_shrink_param; // @[Misc.scala:38:36] wire [1:0] r_3_1 = _r_T_180 ? 2'h2 : _r_T_179; // @[Misc.scala:38:63, :56:20] wire [1:0] voluntaryNewCoh_state = r_3_1; // @[Misc.scala:38:63] wire _s2_update_meta_T = s2_hit_state_state == s2_new_hit_state_state; // @[Metadata.scala:46:46, :160:20] wire s2_update_meta = ~_s2_update_meta_T; // @[Metadata.scala:46:46, :47:40] wire s2_dont_nack_uncached = s2_valid_uncached_pending & tl_out_a_ready; // @[DCache.scala:159:22, :430:64, :440:57] wire _s2_dont_nack_misc_T_7 = ~s2_hit; // @[Misc.scala:35:9] wire _s2_dont_nack_misc_T_10 = s2_req_cmd == 5'h17; // @[DCache.scala:339:19, :444:17] wire _s2_dont_nack_misc_T_11 = _s2_dont_nack_misc_T_10; // @[DCache.scala:443:55, :444:17] wire s2_dont_nack_misc = _s2_dont_nack_misc_T_1 & _s2_dont_nack_misc_T_11; // @[DCache.scala:441:{43,61}, :443:55] wire _io_cpu_s2_nack_T = ~s2_dont_nack_uncached; // @[DCache.scala:440:57, :445:41] wire _io_cpu_s2_nack_T_1 = s2_valid_no_xcpt & _io_cpu_s2_nack_T; // @[DCache.scala:332:35, :445:{38,41}] wire _io_cpu_s2_nack_T_2 = ~s2_dont_nack_misc; // @[DCache.scala:441:61, :445:67] wire _io_cpu_s2_nack_T_3 = _io_cpu_s2_nack_T_1 & _io_cpu_s2_nack_T_2; // @[DCache.scala:445:{38,64,67}] wire _io_cpu_s2_nack_T_4 = ~s2_valid_hit; // @[DCache.scala:422:48, :445:89] assign _io_cpu_s2_nack_T_5 = _io_cpu_s2_nack_T_3 & _io_cpu_s2_nack_T_4; // @[DCache.scala:445:{64,86,89}] assign io_cpu_s2_nack_0 = _io_cpu_s2_nack_T_5; // @[DCache.scala:101:7, :445:86] assign _metaArb_io_in_2_valid_T = s2_valid_hit_pre_data_ecc_and_waw & s2_update_meta; // @[Metadata.scala:47:40] wire _T_40 = io_cpu_s2_nack_0 \| _metaArb_io_in_2_valid_T; // @[DCache.scala:101:7, :446:24, :462:63] wire [1:0] _s2_first_meta_corrected_T_9_coh_state = _s2_first_meta_corrected_T_8_coh_state; // @[Mux.scala:50:70] wire [19:0] _s2_first_meta_corrected_T_9_tag = _s2_first_meta_corrected_T_8_tag; // @[Mux.scala:50:70] wire [1:0] _s2_first_meta_corrected_T_10_coh_state = _s2_first_meta_corrected_T_9_coh_state; // @[Mux.scala:50:70] wire [19:0] _s2_first_meta_corrected_T_10_tag = _s2_first_meta_corrected_T_9_tag; // @[Mux.scala:50:70] wire [1:0] _s2_first_meta_corrected_T_11_coh_state = _s2_first_meta_corrected_T_10_coh_state; // @[Mux.scala:50:70] wire [19:0] _s2_first_meta_corrected_T_11_tag = _s2_first_meta_corrected_T_10_tag; // @[Mux.scala:50:70] wire [1:0] _s2_first_meta_corrected_T_12_coh_state = _s2_first_meta_corrected_T_11_coh_state; // @[Mux.scala:50:70] wire [19:0] _s2_first_meta_corrected_T_12_tag = _s2_first_meta_corrected_T_11_tag; // @[Mux.scala:50:70] wire [1:0] _s2_first_meta_corrected_T_13_coh_state = _s2_first_meta_corrected_T_12_coh_state; // @[Mux.scala:50:70] wire [19:0] _s2_first_meta_corrected_T_13_tag = _s2_first_meta_corrected_T_12_tag; // @[Mux.scala:50:70] wire [1:0] s2_first_meta_corrected_coh_state = _s2_first_meta_corrected_T_13_coh_state; // @[Mux.scala:50:70] wire [19:0] s2_first_meta_corrected_tag = _s2_first_meta_corrected_T_13_tag; // @[Mux.scala:50:70] wire [1:0] metaArb_io_in_1_bits_data_new_meta_coh_state = s2_first_meta_corrected_coh_state; // @[Mux.scala:50:70] wire [19:0] metaArb_io_in_1_bits_data_new_meta_tag = s2_first_meta_corrected_tag; // @[Mux.scala:50:70] wire _metaArb_io_in_1_valid_T = s2_valid_masked \| s2_flush_valid_pre_tag_ecc; // @[DCache.scala:337:42, :355:43, :450:63] wire _metaArb_io_in_1_valid_T_1 = _metaArb_io_in_1_valid_T \| s2_probe; // @[DCache.scala:333:25, :450:{63,93}] wire [5:0] _metaArb_io_in_1_bits_idx_T = probe_bits_address[11:6]; // @[DCache.scala:184:29, :1200:47] wire [5:0] _metaArb_io_in_6_bits_idx_T_1 = probe_bits_address[11:6]; // @[DCache.scala:184:29, :1200:47] wire [5:0] _dataArb_io_in_2_bits_addr_T = probe_bits_address[11:6]; // @[DCache.scala:184:29, :1200:47] assign _metaArb_io_in_4_bits_idx_T = probe_bits_address[11:6]; // @[DCache.scala:184:29, :1200:47] wire [5:0] _metaArb_io_in_1_bits_idx_T_1 = s2_vaddr[11:6]; // @[DCache.scala:351:21, :453:76] assign _metaArb_io_in_2_bits_idx_T = s2_vaddr[11:6]; // @[DCache.scala:351:21, :453:76, :465:40] assign _metaArb_io_in_3_bits_idx_T = s2_vaddr[11:6]; // @[DCache.scala:351:21, :453:76, :744:40] assign _metaArb_io_in_1_bits_idx_T_2 = s2_probe ? _metaArb_io_in_1_bits_idx_T : _metaArb_io_in_1_bits_idx_T_1; // @[DCache.scala:333:25, :453:{35,76}, :1200:47] assign metaArb_io_in_1_bits_idx = _metaArb_io_in_1_bits_idx_T_2; // @[DCache.scala:135:28, :453:35] wire [11:0] _metaArb_io_in_1_bits_addr_T_1 = {_metaArb_io_in_1_bits_idx_T_2, 6'h0}; // @[DCache.scala:453:35, :454:98] assign _metaArb_io_in_1_bits_addr_T_2 = {_metaArb_io_in_1_bits_addr_T, _metaArb_io_in_1_bits_addr_T_1}; // @[DCache.scala:454:{36,58,98}] assign metaArb_io_in_1_bits_addr = _metaArb_io_in_1_bits_addr_T_2; // @[DCache.scala:135:28, :454:36] assign _metaArb_io_in_1_bits_data_T = {metaArb_io_in_1_bits_data_new_meta_coh_state, metaArb_io_in_1_bits_data_new_meta_tag}; // @[DCache.scala:456:31, :458:14] assign metaArb_io_in_1_bits_data = _metaArb_io_in_1_bits_data_T; // @[DCache.scala:135:28, :458:14] assign metaArb_io_in_2_valid = _metaArb_io_in_2_valid_T; // @[DCache.scala:135:28, :462:63] assign metaArb_io_in_2_bits_idx = _metaArb_io_in_2_bits_idx_T; // @[DCache.scala:135:28, :465:40] wire [11:0] _metaArb_io_in_2_bits_addr_T_1 = s2_vaddr[11:0]; // @[DCache.scala:351:21, :466:80] wire [11:0] _metaArb_io_in_3_bits_addr_T_1 = s2_vaddr[11:0]; // @[DCache.scala:351:21, :466:80, :745:80] assign _metaArb_io_in_2_bits_addr_T_2 = {_metaArb_io_in_2_bits_addr_T, _metaArb_io_in_2_bits_addr_T_1}; // @[DCache.scala:466:{36,58,80}] assign metaArb_io_in_2_bits_addr = _metaArb_io_in_2_bits_addr_T_2; // @[DCache.scala:135:28, :466:36] wire [27:0] _metaArb_io_in_2_bits_data_T = s2_req_addr[39:12]; // @[DCache.scala:339:19, :467:68] wire [27:0] _metaArb_io_in_3_bits_data_T = s2_req_addr[39:12]; // @[DCache.scala:339:19, :467:68, :746:68] wire [19:0] metaArb_io_in_2_bits_data_meta_tag; // @[HellaCache.scala:305:20] assign metaArb_io_in_2_bits_data_meta_tag = _metaArb_io_in_2_bits_data_T[19:0]; // @[HellaCache.scala:305:20, :306:14] assign _metaArb_io_in_2_bits_data_T_1 = {metaArb_io_in_2_bits_data_meta_coh_state, metaArb_io_in_2_bits_data_meta_tag}; // @[HellaCache.scala:305:20] assign metaArb_io_in_2_bits_data = _metaArb_io_in_2_bits_data_T_1; // @[DCache.scala:135:28, :467:97] wire s2_lr = _s2_lr_T; // @[DCache.scala:470:{56,70}] wire s2_sc = _s2_sc_T; // @[DCache.scala:471:{56,70}] wire io_cpu_resp_bits_data_doZero_2 = s2_sc; // @[DCache.scala:471:56] reg [6:0] lrscCount; // @[DCache.scala:472:26] wire lrscValid = \|(lrscCount[6:2]); // @[DCache.scala:472:26, :473:29] wire _lrscBackingOff_T = \|lrscCount; // @[DCache.scala:472:26, :474:34] wire _lrscBackingOff_T_1 = ~lrscValid; // @[DCache.scala:473:29, :474:43] wire lrscBackingOff = _lrscBackingOff_T & _lrscBackingOff_T_1; // @[DCache.scala:474:{34,40,43}] reg [33:0] lrscAddr; // @[DCache.scala:475:21] wire [33:0] _lrscAddrMatch_T = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49] wire [33:0] _lrscAddr_T = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49, :480:29] wire [33:0] _acquire_address_T = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49, :578:38] wire [33:0] _tl_out_a_bits_T_1 = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49, :1210:39] wire [33:0] _io_errors_bus_bits_T = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49, :1130:58] wire lrscAddrMatch = lrscAddr == _lrscAddrMatch_T; // @[DCache.scala:475:21, :476:{32,49}] wire _s2_sc_fail_T = lrscValid & lrscAddrMatch; // @[DCache.scala:473:29, :476:32, :477:41] wire _s2_sc_fail_T_1 = ~_s2_sc_fail_T; // @[DCache.scala:477:{29,41}] wire s2_sc_fail = s2_sc & _s2_sc_fail_T_1; // @[DCache.scala:471:56, :477:{26,29}] wire [6:0] _lrscCount_T = s2_hit ? 7'h4F : 7'h0; // @[Misc.scala:35:9] wire [7:0] _lrscCount_T_1 = {1'h0, lrscCount} - 8'h1; // @[DCache.scala:472:26, :482:51] wire [6:0] _lrscCount_T_2 = _lrscCount_T_1[6:0]; // @[DCache.scala:482:51] wire _s2_correct_T = ~any_pstore_valid; // @[DCache.scala:230:30, :487:37] wire _s2_correct_T_2 = any_pstore_valid \| s2_valid; // @[DCache.scala:230:30, :331:25, :487:84] reg s2_correct_REG; // @[DCache.scala:487:66] wire _s2_correct_T_3 = ~s2_correct_REG; // @[DCache.scala:487:{58,66}] wire _GEN_95 = s1_valid_not_nacked & s1_write; // @[DCache.scala:187:38, :492:63] wire _pstore1_cmd_T; // @[DCache.scala:492:63] assign _pstore1_cmd_T = _GEN_95; // @[DCache.scala:492:63] wire _pstore1_addr_T; // @[DCache.scala:493:62] assign _pstore1_addr_T = _GEN_95; // @[DCache.scala:492:63, :493:62] wire _pstore1_data_T; // @[DCache.scala:494:73] assign _pstore1_data_T = _GEN_95; // @[DCache.scala:492:63, :494:73] wire _pstore1_way_T; // @[DCache.scala:495:63] assign _pstore1_way_T = _GEN_95; // @[DCache.scala:492:63, :495:63] wire _pstore1_mask_T; // @[DCache.scala:496:61] assign _pstore1_mask_T = _GEN_95; // @[DCache.scala:492:63, :496:61] wire _pstore1_rmw_T_53; // @[DCache.scala:498:84] assign _pstore1_rmw_T_53 = _GEN_95; // @[DCache.scala:492:63, :498:84] reg [4:0] pstore1_cmd; // @[DCache.scala:492:30] reg [39:0] pstore1_addr; // @[DCache.scala:493:31] wire [39:0] _pstore2_addr_T = pstore1_addr; // @[DCache.scala:493:31, :524:35] reg [63:0] pstore1_data; // @[DCache.scala:494:31] assign io_cpu_resp_bits_store_data_0 = pstore1_data; // @[DCache.scala:101:7, :494:31] wire [63:0] put_data = pstore1_data; // @[Edges.scala:480:17] wire [63:0] putpartial_data = pstore1_data; // @[Edges.scala:500:17] wire [63:0] atomics_a_data = pstore1_data; // @[Edges.scala:534:17] wire [63:0] atomics_a_1_data = pstore1_data; // @[Edges.scala:534:17] wire [63:0] atomics_a_2_data = pstore1_data; // @[Edges.scala:534:17] wire [63:0] atomics_a_3_data = pstore1_data; // @[Edges.scala:534:17] wire [63:0] atomics_a_4_data = pstore1_data; // @[Edges.scala:517:17] wire [63:0] atomics_a_5_data = pstore1_data; // @[Edges.scala:517:17] wire [63:0] atomics_a_6_data = pstore1_data; // @[Edges.scala:517:17] wire [63:0] atomics_a_7_data = pstore1_data; // @[Edges.scala:517:17] wire [63:0] atomics_a_8_data = pstore1_data; // @[Edges.scala:517:17] wire [63:0] _amoalu_io_rhs_T = pstore1_data; // @[DCache.scala:494:31, :986:37] reg [7:0] pstore1_way; // @[DCache.scala:495:30] wire [7:0] _pstore2_way_T = pstore1_way; // @[DCache.scala:495:30, :525:34] reg [7:0] pstore1_mask; // @[DCache.scala:496:31] wire [7:0] pstore2_storegen_mask_mergedMask = pstore1_mask; // @[DCache.scala:496:31, :533:37] wire [7:0] _amoalu_io_mask_T = pstore1_mask; // @[DCache.scala:496:31, :983:38] wire [63:0] pstore1_storegen_data; // @[DCache.scala:497:42] wire _pstore1_rmw_T_4 = _pstore1_rmw_T \| _pstore1_rmw_T_1; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_5 = _pstore1_rmw_T_4 \| _pstore1_rmw_T_2; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_6 = _pstore1_rmw_T_5 \| _pstore1_rmw_T_3; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_11 = _pstore1_rmw_T_7 \| _pstore1_rmw_T_8; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_12 = _pstore1_rmw_T_11 \| _pstore1_rmw_T_9; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_13 = _pstore1_rmw_T_12 \| _pstore1_rmw_T_10; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_19 = _pstore1_rmw_T_14 \| _pstore1_rmw_T_15; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_20 = _pstore1_rmw_T_19 \| _pstore1_rmw_T_16; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_21 = _pstore1_rmw_T_20 \| _pstore1_rmw_T_17; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_22 = _pstore1_rmw_T_21 \| _pstore1_rmw_T_18; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_23 = _pstore1_rmw_T_13 \| _pstore1_rmw_T_22; // @[package.scala:81:59] wire _pstore1_rmw_T_24 = _pstore1_rmw_T_6 \| _pstore1_rmw_T_23; // @[package.scala:81:59] wire _pstore1_rmw_T_27 = _pstore1_rmw_T_25 \| _pstore1_rmw_T_26; // @[Consts.scala:90:{32,42,49}] wire _pstore1_rmw_T_29 = _pstore1_rmw_T_27 \| _pstore1_rmw_T_28; // @[Consts.scala:90:{42,59,66}] wire _pstore1_rmw_T_34 = _pstore1_rmw_T_30 \| _pstore1_rmw_T_31; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_35 = _pstore1_rmw_T_34 \| _pstore1_rmw_T_32; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_36 = _pstore1_rmw_T_35 \| _pstore1_rmw_T_33; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_42 = _pstore1_rmw_T_37 \| _pstore1_rmw_T_38; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_43 = _pstore1_rmw_T_42 \| _pstore1_rmw_T_39; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_44 = _pstore1_rmw_T_43 \| _pstore1_rmw_T_40; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_45 = _pstore1_rmw_T_44 \| _pstore1_rmw_T_41; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_46 = _pstore1_rmw_T_36 \| _pstore1_rmw_T_45; // @[package.scala:81:59] wire _pstore1_rmw_T_47 = _pstore1_rmw_T_29 \| _pstore1_rmw_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _pstore1_rmw_T_50 = _pstore1_rmw_T_48; // @[DCache.scala:1191:{35,45}] wire _pstore1_rmw_T_51 = _pstore1_rmw_T_47 & _pstore1_rmw_T_50; // @[DCache.scala:1191:{23,45}] wire _pstore1_rmw_T_52 = _pstore1_rmw_T_24 \| _pstore1_rmw_T_51; // @[DCache.scala:1190:21, :1191:23] reg pstore1_rmw_r; // @[DCache.scala:498:44] wire pstore1_rmw = pstore1_rmw_r; // @[DCache.scala:498:{32,44}] wire _pstore1_merge_likely_T = s2_valid_not_nacked_in_s1 & s2_write; // @[DCache.scala:336:44, :499:56] wire _GEN_96 = s2_valid_hit & s2_write; // @[DCache.scala:422:48, :490:46] wire _pstore1_merge_T; // @[DCache.scala:490:46] assign _pstore1_merge_T = _GEN_96; // @[DCache.scala:490:46] wire _pstore1_valid_T; // @[DCache.scala:490:46] assign _pstore1_valid_T = _GEN_96; // @[DCache.scala:490:46] wire _pstore1_held_T; // @[DCache.scala:490:46] assign _pstore1_held_T = _GEN_96; // @[DCache.scala:490:46] wire _pstore1_merge_T_1 = ~s2_sc_fail; // @[DCache.scala:477:26, :490:61] wire _pstore1_merge_T_2 = _pstore1_merge_T & _pstore1_merge_T_1; // @[DCache.scala:490:{46,58,61}] wire _pstore1_merge_T_4 = _pstore1_merge_T_2; // @[DCache.scala:490:58, :491:48] reg pstore2_valid; // @[DCache.scala:501:30] wire _pstore_drain_opportunistic_res_T_2 = _pstore_drain_opportunistic_res_T \| _pstore_drain_opportunistic_res_T_1; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_res_T_3 = ~_pstore_drain_opportunistic_res_T_2; // @[package.scala:81:59] wire pstore_drain_opportunistic_res = _pstore_drain_opportunistic_res_T_3; // @[DCache.scala:1185:{15,46}] wire _pstore_drain_opportunistic_T_4 = _pstore_drain_opportunistic_T \| _pstore_drain_opportunistic_T_1; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_5 = _pstore_drain_opportunistic_T_4 \| _pstore_drain_opportunistic_T_2; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_6 = _pstore_drain_opportunistic_T_5 \| _pstore_drain_opportunistic_T_3; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_11 = _pstore_drain_opportunistic_T_7 \| _pstore_drain_opportunistic_T_8; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_12 = _pstore_drain_opportunistic_T_11 \| _pstore_drain_opportunistic_T_9; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_13 = _pstore_drain_opportunistic_T_12 \| _pstore_drain_opportunistic_T_10; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_19 = _pstore_drain_opportunistic_T_14 \| _pstore_drain_opportunistic_T_15; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_20 = _pstore_drain_opportunistic_T_19 \| _pstore_drain_opportunistic_T_16; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_21 = _pstore_drain_opportunistic_T_20 \| _pstore_drain_opportunistic_T_17; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_22 = _pstore_drain_opportunistic_T_21 \| _pstore_drain_opportunistic_T_18; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_23 = _pstore_drain_opportunistic_T_13 \| _pstore_drain_opportunistic_T_22; // @[package.scala:81:59] wire _pstore_drain_opportunistic_T_24 = _pstore_drain_opportunistic_T_6 \| _pstore_drain_opportunistic_T_23; // @[package.scala:81:59] wire _pstore_drain_opportunistic_T_27 = _pstore_drain_opportunistic_T_25 \| _pstore_drain_opportunistic_T_26; // @[Consts.scala:90:{32,42,49}] wire _pstore_drain_opportunistic_T_29 = _pstore_drain_opportunistic_T_27 \| _pstore_drain_opportunistic_T_28; // @[Consts.scala:90:{42,59,66}] wire _pstore_drain_opportunistic_T_34 = _pstore_drain_opportunistic_T_30 \| _pstore_drain_opportunistic_T_31; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_35 = _pstore_drain_opportunistic_T_34 \| _pstore_drain_opportunistic_T_32; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_36 = _pstore_drain_opportunistic_T_35 \| _pstore_drain_opportunistic_T_33; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_42 = _pstore_drain_opportunistic_T_37 \| _pstore_drain_opportunistic_T_38; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_43 = _pstore_drain_opportunistic_T_42 \| _pstore_drain_opportunistic_T_39; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_44 = _pstore_drain_opportunistic_T_43 \| _pstore_drain_opportunistic_T_40; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_45 = _pstore_drain_opportunistic_T_44 \| _pstore_drain_opportunistic_T_41; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_46 = _pstore_drain_opportunistic_T_36 \| _pstore_drain_opportunistic_T_45; // @[package.scala:81:59] wire _pstore_drain_opportunistic_T_47 = _pstore_drain_opportunistic_T_29 \| _pstore_drain_opportunistic_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _pstore_drain_opportunistic_T_50 = _pstore_drain_opportunistic_T_48; // @[DCache.scala:1191:{35,45}] wire _pstore_drain_opportunistic_T_51 = _pstore_drain_opportunistic_T_47 & _pstore_drain_opportunistic_T_50; // @[DCache.scala:1191:{23,45}] wire _pstore_drain_opportunistic_T_52 = _pstore_drain_opportunistic_T_24 \| _pstore_drain_opportunistic_T_51; // @[DCache.scala:1190:21, :1191:23] wire _pstore_drain_opportunistic_T_53 = ~_pstore_drain_opportunistic_T_52; // @[DCache.scala:1186:12, :1190:21] wire _pstore_drain_opportunistic_T_54 = _pstore_drain_opportunistic_T_53 \| pstore_drain_opportunistic_res; // @[DCache.scala:1185:46, :1186:{12,28}] wire _pstore_drain_opportunistic_T_56 = ~_pstore_drain_opportunistic_T_55; // @[DCache.scala:1186:11] wire _pstore_drain_opportunistic_T_57 = ~_pstore_drain_opportunistic_T_54; // @[DCache.scala:1186:{11,28}] wire _pstore_drain_opportunistic_T_58 = io_cpu_req_valid_0 & pstore_drain_opportunistic_res; // @[DCache.scala:101:7, :502:55, :1185:46] wire _pstore_drain_opportunistic_T_59 = ~_pstore_drain_opportunistic_T_58; // @[DCache.scala:502:{36,55}] wire pstore_drain_opportunistic = _pstore_drain_opportunistic_T_59; // @[DCache.scala:502:{36,92}] reg pstore_drain_on_miss_REG; // @[DCache.scala:503:56] wire pstore_drain_on_miss = releaseInFlight \| pstore_drain_on_miss_REG; // @[DCache.scala:334:46, :503:{46,56}] reg pstore1_held; // @[DCache.scala:504:29] wire _GEN_97 = s2_valid & s2_write; // @[DCache.scala:331:25, :505:39] wire _pstore1_valid_likely_T; // @[DCache.scala:505:39] assign _pstore1_valid_likely_T = _GEN_97; // @[DCache.scala:505:39] wire _io_cpu_perf_storeBufferEmptyAfterLoad_T_1; // @[DCache.scala:1082:16] assign _io_cpu_perf_storeBufferEmptyAfterLoad_T_1 = _GEN_97; // @[DCache.scala:505:39, :1082:16] wire _io_cpu_perf_storeBufferEmptyAfterStore_T_1; // @[DCache.scala:1086:15] assign _io_cpu_perf_storeBufferEmptyAfterStore_T_1 = _GEN_97; // @[DCache.scala:505:39, :1086:15] wire _io_cpu_perf_storeBufferEmptyAfterStore_T_4; // @[DCache.scala:1087:16] assign _io_cpu_perf_storeBufferEmptyAfterStore_T_4 = _GEN_97; // @[DCache.scala:505:39, :1087:16] wire _io_cpu_perf_canAcceptStoreThenLoad_T; // @[DCache.scala:1089:16] assign _io_cpu_perf_canAcceptStoreThenLoad_T = _GEN_97; // @[DCache.scala:505:39, :1089:16] wire _io_cpu_perf_canAcceptLoadThenLoad_T_55; // @[DCache.scala:1092:100] assign _io_cpu_perf_canAcceptLoadThenLoad_T_55 = _GEN_97; // @[DCache.scala:505:39, :1092:100] wire pstore1_valid_likely = _pstore1_valid_likely_T \| pstore1_held; // @[DCache.scala:504:29, :505:{39,51}] wire _pstore1_valid_T_1 = ~s2_sc_fail; // @[DCache.scala:477:26, :490:61] wire _pstore1_valid_T_2 = _pstore1_valid_T & _pstore1_valid_T_1; // @[DCache.scala:490:{46,58,61}] wire _pstore1_valid_T_4 = _pstore1_valid_T_2; // @[DCache.scala:490:58, :491:48] wire pstore1_valid = _pstore1_valid_T_4 \| pstore1_held; // @[DCache.scala:491:48, :504:29, :507:38] wire _advance_pstore1_T = pstore1_valid; // @[DCache.scala:507:38, :522:40] assign _any_pstore_valid_T = pstore1_held \| pstore2_valid; // @[DCache.scala:501:30, :504:29, :508:36] assign any_pstore_valid = _any_pstore_valid_T; // @[DCache.scala:230:30, :508:36] wire _GEN_98 = pstore1_valid_likely & pstore2_valid; // @[DCache.scala:501:30, :505:51, :509:54] wire _pstore_drain_structural_T; // @[DCache.scala:509:54] assign _pstore_drain_structural_T = _GEN_98; // @[DCache.scala:509:54] wire _io_cpu_perf_canAcceptStoreThenLoad_T_6; // @[DCache.scala:1090:20] assign _io_cpu_perf_canAcceptStoreThenLoad_T_6 = _GEN_98; // @[DCache.scala:509:54, :1090:20] wire _GEN_99 = s1_valid & s1_write; // @[DCache.scala:182:25, :509:85] wire _pstore_drain_structural_T_1; // @[DCache.scala:509:85] assign _pstore_drain_structural_T_1 = _GEN_99; // @[DCache.scala:509:85] wire _io_cpu_perf_storeBufferEmptyAfterLoad_T; // @[DCache.scala:1081:15] assign _io_cpu_perf_storeBufferEmptyAfterLoad_T = _GEN_99; // @[DCache.scala:509:85, :1081:15] wire _io_cpu_perf_storeBufferEmptyAfterStore_T; // @[DCache.scala:1085:15] assign _io_cpu_perf_storeBufferEmptyAfterStore_T = _GEN_99; // @[DCache.scala:509:85, :1085:15] wire _io_cpu_perf_canAcceptStoreThenLoad_T_2; // @[DCache.scala:1089:57] assign _io_cpu_perf_canAcceptStoreThenLoad_T_2 = _GEN_99; // @[DCache.scala:509:85, :1089:57] wire _io_cpu_perf_canAcceptStoreThenLoad_T_7; // @[DCache.scala:1090:57] assign _io_cpu_perf_canAcceptStoreThenLoad_T_7 = _GEN_99; // @[DCache.scala:509:85, :1090:57] wire _io_cpu_perf_canAcceptLoadThenLoad_T; // @[DCache.scala:1092:52] assign _io_cpu_perf_canAcceptLoadThenLoad_T = _GEN_99; // @[DCache.scala:509:85, :1092:52] wire _pstore_drain_structural_T_2 = _pstore_drain_structural_T_1 \| pstore1_rmw; // @[DCache.scala:498:32, :509:{85,98}] wire pstore_drain_structural = _pstore_drain_structural_T & _pstore_drain_structural_T_2; // @[DCache.scala:509:{54,71,98}] wire _pstore_drain_T_1 = pstore_drain_structural; // @[DCache.scala:509:71, :517:17] wire _dataArb_io_in_0_valid_T_1 = pstore_drain_structural; // @[DCache.scala:509:71, :517:17] wire _T_49 = s2_valid_hit_pre_data_ecc & s2_write; // @[DCache.scala:420:69, :506:72] wire _pstore_drain_T_2; // @[DCache.scala:506:72] assign _pstore_drain_T_2 = _T_49; // @[DCache.scala:506:72] wire _dataArb_io_in_0_valid_T_2; // @[DCache.scala:506:72] assign _dataArb_io_in_0_valid_T_2 = _T_49; // @[DCache.scala:506:72] wire _pstore_drain_T_4 = _pstore_drain_T_2; // @[DCache.scala:506:{72,84}] wire _pstore_drain_T_5 = _pstore_drain_T_4 \| pstore1_held; // @[DCache.scala:504:29, :506:{84,96}] wire _pstore_drain_T_6 = ~pstore1_rmw; // @[DCache.scala:498:32, :518:44] wire _pstore_drain_T_7 = _pstore_drain_T_5 & _pstore_drain_T_6; // @[DCache.scala:506:96, :518:{41,44}] wire _pstore_drain_T_8 = _pstore_drain_T_7 \| pstore2_valid; // @[DCache.scala:501:30, :518:{41,58}] wire _GEN_100 = pstore_drain_opportunistic \| pstore_drain_on_miss; // @[DCache.scala:502:92, :503:46, :518:107] wire _pstore_drain_T_9; // @[DCache.scala:518:107] assign _pstore_drain_T_9 = _GEN_100; // @[DCache.scala:518:107] wire _dataArb_io_in_0_valid_T_9; // @[DCache.scala:518:107] assign _dataArb_io_in_0_valid_T_9 = _GEN_100; // @[DCache.scala:518:107] wire _pstore_drain_T_10 = _pstore_drain_T_8 & _pstore_drain_T_9; // @[DCache.scala:518:{58,76,107}] wire _pstore_drain_T_11 = _pstore_drain_T_1 \| _pstore_drain_T_10; // @[DCache.scala:517:{17,44}, :518:76] assign pstore_drain = _pstore_drain_T_11; // @[DCache.scala:516:27, :517:44] assign dataArb_io_in_0_bits_write = pstore_drain; // @[DCache.scala:152:28, :516:27] wire _pstore1_held_T_1 = ~s2_sc_fail; // @[DCache.scala:477:26, :490:61] wire _pstore1_held_T_2 = _pstore1_held_T & _pstore1_held_T_1; // @[DCache.scala:490:{46,58,61}] wire _pstore1_held_T_4 = _pstore1_held_T_2; // @[DCache.scala:490:58, :491:48] wire _pstore1_held_T_6 = _pstore1_held_T_4; // @[DCache.scala:491:48, :521:35] wire _pstore1_held_T_7 = _pstore1_held_T_6 \| pstore1_held; // @[DCache.scala:504:29, :521:{35,54}] wire _pstore1_held_T_8 = _pstore1_held_T_7 & pstore2_valid; // @[DCache.scala:501:30, :521:{54,71}] wire _pstore1_held_T_9 = ~pstore_drain; // @[DCache.scala:516:27, :521:91] wire _pstore1_held_T_10 = _pstore1_held_T_8 & _pstore1_held_T_9; // @[DCache.scala:521:{71,88,91}] wire _advance_pstore1_T_1 = pstore2_valid == pstore_drain; // @[DCache.scala:501:30, :516:27, :522:79] wire advance_pstore1 = _advance_pstore1_T & _advance_pstore1_T_1; // @[DCache.scala:522:{40,61,79}] wire _pstore2_storegen_data_T_3 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_7 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_11 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_15 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_19 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_23 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_27 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_31 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_mask_T = advance_pstore1; // @[DCache.scala:522:61, :532:27] wire _pstore2_valid_T = ~pstore_drain; // @[DCache.scala:516:27, :521:91, :523:37] wire _pstore2_valid_T_1 = pstore2_valid & _pstore2_valid_T; // @[DCache.scala:501:30, :523:{34,37}] wire _pstore2_valid_T_2 = _pstore2_valid_T_1 \| advance_pstore1; // @[DCache.scala:522:61, :523:{34,51}] reg [39:0] pstore2_addr; // @[DCache.scala:524:31] reg [7:0] pstore2_way; // @[DCache.scala:525:30] wire [7:0] _pstore2_storegen_data_T = pstore1_storegen_data[7:0]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_1 = pstore1_mask[0]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_3 = pstore1_mask[0]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_4 = pstore1_storegen_data[15:8]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_5 = pstore1_mask[1]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_4 = pstore1_mask[1]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_1; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_8 = pstore1_storegen_data[23:16]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_9 = pstore1_mask[2]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_5 = pstore1_mask[2]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_2; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_12 = pstore1_storegen_data[31:24]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_13 = pstore1_mask[3]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_6 = pstore1_mask[3]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_3; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_16 = pstore1_storegen_data[39:32]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_17 = pstore1_mask[4]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_7 = pstore1_mask[4]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_4; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_20 = pstore1_storegen_data[47:40]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_21 = pstore1_mask[5]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_8 = pstore1_mask[5]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_5; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_24 = pstore1_storegen_data[55:48]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_25 = pstore1_mask[6]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_9 = pstore1_mask[6]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_6; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_28 = pstore1_storegen_data[63:56]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_29 = pstore1_mask[7]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_10 = pstore1_mask[7]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_7; // @[DCache.scala:528:22] wire [15:0] pstore2_storegen_data_lo_lo = {pstore2_storegen_data_r_1, pstore2_storegen_data_r}; // @[package.scala:45:27] wire [15:0] pstore2_storegen_data_lo_hi = {pstore2_storegen_data_r_3, pstore2_storegen_data_r_2}; // @[package.scala:45:27] wire [31:0] pstore2_storegen_data_lo = {pstore2_storegen_data_lo_hi, pstore2_storegen_data_lo_lo}; // @[package.scala:45:27] wire [15:0] pstore2_storegen_data_hi_lo = {pstore2_storegen_data_r_5, pstore2_storegen_data_r_4}; // @[package.scala:45:27] wire [15:0] pstore2_storegen_data_hi_hi = {pstore2_storegen_data_r_7, pstore2_storegen_data_r_6}; // @[package.scala:45:27] wire [31:0] pstore2_storegen_data_hi = {pstore2_storegen_data_hi_hi, pstore2_storegen_data_hi_lo}; // @[package.scala:45:27] wire [63:0] pstore2_storegen_data = {pstore2_storegen_data_hi, pstore2_storegen_data_lo}; // @[package.scala:45:27] reg [7:0] pstore2_storegen_mask; // @[DCache.scala:531:19] wire [7:0] _pstore2_storegen_mask_mask_T = ~pstore2_storegen_mask_mergedMask; // @[DCache.scala:533:37, :534:37] wire [7:0] _pstore2_storegen_mask_mask_T_1 = _pstore2_storegen_mask_mask_T; // @[DCache.scala:534:{19,37}] wire [7:0] _pstore2_storegen_mask_mask_T_2 = ~_pstore2_storegen_mask_mask_T_1; // @[DCache.scala:534:{15,19}] wire _dataArb_io_in_0_valid_T_4 = _dataArb_io_in_0_valid_T_2; // @[DCache.scala:506:{72,84}] wire _dataArb_io_in_0_valid_T_5 = _dataArb_io_in_0_valid_T_4 \| pstore1_held; // @[DCache.scala:504:29, :506:{84,96}] wire _dataArb_io_in_0_valid_T_6 = ~pstore1_rmw; // @[DCache.scala:498:32, :518:44] wire _dataArb_io_in_0_valid_T_7 = _dataArb_io_in_0_valid_T_5 & _dataArb_io_in_0_valid_T_6; // @[DCache.scala:506:96, :518:{41,44}] wire _dataArb_io_in_0_valid_T_8 = _dataArb_io_in_0_valid_T_7 \| pstore2_valid; // @[DCache.scala:501:30, :518:{41,58}] wire _dataArb_io_in_0_valid_T_10 = _dataArb_io_in_0_valid_T_8 & _dataArb_io_in_0_valid_T_9; // @[DCache.scala:518:{58,76,107}] wire _dataArb_io_in_0_valid_T_11 = _dataArb_io_in_0_valid_T_1 \| _dataArb_io_in_0_valid_T_10; // @[DCache.scala:517:{17,44}, :518:76] assign _dataArb_io_in_0_valid_T_12 = _dataArb_io_in_0_valid_T_11; // @[DCache.scala:516:27, :517:44] assign dataArb_io_in_0_valid = _dataArb_io_in_0_valid_T_12; // @[DCache.scala:152:28, :516:27] wire [39:0] _GEN_101 = pstore2_valid ? pstore2_addr : pstore1_addr; // @[DCache.scala:493:31, :501:30, :524:31, :549:36] wire [39:0] _dataArb_io_in_0_bits_addr_T; // @[DCache.scala:549:36] assign _dataArb_io_in_0_bits_addr_T = _GEN_101; // @[DCache.scala:549:36] wire [39:0] _dataArb_io_in_0_bits_wordMask_wordMask_T; // @[DCache.scala:554:32] assign _dataArb_io_in_0_bits_wordMask_wordMask_T = _GEN_101; // @[DCache.scala:549:36, :554:32] assign dataArb_io_in_0_bits_addr = _dataArb_io_in_0_bits_addr_T[11:0]; // @[DCache.scala:152:28, :549:{30,36}] assign _dataArb_io_in_0_bits_way_en_T = pstore2_valid ? pstore2_way : pstore1_way; // @[DCache.scala:495:30, :501:30, :525:30, :550:38] assign dataArb_io_in_0_bits_way_en = _dataArb_io_in_0_bits_way_en_T; // @[DCache.scala:152:28, :550:38] wire [63:0] _dataArb_io_in_0_bits_wdata_T = pstore2_valid ? pstore2_storegen_data : pstore1_data; // @[package.scala:45:27] wire [7:0] _dataArb_io_in_0_bits_wdata_T_1 = _dataArb_io_in_0_bits_wdata_T[7:0]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_2 = _dataArb_io_in_0_bits_wdata_T[15:8]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_3 = _dataArb_io_in_0_bits_wdata_T[23:16]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_4 = _dataArb_io_in_0_bits_wdata_T[31:24]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_5 = _dataArb_io_in_0_bits_wdata_T[39:32]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_6 = _dataArb_io_in_0_bits_wdata_T[47:40]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_7 = _dataArb_io_in_0_bits_wdata_T[55:48]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_8 = _dataArb_io_in_0_bits_wdata_T[63:56]; // @[package.scala:211:50] wire [15:0] dataArb_io_in_0_bits_wdata_lo_lo = {_dataArb_io_in_0_bits_wdata_T_2, _dataArb_io_in_0_bits_wdata_T_1}; // @[package.scala:45:27, :211:50] wire [15:0] dataArb_io_in_0_bits_wdata_lo_hi = {_dataArb_io_in_0_bits_wdata_T_4, _dataArb_io_in_0_bits_wdata_T_3}; // @[package.scala:45:27, :211:50] wire [31:0] dataArb_io_in_0_bits_wdata_lo = {dataArb_io_in_0_bits_wdata_lo_hi, dataArb_io_in_0_bits_wdata_lo_lo}; // @[package.scala:45:27] wire [15:0] dataArb_io_in_0_bits_wdata_hi_lo = {_dataArb_io_in_0_bits_wdata_T_6, _dataArb_io_in_0_bits_wdata_T_5}; // @[package.scala:45:27, :211:50] wire [15:0] dataArb_io_in_0_bits_wdata_hi_hi = {_dataArb_io_in_0_bits_wdata_T_8, _dataArb_io_in_0_bits_wdata_T_7}; // @[package.scala:45:27, :211:50] wire [31:0] dataArb_io_in_0_bits_wdata_hi = {dataArb_io_in_0_bits_wdata_hi_hi, dataArb_io_in_0_bits_wdata_hi_lo}; // @[package.scala:45:27] assign _dataArb_io_in_0_bits_wdata_T_9 = {dataArb_io_in_0_bits_wdata_hi, dataArb_io_in_0_bits_wdata_lo}; // @[package.scala:45:27] assign dataArb_io_in_0_bits_wdata = _dataArb_io_in_0_bits_wdata_T_9; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T = _dataArb_io_in_0_bits_eccMask_T_17[0]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_1 = _dataArb_io_in_0_bits_eccMask_T_17[1]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_2 = _dataArb_io_in_0_bits_eccMask_T_17[2]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_3 = _dataArb_io_in_0_bits_eccMask_T_17[3]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_4 = _dataArb_io_in_0_bits_eccMask_T_17[4]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_5 = _dataArb_io_in_0_bits_eccMask_T_17[5]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_6 = _dataArb_io_in_0_bits_eccMask_T_17[6]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_7 = _dataArb_io_in_0_bits_eccMask_T_17[7]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_8 = _dataArb_io_in_0_bits_wordMask_eccMask_T \| _dataArb_io_in_0_bits_wordMask_eccMask_T_1; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_9 = _dataArb_io_in_0_bits_wordMask_eccMask_T_8 \| _dataArb_io_in_0_bits_wordMask_eccMask_T_2; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_10 = _dataArb_io_in_0_bits_wordMask_eccMask_T_9 \| _dataArb_io_in_0_bits_wordMask_eccMask_T_3; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_11 = _dataArb_io_in_0_bits_wordMask_eccMask_T_10 \| _dataArb_io_in_0_bits_wordMask_eccMask_T_4; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_12 = _dataArb_io_in_0_bits_wordMask_eccMask_T_11 \| _dataArb_io_in_0_bits_wordMask_eccMask_T_5; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_13 = _dataArb_io_in_0_bits_wordMask_eccMask_T_12 \| _dataArb_io_in_0_bits_wordMask_eccMask_T_6; // @[package.scala:81:59] wire dataArb_io_in_0_bits_wordMask_eccMask = _dataArb_io_in_0_bits_wordMask_eccMask_T_13 \| _dataArb_io_in_0_bits_wordMask_eccMask_T_7; // @[package.scala:81:59] wire [1:0] _dataArb_io_in_0_bits_wordMask_T_3 = {1'h0, dataArb_io_in_0_bits_wordMask_eccMask}; // @[package.scala:81:59] assign dataArb_io_in_0_bits_wordMask = _dataArb_io_in_0_bits_wordMask_T_3[0]; // @[DCache.scala:152:28, :552:34, :555:55] wire [7:0] _dataArb_io_in_0_bits_eccMask_T = pstore2_valid ? pstore2_storegen_mask : pstore1_mask; // @[DCache.scala:496:31, :501:30, :531:19, :557:47] wire _dataArb_io_in_0_bits_eccMask_T_1 = _dataArb_io_in_0_bits_eccMask_T[0]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_9 = _dataArb_io_in_0_bits_eccMask_T_1; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_2 = _dataArb_io_in_0_bits_eccMask_T[1]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_10 = _dataArb_io_in_0_bits_eccMask_T_2; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_3 = _dataArb_io_in_0_bits_eccMask_T[2]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_11 = _dataArb_io_in_0_bits_eccMask_T_3; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_4 = _dataArb_io_in_0_bits_eccMask_T[3]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_12 = _dataArb_io_in_0_bits_eccMask_T_4; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_5 = _dataArb_io_in_0_bits_eccMask_T[4]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_13 = _dataArb_io_in_0_bits_eccMask_T_5; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_6 = _dataArb_io_in_0_bits_eccMask_T[5]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_14 = _dataArb_io_in_0_bits_eccMask_T_6; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_7 = _dataArb_io_in_0_bits_eccMask_T[6]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_15 = _dataArb_io_in_0_bits_eccMask_T_7; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_8 = _dataArb_io_in_0_bits_eccMask_T[7]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_16 = _dataArb_io_in_0_bits_eccMask_T_8; // @[package.scala:211:50] wire [1:0] dataArb_io_in_0_bits_eccMask_lo_lo = {_dataArb_io_in_0_bits_eccMask_T_10, _dataArb_io_in_0_bits_eccMask_T_9}; // @[package.scala:45:27] wire [1:0] dataArb_io_in_0_bits_eccMask_lo_hi = {_dataArb_io_in_0_bits_eccMask_T_12, _dataArb_io_in_0_bits_eccMask_T_11}; // @[package.scala:45:27] wire [3:0] dataArb_io_in_0_bits_eccMask_lo = {dataArb_io_in_0_bits_eccMask_lo_hi, dataArb_io_in_0_bits_eccMask_lo_lo}; // @[package.scala:45:27] wire [1:0] dataArb_io_in_0_bits_eccMask_hi_lo = {_dataArb_io_in_0_bits_eccMask_T_14, _dataArb_io_in_0_bits_eccMask_T_13}; // @[package.scala:45:27] wire [1:0] dataArb_io_in_0_bits_eccMask_hi_hi = {_dataArb_io_in_0_bits_eccMask_T_16, _dataArb_io_in_0_bits_eccMask_T_15}; // @[package.scala:45:27] wire [3:0] dataArb_io_in_0_bits_eccMask_hi = {dataArb_io_in_0_bits_eccMask_hi_hi, dataArb_io_in_0_bits_eccMask_hi_lo}; // @[package.scala:45:27] assign _dataArb_io_in_0_bits_eccMask_T_17 = {dataArb_io_in_0_bits_eccMask_hi, dataArb_io_in_0_bits_eccMask_lo}; // @[package.scala:45:27] assign dataArb_io_in_0_bits_eccMask = _dataArb_io_in_0_bits_eccMask_T_17; // @[package.scala:45:27] wire [8:0] _s1_hazard_T = pstore1_addr[11:3]; // @[DCache.scala:493:31, :561:9] wire [8:0] _s1_hazard_T_1 = s1_vaddr[11:3]; // @[DCache.scala:197:21, :561:43] wire [8:0] _s1_hazard_T_63 = s1_vaddr[11:3]; // @[DCache.scala:197:21, :561:43] wire _s1_hazard_T_2 = _s1_hazard_T == _s1_hazard_T_1; // @[DCache.scala:561:{9,31,43}] wire _s1_hazard_T_11 = _s1_hazard_T_3; // @[package.scala:211:50] wire _s1_hazard_T_12 = _s1_hazard_T_4; // @[package.scala:211:50] wire _s1_hazard_T_13 = _s1_hazard_T_5; // @[package.scala:211:50] wire _s1_hazard_T_14 = _s1_hazard_T_6; // @[package.scala:211:50] wire _s1_hazard_T_15 = _s1_hazard_T_7; // @[package.scala:211:50] wire _s1_hazard_T_16 = _s1_hazard_T_8; // @[package.scala:211:50] wire _s1_hazard_T_17 = _s1_hazard_T_9; // @[package.scala:211:50] wire _s1_hazard_T_18 = _s1_hazard_T_10; // @[package.scala:211:50] wire [1:0] s1_hazard_lo_lo = {_s1_hazard_T_12, _s1_hazard_T_11}; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_hi = {_s1_hazard_T_14, _s1_hazard_T_13}; // @[package.scala:45:27] wire [3:0] s1_hazard_lo = {s1_hazard_lo_hi, s1_hazard_lo_lo}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_lo = {_s1_hazard_T_16, _s1_hazard_T_15}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_hi = {_s1_hazard_T_18, _s1_hazard_T_17}; // @[package.scala:45:27] wire [3:0] s1_hazard_hi = {s1_hazard_hi_hi, s1_hazard_hi_lo}; // @[package.scala:45:27] wire [7:0] _s1_hazard_T_19 = {s1_hazard_hi, s1_hazard_lo}; // @[package.scala:45:27] wire _s1_hazard_T_20 = _s1_hazard_T_19[0]; // @[package.scala:45:27] wire _s1_hazard_T_21 = _s1_hazard_T_19[1]; // @[package.scala:45:27] wire _s1_hazard_T_22 = _s1_hazard_T_19[2]; // @[package.scala:45:27] wire _s1_hazard_T_23 = _s1_hazard_T_19[3]; // @[package.scala:45:27] wire _s1_hazard_T_24 = _s1_hazard_T_19[4]; // @[package.scala:45:27] wire _s1_hazard_T_25 = _s1_hazard_T_19[5]; // @[package.scala:45:27] wire _s1_hazard_T_26 = _s1_hazard_T_19[6]; // @[package.scala:45:27] wire _s1_hazard_T_27 = _s1_hazard_T_19[7]; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_lo_1 = {_s1_hazard_T_21, _s1_hazard_T_20}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_lo_hi_1 = {_s1_hazard_T_23, _s1_hazard_T_22}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_lo_1 = {s1_hazard_lo_hi_1, s1_hazard_lo_lo_1}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_lo_1 = {_s1_hazard_T_25, _s1_hazard_T_24}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_hi_1 = {_s1_hazard_T_27, _s1_hazard_T_26}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_hi_1 = {s1_hazard_hi_hi_1, s1_hazard_hi_lo_1}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_28 = {s1_hazard_hi_1, s1_hazard_lo_1}; // @[DCache.scala:1182:52] wire _s1_hazard_T_29 = s1_mask_xwr[0]; // @[package.scala:211:50] wire _s1_hazard_T_91 = s1_mask_xwr[0]; // @[package.scala:211:50] wire _s1_hazard_T_37 = _s1_hazard_T_29; // @[package.scala:211:50] wire _s1_hazard_T_30 = s1_mask_xwr[1]; // @[package.scala:211:50] wire _s1_hazard_T_92 = s1_mask_xwr[1]; // @[package.scala:211:50] wire _s1_hazard_T_38 = _s1_hazard_T_30; // @[package.scala:211:50] wire _s1_hazard_T_31 = s1_mask_xwr[2]; // @[package.scala:211:50] wire _s1_hazard_T_93 = s1_mask_xwr[2]; // @[package.scala:211:50] wire _s1_hazard_T_39 = _s1_hazard_T_31; // @[package.scala:211:50] wire _s1_hazard_T_32 = s1_mask_xwr[3]; // @[package.scala:211:50] wire _s1_hazard_T_94 = s1_mask_xwr[3]; // @[package.scala:211:50] wire _s1_hazard_T_40 = _s1_hazard_T_32; // @[package.scala:211:50] wire _s1_hazard_T_33 = s1_mask_xwr[4]; // @[package.scala:211:50] wire _s1_hazard_T_95 = s1_mask_xwr[4]; // @[package.scala:211:50] wire _s1_hazard_T_41 = _s1_hazard_T_33; // @[package.scala:211:50] wire _s1_hazard_T_34 = s1_mask_xwr[5]; // @[package.scala:211:50] wire _s1_hazard_T_96 = s1_mask_xwr[5]; // @[package.scala:211:50] wire _s1_hazard_T_42 = _s1_hazard_T_34; // @[package.scala:211:50] wire _s1_hazard_T_35 = s1_mask_xwr[6]; // @[package.scala:211:50] wire _s1_hazard_T_97 = s1_mask_xwr[6]; // @[package.scala:211:50] wire _s1_hazard_T_43 = _s1_hazard_T_35; // @[package.scala:211:50] wire _s1_hazard_T_36 = s1_mask_xwr[7]; // @[package.scala:211:50] wire _s1_hazard_T_98 = s1_mask_xwr[7]; // @[package.scala:211:50] wire _s1_hazard_T_44 = _s1_hazard_T_36; // @[package.scala:211:50] wire [1:0] s1_hazard_lo_lo_2 = {_s1_hazard_T_38, _s1_hazard_T_37}; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_hi_2 = {_s1_hazard_T_40, _s1_hazard_T_39}; // @[package.scala:45:27] wire [3:0] s1_hazard_lo_2 = {s1_hazard_lo_hi_2, s1_hazard_lo_lo_2}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_lo_2 = {_s1_hazard_T_42, _s1_hazard_T_41}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_hi_2 = {_s1_hazard_T_44, _s1_hazard_T_43}; // @[package.scala:45:27] wire [3:0] s1_hazard_hi_2 = {s1_hazard_hi_hi_2, s1_hazard_hi_lo_2}; // @[package.scala:45:27] wire [7:0] _s1_hazard_T_45 = {s1_hazard_hi_2, s1_hazard_lo_2}; // @[package.scala:45:27] wire _s1_hazard_T_46 = _s1_hazard_T_45[0]; // @[package.scala:45:27] wire _s1_hazard_T_47 = _s1_hazard_T_45[1]; // @[package.scala:45:27] wire _s1_hazard_T_48 = _s1_hazard_T_45[2]; // @[package.scala:45:27] wire _s1_hazard_T_49 = _s1_hazard_T_45[3]; // @[package.scala:45:27] wire _s1_hazard_T_50 = _s1_hazard_T_45[4]; // @[package.scala:45:27] wire _s1_hazard_T_51 = _s1_hazard_T_45[5]; // @[package.scala:45:27] wire _s1_hazard_T_52 = _s1_hazard_T_45[6]; // @[package.scala:45:27] wire _s1_hazard_T_53 = _s1_hazard_T_45[7]; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_lo_3 = {_s1_hazard_T_47, _s1_hazard_T_46}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_lo_hi_3 = {_s1_hazard_T_49, _s1_hazard_T_48}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_lo_3 = {s1_hazard_lo_hi_3, s1_hazard_lo_lo_3}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_lo_3 = {_s1_hazard_T_51, _s1_hazard_T_50}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_hi_3 = {_s1_hazard_T_53, _s1_hazard_T_52}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_hi_3 = {s1_hazard_hi_hi_3, s1_hazard_hi_lo_3}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_54 = {s1_hazard_hi_3, s1_hazard_lo_3}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_55 = _s1_hazard_T_28 & _s1_hazard_T_54; // @[DCache.scala:562:38, :1182:52] wire _s1_hazard_T_56 = \|_s1_hazard_T_55; // @[DCache.scala:562:{38,66}] wire [7:0] _s1_hazard_T_57 = pstore1_mask & s1_mask_xwr; // @[DCache.scala:496:31, :562:77] wire _s1_hazard_T_58 = \|_s1_hazard_T_57; // @[DCache.scala:562:{77,92}] wire _s1_hazard_T_59 = s1_write ? _s1_hazard_T_56 : _s1_hazard_T_58; // @[DCache.scala:562:{8,66,92}] wire _s1_hazard_T_60 = _s1_hazard_T_2 & _s1_hazard_T_59; // @[DCache.scala:561:{31,65}, :562:8] wire _s1_hazard_T_61 = pstore1_valid_likely & _s1_hazard_T_60; // @[DCache.scala:505:51, :561:65, :564:27] wire [8:0] _s1_hazard_T_62 = pstore2_addr[11:3]; // @[DCache.scala:524:31, :561:9] wire _s1_hazard_T_64 = _s1_hazard_T_62 == _s1_hazard_T_63; // @[DCache.scala:561:{9,31,43}] wire _s1_hazard_T_65 = pstore2_storegen_mask[0]; // @[package.scala:211:50] wire _s1_hazard_T_73 = _s1_hazard_T_65; // @[package.scala:211:50] wire _s1_hazard_T_66 = pstore2_storegen_mask[1]; // @[package.scala:211:50] wire _s1_hazard_T_74 = _s1_hazard_T_66; // @[package.scala:211:50] wire _s1_hazard_T_67 = pstore2_storegen_mask[2]; // @[package.scala:211:50] wire _s1_hazard_T_75 = _s1_hazard_T_67; // @[package.scala:211:50] wire _s1_hazard_T_68 = pstore2_storegen_mask[3]; // @[package.scala:211:50] wire _s1_hazard_T_76 = _s1_hazard_T_68; // @[package.scala:211:50] wire _s1_hazard_T_69 = pstore2_storegen_mask[4]; // @[package.scala:211:50] wire _s1_hazard_T_77 = _s1_hazard_T_69; // @[package.scala:211:50] wire _s1_hazard_T_70 = pstore2_storegen_mask[5]; // @[package.scala:211:50] wire _s1_hazard_T_78 = _s1_hazard_T_70; // @[package.scala:211:50] wire _s1_hazard_T_71 = pstore2_storegen_mask[6]; // @[package.scala:211:50] wire _s1_hazard_T_79 = _s1_hazard_T_71; // @[package.scala:211:50] wire _s1_hazard_T_72 = pstore2_storegen_mask[7]; // @[package.scala:211:50] wire _s1_hazard_T_80 = _s1_hazard_T_72; // @[package.scala:211:50] wire [1:0] s1_hazard_lo_lo_4 = {_s1_hazard_T_74, _s1_hazard_T_73}; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_hi_4 = {_s1_hazard_T_76, _s1_hazard_T_75}; // @[package.scala:45:27] wire [3:0] s1_hazard_lo_4 = {s1_hazard_lo_hi_4, s1_hazard_lo_lo_4}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_lo_4 = {_s1_hazard_T_78, _s1_hazard_T_77}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_hi_4 = {_s1_hazard_T_80, _s1_hazard_T_79}; // @[package.scala:45:27] wire [3:0] s1_hazard_hi_4 = {s1_hazard_hi_hi_4, s1_hazard_hi_lo_4}; // @[package.scala:45:27] wire [7:0] _s1_hazard_T_81 = {s1_hazard_hi_4, s1_hazard_lo_4}; // @[package.scala:45:27] wire _s1_hazard_T_82 = _s1_hazard_T_81[0]; // @[package.scala:45:27] wire _s1_hazard_T_83 = _s1_hazard_T_81[1]; // @[package.scala:45:27] wire _s1_hazard_T_84 = _s1_hazard_T_81[2]; // @[package.scala:45:27] wire _s1_hazard_T_85 = _s1_hazard_T_81[3]; // @[package.scala:45:27] wire _s1_hazard_T_86 = _s1_hazard_T_81[4]; // @[package.scala:45:27] wire _s1_hazard_T_87 = _s1_hazard_T_81[5]; // @[package.scala:45:27] wire _s1_hazard_T_88 = _s1_hazard_T_81[6]; // @[package.scala:45:27] wire _s1_hazard_T_89 = _s1_hazard_T_81[7]; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_lo_5 = {_s1_hazard_T_83, _s1_hazard_T_82}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_lo_hi_5 = {_s1_hazard_T_85, _s1_hazard_T_84}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_lo_5 = {s1_hazard_lo_hi_5, s1_hazard_lo_lo_5}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_lo_5 = {_s1_hazard_T_87, _s1_hazard_T_86}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_hi_5 = {_s1_hazard_T_89, _s1_hazard_T_88}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_hi_5 = {s1_hazard_hi_hi_5, s1_hazard_hi_lo_5}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_90 = {s1_hazard_hi_5, s1_hazard_lo_5}; // @[DCache.scala:1182:52] wire _s1_hazard_T_99 = _s1_hazard_T_91; // @[package.scala:211:50] wire _s1_hazard_T_100 = _s1_hazard_T_92; // @[package.scala:211:50] wire _s1_hazard_T_101 = _s1_hazard_T_93; // @[package.scala:211:50] wire _s1_hazard_T_102 = _s1_hazard_T_94; // @[package.scala:211:50] wire _s1_hazard_T_103 = _s1_hazard_T_95; // @[package.scala:211:50] wire _s1_hazard_T_104 = _s1_hazard_T_96; // @[package.scala:211:50] wire _s1_hazard_T_105 = _s1_hazard_T_97; // @[package.scala:211:50] wire _s1_hazard_T_106 = _s1_hazard_T_98; // @[package.scala:211:50] wire [1:0] s1_hazard_lo_lo_6 = {_s1_hazard_T_100, _s1_hazard_T_99}; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_hi_6 = {_s1_hazard_T_102, _s1_hazard_T_101}; // @[package.scala:45:27] wire [3:0] s1_hazard_lo_6 = {s1_hazard_lo_hi_6, s1_hazard_lo_lo_6}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_lo_6 = {_s1_hazard_T_104, _s1_hazard_T_103}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_hi_6 = {_s1_hazard_T_106, _s1_hazard_T_105}; // @[package.scala:45:27] wire [3:0] s1_hazard_hi_6 = {s1_hazard_hi_hi_6, s1_hazard_hi_lo_6}; // @[package.scala:45:27] wire [7:0] _s1_hazard_T_107 = {s1_hazard_hi_6, s1_hazard_lo_6}; // @[package.scala:45:27] wire _s1_hazard_T_108 = _s1_hazard_T_107[0]; // @[package.scala:45:27] wire _s1_hazard_T_109 = _s1_hazard_T_107[1]; // @[package.scala:45:27] wire _s1_hazard_T_110 = _s1_hazard_T_107[2]; // @[package.scala:45:27] wire _s1_hazard_T_111 = _s1_hazard_T_107[3]; // @[package.scala:45:27] wire _s1_hazard_T_112 = _s1_hazard_T_107[4]; // @[package.scala:45:27] wire _s1_hazard_T_113 = _s1_hazard_T_107[5]; // @[package.scala:45:27] wire _s1_hazard_T_114 = _s1_hazard_T_107[6]; // @[package.scala:45:27] wire _s1_hazard_T_115 = _s1_hazard_T_107[7]; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_lo_7 = {_s1_hazard_T_109, _s1_hazard_T_108}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_lo_hi_7 = {_s1_hazard_T_111, _s1_hazard_T_110}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_lo_7 = {s1_hazard_lo_hi_7, s1_hazard_lo_lo_7}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_lo_7 = {_s1_hazard_T_113, _s1_hazard_T_112}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_hi_7 = {_s1_hazard_T_115, _s1_hazard_T_114}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_hi_7 = {s1_hazard_hi_hi_7, s1_hazard_hi_lo_7}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_116 = {s1_hazard_hi_7, s1_hazard_lo_7}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_117 = _s1_hazard_T_90 & _s1_hazard_T_116; // @[DCache.scala:562:38, :1182:52] wire _s1_hazard_T_118 = \|_s1_hazard_T_117; // @[DCache.scala:562:{38,66}] wire [7:0] _s1_hazard_T_119 = pstore2_storegen_mask & s1_mask_xwr; // @[DCache.scala:531:19, :562:77] wire _s1_hazard_T_120 = \|_s1_hazard_T_119; // @[DCache.scala:562:{77,92}] wire _s1_hazard_T_121 = s1_write ? _s1_hazard_T_118 : _s1_hazard_T_120; // @[DCache.scala:562:{8,66,92}] wire _s1_hazard_T_122 = _s1_hazard_T_64 & _s1_hazard_T_121; // @[DCache.scala:561:{31,65}, :562:8] wire _s1_hazard_T_123 = pstore2_valid & _s1_hazard_T_122; // @[DCache.scala:501:30, :561:65, :565:21] wire s1_hazard = _s1_hazard_T_61 \| _s1_hazard_T_123; // @[DCache.scala:564:{27,69}, :565:21] wire s1_raw_hazard = s1_read & s1_hazard; // @[DCache.scala:564:69, :566:31] wire _T_60 = s1_valid & s1_raw_hazard; // @[DCache.scala:182:25, :566:31, :571:18] reg io_cpu_s2_nack_cause_raw_REG; // @[DCache.scala:574:38] assign _io_cpu_s2_nack_cause_raw_T_3 = io_cpu_s2_nack_cause_raw_REG; // @[DCache.scala:574:{38,54}] assign io_cpu_s2_nack_cause_raw_0 = _io_cpu_s2_nack_cause_raw_T_3; // @[DCache.scala:101:7, :574:54] wire _a_source_T = ~uncachedInFlight_0; // @[DCache.scala:236:33, :577:34] wire [1:0] _a_source_T_1 = {_a_source_T, 1'h0}; // @[DCache.scala:577:{34,59}] wire _a_source_T_2 = _a_source_T_1[0]; // @[OneHot.scala:48:45] wire _a_source_T_3 = _a_source_T_1[1]; // @[OneHot.scala:48:45] wire a_source = ~_a_source_T_2; // @[OneHot.scala:48:45] wire get_source = a_source; // @[Mux.scala:50:70] wire put_source = a_source; // @[Mux.scala:50:70] wire putpartial_source = a_source; // @[Mux.scala:50:70] wire atomics_a_source = a_source; // @[Mux.scala:50:70] wire atomics_a_1_source = a_source; // @[Mux.scala:50:70] wire atomics_a_2_source = a_source; // @[Mux.scala:50:70] wire atomics_a_3_source = a_source; // @[Mux.scala:50:70] wire atomics_a_4_source = a_source; // @[Mux.scala:50:70] wire atomics_a_5_source = a_source; // @[Mux.scala:50:70] wire atomics_a_6_source = a_source; // @[Mux.scala:50:70] wire atomics_a_7_source = a_source; // @[Mux.scala:50:70] wire atomics_a_8_source = a_source; // @[Mux.scala:50:70] wire a_sel_shiftAmount = a_source; // @[OneHot.scala:64:49] wire [39:0] acquire_address = {_acquire_address_T, 6'h0}; // @[DCache.scala:578:{38,49}] wire [22:0] a_mask = {15'h0, pstore1_mask}; // @[DCache.scala:496:31, :582:29] wire [39:0] _GEN_102 = {s2_req_addr[39:14], s2_req_addr[13:0] ^ 14'h3000}; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_4; // @[Parameters.scala:137:31] assign _get_legal_T_4 = _GEN_102; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_4; // @[Parameters.scala:137:31] assign _put_legal_T_4 = _GEN_102; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_4; // @[Parameters.scala:137:31] assign _putpartial_legal_T_4 = _GEN_102; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_5 = {1'h0, _get_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_6 = _get_legal_T_5 & 41'h9A013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_7 = _get_legal_T_6; // @[Parameters.scala:137:46] wire _get_legal_T_8 = _get_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_9 = _get_legal_T_8; // @[Parameters.scala:684:54] wire _get_legal_T_62 = _get_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [40:0] _get_legal_T_15 = {1'h0, _get_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_16 = _get_legal_T_15 & 41'h9A012000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_17 = _get_legal_T_16; // @[Parameters.scala:137:46] wire _get_legal_T_18 = _get_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_103 = {s2_req_addr[39:17], s2_req_addr[16:0] ^ 17'h10000}; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_19; // @[Parameters.scala:137:31] assign _get_legal_T_19 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_24; // @[Parameters.scala:137:31] assign _get_legal_T_24 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_63; // @[Parameters.scala:137:31] assign _put_legal_T_63 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_63; // @[Parameters.scala:137:31] assign _putpartial_legal_T_63 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_47; // @[Parameters.scala:137:31] assign _atomics_legal_T_47 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_101; // @[Parameters.scala:137:31] assign _atomics_legal_T_101 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_155; // @[Parameters.scala:137:31] assign _atomics_legal_T_155 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_209; // @[Parameters.scala:137:31] assign _atomics_legal_T_209 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_263; // @[Parameters.scala:137:31] assign _atomics_legal_T_263 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_317; // @[Parameters.scala:137:31] assign _atomics_legal_T_317 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_371; // @[Parameters.scala:137:31] assign _atomics_legal_T_371 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_425; // @[Parameters.scala:137:31] assign _atomics_legal_T_425 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_479; // @[Parameters.scala:137:31] assign _atomics_legal_T_479 = _GEN_103; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_20 = {1'h0, _get_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_21 = _get_legal_T_20 & 41'h98013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_22 = _get_legal_T_21; // @[Parameters.scala:137:46] wire _get_legal_T_23 = _get_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _get_legal_T_25 = {1'h0, _get_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_26 = _get_legal_T_25 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_27 = _get_legal_T_26; // @[Parameters.scala:137:46] wire _get_legal_T_28 = _get_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_104 = {s2_req_addr[39:26], s2_req_addr[25:0] ^ 26'h2000000}; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_29; // @[Parameters.scala:137:31] assign _get_legal_T_29 = _GEN_104; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_24; // @[Parameters.scala:137:31] assign _put_legal_T_24 = _GEN_104; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_24; // @[Parameters.scala:137:31] assign _putpartial_legal_T_24 = _GEN_104; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_30 = {1'h0, _get_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_31 = _get_legal_T_30 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_32 = _get_legal_T_31; // @[Parameters.scala:137:46] wire _get_legal_T_33 = _get_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_105 = {s2_req_addr[39:28], s2_req_addr[27:0] ^ 28'h8000000}; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_34; // @[Parameters.scala:137:31] assign _get_legal_T_34 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_39; // @[Parameters.scala:137:31] assign _get_legal_T_39 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_34; // @[Parameters.scala:137:31] assign _put_legal_T_34 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_39; // @[Parameters.scala:137:31] assign _put_legal_T_39 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_34; // @[Parameters.scala:137:31] assign _putpartial_legal_T_34 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_39; // @[Parameters.scala:137:31] assign _putpartial_legal_T_39 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_19; // @[Parameters.scala:137:31] assign _atomics_legal_T_19 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_24; // @[Parameters.scala:137:31] assign _atomics_legal_T_24 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_73; // @[Parameters.scala:137:31] assign _atomics_legal_T_73 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_78; // @[Parameters.scala:137:31] assign _atomics_legal_T_78 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_127; // @[Parameters.scala:137:31] assign _atomics_legal_T_127 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_132; // @[Parameters.scala:137:31] assign _atomics_legal_T_132 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_181; // @[Parameters.scala:137:31] assign _atomics_legal_T_181 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_186; // @[Parameters.scala:137:31] assign _atomics_legal_T_186 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_235; // @[Parameters.scala:137:31] assign _atomics_legal_T_235 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_240; // @[Parameters.scala:137:31] assign _atomics_legal_T_240 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_289; // @[Parameters.scala:137:31] assign _atomics_legal_T_289 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_294; // @[Parameters.scala:137:31] assign _atomics_legal_T_294 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_343; // @[Parameters.scala:137:31] assign _atomics_legal_T_343 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_348; // @[Parameters.scala:137:31] assign _atomics_legal_T_348 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_397; // @[Parameters.scala:137:31] assign _atomics_legal_T_397 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_402; // @[Parameters.scala:137:31] assign _atomics_legal_T_402 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_451; // @[Parameters.scala:137:31] assign _atomics_legal_T_451 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_456; // @[Parameters.scala:137:31] assign _atomics_legal_T_456 = _GEN_105; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_35 = {1'h0, _get_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_36 = _get_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_37 = _get_legal_T_36; // @[Parameters.scala:137:46] wire _get_legal_T_38 = _get_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _get_legal_T_40 = {1'h0, _get_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_41 = _get_legal_T_40 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_42 = _get_legal_T_41; // @[Parameters.scala:137:46] wire _get_legal_T_43 = _get_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_106 = {s2_req_addr[39:29], s2_req_addr[28:0] ^ 29'h10000000}; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_44; // @[Parameters.scala:137:31] assign _get_legal_T_44 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_44; // @[Parameters.scala:137:31] assign _put_legal_T_44 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_44; // @[Parameters.scala:137:31] assign _putpartial_legal_T_44 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_29; // @[Parameters.scala:137:31] assign _atomics_legal_T_29 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_83; // @[Parameters.scala:137:31] assign _atomics_legal_T_83 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_137; // @[Parameters.scala:137:31] assign _atomics_legal_T_137 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_191; // @[Parameters.scala:137:31] assign _atomics_legal_T_191 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_245; // @[Parameters.scala:137:31] assign _atomics_legal_T_245 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_299; // @[Parameters.scala:137:31] assign _atomics_legal_T_299 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_353; // @[Parameters.scala:137:31] assign _atomics_legal_T_353 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_407; // @[Parameters.scala:137:31] assign _atomics_legal_T_407 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_461; // @[Parameters.scala:137:31] assign _atomics_legal_T_461 = _GEN_106; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_45 = {1'h0, _get_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_46 = _get_legal_T_45 & 41'h9A013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_47 = _get_legal_T_46; // @[Parameters.scala:137:46] wire _get_legal_T_48 = _get_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] assign io_cpu_s2_paddr_0 = s2_req_addr[31:0]; // @[DCache.scala:101:7, :339:19] wire [31:0] get_address = s2_req_addr[31:0]; // @[Edges.scala:460:17] wire [31:0] put_address = s2_req_addr[31:0]; // @[Edges.scala:480:17] wire [31:0] putpartial_address = s2_req_addr[31:0]; // @[Edges.scala:500:17] wire [31:0] atomics_a_address = s2_req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_1_address = s2_req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_2_address = s2_req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_3_address = s2_req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_4_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_5_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_6_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_7_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_8_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [39:0] _GEN_107 = {s2_req_addr[39:32], s2_req_addr[31:0] ^ 32'h80000000}; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_49; // @[Parameters.scala:137:31] assign _get_legal_T_49 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_49; // @[Parameters.scala:137:31] assign _put_legal_T_49 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_49; // @[Parameters.scala:137:31] assign _putpartial_legal_T_49 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_34; // @[Parameters.scala:137:31] assign _atomics_legal_T_34 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_88; // @[Parameters.scala:137:31] assign _atomics_legal_T_88 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_142; // @[Parameters.scala:137:31] assign _atomics_legal_T_142 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_196; // @[Parameters.scala:137:31] assign _atomics_legal_T_196 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_250; // @[Parameters.scala:137:31] assign _atomics_legal_T_250 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_304; // @[Parameters.scala:137:31] assign _atomics_legal_T_304 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_358; // @[Parameters.scala:137:31] assign _atomics_legal_T_358 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_412; // @[Parameters.scala:137:31] assign _atomics_legal_T_412 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_466; // @[Parameters.scala:137:31] assign _atomics_legal_T_466 = _GEN_107; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_50 = {1'h0, _get_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_51 = _get_legal_T_50 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_52 = _get_legal_T_51; // @[Parameters.scala:137:46] wire _get_legal_T_53 = _get_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_54 = _get_legal_T_18 \| _get_legal_T_23; // @[Parameters.scala:685:42] wire _get_legal_T_55 = _get_legal_T_54 \| _get_legal_T_28; // @[Parameters.scala:685:42] wire _get_legal_T_56 = _get_legal_T_55 \| _get_legal_T_33; // @[Parameters.scala:685:42] wire _get_legal_T_57 = _get_legal_T_56 \| _get_legal_T_38; // @[Parameters.scala:685:42] wire _get_legal_T_58 = _get_legal_T_57 \| _get_legal_T_43; // @[Parameters.scala:685:42] wire _get_legal_T_59 = _get_legal_T_58 \| _get_legal_T_48; // @[Parameters.scala:685:42] wire _get_legal_T_60 = _get_legal_T_59 \| _get_legal_T_53; // @[Parameters.scala:685:42] wire _get_legal_T_61 = _get_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire get_legal = _get_legal_T_62 \| _get_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire [7:0] _get_a_mask_T; // @[Misc.scala:222:10] wire [3:0] get_size; // @[Edges.scala:460:17] wire [7:0] get_mask; // @[Edges.scala:460:17] wire [3:0] _GEN_108 = {2'h0, s2_req_size}; // @[Edges.scala:463:15] assign get_size = _GEN_108; // @[Edges.scala:460:17, :463:15] wire [3:0] put_size; // @[Edges.scala:480:17] assign put_size = _GEN_108; // @[Edges.scala:463:15, :480:17] wire [3:0] putpartial_size; // @[Edges.scala:500:17] assign putpartial_size = _GEN_108; // @[Edges.scala:463:15, :500:17] wire [3:0] atomics_a_size; // @[Edges.scala:534:17] assign atomics_a_size = _GEN_108; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_1_size; // @[Edges.scala:534:17] assign atomics_a_1_size = _GEN_108; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_2_size; // @[Edges.scala:534:17] assign atomics_a_2_size = _GEN_108; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_3_size; // @[Edges.scala:534:17] assign atomics_a_3_size = _GEN_108; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_4_size; // @[Edges.scala:517:17] assign atomics_a_4_size = _GEN_108; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_5_size; // @[Edges.scala:517:17] assign atomics_a_5_size = _GEN_108; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_6_size; // @[Edges.scala:517:17] assign atomics_a_6_size = _GEN_108; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_7_size; // @[Edges.scala:517:17] assign atomics_a_7_size = _GEN_108; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_8_size; // @[Edges.scala:517:17] assign atomics_a_8_size = _GEN_108; // @[Edges.scala:463:15, :517:17] wire [2:0] _GEN_109 = {1'h0, s2_req_size}; // @[Misc.scala:202:34] wire [2:0] _get_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _get_a_mask_sizeOH_T = _GEN_109; // @[Misc.scala:202:34] wire [2:0] _put_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _put_a_mask_sizeOH_T = _GEN_109; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T = _GEN_109; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_3; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_3 = _GEN_109; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_6; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_6 = _GEN_109; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_9; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_9 = _GEN_109; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_12; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_12 = _GEN_109; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_15; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_15 = _GEN_109; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_18; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_18 = _GEN_109; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_21; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_21 = _GEN_109; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_24; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_24 = _GEN_109; // @[Misc.scala:202:34] wire [1:0] get_a_mask_sizeOH_shiftAmount = _get_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _get_a_mask_sizeOH_T_1 = 4'h1 << get_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _get_a_mask_sizeOH_T_2 = _get_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] get_a_mask_sizeOH = {_get_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire get_a_mask_sub_sub_sub_0_1 = &s2_req_size; // @[Misc.scala:206:21] wire get_a_mask_sub_sub_size = get_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_sub_bit = s2_req_addr[2]; // @[Misc.scala:210:26] wire put_a_mask_sub_sub_bit = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_1 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_2 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_3 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_4 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_5 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_6 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_7 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_8 = s2_req_addr[2]; // @[Misc.scala:210:26] wire _io_cpu_resp_bits_data_shifted_T = s2_req_addr[2]; // @[Misc.scala:210:26] wire _io_cpu_resp_bits_data_word_bypass_shifted_T = s2_req_addr[2]; // @[Misc.scala:210:26] wire get_a_mask_sub_sub_1_2 = get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire get_a_mask_sub_sub_nbit = ~get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_sub_0_2 = get_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_sub_acc_T = get_a_mask_sub_sub_size & get_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_0_1 = get_a_mask_sub_sub_sub_0_1 \| _get_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _get_a_mask_sub_sub_acc_T_1 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_1_1 = get_a_mask_sub_sub_sub_0_1 \| _get_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire get_a_mask_sub_size = get_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_bit = s2_req_addr[1]; // @[Misc.scala:210:26] wire put_a_mask_sub_bit = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_1 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_2 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_3 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_4 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_5 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_6 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_7 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_8 = s2_req_addr[1]; // @[Misc.scala:210:26] wire _io_cpu_resp_bits_data_shifted_T_3 = s2_req_addr[1]; // @[Misc.scala:210:26] wire get_a_mask_sub_nbit = ~get_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_0_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T = get_a_mask_sub_size & get_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_0_1 = get_a_mask_sub_sub_0_1 \| _get_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_1_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_1 = get_a_mask_sub_size & get_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_1_1 = get_a_mask_sub_sub_0_1 \| _get_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_2_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T_2 = get_a_mask_sub_size & get_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_2_1 = get_a_mask_sub_sub_1_1 \| _get_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_3_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_3 = get_a_mask_sub_size & get_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_3_1 = get_a_mask_sub_sub_1_1 \| _get_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_size = get_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_bit = s2_req_addr[0]; // @[Misc.scala:210:26] wire put_a_mask_bit = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_1 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_2 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_3 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_4 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_5 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_6 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_7 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_8 = s2_req_addr[0]; // @[Misc.scala:210:26] wire _io_cpu_resp_bits_data_shifted_T_6 = s2_req_addr[0]; // @[Misc.scala:210:26] wire get_a_mask_nbit = ~get_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_eq = get_a_mask_sub_0_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T = get_a_mask_size & get_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc = get_a_mask_sub_0_1 \| _get_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_1 = get_a_mask_sub_0_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_1 = get_a_mask_size & get_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_1 = get_a_mask_sub_0_1 \| _get_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_2 = get_a_mask_sub_1_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_2 = get_a_mask_size & get_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_2 = get_a_mask_sub_1_1 \| _get_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_3 = get_a_mask_sub_1_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_3 = get_a_mask_size & get_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_3 = get_a_mask_sub_1_1 \| _get_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_4 = get_a_mask_sub_2_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_4 = get_a_mask_size & get_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_4 = get_a_mask_sub_2_1 \| _get_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_5 = get_a_mask_sub_2_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_5 = get_a_mask_size & get_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_5 = get_a_mask_sub_2_1 \| _get_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_6 = get_a_mask_sub_3_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_6 = get_a_mask_size & get_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_6 = get_a_mask_sub_3_1 \| _get_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_7 = get_a_mask_sub_3_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_7 = get_a_mask_size & get_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_7 = get_a_mask_sub_3_1 \| _get_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] get_a_mask_lo_lo = {get_a_mask_acc_1, get_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_lo_hi = {get_a_mask_acc_3, get_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_lo = {get_a_mask_lo_hi, get_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_hi_lo = {get_a_mask_acc_5, get_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_hi_hi = {get_a_mask_acc_7, get_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_hi = {get_a_mask_hi_hi, get_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _get_a_mask_T = {get_a_mask_hi, get_a_mask_lo}; // @[Misc.scala:222:10] assign get_mask = _get_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _put_legal_T_5 = {1'h0, _put_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_6 = _put_legal_T_5 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_7 = _put_legal_T_6; // @[Parameters.scala:137:46] wire _put_legal_T_8 = _put_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_9 = _put_legal_T_8; // @[Parameters.scala:684:54] wire _put_legal_T_69 = _put_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [40:0] _put_legal_T_15 = {1'h0, _put_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_16 = _put_legal_T_15 & 41'h9A112000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_17 = _put_legal_T_16; // @[Parameters.scala:137:46] wire _put_legal_T_18 = _put_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_110 = {s2_req_addr[39:21], s2_req_addr[20:0] ^ 21'h100000}; // @[DCache.scala:339:19] wire [39:0] _put_legal_T_19; // @[Parameters.scala:137:31] assign _put_legal_T_19 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_19; // @[Parameters.scala:137:31] assign _putpartial_legal_T_19 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_9; // @[Parameters.scala:137:31] assign _atomics_legal_T_9 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_63; // @[Parameters.scala:137:31] assign _atomics_legal_T_63 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_117; // @[Parameters.scala:137:31] assign _atomics_legal_T_117 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_171; // @[Parameters.scala:137:31] assign _atomics_legal_T_171 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_225; // @[Parameters.scala:137:31] assign _atomics_legal_T_225 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_279; // @[Parameters.scala:137:31] assign _atomics_legal_T_279 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_333; // @[Parameters.scala:137:31] assign _atomics_legal_T_333 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_387; // @[Parameters.scala:137:31] assign _atomics_legal_T_387 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_441; // @[Parameters.scala:137:31] assign _atomics_legal_T_441 = _GEN_110; // @[Parameters.scala:137:31] wire [40:0] _put_legal_T_20 = {1'h0, _put_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_21 = _put_legal_T_20 & 41'h9A103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_22 = _put_legal_T_21; // @[Parameters.scala:137:46] wire _put_legal_T_23 = _put_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_25 = {1'h0, _put_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_26 = _put_legal_T_25 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_27 = _put_legal_T_26; // @[Parameters.scala:137:46] wire _put_legal_T_28 = _put_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_111 = {s2_req_addr[39:26], s2_req_addr[25:0] ^ 26'h2010000}; // @[DCache.scala:339:19] wire [39:0] _put_legal_T_29; // @[Parameters.scala:137:31] assign _put_legal_T_29 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_29; // @[Parameters.scala:137:31] assign _putpartial_legal_T_29 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_14; // @[Parameters.scala:137:31] assign _atomics_legal_T_14 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_68; // @[Parameters.scala:137:31] assign _atomics_legal_T_68 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_122; // @[Parameters.scala:137:31] assign _atomics_legal_T_122 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_176; // @[Parameters.scala:137:31] assign _atomics_legal_T_176 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_230; // @[Parameters.scala:137:31] assign _atomics_legal_T_230 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_284; // @[Parameters.scala:137:31] assign _atomics_legal_T_284 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_338; // @[Parameters.scala:137:31] assign _atomics_legal_T_338 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_392; // @[Parameters.scala:137:31] assign _atomics_legal_T_392 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_446; // @[Parameters.scala:137:31] assign _atomics_legal_T_446 = _GEN_111; // @[Parameters.scala:137:31] wire [40:0] _put_legal_T_30 = {1'h0, _put_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_31 = _put_legal_T_30 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_32 = _put_legal_T_31; // @[Parameters.scala:137:46] wire _put_legal_T_33 = _put_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_35 = {1'h0, _put_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_36 = _put_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_37 = _put_legal_T_36; // @[Parameters.scala:137:46] wire _put_legal_T_38 = _put_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_40 = {1'h0, _put_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_41 = _put_legal_T_40 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_42 = _put_legal_T_41; // @[Parameters.scala:137:46] wire _put_legal_T_43 = _put_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_45 = {1'h0, _put_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_46 = _put_legal_T_45 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_47 = _put_legal_T_46; // @[Parameters.scala:137:46] wire _put_legal_T_48 = _put_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_50 = {1'h0, _put_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_51 = _put_legal_T_50 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_52 = _put_legal_T_51; // @[Parameters.scala:137:46] wire _put_legal_T_53 = _put_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_54 = _put_legal_T_18 \| _put_legal_T_23; // @[Parameters.scala:685:42] wire _put_legal_T_55 = _put_legal_T_54 \| _put_legal_T_28; // @[Parameters.scala:685:42] wire _put_legal_T_56 = _put_legal_T_55 \| _put_legal_T_33; // @[Parameters.scala:685:42] wire _put_legal_T_57 = _put_legal_T_56 \| _put_legal_T_38; // @[Parameters.scala:685:42] wire _put_legal_T_58 = _put_legal_T_57 \| _put_legal_T_43; // @[Parameters.scala:685:42] wire _put_legal_T_59 = _put_legal_T_58 \| _put_legal_T_48; // @[Parameters.scala:685:42] wire _put_legal_T_60 = _put_legal_T_59 \| _put_legal_T_53; // @[Parameters.scala:685:42] wire _put_legal_T_61 = _put_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire [40:0] _put_legal_T_64 = {1'h0, _put_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_65 = _put_legal_T_64 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_66 = _put_legal_T_65; // @[Parameters.scala:137:46] wire _put_legal_T_67 = _put_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_70 = _put_legal_T_69 \| _put_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire put_legal = _put_legal_T_70; // @[Parameters.scala:686:26] wire [7:0] _put_a_mask_T; // @[Misc.scala:222:10] wire [7:0] put_mask; // @[Edges.scala:480:17] wire [1:0] put_a_mask_sizeOH_shiftAmount = _put_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _put_a_mask_sizeOH_T_1 = 4'h1 << put_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _put_a_mask_sizeOH_T_2 = _put_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] put_a_mask_sizeOH = {_put_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire put_a_mask_sub_sub_sub_0_1 = &s2_req_size; // @[Misc.scala:206:21] wire put_a_mask_sub_sub_size = put_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_sub_1_2 = put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire put_a_mask_sub_sub_nbit = ~put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_sub_0_2 = put_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_sub_acc_T = put_a_mask_sub_sub_size & put_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_0_1 = put_a_mask_sub_sub_sub_0_1 \| _put_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _put_a_mask_sub_sub_acc_T_1 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_1_1 = put_a_mask_sub_sub_sub_0_1 \| _put_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire put_a_mask_sub_size = put_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_nbit = ~put_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_0_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T = put_a_mask_sub_size & put_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_0_1 = put_a_mask_sub_sub_0_1 \| _put_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_1_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_1 = put_a_mask_sub_size & put_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_1_1 = put_a_mask_sub_sub_0_1 \| _put_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_2_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T_2 = put_a_mask_sub_size & put_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_2_1 = put_a_mask_sub_sub_1_1 \| _put_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_3_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_3 = put_a_mask_sub_size & put_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_3_1 = put_a_mask_sub_sub_1_1 \| _put_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_size = put_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_nbit = ~put_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_eq = put_a_mask_sub_0_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T = put_a_mask_size & put_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc = put_a_mask_sub_0_1 \| _put_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_1 = put_a_mask_sub_0_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_1 = put_a_mask_size & put_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_1 = put_a_mask_sub_0_1 \| _put_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_2 = put_a_mask_sub_1_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_2 = put_a_mask_size & put_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_2 = put_a_mask_sub_1_1 \| _put_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_3 = put_a_mask_sub_1_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_3 = put_a_mask_size & put_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_3 = put_a_mask_sub_1_1 \| _put_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_4 = put_a_mask_sub_2_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_4 = put_a_mask_size & put_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_4 = put_a_mask_sub_2_1 \| _put_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_5 = put_a_mask_sub_2_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_5 = put_a_mask_size & put_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_5 = put_a_mask_sub_2_1 \| _put_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_6 = put_a_mask_sub_3_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_6 = put_a_mask_size & put_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_6 = put_a_mask_sub_3_1 \| _put_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_7 = put_a_mask_sub_3_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_7 = put_a_mask_size & put_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_7 = put_a_mask_sub_3_1 \| _put_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] put_a_mask_lo_lo = {put_a_mask_acc_1, put_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_lo_hi = {put_a_mask_acc_3, put_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_lo = {put_a_mask_lo_hi, put_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] put_a_mask_hi_lo = {put_a_mask_acc_5, put_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_hi_hi = {put_a_mask_acc_7, put_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_hi = {put_a_mask_hi_hi, put_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _put_a_mask_T = {put_a_mask_hi, put_a_mask_lo}; // @[Misc.scala:222:10] assign put_mask = _put_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _putpartial_legal_T_5 = {1'h0, _putpartial_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_6 = _putpartial_legal_T_5 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_7 = _putpartial_legal_T_6; // @[Parameters.scala:137:46] wire _putpartial_legal_T_8 = _putpartial_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _putpartial_legal_T_9 = _putpartial_legal_T_8; // @[Parameters.scala:684:54] wire _putpartial_legal_T_69 = _putpartial_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [40:0] _putpartial_legal_T_15 = {1'h0, _putpartial_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_16 = _putpartial_legal_T_15 & 41'h9A112000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_17 = _putpartial_legal_T_16; // @[Parameters.scala:137:46] wire _putpartial_legal_T_18 = _putpartial_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_20 = {1'h0, _putpartial_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_21 = _putpartial_legal_T_20 & 41'h9A103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_22 = _putpartial_legal_T_21; // @[Parameters.scala:137:46] wire _putpartial_legal_T_23 = _putpartial_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_25 = {1'h0, _putpartial_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_26 = _putpartial_legal_T_25 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_27 = _putpartial_legal_T_26; // @[Parameters.scala:137:46] wire _putpartial_legal_T_28 = _putpartial_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_30 = {1'h0, _putpartial_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_31 = _putpartial_legal_T_30 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_32 = _putpartial_legal_T_31; // @[Parameters.scala:137:46] wire _putpartial_legal_T_33 = _putpartial_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_35 = {1'h0, _putpartial_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_36 = _putpartial_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_37 = _putpartial_legal_T_36; // @[Parameters.scala:137:46] wire _putpartial_legal_T_38 = _putpartial_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_40 = {1'h0, _putpartial_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_41 = _putpartial_legal_T_40 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_42 = _putpartial_legal_T_41; // @[Parameters.scala:137:46] wire _putpartial_legal_T_43 = _putpartial_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_45 = {1'h0, _putpartial_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_46 = _putpartial_legal_T_45 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_47 = _putpartial_legal_T_46; // @[Parameters.scala:137:46] wire _putpartial_legal_T_48 = _putpartial_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_50 = {1'h0, _putpartial_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_51 = _putpartial_legal_T_50 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_52 = _putpartial_legal_T_51; // @[Parameters.scala:137:46] wire _putpartial_legal_T_53 = _putpartial_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _putpartial_legal_T_54 = _putpartial_legal_T_18 \| _putpartial_legal_T_23; // @[Parameters.scala:685:42] wire _putpartial_legal_T_55 = _putpartial_legal_T_54 \| _putpartial_legal_T_28; // @[Parameters.scala:685:42] wire _putpartial_legal_T_56 = _putpartial_legal_T_55 \| _putpartial_legal_T_33; // @[Parameters.scala:685:42] wire _putpartial_legal_T_57 = _putpartial_legal_T_56 \| _putpartial_legal_T_38; // @[Parameters.scala:685:42] wire _putpartial_legal_T_58 = _putpartial_legal_T_57 \| _putpartial_legal_T_43; // @[Parameters.scala:685:42] wire _putpartial_legal_T_59 = _putpartial_legal_T_58 \| _putpartial_legal_T_48; // @[Parameters.scala:685:42] wire _putpartial_legal_T_60 = _putpartial_legal_T_59 \| _putpartial_legal_T_53; // @[Parameters.scala:685:42] wire _putpartial_legal_T_61 = _putpartial_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire [40:0] _putpartial_legal_T_64 = {1'h0, _putpartial_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_65 = _putpartial_legal_T_64 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_66 = _putpartial_legal_T_65; // @[Parameters.scala:137:46] wire _putpartial_legal_T_67 = _putpartial_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _putpartial_legal_T_70 = _putpartial_legal_T_69 \| _putpartial_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire putpartial_legal = _putpartial_legal_T_70; // @[Parameters.scala:686:26] wire [7:0] putpartial_mask; // @[Edges.scala:500:17] assign putpartial_mask = a_mask[7:0]; // @[Edges.scala:500:17, :508:15] wire [40:0] _atomics_legal_T_5 = {1'h0, _atomics_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_6 = _atomics_legal_T_5 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_7 = _atomics_legal_T_6; // @[Parameters.scala:137:46] wire _atomics_legal_T_8 = _atomics_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_10 = {1'h0, _atomics_legal_T_9}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_11 = _atomics_legal_T_10 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_12 = _atomics_legal_T_11; // @[Parameters.scala:137:46] wire _atomics_legal_T_13 = _atomics_legal_T_12 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_15 = {1'h0, _atomics_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_16 = _atomics_legal_T_15 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_17 = _atomics_legal_T_16; // @[Parameters.scala:137:46] wire _atomics_legal_T_18 = _atomics_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_20 = {1'h0, _atomics_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_21 = _atomics_legal_T_20 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_22 = _atomics_legal_T_21; // @[Parameters.scala:137:46] wire _atomics_legal_T_23 = _atomics_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_25 = {1'h0, _atomics_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_26 = _atomics_legal_T_25 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_27 = _atomics_legal_T_26; // @[Parameters.scala:137:46] wire _atomics_legal_T_28 = _atomics_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_30 = {1'h0, _atomics_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_31 = _atomics_legal_T_30 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_32 = _atomics_legal_T_31; // @[Parameters.scala:137:46] wire _atomics_legal_T_33 = _atomics_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_35 = {1'h0, _atomics_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_36 = _atomics_legal_T_35 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_37 = _atomics_legal_T_36; // @[Parameters.scala:137:46] wire _atomics_legal_T_38 = _atomics_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_39 = _atomics_legal_T_8 \| _atomics_legal_T_13; // @[Parameters.scala:685:42] wire _atomics_legal_T_40 = _atomics_legal_T_39 \| _atomics_legal_T_18; // @[Parameters.scala:685:42] wire _atomics_legal_T_41 = _atomics_legal_T_40 \| _atomics_legal_T_23; // @[Parameters.scala:685:42] wire _atomics_legal_T_42 = _atomics_legal_T_41 \| _atomics_legal_T_28; // @[Parameters.scala:685:42] wire _atomics_legal_T_43 = _atomics_legal_T_42 \| _atomics_legal_T_33; // @[Parameters.scala:685:42] wire _atomics_legal_T_44 = _atomics_legal_T_43 \| _atomics_legal_T_38; // @[Parameters.scala:685:42] wire _atomics_legal_T_45 = _atomics_legal_T_44; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_53 = _atomics_legal_T_45; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_48 = {1'h0, _atomics_legal_T_47}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_49 = _atomics_legal_T_48 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_50 = _atomics_legal_T_49; // @[Parameters.scala:137:46] wire _atomics_legal_T_51 = _atomics_legal_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal = _atomics_legal_T_53; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount = _atomics_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_1 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_2 = _atomics_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH = {_atomics_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size = atomics_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2 = atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit = ~atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2 = atomics_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1 = atomics_a_mask_sub_sub_sub_0_1 \| _atomics_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_1 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1 = atomics_a_mask_sub_sub_sub_0_1 \| _atomics_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size = atomics_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit = ~atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T = atomics_a_mask_sub_size & atomics_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1 = atomics_a_mask_sub_sub_0_1 \| _atomics_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_1 = atomics_a_mask_sub_size & atomics_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1 = atomics_a_mask_sub_sub_0_1 \| _atomics_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_2 = atomics_a_mask_sub_size & atomics_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1 = atomics_a_mask_sub_sub_1_1 \| _atomics_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_3 = atomics_a_mask_sub_size & atomics_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1 = atomics_a_mask_sub_sub_1_1 \| _atomics_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size = atomics_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit = ~atomics_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq = atomics_a_mask_sub_0_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T = atomics_a_mask_size & atomics_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc = atomics_a_mask_sub_0_1 \| _atomics_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_1 = atomics_a_mask_sub_0_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_1 = atomics_a_mask_size & atomics_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_1 = atomics_a_mask_sub_0_1 \| _atomics_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_2 = atomics_a_mask_sub_1_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_2 = atomics_a_mask_size & atomics_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_2 = atomics_a_mask_sub_1_1 \| _atomics_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_3 = atomics_a_mask_sub_1_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_3 = atomics_a_mask_size & atomics_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_3 = atomics_a_mask_sub_1_1 \| _atomics_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_4 = atomics_a_mask_sub_2_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_4 = atomics_a_mask_size & atomics_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_4 = atomics_a_mask_sub_2_1 \| _atomics_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_5 = atomics_a_mask_sub_2_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_5 = atomics_a_mask_size & atomics_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_5 = atomics_a_mask_sub_2_1 \| _atomics_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_6 = atomics_a_mask_sub_3_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_6 = atomics_a_mask_size & atomics_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_6 = atomics_a_mask_sub_3_1 \| _atomics_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_7 = atomics_a_mask_sub_3_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_7 = atomics_a_mask_size & atomics_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_7 = atomics_a_mask_sub_3_1 \| _atomics_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo = {atomics_a_mask_acc_1, atomics_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi = {atomics_a_mask_acc_3, atomics_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo = {atomics_a_mask_lo_hi, atomics_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo = {atomics_a_mask_acc_5, atomics_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi = {atomics_a_mask_acc_7, atomics_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi = {atomics_a_mask_hi_hi, atomics_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _atomics_a_mask_T = {atomics_a_mask_hi, atomics_a_mask_lo}; // @[Misc.scala:222:10] assign atomics_a_mask = _atomics_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_59 = {1'h0, _atomics_legal_T_58}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_60 = _atomics_legal_T_59 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_61 = _atomics_legal_T_60; // @[Parameters.scala:137:46] wire _atomics_legal_T_62 = _atomics_legal_T_61 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_64 = {1'h0, _atomics_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_65 = _atomics_legal_T_64 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_66 = _atomics_legal_T_65; // @[Parameters.scala:137:46] wire _atomics_legal_T_67 = _atomics_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_69 = {1'h0, _atomics_legal_T_68}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_70 = _atomics_legal_T_69 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_71 = _atomics_legal_T_70; // @[Parameters.scala:137:46] wire _atomics_legal_T_72 = _atomics_legal_T_71 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_74 = {1'h0, _atomics_legal_T_73}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_75 = _atomics_legal_T_74 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_76 = _atomics_legal_T_75; // @[Parameters.scala:137:46] wire _atomics_legal_T_77 = _atomics_legal_T_76 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_79 = {1'h0, _atomics_legal_T_78}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_80 = _atomics_legal_T_79 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_81 = _atomics_legal_T_80; // @[Parameters.scala:137:46] wire _atomics_legal_T_82 = _atomics_legal_T_81 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_84 = {1'h0, _atomics_legal_T_83}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_85 = _atomics_legal_T_84 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_86 = _atomics_legal_T_85; // @[Parameters.scala:137:46] wire _atomics_legal_T_87 = _atomics_legal_T_86 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_89 = {1'h0, _atomics_legal_T_88}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_90 = _atomics_legal_T_89 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_91 = _atomics_legal_T_90; // @[Parameters.scala:137:46] wire _atomics_legal_T_92 = _atomics_legal_T_91 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_93 = _atomics_legal_T_62 \| _atomics_legal_T_67; // @[Parameters.scala:685:42] wire _atomics_legal_T_94 = _atomics_legal_T_93 \| _atomics_legal_T_72; // @[Parameters.scala:685:42] wire _atomics_legal_T_95 = _atomics_legal_T_94 \| _atomics_legal_T_77; // @[Parameters.scala:685:42] wire _atomics_legal_T_96 = _atomics_legal_T_95 \| _atomics_legal_T_82; // @[Parameters.scala:685:42] wire _atomics_legal_T_97 = _atomics_legal_T_96 \| _atomics_legal_T_87; // @[Parameters.scala:685:42] wire _atomics_legal_T_98 = _atomics_legal_T_97 \| _atomics_legal_T_92; // @[Parameters.scala:685:42] wire _atomics_legal_T_99 = _atomics_legal_T_98; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_107 = _atomics_legal_T_99; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_102 = {1'h0, _atomics_legal_T_101}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_103 = _atomics_legal_T_102 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_104 = _atomics_legal_T_103; // @[Parameters.scala:137:46] wire _atomics_legal_T_105 = _atomics_legal_T_104 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_1 = _atomics_legal_T_107; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [7:0] atomics_a_1_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_1 = _atomics_a_mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_4 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_5 = _atomics_a_mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_1 = {_atomics_a_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_1 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_1 = atomics_a_mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_1 = atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_1 = ~atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_1 = atomics_a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_2 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 \| _atomics_a_mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_3 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 \| _atomics_a_mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_1 = atomics_a_mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_1 = ~atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_4 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_1 = atomics_a_mask_sub_sub_0_1_1 \| _atomics_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_5 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_1 = atomics_a_mask_sub_sub_0_1_1 \| _atomics_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_6 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_1 = atomics_a_mask_sub_sub_1_1_1 \| _atomics_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_7 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_1 = atomics_a_mask_sub_sub_1_1_1 \| _atomics_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_1 = atomics_a_mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_1 = ~atomics_a_mask_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_8 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_8 = atomics_a_mask_size_1 & atomics_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_8 = atomics_a_mask_sub_0_1_1 \| _atomics_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_9 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_9 = atomics_a_mask_size_1 & atomics_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_9 = atomics_a_mask_sub_0_1_1 \| _atomics_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_10 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_10 = atomics_a_mask_size_1 & atomics_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_10 = atomics_a_mask_sub_1_1_1 \| _atomics_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_11 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_11 = atomics_a_mask_size_1 & atomics_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_11 = atomics_a_mask_sub_1_1_1 \| _atomics_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_12 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_12 = atomics_a_mask_size_1 & atomics_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_12 = atomics_a_mask_sub_2_1_1 \| _atomics_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_13 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_13 = atomics_a_mask_size_1 & atomics_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_13 = atomics_a_mask_sub_2_1_1 \| _atomics_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_14 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_14 = atomics_a_mask_size_1 & atomics_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_14 = atomics_a_mask_sub_3_1_1 \| _atomics_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_15 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_15 = atomics_a_mask_size_1 & atomics_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_15 = atomics_a_mask_sub_3_1_1 \| _atomics_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_1 = {atomics_a_mask_acc_9, atomics_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_1 = {atomics_a_mask_acc_11, atomics_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_1 = {atomics_a_mask_lo_hi_1, atomics_a_mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_1 = {atomics_a_mask_acc_13, atomics_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_1 = {atomics_a_mask_acc_15, atomics_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_1 = {atomics_a_mask_hi_hi_1, atomics_a_mask_hi_lo_1}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_1 = {atomics_a_mask_hi_1, atomics_a_mask_lo_1}; // @[Misc.scala:222:10] assign atomics_a_1_mask = _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_113 = {1'h0, _atomics_legal_T_112}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_114 = _atomics_legal_T_113 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_115 = _atomics_legal_T_114; // @[Parameters.scala:137:46] wire _atomics_legal_T_116 = _atomics_legal_T_115 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_118 = {1'h0, _atomics_legal_T_117}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_119 = _atomics_legal_T_118 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_120 = _atomics_legal_T_119; // @[Parameters.scala:137:46] wire _atomics_legal_T_121 = _atomics_legal_T_120 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_123 = {1'h0, _atomics_legal_T_122}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_124 = _atomics_legal_T_123 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_125 = _atomics_legal_T_124; // @[Parameters.scala:137:46] wire _atomics_legal_T_126 = _atomics_legal_T_125 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_128 = {1'h0, _atomics_legal_T_127}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_129 = _atomics_legal_T_128 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_130 = _atomics_legal_T_129; // @[Parameters.scala:137:46] wire _atomics_legal_T_131 = _atomics_legal_T_130 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_133 = {1'h0, _atomics_legal_T_132}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_134 = _atomics_legal_T_133 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_135 = _atomics_legal_T_134; // @[Parameters.scala:137:46] wire _atomics_legal_T_136 = _atomics_legal_T_135 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_138 = {1'h0, _atomics_legal_T_137}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_139 = _atomics_legal_T_138 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_140 = _atomics_legal_T_139; // @[Parameters.scala:137:46] wire _atomics_legal_T_141 = _atomics_legal_T_140 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_143 = {1'h0, _atomics_legal_T_142}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_144 = _atomics_legal_T_143 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_145 = _atomics_legal_T_144; // @[Parameters.scala:137:46] wire _atomics_legal_T_146 = _atomics_legal_T_145 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_147 = _atomics_legal_T_116 \| _atomics_legal_T_121; // @[Parameters.scala:685:42] wire _atomics_legal_T_148 = _atomics_legal_T_147 \| _atomics_legal_T_126; // @[Parameters.scala:685:42] wire _atomics_legal_T_149 = _atomics_legal_T_148 \| _atomics_legal_T_131; // @[Parameters.scala:685:42] wire _atomics_legal_T_150 = _atomics_legal_T_149 \| _atomics_legal_T_136; // @[Parameters.scala:685:42] wire _atomics_legal_T_151 = _atomics_legal_T_150 \| _atomics_legal_T_141; // @[Parameters.scala:685:42] wire _atomics_legal_T_152 = _atomics_legal_T_151 \| _atomics_legal_T_146; // @[Parameters.scala:685:42] wire _atomics_legal_T_153 = _atomics_legal_T_152; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_161 = _atomics_legal_T_153; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_156 = {1'h0, _atomics_legal_T_155}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_157 = _atomics_legal_T_156 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_158 = _atomics_legal_T_157; // @[Parameters.scala:137:46] wire _atomics_legal_T_159 = _atomics_legal_T_158 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_2 = _atomics_legal_T_161; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [7:0] atomics_a_2_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_2 = _atomics_a_mask_sizeOH_T_6[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_7 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_2; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_8 = _atomics_a_mask_sizeOH_T_7[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_2 = {_atomics_a_mask_sizeOH_T_8[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_2 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_2 = atomics_a_mask_sizeOH_2[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_2 = atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_2 = ~atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_2 = atomics_a_mask_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_4 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 \| _atomics_a_mask_sub_sub_acc_T_4; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_5 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 \| _atomics_a_mask_sub_sub_acc_T_5; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_2 = atomics_a_mask_sizeOH_2[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_2 = ~atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_8 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_2 = atomics_a_mask_sub_sub_0_1_2 \| _atomics_a_mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_9 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_2 = atomics_a_mask_sub_sub_0_1_2 \| _atomics_a_mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_10 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_2_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_2 = atomics_a_mask_sub_sub_1_1_2 \| _atomics_a_mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_11 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_3_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_2 = atomics_a_mask_sub_sub_1_1_2 \| _atomics_a_mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_2 = atomics_a_mask_sizeOH_2[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_2 = ~atomics_a_mask_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_16 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_16 = atomics_a_mask_size_2 & atomics_a_mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_16 = atomics_a_mask_sub_0_1_2 \| _atomics_a_mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_17 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_17 = atomics_a_mask_size_2 & atomics_a_mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_17 = atomics_a_mask_sub_0_1_2 \| _atomics_a_mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_18 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_18 = atomics_a_mask_size_2 & atomics_a_mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_18 = atomics_a_mask_sub_1_1_2 \| _atomics_a_mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_19 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_19 = atomics_a_mask_size_2 & atomics_a_mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_19 = atomics_a_mask_sub_1_1_2 \| _atomics_a_mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_20 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_20 = atomics_a_mask_size_2 & atomics_a_mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_20 = atomics_a_mask_sub_2_1_2 \| _atomics_a_mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_21 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_21 = atomics_a_mask_size_2 & atomics_a_mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_21 = atomics_a_mask_sub_2_1_2 \| _atomics_a_mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_22 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_22 = atomics_a_mask_size_2 & atomics_a_mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_22 = atomics_a_mask_sub_3_1_2 \| _atomics_a_mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_23 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_23 = atomics_a_mask_size_2 & atomics_a_mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_23 = atomics_a_mask_sub_3_1_2 \| _atomics_a_mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_2 = {atomics_a_mask_acc_17, atomics_a_mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_2 = {atomics_a_mask_acc_19, atomics_a_mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_2 = {atomics_a_mask_lo_hi_2, atomics_a_mask_lo_lo_2}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_2 = {atomics_a_mask_acc_21, atomics_a_mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_2 = {atomics_a_mask_acc_23, atomics_a_mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_2 = {atomics_a_mask_hi_hi_2, atomics_a_mask_hi_lo_2}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_2 = {atomics_a_mask_hi_2, atomics_a_mask_lo_2}; // @[Misc.scala:222:10] assign atomics_a_2_mask = _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_167 = {1'h0, _atomics_legal_T_166}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_168 = _atomics_legal_T_167 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_169 = _atomics_legal_T_168; // @[Parameters.scala:137:46] wire _atomics_legal_T_170 = _atomics_legal_T_169 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_172 = {1'h0, _atomics_legal_T_171}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_173 = _atomics_legal_T_172 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_174 = _atomics_legal_T_173; // @[Parameters.scala:137:46] wire _atomics_legal_T_175 = _atomics_legal_T_174 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_177 = {1'h0, _atomics_legal_T_176}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_178 = _atomics_legal_T_177 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_179 = _atomics_legal_T_178; // @[Parameters.scala:137:46] wire _atomics_legal_T_180 = _atomics_legal_T_179 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_182 = {1'h0, _atomics_legal_T_181}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_183 = _atomics_legal_T_182 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_184 = _atomics_legal_T_183; // @[Parameters.scala:137:46] wire _atomics_legal_T_185 = _atomics_legal_T_184 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_187 = {1'h0, _atomics_legal_T_186}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_188 = _atomics_legal_T_187 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_189 = _atomics_legal_T_188; // @[Parameters.scala:137:46] wire _atomics_legal_T_190 = _atomics_legal_T_189 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_192 = {1'h0, _atomics_legal_T_191}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_193 = _atomics_legal_T_192 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_194 = _atomics_legal_T_193; // @[Parameters.scala:137:46] wire _atomics_legal_T_195 = _atomics_legal_T_194 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_197 = {1'h0, _atomics_legal_T_196}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_198 = _atomics_legal_T_197 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_199 = _atomics_legal_T_198; // @[Parameters.scala:137:46] wire _atomics_legal_T_200 = _atomics_legal_T_199 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_201 = _atomics_legal_T_170 \| _atomics_legal_T_175; // @[Parameters.scala:685:42] wire _atomics_legal_T_202 = _atomics_legal_T_201 \| _atomics_legal_T_180; // @[Parameters.scala:685:42] wire _atomics_legal_T_203 = _atomics_legal_T_202 \| _atomics_legal_T_185; // @[Parameters.scala:685:42] wire _atomics_legal_T_204 = _atomics_legal_T_203 \| _atomics_legal_T_190; // @[Parameters.scala:685:42] wire _atomics_legal_T_205 = _atomics_legal_T_204 \| _atomics_legal_T_195; // @[Parameters.scala:685:42] wire _atomics_legal_T_206 = _atomics_legal_T_205 \| _atomics_legal_T_200; // @[Parameters.scala:685:42] wire _atomics_legal_T_207 = _atomics_legal_T_206; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_215 = _atomics_legal_T_207; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_210 = {1'h0, _atomics_legal_T_209}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_211 = _atomics_legal_T_210 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_212 = _atomics_legal_T_211; // @[Parameters.scala:137:46] wire _atomics_legal_T_213 = _atomics_legal_T_212 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_3 = _atomics_legal_T_215; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [7:0] atomics_a_3_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_3 = _atomics_a_mask_sizeOH_T_9[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_10 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_3; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_11 = _atomics_a_mask_sizeOH_T_10[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_3 = {_atomics_a_mask_sizeOH_T_11[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_3 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_3 = atomics_a_mask_sizeOH_3[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_3 = atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_3 = ~atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_3 = atomics_a_mask_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_6 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 \| _atomics_a_mask_sub_sub_acc_T_6; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_7 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 \| _atomics_a_mask_sub_sub_acc_T_7; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_3 = atomics_a_mask_sizeOH_3[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_3 = ~atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_12 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_3 = atomics_a_mask_sub_sub_0_1_3 \| _atomics_a_mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_13 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_3 = atomics_a_mask_sub_sub_0_1_3 \| _atomics_a_mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_14 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_2_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_3 = atomics_a_mask_sub_sub_1_1_3 \| _atomics_a_mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_15 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_3_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_3 = atomics_a_mask_sub_sub_1_1_3 \| _atomics_a_mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_3 = atomics_a_mask_sizeOH_3[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_3 = ~atomics_a_mask_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_24 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_24 = atomics_a_mask_size_3 & atomics_a_mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_24 = atomics_a_mask_sub_0_1_3 \| _atomics_a_mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_25 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_25 = atomics_a_mask_size_3 & atomics_a_mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_25 = atomics_a_mask_sub_0_1_3 \| _atomics_a_mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_26 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_26 = atomics_a_mask_size_3 & atomics_a_mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_26 = atomics_a_mask_sub_1_1_3 \| _atomics_a_mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_27 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_27 = atomics_a_mask_size_3 & atomics_a_mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_27 = atomics_a_mask_sub_1_1_3 \| _atomics_a_mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_28 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_28 = atomics_a_mask_size_3 & atomics_a_mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_28 = atomics_a_mask_sub_2_1_3 \| _atomics_a_mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_29 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_29 = atomics_a_mask_size_3 & atomics_a_mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_29 = atomics_a_mask_sub_2_1_3 \| _atomics_a_mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_30 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_30 = atomics_a_mask_size_3 & atomics_a_mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_30 = atomics_a_mask_sub_3_1_3 \| _atomics_a_mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_31 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_31 = atomics_a_mask_size_3 & atomics_a_mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_31 = atomics_a_mask_sub_3_1_3 \| _atomics_a_mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_3 = {atomics_a_mask_acc_25, atomics_a_mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_3 = {atomics_a_mask_acc_27, atomics_a_mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_3 = {atomics_a_mask_lo_hi_3, atomics_a_mask_lo_lo_3}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_3 = {atomics_a_mask_acc_29, atomics_a_mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_3 = {atomics_a_mask_acc_31, atomics_a_mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_3 = {atomics_a_mask_hi_hi_3, atomics_a_mask_hi_lo_3}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_3 = {atomics_a_mask_hi_3, atomics_a_mask_lo_3}; // @[Misc.scala:222:10] assign atomics_a_3_mask = _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_221 = {1'h0, _atomics_legal_T_220}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_222 = _atomics_legal_T_221 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_223 = _atomics_legal_T_222; // @[Parameters.scala:137:46] wire _atomics_legal_T_224 = _atomics_legal_T_223 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_226 = {1'h0, _atomics_legal_T_225}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_227 = _atomics_legal_T_226 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_228 = _atomics_legal_T_227; // @[Parameters.scala:137:46] wire _atomics_legal_T_229 = _atomics_legal_T_228 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_231 = {1'h0, _atomics_legal_T_230}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_232 = _atomics_legal_T_231 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_233 = _atomics_legal_T_232; // @[Parameters.scala:137:46] wire _atomics_legal_T_234 = _atomics_legal_T_233 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_236 = {1'h0, _atomics_legal_T_235}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_237 = _atomics_legal_T_236 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_238 = _atomics_legal_T_237; // @[Parameters.scala:137:46] wire _atomics_legal_T_239 = _atomics_legal_T_238 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_241 = {1'h0, _atomics_legal_T_240}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_242 = _atomics_legal_T_241 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_243 = _atomics_legal_T_242; // @[Parameters.scala:137:46] wire _atomics_legal_T_244 = _atomics_legal_T_243 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_246 = {1'h0, _atomics_legal_T_245}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_247 = _atomics_legal_T_246 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_248 = _atomics_legal_T_247; // @[Parameters.scala:137:46] wire _atomics_legal_T_249 = _atomics_legal_T_248 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_251 = {1'h0, _atomics_legal_T_250}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_252 = _atomics_legal_T_251 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_253 = _atomics_legal_T_252; // @[Parameters.scala:137:46] wire _atomics_legal_T_254 = _atomics_legal_T_253 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_255 = _atomics_legal_T_224 \| _atomics_legal_T_229; // @[Parameters.scala:685:42] wire _atomics_legal_T_256 = _atomics_legal_T_255 \| _atomics_legal_T_234; // @[Parameters.scala:685:42] wire _atomics_legal_T_257 = _atomics_legal_T_256 \| _atomics_legal_T_239; // @[Parameters.scala:685:42] wire _atomics_legal_T_258 = _atomics_legal_T_257 \| _atomics_legal_T_244; // @[Parameters.scala:685:42] wire _atomics_legal_T_259 = _atomics_legal_T_258 \| _atomics_legal_T_249; // @[Parameters.scala:685:42] wire _atomics_legal_T_260 = _atomics_legal_T_259 \| _atomics_legal_T_254; // @[Parameters.scala:685:42] wire _atomics_legal_T_261 = _atomics_legal_T_260; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_269 = _atomics_legal_T_261; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_264 = {1'h0, _atomics_legal_T_263}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_265 = _atomics_legal_T_264 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_266 = _atomics_legal_T_265; // @[Parameters.scala:137:46] wire _atomics_legal_T_267 = _atomics_legal_T_266 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_4 = _atomics_legal_T_269; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [7:0] atomics_a_4_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_4 = _atomics_a_mask_sizeOH_T_12[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_13 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_4; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_14 = _atomics_a_mask_sizeOH_T_13[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_4 = {_atomics_a_mask_sizeOH_T_14[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_4 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_4 = atomics_a_mask_sizeOH_4[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_4 = atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_4 = ~atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_4 = atomics_a_mask_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_8 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 \| _atomics_a_mask_sub_sub_acc_T_8; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_9 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 \| _atomics_a_mask_sub_sub_acc_T_9; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_4 = atomics_a_mask_sizeOH_4[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_4 = ~atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_16 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_4 = atomics_a_mask_sub_sub_0_1_4 \| _atomics_a_mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_17 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_4 = atomics_a_mask_sub_sub_0_1_4 \| _atomics_a_mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_18 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_2_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_4 = atomics_a_mask_sub_sub_1_1_4 \| _atomics_a_mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_19 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_3_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_4 = atomics_a_mask_sub_sub_1_1_4 \| _atomics_a_mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_4 = atomics_a_mask_sizeOH_4[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_4 = ~atomics_a_mask_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_32 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_32 = atomics_a_mask_size_4 & atomics_a_mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_32 = atomics_a_mask_sub_0_1_4 \| _atomics_a_mask_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_33 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_33 = atomics_a_mask_size_4 & atomics_a_mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_33 = atomics_a_mask_sub_0_1_4 \| _atomics_a_mask_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_34 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_34 = atomics_a_mask_size_4 & atomics_a_mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_34 = atomics_a_mask_sub_1_1_4 \| _atomics_a_mask_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_35 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_35 = atomics_a_mask_size_4 & atomics_a_mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_35 = atomics_a_mask_sub_1_1_4 \| _atomics_a_mask_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_36 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_36 = atomics_a_mask_size_4 & atomics_a_mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_36 = atomics_a_mask_sub_2_1_4 \| _atomics_a_mask_acc_T_36; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_37 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_37 = atomics_a_mask_size_4 & atomics_a_mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_37 = atomics_a_mask_sub_2_1_4 \| _atomics_a_mask_acc_T_37; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_38 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_38 = atomics_a_mask_size_4 & atomics_a_mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_38 = atomics_a_mask_sub_3_1_4 \| _atomics_a_mask_acc_T_38; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_39 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_39 = atomics_a_mask_size_4 & atomics_a_mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_39 = atomics_a_mask_sub_3_1_4 \| _atomics_a_mask_acc_T_39; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_4 = {atomics_a_mask_acc_33, atomics_a_mask_acc_32}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_4 = {atomics_a_mask_acc_35, atomics_a_mask_acc_34}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_4 = {atomics_a_mask_lo_hi_4, atomics_a_mask_lo_lo_4}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_4 = {atomics_a_mask_acc_37, atomics_a_mask_acc_36}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_4 = {atomics_a_mask_acc_39, atomics_a_mask_acc_38}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_4 = {atomics_a_mask_hi_hi_4, atomics_a_mask_hi_lo_4}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_4 = {atomics_a_mask_hi_4, atomics_a_mask_lo_4}; // @[Misc.scala:222:10] assign atomics_a_4_mask = _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_275 = {1'h0, _atomics_legal_T_274}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_276 = _atomics_legal_T_275 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_277 = _atomics_legal_T_276; // @[Parameters.scala:137:46] wire _atomics_legal_T_278 = _atomics_legal_T_277 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_280 = {1'h0, _atomics_legal_T_279}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_281 = _atomics_legal_T_280 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_282 = _atomics_legal_T_281; // @[Parameters.scala:137:46] wire _atomics_legal_T_283 = _atomics_legal_T_282 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_285 = {1'h0, _atomics_legal_T_284}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_286 = _atomics_legal_T_285 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_287 = _atomics_legal_T_286; // @[Parameters.scala:137:46] wire _atomics_legal_T_288 = _atomics_legal_T_287 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_290 = {1'h0, _atomics_legal_T_289}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_291 = _atomics_legal_T_290 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_292 = _atomics_legal_T_291; // @[Parameters.scala:137:46] wire _atomics_legal_T_293 = _atomics_legal_T_292 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_295 = {1'h0, _atomics_legal_T_294}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_296 = _atomics_legal_T_295 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_297 = _atomics_legal_T_296; // @[Parameters.scala:137:46] wire _atomics_legal_T_298 = _atomics_legal_T_297 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_300 = {1'h0, _atomics_legal_T_299}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_301 = _atomics_legal_T_300 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_302 = _atomics_legal_T_301; // @[Parameters.scala:137:46] wire _atomics_legal_T_303 = _atomics_legal_T_302 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_305 = {1'h0, _atomics_legal_T_304}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_306 = _atomics_legal_T_305 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_307 = _atomics_legal_T_306; // @[Parameters.scala:137:46] wire _atomics_legal_T_308 = _atomics_legal_T_307 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_309 = _atomics_legal_T_278 \| _atomics_legal_T_283; // @[Parameters.scala:685:42] wire _atomics_legal_T_310 = _atomics_legal_T_309 \| _atomics_legal_T_288; // @[Parameters.scala:685:42] wire _atomics_legal_T_311 = _atomics_legal_T_310 \| _atomics_legal_T_293; // @[Parameters.scala:685:42] wire _atomics_legal_T_312 = _atomics_legal_T_311 \| _atomics_legal_T_298; // @[Parameters.scala:685:42] wire _atomics_legal_T_313 = _atomics_legal_T_312 \| _atomics_legal_T_303; // @[Parameters.scala:685:42] wire _atomics_legal_T_314 = _atomics_legal_T_313 \| _atomics_legal_T_308; // @[Parameters.scala:685:42] wire _atomics_legal_T_315 = _atomics_legal_T_314; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_323 = _atomics_legal_T_315; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_318 = {1'h0, _atomics_legal_T_317}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_319 = _atomics_legal_T_318 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_320 = _atomics_legal_T_319; // @[Parameters.scala:137:46] wire _atomics_legal_T_321 = _atomics_legal_T_320 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_5 = _atomics_legal_T_323; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [7:0] atomics_a_5_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_5 = _atomics_a_mask_sizeOH_T_15[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_16 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_5; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_17 = _atomics_a_mask_sizeOH_T_16[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_5 = {_atomics_a_mask_sizeOH_T_17[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_5 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_5 = atomics_a_mask_sizeOH_5[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_5 = atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_5 = ~atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_5 = atomics_a_mask_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_10 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 \| _atomics_a_mask_sub_sub_acc_T_10; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_11 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 \| _atomics_a_mask_sub_sub_acc_T_11; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_5 = atomics_a_mask_sizeOH_5[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_5 = ~atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_20 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_5 = atomics_a_mask_sub_sub_0_1_5 \| _atomics_a_mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_21 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_5 = atomics_a_mask_sub_sub_0_1_5 \| _atomics_a_mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_22 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_2_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_5 = atomics_a_mask_sub_sub_1_1_5 \| _atomics_a_mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_23 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_3_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_5 = atomics_a_mask_sub_sub_1_1_5 \| _atomics_a_mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_5 = atomics_a_mask_sizeOH_5[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_5 = ~atomics_a_mask_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_40 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_40 = atomics_a_mask_size_5 & atomics_a_mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_40 = atomics_a_mask_sub_0_1_5 \| _atomics_a_mask_acc_T_40; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_41 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_41 = atomics_a_mask_size_5 & atomics_a_mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_41 = atomics_a_mask_sub_0_1_5 \| _atomics_a_mask_acc_T_41; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_42 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_42 = atomics_a_mask_size_5 & atomics_a_mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_42 = atomics_a_mask_sub_1_1_5 \| _atomics_a_mask_acc_T_42; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_43 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_43 = atomics_a_mask_size_5 & atomics_a_mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_43 = atomics_a_mask_sub_1_1_5 \| _atomics_a_mask_acc_T_43; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_44 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_44 = atomics_a_mask_size_5 & atomics_a_mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_44 = atomics_a_mask_sub_2_1_5 \| _atomics_a_mask_acc_T_44; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_45 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_45 = atomics_a_mask_size_5 & atomics_a_mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_45 = atomics_a_mask_sub_2_1_5 \| _atomics_a_mask_acc_T_45; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_46 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_46 = atomics_a_mask_size_5 & atomics_a_mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_46 = atomics_a_mask_sub_3_1_5 \| _atomics_a_mask_acc_T_46; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_47 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_47 = atomics_a_mask_size_5 & atomics_a_mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_47 = atomics_a_mask_sub_3_1_5 \| _atomics_a_mask_acc_T_47; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_5 = {atomics_a_mask_acc_41, atomics_a_mask_acc_40}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_5 = {atomics_a_mask_acc_43, atomics_a_mask_acc_42}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_5 = {atomics_a_mask_lo_hi_5, atomics_a_mask_lo_lo_5}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_5 = {atomics_a_mask_acc_45, atomics_a_mask_acc_44}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_5 = {atomics_a_mask_acc_47, atomics_a_mask_acc_46}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_5 = {atomics_a_mask_hi_hi_5, atomics_a_mask_hi_lo_5}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_5 = {atomics_a_mask_hi_5, atomics_a_mask_lo_5}; // @[Misc.scala:222:10] assign atomics_a_5_mask = _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_329 = {1'h0, _atomics_legal_T_328}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_330 = _atomics_legal_T_329 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_331 = _atomics_legal_T_330; // @[Parameters.scala:137:46] wire _atomics_legal_T_332 = _atomics_legal_T_331 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_334 = {1'h0, _atomics_legal_T_333}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_335 = _atomics_legal_T_334 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_336 = _atomics_legal_T_335; // @[Parameters.scala:137:46] wire _atomics_legal_T_337 = _atomics_legal_T_336 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_339 = {1'h0, _atomics_legal_T_338}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_340 = _atomics_legal_T_339 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_341 = _atomics_legal_T_340; // @[Parameters.scala:137:46] wire _atomics_legal_T_342 = _atomics_legal_T_341 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_344 = {1'h0, _atomics_legal_T_343}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_345 = _atomics_legal_T_344 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_346 = _atomics_legal_T_345; // @[Parameters.scala:137:46] wire _atomics_legal_T_347 = _atomics_legal_T_346 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_349 = {1'h0, _atomics_legal_T_348}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_350 = _atomics_legal_T_349 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_351 = _atomics_legal_T_350; // @[Parameters.scala:137:46] wire _atomics_legal_T_352 = _atomics_legal_T_351 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_354 = {1'h0, _atomics_legal_T_353}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_355 = _atomics_legal_T_354 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_356 = _atomics_legal_T_355; // @[Parameters.scala:137:46] wire _atomics_legal_T_357 = _atomics_legal_T_356 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_359 = {1'h0, _atomics_legal_T_358}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_360 = _atomics_legal_T_359 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_361 = _atomics_legal_T_360; // @[Parameters.scala:137:46] wire _atomics_legal_T_362 = _atomics_legal_T_361 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_363 = _atomics_legal_T_332 \| _atomics_legal_T_337; // @[Parameters.scala:685:42] wire _atomics_legal_T_364 = _atomics_legal_T_363 \| _atomics_legal_T_342; // @[Parameters.scala:685:42] wire _atomics_legal_T_365 = _atomics_legal_T_364 \| _atomics_legal_T_347; // @[Parameters.scala:685:42] wire _atomics_legal_T_366 = _atomics_legal_T_365 \| _atomics_legal_T_352; // @[Parameters.scala:685:42] wire _atomics_legal_T_367 = _atomics_legal_T_366 \| _atomics_legal_T_357; // @[Parameters.scala:685:42] wire _atomics_legal_T_368 = _atomics_legal_T_367 \| _atomics_legal_T_362; // @[Parameters.scala:685:42] wire _atomics_legal_T_369 = _atomics_legal_T_368; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_377 = _atomics_legal_T_369; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_372 = {1'h0, _atomics_legal_T_371}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_373 = _atomics_legal_T_372 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_374 = _atomics_legal_T_373; // @[Parameters.scala:137:46] wire _atomics_legal_T_375 = _atomics_legal_T_374 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_6 = _atomics_legal_T_377; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [7:0] atomics_a_6_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_6 = _atomics_a_mask_sizeOH_T_18[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_19 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_6; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_20 = _atomics_a_mask_sizeOH_T_19[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_6 = {_atomics_a_mask_sizeOH_T_20[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_6 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_6 = atomics_a_mask_sizeOH_6[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_6 = atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_6 = ~atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_6 = atomics_a_mask_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_12 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 \| _atomics_a_mask_sub_sub_acc_T_12; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_13 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 \| _atomics_a_mask_sub_sub_acc_T_13; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_6 = atomics_a_mask_sizeOH_6[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_6 = ~atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_24 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_6 = atomics_a_mask_sub_sub_0_1_6 \| _atomics_a_mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_25 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_6 = atomics_a_mask_sub_sub_0_1_6 \| _atomics_a_mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_26 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_2_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_6 = atomics_a_mask_sub_sub_1_1_6 \| _atomics_a_mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_27 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_3_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_6 = atomics_a_mask_sub_sub_1_1_6 \| _atomics_a_mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_6 = atomics_a_mask_sizeOH_6[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_6 = ~atomics_a_mask_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_48 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_48 = atomics_a_mask_size_6 & atomics_a_mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_48 = atomics_a_mask_sub_0_1_6 \| _atomics_a_mask_acc_T_48; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_49 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_49 = atomics_a_mask_size_6 & atomics_a_mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_49 = atomics_a_mask_sub_0_1_6 \| _atomics_a_mask_acc_T_49; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_50 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_50 = atomics_a_mask_size_6 & atomics_a_mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_50 = atomics_a_mask_sub_1_1_6 \| _atomics_a_mask_acc_T_50; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_51 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_51 = atomics_a_mask_size_6 & atomics_a_mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_51 = atomics_a_mask_sub_1_1_6 \| _atomics_a_mask_acc_T_51; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_52 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_52 = atomics_a_mask_size_6 & atomics_a_mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_52 = atomics_a_mask_sub_2_1_6 \| _atomics_a_mask_acc_T_52; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_53 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_53 = atomics_a_mask_size_6 & atomics_a_mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_53 = atomics_a_mask_sub_2_1_6 \| _atomics_a_mask_acc_T_53; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_54 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_54 = atomics_a_mask_size_6 & atomics_a_mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_54 = atomics_a_mask_sub_3_1_6 \| _atomics_a_mask_acc_T_54; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_55 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_55 = atomics_a_mask_size_6 & atomics_a_mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_55 = atomics_a_mask_sub_3_1_6 \| _atomics_a_mask_acc_T_55; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_6 = {atomics_a_mask_acc_49, atomics_a_mask_acc_48}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_6 = {atomics_a_mask_acc_51, atomics_a_mask_acc_50}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_6 = {atomics_a_mask_lo_hi_6, atomics_a_mask_lo_lo_6}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_6 = {atomics_a_mask_acc_53, atomics_a_mask_acc_52}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_6 = {atomics_a_mask_acc_55, atomics_a_mask_acc_54}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_6 = {atomics_a_mask_hi_hi_6, atomics_a_mask_hi_lo_6}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_6 = {atomics_a_mask_hi_6, atomics_a_mask_lo_6}; // @[Misc.scala:222:10] assign atomics_a_6_mask = _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_383 = {1'h0, _atomics_legal_T_382}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_384 = _atomics_legal_T_383 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_385 = _atomics_legal_T_384; // @[Parameters.scala:137:46] wire _atomics_legal_T_386 = _atomics_legal_T_385 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_388 = {1'h0, _atomics_legal_T_387}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_389 = _atomics_legal_T_388 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_390 = _atomics_legal_T_389; // @[Parameters.scala:137:46] wire _atomics_legal_T_391 = _atomics_legal_T_390 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_393 = {1'h0, _atomics_legal_T_392}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_394 = _atomics_legal_T_393 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_395 = _atomics_legal_T_394; // @[Parameters.scala:137:46] wire _atomics_legal_T_396 = _atomics_legal_T_395 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_398 = {1'h0, _atomics_legal_T_397}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_399 = _atomics_legal_T_398 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_400 = _atomics_legal_T_399; // @[Parameters.scala:137:46] wire _atomics_legal_T_401 = _atomics_legal_T_400 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_403 = {1'h0, _atomics_legal_T_402}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_404 = _atomics_legal_T_403 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_405 = _atomics_legal_T_404; // @[Parameters.scala:137:46] wire _atomics_legal_T_406 = _atomics_legal_T_405 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_408 = {1'h0, _atomics_legal_T_407}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_409 = _atomics_legal_T_408 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_410 = _atomics_legal_T_409; // @[Parameters.scala:137:46] wire _atomics_legal_T_411 = _atomics_legal_T_410 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_413 = {1'h0, _atomics_legal_T_412}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_414 = _atomics_legal_T_413 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_415 = _atomics_legal_T_414; // @[Parameters.scala:137:46] wire _atomics_legal_T_416 = _atomics_legal_T_415 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_417 = _atomics_legal_T_386 \| _atomics_legal_T_391; // @[Parameters.scala:685:42] wire _atomics_legal_T_418 = _atomics_legal_T_417 \| _atomics_legal_T_396; // @[Parameters.scala:685:42] wire _atomics_legal_T_419 = _atomics_legal_T_418 \| _atomics_legal_T_401; // @[Parameters.scala:685:42] wire _atomics_legal_T_420 = _atomics_legal_T_419 \| _atomics_legal_T_406; // @[Parameters.scala:685:42] wire _atomics_legal_T_421 = _atomics_legal_T_420 \| _atomics_legal_T_411; // @[Parameters.scala:685:42] wire _atomics_legal_T_422 = _atomics_legal_T_421 \| _atomics_legal_T_416; // @[Parameters.scala:685:42] wire _atomics_legal_T_423 = _atomics_legal_T_422; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_431 = _atomics_legal_T_423; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_426 = {1'h0, _atomics_legal_T_425}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_427 = _atomics_legal_T_426 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_428 = _atomics_legal_T_427; // @[Parameters.scala:137:46] wire _atomics_legal_T_429 = _atomics_legal_T_428 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_7 = _atomics_legal_T_431; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [7:0] atomics_a_7_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_7 = _atomics_a_mask_sizeOH_T_21[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_22 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_7; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_23 = _atomics_a_mask_sizeOH_T_22[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_7 = {_atomics_a_mask_sizeOH_T_23[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_7 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_7 = atomics_a_mask_sizeOH_7[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_7 = atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_7 = ~atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_7 = atomics_a_mask_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_14 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 \| _atomics_a_mask_sub_sub_acc_T_14; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_15 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 \| _atomics_a_mask_sub_sub_acc_T_15; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_7 = atomics_a_mask_sizeOH_7[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_7 = ~atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_28 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_7 = atomics_a_mask_sub_sub_0_1_7 \| _atomics_a_mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_29 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_7 = atomics_a_mask_sub_sub_0_1_7 \| _atomics_a_mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_30 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_2_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_7 = atomics_a_mask_sub_sub_1_1_7 \| _atomics_a_mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_31 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_3_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_7 = atomics_a_mask_sub_sub_1_1_7 \| _atomics_a_mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_7 = atomics_a_mask_sizeOH_7[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_7 = ~atomics_a_mask_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_56 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_56 = atomics_a_mask_size_7 & atomics_a_mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_56 = atomics_a_mask_sub_0_1_7 \| _atomics_a_mask_acc_T_56; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_57 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_57 = atomics_a_mask_size_7 & atomics_a_mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_57 = atomics_a_mask_sub_0_1_7 \| _atomics_a_mask_acc_T_57; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_58 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_58 = atomics_a_mask_size_7 & atomics_a_mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_58 = atomics_a_mask_sub_1_1_7 \| _atomics_a_mask_acc_T_58; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_59 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_59 = atomics_a_mask_size_7 & atomics_a_mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_59 = atomics_a_mask_sub_1_1_7 \| _atomics_a_mask_acc_T_59; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_60 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_60 = atomics_a_mask_size_7 & atomics_a_mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_60 = atomics_a_mask_sub_2_1_7 \| _atomics_a_mask_acc_T_60; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_61 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_61 = atomics_a_mask_size_7 & atomics_a_mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_61 = atomics_a_mask_sub_2_1_7 \| _atomics_a_mask_acc_T_61; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_62 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_62 = atomics_a_mask_size_7 & atomics_a_mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_62 = atomics_a_mask_sub_3_1_7 \| _atomics_a_mask_acc_T_62; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_63 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_63 = atomics_a_mask_size_7 & atomics_a_mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_63 = atomics_a_mask_sub_3_1_7 \| _atomics_a_mask_acc_T_63; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_7 = {atomics_a_mask_acc_57, atomics_a_mask_acc_56}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_7 = {atomics_a_mask_acc_59, atomics_a_mask_acc_58}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_7 = {atomics_a_mask_lo_hi_7, atomics_a_mask_lo_lo_7}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_7 = {atomics_a_mask_acc_61, atomics_a_mask_acc_60}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_7 = {atomics_a_mask_acc_63, atomics_a_mask_acc_62}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_7 = {atomics_a_mask_hi_hi_7, atomics_a_mask_hi_lo_7}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_7 = {atomics_a_mask_hi_7, atomics_a_mask_lo_7}; // @[Misc.scala:222:10] assign atomics_a_7_mask = _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_437 = {1'h0, _atomics_legal_T_436}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_438 = _atomics_legal_T_437 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_439 = _atomics_legal_T_438; // @[Parameters.scala:137:46] wire _atomics_legal_T_440 = _atomics_legal_T_439 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_442 = {1'h0, _atomics_legal_T_441}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_443 = _atomics_legal_T_442 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_444 = _atomics_legal_T_443; // @[Parameters.scala:137:46] wire _atomics_legal_T_445 = _atomics_legal_T_444 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_447 = {1'h0, _atomics_legal_T_446}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_448 = _atomics_legal_T_447 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_449 = _atomics_legal_T_448; // @[Parameters.scala:137:46] wire _atomics_legal_T_450 = _atomics_legal_T_449 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_452 = {1'h0, _atomics_legal_T_451}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_453 = _atomics_legal_T_452 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_454 = _atomics_legal_T_453; // @[Parameters.scala:137:46] wire _atomics_legal_T_455 = _atomics_legal_T_454 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_457 = {1'h0, _atomics_legal_T_456}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_458 = _atomics_legal_T_457 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_459 = _atomics_legal_T_458; // @[Parameters.scala:137:46] wire _atomics_legal_T_460 = _atomics_legal_T_459 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_462 = {1'h0, _atomics_legal_T_461}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_463 = _atomics_legal_T_462 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_464 = _atomics_legal_T_463; // @[Parameters.scala:137:46] wire _atomics_legal_T_465 = _atomics_legal_T_464 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_467 = {1'h0, _atomics_legal_T_466}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_468 = _atomics_legal_T_467 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_469 = _atomics_legal_T_468; // @[Parameters.scala:137:46] wire _atomics_legal_T_470 = _atomics_legal_T_469 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_471 = _atomics_legal_T_440 \| _atomics_legal_T_445; // @[Parameters.scala:685:42] wire _atomics_legal_T_472 = _atomics_legal_T_471 \| _atomics_legal_T_450; // @[Parameters.scala:685:42] wire _atomics_legal_T_473 = _atomics_legal_T_472 \| _atomics_legal_T_455; // @[Parameters.scala:685:42] wire _atomics_legal_T_474 = _atomics_legal_T_473 \| _atomics_legal_T_460; // @[Parameters.scala:685:42] wire _atomics_legal_T_475 = _atomics_legal_T_474 \| _atomics_legal_T_465; // @[Parameters.scala:685:42] wire _atomics_legal_T_476 = _atomics_legal_T_475 \| _atomics_legal_T_470; // @[Parameters.scala:685:42] wire _atomics_legal_T_477 = _atomics_legal_T_476; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_485 = _atomics_legal_T_477; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_480 = {1'h0, _atomics_legal_T_479}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_481 = _atomics_legal_T_480 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_482 = _atomics_legal_T_481; // @[Parameters.scala:137:46] wire _atomics_legal_T_483 = _atomics_legal_T_482 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_8 = _atomics_legal_T_485; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire [7:0] atomics_a_8_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_8 = _atomics_a_mask_sizeOH_T_24[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_25 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_8; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_26 = _atomics_a_mask_sizeOH_T_25[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_8 = {_atomics_a_mask_sizeOH_T_26[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_8 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_8 = atomics_a_mask_sizeOH_8[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_8 = atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_8 = ~atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_8 = atomics_a_mask_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_16 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 \| _atomics_a_mask_sub_sub_acc_T_16; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_17 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 \| _atomics_a_mask_sub_sub_acc_T_17; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_8 = atomics_a_mask_sizeOH_8[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_8 = ~atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_32 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_8 = atomics_a_mask_sub_sub_0_1_8 \| _atomics_a_mask_sub_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_33 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_8 = atomics_a_mask_sub_sub_0_1_8 \| _atomics_a_mask_sub_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_34 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_2_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_8 = atomics_a_mask_sub_sub_1_1_8 \| _atomics_a_mask_sub_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_35 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_3_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_8 = atomics_a_mask_sub_sub_1_1_8 \| _atomics_a_mask_sub_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_8 = atomics_a_mask_sizeOH_8[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_8 = ~atomics_a_mask_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_64 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_64 = atomics_a_mask_size_8 & atomics_a_mask_eq_64; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_64 = atomics_a_mask_sub_0_1_8 \| _atomics_a_mask_acc_T_64; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_65 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_65 = atomics_a_mask_size_8 & atomics_a_mask_eq_65; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_65 = atomics_a_mask_sub_0_1_8 \| _atomics_a_mask_acc_T_65; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_66 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_66 = atomics_a_mask_size_8 & atomics_a_mask_eq_66; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_66 = atomics_a_mask_sub_1_1_8 \| _atomics_a_mask_acc_T_66; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_67 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_67 = atomics_a_mask_size_8 & atomics_a_mask_eq_67; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_67 = atomics_a_mask_sub_1_1_8 \| _atomics_a_mask_acc_T_67; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_68 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_68 = atomics_a_mask_size_8 & atomics_a_mask_eq_68; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_68 = atomics_a_mask_sub_2_1_8 \| _atomics_a_mask_acc_T_68; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_69 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_69 = atomics_a_mask_size_8 & atomics_a_mask_eq_69; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_69 = atomics_a_mask_sub_2_1_8 \| _atomics_a_mask_acc_T_69; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_70 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_70 = atomics_a_mask_size_8 & atomics_a_mask_eq_70; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_70 = atomics_a_mask_sub_3_1_8 \| _atomics_a_mask_acc_T_70; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_71 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_71 = atomics_a_mask_size_8 & atomics_a_mask_eq_71; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_71 = atomics_a_mask_sub_3_1_8 \| _atomics_a_mask_acc_T_71; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_8 = {atomics_a_mask_acc_65, atomics_a_mask_acc_64}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_8 = {atomics_a_mask_acc_67, atomics_a_mask_acc_66}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_8 = {atomics_a_mask_lo_hi_8, atomics_a_mask_lo_lo_8}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_8 = {atomics_a_mask_acc_69, atomics_a_mask_acc_68}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_8 = {atomics_a_mask_acc_71, atomics_a_mask_acc_70}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_8 = {atomics_a_mask_hi_hi_8, atomics_a_mask_hi_lo_8}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_8 = {atomics_a_mask_hi_8, atomics_a_mask_lo_8}; // @[Misc.scala:222:10] assign atomics_a_8_mask = _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire [2:0] _GEN_112 = _atomics_T ? 3'h3 : 3'h0; // @[DCache.scala:587:81] wire [2:0] _atomics_T_1_opcode; // @[DCache.scala:587:81] assign _atomics_T_1_opcode = _GEN_112; // @[DCache.scala:587:81] wire [2:0] _atomics_T_1_param; // @[DCache.scala:587:81] assign _atomics_T_1_param = _GEN_112; // @[DCache.scala:587:81] wire [3:0] _atomics_T_1_size = _atomics_T ? atomics_a_size : 4'h0; // @[Edges.scala:534:17] wire _atomics_T_1_source = _atomics_T & atomics_a_source; // @[Edges.scala:534:17] wire [31:0] _atomics_T_1_address = _atomics_T ? atomics_a_address : 32'h0; // @[Edges.scala:534:17] wire [7:0] _atomics_T_1_mask = _atomics_T ? atomics_a_mask : 8'h0; // @[Edges.scala:534:17] wire [63:0] _atomics_T_1_data = _atomics_T ? atomics_a_data : 64'h0; // @[Edges.scala:534:17] wire [2:0] _atomics_T_3_opcode = _atomics_T_2 ? 3'h3 : _atomics_T_1_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_3_param = _atomics_T_2 ? 3'h0 : _atomics_T_1_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_3_size = _atomics_T_2 ? atomics_a_1_size : _atomics_T_1_size; // @[Edges.scala:534:17] wire _atomics_T_3_source = _atomics_T_2 ? atomics_a_1_source : _atomics_T_1_source; // @[Edges.scala:534:17] wire [31:0] _atomics_T_3_address = _atomics_T_2 ? atomics_a_1_address : _atomics_T_1_address; // @[Edges.scala:534:17] wire [7:0] _atomics_T_3_mask = _atomics_T_2 ? atomics_a_1_mask : _atomics_T_1_mask; // @[Edges.scala:534:17] wire [63:0] _atomics_T_3_data = _atomics_T_2 ? atomics_a_1_data : _atomics_T_1_data; // @[Edges.scala:534:17] wire [2:0] _atomics_T_5_opcode = _atomics_T_4 ? 3'h3 : _atomics_T_3_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_5_param = _atomics_T_4 ? 3'h1 : _atomics_T_3_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_5_size = _atomics_T_4 ? atomics_a_2_size : _atomics_T_3_size; // @[Edges.scala:534:17] wire _atomics_T_5_source = _atomics_T_4 ? atomics_a_2_source : _atomics_T_3_source; // @[Edges.scala:534:17] wire [31:0] _atomics_T_5_address = _atomics_T_4 ? atomics_a_2_address : _atomics_T_3_address; // @[Edges.scala:534:17] wire [7:0] _atomics_T_5_mask = _atomics_T_4 ? atomics_a_2_mask : _atomics_T_3_mask; // @[Edges.scala:534:17] wire [63:0] _atomics_T_5_data = _atomics_T_4 ? atomics_a_2_data : _atomics_T_3_data; // @[Edges.scala:534:17] wire [2:0] _atomics_T_7_opcode = _atomics_T_6 ? 3'h3 : _atomics_T_5_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_7_param = _atomics_T_6 ? 3'h2 : _atomics_T_5_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_7_size = _atomics_T_6 ? atomics_a_3_size : _atomics_T_5_size; // @[Edges.scala:534:17] wire _atomics_T_7_source = _atomics_T_6 ? atomics_a_3_source : _atomics_T_5_source; // @[Edges.scala:534:17] wire [31:0] _atomics_T_7_address = _atomics_T_6 ? atomics_a_3_address : _atomics_T_5_address; // @[Edges.scala:534:17] wire [7:0] _atomics_T_7_mask = _atomics_T_6 ? atomics_a_3_mask : _atomics_T_5_mask; // @[Edges.scala:534:17] wire [63:0] _atomics_T_7_data = _atomics_T_6 ? atomics_a_3_data : _atomics_T_5_data; // @[Edges.scala:534:17] wire [2:0] _atomics_T_9_opcode = _atomics_T_8 ? 3'h2 : _atomics_T_7_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_9_param = _atomics_T_8 ? 3'h4 : _atomics_T_7_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_9_size = _atomics_T_8 ? atomics_a_4_size : _atomics_T_7_size; // @[Edges.scala:517:17] wire _atomics_T_9_source = _atomics_T_8 ? atomics_a_4_source : _atomics_T_7_source; // @[Edges.scala:517:17] wire [31:0] _atomics_T_9_address = _atomics_T_8 ? atomics_a_4_address : _atomics_T_7_address; // @[Edges.scala:517:17] wire [7:0] _atomics_T_9_mask = _atomics_T_8 ? atomics_a_4_mask : _atomics_T_7_mask; // @[Edges.scala:517:17] wire [63:0] _atomics_T_9_data = _atomics_T_8 ? atomics_a_4_data : _atomics_T_7_data; // @[Edges.scala:517:17] wire [2:0] _atomics_T_11_opcode = _atomics_T_10 ? 3'h2 : _atomics_T_9_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_11_param = _atomics_T_10 ? 3'h0 : _atomics_T_9_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_11_size = _atomics_T_10 ? atomics_a_5_size : _atomics_T_9_size; // @[Edges.scala:517:17] wire _atomics_T_11_source = _atomics_T_10 ? atomics_a_5_source : _atomics_T_9_source; // @[Edges.scala:517:17] wire [31:0] _atomics_T_11_address = _atomics_T_10 ? atomics_a_5_address : _atomics_T_9_address; // @[Edges.scala:517:17] wire [7:0] _atomics_T_11_mask = _atomics_T_10 ? atomics_a_5_mask : _atomics_T_9_mask; // @[Edges.scala:517:17] wire [63:0] _atomics_T_11_data = _atomics_T_10 ? atomics_a_5_data : _atomics_T_9_data; // @[Edges.scala:517:17] wire [2:0] _atomics_T_13_opcode = _atomics_T_12 ? 3'h2 : _atomics_T_11_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_13_param = _atomics_T_12 ? 3'h1 : _atomics_T_11_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_13_size = _atomics_T_12 ? atomics_a_6_size : _atomics_T_11_size; // @[Edges.scala:517:17] wire _atomics_T_13_source = _atomics_T_12 ? atomics_a_6_source : _atomics_T_11_source; // @[Edges.scala:517:17] wire [31:0] _atomics_T_13_address = _atomics_T_12 ? atomics_a_6_address : _atomics_T_11_address; // @[Edges.scala:517:17] wire [7:0] _atomics_T_13_mask = _atomics_T_12 ? atomics_a_6_mask : _atomics_T_11_mask; // @[Edges.scala:517:17] wire [63:0] _atomics_T_13_data = _atomics_T_12 ? atomics_a_6_data : _atomics_T_11_data; // @[Edges.scala:517:17] wire [2:0] _atomics_T_15_opcode = _atomics_T_14 ? 3'h2 : _atomics_T_13_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_15_param = _atomics_T_14 ? 3'h2 : _atomics_T_13_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_15_size = _atomics_T_14 ? atomics_a_7_size : _atomics_T_13_size; // @[Edges.scala:517:17] wire _atomics_T_15_source = _atomics_T_14 ? atomics_a_7_source : _atomics_T_13_source; // @[Edges.scala:517:17] wire [31:0] _atomics_T_15_address = _atomics_T_14 ? atomics_a_7_address : _atomics_T_13_address; // @[Edges.scala:517:17] wire [7:0] _atomics_T_15_mask = _atomics_T_14 ? atomics_a_7_mask : _atomics_T_13_mask; // @[Edges.scala:517:17] wire [63:0] _atomics_T_15_data = _atomics_T_14 ? atomics_a_7_data : _atomics_T_13_data; // @[Edges.scala:517:17] wire [2:0] atomics_opcode = _atomics_T_16 ? 3'h2 : _atomics_T_15_opcode; // @[DCache.scala:587:81] wire [2:0] atomics_param = _atomics_T_16 ? 3'h3 : _atomics_T_15_param; // @[DCache.scala:587:81] wire [3:0] atomics_size = _atomics_T_16 ? atomics_a_8_size : _atomics_T_15_size; // @[Edges.scala:517:17] wire atomics_source = _atomics_T_16 ? atomics_a_8_source : _atomics_T_15_source; // @[Edges.scala:517:17] wire [31:0] atomics_address = _atomics_T_16 ? atomics_a_8_address : _atomics_T_15_address; // @[Edges.scala:517:17] wire [7:0] atomics_mask = _atomics_T_16 ? atomics_a_8_mask : _atomics_T_15_mask; // @[Edges.scala:517:17] wire [63:0] atomics_data = _atomics_T_16 ? atomics_a_8_data : _atomics_T_15_data; // @[Edges.scala:517:17] wire [39:0] _tl_out_a_valid_T_1 = {s2_req_addr[39:32], s2_req_addr[31:0] ^ release_ack_addr}; // @[DCache.scala:227:29, :339:19, :606:43] wire [14:0] _tl_out_a_valid_T_2 = _tl_out_a_valid_T_1[20:6]; // @[DCache.scala:606:{43,62}] wire _tl_out_a_valid_T_3 = _tl_out_a_valid_T_2 == 15'h0; // @[DCache.scala:582:29, :606:{62,118}] wire _tl_out_a_valid_T_4 = release_ack_wait & _tl_out_a_valid_T_3; // @[DCache.scala:226:33, :606:{27,118}] wire _tl_out_a_valid_T_5 = ~_tl_out_a_valid_T_4; // @[DCache.scala:606:{8,27}] wire _tl_out_a_valid_T_6 = s2_valid_cached_miss & _tl_out_a_valid_T_5; // @[DCache.scala:425:60, :605:29, :606:8] wire _tl_out_a_valid_T_7 = ~release_ack_wait; // @[DCache.scala:226:33, :607:47] wire _tl_out_a_valid_T_10 = ~s2_victim_dirty; // @[Misc.scala:38:9] wire _tl_out_a_valid_T_11 = _tl_out_a_valid_T_10; // @[DCache.scala:607:{88,91}] wire _tl_out_a_valid_T_12 = _tl_out_a_valid_T_6 & _tl_out_a_valid_T_11; // @[DCache.scala:605:29, :606:127, :607:88] wire _tl_out_a_valid_T_13 = s2_valid_uncached_pending \| _tl_out_a_valid_T_12; // @[DCache.scala:430:64, :604:32, :606:127] assign _tl_out_a_valid_T_14 = _tl_out_a_valid_T_13; // @[DCache.scala:603:37, :604:32] assign tl_out_a_valid = _tl_out_a_valid_T_14; // @[DCache.scala:159:22, :603:37] wire _tl_out_a_bits_T = ~s2_uncached; // @[DCache.scala:424:39, :425:47, :608:24] wire [39:0] _tl_out_a_bits_T_2 = {_tl_out_a_bits_T_1, 6'h0}; // @[DCache.scala:1210:{39,60}] wire [39:0] _tl_out_a_bits_legal_T_1 = _tl_out_a_bits_T_2; // @[DCache.scala:1210:60] wire [40:0] _tl_out_a_bits_legal_T_2 = {1'h0, _tl_out_a_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _tl_out_a_bits_legal_T_3 = _tl_out_a_bits_legal_T_2 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _tl_out_a_bits_legal_T_4 = _tl_out_a_bits_legal_T_3; // @[Parameters.scala:137:46] wire _tl_out_a_bits_legal_T_5 = _tl_out_a_bits_legal_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _tl_out_a_bits_legal_T_6 = {_tl_out_a_bits_T_2[39:17], _tl_out_a_bits_T_2[16:0] ^ 17'h10000}; // @[DCache.scala:1210:60] wire [40:0] _tl_out_a_bits_legal_T_7 = {1'h0, _tl_out_a_bits_legal_T_6}; // @[Parameters.scala:137:{31,41}] wire [40:0] _tl_out_a_bits_legal_T_8 = _tl_out_a_bits_legal_T_7 & 41'h8C011000; // @[Parameters.scala:137:{41,46}] wire [40:0] _tl_out_a_bits_legal_T_9 = _tl_out_a_bits_legal_T_8; // @[Parameters.scala:137:46] wire _tl_out_a_bits_legal_T_10 = _tl_out_a_bits_legal_T_9 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _tl_out_a_bits_legal_T_11 = {_tl_out_a_bits_T_2[39:28], _tl_out_a_bits_T_2[27:0] ^ 28'hC000000}; // @[DCache.scala:1210:60] wire [40:0] _tl_out_a_bits_legal_T_12 = {1'h0, _tl_out_a_bits_legal_T_11}; // @[Parameters.scala:137:{31,41}] wire [40:0] _tl_out_a_bits_legal_T_13 = _tl_out_a_bits_legal_T_12 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _tl_out_a_bits_legal_T_14 = _tl_out_a_bits_legal_T_13; // @[Parameters.scala:137:46] wire _tl_out_a_bits_legal_T_15 = _tl_out_a_bits_legal_T_14 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _tl_out_a_bits_legal_T_16 = _tl_out_a_bits_legal_T_5 \| _tl_out_a_bits_legal_T_10; // @[Parameters.scala:685:42] wire _tl_out_a_bits_legal_T_17 = _tl_out_a_bits_legal_T_16 \| _tl_out_a_bits_legal_T_15; // @[Parameters.scala:685:42] wire [39:0] _tl_out_a_bits_legal_T_21 = {_tl_out_a_bits_T_2[39:28], _tl_out_a_bits_T_2[27:0] ^ 28'h8000000}; // @[DCache.scala:1210:60] wire [40:0] _tl_out_a_bits_legal_T_22 = {1'h0, _tl_out_a_bits_legal_T_21}; // @[Parameters.scala:137:{31,41}] wire [40:0] _tl_out_a_bits_legal_T_23 = _tl_out_a_bits_legal_T_22 & 41'h8C010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _tl_out_a_bits_legal_T_24 = _tl_out_a_bits_legal_T_23; // @[Parameters.scala:137:46] wire _tl_out_a_bits_legal_T_25 = _tl_out_a_bits_legal_T_24 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] tl_out_a_bits_a_address = _tl_out_a_bits_T_2[31:0]; // @[Edges.scala:346:17] wire [39:0] _tl_out_a_bits_legal_T_26 = {_tl_out_a_bits_T_2[39:32], tl_out_a_bits_a_address ^ 32'h80000000}; // @[Edges.scala:346:17] wire [40:0] _tl_out_a_bits_legal_T_27 = {1'h0, _tl_out_a_bits_legal_T_26}; // @[Parameters.scala:137:{31,41}] wire [40:0] _tl_out_a_bits_legal_T_28 = _tl_out_a_bits_legal_T_27 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _tl_out_a_bits_legal_T_29 = _tl_out_a_bits_legal_T_28; // @[Parameters.scala:137:46] wire _tl_out_a_bits_legal_T_30 = _tl_out_a_bits_legal_T_29 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _tl_out_a_bits_legal_T_31 = _tl_out_a_bits_legal_T_25 \| _tl_out_a_bits_legal_T_30; // @[Parameters.scala:685:42] wire _tl_out_a_bits_legal_T_32 = _tl_out_a_bits_legal_T_31; // @[Parameters.scala:684:54, :685:42] wire tl_out_a_bits_legal = _tl_out_a_bits_legal_T_32; // @[Parameters.scala:684:54, :686:26] wire [2:0] tl_out_a_bits_a_param; // @[Edges.scala:346:17] assign tl_out_a_bits_a_param = {1'h0, s2_grow_param}; // @[Misc.scala:35:36] wire tl_out_a_bits_a_mask_sub_sub_bit = _tl_out_a_bits_T_2[2]; // @[Misc.scala:210:26] wire tl_out_a_bits_a_mask_sub_sub_1_2 = tl_out_a_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire tl_out_a_bits_a_mask_sub_sub_nbit = ~tl_out_a_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire tl_out_a_bits_a_mask_sub_sub_0_2 = tl_out_a_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_sub_sub_acc_T = tl_out_a_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire _tl_out_a_bits_a_mask_sub_sub_acc_T_1 = tl_out_a_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_sub_bit = _tl_out_a_bits_T_2[1]; // @[Misc.scala:210:26] wire tl_out_a_bits_a_mask_sub_nbit = ~tl_out_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire tl_out_a_bits_a_mask_sub_0_2 = tl_out_a_bits_a_mask_sub_sub_0_2 & tl_out_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire tl_out_a_bits_a_mask_sub_1_2 = tl_out_a_bits_a_mask_sub_sub_0_2 & tl_out_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire tl_out_a_bits_a_mask_sub_2_2 = tl_out_a_bits_a_mask_sub_sub_1_2 & tl_out_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire tl_out_a_bits_a_mask_sub_3_2 = tl_out_a_bits_a_mask_sub_sub_1_2 & tl_out_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire tl_out_a_bits_a_mask_bit = _tl_out_a_bits_T_2[0]; // @[Misc.scala:210:26] wire tl_out_a_bits_a_mask_nbit = ~tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire tl_out_a_bits_a_mask_eq = tl_out_a_bits_a_mask_sub_0_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T = tl_out_a_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_1 = tl_out_a_bits_a_mask_sub_0_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_1 = tl_out_a_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_2 = tl_out_a_bits_a_mask_sub_1_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T_2 = tl_out_a_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_3 = tl_out_a_bits_a_mask_sub_1_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_3 = tl_out_a_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_4 = tl_out_a_bits_a_mask_sub_2_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T_4 = tl_out_a_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_5 = tl_out_a_bits_a_mask_sub_2_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_5 = tl_out_a_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_6 = tl_out_a_bits_a_mask_sub_3_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T_6 = tl_out_a_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_7 = tl_out_a_bits_a_mask_sub_3_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_7 = tl_out_a_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38] wire _tl_out_a_bits_T_3 = ~s2_write; // @[DCache.scala:609:9] wire _tl_out_a_bits_T_5 = ~s2_read; // @[DCache.scala:611:9] wire [2:0] _tl_out_a_bits_T_6_opcode = _tl_out_a_bits_T_5 ? 3'h0 : atomics_opcode; // @[DCache.scala:587:81, :611:{8,9}] wire [2:0] _tl_out_a_bits_T_6_param = _tl_out_a_bits_T_5 ? 3'h0 : atomics_param; // @[DCache.scala:587:81, :611:{8,9}] wire [3:0] _tl_out_a_bits_T_6_size = _tl_out_a_bits_T_5 ? put_size : atomics_size; // @[Edges.scala:480:17] wire _tl_out_a_bits_T_6_source = _tl_out_a_bits_T_5 ? put_source : atomics_source; // @[Edges.scala:480:17] wire [31:0] _tl_out_a_bits_T_6_address = _tl_out_a_bits_T_5 ? put_address : atomics_address; // @[Edges.scala:480:17] wire [7:0] _tl_out_a_bits_T_6_mask = _tl_out_a_bits_T_5 ? put_mask : atomics_mask; // @[Edges.scala:480:17] wire [63:0] _tl_out_a_bits_T_6_data = _tl_out_a_bits_T_5 ? put_data : atomics_data; // @[Edges.scala:480:17] wire [2:0] _tl_out_a_bits_T_7_opcode = _tl_out_a_bits_T_4 ? 3'h1 : _tl_out_a_bits_T_6_opcode; // @[DCache.scala:610:{8,20}, :611:8] wire [2:0] _tl_out_a_bits_T_7_param = _tl_out_a_bits_T_4 ? 3'h0 : _tl_out_a_bits_T_6_param; // @[DCache.scala:610:{8,20}, :611:8] wire [3:0] _tl_out_a_bits_T_7_size = _tl_out_a_bits_T_4 ? putpartial_size : _tl_out_a_bits_T_6_size; // @[Edges.scala:500:17] wire _tl_out_a_bits_T_7_source = _tl_out_a_bits_T_4 ? putpartial_source : _tl_out_a_bits_T_6_source; // @[Edges.scala:500:17] wire [31:0] _tl_out_a_bits_T_7_address = _tl_out_a_bits_T_4 ? putpartial_address : _tl_out_a_bits_T_6_address; // @[Edges.scala:500:17] wire [7:0] _tl_out_a_bits_T_7_mask = _tl_out_a_bits_T_4 ? putpartial_mask : _tl_out_a_bits_T_6_mask; // @[Edges.scala:500:17] wire [63:0] _tl_out_a_bits_T_7_data = _tl_out_a_bits_T_4 ? putpartial_data : _tl_out_a_bits_T_6_data; // @[Edges.scala:500:17] wire [2:0] _tl_out_a_bits_T_8_opcode = _tl_out_a_bits_T_3 ? 3'h4 : _tl_out_a_bits_T_7_opcode; // @[DCache.scala:609:{8,9}, :610:8] wire [2:0] _tl_out_a_bits_T_8_param = _tl_out_a_bits_T_3 ? 3'h0 : _tl_out_a_bits_T_7_param; // @[DCache.scala:609:{8,9}, :610:8] wire [3:0] _tl_out_a_bits_T_8_size = _tl_out_a_bits_T_3 ? get_size : _tl_out_a_bits_T_7_size; // @[Edges.scala:460:17] wire _tl_out_a_bits_T_8_source = _tl_out_a_bits_T_3 ? get_source : _tl_out_a_bits_T_7_source; // @[Edges.scala:460:17] wire [31:0] _tl_out_a_bits_T_8_address = _tl_out_a_bits_T_3 ? get_address : _tl_out_a_bits_T_7_address; // @[Edges.scala:460:17] wire [7:0] _tl_out_a_bits_T_8_mask = _tl_out_a_bits_T_3 ? get_mask : _tl_out_a_bits_T_7_mask; // @[Edges.scala:460:17] wire [63:0] _tl_out_a_bits_T_8_data = _tl_out_a_bits_T_3 ? 64'h0 : _tl_out_a_bits_T_7_data; // @[DCache.scala:609:{8,9}, :610:8] assign _tl_out_a_bits_T_9_opcode = _tl_out_a_bits_T ? 3'h6 : _tl_out_a_bits_T_8_opcode; // @[DCache.scala:608:{23,24}, :609:8] assign _tl_out_a_bits_T_9_param = _tl_out_a_bits_T ? tl_out_a_bits_a_param : _tl_out_a_bits_T_8_param; // @[Edges.scala:346:17] assign _tl_out_a_bits_T_9_size = _tl_out_a_bits_T ? 4'h6 : _tl_out_a_bits_T_8_size; // @[DCache.scala:608:{23,24}, :609:8] assign _tl_out_a_bits_T_9_source = ~_tl_out_a_bits_T & _tl_out_a_bits_T_8_source; // @[DCache.scala:608:{23,24}, :609:8] assign _tl_out_a_bits_T_9_address = _tl_out_a_bits_T ? tl_out_a_bits_a_address : _tl_out_a_bits_T_8_address; // @[Edges.scala:346:17] assign _tl_out_a_bits_T_9_mask = _tl_out_a_bits_T ? 8'hFF : _tl_out_a_bits_T_8_mask; // @[DCache.scala:608:{23,24}, :609:8] assign _tl_out_a_bits_T_9_data = _tl_out_a_bits_T ? 64'h0 : _tl_out_a_bits_T_8_data; // @[DCache.scala:608:{23,24}, :609:8] assign tl_out_a_bits_opcode = _tl_out_a_bits_T_9_opcode; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_param = _tl_out_a_bits_T_9_param; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_size = _tl_out_a_bits_T_9_size; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_source = _tl_out_a_bits_T_9_source; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_address = _tl_out_a_bits_T_9_address; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_mask = _tl_out_a_bits_T_9_mask; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_data = _tl_out_a_bits_T_9_data; // @[DCache.scala:159:22, :608:23] wire [1:0] _a_sel_T = 2'h1 << a_sel_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _a_sel_T_1 = _a_sel_T; // @[OneHot.scala:65:{12,27}] wire a_sel = _a_sel_T_1[1]; // @[OneHot.scala:65:27] wire _io_cpu_perf_acquire_T = tl_out_a_ready & tl_out_a_valid; // @[Decoupled.scala:51:35] wire [4:0] _uncachedReqs_0_cmd_T_1 = {_uncachedReqs_0_cmd_T, 4'h1}; // @[DCache.scala:637:{37,49}] wire [4:0] _uncachedReqs_0_cmd_T_2 = s2_write ? _uncachedReqs_0_cmd_T_1 : 5'h0; // @[DCache.scala:637:{23,37}] wire _T_82 = nodeOut_d_ready & nodeOut_d_valid; // @[Decoupled.scala:51:35] wire _io_cpu_replay_next_T; // @[Decoupled.scala:51:35] assign _io_cpu_replay_next_T = _T_82; // @[Decoupled.scala:51:35] wire _io_cpu_perf_blocked_near_end_of_refill_T; // @[Decoupled.scala:51:35] assign _io_cpu_perf_blocked_near_end_of_refill_T = _T_82; // @[Decoupled.scala:51:35] wire _io_errors_bus_valid_T; // @[Decoupled.scala:51:35] assign _io_errors_bus_valid_T = _T_82; // @[Decoupled.scala:51:35] wire [26:0] _r_beats1_decode_T = 27'hFFF << nodeOut_d_bits_size; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire r_beats1_opdata = nodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] r_counter; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_last = _r_last_T \| _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_done = d_last & _T_82; // @[Decoupled.scala:51:35] wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T = d_first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] d_address_inc = {r_4, 3'h0}; // @[Edges.scala:234:25, :269:29] wire grantIsUncachedData = nodeOut_d_bits_opcode == 3'h1; // @[package.scala:16:47] wire grantIsUncached = grantIsUncachedData \| nodeOut_d_bits_opcode == 3'h0 \| nodeOut_d_bits_opcode == 3'h2; // @[package.scala:16:47, :81:59] wire _tl_d_data_encoded_T_9 = io_ptw_customCSRs_csrs_0_value_0[9]; // @[CustomCSRs.scala:47:65] wire _tl_d_data_encoded_T_10 = ~_tl_d_data_encoded_T_9; // @[CustomCSRs.scala:47:65] wire _tl_d_data_encoded_T_11 = nodeOut_d_bits_corrupt & _tl_d_data_encoded_T_10; // @[DCache.scala:663:{77,80}] wire _tl_d_data_encoded_T_12 = ~grantIsUncached; // @[package.scala:81:59] wire _tl_d_data_encoded_T_13 = _tl_d_data_encoded_T_11 & _tl_d_data_encoded_T_12; // @[DCache.scala:663:{77,126,129}] wire [15:0] tl_d_data_encoded_lo_lo_1 = {_tl_d_data_encoded_T_15, _tl_d_data_encoded_T_14}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_lo_hi_1 = {_tl_d_data_encoded_T_17, _tl_d_data_encoded_T_16}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_lo_1 = {tl_d_data_encoded_lo_hi_1, tl_d_data_encoded_lo_lo_1}; // @[package.scala:45:27] wire [15:0] tl_d_data_encoded_hi_lo_1 = {_tl_d_data_encoded_T_19, _tl_d_data_encoded_T_18}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_hi_hi_1 = {_tl_d_data_encoded_T_21, _tl_d_data_encoded_T_20}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_hi_1 = {tl_d_data_encoded_hi_hi_1, tl_d_data_encoded_hi_lo_1}; // @[package.scala:45:27] assign _tl_d_data_encoded_T_22 = {tl_d_data_encoded_hi_1, tl_d_data_encoded_lo_1}; // @[package.scala:45:27] assign tl_d_data_encoded = _tl_d_data_encoded_T_22; // @[package.scala:45:27] wire _grantIsCached_T = nodeOut_d_bits_opcode == 3'h4; // @[package.scala:16:47] wire _GEN_113 = nodeOut_d_bits_opcode == 3'h5; // @[package.scala:16:47] wire _grantIsCached_T_1; // @[package.scala:16:47] assign _grantIsCached_T_1 = _GEN_113; // @[package.scala:16:47] wire grantIsRefill; // @[DCache.scala:666:29] assign grantIsRefill = _GEN_113; // @[package.scala:16:47] wire grantIsCached = _grantIsCached_T \| _grantIsCached_T_1; // @[package.scala:16:47, :81:59] wire grantIsVoluntary = nodeOut_d_bits_opcode == 3'h6; // @[DCache.scala:665:32] reg grantInProgress; // @[DCache.scala:667:32] reg [2:0] blockProbeAfterGrantCount; // @[DCache.scala:668:42] wire [3:0] _blockProbeAfterGrantCount_T = {1'h0, blockProbeAfterGrantCount} - 4'h1; // @[DCache.scala:668:42, :669:99] wire [2:0] _blockProbeAfterGrantCount_T_1 = _blockProbeAfterGrantCount_T[2:0]; // @[DCache.scala:669:99] wire _T_107 = release_state == 4'h6; // @[package.scala:16:47] wire _canAcceptCachedGrant_T_1; // @[package.scala:16:47] assign _canAcceptCachedGrant_T_1 = _T_107; // @[package.scala:16:47] wire _metaArb_io_in_4_valid_T; // @[package.scala:16:47] assign _metaArb_io_in_4_valid_T = _T_107; // @[package.scala:16:47] wire _T_111 = release_state == 4'h9; // @[package.scala:16:47] wire _canAcceptCachedGrant_T_2; // @[package.scala:16:47] assign _canAcceptCachedGrant_T_2 = _T_111; // @[package.scala:16:47] wire _nodeOut_c_valid_T_1; // @[DCache.scala:810:91] assign _nodeOut_c_valid_T_1 = _T_111; // @[package.scala:16:47] wire _canAcceptCachedGrant_T_3 = _canAcceptCachedGrant_T \| _canAcceptCachedGrant_T_1; // @[package.scala:16:47, :81:59] wire _canAcceptCachedGrant_T_4 = _canAcceptCachedGrant_T_3 \| _canAcceptCachedGrant_T_2; // @[package.scala:16:47, :81:59] wire canAcceptCachedGrant = ~_canAcceptCachedGrant_T_4; // @[package.scala:81:59] wire _nodeOut_d_ready_T = ~d_first; // @[Edges.scala:231:25] wire _nodeOut_d_ready_T_1 = _nodeOut_d_ready_T \| nodeOut_e_ready; // @[DCache.scala:671:{41,50}] wire _nodeOut_d_ready_T_2 = _nodeOut_d_ready_T_1 & canAcceptCachedGrant; // @[DCache.scala:670:30, :671:{50,69}] wire _nodeOut_d_ready_T_3 = ~grantIsCached \| _nodeOut_d_ready_T_2; // @[package.scala:81:59] wire [1:0] _uncachedRespIdxOH_T = 2'h1 << uncachedRespIdxOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _uncachedRespIdxOH_T_1 = _uncachedRespIdxOH_T; // @[OneHot.scala:65:{12,27}] wire uncachedRespIdxOH = _uncachedRespIdxOH_T_1[1]; // @[OneHot.scala:65:27] wire _uncachedResp_T = uncachedRespIdxOH; // @[Mux.scala:32:36] wire _GEN_114 = _T_82 & grantIsCached; // @[Decoupled.scala:51:35] assign replace = _GEN_114 & d_last; // @[Replacement.scala:37:29, :38:11] wire _T_74 = uncachedRespIdxOH & d_last; // @[Edges.scala:232:33] assign s1_data_way = ~_T_82 \| grantIsCached \| ~(grantIsUncached & grantIsUncachedData) ? {1'h0, _s1_data_way_T} : 9'h100; // @[Decoupled.scala:51:35] wire [28:0] _s2_req_addr_dontCareBits_T = s1_paddr[31:3]; // @[DCache.scala:298:21, :701:41] wire [31:0] s2_req_addr_dontCareBits = {_s2_req_addr_dontCareBits_T, 3'h0}; // @[DCache.scala:701:{41,55}] wire [2:0] _s2_req_addr_T = uncachedResp_addr[2:0]; // @[DCache.scala:238:30, :702:45] wire [31:0] _s2_req_addr_T_1 = {s2_req_addr_dontCareBits[31:3], s2_req_addr_dontCareBits[2:0] \| _s2_req_addr_T}; // @[DCache.scala:701:55, :702:{26,45}] wire _nodeOut_e_valid_T = nodeOut_d_valid & d_first; // @[Edges.scala:231:25] wire _nodeOut_e_valid_T_1 = _nodeOut_e_valid_T & grantIsCached; // @[package.scala:81:59] wire _nodeOut_e_valid_T_2 = _nodeOut_e_valid_T_1 & canAcceptCachedGrant; // @[DCache.scala:670:30, :714:{47,64}] assign nodeOut_e_bits_sink = nodeOut_e_bits_e_sink; // @[Edges.scala:451:17] wire _dataArb_io_in_1_valid_T = nodeOut_d_valid & grantIsRefill; // @[DCache.scala:666:29, :721:44] wire _dataArb_io_in_1_valid_T_1 = _dataArb_io_in_1_valid_T & canAcceptCachedGrant; // @[DCache.scala:670:30, :721:{44,61}] wire _T_90 = grantIsRefill & ~dataArb_io_in_1_ready; // @[DCache.scala:152:28, :666:29, :722:{23,26}] assign nodeOut_e_valid = ~_T_90 & _nodeOut_e_valid_T_2; // @[DCache.scala:714:{18,64}, :722:{23,51}, :723:20] wire [33:0] _dataArb_io_in_1_bits_addr_T = s2_vaddr[39:6]; // @[DCache.scala:351:21, :728:46] wire [39:0] _dataArb_io_in_1_bits_addr_T_1 = {_dataArb_io_in_1_bits_addr_T, 6'h0}; // @[DCache.scala:728:{46,57}] wire [39:0] _dataArb_io_in_1_bits_addr_T_2 = {_dataArb_io_in_1_bits_addr_T_1[39:12], _dataArb_io_in_1_bits_addr_T_1[11:0] \| d_address_inc}; // @[Edges.scala:269:29] assign dataArb_io_in_1_bits_addr = _dataArb_io_in_1_bits_addr_T_2[11:0]; // @[DCache.scala:152:28, :728:{32,67}] wire _metaArb_io_in_3_valid_T = grantIsCached & d_done; // @[package.scala:81:59] wire _metaArb_io_in_3_valid_T_1 = ~nodeOut_d_bits_denied; // @[DCache.scala:741:56] assign _metaArb_io_in_3_valid_T_2 = _metaArb_io_in_3_valid_T & _metaArb_io_in_3_valid_T_1; // @[DCache.scala:741:{43,53,56}] assign metaArb_io_in_3_valid = _metaArb_io_in_3_valid_T_2; // @[DCache.scala:135:28, :741:53] assign metaArb_io_in_3_bits_idx = _metaArb_io_in_3_bits_idx_T; // @[DCache.scala:135:28, :744:40] assign _metaArb_io_in_3_bits_addr_T_2 = {_metaArb_io_in_3_bits_addr_T, _metaArb_io_in_3_bits_addr_T_1}; // @[DCache.scala:745:{36,58,80}] assign metaArb_io_in_3_bits_addr = _metaArb_io_in_3_bits_addr_T_2; // @[DCache.scala:135:28, :745:36] wire _metaArb_io_in_3_bits_data_c_cat_T_2 = _metaArb_io_in_3_bits_data_c_cat_T \| _metaArb_io_in_3_bits_data_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _metaArb_io_in_3_bits_data_c_cat_T_4 = _metaArb_io_in_3_bits_data_c_cat_T_2 \| _metaArb_io_in_3_bits_data_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _metaArb_io_in_3_bits_data_c_cat_T_9 = _metaArb_io_in_3_bits_data_c_cat_T_5 \| _metaArb_io_in_3_bits_data_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_10 = _metaArb_io_in_3_bits_data_c_cat_T_9 \| _metaArb_io_in_3_bits_data_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_11 = _metaArb_io_in_3_bits_data_c_cat_T_10 \| _metaArb_io_in_3_bits_data_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_17 = _metaArb_io_in_3_bits_data_c_cat_T_12 \| _metaArb_io_in_3_bits_data_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_18 = _metaArb_io_in_3_bits_data_c_cat_T_17 \| _metaArb_io_in_3_bits_data_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_19 = _metaArb_io_in_3_bits_data_c_cat_T_18 \| _metaArb_io_in_3_bits_data_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_20 = _metaArb_io_in_3_bits_data_c_cat_T_19 \| _metaArb_io_in_3_bits_data_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_21 = _metaArb_io_in_3_bits_data_c_cat_T_11 \| _metaArb_io_in_3_bits_data_c_cat_T_20; // @[package.scala:81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_22 = _metaArb_io_in_3_bits_data_c_cat_T_4 \| _metaArb_io_in_3_bits_data_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _metaArb_io_in_3_bits_data_c_cat_T_25 = _metaArb_io_in_3_bits_data_c_cat_T_23 \| _metaArb_io_in_3_bits_data_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _metaArb_io_in_3_bits_data_c_cat_T_27 = _metaArb_io_in_3_bits_data_c_cat_T_25 \| _metaArb_io_in_3_bits_data_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _metaArb_io_in_3_bits_data_c_cat_T_32 = _metaArb_io_in_3_bits_data_c_cat_T_28 \| _metaArb_io_in_3_bits_data_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_33 = _metaArb_io_in_3_bits_data_c_cat_T_32 \| _metaArb_io_in_3_bits_data_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_34 = _metaArb_io_in_3_bits_data_c_cat_T_33 \| _metaArb_io_in_3_bits_data_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_40 = _metaArb_io_in_3_bits_data_c_cat_T_35 \| _metaArb_io_in_3_bits_data_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_41 = _metaArb_io_in_3_bits_data_c_cat_T_40 \| _metaArb_io_in_3_bits_data_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_42 = _metaArb_io_in_3_bits_data_c_cat_T_41 \| _metaArb_io_in_3_bits_data_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_43 = _metaArb_io_in_3_bits_data_c_cat_T_42 \| _metaArb_io_in_3_bits_data_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_44 = _metaArb_io_in_3_bits_data_c_cat_T_34 \| _metaArb_io_in_3_bits_data_c_cat_T_43; // @[package.scala:81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_45 = _metaArb_io_in_3_bits_data_c_cat_T_27 \| _metaArb_io_in_3_bits_data_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _metaArb_io_in_3_bits_data_c_cat_T_47 = _metaArb_io_in_3_bits_data_c_cat_T_45 \| _metaArb_io_in_3_bits_data_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _metaArb_io_in_3_bits_data_c_cat_T_49 = _metaArb_io_in_3_bits_data_c_cat_T_47 \| _metaArb_io_in_3_bits_data_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] metaArb_io_in_3_bits_data_c = {_metaArb_io_in_3_bits_data_c_cat_T_22, _metaArb_io_in_3_bits_data_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _metaArb_io_in_3_bits_data_T_1 = {metaArb_io_in_3_bits_data_c, nodeOut_d_bits_param}; // @[Metadata.scala:29:18, :84:18] wire _metaArb_io_in_3_bits_data_T_10 = _metaArb_io_in_3_bits_data_T_1 == 4'h1; // @[Metadata.scala:84:{18,38}] wire [1:0] _metaArb_io_in_3_bits_data_T_11 = {1'h0, _metaArb_io_in_3_bits_data_T_10}; // @[Metadata.scala:84:38] wire _metaArb_io_in_3_bits_data_T_12 = _metaArb_io_in_3_bits_data_T_1 == 4'h0; // @[Metadata.scala:84:{18,38}] wire [1:0] _metaArb_io_in_3_bits_data_T_13 = _metaArb_io_in_3_bits_data_T_12 ? 2'h2 : _metaArb_io_in_3_bits_data_T_11; // @[Metadata.scala:84:38] wire _metaArb_io_in_3_bits_data_T_14 = _metaArb_io_in_3_bits_data_T_1 == 4'h4; // @[Metadata.scala:84:{18,38}] wire [1:0] _metaArb_io_in_3_bits_data_T_15 = _metaArb_io_in_3_bits_data_T_14 ? 2'h2 : _metaArb_io_in_3_bits_data_T_13; // @[Metadata.scala:84:38] wire _metaArb_io_in_3_bits_data_T_16 = _metaArb_io_in_3_bits_data_T_1 == 4'hC; // @[Metadata.scala:84:{18,38}] wire [1:0] _metaArb_io_in_3_bits_data_T_17 = _metaArb_io_in_3_bits_data_T_16 ? 2'h3 : _metaArb_io_in_3_bits_data_T_15; // @[Metadata.scala:84:38] wire [1:0] metaArb_io_in_3_bits_data_meta_state = _metaArb_io_in_3_bits_data_T_17; // @[Metadata.scala:84:38, :160:20] wire [1:0] metaArb_io_in_3_bits_data_meta_1_coh_state = metaArb_io_in_3_bits_data_meta_state; // @[Metadata.scala:160:20] wire [19:0] metaArb_io_in_3_bits_data_meta_1_tag; // @[HellaCache.scala:305:20] assign metaArb_io_in_3_bits_data_meta_1_tag = _metaArb_io_in_3_bits_data_T[19:0]; // @[HellaCache.scala:305:20, :306:14] assign _metaArb_io_in_3_bits_data_T_18 = {metaArb_io_in_3_bits_data_meta_1_coh_state, metaArb_io_in_3_bits_data_meta_1_tag}; // @[HellaCache.scala:305:20] assign metaArb_io_in_3_bits_data = _metaArb_io_in_3_bits_data_T_18; // @[DCache.scala:135:28, :746:134] reg blockUncachedGrant; // @[DCache.scala:750:33] wire _T_92 = grantIsUncachedData & (blockUncachedGrant \| s1_valid); // @[package.scala:16:47] assign nodeOut_d_ready = ~(_T_92 \| _T_90) & _nodeOut_d_ready_T_3; // @[DCache.scala:671:{18,24}, :722:{23,51}, :724:20, :752:{31,68}, :753:22] assign io_cpu_req_ready_0 = _T_92 ? ~(nodeOut_d_valid \| _T_10 \| ~metaArb_io_in_7_ready \| _T_4) & _io_cpu_req_ready_T_4 : ~(_T_10 \| ~metaArb_io_in_7_ready \| _T_4) & _io_cpu_req_ready_T_4; // @[DCache.scala:101:7, :135:28, :195:9, :233:{20,73}, :258:{33,45,64}, :267:{34,53}, :275:{27,53,79,98}, :752:{31,68}, :755:29, :756:26] wire _GEN_115 = _T_92 & nodeOut_d_valid; // @[DCache.scala:721:26, :752:{31,68}, :755:29, :757:32] assign dataArb_io_in_1_valid = _GEN_115 \| _dataArb_io_in_1_valid_T_1; // @[DCache.scala:152:28, :721:{26,61}, :752:68, :755:29, :757:32] assign dataArb_io_in_1_bits_write = ~_T_92 \| ~nodeOut_d_valid; // @[DCache.scala:152:28, :727:33, :752:{31,68}, :755:29, :758:37] wire _blockUncachedGrant_T = ~dataArb_io_in_1_ready; // @[DCache.scala:152:28, :722:26, :759:31] wire _block_probe_for_core_progress_T = \|blockProbeAfterGrantCount; // @[DCache.scala:668:42, :669:35, :766:65] wire block_probe_for_core_progress = _block_probe_for_core_progress_T \| lrscValid; // @[DCache.scala:473:29, :766:{65,71}] wire [31:0] _block_probe_for_pending_release_ack_T = nodeOut_b_bits_address ^ release_ack_addr; // @[DCache.scala:227:29, :767:88] wire [14:0] _block_probe_for_pending_release_ack_T_1 = _block_probe_for_pending_release_ack_T[20:6]; // @[DCache.scala:767:{88,107}] wire _block_probe_for_pending_release_ack_T_2 = _block_probe_for_pending_release_ack_T_1 == 15'h0; // @[DCache.scala:582:29, :767:{107,163}] wire block_probe_for_pending_release_ack = release_ack_wait & _block_probe_for_pending_release_ack_T_2; // @[DCache.scala:226:33, :767:{62,163}] wire _block_probe_for_ordering_T = releaseInFlight \| block_probe_for_pending_release_ack; // @[DCache.scala:334:46, :767:62, :768:50] wire block_probe_for_ordering = _block_probe_for_ordering_T \| grantInProgress; // @[DCache.scala:667:32, :768:{50,89}] wire _metaArb_io_in_6_valid_T = ~block_probe_for_core_progress; // @[DCache.scala:766:71, :769:48] wire _metaArb_io_in_6_valid_T_1 = _metaArb_io_in_6_valid_T \| lrscBackingOff; // @[DCache.scala:474:40, :769:{48,79}] wire _metaArb_io_in_6_valid_T_2 = nodeOut_b_valid & _metaArb_io_in_6_valid_T_1; // @[DCache.scala:769:{44,79}] wire _nodeOut_b_ready_T = block_probe_for_core_progress \| block_probe_for_ordering; // @[DCache.scala:766:71, :768:89, :770:79] wire _nodeOut_b_ready_T_1 = _nodeOut_b_ready_T \| s1_valid; // @[DCache.scala:182:25, :770:{79,107}] wire _nodeOut_b_ready_T_2 = _nodeOut_b_ready_T_1 \| s2_valid; // @[DCache.scala:331:25, :770:{107,119}] wire _nodeOut_b_ready_T_3 = ~_nodeOut_b_ready_T_2; // @[DCache.scala:770:{47,119}] assign _nodeOut_b_ready_T_4 = metaArb_io_in_6_ready & _nodeOut_b_ready_T_3; // @[DCache.scala:135:28, :770:{44,47}] assign nodeOut_b_ready = _nodeOut_b_ready_T_4; // @[DCache.scala:770:44] wire [5:0] _metaArb_io_in_6_bits_idx_T = nodeOut_b_bits_address[11:6]; // @[DCache.scala:1200:47] wire [7:0] _metaArb_io_in_6_bits_addr_T = io_cpu_req_bits_addr_0[39:32]; // @[DCache.scala:101:7, :773:58] wire [7:0] _metaArb_io_in_6_bits_addr_T_2 = io_cpu_req_bits_addr_0[39:32]; // @[DCache.scala:101:7, :773:58, :844:62] wire [39:0] _metaArb_io_in_6_bits_addr_T_1 = {_metaArb_io_in_6_bits_addr_T, nodeOut_b_bits_address}; // @[DCache.scala:773:{36,58}] assign _s1_victim_way_T = lfsr[2:0]; // @[PRNG.scala:95:17] assign s1_victim_way = _s1_victim_way_T; // @[package.scala:163:13] wire _T_126 = nodeOut_c_ready & nodeOut_c_valid; // @[Decoupled.scala:51:35] wire _releaseRejected_T; // @[Decoupled.scala:51:35] assign _releaseRejected_T = _T_126; // @[Decoupled.scala:51:35] wire _io_cpu_perf_release_T; // @[Decoupled.scala:51:35] assign _io_cpu_perf_release_T = _T_126; // @[Decoupled.scala:51:35] wire [26:0] _GEN_116 = 27'hFFF << nodeOut_c_bits_size; // @[package.scala:243:71] wire [26:0] _r_beats1_decode_T_3; // @[package.scala:243:71] assign _r_beats1_decode_T_3 = _GEN_116; // @[package.scala:243:71] wire [26:0] _io_cpu_perf_release_beats1_decode_T; // @[package.scala:243:71] assign _io_cpu_perf_release_beats1_decode_T = _GEN_116; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_4 = _r_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_5 = ~_r_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] r_beats1_decode_1 = _r_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire r_beats1_opdata_1 = nodeOut_c_bits_opcode[0]; // @[Edges.scala:102:36] wire io_cpu_perf_release_beats1_opdata = nodeOut_c_bits_opcode[0]; // @[Edges.scala:102:36] wire [8:0] r_beats1_1 = r_beats1_opdata_1 ? r_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] r_counter_1; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T_1 = {1'h0, r_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1_1 = _r_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first = r_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T_2 = r_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_3 = r_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_last = _r_last_T_2 \| _r_last_T_3; // @[Edges.scala:232:{25,33,43}] wire releaseDone = c_last & _T_126; // @[Decoupled.scala:51:35] wire [8:0] _r_count_T_1 = ~r_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_count = r_beats1_1 & _r_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T_1 = c_first ? r_beats1_1 : r_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire _releaseRejected_T_2; // @[DCache.scala:803:44] wire releaseRejected; // @[DCache.scala:800:29] wire _s1_release_data_valid_T = dataArb_io_in_2_ready & _dataArb_io_in_2_valid_T_1; // @[Decoupled.scala:51:35] reg s1_release_data_valid; // @[DCache.scala:801:38] wire _s2_release_data_valid_T = ~releaseRejected; // @[DCache.scala:800:29, :802:64] wire _s2_release_data_valid_T_1 = s1_release_data_valid & _s2_release_data_valid_T; // @[DCache.scala:801:38, :802:{61,64}] reg s2_release_data_valid; // @[DCache.scala:802:38] wire _nodeOut_c_valid_T_3 = s2_release_data_valid; // @[DCache.scala:802:38, :810:44] wire _releaseRejected_T_1 = ~_releaseRejected_T; // @[Decoupled.scala:51:35] assign _releaseRejected_T_2 = s2_release_data_valid & _releaseRejected_T_1; // @[DCache.scala:802:38, :803:{44,47}] assign releaseRejected = _releaseRejected_T_2; // @[DCache.scala:800:29, :803:44] wire [9:0] _releaseDataBeat_T = {1'h0, c_count}; // @[Edges.scala:234:25] wire [1:0] _releaseDataBeat_T_1 = {1'h0, s2_release_data_valid}; // @[DCache.scala:802:38, :804:98] wire [2:0] _releaseDataBeat_T_2 = {2'h0, s1_release_data_valid} + {1'h0, _releaseDataBeat_T_1}; // @[DCache.scala:801:38, :804:{93,98}] wire [1:0] _releaseDataBeat_T_3 = _releaseDataBeat_T_2[1:0]; // @[DCache.scala:804:93] wire [1:0] _releaseDataBeat_T_4 = releaseRejected ? 2'h0 : _releaseDataBeat_T_3; // @[DCache.scala:800:29, :804:{48,93}] wire [10:0] _releaseDataBeat_T_5 = {1'h0, _releaseDataBeat_T} + {9'h0, _releaseDataBeat_T_4}; // @[DCache.scala:804:{28,43,48}] wire [9:0] releaseDataBeat = _releaseDataBeat_T_5[9:0]; // @[DCache.scala:804:43] wire _nodeOut_c_valid_T_4 = c_first & release_ack_wait; // @[Edges.scala:231:25] wire _nodeOut_c_valid_T_5 = ~_nodeOut_c_valid_T_4; // @[DCache.scala:810:{120,130}] wire _nodeOut_c_valid_T_6 = _nodeOut_c_valid_T_3 & _nodeOut_c_valid_T_5; // @[DCache.scala:810:{44,117,120}] wire [1:0] newCoh_state; // @[DCache.scala:812:27] wire [1:0] metaArb_io_in_4_bits_data_meta_coh_state = newCoh_state; // @[HellaCache.scala:305:20] wire _release_state_T_8 = s2_valid_flush_line \| s2_flush_valid; // @[DCache.scala:363:51, :419:75, :817:34, :820:151] wire _discard_line_T = s2_req_size[1]; // @[DCache.scala:339:19, :818:60] wire _discard_line_T_1 = s2_valid_flush_line & _discard_line_T; // @[DCache.scala:419:75, :818:{46,60}] wire _discard_line_T_3 = s2_flush_valid & _discard_line_T_2; // @[DCache.scala:363:51, :818:{82,102}] wire discard_line = _discard_line_T_1 \| _discard_line_T_3; // @[DCache.scala:818:{46,64,82}] wire _release_state_T = ~discard_line; // @[DCache.scala:818:64, :819:47] wire _release_state_T_1 = s2_victim_dirty & _release_state_T; // @[Misc.scala:38:9] wire _release_state_T_3 = ~release_ack_wait; // @[DCache.scala:226:33, :607:47, :820:57] wire _release_state_T_6 = \|s2_victim_state_state; // @[Metadata.scala:50:45] wire _release_state_T_9 = ~s2_hit_valid; // @[Metadata.scala:50:45] wire _release_state_T_10 = s2_readwrite & _release_state_T_9; // @[DCache.scala:354:30, :820:{185,188}] wire _release_state_T_11 = _release_state_T_8 \| _release_state_T_10; // @[DCache.scala:820:{151,169,185}] wire [3:0] _release_state_T_14 = _release_state_T_1 ? 4'h1 : 4'h6; // @[DCache.scala:819:{27,44}] wire [5:0] _probe_bits_T_1 = s2_req_addr[11:6]; // @[DCache.scala:339:19, :822:76] wire [25:0] _probe_bits_T_2 = {s2_victim_tag, _probe_bits_T_1}; // @[DCache.scala:433:26, :822:{49,76}] wire [31:0] _probe_bits_T_3 = {_probe_bits_T_2, 6'h0}; // @[DCache.scala:822:{49,96}] wire [31:0] probe_bits_res_address = _probe_bits_T_3; // @[DCache.scala:822:96, :1202:19] wire probeNack; // @[DCache.scala:825:34] wire [3:0] _release_state_T_15 = {1'h0, releaseDone, 2'h3}; // @[Edges.scala:233:22] wire _probeNack_T = ~releaseDone; // @[Edges.scala:233:22] assign probeNack = s2_prb_ack_data \| (\|s2_probe_state_state) \| _probeNack_T; // @[Misc.scala:38:9] wire [3:0] _release_state_T_16 = releaseDone ? 4'h0 : 4'h5; // @[Edges.scala:233:22] assign s1_nack = s2_probe ? probeNack \| _T_60 \| _T_40 \| _T_14 : _T_60 \| _T_40 \| _T_14; // @[DCache.scala:185:28, :276:{39,58,79}, :288:{75,85}, :333:25, :446:{24,82,92}, :571:{18,36,46}, :824:21, :825:34, :839:{24,34}] wire _T_102 = release_state == 4'h4; // @[DCache.scala:228:30, :841:25] assign metaArb_io_in_6_valid = _T_102 \| _metaArb_io_in_6_valid_T_2; // @[DCache.scala:135:28, :769:{26,44}, :841:{25,44}, :842:30] assign metaArb_io_in_6_bits_idx = _T_102 ? _metaArb_io_in_6_bits_idx_T_1 : _metaArb_io_in_6_bits_idx_T; // @[DCache.scala:135:28, :772:29, :841:{25,44}, :843:33, :1200:47] wire [39:0] _metaArb_io_in_6_bits_addr_T_3 = {_metaArb_io_in_6_bits_addr_T_2, probe_bits_address}; // @[DCache.scala:184:29, :844:{40,62}] assign metaArb_io_in_6_bits_addr = _T_102 ? _metaArb_io_in_6_bits_addr_T_3 : _metaArb_io_in_6_bits_addr_T_1; // @[DCache.scala:135:28, :773:{30,36}, :841:{25,44}, :844:{34,40}] wire _T_103 = release_state == 4'h5; // @[DCache.scala:228:30, :850:25] wire _T_104 = release_state == 4'h3; // @[DCache.scala:228:30, :854:25] assign nodeOut_c_valid = _T_104 \| _T_103 \| s2_probe & ~s2_prb_ack_data \| _nodeOut_c_valid_T_6; // @[Misc.scala:38:9] wire _GEN_117 = _T_104 \| ~(~s2_probe \| s2_prb_ack_data \| ~(\|s2_probe_state_state)); // @[Misc.scala:38:9] wire _T_110 = _T_106 \| _T_107 \| _T_111; // @[package.scala:16:47, :81:59] assign nodeOut_c_bits_opcode = _T_110 ? {2'h3, ~_T_111} : {2'h2, _inWriteback_T_1}; // @[package.scala:16:47, :81:59] assign nodeOut_c_bits_param = _T_110 ? (_T_111 ? nodeOut_c_bits_c_param : nodeOut_c_bits_c_1_param) : _inWriteback_T_1 ? dirtyReleaseMessage_param : _GEN_117 ? cleanReleaseMessage_param : 3'h5; // @[package.scala:16:47, :81:59] assign nodeOut_c_bits_size = _T_110 ? 4'h6 : _inWriteback_T_1 ? dirtyReleaseMessage_size : _GEN_117 ? cleanReleaseMessage_size : nackResponseMessage_size; // @[package.scala:16:47, :81:59] assign newCoh_state = _T_110 ? voluntaryNewCoh_state : probeNewCoh_state; // @[package.scala:81:59] assign releaseWay = _T_110 ? s2_victim_or_hit_way : s2_probe_way; // @[package.scala:81:59] wire _dataArb_io_in_2_valid_T = releaseDataBeat < 10'h8; // @[DCache.scala:804:43, :900:60] assign _dataArb_io_in_2_valid_T_1 = inWriteback & _dataArb_io_in_2_valid_T; // @[package.scala:81:59] assign dataArb_io_in_2_valid = _dataArb_io_in_2_valid_T_1; // @[DCache.scala:152:28, :900:41] wire [11:0] _dataArb_io_in_2_bits_addr_T_1 = {_dataArb_io_in_2_bits_addr_T, 6'h0}; // @[DCache.scala:903:55, :1200:47] wire [2:0] _dataArb_io_in_2_bits_addr_T_2 = releaseDataBeat[2:0]; // @[DCache.scala:804:43, :903:90] wire [5:0] _dataArb_io_in_2_bits_addr_T_3 = {_dataArb_io_in_2_bits_addr_T_2, 3'h0}; // @[DCache.scala:903:{90,117}] assign _dataArb_io_in_2_bits_addr_T_4 = {_dataArb_io_in_2_bits_addr_T_1[11:6], _dataArb_io_in_2_bits_addr_T_1[5:0] \| _dataArb_io_in_2_bits_addr_T_3}; // @[DCache.scala:903:{55,72,117}] assign dataArb_io_in_2_bits_addr = _dataArb_io_in_2_bits_addr_T_4; // @[DCache.scala:152:28, :903:72] wire _metaArb_io_in_4_valid_T_1 = release_state == 4'h7; // @[package.scala:16:47] assign _metaArb_io_in_4_valid_T_2 = _metaArb_io_in_4_valid_T \| _metaArb_io_in_4_valid_T_1; // @[package.scala:16:47, :81:59] assign metaArb_io_in_4_valid = _metaArb_io_in_4_valid_T_2; // @[package.scala:81:59] assign metaArb_io_in_4_bits_idx = _metaArb_io_in_4_bits_idx_T; // @[DCache.scala:135:28, :1200:47] wire [11:0] _metaArb_io_in_4_bits_addr_T_1 = probe_bits_address[11:0]; // @[DCache.scala:184:29, :912:90] assign _metaArb_io_in_4_bits_addr_T_2 = {_metaArb_io_in_4_bits_addr_T, _metaArb_io_in_4_bits_addr_T_1}; // @[DCache.scala:912:{36,58,90}] assign metaArb_io_in_4_bits_addr = _metaArb_io_in_4_bits_addr_T_2; // @[DCache.scala:135:28, :912:36] wire [19:0] _metaArb_io_in_4_bits_data_T = nodeOut_c_bits_address[31:12]; // @[DCache.scala:913:78] wire [19:0] metaArb_io_in_4_bits_data_meta_tag = _metaArb_io_in_4_bits_data_T; // @[HellaCache.scala:305:20] assign _metaArb_io_in_4_bits_data_T_1 = {metaArb_io_in_4_bits_data_meta_coh_state, metaArb_io_in_4_bits_data_meta_tag}; // @[HellaCache.scala:305:20] assign metaArb_io_in_4_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97] assign metaArb_io_in_5_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97] assign metaArb_io_in_6_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97] assign metaArb_io_in_7_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97] wire _io_cpu_s2_uncached_T = ~s2_hit; // @[Misc.scala:35:9] assign _io_cpu_s2_uncached_T_1 = s2_uncached & _io_cpu_s2_uncached_T; // @[DCache.scala:424:39, :920:{37,40}] assign io_cpu_s2_uncached_0 = _io_cpu_s2_uncached_T_1; // @[DCache.scala:101:7, :920:37] wire _io_cpu_ordered_T_2 = ~s2_req_no_xcpt; // @[DCache.scala:339:19, :929:72] wire _io_cpu_ordered_T_3 = s2_valid & _io_cpu_ordered_T_2; // @[DCache.scala:331:25, :929:{69,72}] wire _io_cpu_ordered_T_4 = _io_cpu_ordered_T_1 \| _io_cpu_ordered_T_3; // @[DCache.scala:929:{32,57,69}] wire _io_cpu_ordered_T_5 = _io_cpu_ordered_T_4 \| cached_grant_wait; // @[DCache.scala:223:34, :929:{57,94}] wire _io_cpu_ordered_T_7 = _io_cpu_ordered_T_5 \| _io_cpu_ordered_T_6; // @[DCache.scala:929:{94,115,142}] assign _io_cpu_ordered_T_8 = ~_io_cpu_ordered_T_7; // @[DCache.scala:929:{21,115}] assign io_cpu_ordered_0 = _io_cpu_ordered_T_8; // @[DCache.scala:101:7, :929:21] wire _io_cpu_store_pending_T_2 = _io_cpu_store_pending_T \| _io_cpu_store_pending_T_1; // @[Consts.scala:90:{32,42,49}] wire _io_cpu_store_pending_T_4 = _io_cpu_store_pending_T_2 \| _io_cpu_store_pending_T_3; // @[Consts.scala:90:{42,59,66}] wire _io_cpu_store_pending_T_9 = _io_cpu_store_pending_T_5 \| _io_cpu_store_pending_T_6; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_10 = _io_cpu_store_pending_T_9 \| _io_cpu_store_pending_T_7; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_11 = _io_cpu_store_pending_T_10 \| _io_cpu_store_pending_T_8; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_17 = _io_cpu_store_pending_T_12 \| _io_cpu_store_pending_T_13; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_18 = _io_cpu_store_pending_T_17 \| _io_cpu_store_pending_T_14; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_19 = _io_cpu_store_pending_T_18 \| _io_cpu_store_pending_T_15; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_20 = _io_cpu_store_pending_T_19 \| _io_cpu_store_pending_T_16; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_21 = _io_cpu_store_pending_T_11 \| _io_cpu_store_pending_T_20; // @[package.scala:81:59] wire _io_cpu_store_pending_T_22 = _io_cpu_store_pending_T_4 \| _io_cpu_store_pending_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _io_cpu_store_pending_T_23 = cached_grant_wait & _io_cpu_store_pending_T_22; // @[DCache.scala:223:34, :930:46] assign _io_cpu_store_pending_T_25 = _io_cpu_store_pending_T_23 \| _io_cpu_store_pending_T_24; // @[DCache.scala:930:{46,70,97}] assign io_cpu_store_pending_0 = _io_cpu_store_pending_T_25; // @[DCache.scala:101:7, :930:70] wire _s1_xcpt_valid_T_2 = ~s1_nack; // @[DCache.scala:185:28, :187:41, :932:68] wire s1_xcpt_valid = _s1_xcpt_valid_T_1 & _s1_xcpt_valid_T_2; // @[DCache.scala:932:{40,65,68}] reg io_cpu_s2_xcpt_REG; // @[DCache.scala:933:32] wire _io_cpu_s2_xcpt_T_miss = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_miss; // @[DCache.scala:342:24, :933:{24,32}] wire [31:0] _io_cpu_s2_xcpt_T_paddr = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_paddr : 32'h0; // @[DCache.scala:342:24, :933:{24,32}] wire [39:0] _io_cpu_s2_xcpt_T_gpa = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_gpa : 40'h0; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_pf_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_ld; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_pf_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_st; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_pf_inst = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_inst; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_ae_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_ld; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_ae_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_st; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_ae_inst = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_inst; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_ma_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ma_ld; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_ma_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ma_st; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_cacheable = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_cacheable; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_must_alloc = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_must_alloc; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_prefetchable = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_prefetchable; // @[DCache.scala:342:24, :933:{24,32}] wire [1:0] _io_cpu_s2_xcpt_T_size = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_size : 2'h0; // @[DCache.scala:342:24, :933:{24,32}] wire [4:0] _io_cpu_s2_xcpt_T_cmd = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_cmd : 5'h0; // @[DCache.scala:342:24, :933:{24,32}] assign io_cpu_s2_xcpt_pf_ld_0 = _io_cpu_s2_xcpt_T_pf_ld; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_pf_st_0 = _io_cpu_s2_xcpt_T_pf_st; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_ae_ld_0 = _io_cpu_s2_xcpt_T_ae_ld; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_ae_st_0 = _io_cpu_s2_xcpt_T_ae_st; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_ma_ld_0 = _io_cpu_s2_xcpt_T_ma_ld; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_ma_st_0 = _io_cpu_s2_xcpt_T_ma_st; // @[DCache.scala:101:7, :933:24] reg [63:0] s2_uncached_data_word; // @[DCache.scala:947:40] reg doUncachedResp; // @[DCache.scala:948:31] assign io_cpu_resp_bits_replay_0 = doUncachedResp; // @[DCache.scala:101:7, :948:31] wire _io_cpu_resp_valid_T = s2_valid_hit_pre_data_ecc \| doUncachedResp; // @[DCache.scala:420:69, :948:31, :949:51] assign _io_cpu_resp_valid_T_2 = _io_cpu_resp_valid_T; // @[DCache.scala:949:{51,70}] assign io_cpu_resp_valid_0 = _io_cpu_resp_valid_T_2; // @[DCache.scala:101:7, :949:70] wire _io_cpu_replay_next_T_1 = _io_cpu_replay_next_T & grantIsUncachedData; // @[Decoupled.scala:51:35] assign _io_cpu_replay_next_T_3 = _io_cpu_replay_next_T_1; // @[DCache.scala:950:{39,62}] assign io_cpu_replay_next_0 = _io_cpu_replay_next_T_3; // @[DCache.scala:101:7, :950:62]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_29( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_54 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_72 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_74 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_78 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_80 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_84 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_86 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_90 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_92 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_12 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_13 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'hB; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_31 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_37 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = _source_ok_T_31 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_38 = _source_ok_T_37 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire _source_ok_T_43 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire _source_ok_T_44 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_50 = _source_ok_T_49 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_50 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_20 = _uncommonBits_T_20[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_26 = _uncommonBits_T_26[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_27 = _uncommonBits_T_27[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_32 = _uncommonBits_T_32[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_33 = _uncommonBits_T_33[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_55 = _uncommonBits_T_55[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_60 = _uncommonBits_T_60[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_61 = _uncommonBits_T_61[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_62 = _uncommonBits_T_62[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_67 = _uncommonBits_T_67[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_68 = _uncommonBits_T_68[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_75 = _uncommonBits_T_75[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_76 = _uncommonBits_T_76[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_51 = io_in_d_bits_source_0 == 7'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_51; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_52 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_58 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_64 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_70 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_53 = _source_ok_T_52 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_55 = _source_ok_T_53; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_57; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_59 = _source_ok_T_58 == 5'h9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_65 = _source_ok_T_64 == 5'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_69; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_71 = _source_ok_T_70 == 5'hB; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_73 = _source_ok_T_71; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_75 = _source_ok_T_73; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_75; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_76 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_82 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_88 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_77 = _source_ok_T_76 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_79 = _source_ok_T_77; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_81 = _source_ok_T_79; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_81; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_83 = _source_ok_T_82 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_85 = _source_ok_T_83; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_87 = _source_ok_T_85; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_6 = _source_ok_T_87; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_89 = _source_ok_T_88 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_91 = _source_ok_T_89; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_93 = _source_ok_T_91; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_7 = _source_ok_T_93; // @[Parameters.scala:1138:31] wire _source_ok_T_94 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_94; // @[Parameters.scala:1138:31] wire _source_ok_T_95 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_96 = _source_ok_T_95 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_97 = _source_ok_T_96 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_98 = _source_ok_T_97 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_99 = _source_ok_T_98 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_100 = _source_ok_T_99 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_101 = _source_ok_T_100 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_101 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1266 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1266; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1266; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_1339 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1339; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1339; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1339; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1192 = _T_1266 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1192 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1192 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1192 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1192 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1192 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1238 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1238 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1207 = _T_1339 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1207 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1207 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1207 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1310 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1310 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1292 = _T_1339 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1292 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1292 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1292 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File TilelinkAdapters.scala: package constellation.protocol import chisel3._ import chisel3.util._ import constellation.channel._ import constellation.noc._ import constellation.soc.{CanAttachToGlobalNoC} import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import scala.collection.immutable.{ListMap} abstract class TLChannelToNoC[T <: TLChannel](gen: => T, edge: TLEdge, idToEgress: Int => Int)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Flipped(Decoupled(gen)) val flit = Decoupled(new IngressFlit(flitWidth)) }) def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B // convert decoupled to irrevocable val q = Module(new Queue(gen, 1, pipe=true, flow=true)) val protocol = q.io.deq val has_body = Wire(Bool()) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val head = edge.first(protocol.bits, protocol.fire) val tail = edge.last(protocol.bits, protocol.fire) def requestOH: Seq[Bool] val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt)) val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt)) val is_body = RegInit(false.B) io.flit.valid := protocol.valid protocol.ready := io.flit.ready && (is_body \|\| !has_body) io.flit.bits.head := head && !is_body io.flit.bits.tail := tail && (is_body \|\| !has_body) io.flit.bits.egress_id := Mux1H(requestOH.zipWithIndex.map { case (r, i) => r -> idToEgress(i).U }) io.flit.bits.payload := Mux(is_body, body, const) when (io.flit.fire && io.flit.bits.head) { is_body := true.B } when (io.flit.fire && io.flit.bits.tail) { is_body := false.B } } abstract class TLChannelFromNoC[T <: TLChannel](gen: => T)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Decoupled(gen) val flit = Flipped(Decoupled(new EgressFlit(flitWidth))) }) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) val protocol = Wire(Decoupled(gen)) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val is_const = RegInit(true.B) val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W)) val const = Mux(io.flit.bits.head, io.flit.bits.payload, const_reg) io.flit.ready := (is_const && !io.flit.bits.tail) \|\| protocol.ready protocol.valid := (!is_const \|\| io.flit.bits.tail) && io.flit.valid def assign(i: UInt, sigs: Seq[Data]) = { var t = i for (s <- sigs.reverse) { s := t.asTypeOf(s.cloneType) t = t >> s.getWidth } } assign(const, const_fields) assign(io.flit.bits.payload, body_fields) when (io.flit.fire && io.flit.bits.head) { is_const := false.B; const_reg := io.flit.bits.payload } when (io.flit.fire && io.flit.bits.tail) { is_const := true.B } } trait HasAddressDecoder { // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) val edgeIn: TLEdge val edgesOut: Seq[TLEdge] lazy val reacheableIO = edgesOut.map { mp => edgeIn.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} }.toVector lazy val releaseIO = (edgesOut zip reacheableIO).map { case (mp, reachable) => reachable && edgeIn.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector def outputPortFn(connectIO: Seq[Boolean]) = { val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectIO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_\|\|_)) } } class TLAToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToAEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleA(bundle), edgeIn, slaveToAEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) \|\| (~protocol.bits.mask =/= 0.U) lazy val connectAIO = reacheableIO lazy val requestOH = outputPortFn(connectAIO).zipWithIndex.map { case (o, j) => connectAIO(j).B && (unique(connectAIO) \|\| o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source \| sourceStart.U } class TLAFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleA(bundle))(p) { io.protocol <> protocol when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLBToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToBIngress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleB(bundle), edgeOut, masterToBIngress)(p) { has_body := edgeOut.hasData(protocol.bits) \|\| (~protocol.bits.mask =/= 0.U) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol } class TLBFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleB(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLCToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToCEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleC(bundle), edgeIn, slaveToCEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) lazy val connectCIO = releaseIO lazy val requestOH = outputPortFn(connectCIO).zipWithIndex.map { case (o, j) => connectCIO(j).B && (unique(connectCIO) \|\| o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source \| sourceStart.U } class TLCFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleC(bundle))(p) { io.protocol <> protocol } class TLDToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToDIngress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleD(bundle), edgeOut, masterToDIngress)(p) { has_body := edgeOut.hasData(protocol.bits) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol q.io.enq.bits.sink := io.protocol.bits.sink \| sourceStart.U } class TLDFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleD(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) } class TLEToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToEEgress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleE(bundle), edgeIn, slaveToEEgress)(p) { has_body := edgeIn.hasData(protocol.bits) lazy val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) lazy val requestOH = outputIdRanges.map { o => o.contains(protocol.bits.sink) } q.io.enq <> io.protocol } class TLEFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleE(bundle))(p) { io.protocol <> protocol io.protocol.bits.sink := trim(protocol.bits.sink, sourceSize) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLDToNoC_3( // @[TilelinkAdapters.scala:171:7] input clock, // @[TilelinkAdapters.scala:171:7] input reset, // @[TilelinkAdapters.scala:171:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [1:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [4:0] io_protocol_bits_sink, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_denied, // @[TilelinkAdapters.scala:19:14] input [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [64:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [3:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [1:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [5:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [4:0] _q_io_deq_bits_sink; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_denied; // @[TilelinkAdapters.scala:26:17] wire [63:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [20:0] _tail_beats1_decode_T = 21'h3F << _q_io_deq_bits_size; // @[package.scala:243:71] reg [2:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire [2:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[5:3]) : 3'h0; // @[package.scala:243:{46,71,76}] reg [2:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire q_io_deq_ready = io_flit_ready & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:106:36] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 3'h1 \| tail_beats1 == 3'h0) & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:106:36, :221:14, :229:27, :232:{25,33,43}] wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:171:7] if (reset) begin // @[TilelinkAdapters.scala:171:7] head_counter <= 3'h0; // @[Edges.scala:229:27] tail_counter <= 3'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :171:7] end else begin // @[TilelinkAdapters.scala:171:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[5:3]) : 3'h0) : head_counter - 3'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 3'h0 ? tail_beats1 : tail_counter - 3'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 \| is_body); // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /* * Object to get the FP rounding mode out of a packed immediate. / object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /* * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) / object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File tage.scala: package boom.v3.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc} import scala.math.min class TageResp extends Bundle { val ctr = UInt(3.W) val u = UInt(2.W) } class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int) (implicit p: Parameters) extends BoomModule()(p) with HasBoomFrontendParameters { require(histLength <= globalHistoryLength) val nWrBypassEntries = 2 val io = IO( new Bundle { val f1_req_valid = Input(Bool()) val f1_req_pc = Input(UInt(vaddrBitsExtended.W)) val f1_req_ghist = Input(UInt(globalHistoryLength.W)) val f3_resp = Output(Vec(bankWidth, Valid(new TageResp))) val update_mask = Input(Vec(bankWidth, Bool())) val update_taken = Input(Vec(bankWidth, Bool())) val update_alloc = Input(Vec(bankWidth, Bool())) val update_old_ctr = Input(Vec(bankWidth, UInt(3.W))) val update_pc = Input(UInt()) val update_hist = Input(UInt()) val update_u_mask = Input(Vec(bankWidth, Bool())) val update_u = Input(Vec(bankWidth, UInt(2.W))) }) def compute_folded_hist(hist: UInt, l: Int) = { val nChunks = (histLength + l - 1) / l val hist_chunks = (0 until nChunks) map {i => hist(min((i+1)l, histLength)-1, il) } hist_chunks.reduce(_^_) } def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = { val idx_history = compute_folded_hist(hist, log2Ceil(nRows)) val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0) val tag_history = compute_folded_hist(hist, tagSz) val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0) (idx, tag) } def inc_ctr(ctr: UInt, taken: Bool): UInt = { Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U), Mux(ctr === 7.U, 7.U, ctr + 1.U)) } val doing_reset = RegInit(true.B) val reset_idx = RegInit(0.U(log2Ceil(nRows).W)) reset_idx := reset_idx + doing_reset when (reset_idx === (nRows-1).U) { doing_reset := false.B } class TageEntry extends Bundle { val valid = Bool() // TODO: Remove this valid bit val tag = UInt(tagSz.W) val ctr = UInt(3.W) } val tageEntrySz = 1 + tagSz + 3 val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist) val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool())) val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool())) val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W))) val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz)) val s2_tag = RegNext(s1_tag) val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry))) val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid) val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid) val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset)) for (w <- 0 until bankWidth) { // This bit indicates the TAGE table matched here io.f3_resp(w).valid := RegNext(s2_req_rhits(w)) io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w))) io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr) } val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W)) when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U } val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod) val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist) val update_wdata = Wire(Vec(bankWidth, new TageEntry)) table.write( Mux(doing_reset, reset_idx , update_idx), Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))), Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools ) val update_hi_wdata = Wire(Vec(bankWidth, Bool())) hi_us.write( Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)), Mux(doing_reset \|\| doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata), Mux(doing_reset \|\| doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools ) val update_lo_wdata = Wire(Vec(bankWidth, Bool())) lo_us.write( Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)), Mux(doing_reset \|\| doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata), Mux(doing_reset \|\| doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools ) val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W))) val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W))) val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W)))) val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W)) val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i => !doing_reset && wrbypass_tags(i) === update_tag && wrbypass_idxs(i) === update_idx }) val wrbypass_hit = wrbypass_hits.reduce(_\|\|_) val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits) for (w <- 0 until bankWidth) { update_wdata(w).ctr := Mux(io.update_alloc(w), Mux(io.update_taken(w), 4.U, 3.U ), Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)), inc_ctr(io.update_old_ctr(w), io.update_taken(w)) ) ) update_wdata(w).valid := true.B update_wdata(w).tag := update_tag update_hi_wdata(w) := io.update_u(w)(1) update_lo_wdata(w) := io.update_u(w)(0) } when (io.update_mask.reduce(_\|\|_)) { when (wrbypass_hits.reduce(_\|\|_)) { wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr)) } .otherwise { wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr)) wrbypass_tags(wrbypass_enq_idx) := update_tag wrbypass_idxs(wrbypass_enq_idx) := update_idx wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries) } } } case class BoomTageParams( // nSets, histLen, tagSz tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7), ( 128, 4, 7), ( 256, 8, 8), ( 256, 16, 8), ( 128, 32, 9), ( 128, 64, 9)), uBitPeriod: Int = 2048 ) class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p) { val tageUBitPeriod = params.uBitPeriod val tageNTables = params.tableInfo.size class TageMeta extends Bundle { val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W))) val alt_differs = Vec(bankWidth, Output(Bool())) val provider_u = Vec(bankWidth, Output(UInt(2.W))) val provider_ctr = Vec(bankWidth, Output(UInt(3.W))) val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W))) } val f3_meta = Wire(new TageMeta) override val metaSz = f3_meta.asUInt.getWidth require(metaSz <= bpdMaxMetaLength) def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = { Mux(!alt_differs, u, Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U), Mux(u === 3.U, 3.U, u + 1.U))) } val tt = params.tableInfo map { case (n, l, s) => { val t = Module(new TageTable(n, s, l, params.uBitPeriod)) t.io.f1_req_valid := RegNext(io.f0_valid) t.io.f1_req_pc := RegNext(io.f0_pc) t.io.f1_req_ghist := io.f1_ghist (t, t.mems) } } val tables = tt.map(_._1) val mems = tt.map(_._2).flatten val f3_resps = VecInit(tables.map(_.io.f3_resp)) val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta) val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) & Fill(bankWidth, s1_update.bits.cfi_mispredicted) val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool())))) val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W))))) val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool()))) val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W)))) val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool()))) val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W)))) s1_update_taken := DontCare s1_update_old_ctr := DontCare s1_update_alloc := DontCare s1_update_u := DontCare for (w <- 0 until bankWidth) { var altpred = io.resp_in(0).f3(w).taken val final_altpred = WireInit(io.resp_in(0).f3(w).taken) var provided = false.B var provider = 0.U io.resp.f3(w).taken := io.resp_in(0).f3(w).taken for (i <- 0 until tageNTables) { val hit = f3_resps(i)(w).valid val ctr = f3_resps(i)(w).bits.ctr when (hit) { io.resp.f3(w).taken := Mux(ctr === 3.U \|\| ctr === 4.U, altpred, ctr(2)) final_altpred := altpred } provided = provided \|\| hit provider = Mux(hit, i.U, provider) altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred) } f3_meta.provider(w).valid := provided f3_meta.provider(w).bits := provider f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr // Create a mask of tables which did not hit our query, and also contain useless entries // and also uses a longer history than the provider val allocatable_slots = ( VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt & ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided)) ) val alloc_lfsr = random.LFSR(tageNTables max 2) val first_entry = PriorityEncoder(allocatable_slots) val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr) val alloc_entry = Mux(allocatable_slots(masked_entry), masked_entry, first_entry) f3_meta.allocate(w).valid := allocatable_slots =/= 0.U f3_meta.allocate(w).bits := alloc_entry val update_was_taken = (s1_update.bits.cfi_idx.valid && (s1_update.bits.cfi_idx.bits === w.U) && s1_update.bits.cfi_taken) when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) { when (s1_update_meta.provider(w).valid) { val provider = s1_update_meta.provider(w).bits s1_update_mask(provider)(w) := true.B s1_update_u_mask(provider)(w) := true.B val new_u = inc_u(s1_update_meta.provider_u(w), s1_update_meta.alt_differs(w), s1_update_mispredict_mask(w)) s1_update_u (provider)(w) := new_u s1_update_taken (provider)(w) := update_was_taken s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w) s1_update_alloc (provider)(w) := false.B } } } when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) { val idx = s1_update.bits.cfi_idx.bits val allocate = s1_update_meta.allocate(idx) when (allocate.valid) { s1_update_mask (allocate.bits)(idx) := true.B s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken s1_update_alloc(allocate.bits)(idx) := true.B s1_update_u_mask(allocate.bits)(idx) := true.B s1_update_u (allocate.bits)(idx) := 0.U } .otherwise { val provider = s1_update_meta.provider(idx) val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U) for (i <- 0 until tageNTables) { when (decr_mask(i)) { s1_update_u_mask(i)(idx) := true.B s1_update_u (i)(idx) := 0.U } } } } for (i <- 0 until tageNTables) { for (w <- 0 until bankWidth) { tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w)) tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w)) tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w)) tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w)) tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w)) tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w)) } tables(i).io.update_pc := RegNext(s1_update.bits.pc) tables(i).io.update_hist := RegNext(s1_update.bits.ghist) } //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0)) io.f3_meta := f3_meta.asUInt }	module TageTable_6( // @[tage.scala:24:7] input clock, // @[tage.scala:24:7] input reset, // @[tage.scala:24:7] input io_f1_req_valid, // @[tage.scala:31:14] input [39:0] io_f1_req_pc, // @[tage.scala:31:14] input [63:0] io_f1_req_ghist, // @[tage.scala:31:14] output io_f3_resp_0_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_0_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_0_bits_u, // @[tage.scala:31:14] output io_f3_resp_1_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_1_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_1_bits_u, // @[tage.scala:31:14] output io_f3_resp_2_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_2_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_2_bits_u, // @[tage.scala:31:14] output io_f3_resp_3_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_3_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_3_bits_u, // @[tage.scala:31:14] input io_update_mask_0, // @[tage.scala:31:14] input io_update_mask_1, // @[tage.scala:31:14] input io_update_mask_2, // @[tage.scala:31:14] input io_update_mask_3, // @[tage.scala:31:14] input io_update_taken_0, // @[tage.scala:31:14] input io_update_taken_1, // @[tage.scala:31:14] input io_update_taken_2, // @[tage.scala:31:14] input io_update_taken_3, // @[tage.scala:31:14] input io_update_alloc_0, // @[tage.scala:31:14] input io_update_alloc_1, // @[tage.scala:31:14] input io_update_alloc_2, // @[tage.scala:31:14] input io_update_alloc_3, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_0, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_1, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_2, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_3, // @[tage.scala:31:14] input [39:0] io_update_pc, // @[tage.scala:31:14] input [63:0] io_update_hist, // @[tage.scala:31:14] input io_update_u_mask_0, // @[tage.scala:31:14] input io_update_u_mask_1, // @[tage.scala:31:14] input io_update_u_mask_2, // @[tage.scala:31:14] input io_update_u_mask_3, // @[tage.scala:31:14] input [1:0] io_update_u_0, // @[tage.scala:31:14] input [1:0] io_update_u_1, // @[tage.scala:31:14] input [1:0] io_update_u_2, // @[tage.scala:31:14] input [1:0] io_update_u_3 // @[tage.scala:31:14] ); wire lo_us_MPORT_2_data_3; // @[tage.scala:137:8] wire lo_us_MPORT_2_data_2; // @[tage.scala:137:8] wire lo_us_MPORT_2_data_1; // @[tage.scala:137:8] wire lo_us_MPORT_2_data_0; // @[tage.scala:137:8] wire hi_us_MPORT_1_data_3; // @[tage.scala:130:8] wire hi_us_MPORT_1_data_2; // @[tage.scala:130:8] wire hi_us_MPORT_1_data_1; // @[tage.scala:130:8] wire hi_us_MPORT_1_data_0; // @[tage.scala:130:8] wire [10:0] table_MPORT_data_3; // @[tage.scala:123:8] wire [10:0] table_MPORT_data_2; // @[tage.scala:123:8] wire [10:0] table_MPORT_data_1; // @[tage.scala:123:8] wire [10:0] table_MPORT_data_0; // @[tage.scala:123:8] wire _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:87] wire _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:87] wire _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:87] wire _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:87] wire [43:0] _table_R0_data; // @[tage.scala:91:27] wire [3:0] _lo_us_R0_data; // @[tage.scala:90:27] wire [3:0] _hi_us_R0_data; // @[tage.scala:89:27] wire io_f1_req_valid_0 = io_f1_req_valid; // @[tage.scala:24:7] wire [39:0] io_f1_req_pc_0 = io_f1_req_pc; // @[tage.scala:24:7] wire [63:0] io_f1_req_ghist_0 = io_f1_req_ghist; // @[tage.scala:24:7] wire io_update_mask_0_0 = io_update_mask_0; // @[tage.scala:24:7] wire io_update_mask_1_0 = io_update_mask_1; // @[tage.scala:24:7] wire io_update_mask_2_0 = io_update_mask_2; // @[tage.scala:24:7] wire io_update_mask_3_0 = io_update_mask_3; // @[tage.scala:24:7] wire io_update_taken_0_0 = io_update_taken_0; // @[tage.scala:24:7] wire io_update_taken_1_0 = io_update_taken_1; // @[tage.scala:24:7] wire io_update_taken_2_0 = io_update_taken_2; // @[tage.scala:24:7] wire io_update_taken_3_0 = io_update_taken_3; // @[tage.scala:24:7] wire io_update_alloc_0_0 = io_update_alloc_0; // @[tage.scala:24:7] wire io_update_alloc_1_0 = io_update_alloc_1; // @[tage.scala:24:7] wire io_update_alloc_2_0 = io_update_alloc_2; // @[tage.scala:24:7] wire io_update_alloc_3_0 = io_update_alloc_3; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_0_0 = io_update_old_ctr_0; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_1_0 = io_update_old_ctr_1; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_2_0 = io_update_old_ctr_2; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_3_0 = io_update_old_ctr_3; // @[tage.scala:24:7] wire [39:0] io_update_pc_0 = io_update_pc; // @[tage.scala:24:7] wire [63:0] io_update_hist_0 = io_update_hist; // @[tage.scala:24:7] wire io_update_u_mask_0_0 = io_update_u_mask_0; // @[tage.scala:24:7] wire io_update_u_mask_1_0 = io_update_u_mask_1; // @[tage.scala:24:7] wire io_update_u_mask_2_0 = io_update_u_mask_2; // @[tage.scala:24:7] wire io_update_u_mask_3_0 = io_update_u_mask_3; // @[tage.scala:24:7] wire [1:0] io_update_u_0_0 = io_update_u_0; // @[tage.scala:24:7] wire [1:0] io_update_u_1_0 = io_update_u_1; // @[tage.scala:24:7] wire [1:0] io_update_u_2_0 = io_update_u_2; // @[tage.scala:24:7] wire [1:0] io_update_u_3_0 = io_update_u_3; // @[tage.scala:24:7] wire update_wdata_0_valid = 1'h1; // @[tage.scala:119:26] wire update_wdata_1_valid = 1'h1; // @[tage.scala:119:26] wire update_wdata_2_valid = 1'h1; // @[tage.scala:119:26] wire update_wdata_3_valid = 1'h1; // @[tage.scala:119:26] wire [2:0] io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_0_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_0_valid_0; // @[tage.scala:24:7] wire [2:0] io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_1_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_1_valid_0; // @[tage.scala:24:7] wire [2:0] io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_2_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_2_valid_0; // @[tage.scala:24:7] wire [2:0] io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_3_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_3_valid_0; // @[tage.scala:24:7] reg doing_reset; // @[tage.scala:72:28] reg [6:0] reset_idx; // @[tage.scala:73:26] wire [7:0] _reset_idx_T = {1'h0, reset_idx} + {7'h0, doing_reset}; // @[tage.scala:72:28, :73:26, :74:26] wire [6:0] _reset_idx_T_1 = _reset_idx_T[6:0]; // @[tage.scala:74:26] wire [1:0] idx_history = io_f1_req_ghist_0[1:0]; // @[tage.scala:24:7, :53:11] wire [1:0] tag_history = io_f1_req_ghist_0[1:0]; // @[tage.scala:24:7, :53:11] wire [36:0] _idx_T = {io_f1_req_pc_0[39:5], io_f1_req_pc_0[4:3] ^ idx_history}; // @[frontend.scala:162:35] wire [6:0] s1_hashed_idx = _idx_T[6:0]; // @[tage.scala:60:{29,43}] wire [6:0] _s2_req_rtage_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :97:40] wire [6:0] _s2_req_rhius_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :98:32] wire [6:0] _s2_req_rlous_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :99:32] wire [29:0] _tag_T = io_f1_req_pc_0[39:10]; // @[frontend.scala:162:35] wire [29:0] _tag_T_1 = {_tag_T[29:2], _tag_T[1:0] ^ tag_history}; // @[tage.scala:53:11, :62:{30,50}] wire [6:0] s1_tag = _tag_T_1[6:0]; // @[tage.scala:62:{50,64}] wire [10:0] _s2_req_rtage_WIRE_2 = _table_R0_data[10:0]; // @[tage.scala:91:27, :97:87] wire [10:0] _s2_req_rtage_WIRE_4 = _table_R0_data[21:11]; // @[tage.scala:91:27, :97:87] wire [10:0] _s2_req_rtage_WIRE_6 = _table_R0_data[32:22]; // @[tage.scala:91:27, :97:87] wire [10:0] _s2_req_rtage_WIRE_8 = _table_R0_data[43:33]; // @[tage.scala:91:27, :97:87] reg [6:0] s2_tag; // @[tage.scala:95:29] wire _s2_req_rtage_T_2; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_T_1; // @[tage.scala:97:87] wire s2_req_rtage_0_valid = _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T; // @[tage.scala:97:87] wire [6:0] s2_req_rtage_0_tag = _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_0_ctr = _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T = _s2_req_rtage_WIRE_2[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_1_ctr = _s2_req_rtage_T; // @[tage.scala:97:87] assign _s2_req_rtage_T_1 = _s2_req_rtage_WIRE_2[9:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_1_tag = _s2_req_rtage_T_1; // @[tage.scala:97:87] assign _s2_req_rtage_T_2 = _s2_req_rtage_WIRE_2[10]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_1_valid = _s2_req_rtage_T_2; // @[tage.scala:97:87] wire _s2_req_rtage_T_5; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_T_4; // @[tage.scala:97:87] wire s2_req_rtage_1_valid = _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T_3; // @[tage.scala:97:87] wire [6:0] s2_req_rtage_1_tag = _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_1_ctr = _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T_3 = _s2_req_rtage_WIRE_4[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_3_ctr = _s2_req_rtage_T_3; // @[tage.scala:97:87] assign _s2_req_rtage_T_4 = _s2_req_rtage_WIRE_4[9:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_3_tag = _s2_req_rtage_T_4; // @[tage.scala:97:87] assign _s2_req_rtage_T_5 = _s2_req_rtage_WIRE_4[10]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_3_valid = _s2_req_rtage_T_5; // @[tage.scala:97:87] wire _s2_req_rtage_T_8; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_T_7; // @[tage.scala:97:87] wire s2_req_rtage_2_valid = _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T_6; // @[tage.scala:97:87] wire [6:0] s2_req_rtage_2_tag = _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_2_ctr = _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T_6 = _s2_req_rtage_WIRE_6[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_5_ctr = _s2_req_rtage_T_6; // @[tage.scala:97:87] assign _s2_req_rtage_T_7 = _s2_req_rtage_WIRE_6[9:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_5_tag = _s2_req_rtage_T_7; // @[tage.scala:97:87] assign _s2_req_rtage_T_8 = _s2_req_rtage_WIRE_6[10]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_5_valid = _s2_req_rtage_T_8; // @[tage.scala:97:87] wire _s2_req_rtage_T_11; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_T_10; // @[tage.scala:97:87] wire s2_req_rtage_3_valid = _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T_9; // @[tage.scala:97:87] wire [6:0] s2_req_rtage_3_tag = _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_3_ctr = _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T_9 = _s2_req_rtage_WIRE_8[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_7_ctr = _s2_req_rtage_T_9; // @[tage.scala:97:87] assign _s2_req_rtage_T_10 = _s2_req_rtage_WIRE_8[9:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_7_tag = _s2_req_rtage_T_10; // @[tage.scala:97:87] assign _s2_req_rtage_T_11 = _s2_req_rtage_WIRE_8[10]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_7_valid = _s2_req_rtage_T_11; // @[tage.scala:97:87] wire _s2_req_rhits_T = s2_req_rtage_0_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_1 = s2_req_rtage_0_valid & _s2_req_rhits_T; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_2 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_3 = _s2_req_rhits_T_1 & _s2_req_rhits_T_2; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_0 = _s2_req_rhits_T_3; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_4 = s2_req_rtage_1_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_5 = s2_req_rtage_1_valid & _s2_req_rhits_T_4; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_6 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_7 = _s2_req_rhits_T_5 & _s2_req_rhits_T_6; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_1 = _s2_req_rhits_T_7; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_8 = s2_req_rtage_2_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_9 = s2_req_rtage_2_valid & _s2_req_rhits_T_8; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_10 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_11 = _s2_req_rhits_T_9 & _s2_req_rhits_T_10; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_2 = _s2_req_rhits_T_11; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_12 = s2_req_rtage_3_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_13 = s2_req_rtage_3_valid & _s2_req_rhits_T_12; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_14 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_15 = _s2_req_rhits_T_13 & _s2_req_rhits_T_14; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_3 = _s2_req_rhits_T_15; // @[tage.scala:100:{29,80}] reg io_f3_resp_0_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_0_valid_0 = io_f3_resp_0_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_0_bits_u_T = {_hi_us_R0_data[0], _lo_us_R0_data[0]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_0_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_0_bits_u_0 = io_f3_resp_0_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_0_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_0_bits_ctr_0 = io_f3_resp_0_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg io_f3_resp_1_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_1_valid_0 = io_f3_resp_1_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_1_bits_u_T = {_hi_us_R0_data[1], _lo_us_R0_data[1]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_1_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_1_bits_u_0 = io_f3_resp_1_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_1_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_1_bits_ctr_0 = io_f3_resp_1_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg io_f3_resp_2_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_2_valid_0 = io_f3_resp_2_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_2_bits_u_T = {_hi_us_R0_data[2], _lo_us_R0_data[2]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_2_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_2_bits_u_0 = io_f3_resp_2_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_2_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_2_bits_ctr_0 = io_f3_resp_2_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg io_f3_resp_3_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_3_valid_0 = io_f3_resp_3_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_3_bits_u_T = {_hi_us_R0_data[3], _lo_us_R0_data[3]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_3_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_3_bits_u_0 = io_f3_resp_3_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_3_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_3_bits_ctr_0 = io_f3_resp_3_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg [18:0] clear_u_ctr; // @[tage.scala:109:28] wire [19:0] _clear_u_ctr_T = {1'h0, clear_u_ctr} + 20'h1; // @[tage.scala:109:28, :110:85] wire [18:0] _clear_u_ctr_T_1 = _clear_u_ctr_T[18:0]; // @[tage.scala:110:85] wire [10:0] _doing_clear_u_T = clear_u_ctr[10:0]; // @[tage.scala:109:28, :112:34] wire doing_clear_u = _doing_clear_u_T == 11'h0; // @[tage.scala:112:{34,61}] wire _doing_clear_u_hi_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:54] wire _doing_clear_u_lo_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:54, :114:54] wire _doing_clear_u_hi_T_1 = _doing_clear_u_hi_T; // @[tage.scala:113:{54,95}] wire doing_clear_u_hi = doing_clear_u & _doing_clear_u_hi_T_1; // @[tage.scala:112:61, :113:{40,95}] wire _doing_clear_u_lo_T_1 = ~_doing_clear_u_lo_T; // @[tage.scala:114:{54,95}] wire doing_clear_u_lo = doing_clear_u & _doing_clear_u_lo_T_1; // @[tage.scala:112:61, :114:{40,95}] wire [7:0] clear_u_idx = clear_u_ctr[18:11]; // @[tage.scala:109:28, :115:33] wire [1:0] idx_history_1 = io_update_hist_0[1:0]; // @[tage.scala:24:7, :53:11] wire [1:0] tag_history_1 = io_update_hist_0[1:0]; // @[tage.scala:24:7, :53:11] wire [36:0] _idx_T_1 = {io_update_pc_0[39:5], io_update_pc_0[4:3] ^ idx_history_1}; // @[frontend.scala:162:35] wire [6:0] update_idx = _idx_T_1[6:0]; // @[tage.scala:60:{29,43}] wire [29:0] _tag_T_2 = io_update_pc_0[39:10]; // @[frontend.scala:162:35] wire [29:0] _tag_T_3 = {_tag_T_2[29:2], _tag_T_2[1:0] ^ tag_history_1}; // @[tage.scala:53:11, :62:{30,50}] wire [6:0] update_tag = _tag_T_3[6:0]; // @[tage.scala:62:{50,64}] wire [6:0] update_wdata_0_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [6:0] update_wdata_1_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [6:0] update_wdata_2_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [6:0] update_wdata_3_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [2:0] _update_wdata_0_ctr_T_22; // @[tage.scala:155:33] wire [2:0] _update_wdata_1_ctr_T_22; // @[tage.scala:155:33] wire [2:0] _update_wdata_2_ctr_T_22; // @[tage.scala:155:33] wire [2:0] _update_wdata_3_ctr_T_22; // @[tage.scala:155:33] wire [2:0] update_wdata_0_ctr; // @[tage.scala:119:26] wire [2:0] update_wdata_1_ctr; // @[tage.scala:119:26] wire [2:0] update_wdata_2_ctr; // @[tage.scala:119:26] wire [2:0] update_wdata_3_ctr; // @[tage.scala:119:26] wire [7:0] hi = {1'h1, update_wdata_0_tag}; // @[tage.scala:119:26, :123:102] wire [7:0] hi_1 = {1'h1, update_wdata_1_tag}; // @[tage.scala:119:26, :123:102] wire [7:0] hi_2 = {1'h1, update_wdata_2_tag}; // @[tage.scala:119:26, :123:102] wire [7:0] hi_3 = {1'h1, update_wdata_3_tag}; // @[tage.scala:119:26, :123:102] assign table_MPORT_data_0 = doing_reset ? 11'h0 : {hi, update_wdata_0_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] assign table_MPORT_data_1 = doing_reset ? 11'h0 : {hi_1, update_wdata_1_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] assign table_MPORT_data_2 = doing_reset ? 11'h0 : {hi_2, update_wdata_2_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] assign table_MPORT_data_3 = doing_reset ? 11'h0 : {hi_3, update_wdata_3_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] wire [1:0] lo = {io_update_mask_1_0, io_update_mask_0_0}; // @[tage.scala:24:7, :124:90] wire [1:0] hi_4 = {io_update_mask_3_0, io_update_mask_2_0}; // @[tage.scala:24:7, :124:90] wire _update_hi_wdata_0_T; // @[tage.scala:166:44] wire _update_hi_wdata_1_T; // @[tage.scala:166:44] wire _update_hi_wdata_2_T; // @[tage.scala:166:44] wire _update_hi_wdata_3_T; // @[tage.scala:166:44] wire update_hi_wdata_0; // @[tage.scala:127:29] wire update_hi_wdata_1; // @[tage.scala:127:29] wire update_hi_wdata_2; // @[tage.scala:127:29] wire update_hi_wdata_3; // @[tage.scala:127:29] wire _T_20 = doing_reset \| doing_clear_u_hi; // @[tage.scala:72:28, :113:40, :130:21] assign hi_us_MPORT_1_data_0 = ~_T_20 & update_hi_wdata_0; // @[tage.scala:127:29, :130:{8,21}] assign hi_us_MPORT_1_data_1 = ~_T_20 & update_hi_wdata_1; // @[tage.scala:127:29, :130:{8,21}] assign hi_us_MPORT_1_data_2 = ~_T_20 & update_hi_wdata_2; // @[tage.scala:127:29, :130:{8,21}] assign hi_us_MPORT_1_data_3 = ~_T_20 & update_hi_wdata_3; // @[tage.scala:127:29, :130:{8,21}] wire [1:0] _GEN = {io_update_u_mask_1_0, io_update_u_mask_0_0}; // @[tage.scala:24:7, :131:80] wire [1:0] lo_1; // @[tage.scala:131:80] assign lo_1 = _GEN; // @[tage.scala:131:80] wire [1:0] lo_2; // @[tage.scala:138:80] assign lo_2 = _GEN; // @[tage.scala:131:80, :138:80] wire [1:0] _GEN_0 = {io_update_u_mask_3_0, io_update_u_mask_2_0}; // @[tage.scala:24:7, :131:80] wire [1:0] hi_5; // @[tage.scala:131:80] assign hi_5 = _GEN_0; // @[tage.scala:131:80] wire [1:0] hi_6; // @[tage.scala:138:80] assign hi_6 = _GEN_0; // @[tage.scala:131:80, :138:80] wire _update_lo_wdata_0_T; // @[tage.scala:167:44] wire _update_lo_wdata_1_T; // @[tage.scala:167:44] wire _update_lo_wdata_2_T; // @[tage.scala:167:44] wire _update_lo_wdata_3_T; // @[tage.scala:167:44] wire update_lo_wdata_0; // @[tage.scala:134:29] wire update_lo_wdata_1; // @[tage.scala:134:29] wire update_lo_wdata_2; // @[tage.scala:134:29] wire update_lo_wdata_3; // @[tage.scala:134:29] wire _T_33 = doing_reset \| doing_clear_u_lo; // @[tage.scala:72:28, :114:40, :137:21] assign lo_us_MPORT_2_data_0 = ~_T_33 & update_lo_wdata_0; // @[tage.scala:134:29, :137:{8,21}] assign lo_us_MPORT_2_data_1 = ~_T_33 & update_lo_wdata_1; // @[tage.scala:134:29, :137:{8,21}] assign lo_us_MPORT_2_data_2 = ~_T_33 & update_lo_wdata_2; // @[tage.scala:134:29, :137:{8,21}] assign lo_us_MPORT_2_data_3 = ~_T_33 & update_lo_wdata_3; // @[tage.scala:134:29, :137:{8,21}] reg [6:0] wrbypass_tags_0; // @[tage.scala:141:29] reg [6:0] wrbypass_tags_1; // @[tage.scala:141:29] reg [6:0] wrbypass_idxs_0; // @[tage.scala:142:29] reg [6:0] wrbypass_idxs_1; // @[tage.scala:142:29] reg [2:0] wrbypass_0_0; // @[tage.scala:143:29] reg [2:0] wrbypass_0_1; // @[tage.scala:143:29] reg [2:0] wrbypass_0_2; // @[tage.scala:143:29] reg [2:0] wrbypass_0_3; // @[tage.scala:143:29] reg [2:0] wrbypass_1_0; // @[tage.scala:143:29] reg [2:0] wrbypass_1_1; // @[tage.scala:143:29] reg [2:0] wrbypass_1_2; // @[tage.scala:143:29] reg [2:0] wrbypass_1_3; // @[tage.scala:143:29] reg wrbypass_enq_idx; // @[tage.scala:144:33] wire _wrbypass_hits_T = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5] wire _wrbypass_hits_T_1 = wrbypass_tags_0 == update_tag; // @[tage.scala:62:64, :141:29, :148:22] wire _wrbypass_hits_T_2 = _wrbypass_hits_T & _wrbypass_hits_T_1; // @[tage.scala:147:{5,18}, :148:22] wire _wrbypass_hits_T_3 = wrbypass_idxs_0 == update_idx; // @[tage.scala:60:43, :142:29, :149:22] wire _wrbypass_hits_T_4 = _wrbypass_hits_T_2 & _wrbypass_hits_T_3; // @[tage.scala:147:18, :148:37, :149:22] wire wrbypass_hits_0 = _wrbypass_hits_T_4; // @[tage.scala:146:33, :148:37] wire _wrbypass_hits_T_5 = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5] wire _wrbypass_hits_T_6 = wrbypass_tags_1 == update_tag; // @[tage.scala:62:64, :141:29, :148:22] wire _wrbypass_hits_T_7 = _wrbypass_hits_T_5 & _wrbypass_hits_T_6; // @[tage.scala:147:{5,18}, :148:22] wire _wrbypass_hits_T_8 = wrbypass_idxs_1 == update_idx; // @[tage.scala:60:43, :142:29, :149:22] wire _wrbypass_hits_T_9 = _wrbypass_hits_T_7 & _wrbypass_hits_T_8; // @[tage.scala:147:18, :148:37, :149:22] wire wrbypass_hits_1 = _wrbypass_hits_T_9; // @[tage.scala:146:33, :148:37] wire wrbypass_hit = wrbypass_hits_0 \| wrbypass_hits_1; // @[tage.scala:146:33, :151:48] wire wrbypass_hit_idx = ~wrbypass_hits_0; // @[Mux.scala:50:70] wire [2:0] _update_wdata_0_ctr_T = io_update_taken_0_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_0_ctr_T_1 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire [2:0] _GEN_1 = wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0; // @[Mux.scala:50:70] wire [2:0] _GEN_2 = wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1; // @[Mux.scala:50:70] wire [2:0] _GEN_3 = wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2; // @[Mux.scala:50:70] wire [2:0] _GEN_4 = wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3; // @[Mux.scala:50:70] wire _update_wdata_0_ctr_T_2 = _GEN_1 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_5 = {1'h0, _GEN_1}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_0_ctr_T_3 = _GEN_5 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_4 = _update_wdata_0_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_5 = _update_wdata_0_ctr_T_2 ? 3'h0 : _update_wdata_0_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_6 = &_GEN_1; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_0_ctr_T_7 = _GEN_5 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_8 = _update_wdata_0_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_9 = _update_wdata_0_ctr_T_6 ? 3'h7 : _update_wdata_0_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_10 = _update_wdata_0_ctr_T_1 ? _update_wdata_0_ctr_T_5 : _update_wdata_0_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_0_ctr_T_11 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_0_ctr_T_12 = io_update_old_ctr_0_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_6 = {1'h0, io_update_old_ctr_0_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_0_ctr_T_13 = _GEN_6 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_14 = _update_wdata_0_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_15 = _update_wdata_0_ctr_T_12 ? 3'h0 : _update_wdata_0_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_16 = &io_update_old_ctr_0_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_0_ctr_T_17 = _GEN_6 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_18 = _update_wdata_0_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_19 = _update_wdata_0_ctr_T_16 ? 3'h7 : _update_wdata_0_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_20 = _update_wdata_0_ctr_T_11 ? _update_wdata_0_ctr_T_15 : _update_wdata_0_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_0_ctr_T_21 = wrbypass_hit ? _update_wdata_0_ctr_T_10 : _update_wdata_0_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_0_ctr_T_22 = io_update_alloc_0_0 ? _update_wdata_0_ctr_T : _update_wdata_0_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_0_ctr = _update_wdata_0_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_0_T = io_update_u_0_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_0 = _update_hi_wdata_0_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_0_T = io_update_u_0_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_0 = _update_lo_wdata_0_T; // @[tage.scala:134:29, :167:44] wire [2:0] _update_wdata_1_ctr_T = io_update_taken_1_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_1_ctr_T_1 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_2 = _GEN_2 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_7 = {1'h0, _GEN_2}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_1_ctr_T_3 = _GEN_7 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_4 = _update_wdata_1_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_5 = _update_wdata_1_ctr_T_2 ? 3'h0 : _update_wdata_1_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_6 = &_GEN_2; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_1_ctr_T_7 = _GEN_7 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_8 = _update_wdata_1_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_9 = _update_wdata_1_ctr_T_6 ? 3'h7 : _update_wdata_1_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_10 = _update_wdata_1_ctr_T_1 ? _update_wdata_1_ctr_T_5 : _update_wdata_1_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_1_ctr_T_11 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_12 = io_update_old_ctr_1_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_8 = {1'h0, io_update_old_ctr_1_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_1_ctr_T_13 = _GEN_8 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_14 = _update_wdata_1_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_15 = _update_wdata_1_ctr_T_12 ? 3'h0 : _update_wdata_1_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_16 = &io_update_old_ctr_1_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_1_ctr_T_17 = _GEN_8 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_18 = _update_wdata_1_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_19 = _update_wdata_1_ctr_T_16 ? 3'h7 : _update_wdata_1_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_20 = _update_wdata_1_ctr_T_11 ? _update_wdata_1_ctr_T_15 : _update_wdata_1_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_1_ctr_T_21 = wrbypass_hit ? _update_wdata_1_ctr_T_10 : _update_wdata_1_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_1_ctr_T_22 = io_update_alloc_1_0 ? _update_wdata_1_ctr_T : _update_wdata_1_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_1_ctr = _update_wdata_1_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_1_T = io_update_u_1_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_1 = _update_hi_wdata_1_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_1_T = io_update_u_1_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_1 = _update_lo_wdata_1_T; // @[tage.scala:134:29, :167:44] wire [2:0] _update_wdata_2_ctr_T = io_update_taken_2_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_2_ctr_T_1 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_2 = _GEN_3 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_9 = {1'h0, _GEN_3}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_2_ctr_T_3 = _GEN_9 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_4 = _update_wdata_2_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_5 = _update_wdata_2_ctr_T_2 ? 3'h0 : _update_wdata_2_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_6 = &_GEN_3; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_2_ctr_T_7 = _GEN_9 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_8 = _update_wdata_2_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_9 = _update_wdata_2_ctr_T_6 ? 3'h7 : _update_wdata_2_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_10 = _update_wdata_2_ctr_T_1 ? _update_wdata_2_ctr_T_5 : _update_wdata_2_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_2_ctr_T_11 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_12 = io_update_old_ctr_2_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_10 = {1'h0, io_update_old_ctr_2_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_2_ctr_T_13 = _GEN_10 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_14 = _update_wdata_2_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_15 = _update_wdata_2_ctr_T_12 ? 3'h0 : _update_wdata_2_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_16 = &io_update_old_ctr_2_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_2_ctr_T_17 = _GEN_10 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_18 = _update_wdata_2_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_19 = _update_wdata_2_ctr_T_16 ? 3'h7 : _update_wdata_2_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_20 = _update_wdata_2_ctr_T_11 ? _update_wdata_2_ctr_T_15 : _update_wdata_2_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_2_ctr_T_21 = wrbypass_hit ? _update_wdata_2_ctr_T_10 : _update_wdata_2_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_2_ctr_T_22 = io_update_alloc_2_0 ? _update_wdata_2_ctr_T : _update_wdata_2_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_2_ctr = _update_wdata_2_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_2_T = io_update_u_2_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_2 = _update_hi_wdata_2_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_2_T = io_update_u_2_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_2 = _update_lo_wdata_2_T; // @[tage.scala:134:29, :167:44] wire [2:0] _update_wdata_3_ctr_T = io_update_taken_3_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_3_ctr_T_1 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_2 = _GEN_4 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_11 = {1'h0, _GEN_4}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_3_ctr_T_3 = _GEN_11 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_4 = _update_wdata_3_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_5 = _update_wdata_3_ctr_T_2 ? 3'h0 : _update_wdata_3_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_6 = &_GEN_4; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_3_ctr_T_7 = _GEN_11 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_8 = _update_wdata_3_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_9 = _update_wdata_3_ctr_T_6 ? 3'h7 : _update_wdata_3_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_10 = _update_wdata_3_ctr_T_1 ? _update_wdata_3_ctr_T_5 : _update_wdata_3_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_3_ctr_T_11 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_12 = io_update_old_ctr_3_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_12 = {1'h0, io_update_old_ctr_3_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_3_ctr_T_13 = _GEN_12 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_14 = _update_wdata_3_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_15 = _update_wdata_3_ctr_T_12 ? 3'h0 : _update_wdata_3_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_16 = &io_update_old_ctr_3_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_3_ctr_T_17 = _GEN_12 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_18 = _update_wdata_3_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_19 = _update_wdata_3_ctr_T_16 ? 3'h7 : _update_wdata_3_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_20 = _update_wdata_3_ctr_T_11 ? _update_wdata_3_ctr_T_15 : _update_wdata_3_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_3_ctr_T_21 = wrbypass_hit ? _update_wdata_3_ctr_T_10 : _update_wdata_3_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_3_ctr_T_22 = io_update_alloc_3_0 ? _update_wdata_3_ctr_T : _update_wdata_3_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_3_ctr = _update_wdata_3_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_3_T = io_update_u_3_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_3 = _update_hi_wdata_3_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_3_T = io_update_u_3_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_3 = _update_lo_wdata_3_T; // @[tage.scala:134:29, :167:44] wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1; // @[util.scala:203:14] wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0]; // @[util.scala:203:14] wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1; // @[util.scala:203:{14,20}] wire _T_44 = io_update_mask_0_0 \| io_update_mask_1_0 \| io_update_mask_2_0 \| io_update_mask_3_0; // @[tage.scala:24:7, :170:32] wire _GEN_13 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx; // @[Mux.scala:50:70] wire _GEN_14 = ~_T_44 \| wrbypass_hit \| wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39] wire _GEN_15 = ~_T_44 \| wrbypass_hit \| ~wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39] always @(posedge clock) begin // @[tage.scala:24:7] if (reset) begin // @[tage.scala:24:7] doing_reset <= 1'h1; // @[tage.scala:72:28] reset_idx <= 7'h0; // @[tage.scala:73:26] clear_u_ctr <= 19'h0; // @[tage.scala:109:28] wrbypass_enq_idx <= 1'h0; // @[tage.scala:144:33] end else begin // @[tage.scala:24:7] doing_reset <= reset_idx != 7'h7F & doing_reset; // @[tage.scala:72:28, :73:26, :75:{19,36,50}] reset_idx <= _reset_idx_T_1; // @[tage.scala:73:26, :74:26] clear_u_ctr <= doing_reset ? 19'h1 : _clear_u_ctr_T_1; // @[tage.scala:72:28, :109:28, :110:{22,36,70,85}] if (~_T_44 \| wrbypass_hit) begin // @[tage.scala:143:29, :144:33, :151:48, :170:{32,38}, :171:39] end else // @[tage.scala:144:33, :170:38, :171:39] wrbypass_enq_idx <= _wrbypass_enq_idx_T_2; // @[util.scala:203:20] end s2_tag <= s1_tag; // @[tage.scala:62:64, :95:29] io_f3_resp_0_valid_REG <= s2_req_rhits_0; // @[tage.scala:100:29, :104:38] io_f3_resp_0_bits_u_REG <= _io_f3_resp_0_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_0_bits_ctr_REG <= s2_req_rtage_0_ctr; // @[tage.scala:97:29, :106:38] io_f3_resp_1_valid_REG <= s2_req_rhits_1; // @[tage.scala:100:29, :104:38] io_f3_resp_1_bits_u_REG <= _io_f3_resp_1_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_1_bits_ctr_REG <= s2_req_rtage_1_ctr; // @[tage.scala:97:29, :106:38] io_f3_resp_2_valid_REG <= s2_req_rhits_2; // @[tage.scala:100:29, :104:38] io_f3_resp_2_bits_u_REG <= _io_f3_resp_2_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_2_bits_ctr_REG <= s2_req_rtage_2_ctr; // @[tage.scala:97:29, :106:38] io_f3_resp_3_valid_REG <= s2_req_rhits_3; // @[tage.scala:100:29, :104:38] io_f3_resp_3_bits_u_REG <= _io_f3_resp_3_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_3_bits_ctr_REG <= s2_req_rtage_3_ctr; // @[tage.scala:97:29, :106:38] if (_GEN_14) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39] end else // @[tage.scala:141:29, :170:38, :171:39, :175:39] wrbypass_tags_0 <= update_tag; // @[tage.scala:62:64, :141:29] if (_GEN_15) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39] end else // @[tage.scala:141:29, :170:38, :171:39, :175:39] wrbypass_tags_1 <= update_tag; // @[tage.scala:62:64, :141:29] if (_GEN_14) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39] end else // @[tage.scala:142:29, :170:38, :171:39, :176:39] wrbypass_idxs_0 <= update_idx; // @[tage.scala:60:43, :142:29] if (_GEN_15) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39] end else // @[tage.scala:142:29, :170:38, :171:39, :176:39] wrbypass_idxs_1 <= update_idx; // @[tage.scala:60:43, :142:29] if (~_T_44 \| _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39] end else begin // @[tage.scala:143:29, :170:38, :171:39] wrbypass_0_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29] wrbypass_0_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29] wrbypass_0_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29] wrbypass_0_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29] end if (_T_44 & _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39] wrbypass_1_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29] wrbypass_1_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29] wrbypass_1_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29] wrbypass_1_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29] end always @(posedge) hi_us_5 hi_us ( // @[tage.scala:89:27] .R0_addr (_s2_req_rhius_WIRE), // @[tage.scala:98:32] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_hi_us_R0_data), .W0_addr (doing_reset ? reset_idx : doing_clear_u_hi ? clear_u_idx[6:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :113:40, :115:33, :129:{8,36}] .W0_clk (clock), .W0_data ({hi_us_MPORT_1_data_3, hi_us_MPORT_1_data_2, hi_us_MPORT_1_data_1, hi_us_MPORT_1_data_0}), // @[tage.scala:89:27, :130:8] .W0_mask (_T_20 ? 4'hF : {hi_5, lo_1}) // @[tage.scala:130:21, :131:{8,80}] ); // @[tage.scala:89:27] lo_us_5 lo_us ( // @[tage.scala:90:27] .R0_addr (_s2_req_rlous_WIRE), // @[tage.scala:99:32] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_lo_us_R0_data), .W0_addr (doing_reset ? reset_idx : doing_clear_u_lo ? clear_u_idx[6:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :114:40, :115:33, :136:{8,36}] .W0_clk (clock), .W0_data ({lo_us_MPORT_2_data_3, lo_us_MPORT_2_data_2, lo_us_MPORT_2_data_1, lo_us_MPORT_2_data_0}), // @[tage.scala:90:27, :137:8] .W0_mask (_T_33 ? 4'hF : {hi_6, lo_2}) // @[tage.scala:137:21, :138:{8,80}] ); // @[tage.scala:90:27] table_5 table_0 ( // @[tage.scala:91:27] .R0_addr (_s2_req_rtage_WIRE), // @[tage.scala:97:40] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_table_R0_data), .W0_addr (doing_reset ? reset_idx : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :122:8] .W0_clk (clock), .W0_data ({table_MPORT_data_3, table_MPORT_data_2, table_MPORT_data_1, table_MPORT_data_0}), // @[tage.scala:91:27, :123:8] .W0_mask (doing_reset ? 4'hF : {hi_4, lo}) // @[tage.scala:72:28, :124:{8,90}] ); // @[tage.scala:91:27] assign io_f3_resp_0_valid = io_f3_resp_0_valid_0; // @[tage.scala:24:7] assign io_f3_resp_0_bits_ctr = io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_0_bits_u = io_f3_resp_0_bits_u_0; // @[tage.scala:24:7] assign io_f3_resp_1_valid = io_f3_resp_1_valid_0; // @[tage.scala:24:7] assign io_f3_resp_1_bits_ctr = io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_1_bits_u = io_f3_resp_1_bits_u_0; // @[tage.scala:24:7] assign io_f3_resp_2_valid = io_f3_resp_2_valid_0; // @[tage.scala:24:7] assign io_f3_resp_2_bits_ctr = io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_2_bits_u = io_f3_resp_2_bits_u_0; // @[tage.scala:24:7] assign io_f3_resp_3_valid = io_f3_resp_3_valid_0; // @[tage.scala:24:7] assign io_f3_resp_3_bits_ctr = io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_3_bits_u = io_f3_resp_3_bits_u_0; // @[tage.scala:24:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File MulAddRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //* POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //* UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //* REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero \|\| rawB.isZero \|\| (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign \|\| (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //* NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR \|\| reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) \|\| isSigNaNRawFloat(rawB) \|\| isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN \|\| rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR \|\| CDom_reduced4SigExtra \|\| CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR \|\| notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA \|\| io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd \|\| io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA \|\| io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny \|\| (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) \|\| (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) \|\| (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA \|\| io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB \|\| io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros \|\| (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) \|\| (io.fromPreMul.isInfC && opSignC) \|\| (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) \|\| (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd \|\| opSignC)) \|\| (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }	module MulAddRecFN_e8_s24_17( // @[MulAddRecFN.scala:300:7] input [32:0] io_a, // @[MulAddRecFN.scala:303:16] input [32:0] io_b, // @[MulAddRecFN.scala:303:16] output [32:0] io_out // @[MulAddRecFN.scala:303:16] ); wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15] wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15] wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15] wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15] wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[MulAddRecFN.scala:317:15] wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15] wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15] wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15] wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15] wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7] wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:300:7] wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :317:15, :319:15, :339:15] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15] wire [32:0] io_c = 33'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7] wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7] wire [47:0] _mulAddResult_T = {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[MulAddRecFN.scala:317:15, :327:45] wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50] MulAddRecFNToRaw_preMul_e8_s24_17 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15] .io_a (io_a_0), // @[MulAddRecFN.scala:300:7] .io_b (io_b_0), // @[MulAddRecFN.scala:300:7] .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA), .io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB), .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), .io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), .io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) ); // @[MulAddRecFN.scala:317:15] MulAddRecFNToRaw_postMul_e8_s24_17 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15] .io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15] .io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) ); // @[MulAddRecFN.scala:319:15] RoundRawFNToRecFN_e8_s24_17 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15] .io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15] .io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15] .io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15] .io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15] .io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15] .io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulAddRecFN.scala:339:15] assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_317( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /* TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. / case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_) } def genRegDescsJson(mapping: RegField.Map): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_) } } /* Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. / trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map): Unit = { controlNode.regmap(mapping:_) } } File MuxLiteral.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.log2Ceil import scala.reflect.ClassTag / MuxLiteral creates a lookup table from a key to a list of values. * Unlike MuxLookup, the table keys must be exclusive literals. / object MuxLiteral { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T = MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) }) } object MuxSeq { def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T = MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) }) } object MuxTable { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = { /* All keys must be >= 0 and distinct / cases.foreach { case (k, _) => require (k >= 0) } require (cases.map(_._1).distinct.size == cases.size) / Filter out any cases identical to the default / val simple = cases.filter { case (k, v) => !default.isLit \|\| !v.isLit \|\| v.litValue != default.litValue } val maxKey = (BigInt(0) +: simple.map(_._1)).max val endIndex = BigInt(1) << log2Ceil(maxKey+1) if (simple.isEmpty) { default } else if (endIndex <= 2simple.size) { /* The dense encoding case uses a Vec / val table = Array.fill(endIndex.toInt) { default } simple.foreach { case (k, v) => table(k.toInt) = v } Mux(index >= endIndex.U, default, VecInit(table)(index)) } else { / The sparse encoding case uses switch / val out = WireDefault(default) simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) => acc.is (k.U) { out := v } } out } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File Plic.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.tilelink import chisel3._ import chisel3.experimental._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet} import freechips.rocketchip.resources.{Description, Resource, ResourceBinding, ResourceBindings, ResourceInt, SimpleDevice} import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters} import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldRdAction, RegFieldWrType, RegReadFn, RegWriteFn} import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation} import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode} import freechips.rocketchip.util.{Annotated, MuxT, property} import scala.math.min import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.SeqToAugmentedSeq class GatewayPLICIO extends Bundle { val valid = Output(Bool()) val ready = Input(Bool()) val complete = Input(Bool()) } class LevelGateway extends Module { val io = IO(new Bundle { val interrupt = Input(Bool()) val plic = new GatewayPLICIO }) val inFlight = RegInit(false.B) when (io.interrupt && io.plic.ready) { inFlight := true.B } when (io.plic.complete) { inFlight := false.B } io.plic.valid := io.interrupt && !inFlight } object PLICConsts { def maxDevices = 1023 def maxMaxHarts = 15872 def priorityBase = 0x0 def pendingBase = 0x1000 def enableBase = 0x2000 def hartBase = 0x200000 def claimOffset = 4 def priorityBytes = 4 def enableOffset(i: Int) = i * ((maxDevices+7)/8) def hartOffset(i: Int) = i * 0x1000 def enableBase(i: Int):Int = enableOffset(i) + enableBase def hartBase(i: Int):Int = hartOffset(i) + hartBase def size(maxHarts: Int): Int = { require(maxHarts > 0 && maxHarts <= maxMaxHarts, s"Must be: maxHarts=$maxHarts > 0 && maxHarts <= PLICConsts.maxMaxHarts=${PLICConsts.maxMaxHarts}") 1 << log2Ceil(hartBase(maxHarts)) } require(hartBase >= enableBase(maxMaxHarts)) } case class PLICParams(baseAddress: BigInt = 0xC000000, maxPriorities: Int = 7, intStages: Int = 0, maxHarts: Int = PLICConsts.maxMaxHarts) { require (maxPriorities >= 0) def address = AddressSet(baseAddress, PLICConsts.size(maxHarts)-1) } case object PLICKey extends Field[Option[PLICParams]](None) case class PLICAttachParams( slaveWhere: TLBusWrapperLocation = CBUS ) case object PLICAttachKey extends Field(PLICAttachParams()) /** Platform-Level Interrupt Controller / class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule { // plic0 => max devices 1023 val device: SimpleDevice = new SimpleDevice("interrupt-controller", Seq("riscv,plic0")) { override val alwaysExtended = true override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources) val extra = Map( "interrupt-controller" -> Nil, "riscv,ndev" -> Seq(ResourceInt(nDevices)), "riscv,max-priority" -> Seq(ResourceInt(nPriorities)), "#interrupt-cells" -> Seq(ResourceInt(1))) Description(name, mapping ++ extra) } } val node : TLRegisterNode = TLRegisterNode( address = Seq(params.address), device = device, beatBytes = beatBytes, undefZero = true, concurrency = 1) // limiting concurrency handles RAW hazards on claim registers val intnode: IntNexusNode = IntNexusNode( sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) }, sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, outputRequiresInput = false, inputRequiresOutput = false) / Negotiated sizes / def nDevices: Int = intnode.edges.in.map(_.source.num).sum def minPriorities = min(params.maxPriorities, nDevices) def nPriorities = (1 << log2Ceil(minPriorities+1)) - 1 // round up to next 2^n-1 def nHarts = intnode.edges.out.map(_.source.num).sum // Assign all the devices unique ranges lazy val sources = intnode.edges.in.map(_.source) lazy val flatSources = (sources zip sources.map(_.num).scanLeft(0)(_+_).init).map { case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o))) }.flatten ResourceBinding { flatSources.foreach { s => s.resources.foreach { r => // +1 because interrupt 0 is reserved (s.range.start until s.range.end).foreach { i => r.bind(device, ResourceInt(i+1)) } } } } lazy val module = new Impl class Impl extends LazyModuleImp(this) { Annotated.params(this, params) val (io_devices, edgesIn) = intnode.in.unzip val (io_harts, _) = intnode.out.unzip // Compact the interrupt vector the same way val interrupts = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten // This flattens the harts into an MSMSMSMSMS... or MMMMM.... sequence val harts = io_harts.flatten def getNInterrupts = interrupts.size println(s"Interrupt map (${nHarts} harts ${nDevices} interrupts):") flatSources.foreach { s => // +1 because 0 is reserved, +1-1 because the range is half-open println(s" [${s.range.start+1}, ${s.range.end}] => ${s.name}") } println("") require (nDevices == interrupts.size, s"Must be: nDevices=$nDevices == interrupts.size=${interrupts.size}") require (nHarts == harts.size, s"Must be: nHarts=$nHarts == harts.size=${harts.size}") require(nDevices <= PLICConsts.maxDevices, s"Must be: nDevices=$nDevices <= PLICConsts.maxDevices=${PLICConsts.maxDevices}") require(nHarts > 0 && nHarts <= params.maxHarts, s"Must be: nHarts=$nHarts > 0 && nHarts <= PLICParams.maxHarts=${params.maxHarts}") // For now, use LevelGateways for all TL2 interrupts val gateways = interrupts.map { case i => val gateway = Module(new LevelGateway) gateway.io.interrupt := i gateway.io.plic } val prioBits = log2Ceil(nPriorities+1) val priority = if (nPriorities > 0) Reg(Vec(nDevices, UInt(prioBits.W))) else WireDefault(VecInit.fill(nDevices max 1)(1.U)) val threshold = if (nPriorities > 0) Reg(Vec(nHarts, UInt(prioBits.W))) else WireDefault(VecInit.fill(nHarts)(0.U)) val pending = RegInit(VecInit.fill(nDevices max 1){false.B}) / Construct the enable registers, chunked into 8-bit segments to reduce verilog size / val firstEnable = nDevices min 7 val fullEnables = (nDevices - firstEnable) / 8 val tailEnable = nDevices - firstEnable - 8fullEnables def enableRegs = (Reg(UInt(firstEnable.W)) +: Seq.fill(fullEnables) { Reg(UInt(8.W)) }) ++ (if (tailEnable > 0) Some(Reg(UInt(tailEnable.W))) else None) val enables = Seq.fill(nHarts) { enableRegs } val enableVec = VecInit(enables.map(x => Cat(x.reverse))) val enableVec0 = VecInit(enableVec.map(x => Cat(x, 0.U(1.W)))) val maxDevs = Reg(Vec(nHarts, UInt(log2Ceil(nDevices+1).W))) val pendingUInt = Cat(pending.reverse) if(nDevices > 0) { for (hart <- 0 until nHarts) { val fanin = Module(new PLICFanIn(nDevices, prioBits)) fanin.io.prio := priority fanin.io.ip := enableVec(hart) & pendingUInt maxDevs(hart) := fanin.io.dev harts(hart) := ShiftRegister(RegNext(fanin.io.max) > threshold(hart), params.intStages) } } // Priority registers are 32-bit aligned so treat each as its own group. // Otherwise, the off-by-one nature of the priority registers gets confusing. require(PLICConsts.priorityBytes == 4, s"PLIC Priority register descriptions assume 32-bits per priority, not ${PLICConsts.priorityBytes}") def priorityRegDesc(i: Int) = RegFieldDesc( name = s"priority_$i", desc = s"Acting priority of interrupt source $i", group = Some(s"priority_${i}"), groupDesc = Some(s"Acting priority of interrupt source ${i}"), reset = if (nPriorities > 0) None else Some(1)) def pendingRegDesc(i: Int) = RegFieldDesc( name = s"pending_$i", desc = s"Set to 1 if interrupt source $i is pending, regardless of its enable or priority setting.", group = Some("pending"), groupDesc = Some("Pending Bit Array. 1 Bit for each interrupt source."), volatile = true) def enableRegDesc(i: Int, j: Int, wide: Int) = { val low = if (j == 0) 1 else j8 val high = low + wide - 1 RegFieldDesc( name = s"enables_${j}", desc = s"Targets ${low}-${high}. Set bits to 1 if interrupt should be enabled.", group = Some(s"enables_${i}"), groupDesc = Some(s"Enable bits for each interrupt source for target $i. 1 bit for each interrupt source.")) } def priorityRegField(x: UInt, i: Int) = if (nPriorities > 0) { RegField(prioBits, x, priorityRegDesc(i)) } else { RegField.r(prioBits, x, priorityRegDesc(i)) } val priorityRegFields = priority.zipWithIndex.map { case (p, i) => PLICConsts.priorityBase+PLICConsts.priorityBytes(i+1) -> Seq(priorityRegField(p, i+1)) } val pendingRegFields = Seq(PLICConsts.pendingBase -> (RegField(1) +: pending.zipWithIndex.map { case (b, i) => RegField.r(1, b, pendingRegDesc(i+1))})) val enableRegFields = enables.zipWithIndex.map { case (e, i) => PLICConsts.enableBase(i) -> (RegField(1) +: e.zipWithIndex.map { case (x, j) => RegField(x.getWidth, x, enableRegDesc(i, j, x.getWidth)) }) } // When a hart reads a claim/complete register, then the // device which is currently its highest priority is no longer pending. // This code exploits the fact that, practically, only one claim/complete // register can be read at a time. We check for this because if the address map // were to change, it may no longer be true. // Note: PLIC doesn't care which hart reads the register. val claimer = Wire(Vec(nHarts, Bool())) assert((claimer.asUInt & (claimer.asUInt - 1.U)) === 0.U) // One-Hot val claiming = Seq.tabulate(nHarts){i => Mux(claimer(i), maxDevs(i), 0.U)}.reduceLeft(_\|_) val claimedDevs = VecInit(UIntToOH(claiming, nDevices+1).asBools) ((pending zip gateways) zip claimedDevs.tail) foreach { case ((p, g), c) => g.ready := !p when (c \|\| g.valid) { p := !c } } // When a hart writes a claim/complete register, then // the written device (as long as it is actually enabled for that // hart) is marked complete. // This code exploits the fact that, practically, only one claim/complete register // can be written at a time. We check for this because if the address map // were to change, it may no longer be true. // Note -- PLIC doesn't care which hart writes the register. val completer = Wire(Vec(nHarts, Bool())) assert((completer.asUInt & (completer.asUInt - 1.U)) === 0.U) // One-Hot val completerDev = Wire(UInt(log2Up(nDevices + 1).W)) val completedDevs = Mux(completer.reduce(_ \|\| _), UIntToOH(completerDev, nDevices+1), 0.U) (gateways zip completedDevs.asBools.tail) foreach { case (g, c) => g.complete := c } def thresholdRegDesc(i: Int) = RegFieldDesc( name = s"threshold_$i", desc = s"Interrupt & claim threshold for target $i. Maximum value is ${nPriorities}.", reset = if (nPriorities > 0) None else Some(1)) def thresholdRegField(x: UInt, i: Int) = if (nPriorities > 0) { RegField(prioBits, x, thresholdRegDesc(i)) } else { RegField.r(prioBits, x, thresholdRegDesc(i)) } val hartRegFields = Seq.tabulate(nHarts) { i => PLICConsts.hartBase(i) -> Seq( thresholdRegField(threshold(i), i), RegField(32-prioBits), RegField(32, RegReadFn { valid => claimer(i) := valid (true.B, maxDevs(i)) }, RegWriteFn { (valid, data) => assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0), "completerDev should be consistent for all harts") completerDev := data.extract(log2Ceil(nDevices+1)-1, 0) completer(i) := valid && enableVec0(i)(completerDev) true.B }, Some(RegFieldDesc(s"claim_complete_$i", s"Claim/Complete register for Target $i. Reading this register returns the claimed interrupt number and makes it no longer pending." + s"Writing the interrupt number back completes the interrupt.", reset = None, wrType = Some(RegFieldWrType.MODIFY), rdAction = Some(RegFieldRdAction.MODIFY), volatile = true)) ) ) } node.regmap((priorityRegFields ++ pendingRegFields ++ enableRegFields ++ hartRegFields):_) if (nDevices >= 2) { val claimed = claimer(0) && maxDevs(0) > 0.U val completed = completer(0) property.cover(claimed && RegEnable(claimed, false.B, claimed \|\| completed), "TWO_CLAIMS", "two claims with no intervening complete") property.cover(completed && RegEnable(completed, false.B, claimed \|\| completed), "TWO_COMPLETES", "two completes with no intervening claim") val ep = enables(0).asUInt & pending.asUInt val ep2 = RegNext(ep) val diff = ep & ~ep2 property.cover((diff & (diff - 1.U)) =/= 0.U, "TWO_INTS_PENDING", "two enabled interrupts became pending on same cycle") if (nPriorities > 0) ccover(maxDevs(0) > (1.U << priority(0).getWidth) && maxDevs(0) <= Cat(1.U, threshold(0)), "THRESHOLD", "interrupt pending but less than threshold") } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"PLIC_$label", "Interrupts;;" + desc) } } class PLICFanIn(nDevices: Int, prioBits: Int) extends Module { val io = IO(new Bundle { val prio = Flipped(Vec(nDevices, UInt(prioBits.W))) val ip = Flipped(UInt(nDevices.W)) val dev = UInt(log2Ceil(nDevices+1).W) val max = UInt(prioBits.W) }) def findMax(x: Seq[UInt]): (UInt, UInt) = { if (x.length > 1) { val half = 1 << (log2Ceil(x.length) - 1) val left = findMax(x take half) val right = findMax(x drop half) MuxT(left._1 >= right._1, left, (right._1, half.U \| right._2)) } else (x.head, 0.U) } val effectivePriority = (1.U << prioBits) +: (io.ip.asBools zip io.prio).map { case (p, x) => Cat(p, x) } val (maxPri, maxDev) = findMax(effectivePriority) io.max := maxPri // strips the always-constant high '1' bit io.dev := maxDev } /* Trait that will connect a PLIC to a subsystem / trait CanHavePeripheryPLIC { this: BaseSubsystem => val (plicOpt, plicDomainOpt) = p(PLICKey).map { params => val tlbus = locateTLBusWrapper(p(PLICAttachKey).slaveWhere) val plicDomainWrapper = tlbus.generateSynchronousDomain("PLIC").suggestName("plic_domain") val plic = plicDomainWrapper { LazyModule(new TLPLIC(params, tlbus.beatBytes)) } plicDomainWrapper { plic.node := tlbus.coupleTo("plic") { TLFragmenter(tlbus, Some("PLIC")) := _ } } plicDomainWrapper { plic.intnode := ibus.toPLIC } (plic, plicDomainWrapper) }.unzip }	module TLPLIC( // @[Plic.scala:132:9] input clock, // @[Plic.scala:132:9] input reset, // @[Plic.scala:132:9] input auto_int_in_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_1_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_0_0, // @[LazyModuleImp.scala:107:25] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [12:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [12:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [12:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [22:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire _out_back_front_q_io_deq_valid; // @[RegisterRouter.scala:87:24] wire _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire [22:0] _out_back_front_q_io_deq_bits_index; // @[RegisterRouter.scala:87:24] wire [63:0] _out_back_front_q_io_deq_bits_data; // @[RegisterRouter.scala:87:24] wire [7:0] _out_back_front_q_io_deq_bits_mask; // @[RegisterRouter.scala:87:24] wire _fanin_1_io_dev; // @[Plic.scala:189:27] wire _fanin_1_io_max; // @[Plic.scala:189:27] wire _fanin_io_dev; // @[Plic.scala:189:27] wire _fanin_io_max; // @[Plic.scala:189:27] wire _gateways_gateway_io_plic_valid; // @[Plic.scala:160:27] wire auto_int_in_0_0 = auto_int_in_0; // @[Plic.scala:132:9] wire auto_in_a_valid_0 = auto_in_a_valid; // @[Plic.scala:132:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Plic.scala:132:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Plic.scala:132:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Plic.scala:132:9] wire [12:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Plic.scala:132:9] wire [27:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Plic.scala:132:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Plic.scala:132:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Plic.scala:132:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Plic.scala:132:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Plic.scala:132:9] wire _out_T_73 = reset; // @[Plic.scala:298:19] wire _out_T_109 = reset; // @[Plic.scala:298:19] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire [1:0] auto_in_d_bits_param = 2'h0; // @[Plic.scala:132:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire auto_in_d_bits_sink = 1'h0; // @[Plic.scala:132:9] wire auto_in_d_bits_denied = 1'h0; // @[Plic.scala:132:9] wire auto_in_d_bits_corrupt = 1'h0; // @[Plic.scala:132:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _pending_WIRE_0 = 1'h0; // @[Plic.scala:172:55] wire _out_T_19 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_20 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_prepend_T = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_39 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_40 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_129 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_130 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_6 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_28 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_32 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_40 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_48 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_52 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_56 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_60 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_64 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_66 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_29 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_33 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_41 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_49 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_53 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_57 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_61 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_65 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_67 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_28 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_32 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_40 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_48 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_52 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_56 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_60 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_64 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_66 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_29 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_33 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_41 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_49 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_53 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_57 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_61 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_65 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_67 = 1'h0; // @[MuxLiteral.scala:49:17] wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [63:0] nodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire [2:0] nodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [31:0] _out_prepend_T_7 = 32'h0; // @[RegisterRouter.scala:87:24] wire [22:0] out_maskMatch = 23'h7BF9EF; // @[RegisterRouter.scala:87:24] wire intnodeIn_0 = auto_int_in_0_0; // @[Plic.scala:132:9] wire x1_intnodeOut_0; // @[MixedNode.scala:542:17] wire intnodeOut_0; // @[MixedNode.scala:542:17] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Plic.scala:132:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Plic.scala:132:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Plic.scala:132:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Plic.scala:132:9] wire [12:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Plic.scala:132:9] wire [27:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Plic.scala:132:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Plic.scala:132:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Plic.scala:132:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Plic.scala:132:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Plic.scala:132:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [12:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_int_out_1_0_0; // @[Plic.scala:132:9] wire auto_int_out_0_0_0; // @[Plic.scala:132:9] wire auto_in_a_ready_0; // @[Plic.scala:132:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Plic.scala:132:9] wire [1:0] auto_in_d_bits_size_0; // @[Plic.scala:132:9] wire [12:0] auto_in_d_bits_source_0; // @[Plic.scala:132:9] wire [63:0] auto_in_d_bits_data_0; // @[Plic.scala:132:9] wire auto_in_d_valid_0; // @[Plic.scala:132:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Plic.scala:132:9] wire in_valid = nodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = nodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [12:0] in_bits_extra_tlrr_extra_source = nodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = nodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = nodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = nodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Plic.scala:132:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Plic.scala:132:9] wire [1:0] nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Plic.scala:132:9] wire [12:0] nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Plic.scala:132:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Plic.scala:132:9] wire _intnodeOut_0_T; // @[Plic.scala:193:60] assign auto_int_out_0_0_0 = intnodeOut_0; // @[Plic.scala:132:9] wire _intnodeOut_0_T_1; // @[Plic.scala:193:60] assign auto_int_out_1_0_0 = x1_intnodeOut_0; // @[Plic.scala:132:9] reg priority_0; // @[Plic.scala:167:31] reg threshold_0; // @[Plic.scala:170:31] wire _out_T_95 = threshold_0; // @[RegisterRouter.scala:87:24] reg threshold_1; // @[Plic.scala:170:31] wire _out_T_59 = threshold_1; // @[RegisterRouter.scala:87:24] reg pending_0; // @[Plic.scala:172:26] reg enables_0_0; // @[Plic.scala:178:26] wire enableVec_0 = enables_0_0; // @[Plic.scala:178:26, :182:28] reg enables_1_0; // @[Plic.scala:178:26] wire enableVec_1 = enables_1_0; // @[Plic.scala:178:26, :182:28] wire [1:0] _enableVec0_T = {enableVec_0, 1'h0}; // @[Plic.scala:182:28, :183:52] wire [1:0] enableVec0_0 = _enableVec0_T; // @[Plic.scala:183:{29,52}] wire [1:0] _enableVec0_T_1 = {enableVec_1, 1'h0}; // @[Plic.scala:182:28, :183:52] wire [1:0] enableVec0_1 = _enableVec0_T_1; // @[Plic.scala:183:{29,52}] reg maxDevs_0; // @[Plic.scala:185:22] reg maxDevs_1; // @[Plic.scala:185:22] wire _fanin_io_ip_T = enableVec_0 & pending_0; // @[Plic.scala:172:26, :182:28, :191:40] reg intnodeOut_0_REG; // @[Plic.scala:193:45] assign _intnodeOut_0_T = intnodeOut_0_REG > threshold_0; // @[Plic.scala:170:31, :193:{45,60}] assign intnodeOut_0 = _intnodeOut_0_T; // @[Plic.scala:193:60] wire _fanin_io_ip_T_1 = enableVec_1 & pending_0; // @[Plic.scala:172:26, :182:28, :191:40] reg intnodeOut_0_REG_1; // @[Plic.scala:193:45] assign _intnodeOut_0_T_1 = intnodeOut_0_REG_1 > threshold_1; // @[Plic.scala:170:31, :193:{45,60}] assign x1_intnodeOut_0 = _intnodeOut_0_T_1; // @[Plic.scala:193:60] wire out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_roready_6; // @[RegisterRouter.scala:87:24] wire claimer_0; // @[Plic.scala:250:23] wire claimer_1; // @[Plic.scala:250:23] wire _claiming_T = claimer_0 & maxDevs_0; // @[Plic.scala:185:22, :250:23, :252:49] wire _claiming_T_1 = claimer_1 & maxDevs_1; // @[Plic.scala:185:22, :250:23, :252:49] wire claiming = _claiming_T \| _claiming_T_1; // @[Plic.scala:252:{49,92}] wire claimedDevs_shiftAmount = claiming; // @[OneHot.scala:64:49] wire [1:0] _claimedDevs_T = 2'h1 << claimedDevs_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _claimedDevs_T_1 = _claimedDevs_T; // @[OneHot.scala:65:{12,27}] wire _claimedDevs_T_2 = _claimedDevs_T_1[0]; // @[OneHot.scala:65:27] wire claimedDevs_0 = _claimedDevs_T_2; // @[Plic.scala:253:{30,62}] wire _claimedDevs_T_3 = _claimedDevs_T_1[1]; // @[OneHot.scala:65:27] wire claimedDevs_1 = _claimedDevs_T_3; // @[Plic.scala:253:{30,62}] wire _gateway_io_plic_ready_T = ~pending_0; // @[Plic.scala:172:26, :256:18] wire _pending_0_T = ~claimedDevs_1; // @[Plic.scala:253:30, :257:34] wire _out_completer_0_T_2; // @[Plic.scala:301:35] wire _out_completer_1_T_2; // @[Plic.scala:301:35] wire completer_0; // @[Plic.scala:267:25] wire completer_1; // @[Plic.scala:267:25] wire _out_completerDev_T_1; // @[package.scala:163:13] wire completerDev; // @[Plic.scala:269:28] wire completedDevs_shiftAmount = completerDev; // @[OneHot.scala:64:49] wire _completedDevs_T = completer_0 \| completer_1; // @[Plic.scala:267:25, :270:48] wire [1:0] _completedDevs_T_1 = 2'h1 << completedDevs_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _completedDevs_T_2 = _completedDevs_T_1; // @[OneHot.scala:65:{12,27}] wire [1:0] completedDevs = _completedDevs_T ? _completedDevs_T_2 : 2'h0; // @[OneHot.scala:65:27] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign nodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [22:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [12:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = nodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [24:0] _in_bits_index_T = nodeIn_a_bits_address[27:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[22:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_q_io_deq_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign nodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_12; // @[RegisterRouter.scala:87:24] wire _nodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign nodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] wire out_front_valid; // @[RegisterRouter.scala:87:24] wire [22:0] out_findex = out_front_bits_index & 23'h7BF9EF; // @[RegisterRouter.scala:87:24] wire [22:0] out_bindex = _out_back_front_q_io_deq_bits_index & 23'h7BF9EF; // @[RegisterRouter.scala:87:24] wire _GEN = out_findex == 23'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_T_2; // @[RegisterRouter.scala:87:24] assign _out_T_2 = _GEN; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN; // @[RegisterRouter.scala:87:24] wire _out_T_6; // @[RegisterRouter.scala:87:24] assign _out_T_6 = _GEN; // @[RegisterRouter.scala:87:24] wire _out_T_8; // @[RegisterRouter.scala:87:24] assign _out_T_8 = _GEN; // @[RegisterRouter.scala:87:24] wire _out_T_10; // @[RegisterRouter.scala:87:24] assign _out_T_10 = _GEN; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_bindex == 23'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_3; // @[RegisterRouter.scala:87:24] assign _out_T_3 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_7; // @[RegisterRouter.scala:87:24] assign _out_T_7 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_9; // @[RegisterRouter.scala:87:24] assign _out_T_9 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_11; // @[RegisterRouter.scala:87:24] assign _out_T_11 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_12; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire out_roready_8; // @[RegisterRouter.scala:87:24] wire out_roready_9; // @[RegisterRouter.scala:87:24] wire out_roready_10; // @[RegisterRouter.scala:87:24] wire out_roready_11; // @[RegisterRouter.scala:87:24] wire out_roready_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire out_woready_10; // @[RegisterRouter.scala:87:24] wire out_woready_11; // @[RegisterRouter.scala:87:24] wire out_woready_12; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = _out_back_front_q_io_deq_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = _out_back_front_q_io_deq_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = _out_back_front_q_io_deq_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = _out_back_front_q_io_deq_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = _out_back_front_q_io_deq_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = _out_back_front_q_io_deq_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = _out_back_front_q_io_deq_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = _out_back_front_q_io_deq_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_2 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_2 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_4 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_4 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_7 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_7 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_10 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_10 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_2 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_2 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_4 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_4 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_7 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_7 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_10 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_10 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_13 = out_f_rivalid; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_14 = out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_12 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_32 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_50 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_86 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_122 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_15 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_16 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_17 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_18 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_1 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_1 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_3 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_3 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_11 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_11 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = _out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = _out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire _out_romask_T_1 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_1 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_3 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_3 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_11 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_11 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = _out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = _out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_22 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_23 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_24 = out_f_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire _out_T_25 = out_f_woready_1; // @[RegisterRouter.scala:87:24] wire _out_T_21 = _out_back_front_q_io_deq_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_41 = _out_back_front_q_io_deq_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_131 = _out_back_front_q_io_deq_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_26 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_27 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_28 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_29 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend = {enables_1_0, 1'h0}; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_30 = out_prepend; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_31 = _out_T_30; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = _out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = _out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire out_romask_2 = _out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = _out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_33 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_34 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] wire _out_T_35 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_36 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_37 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_38 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = _out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = _out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire out_romask_3 = _out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = _out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_42 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_43 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] wire _out_T_44 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_45 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_46 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_47 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_1 = {pending_0, 1'h0}; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_48 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_49 = _out_T_48; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = _out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = _out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire out_romask_4 = _out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = _out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_51 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_52 = out_f_roready_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_53 = out_f_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] wire _out_T_54 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_55 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_56 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_57 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_58 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire _out_T_60 = _out_T_59; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_2 = _out_T_60; // @[RegisterRouter.scala:87:24] wire [30:0] _out_rimask_T_5 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_wimask_T_5 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_rimask_T_8 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_wimask_T_8 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = \|_out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire [30:0] _out_romask_T_5 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_womask_T_5 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_romask_T_8 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_womask_T_8 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = \|_out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_62 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_63 = out_f_roready_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_61 = _out_back_front_q_io_deq_bits_data[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_97 = _out_back_front_q_io_deq_bits_data[31:1]; // @[RegisterRouter.scala:87:24] wire _out_T_64 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_65 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_66 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_67 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_2 = {1'h0, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_68 = {30'h0, out_prepend_2}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_69 = _out_T_68; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_3 = _out_T_69; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_6 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_6 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_9 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_9 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = \|_out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_6 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_6 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_9 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_9 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire out_romask_6 = \|_out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_76 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24] assign out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] assign claimer_1 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire _out_T_77 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_78 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] wire _out_T_79 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_70 = _out_back_front_q_io_deq_bits_data[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_106 = _out_back_front_q_io_deq_bits_data[63:32]; // @[RegisterRouter.scala:87:24] wire _out_T_71 = _out_T_70[0]; // @[package.scala:163:13] wire _out_completerDev_T = _out_T_70[0]; // @[package.scala:163:13] wire _out_T_72 = completerDev == _out_T_71; // @[package.scala:163:13] wire _out_T_74 = ~_out_T_73; // @[Plic.scala:298:19] wire _out_T_75 = ~_out_T_72; // @[Plic.scala:298:{19,33}] wire [1:0] _GEN_1 = {1'h0, completerDev}; // @[Plic.scala:269:28, :301:51] wire [1:0] _out_completer_1_T = enableVec0_1 >> _GEN_1; // @[Plic.scala:183:29, :301:51] wire _out_completer_1_T_1 = _out_completer_1_T[0]; // @[Plic.scala:301:51] assign _out_completer_1_T_2 = out_f_woready_6 & _out_completer_1_T_1; // @[RegisterRouter.scala:87:24] assign completer_1 = _out_completer_1_T_2; // @[Plic.scala:267:25, :301:35] wire _out_T_80 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_81 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_82 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_83 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_3 = {maxDevs_1, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_84 = {31'h0, out_prepend_3}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_85 = _out_T_84; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = _out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = _out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire out_romask_7 = _out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = _out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_87 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_88 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_89 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] wire _out_T_90 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire _out_T_91 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_92 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_93 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_94 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire _out_T_96 = _out_T_95; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_4 = _out_T_96; // @[RegisterRouter.scala:87:24] wire out_rimask_8 = \|_out_rimask_T_8; // @[RegisterRouter.scala:87:24] wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24] wire out_romask_8 = \|_out_romask_T_8; // @[RegisterRouter.scala:87:24] wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_98 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_99 = out_f_roready_8; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24] wire out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24] wire _out_T_100 = ~out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_101 = ~out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_102 = ~out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_103 = ~out_womask_8; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_4 = {1'h0, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_104 = {30'h0, out_prepend_4}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_105 = _out_T_104; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_5 = _out_T_105; // @[RegisterRouter.scala:87:24] wire out_rimask_9 = \|_out_rimask_T_9; // @[RegisterRouter.scala:87:24] wire out_wimask_9 = &_out_wimask_T_9; // @[RegisterRouter.scala:87:24] wire out_romask_9 = \|_out_romask_T_9; // @[RegisterRouter.scala:87:24] wire out_womask_9 = &_out_womask_T_9; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_112 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24] assign out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24] assign claimer_0 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire _out_T_113 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_114 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24] wire _out_T_115 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire _out_T_107 = _out_T_106[0]; // @[package.scala:163:13] assign _out_completerDev_T_1 = _out_T_106[0]; // @[package.scala:163:13] wire _out_T_108 = completerDev == _out_T_107; // @[package.scala:163:13] wire _out_T_110 = ~_out_T_109; // @[Plic.scala:298:19] wire _out_T_111 = ~_out_T_108; // @[Plic.scala:298:{19,33}]
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical /) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File RoundAnyRawFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows \| flRoundOpt_subnormsAlwaysExact) ) != 0) \|\| (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) \|\| (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) \|\| (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) \| doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit \|\| anyRoundExtra val roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && roundPosBit) \|\| (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig \| roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 \| Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //* REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //* WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) \|\| adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && unboundedRange_roundPosBit) \|\| (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow \|\| //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow \|\| anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc \|\| io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc \|\| io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow \|\| (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even \|\| roundingMode_near_maxMag \|\| roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp \|\| roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut \|\| (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero \|\| common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) \| Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) \| Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) \| Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) \| Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut \|\| io.in.isZero \|\| common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) \| Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }	module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_85( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 \| _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 \| _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 \| _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 \| _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] \| doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = \|_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = \|_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit \| anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig \| roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = \|_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 \| _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow \| _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow \| anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 \| io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow \| _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut \| _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 \| _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 \| _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut \| io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_487( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_43( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_299 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire \|\| io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) \|\| !io.outCol.fire) assert(!(state === 1.U) \|\| !io.inRow.fire) }	module PE_131( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File regfile.scala: //**************************************************************************** // Copyright (c) 2013 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Register File (Abstract class and Synthesizable RegFile) //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.exu import scala.collection.mutable.ArrayBuffer import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix} / * IO bundle for a register read port * * @param addrWidth size of register address in bits * @param dataWidth size of register in bits / class RegisterFileReadPortIO(val addrWidth: Int, val dataWidth: Int)(implicit p: Parameters) extends BoomBundle { val addr = Input(UInt(addrWidth.W)) val data = Output(UInt(dataWidth.W)) } /* * IO bundle for the register write port * * @param addrWidth size of register address in bits * @param dataWidth size of register in bits / class RegisterFileWritePort(val addrWidth: Int, val dataWidth: Int)(implicit p: Parameters) extends BoomBundle { val addr = UInt(addrWidth.W) val data = UInt(dataWidth.W) } /* * Utility function to turn ExeUnitResps to match the regfile's WritePort I/Os. / object WritePort { def apply(enq: DecoupledIO[ExeUnitResp], addrWidth: Int, dataWidth: Int, rtype: UInt) (implicit p: Parameters): Valid[RegisterFileWritePort] = { val wport = Wire(Valid(new RegisterFileWritePort(addrWidth, dataWidth))) wport.valid := enq.valid && enq.bits.uop.dst_rtype === rtype wport.bits.addr := enq.bits.uop.pdst wport.bits.data := enq.bits.data enq.ready := true.B wport } } /* * Register file abstract class * * @param numRegisters number of registers * @param numReadPorts number of read ports * @param numWritePorts number of write ports * @param registerWidth size of registers in bits * @param bypassableArray list of write ports from func units to the read port of the regfile / abstract class RegisterFile( numRegisters: Int, numReadPorts: Int, numWritePorts: Int, registerWidth: Int, bypassableArray: Seq[Boolean]) // which write ports can be bypassed to the read ports? (implicit p: Parameters) extends BoomModule { val io = IO(new BoomBundle { val read_ports = Vec(numReadPorts, new RegisterFileReadPortIO(maxPregSz, registerWidth)) val write_ports = Flipped(Vec(numWritePorts, Valid(new RegisterFileWritePort(maxPregSz, registerWidth)))) }) private val rf_cost = (numReadPorts + numWritePorts) (numReadPorts + 2numWritePorts) private val type_str = if (registerWidth == fLen+1) "Floating Point" else "Integer" override def toString: String = BoomCoreStringPrefix( "==" + type_str + " Regfile==", "Num RF Read Ports : " + numReadPorts, "Num RF Write Ports : " + numWritePorts, "RF Cost (R+W)(R+2W) : " + rf_cost, "Bypassable Units : " + bypassableArray) } /** * A synthesizable model of a Register File. You will likely want to blackbox this for more than modest port counts. * * @param numRegisters number of registers * @param numReadPorts number of read ports * @param numWritePorts number of write ports * @param registerWidth size of registers in bits * @param bypassableArray list of write ports from func units to the read port of the regfile */ class RegisterFileSynthesizable( numRegisters: Int, numReadPorts: Int, numWritePorts: Int, registerWidth: Int, bypassableArray: Seq[Boolean]) (implicit p: Parameters) extends RegisterFile(numRegisters, numReadPorts, numWritePorts, registerWidth, bypassableArray) { // -------------------------------------------------------------- val regfile = Mem(numRegisters, UInt(registerWidth.W)) // -------------------------------------------------------------- // Read ports. val read_data = Wire(Vec(numReadPorts, UInt(registerWidth.W))) // Register the read port addresses to give a full cycle to the RegisterRead Stage (if desired). val read_addrs = io.read_ports.map(p => RegNext(p.addr)) for (i <- 0 until numReadPorts) { read_data(i) := regfile(read_addrs(i)) } // -------------------------------------------------------------- // Bypass out of the ALU's write ports. // We are assuming we cannot bypass a writer to a reader within the regfile memory // for a write that occurs at the end of cycle S1 and a read that returns data on cycle S1. // But since these bypasses are expensive, and not all write ports need to bypass their data, // only perform the w->r bypass on a select number of write ports. require (bypassableArray.length == io.write_ports.length) if (bypassableArray.reduce(_\|\|_)) { val bypassable_wports = ArrayBuffer[Valid[RegisterFileWritePort]]() io.write_ports zip bypassableArray map { case (wport, b) => if (b) { bypassable_wports += wport} } for (i <- 0 until numReadPorts) { val bypass_ens = bypassable_wports.map(x => x.valid && x.bits.addr === read_addrs(i)) val bypass_data = Mux1H(VecInit(bypass_ens.toSeq), VecInit(bypassable_wports.map(_.bits.data).toSeq)) io.read_ports(i).data := Mux(bypass_ens.reduce(_\|_), bypass_data, read_data(i)) } } else { for (i <- 0 until numReadPorts) { io.read_ports(i).data := read_data(i) } } // -------------------------------------------------------------- // Write ports. for (wport <- io.write_ports) { when (wport.valid) { regfile(wport.bits.addr) := wport.bits.data } } // ensure there is only 1 writer per register (unless to preg0) if (numWritePorts > 1) { for (i <- 0 until (numWritePorts - 1)) { for (j <- (i + 1) until numWritePorts) { assert(!io.write_ports(i).valid \|\| !io.write_ports(j).valid \|\| (io.write_ports(i).bits.addr =/= io.write_ports(j).bits.addr) \|\| (io.write_ports(i).bits.addr === 0.U), // note: you only have to check one here "[regfile] too many writers a register") } } } }	module RegisterFileSynthesizable_5( // @[regfile.scala:106:7] input clock, // @[regfile.scala:106:7] input reset // @[regfile.scala:106:7] ); wire io_write_ports_0_valid = 1'h0; // @[regfile.scala:106:7] wire io_write_ports_0_bits_data = 1'h0; // @[regfile.scala:106:7] wire read_data_0 = 1'h0; // @[regfile.scala:122:23] wire read_data_1 = 1'h0; // @[regfile.scala:122:23] wire bypass_ens_0 = 1'h0; // @[regfile.scala:145:59] wire _bypass_data_WIRE_0 = 1'h0; // @[regfile.scala:148:38] wire _bypass_data_WIRE_1_0 = 1'h0; // @[regfile.scala:148:65] wire bypass_ens_0_1 = 1'h0; // @[regfile.scala:145:59] wire _bypass_data_WIRE_2_0 = 1'h0; // @[regfile.scala:148:38] wire _bypass_data_WIRE_3_0 = 1'h0; // @[regfile.scala:148:65] wire [5:0] io_read_ports_0_addr = 6'h0; // @[regfile.scala:82:14, :106:7] wire [5:0] io_read_ports_1_addr = 6'h0; // @[regfile.scala:82:14, :106:7] wire [5:0] io_write_ports_0_bits_addr = 6'h0; // @[regfile.scala:82:14, :106:7] wire [5:0] _read_data_0_T = 6'h0; // @[regfile.scala:82:14, :106:7, :128:28] wire [5:0] _read_data_1_T = 6'h0; // @[regfile.scala:82:14, :106:7, :128:28] wire [3:0] _read_data_0_T_1 = 4'h0; // @[regfile.scala:128:28] wire [3:0] _read_data_1_T_1 = 4'h0; // @[regfile.scala:128:28] wire _bypass_ens_T = 1'h1; // @[regfile.scala:146:21] wire _bypass_ens_T_1 = 1'h1; // @[regfile.scala:146:21] wire _io_read_ports_0_data_T; // @[regfile.scala:150:35] wire _io_read_ports_1_data_T; // @[regfile.scala:150:35] wire io_read_ports_0_data; // @[regfile.scala:106:7] wire io_read_ports_1_data; // @[regfile.scala:106:7] assign _io_read_ports_0_data_T = read_data_0; // @[regfile.scala:122:23, :150:35] assign _io_read_ports_1_data_T = read_data_1; // @[regfile.scala:122:23, :150:35] assign io_read_ports_0_data = _io_read_ports_0_data_T; // @[regfile.scala:106:7, :150:35] assign io_read_ports_1_data = _io_read_ports_1_data_T; // @[regfile.scala:106:7, :150:35] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_131( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_387 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }	module IntSyncSyncCrossingSink_n0x0_2(); // @[Crossing.scala:96:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) \|\| flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask \| lo_mask)(n-1,0) } } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire \|\| !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v4.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v4.common._ import boom.v4.util._ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val grant = Input(Bool()) val iss_uop = Output(new MicroOp()) val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val squash_grant = Input(Bool()) val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val child_rebusys = Input(UInt(aluWidth.W)) } class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters) extends BoomModule { val io = IO(new IssueSlotIO(numWakeupPorts)) val slot_valid = RegInit(false.B) val slot_uop = Reg(new MicroOp()) val next_valid = WireInit(slot_valid) val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop)) val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop) io.valid := slot_valid io.out_uop := next_uop io.will_be_valid := next_valid && !killed when (io.kill) { slot_valid := false.B } .elsewhen (io.in_uop.valid) { slot_valid := true.B } .elsewhen (io.clear) { slot_valid := false.B } .otherwise { slot_valid := next_valid && !killed } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (!slot_valid \|\| io.clear \|\| io.kill) } .otherwise { slot_uop := next_uop } // Wakeups next_uop.iw_p1_bypass_hint := false.B next_uop.iw_p2_bypass_hint := false.B next_uop.iw_p3_bypass_hint := false.B next_uop.iw_p1_speculative_child := 0.U next_uop.iw_p2_speculative_child := 0.U val rebusied_prs1 = WireInit(false.B) val rebusied_prs2 = WireInit(false.B) val rebusied = rebusied_prs1 \|\| rebusied_prs2 val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 } val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 } val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 } val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m } val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m } val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m } val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m } val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m } val bypassables = io.wakeup_ports.map { w => w.bits.bypassable } val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask } when (prs1_wakeups.reduce(_\|\|_)) { next_uop.prs1_busy := false.B next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks) next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables) } when ((prs1_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) && slot_uop.lrs1_rtype === RT_FIX) { next_uop.prs1_busy := true.B rebusied_prs1 := true.B } when (prs2_wakeups.reduce(_\|\|_)) { next_uop.prs2_busy := false.B next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks) next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables) } when ((prs2_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) && slot_uop.lrs2_rtype === RT_FIX) { next_uop.prs2_busy := true.B rebusied_prs2 := true.B } when (prs3_wakeups.reduce(_\|\|_)) { next_uop.prs3_busy := false.B next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables) } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) { next_uop.ppred_busy := false.B } val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B) val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) io.request := slot_valid && !slot_uop.iw_issued && ( iss_ready \|\| agen_ready \|\| dgen_ready ) io.iss_uop := slot_uop // Update state for current micro-op based on grant next_uop.iw_issued := false.B next_uop.iw_issued_partial_agen := false.B next_uop.iw_issued_partial_dgen := false.B when (io.grant && !io.squash_grant) { next_uop.iw_issued := true.B } if (isMem) { when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) { when (agen_ready) { // Issue the AGEN, next slot entry is a DGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_agen := true.B } io.iss_uop.fu_code(FC_AGEN) := true.B io.iss_uop.fu_code(FC_DGEN) := false.B } .otherwise { // Issue the DGEN, next slot entry is the AGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_dgen := true.B } io.iss_uop.fu_code(FC_AGEN) := false.B io.iss_uop.fu_code(FC_DGEN) := true.B io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } } .elsewhen (slot_uop.fu_code(FC_DGEN)) { io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } io.iss_uop.lrs2_rtype := RT_X io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE } when (slot_valid && slot_uop.iw_issued) { next_valid := rebusied if (isMem) { when (slot_uop.iw_issued_partial_agen) { next_valid := true.B when (!rebusied_prs1) { next_uop.fu_code(FC_AGEN) := false.B next_uop.fu_code(FC_DGEN) := true.B } } .elsewhen (slot_uop.iw_issued_partial_dgen) { next_valid := true.B when (!rebusied_prs2) { next_uop.fu_code(FC_AGEN) := true.B next_uop.fu_code(FC_DGEN) := false.B } } } } }	module IssueSlot_23( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [11:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [11:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [1:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [11:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire [1:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:49:7] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire [1:0] io_iss_uop_lrs2_rtype = 2'h2; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-slot.scala:49:7] wire [1:0] _next_uop_iw_p1_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _next_uop_iw_p2_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [1:0] io_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0 = io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_agen; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen; // @[issue-slot.scala:59:28] wire [1:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [1:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [11:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [5:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [3:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [3:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [11:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [11:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg slot_uop_iw_issued_partial_agen; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_partial_agen_0 = slot_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued_partial_agen = slot_uop_iw_issued_partial_agen; // @[util.scala:104:23] reg slot_uop_iw_issued_partial_dgen; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_partial_dgen_0 = slot_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued_partial_dgen = slot_uop_iw_issued_partial_dgen; // @[util.scala:104:23] reg [1:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [1:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [1:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [11:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [5:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [3:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [3:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [11:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_ppred_busy = next_uop_out_ppred_busy; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [11:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_partial_agen_0 = next_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_partial_dgen_0 = next_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [11:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = \|_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 \| io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to the following Chisel files. File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ class IntXbar()(implicit p: Parameters) extends LazyModule { val intnode = new IntNexusNode( sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, sourceFn = { seq => IntSourcePortParameters((seq zip seq.map(_.num).scanLeft(0)(_+_).init).map { case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o))) }.flatten) }) { override def circuitIdentity = outputs == 1 && inputs == 1 } lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { override def desiredName = s"IntXbar_i${intnode.in.size}_o${intnode.out.size}" val cat = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten intnode.out.foreach { case (o, _) => o := cat } } } class IntSyncXbar()(implicit p: Parameters) extends LazyModule { val intnode = new IntSyncNexusNode( sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, sourceFn = { seq => IntSourcePortParameters((seq zip seq.map(_.num).scanLeft(0)(_+_).init).map { case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o))) }.flatten) }) { override def circuitIdentity = outputs == 1 && inputs == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncXbar_i${intnode.in.size}_o${intnode.out.size}" val cat = intnode.in.map { case (i, e) => i.sync.take(e.source.num) }.flatten intnode.out.foreach { case (o, _) => o.sync := cat } } } object IntXbar { def apply()(implicit p: Parameters): IntNode = { val xbar = LazyModule(new IntXbar) xbar.intnode } } object IntSyncXbar { def apply()(implicit p: Parameters): IntSyncNode = { val xbar = LazyModule(new IntSyncXbar) xbar.intnode } }	module IntXbar_i4_o1_7( // @[Xbar.scala:22:9] input auto_anon_in_3_0, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_0, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_0, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_1, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_0, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1, // @[LazyModuleImp.scala:107:25] output auto_anon_out_2, // @[LazyModuleImp.scala:107:25] output auto_anon_out_3, // @[LazyModuleImp.scala:107:25] output auto_anon_out_4 // @[LazyModuleImp.scala:107:25] ); wire auto_anon_in_3_0_0 = auto_anon_in_3_0; // @[Xbar.scala:22:9] wire auto_anon_in_2_0_0 = auto_anon_in_2_0; // @[Xbar.scala:22:9] wire auto_anon_in_1_0_0 = auto_anon_in_1_0; // @[Xbar.scala:22:9] wire auto_anon_in_1_1_0 = auto_anon_in_1_1; // @[Xbar.scala:22:9] wire auto_anon_in_0_0_0 = auto_anon_in_0_0; // @[Xbar.scala:22:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire anonIn_3_0 = auto_anon_in_3_0_0; // @[Xbar.scala:22:9] wire anonIn_2_0 = auto_anon_in_2_0_0; // @[Xbar.scala:22:9] wire anonIn_1_0 = auto_anon_in_1_0_0; // @[Xbar.scala:22:9] wire anonIn_1_1 = auto_anon_in_1_1_0; // @[Xbar.scala:22:9] wire anonIn_0 = auto_anon_in_0_0_0; // @[Xbar.scala:22:9] wire anonOut_0; // @[MixedNode.scala:542:17] wire anonOut_1; // @[MixedNode.scala:542:17] wire anonOut_2; // @[MixedNode.scala:542:17] wire anonOut_3; // @[MixedNode.scala:542:17] wire anonOut_4; // @[MixedNode.scala:542:17] wire auto_anon_out_0_0; // @[Xbar.scala:22:9] wire auto_anon_out_1_0; // @[Xbar.scala:22:9] wire auto_anon_out_2_0; // @[Xbar.scala:22:9] wire auto_anon_out_3_0; // @[Xbar.scala:22:9] wire auto_anon_out_4_0; // @[Xbar.scala:22:9] assign anonOut_0 = anonIn_0; // @[MixedNode.scala:542:17, :551:17] assign anonOut_1 = anonIn_1_0; // @[MixedNode.scala:542:17, :551:17] assign anonOut_2 = anonIn_1_1; // @[MixedNode.scala:542:17, :551:17] assign anonOut_3 = anonIn_2_0; // @[MixedNode.scala:542:17, :551:17] assign anonOut_4 = anonIn_3_0; // @[MixedNode.scala:542:17, :551:17] assign auto_anon_out_0_0 = anonOut_0; // @[Xbar.scala:22:9] assign auto_anon_out_1_0 = anonOut_1; // @[Xbar.scala:22:9] assign auto_anon_out_2_0 = anonOut_2; // @[Xbar.scala:22:9] assign auto_anon_out_3_0 = anonOut_3; // @[Xbar.scala:22:9] assign auto_anon_out_4_0 = anonOut_4; // @[Xbar.scala:22:9] assign auto_anon_out_0 = auto_anon_out_0_0; // @[Xbar.scala:22:9] assign auto_anon_out_1 = auto_anon_out_1_0; // @[Xbar.scala:22:9] assign auto_anon_out_2 = auto_anon_out_2_0; // @[Xbar.scala:22:9] assign auto_anon_out_3 = auto_anon_out_3_0; // @[Xbar.scala:22:9] assign auto_anon_out_4 = auto_anon_out_4_0; // @[Xbar.scala:22:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_27( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34] wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34] wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34] wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 8'h50; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 6'h10; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 6'h11; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 6'h12; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 6'h13; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 8'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_27 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_33 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire _source_ok_T_28 = _source_ok_T_27 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = _source_ok_T_33 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 8'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire _source_ok_T_41 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 \| _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_49 \| _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [11:0] _is_aligned_T = {6'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_22 = _uncommonBits_T_22[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_23 = _uncommonBits_T_23[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_28 = _uncommonBits_T_28[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_29 = _uncommonBits_T_29[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_34 = _uncommonBits_T_34[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_35 = _uncommonBits_T_35[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_40 = _uncommonBits_T_40[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_41 = _uncommonBits_T_41[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_46 = _uncommonBits_T_46[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_47 = _uncommonBits_T_47[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_52 = _uncommonBits_T_52[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_53 = _uncommonBits_T_53[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_58 = _uncommonBits_T_58[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_59 = _uncommonBits_T_59[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_64 = _uncommonBits_T_64[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_65 = _uncommonBits_T_65[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = io_in_d_bits_source_0 == 8'h50; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_51 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_57 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_63 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_69 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_52 = _source_ok_T_51 == 6'h10; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_58 = _source_ok_T_57 == 6'h11; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_64 = _source_ok_T_63 == 6'h12; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_70 = _source_ok_T_69 == 6'h13; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = io_in_d_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_75; // @[Parameters.scala:1138:31] wire _source_ok_T_76 = io_in_d_bits_source_0 == 8'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_77 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_83 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire _source_ok_T_78 = _source_ok_T_77 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_7 = _source_ok_T_82; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_84 = _source_ok_T_83 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31] wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire _source_ok_T_91 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_92 = _source_ok_T_91 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_93 = _source_ok_T_92 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_94 = _source_ok_T_93 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_95 = _source_ok_T_94 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_96 = _source_ok_T_95 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_97 = _source_ok_T_96 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_98 = _source_ok_T_97 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_99 = _source_ok_T_98 \| _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_99 \| _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _T_1266 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1266; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1266; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] wire _T_1334 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1334; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1334; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1334; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [128:0] a_set; // @[Monitor.scala:626:34] wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [515:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1199 = _T_1266 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1199 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1199 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1199 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1199 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1199 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [128:0] d_clr; // @[Monitor.scala:664:34] wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1245 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1245 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1214 = _T_1334 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1214 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1214 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1214 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [128:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [515:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [515:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [128:0] inflight_1; // @[Monitor.scala:726:35] wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [128:0] d_clr_1; // @[Monitor.scala:774:34] wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [515:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1310 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1310 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1292 = _T_1334 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1292 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1292 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1292 ? _d_sizes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [515:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File SinkA.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class PutBufferAEntry(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val data = UInt(params.inner.bundle.dataBits.W) val mask = UInt((params.inner.bundle.dataBits/8).W) val corrupt = Bool() } class PutBufferPop(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val index = UInt(params.putBits.W) val last = Bool() } class SinkA(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val req = Decoupled(new FullRequest(params)) val a = Flipped(Decoupled(new TLBundleA(params.inner.bundle))) // for use by SourceD: val pb_pop = Flipped(Decoupled(new PutBufferPop(params))) val pb_beat = new PutBufferAEntry(params) }) // No restrictions on the type of buffer val a = params.micro.innerBuf.a(io.a) val putbuffer = Module(new ListBuffer(ListBufferParameters(new PutBufferAEntry(params), params.putLists, params.putBeats, false))) val lists = RegInit((0.U(params.putLists.W))) val lists_set = WireInit(init = 0.U(params.putLists.W)) val lists_clr = WireInit(init = 0.U(params.putLists.W)) lists := (lists \| lists_set) & ~lists_clr val free = !lists.andR val freeOH = ~(leftOR(~lists) << 1) & ~lists val freeIdx = OHToUInt(freeOH) val first = params.inner.first(a) val hasData = params.inner.hasData(a.bits) // We need to split the A input to three places: // If it is the first beat, it must go to req // If it has Data, it must go to the putbuffer // If it has Data AND is the first beat, it must claim a list val req_block = first && !io.req.ready val buf_block = hasData && !putbuffer.io.push.ready val set_block = hasData && first && !free params.ccover(a.valid && req_block, "SINKA_REQ_STALL", "No MSHR available to sink request") params.ccover(a.valid && buf_block, "SINKA_BUF_STALL", "No space in putbuffer for beat") params.ccover(a.valid && set_block, "SINKA_SET_STALL", "No space in putbuffer for request") a.ready := !req_block && !buf_block && !set_block io.req.valid := a.valid && first && !buf_block && !set_block putbuffer.io.push.valid := a.valid && hasData && !req_block && !set_block when (a.valid && first && hasData && !req_block && !buf_block) { lists_set := freeOH } val (tag, set, offset) = params.parseAddress(a.bits.address) val put = Mux(first, freeIdx, RegEnable(freeIdx, first)) io.req.bits.prio := VecInit(1.U(3.W).asBools) io.req.bits.control:= false.B io.req.bits.opcode := a.bits.opcode io.req.bits.param := a.bits.param io.req.bits.size := a.bits.size io.req.bits.source := a.bits.source io.req.bits.offset := offset io.req.bits.set := set io.req.bits.tag := tag io.req.bits.put := put putbuffer.io.push.bits.index := put putbuffer.io.push.bits.data.data := a.bits.data putbuffer.io.push.bits.data.mask := a.bits.mask putbuffer.io.push.bits.data.corrupt := a.bits.corrupt // Grant access to pop the data putbuffer.io.pop.bits := io.pb_pop.bits.index putbuffer.io.pop.valid := io.pb_pop.fire io.pb_pop.ready := putbuffer.io.valid(io.pb_pop.bits.index) io.pb_beat := putbuffer.io.data when (io.pb_pop.fire && io.pb_pop.bits.last) { lists_clr := UIntToOH(io.pb_pop.bits.index, params.putLists) } } File Parameters.scala: / * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relListscache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_\|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x \| 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ \|\| _) (matches, bits.U) } expanded \| Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) \|\| (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) \|\| ((opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm \|\| opcode === TLMessages.Get \|\| (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN \|\| param === TLPermissions.BtoN \|\| param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB \|\| param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module SinkA( // @[SinkA.scala:38:7] input clock, // @[SinkA.scala:38:7] input reset, // @[SinkA.scala:38:7] input io_req_ready, // @[SinkA.scala:40:14] output io_req_valid, // @[SinkA.scala:40:14] output [2:0] io_req_bits_opcode, // @[SinkA.scala:40:14] output [2:0] io_req_bits_param, // @[SinkA.scala:40:14] output [2:0] io_req_bits_size, // @[SinkA.scala:40:14] output [8:0] io_req_bits_source, // @[SinkA.scala:40:14] output [12:0] io_req_bits_tag, // @[SinkA.scala:40:14] output [5:0] io_req_bits_offset, // @[SinkA.scala:40:14] output [5:0] io_req_bits_put, // @[SinkA.scala:40:14] output [9:0] io_req_bits_set, // @[SinkA.scala:40:14] output io_a_ready, // @[SinkA.scala:40:14] input io_a_valid, // @[SinkA.scala:40:14] input [2:0] io_a_bits_opcode, // @[SinkA.scala:40:14] input [2:0] io_a_bits_param, // @[SinkA.scala:40:14] input [2:0] io_a_bits_size, // @[SinkA.scala:40:14] input [8:0] io_a_bits_source, // @[SinkA.scala:40:14] input [31:0] io_a_bits_address, // @[SinkA.scala:40:14] input [7:0] io_a_bits_mask, // @[SinkA.scala:40:14] input [63:0] io_a_bits_data, // @[SinkA.scala:40:14] input io_a_bits_corrupt, // @[SinkA.scala:40:14] output io_pb_pop_ready, // @[SinkA.scala:40:14] input io_pb_pop_valid, // @[SinkA.scala:40:14] input [5:0] io_pb_pop_bits_index, // @[SinkA.scala:40:14] input io_pb_pop_bits_last, // @[SinkA.scala:40:14] output [63:0] io_pb_beat_data, // @[SinkA.scala:40:14] output [7:0] io_pb_beat_mask, // @[SinkA.scala:40:14] output io_pb_beat_corrupt // @[SinkA.scala:40:14] ); wire _putbuffer_io_push_ready; // @[SinkA.scala:51:25] wire [39:0] _putbuffer_io_valid; // @[SinkA.scala:51:25] wire io_req_ready_0 = io_req_ready; // @[SinkA.scala:38:7] wire io_a_valid_0 = io_a_valid; // @[SinkA.scala:38:7] wire [2:0] io_a_bits_opcode_0 = io_a_bits_opcode; // @[SinkA.scala:38:7] wire [2:0] io_a_bits_param_0 = io_a_bits_param; // @[SinkA.scala:38:7] wire [2:0] io_a_bits_size_0 = io_a_bits_size; // @[SinkA.scala:38:7] wire [8:0] io_a_bits_source_0 = io_a_bits_source; // @[SinkA.scala:38:7] wire [31:0] io_a_bits_address_0 = io_a_bits_address; // @[SinkA.scala:38:7] wire [7:0] io_a_bits_mask_0 = io_a_bits_mask; // @[SinkA.scala:38:7] wire [63:0] io_a_bits_data_0 = io_a_bits_data; // @[SinkA.scala:38:7] wire io_a_bits_corrupt_0 = io_a_bits_corrupt; // @[SinkA.scala:38:7] wire io_pb_pop_valid_0 = io_pb_pop_valid; // @[SinkA.scala:38:7] wire [5:0] io_pb_pop_bits_index_0 = io_pb_pop_bits_index; // @[SinkA.scala:38:7] wire io_pb_pop_bits_last_0 = io_pb_pop_bits_last; // @[SinkA.scala:38:7] wire io_req_bits_prio_1 = 1'h0; // @[SinkA.scala:38:7] wire io_req_bits_prio_2 = 1'h0; // @[SinkA.scala:38:7] wire io_req_bits_control = 1'h0; // @[SinkA.scala:38:7] wire io_req_bits_prio_0 = 1'h1; // @[SinkA.scala:38:7] wire _io_req_valid_T_4; // @[SinkA.scala:79:50] wire [12:0] tag_1; // @[Parameters.scala:217:9] wire [5:0] offset_1; // @[Parameters.scala:217:50] wire [5:0] put; // @[SinkA.scala:84:16] wire [9:0] set_1; // @[Parameters.scala:217:28] wire _io_a_ready_T_4; // @[SinkA.scala:78:39] wire [2:0] io_req_bits_opcode_0 = io_a_bits_opcode_0; // @[SinkA.scala:38:7] wire [2:0] io_req_bits_param_0 = io_a_bits_param_0; // @[SinkA.scala:38:7] wire [2:0] io_req_bits_size_0 = io_a_bits_size_0; // @[SinkA.scala:38:7] wire [8:0] io_req_bits_source_0 = io_a_bits_source_0; // @[SinkA.scala:38:7] wire _io_pb_pop_ready_T_1; // @[SinkA.scala:105:40] wire [5:0] lists_clr_shiftAmount = io_pb_pop_bits_index_0; // @[OneHot.scala:64:49] wire [12:0] io_req_bits_tag_0; // @[SinkA.scala:38:7] wire [5:0] io_req_bits_offset_0; // @[SinkA.scala:38:7] wire [5:0] io_req_bits_put_0; // @[SinkA.scala:38:7] wire [9:0] io_req_bits_set_0; // @[SinkA.scala:38:7] wire io_req_valid_0; // @[SinkA.scala:38:7] wire io_a_ready_0; // @[SinkA.scala:38:7] wire io_pb_pop_ready_0; // @[SinkA.scala:38:7] wire [63:0] io_pb_beat_data_0; // @[SinkA.scala:38:7] wire [7:0] io_pb_beat_mask_0; // @[SinkA.scala:38:7] wire io_pb_beat_corrupt_0; // @[SinkA.scala:38:7] reg [39:0] lists; // @[SinkA.scala:52:22] wire [39:0] lists_set; // @[SinkA.scala:54:27] wire [39:0] lists_clr; // @[SinkA.scala:55:27] wire [39:0] _lists_T = lists \| lists_set; // @[SinkA.scala:52:22, :54:27, :56:19] wire [39:0] _lists_T_1 = ~lists_clr; // @[SinkA.scala:55:27, :56:34] wire [39:0] _lists_T_2 = _lists_T & _lists_T_1; // @[SinkA.scala:56:{19,32,34}] wire _free_T = &lists; // @[SinkA.scala:52:22, :58:21] wire free = ~_free_T; // @[SinkA.scala:58:{14,21}] wire [39:0] _freeOH_T = ~lists; // @[SinkA.scala:52:22, :59:25] wire [40:0] _freeOH_T_1 = {_freeOH_T, 1'h0}; // @[package.scala:253:48] wire [39:0] _freeOH_T_2 = _freeOH_T_1[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_3 = _freeOH_T \| _freeOH_T_2; // @[package.scala:253:{43,53}] wire [41:0] _freeOH_T_4 = {_freeOH_T_3, 2'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_5 = _freeOH_T_4[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_6 = _freeOH_T_3 \| _freeOH_T_5; // @[package.scala:253:{43,53}] wire [43:0] _freeOH_T_7 = {_freeOH_T_6, 4'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_8 = _freeOH_T_7[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_9 = _freeOH_T_6 \| _freeOH_T_8; // @[package.scala:253:{43,53}] wire [47:0] _freeOH_T_10 = {_freeOH_T_9, 8'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_11 = _freeOH_T_10[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_12 = _freeOH_T_9 \| _freeOH_T_11; // @[package.scala:253:{43,53}] wire [55:0] _freeOH_T_13 = {_freeOH_T_12, 16'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_14 = _freeOH_T_13[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_15 = _freeOH_T_12 \| _freeOH_T_14; // @[package.scala:253:{43,53}] wire [71:0] _freeOH_T_16 = {_freeOH_T_15, 32'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_17 = _freeOH_T_16[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_18 = _freeOH_T_15 \| _freeOH_T_17; // @[package.scala:253:{43,53}] wire [39:0] _freeOH_T_19 = _freeOH_T_18; // @[package.scala:253:43, :254:17] wire [40:0] _freeOH_T_20 = {_freeOH_T_19, 1'h0}; // @[package.scala:254:17] wire [40:0] _freeOH_T_21 = ~_freeOH_T_20; // @[SinkA.scala:59:{16,33}] wire [39:0] _freeOH_T_22 = ~lists; // @[SinkA.scala:52:22, :59:{25,41}] wire [40:0] freeOH = {1'h0, _freeOH_T_21[39:0] & _freeOH_T_22}; // @[SinkA.scala:59:{16,39,41}] wire [8:0] freeIdx_hi = freeOH[40:32]; // @[OneHot.scala:30:18] wire [31:0] freeIdx_lo = freeOH[31:0]; // @[OneHot.scala:31:18] wire _freeIdx_T = \|freeIdx_hi; // @[OneHot.scala:30:18, :32:14] wire [31:0] _freeIdx_T_1 = {23'h0, freeIdx_hi} \| freeIdx_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [15:0] freeIdx_hi_1 = _freeIdx_T_1[31:16]; // @[OneHot.scala:30:18, :32:28] wire [15:0] freeIdx_lo_1 = _freeIdx_T_1[15:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_2 = \|freeIdx_hi_1; // @[OneHot.scala:30:18, :32:14] wire [15:0] _freeIdx_T_3 = freeIdx_hi_1 \| freeIdx_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] freeIdx_hi_2 = _freeIdx_T_3[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] freeIdx_lo_2 = _freeIdx_T_3[7:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_4 = \|freeIdx_hi_2; // @[OneHot.scala:30:18, :32:14] wire [7:0] _freeIdx_T_5 = freeIdx_hi_2 \| freeIdx_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] freeIdx_hi_3 = _freeIdx_T_5[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] freeIdx_lo_3 = _freeIdx_T_5[3:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_6 = \|freeIdx_hi_3; // @[OneHot.scala:30:18, :32:14] wire [3:0] _freeIdx_T_7 = freeIdx_hi_3 \| freeIdx_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] freeIdx_hi_4 = _freeIdx_T_7[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] freeIdx_lo_4 = _freeIdx_T_7[1:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_8 = \|freeIdx_hi_4; // @[OneHot.scala:30:18, :32:14] wire [1:0] _freeIdx_T_9 = freeIdx_hi_4 \| freeIdx_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28] wire _freeIdx_T_10 = _freeIdx_T_9[1]; // @[OneHot.scala:32:28] wire [1:0] _freeIdx_T_11 = {_freeIdx_T_8, _freeIdx_T_10}; // @[OneHot.scala:32:{10,14}] wire [2:0] _freeIdx_T_12 = {_freeIdx_T_6, _freeIdx_T_11}; // @[OneHot.scala:32:{10,14}] wire [3:0] _freeIdx_T_13 = {_freeIdx_T_4, _freeIdx_T_12}; // @[OneHot.scala:32:{10,14}] wire [4:0] _freeIdx_T_14 = {_freeIdx_T_2, _freeIdx_T_13}; // @[OneHot.scala:32:{10,14}] wire [5:0] freeIdx = {_freeIdx_T, _freeIdx_T_14}; // @[OneHot.scala:32:{10,14}] wire _first_T = io_a_ready_0 & io_a_valid_0; // @[Decoupled.scala:51:35] wire [12:0] _first_beats1_decode_T = 13'h3F << io_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _first_beats1_decode_T_1 = _first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _first_beats1_decode_T_2 = ~_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] first_beats1_decode = _first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _first_beats1_opdata_T = io_a_bits_opcode_0[2]; // @[Edges.scala:92:37] wire _hasData_opdata_T = io_a_bits_opcode_0[2]; // @[Edges.scala:92:37] wire first_beats1_opdata = ~_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] first_beats1 = first_beats1_opdata ? first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] first_counter; // @[Edges.scala:229:27] wire [3:0] _first_counter1_T = {1'h0, first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] first_counter1 = _first_counter1_T[2:0]; // @[Edges.scala:230:28] wire first = first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _first_last_T = first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _first_last_T_1 = first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire first_last = _first_last_T \| _first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire first_done = first_last & _first_T; // @[Decoupled.scala:51:35] wire [2:0] _first_count_T = ~first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] first_count = first_beats1 & _first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _first_counter_T = first ? first_beats1 : first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire hasData = ~_hasData_opdata_T; // @[Edges.scala:92:{28,37}] wire _req_block_T = ~io_req_ready_0; // @[SinkA.scala:38:7, :70:28] wire req_block = first & _req_block_T; // @[Edges.scala:231:25] wire _buf_block_T = ~_putbuffer_io_push_ready; // @[SinkA.scala:51:25, :71:30] wire buf_block = hasData & _buf_block_T; // @[Edges.scala:92:28] wire _set_block_T = hasData & first; // @[Edges.scala:92:28, :231:25] wire _set_block_T_1 = ~free; // @[SinkA.scala:58:14, :72:39] wire set_block = _set_block_T & _set_block_T_1; // @[SinkA.scala:72:{27,36,39}] wire _io_a_ready_T = ~req_block; // @[SinkA.scala:70:25, :78:14] wire _io_a_ready_T_1 = ~buf_block; // @[SinkA.scala:71:27, :78:28] wire _io_a_ready_T_2 = _io_a_ready_T & _io_a_ready_T_1; // @[SinkA.scala:78:{14,25,28}] wire _io_a_ready_T_3 = ~set_block; // @[SinkA.scala:72:36, :78:42] assign _io_a_ready_T_4 = _io_a_ready_T_2 & _io_a_ready_T_3; // @[SinkA.scala:78:{25,39,42}] assign io_a_ready_0 = _io_a_ready_T_4; // @[SinkA.scala:38:7, :78:39] wire _io_req_valid_T = io_a_valid_0 & first; // @[Edges.scala:231:25] wire _io_req_valid_T_1 = ~buf_block; // @[SinkA.scala:71:27, :78:28, :79:39] wire _io_req_valid_T_2 = _io_req_valid_T & _io_req_valid_T_1; // @[SinkA.scala:79:{27,36,39}] wire _io_req_valid_T_3 = ~set_block; // @[SinkA.scala:72:36, :78:42, :79:53] assign _io_req_valid_T_4 = _io_req_valid_T_2 & _io_req_valid_T_3; // @[SinkA.scala:79:{36,50,53}] assign io_req_valid_0 = _io_req_valid_T_4; // @[SinkA.scala:38:7, :79:50] wire _putbuffer_io_push_valid_T = io_a_valid_0 & hasData; // @[Edges.scala:92:28] wire _putbuffer_io_push_valid_T_1 = ~req_block; // @[SinkA.scala:70:25, :78:14, :80:52] wire _putbuffer_io_push_valid_T_2 = _putbuffer_io_push_valid_T & _putbuffer_io_push_valid_T_1; // @[SinkA.scala:80:{38,49,52}] wire _putbuffer_io_push_valid_T_3 = ~set_block; // @[SinkA.scala:72:36, :78:42, :80:66] wire _putbuffer_io_push_valid_T_4 = _putbuffer_io_push_valid_T_2 & _putbuffer_io_push_valid_T_3; // @[SinkA.scala:80:{49,63,66}] assign lists_set = _io_req_valid_T & hasData & ~req_block & ~buf_block ? freeOH[39:0] : 40'h0; // @[Edges.scala:92:28] wire _offset_T = io_a_bits_address_0[0]; // @[SinkA.scala:38:7] wire _offset_T_1 = io_a_bits_address_0[1]; // @[SinkA.scala:38:7] wire _offset_T_2 = io_a_bits_address_0[2]; // @[SinkA.scala:38:7] wire _offset_T_3 = io_a_bits_address_0[3]; // @[SinkA.scala:38:7] wire _offset_T_4 = io_a_bits_address_0[4]; // @[SinkA.scala:38:7] wire _offset_T_5 = io_a_bits_address_0[5]; // @[SinkA.scala:38:7] wire _offset_T_6 = io_a_bits_address_0[6]; // @[SinkA.scala:38:7] wire _offset_T_7 = io_a_bits_address_0[7]; // @[SinkA.scala:38:7] wire _offset_T_8 = io_a_bits_address_0[8]; // @[SinkA.scala:38:7] wire _offset_T_9 = io_a_bits_address_0[9]; // @[SinkA.scala:38:7] wire _offset_T_10 = io_a_bits_address_0[10]; // @[SinkA.scala:38:7] wire _offset_T_11 = io_a_bits_address_0[11]; // @[SinkA.scala:38:7] wire _offset_T_12 = io_a_bits_address_0[12]; // @[SinkA.scala:38:7] wire _offset_T_13 = io_a_bits_address_0[13]; // @[SinkA.scala:38:7] wire _offset_T_14 = io_a_bits_address_0[14]; // @[SinkA.scala:38:7] wire _offset_T_15 = io_a_bits_address_0[15]; // @[SinkA.scala:38:7] wire _offset_T_16 = io_a_bits_address_0[16]; // @[SinkA.scala:38:7] wire _offset_T_17 = io_a_bits_address_0[17]; // @[SinkA.scala:38:7] wire _offset_T_18 = io_a_bits_address_0[18]; // @[SinkA.scala:38:7] wire _offset_T_19 = io_a_bits_address_0[19]; // @[SinkA.scala:38:7] wire _offset_T_20 = io_a_bits_address_0[20]; // @[SinkA.scala:38:7] wire _offset_T_21 = io_a_bits_address_0[21]; // @[SinkA.scala:38:7] wire _offset_T_22 = io_a_bits_address_0[22]; // @[SinkA.scala:38:7] wire _offset_T_23 = io_a_bits_address_0[23]; // @[SinkA.scala:38:7] wire _offset_T_24 = io_a_bits_address_0[24]; // @[SinkA.scala:38:7] wire _offset_T_25 = io_a_bits_address_0[25]; // @[SinkA.scala:38:7] wire _offset_T_26 = io_a_bits_address_0[26]; // @[SinkA.scala:38:7] wire _offset_T_27 = io_a_bits_address_0[27]; // @[SinkA.scala:38:7] wire _offset_T_28 = io_a_bits_address_0[31]; // @[SinkA.scala:38:7] wire [1:0] offset_lo_lo_lo_hi = {_offset_T_2, _offset_T_1}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_lo_lo_lo = {offset_lo_lo_lo_hi, _offset_T}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_lo_hi_lo = {_offset_T_4, _offset_T_3}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_lo_hi_hi = {_offset_T_6, _offset_T_5}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_lo_lo_hi = {offset_lo_lo_hi_hi, offset_lo_lo_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_lo_lo = {offset_lo_lo_hi, offset_lo_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_lo_hi_lo_hi = {_offset_T_9, _offset_T_8}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_lo_hi_lo = {offset_lo_hi_lo_hi, _offset_T_7}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_hi_hi_lo = {_offset_T_11, _offset_T_10}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_hi_hi_hi = {_offset_T_13, _offset_T_12}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_lo_hi_hi = {offset_lo_hi_hi_hi, offset_lo_hi_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_lo_hi = {offset_lo_hi_hi, offset_lo_hi_lo}; // @[Parameters.scala:214:21] wire [13:0] offset_lo = {offset_lo_hi, offset_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_hi_lo_lo_hi = {_offset_T_16, _offset_T_15}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_hi_lo_lo = {offset_hi_lo_lo_hi, _offset_T_14}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_lo_hi_lo = {_offset_T_18, _offset_T_17}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_lo_hi_hi = {_offset_T_20, _offset_T_19}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_hi_lo_hi = {offset_hi_lo_hi_hi, offset_hi_lo_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_hi_lo = {offset_hi_lo_hi, offset_hi_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_hi_hi_lo_lo = {_offset_T_22, _offset_T_21}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_hi_lo_hi = {_offset_T_24, _offset_T_23}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_hi_hi_lo = {offset_hi_hi_lo_hi, offset_hi_hi_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_hi_hi_hi_lo = {_offset_T_26, _offset_T_25}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_hi_hi_hi = {_offset_T_28, _offset_T_27}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_hi_hi_hi = {offset_hi_hi_hi_hi, offset_hi_hi_hi_lo}; // @[Parameters.scala:214:21] wire [7:0] offset_hi_hi = {offset_hi_hi_hi, offset_hi_hi_lo}; // @[Parameters.scala:214:21] wire [14:0] offset_hi = {offset_hi_hi, offset_hi_lo}; // @[Parameters.scala:214:21] wire [28:0] offset = {offset_hi, offset_lo}; // @[Parameters.scala:214:21] wire [22:0] set = offset[28:6]; // @[Parameters.scala:214:21, :215:22] wire [12:0] tag = set[22:10]; // @[Parameters.scala:215:22, :216:19] assign tag_1 = tag; // @[Parameters.scala:216:19, :217:9] assign io_req_bits_tag_0 = tag_1; // @[SinkA.scala:38:7] assign set_1 = set[9:0]; // @[Parameters.scala:215:22, :217:28] assign io_req_bits_set_0 = set_1; // @[SinkA.scala:38:7] assign offset_1 = offset[5:0]; // @[Parameters.scala:214:21, :217:50] assign io_req_bits_offset_0 = offset_1; // @[SinkA.scala:38:7] reg [5:0] put_r; // @[SinkA.scala:84:42] assign put = first ? freeIdx : put_r; // @[OneHot.scala:32:10] assign io_req_bits_put_0 = put; // @[SinkA.scala:38:7, :84:16] wire _putbuffer_io_pop_valid_T = io_pb_pop_ready_0 & io_pb_pop_valid_0; // @[Decoupled.scala:51:35] wire [39:0] _io_pb_pop_ready_T = _putbuffer_io_valid >> io_pb_pop_bits_index_0; // @[SinkA.scala:38:7, :51:25, :105:40] assign _io_pb_pop_ready_T_1 = _io_pb_pop_ready_T[0]; // @[SinkA.scala:105:40] assign io_pb_pop_ready_0 = _io_pb_pop_ready_T_1; // @[SinkA.scala:38:7, :105:40] wire [63:0] _lists_clr_T = 64'h1 << lists_clr_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [39:0] _lists_clr_T_1 = _lists_clr_T[39:0]; // @[OneHot.scala:65:{12,27}] assign lists_clr = _putbuffer_io_pop_valid_T & io_pb_pop_bits_last_0 ? _lists_clr_T_1 : 40'h0; // @[OneHot.scala:65:27] always @(posedge clock) begin // @[SinkA.scala:38:7] if (reset) begin // @[SinkA.scala:38:7] lists <= 40'h0; // @[SinkA.scala:52:22] first_counter <= 3'h0; // @[Edges.scala:229:27] end else begin // @[SinkA.scala:38:7] lists <= _lists_T_2; // @[SinkA.scala:52:22, :56:32] if (_first_T) // @[Decoupled.scala:51:35] first_counter <= _first_counter_T; // @[Edges.scala:229:27, :236:21] end if (first) // @[Edges.scala:231:25] put_r <= freeIdx; // @[OneHot.scala:32:10] always @(posedge) ListBuffer_PutBufferAEntry_q40_e40 putbuffer ( // @[SinkA.scala:51:25] .clock (clock), .reset (reset), .io_push_ready (_putbuffer_io_push_ready), .io_push_valid (_putbuffer_io_push_valid_T_4), // @[SinkA.scala:80:63] .io_push_bits_index (put), // @[SinkA.scala:84:16] .io_push_bits_data_data (io_a_bits_data_0), // @[SinkA.scala:38:7] .io_push_bits_data_mask (io_a_bits_mask_0), // @[SinkA.scala:38:7] .io_push_bits_data_corrupt (io_a_bits_corrupt_0), // @[SinkA.scala:38:7] .io_valid (_putbuffer_io_valid), .io_pop_valid (_putbuffer_io_pop_valid_T), // @[Decoupled.scala:51:35] .io_pop_bits (io_pb_pop_bits_index_0), // @[SinkA.scala:38:7] .io_data_data (io_pb_beat_data_0), .io_data_mask (io_pb_beat_mask_0), .io_data_corrupt (io_pb_beat_corrupt_0) ); // @[SinkA.scala:51:25] assign io_req_valid = io_req_valid_0; // @[SinkA.scala:38:7] assign io_req_bits_opcode = io_req_bits_opcode_0; // @[SinkA.scala:38:7] assign io_req_bits_param = io_req_bits_param_0; // @[SinkA.scala:38:7] assign io_req_bits_size = io_req_bits_size_0; // @[SinkA.scala:38:7] assign io_req_bits_source = io_req_bits_source_0; // @[SinkA.scala:38:7] assign io_req_bits_tag = io_req_bits_tag_0; // @[SinkA.scala:38:7] assign io_req_bits_offset = io_req_bits_offset_0; // @[SinkA.scala:38:7] assign io_req_bits_put = io_req_bits_put_0; // @[SinkA.scala:38:7] assign io_req_bits_set = io_req_bits_set_0; // @[SinkA.scala:38:7] assign io_a_ready = io_a_ready_0; // @[SinkA.scala:38:7] assign io_pb_pop_ready = io_pb_pop_ready_0; // @[SinkA.scala:38:7] assign io_pb_beat_data = io_pb_beat_data_0; // @[SinkA.scala:38:7] assign io_pb_beat_mask = io_pb_beat_mask_0; // @[SinkA.scala:38:7] assign io_pb_beat_corrupt = io_pb_beat_corrupt_0; // @[SinkA.scala:38:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire \|\| io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) \|\| !io.outCol.fire) assert(!(state === 1.U) \|\| !io.inRow.fire) }	module PE_20( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_57( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [12:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [12:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [12:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [12:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [12:0] _c_first_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_first_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_first_WIRE_2_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_first_WIRE_3_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_set_wo_ready_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_set_wo_ready_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_set_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_set_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_opcodes_set_interm_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_opcodes_set_interm_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_sizes_set_interm_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_sizes_set_interm_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_opcodes_set_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_opcodes_set_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_sizes_set_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_sizes_set_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_probe_ack_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_probe_ack_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_probe_ack_WIRE_2_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_probe_ack_WIRE_3_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_2_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_3_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_4_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_5_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [65537:0] _c_sizes_set_T_1 = 65538'h0; // @[Monitor.scala:768:52] wire [15:0] _c_opcodes_set_T = 16'h0; // @[Monitor.scala:767:79] wire [15:0] _c_sizes_set_T = 16'h0; // @[Monitor.scala:768:77] wire [65538:0] _c_opcodes_set_T_1 = 65539'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [8191:0] _c_set_wo_ready_T = 8192'h1; // @[OneHot.scala:58:35] wire [8191:0] _c_set_T = 8192'h1; // @[OneHot.scala:58:35] wire [16447:0] c_opcodes_set = 16448'h0; // @[Monitor.scala:740:34] wire [16447:0] c_sizes_set = 16448'h0; // @[Monitor.scala:741:34] wire [4111:0] c_set = 4112'h0; // @[Monitor.scala:738:34] wire [4111:0] c_set_wo_ready = 4112'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [12:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 13'h1010; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {18'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [12:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [12:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 13'h1010; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [12:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [12:0] source_1; // @[Monitor.scala:541:22] reg [4111:0] inflight; // @[Monitor.scala:614:27] reg [16447:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [16447:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [4111:0] a_set; // @[Monitor.scala:626:34] wire [4111:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [16447:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [16447:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [15:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [15:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [15:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [15:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [15:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [15:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [15:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [15:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [16447:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [16447:0] _a_opcode_lookup_T_6 = {16444'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [16447:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[16447:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [16447:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [16447:0] _a_size_lookup_T_6 = {16444'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [16447:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[16447:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [8191:0] _GEN_2 = 8192'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [8191:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [8191:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [15:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [15:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [15:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [65538:0] _a_opcodes_set_T_1 = {65535'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[16447:0] : 16448'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [65537:0] _a_sizes_set_T_1 = {65535'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[16447:0] : 16448'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [4111:0] d_clr; // @[Monitor.scala:664:34] wire [4111:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [16447:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [16447:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [8191:0] _GEN_5 = 8192'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [8191:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [8191:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [8191:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [8191:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35] wire [65550:0] _d_opcodes_clr_T_5 = 65551'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[16447:0] : 16448'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [65550:0] _d_sizes_clr_T_5 = 65551'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[16447:0] : 16448'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [4111:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [4111:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [4111:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [16447:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [16447:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [16447:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [16447:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [16447:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [16447:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [4111:0] inflight_1; // @[Monitor.scala:726:35] wire [4111:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [16447:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [16447:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [16447:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [16447:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [16447:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [16447:0] _c_opcode_lookup_T_6 = {16444'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [16447:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[16447:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [16447:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [16447:0] _c_size_lookup_T_6 = {16444'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [16447:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[16447:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [4111:0] d_clr_1; // @[Monitor.scala:774:34] wire [4111:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [16447:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [16447:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[4111:0] : 4112'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[4111:0] : 4112'h0; // @[OneHot.scala:58:35] wire [65550:0] _d_opcodes_clr_T_11 = 65551'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[16447:0] : 16448'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [65550:0] _d_sizes_clr_T_11 = 65551'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[16447:0] : 16448'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 13'h0; // @[Monitor.scala:36:7, :795:113] wire [4111:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [4111:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [16447:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [16447:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [16447:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [16447:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File AtomicAutomata.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.util.leftOR import scala.math.{min,max} // Ensures that all downstream RW managers support Atomic operations. // If !passthrough, intercept all Atomics. Otherwise, only intercept those unsupported downstream. class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(implicit p: Parameters) extends LazyModule { require (concurrency >= 1) val node = TLAdapterNode( managerFn = { case mp => mp.v1copy(managers = mp.managers.map { m => val ourSupport = TransferSizes(1, mp.beatBytes) def widen(x: TransferSizes) = if (passthrough && x.min <= 2mp.beatBytes) TransferSizes(1, max(mp.beatBytes, x.max)) else ourSupport val canDoit = m.supportsPutFull.contains(ourSupport) && m.supportsGet.contains(ourSupport) // Blow up if there are devices to which we cannot add Atomics, because their R\|W are too inflexible require (!m.supportsPutFull \|\| !m.supportsGet \|\| canDoit, s"${m.name} has $ourSupport, needed PutFull(${m.supportsPutFull}) or Get(${m.supportsGet})") m.v1copy( supportsArithmetic = if (!arithmetic \|\| !canDoit) m.supportsArithmetic else widen(m.supportsArithmetic), supportsLogical = if (!logical \|\| !canDoit) m.supportsLogical else widen(m.supportsLogical), mayDenyGet = m.mayDenyGet \|\| m.mayDenyPut) })}) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val managers = edgeOut.manager.managers val beatBytes = edgeOut.manager.beatBytes // To which managers are we adding atomic support? val ourSupport = TransferSizes(1, beatBytes) val managersNeedingHelp = managers.filter { m => m.supportsPutFull.contains(ourSupport) && m.supportsGet.contains(ourSupport) && ((logical && !m.supportsLogical .contains(ourSupport)) \|\| (arithmetic && !m.supportsArithmetic.contains(ourSupport)) \|\| !passthrough) // we will do atomics for everyone we can } // Managers that need help with atomics must necessarily have this node as the root of a tree in the node graph. // (But they must also ensure no sideband operations can get between the read and write.) val violations = managersNeedingHelp.flatMap(_.findTreeViolation()).map { node => (node.name, node.inputs.map(_._1.name)) } require(violations.isEmpty, s"AtomicAutomata can only help nodes for which it is at the root of a diplomatic node tree," + "but the following violations were found:\n" + violations.map(v => s"(${v._1} has parents ${v._2})").mkString("\n")) // We cannot add atomics to a non-FIFO manager managersNeedingHelp foreach { m => require (m.fifoId.isDefined) } // We need to preserve FIFO semantics across FIFO domains, not managers // Suppose you have Put(42) Atomic(+1) both inflight; valid results: 42 or 43 // If we allow Put(42) Get() Put(+1) concurrent; valid results: 42 43 OR undef // Making non-FIFO work requires waiting for all Acks to come back (=> use FIFOFixer) val domainsNeedingHelp = managersNeedingHelp.map(_.fifoId.get).distinct // Don't overprovision the CAM val camSize = min(domainsNeedingHelp.size, concurrency) // Compact the fifoIds to only those we care about def camFifoId(m: TLSlaveParameters) = m.fifoId.map(id => max(0, domainsNeedingHelp.indexOf(id))).getOrElse(0) // CAM entry state machine val FREE = 0.U // unused waiting on Atomic from A val GET = 3.U // Get sent down A waiting on AccessDataAck from D val AMO = 2.U // AccessDataAck sent up D waiting for A availability val ACK = 1.U // Put sent down A waiting for PutAck from D val params = TLAtomicAutomata.CAMParams(out.a.bits.params, domainsNeedingHelp.size) // Do we need to do anything at all? if (camSize > 0) { val initval = Wire(new TLAtomicAutomata.CAM_S(params)) initval.state := FREE val cam_s = RegInit(VecInit.fill(camSize)(initval)) val cam_a = Reg(Vec(camSize, new TLAtomicAutomata.CAM_A(params))) val cam_d = Reg(Vec(camSize, new TLAtomicAutomata.CAM_D(params))) val cam_free = cam_s.map(_.state === FREE) val cam_amo = cam_s.map(_.state === AMO) val cam_abusy = cam_s.map(e => e.state === GET \|\| e.state === AMO) // A is blocked val cam_dmatch = cam_s.map(e => e.state =/= FREE) // D should inspect these entries // Can the manager already handle this message? val a_address = edgeIn.address(in.a.bits) val a_size = edgeIn.size(in.a.bits) val a_canLogical = passthrough.B && edgeOut.manager.supportsLogicalFast (a_address, a_size) val a_canArithmetic = passthrough.B && edgeOut.manager.supportsArithmeticFast(a_address, a_size) val a_isLogical = in.a.bits.opcode === TLMessages.LogicalData val a_isArithmetic = in.a.bits.opcode === TLMessages.ArithmeticData val a_isSupported = Mux(a_isLogical, a_canLogical, Mux(a_isArithmetic, a_canArithmetic, true.B)) // Must we do a Put? val a_cam_any_put = cam_amo.reduce(_ \|\| _) val a_cam_por_put = cam_amo.scanLeft(false.B)(_\|\|_).init val a_cam_sel_put = (cam_amo zip a_cam_por_put) map { case (a, b) => a && !b } val a_cam_a = PriorityMux(cam_amo, cam_a) val a_cam_d = PriorityMux(cam_amo, cam_d) val a_a = a_cam_a.bits.data val a_d = a_cam_d.data // Does the A request conflict with an inflight AMO? val a_fifoId = edgeOut.manager.fastProperty(a_address, camFifoId _, (i:Int) => i.U) val a_cam_busy = (cam_abusy zip cam_a.map(_.fifoId === a_fifoId)) map { case (a,b) => a&&b } reduce (_\|\|_) // (Where) are we are allocating in the CAM? val a_cam_any_free = cam_free.reduce(_ \|\| _) val a_cam_por_free = cam_free.scanLeft(false.B)(_\|\|_).init val a_cam_sel_free = (cam_free zip a_cam_por_free) map { case (a,b) => a && !b } // Logical AMO val indexes = Seq.tabulate(beatBytes8) { i => Cat(a_a(i,i), a_d(i,i)) } val logic_out = Cat(indexes.map(x => a_cam_a.lut(x).asUInt).reverse) // Arithmetic AMO val unsigned = a_cam_a.bits.param(1) val take_max = a_cam_a.bits.param(0) val adder = a_cam_a.bits.param(2) val mask = a_cam_a.bits.mask val signSel = ~(~mask \| (mask >> 1)) val signbits_a = Cat(Seq.tabulate(beatBytes) { i => a_a(8i+7,8i+7) } .reverse) val signbits_d = Cat(Seq.tabulate(beatBytes) { i => a_d(8i+7,8i+7) } .reverse) // Move the selected sign bit into the first byte position it will extend val signbit_a = ((signbits_a & signSel) << 1)(beatBytes-1, 0) val signbit_d = ((signbits_d & signSel) << 1)(beatBytes-1, 0) val signext_a = FillInterleaved(8, leftOR(signbit_a)) val signext_d = FillInterleaved(8, leftOR(signbit_d)) // NOTE: sign-extension does not change the relative ordering in EITHER unsigned or signed arithmetic val wide_mask = FillInterleaved(8, mask) val a_a_ext = (a_a & wide_mask) \| signext_a val a_d_ext = (a_d & wide_mask) \| signext_d val a_d_inv = Mux(adder, a_d_ext, ~a_d_ext) val adder_out = a_a_ext + a_d_inv val h = 8beatBytes-1 // now sign-extended; use biggest bit val a_bigger_uneq = unsigned === a_a_ext(h) // result if high bits are unequal val a_bigger = Mux(a_a_ext(h) === a_d_ext(h), !adder_out(h), a_bigger_uneq) val pick_a = take_max === a_bigger val arith_out = Mux(adder, adder_out, Mux(pick_a, a_a, a_d)) // AMO result data val amo_data = if (!logical) arith_out else if (!arithmetic) logic_out else Mux(a_cam_a.bits.opcode(0), logic_out, arith_out) // Potentially mutate the message from inner val source_i = Wire(chiselTypeOf(in.a)) val a_allow = !a_cam_busy && (a_isSupported \|\| a_cam_any_free) in.a.ready := source_i.ready && a_allow source_i.valid := in.a.valid && a_allow source_i.bits := in.a.bits when (!a_isSupported) { // minimal mux difference source_i.bits.opcode := TLMessages.Get source_i.bits.param := 0.U } // Potentially take the message from the CAM val source_c = Wire(chiselTypeOf(in.a)) source_c.valid := a_cam_any_put source_c.bits := edgeOut.Put( fromSource = a_cam_a.bits.source, toAddress = edgeIn.address(a_cam_a.bits), lgSize = a_cam_a.bits.size, data = amo_data, corrupt = a_cam_a.bits.corrupt \|\| a_cam_d.corrupt)._2 source_c.bits.user :<= a_cam_a.bits.user source_c.bits.echo :<= a_cam_a.bits.echo // Finishing an AMO from the CAM has highest priority TLArbiter(TLArbiter.lowestIndexFirst)(out.a, (0.U, source_c), (edgeOut.numBeats1(in.a.bits), source_i)) // Capture the A state into the CAM when (source_i.fire && !a_isSupported) { (a_cam_sel_free zip cam_a) foreach { case (en, r) => when (en) { r.fifoId := a_fifoId r.bits := in.a.bits r.lut := MuxLookup(in.a.bits.param(1, 0), 0.U(4.W))(Array( TLAtomics.AND -> 0x8.U, TLAtomics.OR -> 0xe.U, TLAtomics.XOR -> 0x6.U, TLAtomics.SWAP -> 0xc.U)) } } (a_cam_sel_free zip cam_s) foreach { case (en, r) => when (en) { r.state := GET } } } // Advance the put state when (source_c.fire) { (a_cam_sel_put zip cam_s) foreach { case (en, r) => when (en) { r.state := ACK } } } // We need to deal with a potential D response in the same cycle as the A request val d_first = edgeOut.first(out.d) val d_cam_sel_raw = cam_a.map(_.bits.source === in.d.bits.source) val d_cam_sel_match = (d_cam_sel_raw zip cam_dmatch) map { case (a,b) => a&&b } val d_cam_data = Mux1H(d_cam_sel_match, cam_d.map(_.data)) val d_cam_denied = Mux1H(d_cam_sel_match, cam_d.map(_.denied)) val d_cam_corrupt = Mux1H(d_cam_sel_match, cam_d.map(_.corrupt)) val d_cam_sel_bypass = if (edgeOut.manager.minLatency > 0) false.B else out.d.bits.source === in.a.bits.source && in.a.valid && !a_isSupported val d_cam_sel = (a_cam_sel_free zip d_cam_sel_match) map { case (a,d) => Mux(d_cam_sel_bypass, a, d) } val d_cam_sel_any = d_cam_sel_bypass \|\| d_cam_sel_match.reduce(_ \|\| _) val d_ackd = out.d.bits.opcode === TLMessages.AccessAckData val d_ack = out.d.bits.opcode === TLMessages.AccessAck when (out.d.fire && d_first) { (d_cam_sel zip cam_d) foreach { case (en, r) => when (en && d_ackd) { r.data := out.d.bits.data r.denied := out.d.bits.denied r.corrupt := out.d.bits.corrupt } } (d_cam_sel zip cam_s) foreach { case (en, r) => when (en) { // Note: it is important that this comes AFTER the := GET, so we can go FREE=>GET=>AMO in one cycle r.state := Mux(d_ackd, AMO, FREE) } } } val d_drop = d_first && d_ackd && d_cam_sel_any val d_replace = d_first && d_ack && d_cam_sel_match.reduce(_ \|\| _) in.d.valid := out.d.valid && !d_drop out.d.ready := in.d.ready \|\| d_drop in.d.bits := out.d.bits when (d_replace) { // minimal muxes in.d.bits.opcode := TLMessages.AccessAckData in.d.bits.data := d_cam_data in.d.bits.corrupt := d_cam_corrupt \|\| out.d.bits.denied in.d.bits.denied := d_cam_denied \|\| out.d.bits.denied } } else { out.a.valid := in.a.valid in.a.ready := out.a.ready out.a.bits := in.a.bits in.d.valid := out.d.valid out.d.ready := in.d.ready in.d.bits := out.d.bits } if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { in.b.valid := out.b.valid out.b.ready := in.b.ready in.b.bits := out.b.bits out.c.valid := in.c.valid in.c.ready := out.c.ready out.c.bits := in.c.bits out.e.valid := in.e.valid in.e.ready := out.e.ready out.e.bits := in.e.bits } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLAtomicAutomata { def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val atomics = LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough) { override lazy val desiredName = (Seq("TLAtomicAutomata") ++ nameSuffix).mkString("_") }) atomics.node } case class CAMParams(a: TLBundleParameters, domainsNeedingHelp: Int) class CAM_S(val params: CAMParams) extends Bundle { val state = UInt(2.W) } class CAM_A(val params: CAMParams) extends Bundle { val bits = new TLBundleA(params.a) val fifoId = UInt(log2Up(params.domainsNeedingHelp).W) val lut = UInt(4.W) } class CAM_D(val params: CAMParams) extends Bundle { val data = UInt(params.a.dataBits.W) val denied = Bool() val corrupt = Bool() } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMAtomicAutomata(txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("AtomicAutomata")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) // Confirm that the AtomicAutomata combines read + write errors import TLMessages._ val test = new RequestPattern({a: TLBundleA => val doesA = a.opcode === ArithmeticData \|\| a.opcode === LogicalData val doesR = a.opcode === Get \|\| doesA val doesW = a.opcode === PutFullData \|\| a.opcode === PutPartialData \|\| doesA (doesR && RequestPattern.overlaps(Seq(AddressSet(0x08, ~0x08)))(a)) \|\| (doesW && RequestPattern.overlaps(Seq(AddressSet(0x10, ~0x10)))(a)) }) (ram.node := TLErrorEvaluator(test) := TLFragmenter(4, 256) := TLDelayer(0.1) := TLAtomicAutomata() := TLDelayer(0.1) := TLErrorEvaluator(test, testOn=true, testOff=true) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMAtomicAutomataTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMAtomicAutomata(txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File PeripheryBus.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.{BuiltInZeroDeviceParams, BuiltInErrorDeviceParams, HasBuiltInDeviceParams, BuiltInDevices} import freechips.rocketchip.diplomacy.BufferParams import freechips.rocketchip.tilelink.{ RegionReplicator, ReplicatedRegion, HasTLBusParams, HasRegionReplicatorParams, TLBusWrapper, TLBusWrapperInstantiationLike, TLFIFOFixer, TLNode, TLXbar, TLInwardNode, TLOutwardNode, TLBuffer, TLWidthWidget, TLAtomicAutomata, TLEdge } import freechips.rocketchip.util.Location case class BusAtomics( arithmetic: Boolean = true, buffer: BufferParams = BufferParams.default, widenBytes: Option[Int] = None ) case class PeripheryBusParams( beatBytes: Int, blockBytes: Int, atomics: Option[BusAtomics] = Some(BusAtomics()), dtsFrequency: Option[BigInt] = None, zeroDevice: Option[BuiltInZeroDeviceParams] = None, errorDevice: Option[BuiltInErrorDeviceParams] = None, replication: Option[ReplicatedRegion] = None) extends HasTLBusParams with HasBuiltInDeviceParams with HasRegionReplicatorParams with TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): PeripheryBus = { val pbus = LazyModule(new PeripheryBus(this, loc.name)) pbus.suggestName(loc.name) context.tlBusWrapperLocationMap += (loc -> pbus) pbus } } class PeripheryBus(params: PeripheryBusParams, name: String)(implicit p: Parameters) extends TLBusWrapper(params, name) { override lazy val desiredName = s"PeripheryBus_$name" private val replicator = params.replication.map(r => LazyModule(new RegionReplicator(r))) val prefixNode = replicator.map { r => r.prefix := addressPrefixNexusNode addressPrefixNexusNode } private val fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all)) private val node: TLNode = params.atomics.map { pa => val in_xbar = LazyModule(new TLXbar(nameSuffix = Some(s"${name}_in"))) val out_xbar = LazyModule(new TLXbar(nameSuffix = Some(s"${name}_out"))) val fixer_node = replicator.map(fixer.node := _.node).getOrElse(fixer.node) (out_xbar.node := fixer_node := TLBuffer(pa.buffer) := (pa.widenBytes.filter(_ > beatBytes).map { w => TLWidthWidget(w) := TLAtomicAutomata(arithmetic = pa.arithmetic, nameSuffix = Some(name)) } .getOrElse { TLAtomicAutomata(arithmetic = pa.arithmetic, nameSuffix = Some(name)) }) := in_xbar.node) } .getOrElse { TLXbar() := fixer.node } def inwardNode: TLInwardNode = node def outwardNode: TLOutwardNode = node def busView: TLEdge = fixer.node.edges.in.head val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode) } File ClockGroup.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.prci import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.resources.FixedClockResource case class ClockGroupingNode(groupName: String)(implicit valName: ValName) extends MixedNexusNode(ClockGroupImp, ClockImp)( dFn = { _ => ClockSourceParameters() }, uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq) }) { override def circuitIdentity = outputs.size == 1 } class ClockGroup(groupName: String)(implicit p: Parameters) extends LazyModule { val node = ClockGroupingNode(groupName) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in(0) val (out, _) = node.out.unzip require (node.in.size == 1) require (in.member.size == out.size) (in.member.data zip out) foreach { case (i, o) => o := i } } } object ClockGroup { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroup(valName.name)).node } case class ClockGroupAggregateNode(groupName: String)(implicit valName: ValName) extends NexusNode(ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq.flatMap(_.members))}) { override def circuitIdentity = outputs.size == 1 } class ClockGroupAggregator(groupName: String)(implicit p: Parameters) extends LazyModule { val node = ClockGroupAggregateNode(groupName) override lazy val desiredName = s"ClockGroupAggregator_$groupName" lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in.unzip val (out, _) = node.out.unzip val outputs = out.flatMap(_.member.data) require (node.in.size == 1, s"Aggregator for groupName: ${groupName} had ${node.in.size} inward edges instead of 1") require (in.head.member.size == outputs.size) in.head.member.data.zip(outputs).foreach { case (i, o) => o := i } } } object ClockGroupAggregator { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupAggregator(valName.name)).node } class SimpleClockGroupSource(numSources: Int = 1)(implicit p: Parameters) extends LazyModule { val node = ClockGroupSourceNode(List.fill(numSources) { ClockGroupSourceParameters() }) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val (out, _) = node.out.unzip out.map { out: ClockGroupBundle => out.member.data.foreach { o => o.clock := clock; o.reset := reset } } } } object SimpleClockGroupSource { def apply(num: Int = 1)(implicit p: Parameters, valName: ValName) = LazyModule(new SimpleClockGroupSource(num)).node } case class FixedClockBroadcastNode(fixedClockOpt: Option[ClockParameters])(implicit valName: ValName) extends NexusNode(ClockImp)( dFn = { seq => fixedClockOpt.map(_ => ClockSourceParameters(give = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSourceParameters()) }, uFn = { seq => fixedClockOpt.map(_ => ClockSinkParameters(take = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSinkParameters()) }, inputRequiresOutput = false) { def fixedClockResources(name: String, prefix: String = "soc/"): Seq[Option[FixedClockResource]] = Seq(fixedClockOpt.map(t => new FixedClockResource(name, t.freqMHz, prefix))) } class FixedClockBroadcast(fixedClockOpt: Option[ClockParameters])(implicit p: Parameters) extends LazyModule { val node = new FixedClockBroadcastNode(fixedClockOpt) { override def circuitIdentity = outputs.size == 1 } lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in(0) val (out, _) = node.out.unzip override def desiredName = s"FixedClockBroadcast_${out.size}" require (node.in.size == 1, "FixedClockBroadcast can only broadcast a single clock") out.foreach { _ := in } } } object FixedClockBroadcast { def apply(fixedClockOpt: Option[ClockParameters] = None)(implicit p: Parameters, valName: ValName) = LazyModule(new FixedClockBroadcast(fixedClockOpt)).node } case class PRCIClockGroupNode()(implicit valName: ValName) extends NexusNode(ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, uFn = { _ => ClockGroupSinkParameters("prci", Nil) }, outputRequiresInput = false) File WidthWidget.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.util.{Repeater, UIntToOH1} // innBeatBytes => the new client-facing bus width class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule { private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes val node = new TLAdapterNode( clientFn = { case c => c }, managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){ override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired) } override lazy val desiredName = s"TLWidthWidget$innerBeatBytes" lazy val module = new Impl class Impl extends LazyModuleImp(this) { def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = outBytes / inBytes val keepBits = log2Ceil(outBytes) val dropBits = log2Ceil(inBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit \|\| !hasData val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR } val corrupt_reg = RegInit(false.B) val corrupt_in = edgeIn.corrupt(in.bits) val corrupt_out = corrupt_in \|\| corrupt_reg when (in.fire) { count := count + 1.U corrupt_reg := corrupt_out when (last) { count := 0.U corrupt_reg := false.B } } def helper(idata: UInt): UInt = { // rdata is X until the first time a multi-beat write occurs. // Prevent the X from leaking outside by jamming the mux control until // the first time rdata is written (and hence no longer X). val rdata_written_once = RegInit(false.B) val masked_enable = enable.map(_ \|\| !rdata_written_once) val odata = Seq.fill(ratio) { WireInit(idata) } val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata))) val pdata = rdata :+ idata val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) } when (in.fire && !last) { rdata_written_once := true.B (rdata zip mdata) foreach { case (r, m) => r := m } } Cat(mdata.reverse) } in.ready := out.ready \|\| !last out.valid := in.valid && last out.bits := in.bits // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits))) edgeOut.corrupt(out.bits) := corrupt_out (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleC, i: TLBundleC) => () case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossible bundle combination in WidthWidget") } } def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = inBytes / outBytes val keepBits = log2Ceil(inBytes) val dropBits = log2Ceil(outBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit \|\| !hasData when (out.fire) { count := count + 1.U when (last) { count := 0.U } } // For sub-beat transfer, extract which part matters val sel = in.bits match { case a: TLBundleA => a.address(keepBits-1, dropBits) case b: TLBundleB => b.address(keepBits-1, dropBits) case c: TLBundleC => c.address(keepBits-1, dropBits) case d: TLBundleD => { val sel = sourceMap(d.source) val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway } } val index = sel \| count def helper(idata: UInt, width: Int): UInt = { val mux = VecInit.tabulate(ratio) { i => idata((i+1)outByteswidth-1, ioutByteswidth) } mux(index) } out.bits := in.bits out.valid := in.valid in.ready := out.ready // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8)) (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1) case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1) case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossbile bundle combination in WidthWidget") } // Repeat the input if we're not last !last } def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) { // nothing to do; pass it through out.bits := in.bits out.valid := in.valid in.ready := out.ready } else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) { // split input to output val repeat = Wire(Bool()) val repeated = Repeater(in, repeat) val cated = Wire(chiselTypeOf(repeated)) cated <> repeated edgeIn.data(cated.bits) := Cat( edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes8-1, edgeOut.manager.beatBytes8), edgeIn.data(in.bits)(edgeOut.manager.beatBytes8-1, 0)) repeat := split(edgeIn, cated, edgeOut, out, sourceMap) } else { // merge input to output merge(edgeIn, in, edgeOut, out) } } (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => // If the master is narrower than the slave, the D channel must be narrowed. // This is tricky, because the D channel has no address data. // Thus, you don't know which part of a sub-beat transfer to extract. // To fix this, we record the relevant address bits for all sources. // The assumption is that this sort of situation happens only where // you connect a narrow master to the system bus, so there are few sources. def sourceMap(source_bits: UInt) = { val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes) val keepBits = log2Ceil(edgeOut.manager.beatBytes) val dropBits = log2Ceil(edgeIn.manager.beatBytes) val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W))) val a_sel = in.a.bits.address(keepBits-1, dropBits) when (in.a.fire) { if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning sources(0) := a_sel } else { sources(in.a.bits.source) := a_sel } } // depopulate unused source registers: edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U } val bypass = in.a.valid && in.a.bits.source === source if (edgeIn.manager.minLatency > 0) sources(source) else Mux(bypass, a_sel, sources(source)) } splice(edgeIn, in.a, edgeOut, out.a, sourceMap) splice(edgeOut, out.d, edgeIn, in.d, sourceMap) if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { splice(edgeOut, out.b, edgeIn, in.b, sourceMap) splice(edgeIn, in.c, edgeOut, out.c, sourceMap) out.e.valid := in.e.valid out.e.bits := in.e.bits in.e.ready := out.e.ready } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLWidthWidget { def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode = { val widget = LazyModule(new TLWidthWidget(innerBeatBytes)) widget.node } def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("WidthWidget")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) (ram.node := TLDelayer(0.1) := TLFragmenter(4, 256) := TLWidthWidget(second) := TLWidthWidget(first) := TLDelayer(0.1) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module) dut.io.start := DontCare io.finished := dut.io.finished } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} \|acquireB = ${acquireB} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT \|\| supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB \|\| regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED \|\| supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED \|\| supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB \|\| supportsGet, w = supportsAcquireT \|\| supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} \|Slave Address = ${address} \|supports = ${supports.infoString} \| \|""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ \|\| _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ \|\| _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_\|\|_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ \|\| _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B \|\| s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} \|visibility = ${visibility} \|emits = ${emits.infoString} \|sourceId = ${sourceId} \| \|""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ \|\| _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ \|\| _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ \|\| _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ \|\| _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ \|\| _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ \|\| _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ \|\| _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ \|\| _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE \|\| x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps / class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File CustomBootPin.scala: package testchipip.boot import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ case class CustomBootPinParams( customBootAddress: BigInt = 0x80000000L, // Default is DRAM_BASE masterWhere: TLBusWrapperLocation = CBUS // This needs to write to clint and bootaddrreg, which are on CBUS/PBUS ) case object CustomBootPinKey extends Field[Option[CustomBootPinParams]](None) trait CanHavePeripheryCustomBootPin { this: BaseSubsystem => val custom_boot_pin = p(CustomBootPinKey).map { params => require(p(BootAddrRegKey).isDefined, "CustomBootPin relies on existence of BootAddrReg") val tlbus = locateTLBusWrapper(params.masterWhere) val clientParams = TLMasterPortParameters.v1( clients = Seq(TLMasterParameters.v1( name = "custom-boot", sourceId = IdRange(0, 1), )), minLatency = 1 ) val inner_io = tlbus { val node = TLClientNode(Seq(clientParams)) tlbus.coupleFrom(s"port_named_custom_boot_pin") ({ _ := node }) InModuleBody { val custom_boot = IO(Input(Bool())).suggestName("custom_boot") val (tl, edge) = node.out(0) val inactive :: waiting_bootaddr_reg_a :: waiting_bootaddr_reg_d :: waiting_msip_a :: waiting_msip_d :: dead :: Nil = Enum(6) val state = RegInit(inactive) tl.a.valid := false.B tl.a.bits := DontCare tl.d.ready := true.B switch (state) { is (inactive) { when (custom_boot) { state := waiting_bootaddr_reg_a } } is (waiting_bootaddr_reg_a) { tl.a.valid := true.B tl.a.bits := edge.Put( toAddress = p(BootAddrRegKey).get.bootRegAddress.U, fromSource = 0.U, lgSize = 2.U, data = params.customBootAddress.U )._2 when (tl.a.fire) { state := waiting_bootaddr_reg_d } } is (waiting_bootaddr_reg_d) { when (tl.d.fire) { state := waiting_msip_a } } is (waiting_msip_a) { tl.a.valid := true.B tl.a.bits := edge.Put( toAddress = (p(CLINTKey).get.baseAddress + CLINTConsts.msipOffset(0)).U, // msip for hart0 fromSource = 0.U, lgSize = log2Ceil(CLINTConsts.msipBytes).U, data = 1.U )._2 when (tl.a.fire) { state := waiting_msip_d } } is (waiting_msip_d) { when (tl.d.fire) { state := dead } } is (dead) { when (!custom_boot) { state := inactive } } } custom_boot } } val outer_io = InModuleBody { val custom_boot = IO(Input(Bool())).suggestName("custom_boot") inner_io := custom_boot custom_boot } outer_io } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File LazyScope.scala: package org.chipsalliance.diplomacy.lazymodule import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.ValName /** Allows dynamic creation of [[Module]] hierarchy and "shoving" logic into a [[LazyModule]]. / trait LazyScope { this: LazyModule => override def toString: String = s"LazyScope named $name" /* Evaluate `body` in the current [[LazyModule.scope]] / def apply[T](body: => T): T = { // Preserve the previous value of the [[LazyModule.scope]], because when calling [[apply]] function, // [[LazyModule.scope]] will be altered. val saved = LazyModule.scope // [[LazyModule.scope]] stack push. LazyModule.scope = Some(this) // Evaluate [[body]] in the current `scope`, saving the result to [[out]]. val out = body // Check that the `scope` after evaluating `body` is the same as when we started. require(LazyModule.scope.isDefined, s"LazyScope $name tried to exit, but scope was empty!") require( LazyModule.scope.get eq this, s"LazyScope $name exited before LazyModule ${LazyModule.scope.get.name} was closed" ) // [[LazyModule.scope]] stack pop. LazyModule.scope = saved out } } /* Used to automatically create a level of module hierarchy (a [[SimpleLazyModule]]) within which [[LazyModule]]s can * be instantiated and connected. * * It will instantiate a [[SimpleLazyModule]] to manage evaluation of `body` and evaluate `body` code snippets in this * scope. / object LazyScope { /* Create a [[LazyScope]] with an implicit instance name. * * @param body * code executed within the generated [[SimpleLazyModule]]. * @param valName * instance name of generated [[SimpleLazyModule]]. * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. / def apply[T]( body: => T )( implicit valName: ValName, p: Parameters ): T = { apply(valName.value, "SimpleLazyModule", None)(body)(p) } /* Create a [[LazyScope]] with an explicitly defined instance name. * * @param name * instance name of generated [[SimpleLazyModule]]. * @param body * code executed within the generated `SimpleLazyModule` * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. / def apply[T]( name: String )(body: => T )( implicit p: Parameters ): T = { apply(name, "SimpleLazyModule", None)(body)(p) } /* Create a [[LazyScope]] with an explicit instance and class name, and control inlining. * * @param name * instance name of generated [[SimpleLazyModule]]. * @param desiredModuleName * class name of generated [[SimpleLazyModule]]. * @param overrideInlining * tell FIRRTL that this [[SimpleLazyModule]]'s module should be inlined. * @param body * code executed within the generated `SimpleLazyModule` * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. / def apply[T]( name: String, desiredModuleName: String, overrideInlining: Option[Boolean] = None )(body: => T )( implicit p: Parameters ): T = { val scope = LazyModule(new SimpleLazyModule with LazyScope { override lazy val desiredName = desiredModuleName override def shouldBeInlined = overrideInlining.getOrElse(super.shouldBeInlined) }).suggestName(name) scope { body } } /* Create a [[LazyScope]] to temporarily group children for some reason, but tell Firrtl to inline it. * * For example, we might want to control a set of children's clocks but then not keep the parent wrapper. * * @param body * code executed within the generated `SimpleLazyModule` * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. */ def inline[T]( body: => T )( implicit p: Parameters ): T = { apply("noname", "ShouldBeInlined", Some(false))(body)(p) } }	module PeripheryBus_cbus( // @[ClockDomain.scala:14:9] input auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [20:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bootrom_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bootrom_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [16:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bootrom_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bootrom_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_debug_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_debug_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [11:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_debug_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_debug_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_plic_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_plic_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_plic_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_plic_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_clint_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_clint_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_clint_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_clint_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_l2_ctrl_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_l2_ctrl_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_l2_ctrl_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_l2_ctrl_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_5_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_5_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_4_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_4_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_3_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_3_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_2_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_2_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_1_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_1_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_0_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_0_reset, // @[LazyModuleImp.scala:107:25] input auto_cbus_clock_groups_in_member_cbus_0_clock, // @[LazyModuleImp.scala:107:25] input auto_cbus_clock_groups_in_member_cbus_0_reset, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input custom_boot // @[CustomBootPin.scala:36:29] ); wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_valid; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_a_ready; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_valid; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_a_valid; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_a_ready; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [28:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_address; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire [6:0] coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire [28:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [6:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_auto_widget_anon_in_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_widget_anon_in_a_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [28:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [6:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire buffer_1_auto_out_d_valid; // @[Buffer.scala:40:9] wire buffer_1_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_1_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire buffer_1_auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_1_auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire [5:0] buffer_1_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_1_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_1_auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_1_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_1_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_1_auto_in_d_valid; // @[Buffer.scala:40:9] wire buffer_1_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_1_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_1_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire buffer_1_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_1_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [5:0] buffer_1_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_1_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_1_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_1_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_1_auto_in_a_valid; // @[Buffer.scala:40:9] wire buffer_1_auto_in_a_ready; // @[Buffer.scala:40:9] wire buffer_1_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_1_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_1_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [28:0] buffer_1_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [5:0] buffer_1_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_1_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_1_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_1_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire cbus_clock_groups_auto_out_member_cbus_0_reset; // @[ClockGroup.scala:53:9] wire cbus_clock_groups_auto_out_member_cbus_0_clock; // @[ClockGroup.scala:53:9] wire _coupler_to_prci_ctrl_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_prci_ctrl_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [1:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_param; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire _coupler_to_prci_ctrl_auto_tl_in_d_bits_sink; // @[LazyScope.scala:98:27] wire _coupler_to_prci_ctrl_auto_tl_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_prci_ctrl_auto_tl_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_to_bootrom_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_bootrom_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_bootrom_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_bootrom_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_bootrom_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_debug_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_debug_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_debug_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_debug_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_debug_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_debug_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_plic_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_plic_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_plic_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_plic_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_plic_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_plic_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_clint_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_clint_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_clint_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_clint_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_clint_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_clint_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_l2_ctrl_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_l2_ctrl_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [1:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_param; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire _coupler_to_l2_ctrl_auto_tl_in_d_bits_sink; // @[LazyScope.scala:98:27] wire _coupler_to_l2_ctrl_auto_tl_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_l2_ctrl_auto_tl_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _wrapped_error_device_auto_buffer_in_a_ready; // @[LazyScope.scala:98:27] wire _wrapped_error_device_auto_buffer_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _wrapped_error_device_auto_buffer_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [1:0] _wrapped_error_device_auto_buffer_in_d_bits_param; // @[LazyScope.scala:98:27] wire [3:0] _wrapped_error_device_auto_buffer_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _wrapped_error_device_auto_buffer_in_d_bits_source; // @[LazyScope.scala:98:27] wire _wrapped_error_device_auto_buffer_in_d_bits_sink; // @[LazyScope.scala:98:27] wire _wrapped_error_device_auto_buffer_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _wrapped_error_device_auto_buffer_in_d_bits_data; // @[LazyScope.scala:98:27] wire _wrapped_error_device_auto_buffer_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _atomics_auto_in_a_ready; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_valid; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_in_d_bits_opcode; // @[AtomicAutomata.scala:289:29] wire [1:0] _atomics_auto_in_d_bits_param; // @[AtomicAutomata.scala:289:29] wire [3:0] _atomics_auto_in_d_bits_size; // @[AtomicAutomata.scala:289:29] wire [6:0] _atomics_auto_in_d_bits_source; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_bits_sink; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_bits_denied; // @[AtomicAutomata.scala:289:29] wire [63:0] _atomics_auto_in_d_bits_data; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_bits_corrupt; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_valid; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_opcode; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_param; // @[AtomicAutomata.scala:289:29] wire [3:0] _atomics_auto_out_a_bits_size; // @[AtomicAutomata.scala:289:29] wire [6:0] _atomics_auto_out_a_bits_source; // @[AtomicAutomata.scala:289:29] wire [28:0] _atomics_auto_out_a_bits_address; // @[AtomicAutomata.scala:289:29] wire [7:0] _atomics_auto_out_a_bits_mask; // @[AtomicAutomata.scala:289:29] wire [63:0] _atomics_auto_out_a_bits_data; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_bits_corrupt; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_d_ready; // @[AtomicAutomata.scala:289:29] wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28] wire [3:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28] wire [6:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28] wire _buffer_auto_out_a_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_out_a_bits_opcode; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_out_a_bits_param; // @[Buffer.scala:75:28] wire [3:0] _buffer_auto_out_a_bits_size; // @[Buffer.scala:75:28] wire [6:0] _buffer_auto_out_a_bits_source; // @[Buffer.scala:75:28] wire [28:0] _buffer_auto_out_a_bits_address; // @[Buffer.scala:75:28] wire [7:0] _buffer_auto_out_a_bits_mask; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_out_a_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:75:28] wire _buffer_auto_out_d_ready; // @[Buffer.scala:75:28] wire _out_xbar_auto_anon_in_a_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_in_d_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_in_d_bits_opcode; // @[PeripheryBus.scala:57:30] wire [1:0] _out_xbar_auto_anon_in_d_bits_param; // @[PeripheryBus.scala:57:30] wire [3:0] _out_xbar_auto_anon_in_d_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_in_d_bits_source; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_in_d_bits_sink; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_in_d_bits_denied; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_in_d_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_in_d_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_7_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_7_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_7_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_7_a_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_out_7_a_bits_source; // @[PeripheryBus.scala:57:30] wire [20:0] _out_xbar_auto_anon_out_7_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_7_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_7_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_7_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_7_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_6_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_6_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_6_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_6_a_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_out_6_a_bits_source; // @[PeripheryBus.scala:57:30] wire [16:0] _out_xbar_auto_anon_out_6_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_6_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_6_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_6_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_6_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_5_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_5_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_5_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_5_a_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_out_5_a_bits_source; // @[PeripheryBus.scala:57:30] wire [11:0] _out_xbar_auto_anon_out_5_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_5_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_5_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_5_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_5_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_4_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_4_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_4_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_4_a_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_out_4_a_bits_source; // @[PeripheryBus.scala:57:30] wire [27:0] _out_xbar_auto_anon_out_4_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_4_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_4_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_4_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_4_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_3_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_3_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_3_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_3_a_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_out_3_a_bits_source; // @[PeripheryBus.scala:57:30] wire [25:0] _out_xbar_auto_anon_out_3_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_3_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_3_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_3_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_3_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_out_1_a_bits_source; // @[PeripheryBus.scala:57:30] wire [25:0] _out_xbar_auto_anon_out_1_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_1_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_1_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_param; // @[PeripheryBus.scala:57:30] wire [3:0] _out_xbar_auto_anon_out_0_a_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_out_0_a_bits_source; // @[PeripheryBus.scala:57:30] wire [13:0] _out_xbar_auto_anon_out_0_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_0_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_0_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_d_ready; // @[PeripheryBus.scala:57:30] wire _in_xbar_auto_anon_out_a_valid; // @[PeripheryBus.scala:56:29] wire [2:0] _in_xbar_auto_anon_out_a_bits_opcode; // @[PeripheryBus.scala:56:29] wire [2:0] _in_xbar_auto_anon_out_a_bits_param; // @[PeripheryBus.scala:56:29] wire [3:0] _in_xbar_auto_anon_out_a_bits_size; // @[PeripheryBus.scala:56:29] wire [6:0] _in_xbar_auto_anon_out_a_bits_source; // @[PeripheryBus.scala:56:29] wire [28:0] _in_xbar_auto_anon_out_a_bits_address; // @[PeripheryBus.scala:56:29] wire [7:0] _in_xbar_auto_anon_out_a_bits_mask; // @[PeripheryBus.scala:56:29] wire [63:0] _in_xbar_auto_anon_out_a_bits_data; // @[PeripheryBus.scala:56:29] wire _in_xbar_auto_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:56:29] wire _in_xbar_auto_anon_out_d_ready; // @[PeripheryBus.scala:56:29] wire _fixer_auto_anon_in_a_ready; // @[PeripheryBus.scala:54:33] wire _fixer_auto_anon_in_d_valid; // @[PeripheryBus.scala:54:33] wire [2:0] _fixer_auto_anon_in_d_bits_opcode; // @[PeripheryBus.scala:54:33] wire [1:0] _fixer_auto_anon_in_d_bits_param; // @[PeripheryBus.scala:54:33] wire [3:0] _fixer_auto_anon_in_d_bits_size; // @[PeripheryBus.scala:54:33] wire [6:0] _fixer_auto_anon_in_d_bits_source; // @[PeripheryBus.scala:54:33] wire _fixer_auto_anon_in_d_bits_sink; // @[PeripheryBus.scala:54:33] wire _fixer_auto_anon_in_d_bits_denied; // @[PeripheryBus.scala:54:33] wire [63:0] _fixer_auto_anon_in_d_bits_data; // @[PeripheryBus.scala:54:33] wire _fixer_auto_anon_in_d_bits_corrupt; // @[PeripheryBus.scala:54:33] wire _fixer_auto_anon_out_a_valid; // @[PeripheryBus.scala:54:33] wire [2:0] _fixer_auto_anon_out_a_bits_opcode; // @[PeripheryBus.scala:54:33] wire [2:0] _fixer_auto_anon_out_a_bits_param; // @[PeripheryBus.scala:54:33] wire [3:0] _fixer_auto_anon_out_a_bits_size; // @[PeripheryBus.scala:54:33] wire [6:0] _fixer_auto_anon_out_a_bits_source; // @[PeripheryBus.scala:54:33] wire [28:0] _fixer_auto_anon_out_a_bits_address; // @[PeripheryBus.scala:54:33] wire [7:0] _fixer_auto_anon_out_a_bits_mask; // @[PeripheryBus.scala:54:33] wire [63:0] _fixer_auto_anon_out_a_bits_data; // @[PeripheryBus.scala:54:33] wire _fixer_auto_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:54:33] wire _fixer_auto_anon_out_d_ready; // @[PeripheryBus.scala:54:33] wire auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [6:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_a_ready_0 = auto_coupler_to_bootrom_fragmenter_anon_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_d_valid_0 = auto_coupler_to_bootrom_fragmenter_anon_out_d_valid; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size_0 = auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [10:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source_0 = auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data_0 = auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_a_ready_0 = auto_coupler_to_debug_fragmenter_anon_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_d_valid_0 = auto_coupler_to_debug_fragmenter_anon_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode_0 = auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_size_0 = auto_coupler_to_debug_fragmenter_anon_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [10:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_source_0 = auto_coupler_to_debug_fragmenter_anon_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_data_0 = auto_coupler_to_debug_fragmenter_anon_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_a_ready_0 = auto_coupler_to_plic_fragmenter_anon_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_d_valid_0 = auto_coupler_to_plic_fragmenter_anon_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode_0 = auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_size_0 = auto_coupler_to_plic_fragmenter_anon_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [10:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_source_0 = auto_coupler_to_plic_fragmenter_anon_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_data_0 = auto_coupler_to_plic_fragmenter_anon_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_a_ready_0 = auto_coupler_to_clint_fragmenter_anon_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_d_valid_0 = auto_coupler_to_clint_fragmenter_anon_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode_0 = auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_size_0 = auto_coupler_to_clint_fragmenter_anon_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [10:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_source_0 = auto_coupler_to_clint_fragmenter_anon_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_data_0 = auto_coupler_to_clint_fragmenter_anon_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [6:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_a_ready_0 = auto_coupler_to_l2_ctrl_buffer_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_d_valid_0 = auto_coupler_to_l2_ctrl_buffer_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode_0 = auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_size_0 = auto_coupler_to_l2_ctrl_buffer_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [10:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_source_0 = auto_coupler_to_l2_ctrl_buffer_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_data_0 = auto_coupler_to_l2_ctrl_buffer_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_cbus_clock_groups_in_member_cbus_0_clock_0 = auto_cbus_clock_groups_in_member_cbus_0_clock; // @[ClockDomain.scala:14:9] wire auto_cbus_clock_groups_in_member_cbus_0_reset_0 = auto_cbus_clock_groups_in_member_cbus_0_reset; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_valid_0 = auto_bus_xing_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_opcode_0 = auto_bus_xing_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_param_0 = auto_bus_xing_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_bus_xing_in_a_bits_size_0 = auto_bus_xing_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] auto_bus_xing_in_a_bits_source_0 = auto_bus_xing_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [28:0] auto_bus_xing_in_a_bits_address_0 = auto_bus_xing_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_bus_xing_in_a_bits_mask_0 = auto_bus_xing_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_bus_xing_in_a_bits_data_0 = auto_bus_xing_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_bits_corrupt_0 = auto_bus_xing_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_ready_0 = auto_bus_xing_in_d_ready; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] nodeOut_a_bits_a_mask_hi_lo = 2'h0; // @[Misc.scala:222:10] wire [1:0] nodeOut_a_bits_a_mask_hi_hi = 2'h0; // @[Misc.scala:222:10] wire [1:0] nodeOut_a_bits_a_mask_hi_lo_1 = 2'h0; // @[Misc.scala:222:10] wire [1:0] nodeOut_a_bits_a_mask_hi_hi_1 = 2'h0; // @[Misc.scala:222:10] wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire cbus_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire cbus_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire cbus_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_source = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_source = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_source = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_source = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_tlOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire coupler_from_port_named_custom_boot_pin_tlIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire coupler_from_port_named_custom_boot_pin_tlIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire _nodeOut_a_bits_legal_T_8 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_9 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_a_bits_legal_T_23 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_28 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_33 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_38 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_43 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_50 = 1'h0; // @[Parameters.scala:684:29] wire _nodeOut_a_bits_legal_T_55 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_56 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_a_bits_legal_T_57 = 1'h0; // @[Parameters.scala:686:26] wire nodeOut_a_bits_a_source = 1'h0; // @[Edges.scala:480:17] wire nodeOut_a_bits_a_corrupt = 1'h0; // @[Edges.scala:480:17] wire nodeOut_a_bits_a_mask_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire nodeOut_a_bits_a_mask_sub_sub_1_2 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_sub_1_1 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _nodeOut_a_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_1_2 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_2_2 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_2_1 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_3_2 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_3_1 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_1 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_eq_2 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_eq_3 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_eq_4 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_4 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_5 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_5 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_6 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_6 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_7 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_7 = 1'h0; // @[Misc.scala:215:29] wire _nodeOut_a_bits_legal_T_67 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_a_bits_legal_T_77 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_82 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_92 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_97 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_102 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_103 = 1'h0; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_109 = 1'h0; // @[Parameters.scala:684:29] wire _nodeOut_a_bits_legal_T_114 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_115 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_a_bits_legal_T_116 = 1'h0; // @[Parameters.scala:686:26] wire nodeOut_a_bits_a_1_source = 1'h0; // @[Edges.scala:480:17] wire nodeOut_a_bits_a_1_corrupt = 1'h0; // @[Edges.scala:480:17] wire nodeOut_a_bits_a_mask_sub_sub_sub_0_1_1 = 1'h0; // @[Misc.scala:206:21] wire nodeOut_a_bits_a_mask_sub_sub_1_2_1 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_sub_1_1_1 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _nodeOut_a_bits_a_mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_1_2_1 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_2_2_1 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_2_1_1 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_3_2_1 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_3_1_1 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_9 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_eq_10 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_eq_11 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_eq_12 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_12 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_13 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_13 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_14 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_14 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_15 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_15 = 1'h0; // @[Misc.scala:215:29] wire [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_opcode = 3'h1; // @[ClockDomain.scala:14:9] wire [7:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_mask = 8'hF; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_mask = 8'hF; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_mask = 8'hF; // @[MixedNode.scala:542:17] wire [7:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_mask = 8'hF; // @[MixedNode.scala:551:17] wire [7:0] nodeOut_a_bits_mask = 8'hF; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_a_mask = 8'hF; // @[Edges.scala:480:17] wire [7:0] _nodeOut_a_bits_a_mask_T = 8'hF; // @[Misc.scala:222:10] wire [7:0] nodeOut_a_bits_a_1_mask = 8'hF; // @[Edges.scala:480:17] wire [7:0] _nodeOut_a_bits_a_mask_T_1 = 8'hF; // @[Misc.scala:222:10] wire [3:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_size = 4'h2; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_size = 4'h2; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_size = 4'h2; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_size = 4'h2; // @[MixedNode.scala:551:17] wire [3:0] nodeOut_a_bits_size = 4'h2; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_a_size = 4'h2; // @[Edges.scala:480:17] wire [3:0] nodeOut_a_bits_a_1_size = 4'h2; // @[Edges.scala:480:17] wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_opcode = 3'h0; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_param = 3'h0; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_opcode = 3'h0; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_param = 3'h0; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_opcode = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_bits_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_a_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] nodeOut_a_bits_a_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] nodeOut_a_bits_a_1_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] nodeOut_a_bits_a_1_param = 3'h0; // @[Edges.scala:480:17] wire [3:0] nodeOut_a_bits_a_mask_hi = 4'h0; // @[Misc.scala:222:10] wire [3:0] nodeOut_a_bits_a_mask_hi_1 = 4'h0; // @[Misc.scala:222:10] wire [3:0] nodeOut_a_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] nodeOut_a_bits_a_mask_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [1:0] nodeOut_a_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] nodeOut_a_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] nodeOut_a_bits_a_mask_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] nodeOut_a_bits_a_mask_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_ready = 1'h1; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_ready = 1'h1; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_tlOut_d_ready = 1'h1; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlIn_d_ready = 1'h1; // @[MixedNode.scala:551:17] wire nodeOut_d_ready = 1'h1; // @[MixedNode.scala:542:17] wire _nodeOut_a_bits_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _nodeOut_a_bits_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _nodeOut_a_bits_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _nodeOut_a_bits_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _nodeOut_a_bits_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _nodeOut_a_bits_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _nodeOut_a_bits_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _nodeOut_a_bits_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _nodeOut_a_bits_legal_T_18 = 1'h1; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_44 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_45 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_46 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_47 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_48 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_49 = 1'h1; // @[Parameters.scala:684:54] wire _nodeOut_a_bits_legal_T_58 = 1'h1; // @[Parameters.scala:686:26] wire nodeOut_a_bits_legal = 1'h1; // @[Parameters.scala:686:26] wire nodeOut_a_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire nodeOut_a_bits_a_mask_sub_sub_nbit = 1'h1; // @[Misc.scala:211:20] wire nodeOut_a_bits_a_mask_sub_sub_0_2 = 1'h1; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_sub_acc_T = 1'h1; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_nbit = 1'h1; // @[Misc.scala:211:20] wire nodeOut_a_bits_a_mask_sub_0_2 = 1'h1; // @[Misc.scala:214:27] wire nodeOut_a_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire nodeOut_a_bits_a_mask_nbit = 1'h1; // @[Misc.scala:211:20] wire nodeOut_a_bits_a_mask_eq = 1'h1; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T = 1'h1; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _nodeOut_a_bits_legal_T_59 = 1'h1; // @[Parameters.scala:92:28] wire _nodeOut_a_bits_legal_T_60 = 1'h1; // @[Parameters.scala:92:38] wire _nodeOut_a_bits_legal_T_61 = 1'h1; // @[Parameters.scala:92:33] wire _nodeOut_a_bits_legal_T_62 = 1'h1; // @[Parameters.scala:684:29] wire _nodeOut_a_bits_legal_T_69 = 1'h1; // @[Parameters.scala:92:28] wire _nodeOut_a_bits_legal_T_70 = 1'h1; // @[Parameters.scala:92:38] wire _nodeOut_a_bits_legal_T_71 = 1'h1; // @[Parameters.scala:92:33] wire _nodeOut_a_bits_legal_T_72 = 1'h1; // @[Parameters.scala:684:29] wire _nodeOut_a_bits_legal_T_87 = 1'h1; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_104 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_105 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_106 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_107 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_108 = 1'h1; // @[Parameters.scala:684:54] wire _nodeOut_a_bits_legal_T_117 = 1'h1; // @[Parameters.scala:686:26] wire nodeOut_a_bits_legal_1 = 1'h1; // @[Parameters.scala:686:26] wire nodeOut_a_bits_a_mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire nodeOut_a_bits_a_mask_sub_sub_nbit_1 = 1'h1; // @[Misc.scala:211:20] wire nodeOut_a_bits_a_mask_sub_sub_0_2_1 = 1'h1; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_sub_acc_T_2 = 1'h1; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_nbit_1 = 1'h1; // @[Misc.scala:211:20] wire nodeOut_a_bits_a_mask_sub_0_2_1 = 1'h1; // @[Misc.scala:214:27] wire nodeOut_a_bits_a_mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire nodeOut_a_bits_a_mask_nbit_1 = 1'h1; // @[Misc.scala:211:20] wire nodeOut_a_bits_a_mask_eq_8 = 1'h1; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_8 = 1'h1; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire [2:0] nodeOut_a_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [2:0] nodeOut_a_bits_a_mask_sizeOH_1 = 3'h5; // @[Misc.scala:202:81] wire [2:0] _nodeOut_a_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] _nodeOut_a_bits_a_mask_sizeOH_T_5 = 3'h4; // @[OneHot.scala:65:27] wire [3:0] _nodeOut_a_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _nodeOut_a_bits_a_mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [1:0] nodeOut_a_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [1:0] nodeOut_a_bits_a_mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [63:0] nodeOut_a_bits_a_1_data = 64'h1; // @[Edges.scala:480:17] wire [28:0] nodeOut_a_bits_a_1_address = 29'h2000000; // @[Edges.scala:480:17] wire [29:0] _nodeOut_a_bits_legal_T_112 = 30'h2010000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_113 = 30'h2010000; // @[Parameters.scala:137:46] wire [26:0] _nodeOut_a_bits_legal_T_111 = 27'h2010000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_99 = 30'h12000000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_100 = 30'h12000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_101 = 30'h12000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_36 = 30'h8000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_37 = 30'h8000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_95 = 30'h8000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_96 = 30'h8000000; // @[Parameters.scala:137:46] wire [28:0] _nodeOut_a_bits_legal_T_94 = 29'hA000000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_53 = 30'h10000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_54 = 30'h10000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_90 = 30'h10000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_91 = 30'h10000; // @[Parameters.scala:137:46] wire [26:0] _nodeOut_a_bits_legal_T_89 = 27'h10000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_16 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_17 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_85 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_86 = 30'h0; // @[Parameters.scala:137:46] wire [26:0] _nodeOut_a_bits_legal_T_84 = 27'h0; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_80 = 30'h2100000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_81 = 30'h2100000; // @[Parameters.scala:137:46] wire [26:0] _nodeOut_a_bits_legal_T_79 = 27'h2100000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_26 = 30'h2000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_27 = 30'h2000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_75 = 30'h2000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_76 = 30'h2000000; // @[Parameters.scala:137:46] wire [26:0] _nodeOut_a_bits_legal_T_74 = 27'h2000000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_65 = 30'h2003000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_66 = 30'h2003000; // @[Parameters.scala:137:46] wire [26:0] _nodeOut_a_bits_legal_T_64 = 27'h2003000; // @[Parameters.scala:137:41] wire [63:0] nodeOut_a_bits_a_data = 64'h80000000; // @[Edges.scala:480:17] wire [28:0] nodeOut_a_bits_a_address = 29'h1000; // @[Edges.scala:480:17] wire [17:0] _nodeOut_a_bits_legal_T_52 = 18'h11000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_40 = 30'h10001000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_41 = 30'h10001000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_42 = 30'h10001000; // @[Parameters.scala:137:46] wire [28:0] _nodeOut_a_bits_legal_T_35 = 29'h8001000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_31 = 30'h2011000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_32 = 30'h2011000; // @[Parameters.scala:137:46] wire [26:0] _nodeOut_a_bits_legal_T_30 = 27'h2011000; // @[Parameters.scala:137:41] wire [26:0] _nodeOut_a_bits_legal_T_25 = 27'h2001000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_21 = 30'h101000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_22 = 30'h101000; // @[Parameters.scala:137:46] wire [21:0] _nodeOut_a_bits_legal_T_20 = 22'h101000; // @[Parameters.scala:137:41] wire [13:0] _nodeOut_a_bits_legal_T_15 = 14'h1000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_6 = 30'h2000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_7 = 30'h2000; // @[Parameters.scala:137:46] wire [14:0] _nodeOut_a_bits_legal_T_5 = 15'h2000; // @[Parameters.scala:137:41] wire [25:0] _nodeOut_a_bits_legal_T_110 = 26'h2010000; // @[Parameters.scala:137:31] wire [28:0] _nodeOut_a_bits_legal_T_98 = 29'h12000000; // @[Parameters.scala:137:31] wire [27:0] _nodeOut_a_bits_legal_T_93 = 28'hA000000; // @[Parameters.scala:137:31] wire [25:0] _nodeOut_a_bits_legal_T_88 = 26'h10000; // @[Parameters.scala:137:31] wire [25:0] _nodeOut_a_bits_legal_T_83 = 26'h0; // @[Parameters.scala:137:31] wire [25:0] _nodeOut_a_bits_legal_T_78 = 26'h2100000; // @[Parameters.scala:137:31] wire [25:0] _nodeOut_a_bits_legal_T_63 = 26'h2003000; // @[Parameters.scala:137:31] wire [16:0] _nodeOut_a_bits_legal_T_51 = 17'h11000; // @[Parameters.scala:137:31] wire [28:0] _nodeOut_a_bits_legal_T_39 = 29'h10001000; // @[Parameters.scala:137:31] wire [27:0] _nodeOut_a_bits_legal_T_34 = 28'h8001000; // @[Parameters.scala:137:31] wire [25:0] _nodeOut_a_bits_legal_T_29 = 26'h2011000; // @[Parameters.scala:137:31] wire [25:0] _nodeOut_a_bits_legal_T_24 = 26'h2001000; // @[Parameters.scala:137:31] wire [20:0] _nodeOut_a_bits_legal_T_19 = 21'h101000; // @[Parameters.scala:137:31] wire [13:0] _nodeOut_a_bits_legal_T_4 = 14'h2000; // @[Parameters.scala:137:31] wire [2:0] _nodeOut_a_bits_a_mask_sizeOH_T = 3'h2; // @[Misc.scala:202:34] wire [2:0] _nodeOut_a_bits_a_mask_sizeOH_T_3 = 3'h2; // @[Misc.scala:202:34] wire [25:0] _nodeOut_a_bits_legal_T_73 = 26'h2000000; // @[Parameters.scala:137:31] wire [12:0] _nodeOut_a_bits_legal_T_14 = 13'h1000; // @[Parameters.scala:137:31] wire coupler_to_bus_named_pbus_auto_bus_xing_out_a_ready = auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_pbus_auto_bus_xing_out_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [6:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [28:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_bus_xing_out_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_bus_xing_out_d_valid = auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_opcode = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_param = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_size = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [6:0] coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_source = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_sink = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_denied = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_data = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_corrupt = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire cbus_clock_groups_auto_in_member_cbus_0_clock = auto_cbus_clock_groups_in_member_cbus_0_clock_0; // @[ClockGroup.scala:53:9] wire cbus_clock_groups_auto_in_member_cbus_0_reset = auto_cbus_clock_groups_in_member_cbus_0_reset_0; // @[ClockGroup.scala:53:9] wire bus_xingIn_a_ready; // @[MixedNode.scala:551:17] wire bus_xingIn_a_valid = auto_bus_xing_in_a_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_opcode = auto_bus_xing_in_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_param = auto_bus_xing_in_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] bus_xingIn_a_bits_size = auto_bus_xing_in_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] bus_xingIn_a_bits_source = auto_bus_xing_in_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [28:0] bus_xingIn_a_bits_address = auto_bus_xing_in_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] bus_xingIn_a_bits_mask = auto_bus_xing_in_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] bus_xingIn_a_bits_data = auto_bus_xing_in_a_bits_data_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_a_bits_corrupt = auto_bus_xing_in_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_d_ready = auto_bus_xing_in_d_ready_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17] wire [5:0] bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [6:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [20:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [10:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [16:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [10:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [11:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [10:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [27:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [10:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [25:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [6:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [28:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [10:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [25:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_d_ready_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_5_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_5_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_4_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_4_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_3_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_3_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_2_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_2_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] wire cbus_clock_groups_nodeIn_member_cbus_0_clock = cbus_clock_groups_auto_in_member_cbus_0_clock; // @[ClockGroup.scala:53:9] wire cbus_clock_groups_nodeOut_member_cbus_0_clock; // @[MixedNode.scala:542:17] wire cbus_clock_groups_nodeIn_member_cbus_0_reset = cbus_clock_groups_auto_in_member_cbus_0_reset; // @[ClockGroup.scala:53:9] wire cbus_clock_groups_nodeOut_member_cbus_0_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_in_member_cbus_0_clock = cbus_clock_groups_auto_out_member_cbus_0_clock; // @[ClockGroup.scala:24:9, :53:9] wire clockGroup_auto_in_member_cbus_0_reset = cbus_clock_groups_auto_out_member_cbus_0_reset; // @[ClockGroup.scala:24:9, :53:9] assign cbus_clock_groups_auto_out_member_cbus_0_clock = cbus_clock_groups_nodeOut_member_cbus_0_clock; // @[ClockGroup.scala:53:9] assign cbus_clock_groups_auto_out_member_cbus_0_reset = cbus_clock_groups_nodeOut_member_cbus_0_reset; // @[ClockGroup.scala:53:9] assign cbus_clock_groups_nodeOut_member_cbus_0_clock = cbus_clock_groups_nodeIn_member_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign cbus_clock_groups_nodeOut_member_cbus_0_reset = cbus_clock_groups_nodeIn_member_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17] wire clockGroup_nodeIn_member_cbus_0_clock = clockGroup_auto_in_member_cbus_0_clock; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17] wire clockGroup_nodeIn_member_cbus_0_reset = clockGroup_auto_in_member_cbus_0_reset; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9] wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9] assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17] wire buffer_1_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire bus_xingOut_a_ready = buffer_1_auto_in_a_ready; // @[Buffer.scala:40:9] wire bus_xingOut_a_valid; // @[MixedNode.scala:542:17] wire buffer_1_nodeIn_a_valid = buffer_1_auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_1_nodeIn_a_bits_opcode = buffer_1_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_1_nodeIn_a_bits_param = buffer_1_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_1_nodeIn_a_bits_size = buffer_1_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [5:0] bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [5:0] buffer_1_nodeIn_a_bits_source = buffer_1_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [28:0] bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [28:0] buffer_1_nodeIn_a_bits_address = buffer_1_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_1_nodeIn_a_bits_mask = buffer_1_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_1_nodeIn_a_bits_data = buffer_1_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_1_nodeIn_a_bits_corrupt = buffer_1_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire bus_xingOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_1_nodeIn_d_ready = buffer_1_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_1_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_1_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire bus_xingOut_d_valid = buffer_1_auto_in_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_1_nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] bus_xingOut_d_bits_opcode = buffer_1_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_1_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] bus_xingOut_d_bits_param = buffer_1_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [5:0] buffer_1_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] bus_xingOut_d_bits_size = buffer_1_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire buffer_1_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [5:0] bus_xingOut_d_bits_source = buffer_1_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire buffer_1_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire bus_xingOut_d_bits_sink = buffer_1_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_1_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire bus_xingOut_d_bits_denied = buffer_1_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_1_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] bus_xingOut_d_bits_data = buffer_1_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire bus_xingOut_d_bits_corrupt = buffer_1_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_1_nodeOut_a_ready = buffer_1_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_1_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] buffer_1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_1_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] buffer_1_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [5:0] buffer_1_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] buffer_1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] buffer_1_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] buffer_1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire buffer_1_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_1_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_1_nodeOut_d_valid = buffer_1_auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_1_nodeOut_d_bits_opcode = buffer_1_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_1_nodeOut_d_bits_param = buffer_1_auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_1_nodeOut_d_bits_size = buffer_1_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [5:0] buffer_1_nodeOut_d_bits_source = buffer_1_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire buffer_1_nodeOut_d_bits_sink = buffer_1_auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_1_nodeOut_d_bits_denied = buffer_1_auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_1_nodeOut_d_bits_data = buffer_1_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire buffer_1_nodeOut_d_bits_corrupt = buffer_1_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire [2:0] buffer_1_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_1_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_1_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [5:0] buffer_1_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [28:0] buffer_1_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_1_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_1_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_1_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_1_auto_out_a_valid; // @[Buffer.scala:40:9] wire buffer_1_auto_out_d_ready; // @[Buffer.scala:40:9] assign buffer_1_nodeIn_a_ready = buffer_1_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_auto_out_a_valid = buffer_1_nodeOut_a_valid; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_opcode = buffer_1_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_param = buffer_1_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_size = buffer_1_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_source = buffer_1_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_address = buffer_1_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_mask = buffer_1_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_data = buffer_1_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_corrupt = buffer_1_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_1_auto_out_d_ready = buffer_1_nodeOut_d_ready; // @[Buffer.scala:40:9] assign buffer_1_nodeIn_d_valid = buffer_1_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_opcode = buffer_1_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_param = buffer_1_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_size = buffer_1_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_source = buffer_1_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_sink = buffer_1_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_denied = buffer_1_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_data = buffer_1_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_corrupt = buffer_1_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_auto_in_a_ready = buffer_1_nodeIn_a_ready; // @[Buffer.scala:40:9] assign buffer_1_nodeOut_a_valid = buffer_1_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_opcode = buffer_1_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_param = buffer_1_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_size = buffer_1_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_source = buffer_1_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_address = buffer_1_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_mask = buffer_1_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_data = buffer_1_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_corrupt = buffer_1_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_d_ready = buffer_1_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_auto_in_d_valid = buffer_1_nodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_opcode = buffer_1_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_param = buffer_1_nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_size = buffer_1_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_source = buffer_1_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_sink = buffer_1_nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_denied = buffer_1_nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_data = buffer_1_nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_corrupt = buffer_1_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_a_valid = coupler_to_bus_named_pbus_auto_widget_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_opcode = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_param = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_size = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [6:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_source = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [28:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_address = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_mask = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_data = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_corrupt = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_d_ready = coupler_to_bus_named_pbus_auto_widget_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [6:0] coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_bus_xingOut_a_ready = coupler_to_bus_named_pbus_auto_bus_xing_out_a_ready; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_pbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_size; // @[ClockDomain.scala:14:9] wire [6:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_source; // @[ClockDomain.scala:14:9] wire [28:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_data; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_pbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_pbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_d_ready; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_pbus_bus_xingOut_d_valid = coupler_to_bus_named_pbus_auto_bus_xing_out_d_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_pbus_bus_xingOut_d_bits_opcode = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_to_bus_named_pbus_bus_xingOut_d_bits_param = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_param; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_pbus_bus_xingOut_d_bits_size = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_size; // @[MixedNode.scala:542:17] wire [6:0] coupler_to_bus_named_pbus_bus_xingOut_d_bits_source = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_source; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_pbus_bus_xingOut_d_bits_sink = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_sink; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_pbus_bus_xingOut_d_bits_denied = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_denied; // @[MixedNode.scala:542:17] wire [63:0] coupler_to_bus_named_pbus_bus_xingOut_d_bits_data = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_data; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_pbus_bus_xingOut_d_bits_corrupt = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_pbus_auto_widget_anon_in_a_ready; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [6:0] coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_source; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_widget_anon_in_d_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_widget_anonIn_a_ready; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_a_ready = coupler_to_bus_named_pbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonIn_a_valid = coupler_to_bus_named_pbus_widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_opcode = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_param = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_size = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [6:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_source = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [28:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_address = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_mask = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_data = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonIn_a_bits_corrupt = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonIn_d_ready = coupler_to_bus_named_pbus_widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonIn_d_valid; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_valid = coupler_to_bus_named_pbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_opcode = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_pbus_widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_param = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_size = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [6:0] coupler_to_bus_named_pbus_widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_source = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_sink = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_denied = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_data = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_corrupt = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_bus_xingIn_a_ready; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_pbus_widget_anonOut_a_ready = coupler_to_bus_named_pbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_pbus_bus_xingIn_a_valid = coupler_to_bus_named_pbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_opcode = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_param = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [6:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_size = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire [28:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [6:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_source = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [28:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_address = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire [7:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_mask = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_data = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonOut_d_ready; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_pbus_bus_xingIn_a_bits_corrupt = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_bus_xingIn_d_ready = coupler_to_bus_named_pbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_bus_xingIn_d_valid; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_pbus_widget_anonOut_d_valid = coupler_to_bus_named_pbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_pbus_widget_anonOut_d_bits_opcode = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_pbus_bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] coupler_to_bus_named_pbus_widget_anonOut_d_bits_param = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_pbus_widget_anonOut_d_bits_size = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [6:0] coupler_to_bus_named_pbus_bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17] wire [6:0] coupler_to_bus_named_pbus_widget_anonOut_d_bits_source = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_pbus_widget_anonOut_d_bits_sink = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_pbus_widget_anonOut_d_bits_denied = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17] wire [63:0] coupler_to_bus_named_pbus_widget_anonOut_d_bits_data = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_pbus_widget_anonOut_d_bits_corrupt = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_anonIn_a_ready = coupler_to_bus_named_pbus_widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_valid = coupler_to_bus_named_pbus_widget_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_opcode = coupler_to_bus_named_pbus_widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_param = coupler_to_bus_named_pbus_widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_size = coupler_to_bus_named_pbus_widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_source = coupler_to_bus_named_pbus_widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_address = coupler_to_bus_named_pbus_widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_mask = coupler_to_bus_named_pbus_widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_data = coupler_to_bus_named_pbus_widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_corrupt = coupler_to_bus_named_pbus_widget_anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_ready = coupler_to_bus_named_pbus_widget_anonOut_d_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_anonIn_d_valid = coupler_to_bus_named_pbus_widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_opcode = coupler_to_bus_named_pbus_widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_param = coupler_to_bus_named_pbus_widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_size = coupler_to_bus_named_pbus_widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_source = coupler_to_bus_named_pbus_widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_sink = coupler_to_bus_named_pbus_widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_denied = coupler_to_bus_named_pbus_widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_data = coupler_to_bus_named_pbus_widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_corrupt = coupler_to_bus_named_pbus_widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_auto_anon_in_a_ready = coupler_to_bus_named_pbus_widget_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_anonOut_a_valid = coupler_to_bus_named_pbus_widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_opcode = coupler_to_bus_named_pbus_widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_param = coupler_to_bus_named_pbus_widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_size = coupler_to_bus_named_pbus_widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_source = coupler_to_bus_named_pbus_widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_address = coupler_to_bus_named_pbus_widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_mask = coupler_to_bus_named_pbus_widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_data = coupler_to_bus_named_pbus_widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_corrupt = coupler_to_bus_named_pbus_widget_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_d_ready = coupler_to_bus_named_pbus_widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_valid = coupler_to_bus_named_pbus_widget_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_opcode = coupler_to_bus_named_pbus_widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_param = coupler_to_bus_named_pbus_widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_size = coupler_to_bus_named_pbus_widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_source = coupler_to_bus_named_pbus_widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_sink = coupler_to_bus_named_pbus_widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_denied = coupler_to_bus_named_pbus_widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_data = coupler_to_bus_named_pbus_widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_corrupt = coupler_to_bus_named_pbus_widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_bus_xingIn_a_ready = coupler_to_bus_named_pbus_bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_valid = coupler_to_bus_named_pbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_opcode = coupler_to_bus_named_pbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_param = coupler_to_bus_named_pbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_size = coupler_to_bus_named_pbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_source = coupler_to_bus_named_pbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_address = coupler_to_bus_named_pbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_mask = coupler_to_bus_named_pbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_data = coupler_to_bus_named_pbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_corrupt = coupler_to_bus_named_pbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_d_ready = coupler_to_bus_named_pbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_valid = coupler_to_bus_named_pbus_bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_opcode = coupler_to_bus_named_pbus_bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_param = coupler_to_bus_named_pbus_bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_size = coupler_to_bus_named_pbus_bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_source = coupler_to_bus_named_pbus_bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_sink = coupler_to_bus_named_pbus_bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_denied = coupler_to_bus_named_pbus_bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_data = coupler_to_bus_named_pbus_bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_corrupt = coupler_to_bus_named_pbus_bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_ready = coupler_to_bus_named_pbus_bus_xingIn_a_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_bus_xingOut_a_valid = coupler_to_bus_named_pbus_bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_opcode = coupler_to_bus_named_pbus_bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_param = coupler_to_bus_named_pbus_bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_size = coupler_to_bus_named_pbus_bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_source = coupler_to_bus_named_pbus_bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_address = coupler_to_bus_named_pbus_bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_mask = coupler_to_bus_named_pbus_bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_data = coupler_to_bus_named_pbus_bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_corrupt = coupler_to_bus_named_pbus_bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_d_ready = coupler_to_bus_named_pbus_bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_valid = coupler_to_bus_named_pbus_bus_xingIn_d_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_opcode = coupler_to_bus_named_pbus_bus_xingIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_param = coupler_to_bus_named_pbus_bus_xingIn_d_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_size = coupler_to_bus_named_pbus_bus_xingIn_d_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_source = coupler_to_bus_named_pbus_bus_xingIn_d_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_sink = coupler_to_bus_named_pbus_bus_xingIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_denied = coupler_to_bus_named_pbus_bus_xingIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_data = coupler_to_bus_named_pbus_bus_xingIn_d_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_corrupt = coupler_to_bus_named_pbus_bus_xingIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_from_port_named_custom_boot_pin_tlIn_a_ready; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = coupler_from_port_named_custom_boot_pin_auto_tl_in_a_ready; // @[MixedNode.scala:542:17] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlIn_a_valid = coupler_from_port_named_custom_boot_pin_auto_tl_in_a_valid; // @[MixedNode.scala:551:17] wire [28:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [28:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_address = coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_address; // @[MixedNode.scala:551:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_data = coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_port_named_custom_boot_pin_tlIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_port_named_custom_boot_pin_tlIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire nodeOut_d_valid = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_valid; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_port_named_custom_boot_pin_tlIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_d_bits_opcode = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_port_named_custom_boot_pin_tlIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_d_bits_param = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_d_bits_size = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_size; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlIn_d_bits_sink; // @[MixedNode.scala:551:17] wire coupler_from_port_named_custom_boot_pin_tlIn_d_bits_denied; // @[MixedNode.scala:551:17] wire nodeOut_d_bits_sink = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_sink; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_port_named_custom_boot_pin_tlIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeOut_d_bits_denied = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_denied; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] nodeOut_d_bits_data = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_corrupt = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_a_ready = coupler_from_port_named_custom_boot_pin_auto_tl_out_a_ready; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_a_valid; // @[MixedNode.scala:542:17] wire [28:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_address; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_d_valid = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_port_named_custom_boot_pin_tlOut_d_bits_opcode = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_port_named_custom_boot_pin_tlOut_d_bits_param = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_port_named_custom_boot_pin_tlOut_d_bits_size = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_size; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_d_bits_sink = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_sink; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_d_bits_denied = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_denied; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_port_named_custom_boot_pin_tlOut_d_bits_data = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_d_bits_corrupt = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_corrupt; // @[MixedNode.scala:542:17] wire [28:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_a_valid; // @[LazyModuleImp.scala:138:7] assign coupler_from_port_named_custom_boot_pin_tlIn_a_ready = coupler_from_port_named_custom_boot_pin_tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_out_a_valid = coupler_from_port_named_custom_boot_pin_tlOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_address = coupler_from_port_named_custom_boot_pin_tlOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_data = coupler_from_port_named_custom_boot_pin_tlOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_valid = coupler_from_port_named_custom_boot_pin_tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_opcode = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_param = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_size = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_sink = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_denied = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_data = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_corrupt = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_a_ready = coupler_from_port_named_custom_boot_pin_tlIn_a_ready; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_tlOut_a_valid = coupler_from_port_named_custom_boot_pin_tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlOut_a_bits_address = coupler_from_port_named_custom_boot_pin_tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlOut_a_bits_data = coupler_from_port_named_custom_boot_pin_tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_valid = coupler_from_port_named_custom_boot_pin_tlIn_d_valid; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_opcode = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_param = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_size = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_sink = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_denied = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_data = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_corrupt = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] assign bus_xingIn_a_ready = bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_auto_in_a_valid = bus_xingOut_a_valid; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_opcode = bus_xingOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_param = bus_xingOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_size = bus_xingOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_source = bus_xingOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_address = bus_xingOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_mask = bus_xingOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_data = bus_xingOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_corrupt = bus_xingOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_ready = bus_xingOut_d_ready; // @[Buffer.scala:40:9] assign bus_xingIn_d_valid = bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_opcode = bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_param = bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_size = bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_source = bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_sink = bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_denied = bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_data = bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_corrupt = bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign auto_bus_xing_in_a_ready_0 = bus_xingIn_a_ready; // @[ClockDomain.scala:14:9] assign bus_xingOut_a_valid = bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_opcode = bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_param = bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_size = bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_source = bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_address = bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_mask = bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_data = bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_corrupt = bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_d_ready = bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_bus_xing_in_d_valid_0 = bus_xingIn_d_valid; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_opcode_0 = bus_xingIn_d_bits_opcode; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_param_0 = bus_xingIn_d_bits_param; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_size_0 = bus_xingIn_d_bits_size; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_source_0 = bus_xingIn_d_bits_source; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_sink_0 = bus_xingIn_d_bits_sink; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_denied_0 = bus_xingIn_d_bits_denied; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_data_0 = bus_xingIn_d_bits_data; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_corrupt_0 = bus_xingIn_d_bits_corrupt; // @[ClockDomain.scala:14:9] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_a_valid = nodeOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_address = nodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_data = nodeOut_a_bits_data; // @[MixedNode.scala:542:17] reg [2:0] state; // @[CustomBootPin.scala:39:28] wire _T_1 = state == 3'h1; // @[CustomBootPin.scala:39:28, :43:24] assign nodeOut_a_valid = (\|state) & (_T_1 \| state != 3'h2 & state == 3'h3); // @[CustomBootPin.scala:39:28, :40:20, :43:24, :46:24] assign nodeOut_a_bits_address = _T_1 ? 29'h1000 : 29'h2000000; // @[CustomBootPin.scala:43:24, :47:23] assign nodeOut_a_bits_data = _T_1 ? 64'h80000000 : 64'h1; // @[CustomBootPin.scala:43:24, :47:23] wire [2:0] _GEN = state == 3'h5 & ~custom_boot ? 3'h0 : state; // @[CustomBootPin.scala:39:28, :43:24, :67:{29,43,51}] wire [7:0][2:0] _GEN_0 = {{_GEN}, {_GEN}, {_GEN}, {nodeOut_d_valid ? 3'h5 : state}, {nodeOut_a_ready & nodeOut_a_valid ? 3'h4 : state}, {nodeOut_d_valid ? 3'h3 : state}, {nodeOut_a_ready & nodeOut_a_valid ? 3'h2 : state}, {custom_boot ? 3'h1 : state}}; // @[Decoupled.scala:51:35] always @(posedge childClock) begin // @[LazyModuleImp.scala:155:31] if (childReset) // @[LazyModuleImp.scala:155:31, :158:31] state <= 3'h0; // @[CustomBootPin.scala:39:28] else // @[LazyModuleImp.scala:155:31] state <= _GEN_0[state]; // @[CustomBootPin.scala:39:28, :43:24, :44:46, :53:30, :55:58, :64:30, :66:50] always @(posedge) FixedClockBroadcast_7 fixedClockNode ( // @[ClockGroup.scala:115:114] .auto_anon_in_clock (clockGroup_auto_out_clock), // @[ClockGroup.scala:24:9] .auto_anon_in_reset (clockGroup_auto_out_reset), // @[ClockGroup.scala:24:9] .auto_anon_out_6_clock (auto_fixedClockNode_anon_out_5_clock_0), .auto_anon_out_6_reset (auto_fixedClockNode_anon_out_5_reset_0), .auto_anon_out_5_clock (auto_fixedClockNode_anon_out_4_clock_0), .auto_anon_out_5_reset (auto_fixedClockNode_anon_out_4_reset_0), .auto_anon_out_4_clock (auto_fixedClockNode_anon_out_3_clock_0), .auto_anon_out_4_reset (auto_fixedClockNode_anon_out_3_reset_0), .auto_anon_out_3_clock (auto_fixedClockNode_anon_out_2_clock_0), .auto_anon_out_3_reset (auto_fixedClockNode_anon_out_2_reset_0), .auto_anon_out_2_clock (auto_fixedClockNode_anon_out_1_clock_0), .auto_anon_out_2_reset (auto_fixedClockNode_anon_out_1_reset_0), .auto_anon_out_1_clock (auto_fixedClockNode_anon_out_0_clock_0), .auto_anon_out_1_reset (auto_fixedClockNode_anon_out_0_reset_0), .auto_anon_out_0_clock (clockSinkNodeIn_clock), .auto_anon_out_0_reset (clockSinkNodeIn_reset) ); // @[ClockGroup.scala:115:114] TLFIFOFixer_2 fixer ( // @[PeripheryBus.scala:54:33] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_a_ready (_fixer_auto_anon_in_a_ready), .auto_anon_in_a_valid (_buffer_auto_out_a_valid), // @[Buffer.scala:75:28] .auto_anon_in_a_bits_opcode (_buffer_auto_out_a_bits_opcode), // @[Buffer.scala:75:28] .auto_anon_in_a_bits_param (_buffer_auto_out_a_bits_param), // @[Buffer.scala:75:28] .auto_anon_in_a_bits_size (_buffer_auto_out_a_bits_size), // @[Buffer.scala:75:28] .auto_anon_in_a_bits_source (_buffer_auto_out_a_bits_source), // @[Buffer.scala:75:28] .auto_anon_in_a_bits_address (_buffer_auto_out_a_bits_address), // @[Buffer.scala:75:28] .auto_anon_in_a_bits_mask (_buffer_auto_out_a_bits_mask), // @[Buffer.scala:75:28] .auto_anon_in_a_bits_data (_buffer_auto_out_a_bits_data), // @[Buffer.scala:75:28] .auto_anon_in_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt), // @[Buffer.scala:75:28] .auto_anon_in_d_ready (_buffer_auto_out_d_ready), // @[Buffer.scala:75:28] .auto_anon_in_d_valid (_fixer_auto_anon_in_d_valid), .auto_anon_in_d_bits_opcode (_fixer_auto_anon_in_d_bits_opcode), .auto_anon_in_d_bits_param (_fixer_auto_anon_in_d_bits_param), .auto_anon_in_d_bits_size (_fixer_auto_anon_in_d_bits_size), .auto_anon_in_d_bits_source (_fixer_auto_anon_in_d_bits_source), .auto_anon_in_d_bits_sink (_fixer_auto_anon_in_d_bits_sink), .auto_anon_in_d_bits_denied (_fixer_auto_anon_in_d_bits_denied), .auto_anon_in_d_bits_data (_fixer_auto_anon_in_d_bits_data), .auto_anon_in_d_bits_corrupt (_fixer_auto_anon_in_d_bits_corrupt), .auto_anon_out_a_ready (_out_xbar_auto_anon_in_a_ready), // @[PeripheryBus.scala:57:30] .auto_anon_out_a_valid (_fixer_auto_anon_out_a_valid), .auto_anon_out_a_bits_opcode (_fixer_auto_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (_fixer_auto_anon_out_a_bits_param), .auto_anon_out_a_bits_size (_fixer_auto_anon_out_a_bits_size), .auto_anon_out_a_bits_source (_fixer_auto_anon_out_a_bits_source), .auto_anon_out_a_bits_address (_fixer_auto_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (_fixer_auto_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (_fixer_auto_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (_fixer_auto_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (_fixer_auto_anon_out_d_ready), .auto_anon_out_d_valid (_out_xbar_auto_anon_in_d_valid), // @[PeripheryBus.scala:57:30] .auto_anon_out_d_bits_opcode (_out_xbar_auto_anon_in_d_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_anon_out_d_bits_param (_out_xbar_auto_anon_in_d_bits_param), // @[PeripheryBus.scala:57:30] .auto_anon_out_d_bits_size (_out_xbar_auto_anon_in_d_bits_size), // @[PeripheryBus.scala:57:30] .auto_anon_out_d_bits_source (_out_xbar_auto_anon_in_d_bits_source), // @[PeripheryBus.scala:57:30] .auto_anon_out_d_bits_sink (_out_xbar_auto_anon_in_d_bits_sink), // @[PeripheryBus.scala:57:30] .auto_anon_out_d_bits_denied (_out_xbar_auto_anon_in_d_bits_denied), // @[PeripheryBus.scala:57:30] .auto_anon_out_d_bits_data (_out_xbar_auto_anon_in_d_bits_data), // @[PeripheryBus.scala:57:30] .auto_anon_out_d_bits_corrupt (_out_xbar_auto_anon_in_d_bits_corrupt) // @[PeripheryBus.scala:57:30] ); // @[PeripheryBus.scala:54:33] TLXbar_cbus_in_i2_o1_a29d64s7k1z4u in_xbar ( // @[PeripheryBus.scala:56:29] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_1_a_ready (coupler_from_port_named_custom_boot_pin_auto_tl_out_a_ready), .auto_anon_in_1_a_valid (coupler_from_port_named_custom_boot_pin_auto_tl_out_a_valid), // @[LazyModuleImp.scala:138:7] .auto_anon_in_1_a_bits_address (coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_address), // @[LazyModuleImp.scala:138:7] .auto_anon_in_1_a_bits_data (coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_data), // @[LazyModuleImp.scala:138:7] .auto_anon_in_1_d_valid (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_valid), .auto_anon_in_1_d_bits_opcode (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_opcode), .auto_anon_in_1_d_bits_param (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_param), .auto_anon_in_1_d_bits_size (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_size), .auto_anon_in_1_d_bits_sink (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_sink), .auto_anon_in_1_d_bits_denied (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_denied), .auto_anon_in_1_d_bits_data (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_data), .auto_anon_in_1_d_bits_corrupt (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_corrupt), .auto_anon_in_0_a_ready (buffer_1_auto_out_a_ready), .auto_anon_in_0_a_valid (buffer_1_auto_out_a_valid), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_opcode (buffer_1_auto_out_a_bits_opcode), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_param (buffer_1_auto_out_a_bits_param), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_size (buffer_1_auto_out_a_bits_size), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_source (buffer_1_auto_out_a_bits_source), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_address (buffer_1_auto_out_a_bits_address), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_mask (buffer_1_auto_out_a_bits_mask), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_data (buffer_1_auto_out_a_bits_data), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_corrupt (buffer_1_auto_out_a_bits_corrupt), // @[Buffer.scala:40:9] .auto_anon_in_0_d_ready (buffer_1_auto_out_d_ready), // @[Buffer.scala:40:9] .auto_anon_in_0_d_valid (buffer_1_auto_out_d_valid), .auto_anon_in_0_d_bits_opcode (buffer_1_auto_out_d_bits_opcode), .auto_anon_in_0_d_bits_param (buffer_1_auto_out_d_bits_param), .auto_anon_in_0_d_bits_size (buffer_1_auto_out_d_bits_size), .auto_anon_in_0_d_bits_source (buffer_1_auto_out_d_bits_source), .auto_anon_in_0_d_bits_sink (buffer_1_auto_out_d_bits_sink), .auto_anon_in_0_d_bits_denied (buffer_1_auto_out_d_bits_denied), .auto_anon_in_0_d_bits_data (buffer_1_auto_out_d_bits_data), .auto_anon_in_0_d_bits_corrupt (buffer_1_auto_out_d_bits_corrupt), .auto_anon_out_a_ready (_atomics_auto_in_a_ready), // @[AtomicAutomata.scala:289:29] .auto_anon_out_a_valid (_in_xbar_auto_anon_out_a_valid), .auto_anon_out_a_bits_opcode (_in_xbar_auto_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (_in_xbar_auto_anon_out_a_bits_param), .auto_anon_out_a_bits_size (_in_xbar_auto_anon_out_a_bits_size), .auto_anon_out_a_bits_source (_in_xbar_auto_anon_out_a_bits_source), .auto_anon_out_a_bits_address (_in_xbar_auto_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (_in_xbar_auto_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (_in_xbar_auto_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (_in_xbar_auto_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (_in_xbar_auto_anon_out_d_ready), .auto_anon_out_d_valid (_atomics_auto_in_d_valid), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_opcode (_atomics_auto_in_d_bits_opcode), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_param (_atomics_auto_in_d_bits_param), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_size (_atomics_auto_in_d_bits_size), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_source (_atomics_auto_in_d_bits_source), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_sink (_atomics_auto_in_d_bits_sink), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_denied (_atomics_auto_in_d_bits_denied), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_data (_atomics_auto_in_d_bits_data), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_corrupt (_atomics_auto_in_d_bits_corrupt) // @[AtomicAutomata.scala:289:29] ); // @[PeripheryBus.scala:56:29] TLXbar_cbus_out_i1_o8_a29d64s7k1z4u out_xbar ( // @[PeripheryBus.scala:57:30] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_a_ready (_out_xbar_auto_anon_in_a_ready), .auto_anon_in_a_valid (_fixer_auto_anon_out_a_valid), // @[PeripheryBus.scala:54:33] .auto_anon_in_a_bits_opcode (_fixer_auto_anon_out_a_bits_opcode), // @[PeripheryBus.scala:54:33] .auto_anon_in_a_bits_param (_fixer_auto_anon_out_a_bits_param), // @[PeripheryBus.scala:54:33] .auto_anon_in_a_bits_size (_fixer_auto_anon_out_a_bits_size), // @[PeripheryBus.scala:54:33] .auto_anon_in_a_bits_source (_fixer_auto_anon_out_a_bits_source), // @[PeripheryBus.scala:54:33] .auto_anon_in_a_bits_address (_fixer_auto_anon_out_a_bits_address), // @[PeripheryBus.scala:54:33] .auto_anon_in_a_bits_mask (_fixer_auto_anon_out_a_bits_mask), // @[PeripheryBus.scala:54:33] .auto_anon_in_a_bits_data (_fixer_auto_anon_out_a_bits_data), // @[PeripheryBus.scala:54:33] .auto_anon_in_a_bits_corrupt (_fixer_auto_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:54:33] .auto_anon_in_d_ready (_fixer_auto_anon_out_d_ready), // @[PeripheryBus.scala:54:33] .auto_anon_in_d_valid (_out_xbar_auto_anon_in_d_valid), .auto_anon_in_d_bits_opcode (_out_xbar_auto_anon_in_d_bits_opcode), .auto_anon_in_d_bits_param (_out_xbar_auto_anon_in_d_bits_param), .auto_anon_in_d_bits_size (_out_xbar_auto_anon_in_d_bits_size), .auto_anon_in_d_bits_source (_out_xbar_auto_anon_in_d_bits_source), .auto_anon_in_d_bits_sink (_out_xbar_auto_anon_in_d_bits_sink), .auto_anon_in_d_bits_denied (_out_xbar_auto_anon_in_d_bits_denied), .auto_anon_in_d_bits_data (_out_xbar_auto_anon_in_d_bits_data), .auto_anon_in_d_bits_corrupt (_out_xbar_auto_anon_in_d_bits_corrupt), .auto_anon_out_7_a_ready (_coupler_to_prci_ctrl_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_7_a_valid (_out_xbar_auto_anon_out_7_a_valid), .auto_anon_out_7_a_bits_opcode (_out_xbar_auto_anon_out_7_a_bits_opcode), .auto_anon_out_7_a_bits_param (_out_xbar_auto_anon_out_7_a_bits_param), .auto_anon_out_7_a_bits_size (_out_xbar_auto_anon_out_7_a_bits_size), .auto_anon_out_7_a_bits_source (_out_xbar_auto_anon_out_7_a_bits_source), .auto_anon_out_7_a_bits_address (_out_xbar_auto_anon_out_7_a_bits_address), .auto_anon_out_7_a_bits_mask (_out_xbar_auto_anon_out_7_a_bits_mask), .auto_anon_out_7_a_bits_data (_out_xbar_auto_anon_out_7_a_bits_data), .auto_anon_out_7_a_bits_corrupt (_out_xbar_auto_anon_out_7_a_bits_corrupt), .auto_anon_out_7_d_ready (_out_xbar_auto_anon_out_7_d_ready), .auto_anon_out_7_d_valid (_coupler_to_prci_ctrl_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_opcode (_coupler_to_prci_ctrl_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_param (_coupler_to_prci_ctrl_auto_tl_in_d_bits_param), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_size (_coupler_to_prci_ctrl_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_source (_coupler_to_prci_ctrl_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_sink (_coupler_to_prci_ctrl_auto_tl_in_d_bits_sink), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_denied (_coupler_to_prci_ctrl_auto_tl_in_d_bits_denied), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_data (_coupler_to_prci_ctrl_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_corrupt (_coupler_to_prci_ctrl_auto_tl_in_d_bits_corrupt), // @[LazyScope.scala:98:27] .auto_anon_out_6_a_ready (_coupler_to_bootrom_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_6_a_valid (_out_xbar_auto_anon_out_6_a_valid), .auto_anon_out_6_a_bits_opcode (_out_xbar_auto_anon_out_6_a_bits_opcode), .auto_anon_out_6_a_bits_param (_out_xbar_auto_anon_out_6_a_bits_param), .auto_anon_out_6_a_bits_size (_out_xbar_auto_anon_out_6_a_bits_size), .auto_anon_out_6_a_bits_source (_out_xbar_auto_anon_out_6_a_bits_source), .auto_anon_out_6_a_bits_address (_out_xbar_auto_anon_out_6_a_bits_address), .auto_anon_out_6_a_bits_mask (_out_xbar_auto_anon_out_6_a_bits_mask), .auto_anon_out_6_a_bits_data (_out_xbar_auto_anon_out_6_a_bits_data), .auto_anon_out_6_a_bits_corrupt (_out_xbar_auto_anon_out_6_a_bits_corrupt), .auto_anon_out_6_d_ready (_out_xbar_auto_anon_out_6_d_ready), .auto_anon_out_6_d_valid (_coupler_to_bootrom_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_6_d_bits_size (_coupler_to_bootrom_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_6_d_bits_source (_coupler_to_bootrom_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_6_d_bits_data (_coupler_to_bootrom_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_5_a_ready (_coupler_to_debug_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_5_a_valid (_out_xbar_auto_anon_out_5_a_valid), .auto_anon_out_5_a_bits_opcode (_out_xbar_auto_anon_out_5_a_bits_opcode), .auto_anon_out_5_a_bits_param (_out_xbar_auto_anon_out_5_a_bits_param), .auto_anon_out_5_a_bits_size (_out_xbar_auto_anon_out_5_a_bits_size), .auto_anon_out_5_a_bits_source (_out_xbar_auto_anon_out_5_a_bits_source), .auto_anon_out_5_a_bits_address (_out_xbar_auto_anon_out_5_a_bits_address), .auto_anon_out_5_a_bits_mask (_out_xbar_auto_anon_out_5_a_bits_mask), .auto_anon_out_5_a_bits_data (_out_xbar_auto_anon_out_5_a_bits_data), .auto_anon_out_5_a_bits_corrupt (_out_xbar_auto_anon_out_5_a_bits_corrupt), .auto_anon_out_5_d_ready (_out_xbar_auto_anon_out_5_d_ready), .auto_anon_out_5_d_valid (_coupler_to_debug_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_5_d_bits_opcode (_coupler_to_debug_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_5_d_bits_size (_coupler_to_debug_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_5_d_bits_source (_coupler_to_debug_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_5_d_bits_data (_coupler_to_debug_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_4_a_ready (_coupler_to_plic_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_4_a_valid (_out_xbar_auto_anon_out_4_a_valid), .auto_anon_out_4_a_bits_opcode (_out_xbar_auto_anon_out_4_a_bits_opcode), .auto_anon_out_4_a_bits_param (_out_xbar_auto_anon_out_4_a_bits_param), .auto_anon_out_4_a_bits_size (_out_xbar_auto_anon_out_4_a_bits_size), .auto_anon_out_4_a_bits_source (_out_xbar_auto_anon_out_4_a_bits_source), .auto_anon_out_4_a_bits_address (_out_xbar_auto_anon_out_4_a_bits_address), .auto_anon_out_4_a_bits_mask (_out_xbar_auto_anon_out_4_a_bits_mask), .auto_anon_out_4_a_bits_data (_out_xbar_auto_anon_out_4_a_bits_data), .auto_anon_out_4_a_bits_corrupt (_out_xbar_auto_anon_out_4_a_bits_corrupt), .auto_anon_out_4_d_ready (_out_xbar_auto_anon_out_4_d_ready), .auto_anon_out_4_d_valid (_coupler_to_plic_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_4_d_bits_opcode (_coupler_to_plic_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_4_d_bits_size (_coupler_to_plic_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_4_d_bits_source (_coupler_to_plic_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_4_d_bits_data (_coupler_to_plic_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_3_a_ready (_coupler_to_clint_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_3_a_valid (_out_xbar_auto_anon_out_3_a_valid), .auto_anon_out_3_a_bits_opcode (_out_xbar_auto_anon_out_3_a_bits_opcode), .auto_anon_out_3_a_bits_param (_out_xbar_auto_anon_out_3_a_bits_param), .auto_anon_out_3_a_bits_size (_out_xbar_auto_anon_out_3_a_bits_size), .auto_anon_out_3_a_bits_source (_out_xbar_auto_anon_out_3_a_bits_source), .auto_anon_out_3_a_bits_address (_out_xbar_auto_anon_out_3_a_bits_address), .auto_anon_out_3_a_bits_mask (_out_xbar_auto_anon_out_3_a_bits_mask), .auto_anon_out_3_a_bits_data (_out_xbar_auto_anon_out_3_a_bits_data), .auto_anon_out_3_a_bits_corrupt (_out_xbar_auto_anon_out_3_a_bits_corrupt), .auto_anon_out_3_d_ready (_out_xbar_auto_anon_out_3_d_ready), .auto_anon_out_3_d_valid (_coupler_to_clint_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_3_d_bits_opcode (_coupler_to_clint_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_3_d_bits_size (_coupler_to_clint_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_3_d_bits_source (_coupler_to_clint_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_3_d_bits_data (_coupler_to_clint_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_2_a_ready (coupler_to_bus_named_pbus_auto_widget_anon_in_a_ready), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_a_valid (coupler_to_bus_named_pbus_auto_widget_anon_in_a_valid), .auto_anon_out_2_a_bits_opcode (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_opcode), .auto_anon_out_2_a_bits_param (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_param), .auto_anon_out_2_a_bits_size (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_size), .auto_anon_out_2_a_bits_source (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_source), .auto_anon_out_2_a_bits_address (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_address), .auto_anon_out_2_a_bits_mask (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_mask), .auto_anon_out_2_a_bits_data (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_data), .auto_anon_out_2_a_bits_corrupt (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_corrupt), .auto_anon_out_2_d_ready (coupler_to_bus_named_pbus_auto_widget_anon_in_d_ready), .auto_anon_out_2_d_valid (coupler_to_bus_named_pbus_auto_widget_anon_in_d_valid), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_opcode (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_opcode), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_param (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_param), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_size (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_size), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_source (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_source), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_sink (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_sink), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_denied (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_denied), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_data (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_data), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_corrupt (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_corrupt), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_a_ready (_coupler_to_l2_ctrl_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_1_a_valid (_out_xbar_auto_anon_out_1_a_valid), .auto_anon_out_1_a_bits_opcode (_out_xbar_auto_anon_out_1_a_bits_opcode), .auto_anon_out_1_a_bits_param (_out_xbar_auto_anon_out_1_a_bits_param), .auto_anon_out_1_a_bits_size (_out_xbar_auto_anon_out_1_a_bits_size), .auto_anon_out_1_a_bits_source (_out_xbar_auto_anon_out_1_a_bits_source), .auto_anon_out_1_a_bits_address (_out_xbar_auto_anon_out_1_a_bits_address), .auto_anon_out_1_a_bits_mask (_out_xbar_auto_anon_out_1_a_bits_mask), .auto_anon_out_1_a_bits_data (_out_xbar_auto_anon_out_1_a_bits_data), .auto_anon_out_1_a_bits_corrupt (_out_xbar_auto_anon_out_1_a_bits_corrupt), .auto_anon_out_1_d_ready (_out_xbar_auto_anon_out_1_d_ready), .auto_anon_out_1_d_valid (_coupler_to_l2_ctrl_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_opcode (_coupler_to_l2_ctrl_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_param (_coupler_to_l2_ctrl_auto_tl_in_d_bits_param), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_size (_coupler_to_l2_ctrl_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_source (_coupler_to_l2_ctrl_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_sink (_coupler_to_l2_ctrl_auto_tl_in_d_bits_sink), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_denied (_coupler_to_l2_ctrl_auto_tl_in_d_bits_denied), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_data (_coupler_to_l2_ctrl_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_corrupt (_coupler_to_l2_ctrl_auto_tl_in_d_bits_corrupt), // @[LazyScope.scala:98:27] .auto_anon_out_0_a_ready (_wrapped_error_device_auto_buffer_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_0_a_valid (_out_xbar_auto_anon_out_0_a_valid), .auto_anon_out_0_a_bits_opcode (_out_xbar_auto_anon_out_0_a_bits_opcode), .auto_anon_out_0_a_bits_param (_out_xbar_auto_anon_out_0_a_bits_param), .auto_anon_out_0_a_bits_size (_out_xbar_auto_anon_out_0_a_bits_size), .auto_anon_out_0_a_bits_source (_out_xbar_auto_anon_out_0_a_bits_source), .auto_anon_out_0_a_bits_address (_out_xbar_auto_anon_out_0_a_bits_address), .auto_anon_out_0_a_bits_mask (_out_xbar_auto_anon_out_0_a_bits_mask), .auto_anon_out_0_a_bits_data (_out_xbar_auto_anon_out_0_a_bits_data), .auto_anon_out_0_a_bits_corrupt (_out_xbar_auto_anon_out_0_a_bits_corrupt), .auto_anon_out_0_d_ready (_out_xbar_auto_anon_out_0_d_ready), .auto_anon_out_0_d_valid (_wrapped_error_device_auto_buffer_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_opcode (_wrapped_error_device_auto_buffer_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_param (_wrapped_error_device_auto_buffer_in_d_bits_param), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_size (_wrapped_error_device_auto_buffer_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_source (_wrapped_error_device_auto_buffer_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_sink (_wrapped_error_device_auto_buffer_in_d_bits_sink), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_denied (_wrapped_error_device_auto_buffer_in_d_bits_denied), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_data (_wrapped_error_device_auto_buffer_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_corrupt (_wrapped_error_device_auto_buffer_in_d_bits_corrupt) // @[LazyScope.scala:98:27] ); // @[PeripheryBus.scala:57:30] TLBuffer_a29d64s7k1z4u buffer ( // @[Buffer.scala:75:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (_buffer_auto_in_a_ready), .auto_in_a_valid (_atomics_auto_out_a_valid), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_opcode (_atomics_auto_out_a_bits_opcode), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_param (_atomics_auto_out_a_bits_param), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_size (_atomics_auto_out_a_bits_size), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_source (_atomics_auto_out_a_bits_source), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_address (_atomics_auto_out_a_bits_address), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_mask (_atomics_auto_out_a_bits_mask), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_data (_atomics_auto_out_a_bits_data), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_corrupt (_atomics_auto_out_a_bits_corrupt), // @[AtomicAutomata.scala:289:29] .auto_in_d_ready (_atomics_auto_out_d_ready), // @[AtomicAutomata.scala:289:29] .auto_in_d_valid (_buffer_auto_in_d_valid), .auto_in_d_bits_opcode (_buffer_auto_in_d_bits_opcode), .auto_in_d_bits_param (_buffer_auto_in_d_bits_param), .auto_in_d_bits_size (_buffer_auto_in_d_bits_size), .auto_in_d_bits_source (_buffer_auto_in_d_bits_source), .auto_in_d_bits_sink (_buffer_auto_in_d_bits_sink), .auto_in_d_bits_denied (_buffer_auto_in_d_bits_denied), .auto_in_d_bits_data (_buffer_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt), .auto_out_a_ready (_fixer_auto_anon_in_a_ready), // @[PeripheryBus.scala:54:33] .auto_out_a_valid (_buffer_auto_out_a_valid), .auto_out_a_bits_opcode (_buffer_auto_out_a_bits_opcode), .auto_out_a_bits_param (_buffer_auto_out_a_bits_param), .auto_out_a_bits_size (_buffer_auto_out_a_bits_size), .auto_out_a_bits_source (_buffer_auto_out_a_bits_source), .auto_out_a_bits_address (_buffer_auto_out_a_bits_address), .auto_out_a_bits_mask (_buffer_auto_out_a_bits_mask), .auto_out_a_bits_data (_buffer_auto_out_a_bits_data), .auto_out_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt), .auto_out_d_ready (_buffer_auto_out_d_ready), .auto_out_d_valid (_fixer_auto_anon_in_d_valid), // @[PeripheryBus.scala:54:33] .auto_out_d_bits_opcode (_fixer_auto_anon_in_d_bits_opcode), // @[PeripheryBus.scala:54:33] .auto_out_d_bits_param (_fixer_auto_anon_in_d_bits_param), // @[PeripheryBus.scala:54:33] .auto_out_d_bits_size (_fixer_auto_anon_in_d_bits_size), // @[PeripheryBus.scala:54:33] .auto_out_d_bits_source (_fixer_auto_anon_in_d_bits_source), // @[PeripheryBus.scala:54:33] .auto_out_d_bits_sink (_fixer_auto_anon_in_d_bits_sink), // @[PeripheryBus.scala:54:33] .auto_out_d_bits_denied (_fixer_auto_anon_in_d_bits_denied), // @[PeripheryBus.scala:54:33] .auto_out_d_bits_data (_fixer_auto_anon_in_d_bits_data), // @[PeripheryBus.scala:54:33] .auto_out_d_bits_corrupt (_fixer_auto_anon_in_d_bits_corrupt) // @[PeripheryBus.scala:54:33] ); // @[Buffer.scala:75:28] TLAtomicAutomata_cbus atomics ( // @[AtomicAutomata.scala:289:29] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (_atomics_auto_in_a_ready), .auto_in_a_valid (_in_xbar_auto_anon_out_a_valid), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_opcode (_in_xbar_auto_anon_out_a_bits_opcode), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_param (_in_xbar_auto_anon_out_a_bits_param), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_size (_in_xbar_auto_anon_out_a_bits_size), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_source (_in_xbar_auto_anon_out_a_bits_source), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_address (_in_xbar_auto_anon_out_a_bits_address), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_mask (_in_xbar_auto_anon_out_a_bits_mask), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_data (_in_xbar_auto_anon_out_a_bits_data), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_corrupt (_in_xbar_auto_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:56:29] .auto_in_d_ready (_in_xbar_auto_anon_out_d_ready), // @[PeripheryBus.scala:56:29] .auto_in_d_valid (_atomics_auto_in_d_valid), .auto_in_d_bits_opcode (_atomics_auto_in_d_bits_opcode), .auto_in_d_bits_param (_atomics_auto_in_d_bits_param), .auto_in_d_bits_size (_atomics_auto_in_d_bits_size), .auto_in_d_bits_source (_atomics_auto_in_d_bits_source), .auto_in_d_bits_sink (_atomics_auto_in_d_bits_sink), .auto_in_d_bits_denied (_atomics_auto_in_d_bits_denied), .auto_in_d_bits_data (_atomics_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_atomics_auto_in_d_bits_corrupt), .auto_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28] .auto_out_a_valid (_atomics_auto_out_a_valid), .auto_out_a_bits_opcode (_atomics_auto_out_a_bits_opcode), .auto_out_a_bits_param (_atomics_auto_out_a_bits_param), .auto_out_a_bits_size (_atomics_auto_out_a_bits_size), .auto_out_a_bits_source (_atomics_auto_out_a_bits_source), .auto_out_a_bits_address (_atomics_auto_out_a_bits_address), .auto_out_a_bits_mask (_atomics_auto_out_a_bits_mask), .auto_out_a_bits_data (_atomics_auto_out_a_bits_data), .auto_out_a_bits_corrupt (_atomics_auto_out_a_bits_corrupt), .auto_out_d_ready (_atomics_auto_out_d_ready), .auto_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28] .auto_out_d_bits_opcode (_buffer_auto_in_d_bits_opcode), // @[Buffer.scala:75:28] .auto_out_d_bits_param (_buffer_auto_in_d_bits_param), // @[Buffer.scala:75:28] .auto_out_d_bits_size (_buffer_auto_in_d_bits_size), // @[Buffer.scala:75:28] .auto_out_d_bits_source (_buffer_auto_in_d_bits_source), // @[Buffer.scala:75:28] .auto_out_d_bits_sink (_buffer_auto_in_d_bits_sink), // @[Buffer.scala:75:28] .auto_out_d_bits_denied (_buffer_auto_in_d_bits_denied), // @[Buffer.scala:75:28] .auto_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28] .auto_out_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt) // @[Buffer.scala:75:28] ); // @[AtomicAutomata.scala:289:29] ErrorDeviceWrapper wrapped_error_device ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_buffer_in_a_ready (_wrapped_error_device_auto_buffer_in_a_ready), .auto_buffer_in_a_valid (_out_xbar_auto_anon_out_0_a_valid), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_opcode (_out_xbar_auto_anon_out_0_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_param (_out_xbar_auto_anon_out_0_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_size (_out_xbar_auto_anon_out_0_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_source (_out_xbar_auto_anon_out_0_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_address (_out_xbar_auto_anon_out_0_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_mask (_out_xbar_auto_anon_out_0_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_data (_out_xbar_auto_anon_out_0_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_corrupt (_out_xbar_auto_anon_out_0_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_buffer_in_d_ready (_out_xbar_auto_anon_out_0_d_ready), // @[PeripheryBus.scala:57:30] .auto_buffer_in_d_valid (_wrapped_error_device_auto_buffer_in_d_valid), .auto_buffer_in_d_bits_opcode (_wrapped_error_device_auto_buffer_in_d_bits_opcode), .auto_buffer_in_d_bits_param (_wrapped_error_device_auto_buffer_in_d_bits_param), .auto_buffer_in_d_bits_size (_wrapped_error_device_auto_buffer_in_d_bits_size), .auto_buffer_in_d_bits_source (_wrapped_error_device_auto_buffer_in_d_bits_source), .auto_buffer_in_d_bits_sink (_wrapped_error_device_auto_buffer_in_d_bits_sink), .auto_buffer_in_d_bits_denied (_wrapped_error_device_auto_buffer_in_d_bits_denied), .auto_buffer_in_d_bits_data (_wrapped_error_device_auto_buffer_in_d_bits_data), .auto_buffer_in_d_bits_corrupt (_wrapped_error_device_auto_buffer_in_d_bits_corrupt) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_cbus_to_l2_ctrl coupler_to_l2_ctrl ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_buffer_out_a_ready (auto_coupler_to_l2_ctrl_buffer_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_a_valid (auto_coupler_to_l2_ctrl_buffer_out_a_valid_0), .auto_buffer_out_a_bits_opcode (auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode_0), .auto_buffer_out_a_bits_param (auto_coupler_to_l2_ctrl_buffer_out_a_bits_param_0), .auto_buffer_out_a_bits_size (auto_coupler_to_l2_ctrl_buffer_out_a_bits_size_0), .auto_buffer_out_a_bits_source (auto_coupler_to_l2_ctrl_buffer_out_a_bits_source_0), .auto_buffer_out_a_bits_address (auto_coupler_to_l2_ctrl_buffer_out_a_bits_address_0), .auto_buffer_out_a_bits_mask (auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask_0), .auto_buffer_out_a_bits_data (auto_coupler_to_l2_ctrl_buffer_out_a_bits_data_0), .auto_buffer_out_a_bits_corrupt (auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt_0), .auto_buffer_out_d_ready (auto_coupler_to_l2_ctrl_buffer_out_d_ready_0), .auto_buffer_out_d_valid (auto_coupler_to_l2_ctrl_buffer_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_opcode (auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_size (auto_coupler_to_l2_ctrl_buffer_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_source (auto_coupler_to_l2_ctrl_buffer_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_data (auto_coupler_to_l2_ctrl_buffer_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_l2_ctrl_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_1_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_1_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_1_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_1_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_1_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_1_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_1_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_1_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_1_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_1_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_l2_ctrl_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_l2_ctrl_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_param (_coupler_to_l2_ctrl_auto_tl_in_d_bits_param), .auto_tl_in_d_bits_size (_coupler_to_l2_ctrl_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_l2_ctrl_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_sink (_coupler_to_l2_ctrl_auto_tl_in_d_bits_sink), .auto_tl_in_d_bits_denied (_coupler_to_l2_ctrl_auto_tl_in_d_bits_denied), .auto_tl_in_d_bits_data (_coupler_to_l2_ctrl_auto_tl_in_d_bits_data), .auto_tl_in_d_bits_corrupt (_coupler_to_l2_ctrl_auto_tl_in_d_bits_corrupt) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_cbus_to_clint coupler_to_clint ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_fragmenter_anon_out_a_ready (auto_coupler_to_clint_fragmenter_anon_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_a_valid (auto_coupler_to_clint_fragmenter_anon_out_a_valid_0), .auto_fragmenter_anon_out_a_bits_opcode (auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode_0), .auto_fragmenter_anon_out_a_bits_param (auto_coupler_to_clint_fragmenter_anon_out_a_bits_param_0), .auto_fragmenter_anon_out_a_bits_size (auto_coupler_to_clint_fragmenter_anon_out_a_bits_size_0), .auto_fragmenter_anon_out_a_bits_source (auto_coupler_to_clint_fragmenter_anon_out_a_bits_source_0), .auto_fragmenter_anon_out_a_bits_address (auto_coupler_to_clint_fragmenter_anon_out_a_bits_address_0), .auto_fragmenter_anon_out_a_bits_mask (auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask_0), .auto_fragmenter_anon_out_a_bits_data (auto_coupler_to_clint_fragmenter_anon_out_a_bits_data_0), .auto_fragmenter_anon_out_a_bits_corrupt (auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt_0), .auto_fragmenter_anon_out_d_ready (auto_coupler_to_clint_fragmenter_anon_out_d_ready_0), .auto_fragmenter_anon_out_d_valid (auto_coupler_to_clint_fragmenter_anon_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_opcode (auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_size (auto_coupler_to_clint_fragmenter_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_source (auto_coupler_to_clint_fragmenter_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_data (auto_coupler_to_clint_fragmenter_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_clint_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_3_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_3_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_3_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_3_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_3_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_3_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_3_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_3_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_3_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_3_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_clint_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_clint_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_clint_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_clint_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_data (_coupler_to_clint_auto_tl_in_d_bits_data) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_cbus_to_plic coupler_to_plic ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_fragmenter_anon_out_a_ready (auto_coupler_to_plic_fragmenter_anon_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_a_valid (auto_coupler_to_plic_fragmenter_anon_out_a_valid_0), .auto_fragmenter_anon_out_a_bits_opcode (auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode_0), .auto_fragmenter_anon_out_a_bits_param (auto_coupler_to_plic_fragmenter_anon_out_a_bits_param_0), .auto_fragmenter_anon_out_a_bits_size (auto_coupler_to_plic_fragmenter_anon_out_a_bits_size_0), .auto_fragmenter_anon_out_a_bits_source (auto_coupler_to_plic_fragmenter_anon_out_a_bits_source_0), .auto_fragmenter_anon_out_a_bits_address (auto_coupler_to_plic_fragmenter_anon_out_a_bits_address_0), .auto_fragmenter_anon_out_a_bits_mask (auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask_0), .auto_fragmenter_anon_out_a_bits_data (auto_coupler_to_plic_fragmenter_anon_out_a_bits_data_0), .auto_fragmenter_anon_out_a_bits_corrupt (auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt_0), .auto_fragmenter_anon_out_d_ready (auto_coupler_to_plic_fragmenter_anon_out_d_ready_0), .auto_fragmenter_anon_out_d_valid (auto_coupler_to_plic_fragmenter_anon_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_opcode (auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_size (auto_coupler_to_plic_fragmenter_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_source (auto_coupler_to_plic_fragmenter_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_data (auto_coupler_to_plic_fragmenter_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_plic_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_4_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_4_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_4_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_4_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_4_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_4_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_4_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_4_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_4_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_4_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_plic_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_plic_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_plic_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_plic_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_data (_coupler_to_plic_auto_tl_in_d_bits_data) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_cbus_to_debug coupler_to_debug ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_fragmenter_anon_out_a_ready (auto_coupler_to_debug_fragmenter_anon_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_a_valid (auto_coupler_to_debug_fragmenter_anon_out_a_valid_0), .auto_fragmenter_anon_out_a_bits_opcode (auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode_0), .auto_fragmenter_anon_out_a_bits_param (auto_coupler_to_debug_fragmenter_anon_out_a_bits_param_0), .auto_fragmenter_anon_out_a_bits_size (auto_coupler_to_debug_fragmenter_anon_out_a_bits_size_0), .auto_fragmenter_anon_out_a_bits_source (auto_coupler_to_debug_fragmenter_anon_out_a_bits_source_0), .auto_fragmenter_anon_out_a_bits_address (auto_coupler_to_debug_fragmenter_anon_out_a_bits_address_0), .auto_fragmenter_anon_out_a_bits_mask (auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask_0), .auto_fragmenter_anon_out_a_bits_data (auto_coupler_to_debug_fragmenter_anon_out_a_bits_data_0), .auto_fragmenter_anon_out_a_bits_corrupt (auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt_0), .auto_fragmenter_anon_out_d_ready (auto_coupler_to_debug_fragmenter_anon_out_d_ready_0), .auto_fragmenter_anon_out_d_valid (auto_coupler_to_debug_fragmenter_anon_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_opcode (auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_size (auto_coupler_to_debug_fragmenter_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_source (auto_coupler_to_debug_fragmenter_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_data (auto_coupler_to_debug_fragmenter_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_debug_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_5_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_5_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_5_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_5_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_5_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_5_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_5_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_5_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_5_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_5_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_debug_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_debug_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_debug_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_debug_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_data (_coupler_to_debug_auto_tl_in_d_bits_data) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_cbus_to_bootrom coupler_to_bootrom ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_fragmenter_anon_out_a_ready (auto_coupler_to_bootrom_fragmenter_anon_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_a_valid (auto_coupler_to_bootrom_fragmenter_anon_out_a_valid_0), .auto_fragmenter_anon_out_a_bits_opcode (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode_0), .auto_fragmenter_anon_out_a_bits_param (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param_0), .auto_fragmenter_anon_out_a_bits_size (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size_0), .auto_fragmenter_anon_out_a_bits_source (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source_0), .auto_fragmenter_anon_out_a_bits_address (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address_0), .auto_fragmenter_anon_out_a_bits_mask (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask_0), .auto_fragmenter_anon_out_a_bits_data (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data_0), .auto_fragmenter_anon_out_a_bits_corrupt (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt_0), .auto_fragmenter_anon_out_d_ready (auto_coupler_to_bootrom_fragmenter_anon_out_d_ready_0), .auto_fragmenter_anon_out_d_valid (auto_coupler_to_bootrom_fragmenter_anon_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_size (auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_source (auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_data (auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_bootrom_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_6_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_6_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_6_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_6_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_6_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_6_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_6_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_6_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_6_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_6_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_bootrom_auto_tl_in_d_valid), .auto_tl_in_d_bits_size (_coupler_to_bootrom_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_bootrom_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_data (_coupler_to_bootrom_auto_tl_in_d_bits_data) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_cbus_to_prci_ctrl coupler_to_prci_ctrl ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_fixer_anon_out_a_ready (auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_fixer_anon_out_a_valid (auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid_0), .auto_fixer_anon_out_a_bits_opcode (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode_0), .auto_fixer_anon_out_a_bits_param (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param_0), .auto_fixer_anon_out_a_bits_size (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size_0), .auto_fixer_anon_out_a_bits_source (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source_0), .auto_fixer_anon_out_a_bits_address (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address_0), .auto_fixer_anon_out_a_bits_mask (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask_0), .auto_fixer_anon_out_a_bits_data (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data_0), .auto_fixer_anon_out_a_bits_corrupt (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt_0), .auto_fixer_anon_out_d_ready (auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready_0), .auto_fixer_anon_out_d_valid (auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_fixer_anon_out_d_bits_opcode (auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_fixer_anon_out_d_bits_size (auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_fixer_anon_out_d_bits_source (auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_fixer_anon_out_d_bits_data (auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_prci_ctrl_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_7_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_7_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_7_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_7_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_7_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_7_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_7_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_7_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_7_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_7_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_prci_ctrl_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_prci_ctrl_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_param (_coupler_to_prci_ctrl_auto_tl_in_d_bits_param), .auto_tl_in_d_bits_size (_coupler_to_prci_ctrl_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_prci_ctrl_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_sink (_coupler_to_prci_ctrl_auto_tl_in_d_bits_sink), .auto_tl_in_d_bits_denied (_coupler_to_prci_ctrl_auto_tl_in_d_bits_denied), .auto_tl_in_d_bits_data (_coupler_to_prci_ctrl_auto_tl_in_d_bits_data), .auto_tl_in_d_bits_corrupt (_coupler_to_prci_ctrl_auto_tl_in_d_bits_corrupt) ); // @[LazyScope.scala:98:27] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid = auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready = auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_valid = auto_coupler_to_bootrom_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_d_ready = auto_coupler_to_bootrom_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_valid = auto_coupler_to_debug_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode = auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_param = auto_coupler_to_debug_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_size = auto_coupler_to_debug_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_source = auto_coupler_to_debug_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_address = auto_coupler_to_debug_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask = auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_data = auto_coupler_to_debug_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt = auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_d_ready = auto_coupler_to_debug_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_valid = auto_coupler_to_plic_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode = auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_param = auto_coupler_to_plic_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_size = auto_coupler_to_plic_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_source = auto_coupler_to_plic_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_address = auto_coupler_to_plic_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask = auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_data = auto_coupler_to_plic_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt = auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_d_ready = auto_coupler_to_plic_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_valid = auto_coupler_to_clint_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode = auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_param = auto_coupler_to_clint_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_size = auto_coupler_to_clint_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_source = auto_coupler_to_clint_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_address = auto_coupler_to_clint_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask = auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_data = auto_coupler_to_clint_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt = auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_d_ready = auto_coupler_to_clint_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid = auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready = auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_valid = auto_coupler_to_l2_ctrl_buffer_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode = auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_param = auto_coupler_to_l2_ctrl_buffer_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_size = auto_coupler_to_l2_ctrl_buffer_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_source = auto_coupler_to_l2_ctrl_buffer_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_address = auto_coupler_to_l2_ctrl_buffer_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask = auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_data = auto_coupler_to_l2_ctrl_buffer_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt = auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_d_ready = auto_coupler_to_l2_ctrl_buffer_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_5_clock = auto_fixedClockNode_anon_out_5_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_5_reset = auto_fixedClockNode_anon_out_5_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_4_clock = auto_fixedClockNode_anon_out_4_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_4_reset = auto_fixedClockNode_anon_out_4_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_3_clock = auto_fixedClockNode_anon_out_3_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_3_reset = auto_fixedClockNode_anon_out_3_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_2_clock = auto_fixedClockNode_anon_out_2_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_2_reset = auto_fixedClockNode_anon_out_2_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_1_clock = auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_1_reset = auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_0_clock = auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_0_reset = auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_a_ready = auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_valid = auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_opcode = auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_param = auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_size = auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_source = auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_sink = auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_denied = auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_data = auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_corrupt = auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File EgressUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} class EgressUnit(coupleSAVA: Boolean, combineSAST: Boolean, inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: EgressChannelParams) (implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) { class EgressUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) { val out = Decoupled(new EgressFlit(cParam.payloadBits)) } val io = IO(new EgressUnitIO) val channel_empty = RegInit(true.B) val flow = Reg(new FlowRoutingBundle) val q = Module(new Queue(new EgressFlit(cParam.payloadBits), 3 - (if (combineSAST) 1 else 0), flow=true)) q.io.enq.valid := io.in(0).valid q.io.enq.bits.head := io.in(0).bits.head q.io.enq.bits.tail := io.in(0).bits.tail val flows = cParam.possibleFlows.toSeq if (flows.size == 0) { q.io.enq.bits.ingress_id := 0.U(1.W) } else { q.io.enq.bits.ingress_id := Mux1H( flows.map(f => (f.ingressNode.U === io.in(0).bits.flow.ingress_node && f.ingressNodeId.U === io.in(0).bits.flow.ingress_node_id)), flows.map(f => f.ingressId.U(ingressIdBits.W)) ) } q.io.enq.bits.payload := io.in(0).bits.payload io.out <> q.io.deq assert(!(q.io.enq.valid && !q.io.enq.ready)) io.credit_available(0) := q.io.count === 0.U io.channel_status(0).occupied := !channel_empty io.channel_status(0).flow := flow when (io.credit_alloc(0).alloc && io.credit_alloc(0).tail) { channel_empty := true.B if (coupleSAVA) io.channel_status(0).occupied := false.B } when (io.allocs(0).alloc) { channel_empty := false.B flow := io.allocs(0).flow } }	module EgressUnit_14( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [144:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14] input [2:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] input io_out_ready, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [144:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30] wire _q_io_enq_bits_ingress_id_T_37 = io_in_0_bits_flow_ingress_node_id == 3'h0; // @[EgressUnit.scala:32:27]
Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 \|\| cParam.destSpeedup > 1 \|\| fullSize <= 1) \|\| !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_\|\|_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) \| (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_\|\|_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow \|\| routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }	module mem_20x75( // @[InputUnit.scala:85:18] input [4:0] R0_addr, input R0_en, input R0_clk, output [74:0] R0_data, input [4:0] R1_addr, input R1_en, input R1_clk, output [74:0] R1_data, input [4:0] R2_addr, input R2_en, input R2_clk, output [74:0] R2_data, input [4:0] R3_addr, input R3_en, input R3_clk, output [74:0] R3_data, input [4:0] R4_addr, input R4_en, input R4_clk, output [74:0] R4_data, input [4:0] R5_addr, input R5_en, input R5_clk, output [74:0] R5_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [74:0] W0_data ); reg [74:0] Memory[0:19]; // @[InputUnit.scala:85:18] always @(posedge W0_clk) begin // @[InputUnit.scala:85:18] if (W0_en & 1'h1) // @[InputUnit.scala:85:18] Memory[W0_addr] <= W0_data; // @[InputUnit.scala:85:18] always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File AtomicAutomata.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.util.leftOR import scala.math.{min,max} // Ensures that all downstream RW managers support Atomic operations. // If !passthrough, intercept all Atomics. Otherwise, only intercept those unsupported downstream. class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(implicit p: Parameters) extends LazyModule { require (concurrency >= 1) val node = TLAdapterNode( managerFn = { case mp => mp.v1copy(managers = mp.managers.map { m => val ourSupport = TransferSizes(1, mp.beatBytes) def widen(x: TransferSizes) = if (passthrough && x.min <= 2mp.beatBytes) TransferSizes(1, max(mp.beatBytes, x.max)) else ourSupport val canDoit = m.supportsPutFull.contains(ourSupport) && m.supportsGet.contains(ourSupport) // Blow up if there are devices to which we cannot add Atomics, because their R\|W are too inflexible require (!m.supportsPutFull \|\| !m.supportsGet \|\| canDoit, s"${m.name} has $ourSupport, needed PutFull(${m.supportsPutFull}) or Get(${m.supportsGet})") m.v1copy( supportsArithmetic = if (!arithmetic \|\| !canDoit) m.supportsArithmetic else widen(m.supportsArithmetic), supportsLogical = if (!logical \|\| !canDoit) m.supportsLogical else widen(m.supportsLogical), mayDenyGet = m.mayDenyGet \|\| m.mayDenyPut) })}) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val managers = edgeOut.manager.managers val beatBytes = edgeOut.manager.beatBytes // To which managers are we adding atomic support? val ourSupport = TransferSizes(1, beatBytes) val managersNeedingHelp = managers.filter { m => m.supportsPutFull.contains(ourSupport) && m.supportsGet.contains(ourSupport) && ((logical && !m.supportsLogical .contains(ourSupport)) \|\| (arithmetic && !m.supportsArithmetic.contains(ourSupport)) \|\| !passthrough) // we will do atomics for everyone we can } // Managers that need help with atomics must necessarily have this node as the root of a tree in the node graph. // (But they must also ensure no sideband operations can get between the read and write.) val violations = managersNeedingHelp.flatMap(_.findTreeViolation()).map { node => (node.name, node.inputs.map(_._1.name)) } require(violations.isEmpty, s"AtomicAutomata can only help nodes for which it is at the root of a diplomatic node tree," + "but the following violations were found:\n" + violations.map(v => s"(${v._1} has parents ${v._2})").mkString("\n")) // We cannot add atomics to a non-FIFO manager managersNeedingHelp foreach { m => require (m.fifoId.isDefined) } // We need to preserve FIFO semantics across FIFO domains, not managers // Suppose you have Put(42) Atomic(+1) both inflight; valid results: 42 or 43 // If we allow Put(42) Get() Put(+1) concurrent; valid results: 42 43 OR undef // Making non-FIFO work requires waiting for all Acks to come back (=> use FIFOFixer) val domainsNeedingHelp = managersNeedingHelp.map(_.fifoId.get).distinct // Don't overprovision the CAM val camSize = min(domainsNeedingHelp.size, concurrency) // Compact the fifoIds to only those we care about def camFifoId(m: TLSlaveParameters) = m.fifoId.map(id => max(0, domainsNeedingHelp.indexOf(id))).getOrElse(0) // CAM entry state machine val FREE = 0.U // unused waiting on Atomic from A val GET = 3.U // Get sent down A waiting on AccessDataAck from D val AMO = 2.U // AccessDataAck sent up D waiting for A availability val ACK = 1.U // Put sent down A waiting for PutAck from D val params = TLAtomicAutomata.CAMParams(out.a.bits.params, domainsNeedingHelp.size) // Do we need to do anything at all? if (camSize > 0) { val initval = Wire(new TLAtomicAutomata.CAM_S(params)) initval.state := FREE val cam_s = RegInit(VecInit.fill(camSize)(initval)) val cam_a = Reg(Vec(camSize, new TLAtomicAutomata.CAM_A(params))) val cam_d = Reg(Vec(camSize, new TLAtomicAutomata.CAM_D(params))) val cam_free = cam_s.map(_.state === FREE) val cam_amo = cam_s.map(_.state === AMO) val cam_abusy = cam_s.map(e => e.state === GET \|\| e.state === AMO) // A is blocked val cam_dmatch = cam_s.map(e => e.state =/= FREE) // D should inspect these entries // Can the manager already handle this message? val a_address = edgeIn.address(in.a.bits) val a_size = edgeIn.size(in.a.bits) val a_canLogical = passthrough.B && edgeOut.manager.supportsLogicalFast (a_address, a_size) val a_canArithmetic = passthrough.B && edgeOut.manager.supportsArithmeticFast(a_address, a_size) val a_isLogical = in.a.bits.opcode === TLMessages.LogicalData val a_isArithmetic = in.a.bits.opcode === TLMessages.ArithmeticData val a_isSupported = Mux(a_isLogical, a_canLogical, Mux(a_isArithmetic, a_canArithmetic, true.B)) // Must we do a Put? val a_cam_any_put = cam_amo.reduce(_ \|\| _) val a_cam_por_put = cam_amo.scanLeft(false.B)(_\|\|_).init val a_cam_sel_put = (cam_amo zip a_cam_por_put) map { case (a, b) => a && !b } val a_cam_a = PriorityMux(cam_amo, cam_a) val a_cam_d = PriorityMux(cam_amo, cam_d) val a_a = a_cam_a.bits.data val a_d = a_cam_d.data // Does the A request conflict with an inflight AMO? val a_fifoId = edgeOut.manager.fastProperty(a_address, camFifoId _, (i:Int) => i.U) val a_cam_busy = (cam_abusy zip cam_a.map(_.fifoId === a_fifoId)) map { case (a,b) => a&&b } reduce (_\|\|_) // (Where) are we are allocating in the CAM? val a_cam_any_free = cam_free.reduce(_ \|\| _) val a_cam_por_free = cam_free.scanLeft(false.B)(_\|\|_).init val a_cam_sel_free = (cam_free zip a_cam_por_free) map { case (a,b) => a && !b } // Logical AMO val indexes = Seq.tabulate(beatBytes8) { i => Cat(a_a(i,i), a_d(i,i)) } val logic_out = Cat(indexes.map(x => a_cam_a.lut(x).asUInt).reverse) // Arithmetic AMO val unsigned = a_cam_a.bits.param(1) val take_max = a_cam_a.bits.param(0) val adder = a_cam_a.bits.param(2) val mask = a_cam_a.bits.mask val signSel = ~(~mask \| (mask >> 1)) val signbits_a = Cat(Seq.tabulate(beatBytes) { i => a_a(8i+7,8i+7) } .reverse) val signbits_d = Cat(Seq.tabulate(beatBytes) { i => a_d(8i+7,8i+7) } .reverse) // Move the selected sign bit into the first byte position it will extend val signbit_a = ((signbits_a & signSel) << 1)(beatBytes-1, 0) val signbit_d = ((signbits_d & signSel) << 1)(beatBytes-1, 0) val signext_a = FillInterleaved(8, leftOR(signbit_a)) val signext_d = FillInterleaved(8, leftOR(signbit_d)) // NOTE: sign-extension does not change the relative ordering in EITHER unsigned or signed arithmetic val wide_mask = FillInterleaved(8, mask) val a_a_ext = (a_a & wide_mask) \| signext_a val a_d_ext = (a_d & wide_mask) \| signext_d val a_d_inv = Mux(adder, a_d_ext, ~a_d_ext) val adder_out = a_a_ext + a_d_inv val h = 8beatBytes-1 // now sign-extended; use biggest bit val a_bigger_uneq = unsigned === a_a_ext(h) // result if high bits are unequal val a_bigger = Mux(a_a_ext(h) === a_d_ext(h), !adder_out(h), a_bigger_uneq) val pick_a = take_max === a_bigger val arith_out = Mux(adder, adder_out, Mux(pick_a, a_a, a_d)) // AMO result data val amo_data = if (!logical) arith_out else if (!arithmetic) logic_out else Mux(a_cam_a.bits.opcode(0), logic_out, arith_out) // Potentially mutate the message from inner val source_i = Wire(chiselTypeOf(in.a)) val a_allow = !a_cam_busy && (a_isSupported \|\| a_cam_any_free) in.a.ready := source_i.ready && a_allow source_i.valid := in.a.valid && a_allow source_i.bits := in.a.bits when (!a_isSupported) { // minimal mux difference source_i.bits.opcode := TLMessages.Get source_i.bits.param := 0.U } // Potentially take the message from the CAM val source_c = Wire(chiselTypeOf(in.a)) source_c.valid := a_cam_any_put source_c.bits := edgeOut.Put( fromSource = a_cam_a.bits.source, toAddress = edgeIn.address(a_cam_a.bits), lgSize = a_cam_a.bits.size, data = amo_data, corrupt = a_cam_a.bits.corrupt \|\| a_cam_d.corrupt)._2 source_c.bits.user :<= a_cam_a.bits.user source_c.bits.echo :<= a_cam_a.bits.echo // Finishing an AMO from the CAM has highest priority TLArbiter(TLArbiter.lowestIndexFirst)(out.a, (0.U, source_c), (edgeOut.numBeats1(in.a.bits), source_i)) // Capture the A state into the CAM when (source_i.fire && !a_isSupported) { (a_cam_sel_free zip cam_a) foreach { case (en, r) => when (en) { r.fifoId := a_fifoId r.bits := in.a.bits r.lut := MuxLookup(in.a.bits.param(1, 0), 0.U(4.W))(Array( TLAtomics.AND -> 0x8.U, TLAtomics.OR -> 0xe.U, TLAtomics.XOR -> 0x6.U, TLAtomics.SWAP -> 0xc.U)) } } (a_cam_sel_free zip cam_s) foreach { case (en, r) => when (en) { r.state := GET } } } // Advance the put state when (source_c.fire) { (a_cam_sel_put zip cam_s) foreach { case (en, r) => when (en) { r.state := ACK } } } // We need to deal with a potential D response in the same cycle as the A request val d_first = edgeOut.first(out.d) val d_cam_sel_raw = cam_a.map(_.bits.source === in.d.bits.source) val d_cam_sel_match = (d_cam_sel_raw zip cam_dmatch) map { case (a,b) => a&&b } val d_cam_data = Mux1H(d_cam_sel_match, cam_d.map(_.data)) val d_cam_denied = Mux1H(d_cam_sel_match, cam_d.map(_.denied)) val d_cam_corrupt = Mux1H(d_cam_sel_match, cam_d.map(_.corrupt)) val d_cam_sel_bypass = if (edgeOut.manager.minLatency > 0) false.B else out.d.bits.source === in.a.bits.source && in.a.valid && !a_isSupported val d_cam_sel = (a_cam_sel_free zip d_cam_sel_match) map { case (a,d) => Mux(d_cam_sel_bypass, a, d) } val d_cam_sel_any = d_cam_sel_bypass \|\| d_cam_sel_match.reduce(_ \|\| _) val d_ackd = out.d.bits.opcode === TLMessages.AccessAckData val d_ack = out.d.bits.opcode === TLMessages.AccessAck when (out.d.fire && d_first) { (d_cam_sel zip cam_d) foreach { case (en, r) => when (en && d_ackd) { r.data := out.d.bits.data r.denied := out.d.bits.denied r.corrupt := out.d.bits.corrupt } } (d_cam_sel zip cam_s) foreach { case (en, r) => when (en) { // Note: it is important that this comes AFTER the := GET, so we can go FREE=>GET=>AMO in one cycle r.state := Mux(d_ackd, AMO, FREE) } } } val d_drop = d_first && d_ackd && d_cam_sel_any val d_replace = d_first && d_ack && d_cam_sel_match.reduce(_ \|\| _) in.d.valid := out.d.valid && !d_drop out.d.ready := in.d.ready \|\| d_drop in.d.bits := out.d.bits when (d_replace) { // minimal muxes in.d.bits.opcode := TLMessages.AccessAckData in.d.bits.data := d_cam_data in.d.bits.corrupt := d_cam_corrupt \|\| out.d.bits.denied in.d.bits.denied := d_cam_denied \|\| out.d.bits.denied } } else { out.a.valid := in.a.valid in.a.ready := out.a.ready out.a.bits := in.a.bits in.d.valid := out.d.valid out.d.ready := in.d.ready in.d.bits := out.d.bits } if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { in.b.valid := out.b.valid out.b.ready := in.b.ready in.b.bits := out.b.bits out.c.valid := in.c.valid in.c.ready := out.c.ready out.c.bits := in.c.bits out.e.valid := in.e.valid in.e.ready := out.e.ready out.e.bits := in.e.bits } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLAtomicAutomata { def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val atomics = LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough) { override lazy val desiredName = (Seq("TLAtomicAutomata") ++ nameSuffix).mkString("_") }) atomics.node } case class CAMParams(a: TLBundleParameters, domainsNeedingHelp: Int) class CAM_S(val params: CAMParams) extends Bundle { val state = UInt(2.W) } class CAM_A(val params: CAMParams) extends Bundle { val bits = new TLBundleA(params.a) val fifoId = UInt(log2Up(params.domainsNeedingHelp).W) val lut = UInt(4.W) } class CAM_D(val params: CAMParams) extends Bundle { val data = UInt(params.a.dataBits.W) val denied = Bool() val corrupt = Bool() } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMAtomicAutomata(txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("AtomicAutomata")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) // Confirm that the AtomicAutomata combines read + write errors import TLMessages._ val test = new RequestPattern({a: TLBundleA => val doesA = a.opcode === ArithmeticData \|\| a.opcode === LogicalData val doesR = a.opcode === Get \|\| doesA val doesW = a.opcode === PutFullData \|\| a.opcode === PutPartialData \|\| doesA (doesR && RequestPattern.overlaps(Seq(AddressSet(0x08, ~0x08)))(a)) \|\| (doesW && RequestPattern.overlaps(Seq(AddressSet(0x10, ~0x10)))(a)) }) (ram.node := TLErrorEvaluator(test) := TLFragmenter(4, 256) := TLDelayer(0.1) := TLAtomicAutomata() := TLDelayer(0.1) := TLErrorEvaluator(test, testOn=true, testOff=true) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMAtomicAutomataTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMAtomicAutomata(txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File Arbiter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ object TLArbiter { // (valids, select) => readys type Policy = (Integer, UInt, Bool) => UInt val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0) val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width)) val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else { val valid = valids(width-1, 0) assert (valid === valids) val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0)) val filter = Cat(valid & ~mask, valid) val unready = (rightOR(filter, width2, width) >> 1) \| (mask << width) val readys = ~((unready >> width) & unready(width-1, 0)) when (select && valid.orR) { mask := leftOR(readys & valid, width) } readys(width-1, 0) } def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = { apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_) } def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])): Unit = { if (sources.isEmpty) { sink.bits := DontCare } else if (sources.size == 1) { sink :<>= sources.head._2 } else { val pairs = sources.toList val beatsIn = pairs.map(_._1) val sourcesIn = pairs.map(_._2) // The number of beats which remain to be sent val beatsLeft = RegInit(0.U) val idle = beatsLeft === 0.U val latch = idle && sink.ready // winner (if any) claims sink // Who wants access to the sink? val valids = sourcesIn.map(_.valid) // Arbitrate amongst the requests val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools) // Which request wins arbitration? val winner = VecInit((readys zip valids) map { case (r,v) => r&&v }) // Confirm the policy works properly require (readys.size == valids.size) // Never two winners val prefixOR = winner.scanLeft(false.B)(_\|\|_).init assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _}) // If there was any request, there is a winner assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_)) // Track remaining beats val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) } val initBeats = maskedBeats.reduce(_ \| _) // no winner => 0 beats beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire) // The one-hot source granted access in the previous cycle val state = RegInit(VecInit(Seq.fill(sources.size)(false.B))) val muxState = Mux(idle, winner, state) state := muxState val allowed = Mux(idle, readys, state) (sourcesIn zip allowed) foreach { case (s, r) => s.ready := sink.ready && r } sink.valid := Mux(idle, valids.reduce(_\|\|_), Mux1H(state, valids)) sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits)) } } } // Synthesizable unit tests import freechips.rocketchip.unittest._ abstract class DecoupledArbiterTest( policy: TLArbiter.Policy, txns: Int, timeout: Int, val numSources: Int, beatsLeftFromIdx: Int => UInt) (implicit p: Parameters) extends UnitTest(timeout) { val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W)))) dontTouch(sources.suggestName("sources")) val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W))) dontTouch(sink.suggestName("sink")) val count = RegInit(0.U(log2Ceil(txns).W)) val lfsr = LFSR(16, true.B) sources.zipWithIndex.map { case (z, i) => z.bits := i.U } TLArbiter(policy)(sink, sources.zipWithIndex.map { case (z, i) => (beatsLeftFromIdx(i), z) }:_) count := count + 1.U io.finished := count >= txns.U } /** This tests that when a specific pattern of source valids are driven, * a new index from amongst that pattern is always selected, * unless one of those sources takes multiple beats, * in which case the same index should be selected until the arbiter goes idle. / class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false) (implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U) { val lastWinner = RegInit((numSources+1).U) val beatsLeft = RegInit(0.U(log2Ceil(numSources).W)) val first = lastWinner > numSources.U val valid = lfsr(0) val ready = lfsr(15) sink.ready := ready sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid) } when (sink.fire) { if (print) { printf("TestRobin: %d\n", sink.bits) } when (beatsLeft === 0.U) { assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.") lastWinner := sink.bits beatsLeft := sink.bits } .otherwise { assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats") beatsLeft := beatsLeft - 1.U } } if (print) { when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) } } } /* This tests that the lowest index is always selected across random single cycle transactions. / class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertLowest(id: Int): Unit = { when (sources(id).valid) { assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) } } /* This tests that the highest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertHighest(id: Int): Unit = { when (sources(id).valid) { assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) } }	module TLAtomicAutomata( // @[AtomicAutomata.scala:36:9] input clock, // @[AtomicAutomata.scala:36:9] input reset, // @[AtomicAutomata.scala:36:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire source_i_ready; // @[Arbiter.scala:94:31] reg [1:0] cam_s_0_state; // @[AtomicAutomata.scala:82:28] reg [2:0] cam_a_0_bits_opcode; // @[AtomicAutomata.scala:83:24] reg [2:0] cam_a_0_bits_param; // @[AtomicAutomata.scala:83:24] reg [3:0] cam_a_0_bits_size; // @[AtomicAutomata.scala:83:24] reg [6:0] cam_a_0_bits_source; // @[AtomicAutomata.scala:83:24] reg [28:0] cam_a_0_bits_address; // @[AtomicAutomata.scala:83:24] reg [7:0] cam_a_0_bits_mask; // @[AtomicAutomata.scala:83:24] reg [63:0] cam_a_0_bits_data; // @[AtomicAutomata.scala:83:24] reg cam_a_0_bits_corrupt; // @[AtomicAutomata.scala:83:24] reg [3:0] cam_a_0_lut; // @[AtomicAutomata.scala:83:24] reg [63:0] cam_d_0_data; // @[AtomicAutomata.scala:84:24] reg cam_d_0_denied; // @[AtomicAutomata.scala:84:24] reg cam_d_0_corrupt; // @[AtomicAutomata.scala:84:24] wire cam_free_0 = cam_s_0_state == 2'h0; // @[AtomicAutomata.scala:82:28, :86:44] wire winner_0 = cam_s_0_state == 2'h2; // @[AtomicAutomata.scala:82:28, :87:44] wire _a_canArithmetic_T_3 = auto_in_a_bits_size < 4'h4; // @[Parameters.scala:92:38] wire [4:0] _GEN = {auto_in_a_bits_address[28:27], auto_in_a_bits_address[25], auto_in_a_bits_address[16], ~(auto_in_a_bits_address[12])}; // @[Parameters.scala:137:{31,41,46}] wire [4:0] _GEN_0 = {auto_in_a_bits_address[28:27] ^ 2'h2, auto_in_a_bits_address[25], auto_in_a_bits_address[16], auto_in_a_bits_address[12]}; // @[Parameters.scala:137:{31,41,46}] wire a_isSupported = auto_in_a_bits_opcode == 3'h3 ? _a_canArithmetic_T_3 & (~(\|_GEN) \| ~(\|_GEN_0)) : auto_in_a_bits_opcode != 3'h2 \| _a_canArithmetic_T_3 & (~(\|_GEN) \| ~(\|_GEN_0)); // @[Parameters.scala:684:54, :685:42] wire [3:0] _logic_out_T = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[0], cam_d_0_data[0]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_2 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[1], cam_d_0_data[1]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_4 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[2], cam_d_0_data[2]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_6 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[3], cam_d_0_data[3]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_8 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[4], cam_d_0_data[4]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_10 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[5], cam_d_0_data[5]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_12 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[6], cam_d_0_data[6]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_14 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[7], cam_d_0_data[7]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_16 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[8], cam_d_0_data[8]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_18 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[9], cam_d_0_data[9]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_20 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[10], cam_d_0_data[10]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_22 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[11], cam_d_0_data[11]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_24 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[12], cam_d_0_data[12]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_26 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[13], cam_d_0_data[13]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_28 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[14], cam_d_0_data[14]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_30 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[15], cam_d_0_data[15]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_32 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[16], cam_d_0_data[16]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_34 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[17], cam_d_0_data[17]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_36 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[18], cam_d_0_data[18]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_38 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[19], cam_d_0_data[19]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_40 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[20], cam_d_0_data[20]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_42 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[21], cam_d_0_data[21]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_44 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[22], cam_d_0_data[22]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_46 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[23], cam_d_0_data[23]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_48 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[24], cam_d_0_data[24]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_50 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[25], cam_d_0_data[25]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_52 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[26], cam_d_0_data[26]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_54 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[27], cam_d_0_data[27]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_56 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[28], cam_d_0_data[28]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_58 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[29], cam_d_0_data[29]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_60 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[30], cam_d_0_data[30]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_62 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[31], cam_d_0_data[31]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_64 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[32], cam_d_0_data[32]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_66 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[33], cam_d_0_data[33]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_68 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[34], cam_d_0_data[34]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_70 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[35], cam_d_0_data[35]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_72 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[36], cam_d_0_data[36]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_74 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[37], cam_d_0_data[37]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_76 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[38], cam_d_0_data[38]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_78 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[39], cam_d_0_data[39]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_80 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[40], cam_d_0_data[40]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_82 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[41], cam_d_0_data[41]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_84 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[42], cam_d_0_data[42]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_86 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[43], cam_d_0_data[43]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_88 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[44], cam_d_0_data[44]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_90 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[45], cam_d_0_data[45]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_92 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[46], cam_d_0_data[46]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_94 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[47], cam_d_0_data[47]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_96 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[48], cam_d_0_data[48]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_98 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[49], cam_d_0_data[49]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_100 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[50], cam_d_0_data[50]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_102 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[51], cam_d_0_data[51]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_104 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[52], cam_d_0_data[52]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_106 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[53], cam_d_0_data[53]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_108 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[54], cam_d_0_data[54]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_110 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[55], cam_d_0_data[55]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_112 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[56], cam_d_0_data[56]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_114 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[57], cam_d_0_data[57]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_116 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[58], cam_d_0_data[58]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_118 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[59], cam_d_0_data[59]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_120 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[60], cam_d_0_data[60]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_122 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[61], cam_d_0_data[61]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_124 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[62], cam_d_0_data[62]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_126 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[63], cam_d_0_data[63]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [6:0] _GEN_1 = ~(cam_a_0_bits_mask[6:0]) \| cam_a_0_bits_mask[7:1]; // @[AtomicAutomata.scala:83:24, :127:{25,31,39}] wire [6:0] _signbit_a_T = {cam_a_0_bits_data[55], cam_a_0_bits_data[47], cam_a_0_bits_data[39], cam_a_0_bits_data[31], cam_a_0_bits_data[23], cam_a_0_bits_data[15], cam_a_0_bits_data[7]} & ~_GEN_1; // @[AtomicAutomata.scala:83:24, :119:63, :127:{23,31}, :128:29, :131:38] wire [6:0] _signbit_d_T = {cam_d_0_data[55], cam_d_0_data[47], cam_d_0_data[39], cam_d_0_data[31], cam_d_0_data[23], cam_d_0_data[15], cam_d_0_data[7]} & ~_GEN_1; // @[AtomicAutomata.scala:84:24, :119:73, :127:{23,31}, :129:29, :132:38] wire [5:0] _GEN_2 = _signbit_a_T[6:1] \| _signbit_a_T[5:0]; // @[package.scala:253:{43,53}] wire [3:0] _GEN_3 = _GEN_2[5:2] \| _GEN_2[3:0]; // @[package.scala:253:{43,53}] wire _signext_a_T_13 = _GEN_2[1] \| _signbit_a_T[0]; // @[package.scala:253:43] wire [5:0] _GEN_4 = _signbit_d_T[6:1] \| _signbit_d_T[5:0]; // @[package.scala:253:{43,53}] wire [3:0] _GEN_5 = _GEN_4[5:2] \| _GEN_4[3:0]; // @[package.scala:253:{43,53}] wire _signext_d_T_13 = _GEN_4[1] \| _signbit_d_T[0]; // @[package.scala:253:43] wire [63:0] wide_mask = {{8{cam_a_0_bits_mask[7]}}, {8{cam_a_0_bits_mask[6]}}, {8{cam_a_0_bits_mask[5]}}, {8{cam_a_0_bits_mask[4]}}, {8{cam_a_0_bits_mask[3]}}, {8{cam_a_0_bits_mask[2]}}, {8{cam_a_0_bits_mask[1]}}, {8{cam_a_0_bits_mask[0]}}}; // @[AtomicAutomata.scala:83:24, :136:40] wire [63:0] a_a_ext = cam_a_0_bits_data & wide_mask \| {{8{_GEN_3[3] \| _signext_a_T_13}}, {8{_GEN_3[2] \| _GEN_2[0]}}, {8{_GEN_3[1] \| _signbit_a_T[0]}}, {8{_GEN_3[0]}}, {8{_signext_a_T_13}}, {8{_GEN_2[0]}}, {8{_signbit_a_T[0]}}, 8'h0}; // @[package.scala:253:43] wire [63:0] a_d_ext = cam_d_0_data & wide_mask \| {{8{_GEN_5[3] \| _signext_d_T_13}}, {8{_GEN_5[2] \| _GEN_4[0]}}, {8{_GEN_5[1] \| _signbit_d_T[0]}}, {8{_GEN_5[0]}}, {8{_signext_d_T_13}}, {8{_GEN_4[0]}}, {8{_signbit_d_T[0]}}, 8'h0}; // @[package.scala:253:43] wire [63:0] _adder_out_T = a_a_ext + ({64{~(cam_a_0_bits_param[2])}} ^ a_d_ext); // @[AtomicAutomata.scala:83:24, :125:39, :137:41, :138:41, :139:26, :140:33] wire a_allow = ~((&cam_s_0_state) \| winner_0) & (a_isSupported \| cam_free_0); // @[AtomicAutomata.scala:82:28, :86:44, :87:44, :88:{49,57}, :98:32, :155:{23,35,53}] wire nodeIn_a_ready = source_i_ready & a_allow; // @[AtomicAutomata.scala:155:35, :156:38] wire source_i_valid = auto_in_a_valid & a_allow; // @[AtomicAutomata.scala:155:35, :157:38] wire source_c_bits_a_mask_sub_sub_sub_0_1 = cam_a_0_bits_size > 4'h2; // @[Misc.scala:206:21] wire source_c_bits_a_mask_sub_sub_size = cam_a_0_bits_size[1:0] == 2'h2; // @[OneHot.scala:64:49] wire source_c_bits_a_mask_sub_sub_0_1 = source_c_bits_a_mask_sub_sub_sub_0_1 \| source_c_bits_a_mask_sub_sub_size & ~(cam_a_0_bits_address[2]); // @[Misc.scala:206:21, :209:26, :210:26, :211:20, :215:{29,38}] wire source_c_bits_a_mask_sub_sub_1_1 = source_c_bits_a_mask_sub_sub_sub_0_1 \| source_c_bits_a_mask_sub_sub_size & cam_a_0_bits_address[2]; // @[Misc.scala:206:21, :209:26, :210:26, :215:{29,38}] wire source_c_bits_a_mask_sub_size = cam_a_0_bits_size[1:0] == 2'h1; // @[OneHot.scala:64:49] wire source_c_bits_a_mask_sub_0_2 = ~(cam_a_0_bits_address[2]) & ~(cam_a_0_bits_address[1]); // @[Misc.scala:210:26, :211:20, :214:27] wire source_c_bits_a_mask_sub_0_1 = source_c_bits_a_mask_sub_sub_0_1 \| source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}] wire source_c_bits_a_mask_sub_1_2 = ~(cam_a_0_bits_address[2]) & cam_a_0_bits_address[1]; // @[Misc.scala:210:26, :211:20, :214:27] wire source_c_bits_a_mask_sub_1_1 = source_c_bits_a_mask_sub_sub_0_1 \| source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}] wire source_c_bits_a_mask_sub_2_2 = cam_a_0_bits_address[2] & ~(cam_a_0_bits_address[1]); // @[Misc.scala:210:26, :211:20, :214:27] wire source_c_bits_a_mask_sub_2_1 = source_c_bits_a_mask_sub_sub_1_1 \| source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}] wire source_c_bits_a_mask_sub_3_2 = cam_a_0_bits_address[2] & cam_a_0_bits_address[1]; // @[Misc.scala:210:26, :214:27] wire source_c_bits_a_mask_sub_3_1 = source_c_bits_a_mask_sub_sub_1_1 \| source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}] reg [8:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire winner_1 = ~winner_0 & source_i_valid; // @[AtomicAutomata.scala:87:44, :157:38] wire _nodeOut_a_valid_T = winner_0 \| source_i_valid; // @[AtomicAutomata.scala:87:44, :157:38]
Generate the Verilog code corresponding to the following Chisel files. File btb.scala: package boom.v3.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix} import scala.math.min case class BoomBTBParams( nSets: Int = 128, nWays: Int = 2, offsetSz: Int = 13, extendedNSets: Int = 128 ) class BTBBranchPredictorBank(params: BoomBTBParams = BoomBTBParams())(implicit p: Parameters) extends BranchPredictorBank()(p) { override val nSets = params.nSets override val nWays = params.nWays val tagSz = vaddrBitsExtended - log2Ceil(nSets) - log2Ceil(fetchWidth) - 1 val offsetSz = params.offsetSz val extendedNSets = params.extendedNSets require(isPow2(nSets)) require(isPow2(extendedNSets) \|\| extendedNSets == 0) require(extendedNSets <= nSets) require(extendedNSets >= 1) class BTBEntry extends Bundle { val offset = SInt(offsetSz.W) val extended = Bool() } val btbEntrySz = offsetSz + 1 class BTBMeta extends Bundle { val is_br = Bool() val tag = UInt(tagSz.W) } val btbMetaSz = tagSz + 1 class BTBPredictMeta extends Bundle { val write_way = UInt(log2Ceil(nWays).W) } val s1_meta = Wire(new BTBPredictMeta) val f3_meta = RegNext(RegNext(s1_meta)) io.f3_meta := f3_meta.asUInt override val metaSz = s1_meta.asUInt.getWidth val doing_reset = RegInit(true.B) val reset_idx = RegInit(0.U(log2Ceil(nSets).W)) reset_idx := reset_idx + doing_reset when (reset_idx === (nSets-1).U) { doing_reset := false.B } val meta = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbMetaSz.W))) } val btb = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbEntrySz.W))) } val ebtb = SyncReadMem(extendedNSets, UInt(vaddrBitsExtended.W)) val mems = (((0 until nWays) map ({w:Int => Seq( (f"btb_meta_way$w", nSets, bankWidth * btbMetaSz), (f"btb_data_way$w", nSets, bankWidth * btbEntrySz))})).flatten ++ Seq(("ebtb", extendedNSets, vaddrBitsExtended))) val s1_req_rbtb = VecInit(btb.map { b => VecInit(b.read(s0_idx , s0_valid).map(_.asTypeOf(new BTBEntry))) }) val s1_req_rmeta = VecInit(meta.map { m => VecInit(m.read(s0_idx, s0_valid).map(_.asTypeOf(new BTBMeta))) }) val s1_req_rebtb = ebtb.read(s0_idx, s0_valid) val s1_req_tag = s1_idx >> log2Ceil(nSets) val s1_resp = Wire(Vec(bankWidth, Valid(UInt(vaddrBitsExtended.W)))) val s1_is_br = Wire(Vec(bankWidth, Bool())) val s1_is_jal = Wire(Vec(bankWidth, Bool())) val s1_hit_ohs = VecInit((0 until bankWidth) map { i => VecInit((0 until nWays) map { w => s1_req_rmeta(w)(i).tag === s1_req_tag(tagSz-1,0) }) }) val s1_hits = s1_hit_ohs.map { oh => oh.reduce(_\|\|_) } val s1_hit_ways = s1_hit_ohs.map { oh => PriorityEncoder(oh) } for (w <- 0 until bankWidth) { val entry_meta = s1_req_rmeta(s1_hit_ways(w))(w) val entry_btb = s1_req_rbtb(s1_hit_ways(w))(w) s1_resp(w).valid := !doing_reset && s1_valid && s1_hits(w) s1_resp(w).bits := Mux( entry_btb.extended, s1_req_rebtb, (s1_pc.asSInt + (w << 1).S + entry_btb.offset).asUInt) s1_is_br(w) := !doing_reset && s1_resp(w).valid && entry_meta.is_br s1_is_jal(w) := !doing_reset && s1_resp(w).valid && !entry_meta.is_br io.resp.f2(w) := io.resp_in(0).f2(w) io.resp.f3(w) := io.resp_in(0).f3(w) when (RegNext(s1_hits(w))) { io.resp.f2(w).predicted_pc := RegNext(s1_resp(w)) io.resp.f2(w).is_br := RegNext(s1_is_br(w)) io.resp.f2(w).is_jal := RegNext(s1_is_jal(w)) when (RegNext(s1_is_jal(w))) { io.resp.f2(w).taken := true.B } } when (RegNext(RegNext(s1_hits(w)))) { io.resp.f3(w).predicted_pc := RegNext(io.resp.f2(w).predicted_pc) io.resp.f3(w).is_br := RegNext(io.resp.f2(w).is_br) io.resp.f3(w).is_jal := RegNext(io.resp.f2(w).is_jal) when (RegNext(RegNext(s1_is_jal(w)))) { io.resp.f3(w).taken := true.B } } } val alloc_way = if (nWays > 1) { val r_metas = Cat(VecInit(s1_req_rmeta.map { w => VecInit(w.map(_.tag)) }).asUInt, s1_req_tag(tagSz-1,0)) val l = log2Ceil(nWays) val nChunks = (r_metas.getWidth + l - 1) / l val chunks = (0 until nChunks) map { i => r_metas(min((i+1)l, r_metas.getWidth)-1, il) } chunks.reduce(_^_) } else { 0.U } s1_meta.write_way := Mux(s1_hits.reduce(_\|\|_), PriorityEncoder(s1_hit_ohs.map(_.asUInt).reduce(_\|_)), alloc_way) val s1_update_cfi_idx = s1_update.bits.cfi_idx.bits val s1_update_meta = s1_update.bits.meta.asTypeOf(new BTBPredictMeta) val max_offset_value = Cat(0.B, ~(0.U((offsetSz-1).W))).asSInt val min_offset_value = Cat(1.B, (0.U((offsetSz-1).W))).asSInt val new_offset_value = (s1_update.bits.target.asSInt - (s1_update.bits.pc + (s1_update.bits.cfi_idx.bits << 1)).asSInt) val offset_is_extended = (new_offset_value > max_offset_value \|\| new_offset_value < min_offset_value) val s1_update_wbtb_data = Wire(new BTBEntry) s1_update_wbtb_data.extended := offset_is_extended s1_update_wbtb_data.offset := new_offset_value val s1_update_wbtb_mask = (UIntToOH(s1_update_cfi_idx) & Fill(bankWidth, s1_update.bits.cfi_idx.valid && s1_update.valid && s1_update.bits.cfi_taken && s1_update.bits.is_commit_update)) val s1_update_wmeta_mask = ((s1_update_wbtb_mask \| s1_update.bits.br_mask) & (Fill(bankWidth, s1_update.valid && s1_update.bits.is_commit_update) \| (Fill(bankWidth, s1_update.valid) & s1_update.bits.btb_mispredicts) ) ) val s1_update_wmeta_data = Wire(Vec(bankWidth, new BTBMeta)) for (w <- 0 until bankWidth) { s1_update_wmeta_data(w).tag := Mux(s1_update.bits.btb_mispredicts(w), 0.U, s1_update_idx >> log2Ceil(nSets)) s1_update_wmeta_data(w).is_br := s1_update.bits.br_mask(w) } for (w <- 0 until nWays) { when (doing_reset \|\| s1_update_meta.write_way === w.U \|\| (w == 0 && nWays == 1).B) { btb(w).write( Mux(doing_reset, reset_idx, s1_update_idx), Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(btbEntrySz.W) }), VecInit(Seq.fill(bankWidth) { s1_update_wbtb_data.asUInt })), Mux(doing_reset, (~(0.U(bankWidth.W))), s1_update_wbtb_mask).asBools ) meta(w).write( Mux(doing_reset, reset_idx, s1_update_idx), Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(btbMetaSz.W) }), VecInit(s1_update_wmeta_data.map(_.asUInt))), Mux(doing_reset, (~(0.U(bankWidth.W))), s1_update_wmeta_mask).asBools ) } } when (s1_update_wbtb_mask =/= 0.U && offset_is_extended) { ebtb.write(s1_update_idx, s1_update.bits.target) } }	module btb_0_1( // @[btb.scala:66:47] input [6:0] R0_addr, input R0_en, input R0_clk, output [55:0] R0_data, input [6:0] W0_addr, input W0_en, input W0_clk, input [55:0] W0_data, input [3:0] W0_mask ); btb_0_ext btb_0_ext ( // @[btb.scala:66:47] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data), .W0_mask (W0_mask) ); // @[btb.scala:66:47] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File SourceD.scala: / * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import TLMessages._ import TLAtomics._ import TLPermissions._ class SourceDRequest(params: InclusiveCacheParameters) extends FullRequest(params) { val sink = UInt(params.inner.bundle.sinkBits.W) val way = UInt(params.wayBits.W) val bad = Bool() } class SourceDHazard(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val way = UInt(params.wayBits.W) } class PutBufferACEntry(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val data = UInt(params.inner.bundle.dataBits.W) val mask = UInt((params.inner.bundle.dataBits/8).W) val corrupt = Bool() } class SourceD(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val req = Flipped(Decoupled(new SourceDRequest(params))) val d = Decoupled(new TLBundleD(params.inner.bundle)) // Put data from SinkA val pb_pop = Decoupled(new PutBufferPop(params)) val pb_beat = Flipped(new PutBufferAEntry(params)) // Release data from SinkC val rel_pop = Decoupled(new PutBufferPop(params)) val rel_beat = Flipped(new PutBufferCEntry(params)) // Access to the BankedStore val bs_radr = Decoupled(new BankedStoreInnerAddress(params)) val bs_rdat = Flipped(new BankedStoreInnerDecoded(params)) val bs_wadr = Decoupled(new BankedStoreInnerAddress(params)) val bs_wdat = new BankedStoreInnerPoison(params) // Is it safe to evict/replace this way? val evict_req = Flipped(new SourceDHazard(params)) val evict_safe = Bool() val grant_req = Flipped(new SourceDHazard(params)) val grant_safe = Bool() }) val beatBytes = params.inner.manager.beatBytes val writeBytes = params.micro.writeBytes val s1_valid = Wire(Bool()) val s2_valid = Wire(Bool()) val s3_valid = Wire(Bool()) val s2_ready = Wire(Bool()) val s3_ready = Wire(Bool()) val s4_ready = Wire(Bool()) ////////////////////////////////////// STAGE 1 ////////////////////////////////////// // Reform the request beats val busy = RegInit(false.B) val s1_block_r = RegInit(false.B) val s1_counter = RegInit(0.U(params.innerBeatBits.W)) val s1_req_reg = RegEnable(io.req.bits, !busy && io.req.valid) val s1_req = Mux(!busy, io.req.bits, s1_req_reg) val s1_x_bypass = Wire(UInt((beatBytes/writeBytes).W)) // might go from high=>low during stall val s1_latch_bypass = RegNext(!(busy \|\| io.req.valid) \|\| s2_ready) val s1_bypass = Mux(s1_latch_bypass, s1_x_bypass, RegEnable(s1_x_bypass, s1_latch_bypass)) val s1_mask = MaskGen(s1_req.offset, s1_req.size, beatBytes, writeBytes) & ~s1_bypass val s1_grant = (s1_req.opcode === AcquireBlock && s1_req.param === BtoT) \|\| s1_req.opcode === AcquirePerm val s1_need_r = s1_mask.orR && s1_req.prio(0) && s1_req.opcode =/= Hint && !s1_grant && (s1_req.opcode =/= PutFullData \|\| s1_req.size < log2Ceil(writeBytes).U ) val s1_valid_r = (busy \|\| io.req.valid) && s1_need_r && !s1_block_r val s1_need_pb = Mux(s1_req.prio(0), !s1_req.opcode(2), s1_req.opcode(0)) // hasData val s1_single = Mux(s1_req.prio(0), s1_req.opcode === Hint \|\| s1_grant, s1_req.opcode === Release) val s1_retires = !s1_single // retire all operations with data in s3 for bypass (saves energy) // Alternatively: val s1_retires = s1_need_pb // retire only updates for bypass (less backpressure from WB) val s1_beats1 = Mux(s1_single, 0.U, UIntToOH1(s1_req.size, log2Up(params.cache.blockBytes)) >> log2Ceil(beatBytes)) val s1_beat = (s1_req.offset >> log2Ceil(beatBytes)) \| s1_counter val s1_last = s1_counter === s1_beats1 val s1_first = s1_counter === 0.U params.ccover(s1_block_r, "SOURCED_1_SRAM_HOLD", "SRAM read-out successful, but stalled by stage 2") params.ccover(!s1_latch_bypass, "SOURCED_1_BYPASS_HOLD", "Bypass match successful, but stalled by stage 2") params.ccover((busy \|\| io.req.valid) && !s1_need_r, "SOURCED_1_NO_MODIFY", "Transaction servicable without SRAM") io.bs_radr.valid := s1_valid_r io.bs_radr.bits.noop := false.B io.bs_radr.bits.way := s1_req.way io.bs_radr.bits.set := s1_req.set io.bs_radr.bits.beat := s1_beat io.bs_radr.bits.mask := s1_mask params.ccover(io.bs_radr.valid && !io.bs_radr.ready, "SOURCED_1_READ_STALL", "Data readout stalled") // Make a queue to catch BS readout during stalls val queue = Module(new Queue(chiselTypeOf(io.bs_rdat), 3, flow=true)) queue.io.enq.valid := RegNext(RegNext(io.bs_radr.fire)) queue.io.enq.bits := io.bs_rdat assert (!queue.io.enq.valid \|\| queue.io.enq.ready) params.ccover(!queue.io.enq.ready, "SOURCED_1_QUEUE_FULL", "Filled SRAM skidpad queue completely") when (io.bs_radr.fire) { s1_block_r := true.B } when (io.req.valid) { busy := true.B } when (s1_valid && s2_ready) { s1_counter := s1_counter + 1.U s1_block_r := false.B when (s1_last) { s1_counter := 0.U busy := false.B } } params.ccover(s1_valid && !s2_ready, "SOURCED_1_STALL", "Stage 1 pipeline blocked") io.req.ready := !busy s1_valid := (busy \|\| io.req.valid) && (!s1_valid_r \|\| io.bs_radr.ready) ////////////////////////////////////// STAGE 2 ////////////////////////////////////// // Fetch the request data val s2_latch = s1_valid && s2_ready val s2_full = RegInit(false.B) val s2_valid_pb = RegInit(false.B) val s2_beat = RegEnable(s1_beat, s2_latch) val s2_bypass = RegEnable(s1_bypass, s2_latch) val s2_req = RegEnable(s1_req, s2_latch) val s2_last = RegEnable(s1_last, s2_latch) val s2_need_r = RegEnable(s1_need_r, s2_latch) val s2_need_pb = RegEnable(s1_need_pb, s2_latch) val s2_retires = RegEnable(s1_retires, s2_latch) val s2_need_d = RegEnable(!s1_need_pb \|\| s1_first, s2_latch) val s2_pdata_raw = Wire(new PutBufferACEntry(params)) val s2_pdata = s2_pdata_raw holdUnless s2_valid_pb s2_pdata_raw.data := Mux(s2_req.prio(0), io.pb_beat.data, io.rel_beat.data) s2_pdata_raw.mask := Mux(s2_req.prio(0), io.pb_beat.mask, ~0.U(params.inner.manager.beatBytes.W)) s2_pdata_raw.corrupt := Mux(s2_req.prio(0), io.pb_beat.corrupt, io.rel_beat.corrupt) io.pb_pop.valid := s2_valid_pb && s2_req.prio(0) io.pb_pop.bits.index := s2_req.put io.pb_pop.bits.last := s2_last io.rel_pop.valid := s2_valid_pb && !s2_req.prio(0) io.rel_pop.bits.index := s2_req.put io.rel_pop.bits.last := s2_last params.ccover(io.pb_pop.valid && !io.pb_pop.ready, "SOURCED_2_PUTA_STALL", "Channel A put buffer was not ready in time") if (!params.firstLevel) params.ccover(io.rel_pop.valid && !io.rel_pop.ready, "SOURCED_2_PUTC_STALL", "Channel C put buffer was not ready in time") val pb_ready = Mux(s2_req.prio(0), io.pb_pop.ready, io.rel_pop.ready) when (pb_ready) { s2_valid_pb := false.B } when (s2_valid && s3_ready) { s2_full := false.B } when (s2_latch) { s2_valid_pb := s1_need_pb } when (s2_latch) { s2_full := true.B } params.ccover(s2_valid && !s3_ready, "SOURCED_2_STALL", "Stage 2 pipeline blocked") s2_valid := s2_full && (!s2_valid_pb \|\| pb_ready) s2_ready := !s2_full \|\| (s3_ready && (!s2_valid_pb \|\| pb_ready)) ////////////////////////////////////// STAGE 3 ////////////////////////////////////// // Send D response val s3_latch = s2_valid && s3_ready val s3_full = RegInit(false.B) val s3_valid_d = RegInit(false.B) val s3_beat = RegEnable(s2_beat, s3_latch) val s3_bypass = RegEnable(s2_bypass, s3_latch) val s3_req = RegEnable(s2_req, s3_latch) val s3_adjusted_opcode = Mux(s3_req.bad, Get, s3_req.opcode) // kill update when denied val s3_last = RegEnable(s2_last, s3_latch) val s3_pdata = RegEnable(s2_pdata, s3_latch) val s3_need_pb = RegEnable(s2_need_pb, s3_latch) val s3_retires = RegEnable(s2_retires, s3_latch) val s3_need_r = RegEnable(s2_need_r, s3_latch) val s3_need_bs = s3_need_pb val s3_acq = s3_req.opcode === AcquireBlock \|\| s3_req.opcode === AcquirePerm // Collect s3's data from either the BankedStore or bypass // NOTE: we use the s3_bypass passed down from s1_bypass, because s2-s4 were guarded by the hazard checks and not stale val s3_bypass_data = Wire(UInt()) def chunk(x: UInt): Seq[UInt] = Seq.tabulate(beatBytes/writeBytes) { i => x((i+1)writeBytes8-1, iwriteBytes*8) } def chop (x: UInt): Seq[Bool] = Seq.tabulate(beatBytes/writeBytes) { i => x(i) } def bypass(sel: UInt, x: UInt, y: UInt) = (chop(sel) zip (chunk(x) zip chunk(y))) .map { case (s, (x, y)) => Mux(s, x, y) } .asUInt val s3_rdata = bypass(s3_bypass, s3_bypass_data, queue.io.deq.bits.data) // Lookup table for response codes val grant = Mux(s3_req.param === BtoT, Grant, GrantData) val resp_opcode = VecInit(Seq(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, grant, Grant)) // No restrictions on the type of buffer used here val d = Wire(chiselTypeOf(io.d)) io.d <> params.micro.innerBuf.d(d) d.valid := s3_valid_d d.bits.opcode := Mux(s3_req.prio(0), resp_opcode(s3_req.opcode), ReleaseAck) d.bits.param := Mux(s3_req.prio(0) && s3_acq, Mux(s3_req.param =/= NtoB, toT, toB), 0.U) d.bits.size := s3_req.size d.bits.source := s3_req.source d.bits.sink := s3_req.sink d.bits.denied := s3_req.bad d.bits.data := s3_rdata d.bits.corrupt := s3_req.bad && d.bits.opcode(0) queue.io.deq.ready := s3_valid && s4_ready && s3_need_r assert (!s3_full \|\| !s3_need_r \|\| queue.io.deq.valid) when (d.ready) { s3_valid_d := false.B } when (s3_valid && s4_ready) { s3_full := false.B } when (s3_latch) { s3_valid_d := s2_need_d } when (s3_latch) { s3_full := true.B } params.ccover(s3_valid && !s4_ready, "SOURCED_3_STALL", "Stage 3 pipeline blocked") s3_valid := s3_full && (!s3_valid_d \|\| d.ready) s3_ready := !s3_full \|\| (s4_ready && (!s3_valid_d \|\| d.ready)) ////////////////////////////////////// STAGE 4 ////////////////////////////////////// // Writeback updated data val s4_latch = s3_valid && s3_retires && s4_ready val s4_full = RegInit(false.B) val s4_beat = RegEnable(s3_beat, s4_latch) val s4_need_r = RegEnable(s3_need_r, s4_latch) val s4_need_bs = RegEnable(s3_need_bs, s4_latch) val s4_need_pb = RegEnable(s3_need_pb, s4_latch) val s4_req = RegEnable(s3_req, s4_latch) val s4_adjusted_opcode = RegEnable(s3_adjusted_opcode, s4_latch) val s4_pdata = RegEnable(s3_pdata, s4_latch) val s4_rdata = RegEnable(s3_rdata, s4_latch) val atomics = Module(new Atomics(params.inner.bundle)) atomics.io.write := s4_req.prio(2) atomics.io.a.opcode := s4_adjusted_opcode atomics.io.a.param := s4_req.param atomics.io.a.size := 0.U atomics.io.a.source := 0.U atomics.io.a.address := 0.U atomics.io.a.mask := s4_pdata.mask atomics.io.a.data := s4_pdata.data atomics.io.a.corrupt := DontCare atomics.io.data_in := s4_rdata io.bs_wadr.valid := s4_full && s4_need_bs io.bs_wadr.bits.noop := false.B io.bs_wadr.bits.way := s4_req.way io.bs_wadr.bits.set := s4_req.set io.bs_wadr.bits.beat := s4_beat io.bs_wadr.bits.mask := Cat(s4_pdata.mask.asBools.grouped(writeBytes).map(_.reduce(_\|\|_)).toList.reverse) io.bs_wdat.data := atomics.io.data_out assert (!(s4_full && s4_need_pb && s4_pdata.corrupt), "Data poisoning unsupported") params.ccover(io.bs_wadr.valid && !io.bs_wadr.ready, "SOURCED_4_WRITEBACK_STALL", "Data writeback stalled") params.ccover(s4_req.prio(0) && s4_req.opcode === ArithmeticData && s4_req.param === MIN, "SOURCED_4_ATOMIC_MIN", "Evaluated a signed minimum atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === ArithmeticData && s4_req.param === MAX, "SOURCED_4_ATOMIC_MAX", "Evaluated a signed maximum atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === ArithmeticData && s4_req.param === MINU, "SOURCED_4_ATOMIC_MINU", "Evaluated an unsigned minimum atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === ArithmeticData && s4_req.param === MAXU, "SOURCED_4_ATOMIC_MAXU", "Evaluated an unsigned minimum atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === ArithmeticData && s4_req.param === ADD, "SOURCED_4_ATOMIC_ADD", "Evaluated an addition atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === LogicalData && s4_req.param === XOR, "SOURCED_4_ATOMIC_XOR", "Evaluated a bitwise XOR atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === LogicalData && s4_req.param === OR, "SOURCED_4_ATOMIC_OR", "Evaluated a bitwise OR atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === LogicalData && s4_req.param === AND, "SOURCED_4_ATOMIC_AND", "Evaluated a bitwise AND atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === LogicalData && s4_req.param === SWAP, "SOURCED_4_ATOMIC_SWAP", "Evaluated a bitwise SWAP atomic") when (io.bs_wadr.ready \|\| !s4_need_bs) { s4_full := false.B } when (s4_latch) { s4_full := true.B } s4_ready := !s3_retires \|\| !s4_full \|\| io.bs_wadr.ready \|\| !s4_need_bs ////////////////////////////////////// RETIRED ////////////////////////////////////// // Record for bypass the last three retired writebacks // We need 3 slots to collect what was in s2, s3, s4 when the request was in s1 // ... you can't rely on s4 being full if bubbles got introduced between s1 and s2 val retire = s4_full && (io.bs_wadr.ready \|\| !s4_need_bs) val s5_req = RegEnable(s4_req, retire) val s5_beat = RegEnable(s4_beat, retire) val s5_dat = RegEnable(atomics.io.data_out, retire) val s6_req = RegEnable(s5_req, retire) val s6_beat = RegEnable(s5_beat, retire) val s6_dat = RegEnable(s5_dat, retire) val s7_dat = RegEnable(s6_dat, retire) ////////////////////////////////////// BYPASSS ////////////////////////////////////// // Manually retime this circuit to pull a register stage forward val pre_s3_req = Mux(s3_latch, s2_req, s3_req) val pre_s4_req = Mux(s4_latch, s3_req, s4_req) val pre_s5_req = Mux(retire, s4_req, s5_req) val pre_s6_req = Mux(retire, s5_req, s6_req) val pre_s3_beat = Mux(s3_latch, s2_beat, s3_beat) val pre_s4_beat = Mux(s4_latch, s3_beat, s4_beat) val pre_s5_beat = Mux(retire, s4_beat, s5_beat) val pre_s6_beat = Mux(retire, s5_beat, s6_beat) val pre_s5_dat = Mux(retire, atomics.io.data_out, s5_dat) val pre_s6_dat = Mux(retire, s5_dat, s6_dat) val pre_s7_dat = Mux(retire, s6_dat, s7_dat) val pre_s4_full = s4_latch \|\| (!(io.bs_wadr.ready \|\| !s4_need_bs) && s4_full) val pre_s3_4_match = pre_s4_req.set === pre_s3_req.set && pre_s4_req.way === pre_s3_req.way && pre_s4_beat === pre_s3_beat && pre_s4_full val pre_s3_5_match = pre_s5_req.set === pre_s3_req.set && pre_s5_req.way === pre_s3_req.way && pre_s5_beat === pre_s3_beat val pre_s3_6_match = pre_s6_req.set === pre_s3_req.set && pre_s6_req.way === pre_s3_req.way && pre_s6_beat === pre_s3_beat val pre_s3_4_bypass = Mux(pre_s3_4_match, MaskGen(pre_s4_req.offset, pre_s4_req.size, beatBytes, writeBytes), 0.U) val pre_s3_5_bypass = Mux(pre_s3_5_match, MaskGen(pre_s5_req.offset, pre_s5_req.size, beatBytes, writeBytes), 0.U) val pre_s3_6_bypass = Mux(pre_s3_6_match, MaskGen(pre_s6_req.offset, pre_s6_req.size, beatBytes, writeBytes), 0.U) s3_bypass_data := bypass(RegNext(pre_s3_4_bypass), atomics.io.data_out, RegNext( bypass(pre_s3_5_bypass, pre_s5_dat, bypass(pre_s3_6_bypass, pre_s6_dat, pre_s7_dat)))) // Detect which parts of s1 will be bypassed from later pipeline stages (s1-s4) // Note: we also bypass from reads ahead in the pipeline to save power val s1_2_match = s2_req.set === s1_req.set && s2_req.way === s1_req.way && s2_beat === s1_beat && s2_full && s2_retires val s1_3_match = s3_req.set === s1_req.set && s3_req.way === s1_req.way && s3_beat === s1_beat && s3_full && s3_retires val s1_4_match = s4_req.set === s1_req.set && s4_req.way === s1_req.way && s4_beat === s1_beat && s4_full for (i <- 0 until 8) { val cover = 1.U val s2 = s1_2_match === cover(0) val s3 = s1_3_match === cover(1) val s4 = s1_4_match === cover(2) params.ccover(io.req.valid && s2 && s3 && s4, "SOURCED_BYPASS_CASE_" + i, "Bypass data from all subsets of pipeline stages") } val s1_2_bypass = Mux(s1_2_match, MaskGen(s2_req.offset, s2_req.size, beatBytes, writeBytes), 0.U) val s1_3_bypass = Mux(s1_3_match, MaskGen(s3_req.offset, s3_req.size, beatBytes, writeBytes), 0.U) val s1_4_bypass = Mux(s1_4_match, MaskGen(s4_req.offset, s4_req.size, beatBytes, writeBytes), 0.U) s1_x_bypass := s1_2_bypass \| s1_3_bypass \| s1_4_bypass ////////////////////////////////////// HAZARDS ////////////////////////////////////// // SinkC, SourceC, and SinkD can never interfer with each other because their operation // is fully contained with an execution plan of an MSHR. That MSHR owns the entire set, so // there is no way for a data race. // However, SourceD is special. We allow it to run ahead after the MSHR and scheduler have // released control of a set+way. This is necessary to allow single cycle occupancy for // hits. Thus, we need to be careful about data hazards between SourceD and the other ports // of the BankedStore. We can at least compare to registers 's1_req_reg', because the first // cycle of SourceD falls within the occupancy of the MSHR's plan. // Must ReleaseData=> be interlocked? RaW hazard io.evict_safe := (!busy \|\| io.evict_req.way =/= s1_req_reg.way \|\| io.evict_req.set =/= s1_req_reg.set) && (!s2_full \|\| io.evict_req.way =/= s2_req.way \|\| io.evict_req.set =/= s2_req.set) && (!s3_full \|\| io.evict_req.way =/= s3_req.way \|\| io.evict_req.set =/= s3_req.set) && (!s4_full \|\| io.evict_req.way =/= s4_req.way \|\| io.evict_req.set =/= s4_req.set) // Must =>GrantData be interlocked? WaR hazard io.grant_safe := (!busy \|\| io.grant_req.way =/= s1_req_reg.way \|\| io.grant_req.set =/= s1_req_reg.set) && (!s2_full \|\| io.grant_req.way =/= s2_req.way \|\| io.grant_req.set =/= s2_req.set) && (!s3_full \|\| io.grant_req.way =/= s3_req.way \|\| io.grant_req.set =/= s3_req.set) && (!s4_full \|\| io.grant_req.way =/= s4_req.way \|\| io.grant_req.set =/= s4_req.set) // SourceD cannot overlap with SinkC b/c the only way inner caches could become // dirty such that they want to put data in via SinkC is if we Granted them permissions, // which must flow through the SourecD pipeline. }	module SourceD( // @[SourceD.scala:48:7] input clock, // @[SourceD.scala:48:7] input reset, // @[SourceD.scala:48:7] output io_req_ready, // @[SourceD.scala:50:14] input io_req_valid, // @[SourceD.scala:50:14] input io_req_bits_prio_0, // @[SourceD.scala:50:14] input io_req_bits_prio_1, // @[SourceD.scala:50:14] input io_req_bits_prio_2, // @[SourceD.scala:50:14] input io_req_bits_control, // @[SourceD.scala:50:14] input [2:0] io_req_bits_opcode, // @[SourceD.scala:50:14] input [2:0] io_req_bits_param, // @[SourceD.scala:50:14] input [2:0] io_req_bits_size, // @[SourceD.scala:50:14] input [7:0] io_req_bits_source, // @[SourceD.scala:50:14] input [12:0] io_req_bits_tag, // @[SourceD.scala:50:14] input [5:0] io_req_bits_offset, // @[SourceD.scala:50:14] input [5:0] io_req_bits_put, // @[SourceD.scala:50:14] input [9:0] io_req_bits_set, // @[SourceD.scala:50:14] input [3:0] io_req_bits_sink, // @[SourceD.scala:50:14] input [2:0] io_req_bits_way, // @[SourceD.scala:50:14] input io_req_bits_bad, // @[SourceD.scala:50:14] input io_d_ready, // @[SourceD.scala:50:14] output io_d_valid, // @[SourceD.scala:50:14] output [2:0] io_d_bits_opcode, // @[SourceD.scala:50:14] output [1:0] io_d_bits_param, // @[SourceD.scala:50:14] output [2:0] io_d_bits_size, // @[SourceD.scala:50:14] output [7:0] io_d_bits_source, // @[SourceD.scala:50:14] output [3:0] io_d_bits_sink, // @[SourceD.scala:50:14] output io_d_bits_denied, // @[SourceD.scala:50:14] output [127:0] io_d_bits_data, // @[SourceD.scala:50:14] output io_d_bits_corrupt, // @[SourceD.scala:50:14] input io_pb_pop_ready, // @[SourceD.scala:50:14] output io_pb_pop_valid, // @[SourceD.scala:50:14] output [5:0] io_pb_pop_bits_index, // @[SourceD.scala:50:14] output io_pb_pop_bits_last, // @[SourceD.scala:50:14] input [127:0] io_pb_beat_data, // @[SourceD.scala:50:14] input [15:0] io_pb_beat_mask, // @[SourceD.scala:50:14] input io_pb_beat_corrupt, // @[SourceD.scala:50:14] input io_rel_pop_ready, // @[SourceD.scala:50:14] output io_rel_pop_valid, // @[SourceD.scala:50:14] output [5:0] io_rel_pop_bits_index, // @[SourceD.scala:50:14] output io_rel_pop_bits_last, // @[SourceD.scala:50:14] input [127:0] io_rel_beat_data, // @[SourceD.scala:50:14] input io_rel_beat_corrupt, // @[SourceD.scala:50:14] input io_bs_radr_ready, // @[SourceD.scala:50:14] output io_bs_radr_valid, // @[SourceD.scala:50:14] output [2:0] io_bs_radr_bits_way, // @[SourceD.scala:50:14] output [9:0] io_bs_radr_bits_set, // @[SourceD.scala:50:14] output [1:0] io_bs_radr_bits_beat, // @[SourceD.scala:50:14] output [1:0] io_bs_radr_bits_mask, // @[SourceD.scala:50:14] input [127:0] io_bs_rdat_data, // @[SourceD.scala:50:14] input io_bs_wadr_ready, // @[SourceD.scala:50:14] output io_bs_wadr_valid, // @[SourceD.scala:50:14] output [2:0] io_bs_wadr_bits_way, // @[SourceD.scala:50:14] output [9:0] io_bs_wadr_bits_set, // @[SourceD.scala:50:14] output [1:0] io_bs_wadr_bits_beat, // @[SourceD.scala:50:14] output [1:0] io_bs_wadr_bits_mask, // @[SourceD.scala:50:14] output [127:0] io_bs_wdat_data, // @[SourceD.scala:50:14] input [9:0] io_evict_req_set, // @[SourceD.scala:50:14] input [2:0] io_evict_req_way, // @[SourceD.scala:50:14] output io_evict_safe, // @[SourceD.scala:50:14] input [9:0] io_grant_req_set, // @[SourceD.scala:50:14] input [2:0] io_grant_req_way, // @[SourceD.scala:50:14] output io_grant_safe // @[SourceD.scala:50:14] ); wire [127:0] _atomics_io_data_out; // @[SourceD.scala:258:23] wire _queue_io_enq_ready; // @[SourceD.scala:120:21] wire _queue_io_deq_valid; // @[SourceD.scala:120:21] wire [127:0] _queue_io_deq_bits_data; // @[SourceD.scala:120:21] wire io_req_valid_0 = io_req_valid; // @[SourceD.scala:48:7] wire io_req_bits_prio_0_0 = io_req_bits_prio_0; // @[SourceD.scala:48:7] wire io_req_bits_prio_1_0 = io_req_bits_prio_1; // @[SourceD.scala:48:7] wire io_req_bits_prio_2_0 = io_req_bits_prio_2; // @[SourceD.scala:48:7] wire io_req_bits_control_0 = io_req_bits_control; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_opcode_0 = io_req_bits_opcode; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_size_0 = io_req_bits_size; // @[SourceD.scala:48:7] wire [7:0] io_req_bits_source_0 = io_req_bits_source; // @[SourceD.scala:48:7] wire [12:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_offset_0 = io_req_bits_offset; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_put_0 = io_req_bits_put; // @[SourceD.scala:48:7] wire [9:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceD.scala:48:7] wire [3:0] io_req_bits_sink_0 = io_req_bits_sink; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_way_0 = io_req_bits_way; // @[SourceD.scala:48:7] wire io_req_bits_bad_0 = io_req_bits_bad; // @[SourceD.scala:48:7] wire io_d_ready_0 = io_d_ready; // @[SourceD.scala:48:7] wire io_pb_pop_ready_0 = io_pb_pop_ready; // @[SourceD.scala:48:7] wire [127:0] io_pb_beat_data_0 = io_pb_beat_data; // @[SourceD.scala:48:7] wire [15:0] io_pb_beat_mask_0 = io_pb_beat_mask; // @[SourceD.scala:48:7] wire io_pb_beat_corrupt_0 = io_pb_beat_corrupt; // @[SourceD.scala:48:7] wire io_rel_pop_ready_0 = io_rel_pop_ready; // @[SourceD.scala:48:7] wire [127:0] io_rel_beat_data_0 = io_rel_beat_data; // @[SourceD.scala:48:7] wire io_rel_beat_corrupt_0 = io_rel_beat_corrupt; // @[SourceD.scala:48:7] wire io_bs_radr_ready_0 = io_bs_radr_ready; // @[SourceD.scala:48:7] wire [127:0] io_bs_rdat_data_0 = io_bs_rdat_data; // @[SourceD.scala:48:7] wire io_bs_wadr_ready_0 = io_bs_wadr_ready; // @[SourceD.scala:48:7] wire [9:0] io_evict_req_set_0 = io_evict_req_set; // @[SourceD.scala:48:7] wire [2:0] io_evict_req_way_0 = io_evict_req_way; // @[SourceD.scala:48:7] wire [9:0] io_grant_req_set_0 = io_grant_req_set; // @[SourceD.scala:48:7] wire [2:0] io_grant_req_way_0 = io_grant_req_way; // @[SourceD.scala:48:7] wire io_bs_radr_bits_noop = 1'h0; // @[SourceD.scala:48:7] wire io_bs_wadr_bits_noop = 1'h0; // @[SourceD.scala:48:7] wire s1_mask_size = 1'h1; // @[Misc.scala:209:26] wire pre_s3_4_bypass_size = 1'h1; // @[Misc.scala:209:26] wire pre_s3_5_bypass_size = 1'h1; // @[Misc.scala:209:26] wire pre_s3_6_bypass_size = 1'h1; // @[Misc.scala:209:26] wire s1_2_bypass_size = 1'h1; // @[Misc.scala:209:26] wire s1_3_bypass_size = 1'h1; // @[Misc.scala:209:26] wire s1_4_bypass_size = 1'h1; // @[Misc.scala:209:26] wire [3:0] s1_mask_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_4_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_5_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_6_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_2_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_3_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_4_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [2:0] resp_opcode_0 = 3'h0; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_1 = 3'h0; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_7 = 3'h4; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_5 = 3'h2; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_2 = 3'h1; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_3 = 3'h1; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_4 = 3'h1; // @[SourceD.scala:215:28] wire [15:0] _s2_pdata_raw_mask_T = 16'hFFFF; // @[SourceD.scala:161:64] wire _io_req_ready_T; // @[SourceD.scala:140:19] wire d_ready = io_d_ready_0; // @[SourceD.scala:48:7, :218:15] wire d_valid; // @[SourceD.scala:218:15] wire [2:0] d_bits_opcode; // @[SourceD.scala:218:15] wire [1:0] d_bits_param; // @[SourceD.scala:218:15] wire [2:0] d_bits_size; // @[SourceD.scala:218:15] wire [7:0] d_bits_source; // @[SourceD.scala:218:15] wire [3:0] d_bits_sink; // @[SourceD.scala:218:15] wire d_bits_denied; // @[SourceD.scala:218:15] wire [127:0] d_bits_data; // @[SourceD.scala:218:15] wire d_bits_corrupt; // @[SourceD.scala:218:15] wire _io_pb_pop_valid_T; // @[SourceD.scala:164:34] wire _io_rel_pop_valid_T_1; // @[SourceD.scala:167:35] wire s1_valid_r; // @[SourceD.scala:96:56] wire [2:0] s1_req_way; // @[SourceD.scala:88:19] wire [9:0] s1_req_set; // @[SourceD.scala:88:19] wire [1:0] s1_beat; // @[SourceD.scala:102:56] wire [1:0] s1_mask; // @[SourceD.scala:92:76] wire _io_bs_wadr_valid_T; // @[SourceD.scala:270:31] wire [1:0] _io_bs_wadr_bits_mask_T_30; // @[SourceD.scala:275:30] wire _io_evict_safe_T_22; // @[SourceD.scala:378:90] wire _io_grant_safe_T_22; // @[SourceD.scala:385:90] wire io_req_ready_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_opcode_0; // @[SourceD.scala:48:7] wire [1:0] io_d_bits_param_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_size_0; // @[SourceD.scala:48:7] wire [7:0] io_d_bits_source_0; // @[SourceD.scala:48:7] wire [3:0] io_d_bits_sink_0; // @[SourceD.scala:48:7] wire io_d_bits_denied_0; // @[SourceD.scala:48:7] wire [127:0] io_d_bits_data_0; // @[SourceD.scala:48:7] wire io_d_bits_corrupt_0; // @[SourceD.scala:48:7] wire io_d_valid_0; // @[SourceD.scala:48:7] wire [5:0] io_pb_pop_bits_index_0; // @[SourceD.scala:48:7] wire io_pb_pop_bits_last_0; // @[SourceD.scala:48:7] wire io_pb_pop_valid_0; // @[SourceD.scala:48:7] wire [5:0] io_rel_pop_bits_index_0; // @[SourceD.scala:48:7] wire io_rel_pop_bits_last_0; // @[SourceD.scala:48:7] wire io_rel_pop_valid_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_radr_bits_way_0; // @[SourceD.scala:48:7] wire [9:0] io_bs_radr_bits_set_0; // @[SourceD.scala:48:7] wire [1:0] io_bs_radr_bits_beat_0; // @[SourceD.scala:48:7] wire [1:0] io_bs_radr_bits_mask_0; // @[SourceD.scala:48:7] wire io_bs_radr_valid_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_wadr_bits_way_0; // @[SourceD.scala:48:7] wire [9:0] io_bs_wadr_bits_set_0; // @[SourceD.scala:48:7] wire [1:0] io_bs_wadr_bits_beat_0; // @[SourceD.scala:48:7] wire [1:0] io_bs_wadr_bits_mask_0; // @[SourceD.scala:48:7] wire io_bs_wadr_valid_0; // @[SourceD.scala:48:7] wire [127:0] io_bs_wdat_data_0; // @[SourceD.scala:48:7] wire io_evict_safe_0; // @[SourceD.scala:48:7] wire io_grant_safe_0; // @[SourceD.scala:48:7] wire _s1_valid_T_3; // @[SourceD.scala:141:38] wire s1_valid; // @[SourceD.scala:74:22] wire _s2_valid_T_2; // @[SourceD.scala:183:23] wire s2_valid; // @[SourceD.scala:75:22] wire _s3_valid_T_2; // @[SourceD.scala:241:23] wire s3_valid; // @[SourceD.scala:76:22] wire _s2_ready_T_4; // @[SourceD.scala:184:24] wire s2_ready; // @[SourceD.scala:77:22] wire _s3_ready_T_4; // @[SourceD.scala:242:24] wire s3_ready; // @[SourceD.scala:78:22] wire _s4_ready_T_5; // @[SourceD.scala:293:59] wire s4_ready; // @[SourceD.scala:79:22] reg busy; // @[SourceD.scala:84:21] reg s1_block_r; // @[SourceD.scala:85:27] reg [1:0] s1_counter; // @[SourceD.scala:86:27] wire _s1_req_reg_T = ~busy; // @[SourceD.scala:84:21, :87:43] wire _s1_req_reg_T_1 = _s1_req_reg_T & io_req_valid_0; // @[SourceD.scala:48:7, :87:{43,49}] reg s1_req_reg_prio_0; // @[SourceD.scala:87:29] reg s1_req_reg_prio_1; // @[SourceD.scala:87:29] reg s1_req_reg_prio_2; // @[SourceD.scala:87:29] reg s1_req_reg_control; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_opcode; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_param; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_size; // @[SourceD.scala:87:29] reg [7:0] s1_req_reg_source; // @[SourceD.scala:87:29] reg [12:0] s1_req_reg_tag; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_offset; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_put; // @[SourceD.scala:87:29] reg [9:0] s1_req_reg_set; // @[SourceD.scala:87:29] reg [3:0] s1_req_reg_sink; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_way; // @[SourceD.scala:87:29] reg s1_req_reg_bad; // @[SourceD.scala:87:29] wire _s1_req_T = ~busy; // @[SourceD.scala:84:21, :87:43, :88:20] wire s1_req_prio_0 = _s1_req_T ? io_req_bits_prio_0_0 : s1_req_reg_prio_0; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_prio_1 = _s1_req_T ? io_req_bits_prio_1_0 : s1_req_reg_prio_1; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_prio_2 = _s1_req_T ? io_req_bits_prio_2_0 : s1_req_reg_prio_2; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_control = _s1_req_T ? io_req_bits_control_0 : s1_req_reg_control; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_opcode = _s1_req_T ? io_req_bits_opcode_0 : s1_req_reg_opcode; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_param = _s1_req_T ? io_req_bits_param_0 : s1_req_reg_param; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_size = _s1_req_T ? io_req_bits_size_0 : s1_req_reg_size; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [7:0] s1_req_source = _s1_req_T ? io_req_bits_source_0 : s1_req_reg_source; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [12:0] s1_req_tag = _s1_req_T ? io_req_bits_tag_0 : s1_req_reg_tag; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_offset = _s1_req_T ? io_req_bits_offset_0 : s1_req_reg_offset; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_put = _s1_req_T ? io_req_bits_put_0 : s1_req_reg_put; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign s1_req_set = _s1_req_T ? io_req_bits_set_0 : s1_req_reg_set; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [3:0] s1_req_sink = _s1_req_T ? io_req_bits_sink_0 : s1_req_reg_sink; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign s1_req_way = _s1_req_T ? io_req_bits_way_0 : s1_req_reg_way; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_bad = _s1_req_T ? io_req_bits_bad_0 : s1_req_reg_bad; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign io_bs_radr_bits_set_0 = s1_req_set; // @[SourceD.scala:48:7, :88:19] assign io_bs_radr_bits_way_0 = s1_req_way; // @[SourceD.scala:48:7, :88:19] wire [1:0] _s1_x_bypass_T_1; // @[SourceD.scala:360:44] wire [1:0] s1_x_bypass; // @[SourceD.scala:89:25] wire _T_1 = busy \| io_req_valid_0; // @[SourceD.scala:48:7, :84:21, :90:40] wire _s1_latch_bypass_T; // @[SourceD.scala:90:40] assign _s1_latch_bypass_T = _T_1; // @[SourceD.scala:90:40] wire _s1_valid_r_T; // @[SourceD.scala:96:26] assign _s1_valid_r_T = _T_1; // @[SourceD.scala:90:40, :96:26] wire _s1_valid_T; // @[SourceD.scala:141:21] assign _s1_valid_T = _T_1; // @[SourceD.scala:90:40, :141:21] wire _s1_latch_bypass_T_1 = ~_s1_latch_bypass_T; // @[SourceD.scala:90:{33,40}] wire _s1_latch_bypass_T_2 = _s1_latch_bypass_T_1 \| s2_ready; // @[SourceD.scala:77:22, :90:{33,57}] reg s1_latch_bypass; // @[SourceD.scala:90:32] reg [1:0] s1_bypass_r; // @[SourceD.scala:91:62] wire [1:0] s1_bypass = s1_latch_bypass ? s1_x_bypass : s1_bypass_r; // @[SourceD.scala:89:25, :90:32, :91:{22,62}] wire [3:0] _s1_mask_sizeOH_T = {1'h0, s1_req_size}; // @[Misc.scala:202:34] wire [1:0] s1_mask_sizeOH_shiftAmount = _s1_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _s1_mask_sizeOH_T_1 = 4'h1 << s1_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _s1_mask_sizeOH_T_2 = _s1_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire s1_mask_sub_0_1 = s1_req_size[2]; // @[Misc.scala:206:21] wire s1_mask_bit = s1_req_offset[3]; // @[Misc.scala:210:26] wire s1_mask_eq_1 = s1_mask_bit; // @[Misc.scala:210:26, :214:27] wire s1_mask_nbit = ~s1_mask_bit; // @[Misc.scala:210:26, :211:20] wire s1_mask_eq = s1_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _s1_mask_acc_T = s1_mask_eq; // @[Misc.scala:214:27, :215:38] wire s1_mask_acc = s1_mask_sub_0_1 \| _s1_mask_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _s1_mask_acc_T_1 = s1_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire s1_mask_acc_1 = s1_mask_sub_0_1 \| _s1_mask_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire [1:0] _s1_mask_T = {s1_mask_acc_1, s1_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] _s1_mask_T_1 = ~s1_bypass; // @[SourceD.scala:91:22, :92:78] assign s1_mask = _s1_mask_T & _s1_mask_T_1; // @[Misc.scala:222:10] assign io_bs_radr_bits_mask_0 = s1_mask; // @[SourceD.scala:48:7, :92:76] wire _GEN = s1_req_opcode == 3'h6; // @[SourceD.scala:88:19, :93:33] wire _s1_grant_T; // @[SourceD.scala:93:33] assign _s1_grant_T = _GEN; // @[SourceD.scala:93:33] wire _s1_single_T_2; // @[SourceD.scala:98:89] assign _s1_single_T_2 = _GEN; // @[SourceD.scala:93:33, :98:89] wire _s1_grant_T_1 = s1_req_param == 3'h2; // @[SourceD.scala:88:19, :93:66] wire _s1_grant_T_2 = _s1_grant_T & _s1_grant_T_1; // @[SourceD.scala:93:{33,50,66}] wire _s1_grant_T_3 = &s1_req_opcode; // @[SourceD.scala:88:19, :93:93] wire s1_grant = _s1_grant_T_2 \| _s1_grant_T_3; // @[SourceD.scala:93:{50,76,93}] wire _s1_need_r_T = \|s1_mask; // @[SourceD.scala:92:76, :94:27] wire _s1_need_r_T_1 = _s1_need_r_T & s1_req_prio_0; // @[SourceD.scala:88:19, :94:{27,31}] wire _s1_need_r_T_2 = s1_req_opcode != 3'h5; // @[SourceD.scala:88:19, :94:66] wire _s1_need_r_T_3 = _s1_need_r_T_1 & _s1_need_r_T_2; // @[SourceD.scala:94:{31,49,66}] wire _s1_need_r_T_4 = ~s1_grant; // @[SourceD.scala:93:76, :94:78] wire _s1_need_r_T_5 = _s1_need_r_T_3 & _s1_need_r_T_4; // @[SourceD.scala:94:{49,75,78}] wire _s1_need_r_T_6 = \|s1_req_opcode; // @[SourceD.scala:88:19, :95:34] wire _s1_need_r_T_7 = s1_req_size < 3'h3; // @[SourceD.scala:88:19, :95:65] wire _s1_need_r_T_8 = _s1_need_r_T_6 \| _s1_need_r_T_7; // @[SourceD.scala:95:{34,50,65}] wire s1_need_r = _s1_need_r_T_5 & _s1_need_r_T_8; // @[SourceD.scala:94:{75,88}, :95:50] wire _s1_valid_r_T_1 = _s1_valid_r_T & s1_need_r; // @[SourceD.scala:94:88, :96:{26,43}] wire _s1_valid_r_T_2 = ~s1_block_r; // @[SourceD.scala:85:27, :96:59] assign s1_valid_r = _s1_valid_r_T_1 & _s1_valid_r_T_2; // @[SourceD.scala:96:{43,56,59}] assign io_bs_radr_valid_0 = s1_valid_r; // @[SourceD.scala:48:7, :96:56] wire _s1_need_pb_T = s1_req_opcode[2]; // @[SourceD.scala:88:19, :97:54] wire _s1_need_pb_T_1 = ~_s1_need_pb_T; // @[SourceD.scala:97:{40,54}] wire _s1_need_pb_T_2 = s1_req_opcode[0]; // @[SourceD.scala:88:19, :97:72] wire s1_need_pb = s1_req_prio_0 ? _s1_need_pb_T_1 : _s1_need_pb_T_2; // @[SourceD.scala:88:19, :97:{23,40,72}] wire _s1_single_T = s1_req_opcode == 3'h5; // @[SourceD.scala:88:19, :98:53] wire _s1_single_T_1 = _s1_single_T \| s1_grant; // @[SourceD.scala:93:76, :98:{53,62}] wire s1_single = s1_req_prio_0 ? _s1_single_T_1 : _s1_single_T_2; // @[SourceD.scala:88:19, :98:{22,62,89}] wire s1_retires = ~s1_single; // @[SourceD.scala:98:22, :99:20] wire [12:0] _s1_beats1_T = 13'h3F << s1_req_size; // @[package.scala:243:71] wire [5:0] _s1_beats1_T_1 = _s1_beats1_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _s1_beats1_T_2 = ~_s1_beats1_T_1; // @[package.scala:243:{46,76}] wire [1:0] _s1_beats1_T_3 = _s1_beats1_T_2[5:4]; // @[package.scala:243:46] wire [1:0] s1_beats1 = s1_single ? 2'h0 : _s1_beats1_T_3; // @[SourceD.scala:98:22, :101:{22,95}] wire [1:0] _s1_beat_T = s1_req_offset[5:4]; // @[SourceD.scala:88:19, :102:32] assign s1_beat = _s1_beat_T \| s1_counter; // @[SourceD.scala:86:27, :102:{32,56}] assign io_bs_radr_bits_beat_0 = s1_beat; // @[SourceD.scala:48:7, :102:56] wire s1_last = s1_counter == s1_beats1; // @[SourceD.scala:86:27, :101:22, :103:28] wire s1_first = s1_counter == 2'h0; // @[SourceD.scala:86:27, :104:29] wire _queue_io_enq_valid_T = io_bs_radr_ready_0 & io_bs_radr_valid_0; // @[Decoupled.scala:51:35] reg queue_io_enq_valid_REG; // @[SourceD.scala:121:40] reg queue_io_enq_valid_REG_1; // @[SourceD.scala:121:32] wire s2_latch = s1_valid & s2_ready; // @[SourceD.scala:74:22, :77:22, :129:18, :146:27] wire [2:0] _s1_counter_T = {1'h0, s1_counter} + 3'h1; // @[SourceD.scala:86:27, :130:30] wire [1:0] _s1_counter_T_1 = _s1_counter_T[1:0]; // @[SourceD.scala:130:30] assign _io_req_ready_T = ~busy; // @[SourceD.scala:84:21, :87:43, :140:19] assign io_req_ready_0 = _io_req_ready_T; // @[SourceD.scala:48:7, :140:19] wire _s1_valid_T_1 = ~s1_valid_r; // @[SourceD.scala:96:56, :141:42] wire _s1_valid_T_2 = _s1_valid_T_1 \| io_bs_radr_ready_0; // @[SourceD.scala:48:7, :141:{42,54}] assign _s1_valid_T_3 = _s1_valid_T & _s1_valid_T_2; // @[SourceD.scala:141:{21,38,54}] assign s1_valid = _s1_valid_T_3; // @[SourceD.scala:74:22, :141:38] reg s2_full; // @[SourceD.scala:147:24] reg s2_valid_pb; // @[SourceD.scala:148:28] reg [1:0] s2_beat; // @[SourceD.scala:149:26] reg [1:0] s2_bypass; // @[SourceD.scala:150:28] reg s2_req_prio_0; // @[SourceD.scala:151:25] reg s2_req_prio_1; // @[SourceD.scala:151:25] reg s2_req_prio_2; // @[SourceD.scala:151:25] reg s2_req_control; // @[SourceD.scala:151:25] reg [2:0] s2_req_opcode; // @[SourceD.scala:151:25] reg [2:0] s2_req_param; // @[SourceD.scala:151:25] reg [2:0] s2_req_size; // @[SourceD.scala:151:25] reg [7:0] s2_req_source; // @[SourceD.scala:151:25] reg [12:0] s2_req_tag; // @[SourceD.scala:151:25] reg [5:0] s2_req_offset; // @[SourceD.scala:151:25] reg [5:0] s2_req_put; // @[SourceD.scala:151:25] assign io_pb_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25] assign io_rel_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25] reg [9:0] s2_req_set; // @[SourceD.scala:151:25] reg [3:0] s2_req_sink; // @[SourceD.scala:151:25] reg [2:0] s2_req_way; // @[SourceD.scala:151:25] reg s2_req_bad; // @[SourceD.scala:151:25] reg s2_last; // @[SourceD.scala:152:26] assign io_pb_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26] assign io_rel_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26] reg s2_need_r; // @[SourceD.scala:153:28] reg s2_need_pb; // @[SourceD.scala:154:29] reg s2_retires; // @[SourceD.scala:155:29] wire _s2_need_d_T = ~s1_need_pb; // @[SourceD.scala:97:23, :156:29] wire _s2_need_d_T_1 = _s2_need_d_T \| s1_first; // @[SourceD.scala:104:29, :156:{29,41}] reg s2_need_d; // @[SourceD.scala:156:28] wire [127:0] _s2_pdata_raw_data_T; // @[SourceD.scala:160:30] wire [15:0] _s2_pdata_raw_mask_T_1; // @[SourceD.scala:161:30] wire _s2_pdata_raw_corrupt_T; // @[SourceD.scala:162:30] wire [127:0] s2_pdata_raw_data; // @[SourceD.scala:157:26] wire [15:0] s2_pdata_raw_mask; // @[SourceD.scala:157:26] wire s2_pdata_raw_corrupt; // @[SourceD.scala:157:26] reg [127:0] s2_pdata_r_data; // @[package.scala:88:63] reg [15:0] s2_pdata_r_mask; // @[package.scala:88:63] reg s2_pdata_r_corrupt; // @[package.scala:88:63] wire [127:0] s2_pdata_data = s2_valid_pb ? s2_pdata_raw_data : s2_pdata_r_data; // @[package.scala:88:{42,63}] wire [15:0] s2_pdata_mask = s2_valid_pb ? s2_pdata_raw_mask : s2_pdata_r_mask; // @[package.scala:88:{42,63}] wire s2_pdata_corrupt = s2_valid_pb ? s2_pdata_raw_corrupt : s2_pdata_r_corrupt; // @[package.scala:88:{42,63}] assign _s2_pdata_raw_data_T = s2_req_prio_0 ? io_pb_beat_data_0 : io_rel_beat_data_0; // @[SourceD.scala:48:7, :151:25, :160:30] assign s2_pdata_raw_data = _s2_pdata_raw_data_T; // @[SourceD.scala:157:26, :160:30] assign _s2_pdata_raw_mask_T_1 = s2_req_prio_0 ? io_pb_beat_mask_0 : 16'hFFFF; // @[SourceD.scala:48:7, :151:25, :161:30] assign s2_pdata_raw_mask = _s2_pdata_raw_mask_T_1; // @[SourceD.scala:157:26, :161:30] assign _s2_pdata_raw_corrupt_T = s2_req_prio_0 ? io_pb_beat_corrupt_0 : io_rel_beat_corrupt_0; // @[SourceD.scala:48:7, :151:25, :162:30] assign s2_pdata_raw_corrupt = _s2_pdata_raw_corrupt_T; // @[SourceD.scala:157:26, :162:30] assign _io_pb_pop_valid_T = s2_valid_pb & s2_req_prio_0; // @[SourceD.scala:148:28, :151:25, :164:34] assign io_pb_pop_valid_0 = _io_pb_pop_valid_T; // @[SourceD.scala:48:7, :164:34] wire _io_rel_pop_valid_T = ~s2_req_prio_0; // @[SourceD.scala:151:25, :167:38] assign _io_rel_pop_valid_T_1 = s2_valid_pb & _io_rel_pop_valid_T; // @[SourceD.scala:148:28, :167:{35,38}] assign io_rel_pop_valid_0 = _io_rel_pop_valid_T_1; // @[SourceD.scala:48:7, :167:35] wire pb_ready = s2_req_prio_0 ? io_pb_pop_ready_0 : io_rel_pop_ready_0; // @[SourceD.scala:48:7, :151:25, :175:21] wire s3_latch = s2_valid & s3_ready; // @[SourceD.scala:75:22, :78:22, :177:18, :189:27] wire _s2_valid_T = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27] wire _s2_valid_T_1 = _s2_valid_T \| pb_ready; // @[SourceD.scala:175:21, :183:{27,40}] assign _s2_valid_T_2 = s2_full & _s2_valid_T_1; // @[SourceD.scala:147:24, :183:{23,40}] assign s2_valid = _s2_valid_T_2; // @[SourceD.scala:75:22, :183:23] wire _s2_ready_T = ~s2_full; // @[SourceD.scala:147:24, :184:15] wire _s2_ready_T_1 = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27, :184:41] wire _s2_ready_T_2 = _s2_ready_T_1 \| pb_ready; // @[SourceD.scala:175:21, :184:{41,54}] wire _s2_ready_T_3 = s3_ready & _s2_ready_T_2; // @[SourceD.scala:78:22, :184:{37,54}] assign _s2_ready_T_4 = _s2_ready_T \| _s2_ready_T_3; // @[SourceD.scala:184:{15,24,37}] assign s2_ready = _s2_ready_T_4; // @[SourceD.scala:77:22, :184:24] reg s3_full; // @[SourceD.scala:190:24] reg s3_valid_d; // @[SourceD.scala:191:27] assign d_valid = s3_valid_d; // @[SourceD.scala:191:27, :218:15] reg [1:0] s3_beat; // @[SourceD.scala:192:26] wire [1:0] pre_s3_beat = s3_latch ? s2_beat : s3_beat; // @[SourceD.scala:149:26, :189:27, :192:26, :319:24] reg [1:0] s3_bypass; // @[SourceD.scala:193:28] reg s3_req_prio_0; // @[SourceD.scala:194:25] reg s3_req_prio_1; // @[SourceD.scala:194:25] reg s3_req_prio_2; // @[SourceD.scala:194:25] reg s3_req_control; // @[SourceD.scala:194:25] reg [2:0] s3_req_opcode; // @[SourceD.scala:194:25] reg [2:0] s3_req_param; // @[SourceD.scala:194:25] reg [2:0] s3_req_size; // @[SourceD.scala:194:25] assign d_bits_size = s3_req_size; // @[SourceD.scala:194:25, :218:15] reg [7:0] s3_req_source; // @[SourceD.scala:194:25] assign d_bits_source = s3_req_source; // @[SourceD.scala:194:25, :218:15] reg [12:0] s3_req_tag; // @[SourceD.scala:194:25] reg [5:0] s3_req_offset; // @[SourceD.scala:194:25] reg [5:0] s3_req_put; // @[SourceD.scala:194:25] reg [9:0] s3_req_set; // @[SourceD.scala:194:25] reg [3:0] s3_req_sink; // @[SourceD.scala:194:25] assign d_bits_sink = s3_req_sink; // @[SourceD.scala:194:25, :218:15] reg [2:0] s3_req_way; // @[SourceD.scala:194:25] reg s3_req_bad; // @[SourceD.scala:194:25] assign d_bits_denied = s3_req_bad; // @[SourceD.scala:194:25, :218:15] wire pre_s3_req_prio_0 = s3_latch ? s2_req_prio_0 : s3_req_prio_0; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_prio_1 = s3_latch ? s2_req_prio_1 : s3_req_prio_1; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_prio_2 = s3_latch ? s2_req_prio_2 : s3_req_prio_2; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_control = s3_latch ? s2_req_control : s3_req_control; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_opcode = s3_latch ? s2_req_opcode : s3_req_opcode; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_param = s3_latch ? s2_req_param : s3_req_param; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_size = s3_latch ? s2_req_size : s3_req_size; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [7:0] pre_s3_req_source = s3_latch ? s2_req_source : s3_req_source; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [12:0] pre_s3_req_tag = s3_latch ? s2_req_tag : s3_req_tag; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_offset = s3_latch ? s2_req_offset : s3_req_offset; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_put = s3_latch ? s2_req_put : s3_req_put; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [9:0] pre_s3_req_set = s3_latch ? s2_req_set : s3_req_set; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [3:0] pre_s3_req_sink = s3_latch ? s2_req_sink : s3_req_sink; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_way = s3_latch ? s2_req_way : s3_req_way; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_bad = s3_latch ? s2_req_bad : s3_req_bad; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] s3_adjusted_opcode = s3_req_bad ? 3'h4 : s3_req_opcode; // @[SourceD.scala:194:25, :195:31] reg s3_last; // @[SourceD.scala:196:26] reg [127:0] s3_pdata_data; // @[SourceD.scala:197:27] reg [15:0] s3_pdata_mask; // @[SourceD.scala:197:27] reg s3_pdata_corrupt; // @[SourceD.scala:197:27] reg s3_need_pb; // @[SourceD.scala:198:29] reg s3_retires; // @[SourceD.scala:199:29] reg s3_need_r; // @[SourceD.scala:200:28] wire _s3_acq_T = s3_req_opcode == 3'h6; // @[SourceD.scala:194:25, :202:30] wire _s3_acq_T_1 = &s3_req_opcode; // @[SourceD.scala:194:25, :202:64] wire s3_acq = _s3_acq_T \| _s3_acq_T_1; // @[SourceD.scala:202:{30,47,64}] wire [127:0] _s3_bypass_data_T_26; // @[package.scala:45:27] wire [127:0] s3_bypass_data; // @[SourceD.scala:206:28] wire _s3_rdata_T = s3_bypass[0]; // @[SourceD.scala:193:28, :208:78] wire _s3_rdata_T_1 = s3_bypass[1]; // @[SourceD.scala:193:28, :208:78] wire [63:0] _s3_rdata_T_2 = s3_bypass_data[63:0]; // @[SourceD.scala:206:28, :207:78] wire [63:0] _s3_rdata_T_3 = s3_bypass_data[127:64]; // @[SourceD.scala:206:28, :207:78] wire [63:0] _s3_rdata_T_4 = _queue_io_deq_bits_data[63:0]; // @[SourceD.scala:120:21, :207:78] wire [63:0] _s3_rdata_T_5 = _queue_io_deq_bits_data[127:64]; // @[SourceD.scala:120:21, :207:78] wire [63:0] _s3_rdata_T_6 = _s3_rdata_T ? _s3_rdata_T_2 : _s3_rdata_T_4; // @[SourceD.scala:207:78, :208:78, :210:75] wire [63:0] _s3_rdata_T_7 = _s3_rdata_T_1 ? _s3_rdata_T_3 : _s3_rdata_T_5; // @[SourceD.scala:207:78, :208:78, :210:75] wire [127:0] s3_rdata = {_s3_rdata_T_7, _s3_rdata_T_6}; // @[package.scala:45:27] assign d_bits_data = s3_rdata; // @[package.scala:45:27] wire _grant_T = s3_req_param == 3'h2; // @[SourceD.scala:194:25, :214:32] wire [2:0] grant = {2'h2, ~_grant_T}; // @[SourceD.scala:214:{18,32}] wire [2:0] resp_opcode_6 = grant; // @[SourceD.scala:214:18, :215:28] assign io_d_valid_0 = d_valid; // @[SourceD.scala:48:7, :218:15] wire [2:0] _d_bits_opcode_T; // @[SourceD.scala:222:24] assign io_d_bits_opcode_0 = d_bits_opcode; // @[SourceD.scala:48:7, :218:15] wire [1:0] _d_bits_param_T_3; // @[SourceD.scala:223:24] assign io_d_bits_param_0 = d_bits_param; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_size_0 = d_bits_size; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_source_0 = d_bits_source; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_sink_0 = d_bits_sink; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_denied_0 = d_bits_denied; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_data_0 = d_bits_data; // @[SourceD.scala:48:7, :218:15] wire _d_bits_corrupt_T_1; // @[SourceD.scala:229:32] assign io_d_bits_corrupt_0 = d_bits_corrupt; // @[SourceD.scala:48:7, :218:15] wire [7:0][2:0] _GEN_0 = {{3'h4}, {resp_opcode_6}, {3'h2}, {3'h1}, {3'h1}, {3'h1}, {3'h0}, {3'h0}}; // @[SourceD.scala:215:28, :222:24] assign _d_bits_opcode_T = s3_req_prio_0 ? _GEN_0[s3_req_opcode] : 3'h6; // @[SourceD.scala:194:25, :222:24] assign d_bits_opcode = _d_bits_opcode_T; // @[SourceD.scala:218:15, :222:24] wire _d_bits_param_T = s3_req_prio_0 & s3_acq; // @[SourceD.scala:194:25, :202:47, :223:40] wire _d_bits_param_T_1 = \|s3_req_param; // @[SourceD.scala:194:25, :223:68] wire [1:0] _d_bits_param_T_2 = {1'h0, ~_d_bits_param_T_1}; // @[SourceD.scala:223:{54,68}] assign _d_bits_param_T_3 = _d_bits_param_T ? _d_bits_param_T_2 : 2'h0; // @[SourceD.scala:223:{24,40,54}] assign d_bits_param = _d_bits_param_T_3; // @[SourceD.scala:218:15, :223:24] wire _d_bits_corrupt_T = d_bits_opcode[0]; // @[SourceD.scala:218:15, :229:48] assign _d_bits_corrupt_T_1 = s3_req_bad & _d_bits_corrupt_T; // @[SourceD.scala:194:25, :229:{32,48}] assign d_bits_corrupt = _d_bits_corrupt_T_1; // @[SourceD.scala:218:15, :229:32] wire _queue_io_deq_ready_T = s3_valid & s4_ready; // @[SourceD.scala:76:22, :79:22, :231:34] wire _queue_io_deq_ready_T_1 = _queue_io_deq_ready_T & s3_need_r; // @[SourceD.scala:200:28, :231:{34,46}] wire _s3_valid_T = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27] wire _s3_valid_T_1 = _s3_valid_T \| d_ready; // @[SourceD.scala:218:15, :241:{27,39}] assign _s3_valid_T_2 = s3_full & _s3_valid_T_1; // @[SourceD.scala:190:24, :241:{23,39}] assign s3_valid = _s3_valid_T_2; // @[SourceD.scala:76:22, :241:23] wire _s3_ready_T = ~s3_full; // @[SourceD.scala:190:24, :232:11, :242:15] wire _s3_ready_T_1 = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27, :242:41] wire _s3_ready_T_2 = _s3_ready_T_1 \| d_ready; // @[SourceD.scala:218:15, :242:{41,53}] wire _s3_ready_T_3 = s4_ready & _s3_ready_T_2; // @[SourceD.scala:79:22, :242:{37,53}] assign _s3_ready_T_4 = _s3_ready_T \| _s3_ready_T_3; // @[SourceD.scala:242:{15,24,37}] assign s3_ready = _s3_ready_T_4; // @[SourceD.scala:78:22, :242:24] wire _s4_latch_T = s3_valid & s3_retires; // @[SourceD.scala:76:22, :199:29, :247:27] wire s4_latch = _s4_latch_T & s4_ready; // @[SourceD.scala:79:22, :247:{27,41}] reg s4_full; // @[SourceD.scala:248:24] reg [1:0] s4_beat; // @[SourceD.scala:249:26] assign io_bs_wadr_bits_beat_0 = s4_beat; // @[SourceD.scala:48:7, :249:26] wire [1:0] pre_s4_beat = s4_latch ? s3_beat : s4_beat; // @[SourceD.scala:192:26, :247:41, :249:26, :320:24] reg s4_need_r; // @[SourceD.scala:250:28] reg s4_need_bs; // @[SourceD.scala:251:29] reg s4_need_pb; // @[SourceD.scala:252:29] reg s4_req_prio_0; // @[SourceD.scala:253:25] reg s4_req_prio_1; // @[SourceD.scala:253:25] reg s4_req_prio_2; // @[SourceD.scala:253:25] reg s4_req_control; // @[SourceD.scala:253:25] reg [2:0] s4_req_opcode; // @[SourceD.scala:253:25] reg [2:0] s4_req_param; // @[SourceD.scala:253:25] reg [2:0] s4_req_size; // @[SourceD.scala:253:25] reg [7:0] s4_req_source; // @[SourceD.scala:253:25] reg [12:0] s4_req_tag; // @[SourceD.scala:253:25] reg [5:0] s4_req_offset; // @[SourceD.scala:253:25] reg [5:0] s4_req_put; // @[SourceD.scala:253:25] reg [9:0] s4_req_set; // @[SourceD.scala:253:25] assign io_bs_wadr_bits_set_0 = s4_req_set; // @[SourceD.scala:48:7, :253:25] reg [3:0] s4_req_sink; // @[SourceD.scala:253:25] reg [2:0] s4_req_way; // @[SourceD.scala:253:25] assign io_bs_wadr_bits_way_0 = s4_req_way; // @[SourceD.scala:48:7, :253:25] reg s4_req_bad; // @[SourceD.scala:253:25] wire pre_s4_req_prio_0 = s4_latch ? s3_req_prio_0 : s4_req_prio_0; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_prio_1 = s4_latch ? s3_req_prio_1 : s4_req_prio_1; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_prio_2 = s4_latch ? s3_req_prio_2 : s4_req_prio_2; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_control = s4_latch ? s3_req_control : s4_req_control; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_opcode = s4_latch ? s3_req_opcode : s4_req_opcode; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_param = s4_latch ? s3_req_param : s4_req_param; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_size = s4_latch ? s3_req_size : s4_req_size; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [7:0] pre_s4_req_source = s4_latch ? s3_req_source : s4_req_source; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [12:0] pre_s4_req_tag = s4_latch ? s3_req_tag : s4_req_tag; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_offset = s4_latch ? s3_req_offset : s4_req_offset; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_put = s4_latch ? s3_req_put : s4_req_put; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [9:0] pre_s4_req_set = s4_latch ? s3_req_set : s4_req_set; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [3:0] pre_s4_req_sink = s4_latch ? s3_req_sink : s4_req_sink; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_way = s4_latch ? s3_req_way : s4_req_way; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_bad = s4_latch ? s3_req_bad : s4_req_bad; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] reg [2:0] s4_adjusted_opcode; // @[SourceD.scala:254:37] reg [127:0] s4_pdata_data; // @[SourceD.scala:255:27] reg [15:0] s4_pdata_mask; // @[SourceD.scala:255:27] reg s4_pdata_corrupt; // @[SourceD.scala:255:27] reg [127:0] s4_rdata; // @[SourceD.scala:256:27] assign _io_bs_wadr_valid_T = s4_full & s4_need_bs; // @[SourceD.scala:248:24, :251:29, :270:31] assign io_bs_wadr_valid_0 = _io_bs_wadr_valid_T; // @[SourceD.scala:48:7, :270:31] wire _io_bs_wadr_bits_mask_T = s4_pdata_mask[0]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_1 = s4_pdata_mask[1]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_2 = s4_pdata_mask[2]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_3 = s4_pdata_mask[3]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_4 = s4_pdata_mask[4]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_5 = s4_pdata_mask[5]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_6 = s4_pdata_mask[6]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_7 = s4_pdata_mask[7]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_8 = s4_pdata_mask[8]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_9 = s4_pdata_mask[9]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_10 = s4_pdata_mask[10]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_11 = s4_pdata_mask[11]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_12 = s4_pdata_mask[12]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_13 = s4_pdata_mask[13]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_14 = s4_pdata_mask[14]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_15 = s4_pdata_mask[15]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_16 = _io_bs_wadr_bits_mask_T \| _io_bs_wadr_bits_mask_T_1; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_17 = _io_bs_wadr_bits_mask_T_16 \| _io_bs_wadr_bits_mask_T_2; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_18 = _io_bs_wadr_bits_mask_T_17 \| _io_bs_wadr_bits_mask_T_3; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_19 = _io_bs_wadr_bits_mask_T_18 \| _io_bs_wadr_bits_mask_T_4; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_20 = _io_bs_wadr_bits_mask_T_19 \| _io_bs_wadr_bits_mask_T_5; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_21 = _io_bs_wadr_bits_mask_T_20 \| _io_bs_wadr_bits_mask_T_6; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_22 = _io_bs_wadr_bits_mask_T_21 \| _io_bs_wadr_bits_mask_T_7; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_23 = _io_bs_wadr_bits_mask_T_8 \| _io_bs_wadr_bits_mask_T_9; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_24 = _io_bs_wadr_bits_mask_T_23 \| _io_bs_wadr_bits_mask_T_10; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_25 = _io_bs_wadr_bits_mask_T_24 \| _io_bs_wadr_bits_mask_T_11; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_26 = _io_bs_wadr_bits_mask_T_25 \| _io_bs_wadr_bits_mask_T_12; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_27 = _io_bs_wadr_bits_mask_T_26 \| _io_bs_wadr_bits_mask_T_13; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_28 = _io_bs_wadr_bits_mask_T_27 \| _io_bs_wadr_bits_mask_T_14; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_29 = _io_bs_wadr_bits_mask_T_28 \| _io_bs_wadr_bits_mask_T_15; // @[SourceD.scala:275:{45,87}] assign _io_bs_wadr_bits_mask_T_30 = {_io_bs_wadr_bits_mask_T_29, _io_bs_wadr_bits_mask_T_22}; // @[SourceD.scala:275:{30,87}] assign io_bs_wadr_bits_mask_0 = _io_bs_wadr_bits_mask_T_30; // @[SourceD.scala:48:7, :275:30]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_213( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_389 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) \|\| flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask \| lo_mask)(n-1,0) } } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire \|\| !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v4.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v4.common._ import boom.v4.util._ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val grant = Input(Bool()) val iss_uop = Output(new MicroOp()) val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val squash_grant = Input(Bool()) val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val child_rebusys = Input(UInt(aluWidth.W)) } class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters) extends BoomModule { val io = IO(new IssueSlotIO(numWakeupPorts)) val slot_valid = RegInit(false.B) val slot_uop = Reg(new MicroOp()) val next_valid = WireInit(slot_valid) val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop)) val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop) io.valid := slot_valid io.out_uop := next_uop io.will_be_valid := next_valid && !killed when (io.kill) { slot_valid := false.B } .elsewhen (io.in_uop.valid) { slot_valid := true.B } .elsewhen (io.clear) { slot_valid := false.B } .otherwise { slot_valid := next_valid && !killed } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (!slot_valid \|\| io.clear \|\| io.kill) } .otherwise { slot_uop := next_uop } // Wakeups next_uop.iw_p1_bypass_hint := false.B next_uop.iw_p2_bypass_hint := false.B next_uop.iw_p3_bypass_hint := false.B next_uop.iw_p1_speculative_child := 0.U next_uop.iw_p2_speculative_child := 0.U val rebusied_prs1 = WireInit(false.B) val rebusied_prs2 = WireInit(false.B) val rebusied = rebusied_prs1 \|\| rebusied_prs2 val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 } val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 } val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 } val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m } val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m } val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m } val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m } val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m } val bypassables = io.wakeup_ports.map { w => w.bits.bypassable } val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask } when (prs1_wakeups.reduce(_\|\|_)) { next_uop.prs1_busy := false.B next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks) next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables) } when ((prs1_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) && slot_uop.lrs1_rtype === RT_FIX) { next_uop.prs1_busy := true.B rebusied_prs1 := true.B } when (prs2_wakeups.reduce(_\|\|_)) { next_uop.prs2_busy := false.B next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks) next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables) } when ((prs2_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) && slot_uop.lrs2_rtype === RT_FIX) { next_uop.prs2_busy := true.B rebusied_prs2 := true.B } when (prs3_wakeups.reduce(_\|\|_)) { next_uop.prs3_busy := false.B next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables) } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) { next_uop.ppred_busy := false.B } val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B) val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) io.request := slot_valid && !slot_uop.iw_issued && ( iss_ready \|\| agen_ready \|\| dgen_ready ) io.iss_uop := slot_uop // Update state for current micro-op based on grant next_uop.iw_issued := false.B next_uop.iw_issued_partial_agen := false.B next_uop.iw_issued_partial_dgen := false.B when (io.grant && !io.squash_grant) { next_uop.iw_issued := true.B } if (isMem) { when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) { when (agen_ready) { // Issue the AGEN, next slot entry is a DGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_agen := true.B } io.iss_uop.fu_code(FC_AGEN) := true.B io.iss_uop.fu_code(FC_DGEN) := false.B } .otherwise { // Issue the DGEN, next slot entry is the AGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_dgen := true.B } io.iss_uop.fu_code(FC_AGEN) := false.B io.iss_uop.fu_code(FC_DGEN) := true.B io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } } .elsewhen (slot_uop.fu_code(FC_DGEN)) { io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } io.iss_uop.lrs2_rtype := RT_X io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE } when (slot_valid && slot_uop.iw_issued) { next_valid := rebusied if (isMem) { when (slot_uop.iw_issued_partial_agen) { next_valid := true.B when (!rebusied_prs1) { next_uop.fu_code(FC_AGEN) := false.B next_uop.fu_code(FC_DGEN) := true.B } } .elsewhen (slot_uop.iw_issued_partial_dgen) { next_valid := true.B when (!rebusied_prs2) { next_uop.fu_code(FC_AGEN) := true.B next_uop.fu_code(FC_DGEN) := false.B } } } } }	module IssueSlot_29( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [11:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [11:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [1:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [11:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire [1:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [1:0] io_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-slot.scala:49:7] wire [1:0] _next_uop_iw_p1_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _next_uop_iw_p2_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [1:0] io_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire [1:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [1:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [11:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [5:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [3:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [3:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [11:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [11:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [1:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [1:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [1:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [11:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [5:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [3:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [3:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [11:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_ppred_busy = next_uop_out_ppred_busy; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [11:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [11:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = \|_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 \| io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to the following Chisel files. File ShiftRegisterPriorityQueue.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ // TODO : support enq & deq at the same cycle class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle { val output_prev = KeyValue(keyWidth, value) val output_nxt = KeyValue(keyWidth, value) val input_prev = Flipped(KeyValue(keyWidth, value)) val input_nxt = Flipped(KeyValue(keyWidth, value)) val cmd = Flipped(Valid(UInt(1.W))) val insert_here = Input(Bool()) val cur_input_keyval = Flipped(KeyValue(keyWidth, value)) val cur_output_keyval = KeyValue(keyWidth, value) } class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module { val io = IO(new PriorityQueueStageIO(keyWidth, value)) dontTouch(io) val CMD_DEQ = 0.U val CMD_ENQ = 1.U val MAX_VALUE = (1 << keyWidth) - 1 val key_reg = RegInit(MAX_VALUE.U(keyWidth.W)) val value_reg = Reg(value) io.output_prev.key := key_reg io.output_prev.value := value_reg io.output_nxt.key := key_reg io.output_nxt.value := value_reg io.cur_output_keyval.key := key_reg io.cur_output_keyval.value := value_reg when (io.cmd.valid) { switch (io.cmd.bits) { is (CMD_DEQ) { key_reg := io.input_nxt.key value_reg := io.input_nxt.value } is (CMD_ENQ) { when (io.insert_here) { key_reg := io.cur_input_keyval.key value_reg := io.cur_input_keyval.value } .elsewhen (key_reg >= io.cur_input_keyval.key) { key_reg := io.input_prev.key value_reg := io.input_prev.value } .otherwise { // do nothing } } } } } object PriorityQueueStage { def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v) } // TODO // - This design is not scalable as the enqued_keyval is broadcasted to all the stages // - Add pipeline registers later class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle { val cnt_bits = log2Ceil(queSize+1) val counter = Output(UInt(cnt_bits.W)) val enq = Flipped(Decoupled(KeyValue(keyWidth, value))) val deq = Decoupled(KeyValue(keyWidth, value)) } class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module { val keyWidthInternal = keyWidth + 1 val CMD_DEQ = 0.U val CMD_ENQ = 1.U val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value)) dontTouch(io) val MAX_VALUE = ((1 << keyWidthInternal) - 1).U val cnt_bits = log2Ceil(queSize+1) // do not consider cases where we are inserting more entries then the queSize val counter = RegInit(0.U(cnt_bits.W)) io.counter := counter val full = (counter === queSize.U) val empty = (counter === 0.U) io.deq.valid := !empty io.enq.ready := !full when (io.enq.fire) { counter := counter + 1.U } when (io.deq.fire) { counter := counter - 1.U } val cmd_valid = io.enq.valid \|\| io.deq.ready val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ) assert(!(io.enq.valid && io.deq.ready)) val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value))) for (i <- 0 until (queSize - 1)) { stages(i+1).io.input_prev <> stages(i).io.output_nxt stages(i).io.input_nxt <> stages(i+1).io.output_prev } stages(queSize-1).io.input_nxt.key := MAX_VALUE // stages(queSize-1).io.input_nxt.value := stages(queSize-1).io.input_nxt.value.symbol := 0.U // stages(queSize-1).io.input_nxt.value.child(0) := 0.U // stages(queSize-1).io.input_nxt.value.child(1) := 0.U stages(0).io.input_prev.key := io.enq.bits.key stages(0).io.input_prev.value <> io.enq.bits.value for (i <- 0 until queSize) { stages(i).io.cmd.valid := cmd_valid stages(i).io.cmd.bits := cmd stages(i).io.cur_input_keyval <> io.enq.bits } val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B))) for (i <- 0 until queSize) { is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key) } val is_large_or_equal_cat = Wire(UInt(queSize.W)) is_large_or_equal_cat := Cat(is_large_or_equal.reverse) val insert_here_idx = PriorityEncoder(is_large_or_equal_cat) for (i <- 0 until queSize) { when (i.U === insert_here_idx) { stages(i).io.insert_here := true.B } .otherwise { stages(i).io.insert_here := false.B } } io.deq.bits <> stages(0).io.output_prev }	module PriorityQueueStage_38( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module MacUnit_50( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_17( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_26 = _source_ok_T_25 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_29 = source_ok_uncommonBits_4 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h23; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_39 = _source_ok_T_38 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_40 = _source_ok_T_39 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_40 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_41 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_42 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_48 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_54 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_60 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_66 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_43 = _source_ok_T_42 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_49 = _source_ok_T_48 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_53; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_55 = _source_ok_T_54 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_61 = _source_ok_T_60 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_65; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_67 = _source_ok_T_66 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = source_ok_uncommonBits_9 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_71 = _source_ok_T_69 & _source_ok_T_70; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_5 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = io_in_d_bits_source_0 == 7'h23; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_78 = _source_ok_T_77 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_79 = _source_ok_T_78 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_80 = _source_ok_T_79 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_81 = _source_ok_T_80 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_81 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1610 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1610; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1610; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1683 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1683; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1683; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1683; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [519:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1536 = _T_1610 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1536 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1536 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1536 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1536 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1536 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1582 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1582 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1551 = _T_1683 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1551 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1551 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1551 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [519:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1654 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1654 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1636 = _T_1683 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1636 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1636 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1636 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_2( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_2 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RecFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import consts._ class RecFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val in = Input(Bits((inExpWidth + inSigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in); if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- io.out := io.in<<(outSigWidth - inSigWidth) io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W) } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( inExpWidth, inSigWidth, outExpWidth, outSigWidth, flRoundOpt_sigMSBitAlwaysZero )) roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn) roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := rawIn roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } } File rawFloatFromRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ /---------------------------------------------------------------------------- \| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be \| set. ----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }	module RecFNToRecFN_28( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncQueueSource_TLBundleA_a32d64s2k3z4c( // @[AsyncQueue.scala:70:7] input clock, // @[AsyncQueue.scala:70:7] input reset, // @[AsyncQueue.scala:70:7] output io_enq_ready, // @[AsyncQueue.scala:73:14] input io_enq_valid, // @[AsyncQueue.scala:73:14] input [2:0] io_enq_bits_opcode, // @[AsyncQueue.scala:73:14] input [2:0] io_enq_bits_param, // @[AsyncQueue.scala:73:14] input [3:0] io_enq_bits_size, // @[AsyncQueue.scala:73:14] input [1:0] io_enq_bits_source, // @[AsyncQueue.scala:73:14] input [31:0] io_enq_bits_address, // @[AsyncQueue.scala:73:14] input [7:0] io_enq_bits_mask, // @[AsyncQueue.scala:73:14] input [63:0] io_enq_bits_data, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_0_opcode, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_0_param, // @[AsyncQueue.scala:73:14] output [3:0] io_async_mem_0_size, // @[AsyncQueue.scala:73:14] output [1:0] io_async_mem_0_source, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_0_address, // @[AsyncQueue.scala:73:14] output [7:0] io_async_mem_0_mask, // @[AsyncQueue.scala:73:14] output [63:0] io_async_mem_0_data, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_1_opcode, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_1_param, // @[AsyncQueue.scala:73:14] output [3:0] io_async_mem_1_size, // @[AsyncQueue.scala:73:14] output [1:0] io_async_mem_1_source, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_1_address, // @[AsyncQueue.scala:73:14] output [7:0] io_async_mem_1_mask, // @[AsyncQueue.scala:73:14] output [63:0] io_async_mem_1_data, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_2_opcode, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_2_param, // @[AsyncQueue.scala:73:14] output [3:0] io_async_mem_2_size, // @[AsyncQueue.scala:73:14] output [1:0] io_async_mem_2_source, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_2_address, // @[AsyncQueue.scala:73:14] output [7:0] io_async_mem_2_mask, // @[AsyncQueue.scala:73:14] output [63:0] io_async_mem_2_data, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_3_opcode, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_3_param, // @[AsyncQueue.scala:73:14] output [3:0] io_async_mem_3_size, // @[AsyncQueue.scala:73:14] output [1:0] io_async_mem_3_source, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_3_address, // @[AsyncQueue.scala:73:14] output [7:0] io_async_mem_3_mask, // @[AsyncQueue.scala:73:14] output [63:0] io_async_mem_3_data, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_4_opcode, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_4_param, // @[AsyncQueue.scala:73:14] output [3:0] io_async_mem_4_size, // @[AsyncQueue.scala:73:14] output [1:0] io_async_mem_4_source, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_4_address, // @[AsyncQueue.scala:73:14] output [7:0] io_async_mem_4_mask, // @[AsyncQueue.scala:73:14] output [63:0] io_async_mem_4_data, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_5_opcode, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_5_param, // @[AsyncQueue.scala:73:14] output [3:0] io_async_mem_5_size, // @[AsyncQueue.scala:73:14] output [1:0] io_async_mem_5_source, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_5_address, // @[AsyncQueue.scala:73:14] output [7:0] io_async_mem_5_mask, // @[AsyncQueue.scala:73:14] output [63:0] io_async_mem_5_data, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_6_opcode, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_6_param, // @[AsyncQueue.scala:73:14] output [3:0] io_async_mem_6_size, // @[AsyncQueue.scala:73:14] output [1:0] io_async_mem_6_source, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_6_address, // @[AsyncQueue.scala:73:14] output [7:0] io_async_mem_6_mask, // @[AsyncQueue.scala:73:14] output [63:0] io_async_mem_6_data, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_7_opcode, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_7_param, // @[AsyncQueue.scala:73:14] output [3:0] io_async_mem_7_size, // @[AsyncQueue.scala:73:14] output [1:0] io_async_mem_7_source, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_7_address, // @[AsyncQueue.scala:73:14] output [7:0] io_async_mem_7_mask, // @[AsyncQueue.scala:73:14] output [63:0] io_async_mem_7_data, // @[AsyncQueue.scala:73:14] input [3:0] io_async_ridx, // @[AsyncQueue.scala:73:14] output [3:0] io_async_widx, // @[AsyncQueue.scala:73:14] input io_async_safe_ridx_valid, // @[AsyncQueue.scala:73:14] output io_async_safe_widx_valid, // @[AsyncQueue.scala:73:14] output io_async_safe_source_reset_n, // @[AsyncQueue.scala:73:14] input io_async_safe_sink_reset_n // @[AsyncQueue.scala:73:14] ); wire _sink_extend_io_out; // @[AsyncQueue.scala:105:30] wire _source_valid_0_io_out; // @[AsyncQueue.scala:102:32] wire io_enq_valid_0 = io_enq_valid; // @[AsyncQueue.scala:70:7] wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[AsyncQueue.scala:70:7] wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[AsyncQueue.scala:70:7] wire [3:0] io_enq_bits_size_0 = io_enq_bits_size; // @[AsyncQueue.scala:70:7] wire [1:0] io_enq_bits_source_0 = io_enq_bits_source; // @[AsyncQueue.scala:70:7] wire [31:0] io_enq_bits_address_0 = io_enq_bits_address; // @[AsyncQueue.scala:70:7] wire [7:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[AsyncQueue.scala:70:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[AsyncQueue.scala:70:7] wire [3:0] io_async_ridx_0 = io_async_ridx; // @[AsyncQueue.scala:70:7] wire io_async_safe_ridx_valid_0 = io_async_safe_ridx_valid; // @[AsyncQueue.scala:70:7] wire io_async_safe_sink_reset_n_0 = io_async_safe_sink_reset_n; // @[AsyncQueue.scala:70:7] wire _widx_T = reset; // @[AsyncQueue.scala:83:30] wire _ready_reg_T = reset; // @[AsyncQueue.scala:90:35] wire _widx_reg_T = reset; // @[AsyncQueue.scala:93:34] wire _source_valid_0_reset_T = reset; // @[AsyncQueue.scala:107:36] wire _source_valid_1_reset_T = reset; // @[AsyncQueue.scala:108:36] wire _sink_extend_reset_T = reset; // @[AsyncQueue.scala:109:36] wire _sink_valid_reset_T = reset; // @[AsyncQueue.scala:110:35] wire _io_async_safe_source_reset_n_T = reset; // @[AsyncQueue.scala:123:34] wire io_enq_bits_corrupt = 1'h0; // @[AsyncQueue.scala:70:7] wire io_async_mem_0_corrupt = 1'h0; // @[AsyncQueue.scala:70:7] wire io_async_mem_1_corrupt = 1'h0; // @[AsyncQueue.scala:70:7] wire io_async_mem_2_corrupt = 1'h0; // @[AsyncQueue.scala:70:7] wire io_async_mem_3_corrupt = 1'h0; // @[AsyncQueue.scala:70:7] wire io_async_mem_4_corrupt = 1'h0; // @[AsyncQueue.scala:70:7] wire io_async_mem_5_corrupt = 1'h0; // @[AsyncQueue.scala:70:7] wire io_async_mem_6_corrupt = 1'h0; // @[AsyncQueue.scala:70:7] wire io_async_mem_7_corrupt = 1'h0; // @[AsyncQueue.scala:70:7] wire _io_enq_ready_T; // @[AsyncQueue.scala:91:29] wire _io_async_safe_source_reset_n_T_1; // @[AsyncQueue.scala:123:27] wire io_enq_ready_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_0_opcode_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_0_param_0; // @[AsyncQueue.scala:70:7] wire [3:0] io_async_mem_0_size_0; // @[AsyncQueue.scala:70:7] wire [1:0] io_async_mem_0_source_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_0_address_0; // @[AsyncQueue.scala:70:7] wire [7:0] io_async_mem_0_mask_0; // @[AsyncQueue.scala:70:7] wire [63:0] io_async_mem_0_data_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_1_opcode_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_1_param_0; // @[AsyncQueue.scala:70:7] wire [3:0] io_async_mem_1_size_0; // @[AsyncQueue.scala:70:7] wire [1:0] io_async_mem_1_source_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_1_address_0; // @[AsyncQueue.scala:70:7] wire [7:0] io_async_mem_1_mask_0; // @[AsyncQueue.scala:70:7] wire [63:0] io_async_mem_1_data_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_2_opcode_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_2_param_0; // @[AsyncQueue.scala:70:7] wire [3:0] io_async_mem_2_size_0; // @[AsyncQueue.scala:70:7] wire [1:0] io_async_mem_2_source_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_2_address_0; // @[AsyncQueue.scala:70:7] wire [7:0] io_async_mem_2_mask_0; // @[AsyncQueue.scala:70:7] wire [63:0] io_async_mem_2_data_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_3_opcode_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_3_param_0; // @[AsyncQueue.scala:70:7] wire [3:0] io_async_mem_3_size_0; // @[AsyncQueue.scala:70:7] wire [1:0] io_async_mem_3_source_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_3_address_0; // @[AsyncQueue.scala:70:7] wire [7:0] io_async_mem_3_mask_0; // @[AsyncQueue.scala:70:7] wire [63:0] io_async_mem_3_data_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_4_opcode_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_4_param_0; // @[AsyncQueue.scala:70:7] wire [3:0] io_async_mem_4_size_0; // @[AsyncQueue.scala:70:7] wire [1:0] io_async_mem_4_source_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_4_address_0; // @[AsyncQueue.scala:70:7] wire [7:0] io_async_mem_4_mask_0; // @[AsyncQueue.scala:70:7] wire [63:0] io_async_mem_4_data_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_5_opcode_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_5_param_0; // @[AsyncQueue.scala:70:7] wire [3:0] io_async_mem_5_size_0; // @[AsyncQueue.scala:70:7] wire [1:0] io_async_mem_5_source_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_5_address_0; // @[AsyncQueue.scala:70:7] wire [7:0] io_async_mem_5_mask_0; // @[AsyncQueue.scala:70:7] wire [63:0] io_async_mem_5_data_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_6_opcode_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_6_param_0; // @[AsyncQueue.scala:70:7] wire [3:0] io_async_mem_6_size_0; // @[AsyncQueue.scala:70:7] wire [1:0] io_async_mem_6_source_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_6_address_0; // @[AsyncQueue.scala:70:7] wire [7:0] io_async_mem_6_mask_0; // @[AsyncQueue.scala:70:7] wire [63:0] io_async_mem_6_data_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_7_opcode_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_7_param_0; // @[AsyncQueue.scala:70:7] wire [3:0] io_async_mem_7_size_0; // @[AsyncQueue.scala:70:7] wire [1:0] io_async_mem_7_source_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_7_address_0; // @[AsyncQueue.scala:70:7] wire [7:0] io_async_mem_7_mask_0; // @[AsyncQueue.scala:70:7] wire [63:0] io_async_mem_7_data_0; // @[AsyncQueue.scala:70:7] wire io_async_safe_widx_valid_0; // @[AsyncQueue.scala:70:7] wire io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:70:7] wire [3:0] io_async_widx_0; // @[AsyncQueue.scala:70:7] wire sink_ready; // @[AsyncQueue.scala:81:28] reg [2:0] mem_0_opcode; // @[AsyncQueue.scala:82:16] assign io_async_mem_0_opcode_0 = mem_0_opcode; // @[AsyncQueue.scala:70:7, :82:16] reg [2:0] mem_0_param; // @[AsyncQueue.scala:82:16] assign io_async_mem_0_param_0 = mem_0_param; // @[AsyncQueue.scala:70:7, :82:16] reg [3:0] mem_0_size; // @[AsyncQueue.scala:82:16] assign io_async_mem_0_size_0 = mem_0_size; // @[AsyncQueue.scala:70:7, :82:16] reg [1:0] mem_0_source; // @[AsyncQueue.scala:82:16] assign io_async_mem_0_source_0 = mem_0_source; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_0_address; // @[AsyncQueue.scala:82:16] assign io_async_mem_0_address_0 = mem_0_address; // @[AsyncQueue.scala:70:7, :82:16] reg [7:0] mem_0_mask; // @[AsyncQueue.scala:82:16] assign io_async_mem_0_mask_0 = mem_0_mask; // @[AsyncQueue.scala:70:7, :82:16] reg [63:0] mem_0_data; // @[AsyncQueue.scala:82:16] assign io_async_mem_0_data_0 = mem_0_data; // @[AsyncQueue.scala:70:7, :82:16] reg [2:0] mem_1_opcode; // @[AsyncQueue.scala:82:16] assign io_async_mem_1_opcode_0 = mem_1_opcode; // @[AsyncQueue.scala:70:7, :82:16] reg [2:0] mem_1_param; // @[AsyncQueue.scala:82:16] assign io_async_mem_1_param_0 = mem_1_param; // @[AsyncQueue.scala:70:7, :82:16] reg [3:0] mem_1_size; // @[AsyncQueue.scala:82:16] assign io_async_mem_1_size_0 = mem_1_size; // @[AsyncQueue.scala:70:7, :82:16] reg [1:0] mem_1_source; // @[AsyncQueue.scala:82:16] assign io_async_mem_1_source_0 = mem_1_source; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_1_address; // @[AsyncQueue.scala:82:16] assign io_async_mem_1_address_0 = mem_1_address; // @[AsyncQueue.scala:70:7, :82:16] reg [7:0] mem_1_mask; // @[AsyncQueue.scala:82:16] assign io_async_mem_1_mask_0 = mem_1_mask; // @[AsyncQueue.scala:70:7, :82:16] reg [63:0] mem_1_data; // @[AsyncQueue.scala:82:16] assign io_async_mem_1_data_0 = mem_1_data; // @[AsyncQueue.scala:70:7, :82:16] reg [2:0] mem_2_opcode; // @[AsyncQueue.scala:82:16] assign io_async_mem_2_opcode_0 = mem_2_opcode; // @[AsyncQueue.scala:70:7, :82:16] reg [2:0] mem_2_param; // @[AsyncQueue.scala:82:16] assign io_async_mem_2_param_0 = mem_2_param; // @[AsyncQueue.scala:70:7, :82:16] reg [3:0] mem_2_size; // @[AsyncQueue.scala:82:16] assign io_async_mem_2_size_0 = mem_2_size; // @[AsyncQueue.scala:70:7, :82:16] reg [1:0] mem_2_source; // @[AsyncQueue.scala:82:16] assign io_async_mem_2_source_0 = mem_2_source; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_2_address; // @[AsyncQueue.scala:82:16] assign io_async_mem_2_address_0 = mem_2_address; // @[AsyncQueue.scala:70:7, :82:16] reg [7:0] mem_2_mask; // @[AsyncQueue.scala:82:16] assign io_async_mem_2_mask_0 = mem_2_mask; // @[AsyncQueue.scala:70:7, :82:16] reg [63:0] mem_2_data; // @[AsyncQueue.scala:82:16] assign io_async_mem_2_data_0 = mem_2_data; // @[AsyncQueue.scala:70:7, :82:16] reg [2:0] mem_3_opcode; // @[AsyncQueue.scala:82:16] assign io_async_mem_3_opcode_0 = mem_3_opcode; // @[AsyncQueue.scala:70:7, :82:16] reg [2:0] mem_3_param; // @[AsyncQueue.scala:82:16] assign io_async_mem_3_param_0 = mem_3_param; // @[AsyncQueue.scala:70:7, :82:16] reg [3:0] mem_3_size; // @[AsyncQueue.scala:82:16] assign io_async_mem_3_size_0 = mem_3_size; // @[AsyncQueue.scala:70:7, :82:16] reg [1:0] mem_3_source; // @[AsyncQueue.scala:82:16] assign io_async_mem_3_source_0 = mem_3_source; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_3_address; // @[AsyncQueue.scala:82:16] assign io_async_mem_3_address_0 = mem_3_address; // @[AsyncQueue.scala:70:7, :82:16] reg [7:0] mem_3_mask; // @[AsyncQueue.scala:82:16] assign io_async_mem_3_mask_0 = mem_3_mask; // @[AsyncQueue.scala:70:7, :82:16] reg [63:0] mem_3_data; // @[AsyncQueue.scala:82:16] assign io_async_mem_3_data_0 = mem_3_data; // @[AsyncQueue.scala:70:7, :82:16] reg [2:0] mem_4_opcode; // @[AsyncQueue.scala:82:16] assign io_async_mem_4_opcode_0 = mem_4_opcode; // @[AsyncQueue.scala:70:7, :82:16] reg [2:0] mem_4_param; // @[AsyncQueue.scala:82:16] assign io_async_mem_4_param_0 = mem_4_param; // @[AsyncQueue.scala:70:7, :82:16] reg [3:0] mem_4_size; // @[AsyncQueue.scala:82:16] assign io_async_mem_4_size_0 = mem_4_size; // @[AsyncQueue.scala:70:7, :82:16] reg [1:0] mem_4_source; // @[AsyncQueue.scala:82:16] assign io_async_mem_4_source_0 = mem_4_source; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_4_address; // @[AsyncQueue.scala:82:16] assign io_async_mem_4_address_0 = mem_4_address; // @[AsyncQueue.scala:70:7, :82:16] reg [7:0] mem_4_mask; // @[AsyncQueue.scala:82:16] assign io_async_mem_4_mask_0 = mem_4_mask; // @[AsyncQueue.scala:70:7, :82:16] reg [63:0] mem_4_data; // @[AsyncQueue.scala:82:16] assign io_async_mem_4_data_0 = mem_4_data; // @[AsyncQueue.scala:70:7, :82:16] reg [2:0] mem_5_opcode; // @[AsyncQueue.scala:82:16] assign io_async_mem_5_opcode_0 = mem_5_opcode; // @[AsyncQueue.scala:70:7, :82:16] reg [2:0] mem_5_param; // @[AsyncQueue.scala:82:16] assign io_async_mem_5_param_0 = mem_5_param; // @[AsyncQueue.scala:70:7, :82:16] reg [3:0] mem_5_size; // @[AsyncQueue.scala:82:16] assign io_async_mem_5_size_0 = mem_5_size; // @[AsyncQueue.scala:70:7, :82:16] reg [1:0] mem_5_source; // @[AsyncQueue.scala:82:16] assign io_async_mem_5_source_0 = mem_5_source; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_5_address; // @[AsyncQueue.scala:82:16] assign io_async_mem_5_address_0 = mem_5_address; // @[AsyncQueue.scala:70:7, :82:16] reg [7:0] mem_5_mask; // @[AsyncQueue.scala:82:16] assign io_async_mem_5_mask_0 = mem_5_mask; // @[AsyncQueue.scala:70:7, :82:16] reg [63:0] mem_5_data; // @[AsyncQueue.scala:82:16] assign io_async_mem_5_data_0 = mem_5_data; // @[AsyncQueue.scala:70:7, :82:16] reg [2:0] mem_6_opcode; // @[AsyncQueue.scala:82:16] assign io_async_mem_6_opcode_0 = mem_6_opcode; // @[AsyncQueue.scala:70:7, :82:16] reg [2:0] mem_6_param; // @[AsyncQueue.scala:82:16] assign io_async_mem_6_param_0 = mem_6_param; // @[AsyncQueue.scala:70:7, :82:16] reg [3:0] mem_6_size; // @[AsyncQueue.scala:82:16] assign io_async_mem_6_size_0 = mem_6_size; // @[AsyncQueue.scala:70:7, :82:16] reg [1:0] mem_6_source; // @[AsyncQueue.scala:82:16] assign io_async_mem_6_source_0 = mem_6_source; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_6_address; // @[AsyncQueue.scala:82:16] assign io_async_mem_6_address_0 = mem_6_address; // @[AsyncQueue.scala:70:7, :82:16] reg [7:0] mem_6_mask; // @[AsyncQueue.scala:82:16] assign io_async_mem_6_mask_0 = mem_6_mask; // @[AsyncQueue.scala:70:7, :82:16] reg [63:0] mem_6_data; // @[AsyncQueue.scala:82:16] assign io_async_mem_6_data_0 = mem_6_data; // @[AsyncQueue.scala:70:7, :82:16] reg [2:0] mem_7_opcode; // @[AsyncQueue.scala:82:16] assign io_async_mem_7_opcode_0 = mem_7_opcode; // @[AsyncQueue.scala:70:7, :82:16] reg [2:0] mem_7_param; // @[AsyncQueue.scala:82:16] assign io_async_mem_7_param_0 = mem_7_param; // @[AsyncQueue.scala:70:7, :82:16] reg [3:0] mem_7_size; // @[AsyncQueue.scala:82:16] assign io_async_mem_7_size_0 = mem_7_size; // @[AsyncQueue.scala:70:7, :82:16] reg [1:0] mem_7_source; // @[AsyncQueue.scala:82:16] assign io_async_mem_7_source_0 = mem_7_source; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_7_address; // @[AsyncQueue.scala:82:16] assign io_async_mem_7_address_0 = mem_7_address; // @[AsyncQueue.scala:70:7, :82:16] reg [7:0] mem_7_mask; // @[AsyncQueue.scala:82:16] assign io_async_mem_7_mask_0 = mem_7_mask; // @[AsyncQueue.scala:70:7, :82:16] reg [63:0] mem_7_data; // @[AsyncQueue.scala:82:16] assign io_async_mem_7_data_0 = mem_7_data; // @[AsyncQueue.scala:70:7, :82:16] wire _widx_T_1 = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire _widx_T_2 = ~sink_ready; // @[AsyncQueue.scala:81:28, :83:77] wire [3:0] _widx_incremented_T_2; // @[AsyncQueue.scala:53:23] wire [3:0] widx_incremented; // @[AsyncQueue.scala:51:27] reg [3:0] widx_widx_bin; // @[AsyncQueue.scala:52:25] wire [4:0] _widx_incremented_T = {1'h0, widx_widx_bin} + {4'h0, _widx_T_1}; // @[Decoupled.scala:51:35] wire [3:0] _widx_incremented_T_1 = _widx_incremented_T[3:0]; // @[AsyncQueue.scala:53:43] assign _widx_incremented_T_2 = _widx_T_2 ? 4'h0 : _widx_incremented_T_1; // @[AsyncQueue.scala:52:25, :53:{23,43}, :83:77] assign widx_incremented = _widx_incremented_T_2; // @[AsyncQueue.scala:51:27, :53:23] wire [2:0] _widx_T_3 = widx_incremented[3:1]; // @[AsyncQueue.scala:51:27, :54:32] wire [3:0] widx = {widx_incremented[3], widx_incremented[2:0] ^ _widx_T_3}; // @[AsyncQueue.scala:51:27, :54:{17,32}] wire [3:0] ridx; // @[ShiftReg.scala:48:24] wire [3:0] _ready_T = ridx ^ 4'hC; // @[ShiftReg.scala:48:24] wire _ready_T_1 = widx != _ready_T; // @[AsyncQueue.scala:54:17, :85:{34,44}] wire ready = sink_ready & _ready_T_1; // @[AsyncQueue.scala:81:28, :85:{26,34}] wire [2:0] _index_T = io_async_widx_0[2:0]; // @[AsyncQueue.scala:70:7, :87:52] wire _index_T_1 = io_async_widx_0[3]; // @[AsyncQueue.scala:70:7, :87:80] wire [2:0] _index_T_2 = {_index_T_1, 2'h0}; // @[AsyncQueue.scala:87:{80,93}] wire [2:0] index = _index_T ^ _index_T_2; // @[AsyncQueue.scala:87:{52,64,93}] reg ready_reg; // @[AsyncQueue.scala:90:56] assign _io_enq_ready_T = ready_reg & sink_ready; // @[AsyncQueue.scala:81:28, :90:56, :91:29] assign io_enq_ready_0 = _io_enq_ready_T; // @[AsyncQueue.scala:70:7, :91:29] reg [3:0] widx_gray; // @[AsyncQueue.scala:93:55] assign io_async_widx_0 = widx_gray; // @[AsyncQueue.scala:70:7, :93:55] wire _source_valid_0_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46] wire _source_valid_0_reset_T_2 = _source_valid_0_reset_T \| _source_valid_0_reset_T_1; // @[AsyncQueue.scala:107:{36,43,46}] wire _source_valid_0_reset_T_3 = _source_valid_0_reset_T_2; // @[AsyncQueue.scala:107:{43,65}] wire _source_valid_1_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46, :108:46] wire _source_valid_1_reset_T_2 = _source_valid_1_reset_T \| _source_valid_1_reset_T_1; // @[AsyncQueue.scala:108:{36,43,46}] wire _source_valid_1_reset_T_3 = _source_valid_1_reset_T_2; // @[AsyncQueue.scala:108:{43,65}] wire _sink_extend_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46, :109:46] wire _sink_extend_reset_T_2 = _sink_extend_reset_T \| _sink_extend_reset_T_1; // @[AsyncQueue.scala:109:{36,43,46}] wire _sink_extend_reset_T_3 = _sink_extend_reset_T_2; // @[AsyncQueue.scala:109:{43,65}] assign _io_async_safe_source_reset_n_T_1 = ~_io_async_safe_source_reset_n_T; // @[AsyncQueue.scala:123:{27,34}] assign io_async_safe_source_reset_n_0 = _io_async_safe_source_reset_n_T_1; // @[AsyncQueue.scala:70:7, :123:27] always @(posedge clock) begin // @[AsyncQueue.scala:70:7] if (_widx_T_1 & index == 3'h0) begin // @[Decoupled.scala:51:35] mem_0_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16] mem_0_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16] mem_0_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16] mem_0_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16] mem_0_address <= io_enq_bits_address_0; // @[AsyncQueue.scala:70:7, :82:16] mem_0_mask <= io_enq_bits_mask_0; // @[AsyncQueue.scala:70:7, :82:16] mem_0_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16] end if (_widx_T_1 & index == 3'h1) begin // @[Decoupled.scala:51:35] mem_1_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16] mem_1_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16] mem_1_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16] mem_1_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16] mem_1_address <= io_enq_bits_address_0; // @[AsyncQueue.scala:70:7, :82:16] mem_1_mask <= io_enq_bits_mask_0; // @[AsyncQueue.scala:70:7, :82:16] mem_1_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16] end if (_widx_T_1 & index == 3'h2) begin // @[Decoupled.scala:51:35] mem_2_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16] mem_2_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16] mem_2_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16] mem_2_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16] mem_2_address <= io_enq_bits_address_0; // @[AsyncQueue.scala:70:7, :82:16] mem_2_mask <= io_enq_bits_mask_0; // @[AsyncQueue.scala:70:7, :82:16] mem_2_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16] end if (_widx_T_1 & index == 3'h3) begin // @[Decoupled.scala:51:35] mem_3_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16] mem_3_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16] mem_3_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16] mem_3_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16] mem_3_address <= io_enq_bits_address_0; // @[AsyncQueue.scala:70:7, :82:16] mem_3_mask <= io_enq_bits_mask_0; // @[AsyncQueue.scala:70:7, :82:16] mem_3_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16] end if (_widx_T_1 & index == 3'h4) begin // @[Decoupled.scala:51:35] mem_4_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16] mem_4_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16] mem_4_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16] mem_4_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16] mem_4_address <= io_enq_bits_address_0; // @[AsyncQueue.scala:70:7, :82:16] mem_4_mask <= io_enq_bits_mask_0; // @[AsyncQueue.scala:70:7, :82:16] mem_4_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16] end if (_widx_T_1 & index == 3'h5) begin // @[Decoupled.scala:51:35] mem_5_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16] mem_5_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16] mem_5_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16] mem_5_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16] mem_5_address <= io_enq_bits_address_0; // @[AsyncQueue.scala:70:7, :82:16] mem_5_mask <= io_enq_bits_mask_0; // @[AsyncQueue.scala:70:7, :82:16] mem_5_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16] end if (_widx_T_1 & index == 3'h6) begin // @[Decoupled.scala:51:35] mem_6_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16] mem_6_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16] mem_6_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16] mem_6_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16] mem_6_address <= io_enq_bits_address_0; // @[AsyncQueue.scala:70:7, :82:16] mem_6_mask <= io_enq_bits_mask_0; // @[AsyncQueue.scala:70:7, :82:16] mem_6_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16] end if (_widx_T_1 & (&index)) begin // @[Decoupled.scala:51:35] mem_7_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16] mem_7_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16] mem_7_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16] mem_7_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16] mem_7_address <= io_enq_bits_address_0; // @[AsyncQueue.scala:70:7, :82:16] mem_7_mask <= io_enq_bits_mask_0; // @[AsyncQueue.scala:70:7, :82:16] mem_7_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16] end always @(posedge) always @(posedge clock or posedge _widx_T) begin // @[AsyncQueue.scala:70:7, :83:30] if (_widx_T) // @[AsyncQueue.scala:70:7, :83:30] widx_widx_bin <= 4'h0; // @[AsyncQueue.scala:52:25] else // @[AsyncQueue.scala:70:7] widx_widx_bin <= widx_incremented; // @[AsyncQueue.scala:51:27, :52:25] always @(posedge, posedge) always @(posedge clock or posedge _ready_reg_T) begin // @[AsyncQueue.scala:70:7, :90:35] if (_ready_reg_T) // @[AsyncQueue.scala:70:7, :90:35] ready_reg <= 1'h0; // @[AsyncQueue.scala:90:56] else // @[AsyncQueue.scala:70:7] ready_reg <= ready; // @[AsyncQueue.scala:85:26, :90:56] always @(posedge, posedge) always @(posedge clock or posedge _widx_reg_T) begin // @[AsyncQueue.scala:70:7, :93:34] if (_widx_reg_T) // @[AsyncQueue.scala:70:7, :93:34] widx_gray <= 4'h0; // @[AsyncQueue.scala:52:25, :93:55] else // @[AsyncQueue.scala:70:7] widx_gray <= widx; // @[AsyncQueue.scala:54:17, :93:55] always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_63( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_95 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RecFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import consts._ class RecFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val in = Input(Bits((inExpWidth + inSigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in); if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- io.out := io.in<<(outSigWidth - inSigWidth) io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W) } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( inExpWidth, inSigWidth, outExpWidth, outSigWidth, flRoundOpt_sigMSBitAlwaysZero )) roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn) roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := rawIn roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } } File rawFloatFromRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ /---------------------------------------------------------------------------- \| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be \| set. ----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }	module RecFNToRecFN_31( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File Manager.scala: package rerocc.manager import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.prci._ import freechips.rocketchip.subsystem._ import rerocc.bus._ case class ReRoCCManagerParams( managerId: Int, ) case object ReRoCCManagerControlAddress extends Field[BigInt](0x20000) // For local PTW class MiniDCache(reRoCCId: Int, crossing: ClockCrossingType)(implicit p: Parameters) extends DCache(0, crossing)(p) { override def cacheClientParameters = Seq(TLMasterParameters.v1( name = s"ReRoCC ${reRoCCId} DCache", sourceId = IdRange(0, 1), supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes))) override def mmioClientParameters = Seq(TLMasterParameters.v1( name = s"ReRoCC ${reRoCCId} DCache MMIO", sourceId = IdRange(firstMMIO, firstMMIO + cfg.nMMIOs), requestFifo = true)) } class ReRoCCManager(reRoCCTileParams: ReRoCCTileParams, roccOpcode: UInt)(implicit p: Parameters) extends LazyModule { val node = ReRoCCManagerNode(ReRoCCManagerParams(reRoCCTileParams.reroccId)) val ibufEntries = p(ReRoCCIBufEntriesKey) override lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val manager_id = Input(UInt(log2Ceil(p(ReRoCCTileKey).size).W)) val cmd = Decoupled(new RoCCCommand) val resp = Flipped(Decoupled(new RoCCResponse)) val busy = Input(Bool()) val ptw = Flipped(new DatapathPTWIO) }) val (rerocc, edge) = node.in(0) val s_idle :: s_active :: s_rel_wait :: s_sfence :: s_unbusy :: Nil = Enum(5) val numClients = edge.cParams.clients.map(_.nCfgs).sum val client = Reg(UInt(log2Ceil(numClients).W)) val status = Reg(new MStatus) val ptbr = Reg(new PTBR) val state = RegInit(s_idle) io.ptw.ptbr := ptbr io.ptw.hgatp := 0.U.asTypeOf(new PTBR) io.ptw.vsatp := 0.U.asTypeOf(new PTBR) io.ptw.sfence.valid := state === s_sfence io.ptw.sfence.bits.rs1 := false.B io.ptw.sfence.bits.rs2 := false.B io.ptw.sfence.bits.addr := 0.U io.ptw.sfence.bits.asid := 0.U io.ptw.sfence.bits.hv := false.B io.ptw.sfence.bits.hg := false.B io.ptw.status := status io.ptw.hstatus := 0.U.asTypeOf(new HStatus) io.ptw.gstatus := 0.U.asTypeOf(new MStatus) io.ptw.pmp.foreach(_ := 0.U.asTypeOf(new PMP)) val rr_req = Queue(rerocc.req) val (req_first, req_last, req_beat) = ReRoCCMsgFirstLast(rr_req, true) val rr_resp = rerocc.resp rr_req.ready := false.B val inst_q = Module(new Queue(new RoCCCommand, ibufEntries)) val enq_inst = Reg(new RoCCCommand) val next_enq_inst = WireInit(enq_inst) inst_q.io.enq.valid := false.B inst_q.io.enq.bits := next_enq_inst inst_q.io.enq.bits.inst.opcode := roccOpcode // 0 -> acquire ack // 1 -> inst ack // 2 -> writeback // 3 -> rel // 4 -> unbusyack val resp_arb = Module(new ReRoCCMsgArbiter(edge.bundle, 5, false)) rr_resp <> resp_arb.io.out resp_arb.io.in.foreach { i => i.valid := false.B } val status_lower = Reg(UInt(64.W)) when (rr_req.valid) { when (rr_req.bits.opcode === ReRoCCProtocol.mAcquire) { rr_req.ready := resp_arb.io.in(0).ready resp_arb.io.in(0).valid := true.B when (state === s_idle && rr_req.fire) { state := s_active client := rr_req.bits.client_id } } .elsewhen (rr_req.bits.opcode === ReRoCCProtocol.mUStatus) { rr_req.ready := !inst_q.io.deq.valid && !io.busy when (!inst_q.io.deq.valid && !io.busy) { when (req_first) { status_lower := rr_req.bits.data } when (req_last) { status := Cat(rr_req.bits.data, status_lower).asTypeOf(new MStatus) } } } .elsewhen (rr_req.bits.opcode === ReRoCCProtocol.mUPtbr) { rr_req.ready := !inst_q.io.deq.valid && !io.busy when (!inst_q.io.deq.valid && !io.busy) { ptbr := rr_req.bits.data.asTypeOf(new PTBR) } } .elsewhen (rr_req.bits.opcode === ReRoCCProtocol.mInst) { assert(state === s_active && inst_q.io.enq.ready) rr_req.ready := true.B when (req_beat === 0.U) { val inst = rr_req.bits.data.asTypeOf(new RoCCInstruction) enq_inst.inst := inst when (!inst.xs1 ) { enq_inst.rs1 := 0.U } when (!inst.xs2 ) { enq_inst.rs2 := 0.U } } .otherwise { val enq_inst_rs1 = enq_inst.inst.xs1 && req_beat === 1.U val enq_inst_rs2 = enq_inst.inst.xs2 && req_beat === Mux(enq_inst.inst.xs1, 2.U, 1.U) when (enq_inst_rs1) { next_enq_inst.rs1 := rr_req.bits.data } when (enq_inst_rs2) { next_enq_inst.rs2 := rr_req.bits.data } enq_inst := next_enq_inst } when (req_last) { inst_q.io.enq.valid := true.B assert(inst_q.io.enq.ready) } } .elsewhen (rr_req.bits.opcode === ReRoCCProtocol.mRelease) { rr_req.ready := true.B state := s_rel_wait } .elsewhen (rr_req.bits.opcode === ReRoCCProtocol.mUnbusy) { rr_req.ready := true.B state := s_unbusy } .otherwise { assert(false.B) } } // acquire->ack/nack resp_arb.io.in(0).bits.opcode := ReRoCCProtocol.sAcqResp resp_arb.io.in(0).bits.client_id := rr_req.bits.client_id resp_arb.io.in(0).bits.manager_id := io.manager_id resp_arb.io.in(0).bits.data := state === s_idle // insts -> (inst_q, inst_ack) io.cmd.valid := inst_q.io.deq.valid && resp_arb.io.in(1).ready io.cmd.bits := inst_q.io.deq.bits inst_q.io.deq.ready := io.cmd.ready && resp_arb.io.in(1).ready resp_arb.io.in(1).valid := inst_q.io.deq.valid && io.cmd.ready resp_arb.io.in(1).bits.opcode := ReRoCCProtocol.sInstAck resp_arb.io.in(1).bits.client_id := client resp_arb.io.in(1).bits.manager_id := io.manager_id resp_arb.io.in(1).bits.data := 0.U // writebacks val resp = Queue(io.resp) val resp_rd = RegInit(false.B) resp_arb.io.in(2).valid := resp.valid resp_arb.io.in(2).bits.opcode := ReRoCCProtocol.sWrite resp_arb.io.in(2).bits.client_id := client resp_arb.io.in(2).bits.manager_id := io.manager_id resp_arb.io.in(2).bits.data := Mux(resp_rd, resp.bits.rd, resp.bits.data) when (resp_arb.io.in(2).fire) { resp_rd := !resp_rd } resp.ready := resp_arb.io.in(2).ready && resp_rd // release resp_arb.io.in(3).valid := state === s_rel_wait && !io.busy && inst_q.io.count === 0.U resp_arb.io.in(3).bits.opcode := ReRoCCProtocol.sRelResp resp_arb.io.in(3).bits.client_id := client resp_arb.io.in(3).bits.manager_id := io.manager_id resp_arb.io.in(3).bits.data := 0.U when (resp_arb.io.in(3).fire) { state := s_sfence } when (state === s_sfence) { state := s_idle } // unbusyack resp_arb.io.in(4).valid := state === s_unbusy && !io.busy && inst_q.io.count === 0.U resp_arb.io.in(4).bits.opcode := ReRoCCProtocol.sUnbusyAck resp_arb.io.in(4).bits.client_id := client resp_arb.io.in(4).bits.manager_id := io.manager_id resp_arb.io.in(4).bits.data := 0.U when (resp_arb.io.in(4).fire) { state := s_active } } } class ReRoCCManagerTile()(implicit p: Parameters) extends LazyModule { val reRoCCParams = p(TileKey).asInstanceOf[ReRoCCTileParams] val reRoCCId = reRoCCParams.reroccId def this(tileParams: ReRoCCTileParams, p: Parameters) = { this()(p.alterMap(Map( TileKey -> tileParams, TileVisibilityNodeKey -> TLEphemeralNode()(ValName("rerocc_manager")) ))) } val reroccManagerIdSinkNode = BundleBridgeSink[UInt]() val rocc = reRoCCParams.genRoCC.get(p) require(rocc.opcodes.opcodes.size == 1) val rerocc_manager = LazyModule(new ReRoCCManager(reRoCCParams, rocc.opcodes.opcodes.head)) val reRoCCNode = ReRoCCIdentityNode() rerocc_manager.node := ReRoCCBuffer() := reRoCCNode val tlNode = p(TileVisibilityNodeKey) // throttle before TL Node (merged -> val tlXbar = TLXbar() val stlNode = TLIdentityNode() tlXbar :=* rocc.atlNode if (reRoCCParams.mergeTLNodes) { tlXbar :=* rocc.tlNode } else { tlNode :=* rocc.tlNode } tlNode :=* TLBuffer() :=* tlXbar rocc.stlNode := stlNode // minicache val dcache = reRoCCParams.dcacheParams.map(_ => LazyModule(new MiniDCache(reRoCCId, SynchronousCrossing())(p))) dcache.map(d => tlXbar := TLWidthWidget(reRoCCParams.rowBits/8) := d.node) val hellammio: Option[HellaMMIO] = if (!dcache.isDefined) { val h = LazyModule(new HellaMMIO(s"ReRoCC $reRoCCId MMIO")) tlXbar := h.node Some(h) } else { None } val ctrl = LazyModule(new ReRoCCManagerControl(reRoCCId, 8)) override lazy val module = new LazyModuleImp(this) { val dcacheArb = Module(new HellaCacheArbiter(2)(p)) dcache.map(_.module.io.cpu).getOrElse(hellammio.get.module.io) <> dcacheArb.io.mem val edge = dcache.map(_.node.edges.out(0)).getOrElse(hellammio.get.node.edges.out(0)) val ptw = Module(new PTW(1 + rocc.nPTWPorts)(edge, p)) if (dcache.isDefined) { dcache.get.module.io.tlb_port := DontCare dcache.get.module.io.tlb_port.req.valid := false.B ptw.io.requestor(0) <> dcache.get.module.io.ptw } else { ptw.io.requestor(0) := DontCare ptw.io.requestor(0).req.valid := false.B } dcacheArb.io.requestor(0) <> ptw.io.mem val dcIF = Module(new SimpleHellaCacheIF) dcIF.io.requestor <> rocc.module.io.mem dcacheArb.io.requestor(1) <> dcIF.io.cache for (i <- 0 until rocc.nPTWPorts) { ptw.io.requestor(1+i) <> rocc.module.io.ptw(i) } rerocc_manager.module.io.manager_id := reroccManagerIdSinkNode.bundle rocc.module.io.cmd <> rerocc_manager.module.io.cmd rerocc_manager.module.io.resp <> rocc.module.io.resp rerocc_manager.module.io.busy := rocc.module.io.busy ptw.io.dpath <> rerocc_manager.module.io.ptw rocc.module.io.fpu_req.ready := false.B assert(!rocc.module.io.fpu_req.valid) rocc.module.io.fpu_resp.valid := false.B rocc.module.io.fpu_resp.bits := DontCare rocc.module.io.exception := false.B ctrl.module.io.mgr_busy := rerocc_manager.module.io.busy ctrl.module.io.rocc_busy := rocc.module.io.busy } } File LazyRoCC.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util._ import chisel3.experimental.IntParam import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.rocket.{ MStatus, HellaCacheIO, TLBPTWIO, CanHavePTW, CanHavePTWModule, SimpleHellaCacheIF, M_XRD, PTE, PRV, M_SZ } import freechips.rocketchip.tilelink.{ TLNode, TLIdentityNode, TLClientNode, TLMasterParameters, TLMasterPortParameters } import freechips.rocketchip.util.InOrderArbiter case object BuildRoCC extends Field[Seq[Parameters => LazyRoCC]](Nil) class RoCCInstruction extends Bundle { val funct = Bits(7.W) val rs2 = Bits(5.W) val rs1 = Bits(5.W) val xd = Bool() val xs1 = Bool() val xs2 = Bool() val rd = Bits(5.W) val opcode = Bits(7.W) } class RoCCCommand(implicit p: Parameters) extends CoreBundle()(p) { val inst = new RoCCInstruction val rs1 = Bits(xLen.W) val rs2 = Bits(xLen.W) val status = new MStatus } class RoCCResponse(implicit p: Parameters) extends CoreBundle()(p) { val rd = Bits(5.W) val data = Bits(xLen.W) } class RoCCCoreIO(val nRoCCCSRs: Int = 0)(implicit p: Parameters) extends CoreBundle()(p) { val cmd = Flipped(Decoupled(new RoCCCommand)) val resp = Decoupled(new RoCCResponse) val mem = new HellaCacheIO val busy = Output(Bool()) val interrupt = Output(Bool()) val exception = Input(Bool()) val csrs = Flipped(Vec(nRoCCCSRs, new CustomCSRIO)) } class RoCCIO(val nPTWPorts: Int, nRoCCCSRs: Int)(implicit p: Parameters) extends RoCCCoreIO(nRoCCCSRs)(p) { val ptw = Vec(nPTWPorts, new TLBPTWIO) val fpu_req = Decoupled(new FPInput) val fpu_resp = Flipped(Decoupled(new FPResult)) } /* Base classes for Diplomatic TL2 RoCC units / abstract class LazyRoCC( val opcodes: OpcodeSet, val nPTWPorts: Int = 0, val usesFPU: Boolean = false, val roccCSRs: Seq[CustomCSR] = Nil )(implicit p: Parameters) extends LazyModule { val module: LazyRoCCModuleImp require(roccCSRs.map(_.id).toSet.size == roccCSRs.size) val atlNode: TLNode = TLIdentityNode() val tlNode: TLNode = TLIdentityNode() val stlNode: TLNode = TLIdentityNode() } class LazyRoCCModuleImp(outer: LazyRoCC) extends LazyModuleImp(outer) { val io = IO(new RoCCIO(outer.nPTWPorts, outer.roccCSRs.size)) io := DontCare } / Mixins for including RoCC */ trait HasLazyRoCC extends CanHavePTW { this: BaseTile => val roccs = p(BuildRoCC).map(_(p)) val roccCSRs = roccs.map(_.roccCSRs) // the set of custom CSRs requested by all roccs require(roccCSRs.flatten.map(_.id).toSet.size == roccCSRs.flatten.size, "LazyRoCC instantiations require overlapping CSRs") roccs.map(_.atlNode).foreach { atl => tlMasterXbar.node := atl } roccs.map(_.tlNode).foreach { tl => tlOtherMastersNode :=* tl } roccs.map(_.stlNode).foreach { stl => stl := tlSlaveXbar.node } nPTWPorts += roccs.map(_.nPTWPorts).sum nDCachePorts += roccs.size } trait HasLazyRoCCModule extends CanHavePTWModule with HasCoreParameters { this: RocketTileModuleImp => val (respArb, cmdRouter) = if(outer.roccs.nonEmpty) { val respArb = Module(new RRArbiter(new RoCCResponse()(outer.p), outer.roccs.size)) val cmdRouter = Module(new RoccCommandRouter(outer.roccs.map(_.opcodes))(outer.p)) outer.roccs.zipWithIndex.foreach { case (rocc, i) => rocc.module.io.ptw ++=: ptwPorts rocc.module.io.cmd <> cmdRouter.io.out(i) val dcIF = Module(new SimpleHellaCacheIF()(outer.p)) dcIF.io.requestor <> rocc.module.io.mem dcachePorts += dcIF.io.cache respArb.io.in(i) <> Queue(rocc.module.io.resp) } (Some(respArb), Some(cmdRouter)) } else { (None, None) } val roccCSRIOs = outer.roccs.map(_.module.io.csrs) } class AccumulatorExample(opcodes: OpcodeSet, val n: Int = 4)(implicit p: Parameters) extends LazyRoCC(opcodes) { override lazy val module = new AccumulatorExampleModuleImp(this) } class AccumulatorExampleModuleImp(outer: AccumulatorExample)(implicit p: Parameters) extends LazyRoCCModuleImp(outer) with HasCoreParameters { val regfile = Mem(outer.n, UInt(xLen.W)) val busy = RegInit(VecInit(Seq.fill(outer.n){false.B})) val cmd = Queue(io.cmd) val funct = cmd.bits.inst.funct val addr = cmd.bits.rs2(log2Up(outer.n)-1,0) val doWrite = funct === 0.U val doRead = funct === 1.U val doLoad = funct === 2.U val doAccum = funct === 3.U val memRespTag = io.mem.resp.bits.tag(log2Up(outer.n)-1,0) // datapath val addend = cmd.bits.rs1 val accum = regfile(addr) val wdata = Mux(doWrite, addend, accum + addend) when (cmd.fire && (doWrite \|\| doAccum)) { regfile(addr) := wdata } when (io.mem.resp.valid) { regfile(memRespTag) := io.mem.resp.bits.data busy(memRespTag) := false.B } // control when (io.mem.req.fire) { busy(addr) := true.B } val doResp = cmd.bits.inst.xd val stallReg = busy(addr) val stallLoad = doLoad && !io.mem.req.ready val stallResp = doResp && !io.resp.ready cmd.ready := !stallReg && !stallLoad && !stallResp // command resolved if no stalls AND not issuing a load that will need a request // PROC RESPONSE INTERFACE io.resp.valid := cmd.valid && doResp && !stallReg && !stallLoad // valid response if valid command, need a response, and no stalls io.resp.bits.rd := cmd.bits.inst.rd // Must respond with the appropriate tag or undefined behavior io.resp.bits.data := accum // Semantics is to always send out prior accumulator register value io.busy := cmd.valid \|\| busy.reduce(_\|\|_) // Be busy when have pending memory requests or committed possibility of pending requests io.interrupt := false.B // Set this true to trigger an interrupt on the processor (please refer to supervisor documentation) // MEMORY REQUEST INTERFACE io.mem.req.valid := cmd.valid && doLoad && !stallReg && !stallResp io.mem.req.bits.addr := addend io.mem.req.bits.tag := addr io.mem.req.bits.cmd := M_XRD // perform a load (M_XWR for stores) io.mem.req.bits.size := log2Ceil(8).U io.mem.req.bits.signed := false.B io.mem.req.bits.data := 0.U // we're not performing any stores... io.mem.req.bits.phys := false.B io.mem.req.bits.dprv := cmd.bits.status.dprv io.mem.req.bits.dv := cmd.bits.status.dv io.mem.req.bits.no_resp := false.B } class TranslatorExample(opcodes: OpcodeSet)(implicit p: Parameters) extends LazyRoCC(opcodes, nPTWPorts = 1) { override lazy val module = new TranslatorExampleModuleImp(this) } class TranslatorExampleModuleImp(outer: TranslatorExample)(implicit p: Parameters) extends LazyRoCCModuleImp(outer) with HasCoreParameters { val req_addr = Reg(UInt(coreMaxAddrBits.W)) val req_rd = Reg(chiselTypeOf(io.resp.bits.rd)) val req_offset = req_addr(pgIdxBits - 1, 0) val req_vpn = req_addr(coreMaxAddrBits - 1, pgIdxBits) val pte = Reg(new PTE) val s_idle :: s_ptw_req :: s_ptw_resp :: s_resp :: Nil = Enum(4) val state = RegInit(s_idle) io.cmd.ready := (state === s_idle) when (io.cmd.fire) { req_rd := io.cmd.bits.inst.rd req_addr := io.cmd.bits.rs1 state := s_ptw_req } private val ptw = io.ptw(0) when (ptw.req.fire) { state := s_ptw_resp } when (state === s_ptw_resp && ptw.resp.valid) { pte := ptw.resp.bits.pte state := s_resp } when (io.resp.fire) { state := s_idle } ptw.req.valid := (state === s_ptw_req) ptw.req.bits.valid := true.B ptw.req.bits.bits.addr := req_vpn io.resp.valid := (state === s_resp) io.resp.bits.rd := req_rd io.resp.bits.data := Mux(pte.leaf(), Cat(pte.ppn, req_offset), -1.S(xLen.W).asUInt) io.busy := (state =/= s_idle) io.interrupt := false.B io.mem.req.valid := false.B } class CharacterCountExample(opcodes: OpcodeSet)(implicit p: Parameters) extends LazyRoCC(opcodes) { override lazy val module = new CharacterCountExampleModuleImp(this) override val atlNode = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1("CharacterCountRoCC"))))) } class CharacterCountExampleModuleImp(outer: CharacterCountExample)(implicit p: Parameters) extends LazyRoCCModuleImp(outer) with HasCoreParameters with HasL1CacheParameters { val cacheParams = tileParams.dcache.get private val blockOffset = blockOffBits private val beatOffset = log2Up(cacheDataBits/8) val needle = Reg(UInt(8.W)) val addr = Reg(UInt(coreMaxAddrBits.W)) val count = Reg(UInt(xLen.W)) val resp_rd = Reg(chiselTypeOf(io.resp.bits.rd)) val addr_block = addr(coreMaxAddrBits - 1, blockOffset) val offset = addr(blockOffset - 1, 0) val next_addr = (addr_block + 1.U) << blockOffset.U val s_idle :: s_acq :: s_gnt :: s_check :: s_resp :: Nil = Enum(5) val state = RegInit(s_idle) val (tl_out, edgesOut) = outer.atlNode.out(0) val gnt = tl_out.d.bits val recv_data = Reg(UInt(cacheDataBits.W)) val recv_beat = RegInit(0.U(log2Up(cacheDataBeats+1).W)) val data_bytes = VecInit(Seq.tabulate(cacheDataBits/8) { i => recv_data(8 (i + 1) - 1, 8 * i) }) val zero_match = data_bytes.map(_ === 0.U) val needle_match = data_bytes.map(_ === needle) val first_zero = PriorityEncoder(zero_match) val chars_found = PopCount(needle_match.zipWithIndex.map { case (matches, i) => val idx = Cat(recv_beat - 1.U, i.U(beatOffset.W)) matches && idx >= offset && i.U <= first_zero }) val zero_found = zero_match.reduce(_ \|\| _) val finished = Reg(Bool()) io.cmd.ready := (state === s_idle) io.resp.valid := (state === s_resp) io.resp.bits.rd := resp_rd io.resp.bits.data := count tl_out.a.valid := (state === s_acq) tl_out.a.bits := edgesOut.Get( fromSource = 0.U, toAddress = addr_block << blockOffset, lgSize = lgCacheBlockBytes.U)._2 tl_out.d.ready := (state === s_gnt) when (io.cmd.fire) { addr := io.cmd.bits.rs1 needle := io.cmd.bits.rs2 resp_rd := io.cmd.bits.inst.rd count := 0.U finished := false.B state := s_acq } when (tl_out.a.fire) { state := s_gnt } when (tl_out.d.fire) { recv_beat := recv_beat + 1.U recv_data := gnt.data state := s_check } when (state === s_check) { when (!finished) { count := count + chars_found } when (zero_found) { finished := true.B } when (recv_beat === cacheDataBeats.U) { addr := next_addr state := Mux(zero_found \|\| finished, s_resp, s_acq) recv_beat := 0.U } .otherwise { state := s_gnt } } when (io.resp.fire) { state := s_idle } io.busy := (state =/= s_idle) io.interrupt := false.B io.mem.req.valid := false.B // Tie off unused channels tl_out.b.ready := true.B tl_out.c.valid := false.B tl_out.e.valid := false.B } class BlackBoxExample(opcodes: OpcodeSet, blackBoxFile: String)(implicit p: Parameters) extends LazyRoCC(opcodes) { override lazy val module = new BlackBoxExampleModuleImp(this, blackBoxFile) } class BlackBoxExampleModuleImp(outer: BlackBoxExample, blackBoxFile: String)(implicit p: Parameters) extends LazyRoCCModuleImp(outer) with RequireSyncReset with HasCoreParameters { val blackbox = { val roccIo = io Module( new BlackBox( Map( "xLen" -> IntParam(xLen), "PRV_SZ" -> IntParam(PRV.SZ), "coreMaxAddrBits" -> IntParam(coreMaxAddrBits), "dcacheReqTagBits" -> IntParam(roccIo.mem.req.bits.tag.getWidth), "M_SZ" -> IntParam(M_SZ), "mem_req_bits_size_width" -> IntParam(roccIo.mem.req.bits.size.getWidth), "coreDataBits" -> IntParam(coreDataBits), "coreDataBytes" -> IntParam(coreDataBytes), "paddrBits" -> IntParam(paddrBits), "vaddrBitsExtended" -> IntParam(vaddrBitsExtended), "FPConstants_RM_SZ" -> IntParam(FPConstants.RM_SZ), "fLen" -> IntParam(fLen), "FPConstants_FLAGS_SZ" -> IntParam(FPConstants.FLAGS_SZ) ) ) with HasBlackBoxResource { val io = IO( new Bundle { val clock = Input(Clock()) val reset = Input(Reset()) val rocc = chiselTypeOf(roccIo) }) override def desiredName: String = blackBoxFile addResource(s"/vsrc/$blackBoxFile.v") } ) } blackbox.io.clock := clock blackbox.io.reset := reset blackbox.io.rocc.cmd <> io.cmd io.resp <> blackbox.io.rocc.resp io.mem <> blackbox.io.rocc.mem io.busy := blackbox.io.rocc.busy io.interrupt := blackbox.io.rocc.interrupt blackbox.io.rocc.exception := io.exception io.ptw <> blackbox.io.rocc.ptw io.fpu_req <> blackbox.io.rocc.fpu_req blackbox.io.rocc.fpu_resp <> io.fpu_resp } class OpcodeSet(val opcodes: Seq[UInt]) { def \|(set: OpcodeSet) = new OpcodeSet(this.opcodes ++ set.opcodes) def matches(oc: UInt) = opcodes.map(_ === oc).reduce(_ \|\| _) } object OpcodeSet { def custom0 = new OpcodeSet(Seq("b0001011".U)) def custom1 = new OpcodeSet(Seq("b0101011".U)) def custom2 = new OpcodeSet(Seq("b1011011".U)) def custom3 = new OpcodeSet(Seq("b1111011".U)) def all = custom0 \| custom1 \| custom2 \| custom3 } class RoccCommandRouter(opcodes: Seq[OpcodeSet])(implicit p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { val in = Flipped(Decoupled(new RoCCCommand)) val out = Vec(opcodes.size, Decoupled(new RoCCCommand)) val busy = Output(Bool()) }) val cmd = Queue(io.in) val cmdReadys = io.out.zip(opcodes).map { case (out, opcode) => val me = opcode.matches(cmd.bits.inst.opcode) out.valid := cmd.valid && me out.bits := cmd.bits out.ready && me } cmd.ready := cmdReadys.reduce(_ \|\| _) io.busy := cmd.valid assert(PopCount(cmdReadys) <= 1.U, "Custom opcode matched for more than one accelerator") } File Protocol.scala: package rerocc.bus import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tile._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import rerocc.client.{ReRoCCClientParams} import rerocc.manager.{ReRoCCManagerParams} object ReRoCCProtocol { val width = 3 val mAcquire = 0.U(width.W) // beat0: data = inst // beat1: data = mstatus[63:0] // beat2: data = mstatus[127:64] val mInst = 1.U(width.W) // beat0: data = mstatus[63:0] // beat1: data = mstatus[127:0] val mUStatus = 2.U(width.W) // beat0: data = ptbr val mUPtbr = 3.U(width.W) val mRelease = 4.U(width.W) val mUnbusy = 5.U(width.W) // data // data = acquired val sAcqResp = 0.U(width.W) // data = 0 val sInstAck = 1.U(width.W) // beat0: data = data // beat1: data = rd val sWrite = 2.U(width.W) val sRelResp = 3.U(width.W) val sUnbusyAck = 4.U(width.W) val MAX_BEATS = 3 } class ReRoCCMsgBundle(val params: ReRoCCBundleParams) extends Bundle { val opcode = UInt(ReRoCCProtocol.width.W) val client_id = UInt(params.clientIdBits.W) val manager_id = UInt(params.managerIdBits.W) val data = UInt(64.W) } object ReRoCCMsgFirstLast { def apply(m: DecoupledIO[ReRoCCMsgBundle], isReq: Boolean): (Bool, Bool, UInt) = { val beat = RegInit(0.U(log2Ceil(ReRoCCProtocol.MAX_BEATS).W)) val max_beat = RegInit(0.U(log2Ceil(ReRoCCProtocol.MAX_BEATS).W)) val first = beat === 0.U val last = Wire(Bool()) val inst = m.bits.data.asTypeOf(new RoCCInstruction) when (m.fire && first) { max_beat := 0.U if (isReq) { when (m.bits.opcode === ReRoCCProtocol.mInst) { max_beat := inst.xs1 +& inst.xs2 } .elsewhen (m.bits.opcode === ReRoCCProtocol.mUStatus) { max_beat := 1.U } } else { when (m.bits.opcode === ReRoCCProtocol.sWrite) { max_beat := 1.U } } } last := true.B if (isReq) { when (m.bits.opcode === ReRoCCProtocol.mUStatus) { last := beat === max_beat && !first } .elsewhen (m.bits.opcode === ReRoCCProtocol.mInst) { last := Mux(first, !inst.xs1 && !inst.xs2, beat === max_beat) } } else { when (m.bits.opcode === ReRoCCProtocol.sWrite) { last := beat === max_beat && !first } } when (m.fire) { beat := beat + 1.U } when (m.fire && last) { max_beat := 0.U beat := 0.U } (first, last, beat) } } class ReRoCCBundle(val params: ReRoCCBundleParams) extends Bundle { val req = Decoupled(new ReRoCCMsgBundle(params)) val resp = Flipped(Decoupled(new ReRoCCMsgBundle(params))) } case class EmptyParams() object ReRoCCImp extends SimpleNodeImp[ReRoCCClientPortParams, ReRoCCManagerPortParams, ReRoCCEdgeParams, ReRoCCBundle] { def edge(pd: ReRoCCClientPortParams, pu: ReRoCCManagerPortParams, p: Parameters, sourceInfo: SourceInfo) = { ReRoCCEdgeParams(pu, pd) } def bundle(e: ReRoCCEdgeParams) = new ReRoCCBundle(e.bundle) def render(ei: ReRoCCEdgeParams) = RenderedEdge(colour = "#000000" /* black /) } case class ReRoCCClientNode(clientParams: ReRoCCClientParams)(implicit valName: ValName) extends SourceNode(ReRoCCImp)(Seq(ReRoCCClientPortParams(Seq(clientParams)))) case class ReRoCCManagerNode(managerParams: ReRoCCManagerParams)(implicit valName: ValName) extends SinkNode(ReRoCCImp)(Seq(ReRoCCManagerPortParams(Seq(managerParams)))) class ReRoCCBuffer(b: BufferParams = BufferParams.default)(implicit p: Parameters) extends LazyModule { val node = new AdapterNode(ReRoCCImp)({s => s}, {s => s}) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, _), (out, _)) => out.req <> b(in.req) in.resp <> b(out.resp) } } } object ReRoCCBuffer { def apply(b: BufferParams = BufferParams.default)(implicit p: Parameters) = { val rerocc_buffer = LazyModule(new ReRoCCBuffer(b)(p)) rerocc_buffer.node } } case class ReRoCCIdentityNode()(implicit valName: ValName) extends IdentityNode(ReRoCCImp)() File WidthWidget.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.util.{Repeater, UIntToOH1} // innBeatBytes => the new client-facing bus width class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule { private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes val node = new TLAdapterNode( clientFn = { case c => c }, managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){ override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired) } override lazy val desiredName = s"TLWidthWidget$innerBeatBytes" lazy val module = new Impl class Impl extends LazyModuleImp(this) { def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = outBytes / inBytes val keepBits = log2Ceil(outBytes) val dropBits = log2Ceil(inBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit \|\| !hasData val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR } val corrupt_reg = RegInit(false.B) val corrupt_in = edgeIn.corrupt(in.bits) val corrupt_out = corrupt_in \|\| corrupt_reg when (in.fire) { count := count + 1.U corrupt_reg := corrupt_out when (last) { count := 0.U corrupt_reg := false.B } } def helper(idata: UInt): UInt = { // rdata is X until the first time a multi-beat write occurs. // Prevent the X from leaking outside by jamming the mux control until // the first time rdata is written (and hence no longer X). val rdata_written_once = RegInit(false.B) val masked_enable = enable.map(_ \|\| !rdata_written_once) val odata = Seq.fill(ratio) { WireInit(idata) } val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata))) val pdata = rdata :+ idata val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) } when (in.fire && !last) { rdata_written_once := true.B (rdata zip mdata) foreach { case (r, m) => r := m } } Cat(mdata.reverse) } in.ready := out.ready \|\| !last out.valid := in.valid && last out.bits := in.bits // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits))) edgeOut.corrupt(out.bits) := corrupt_out (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleC, i: TLBundleC) => () case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossible bundle combination in WidthWidget") } } def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = inBytes / outBytes val keepBits = log2Ceil(inBytes) val dropBits = log2Ceil(outBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit \|\| !hasData when (out.fire) { count := count + 1.U when (last) { count := 0.U } } // For sub-beat transfer, extract which part matters val sel = in.bits match { case a: TLBundleA => a.address(keepBits-1, dropBits) case b: TLBundleB => b.address(keepBits-1, dropBits) case c: TLBundleC => c.address(keepBits-1, dropBits) case d: TLBundleD => { val sel = sourceMap(d.source) val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway } } val index = sel \| count def helper(idata: UInt, width: Int): UInt = { val mux = VecInit.tabulate(ratio) { i => idata((i+1)outByteswidth-1, ioutByteswidth) } mux(index) } out.bits := in.bits out.valid := in.valid in.ready := out.ready // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8)) (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1) case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1) case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossbile bundle combination in WidthWidget") } // Repeat the input if we're not last !last } def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) { // nothing to do; pass it through out.bits := in.bits out.valid := in.valid in.ready := out.ready } else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) { // split input to output val repeat = Wire(Bool()) val repeated = Repeater(in, repeat) val cated = Wire(chiselTypeOf(repeated)) cated <> repeated edgeIn.data(cated.bits) := Cat( edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes8-1, edgeOut.manager.beatBytes8), edgeIn.data(in.bits)(edgeOut.manager.beatBytes8-1, 0)) repeat := split(edgeIn, cated, edgeOut, out, sourceMap) } else { // merge input to output merge(edgeIn, in, edgeOut, out) } } (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => // If the master is narrower than the slave, the D channel must be narrowed. // This is tricky, because the D channel has no address data. // Thus, you don't know which part of a sub-beat transfer to extract. // To fix this, we record the relevant address bits for all sources. // The assumption is that this sort of situation happens only where // you connect a narrow master to the system bus, so there are few sources. def sourceMap(source_bits: UInt) = { val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes) val keepBits = log2Ceil(edgeOut.manager.beatBytes) val dropBits = log2Ceil(edgeIn.manager.beatBytes) val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W))) val a_sel = in.a.bits.address(keepBits-1, dropBits) when (in.a.fire) { if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning sources(0) := a_sel } else { sources(in.a.bits.source) := a_sel } } // depopulate unused source registers: edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U } val bypass = in.a.valid && in.a.bits.source === source if (edgeIn.manager.minLatency > 0) sources(source) else Mux(bypass, a_sel, sources(source)) } splice(edgeIn, in.a, edgeOut, out.a, sourceMap) splice(edgeOut, out.d, edgeIn, in.d, sourceMap) if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { splice(edgeOut, out.b, edgeIn, in.b, sourceMap) splice(edgeIn, in.c, edgeOut, out.c, sourceMap) out.e.valid := in.e.valid out.e.bits := in.e.bits in.e.ready := out.e.ready } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLWidthWidget { def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode = { val widget = LazyModule(new TLWidthWidget(innerBeatBytes)) widget.node } def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("WidthWidget")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) (ram.node := TLDelayer(0.1) := TLFragmenter(4, 256) := TLWidthWidget(second) := TLWidthWidget(first) := TLDelayer(0.1) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module) dut.io.start := DontCare io.finished := dut.io.finished } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size * node.out.size) > (832)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source \| r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source \| r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink \| r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ \|\| _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) \|\| o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) \|\| o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) \|\| (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }	module ReRoCCManagerTile_3( // @[Manager.scala:237:34] input clock, // @[Manager.scala:237:34] input reset, // @[Manager.scala:237:34] output auto_ctrl_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_ctrl_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrl_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrl_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrl_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_ctrl_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_ctrl_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_ctrl_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_ctrl_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_ctrl_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_ctrl_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_ctrl_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_ctrl_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_ctrl_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_ctrl_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_ctrl_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_buffer_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_buffer_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_re_ro_cc_in_req_ready, // @[LazyModuleImp.scala:107:25] input auto_re_ro_cc_in_req_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_re_ro_cc_in_req_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_re_ro_cc_in_req_bits_client_id, // @[LazyModuleImp.scala:107:25] input auto_re_ro_cc_in_req_bits_manager_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_re_ro_cc_in_req_bits_data, // @[LazyModuleImp.scala:107:25] input auto_re_ro_cc_in_resp_ready, // @[LazyModuleImp.scala:107:25] output auto_re_ro_cc_in_resp_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_re_ro_cc_in_resp_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_re_ro_cc_in_resp_bits_client_id, // @[LazyModuleImp.scala:107:25] output auto_re_ro_cc_in_resp_bits_manager_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_re_ro_cc_in_resp_bits_data, // @[LazyModuleImp.scala:107:25] input [6:0] auto_rerocc_manager_id_sink_in // @[LazyModuleImp.scala:107:25] ); wire reRoCCNodeOut_resp_valid; // @[MixedNode.scala:542:17] wire [63:0] reRoCCNodeOut_resp_bits_data; // @[MixedNode.scala:542:17] wire reRoCCNodeOut_resp_bits_manager_id; // @[MixedNode.scala:542:17] wire [3:0] reRoCCNodeOut_resp_bits_client_id; // @[MixedNode.scala:542:17] wire [2:0] reRoCCNodeOut_resp_bits_opcode; // @[MixedNode.scala:542:17] wire reRoCCNodeOut_req_ready; // @[MixedNode.scala:542:17] wire widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] xbar_out_0_e_bits_sink; // @[Xbar.scala:216:19] wire [2:0] xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19] wire xbar_in_0_d_bits_source; // @[Xbar.scala:159:18] wire xbar_in_0_c_bits_source; // @[Xbar.scala:159:18] wire xbar_in_0_b_bits_source; // @[Xbar.scala:159:18] wire xbar_in_0_a_bits_source; // @[Xbar.scala:159:18] wire xbar_auto_anon_out_e_ready; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire [63:0] xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire [3:0] xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire [1:0] xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_c_ready; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_b_valid; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_b_bits_corrupt; // @[Xbar.scala:74:9] wire [63:0] xbar_auto_anon_out_b_bits_data; // @[Xbar.scala:74:9] wire [7:0] xbar_auto_anon_out_b_bits_mask; // @[Xbar.scala:74:9] wire [31:0] xbar_auto_anon_out_b_bits_address; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_b_bits_source; // @[Xbar.scala:74:9] wire [3:0] xbar_auto_anon_out_b_bits_size; // @[Xbar.scala:74:9] wire [1:0] xbar_auto_anon_out_b_bits_param; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_out_b_bits_opcode; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_e_valid; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_e_ready; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_in_e_bits_sink; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_d_valid; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_d_bits_corrupt; // @[Xbar.scala:74:9] wire [63:0] xbar_auto_anon_in_d_bits_data; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_d_bits_denied; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_in_d_bits_sink; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_d_bits_source; // @[Xbar.scala:74:9] wire [3:0] xbar_auto_anon_in_d_bits_size; // @[Xbar.scala:74:9] wire [1:0] xbar_auto_anon_in_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_in_d_bits_opcode; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_c_valid; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_c_ready; // @[Xbar.scala:74:9] wire [63:0] xbar_auto_anon_in_c_bits_data; // @[Xbar.scala:74:9] wire [31:0] xbar_auto_anon_in_c_bits_address; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_c_bits_source; // @[Xbar.scala:74:9] wire [3:0] xbar_auto_anon_in_c_bits_size; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_in_c_bits_param; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_in_c_bits_opcode; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_b_valid; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_b_ready; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_b_bits_corrupt; // @[Xbar.scala:74:9] wire [63:0] xbar_auto_anon_in_b_bits_data; // @[Xbar.scala:74:9] wire [7:0] xbar_auto_anon_in_b_bits_mask; // @[Xbar.scala:74:9] wire [31:0] xbar_auto_anon_in_b_bits_address; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_b_bits_source; // @[Xbar.scala:74:9] wire [3:0] xbar_auto_anon_in_b_bits_size; // @[Xbar.scala:74:9] wire [1:0] xbar_auto_anon_in_b_bits_param; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_in_b_bits_opcode; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_a_ready; // @[Xbar.scala:74:9] wire [63:0] xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire [7:0] xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [31:0] xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [3:0] xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire _dcIF_io_cache_req_valid; // @[Manager.scala:255:22] wire [39:0] _dcIF_io_cache_req_bits_addr; // @[Manager.scala:255:22] wire [7:0] _dcIF_io_cache_req_bits_tag; // @[Manager.scala:255:22] wire [1:0] _dcIF_io_cache_req_bits_dprv; // @[Manager.scala:255:22] wire _dcIF_io_cache_req_bits_dv; // @[Manager.scala:255:22] wire [63:0] _dcIF_io_cache_s1_data_data; // @[Manager.scala:255:22] wire [7:0] _dcIF_io_cache_s1_data_mask; // @[Manager.scala:255:22] wire _ptw_io_requestor_0_req_ready; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_valid; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_ae_ptw; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_ae_final; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_pf; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_gf; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_hr; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_hw; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_hx; // @[Manager.scala:243:21] wire [9:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_future; // @[Manager.scala:243:21] wire [43:0] _ptw_io_requestor_0_resp_bits_pte_ppn; // @[Manager.scala:243:21] wire [1:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_software; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_pte_d; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_pte_a; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_pte_g; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_pte_u; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_pte_x; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_pte_w; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_pte_r; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_pte_v; // @[Manager.scala:243:21] wire [1:0] _ptw_io_requestor_0_resp_bits_level; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_homogeneous; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_gpa_valid; // @[Manager.scala:243:21] wire [38:0] _ptw_io_requestor_0_resp_bits_gpa_bits; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_gpa_is_pte; // @[Manager.scala:243:21] wire [3:0] _ptw_io_requestor_0_ptbr_mode; // @[Manager.scala:243:21] wire [15:0] _ptw_io_requestor_0_ptbr_asid; // @[Manager.scala:243:21] wire [43:0] _ptw_io_requestor_0_ptbr_ppn; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_debug; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_cease; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_wfi; // @[Manager.scala:243:21] wire [31:0] _ptw_io_requestor_0_status_isa; // @[Manager.scala:243:21] wire [1:0] _ptw_io_requestor_0_status_dprv; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_dv; // @[Manager.scala:243:21] wire [1:0] _ptw_io_requestor_0_status_prv; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_v; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_sd; // @[Manager.scala:243:21] wire [22:0] _ptw_io_requestor_0_status_zero2; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_mpv; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_gva; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_mbe; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_sbe; // @[Manager.scala:243:21] wire [1:0] _ptw_io_requestor_0_status_sxl; // @[Manager.scala:243:21] wire [1:0] _ptw_io_requestor_0_status_uxl; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_sd_rv32; // @[Manager.scala:243:21] wire [7:0] _ptw_io_requestor_0_status_zero1; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_tsr; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_tw; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_tvm; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_mxr; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_sum; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_mprv; // @[Manager.scala:243:21] wire [1:0] _ptw_io_requestor_0_status_xs; // @[Manager.scala:243:21] wire [1:0] _ptw_io_requestor_0_status_fs; // @[Manager.scala:243:21] wire [1:0] _ptw_io_requestor_0_status_mpp; // @[Manager.scala:243:21] wire [1:0] _ptw_io_requestor_0_status_vs; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_spp; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_mpie; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_ube; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_spie; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_upie; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_mie; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_hie; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_sie; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_uie; // @[Manager.scala:243:21] wire _ptw_io_mem_req_valid; // @[Manager.scala:243:21] wire [39:0] _ptw_io_mem_req_bits_addr; // @[Manager.scala:243:21] wire _ptw_io_mem_req_bits_dv; // @[Manager.scala:243:21] wire _ptw_io_mem_s1_kill; // @[Manager.scala:243:21] wire _ptw_io_dpath_perf_pte_miss; // @[Manager.scala:243:21] wire _ptw_io_dpath_clock_enabled; // @[Manager.scala:243:21] wire _dcacheArb_io_requestor_0_req_ready; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_s2_nack; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_s2_nack_cause_raw; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_s2_uncached; // @[Manager.scala:238:27] wire [31:0] _dcacheArb_io_requestor_0_s2_paddr; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_resp_valid; // @[Manager.scala:238:27] wire [39:0] _dcacheArb_io_requestor_0_resp_bits_addr; // @[Manager.scala:238:27] wire [7:0] _dcacheArb_io_requestor_0_resp_bits_tag; // @[Manager.scala:238:27] wire [4:0] _dcacheArb_io_requestor_0_resp_bits_cmd; // @[Manager.scala:238:27] wire [1:0] _dcacheArb_io_requestor_0_resp_bits_size; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_resp_bits_signed; // @[Manager.scala:238:27] wire [1:0] _dcacheArb_io_requestor_0_resp_bits_dprv; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_resp_bits_dv; // @[Manager.scala:238:27] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data; // @[Manager.scala:238:27] wire [7:0] _dcacheArb_io_requestor_0_resp_bits_mask; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_resp_bits_replay; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_resp_bits_has_data; // @[Manager.scala:238:27] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data_word_bypass; // @[Manager.scala:238:27] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data_raw; // @[Manager.scala:238:27] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_store_data; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_replay_next; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_s2_xcpt_ma_ld; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_s2_xcpt_ma_st; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_s2_xcpt_pf_ld; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_s2_xcpt_pf_st; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_s2_xcpt_ae_ld; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_s2_xcpt_ae_st; // @[Manager.scala:238:27] wire [39:0] _dcacheArb_io_requestor_0_s2_gpa; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_ordered; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_store_pending; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_perf_acquire; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_perf_release; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_perf_grant; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_perf_tlbMiss; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_perf_blocked; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_req_ready; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_s2_nack; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_s2_nack_cause_raw; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_s2_uncached; // @[Manager.scala:238:27] wire [31:0] _dcacheArb_io_requestor_1_s2_paddr; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_resp_valid; // @[Manager.scala:238:27] wire [39:0] _dcacheArb_io_requestor_1_resp_bits_addr; // @[Manager.scala:238:27] wire [7:0] _dcacheArb_io_requestor_1_resp_bits_tag; // @[Manager.scala:238:27] wire [4:0] _dcacheArb_io_requestor_1_resp_bits_cmd; // @[Manager.scala:238:27] wire [1:0] _dcacheArb_io_requestor_1_resp_bits_size; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_resp_bits_signed; // @[Manager.scala:238:27] wire [1:0] _dcacheArb_io_requestor_1_resp_bits_dprv; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_resp_bits_dv; // @[Manager.scala:238:27] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data; // @[Manager.scala:238:27] wire [7:0] _dcacheArb_io_requestor_1_resp_bits_mask; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_resp_bits_replay; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_resp_bits_has_data; // @[Manager.scala:238:27] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data_word_bypass; // @[Manager.scala:238:27] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data_raw; // @[Manager.scala:238:27] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_store_data; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_replay_next; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_s2_xcpt_ma_ld; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_s2_xcpt_ma_st; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_s2_xcpt_pf_ld; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_s2_xcpt_pf_st; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_s2_xcpt_ae_ld; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_s2_xcpt_ae_st; // @[Manager.scala:238:27] wire [39:0] _dcacheArb_io_requestor_1_s2_gpa; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_ordered; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_store_pending; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_perf_acquire; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_perf_release; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_perf_grant; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_perf_tlbMiss; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_perf_blocked; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore; // @[Manager.scala:238:27] wire _dcacheArb_io_mem_req_valid; // @[Manager.scala:238:27] wire [39:0] _dcacheArb_io_mem_req_bits_addr; // @[Manager.scala:238:27] wire [7:0] _dcacheArb_io_mem_req_bits_tag; // @[Manager.scala:238:27] wire [1:0] _dcacheArb_io_mem_req_bits_dprv; // @[Manager.scala:238:27] wire _dcacheArb_io_mem_req_bits_dv; // @[Manager.scala:238:27] wire _dcacheArb_io_mem_req_bits_phys; // @[Manager.scala:238:27] wire _dcacheArb_io_mem_s1_kill; // @[Manager.scala:238:27] wire [63:0] _dcacheArb_io_mem_s1_data_data; // @[Manager.scala:238:27] wire [7:0] _dcacheArb_io_mem_s1_data_mask; // @[Manager.scala:238:27] wire _dcache_io_cpu_req_ready; // @[Manager.scala:226:61] wire _dcache_io_cpu_s2_nack; // @[Manager.scala:226:61] wire _dcache_io_cpu_s2_nack_cause_raw; // @[Manager.scala:226:61] wire _dcache_io_cpu_s2_uncached; // @[Manager.scala:226:61] wire [31:0] _dcache_io_cpu_s2_paddr; // @[Manager.scala:226:61] wire _dcache_io_cpu_resp_valid; // @[Manager.scala:226:61] wire [39:0] _dcache_io_cpu_resp_bits_addr; // @[Manager.scala:226:61] wire [7:0] _dcache_io_cpu_resp_bits_tag; // @[Manager.scala:226:61] wire [4:0] _dcache_io_cpu_resp_bits_cmd; // @[Manager.scala:226:61] wire [1:0] _dcache_io_cpu_resp_bits_size; // @[Manager.scala:226:61] wire _dcache_io_cpu_resp_bits_signed; // @[Manager.scala:226:61] wire [1:0] _dcache_io_cpu_resp_bits_dprv; // @[Manager.scala:226:61] wire _dcache_io_cpu_resp_bits_dv; // @[Manager.scala:226:61] wire [63:0] _dcache_io_cpu_resp_bits_data; // @[Manager.scala:226:61] wire [7:0] _dcache_io_cpu_resp_bits_mask; // @[Manager.scala:226:61] wire _dcache_io_cpu_resp_bits_replay; // @[Manager.scala:226:61] wire _dcache_io_cpu_resp_bits_has_data; // @[Manager.scala:226:61] wire [63:0] _dcache_io_cpu_resp_bits_data_word_bypass; // @[Manager.scala:226:61] wire [63:0] _dcache_io_cpu_resp_bits_data_raw; // @[Manager.scala:226:61] wire [63:0] _dcache_io_cpu_resp_bits_store_data; // @[Manager.scala:226:61] wire _dcache_io_cpu_replay_next; // @[Manager.scala:226:61] wire _dcache_io_cpu_s2_xcpt_ma_ld; // @[Manager.scala:226:61] wire _dcache_io_cpu_s2_xcpt_ma_st; // @[Manager.scala:226:61] wire _dcache_io_cpu_s2_xcpt_pf_ld; // @[Manager.scala:226:61] wire _dcache_io_cpu_s2_xcpt_pf_st; // @[Manager.scala:226:61] wire _dcache_io_cpu_s2_xcpt_ae_ld; // @[Manager.scala:226:61] wire _dcache_io_cpu_s2_xcpt_ae_st; // @[Manager.scala:226:61] wire [39:0] _dcache_io_cpu_s2_gpa; // @[Manager.scala:226:61] wire _dcache_io_cpu_ordered; // @[Manager.scala:226:61] wire _dcache_io_cpu_store_pending; // @[Manager.scala:226:61] wire _dcache_io_cpu_perf_acquire; // @[Manager.scala:226:61] wire _dcache_io_cpu_perf_release; // @[Manager.scala:226:61] wire _dcache_io_cpu_perf_grant; // @[Manager.scala:226:61] wire _dcache_io_cpu_perf_tlbMiss; // @[Manager.scala:226:61] wire _dcache_io_cpu_perf_blocked; // @[Manager.scala:226:61] wire _dcache_io_cpu_perf_canAcceptStoreThenLoad; // @[Manager.scala:226:61] wire _dcache_io_cpu_perf_canAcceptStoreThenRMW; // @[Manager.scala:226:61] wire _dcache_io_cpu_perf_canAcceptLoadThenLoad; // @[Manager.scala:226:61] wire _dcache_io_cpu_perf_storeBufferEmptyAfterLoad; // @[Manager.scala:226:61] wire _dcache_io_cpu_perf_storeBufferEmptyAfterStore; // @[Manager.scala:226:61] wire _dcache_io_ptw_req_valid; // @[Manager.scala:226:61] wire [26:0] _dcache_io_ptw_req_bits_bits_addr; // @[Manager.scala:226:61] wire _dcache_io_ptw_req_bits_bits_need_gpa; // @[Manager.scala:226:61] wire _rerocc_buffer_auto_out_req_valid; // @[Protocol.scala:134:35] wire [2:0] _rerocc_buffer_auto_out_req_bits_opcode; // @[Protocol.scala:134:35] wire [3:0] _rerocc_buffer_auto_out_req_bits_client_id; // @[Protocol.scala:134:35] wire _rerocc_buffer_auto_out_req_bits_manager_id; // @[Protocol.scala:134:35] wire [63:0] _rerocc_buffer_auto_out_req_bits_data; // @[Protocol.scala:134:35] wire _rerocc_buffer_auto_out_resp_ready; // @[Protocol.scala:134:35] wire _rerocc_manager_auto_in_req_ready; // @[Manager.scala:209:34] wire _rerocc_manager_auto_in_resp_valid; // @[Manager.scala:209:34] wire [2:0] _rerocc_manager_auto_in_resp_bits_opcode; // @[Manager.scala:209:34] wire [3:0] _rerocc_manager_auto_in_resp_bits_client_id; // @[Manager.scala:209:34] wire _rerocc_manager_auto_in_resp_bits_manager_id; // @[Manager.scala:209:34] wire [63:0] _rerocc_manager_auto_in_resp_bits_data; // @[Manager.scala:209:34] wire [3:0] _rerocc_manager_io_ptw_ptbr_mode; // @[Manager.scala:209:34] wire [15:0] _rerocc_manager_io_ptw_ptbr_asid; // @[Manager.scala:209:34] wire [43:0] _rerocc_manager_io_ptw_ptbr_ppn; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_sfence_valid; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_debug; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_cease; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_wfi; // @[Manager.scala:209:34] wire [31:0] _rerocc_manager_io_ptw_status_isa; // @[Manager.scala:209:34] wire [1:0] _rerocc_manager_io_ptw_status_dprv; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_dv; // @[Manager.scala:209:34] wire [1:0] _rerocc_manager_io_ptw_status_prv; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_v; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_sd; // @[Manager.scala:209:34] wire [22:0] _rerocc_manager_io_ptw_status_zero2; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_mpv; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_gva; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_mbe; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_sbe; // @[Manager.scala:209:34] wire [1:0] _rerocc_manager_io_ptw_status_sxl; // @[Manager.scala:209:34] wire [1:0] _rerocc_manager_io_ptw_status_uxl; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_sd_rv32; // @[Manager.scala:209:34] wire [7:0] _rerocc_manager_io_ptw_status_zero1; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_tsr; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_tw; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_tvm; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_mxr; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_sum; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_mprv; // @[Manager.scala:209:34] wire [1:0] _rerocc_manager_io_ptw_status_xs; // @[Manager.scala:209:34] wire [1:0] _rerocc_manager_io_ptw_status_fs; // @[Manager.scala:209:34] wire [1:0] _rerocc_manager_io_ptw_status_mpp; // @[Manager.scala:209:34] wire [1:0] _rerocc_manager_io_ptw_status_vs; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_spp; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_mpie; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_ube; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_spie; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_upie; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_mie; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_hie; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_sie; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_uie; // @[Manager.scala:209:34] wire _accumulator_cmd_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [6:0] _accumulator_cmd_q_io_deq_bits_inst_funct; // @[Decoupled.scala:362:21] wire _accumulator_cmd_q_io_deq_bits_inst_xd; // @[Decoupled.scala:362:21] wire [63:0] _accumulator_cmd_q_io_deq_bits_rs1; // @[Decoupled.scala:362:21] wire [63:0] _accumulator_cmd_q_io_deq_bits_rs2; // @[Decoupled.scala:362:21] wire [63:0] _regfile_ext_R0_data; // @[LazyRoCC.scala:124:20] wire auto_ctrl_ctrl_in_a_valid_0 = auto_ctrl_ctrl_in_a_valid; // @[Manager.scala:237:34] wire [2:0] auto_ctrl_ctrl_in_a_bits_opcode_0 = auto_ctrl_ctrl_in_a_bits_opcode; // @[Manager.scala:237:34] wire [2:0] auto_ctrl_ctrl_in_a_bits_param_0 = auto_ctrl_ctrl_in_a_bits_param; // @[Manager.scala:237:34] wire [2:0] auto_ctrl_ctrl_in_a_bits_size_0 = auto_ctrl_ctrl_in_a_bits_size; // @[Manager.scala:237:34] wire [6:0] auto_ctrl_ctrl_in_a_bits_source_0 = auto_ctrl_ctrl_in_a_bits_source; // @[Manager.scala:237:34] wire [11:0] auto_ctrl_ctrl_in_a_bits_address_0 = auto_ctrl_ctrl_in_a_bits_address; // @[Manager.scala:237:34] wire [7:0] auto_ctrl_ctrl_in_a_bits_mask_0 = auto_ctrl_ctrl_in_a_bits_mask; // @[Manager.scala:237:34] wire [63:0] auto_ctrl_ctrl_in_a_bits_data_0 = auto_ctrl_ctrl_in_a_bits_data; // @[Manager.scala:237:34] wire auto_ctrl_ctrl_in_a_bits_corrupt_0 = auto_ctrl_ctrl_in_a_bits_corrupt; // @[Manager.scala:237:34] wire auto_ctrl_ctrl_in_d_ready_0 = auto_ctrl_ctrl_in_d_ready; // @[Manager.scala:237:34] wire auto_buffer_out_a_ready_0 = auto_buffer_out_a_ready; // @[Manager.scala:237:34] wire auto_buffer_out_b_valid_0 = auto_buffer_out_b_valid; // @[Manager.scala:237:34] wire [2:0] auto_buffer_out_b_bits_opcode_0 = auto_buffer_out_b_bits_opcode; // @[Manager.scala:237:34] wire [1:0] auto_buffer_out_b_bits_param_0 = auto_buffer_out_b_bits_param; // @[Manager.scala:237:34] wire [3:0] auto_buffer_out_b_bits_size_0 = auto_buffer_out_b_bits_size; // @[Manager.scala:237:34] wire auto_buffer_out_b_bits_source_0 = auto_buffer_out_b_bits_source; // @[Manager.scala:237:34] wire [31:0] auto_buffer_out_b_bits_address_0 = auto_buffer_out_b_bits_address; // @[Manager.scala:237:34] wire [7:0] auto_buffer_out_b_bits_mask_0 = auto_buffer_out_b_bits_mask; // @[Manager.scala:237:34] wire [63:0] auto_buffer_out_b_bits_data_0 = auto_buffer_out_b_bits_data; // @[Manager.scala:237:34] wire auto_buffer_out_b_bits_corrupt_0 = auto_buffer_out_b_bits_corrupt; // @[Manager.scala:237:34] wire auto_buffer_out_c_ready_0 = auto_buffer_out_c_ready; // @[Manager.scala:237:34] wire auto_buffer_out_d_valid_0 = auto_buffer_out_d_valid; // @[Manager.scala:237:34] wire [2:0] auto_buffer_out_d_bits_opcode_0 = auto_buffer_out_d_bits_opcode; // @[Manager.scala:237:34] wire [1:0] auto_buffer_out_d_bits_param_0 = auto_buffer_out_d_bits_param; // @[Manager.scala:237:34] wire [3:0] auto_buffer_out_d_bits_size_0 = auto_buffer_out_d_bits_size; // @[Manager.scala:237:34] wire auto_buffer_out_d_bits_source_0 = auto_buffer_out_d_bits_source; // @[Manager.scala:237:34] wire [2:0] auto_buffer_out_d_bits_sink_0 = auto_buffer_out_d_bits_sink; // @[Manager.scala:237:34] wire auto_buffer_out_d_bits_denied_0 = auto_buffer_out_d_bits_denied; // @[Manager.scala:237:34] wire [63:0] auto_buffer_out_d_bits_data_0 = auto_buffer_out_d_bits_data; // @[Manager.scala:237:34] wire auto_buffer_out_d_bits_corrupt_0 = auto_buffer_out_d_bits_corrupt; // @[Manager.scala:237:34] wire auto_buffer_out_e_ready_0 = auto_buffer_out_e_ready; // @[Manager.scala:237:34] wire auto_re_ro_cc_in_req_valid_0 = auto_re_ro_cc_in_req_valid; // @[Manager.scala:237:34] wire [2:0] auto_re_ro_cc_in_req_bits_opcode_0 = auto_re_ro_cc_in_req_bits_opcode; // @[Manager.scala:237:34] wire [3:0] auto_re_ro_cc_in_req_bits_client_id_0 = auto_re_ro_cc_in_req_bits_client_id; // @[Manager.scala:237:34] wire auto_re_ro_cc_in_req_bits_manager_id_0 = auto_re_ro_cc_in_req_bits_manager_id; // @[Manager.scala:237:34] wire [63:0] auto_re_ro_cc_in_req_bits_data_0 = auto_re_ro_cc_in_req_bits_data; // @[Manager.scala:237:34] wire auto_re_ro_cc_in_resp_ready_0 = auto_re_ro_cc_in_resp_ready; // @[Manager.scala:237:34] wire [6:0] auto_rerocc_manager_id_sink_in_0 = auto_rerocc_manager_id_sink_in; // @[Manager.scala:237:34] wire xbar__requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire xbar_requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107] wire xbar__requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire xbar_requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire xbar__requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire xbar__requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire xbar__requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire xbar__requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire xbar_requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire xbar__requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire xbar__requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire xbar__requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire xbar__requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire xbar_requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire xbar__requestEIO_T_1 = 1'h1; // @[Parameters.scala:54:32] wire xbar__requestEIO_T_2 = 1'h1; // @[Parameters.scala:56:32] wire xbar__requestEIO_T_3 = 1'h1; // @[Parameters.scala:54:67] wire xbar__requestEIO_T_4 = 1'h1; // @[Parameters.scala:57:20] wire xbar_requestEIO_0_0 = 1'h1; // @[Parameters.scala:56:48] wire xbar__portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire xbar__portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire xbar__portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire xbar__portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire xbar__portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire [2:0] accumulator_io_fpu_req_bits_rm = 3'h0; // @[LazyRoCC.scala:122:7] wire [64:0] accumulator_io_fpu_req_bits_in1 = 65'h0; // @[LazyRoCC.scala:122:7] wire [64:0] accumulator_io_fpu_req_bits_in2 = 65'h0; // @[LazyRoCC.scala:122:7] wire [64:0] accumulator_io_fpu_req_bits_in3 = 65'h0; // @[LazyRoCC.scala:122:7] wire [64:0] accumulator_io_fpu_resp_bits_data = 65'h0; // @[LazyRoCC.scala:122:7] wire [32:0] xbar__requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] xbar__requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] xbar__requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] xbar__requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [8:0] xbar_beatsBO_0 = 9'h0; // @[Edges.scala:221:14] wire [39:0] accumulator_io_mem_s2_gpa = 40'h0; // @[LazyRoCC.scala:122:7] wire [31:0] accumulator_io_mem_s2_paddr = 32'h0; // @[LazyRoCC.scala:122:7] wire [4:0] accumulator_io_mem_req_bits_cmd = 5'h0; // @[LazyRoCC.scala:122:7] wire [4:0] accumulator_io_fpu_resp_bits_exc = 5'h0; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_mem_req_bits_size = 2'h3; // @[LazyRoCC.scala:122:7] wire [63:0] accumulator_io_mem_req_bits_data = 64'h0; // @[LazyRoCC.scala:122:7] wire [63:0] accumulator_io_mem_s1_data_data = 64'h0; // @[LazyRoCC.scala:122:7] wire [7:0] accumulator_io_mem_req_bits_mask = 8'h0; // @[LazyRoCC.scala:122:7] wire [7:0] accumulator_io_mem_s1_data_mask = 8'h0; // @[LazyRoCC.scala:122:7] wire auto_ctrl_ctrl_in_d_bits_sink = 1'h0; // @[Manager.scala:237:34] wire auto_ctrl_ctrl_in_d_bits_denied = 1'h0; // @[Manager.scala:237:34] wire auto_ctrl_ctrl_in_d_bits_corrupt = 1'h0; // @[Manager.scala:237:34] wire accumulator_io_mem_req_bits_signed = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_req_bits_phys = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_req_bits_no_resp = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_req_bits_no_alloc = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_req_bits_no_xcpt = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_s1_kill = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_s2_nack = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_s2_nack_cause_raw = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_s2_kill = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_s2_uncached = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_replay_next = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_s2_xcpt_ma_ld = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_s2_xcpt_ma_st = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_s2_xcpt_pf_ld = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_s2_xcpt_pf_st = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_s2_xcpt_gf_ld = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_s2_xcpt_gf_st = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_s2_xcpt_ae_ld = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_s2_xcpt_ae_st = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_s2_gpa_is_pte = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_ordered = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_store_pending = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_perf_acquire = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_perf_release = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_perf_grant = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_perf_tlbMiss = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_perf_blocked = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_keep_clock_enabled = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_clock_enabled = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_interrupt = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_exception = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_ready = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_valid = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_bits_ldst = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_bits_wen = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_bits_ren1 = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_bits_ren2 = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_bits_ren3 = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_bits_swap12 = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_bits_swap23 = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_bits_fromint = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_bits_toint = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_bits_fastpipe = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_bits_fma = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_bits_div = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_bits_sqrt = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_bits_wflags = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_bits_vec = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_resp_ready = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_resp_valid = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator__busy_WIRE_0 = 1'h0; // @[LazyRoCC.scala:125:29] wire accumulator__busy_WIRE_1 = 1'h0; // @[LazyRoCC.scala:125:29] wire accumulator__busy_WIRE_2 = 1'h0; // @[LazyRoCC.scala:125:29] wire accumulator__busy_WIRE_3 = 1'h0; // @[LazyRoCC.scala:125:29] wire xbar_auto_anon_in_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_c_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_c_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire xbar_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire xbar_anonOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire xbar_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire xbar_anonIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire xbar_in_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire xbar_in_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire xbar_out_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire xbar_out_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire xbar__requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire xbar__requestDOI_T = 1'h0; // @[Parameters.scala:54:10] wire xbar__requestEIO_T = 1'h0; // @[Parameters.scala:54:10] wire xbar_portsAOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire xbar_portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire widget_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire widget_anonOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire widget_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire widget_anonIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire [1:0] auto_ctrl_ctrl_in_d_bits_param = 2'h0; // @[Manager.scala:237:34] wire [1:0] accumulator_io_fpu_req_bits_typeTagIn = 2'h0; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_fpu_req_bits_typeTagOut = 2'h0; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_fpu_req_bits_fmaCmd = 2'h0; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_fpu_req_bits_typ = 2'h0; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_fpu_req_bits_fmt = 2'h0; // @[LazyRoCC.scala:122:7] wire reRoCCNodeIn_req_ready; // @[MixedNode.scala:551:17] wire reRoCCNodeIn_req_valid = auto_re_ro_cc_in_req_valid_0; // @[Manager.scala:237:34] wire [2:0] reRoCCNodeIn_req_bits_opcode = auto_re_ro_cc_in_req_bits_opcode_0; // @[Manager.scala:237:34] wire [3:0] reRoCCNodeIn_req_bits_client_id = auto_re_ro_cc_in_req_bits_client_id_0; // @[Manager.scala:237:34] wire reRoCCNodeIn_req_bits_manager_id = auto_re_ro_cc_in_req_bits_manager_id_0; // @[Manager.scala:237:34] wire [63:0] reRoCCNodeIn_req_bits_data = auto_re_ro_cc_in_req_bits_data_0; // @[Manager.scala:237:34] wire reRoCCNodeIn_resp_ready = auto_re_ro_cc_in_resp_ready_0; // @[Manager.scala:237:34] wire reRoCCNodeIn_resp_valid; // @[MixedNode.scala:551:17] wire [2:0] reRoCCNodeIn_resp_bits_opcode; // @[MixedNode.scala:551:17] wire [3:0] reRoCCNodeIn_resp_bits_client_id; // @[MixedNode.scala:551:17] wire reRoCCNodeIn_resp_bits_manager_id; // @[MixedNode.scala:551:17] wire [63:0] reRoCCNodeIn_resp_bits_data; // @[MixedNode.scala:551:17] wire [6:0] reroccManagerIdSinkNodeIn = auto_rerocc_manager_id_sink_in_0; // @[Manager.scala:237:34] wire auto_ctrl_ctrl_in_a_ready_0; // @[Manager.scala:237:34] wire [2:0] auto_ctrl_ctrl_in_d_bits_opcode_0; // @[Manager.scala:237:34] wire [2:0] auto_ctrl_ctrl_in_d_bits_size_0; // @[Manager.scala:237:34] wire [6:0] auto_ctrl_ctrl_in_d_bits_source_0; // @[Manager.scala:237:34] wire [63:0] auto_ctrl_ctrl_in_d_bits_data_0; // @[Manager.scala:237:34] wire auto_ctrl_ctrl_in_d_valid_0; // @[Manager.scala:237:34] wire [2:0] auto_buffer_out_a_bits_opcode_0; // @[Manager.scala:237:34] wire [2:0] auto_buffer_out_a_bits_param_0; // @[Manager.scala:237:34] wire [3:0] auto_buffer_out_a_bits_size_0; // @[Manager.scala:237:34] wire auto_buffer_out_a_bits_source_0; // @[Manager.scala:237:34] wire [31:0] auto_buffer_out_a_bits_address_0; // @[Manager.scala:237:34] wire [7:0] auto_buffer_out_a_bits_mask_0; // @[Manager.scala:237:34] wire [63:0] auto_buffer_out_a_bits_data_0; // @[Manager.scala:237:34] wire auto_buffer_out_a_bits_corrupt_0; // @[Manager.scala:237:34] wire auto_buffer_out_a_valid_0; // @[Manager.scala:237:34] wire auto_buffer_out_b_ready_0; // @[Manager.scala:237:34] wire [2:0] auto_buffer_out_c_bits_opcode_0; // @[Manager.scala:237:34] wire [2:0] auto_buffer_out_c_bits_param_0; // @[Manager.scala:237:34] wire [3:0] auto_buffer_out_c_bits_size_0; // @[Manager.scala:237:34] wire auto_buffer_out_c_bits_source_0; // @[Manager.scala:237:34] wire [31:0] auto_buffer_out_c_bits_address_0; // @[Manager.scala:237:34] wire [63:0] auto_buffer_out_c_bits_data_0; // @[Manager.scala:237:34] wire auto_buffer_out_c_bits_corrupt_0; // @[Manager.scala:237:34] wire auto_buffer_out_c_valid_0; // @[Manager.scala:237:34] wire auto_buffer_out_d_ready_0; // @[Manager.scala:237:34] wire [2:0] auto_buffer_out_e_bits_sink_0; // @[Manager.scala:237:34] wire auto_buffer_out_e_valid_0; // @[Manager.scala:237:34] wire auto_re_ro_cc_in_req_ready_0; // @[Manager.scala:237:34] wire [2:0] auto_re_ro_cc_in_resp_bits_opcode_0; // @[Manager.scala:237:34] wire [3:0] auto_re_ro_cc_in_resp_bits_client_id_0; // @[Manager.scala:237:34] wire auto_re_ro_cc_in_resp_bits_manager_id_0; // @[Manager.scala:237:34] wire [63:0] auto_re_ro_cc_in_resp_bits_data_0; // @[Manager.scala:237:34] wire auto_re_ro_cc_in_resp_valid_0; // @[Manager.scala:237:34] wire accumulator__io_resp_valid_T_4; // @[LazyRoCC.scala:164:53] wire accumulator__io_mem_req_valid_T_4; // @[LazyRoCC.scala:177:56] wire accumulator__io_busy_T_3; // @[LazyRoCC.scala:171:24] wire [6:0] accumulator_io_cmd_bits_inst_funct; // @[LazyRoCC.scala:122:7] wire [4:0] accumulator_io_cmd_bits_inst_rs2; // @[LazyRoCC.scala:122:7] wire [4:0] accumulator_io_cmd_bits_inst_rs1; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_inst_xd; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_inst_xs1; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_inst_xs2; // @[LazyRoCC.scala:122:7] wire [4:0] accumulator_io_cmd_bits_inst_rd; // @[LazyRoCC.scala:122:7] wire [6:0] accumulator_io_cmd_bits_inst_opcode; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_debug; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_cease; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_wfi; // @[LazyRoCC.scala:122:7] wire [31:0] accumulator_io_cmd_bits_status_isa; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_cmd_bits_status_dprv; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_dv; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_cmd_bits_status_prv; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_v; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_sd; // @[LazyRoCC.scala:122:7] wire [22:0] accumulator_io_cmd_bits_status_zero2; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_mpv; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_gva; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_mbe; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_sbe; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_cmd_bits_status_sxl; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_cmd_bits_status_uxl; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_sd_rv32; // @[LazyRoCC.scala:122:7] wire [7:0] accumulator_io_cmd_bits_status_zero1; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_tsr; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_tw; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_tvm; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_mxr; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_sum; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_mprv; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_cmd_bits_status_xs; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_cmd_bits_status_fs; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_cmd_bits_status_mpp; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_cmd_bits_status_vs; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_spp; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_mpie; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_ube; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_spie; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_upie; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_mie; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_hie; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_sie; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_uie; // @[LazyRoCC.scala:122:7] wire [63:0] accumulator_io_cmd_bits_rs1; // @[LazyRoCC.scala:122:7] wire [63:0] accumulator_io_cmd_bits_rs2; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_ready; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_valid; // @[LazyRoCC.scala:122:7] wire [4:0] accumulator_io_resp_bits_rd; // @[LazyRoCC.scala:122:7] wire [63:0] accumulator_io_resp_bits_data; // @[LazyRoCC.scala:122:7] wire accumulator_io_resp_ready; // @[LazyRoCC.scala:122:7] wire accumulator_io_resp_valid; // @[LazyRoCC.scala:122:7] wire [39:0] accumulator_io_mem_req_bits_addr; // @[LazyRoCC.scala:122:7] wire [7:0] accumulator_io_mem_req_bits_tag; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_mem_req_bits_dprv; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_req_bits_dv; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_req_ready; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_req_valid; // @[LazyRoCC.scala:122:7] wire [39:0] accumulator_io_mem_resp_bits_addr; // @[LazyRoCC.scala:122:7] wire [7:0] accumulator_io_mem_resp_bits_tag; // @[LazyRoCC.scala:122:7] wire [4:0] accumulator_io_mem_resp_bits_cmd; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_mem_resp_bits_size; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_resp_bits_signed; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_mem_resp_bits_dprv; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_resp_bits_dv; // @[LazyRoCC.scala:122:7] wire [63:0] accumulator_io_mem_resp_bits_data; // @[LazyRoCC.scala:122:7] wire [7:0] accumulator_io_mem_resp_bits_mask; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_resp_bits_replay; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_resp_bits_has_data; // @[LazyRoCC.scala:122:7] wire [63:0] accumulator_io_mem_resp_bits_data_word_bypass; // @[LazyRoCC.scala:122:7] wire [63:0] accumulator_io_mem_resp_bits_data_raw; // @[LazyRoCC.scala:122:7] wire [63:0] accumulator_io_mem_resp_bits_store_data; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_resp_valid; // @[LazyRoCC.scala:122:7] wire accumulator_io_busy; // @[LazyRoCC.scala:122:7] reg accumulator_busy_0; // @[LazyRoCC.scala:125:21] reg accumulator_busy_1; // @[LazyRoCC.scala:125:21] reg accumulator_busy_2; // @[LazyRoCC.scala:125:21] reg accumulator_busy_3; // @[LazyRoCC.scala:125:21] wire [1:0] accumulator_addr = _accumulator_cmd_q_io_deq_bits_rs2[1:0]; // @[Decoupled.scala:362:21] wire accumulator_doWrite = _accumulator_cmd_q_io_deq_bits_inst_funct == 7'h0; // @[Decoupled.scala:362:21] wire accumulator_doRead = _accumulator_cmd_q_io_deq_bits_inst_funct == 7'h1; // @[Decoupled.scala:362:21] wire accumulator_doLoad = _accumulator_cmd_q_io_deq_bits_inst_funct == 7'h2; // @[Decoupled.scala:362:21] wire accumulator_doAccum = _accumulator_cmd_q_io_deq_bits_inst_funct == 7'h3; // @[Decoupled.scala:362:21] wire [1:0] accumulator_memRespTag = accumulator_io_mem_resp_bits_tag[1:0]; // @[LazyRoCC.scala:122:7, :134:40] wire [64:0] accumulator__wdata_T = {1'h0, _regfile_ext_R0_data} + {1'h0, _accumulator_cmd_q_io_deq_bits_rs1}; // @[Decoupled.scala:362:21] wire [63:0] accumulator__wdata_T_1 = accumulator__wdata_T[63:0]; // @[LazyRoCC.scala:139:42] wire [63:0] accumulator_wdata = accumulator_doWrite ? _accumulator_cmd_q_io_deq_bits_rs1 : accumulator__wdata_T_1; // @[Decoupled.scala:362:21] wire accumulator__q_io_deq_ready_T_4; // @[LazyRoCC.scala:160:40] wire accumulator__stallLoad_T = ~accumulator_io_mem_req_ready; // @[LazyRoCC.scala:122:7, :157:29] wire accumulator_stallLoad = accumulator_doLoad & accumulator__stallLoad_T; // @[LazyRoCC.scala:132:22, :157:{26,29}] wire accumulator__stallResp_T = ~accumulator_io_resp_ready; // @[LazyRoCC.scala:122:7, :158:29] wire accumulator_stallResp = _accumulator_cmd_q_io_deq_bits_inst_xd & accumulator__stallResp_T; // @[Decoupled.scala:362:21] wire [3:0] _GEN = {{accumulator_busy_3}, {accumulator_busy_2}, {accumulator_busy_1}, {accumulator_busy_0}}; // @[LazyRoCC.scala:125:21, :160:16] wire accumulator__q_io_deq_ready_T = ~_GEN[accumulator_addr]; // @[LazyRoCC.scala:129:26, :160:16] wire accumulator__q_io_deq_ready_T_1 = ~accumulator_stallLoad; // @[LazyRoCC.scala:157:26, :160:29] wire accumulator__q_io_deq_ready_T_2 = accumulator__q_io_deq_ready_T & accumulator__q_io_deq_ready_T_1; // @[LazyRoCC.scala:160:{16,26,29}] wire accumulator__q_io_deq_ready_T_3 = ~accumulator_stallResp; // @[LazyRoCC.scala:158:26, :160:43] assign accumulator__q_io_deq_ready_T_4 = accumulator__q_io_deq_ready_T_2 & accumulator__q_io_deq_ready_T_3; // @[LazyRoCC.scala:160:{26,40,43}] wire accumulator__io_resp_valid_T = _accumulator_cmd_q_io_deq_valid & _accumulator_cmd_q_io_deq_bits_inst_xd; // @[Decoupled.scala:362:21] wire accumulator__io_resp_valid_T_1 = ~_GEN[accumulator_addr]; // @[LazyRoCC.scala:129:26, :160:16, :164:43] wire accumulator__io_resp_valid_T_2 = accumulator__io_resp_valid_T & accumulator__io_resp_valid_T_1; // @[LazyRoCC.scala:164:{30,40,43}] wire accumulator__io_resp_valid_T_3 = ~accumulator_stallLoad; // @[LazyRoCC.scala:157:26, :160:29, :164:56] assign accumulator__io_resp_valid_T_4 = accumulator__io_resp_valid_T_2 & accumulator__io_resp_valid_T_3; // @[LazyRoCC.scala:164:{40,53,56}] assign accumulator_io_resp_valid = accumulator__io_resp_valid_T_4; // @[LazyRoCC.scala:122:7, :164:53] wire accumulator__io_busy_T = accumulator_busy_0 \| accumulator_busy_1; // @[LazyRoCC.scala:125:21, :171:40] wire accumulator__io_busy_T_1 = accumulator__io_busy_T \| accumulator_busy_2; // @[LazyRoCC.scala:125:21, :171:40] wire accumulator__io_busy_T_2 = accumulator__io_busy_T_1 \| accumulator_busy_3; // @[LazyRoCC.scala:125:21, :171:40] assign accumulator__io_busy_T_3 = _accumulator_cmd_q_io_deq_valid \| accumulator__io_busy_T_2; // @[Decoupled.scala:362:21] assign accumulator_io_busy = accumulator__io_busy_T_3; // @[LazyRoCC.scala:122:7, :171:24] wire accumulator__io_mem_req_valid_T = _accumulator_cmd_q_io_deq_valid & accumulator_doLoad; // @[Decoupled.scala:362:21] wire accumulator__io_mem_req_valid_T_1 = ~_GEN[accumulator_addr]; // @[LazyRoCC.scala:129:26, :160:16, :177:46] wire accumulator__io_mem_req_valid_T_2 = accumulator__io_mem_req_valid_T & accumulator__io_mem_req_valid_T_1; // @[LazyRoCC.scala:177:{33,43,46}] wire accumulator__io_mem_req_valid_T_3 = ~accumulator_stallResp; // @[LazyRoCC.scala:158:26, :160:43, :177:59] assign accumulator__io_mem_req_valid_T_4 = accumulator__io_mem_req_valid_T_2 & accumulator__io_mem_req_valid_T_3; // @[LazyRoCC.scala:177:{43,56,59}] assign accumulator_io_mem_req_valid = accumulator__io_mem_req_valid_T_4; // @[LazyRoCC.scala:122:7, :177:56] assign accumulator_io_mem_req_bits_addr = _accumulator_cmd_q_io_deq_bits_rs1[39:0]; // @[Decoupled.scala:362:21] assign accumulator_io_mem_req_bits_tag = {6'h0, accumulator_addr}; // @[LazyRoCC.scala:122:7, :129:26, :131:22, :179:23] wire xbar_anonIn_a_ready; // @[MixedNode.scala:551:17] wire widget_auto_anon_out_a_ready = xbar_auto_anon_in_a_ready; // @[Xbar.scala:74:9] wire widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire xbar_anonIn_a_valid = xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire [2:0] widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] xbar_anonIn_a_bits_opcode = xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] xbar_anonIn_a_bits_param = xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire [3:0] xbar_anonIn_a_bits_size = xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire xbar_anonIn_a_bits_source = xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [31:0] xbar_anonIn_a_bits_address = xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire [7:0] xbar_anonIn_a_bits_mask = xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire [63:0] xbar_anonIn_a_bits_data = xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire widget_auto_anon_out_b_ready; // @[WidthWidget.scala:27:9] wire xbar_anonIn_b_ready = xbar_auto_anon_in_b_ready; // @[Xbar.scala:74:9] wire xbar_anonIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] xbar_anonIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire widget_auto_anon_out_b_valid = xbar_auto_anon_in_b_valid; // @[Xbar.scala:74:9] wire [1:0] xbar_anonIn_b_bits_param; // @[MixedNode.scala:551:17] wire [2:0] widget_auto_anon_out_b_bits_opcode = xbar_auto_anon_in_b_bits_opcode; // @[Xbar.scala:74:9] wire [3:0] xbar_anonIn_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] widget_auto_anon_out_b_bits_param = xbar_auto_anon_in_b_bits_param; // @[Xbar.scala:74:9] wire xbar_anonIn_b_bits_source; // @[MixedNode.scala:551:17] wire [3:0] widget_auto_anon_out_b_bits_size = xbar_auto_anon_in_b_bits_size; // @[Xbar.scala:74:9] wire [31:0] xbar_anonIn_b_bits_address; // @[MixedNode.scala:551:17] wire widget_auto_anon_out_b_bits_source = xbar_auto_anon_in_b_bits_source; // @[Xbar.scala:74:9] wire [7:0] xbar_anonIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [31:0] widget_auto_anon_out_b_bits_address = xbar_auto_anon_in_b_bits_address; // @[Xbar.scala:74:9] wire [63:0] xbar_anonIn_b_bits_data; // @[MixedNode.scala:551:17] wire [7:0] widget_auto_anon_out_b_bits_mask = xbar_auto_anon_in_b_bits_mask; // @[Xbar.scala:74:9] wire xbar_anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] widget_auto_anon_out_b_bits_data = xbar_auto_anon_in_b_bits_data; // @[Xbar.scala:74:9] wire xbar_anonIn_c_ready; // @[MixedNode.scala:551:17] wire widget_auto_anon_out_b_bits_corrupt = xbar_auto_anon_in_b_bits_corrupt; // @[Xbar.scala:74:9] wire widget_auto_anon_out_c_ready = xbar_auto_anon_in_c_ready; // @[Xbar.scala:74:9] wire widget_auto_anon_out_c_valid; // @[WidthWidget.scala:27:9] wire xbar_anonIn_c_valid = xbar_auto_anon_in_c_valid; // @[Xbar.scala:74:9] wire [2:0] widget_auto_anon_out_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] xbar_anonIn_c_bits_opcode = xbar_auto_anon_in_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] widget_auto_anon_out_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] xbar_anonIn_c_bits_param = xbar_auto_anon_in_c_bits_param; // @[Xbar.scala:74:9] wire [3:0] widget_auto_anon_out_c_bits_size; // @[WidthWidget.scala:27:9] wire [3:0] xbar_anonIn_c_bits_size = xbar_auto_anon_in_c_bits_size; // @[Xbar.scala:74:9] wire widget_auto_anon_out_c_bits_source; // @[WidthWidget.scala:27:9] wire xbar_anonIn_c_bits_source = xbar_auto_anon_in_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] widget_auto_anon_out_c_bits_address; // @[WidthWidget.scala:27:9] wire [31:0] xbar_anonIn_c_bits_address = xbar_auto_anon_in_c_bits_address; // @[Xbar.scala:74:9] wire [63:0] widget_auto_anon_out_c_bits_data; // @[WidthWidget.scala:27:9] wire [63:0] xbar_anonIn_c_bits_data = xbar_auto_anon_in_c_bits_data; // @[Xbar.scala:74:9] wire widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] wire xbar_anonIn_d_ready = xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire xbar_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] xbar_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire widget_auto_anon_out_d_valid = xbar_auto_anon_in_d_valid; // @[Xbar.scala:74:9] wire [1:0] xbar_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] widget_auto_anon_out_d_bits_opcode = xbar_auto_anon_in_d_bits_opcode; // @[Xbar.scala:74:9] wire [3:0] xbar_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] widget_auto_anon_out_d_bits_param = xbar_auto_anon_in_d_bits_param; // @[Xbar.scala:74:9] wire xbar_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] widget_auto_anon_out_d_bits_size = xbar_auto_anon_in_d_bits_size; // @[Xbar.scala:74:9] wire [2:0] xbar_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire widget_auto_anon_out_d_bits_source = xbar_auto_anon_in_d_bits_source; // @[Xbar.scala:74:9] wire xbar_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] widget_auto_anon_out_d_bits_sink = xbar_auto_anon_in_d_bits_sink; // @[Xbar.scala:74:9] wire [63:0] xbar_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire widget_auto_anon_out_d_bits_denied = xbar_auto_anon_in_d_bits_denied; // @[Xbar.scala:74:9] wire xbar_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] widget_auto_anon_out_d_bits_data = xbar_auto_anon_in_d_bits_data; // @[Xbar.scala:74:9] wire xbar_anonIn_e_ready; // @[MixedNode.scala:551:17] wire widget_auto_anon_out_d_bits_corrupt = xbar_auto_anon_in_d_bits_corrupt; // @[Xbar.scala:74:9] wire widget_auto_anon_out_e_ready = xbar_auto_anon_in_e_ready; // @[Xbar.scala:74:9] wire widget_auto_anon_out_e_valid; // @[WidthWidget.scala:27:9] wire xbar_anonIn_e_valid = xbar_auto_anon_in_e_valid; // @[Xbar.scala:74:9] wire [2:0] widget_auto_anon_out_e_bits_sink; // @[WidthWidget.scala:27:9] wire [2:0] xbar_anonIn_e_bits_sink = xbar_auto_anon_in_e_bits_sink; // @[Xbar.scala:74:9] wire xbar_anonOut_a_ready = xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire xbar_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] xbar_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] xbar_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] xbar_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire xbar_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] xbar_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] xbar_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] xbar_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire xbar_anonOut_b_ready; // @[MixedNode.scala:542:17] wire xbar_anonOut_b_valid = xbar_auto_anon_out_b_valid; // @[Xbar.scala:74:9] wire [2:0] xbar_anonOut_b_bits_opcode = xbar_auto_anon_out_b_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] xbar_anonOut_b_bits_param = xbar_auto_anon_out_b_bits_param; // @[Xbar.scala:74:9] wire [3:0] xbar_anonOut_b_bits_size = xbar_auto_anon_out_b_bits_size; // @[Xbar.scala:74:9] wire xbar_anonOut_b_bits_source = xbar_auto_anon_out_b_bits_source; // @[Xbar.scala:74:9] wire [31:0] xbar_anonOut_b_bits_address = xbar_auto_anon_out_b_bits_address; // @[Xbar.scala:74:9] wire [7:0] xbar_anonOut_b_bits_mask = xbar_auto_anon_out_b_bits_mask; // @[Xbar.scala:74:9] wire [63:0] xbar_anonOut_b_bits_data = xbar_auto_anon_out_b_bits_data; // @[Xbar.scala:74:9] wire xbar_anonOut_b_bits_corrupt = xbar_auto_anon_out_b_bits_corrupt; // @[Xbar.scala:74:9] wire xbar_anonOut_c_ready = xbar_auto_anon_out_c_ready; // @[Xbar.scala:74:9] wire xbar_anonOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] xbar_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] xbar_anonOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] xbar_anonOut_c_bits_size; // @[MixedNode.scala:542:17] wire xbar_anonOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] xbar_anonOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] xbar_anonOut_c_bits_data; // @[MixedNode.scala:542:17] wire xbar_anonOut_d_ready; // @[MixedNode.scala:542:17] wire xbar_anonOut_d_valid = xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire [2:0] xbar_anonOut_d_bits_opcode = xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] xbar_anonOut_d_bits_param = xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] xbar_anonOut_d_bits_size = xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire xbar_anonOut_d_bits_source = xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire [2:0] xbar_anonOut_d_bits_sink = xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9] wire xbar_anonOut_d_bits_denied = xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] xbar_anonOut_d_bits_data = xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire xbar_anonOut_d_bits_corrupt = xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire xbar_anonOut_e_ready = xbar_auto_anon_out_e_ready; // @[Xbar.scala:74:9] wire xbar_anonOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] xbar_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] wire [2:0] xbar_auto_anon_out_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_out_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] xbar_auto_anon_out_a_bits_size; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] xbar_auto_anon_out_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] xbar_auto_anon_out_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] xbar_auto_anon_out_a_bits_data; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_a_valid; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_b_ready; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_out_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_out_c_bits_param; // @[Xbar.scala:74:9] wire [3:0] xbar_auto_anon_out_c_bits_size; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] xbar_auto_anon_out_c_bits_address; // @[Xbar.scala:74:9] wire [63:0] xbar_auto_anon_out_c_bits_data; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_c_valid; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_d_ready; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_out_e_bits_sink; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_e_valid; // @[Xbar.scala:74:9] wire xbar_out_0_a_ready = xbar_anonOut_a_ready; // @[Xbar.scala:216:19] wire xbar_out_0_a_valid; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_valid = xbar_anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_bits_opcode = xbar_anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] xbar_out_0_a_bits_param; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_bits_param = xbar_anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] xbar_out_0_a_bits_size; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_bits_size = xbar_anonOut_a_bits_size; // @[Xbar.scala:74:9] wire xbar_out_0_a_bits_source; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_bits_source = xbar_anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] xbar_out_0_a_bits_address; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_bits_address = xbar_anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_bits_mask = xbar_anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] xbar_out_0_a_bits_data; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_bits_data = xbar_anonOut_a_bits_data; // @[Xbar.scala:74:9] wire xbar_out_0_b_ready; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_b_ready = xbar_anonOut_b_ready; // @[Xbar.scala:74:9] wire xbar_out_0_b_valid = xbar_anonOut_b_valid; // @[Xbar.scala:216:19] wire [2:0] xbar_out_0_b_bits_opcode = xbar_anonOut_b_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] xbar_out_0_b_bits_param = xbar_anonOut_b_bits_param; // @[Xbar.scala:216:19] wire [3:0] xbar_out_0_b_bits_size = xbar_anonOut_b_bits_size; // @[Xbar.scala:216:19] wire xbar_out_0_b_bits_source = xbar_anonOut_b_bits_source; // @[Xbar.scala:216:19] wire [31:0] xbar_out_0_b_bits_address = xbar_anonOut_b_bits_address; // @[Xbar.scala:216:19] wire [7:0] xbar_out_0_b_bits_mask = xbar_anonOut_b_bits_mask; // @[Xbar.scala:216:19] wire [63:0] xbar_out_0_b_bits_data = xbar_anonOut_b_bits_data; // @[Xbar.scala:216:19] wire xbar_out_0_b_bits_corrupt = xbar_anonOut_b_bits_corrupt; // @[Xbar.scala:216:19] wire xbar_out_0_c_ready = xbar_anonOut_c_ready; // @[Xbar.scala:216:19] wire xbar_out_0_c_valid; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_c_valid = xbar_anonOut_c_valid; // @[Xbar.scala:74:9] wire [2:0] xbar_out_0_c_bits_opcode; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_c_bits_opcode = xbar_anonOut_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] xbar_out_0_c_bits_param; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_c_bits_param = xbar_anonOut_c_bits_param; // @[Xbar.scala:74:9] wire [3:0] xbar_out_0_c_bits_size; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_c_bits_size = xbar_anonOut_c_bits_size; // @[Xbar.scala:74:9] wire xbar_out_0_c_bits_source; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_c_bits_source = xbar_anonOut_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] xbar_out_0_c_bits_address; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_c_bits_address = xbar_anonOut_c_bits_address; // @[Xbar.scala:74:9] wire [63:0] xbar_out_0_c_bits_data; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_c_bits_data = xbar_anonOut_c_bits_data; // @[Xbar.scala:74:9] wire xbar_out_0_d_ready; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_d_ready = xbar_anonOut_d_ready; // @[Xbar.scala:74:9] wire xbar_out_0_d_valid = xbar_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] xbar_out_0_d_bits_opcode = xbar_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] xbar_out_0_d_bits_param = xbar_anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [3:0] xbar_out_0_d_bits_size = xbar_anonOut_d_bits_size; // @[Xbar.scala:216:19] wire xbar_out_0_d_bits_source = xbar_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire [2:0] xbar__out_0_d_bits_sink_T = xbar_anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire xbar_out_0_d_bits_denied = xbar_anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] xbar_out_0_d_bits_data = xbar_anonOut_d_bits_data; // @[Xbar.scala:216:19] wire xbar_out_0_d_bits_corrupt = xbar_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire xbar_out_0_e_ready = xbar_anonOut_e_ready; // @[Xbar.scala:216:19] wire xbar_out_0_e_valid; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_e_valid = xbar_anonOut_e_valid; // @[Xbar.scala:74:9] wire [2:0] xbar__anonOut_e_bits_sink_T; // @[Xbar.scala:156:69] assign xbar_auto_anon_out_e_bits_sink = xbar_anonOut_e_bits_sink; // @[Xbar.scala:74:9] wire xbar_in_0_a_ready; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_a_ready = xbar_anonIn_a_ready; // @[Xbar.scala:74:9] wire xbar_in_0_a_valid = xbar_anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] xbar_in_0_a_bits_opcode = xbar_anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] xbar_in_0_a_bits_param = xbar_anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] xbar_in_0_a_bits_size = xbar_anonIn_a_bits_size; // @[Xbar.scala:159:18] wire xbar__in_0_a_bits_source_T = xbar_anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [31:0] xbar_in_0_a_bits_address = xbar_anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] xbar_in_0_a_bits_mask = xbar_anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] xbar_in_0_a_bits_data = xbar_anonIn_a_bits_data; // @[Xbar.scala:159:18] wire xbar_in_0_b_ready = xbar_anonIn_b_ready; // @[Xbar.scala:159:18] wire xbar_in_0_b_valid; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_b_valid = xbar_anonIn_b_valid; // @[Xbar.scala:74:9] wire [2:0] xbar_in_0_b_bits_opcode; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_b_bits_opcode = xbar_anonIn_b_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] xbar_in_0_b_bits_param; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_b_bits_param = xbar_anonIn_b_bits_param; // @[Xbar.scala:74:9] wire [3:0] xbar_in_0_b_bits_size; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_b_bits_size = xbar_anonIn_b_bits_size; // @[Xbar.scala:74:9] wire xbar__anonIn_b_bits_source_T; // @[Xbar.scala:156:69] assign xbar_auto_anon_in_b_bits_source = xbar_anonIn_b_bits_source; // @[Xbar.scala:74:9] wire [31:0] xbar_in_0_b_bits_address; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_b_bits_address = xbar_anonIn_b_bits_address; // @[Xbar.scala:74:9] wire [7:0] xbar_in_0_b_bits_mask; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_b_bits_mask = xbar_anonIn_b_bits_mask; // @[Xbar.scala:74:9] wire [63:0] xbar_in_0_b_bits_data; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_b_bits_data = xbar_anonIn_b_bits_data; // @[Xbar.scala:74:9] wire xbar_in_0_b_bits_corrupt; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_b_bits_corrupt = xbar_anonIn_b_bits_corrupt; // @[Xbar.scala:74:9] wire xbar_in_0_c_ready; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_c_ready = xbar_anonIn_c_ready; // @[Xbar.scala:74:9] wire xbar_in_0_c_valid = xbar_anonIn_c_valid; // @[Xbar.scala:159:18] wire [2:0] xbar_in_0_c_bits_opcode = xbar_anonIn_c_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] xbar_in_0_c_bits_param = xbar_anonIn_c_bits_param; // @[Xbar.scala:159:18] wire [3:0] xbar_in_0_c_bits_size = xbar_anonIn_c_bits_size; // @[Xbar.scala:159:18] wire xbar__in_0_c_bits_source_T = xbar_anonIn_c_bits_source; // @[Xbar.scala:187:55] wire [31:0] xbar_in_0_c_bits_address = xbar_anonIn_c_bits_address; // @[Xbar.scala:159:18] wire [63:0] xbar_in_0_c_bits_data = xbar_anonIn_c_bits_data; // @[Xbar.scala:159:18] wire xbar_in_0_d_ready = xbar_anonIn_d_ready; // @[Xbar.scala:159:18] wire xbar_in_0_d_valid; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_d_valid = xbar_anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_d_bits_opcode = xbar_anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] xbar_in_0_d_bits_param; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_d_bits_param = xbar_anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] xbar_in_0_d_bits_size; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_d_bits_size = xbar_anonIn_d_bits_size; // @[Xbar.scala:74:9] wire xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign xbar_auto_anon_in_d_bits_source = xbar_anonIn_d_bits_source; // @[Xbar.scala:74:9] wire [2:0] xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_d_bits_sink = xbar_anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_d_bits_denied = xbar_anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] xbar_in_0_d_bits_data; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_d_bits_data = xbar_anonIn_d_bits_data; // @[Xbar.scala:74:9] wire xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_d_bits_corrupt = xbar_anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire xbar_in_0_e_ready; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_e_ready = xbar_anonIn_e_ready; // @[Xbar.scala:74:9] wire xbar_in_0_e_valid = xbar_anonIn_e_valid; // @[Xbar.scala:159:18] wire [2:0] xbar_in_0_e_bits_sink = xbar_anonIn_e_bits_sink; // @[Xbar.scala:159:18] wire xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] assign xbar_anonIn_a_ready = xbar_in_0_a_ready; // @[Xbar.scala:159:18] wire xbar__portsAOI_filtered_0_valid_T_1 = xbar_in_0_a_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] xbar_portsAOI_filtered_0_bits_opcode = xbar_in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] xbar_portsAOI_filtered_0_bits_param = xbar_in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] xbar_portsAOI_filtered_0_bits_size = xbar_in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire xbar_portsAOI_filtered_0_bits_source = xbar_in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] xbar__requestAIO_T = xbar_in_0_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] xbar_portsAOI_filtered_0_bits_address = xbar_in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] xbar_portsAOI_filtered_0_bits_mask = xbar_in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] xbar_portsAOI_filtered_0_bits_data = xbar_in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire xbar_portsBIO_filtered_0_ready = xbar_in_0_b_ready; // @[Xbar.scala:159:18, :352:24] wire xbar_portsBIO_filtered_0_valid; // @[Xbar.scala:352:24] assign xbar_anonIn_b_valid = xbar_in_0_b_valid; // @[Xbar.scala:159:18] wire [2:0] xbar_portsBIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign xbar_anonIn_b_bits_opcode = xbar_in_0_b_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] xbar_portsBIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign xbar_anonIn_b_bits_param = xbar_in_0_b_bits_param; // @[Xbar.scala:159:18] wire [3:0] xbar_portsBIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign xbar_anonIn_b_bits_size = xbar_in_0_b_bits_size; // @[Xbar.scala:159:18] wire xbar_portsBIO_filtered_0_bits_source; // @[Xbar.scala:352:24] assign xbar__anonIn_b_bits_source_T = xbar_in_0_b_bits_source; // @[Xbar.scala:156:69, :159:18] wire [31:0] xbar_portsBIO_filtered_0_bits_address; // @[Xbar.scala:352:24] assign xbar_anonIn_b_bits_address = xbar_in_0_b_bits_address; // @[Xbar.scala:159:18] wire [7:0] xbar_portsBIO_filtered_0_bits_mask; // @[Xbar.scala:352:24] assign xbar_anonIn_b_bits_mask = xbar_in_0_b_bits_mask; // @[Xbar.scala:159:18] wire [63:0] xbar_portsBIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign xbar_anonIn_b_bits_data = xbar_in_0_b_bits_data; // @[Xbar.scala:159:18] wire xbar_portsBIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign xbar_anonIn_b_bits_corrupt = xbar_in_0_b_bits_corrupt; // @[Xbar.scala:159:18] wire xbar_portsCOI_filtered_0_ready; // @[Xbar.scala:352:24] assign xbar_anonIn_c_ready = xbar_in_0_c_ready; // @[Xbar.scala:159:18] wire xbar__portsCOI_filtered_0_valid_T_1 = xbar_in_0_c_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] xbar_portsCOI_filtered_0_bits_opcode = xbar_in_0_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] xbar_portsCOI_filtered_0_bits_param = xbar_in_0_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] xbar_portsCOI_filtered_0_bits_size = xbar_in_0_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire xbar_portsCOI_filtered_0_bits_source = xbar_in_0_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] xbar__requestCIO_T = xbar_in_0_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] xbar_portsCOI_filtered_0_bits_address = xbar_in_0_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [63:0] xbar_portsCOI_filtered_0_bits_data = xbar_in_0_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire xbar_portsDIO_filtered_0_ready = xbar_in_0_d_ready; // @[Xbar.scala:159:18, :352:24] wire xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign xbar_anonIn_d_valid = xbar_in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign xbar_anonIn_d_bits_opcode = xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign xbar_anonIn_d_bits_param = xbar_in_0_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign xbar_anonIn_d_bits_size = xbar_in_0_d_bits_size; // @[Xbar.scala:159:18] wire xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24] assign xbar__anonIn_d_bits_source_T = xbar_in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18] wire [2:0] xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24] assign xbar_anonIn_d_bits_sink = xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18] wire xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24] assign xbar_anonIn_d_bits_denied = xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign xbar_anonIn_d_bits_data = xbar_in_0_d_bits_data; // @[Xbar.scala:159:18] wire xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign xbar_anonIn_d_bits_corrupt = xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18] wire xbar_portsEOI_filtered_0_ready; // @[Xbar.scala:352:24] assign xbar_anonIn_e_ready = xbar_in_0_e_ready; // @[Xbar.scala:159:18] wire xbar__portsEOI_filtered_0_valid_T_1 = xbar_in_0_e_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] xbar__requestEIO_uncommonBits_T = xbar_in_0_e_bits_sink; // @[Xbar.scala:159:18] wire [2:0] xbar_portsEOI_filtered_0_bits_sink = xbar_in_0_e_bits_sink; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_a_bits_source = xbar__in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign xbar_anonIn_b_bits_source = xbar__anonIn_b_bits_source_T; // @[Xbar.scala:156:69] assign xbar_in_0_c_bits_source = xbar__in_0_c_bits_source_T; // @[Xbar.scala:159:18, :187:55] assign xbar_anonIn_d_bits_source = xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign xbar_portsAOI_filtered_0_ready = xbar_out_0_a_ready; // @[Xbar.scala:216:19, :352:24] wire xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign xbar_anonOut_a_valid = xbar_out_0_a_valid; // @[Xbar.scala:216:19] assign xbar_anonOut_a_bits_opcode = xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign xbar_anonOut_a_bits_param = xbar_out_0_a_bits_param; // @[Xbar.scala:216:19] assign xbar_anonOut_a_bits_size = xbar_out_0_a_bits_size; // @[Xbar.scala:216:19] assign xbar_anonOut_a_bits_source = xbar_out_0_a_bits_source; // @[Xbar.scala:216:19] assign xbar_anonOut_a_bits_address = xbar_out_0_a_bits_address; // @[Xbar.scala:216:19] assign xbar_anonOut_a_bits_mask = xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19] assign xbar_anonOut_a_bits_data = xbar_out_0_a_bits_data; // @[Xbar.scala:216:19] assign xbar_anonOut_b_ready = xbar_out_0_b_ready; // @[Xbar.scala:216:19] wire xbar__portsBIO_filtered_0_valid_T_1 = xbar_out_0_b_valid; // @[Xbar.scala:216:19, :355:40] assign xbar_portsBIO_filtered_0_bits_opcode = xbar_out_0_b_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign xbar_portsBIO_filtered_0_bits_param = xbar_out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24] assign xbar_portsBIO_filtered_0_bits_size = xbar_out_0_b_bits_size; // @[Xbar.scala:216:19, :352:24] wire xbar__requestBOI_uncommonBits_T = xbar_out_0_b_bits_source; // @[Xbar.scala:216:19] assign xbar_portsBIO_filtered_0_bits_source = xbar_out_0_b_bits_source; // @[Xbar.scala:216:19, :352:24] assign xbar_portsBIO_filtered_0_bits_address = xbar_out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24] assign xbar_portsBIO_filtered_0_bits_mask = xbar_out_0_b_bits_mask; // @[Xbar.scala:216:19, :352:24] assign xbar_portsBIO_filtered_0_bits_data = xbar_out_0_b_bits_data; // @[Xbar.scala:216:19, :352:24] assign xbar_portsBIO_filtered_0_bits_corrupt = xbar_out_0_b_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign xbar_portsCOI_filtered_0_ready = xbar_out_0_c_ready; // @[Xbar.scala:216:19, :352:24] wire xbar_portsCOI_filtered_0_valid; // @[Xbar.scala:352:24] assign xbar_anonOut_c_valid = xbar_out_0_c_valid; // @[Xbar.scala:216:19] assign xbar_anonOut_c_bits_opcode = xbar_out_0_c_bits_opcode; // @[Xbar.scala:216:19] assign xbar_anonOut_c_bits_param = xbar_out_0_c_bits_param; // @[Xbar.scala:216:19] assign xbar_anonOut_c_bits_size = xbar_out_0_c_bits_size; // @[Xbar.scala:216:19] assign xbar_anonOut_c_bits_source = xbar_out_0_c_bits_source; // @[Xbar.scala:216:19] assign xbar_anonOut_c_bits_address = xbar_out_0_c_bits_address; // @[Xbar.scala:216:19] assign xbar_anonOut_c_bits_data = xbar_out_0_c_bits_data; // @[Xbar.scala:216:19] assign xbar_anonOut_d_ready = xbar_out_0_d_ready; // @[Xbar.scala:216:19] wire xbar__portsDIO_filtered_0_valid_T_1 = xbar_out_0_d_valid; // @[Xbar.scala:216:19, :355:40] assign xbar_portsDIO_filtered_0_bits_opcode = xbar_out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign xbar_portsDIO_filtered_0_bits_param = xbar_out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign xbar_portsDIO_filtered_0_bits_size = xbar_out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire xbar__requestDOI_uncommonBits_T = xbar_out_0_d_bits_source; // @[Xbar.scala:216:19] assign xbar_portsDIO_filtered_0_bits_source = xbar_out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign xbar_portsDIO_filtered_0_bits_sink = xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign xbar_portsDIO_filtered_0_bits_denied = xbar_out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign xbar_portsDIO_filtered_0_bits_data = xbar_out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign xbar_portsDIO_filtered_0_bits_corrupt = xbar_out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign xbar_portsEOI_filtered_0_ready = xbar_out_0_e_ready; // @[Xbar.scala:216:19, :352:24] wire xbar_portsEOI_filtered_0_valid; // @[Xbar.scala:352:24] assign xbar_anonOut_e_valid = xbar_out_0_e_valid; // @[Xbar.scala:216:19] assign xbar__anonOut_e_bits_sink_T = xbar_out_0_e_bits_sink; // @[Xbar.scala:156:69, :216:19] assign xbar_out_0_d_bits_sink = xbar__out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] assign xbar_anonOut_e_bits_sink = xbar__anonOut_e_bits_sink_T; // @[Xbar.scala:156:69] wire [32:0] xbar__requestAIO_T_1 = {1'h0, xbar__requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] xbar__requestCIO_T_1 = {1'h0, xbar__requestCIO_T}; // @[Parameters.scala:137:{31,41}] wire xbar_requestBOI_uncommonBits = xbar__requestBOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire xbar_requestDOI_uncommonBits = xbar__requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [2:0] xbar_requestEIO_uncommonBits = xbar__requestEIO_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] xbar__beatsAI_decode_T = 27'hFFF << xbar_in_0_a_bits_size; // @[package.scala:243:71] wire [11:0] xbar__beatsAI_decode_T_1 = xbar__beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] xbar__beatsAI_decode_T_2 = ~xbar__beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] xbar_beatsAI_decode = xbar__beatsAI_decode_T_2[11:3]; // @[package.scala:243:46] wire xbar__beatsAI_opdata_T = xbar_in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire xbar_beatsAI_opdata = ~xbar__beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] xbar_beatsAI_0 = xbar_beatsAI_opdata ? xbar_beatsAI_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] xbar__beatsBO_decode_T = 27'hFFF << xbar_out_0_b_bits_size; // @[package.scala:243:71] wire [11:0] xbar__beatsBO_decode_T_1 = xbar__beatsBO_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] xbar__beatsBO_decode_T_2 = ~xbar__beatsBO_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] xbar_beatsBO_decode = xbar__beatsBO_decode_T_2[11:3]; // @[package.scala:243:46] wire xbar__beatsBO_opdata_T = xbar_out_0_b_bits_opcode[2]; // @[Xbar.scala:216:19] wire xbar_beatsBO_opdata = ~xbar__beatsBO_opdata_T; // @[Edges.scala:97:{28,37}] wire [26:0] xbar__beatsCI_decode_T = 27'hFFF << xbar_in_0_c_bits_size; // @[package.scala:243:71] wire [11:0] xbar__beatsCI_decode_T_1 = xbar__beatsCI_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] xbar__beatsCI_decode_T_2 = ~xbar__beatsCI_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] xbar_beatsCI_decode = xbar__beatsCI_decode_T_2[11:3]; // @[package.scala:243:46] wire xbar_beatsCI_opdata = xbar_in_0_c_bits_opcode[0]; // @[Xbar.scala:159:18] wire [8:0] xbar_beatsCI_0 = xbar_beatsCI_opdata ? xbar_beatsCI_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] wire [26:0] xbar__beatsDO_decode_T = 27'hFFF << xbar_out_0_d_bits_size; // @[package.scala:243:71] wire [11:0] xbar__beatsDO_decode_T_1 = xbar__beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] xbar__beatsDO_decode_T_2 = ~xbar__beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] xbar_beatsDO_decode = xbar__beatsDO_decode_T_2[11:3]; // @[package.scala:243:46] wire xbar_beatsDO_opdata = xbar_out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [8:0] xbar_beatsDO_0 = xbar_beatsDO_opdata ? xbar_beatsDO_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] assign xbar_in_0_a_ready = xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign xbar_out_0_a_valid = xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_a_bits_opcode = xbar_portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_a_bits_param = xbar_portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_a_bits_size = xbar_portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_a_bits_source = xbar_portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_a_bits_address = xbar_portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_a_bits_mask = xbar_portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_a_bits_data = xbar_portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign xbar_portsAOI_filtered_0_valid = xbar__portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign xbar_out_0_b_ready = xbar_portsBIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] assign xbar_in_0_b_valid = xbar_portsBIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_b_bits_opcode = xbar_portsBIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_b_bits_param = xbar_portsBIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_b_bits_size = xbar_portsBIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_b_bits_source = xbar_portsBIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_b_bits_address = xbar_portsBIO_filtered_0_bits_address; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_b_bits_mask = xbar_portsBIO_filtered_0_bits_mask; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_b_bits_data = xbar_portsBIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_b_bits_corrupt = xbar_portsBIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] assign xbar_portsBIO_filtered_0_valid = xbar__portsBIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign xbar_in_0_c_ready = xbar_portsCOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign xbar_out_0_c_valid = xbar_portsCOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_c_bits_opcode = xbar_portsCOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_c_bits_param = xbar_portsCOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_c_bits_size = xbar_portsCOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_c_bits_source = xbar_portsCOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_c_bits_address = xbar_portsCOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_c_bits_data = xbar_portsCOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign xbar_portsCOI_filtered_0_valid = xbar__portsCOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign xbar_out_0_d_ready = xbar_portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] assign xbar_in_0_d_valid = xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_d_bits_opcode = xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_d_bits_param = xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_d_bits_size = xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_d_bits_source = xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_d_bits_sink = xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_d_bits_denied = xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_d_bits_data = xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_d_bits_corrupt = xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] assign xbar_portsDIO_filtered_0_valid = xbar__portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign xbar_in_0_e_ready = xbar_portsEOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign xbar_out_0_e_valid = xbar_portsEOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_e_bits_sink = xbar_portsEOI_filtered_0_bits_sink; // @[Xbar.scala:216:19, :352:24] assign xbar_portsEOI_filtered_0_valid = xbar__portsEOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire widget_anonIn_a_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_a_valid = widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_a_bits_opcode = widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_a_bits_param = widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonIn_a_bits_size = widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonIn_a_bits_source = widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonIn_a_bits_address = widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_anonIn_a_bits_mask = widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonIn_a_bits_data = widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonIn_b_ready = widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9] wire widget_anonIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] widget_anonIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] widget_anonIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] widget_anonIn_b_bits_size; // @[MixedNode.scala:551:17] wire widget_anonIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] widget_anonIn_b_bits_address; // @[MixedNode.scala:551:17] wire [7:0] widget_anonIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] widget_anonIn_b_bits_data; // @[MixedNode.scala:551:17] wire widget_anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire widget_anonIn_c_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_c_valid = widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_c_bits_opcode = widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_c_bits_param = widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonIn_c_bits_size = widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonIn_c_bits_source = widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonIn_c_bits_address = widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonIn_c_bits_data = widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonIn_d_ready = widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire widget_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire widget_anonIn_e_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_e_valid = widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_e_bits_sink = widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_ready = widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_valid; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_a_valid = widget_auto_anon_out_a_valid; // @[Xbar.scala:74:9] wire [2:0] widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_a_bits_opcode = widget_auto_anon_out_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_a_bits_param = widget_auto_anon_out_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_a_bits_size = widget_auto_anon_out_a_bits_size; // @[Xbar.scala:74:9] wire widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_a_bits_source = widget_auto_anon_out_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_a_bits_address = widget_auto_anon_out_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_a_bits_mask = widget_auto_anon_out_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_a_bits_data = widget_auto_anon_out_a_bits_data; // @[Xbar.scala:74:9] wire widget_anonOut_b_ready; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_b_ready = widget_auto_anon_out_b_ready; // @[Xbar.scala:74:9] wire widget_anonOut_b_valid = widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_b_bits_opcode = widget_auto_anon_out_b_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonOut_b_bits_param = widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonOut_b_bits_size = widget_auto_anon_out_b_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonOut_b_bits_source = widget_auto_anon_out_b_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonOut_b_bits_address = widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_anonOut_b_bits_mask = widget_auto_anon_out_b_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonOut_b_bits_data = widget_auto_anon_out_b_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonOut_b_bits_corrupt = widget_auto_anon_out_b_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_anonOut_c_ready = widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_c_valid; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_c_valid = widget_auto_anon_out_c_valid; // @[Xbar.scala:74:9] wire [2:0] widget_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_c_bits_opcode = widget_auto_anon_out_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] widget_anonOut_c_bits_param; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_c_bits_param = widget_auto_anon_out_c_bits_param; // @[Xbar.scala:74:9] wire [3:0] widget_anonOut_c_bits_size; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_c_bits_size = widget_auto_anon_out_c_bits_size; // @[Xbar.scala:74:9] wire widget_anonOut_c_bits_source; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_c_bits_source = widget_auto_anon_out_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] widget_anonOut_c_bits_address; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_c_bits_address = widget_auto_anon_out_c_bits_address; // @[Xbar.scala:74:9] wire [63:0] widget_anonOut_c_bits_data; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_c_bits_data = widget_auto_anon_out_c_bits_data; // @[Xbar.scala:74:9] wire widget_anonOut_d_ready; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_d_ready = widget_auto_anon_out_d_ready; // @[Xbar.scala:74:9] wire widget_anonOut_d_valid = widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_d_bits_opcode = widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonOut_d_bits_param = widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonOut_d_bits_size = widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_source = widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_d_bits_sink = widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_denied = widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonOut_d_bits_data = widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_corrupt = widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_anonOut_e_ready = widget_auto_anon_out_e_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_e_valid; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_e_valid = widget_auto_anon_out_e_valid; // @[Xbar.scala:74:9] wire [2:0] widget_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_e_bits_sink = widget_auto_anon_out_e_bits_sink; // @[Xbar.scala:74:9] wire widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_b_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_b_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_b_bits_size; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_b_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_in_b_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_b_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_e_ready; // @[WidthWidget.scala:27:9] assign widget_anonIn_a_ready = widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_a_valid = widget_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_opcode = widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_param = widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_size = widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_source = widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_address = widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_mask = widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_data = widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_b_ready = widget_anonOut_b_ready; // @[WidthWidget.scala:27:9] assign widget_anonIn_b_valid = widget_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_opcode = widget_anonOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_param = widget_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_size = widget_anonOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_source = widget_anonOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_address = widget_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_mask = widget_anonOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_data = widget_anonOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_corrupt = widget_anonOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_c_ready = widget_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_c_valid = widget_anonOut_c_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_opcode = widget_anonOut_c_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_param = widget_anonOut_c_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_size = widget_anonOut_c_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_source = widget_anonOut_c_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_address = widget_anonOut_c_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_data = widget_anonOut_c_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_d_ready = widget_anonOut_d_ready; // @[WidthWidget.scala:27:9] assign widget_anonIn_d_valid = widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_opcode = widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_param = widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_size = widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_source = widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_sink = widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_denied = widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_data = widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_corrupt = widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_e_ready = widget_anonOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_e_valid = widget_anonOut_e_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_e_bits_sink = widget_anonOut_e_bits_sink; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_a_ready = widget_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_a_valid = widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_opcode = widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_param = widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_size = widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_source = widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_address = widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_mask = widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_data = widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_b_ready = widget_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_in_b_valid = widget_anonIn_b_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_opcode = widget_anonIn_b_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_param = widget_anonIn_b_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_size = widget_anonIn_b_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_source = widget_anonIn_b_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_address = widget_anonIn_b_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_mask = widget_anonIn_b_bits_mask; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_data = widget_anonIn_b_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_corrupt = widget_anonIn_b_bits_corrupt; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_c_ready = widget_anonIn_c_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_c_valid = widget_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_opcode = widget_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_param = widget_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_size = widget_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_source = widget_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_address = widget_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_data = widget_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_d_ready = widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_in_d_valid = widget_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_opcode = widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_param = widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_size = widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_source = widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_sink = widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_denied = widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_data = widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_corrupt = widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_e_ready = widget_anonIn_e_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_e_valid = widget_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_e_bits_sink = widget_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign reRoCCNodeIn_req_ready = reRoCCNodeOut_req_ready; // @[MixedNode.scala:542:17, :551:17] assign reRoCCNodeIn_resp_valid = reRoCCNodeOut_resp_valid; // @[MixedNode.scala:542:17, :551:17] assign reRoCCNodeIn_resp_bits_opcode = reRoCCNodeOut_resp_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign reRoCCNodeIn_resp_bits_client_id = reRoCCNodeOut_resp_bits_client_id; // @[MixedNode.scala:542:17, :551:17] assign reRoCCNodeIn_resp_bits_manager_id = reRoCCNodeOut_resp_bits_manager_id; // @[MixedNode.scala:542:17, :551:17] wire [2:0] reRoCCNodeOut_req_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] reRoCCNodeOut_req_bits_client_id; // @[MixedNode.scala:542:17] wire reRoCCNodeOut_req_bits_manager_id; // @[MixedNode.scala:542:17] wire [63:0] reRoCCNodeOut_req_bits_data; // @[MixedNode.scala:542:17] assign reRoCCNodeIn_resp_bits_data = reRoCCNodeOut_resp_bits_data; // @[MixedNode.scala:542:17, :551:17] wire reRoCCNodeOut_req_valid; // @[MixedNode.scala:542:17] wire reRoCCNodeOut_resp_ready; // @[MixedNode.scala:542:17] assign auto_re_ro_cc_in_req_ready_0 = reRoCCNodeIn_req_ready; // @[Manager.scala:237:34] assign reRoCCNodeOut_req_valid = reRoCCNodeIn_req_valid; // @[MixedNode.scala:542:17, :551:17] assign reRoCCNodeOut_req_bits_opcode = reRoCCNodeIn_req_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign reRoCCNodeOut_req_bits_client_id = reRoCCNodeIn_req_bits_client_id; // @[MixedNode.scala:542:17, :551:17] assign reRoCCNodeOut_req_bits_manager_id = reRoCCNodeIn_req_bits_manager_id; // @[MixedNode.scala:542:17, :551:17] assign reRoCCNodeOut_req_bits_data = reRoCCNodeIn_req_bits_data; // @[MixedNode.scala:542:17, :551:17] assign reRoCCNodeOut_resp_ready = reRoCCNodeIn_resp_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_re_ro_cc_in_resp_valid_0 = reRoCCNodeIn_resp_valid; // @[Manager.scala:237:34] assign auto_re_ro_cc_in_resp_bits_opcode_0 = reRoCCNodeIn_resp_bits_opcode; // @[Manager.scala:237:34] assign auto_re_ro_cc_in_resp_bits_client_id_0 = reRoCCNodeIn_resp_bits_client_id; // @[Manager.scala:237:34] assign auto_re_ro_cc_in_resp_bits_manager_id_0 = reRoCCNodeIn_resp_bits_manager_id; // @[Manager.scala:237:34] assign auto_re_ro_cc_in_resp_bits_data_0 = reRoCCNodeIn_resp_bits_data; // @[Manager.scala:237:34] wire accumulator__T_3 = accumulator_io_mem_req_ready & accumulator_io_mem_req_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Manager.scala:237:34] if (reset) begin // @[Manager.scala:237:34] accumulator_busy_0 <= 1'h0; // @[LazyRoCC.scala:125:21] accumulator_busy_1 <= 1'h0; // @[LazyRoCC.scala:125:21] accumulator_busy_2 <= 1'h0; // @[LazyRoCC.scala:125:21] accumulator_busy_3 <= 1'h0; // @[LazyRoCC.scala:125:21] end else begin // @[Manager.scala:237:34] accumulator_busy_0 <= accumulator__T_3 & accumulator_addr == 2'h0 \| ~(accumulator_io_mem_resp_valid & accumulator_memRespTag == 2'h0) & accumulator_busy_0; // @[Decoupled.scala:51:35] accumulator_busy_1 <= accumulator__T_3 & accumulator_addr == 2'h1 \| ~(accumulator_io_mem_resp_valid & accumulator_memRespTag == 2'h1) & accumulator_busy_1; // @[Decoupled.scala:51:35] accumulator_busy_2 <= accumulator__T_3 & accumulator_addr == 2'h2 \| ~(accumulator_io_mem_resp_valid & accumulator_memRespTag == 2'h2) & accumulator_busy_2; // @[Decoupled.scala:51:35] accumulator_busy_3 <= accumulator__T_3 & (&accumulator_addr) \| ~(accumulator_io_mem_resp_valid & (&accumulator_memRespTag)) & accumulator_busy_3; // @[Decoupled.scala:51:35] end always @(posedge) regfile_4x64 regfile_ext ( // @[LazyRoCC.scala:124:20] .R0_addr (accumulator_addr), // @[LazyRoCC.scala:129:26] .R0_en (1'h1), // @[Manager.scala:237:34] .R0_clk (clock), .R0_data (_regfile_ext_R0_data), .W0_addr (accumulator_memRespTag), // @[LazyRoCC.scala:134:40] .W0_en (accumulator_io_mem_resp_valid), // @[LazyRoCC.scala:122:7] .W0_clk (clock), .W0_data (accumulator_io_mem_resp_bits_data), // @[LazyRoCC.scala:122:7] .W1_addr (accumulator_addr), // @[LazyRoCC.scala:129:26] .W1_en (accumulator__q_io_deq_ready_T_4 & _accumulator_cmd_q_io_deq_valid & (accumulator_doWrite \| accumulator_doAccum)), // @[Decoupled.scala:51:35, :362:21] .W1_clk (clock), .W1_data (accumulator_wdata) // @[LazyRoCC.scala:139:18] ); // @[LazyRoCC.scala:124:20] assign accumulator_io_resp_bits_data = _regfile_ext_R0_data; // @[LazyRoCC.scala:122:7, :124:20] Queue2_RoCCCommand_4 accumulator_cmd_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (accumulator_io_cmd_ready), .io_enq_valid (accumulator_io_cmd_valid), // @[LazyRoCC.scala:122:7] .io_enq_bits_inst_funct (accumulator_io_cmd_bits_inst_funct), // @[LazyRoCC.scala:122:7] .io_enq_bits_inst_rs2 (accumulator_io_cmd_bits_inst_rs2), // @[LazyRoCC.scala:122:7] .io_enq_bits_inst_rs1 (accumulator_io_cmd_bits_inst_rs1), // @[LazyRoCC.scala:122:7] .io_enq_bits_inst_xd (accumulator_io_cmd_bits_inst_xd), // @[LazyRoCC.scala:122:7] .io_enq_bits_inst_xs1 (accumulator_io_cmd_bits_inst_xs1), // @[LazyRoCC.scala:122:7] .io_enq_bits_inst_xs2 (accumulator_io_cmd_bits_inst_xs2), // @[LazyRoCC.scala:122:7] .io_enq_bits_inst_rd (accumulator_io_cmd_bits_inst_rd), // @[LazyRoCC.scala:122:7] .io_enq_bits_inst_opcode (accumulator_io_cmd_bits_inst_opcode), // @[LazyRoCC.scala:122:7] .io_enq_bits_rs1 (accumulator_io_cmd_bits_rs1), // @[LazyRoCC.scala:122:7] .io_enq_bits_rs2 (accumulator_io_cmd_bits_rs2), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_debug (accumulator_io_cmd_bits_status_debug), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_cease (accumulator_io_cmd_bits_status_cease), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_wfi (accumulator_io_cmd_bits_status_wfi), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_isa (accumulator_io_cmd_bits_status_isa), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_dprv (accumulator_io_cmd_bits_status_dprv), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_dv (accumulator_io_cmd_bits_status_dv), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_prv (accumulator_io_cmd_bits_status_prv), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_v (accumulator_io_cmd_bits_status_v), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_sd (accumulator_io_cmd_bits_status_sd), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_zero2 (accumulator_io_cmd_bits_status_zero2), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_mpv (accumulator_io_cmd_bits_status_mpv), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_gva (accumulator_io_cmd_bits_status_gva), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_mbe (accumulator_io_cmd_bits_status_mbe), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_sbe (accumulator_io_cmd_bits_status_sbe), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_sxl (accumulator_io_cmd_bits_status_sxl), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_uxl (accumulator_io_cmd_bits_status_uxl), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_sd_rv32 (accumulator_io_cmd_bits_status_sd_rv32), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_zero1 (accumulator_io_cmd_bits_status_zero1), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_tsr (accumulator_io_cmd_bits_status_tsr), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_tw (accumulator_io_cmd_bits_status_tw), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_tvm (accumulator_io_cmd_bits_status_tvm), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_mxr (accumulator_io_cmd_bits_status_mxr), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_sum (accumulator_io_cmd_bits_status_sum), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_mprv (accumulator_io_cmd_bits_status_mprv), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_xs (accumulator_io_cmd_bits_status_xs), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_fs (accumulator_io_cmd_bits_status_fs), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_mpp (accumulator_io_cmd_bits_status_mpp), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_vs (accumulator_io_cmd_bits_status_vs), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_spp (accumulator_io_cmd_bits_status_spp), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_mpie (accumulator_io_cmd_bits_status_mpie), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_ube (accumulator_io_cmd_bits_status_ube), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_spie (accumulator_io_cmd_bits_status_spie), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_upie (accumulator_io_cmd_bits_status_upie), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_mie (accumulator_io_cmd_bits_status_mie), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_hie (accumulator_io_cmd_bits_status_hie), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_sie (accumulator_io_cmd_bits_status_sie), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_uie (accumulator_io_cmd_bits_status_uie), // @[LazyRoCC.scala:122:7] .io_deq_ready (accumulator__q_io_deq_ready_T_4), // @[LazyRoCC.scala:160:40] .io_deq_valid (_accumulator_cmd_q_io_deq_valid), .io_deq_bits_inst_funct (_accumulator_cmd_q_io_deq_bits_inst_funct), .io_deq_bits_inst_xd (_accumulator_cmd_q_io_deq_bits_inst_xd), .io_deq_bits_inst_rd (accumulator_io_resp_bits_rd), .io_deq_bits_rs1 (_accumulator_cmd_q_io_deq_bits_rs1), .io_deq_bits_rs2 (_accumulator_cmd_q_io_deq_bits_rs2), .io_deq_bits_status_dprv (accumulator_io_mem_req_bits_dprv), .io_deq_bits_status_dv (accumulator_io_mem_req_bits_dv) ); // @[Decoupled.scala:362:21] ReRoCCManager_3 rerocc_manager ( // @[Manager.scala:209:34] .clock (clock), .reset (reset), .auto_in_req_ready (_rerocc_manager_auto_in_req_ready), .auto_in_req_valid (_rerocc_buffer_auto_out_req_valid), // @[Protocol.scala:134:35] .auto_in_req_bits_opcode (_rerocc_buffer_auto_out_req_bits_opcode), // @[Protocol.scala:134:35] .auto_in_req_bits_client_id (_rerocc_buffer_auto_out_req_bits_client_id), // @[Protocol.scala:134:35] .auto_in_req_bits_manager_id (_rerocc_buffer_auto_out_req_bits_manager_id), // @[Protocol.scala:134:35] .auto_in_req_bits_data (_rerocc_buffer_auto_out_req_bits_data), // @[Protocol.scala:134:35] .auto_in_resp_ready (_rerocc_buffer_auto_out_resp_ready), // @[Protocol.scala:134:35] .auto_in_resp_valid (_rerocc_manager_auto_in_resp_valid), .auto_in_resp_bits_opcode (_rerocc_manager_auto_in_resp_bits_opcode), .auto_in_resp_bits_client_id (_rerocc_manager_auto_in_resp_bits_client_id), .auto_in_resp_bits_manager_id (_rerocc_manager_auto_in_resp_bits_manager_id), .auto_in_resp_bits_data (_rerocc_manager_auto_in_resp_bits_data), .io_manager_id (reroccManagerIdSinkNodeIn[2:0]), // @[Manager.scala:262:41] .io_cmd_ready (accumulator_io_cmd_ready), // @[LazyRoCC.scala:122:7] .io_cmd_valid (accumulator_io_cmd_valid), .io_cmd_bits_inst_funct (accumulator_io_cmd_bits_inst_funct), .io_cmd_bits_inst_rs2 (accumulator_io_cmd_bits_inst_rs2), .io_cmd_bits_inst_rs1 (accumulator_io_cmd_bits_inst_rs1), .io_cmd_bits_inst_xd (accumulator_io_cmd_bits_inst_xd), .io_cmd_bits_inst_xs1 (accumulator_io_cmd_bits_inst_xs1), .io_cmd_bits_inst_xs2 (accumulator_io_cmd_bits_inst_xs2), .io_cmd_bits_inst_rd (accumulator_io_cmd_bits_inst_rd), .io_cmd_bits_inst_opcode (accumulator_io_cmd_bits_inst_opcode), .io_cmd_bits_rs1 (accumulator_io_cmd_bits_rs1), .io_cmd_bits_rs2 (accumulator_io_cmd_bits_rs2), .io_cmd_bits_status_debug (accumulator_io_cmd_bits_status_debug), .io_cmd_bits_status_cease (accumulator_io_cmd_bits_status_cease), .io_cmd_bits_status_wfi (accumulator_io_cmd_bits_status_wfi), .io_cmd_bits_status_isa (accumulator_io_cmd_bits_status_isa), .io_cmd_bits_status_dprv (accumulator_io_cmd_bits_status_dprv), .io_cmd_bits_status_dv (accumulator_io_cmd_bits_status_dv), .io_cmd_bits_status_prv (accumulator_io_cmd_bits_status_prv), .io_cmd_bits_status_v (accumulator_io_cmd_bits_status_v), .io_cmd_bits_status_sd (accumulator_io_cmd_bits_status_sd), .io_cmd_bits_status_zero2 (accumulator_io_cmd_bits_status_zero2), .io_cmd_bits_status_mpv (accumulator_io_cmd_bits_status_mpv), .io_cmd_bits_status_gva (accumulator_io_cmd_bits_status_gva), .io_cmd_bits_status_mbe (accumulator_io_cmd_bits_status_mbe), .io_cmd_bits_status_sbe (accumulator_io_cmd_bits_status_sbe), .io_cmd_bits_status_sxl (accumulator_io_cmd_bits_status_sxl), .io_cmd_bits_status_uxl (accumulator_io_cmd_bits_status_uxl), .io_cmd_bits_status_sd_rv32 (accumulator_io_cmd_bits_status_sd_rv32), .io_cmd_bits_status_zero1 (accumulator_io_cmd_bits_status_zero1), .io_cmd_bits_status_tsr (accumulator_io_cmd_bits_status_tsr), .io_cmd_bits_status_tw (accumulator_io_cmd_bits_status_tw), .io_cmd_bits_status_tvm (accumulator_io_cmd_bits_status_tvm), .io_cmd_bits_status_mxr (accumulator_io_cmd_bits_status_mxr), .io_cmd_bits_status_sum (accumulator_io_cmd_bits_status_sum), .io_cmd_bits_status_mprv (accumulator_io_cmd_bits_status_mprv), .io_cmd_bits_status_xs (accumulator_io_cmd_bits_status_xs), .io_cmd_bits_status_fs (accumulator_io_cmd_bits_status_fs), .io_cmd_bits_status_mpp (accumulator_io_cmd_bits_status_mpp), .io_cmd_bits_status_vs (accumulator_io_cmd_bits_status_vs), .io_cmd_bits_status_spp (accumulator_io_cmd_bits_status_spp), .io_cmd_bits_status_mpie (accumulator_io_cmd_bits_status_mpie), .io_cmd_bits_status_ube (accumulator_io_cmd_bits_status_ube), .io_cmd_bits_status_spie (accumulator_io_cmd_bits_status_spie), .io_cmd_bits_status_upie (accumulator_io_cmd_bits_status_upie), .io_cmd_bits_status_mie (accumulator_io_cmd_bits_status_mie), .io_cmd_bits_status_hie (accumulator_io_cmd_bits_status_hie), .io_cmd_bits_status_sie (accumulator_io_cmd_bits_status_sie), .io_cmd_bits_status_uie (accumulator_io_cmd_bits_status_uie), .io_resp_ready (accumulator_io_resp_ready), .io_resp_valid (accumulator_io_resp_valid), // @[LazyRoCC.scala:122:7] .io_resp_bits_rd (accumulator_io_resp_bits_rd), // @[LazyRoCC.scala:122:7] .io_resp_bits_data (accumulator_io_resp_bits_data), // @[LazyRoCC.scala:122:7] .io_busy (accumulator_io_busy), // @[LazyRoCC.scala:122:7] .io_ptw_ptbr_mode (_rerocc_manager_io_ptw_ptbr_mode), .io_ptw_ptbr_asid (_rerocc_manager_io_ptw_ptbr_asid), .io_ptw_ptbr_ppn (_rerocc_manager_io_ptw_ptbr_ppn), .io_ptw_sfence_valid (_rerocc_manager_io_ptw_sfence_valid), .io_ptw_status_debug (_rerocc_manager_io_ptw_status_debug), .io_ptw_status_cease (_rerocc_manager_io_ptw_status_cease), .io_ptw_status_wfi (_rerocc_manager_io_ptw_status_wfi), .io_ptw_status_isa (_rerocc_manager_io_ptw_status_isa), .io_ptw_status_dprv (_rerocc_manager_io_ptw_status_dprv), .io_ptw_status_dv (_rerocc_manager_io_ptw_status_dv), .io_ptw_status_prv (_rerocc_manager_io_ptw_status_prv), .io_ptw_status_v (_rerocc_manager_io_ptw_status_v), .io_ptw_status_sd (_rerocc_manager_io_ptw_status_sd), .io_ptw_status_zero2 (_rerocc_manager_io_ptw_status_zero2), .io_ptw_status_mpv (_rerocc_manager_io_ptw_status_mpv), .io_ptw_status_gva (_rerocc_manager_io_ptw_status_gva), .io_ptw_status_mbe (_rerocc_manager_io_ptw_status_mbe), .io_ptw_status_sbe (_rerocc_manager_io_ptw_status_sbe), .io_ptw_status_sxl (_rerocc_manager_io_ptw_status_sxl), .io_ptw_status_uxl (_rerocc_manager_io_ptw_status_uxl), .io_ptw_status_sd_rv32 (_rerocc_manager_io_ptw_status_sd_rv32), .io_ptw_status_zero1 (_rerocc_manager_io_ptw_status_zero1), .io_ptw_status_tsr (_rerocc_manager_io_ptw_status_tsr), .io_ptw_status_tw (_rerocc_manager_io_ptw_status_tw), .io_ptw_status_tvm (_rerocc_manager_io_ptw_status_tvm), .io_ptw_status_mxr (_rerocc_manager_io_ptw_status_mxr), .io_ptw_status_sum (_rerocc_manager_io_ptw_status_sum), .io_ptw_status_mprv (_rerocc_manager_io_ptw_status_mprv), .io_ptw_status_xs (_rerocc_manager_io_ptw_status_xs), .io_ptw_status_fs (_rerocc_manager_io_ptw_status_fs), .io_ptw_status_mpp (_rerocc_manager_io_ptw_status_mpp), .io_ptw_status_vs (_rerocc_manager_io_ptw_status_vs), .io_ptw_status_spp (_rerocc_manager_io_ptw_status_spp), .io_ptw_status_mpie (_rerocc_manager_io_ptw_status_mpie), .io_ptw_status_ube (_rerocc_manager_io_ptw_status_ube), .io_ptw_status_spie (_rerocc_manager_io_ptw_status_spie), .io_ptw_status_upie (_rerocc_manager_io_ptw_status_upie), .io_ptw_status_mie (_rerocc_manager_io_ptw_status_mie), .io_ptw_status_hie (_rerocc_manager_io_ptw_status_hie), .io_ptw_status_sie (_rerocc_manager_io_ptw_status_sie), .io_ptw_status_uie (_rerocc_manager_io_ptw_status_uie), .io_ptw_perf_pte_miss (_ptw_io_dpath_perf_pte_miss), // @[Manager.scala:243:21] .io_ptw_clock_enabled (_ptw_io_dpath_clock_enabled) // @[Manager.scala:243:21] ); // @[Manager.scala:209:34] ReRoCCBuffer_4 rerocc_buffer ( // @[Protocol.scala:134:35] .clock (clock), .reset (reset), .auto_in_req_ready (reRoCCNodeOut_req_ready), .auto_in_req_valid (reRoCCNodeOut_req_valid), // @[MixedNode.scala:542:17] .auto_in_req_bits_opcode (reRoCCNodeOut_req_bits_opcode), // @[MixedNode.scala:542:17] .auto_in_req_bits_client_id (reRoCCNodeOut_req_bits_client_id), // @[MixedNode.scala:542:17] .auto_in_req_bits_manager_id (reRoCCNodeOut_req_bits_manager_id), // @[MixedNode.scala:542:17] .auto_in_req_bits_data (reRoCCNodeOut_req_bits_data), // @[MixedNode.scala:542:17] .auto_in_resp_ready (reRoCCNodeOut_resp_ready), // @[MixedNode.scala:542:17] .auto_in_resp_valid (reRoCCNodeOut_resp_valid), .auto_in_resp_bits_opcode (reRoCCNodeOut_resp_bits_opcode), .auto_in_resp_bits_client_id (reRoCCNodeOut_resp_bits_client_id), .auto_in_resp_bits_manager_id (reRoCCNodeOut_resp_bits_manager_id), .auto_in_resp_bits_data (reRoCCNodeOut_resp_bits_data), .auto_out_req_ready (_rerocc_manager_auto_in_req_ready), // @[Manager.scala:209:34] .auto_out_req_valid (_rerocc_buffer_auto_out_req_valid), .auto_out_req_bits_opcode (_rerocc_buffer_auto_out_req_bits_opcode), .auto_out_req_bits_client_id (_rerocc_buffer_auto_out_req_bits_client_id), .auto_out_req_bits_manager_id (_rerocc_buffer_auto_out_req_bits_manager_id), .auto_out_req_bits_data (_rerocc_buffer_auto_out_req_bits_data), .auto_out_resp_ready (_rerocc_buffer_auto_out_resp_ready), .auto_out_resp_valid (_rerocc_manager_auto_in_resp_valid), // @[Manager.scala:209:34] .auto_out_resp_bits_opcode (_rerocc_manager_auto_in_resp_bits_opcode), // @[Manager.scala:209:34] .auto_out_resp_bits_client_id (_rerocc_manager_auto_in_resp_bits_client_id), // @[Manager.scala:209:34] .auto_out_resp_bits_manager_id (_rerocc_manager_auto_in_resp_bits_manager_id), // @[Manager.scala:209:34] .auto_out_resp_bits_data (_rerocc_manager_auto_in_resp_bits_data) // @[Manager.scala:209:34] ); // @[Protocol.scala:134:35] TLBuffer_a32d64s1k3z4c_7 buffer ( // @[Buffer.scala:75:28] .clock (clock), .reset (reset), .auto_in_a_ready (xbar_auto_anon_out_a_ready), .auto_in_a_valid (xbar_auto_anon_out_a_valid), // @[Xbar.scala:74:9] .auto_in_a_bits_opcode (xbar_auto_anon_out_a_bits_opcode), // @[Xbar.scala:74:9] .auto_in_a_bits_param (xbar_auto_anon_out_a_bits_param), // @[Xbar.scala:74:9] .auto_in_a_bits_size (xbar_auto_anon_out_a_bits_size), // @[Xbar.scala:74:9] .auto_in_a_bits_source (xbar_auto_anon_out_a_bits_source), // @[Xbar.scala:74:9] .auto_in_a_bits_address (xbar_auto_anon_out_a_bits_address), // @[Xbar.scala:74:9] .auto_in_a_bits_mask (xbar_auto_anon_out_a_bits_mask), // @[Xbar.scala:74:9] .auto_in_a_bits_data (xbar_auto_anon_out_a_bits_data), // @[Xbar.scala:74:9] .auto_in_b_ready (xbar_auto_anon_out_b_ready), // @[Xbar.scala:74:9] .auto_in_b_valid (xbar_auto_anon_out_b_valid), .auto_in_b_bits_opcode (xbar_auto_anon_out_b_bits_opcode), .auto_in_b_bits_param (xbar_auto_anon_out_b_bits_param), .auto_in_b_bits_size (xbar_auto_anon_out_b_bits_size), .auto_in_b_bits_source (xbar_auto_anon_out_b_bits_source), .auto_in_b_bits_address (xbar_auto_anon_out_b_bits_address), .auto_in_b_bits_mask (xbar_auto_anon_out_b_bits_mask), .auto_in_b_bits_data (xbar_auto_anon_out_b_bits_data), .auto_in_b_bits_corrupt (xbar_auto_anon_out_b_bits_corrupt), .auto_in_c_ready (xbar_auto_anon_out_c_ready), .auto_in_c_valid (xbar_auto_anon_out_c_valid), // @[Xbar.scala:74:9] .auto_in_c_bits_opcode (xbar_auto_anon_out_c_bits_opcode), // @[Xbar.scala:74:9] .auto_in_c_bits_param (xbar_auto_anon_out_c_bits_param), // @[Xbar.scala:74:9] .auto_in_c_bits_size (xbar_auto_anon_out_c_bits_size), // @[Xbar.scala:74:9] .auto_in_c_bits_source (xbar_auto_anon_out_c_bits_source), // @[Xbar.scala:74:9] .auto_in_c_bits_address (xbar_auto_anon_out_c_bits_address), // @[Xbar.scala:74:9] .auto_in_c_bits_data (xbar_auto_anon_out_c_bits_data), // @[Xbar.scala:74:9] .auto_in_d_ready (xbar_auto_anon_out_d_ready), // @[Xbar.scala:74:9] .auto_in_d_valid (xbar_auto_anon_out_d_valid), .auto_in_d_bits_opcode (xbar_auto_anon_out_d_bits_opcode), .auto_in_d_bits_param (xbar_auto_anon_out_d_bits_param), .auto_in_d_bits_size (xbar_auto_anon_out_d_bits_size), .auto_in_d_bits_source (xbar_auto_anon_out_d_bits_source), .auto_in_d_bits_sink (xbar_auto_anon_out_d_bits_sink), .auto_in_d_bits_denied (xbar_auto_anon_out_d_bits_denied), .auto_in_d_bits_data (xbar_auto_anon_out_d_bits_data), .auto_in_d_bits_corrupt (xbar_auto_anon_out_d_bits_corrupt), .auto_in_e_ready (xbar_auto_anon_out_e_ready), .auto_in_e_valid (xbar_auto_anon_out_e_valid), // @[Xbar.scala:74:9] .auto_in_e_bits_sink (xbar_auto_anon_out_e_bits_sink), // @[Xbar.scala:74:9] .auto_out_a_ready (auto_buffer_out_a_ready_0), // @[Manager.scala:237:34] .auto_out_a_valid (auto_buffer_out_a_valid_0), .auto_out_a_bits_opcode (auto_buffer_out_a_bits_opcode_0), .auto_out_a_bits_param (auto_buffer_out_a_bits_param_0), .auto_out_a_bits_size (auto_buffer_out_a_bits_size_0), .auto_out_a_bits_source (auto_buffer_out_a_bits_source_0), .auto_out_a_bits_address (auto_buffer_out_a_bits_address_0), .auto_out_a_bits_mask (auto_buffer_out_a_bits_mask_0), .auto_out_a_bits_data (auto_buffer_out_a_bits_data_0), .auto_out_a_bits_corrupt (auto_buffer_out_a_bits_corrupt_0), .auto_out_b_ready (auto_buffer_out_b_ready_0), .auto_out_b_valid (auto_buffer_out_b_valid_0), // @[Manager.scala:237:34] .auto_out_b_bits_opcode (auto_buffer_out_b_bits_opcode_0), // @[Manager.scala:237:34] .auto_out_b_bits_param (auto_buffer_out_b_bits_param_0), // @[Manager.scala:237:34] .auto_out_b_bits_size (auto_buffer_out_b_bits_size_0), // @[Manager.scala:237:34] .auto_out_b_bits_source (auto_buffer_out_b_bits_source_0), // @[Manager.scala:237:34] .auto_out_b_bits_address (auto_buffer_out_b_bits_address_0), // @[Manager.scala:237:34] .auto_out_b_bits_mask (auto_buffer_out_b_bits_mask_0), // @[Manager.scala:237:34] .auto_out_b_bits_data (auto_buffer_out_b_bits_data_0), // @[Manager.scala:237:34] .auto_out_b_bits_corrupt (auto_buffer_out_b_bits_corrupt_0), // @[Manager.scala:237:34] .auto_out_c_ready (auto_buffer_out_c_ready_0), // @[Manager.scala:237:34] .auto_out_c_valid (auto_buffer_out_c_valid_0), .auto_out_c_bits_opcode (auto_buffer_out_c_bits_opcode_0), .auto_out_c_bits_param (auto_buffer_out_c_bits_param_0), .auto_out_c_bits_size (auto_buffer_out_c_bits_size_0), .auto_out_c_bits_source (auto_buffer_out_c_bits_source_0), .auto_out_c_bits_address (auto_buffer_out_c_bits_address_0), .auto_out_c_bits_data (auto_buffer_out_c_bits_data_0), .auto_out_c_bits_corrupt (auto_buffer_out_c_bits_corrupt_0), .auto_out_d_ready (auto_buffer_out_d_ready_0), .auto_out_d_valid (auto_buffer_out_d_valid_0), // @[Manager.scala:237:34] .auto_out_d_bits_opcode (auto_buffer_out_d_bits_opcode_0), // @[Manager.scala:237:34] .auto_out_d_bits_param (auto_buffer_out_d_bits_param_0), // @[Manager.scala:237:34] .auto_out_d_bits_size (auto_buffer_out_d_bits_size_0), // @[Manager.scala:237:34] .auto_out_d_bits_source (auto_buffer_out_d_bits_source_0), // @[Manager.scala:237:34] .auto_out_d_bits_sink (auto_buffer_out_d_bits_sink_0), // @[Manager.scala:237:34] .auto_out_d_bits_denied (auto_buffer_out_d_bits_denied_0), // @[Manager.scala:237:34] .auto_out_d_bits_data (auto_buffer_out_d_bits_data_0), // @[Manager.scala:237:34] .auto_out_d_bits_corrupt (auto_buffer_out_d_bits_corrupt_0), // @[Manager.scala:237:34] .auto_out_e_ready (auto_buffer_out_e_ready_0), // @[Manager.scala:237:34] .auto_out_e_valid (auto_buffer_out_e_valid_0), .auto_out_e_bits_sink (auto_buffer_out_e_bits_sink_0) ); // @[Buffer.scala:75:28] MiniDCache_3 dcache ( // @[Manager.scala:226:61] .clock (clock), .reset (reset), .auto_out_a_ready (widget_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9] .auto_out_a_valid (widget_auto_anon_in_a_valid), .auto_out_a_bits_opcode (widget_auto_anon_in_a_bits_opcode), .auto_out_a_bits_param (widget_auto_anon_in_a_bits_param), .auto_out_a_bits_size (widget_auto_anon_in_a_bits_size), .auto_out_a_bits_source (widget_auto_anon_in_a_bits_source), .auto_out_a_bits_address (widget_auto_anon_in_a_bits_address), .auto_out_a_bits_mask (widget_auto_anon_in_a_bits_mask), .auto_out_a_bits_data (widget_auto_anon_in_a_bits_data), .auto_out_b_ready (widget_auto_anon_in_b_ready), .auto_out_b_valid (widget_auto_anon_in_b_valid), // @[WidthWidget.scala:27:9] .auto_out_b_bits_opcode (widget_auto_anon_in_b_bits_opcode), // @[WidthWidget.scala:27:9] .auto_out_b_bits_param (widget_auto_anon_in_b_bits_param), // @[WidthWidget.scala:27:9] .auto_out_b_bits_size (widget_auto_anon_in_b_bits_size), // @[WidthWidget.scala:27:9] .auto_out_b_bits_source (widget_auto_anon_in_b_bits_source), // @[WidthWidget.scala:27:9] .auto_out_b_bits_address (widget_auto_anon_in_b_bits_address), // @[WidthWidget.scala:27:9] .auto_out_b_bits_mask (widget_auto_anon_in_b_bits_mask), // @[WidthWidget.scala:27:9] .auto_out_b_bits_data (widget_auto_anon_in_b_bits_data), // @[WidthWidget.scala:27:9] .auto_out_b_bits_corrupt (widget_auto_anon_in_b_bits_corrupt), // @[WidthWidget.scala:27:9] .auto_out_c_ready (widget_auto_anon_in_c_ready), // @[WidthWidget.scala:27:9] .auto_out_c_valid (widget_auto_anon_in_c_valid), .auto_out_c_bits_opcode (widget_auto_anon_in_c_bits_opcode), .auto_out_c_bits_param (widget_auto_anon_in_c_bits_param), .auto_out_c_bits_size (widget_auto_anon_in_c_bits_size), .auto_out_c_bits_source (widget_auto_anon_in_c_bits_source), .auto_out_c_bits_address (widget_auto_anon_in_c_bits_address), .auto_out_c_bits_data (widget_auto_anon_in_c_bits_data), .auto_out_d_ready (widget_auto_anon_in_d_ready), .auto_out_d_valid (widget_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9] .auto_out_d_bits_opcode (widget_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9] .auto_out_d_bits_param (widget_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9] .auto_out_d_bits_size (widget_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9] .auto_out_d_bits_source (widget_auto_anon_in_d_bits_source), // @[WidthWidget.scala:27:9] .auto_out_d_bits_sink (widget_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9] .auto_out_d_bits_denied (widget_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9] .auto_out_d_bits_data (widget_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9] .auto_out_d_bits_corrupt (widget_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9] .auto_out_e_ready (widget_auto_anon_in_e_ready), // @[WidthWidget.scala:27:9] .auto_out_e_valid (widget_auto_anon_in_e_valid), .auto_out_e_bits_sink (widget_auto_anon_in_e_bits_sink), .io_cpu_req_ready (_dcache_io_cpu_req_ready), .io_cpu_req_valid (_dcacheArb_io_mem_req_valid), // @[Manager.scala:238:27] .io_cpu_req_bits_addr (_dcacheArb_io_mem_req_bits_addr), // @[Manager.scala:238:27] .io_cpu_req_bits_tag (_dcacheArb_io_mem_req_bits_tag), // @[Manager.scala:238:27] .io_cpu_req_bits_dprv (_dcacheArb_io_mem_req_bits_dprv), // @[Manager.scala:238:27] .io_cpu_req_bits_dv (_dcacheArb_io_mem_req_bits_dv), // @[Manager.scala:238:27] .io_cpu_req_bits_phys (_dcacheArb_io_mem_req_bits_phys), // @[Manager.scala:238:27] .io_cpu_s1_kill (_dcacheArb_io_mem_s1_kill), // @[Manager.scala:238:27] .io_cpu_s1_data_data (_dcacheArb_io_mem_s1_data_data), // @[Manager.scala:238:27] .io_cpu_s1_data_mask (_dcacheArb_io_mem_s1_data_mask), // @[Manager.scala:238:27] .io_cpu_s2_nack (_dcache_io_cpu_s2_nack), .io_cpu_s2_nack_cause_raw (_dcache_io_cpu_s2_nack_cause_raw), .io_cpu_s2_uncached (_dcache_io_cpu_s2_uncached), .io_cpu_s2_paddr (_dcache_io_cpu_s2_paddr), .io_cpu_resp_valid (_dcache_io_cpu_resp_valid), .io_cpu_resp_bits_addr (_dcache_io_cpu_resp_bits_addr), .io_cpu_resp_bits_tag (_dcache_io_cpu_resp_bits_tag), .io_cpu_resp_bits_cmd (_dcache_io_cpu_resp_bits_cmd), .io_cpu_resp_bits_size (_dcache_io_cpu_resp_bits_size), .io_cpu_resp_bits_signed (_dcache_io_cpu_resp_bits_signed), .io_cpu_resp_bits_dprv (_dcache_io_cpu_resp_bits_dprv), .io_cpu_resp_bits_dv (_dcache_io_cpu_resp_bits_dv), .io_cpu_resp_bits_data (_dcache_io_cpu_resp_bits_data), .io_cpu_resp_bits_mask (_dcache_io_cpu_resp_bits_mask), .io_cpu_resp_bits_replay (_dcache_io_cpu_resp_bits_replay), .io_cpu_resp_bits_has_data (_dcache_io_cpu_resp_bits_has_data), .io_cpu_resp_bits_data_word_bypass (_dcache_io_cpu_resp_bits_data_word_bypass), .io_cpu_resp_bits_data_raw (_dcache_io_cpu_resp_bits_data_raw), .io_cpu_resp_bits_store_data (_dcache_io_cpu_resp_bits_store_data), .io_cpu_replay_next (_dcache_io_cpu_replay_next), .io_cpu_s2_xcpt_ma_ld (_dcache_io_cpu_s2_xcpt_ma_ld), .io_cpu_s2_xcpt_ma_st (_dcache_io_cpu_s2_xcpt_ma_st), .io_cpu_s2_xcpt_pf_ld (_dcache_io_cpu_s2_xcpt_pf_ld), .io_cpu_s2_xcpt_pf_st (_dcache_io_cpu_s2_xcpt_pf_st), .io_cpu_s2_xcpt_ae_ld (_dcache_io_cpu_s2_xcpt_ae_ld), .io_cpu_s2_xcpt_ae_st (_dcache_io_cpu_s2_xcpt_ae_st), .io_cpu_s2_gpa (_dcache_io_cpu_s2_gpa), .io_cpu_ordered (_dcache_io_cpu_ordered), .io_cpu_store_pending (_dcache_io_cpu_store_pending), .io_cpu_perf_acquire (_dcache_io_cpu_perf_acquire), .io_cpu_perf_release (_dcache_io_cpu_perf_release), .io_cpu_perf_grant (_dcache_io_cpu_perf_grant), .io_cpu_perf_tlbMiss (_dcache_io_cpu_perf_tlbMiss), .io_cpu_perf_blocked (_dcache_io_cpu_perf_blocked), .io_cpu_perf_canAcceptStoreThenLoad (_dcache_io_cpu_perf_canAcceptStoreThenLoad), .io_cpu_perf_canAcceptStoreThenRMW (_dcache_io_cpu_perf_canAcceptStoreThenRMW), .io_cpu_perf_canAcceptLoadThenLoad (_dcache_io_cpu_perf_canAcceptLoadThenLoad), .io_cpu_perf_storeBufferEmptyAfterLoad (_dcache_io_cpu_perf_storeBufferEmptyAfterLoad), .io_cpu_perf_storeBufferEmptyAfterStore (_dcache_io_cpu_perf_storeBufferEmptyAfterStore), .io_ptw_req_ready (_ptw_io_requestor_0_req_ready), // @[Manager.scala:243:21] .io_ptw_req_valid (_dcache_io_ptw_req_valid), .io_ptw_req_bits_bits_addr (_dcache_io_ptw_req_bits_bits_addr), .io_ptw_req_bits_bits_need_gpa (_dcache_io_ptw_req_bits_bits_need_gpa), .io_ptw_resp_valid (_ptw_io_requestor_0_resp_valid), // @[Manager.scala:243:21] .io_ptw_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw), // @[Manager.scala:243:21] .io_ptw_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final), // @[Manager.scala:243:21] .io_ptw_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf), // @[Manager.scala:243:21] .io_ptw_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf), // @[Manager.scala:243:21] .io_ptw_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr), // @[Manager.scala:243:21] .io_ptw_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw), // @[Manager.scala:243:21] .io_ptw_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx), // @[Manager.scala:243:21] .io_ptw_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future), // @[Manager.scala:243:21] .io_ptw_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn), // @[Manager.scala:243:21] .io_ptw_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software), // @[Manager.scala:243:21] .io_ptw_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d), // @[Manager.scala:243:21] .io_ptw_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a), // @[Manager.scala:243:21] .io_ptw_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g), // @[Manager.scala:243:21] .io_ptw_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u), // @[Manager.scala:243:21] .io_ptw_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x), // @[Manager.scala:243:21] .io_ptw_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w), // @[Manager.scala:243:21] .io_ptw_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r), // @[Manager.scala:243:21] .io_ptw_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v), // @[Manager.scala:243:21] .io_ptw_resp_bits_level (_ptw_io_requestor_0_resp_bits_level), // @[Manager.scala:243:21] .io_ptw_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous), // @[Manager.scala:243:21] .io_ptw_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid), // @[Manager.scala:243:21] .io_ptw_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits), // @[Manager.scala:243:21] .io_ptw_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte), // @[Manager.scala:243:21] .io_ptw_ptbr_mode (_ptw_io_requestor_0_ptbr_mode), // @[Manager.scala:243:21] .io_ptw_ptbr_asid (_ptw_io_requestor_0_ptbr_asid), // @[Manager.scala:243:21] .io_ptw_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn), // @[Manager.scala:243:21] .io_ptw_status_debug (_ptw_io_requestor_0_status_debug), // @[Manager.scala:243:21] .io_ptw_status_cease (_ptw_io_requestor_0_status_cease), // @[Manager.scala:243:21] .io_ptw_status_wfi (_ptw_io_requestor_0_status_wfi), // @[Manager.scala:243:21] .io_ptw_status_isa (_ptw_io_requestor_0_status_isa), // @[Manager.scala:243:21] .io_ptw_status_dprv (_ptw_io_requestor_0_status_dprv), // @[Manager.scala:243:21] .io_ptw_status_dv (_ptw_io_requestor_0_status_dv), // @[Manager.scala:243:21] .io_ptw_status_prv (_ptw_io_requestor_0_status_prv), // @[Manager.scala:243:21] .io_ptw_status_v (_ptw_io_requestor_0_status_v), // @[Manager.scala:243:21] .io_ptw_status_sd (_ptw_io_requestor_0_status_sd), // @[Manager.scala:243:21] .io_ptw_status_zero2 (_ptw_io_requestor_0_status_zero2), // @[Manager.scala:243:21] .io_ptw_status_mpv (_ptw_io_requestor_0_status_mpv), // @[Manager.scala:243:21] .io_ptw_status_gva (_ptw_io_requestor_0_status_gva), // @[Manager.scala:243:21] .io_ptw_status_mbe (_ptw_io_requestor_0_status_mbe), // @[Manager.scala:243:21] .io_ptw_status_sbe (_ptw_io_requestor_0_status_sbe), // @[Manager.scala:243:21] .io_ptw_status_sxl (_ptw_io_requestor_0_status_sxl), // @[Manager.scala:243:21] .io_ptw_status_uxl (_ptw_io_requestor_0_status_uxl), // @[Manager.scala:243:21] .io_ptw_status_sd_rv32 (_ptw_io_requestor_0_status_sd_rv32), // @[Manager.scala:243:21] .io_ptw_status_zero1 (_ptw_io_requestor_0_status_zero1), // @[Manager.scala:243:21] .io_ptw_status_tsr (_ptw_io_requestor_0_status_tsr), // @[Manager.scala:243:21] .io_ptw_status_tw (_ptw_io_requestor_0_status_tw), // @[Manager.scala:243:21] .io_ptw_status_tvm (_ptw_io_requestor_0_status_tvm), // @[Manager.scala:243:21] .io_ptw_status_mxr (_ptw_io_requestor_0_status_mxr), // @[Manager.scala:243:21] .io_ptw_status_sum (_ptw_io_requestor_0_status_sum), // @[Manager.scala:243:21] .io_ptw_status_mprv (_ptw_io_requestor_0_status_mprv), // @[Manager.scala:243:21] .io_ptw_status_xs (_ptw_io_requestor_0_status_xs), // @[Manager.scala:243:21] .io_ptw_status_fs (_ptw_io_requestor_0_status_fs), // @[Manager.scala:243:21] .io_ptw_status_mpp (_ptw_io_requestor_0_status_mpp), // @[Manager.scala:243:21] .io_ptw_status_vs (_ptw_io_requestor_0_status_vs), // @[Manager.scala:243:21] .io_ptw_status_spp (_ptw_io_requestor_0_status_spp), // @[Manager.scala:243:21] .io_ptw_status_mpie (_ptw_io_requestor_0_status_mpie), // @[Manager.scala:243:21] .io_ptw_status_ube (_ptw_io_requestor_0_status_ube), // @[Manager.scala:243:21] .io_ptw_status_spie (_ptw_io_requestor_0_status_spie), // @[Manager.scala:243:21] .io_ptw_status_upie (_ptw_io_requestor_0_status_upie), // @[Manager.scala:243:21] .io_ptw_status_mie (_ptw_io_requestor_0_status_mie), // @[Manager.scala:243:21] .io_ptw_status_hie (_ptw_io_requestor_0_status_hie), // @[Manager.scala:243:21] .io_ptw_status_sie (_ptw_io_requestor_0_status_sie), // @[Manager.scala:243:21] .io_ptw_status_uie (_ptw_io_requestor_0_status_uie) // @[Manager.scala:243:21] ); // @[Manager.scala:226:61] ReRoCCManagerControl_3 ctrl ( // @[Manager.scala:235:24] .clock (clock), .reset (reset), .auto_ctrl_in_a_ready (auto_ctrl_ctrl_in_a_ready_0), .auto_ctrl_in_a_valid (auto_ctrl_ctrl_in_a_valid_0), // @[Manager.scala:237:34] .auto_ctrl_in_a_bits_opcode (auto_ctrl_ctrl_in_a_bits_opcode_0), // @[Manager.scala:237:34] .auto_ctrl_in_a_bits_param (auto_ctrl_ctrl_in_a_bits_param_0), // @[Manager.scala:237:34] .auto_ctrl_in_a_bits_size (auto_ctrl_ctrl_in_a_bits_size_0), // @[Manager.scala:237:34] .auto_ctrl_in_a_bits_source (auto_ctrl_ctrl_in_a_bits_source_0), // @[Manager.scala:237:34] .auto_ctrl_in_a_bits_address (auto_ctrl_ctrl_in_a_bits_address_0), // @[Manager.scala:237:34] .auto_ctrl_in_a_bits_mask (auto_ctrl_ctrl_in_a_bits_mask_0), // @[Manager.scala:237:34] .auto_ctrl_in_a_bits_data (auto_ctrl_ctrl_in_a_bits_data_0), // @[Manager.scala:237:34] .auto_ctrl_in_a_bits_corrupt (auto_ctrl_ctrl_in_a_bits_corrupt_0), // @[Manager.scala:237:34] .auto_ctrl_in_d_ready (auto_ctrl_ctrl_in_d_ready_0), // @[Manager.scala:237:34] .auto_ctrl_in_d_valid (auto_ctrl_ctrl_in_d_valid_0), .auto_ctrl_in_d_bits_opcode (auto_ctrl_ctrl_in_d_bits_opcode_0), .auto_ctrl_in_d_bits_size (auto_ctrl_ctrl_in_d_bits_size_0), .auto_ctrl_in_d_bits_source (auto_ctrl_ctrl_in_d_bits_source_0), .auto_ctrl_in_d_bits_data (auto_ctrl_ctrl_in_d_bits_data_0), .io_mgr_busy (accumulator_io_busy), // @[LazyRoCC.scala:122:7] .io_rocc_busy (accumulator_io_busy) // @[LazyRoCC.scala:122:7] ); // @[Manager.scala:235:24] HellaCacheArbiter_4 dcacheArb ( // @[Manager.scala:238:27] .clock (clock), .reset (reset), .io_requestor_0_req_ready (_dcacheArb_io_requestor_0_req_ready), .io_requestor_0_req_valid (_ptw_io_mem_req_valid), // @[Manager.scala:243:21] .io_requestor_0_req_bits_addr (_ptw_io_mem_req_bits_addr), // @[Manager.scala:243:21] .io_requestor_0_req_bits_dv (_ptw_io_mem_req_bits_dv), // @[Manager.scala:243:21] .io_requestor_0_s1_kill (_ptw_io_mem_s1_kill), // @[Manager.scala:243:21] .io_requestor_0_s2_nack (_dcacheArb_io_requestor_0_s2_nack), .io_requestor_0_s2_nack_cause_raw (_dcacheArb_io_requestor_0_s2_nack_cause_raw), .io_requestor_0_s2_uncached (_dcacheArb_io_requestor_0_s2_uncached), .io_requestor_0_s2_paddr (_dcacheArb_io_requestor_0_s2_paddr), .io_requestor_0_resp_valid (_dcacheArb_io_requestor_0_resp_valid), .io_requestor_0_resp_bits_addr (_dcacheArb_io_requestor_0_resp_bits_addr), .io_requestor_0_resp_bits_tag (_dcacheArb_io_requestor_0_resp_bits_tag), .io_requestor_0_resp_bits_cmd (_dcacheArb_io_requestor_0_resp_bits_cmd), .io_requestor_0_resp_bits_size (_dcacheArb_io_requestor_0_resp_bits_size), .io_requestor_0_resp_bits_signed (_dcacheArb_io_requestor_0_resp_bits_signed), .io_requestor_0_resp_bits_dprv (_dcacheArb_io_requestor_0_resp_bits_dprv), .io_requestor_0_resp_bits_dv (_dcacheArb_io_requestor_0_resp_bits_dv), .io_requestor_0_resp_bits_data (_dcacheArb_io_requestor_0_resp_bits_data), .io_requestor_0_resp_bits_mask (_dcacheArb_io_requestor_0_resp_bits_mask), .io_requestor_0_resp_bits_replay (_dcacheArb_io_requestor_0_resp_bits_replay), .io_requestor_0_resp_bits_has_data (_dcacheArb_io_requestor_0_resp_bits_has_data), .io_requestor_0_resp_bits_data_word_bypass (_dcacheArb_io_requestor_0_resp_bits_data_word_bypass), .io_requestor_0_resp_bits_data_raw (_dcacheArb_io_requestor_0_resp_bits_data_raw), .io_requestor_0_resp_bits_store_data (_dcacheArb_io_requestor_0_resp_bits_store_data), .io_requestor_0_replay_next (_dcacheArb_io_requestor_0_replay_next), .io_requestor_0_s2_xcpt_ma_ld (_dcacheArb_io_requestor_0_s2_xcpt_ma_ld), .io_requestor_0_s2_xcpt_ma_st (_dcacheArb_io_requestor_0_s2_xcpt_ma_st), .io_requestor_0_s2_xcpt_pf_ld (_dcacheArb_io_requestor_0_s2_xcpt_pf_ld), .io_requestor_0_s2_xcpt_pf_st (_dcacheArb_io_requestor_0_s2_xcpt_pf_st), .io_requestor_0_s2_xcpt_ae_ld (_dcacheArb_io_requestor_0_s2_xcpt_ae_ld), .io_requestor_0_s2_xcpt_ae_st (_dcacheArb_io_requestor_0_s2_xcpt_ae_st), .io_requestor_0_s2_gpa (_dcacheArb_io_requestor_0_s2_gpa), .io_requestor_0_ordered (_dcacheArb_io_requestor_0_ordered), .io_requestor_0_store_pending (_dcacheArb_io_requestor_0_store_pending), .io_requestor_0_perf_acquire (_dcacheArb_io_requestor_0_perf_acquire), .io_requestor_0_perf_release (_dcacheArb_io_requestor_0_perf_release), .io_requestor_0_perf_grant (_dcacheArb_io_requestor_0_perf_grant), .io_requestor_0_perf_tlbMiss (_dcacheArb_io_requestor_0_perf_tlbMiss), .io_requestor_0_perf_blocked (_dcacheArb_io_requestor_0_perf_blocked), .io_requestor_0_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad), .io_requestor_0_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW), .io_requestor_0_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad), .io_requestor_0_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad), .io_requestor_0_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore), .io_requestor_1_req_ready (_dcacheArb_io_requestor_1_req_ready), .io_requestor_1_req_valid (_dcIF_io_cache_req_valid), // @[Manager.scala:255:22] .io_requestor_1_req_bits_addr (_dcIF_io_cache_req_bits_addr), // @[Manager.scala:255:22] .io_requestor_1_req_bits_tag (_dcIF_io_cache_req_bits_tag), // @[Manager.scala:255:22] .io_requestor_1_req_bits_dprv (_dcIF_io_cache_req_bits_dprv), // @[Manager.scala:255:22] .io_requestor_1_req_bits_dv (_dcIF_io_cache_req_bits_dv), // @[Manager.scala:255:22] .io_requestor_1_s1_data_data (_dcIF_io_cache_s1_data_data), // @[Manager.scala:255:22] .io_requestor_1_s1_data_mask (_dcIF_io_cache_s1_data_mask), // @[Manager.scala:255:22] .io_requestor_1_s2_nack (_dcacheArb_io_requestor_1_s2_nack), .io_requestor_1_s2_nack_cause_raw (_dcacheArb_io_requestor_1_s2_nack_cause_raw), .io_requestor_1_s2_uncached (_dcacheArb_io_requestor_1_s2_uncached), .io_requestor_1_s2_paddr (_dcacheArb_io_requestor_1_s2_paddr), .io_requestor_1_resp_valid (_dcacheArb_io_requestor_1_resp_valid), .io_requestor_1_resp_bits_addr (_dcacheArb_io_requestor_1_resp_bits_addr), .io_requestor_1_resp_bits_tag (_dcacheArb_io_requestor_1_resp_bits_tag), .io_requestor_1_resp_bits_cmd (_dcacheArb_io_requestor_1_resp_bits_cmd), .io_requestor_1_resp_bits_size (_dcacheArb_io_requestor_1_resp_bits_size), .io_requestor_1_resp_bits_signed (_dcacheArb_io_requestor_1_resp_bits_signed), .io_requestor_1_resp_bits_dprv (_dcacheArb_io_requestor_1_resp_bits_dprv), .io_requestor_1_resp_bits_dv (_dcacheArb_io_requestor_1_resp_bits_dv), .io_requestor_1_resp_bits_data (_dcacheArb_io_requestor_1_resp_bits_data), .io_requestor_1_resp_bits_mask (_dcacheArb_io_requestor_1_resp_bits_mask), .io_requestor_1_resp_bits_replay (_dcacheArb_io_requestor_1_resp_bits_replay), .io_requestor_1_resp_bits_has_data (_dcacheArb_io_requestor_1_resp_bits_has_data), .io_requestor_1_resp_bits_data_word_bypass (_dcacheArb_io_requestor_1_resp_bits_data_word_bypass), .io_requestor_1_resp_bits_data_raw (_dcacheArb_io_requestor_1_resp_bits_data_raw), .io_requestor_1_resp_bits_store_data (_dcacheArb_io_requestor_1_resp_bits_store_data), .io_requestor_1_replay_next (_dcacheArb_io_requestor_1_replay_next), .io_requestor_1_s2_xcpt_ma_ld (_dcacheArb_io_requestor_1_s2_xcpt_ma_ld), .io_requestor_1_s2_xcpt_ma_st (_dcacheArb_io_requestor_1_s2_xcpt_ma_st), .io_requestor_1_s2_xcpt_pf_ld (_dcacheArb_io_requestor_1_s2_xcpt_pf_ld), .io_requestor_1_s2_xcpt_pf_st (_dcacheArb_io_requestor_1_s2_xcpt_pf_st), .io_requestor_1_s2_xcpt_ae_ld (_dcacheArb_io_requestor_1_s2_xcpt_ae_ld), .io_requestor_1_s2_xcpt_ae_st (_dcacheArb_io_requestor_1_s2_xcpt_ae_st), .io_requestor_1_s2_gpa (_dcacheArb_io_requestor_1_s2_gpa), .io_requestor_1_ordered (_dcacheArb_io_requestor_1_ordered), .io_requestor_1_store_pending (_dcacheArb_io_requestor_1_store_pending), .io_requestor_1_perf_acquire (_dcacheArb_io_requestor_1_perf_acquire), .io_requestor_1_perf_release (_dcacheArb_io_requestor_1_perf_release), .io_requestor_1_perf_grant (_dcacheArb_io_requestor_1_perf_grant), .io_requestor_1_perf_tlbMiss (_dcacheArb_io_requestor_1_perf_tlbMiss), .io_requestor_1_perf_blocked (_dcacheArb_io_requestor_1_perf_blocked), .io_requestor_1_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad), .io_requestor_1_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW), .io_requestor_1_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad), .io_requestor_1_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad), .io_requestor_1_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore), .io_mem_req_ready (_dcache_io_cpu_req_ready), // @[Manager.scala:226:61] .io_mem_req_valid (_dcacheArb_io_mem_req_valid), .io_mem_req_bits_addr (_dcacheArb_io_mem_req_bits_addr), .io_mem_req_bits_tag (_dcacheArb_io_mem_req_bits_tag), .io_mem_req_bits_dprv (_dcacheArb_io_mem_req_bits_dprv), .io_mem_req_bits_dv (_dcacheArb_io_mem_req_bits_dv), .io_mem_req_bits_phys (_dcacheArb_io_mem_req_bits_phys), .io_mem_s1_kill (_dcacheArb_io_mem_s1_kill), .io_mem_s1_data_data (_dcacheArb_io_mem_s1_data_data), .io_mem_s1_data_mask (_dcacheArb_io_mem_s1_data_mask), .io_mem_s2_nack (_dcache_io_cpu_s2_nack), // @[Manager.scala:226:61] .io_mem_s2_nack_cause_raw (_dcache_io_cpu_s2_nack_cause_raw), // @[Manager.scala:226:61] .io_mem_s2_uncached (_dcache_io_cpu_s2_uncached), // @[Manager.scala:226:61] .io_mem_s2_paddr (_dcache_io_cpu_s2_paddr), // @[Manager.scala:226:61] .io_mem_resp_valid (_dcache_io_cpu_resp_valid), // @[Manager.scala:226:61] .io_mem_resp_bits_addr (_dcache_io_cpu_resp_bits_addr), // @[Manager.scala:226:61] .io_mem_resp_bits_tag (_dcache_io_cpu_resp_bits_tag), // @[Manager.scala:226:61] .io_mem_resp_bits_cmd (_dcache_io_cpu_resp_bits_cmd), // @[Manager.scala:226:61] .io_mem_resp_bits_size (_dcache_io_cpu_resp_bits_size), // @[Manager.scala:226:61] .io_mem_resp_bits_signed (_dcache_io_cpu_resp_bits_signed), // @[Manager.scala:226:61] .io_mem_resp_bits_dprv (_dcache_io_cpu_resp_bits_dprv), // @[Manager.scala:226:61] .io_mem_resp_bits_dv (_dcache_io_cpu_resp_bits_dv), // @[Manager.scala:226:61] .io_mem_resp_bits_data (_dcache_io_cpu_resp_bits_data), // @[Manager.scala:226:61] .io_mem_resp_bits_mask (_dcache_io_cpu_resp_bits_mask), // @[Manager.scala:226:61] .io_mem_resp_bits_replay (_dcache_io_cpu_resp_bits_replay), // @[Manager.scala:226:61] .io_mem_resp_bits_has_data (_dcache_io_cpu_resp_bits_has_data), // @[Manager.scala:226:61] .io_mem_resp_bits_data_word_bypass (_dcache_io_cpu_resp_bits_data_word_bypass), // @[Manager.scala:226:61] .io_mem_resp_bits_data_raw (_dcache_io_cpu_resp_bits_data_raw), // @[Manager.scala:226:61] .io_mem_resp_bits_store_data (_dcache_io_cpu_resp_bits_store_data), // @[Manager.scala:226:61] .io_mem_replay_next (_dcache_io_cpu_replay_next), // @[Manager.scala:226:61] .io_mem_s2_xcpt_ma_ld (_dcache_io_cpu_s2_xcpt_ma_ld), // @[Manager.scala:226:61] .io_mem_s2_xcpt_ma_st (_dcache_io_cpu_s2_xcpt_ma_st), // @[Manager.scala:226:61] .io_mem_s2_xcpt_pf_ld (_dcache_io_cpu_s2_xcpt_pf_ld), // @[Manager.scala:226:61] .io_mem_s2_xcpt_pf_st (_dcache_io_cpu_s2_xcpt_pf_st), // @[Manager.scala:226:61] .io_mem_s2_xcpt_ae_ld (_dcache_io_cpu_s2_xcpt_ae_ld), // @[Manager.scala:226:61] .io_mem_s2_xcpt_ae_st (_dcache_io_cpu_s2_xcpt_ae_st), // @[Manager.scala:226:61] .io_mem_s2_gpa (_dcache_io_cpu_s2_gpa), // @[Manager.scala:226:61] .io_mem_ordered (_dcache_io_cpu_ordered), // @[Manager.scala:226:61] .io_mem_store_pending (_dcache_io_cpu_store_pending), // @[Manager.scala:226:61] .io_mem_perf_acquire (_dcache_io_cpu_perf_acquire), // @[Manager.scala:226:61] .io_mem_perf_release (_dcache_io_cpu_perf_release), // @[Manager.scala:226:61] .io_mem_perf_grant (_dcache_io_cpu_perf_grant), // @[Manager.scala:226:61] .io_mem_perf_tlbMiss (_dcache_io_cpu_perf_tlbMiss), // @[Manager.scala:226:61] .io_mem_perf_blocked (_dcache_io_cpu_perf_blocked), // @[Manager.scala:226:61] .io_mem_perf_canAcceptStoreThenLoad (_dcache_io_cpu_perf_canAcceptStoreThenLoad), // @[Manager.scala:226:61] .io_mem_perf_canAcceptStoreThenRMW (_dcache_io_cpu_perf_canAcceptStoreThenRMW), // @[Manager.scala:226:61] .io_mem_perf_canAcceptLoadThenLoad (_dcache_io_cpu_perf_canAcceptLoadThenLoad), // @[Manager.scala:226:61] .io_mem_perf_storeBufferEmptyAfterLoad (_dcache_io_cpu_perf_storeBufferEmptyAfterLoad), // @[Manager.scala:226:61] .io_mem_perf_storeBufferEmptyAfterStore (_dcache_io_cpu_perf_storeBufferEmptyAfterStore) // @[Manager.scala:226:61] ); // @[Manager.scala:238:27] PTW_4 ptw ( // @[Manager.scala:243:21] .clock (clock), .reset (reset), .io_requestor_0_req_ready (_ptw_io_requestor_0_req_ready), .io_requestor_0_req_valid (_dcache_io_ptw_req_valid), // @[Manager.scala:226:61] .io_requestor_0_req_bits_bits_addr (_dcache_io_ptw_req_bits_bits_addr), // @[Manager.scala:226:61] .io_requestor_0_req_bits_bits_need_gpa (_dcache_io_ptw_req_bits_bits_need_gpa), // @[Manager.scala:226:61] .io_requestor_0_resp_valid (_ptw_io_requestor_0_resp_valid), .io_requestor_0_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw), .io_requestor_0_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final), .io_requestor_0_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf), .io_requestor_0_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf), .io_requestor_0_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr), .io_requestor_0_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw), .io_requestor_0_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx), .io_requestor_0_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future), .io_requestor_0_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn), .io_requestor_0_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software), .io_requestor_0_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d), .io_requestor_0_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a), .io_requestor_0_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g), .io_requestor_0_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u), .io_requestor_0_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x), .io_requestor_0_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w), .io_requestor_0_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r), .io_requestor_0_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v), .io_requestor_0_resp_bits_level (_ptw_io_requestor_0_resp_bits_level), .io_requestor_0_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous), .io_requestor_0_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid), .io_requestor_0_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits), .io_requestor_0_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte), .io_requestor_0_ptbr_mode (_ptw_io_requestor_0_ptbr_mode), .io_requestor_0_ptbr_asid (_ptw_io_requestor_0_ptbr_asid), .io_requestor_0_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn), .io_requestor_0_status_debug (_ptw_io_requestor_0_status_debug), .io_requestor_0_status_cease (_ptw_io_requestor_0_status_cease), .io_requestor_0_status_wfi (_ptw_io_requestor_0_status_wfi), .io_requestor_0_status_isa (_ptw_io_requestor_0_status_isa), .io_requestor_0_status_dprv (_ptw_io_requestor_0_status_dprv), .io_requestor_0_status_dv (_ptw_io_requestor_0_status_dv), .io_requestor_0_status_prv (_ptw_io_requestor_0_status_prv), .io_requestor_0_status_v (_ptw_io_requestor_0_status_v), .io_requestor_0_status_sd (_ptw_io_requestor_0_status_sd), .io_requestor_0_status_zero2 (_ptw_io_requestor_0_status_zero2), .io_requestor_0_status_mpv (_ptw_io_requestor_0_status_mpv), .io_requestor_0_status_gva (_ptw_io_requestor_0_status_gva), .io_requestor_0_status_mbe (_ptw_io_requestor_0_status_mbe), .io_requestor_0_status_sbe (_ptw_io_requestor_0_status_sbe), .io_requestor_0_status_sxl (_ptw_io_requestor_0_status_sxl), .io_requestor_0_status_uxl (_ptw_io_requestor_0_status_uxl), .io_requestor_0_status_sd_rv32 (_ptw_io_requestor_0_status_sd_rv32), .io_requestor_0_status_zero1 (_ptw_io_requestor_0_status_zero1), .io_requestor_0_status_tsr (_ptw_io_requestor_0_status_tsr), .io_requestor_0_status_tw (_ptw_io_requestor_0_status_tw), .io_requestor_0_status_tvm (_ptw_io_requestor_0_status_tvm), .io_requestor_0_status_mxr (_ptw_io_requestor_0_status_mxr), .io_requestor_0_status_sum (_ptw_io_requestor_0_status_sum), .io_requestor_0_status_mprv (_ptw_io_requestor_0_status_mprv), .io_requestor_0_status_xs (_ptw_io_requestor_0_status_xs), .io_requestor_0_status_fs (_ptw_io_requestor_0_status_fs), .io_requestor_0_status_mpp (_ptw_io_requestor_0_status_mpp), .io_requestor_0_status_vs (_ptw_io_requestor_0_status_vs), .io_requestor_0_status_spp (_ptw_io_requestor_0_status_spp), .io_requestor_0_status_mpie (_ptw_io_requestor_0_status_mpie), .io_requestor_0_status_ube (_ptw_io_requestor_0_status_ube), .io_requestor_0_status_spie (_ptw_io_requestor_0_status_spie), .io_requestor_0_status_upie (_ptw_io_requestor_0_status_upie), .io_requestor_0_status_mie (_ptw_io_requestor_0_status_mie), .io_requestor_0_status_hie (_ptw_io_requestor_0_status_hie), .io_requestor_0_status_sie (_ptw_io_requestor_0_status_sie), .io_requestor_0_status_uie (_ptw_io_requestor_0_status_uie), .io_mem_req_ready (_dcacheArb_io_requestor_0_req_ready), // @[Manager.scala:238:27] .io_mem_req_valid (_ptw_io_mem_req_valid), .io_mem_req_bits_addr (_ptw_io_mem_req_bits_addr), .io_mem_req_bits_dv (_ptw_io_mem_req_bits_dv), .io_mem_s1_kill (_ptw_io_mem_s1_kill), .io_mem_s2_nack (_dcacheArb_io_requestor_0_s2_nack), // @[Manager.scala:238:27] .io_mem_s2_nack_cause_raw (_dcacheArb_io_requestor_0_s2_nack_cause_raw), // @[Manager.scala:238:27] .io_mem_s2_uncached (_dcacheArb_io_requestor_0_s2_uncached), // @[Manager.scala:238:27] .io_mem_s2_paddr (_dcacheArb_io_requestor_0_s2_paddr), // @[Manager.scala:238:27] .io_mem_resp_valid (_dcacheArb_io_requestor_0_resp_valid), // @[Manager.scala:238:27] .io_mem_resp_bits_addr (_dcacheArb_io_requestor_0_resp_bits_addr), // @[Manager.scala:238:27] .io_mem_resp_bits_tag (_dcacheArb_io_requestor_0_resp_bits_tag), // @[Manager.scala:238:27] .io_mem_resp_bits_cmd (_dcacheArb_io_requestor_0_resp_bits_cmd), // @[Manager.scala:238:27] .io_mem_resp_bits_size (_dcacheArb_io_requestor_0_resp_bits_size), // @[Manager.scala:238:27] .io_mem_resp_bits_signed (_dcacheArb_io_requestor_0_resp_bits_signed), // @[Manager.scala:238:27] .io_mem_resp_bits_dprv (_dcacheArb_io_requestor_0_resp_bits_dprv), // @[Manager.scala:238:27] .io_mem_resp_bits_dv (_dcacheArb_io_requestor_0_resp_bits_dv), // @[Manager.scala:238:27] .io_mem_resp_bits_data (_dcacheArb_io_requestor_0_resp_bits_data), // @[Manager.scala:238:27] .io_mem_resp_bits_mask (_dcacheArb_io_requestor_0_resp_bits_mask), // @[Manager.scala:238:27] .io_mem_resp_bits_replay (_dcacheArb_io_requestor_0_resp_bits_replay), // @[Manager.scala:238:27] .io_mem_resp_bits_has_data (_dcacheArb_io_requestor_0_resp_bits_has_data), // @[Manager.scala:238:27] .io_mem_resp_bits_data_word_bypass (_dcacheArb_io_requestor_0_resp_bits_data_word_bypass), // @[Manager.scala:238:27] .io_mem_resp_bits_data_raw (_dcacheArb_io_requestor_0_resp_bits_data_raw), // @[Manager.scala:238:27] .io_mem_resp_bits_store_data (_dcacheArb_io_requestor_0_resp_bits_store_data), // @[Manager.scala:238:27] .io_mem_replay_next (_dcacheArb_io_requestor_0_replay_next), // @[Manager.scala:238:27] .io_mem_s2_xcpt_ma_ld (_dcacheArb_io_requestor_0_s2_xcpt_ma_ld), // @[Manager.scala:238:27] .io_mem_s2_xcpt_ma_st (_dcacheArb_io_requestor_0_s2_xcpt_ma_st), // @[Manager.scala:238:27] .io_mem_s2_xcpt_pf_ld (_dcacheArb_io_requestor_0_s2_xcpt_pf_ld), // @[Manager.scala:238:27] .io_mem_s2_xcpt_pf_st (_dcacheArb_io_requestor_0_s2_xcpt_pf_st), // @[Manager.scala:238:27] .io_mem_s2_xcpt_ae_ld (_dcacheArb_io_requestor_0_s2_xcpt_ae_ld), // @[Manager.scala:238:27] .io_mem_s2_xcpt_ae_st (_dcacheArb_io_requestor_0_s2_xcpt_ae_st), // @[Manager.scala:238:27] .io_mem_s2_gpa (_dcacheArb_io_requestor_0_s2_gpa), // @[Manager.scala:238:27] .io_mem_ordered (_dcacheArb_io_requestor_0_ordered), // @[Manager.scala:238:27] .io_mem_store_pending (_dcacheArb_io_requestor_0_store_pending), // @[Manager.scala:238:27] .io_mem_perf_acquire (_dcacheArb_io_requestor_0_perf_acquire), // @[Manager.scala:238:27] .io_mem_perf_release (_dcacheArb_io_requestor_0_perf_release), // @[Manager.scala:238:27] .io_mem_perf_grant (_dcacheArb_io_requestor_0_perf_grant), // @[Manager.scala:238:27] .io_mem_perf_tlbMiss (_dcacheArb_io_requestor_0_perf_tlbMiss), // @[Manager.scala:238:27] .io_mem_perf_blocked (_dcacheArb_io_requestor_0_perf_blocked), // @[Manager.scala:238:27] .io_mem_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad), // @[Manager.scala:238:27] .io_mem_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW), // @[Manager.scala:238:27] .io_mem_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad), // @[Manager.scala:238:27] .io_mem_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad), // @[Manager.scala:238:27] .io_mem_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore), // @[Manager.scala:238:27] .io_dpath_ptbr_mode (_rerocc_manager_io_ptw_ptbr_mode), // @[Manager.scala:209:34] .io_dpath_ptbr_asid (_rerocc_manager_io_ptw_ptbr_asid), // @[Manager.scala:209:34] .io_dpath_ptbr_ppn (_rerocc_manager_io_ptw_ptbr_ppn), // @[Manager.scala:209:34] .io_dpath_sfence_valid (_rerocc_manager_io_ptw_sfence_valid), // @[Manager.scala:209:34] .io_dpath_status_debug (_rerocc_manager_io_ptw_status_debug), // @[Manager.scala:209:34] .io_dpath_status_cease (_rerocc_manager_io_ptw_status_cease), // @[Manager.scala:209:34] .io_dpath_status_wfi (_rerocc_manager_io_ptw_status_wfi), // @[Manager.scala:209:34] .io_dpath_status_isa (_rerocc_manager_io_ptw_status_isa), // @[Manager.scala:209:34] .io_dpath_status_dprv (_rerocc_manager_io_ptw_status_dprv), // @[Manager.scala:209:34] .io_dpath_status_dv (_rerocc_manager_io_ptw_status_dv), // @[Manager.scala:209:34] .io_dpath_status_prv (_rerocc_manager_io_ptw_status_prv), // @[Manager.scala:209:34] .io_dpath_status_v (_rerocc_manager_io_ptw_status_v), // @[Manager.scala:209:34] .io_dpath_status_sd (_rerocc_manager_io_ptw_status_sd), // @[Manager.scala:209:34] .io_dpath_status_zero2 (_rerocc_manager_io_ptw_status_zero2), // @[Manager.scala:209:34] .io_dpath_status_mpv (_rerocc_manager_io_ptw_status_mpv), // @[Manager.scala:209:34] .io_dpath_status_gva (_rerocc_manager_io_ptw_status_gva), // @[Manager.scala:209:34] .io_dpath_status_mbe (_rerocc_manager_io_ptw_status_mbe), // @[Manager.scala:209:34] .io_dpath_status_sbe (_rerocc_manager_io_ptw_status_sbe), // @[Manager.scala:209:34] .io_dpath_status_sxl (_rerocc_manager_io_ptw_status_sxl), // @[Manager.scala:209:34] .io_dpath_status_uxl (_rerocc_manager_io_ptw_status_uxl), // @[Manager.scala:209:34] .io_dpath_status_sd_rv32 (_rerocc_manager_io_ptw_status_sd_rv32), // @[Manager.scala:209:34] .io_dpath_status_zero1 (_rerocc_manager_io_ptw_status_zero1), // @[Manager.scala:209:34] .io_dpath_status_tsr (_rerocc_manager_io_ptw_status_tsr), // @[Manager.scala:209:34] .io_dpath_status_tw (_rerocc_manager_io_ptw_status_tw), // @[Manager.scala:209:34] .io_dpath_status_tvm (_rerocc_manager_io_ptw_status_tvm), // @[Manager.scala:209:34] .io_dpath_status_mxr (_rerocc_manager_io_ptw_status_mxr), // @[Manager.scala:209:34] .io_dpath_status_sum (_rerocc_manager_io_ptw_status_sum), // @[Manager.scala:209:34] .io_dpath_status_mprv (_rerocc_manager_io_ptw_status_mprv), // @[Manager.scala:209:34] .io_dpath_status_xs (_rerocc_manager_io_ptw_status_xs), // @[Manager.scala:209:34] .io_dpath_status_fs (_rerocc_manager_io_ptw_status_fs), // @[Manager.scala:209:34] .io_dpath_status_mpp (_rerocc_manager_io_ptw_status_mpp), // @[Manager.scala:209:34] .io_dpath_status_vs (_rerocc_manager_io_ptw_status_vs), // @[Manager.scala:209:34] .io_dpath_status_spp (_rerocc_manager_io_ptw_status_spp), // @[Manager.scala:209:34] .io_dpath_status_mpie (_rerocc_manager_io_ptw_status_mpie), // @[Manager.scala:209:34] .io_dpath_status_ube (_rerocc_manager_io_ptw_status_ube), // @[Manager.scala:209:34] .io_dpath_status_spie (_rerocc_manager_io_ptw_status_spie), // @[Manager.scala:209:34] .io_dpath_status_upie (_rerocc_manager_io_ptw_status_upie), // @[Manager.scala:209:34] .io_dpath_status_mie (_rerocc_manager_io_ptw_status_mie), // @[Manager.scala:209:34] .io_dpath_status_hie (_rerocc_manager_io_ptw_status_hie), // @[Manager.scala:209:34] .io_dpath_status_sie (_rerocc_manager_io_ptw_status_sie), // @[Manager.scala:209:34] .io_dpath_status_uie (_rerocc_manager_io_ptw_status_uie), // @[Manager.scala:209:34] .io_dpath_perf_pte_miss (_ptw_io_dpath_perf_pte_miss), .io_dpath_clock_enabled (_ptw_io_dpath_clock_enabled) ); // @[Manager.scala:243:21] SimpleHellaCacheIF_4 dcIF ( // @[Manager.scala:255:22] .clock (clock), .reset (reset), .io_requestor_req_ready (accumulator_io_mem_req_ready), .io_requestor_req_valid (accumulator_io_mem_req_valid), // @[LazyRoCC.scala:122:7] .io_requestor_req_bits_addr (accumulator_io_mem_req_bits_addr), // @[LazyRoCC.scala:122:7] .io_requestor_req_bits_tag (accumulator_io_mem_req_bits_tag), // @[LazyRoCC.scala:122:7] .io_requestor_req_bits_dprv (accumulator_io_mem_req_bits_dprv), // @[LazyRoCC.scala:122:7] .io_requestor_req_bits_dv (accumulator_io_mem_req_bits_dv), // @[LazyRoCC.scala:122:7] .io_requestor_resp_valid (accumulator_io_mem_resp_valid), .io_requestor_resp_bits_addr (accumulator_io_mem_resp_bits_addr), .io_requestor_resp_bits_tag (accumulator_io_mem_resp_bits_tag), .io_requestor_resp_bits_cmd (accumulator_io_mem_resp_bits_cmd), .io_requestor_resp_bits_size (accumulator_io_mem_resp_bits_size), .io_requestor_resp_bits_signed (accumulator_io_mem_resp_bits_signed), .io_requestor_resp_bits_dprv (accumulator_io_mem_resp_bits_dprv), .io_requestor_resp_bits_dv (accumulator_io_mem_resp_bits_dv), .io_requestor_resp_bits_data (accumulator_io_mem_resp_bits_data), .io_requestor_resp_bits_mask (accumulator_io_mem_resp_bits_mask), .io_requestor_resp_bits_replay (accumulator_io_mem_resp_bits_replay), .io_requestor_resp_bits_has_data (accumulator_io_mem_resp_bits_has_data), .io_requestor_resp_bits_data_word_bypass (accumulator_io_mem_resp_bits_data_word_bypass), .io_requestor_resp_bits_data_raw (accumulator_io_mem_resp_bits_data_raw), .io_requestor_resp_bits_store_data (accumulator_io_mem_resp_bits_store_data), .io_cache_req_ready (_dcacheArb_io_requestor_1_req_ready), // @[Manager.scala:238:27] .io_cache_req_valid (_dcIF_io_cache_req_valid), .io_cache_req_bits_addr (_dcIF_io_cache_req_bits_addr), .io_cache_req_bits_tag (_dcIF_io_cache_req_bits_tag), .io_cache_req_bits_dprv (_dcIF_io_cache_req_bits_dprv), .io_cache_req_bits_dv (_dcIF_io_cache_req_bits_dv), .io_cache_s1_data_data (_dcIF_io_cache_s1_data_data), .io_cache_s1_data_mask (_dcIF_io_cache_s1_data_mask), .io_cache_s2_nack (_dcacheArb_io_requestor_1_s2_nack), // @[Manager.scala:238:27] .io_cache_s2_nack_cause_raw (_dcacheArb_io_requestor_1_s2_nack_cause_raw), // @[Manager.scala:238:27] .io_cache_s2_uncached (_dcacheArb_io_requestor_1_s2_uncached), // @[Manager.scala:238:27] .io_cache_s2_paddr (_dcacheArb_io_requestor_1_s2_paddr), // @[Manager.scala:238:27] .io_cache_resp_valid (_dcacheArb_io_requestor_1_resp_valid), // @[Manager.scala:238:27] .io_cache_resp_bits_addr (_dcacheArb_io_requestor_1_resp_bits_addr), // @[Manager.scala:238:27] .io_cache_resp_bits_tag (_dcacheArb_io_requestor_1_resp_bits_tag), // @[Manager.scala:238:27] .io_cache_resp_bits_cmd (_dcacheArb_io_requestor_1_resp_bits_cmd), // @[Manager.scala:238:27] .io_cache_resp_bits_size (_dcacheArb_io_requestor_1_resp_bits_size), // @[Manager.scala:238:27] .io_cache_resp_bits_signed (_dcacheArb_io_requestor_1_resp_bits_signed), // @[Manager.scala:238:27] .io_cache_resp_bits_dprv (_dcacheArb_io_requestor_1_resp_bits_dprv), // @[Manager.scala:238:27] .io_cache_resp_bits_dv (_dcacheArb_io_requestor_1_resp_bits_dv), // @[Manager.scala:238:27] .io_cache_resp_bits_data (_dcacheArb_io_requestor_1_resp_bits_data), // @[Manager.scala:238:27] .io_cache_resp_bits_mask (_dcacheArb_io_requestor_1_resp_bits_mask), // @[Manager.scala:238:27] .io_cache_resp_bits_replay (_dcacheArb_io_requestor_1_resp_bits_replay), // @[Manager.scala:238:27] .io_cache_resp_bits_has_data (_dcacheArb_io_requestor_1_resp_bits_has_data), // @[Manager.scala:238:27] .io_cache_resp_bits_data_word_bypass (_dcacheArb_io_requestor_1_resp_bits_data_word_bypass), // @[Manager.scala:238:27] .io_cache_resp_bits_data_raw (_dcacheArb_io_requestor_1_resp_bits_data_raw), // @[Manager.scala:238:27] .io_cache_resp_bits_store_data (_dcacheArb_io_requestor_1_resp_bits_store_data), // @[Manager.scala:238:27] .io_cache_replay_next (_dcacheArb_io_requestor_1_replay_next), // @[Manager.scala:238:27] .io_cache_s2_xcpt_ma_ld (_dcacheArb_io_requestor_1_s2_xcpt_ma_ld), // @[Manager.scala:238:27] .io_cache_s2_xcpt_ma_st (_dcacheArb_io_requestor_1_s2_xcpt_ma_st), // @[Manager.scala:238:27] .io_cache_s2_xcpt_pf_ld (_dcacheArb_io_requestor_1_s2_xcpt_pf_ld), // @[Manager.scala:238:27] .io_cache_s2_xcpt_pf_st (_dcacheArb_io_requestor_1_s2_xcpt_pf_st), // @[Manager.scala:238:27] .io_cache_s2_xcpt_ae_ld (_dcacheArb_io_requestor_1_s2_xcpt_ae_ld), // @[Manager.scala:238:27] .io_cache_s2_xcpt_ae_st (_dcacheArb_io_requestor_1_s2_xcpt_ae_st), // @[Manager.scala:238:27] .io_cache_s2_gpa (_dcacheArb_io_requestor_1_s2_gpa), // @[Manager.scala:238:27] .io_cache_ordered (_dcacheArb_io_requestor_1_ordered), // @[Manager.scala:238:27] .io_cache_store_pending (_dcacheArb_io_requestor_1_store_pending), // @[Manager.scala:238:27] .io_cache_perf_acquire (_dcacheArb_io_requestor_1_perf_acquire), // @[Manager.scala:238:27] .io_cache_perf_release (_dcacheArb_io_requestor_1_perf_release), // @[Manager.scala:238:27] .io_cache_perf_grant (_dcacheArb_io_requestor_1_perf_grant), // @[Manager.scala:238:27] .io_cache_perf_tlbMiss (_dcacheArb_io_requestor_1_perf_tlbMiss), // @[Manager.scala:238:27] .io_cache_perf_blocked (_dcacheArb_io_requestor_1_perf_blocked), // @[Manager.scala:238:27] .io_cache_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad), // @[Manager.scala:238:27] .io_cache_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW), // @[Manager.scala:238:27] .io_cache_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad), // @[Manager.scala:238:27] .io_cache_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad), // @[Manager.scala:238:27] .io_cache_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore) // @[Manager.scala:238:27] ); // @[Manager.scala:255:22] assign auto_ctrl_ctrl_in_a_ready = auto_ctrl_ctrl_in_a_ready_0; // @[Manager.scala:237:34] assign auto_ctrl_ctrl_in_d_valid = auto_ctrl_ctrl_in_d_valid_0; // @[Manager.scala:237:34] assign auto_ctrl_ctrl_in_d_bits_opcode = auto_ctrl_ctrl_in_d_bits_opcode_0; // @[Manager.scala:237:34] assign auto_ctrl_ctrl_in_d_bits_size = auto_ctrl_ctrl_in_d_bits_size_0; // @[Manager.scala:237:34] assign auto_ctrl_ctrl_in_d_bits_source = auto_ctrl_ctrl_in_d_bits_source_0; // @[Manager.scala:237:34] assign auto_ctrl_ctrl_in_d_bits_data = auto_ctrl_ctrl_in_d_bits_data_0; // @[Manager.scala:237:34] assign auto_buffer_out_a_valid = auto_buffer_out_a_valid_0; // @[Manager.scala:237:34] assign auto_buffer_out_a_bits_opcode = auto_buffer_out_a_bits_opcode_0; // @[Manager.scala:237:34] assign auto_buffer_out_a_bits_param = auto_buffer_out_a_bits_param_0; // @[Manager.scala:237:34] assign auto_buffer_out_a_bits_size = auto_buffer_out_a_bits_size_0; // @[Manager.scala:237:34] assign auto_buffer_out_a_bits_source = auto_buffer_out_a_bits_source_0; // @[Manager.scala:237:34] assign auto_buffer_out_a_bits_address = auto_buffer_out_a_bits_address_0; // @[Manager.scala:237:34] assign auto_buffer_out_a_bits_mask = auto_buffer_out_a_bits_mask_0; // @[Manager.scala:237:34] assign auto_buffer_out_a_bits_data = auto_buffer_out_a_bits_data_0; // @[Manager.scala:237:34] assign auto_buffer_out_a_bits_corrupt = auto_buffer_out_a_bits_corrupt_0; // @[Manager.scala:237:34] assign auto_buffer_out_b_ready = auto_buffer_out_b_ready_0; // @[Manager.scala:237:34] assign auto_buffer_out_c_valid = auto_buffer_out_c_valid_0; // @[Manager.scala:237:34] assign auto_buffer_out_c_bits_opcode = auto_buffer_out_c_bits_opcode_0; // @[Manager.scala:237:34] assign auto_buffer_out_c_bits_param = auto_buffer_out_c_bits_param_0; // @[Manager.scala:237:34] assign auto_buffer_out_c_bits_size = auto_buffer_out_c_bits_size_0; // @[Manager.scala:237:34] assign auto_buffer_out_c_bits_source = auto_buffer_out_c_bits_source_0; // @[Manager.scala:237:34] assign auto_buffer_out_c_bits_address = auto_buffer_out_c_bits_address_0; // @[Manager.scala:237:34] assign auto_buffer_out_c_bits_data = auto_buffer_out_c_bits_data_0; // @[Manager.scala:237:34] assign auto_buffer_out_c_bits_corrupt = auto_buffer_out_c_bits_corrupt_0; // @[Manager.scala:237:34] assign auto_buffer_out_d_ready = auto_buffer_out_d_ready_0; // @[Manager.scala:237:34] assign auto_buffer_out_e_valid = auto_buffer_out_e_valid_0; // @[Manager.scala:237:34] assign auto_buffer_out_e_bits_sink = auto_buffer_out_e_bits_sink_0; // @[Manager.scala:237:34] assign auto_re_ro_cc_in_req_ready = auto_re_ro_cc_in_req_ready_0; // @[Manager.scala:237:34] assign auto_re_ro_cc_in_resp_valid = auto_re_ro_cc_in_resp_valid_0; // @[Manager.scala:237:34] assign auto_re_ro_cc_in_resp_bits_opcode = auto_re_ro_cc_in_resp_bits_opcode_0; // @[Manager.scala:237:34] assign auto_re_ro_cc_in_resp_bits_client_id = auto_re_ro_cc_in_resp_bits_client_id_0; // @[Manager.scala:237:34] assign auto_re_ro_cc_in_resp_bits_manager_id = auto_re_ro_cc_in_resp_bits_manager_id_0; // @[Manager.scala:237:34] assign auto_re_ro_cc_in_resp_bits_data = auto_re_ro_cc_in_resp_bits_data_0; // @[Manager.scala:237:34] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_182( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_326 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File ZstdCompressorMemWriter.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.{Printable, VecInit} import freechips.rocketchip.tile._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket.{TLBConfig} import freechips.rocketchip.util.DecoupledHelper import freechips.rocketchip.rocket.constants.MemoryOpConstants import freechips.rocketchip.tilelink._ // class WriterBundle extends Bundle { // val data = UInt(128.W) // val validbytes = UInt(6.W) // val end_of_message = Bool() // } class ZstdCompressorMemWriter(val circularQueDepth: Int = 16, val writeCmpFlag: Boolean = true, val printinfo: String = "zcmw") (implicit p: Parameters) extends ZstdCompressorModule with MemoryOpConstants { val io = IO(new Bundle { val memwrites_in = Flipped(Decoupled(new WriterBundle)) val l2io = new L2MemHelperBundle val dest_info = Flipped((Decoupled(new DstWithValInfo))) val bufs_completed = Output(UInt(64.W)) val no_writes_inflight = Output(Bool()) }) val incoming_writes_Q = Module(new Queue(new WriterBundle, queDepth)) incoming_writes_Q.io.enq <> io.memwrites_in val dest_info_Q = Module(new Queue(new DstWithValInfo, queDepth)) dest_info_Q.io.enq <> io.dest_info val decompress_dest_last_fire = RegNext(dest_info_Q.io.deq.fire) val decompress_dest_last_valid = RegNext(dest_info_Q.io.deq.valid) val decompress_dest_printhelp = dest_info_Q.io.deq.valid && (decompress_dest_last_fire \|\| (!decompress_dest_last_valid)) when (decompress_dest_printhelp) { CompressAccelLogger.logInfo("[config-memwriter] got dest info op: 0x%x, cmpflag 0x%x\n", dest_info_Q.io.deq.bits.op, dest_info_Q.io.deq.bits.cmpflag) } val buf_lens_Q = Module(new Queue(UInt(64.W), 10)) when (buf_lens_Q.io.enq.fire) { CompressAccelLogger.logInfo("[" + printinfo + "] enqueued buf len: %d\n", buf_lens_Q.io.enq.bits) } val buf_len_tracker = RegInit(0.U(64.W)) when (incoming_writes_Q.io.deq.fire) { when (incoming_writes_Q.io.deq.bits.end_of_message) { buf_len_tracker := 0.U } .otherwise { buf_len_tracker := buf_len_tracker +& incoming_writes_Q.io.deq.bits.validbytes } } when (incoming_writes_Q.io.deq.fire) { CompressAccelLogger.logInfo("[" + printinfo + "] dat: 0x%x, bytes: 0x%x, EOM: %d\n", incoming_writes_Q.io.deq.bits.data, incoming_writes_Q.io.deq.bits.validbytes, incoming_writes_Q.io.deq.bits.end_of_message ) } val NUM_QUEUES = 32 val QUEUE_DEPTHS = circularQueDepth val write_start_index = RegInit(0.U(log2Up(NUM_QUEUES+1).W)) val mem_resp_queues = Seq.fill(NUM_QUEUES)(Module(new Queue(UInt(8.W), QUEUE_DEPTHS)).io) val len_to_write = incoming_writes_Q.io.deq.bits.validbytes for ( queueno <- 0 until NUM_QUEUES ) { mem_resp_queues(queueno).enq.bits := 0.U } for ( queueno <- 0 until NUM_QUEUES ) { val idx = (write_start_index +& queueno.U) % NUM_QUEUES.U for (j <- 0 until NUM_QUEUES) { when (j.U === idx) { mem_resp_queues(j).enq.bits := (incoming_writes_Q.io.deq.bits.data >> (queueno.U << 3))(7, 0) } } } val wrap_len_index_wide = write_start_index +& len_to_write val wrap_len_index_end = wrap_len_index_wide % NUM_QUEUES.U val wrapped = wrap_len_index_wide >= NUM_QUEUES.U val all_queues_ready = mem_resp_queues.map(_.enq.ready).reduce(_ && _) val end_of_buf = incoming_writes_Q.io.deq.bits.end_of_message val account_for_buf_lens_Q = (!end_of_buf) \|\| (end_of_buf && buf_lens_Q.io.enq.ready) val input_fire_allqueues = DecoupledHelper( incoming_writes_Q.io.deq.valid, all_queues_ready, account_for_buf_lens_Q ) buf_lens_Q.io.enq.valid := input_fire_allqueues.fire(account_for_buf_lens_Q) && end_of_buf buf_lens_Q.io.enq.bits := buf_len_tracker +& incoming_writes_Q.io.deq.bits.validbytes incoming_writes_Q.io.deq.ready := input_fire_allqueues.fire(incoming_writes_Q.io.deq.valid) // when (input_fire_allqueues.fire && !end_of_buf) { when (input_fire_allqueues.fire) { write_start_index := wrap_len_index_end } for ( queueno <- 0 until NUM_QUEUES ) { val use_this_queue = Mux(wrapped, (queueno.U >= write_start_index) \|\| (queueno.U < wrap_len_index_end), (queueno.U >= write_start_index) && (queueno.U < wrap_len_index_end) ) mem_resp_queues(queueno).enq.valid := input_fire_allqueues.fire && use_this_queue } for ( queueno <- 0 until NUM_QUEUES ) { when (mem_resp_queues(queueno).deq.valid) { CompressAccelLogger.logInfo("qi%d,0x%x\n", queueno.U, mem_resp_queues(queueno).deq.bits) } } val read_start_index = RegInit(0.U(log2Up(NUM_QUEUES+1).W)) val remapVecData = Wire(Vec(NUM_QUEUES, UInt(8.W))) val remapVecValids = Wire(Vec(NUM_QUEUES, Bool())) val remapVecReadys = Wire(Vec(NUM_QUEUES, Bool())) for (queueno <- 0 until NUM_QUEUES) { remapVecData(queueno) := 0.U remapVecValids(queueno) := false.B mem_resp_queues(queueno).deq.ready := false.B } for (queueno <- 0 until NUM_QUEUES) { val remapindex = (queueno.U +& read_start_index) % NUM_QUEUES.U for (j <- 0 until NUM_QUEUES) { when (j.U === remapindex) { remapVecData(queueno) := mem_resp_queues(j).deq.bits remapVecValids(queueno) := mem_resp_queues(j).deq.valid mem_resp_queues(j).deq.ready := remapVecReadys(queueno) } } } val count_valids = remapVecValids.map(_.asUInt).reduce(_ +& _) val backend_bytes_written = RegInit(0.U(64.W)) val backend_next_write_addr = dest_info_Q.io.deq.bits.op + backend_bytes_written val throttle_end = Mux(buf_lens_Q.io.deq.valid, buf_lens_Q.io.deq.bits - backend_bytes_written, 32.U) val throttle_end_writeable = Mux(throttle_end >= 32.U, 32.U, Mux(throttle_end(4), 16.U, Mux(throttle_end(3), 8.U, Mux(throttle_end(2), 4.U, Mux(throttle_end(1), 2.U, Mux(throttle_end(0), 1.U, 0.U)))))) val throttle_end_writeable_log2 = Mux(throttle_end >= 32.U, 5.U, Mux(throttle_end(4), 4.U, Mux(throttle_end(3), 3.U, Mux(throttle_end(2), 2.U, Mux(throttle_end(1), 1.U, Mux(throttle_end(0), 0.U, 0.U)))))) val ptr_align_max_bytes_writeable = Mux(backend_next_write_addr(0), 1.U, Mux(backend_next_write_addr(1), 2.U, Mux(backend_next_write_addr(2), 4.U, Mux(backend_next_write_addr(3), 8.U, Mux(backend_next_write_addr(4), 16.U, 32.U))))) val ptr_align_max_bytes_writeable_log2 = Mux(backend_next_write_addr(0), 0.U, Mux(backend_next_write_addr(1), 1.U, Mux(backend_next_write_addr(2), 2.U, Mux(backend_next_write_addr(3), 3.U, Mux(backend_next_write_addr(4), 4.U, 5.U))))) val count_valids_largest_aligned = Mux(count_valids(5), 32.U, Mux(count_valids(4), 16.U, Mux(count_valids(3), 8.U, Mux(count_valids(2), 4.U, Mux(count_valids(1), 2.U, Mux(count_valids(0), 1.U, 0.U)))))) val count_valids_largest_aligned_log2 = Mux(count_valids(5), 5.U, Mux(count_valids(4), 4.U, Mux(count_valids(3), 3.U, Mux(count_valids(2), 2.U, Mux(count_valids(1), 1.U, Mux(count_valids(0), 0.U, 0.U)))))) // TODO: when choosing bytes_to_write, account for amount left in this buf val bytes_to_write = Mux( ptr_align_max_bytes_writeable < count_valids_largest_aligned, Mux(ptr_align_max_bytes_writeable < throttle_end_writeable, ptr_align_max_bytes_writeable, throttle_end_writeable), Mux(count_valids_largest_aligned < throttle_end_writeable, count_valids_largest_aligned, throttle_end_writeable) ) val remapped_write_data = Cat(remapVecData.reverse) // >> ((NUM_QUEUES.U - bytes_to_write) << 3) val enough_data = bytes_to_write =/= 0.U val bytes_to_write_log2 = Mux( ptr_align_max_bytes_writeable_log2 < count_valids_largest_aligned_log2, Mux(ptr_align_max_bytes_writeable_log2 < throttle_end_writeable_log2, ptr_align_max_bytes_writeable_log2, throttle_end_writeable_log2), Mux(count_valids_largest_aligned_log2 < throttle_end_writeable_log2, count_valids_largest_aligned_log2, throttle_end_writeable_log2) ) val write_ptr_override = buf_lens_Q.io.deq.valid && (buf_lens_Q.io.deq.bits === backend_bytes_written) val mem_write_fire = DecoupledHelper( io.l2io.req.ready, enough_data, !write_ptr_override, dest_info_Q.io.deq.valid ) val bool_ptr_write_fire = DecoupledHelper( io.l2io.req.ready, buf_lens_Q.io.deq.valid, buf_lens_Q.io.deq.bits === backend_bytes_written, dest_info_Q.io.deq.valid ) for (queueno <- 0 until NUM_QUEUES) { remapVecReadys(queueno) := (queueno.U < bytes_to_write) && mem_write_fire.fire } when (mem_write_fire.fire) { read_start_index := (read_start_index +& bytes_to_write) % NUM_QUEUES.U backend_bytes_written := backend_bytes_written + bytes_to_write CompressAccelLogger.logInfo("[" + printinfo + "] writefire: addr: 0x%x, data 0x%x, size %d\n", io.l2io.req.bits.addr, io.l2io.req.bits.data, io.l2io.req.bits.size ) } if (writeCmpFlag) { io.l2io.req.valid := mem_write_fire.fire(io.l2io.req.ready) \|\| bool_ptr_write_fire.fire(io.l2io.req.ready) } else { io.l2io.req.valid := mem_write_fire.fire(io.l2io.req.ready) } io.l2io.req.bits.size := Mux(write_ptr_override, 2.U, bytes_to_write_log2) io.l2io.req.bits.addr := Mux(write_ptr_override, dest_info_Q.io.deq.bits.cmpflag, backend_next_write_addr) io.l2io.req.bits.data := Mux(write_ptr_override, dest_info_Q.io.deq.bits.cmpval, remapped_write_data) io.l2io.req.bits.cmd := M_XWR buf_lens_Q.io.deq.ready := bool_ptr_write_fire.fire(buf_lens_Q.io.deq.valid) dest_info_Q.io.deq.ready := bool_ptr_write_fire.fire(dest_info_Q.io.deq.valid) val bufs_completed = RegInit(0.U(64.W)) io.bufs_completed := bufs_completed io.l2io.resp.ready := true.B io.no_writes_inflight := io.l2io.no_memops_inflight when (bool_ptr_write_fire.fire) { bufs_completed := bufs_completed + 1.U backend_bytes_written := 0.U CompressAccelLogger.logInfo("[" + printinfo + "] write cmpflag addr: 0x%x, write ptr val 0x%x\n", dest_info_Q.io.deq.bits.cmpflag, dest_info_Q.io.deq.bits.cmpval) } when (count_valids =/= 0.U) { CompressAccelLogger.logInfo("[" + printinfo + "] write_start_index %d, backend_bytes_written %d, count_valids %d, ptr_align_max_bytes_writeable %d, bytes_to_write %d, bytes_to_write_log2 %d\n", read_start_index, backend_bytes_written, count_valids, ptr_align_max_bytes_writeable, bytes_to_write, bytes_to_write_log2 ) } } File Util.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.{Printable} import freechips.rocketchip.tile._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket.{TLBConfig} import freechips.rocketchip.util.DecoupledHelper import freechips.rocketchip.rocket.constants.MemoryOpConstants object CompressAccelLogger { def logInfo(format: String, args: Bits)(implicit p: Parameters) { val loginfo_cycles = RegInit(0.U(64.W)) loginfo_cycles := loginfo_cycles + 1.U printf("cy: %d, ", loginfo_cycles) printf(Printable.pack(format, args:_)) } def logCritical(format: String, args: Bits)(implicit p: Parameters) { val loginfo_cycles = RegInit(0.U(64.W)) loginfo_cycles := loginfo_cycles + 1.U if (p(CompressAccelPrintfEnable)) { printf(midas.targetutils.SynthesizePrintf("cy: %d, ", loginfo_cycles)) printf(midas.targetutils.SynthesizePrintf(format, args:_)) } else { printf("cy: %d, ", loginfo_cycles) printf(Printable.pack(format, args:_)) } } def logWaveStyle(format: String, args: Bits)(implicit p: Parameters) { } } object CompressAccelParams { }	module ZstdCompressorMemWriter_2( // @[ZstdCompressorMemWriter.scala:23:7] input clock, // @[ZstdCompressorMemWriter.scala:23:7] input reset, // @[ZstdCompressorMemWriter.scala:23:7] output io_memwrites_in_ready, // @[ZstdCompressorMemWriter.scala:26:14] input io_memwrites_in_valid, // @[ZstdCompressorMemWriter.scala:26:14] input [255:0] io_memwrites_in_bits_data, // @[ZstdCompressorMemWriter.scala:26:14] input [5:0] io_memwrites_in_bits_validbytes, // @[ZstdCompressorMemWriter.scala:26:14] input io_memwrites_in_bits_end_of_message, // @[ZstdCompressorMemWriter.scala:26:14] input io_l2io_req_ready, // @[ZstdCompressorMemWriter.scala:26:14] output io_l2io_req_valid, // @[ZstdCompressorMemWriter.scala:26:14] output [63:0] io_l2io_req_bits_addr, // @[ZstdCompressorMemWriter.scala:26:14] output [2:0] io_l2io_req_bits_size, // @[ZstdCompressorMemWriter.scala:26:14] output [255:0] io_l2io_req_bits_data, // @[ZstdCompressorMemWriter.scala:26:14] input io_l2io_resp_valid, // @[ZstdCompressorMemWriter.scala:26:14] input [255:0] io_l2io_resp_bits_data, // @[ZstdCompressorMemWriter.scala:26:14] input io_l2io_no_memops_inflight, // @[ZstdCompressorMemWriter.scala:26:14] output io_dest_info_ready, // @[ZstdCompressorMemWriter.scala:26:14] input io_dest_info_valid, // @[ZstdCompressorMemWriter.scala:26:14] input [63:0] io_dest_info_bits_op, // @[ZstdCompressorMemWriter.scala:26:14] input [63:0] io_dest_info_bits_cmpflag, // @[ZstdCompressorMemWriter.scala:26:14] input [63:0] io_dest_info_bits_cmpval, // @[ZstdCompressorMemWriter.scala:26:14] output [63:0] io_bufs_completed, // @[ZstdCompressorMemWriter.scala:26:14] output io_no_writes_inflight // @[ZstdCompressorMemWriter.scala:26:14] ); wire _Queue16_UInt8_31_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_31_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_31_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_30_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_30_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_30_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_29_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_29_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_29_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_28_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_28_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_28_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_27_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_27_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_27_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_26_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_26_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_26_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_25_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_25_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_25_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_24_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_24_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_24_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_23_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_23_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_23_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_22_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_22_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_22_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_21_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_21_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_21_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_20_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_20_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_20_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_19_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_19_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_19_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_18_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_18_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_18_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_17_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_17_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_17_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_16_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_16_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_16_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_15_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_15_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_15_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_14_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_14_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_14_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_13_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_13_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_13_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_12_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_12_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_12_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_11_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_11_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_11_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_10_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_10_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_10_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_9_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_9_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_9_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_8_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_8_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_7_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_7_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_7_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_6_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_6_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_6_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_5_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_5_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_5_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_4_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_4_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_4_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_3_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_3_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_3_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_2_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_2_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_2_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_1_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_1_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_1_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _buf_lens_Q_io_enq_ready; // @[ZstdCompressorMemWriter.scala:52:26] wire _buf_lens_Q_io_deq_valid; // @[ZstdCompressorMemWriter.scala:52:26] wire [63:0] _buf_lens_Q_io_deq_bits; // @[ZstdCompressorMemWriter.scala:52:26] wire _dest_info_Q_io_deq_valid; // @[ZstdCompressorMemWriter.scala:39:27] wire [63:0] _dest_info_Q_io_deq_bits_op; // @[ZstdCompressorMemWriter.scala:39:27] wire [63:0] _dest_info_Q_io_deq_bits_cmpflag; // @[ZstdCompressorMemWriter.scala:39:27] wire [63:0] _dest_info_Q_io_deq_bits_cmpval; // @[ZstdCompressorMemWriter.scala:39:27] wire _incoming_writes_Q_io_deq_valid; // @[ZstdCompressorMemWriter.scala:35:33] wire [255:0] _incoming_writes_Q_io_deq_bits_data; // @[ZstdCompressorMemWriter.scala:35:33] wire [5:0] _incoming_writes_Q_io_deq_bits_validbytes; // @[ZstdCompressorMemWriter.scala:35:33] wire _incoming_writes_Q_io_deq_bits_end_of_message; // @[ZstdCompressorMemWriter.scala:35:33] wire io_memwrites_in_valid_0 = io_memwrites_in_valid; // @[ZstdCompressorMemWriter.scala:23:7] wire [255:0] io_memwrites_in_bits_data_0 = io_memwrites_in_bits_data; // @[ZstdCompressorMemWriter.scala:23:7] wire [5:0] io_memwrites_in_bits_validbytes_0 = io_memwrites_in_bits_validbytes; // @[ZstdCompressorMemWriter.scala:23:7] wire io_memwrites_in_bits_end_of_message_0 = io_memwrites_in_bits_end_of_message; // @[ZstdCompressorMemWriter.scala:23:7] wire io_l2io_req_ready_0 = io_l2io_req_ready; // @[ZstdCompressorMemWriter.scala:23:7] wire io_l2io_resp_valid_0 = io_l2io_resp_valid; // @[ZstdCompressorMemWriter.scala:23:7] wire [255:0] io_l2io_resp_bits_data_0 = io_l2io_resp_bits_data; // @[ZstdCompressorMemWriter.scala:23:7] wire io_l2io_no_memops_inflight_0 = io_l2io_no_memops_inflight; // @[ZstdCompressorMemWriter.scala:23:7] wire io_dest_info_valid_0 = io_dest_info_valid; // @[ZstdCompressorMemWriter.scala:23:7] wire [63:0] io_dest_info_bits_op_0 = io_dest_info_bits_op; // @[ZstdCompressorMemWriter.scala:23:7] wire [63:0] io_dest_info_bits_cmpflag_0 = io_dest_info_bits_cmpflag; // @[ZstdCompressorMemWriter.scala:23:7] wire [63:0] io_dest_info_bits_cmpval_0 = io_dest_info_bits_cmpval; // @[ZstdCompressorMemWriter.scala:23:7] wire io_l2io_req_bits_cmd = 1'h1; // @[ZstdCompressorMemWriter.scala:23:7] wire io_l2io_resp_ready = 1'h1; // @[ZstdCompressorMemWriter.scala:23:7] wire _throttle_end_writeable_log2_T_6 = 1'h0; // @[ZstdCompressorMemWriter.scala:187:50] wire _count_valids_largest_aligned_log2_T_6 = 1'h0; // @[ZstdCompressorMemWriter.scala:218:56] wire _io_l2io_req_valid_T_1; // @[Misc.scala:26:53] wire [63:0] _io_l2io_req_bits_addr_T; // @[ZstdCompressorMemWriter.scala:283:31] wire [2:0] _io_l2io_req_bits_size_T; // @[ZstdCompressorMemWriter.scala:282:31] wire [255:0] _io_l2io_req_bits_data_T; // @[ZstdCompressorMemWriter.scala:284:31] wire io_no_writes_inflight_0 = io_l2io_no_memops_inflight_0; // @[ZstdCompressorMemWriter.scala:23:7] wire io_memwrites_in_ready_0; // @[ZstdCompressorMemWriter.scala:23:7] wire [63:0] io_l2io_req_bits_addr_0; // @[ZstdCompressorMemWriter.scala:23:7] wire [2:0] io_l2io_req_bits_size_0; // @[ZstdCompressorMemWriter.scala:23:7] wire [255:0] io_l2io_req_bits_data_0; // @[ZstdCompressorMemWriter.scala:23:7] wire io_l2io_req_valid_0; // @[ZstdCompressorMemWriter.scala:23:7] wire io_dest_info_ready_0; // @[ZstdCompressorMemWriter.scala:23:7] wire [63:0] io_bufs_completed_0; // @[ZstdCompressorMemWriter.scala:23:7] wire _dest_info_Q_io_deq_ready_T_1; // @[Misc.scala:26:53] wire _decompress_dest_last_fire_T = _dest_info_Q_io_deq_ready_T_1 & _dest_info_Q_io_deq_valid; // @[Decoupled.scala:51:35] reg decompress_dest_last_fire; // @[ZstdCompressorMemWriter.scala:42:42] reg decompress_dest_last_valid; // @[ZstdCompressorMemWriter.scala:43:43] wire _decompress_dest_printhelp_T = ~decompress_dest_last_valid; // @[ZstdCompressorMemWriter.scala:43:43, :44:94] wire _decompress_dest_printhelp_T_1 = decompress_dest_last_fire \| _decompress_dest_printhelp_T; // @[ZstdCompressorMemWriter.scala:42:42, :44:{90,94}] wire decompress_dest_printhelp = _dest_info_Q_io_deq_valid & _decompress_dest_printhelp_T_1; // @[ZstdCompressorMemWriter.scala:39:27, :44:{60,90}] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38] reg [63:0] buf_len_tracker; // @[ZstdCompressorMemWriter.scala:57:32] wire _incoming_writes_Q_io_deq_ready_T; // @[Misc.scala:26:53] wire _T_10 = _incoming_writes_Q_io_deq_ready_T & _incoming_writes_Q_io_deq_valid; // @[Decoupled.scala:51:35] wire [64:0] _GEN = {1'h0, buf_len_tracker} + {59'h0, _incoming_writes_Q_io_deq_bits_validbytes}; // @[ZstdCompressorMemWriter.scala:35:33, :57:32, :62:42] wire [64:0] _buf_len_tracker_T; // @[ZstdCompressorMemWriter.scala:62:42] assign _buf_len_tracker_T = _GEN; // @[ZstdCompressorMemWriter.scala:62:42] wire [64:0] _buf_lens_Q_io_enq_bits_T; // @[ZstdCompressorMemWriter.scala:112:45] assign _buf_lens_Q_io_enq_bits_T = _GEN; // @[ZstdCompressorMemWriter.scala:62:42, :112:45] reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38] reg [5:0] write_start_index; // @[ZstdCompressorMemWriter.scala:76:34] wire [6:0] _idx_T = {1'h0, write_start_index}; // @[ZstdCompressorMemWriter.scala:76:34, :86:34] wire [6:0] _GEN_0 = _idx_T % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx = _GEN_0[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_1 = _idx_T + 7'h1; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_1 = _idx_T_1 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_1 = _GEN_1[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_2 = _idx_T + 7'h2; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_2 = _idx_T_2 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_2 = _GEN_2[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_3 = _idx_T + 7'h3; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_3 = _idx_T_3 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_3 = _GEN_3[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_4 = _idx_T + 7'h4; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_4 = _idx_T_4 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_4 = _GEN_4[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_5 = _idx_T + 7'h5; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_5 = _idx_T_5 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_5 = _GEN_5[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_6 = _idx_T + 7'h6; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_6 = _idx_T_6 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_6 = _GEN_6[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_7 = _idx_T + 7'h7; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_7 = _idx_T_7 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_7 = _GEN_7[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_8 = _idx_T + 7'h8; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_8 = _idx_T_8 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_8 = _GEN_8[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_9 = _idx_T + 7'h9; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_9 = _idx_T_9 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_9 = _GEN_9[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_10 = _idx_T + 7'hA; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_10 = _idx_T_10 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_10 = _GEN_10[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_11 = _idx_T + 7'hB; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_11 = _idx_T_11 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_11 = _GEN_11[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_12 = _idx_T + 7'hC; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_12 = _idx_T_12 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_12 = _GEN_12[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_13 = _idx_T + 7'hD; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_13 = _idx_T_13 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_13 = _GEN_13[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_14 = _idx_T + 7'hE; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_14 = _idx_T_14 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_14 = _GEN_14[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_15 = _idx_T + 7'hF; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_15 = _idx_T_15 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_15 = _GEN_15[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_16 = _idx_T + 7'h10; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_16 = _idx_T_16 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_16 = _GEN_16[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_17 = _idx_T + 7'h11; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_17 = _idx_T_17 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_17 = _GEN_17[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_18 = _idx_T + 7'h12; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_18 = _idx_T_18 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_18 = _GEN_18[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_19 = _idx_T + 7'h13; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_19 = _idx_T_19 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_19 = _GEN_19[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_20 = _idx_T + 7'h14; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_20 = _idx_T_20 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_20 = _GEN_20[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_21 = _idx_T + 7'h15; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_21 = _idx_T_21 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_21 = _GEN_21[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_22 = _idx_T + 7'h16; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_22 = _idx_T_22 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_22 = _GEN_22[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_23 = _idx_T + 7'h17; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_23 = _idx_T_23 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_23 = _GEN_23[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_24 = _idx_T + 7'h18; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_24 = _idx_T_24 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_24 = _GEN_24[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_25 = _idx_T + 7'h19; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_25 = _idx_T_25 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_25 = _GEN_25[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_26 = _idx_T + 7'h1A; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_26 = _idx_T_26 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_26 = _GEN_26[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_27 = _idx_T + 7'h1B; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_27 = _idx_T_27 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_27 = _GEN_27[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_28 = _idx_T + 7'h1C; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_28 = _idx_T_28 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_28 = _GEN_28[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_29 = _idx_T + 7'h1D; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_29 = _idx_T_29 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_29 = _GEN_29[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_30 = _idx_T + 7'h1E; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_30 = _idx_T_30 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_30 = _GEN_30[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_31 = _idx_T + 7'h1F; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_31 = _idx_T_31 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_31 = _GEN_31[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] wrap_len_index_wide = _idx_T + {1'h0, _incoming_writes_Q_io_deq_bits_validbytes}; // @[ZstdCompressorMemWriter.scala:35:33, :86:34, :95:47] wire [6:0] _GEN_32 = wrap_len_index_wide % 7'h20; // @[ZstdCompressorMemWriter.scala:95:47, :96:48] wire [5:0] wrap_len_index_end = _GEN_32[5:0]; // @[ZstdCompressorMemWriter.scala:96:48] wire wrapped = \|(wrap_len_index_wide[6:5]); // @[ZstdCompressorMemWriter.scala:95:47, :97:37] wire _all_queues_ready_T = _Queue16_UInt8_io_enq_ready & _Queue16_UInt8_1_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_1 = _all_queues_ready_T & _Queue16_UInt8_2_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_2 = _all_queues_ready_T_1 & _Queue16_UInt8_3_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_3 = _all_queues_ready_T_2 & _Queue16_UInt8_4_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_4 = _all_queues_ready_T_3 & _Queue16_UInt8_5_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_5 = _all_queues_ready_T_4 & _Queue16_UInt8_6_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_6 = _all_queues_ready_T_5 & _Queue16_UInt8_7_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_7 = _all_queues_ready_T_6 & _Queue16_UInt8_8_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_8 = _all_queues_ready_T_7 & _Queue16_UInt8_9_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_9 = _all_queues_ready_T_8 & _Queue16_UInt8_10_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_10 = _all_queues_ready_T_9 & _Queue16_UInt8_11_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_11 = _all_queues_ready_T_10 & _Queue16_UInt8_12_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_12 = _all_queues_ready_T_11 & _Queue16_UInt8_13_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_13 = _all_queues_ready_T_12 & _Queue16_UInt8_14_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_14 = _all_queues_ready_T_13 & _Queue16_UInt8_15_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_15 = _all_queues_ready_T_14 & _Queue16_UInt8_16_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_16 = _all_queues_ready_T_15 & _Queue16_UInt8_17_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_17 = _all_queues_ready_T_16 & _Queue16_UInt8_18_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_18 = _all_queues_ready_T_17 & _Queue16_UInt8_19_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_19 = _all_queues_ready_T_18 & _Queue16_UInt8_20_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_20 = _all_queues_ready_T_19 & _Queue16_UInt8_21_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_21 = _all_queues_ready_T_20 & _Queue16_UInt8_22_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_22 = _all_queues_ready_T_21 & _Queue16_UInt8_23_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_23 = _all_queues_ready_T_22 & _Queue16_UInt8_24_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_24 = _all_queues_ready_T_23 & _Queue16_UInt8_25_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_25 = _all_queues_ready_T_24 & _Queue16_UInt8_26_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_26 = _all_queues_ready_T_25 & _Queue16_UInt8_27_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_27 = _all_queues_ready_T_26 & _Queue16_UInt8_28_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_28 = _all_queues_ready_T_27 & _Queue16_UInt8_29_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_29 = _all_queues_ready_T_28 & _Queue16_UInt8_30_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire all_queues_ready = _all_queues_ready_T_29 & _Queue16_UInt8_31_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _account_for_buf_lens_Q_T = ~_incoming_writes_Q_io_deq_bits_end_of_message; // @[ZstdCompressorMemWriter.scala:35:33, :103:33] wire _account_for_buf_lens_Q_T_1 = _incoming_writes_Q_io_deq_bits_end_of_message & _buf_lens_Q_io_enq_ready; // @[ZstdCompressorMemWriter.scala:35:33, :52:26, :103:61] wire account_for_buf_lens_Q = _account_for_buf_lens_Q_T \| _account_for_buf_lens_Q_T_1; // @[ZstdCompressorMemWriter.scala:103:{33,46,61}] wire _buf_lens_Q_io_enq_valid_T = _incoming_writes_Q_io_deq_valid & all_queues_ready; // @[Misc.scala:26:53] wire _buf_lens_Q_io_enq_valid_T_1 = _buf_lens_Q_io_enq_valid_T & _incoming_writes_Q_io_deq_bits_end_of_message; // @[Misc.scala:26:53] assign _incoming_writes_Q_io_deq_ready_T = all_queues_ready & account_for_buf_lens_Q; // @[Misc.scala:26:53] wire _GEN_33 = write_start_index == 6'h0; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T = _GEN_33; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_3; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_3 = _GEN_33; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _use_this_queue_T_1 = \|wrap_len_index_end; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_2 = _use_this_queue_T \| _use_this_queue_T_1; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_4 = \|wrap_len_index_end; // @[ZstdCompressorMemWriter.scala:96:48, :124:77, :125:77] wire _use_this_queue_T_5 = _use_this_queue_T_3 & _use_this_queue_T_4; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue = wrapped ? _use_this_queue_T_2 : _use_this_queue_T_5; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_34 = write_start_index < 6'h2; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_6; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_6 = _GEN_34; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_9; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_9 = _GEN_34; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _use_this_queue_T_7 = \|(wrap_len_index_end[5:1]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_8 = _use_this_queue_T_6 \| _use_this_queue_T_7; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_10 = \|(wrap_len_index_end[5:1]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77, :125:77] wire _use_this_queue_T_11 = _use_this_queue_T_9 & _use_this_queue_T_10; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_1 = wrapped ? _use_this_queue_T_8 : _use_this_queue_T_11; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_35 = write_start_index < 6'h3; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_12; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_12 = _GEN_35; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_15; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_15 = _GEN_35; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_36 = wrap_len_index_end > 6'h2; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_13; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_13 = _GEN_36; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_16; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_16 = _GEN_36; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_14 = _use_this_queue_T_12 \| _use_this_queue_T_13; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_17 = _use_this_queue_T_15 & _use_this_queue_T_16; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_2 = wrapped ? _use_this_queue_T_14 : _use_this_queue_T_17; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_37 = write_start_index < 6'h4; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_18; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_18 = _GEN_37; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_21; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_21 = _GEN_37; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _use_this_queue_T_19 = \|(wrap_len_index_end[5:2]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_20 = _use_this_queue_T_18 \| _use_this_queue_T_19; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_22 = \|(wrap_len_index_end[5:2]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77, :125:77] wire _use_this_queue_T_23 = _use_this_queue_T_21 & _use_this_queue_T_22; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_3 = wrapped ? _use_this_queue_T_20 : _use_this_queue_T_23; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_38 = write_start_index < 6'h5; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_24; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_24 = _GEN_38; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_27; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_27 = _GEN_38; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_39 = wrap_len_index_end > 6'h4; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_25; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_25 = _GEN_39; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_28; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_28 = _GEN_39; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_26 = _use_this_queue_T_24 \| _use_this_queue_T_25; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_29 = _use_this_queue_T_27 & _use_this_queue_T_28; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_4 = wrapped ? _use_this_queue_T_26 : _use_this_queue_T_29; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_40 = write_start_index < 6'h6; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_30; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_30 = _GEN_40; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_33; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_33 = _GEN_40; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_41 = wrap_len_index_end > 6'h5; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_31; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_31 = _GEN_41; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_34; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_34 = _GEN_41; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_32 = _use_this_queue_T_30 \| _use_this_queue_T_31; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_35 = _use_this_queue_T_33 & _use_this_queue_T_34; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_5 = wrapped ? _use_this_queue_T_32 : _use_this_queue_T_35; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_42 = write_start_index < 6'h7; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_36; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_36 = _GEN_42; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_39; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_39 = _GEN_42; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_43 = wrap_len_index_end > 6'h6; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_37; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_37 = _GEN_43; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_40; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_40 = _GEN_43; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_38 = _use_this_queue_T_36 \| _use_this_queue_T_37; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_41 = _use_this_queue_T_39 & _use_this_queue_T_40; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_6 = wrapped ? _use_this_queue_T_38 : _use_this_queue_T_41; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_44 = write_start_index < 6'h8; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_42; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_42 = _GEN_44; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_45; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_45 = _GEN_44; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _use_this_queue_T_43 = \|(wrap_len_index_end[5:3]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_44 = _use_this_queue_T_42 \| _use_this_queue_T_43; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_46 = \|(wrap_len_index_end[5:3]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77, :125:77] wire _use_this_queue_T_47 = _use_this_queue_T_45 & _use_this_queue_T_46; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_7 = wrapped ? _use_this_queue_T_44 : _use_this_queue_T_47; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_45 = write_start_index < 6'h9; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_48; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_48 = _GEN_45; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_51; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_51 = _GEN_45; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_46 = wrap_len_index_end > 6'h8; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_49; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_49 = _GEN_46; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_52; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_52 = _GEN_46; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_50 = _use_this_queue_T_48 \| _use_this_queue_T_49; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_53 = _use_this_queue_T_51 & _use_this_queue_T_52; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_8 = wrapped ? _use_this_queue_T_50 : _use_this_queue_T_53; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_47 = write_start_index < 6'hA; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_54; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_54 = _GEN_47; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_57; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_57 = _GEN_47; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_48 = wrap_len_index_end > 6'h9; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_55; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_55 = _GEN_48; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_58; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_58 = _GEN_48; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_56 = _use_this_queue_T_54 \| _use_this_queue_T_55; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_59 = _use_this_queue_T_57 & _use_this_queue_T_58; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_9 = wrapped ? _use_this_queue_T_56 : _use_this_queue_T_59; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_49 = write_start_index < 6'hB; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_60; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_60 = _GEN_49; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_63; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_63 = _GEN_49; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_50 = wrap_len_index_end > 6'hA; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_61; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_61 = _GEN_50; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_64; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_64 = _GEN_50; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_62 = _use_this_queue_T_60 \| _use_this_queue_T_61; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_65 = _use_this_queue_T_63 & _use_this_queue_T_64; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_10 = wrapped ? _use_this_queue_T_62 : _use_this_queue_T_65; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_51 = write_start_index < 6'hC; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_66; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_66 = _GEN_51; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_69; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_69 = _GEN_51; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_52 = wrap_len_index_end > 6'hB; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_67; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_67 = _GEN_52; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_70; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_70 = _GEN_52; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_68 = _use_this_queue_T_66 \| _use_this_queue_T_67; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_71 = _use_this_queue_T_69 & _use_this_queue_T_70; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_11 = wrapped ? _use_this_queue_T_68 : _use_this_queue_T_71; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_53 = write_start_index < 6'hD; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_72; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_72 = _GEN_53; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_75; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_75 = _GEN_53; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_54 = wrap_len_index_end > 6'hC; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_73; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_73 = _GEN_54; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_76; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_76 = _GEN_54; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_74 = _use_this_queue_T_72 \| _use_this_queue_T_73; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_77 = _use_this_queue_T_75 & _use_this_queue_T_76; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_12 = wrapped ? _use_this_queue_T_74 : _use_this_queue_T_77; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_55 = write_start_index < 6'hE; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_78; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_78 = _GEN_55; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_81; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_81 = _GEN_55; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_56 = wrap_len_index_end > 6'hD; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_79; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_79 = _GEN_56; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_82; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_82 = _GEN_56; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_80 = _use_this_queue_T_78 \| _use_this_queue_T_79; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_83 = _use_this_queue_T_81 & _use_this_queue_T_82; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_13 = wrapped ? _use_this_queue_T_80 : _use_this_queue_T_83; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_57 = write_start_index < 6'hF; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_84; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_84 = _GEN_57; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_87; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_87 = _GEN_57; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_58 = wrap_len_index_end > 6'hE; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_85; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_85 = _GEN_58; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_88; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_88 = _GEN_58; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_86 = _use_this_queue_T_84 \| _use_this_queue_T_85; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_89 = _use_this_queue_T_87 & _use_this_queue_T_88; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_14 = wrapped ? _use_this_queue_T_86 : _use_this_queue_T_89; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_59 = write_start_index < 6'h10; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_90; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_90 = _GEN_59; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_93; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_93 = _GEN_59; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _use_this_queue_T_91 = \|(wrap_len_index_end[5:4]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_92 = _use_this_queue_T_90 \| _use_this_queue_T_91; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_94 = \|(wrap_len_index_end[5:4]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77, :125:77] wire _use_this_queue_T_95 = _use_this_queue_T_93 & _use_this_queue_T_94; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_15 = wrapped ? _use_this_queue_T_92 : _use_this_queue_T_95; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_60 = write_start_index < 6'h11; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_96; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_96 = _GEN_60; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_99; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_99 = _GEN_60; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_61 = wrap_len_index_end > 6'h10; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_97; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_97 = _GEN_61; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_100; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_100 = _GEN_61; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_98 = _use_this_queue_T_96 \| _use_this_queue_T_97; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_101 = _use_this_queue_T_99 & _use_this_queue_T_100; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_16 = wrapped ? _use_this_queue_T_98 : _use_this_queue_T_101; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_62 = write_start_index < 6'h12; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_102; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_102 = _GEN_62; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_105; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_105 = _GEN_62; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_63 = wrap_len_index_end > 6'h11; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_103; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_103 = _GEN_63; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_106; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_106 = _GEN_63; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_104 = _use_this_queue_T_102 \| _use_this_queue_T_103; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_107 = _use_this_queue_T_105 & _use_this_queue_T_106; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_17 = wrapped ? _use_this_queue_T_104 : _use_this_queue_T_107; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_64 = write_start_index < 6'h13; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_108; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_108 = _GEN_64; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_111; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_111 = _GEN_64; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_65 = wrap_len_index_end > 6'h12; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_109; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_109 = _GEN_65; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_112; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_112 = _GEN_65; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_110 = _use_this_queue_T_108 \| _use_this_queue_T_109; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_113 = _use_this_queue_T_111 & _use_this_queue_T_112; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_18 = wrapped ? _use_this_queue_T_110 : _use_this_queue_T_113; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_66 = write_start_index < 6'h14; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_114; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_114 = _GEN_66; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_117; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_117 = _GEN_66; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_67 = wrap_len_index_end > 6'h13; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_115; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_115 = _GEN_67; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_118; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_118 = _GEN_67; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_116 = _use_this_queue_T_114 \| _use_this_queue_T_115; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_119 = _use_this_queue_T_117 & _use_this_queue_T_118; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_19 = wrapped ? _use_this_queue_T_116 : _use_this_queue_T_119; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_68 = write_start_index < 6'h15; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_120; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_120 = _GEN_68; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_123; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_123 = _GEN_68; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_69 = wrap_len_index_end > 6'h14; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_121; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_121 = _GEN_69; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_124; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_124 = _GEN_69; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_122 = _use_this_queue_T_120 \| _use_this_queue_T_121; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_125 = _use_this_queue_T_123 & _use_this_queue_T_124; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_20 = wrapped ? _use_this_queue_T_122 : _use_this_queue_T_125; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_70 = write_start_index < 6'h16; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_126; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_126 = _GEN_70; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_129; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_129 = _GEN_70; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_71 = wrap_len_index_end > 6'h15; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_127; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_127 = _GEN_71; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_130; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_130 = _GEN_71; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_128 = _use_this_queue_T_126 \| _use_this_queue_T_127; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_131 = _use_this_queue_T_129 & _use_this_queue_T_130; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_21 = wrapped ? _use_this_queue_T_128 : _use_this_queue_T_131; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_72 = write_start_index < 6'h17; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_132; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_132 = _GEN_72; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_135; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_135 = _GEN_72; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_73 = wrap_len_index_end > 6'h16; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_133; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_133 = _GEN_73; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_136; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_136 = _GEN_73; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_134 = _use_this_queue_T_132 \| _use_this_queue_T_133; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_137 = _use_this_queue_T_135 & _use_this_queue_T_136; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_22 = wrapped ? _use_this_queue_T_134 : _use_this_queue_T_137; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_74 = write_start_index < 6'h18; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_138; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_138 = _GEN_74; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_141; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_141 = _GEN_74; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_75 = wrap_len_index_end > 6'h17; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_139; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_139 = _GEN_75; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_142; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_142 = _GEN_75; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_140 = _use_this_queue_T_138 \| _use_this_queue_T_139; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_143 = _use_this_queue_T_141 & _use_this_queue_T_142; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_23 = wrapped ? _use_this_queue_T_140 : _use_this_queue_T_143; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_76 = write_start_index < 6'h19; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_144; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_144 = _GEN_76; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_147; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_147 = _GEN_76; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_77 = wrap_len_index_end > 6'h18; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_145; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_145 = _GEN_77; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_148; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_148 = _GEN_77; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_146 = _use_this_queue_T_144 \| _use_this_queue_T_145; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_149 = _use_this_queue_T_147 & _use_this_queue_T_148; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_24 = wrapped ? _use_this_queue_T_146 : _use_this_queue_T_149; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_78 = write_start_index < 6'h1A; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_150; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_150 = _GEN_78; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_153; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_153 = _GEN_78; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_79 = wrap_len_index_end > 6'h19; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_151; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_151 = _GEN_79; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_154; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_154 = _GEN_79; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_152 = _use_this_queue_T_150 \| _use_this_queue_T_151; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_155 = _use_this_queue_T_153 & _use_this_queue_T_154; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_25 = wrapped ? _use_this_queue_T_152 : _use_this_queue_T_155; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_80 = write_start_index < 6'h1B; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_156; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_156 = _GEN_80; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_159; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_159 = _GEN_80; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_81 = wrap_len_index_end > 6'h1A; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_157; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_157 = _GEN_81; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_160; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_160 = _GEN_81; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_158 = _use_this_queue_T_156 \| _use_this_queue_T_157; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_161 = _use_this_queue_T_159 & _use_this_queue_T_160; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_26 = wrapped ? _use_this_queue_T_158 : _use_this_queue_T_161; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_82 = write_start_index < 6'h1C; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_162; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_162 = _GEN_82; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_165; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_165 = _GEN_82; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_83 = wrap_len_index_end > 6'h1B; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_163; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_163 = _GEN_83; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_166; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_166 = _GEN_83; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_164 = _use_this_queue_T_162 \| _use_this_queue_T_163; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_167 = _use_this_queue_T_165 & _use_this_queue_T_166; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_27 = wrapped ? _use_this_queue_T_164 : _use_this_queue_T_167; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_84 = write_start_index < 6'h1D; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_168; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_168 = _GEN_84; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_171; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_171 = _GEN_84; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_85 = wrap_len_index_end > 6'h1C; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_169; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_169 = _GEN_85; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_172; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_172 = _GEN_85; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_170 = _use_this_queue_T_168 \| _use_this_queue_T_169; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_173 = _use_this_queue_T_171 & _use_this_queue_T_172; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_28 = wrapped ? _use_this_queue_T_170 : _use_this_queue_T_173; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_86 = write_start_index < 6'h1E; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_174; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_174 = _GEN_86; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_177; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_177 = _GEN_86; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_87 = wrap_len_index_end > 6'h1D; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_175; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_175 = _GEN_87; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_178; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_178 = _GEN_87; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_176 = _use_this_queue_T_174 \| _use_this_queue_T_175; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_179 = _use_this_queue_T_177 & _use_this_queue_T_178; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_29 = wrapped ? _use_this_queue_T_176 : _use_this_queue_T_179; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_88 = write_start_index < 6'h1F; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_180; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_180 = _GEN_88; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_183; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_183 = _GEN_88; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_89 = wrap_len_index_end > 6'h1E; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_181; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_181 = _GEN_89; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_184; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_184 = _GEN_89; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_182 = _use_this_queue_T_180 \| _use_this_queue_T_181; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_185 = _use_this_queue_T_183 & _use_this_queue_T_184; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_30 = wrapped ? _use_this_queue_T_182 : _use_this_queue_T_185; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _use_this_queue_T_186 = ~(write_start_index[5]); // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_187 = wrap_len_index_end[5]; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_190 = wrap_len_index_end[5]; // @[ZstdCompressorMemWriter.scala:96:48, :124:77, :125:77] wire _use_this_queue_T_188 = _use_this_queue_T_186 \| _use_this_queue_T_187; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_189 = ~(write_start_index[5]); // @[ZstdCompressorMemWriter.scala:76:34, :124:41, :125:41] wire _use_this_queue_T_191 = _use_this_queue_T_189 & _use_this_queue_T_190; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_31 = wrapped ? _use_this_queue_T_188 : _use_this_queue_T_191; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_6; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_12; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_24 = {1'h0, loginfo_cycles_12} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_13; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_26 = {1'h0, loginfo_cycles_13} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_14; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_28 = {1'h0, loginfo_cycles_14} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_15; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_30 = {1'h0, loginfo_cycles_15} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_31 = _loginfo_cycles_T_30[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_16; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_32 = {1'h0, loginfo_cycles_16} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_33 = _loginfo_cycles_T_32[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_17; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_34 = {1'h0, loginfo_cycles_17} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_35 = _loginfo_cycles_T_34[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_18; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_36 = {1'h0, loginfo_cycles_18} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_37 = _loginfo_cycles_T_36[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_19; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_38 = {1'h0, loginfo_cycles_19} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_39 = _loginfo_cycles_T_38[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_20; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_40 = {1'h0, loginfo_cycles_20} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_41 = _loginfo_cycles_T_40[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_21; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_42 = {1'h0, loginfo_cycles_21} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_43 = _loginfo_cycles_T_42[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_22; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_44 = {1'h0, loginfo_cycles_22} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_45 = _loginfo_cycles_T_44[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_23; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_46 = {1'h0, loginfo_cycles_23} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_47 = _loginfo_cycles_T_46[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_24; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_48 = {1'h0, loginfo_cycles_24} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_49 = _loginfo_cycles_T_48[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_25; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_50 = {1'h0, loginfo_cycles_25} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_51 = _loginfo_cycles_T_50[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_26; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_52 = {1'h0, loginfo_cycles_26} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_53 = _loginfo_cycles_T_52[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_27; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_54 = {1'h0, loginfo_cycles_27} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_55 = _loginfo_cycles_T_54[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_28; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_56 = {1'h0, loginfo_cycles_28} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_57 = _loginfo_cycles_T_56[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_29; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_58 = {1'h0, loginfo_cycles_29} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_59 = _loginfo_cycles_T_58[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_30; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_60 = {1'h0, loginfo_cycles_30} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_61 = _loginfo_cycles_T_60[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_31; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_62 = {1'h0, loginfo_cycles_31} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_63 = _loginfo_cycles_T_62[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_32; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_64 = {1'h0, loginfo_cycles_32} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_65 = _loginfo_cycles_T_64[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_33; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_66 = {1'h0, loginfo_cycles_33} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_67 = _loginfo_cycles_T_66[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_34; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_68 = {1'h0, loginfo_cycles_34} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_69 = _loginfo_cycles_T_68[63:0]; // @[Util.scala:19:38] reg [5:0] read_start_index; // @[ZstdCompressorMemWriter.scala:139:33] wire [7:0] remapVecData_0; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_1; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_2; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_3; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_4; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_5; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_6; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_7; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_8; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_9; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_10; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_11; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_12; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_13; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_14; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_15; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_16; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_17; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_18; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_19; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_20; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_21; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_22; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_23; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_24; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_25; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_26; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_27; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_28; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_29; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_30; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_31; // @[ZstdCompressorMemWriter.scala:141:26] wire remapVecValids_0; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_1; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_2; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_3; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_4; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_5; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_6; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_7; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_8; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_9; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_10; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_11; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_12; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_13; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_14; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_15; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_16; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_17; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_18; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_19; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_20; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_21; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_22; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_23; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_24; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_25; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_26; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_27; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_28; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_29; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_30; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_31; // @[ZstdCompressorMemWriter.scala:142:28] wire _remapVecReadys_0_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_1_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_2_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_3_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_4_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_5_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_6_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_7_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_8_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_9_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_10_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_11_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_12_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_13_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_14_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_15_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_16_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_17_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_18_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_19_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_20_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_21_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_22_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_23_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_24_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_25_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_26_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_27_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_28_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_29_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_30_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_31_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire remapVecReadys_0; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_1; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_2; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_3; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_4; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_5; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_6; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_7; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_8; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_9; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_10; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_11; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_12; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_13; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_14; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_15; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_16; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_17; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_18; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_19; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_20; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_21; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_22; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_23; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_24; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_25; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_26; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_27; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_28; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_29; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_30; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_31; // @[ZstdCompressorMemWriter.scala:143:28] wire [6:0] _remapindex_T = {1'h0, read_start_index}; // @[ZstdCompressorMemWriter.scala:139:33, :153:33] wire [6:0] _GEN_90 = _remapindex_T % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex = _GEN_90[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4337 = remapindex == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4338 = remapindex == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4339 = remapindex == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4340 = remapindex == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4341 = remapindex == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4342 = remapindex == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4343 = remapindex == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4344 = remapindex == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4345 = remapindex == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4346 = remapindex == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4347 = remapindex == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4348 = remapindex == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4349 = remapindex == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4350 = remapindex == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4351 = remapindex == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4352 = remapindex == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4353 = remapindex == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4354 = remapindex == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4355 = remapindex == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4356 = remapindex == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4357 = remapindex == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4358 = remapindex == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4359 = remapindex == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4360 = remapindex == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4361 = remapindex == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4362 = remapindex == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4363 = remapindex == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4364 = remapindex == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4365 = remapindex == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4366 = remapindex == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4367 = remapindex == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4368 = remapindex == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_0 = _T_4368 ? _Queue16_UInt8_31_io_deq_bits : _T_4367 ? _Queue16_UInt8_30_io_deq_bits : _T_4366 ? _Queue16_UInt8_29_io_deq_bits : _T_4365 ? _Queue16_UInt8_28_io_deq_bits : _T_4364 ? _Queue16_UInt8_27_io_deq_bits : _T_4363 ? _Queue16_UInt8_26_io_deq_bits : _T_4362 ? _Queue16_UInt8_25_io_deq_bits : _T_4361 ? _Queue16_UInt8_24_io_deq_bits : _T_4360 ? _Queue16_UInt8_23_io_deq_bits : _T_4359 ? _Queue16_UInt8_22_io_deq_bits : _T_4358 ? _Queue16_UInt8_21_io_deq_bits : _T_4357 ? _Queue16_UInt8_20_io_deq_bits : _T_4356 ? _Queue16_UInt8_19_io_deq_bits : _T_4355 ? _Queue16_UInt8_18_io_deq_bits : _T_4354 ? _Queue16_UInt8_17_io_deq_bits : _T_4353 ? _Queue16_UInt8_16_io_deq_bits : _T_4352 ? _Queue16_UInt8_15_io_deq_bits : _T_4351 ? _Queue16_UInt8_14_io_deq_bits : _T_4350 ? _Queue16_UInt8_13_io_deq_bits : _T_4349 ? _Queue16_UInt8_12_io_deq_bits : _T_4348 ? _Queue16_UInt8_11_io_deq_bits : _T_4347 ? _Queue16_UInt8_10_io_deq_bits : _T_4346 ? _Queue16_UInt8_9_io_deq_bits : _T_4345 ? _Queue16_UInt8_8_io_deq_bits : _T_4344 ? _Queue16_UInt8_7_io_deq_bits : _T_4343 ? _Queue16_UInt8_6_io_deq_bits : _T_4342 ? _Queue16_UInt8_5_io_deq_bits : _T_4341 ? _Queue16_UInt8_4_io_deq_bits : _T_4340 ? _Queue16_UInt8_3_io_deq_bits : _T_4339 ? _Queue16_UInt8_2_io_deq_bits : _T_4338 ? _Queue16_UInt8_1_io_deq_bits : _T_4337 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_0 = _T_4368 ? _Queue16_UInt8_31_io_deq_valid : _T_4367 ? _Queue16_UInt8_30_io_deq_valid : _T_4366 ? _Queue16_UInt8_29_io_deq_valid : _T_4365 ? _Queue16_UInt8_28_io_deq_valid : _T_4364 ? _Queue16_UInt8_27_io_deq_valid : _T_4363 ? _Queue16_UInt8_26_io_deq_valid : _T_4362 ? _Queue16_UInt8_25_io_deq_valid : _T_4361 ? _Queue16_UInt8_24_io_deq_valid : _T_4360 ? _Queue16_UInt8_23_io_deq_valid : _T_4359 ? _Queue16_UInt8_22_io_deq_valid : _T_4358 ? _Queue16_UInt8_21_io_deq_valid : _T_4357 ? _Queue16_UInt8_20_io_deq_valid : _T_4356 ? _Queue16_UInt8_19_io_deq_valid : _T_4355 ? _Queue16_UInt8_18_io_deq_valid : _T_4354 ? _Queue16_UInt8_17_io_deq_valid : _T_4353 ? _Queue16_UInt8_16_io_deq_valid : _T_4352 ? _Queue16_UInt8_15_io_deq_valid : _T_4351 ? _Queue16_UInt8_14_io_deq_valid : _T_4350 ? _Queue16_UInt8_13_io_deq_valid : _T_4349 ? _Queue16_UInt8_12_io_deq_valid : _T_4348 ? _Queue16_UInt8_11_io_deq_valid : _T_4347 ? _Queue16_UInt8_10_io_deq_valid : _T_4346 ? _Queue16_UInt8_9_io_deq_valid : _T_4345 ? _Queue16_UInt8_8_io_deq_valid : _T_4344 ? _Queue16_UInt8_7_io_deq_valid : _T_4343 ? _Queue16_UInt8_6_io_deq_valid : _T_4342 ? _Queue16_UInt8_5_io_deq_valid : _T_4341 ? _Queue16_UInt8_4_io_deq_valid : _T_4340 ? _Queue16_UInt8_3_io_deq_valid : _T_4339 ? _Queue16_UInt8_2_io_deq_valid : _T_4338 ? _Queue16_UInt8_1_io_deq_valid : _T_4337 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_1 = _remapindex_T + 7'h1; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_91 = _remapindex_T_1 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_1 = _GEN_91[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4369 = remapindex_1 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4370 = remapindex_1 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4371 = remapindex_1 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4372 = remapindex_1 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4373 = remapindex_1 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4374 = remapindex_1 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4375 = remapindex_1 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4376 = remapindex_1 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4377 = remapindex_1 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4378 = remapindex_1 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4379 = remapindex_1 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4380 = remapindex_1 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4381 = remapindex_1 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4382 = remapindex_1 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4383 = remapindex_1 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4384 = remapindex_1 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4385 = remapindex_1 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4386 = remapindex_1 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4387 = remapindex_1 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4388 = remapindex_1 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4389 = remapindex_1 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4390 = remapindex_1 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4391 = remapindex_1 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4392 = remapindex_1 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4393 = remapindex_1 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4394 = remapindex_1 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4395 = remapindex_1 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4396 = remapindex_1 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4397 = remapindex_1 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4398 = remapindex_1 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4399 = remapindex_1 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4400 = remapindex_1 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_1 = _T_4400 ? _Queue16_UInt8_31_io_deq_bits : _T_4399 ? _Queue16_UInt8_30_io_deq_bits : _T_4398 ? _Queue16_UInt8_29_io_deq_bits : _T_4397 ? _Queue16_UInt8_28_io_deq_bits : _T_4396 ? _Queue16_UInt8_27_io_deq_bits : _T_4395 ? _Queue16_UInt8_26_io_deq_bits : _T_4394 ? _Queue16_UInt8_25_io_deq_bits : _T_4393 ? _Queue16_UInt8_24_io_deq_bits : _T_4392 ? _Queue16_UInt8_23_io_deq_bits : _T_4391 ? _Queue16_UInt8_22_io_deq_bits : _T_4390 ? _Queue16_UInt8_21_io_deq_bits : _T_4389 ? _Queue16_UInt8_20_io_deq_bits : _T_4388 ? _Queue16_UInt8_19_io_deq_bits : _T_4387 ? _Queue16_UInt8_18_io_deq_bits : _T_4386 ? _Queue16_UInt8_17_io_deq_bits : _T_4385 ? _Queue16_UInt8_16_io_deq_bits : _T_4384 ? _Queue16_UInt8_15_io_deq_bits : _T_4383 ? _Queue16_UInt8_14_io_deq_bits : _T_4382 ? _Queue16_UInt8_13_io_deq_bits : _T_4381 ? _Queue16_UInt8_12_io_deq_bits : _T_4380 ? _Queue16_UInt8_11_io_deq_bits : _T_4379 ? _Queue16_UInt8_10_io_deq_bits : _T_4378 ? _Queue16_UInt8_9_io_deq_bits : _T_4377 ? _Queue16_UInt8_8_io_deq_bits : _T_4376 ? _Queue16_UInt8_7_io_deq_bits : _T_4375 ? _Queue16_UInt8_6_io_deq_bits : _T_4374 ? _Queue16_UInt8_5_io_deq_bits : _T_4373 ? _Queue16_UInt8_4_io_deq_bits : _T_4372 ? _Queue16_UInt8_3_io_deq_bits : _T_4371 ? _Queue16_UInt8_2_io_deq_bits : _T_4370 ? _Queue16_UInt8_1_io_deq_bits : _T_4369 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_1 = _T_4400 ? _Queue16_UInt8_31_io_deq_valid : _T_4399 ? _Queue16_UInt8_30_io_deq_valid : _T_4398 ? _Queue16_UInt8_29_io_deq_valid : _T_4397 ? _Queue16_UInt8_28_io_deq_valid : _T_4396 ? _Queue16_UInt8_27_io_deq_valid : _T_4395 ? _Queue16_UInt8_26_io_deq_valid : _T_4394 ? _Queue16_UInt8_25_io_deq_valid : _T_4393 ? _Queue16_UInt8_24_io_deq_valid : _T_4392 ? _Queue16_UInt8_23_io_deq_valid : _T_4391 ? _Queue16_UInt8_22_io_deq_valid : _T_4390 ? _Queue16_UInt8_21_io_deq_valid : _T_4389 ? _Queue16_UInt8_20_io_deq_valid : _T_4388 ? _Queue16_UInt8_19_io_deq_valid : _T_4387 ? _Queue16_UInt8_18_io_deq_valid : _T_4386 ? _Queue16_UInt8_17_io_deq_valid : _T_4385 ? _Queue16_UInt8_16_io_deq_valid : _T_4384 ? _Queue16_UInt8_15_io_deq_valid : _T_4383 ? _Queue16_UInt8_14_io_deq_valid : _T_4382 ? _Queue16_UInt8_13_io_deq_valid : _T_4381 ? _Queue16_UInt8_12_io_deq_valid : _T_4380 ? _Queue16_UInt8_11_io_deq_valid : _T_4379 ? _Queue16_UInt8_10_io_deq_valid : _T_4378 ? _Queue16_UInt8_9_io_deq_valid : _T_4377 ? _Queue16_UInt8_8_io_deq_valid : _T_4376 ? _Queue16_UInt8_7_io_deq_valid : _T_4375 ? _Queue16_UInt8_6_io_deq_valid : _T_4374 ? _Queue16_UInt8_5_io_deq_valid : _T_4373 ? _Queue16_UInt8_4_io_deq_valid : _T_4372 ? _Queue16_UInt8_3_io_deq_valid : _T_4371 ? _Queue16_UInt8_2_io_deq_valid : _T_4370 ? _Queue16_UInt8_1_io_deq_valid : _T_4369 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_2 = _remapindex_T + 7'h2; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_92 = _remapindex_T_2 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_2 = _GEN_92[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4401 = remapindex_2 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4402 = remapindex_2 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4403 = remapindex_2 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4404 = remapindex_2 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4405 = remapindex_2 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4406 = remapindex_2 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4407 = remapindex_2 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4408 = remapindex_2 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4409 = remapindex_2 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4410 = remapindex_2 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4411 = remapindex_2 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4412 = remapindex_2 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4413 = remapindex_2 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4414 = remapindex_2 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4415 = remapindex_2 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4416 = remapindex_2 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4417 = remapindex_2 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4418 = remapindex_2 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4419 = remapindex_2 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4420 = remapindex_2 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4421 = remapindex_2 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4422 = remapindex_2 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4423 = remapindex_2 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4424 = remapindex_2 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4425 = remapindex_2 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4426 = remapindex_2 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4427 = remapindex_2 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4428 = remapindex_2 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4429 = remapindex_2 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4430 = remapindex_2 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4431 = remapindex_2 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4432 = remapindex_2 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_2 = _T_4432 ? _Queue16_UInt8_31_io_deq_bits : _T_4431 ? _Queue16_UInt8_30_io_deq_bits : _T_4430 ? _Queue16_UInt8_29_io_deq_bits : _T_4429 ? _Queue16_UInt8_28_io_deq_bits : _T_4428 ? _Queue16_UInt8_27_io_deq_bits : _T_4427 ? _Queue16_UInt8_26_io_deq_bits : _T_4426 ? _Queue16_UInt8_25_io_deq_bits : _T_4425 ? _Queue16_UInt8_24_io_deq_bits : _T_4424 ? _Queue16_UInt8_23_io_deq_bits : _T_4423 ? _Queue16_UInt8_22_io_deq_bits : _T_4422 ? _Queue16_UInt8_21_io_deq_bits : _T_4421 ? _Queue16_UInt8_20_io_deq_bits : _T_4420 ? _Queue16_UInt8_19_io_deq_bits : _T_4419 ? _Queue16_UInt8_18_io_deq_bits : _T_4418 ? _Queue16_UInt8_17_io_deq_bits : _T_4417 ? _Queue16_UInt8_16_io_deq_bits : _T_4416 ? _Queue16_UInt8_15_io_deq_bits : _T_4415 ? _Queue16_UInt8_14_io_deq_bits : _T_4414 ? _Queue16_UInt8_13_io_deq_bits : _T_4413 ? _Queue16_UInt8_12_io_deq_bits : _T_4412 ? _Queue16_UInt8_11_io_deq_bits : _T_4411 ? _Queue16_UInt8_10_io_deq_bits : _T_4410 ? _Queue16_UInt8_9_io_deq_bits : _T_4409 ? _Queue16_UInt8_8_io_deq_bits : _T_4408 ? _Queue16_UInt8_7_io_deq_bits : _T_4407 ? _Queue16_UInt8_6_io_deq_bits : _T_4406 ? _Queue16_UInt8_5_io_deq_bits : _T_4405 ? _Queue16_UInt8_4_io_deq_bits : _T_4404 ? _Queue16_UInt8_3_io_deq_bits : _T_4403 ? _Queue16_UInt8_2_io_deq_bits : _T_4402 ? _Queue16_UInt8_1_io_deq_bits : _T_4401 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_2 = _T_4432 ? _Queue16_UInt8_31_io_deq_valid : _T_4431 ? _Queue16_UInt8_30_io_deq_valid : _T_4430 ? _Queue16_UInt8_29_io_deq_valid : _T_4429 ? _Queue16_UInt8_28_io_deq_valid : _T_4428 ? _Queue16_UInt8_27_io_deq_valid : _T_4427 ? _Queue16_UInt8_26_io_deq_valid : _T_4426 ? _Queue16_UInt8_25_io_deq_valid : _T_4425 ? _Queue16_UInt8_24_io_deq_valid : _T_4424 ? _Queue16_UInt8_23_io_deq_valid : _T_4423 ? _Queue16_UInt8_22_io_deq_valid : _T_4422 ? _Queue16_UInt8_21_io_deq_valid : _T_4421 ? _Queue16_UInt8_20_io_deq_valid : _T_4420 ? _Queue16_UInt8_19_io_deq_valid : _T_4419 ? _Queue16_UInt8_18_io_deq_valid : _T_4418 ? _Queue16_UInt8_17_io_deq_valid : _T_4417 ? _Queue16_UInt8_16_io_deq_valid : _T_4416 ? _Queue16_UInt8_15_io_deq_valid : _T_4415 ? _Queue16_UInt8_14_io_deq_valid : _T_4414 ? _Queue16_UInt8_13_io_deq_valid : _T_4413 ? _Queue16_UInt8_12_io_deq_valid : _T_4412 ? _Queue16_UInt8_11_io_deq_valid : _T_4411 ? _Queue16_UInt8_10_io_deq_valid : _T_4410 ? _Queue16_UInt8_9_io_deq_valid : _T_4409 ? _Queue16_UInt8_8_io_deq_valid : _T_4408 ? _Queue16_UInt8_7_io_deq_valid : _T_4407 ? _Queue16_UInt8_6_io_deq_valid : _T_4406 ? _Queue16_UInt8_5_io_deq_valid : _T_4405 ? _Queue16_UInt8_4_io_deq_valid : _T_4404 ? _Queue16_UInt8_3_io_deq_valid : _T_4403 ? _Queue16_UInt8_2_io_deq_valid : _T_4402 ? _Queue16_UInt8_1_io_deq_valid : _T_4401 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_3 = _remapindex_T + 7'h3; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_93 = _remapindex_T_3 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_3 = _GEN_93[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4433 = remapindex_3 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4434 = remapindex_3 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4435 = remapindex_3 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4436 = remapindex_3 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4437 = remapindex_3 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4438 = remapindex_3 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4439 = remapindex_3 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4440 = remapindex_3 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4441 = remapindex_3 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4442 = remapindex_3 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4443 = remapindex_3 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4444 = remapindex_3 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4445 = remapindex_3 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4446 = remapindex_3 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4447 = remapindex_3 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4448 = remapindex_3 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4449 = remapindex_3 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4450 = remapindex_3 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4451 = remapindex_3 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4452 = remapindex_3 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4453 = remapindex_3 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4454 = remapindex_3 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4455 = remapindex_3 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4456 = remapindex_3 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4457 = remapindex_3 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4458 = remapindex_3 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4459 = remapindex_3 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4460 = remapindex_3 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4461 = remapindex_3 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4462 = remapindex_3 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4463 = remapindex_3 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4464 = remapindex_3 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_3 = _T_4464 ? _Queue16_UInt8_31_io_deq_bits : _T_4463 ? _Queue16_UInt8_30_io_deq_bits : _T_4462 ? _Queue16_UInt8_29_io_deq_bits : _T_4461 ? _Queue16_UInt8_28_io_deq_bits : _T_4460 ? _Queue16_UInt8_27_io_deq_bits : _T_4459 ? _Queue16_UInt8_26_io_deq_bits : _T_4458 ? _Queue16_UInt8_25_io_deq_bits : _T_4457 ? _Queue16_UInt8_24_io_deq_bits : _T_4456 ? _Queue16_UInt8_23_io_deq_bits : _T_4455 ? _Queue16_UInt8_22_io_deq_bits : _T_4454 ? _Queue16_UInt8_21_io_deq_bits : _T_4453 ? _Queue16_UInt8_20_io_deq_bits : _T_4452 ? _Queue16_UInt8_19_io_deq_bits : _T_4451 ? _Queue16_UInt8_18_io_deq_bits : _T_4450 ? _Queue16_UInt8_17_io_deq_bits : _T_4449 ? _Queue16_UInt8_16_io_deq_bits : _T_4448 ? _Queue16_UInt8_15_io_deq_bits : _T_4447 ? _Queue16_UInt8_14_io_deq_bits : _T_4446 ? _Queue16_UInt8_13_io_deq_bits : _T_4445 ? _Queue16_UInt8_12_io_deq_bits : _T_4444 ? _Queue16_UInt8_11_io_deq_bits : _T_4443 ? _Queue16_UInt8_10_io_deq_bits : _T_4442 ? _Queue16_UInt8_9_io_deq_bits : _T_4441 ? _Queue16_UInt8_8_io_deq_bits : _T_4440 ? _Queue16_UInt8_7_io_deq_bits : _T_4439 ? _Queue16_UInt8_6_io_deq_bits : _T_4438 ? _Queue16_UInt8_5_io_deq_bits : _T_4437 ? _Queue16_UInt8_4_io_deq_bits : _T_4436 ? _Queue16_UInt8_3_io_deq_bits : _T_4435 ? _Queue16_UInt8_2_io_deq_bits : _T_4434 ? _Queue16_UInt8_1_io_deq_bits : _T_4433 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_3 = _T_4464 ? _Queue16_UInt8_31_io_deq_valid : _T_4463 ? _Queue16_UInt8_30_io_deq_valid : _T_4462 ? _Queue16_UInt8_29_io_deq_valid : _T_4461 ? _Queue16_UInt8_28_io_deq_valid : _T_4460 ? _Queue16_UInt8_27_io_deq_valid : _T_4459 ? _Queue16_UInt8_26_io_deq_valid : _T_4458 ? _Queue16_UInt8_25_io_deq_valid : _T_4457 ? _Queue16_UInt8_24_io_deq_valid : _T_4456 ? _Queue16_UInt8_23_io_deq_valid : _T_4455 ? _Queue16_UInt8_22_io_deq_valid : _T_4454 ? _Queue16_UInt8_21_io_deq_valid : _T_4453 ? _Queue16_UInt8_20_io_deq_valid : _T_4452 ? _Queue16_UInt8_19_io_deq_valid : _T_4451 ? _Queue16_UInt8_18_io_deq_valid : _T_4450 ? _Queue16_UInt8_17_io_deq_valid : _T_4449 ? _Queue16_UInt8_16_io_deq_valid : _T_4448 ? _Queue16_UInt8_15_io_deq_valid : _T_4447 ? _Queue16_UInt8_14_io_deq_valid : _T_4446 ? _Queue16_UInt8_13_io_deq_valid : _T_4445 ? _Queue16_UInt8_12_io_deq_valid : _T_4444 ? _Queue16_UInt8_11_io_deq_valid : _T_4443 ? _Queue16_UInt8_10_io_deq_valid : _T_4442 ? _Queue16_UInt8_9_io_deq_valid : _T_4441 ? _Queue16_UInt8_8_io_deq_valid : _T_4440 ? _Queue16_UInt8_7_io_deq_valid : _T_4439 ? _Queue16_UInt8_6_io_deq_valid : _T_4438 ? _Queue16_UInt8_5_io_deq_valid : _T_4437 ? _Queue16_UInt8_4_io_deq_valid : _T_4436 ? _Queue16_UInt8_3_io_deq_valid : _T_4435 ? _Queue16_UInt8_2_io_deq_valid : _T_4434 ? _Queue16_UInt8_1_io_deq_valid : _T_4433 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_4 = _remapindex_T + 7'h4; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_94 = _remapindex_T_4 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_4 = _GEN_94[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4465 = remapindex_4 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4466 = remapindex_4 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4467 = remapindex_4 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4468 = remapindex_4 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4469 = remapindex_4 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4470 = remapindex_4 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4471 = remapindex_4 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4472 = remapindex_4 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4473 = remapindex_4 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4474 = remapindex_4 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4475 = remapindex_4 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4476 = remapindex_4 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4477 = remapindex_4 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4478 = remapindex_4 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4479 = remapindex_4 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4480 = remapindex_4 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4481 = remapindex_4 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4482 = remapindex_4 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4483 = remapindex_4 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4484 = remapindex_4 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4485 = remapindex_4 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4486 = remapindex_4 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4487 = remapindex_4 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4488 = remapindex_4 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4489 = remapindex_4 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4490 = remapindex_4 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4491 = remapindex_4 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4492 = remapindex_4 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4493 = remapindex_4 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4494 = remapindex_4 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4495 = remapindex_4 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4496 = remapindex_4 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_4 = _T_4496 ? _Queue16_UInt8_31_io_deq_bits : _T_4495 ? _Queue16_UInt8_30_io_deq_bits : _T_4494 ? _Queue16_UInt8_29_io_deq_bits : _T_4493 ? _Queue16_UInt8_28_io_deq_bits : _T_4492 ? _Queue16_UInt8_27_io_deq_bits : _T_4491 ? _Queue16_UInt8_26_io_deq_bits : _T_4490 ? _Queue16_UInt8_25_io_deq_bits : _T_4489 ? _Queue16_UInt8_24_io_deq_bits : _T_4488 ? _Queue16_UInt8_23_io_deq_bits : _T_4487 ? _Queue16_UInt8_22_io_deq_bits : _T_4486 ? _Queue16_UInt8_21_io_deq_bits : _T_4485 ? _Queue16_UInt8_20_io_deq_bits : _T_4484 ? _Queue16_UInt8_19_io_deq_bits : _T_4483 ? _Queue16_UInt8_18_io_deq_bits : _T_4482 ? _Queue16_UInt8_17_io_deq_bits : _T_4481 ? _Queue16_UInt8_16_io_deq_bits : _T_4480 ? _Queue16_UInt8_15_io_deq_bits : _T_4479 ? _Queue16_UInt8_14_io_deq_bits : _T_4478 ? _Queue16_UInt8_13_io_deq_bits : _T_4477 ? _Queue16_UInt8_12_io_deq_bits : _T_4476 ? _Queue16_UInt8_11_io_deq_bits : _T_4475 ? _Queue16_UInt8_10_io_deq_bits : _T_4474 ? _Queue16_UInt8_9_io_deq_bits : _T_4473 ? _Queue16_UInt8_8_io_deq_bits : _T_4472 ? _Queue16_UInt8_7_io_deq_bits : _T_4471 ? _Queue16_UInt8_6_io_deq_bits : _T_4470 ? _Queue16_UInt8_5_io_deq_bits : _T_4469 ? _Queue16_UInt8_4_io_deq_bits : _T_4468 ? _Queue16_UInt8_3_io_deq_bits : _T_4467 ? _Queue16_UInt8_2_io_deq_bits : _T_4466 ? _Queue16_UInt8_1_io_deq_bits : _T_4465 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_4 = _T_4496 ? _Queue16_UInt8_31_io_deq_valid : _T_4495 ? _Queue16_UInt8_30_io_deq_valid : _T_4494 ? _Queue16_UInt8_29_io_deq_valid : _T_4493 ? _Queue16_UInt8_28_io_deq_valid : _T_4492 ? _Queue16_UInt8_27_io_deq_valid : _T_4491 ? _Queue16_UInt8_26_io_deq_valid : _T_4490 ? _Queue16_UInt8_25_io_deq_valid : _T_4489 ? _Queue16_UInt8_24_io_deq_valid : _T_4488 ? _Queue16_UInt8_23_io_deq_valid : _T_4487 ? _Queue16_UInt8_22_io_deq_valid : _T_4486 ? _Queue16_UInt8_21_io_deq_valid : _T_4485 ? _Queue16_UInt8_20_io_deq_valid : _T_4484 ? _Queue16_UInt8_19_io_deq_valid : _T_4483 ? _Queue16_UInt8_18_io_deq_valid : _T_4482 ? _Queue16_UInt8_17_io_deq_valid : _T_4481 ? _Queue16_UInt8_16_io_deq_valid : _T_4480 ? _Queue16_UInt8_15_io_deq_valid : _T_4479 ? _Queue16_UInt8_14_io_deq_valid : _T_4478 ? _Queue16_UInt8_13_io_deq_valid : _T_4477 ? _Queue16_UInt8_12_io_deq_valid : _T_4476 ? _Queue16_UInt8_11_io_deq_valid : _T_4475 ? _Queue16_UInt8_10_io_deq_valid : _T_4474 ? _Queue16_UInt8_9_io_deq_valid : _T_4473 ? _Queue16_UInt8_8_io_deq_valid : _T_4472 ? _Queue16_UInt8_7_io_deq_valid : _T_4471 ? _Queue16_UInt8_6_io_deq_valid : _T_4470 ? _Queue16_UInt8_5_io_deq_valid : _T_4469 ? _Queue16_UInt8_4_io_deq_valid : _T_4468 ? _Queue16_UInt8_3_io_deq_valid : _T_4467 ? _Queue16_UInt8_2_io_deq_valid : _T_4466 ? _Queue16_UInt8_1_io_deq_valid : _T_4465 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_5 = _remapindex_T + 7'h5; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_95 = _remapindex_T_5 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_5 = _GEN_95[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4497 = remapindex_5 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4498 = remapindex_5 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4499 = remapindex_5 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4500 = remapindex_5 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4501 = remapindex_5 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4502 = remapindex_5 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4503 = remapindex_5 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4504 = remapindex_5 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4505 = remapindex_5 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4506 = remapindex_5 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4507 = remapindex_5 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4508 = remapindex_5 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4509 = remapindex_5 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4510 = remapindex_5 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4511 = remapindex_5 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4512 = remapindex_5 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4513 = remapindex_5 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4514 = remapindex_5 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4515 = remapindex_5 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4516 = remapindex_5 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4517 = remapindex_5 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4518 = remapindex_5 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4519 = remapindex_5 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4520 = remapindex_5 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4521 = remapindex_5 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4522 = remapindex_5 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4523 = remapindex_5 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4524 = remapindex_5 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4525 = remapindex_5 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4526 = remapindex_5 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4527 = remapindex_5 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4528 = remapindex_5 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_5 = _T_4528 ? _Queue16_UInt8_31_io_deq_bits : _T_4527 ? _Queue16_UInt8_30_io_deq_bits : _T_4526 ? _Queue16_UInt8_29_io_deq_bits : _T_4525 ? _Queue16_UInt8_28_io_deq_bits : _T_4524 ? _Queue16_UInt8_27_io_deq_bits : _T_4523 ? _Queue16_UInt8_26_io_deq_bits : _T_4522 ? _Queue16_UInt8_25_io_deq_bits : _T_4521 ? _Queue16_UInt8_24_io_deq_bits : _T_4520 ? _Queue16_UInt8_23_io_deq_bits : _T_4519 ? _Queue16_UInt8_22_io_deq_bits : _T_4518 ? _Queue16_UInt8_21_io_deq_bits : _T_4517 ? _Queue16_UInt8_20_io_deq_bits : _T_4516 ? _Queue16_UInt8_19_io_deq_bits : _T_4515 ? _Queue16_UInt8_18_io_deq_bits : _T_4514 ? _Queue16_UInt8_17_io_deq_bits : _T_4513 ? _Queue16_UInt8_16_io_deq_bits : _T_4512 ? _Queue16_UInt8_15_io_deq_bits : _T_4511 ? _Queue16_UInt8_14_io_deq_bits : _T_4510 ? _Queue16_UInt8_13_io_deq_bits : _T_4509 ? _Queue16_UInt8_12_io_deq_bits : _T_4508 ? _Queue16_UInt8_11_io_deq_bits : _T_4507 ? _Queue16_UInt8_10_io_deq_bits : _T_4506 ? _Queue16_UInt8_9_io_deq_bits : _T_4505 ? _Queue16_UInt8_8_io_deq_bits : _T_4504 ? _Queue16_UInt8_7_io_deq_bits : _T_4503 ? _Queue16_UInt8_6_io_deq_bits : _T_4502 ? _Queue16_UInt8_5_io_deq_bits : _T_4501 ? _Queue16_UInt8_4_io_deq_bits : _T_4500 ? _Queue16_UInt8_3_io_deq_bits : _T_4499 ? _Queue16_UInt8_2_io_deq_bits : _T_4498 ? _Queue16_UInt8_1_io_deq_bits : _T_4497 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_5 = _T_4528 ? _Queue16_UInt8_31_io_deq_valid : _T_4527 ? _Queue16_UInt8_30_io_deq_valid : _T_4526 ? _Queue16_UInt8_29_io_deq_valid : _T_4525 ? _Queue16_UInt8_28_io_deq_valid : _T_4524 ? _Queue16_UInt8_27_io_deq_valid : _T_4523 ? _Queue16_UInt8_26_io_deq_valid : _T_4522 ? _Queue16_UInt8_25_io_deq_valid : _T_4521 ? _Queue16_UInt8_24_io_deq_valid : _T_4520 ? _Queue16_UInt8_23_io_deq_valid : _T_4519 ? _Queue16_UInt8_22_io_deq_valid : _T_4518 ? _Queue16_UInt8_21_io_deq_valid : _T_4517 ? _Queue16_UInt8_20_io_deq_valid : _T_4516 ? _Queue16_UInt8_19_io_deq_valid : _T_4515 ? _Queue16_UInt8_18_io_deq_valid : _T_4514 ? _Queue16_UInt8_17_io_deq_valid : _T_4513 ? _Queue16_UInt8_16_io_deq_valid : _T_4512 ? _Queue16_UInt8_15_io_deq_valid : _T_4511 ? _Queue16_UInt8_14_io_deq_valid : _T_4510 ? _Queue16_UInt8_13_io_deq_valid : _T_4509 ? _Queue16_UInt8_12_io_deq_valid : _T_4508 ? _Queue16_UInt8_11_io_deq_valid : _T_4507 ? _Queue16_UInt8_10_io_deq_valid : _T_4506 ? _Queue16_UInt8_9_io_deq_valid : _T_4505 ? _Queue16_UInt8_8_io_deq_valid : _T_4504 ? _Queue16_UInt8_7_io_deq_valid : _T_4503 ? _Queue16_UInt8_6_io_deq_valid : _T_4502 ? _Queue16_UInt8_5_io_deq_valid : _T_4501 ? _Queue16_UInt8_4_io_deq_valid : _T_4500 ? _Queue16_UInt8_3_io_deq_valid : _T_4499 ? _Queue16_UInt8_2_io_deq_valid : _T_4498 ? _Queue16_UInt8_1_io_deq_valid : _T_4497 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_6 = _remapindex_T + 7'h6; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_96 = _remapindex_T_6 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_6 = _GEN_96[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4529 = remapindex_6 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4530 = remapindex_6 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4531 = remapindex_6 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4532 = remapindex_6 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4533 = remapindex_6 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4534 = remapindex_6 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4535 = remapindex_6 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4536 = remapindex_6 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4537 = remapindex_6 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4538 = remapindex_6 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4539 = remapindex_6 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4540 = remapindex_6 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4541 = remapindex_6 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4542 = remapindex_6 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4543 = remapindex_6 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4544 = remapindex_6 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4545 = remapindex_6 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4546 = remapindex_6 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4547 = remapindex_6 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4548 = remapindex_6 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4549 = remapindex_6 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4550 = remapindex_6 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4551 = remapindex_6 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4552 = remapindex_6 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4553 = remapindex_6 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4554 = remapindex_6 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4555 = remapindex_6 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4556 = remapindex_6 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4557 = remapindex_6 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4558 = remapindex_6 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4559 = remapindex_6 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4560 = remapindex_6 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_6 = _T_4560 ? _Queue16_UInt8_31_io_deq_bits : _T_4559 ? _Queue16_UInt8_30_io_deq_bits : _T_4558 ? _Queue16_UInt8_29_io_deq_bits : _T_4557 ? _Queue16_UInt8_28_io_deq_bits : _T_4556 ? _Queue16_UInt8_27_io_deq_bits : _T_4555 ? _Queue16_UInt8_26_io_deq_bits : _T_4554 ? _Queue16_UInt8_25_io_deq_bits : _T_4553 ? _Queue16_UInt8_24_io_deq_bits : _T_4552 ? _Queue16_UInt8_23_io_deq_bits : _T_4551 ? _Queue16_UInt8_22_io_deq_bits : _T_4550 ? _Queue16_UInt8_21_io_deq_bits : _T_4549 ? _Queue16_UInt8_20_io_deq_bits : _T_4548 ? _Queue16_UInt8_19_io_deq_bits : _T_4547 ? _Queue16_UInt8_18_io_deq_bits : _T_4546 ? _Queue16_UInt8_17_io_deq_bits : _T_4545 ? _Queue16_UInt8_16_io_deq_bits : _T_4544 ? _Queue16_UInt8_15_io_deq_bits : _T_4543 ? _Queue16_UInt8_14_io_deq_bits : _T_4542 ? _Queue16_UInt8_13_io_deq_bits : _T_4541 ? _Queue16_UInt8_12_io_deq_bits : _T_4540 ? _Queue16_UInt8_11_io_deq_bits : _T_4539 ? _Queue16_UInt8_10_io_deq_bits : _T_4538 ? _Queue16_UInt8_9_io_deq_bits : _T_4537 ? _Queue16_UInt8_8_io_deq_bits : _T_4536 ? _Queue16_UInt8_7_io_deq_bits : _T_4535 ? _Queue16_UInt8_6_io_deq_bits : _T_4534 ? _Queue16_UInt8_5_io_deq_bits : _T_4533 ? _Queue16_UInt8_4_io_deq_bits : _T_4532 ? _Queue16_UInt8_3_io_deq_bits : _T_4531 ? _Queue16_UInt8_2_io_deq_bits : _T_4530 ? _Queue16_UInt8_1_io_deq_bits : _T_4529 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_6 = _T_4560 ? _Queue16_UInt8_31_io_deq_valid : _T_4559 ? _Queue16_UInt8_30_io_deq_valid : _T_4558 ? _Queue16_UInt8_29_io_deq_valid : _T_4557 ? _Queue16_UInt8_28_io_deq_valid : _T_4556 ? _Queue16_UInt8_27_io_deq_valid : _T_4555 ? _Queue16_UInt8_26_io_deq_valid : _T_4554 ? _Queue16_UInt8_25_io_deq_valid : _T_4553 ? _Queue16_UInt8_24_io_deq_valid : _T_4552 ? _Queue16_UInt8_23_io_deq_valid : _T_4551 ? _Queue16_UInt8_22_io_deq_valid : _T_4550 ? _Queue16_UInt8_21_io_deq_valid : _T_4549 ? _Queue16_UInt8_20_io_deq_valid : _T_4548 ? _Queue16_UInt8_19_io_deq_valid : _T_4547 ? _Queue16_UInt8_18_io_deq_valid : _T_4546 ? _Queue16_UInt8_17_io_deq_valid : _T_4545 ? _Queue16_UInt8_16_io_deq_valid : _T_4544 ? _Queue16_UInt8_15_io_deq_valid : _T_4543 ? _Queue16_UInt8_14_io_deq_valid : _T_4542 ? _Queue16_UInt8_13_io_deq_valid : _T_4541 ? _Queue16_UInt8_12_io_deq_valid : _T_4540 ? _Queue16_UInt8_11_io_deq_valid : _T_4539 ? _Queue16_UInt8_10_io_deq_valid : _T_4538 ? _Queue16_UInt8_9_io_deq_valid : _T_4537 ? _Queue16_UInt8_8_io_deq_valid : _T_4536 ? _Queue16_UInt8_7_io_deq_valid : _T_4535 ? _Queue16_UInt8_6_io_deq_valid : _T_4534 ? _Queue16_UInt8_5_io_deq_valid : _T_4533 ? _Queue16_UInt8_4_io_deq_valid : _T_4532 ? _Queue16_UInt8_3_io_deq_valid : _T_4531 ? _Queue16_UInt8_2_io_deq_valid : _T_4530 ? _Queue16_UInt8_1_io_deq_valid : _T_4529 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_7 = _remapindex_T + 7'h7; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_97 = _remapindex_T_7 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_7 = _GEN_97[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4561 = remapindex_7 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4562 = remapindex_7 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4563 = remapindex_7 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4564 = remapindex_7 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4565 = remapindex_7 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4566 = remapindex_7 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4567 = remapindex_7 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4568 = remapindex_7 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4569 = remapindex_7 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4570 = remapindex_7 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4571 = remapindex_7 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4572 = remapindex_7 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4573 = remapindex_7 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4574 = remapindex_7 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4575 = remapindex_7 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4576 = remapindex_7 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4577 = remapindex_7 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4578 = remapindex_7 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4579 = remapindex_7 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4580 = remapindex_7 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4581 = remapindex_7 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4582 = remapindex_7 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4583 = remapindex_7 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4584 = remapindex_7 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4585 = remapindex_7 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4586 = remapindex_7 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4587 = remapindex_7 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4588 = remapindex_7 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4589 = remapindex_7 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4590 = remapindex_7 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4591 = remapindex_7 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4592 = remapindex_7 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_7 = _T_4592 ? _Queue16_UInt8_31_io_deq_bits : _T_4591 ? _Queue16_UInt8_30_io_deq_bits : _T_4590 ? _Queue16_UInt8_29_io_deq_bits : _T_4589 ? _Queue16_UInt8_28_io_deq_bits : _T_4588 ? _Queue16_UInt8_27_io_deq_bits : _T_4587 ? _Queue16_UInt8_26_io_deq_bits : _T_4586 ? _Queue16_UInt8_25_io_deq_bits : _T_4585 ? _Queue16_UInt8_24_io_deq_bits : _T_4584 ? _Queue16_UInt8_23_io_deq_bits : _T_4583 ? _Queue16_UInt8_22_io_deq_bits : _T_4582 ? _Queue16_UInt8_21_io_deq_bits : _T_4581 ? _Queue16_UInt8_20_io_deq_bits : _T_4580 ? _Queue16_UInt8_19_io_deq_bits : _T_4579 ? _Queue16_UInt8_18_io_deq_bits : _T_4578 ? _Queue16_UInt8_17_io_deq_bits : _T_4577 ? _Queue16_UInt8_16_io_deq_bits : _T_4576 ? _Queue16_UInt8_15_io_deq_bits : _T_4575 ? _Queue16_UInt8_14_io_deq_bits : _T_4574 ? _Queue16_UInt8_13_io_deq_bits : _T_4573 ? _Queue16_UInt8_12_io_deq_bits : _T_4572 ? _Queue16_UInt8_11_io_deq_bits : _T_4571 ? _Queue16_UInt8_10_io_deq_bits : _T_4570 ? _Queue16_UInt8_9_io_deq_bits : _T_4569 ? _Queue16_UInt8_8_io_deq_bits : _T_4568 ? _Queue16_UInt8_7_io_deq_bits : _T_4567 ? _Queue16_UInt8_6_io_deq_bits : _T_4566 ? _Queue16_UInt8_5_io_deq_bits : _T_4565 ? _Queue16_UInt8_4_io_deq_bits : _T_4564 ? _Queue16_UInt8_3_io_deq_bits : _T_4563 ? _Queue16_UInt8_2_io_deq_bits : _T_4562 ? _Queue16_UInt8_1_io_deq_bits : _T_4561 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_7 = _T_4592 ? _Queue16_UInt8_31_io_deq_valid : _T_4591 ? _Queue16_UInt8_30_io_deq_valid : _T_4590 ? _Queue16_UInt8_29_io_deq_valid : _T_4589 ? _Queue16_UInt8_28_io_deq_valid : _T_4588 ? _Queue16_UInt8_27_io_deq_valid : _T_4587 ? _Queue16_UInt8_26_io_deq_valid : _T_4586 ? _Queue16_UInt8_25_io_deq_valid : _T_4585 ? _Queue16_UInt8_24_io_deq_valid : _T_4584 ? _Queue16_UInt8_23_io_deq_valid : _T_4583 ? _Queue16_UInt8_22_io_deq_valid : _T_4582 ? _Queue16_UInt8_21_io_deq_valid : _T_4581 ? _Queue16_UInt8_20_io_deq_valid : _T_4580 ? _Queue16_UInt8_19_io_deq_valid : _T_4579 ? _Queue16_UInt8_18_io_deq_valid : _T_4578 ? _Queue16_UInt8_17_io_deq_valid : _T_4577 ? _Queue16_UInt8_16_io_deq_valid : _T_4576 ? _Queue16_UInt8_15_io_deq_valid : _T_4575 ? _Queue16_UInt8_14_io_deq_valid : _T_4574 ? _Queue16_UInt8_13_io_deq_valid : _T_4573 ? _Queue16_UInt8_12_io_deq_valid : _T_4572 ? _Queue16_UInt8_11_io_deq_valid : _T_4571 ? _Queue16_UInt8_10_io_deq_valid : _T_4570 ? _Queue16_UInt8_9_io_deq_valid : _T_4569 ? _Queue16_UInt8_8_io_deq_valid : _T_4568 ? _Queue16_UInt8_7_io_deq_valid : _T_4567 ? _Queue16_UInt8_6_io_deq_valid : _T_4566 ? _Queue16_UInt8_5_io_deq_valid : _T_4565 ? _Queue16_UInt8_4_io_deq_valid : _T_4564 ? _Queue16_UInt8_3_io_deq_valid : _T_4563 ? _Queue16_UInt8_2_io_deq_valid : _T_4562 ? _Queue16_UInt8_1_io_deq_valid : _T_4561 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_8 = _remapindex_T + 7'h8; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_98 = _remapindex_T_8 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_8 = _GEN_98[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4593 = remapindex_8 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4594 = remapindex_8 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4595 = remapindex_8 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4596 = remapindex_8 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4597 = remapindex_8 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4598 = remapindex_8 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4599 = remapindex_8 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4600 = remapindex_8 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4601 = remapindex_8 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4602 = remapindex_8 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4603 = remapindex_8 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4604 = remapindex_8 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4605 = remapindex_8 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4606 = remapindex_8 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4607 = remapindex_8 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4608 = remapindex_8 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4609 = remapindex_8 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4610 = remapindex_8 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4611 = remapindex_8 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4612 = remapindex_8 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4613 = remapindex_8 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4614 = remapindex_8 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4615 = remapindex_8 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4616 = remapindex_8 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4617 = remapindex_8 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4618 = remapindex_8 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4619 = remapindex_8 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4620 = remapindex_8 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4621 = remapindex_8 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4622 = remapindex_8 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4623 = remapindex_8 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4624 = remapindex_8 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_8 = _T_4624 ? _Queue16_UInt8_31_io_deq_bits : _T_4623 ? _Queue16_UInt8_30_io_deq_bits : _T_4622 ? _Queue16_UInt8_29_io_deq_bits : _T_4621 ? _Queue16_UInt8_28_io_deq_bits : _T_4620 ? _Queue16_UInt8_27_io_deq_bits : _T_4619 ? _Queue16_UInt8_26_io_deq_bits : _T_4618 ? _Queue16_UInt8_25_io_deq_bits : _T_4617 ? _Queue16_UInt8_24_io_deq_bits : _T_4616 ? _Queue16_UInt8_23_io_deq_bits : _T_4615 ? _Queue16_UInt8_22_io_deq_bits : _T_4614 ? _Queue16_UInt8_21_io_deq_bits : _T_4613 ? _Queue16_UInt8_20_io_deq_bits : _T_4612 ? _Queue16_UInt8_19_io_deq_bits : _T_4611 ? _Queue16_UInt8_18_io_deq_bits : _T_4610 ? _Queue16_UInt8_17_io_deq_bits : _T_4609 ? _Queue16_UInt8_16_io_deq_bits : _T_4608 ? _Queue16_UInt8_15_io_deq_bits : _T_4607 ? _Queue16_UInt8_14_io_deq_bits : _T_4606 ? _Queue16_UInt8_13_io_deq_bits : _T_4605 ? _Queue16_UInt8_12_io_deq_bits : _T_4604 ? _Queue16_UInt8_11_io_deq_bits : _T_4603 ? _Queue16_UInt8_10_io_deq_bits : _T_4602 ? _Queue16_UInt8_9_io_deq_bits : _T_4601 ? _Queue16_UInt8_8_io_deq_bits : _T_4600 ? _Queue16_UInt8_7_io_deq_bits : _T_4599 ? _Queue16_UInt8_6_io_deq_bits : _T_4598 ? _Queue16_UInt8_5_io_deq_bits : _T_4597 ? _Queue16_UInt8_4_io_deq_bits : _T_4596 ? _Queue16_UInt8_3_io_deq_bits : _T_4595 ? _Queue16_UInt8_2_io_deq_bits : _T_4594 ? _Queue16_UInt8_1_io_deq_bits : _T_4593 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_8 = _T_4624 ? _Queue16_UInt8_31_io_deq_valid : _T_4623 ? _Queue16_UInt8_30_io_deq_valid : _T_4622 ? _Queue16_UInt8_29_io_deq_valid : _T_4621 ? _Queue16_UInt8_28_io_deq_valid : _T_4620 ? _Queue16_UInt8_27_io_deq_valid : _T_4619 ? _Queue16_UInt8_26_io_deq_valid : _T_4618 ? _Queue16_UInt8_25_io_deq_valid : _T_4617 ? _Queue16_UInt8_24_io_deq_valid : _T_4616 ? _Queue16_UInt8_23_io_deq_valid : _T_4615 ? _Queue16_UInt8_22_io_deq_valid : _T_4614 ? _Queue16_UInt8_21_io_deq_valid : _T_4613 ? _Queue16_UInt8_20_io_deq_valid : _T_4612 ? _Queue16_UInt8_19_io_deq_valid : _T_4611 ? _Queue16_UInt8_18_io_deq_valid : _T_4610 ? _Queue16_UInt8_17_io_deq_valid : _T_4609 ? _Queue16_UInt8_16_io_deq_valid : _T_4608 ? _Queue16_UInt8_15_io_deq_valid : _T_4607 ? _Queue16_UInt8_14_io_deq_valid : _T_4606 ? _Queue16_UInt8_13_io_deq_valid : _T_4605 ? _Queue16_UInt8_12_io_deq_valid : _T_4604 ? _Queue16_UInt8_11_io_deq_valid : _T_4603 ? _Queue16_UInt8_10_io_deq_valid : _T_4602 ? _Queue16_UInt8_9_io_deq_valid : _T_4601 ? _Queue16_UInt8_8_io_deq_valid : _T_4600 ? _Queue16_UInt8_7_io_deq_valid : _T_4599 ? _Queue16_UInt8_6_io_deq_valid : _T_4598 ? _Queue16_UInt8_5_io_deq_valid : _T_4597 ? _Queue16_UInt8_4_io_deq_valid : _T_4596 ? _Queue16_UInt8_3_io_deq_valid : _T_4595 ? _Queue16_UInt8_2_io_deq_valid : _T_4594 ? _Queue16_UInt8_1_io_deq_valid : _T_4593 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_9 = _remapindex_T + 7'h9; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_99 = _remapindex_T_9 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_9 = _GEN_99[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4625 = remapindex_9 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4626 = remapindex_9 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4627 = remapindex_9 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4628 = remapindex_9 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4629 = remapindex_9 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4630 = remapindex_9 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4631 = remapindex_9 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4632 = remapindex_9 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4633 = remapindex_9 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4634 = remapindex_9 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4635 = remapindex_9 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4636 = remapindex_9 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4637 = remapindex_9 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4638 = remapindex_9 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4639 = remapindex_9 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4640 = remapindex_9 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4641 = remapindex_9 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4642 = remapindex_9 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4643 = remapindex_9 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4644 = remapindex_9 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4645 = remapindex_9 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4646 = remapindex_9 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4647 = remapindex_9 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4648 = remapindex_9 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4649 = remapindex_9 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4650 = remapindex_9 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4651 = remapindex_9 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4652 = remapindex_9 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4653 = remapindex_9 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4654 = remapindex_9 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4655 = remapindex_9 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4656 = remapindex_9 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_9 = _T_4656 ? _Queue16_UInt8_31_io_deq_bits : _T_4655 ? _Queue16_UInt8_30_io_deq_bits : _T_4654 ? _Queue16_UInt8_29_io_deq_bits : _T_4653 ? _Queue16_UInt8_28_io_deq_bits : _T_4652 ? _Queue16_UInt8_27_io_deq_bits : _T_4651 ? _Queue16_UInt8_26_io_deq_bits : _T_4650 ? _Queue16_UInt8_25_io_deq_bits : _T_4649 ? _Queue16_UInt8_24_io_deq_bits : _T_4648 ? _Queue16_UInt8_23_io_deq_bits : _T_4647 ? _Queue16_UInt8_22_io_deq_bits : _T_4646 ? _Queue16_UInt8_21_io_deq_bits : _T_4645 ? _Queue16_UInt8_20_io_deq_bits : _T_4644 ? _Queue16_UInt8_19_io_deq_bits : _T_4643 ? _Queue16_UInt8_18_io_deq_bits : _T_4642 ? _Queue16_UInt8_17_io_deq_bits : _T_4641 ? _Queue16_UInt8_16_io_deq_bits : _T_4640 ? _Queue16_UInt8_15_io_deq_bits : _T_4639 ? _Queue16_UInt8_14_io_deq_bits : _T_4638 ? _Queue16_UInt8_13_io_deq_bits : _T_4637 ? _Queue16_UInt8_12_io_deq_bits : _T_4636 ? _Queue16_UInt8_11_io_deq_bits : _T_4635 ? _Queue16_UInt8_10_io_deq_bits : _T_4634 ? _Queue16_UInt8_9_io_deq_bits : _T_4633 ? _Queue16_UInt8_8_io_deq_bits : _T_4632 ? _Queue16_UInt8_7_io_deq_bits : _T_4631 ? _Queue16_UInt8_6_io_deq_bits : _T_4630 ? _Queue16_UInt8_5_io_deq_bits : _T_4629 ? _Queue16_UInt8_4_io_deq_bits : _T_4628 ? _Queue16_UInt8_3_io_deq_bits : _T_4627 ? _Queue16_UInt8_2_io_deq_bits : _T_4626 ? _Queue16_UInt8_1_io_deq_bits : _T_4625 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_9 = _T_4656 ? _Queue16_UInt8_31_io_deq_valid : _T_4655 ? _Queue16_UInt8_30_io_deq_valid : _T_4654 ? _Queue16_UInt8_29_io_deq_valid : _T_4653 ? _Queue16_UInt8_28_io_deq_valid : _T_4652 ? _Queue16_UInt8_27_io_deq_valid : _T_4651 ? _Queue16_UInt8_26_io_deq_valid : _T_4650 ? _Queue16_UInt8_25_io_deq_valid : _T_4649 ? _Queue16_UInt8_24_io_deq_valid : _T_4648 ? _Queue16_UInt8_23_io_deq_valid : _T_4647 ? _Queue16_UInt8_22_io_deq_valid : _T_4646 ? _Queue16_UInt8_21_io_deq_valid : _T_4645 ? _Queue16_UInt8_20_io_deq_valid : _T_4644 ? _Queue16_UInt8_19_io_deq_valid : _T_4643 ? _Queue16_UInt8_18_io_deq_valid : _T_4642 ? _Queue16_UInt8_17_io_deq_valid : _T_4641 ? _Queue16_UInt8_16_io_deq_valid : _T_4640 ? _Queue16_UInt8_15_io_deq_valid : _T_4639 ? _Queue16_UInt8_14_io_deq_valid : _T_4638 ? _Queue16_UInt8_13_io_deq_valid : _T_4637 ? _Queue16_UInt8_12_io_deq_valid : _T_4636 ? _Queue16_UInt8_11_io_deq_valid : _T_4635 ? _Queue16_UInt8_10_io_deq_valid : _T_4634 ? _Queue16_UInt8_9_io_deq_valid : _T_4633 ? _Queue16_UInt8_8_io_deq_valid : _T_4632 ? _Queue16_UInt8_7_io_deq_valid : _T_4631 ? _Queue16_UInt8_6_io_deq_valid : _T_4630 ? _Queue16_UInt8_5_io_deq_valid : _T_4629 ? _Queue16_UInt8_4_io_deq_valid : _T_4628 ? _Queue16_UInt8_3_io_deq_valid : _T_4627 ? _Queue16_UInt8_2_io_deq_valid : _T_4626 ? _Queue16_UInt8_1_io_deq_valid : _T_4625 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_10 = _remapindex_T + 7'hA; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_100 = _remapindex_T_10 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_10 = _GEN_100[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4657 = remapindex_10 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4658 = remapindex_10 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4659 = remapindex_10 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4660 = remapindex_10 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4661 = remapindex_10 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4662 = remapindex_10 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4663 = remapindex_10 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4664 = remapindex_10 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4665 = remapindex_10 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4666 = remapindex_10 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4667 = remapindex_10 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4668 = remapindex_10 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4669 = remapindex_10 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4670 = remapindex_10 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4671 = remapindex_10 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4672 = remapindex_10 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4673 = remapindex_10 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4674 = remapindex_10 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4675 = remapindex_10 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4676 = remapindex_10 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4677 = remapindex_10 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4678 = remapindex_10 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4679 = remapindex_10 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4680 = remapindex_10 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4681 = remapindex_10 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4682 = remapindex_10 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4683 = remapindex_10 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4684 = remapindex_10 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4685 = remapindex_10 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4686 = remapindex_10 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4687 = remapindex_10 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4688 = remapindex_10 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_10 = _T_4688 ? _Queue16_UInt8_31_io_deq_bits : _T_4687 ? _Queue16_UInt8_30_io_deq_bits : _T_4686 ? _Queue16_UInt8_29_io_deq_bits : _T_4685 ? _Queue16_UInt8_28_io_deq_bits : _T_4684 ? _Queue16_UInt8_27_io_deq_bits : _T_4683 ? _Queue16_UInt8_26_io_deq_bits : _T_4682 ? _Queue16_UInt8_25_io_deq_bits : _T_4681 ? _Queue16_UInt8_24_io_deq_bits : _T_4680 ? _Queue16_UInt8_23_io_deq_bits : _T_4679 ? _Queue16_UInt8_22_io_deq_bits : _T_4678 ? _Queue16_UInt8_21_io_deq_bits : _T_4677 ? _Queue16_UInt8_20_io_deq_bits : _T_4676 ? _Queue16_UInt8_19_io_deq_bits : _T_4675 ? _Queue16_UInt8_18_io_deq_bits : _T_4674 ? _Queue16_UInt8_17_io_deq_bits : _T_4673 ? _Queue16_UInt8_16_io_deq_bits : _T_4672 ? _Queue16_UInt8_15_io_deq_bits : _T_4671 ? _Queue16_UInt8_14_io_deq_bits : _T_4670 ? _Queue16_UInt8_13_io_deq_bits : _T_4669 ? _Queue16_UInt8_12_io_deq_bits : _T_4668 ? _Queue16_UInt8_11_io_deq_bits : _T_4667 ? _Queue16_UInt8_10_io_deq_bits : _T_4666 ? _Queue16_UInt8_9_io_deq_bits : _T_4665 ? _Queue16_UInt8_8_io_deq_bits : _T_4664 ? _Queue16_UInt8_7_io_deq_bits : _T_4663 ? _Queue16_UInt8_6_io_deq_bits : _T_4662 ? _Queue16_UInt8_5_io_deq_bits : _T_4661 ? _Queue16_UInt8_4_io_deq_bits : _T_4660 ? _Queue16_UInt8_3_io_deq_bits : _T_4659 ? _Queue16_UInt8_2_io_deq_bits : _T_4658 ? _Queue16_UInt8_1_io_deq_bits : _T_4657 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_10 = _T_4688 ? _Queue16_UInt8_31_io_deq_valid : _T_4687 ? _Queue16_UInt8_30_io_deq_valid : _T_4686 ? _Queue16_UInt8_29_io_deq_valid : _T_4685 ? _Queue16_UInt8_28_io_deq_valid : _T_4684 ? _Queue16_UInt8_27_io_deq_valid : _T_4683 ? _Queue16_UInt8_26_io_deq_valid : _T_4682 ? _Queue16_UInt8_25_io_deq_valid : _T_4681 ? _Queue16_UInt8_24_io_deq_valid : _T_4680 ? _Queue16_UInt8_23_io_deq_valid : _T_4679 ? _Queue16_UInt8_22_io_deq_valid : _T_4678 ? _Queue16_UInt8_21_io_deq_valid : _T_4677 ? _Queue16_UInt8_20_io_deq_valid : _T_4676 ? _Queue16_UInt8_19_io_deq_valid : _T_4675 ? _Queue16_UInt8_18_io_deq_valid : _T_4674 ? _Queue16_UInt8_17_io_deq_valid : _T_4673 ? _Queue16_UInt8_16_io_deq_valid : _T_4672 ? _Queue16_UInt8_15_io_deq_valid : _T_4671 ? _Queue16_UInt8_14_io_deq_valid : _T_4670 ? _Queue16_UInt8_13_io_deq_valid : _T_4669 ? _Queue16_UInt8_12_io_deq_valid : _T_4668 ? _Queue16_UInt8_11_io_deq_valid : _T_4667 ? _Queue16_UInt8_10_io_deq_valid : _T_4666 ? _Queue16_UInt8_9_io_deq_valid : _T_4665 ? _Queue16_UInt8_8_io_deq_valid : _T_4664 ? _Queue16_UInt8_7_io_deq_valid : _T_4663 ? _Queue16_UInt8_6_io_deq_valid : _T_4662 ? _Queue16_UInt8_5_io_deq_valid : _T_4661 ? _Queue16_UInt8_4_io_deq_valid : _T_4660 ? _Queue16_UInt8_3_io_deq_valid : _T_4659 ? _Queue16_UInt8_2_io_deq_valid : _T_4658 ? _Queue16_UInt8_1_io_deq_valid : _T_4657 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_11 = _remapindex_T + 7'hB; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_101 = _remapindex_T_11 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_11 = _GEN_101[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4689 = remapindex_11 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4690 = remapindex_11 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4691 = remapindex_11 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4692 = remapindex_11 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4693 = remapindex_11 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4694 = remapindex_11 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4695 = remapindex_11 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4696 = remapindex_11 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4697 = remapindex_11 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4698 = remapindex_11 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4699 = remapindex_11 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4700 = remapindex_11 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4701 = remapindex_11 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4702 = remapindex_11 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4703 = remapindex_11 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4704 = remapindex_11 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4705 = remapindex_11 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4706 = remapindex_11 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4707 = remapindex_11 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4708 = remapindex_11 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4709 = remapindex_11 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4710 = remapindex_11 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4711 = remapindex_11 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4712 = remapindex_11 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4713 = remapindex_11 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4714 = remapindex_11 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4715 = remapindex_11 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4716 = remapindex_11 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4717 = remapindex_11 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4718 = remapindex_11 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4719 = remapindex_11 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4720 = remapindex_11 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_11 = _T_4720 ? _Queue16_UInt8_31_io_deq_bits : _T_4719 ? _Queue16_UInt8_30_io_deq_bits : _T_4718 ? _Queue16_UInt8_29_io_deq_bits : _T_4717 ? _Queue16_UInt8_28_io_deq_bits : _T_4716 ? _Queue16_UInt8_27_io_deq_bits : _T_4715 ? _Queue16_UInt8_26_io_deq_bits : _T_4714 ? _Queue16_UInt8_25_io_deq_bits : _T_4713 ? _Queue16_UInt8_24_io_deq_bits : _T_4712 ? _Queue16_UInt8_23_io_deq_bits : _T_4711 ? _Queue16_UInt8_22_io_deq_bits : _T_4710 ? _Queue16_UInt8_21_io_deq_bits : _T_4709 ? _Queue16_UInt8_20_io_deq_bits : _T_4708 ? _Queue16_UInt8_19_io_deq_bits : _T_4707 ? _Queue16_UInt8_18_io_deq_bits : _T_4706 ? _Queue16_UInt8_17_io_deq_bits : _T_4705 ? _Queue16_UInt8_16_io_deq_bits : _T_4704 ? _Queue16_UInt8_15_io_deq_bits : _T_4703 ? _Queue16_UInt8_14_io_deq_bits : _T_4702 ? _Queue16_UInt8_13_io_deq_bits : _T_4701 ? _Queue16_UInt8_12_io_deq_bits : _T_4700 ? _Queue16_UInt8_11_io_deq_bits : _T_4699 ? _Queue16_UInt8_10_io_deq_bits : _T_4698 ? _Queue16_UInt8_9_io_deq_bits : _T_4697 ? _Queue16_UInt8_8_io_deq_bits : _T_4696 ? _Queue16_UInt8_7_io_deq_bits : _T_4695 ? _Queue16_UInt8_6_io_deq_bits : _T_4694 ? _Queue16_UInt8_5_io_deq_bits : _T_4693 ? _Queue16_UInt8_4_io_deq_bits : _T_4692 ? _Queue16_UInt8_3_io_deq_bits : _T_4691 ? _Queue16_UInt8_2_io_deq_bits : _T_4690 ? _Queue16_UInt8_1_io_deq_bits : _T_4689 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_11 = _T_4720 ? _Queue16_UInt8_31_io_deq_valid : _T_4719 ? _Queue16_UInt8_30_io_deq_valid : _T_4718 ? _Queue16_UInt8_29_io_deq_valid : _T_4717 ? _Queue16_UInt8_28_io_deq_valid : _T_4716 ? _Queue16_UInt8_27_io_deq_valid : _T_4715 ? _Queue16_UInt8_26_io_deq_valid : _T_4714 ? _Queue16_UInt8_25_io_deq_valid : _T_4713 ? _Queue16_UInt8_24_io_deq_valid : _T_4712 ? _Queue16_UInt8_23_io_deq_valid : _T_4711 ? _Queue16_UInt8_22_io_deq_valid : _T_4710 ? _Queue16_UInt8_21_io_deq_valid : _T_4709 ? _Queue16_UInt8_20_io_deq_valid : _T_4708 ? _Queue16_UInt8_19_io_deq_valid : _T_4707 ? _Queue16_UInt8_18_io_deq_valid : _T_4706 ? _Queue16_UInt8_17_io_deq_valid : _T_4705 ? _Queue16_UInt8_16_io_deq_valid : _T_4704 ? _Queue16_UInt8_15_io_deq_valid : _T_4703 ? _Queue16_UInt8_14_io_deq_valid : _T_4702 ? _Queue16_UInt8_13_io_deq_valid : _T_4701 ? _Queue16_UInt8_12_io_deq_valid : _T_4700 ? _Queue16_UInt8_11_io_deq_valid : _T_4699 ? _Queue16_UInt8_10_io_deq_valid : _T_4698 ? _Queue16_UInt8_9_io_deq_valid : _T_4697 ? _Queue16_UInt8_8_io_deq_valid : _T_4696 ? _Queue16_UInt8_7_io_deq_valid : _T_4695 ? _Queue16_UInt8_6_io_deq_valid : _T_4694 ? _Queue16_UInt8_5_io_deq_valid : _T_4693 ? _Queue16_UInt8_4_io_deq_valid : _T_4692 ? _Queue16_UInt8_3_io_deq_valid : _T_4691 ? _Queue16_UInt8_2_io_deq_valid : _T_4690 ? _Queue16_UInt8_1_io_deq_valid : _T_4689 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_12 = _remapindex_T + 7'hC; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_102 = _remapindex_T_12 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_12 = _GEN_102[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4721 = remapindex_12 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4722 = remapindex_12 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4723 = remapindex_12 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4724 = remapindex_12 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4725 = remapindex_12 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4726 = remapindex_12 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4727 = remapindex_12 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4728 = remapindex_12 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4729 = remapindex_12 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4730 = remapindex_12 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4731 = remapindex_12 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4732 = remapindex_12 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4733 = remapindex_12 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4734 = remapindex_12 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4735 = remapindex_12 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4736 = remapindex_12 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4737 = remapindex_12 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4738 = remapindex_12 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4739 = remapindex_12 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4740 = remapindex_12 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4741 = remapindex_12 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4742 = remapindex_12 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4743 = remapindex_12 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4744 = remapindex_12 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4745 = remapindex_12 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4746 = remapindex_12 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4747 = remapindex_12 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4748 = remapindex_12 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4749 = remapindex_12 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4750 = remapindex_12 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4751 = remapindex_12 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4752 = remapindex_12 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_12 = _T_4752 ? _Queue16_UInt8_31_io_deq_bits : _T_4751 ? _Queue16_UInt8_30_io_deq_bits : _T_4750 ? _Queue16_UInt8_29_io_deq_bits : _T_4749 ? _Queue16_UInt8_28_io_deq_bits : _T_4748 ? _Queue16_UInt8_27_io_deq_bits : _T_4747 ? _Queue16_UInt8_26_io_deq_bits : _T_4746 ? _Queue16_UInt8_25_io_deq_bits : _T_4745 ? _Queue16_UInt8_24_io_deq_bits : _T_4744 ? _Queue16_UInt8_23_io_deq_bits : _T_4743 ? _Queue16_UInt8_22_io_deq_bits : _T_4742 ? _Queue16_UInt8_21_io_deq_bits : _T_4741 ? _Queue16_UInt8_20_io_deq_bits : _T_4740 ? _Queue16_UInt8_19_io_deq_bits : _T_4739 ? _Queue16_UInt8_18_io_deq_bits : _T_4738 ? _Queue16_UInt8_17_io_deq_bits : _T_4737 ? _Queue16_UInt8_16_io_deq_bits : _T_4736 ? _Queue16_UInt8_15_io_deq_bits : _T_4735 ? _Queue16_UInt8_14_io_deq_bits : _T_4734 ? _Queue16_UInt8_13_io_deq_bits : _T_4733 ? _Queue16_UInt8_12_io_deq_bits : _T_4732 ? _Queue16_UInt8_11_io_deq_bits : _T_4731 ? _Queue16_UInt8_10_io_deq_bits : _T_4730 ? _Queue16_UInt8_9_io_deq_bits : _T_4729 ? _Queue16_UInt8_8_io_deq_bits : _T_4728 ? _Queue16_UInt8_7_io_deq_bits : _T_4727 ? _Queue16_UInt8_6_io_deq_bits : _T_4726 ? _Queue16_UInt8_5_io_deq_bits : _T_4725 ? _Queue16_UInt8_4_io_deq_bits : _T_4724 ? _Queue16_UInt8_3_io_deq_bits : _T_4723 ? _Queue16_UInt8_2_io_deq_bits : _T_4722 ? _Queue16_UInt8_1_io_deq_bits : _T_4721 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_12 = _T_4752 ? _Queue16_UInt8_31_io_deq_valid : _T_4751 ? _Queue16_UInt8_30_io_deq_valid : _T_4750 ? _Queue16_UInt8_29_io_deq_valid : _T_4749 ? _Queue16_UInt8_28_io_deq_valid : _T_4748 ? _Queue16_UInt8_27_io_deq_valid : _T_4747 ? _Queue16_UInt8_26_io_deq_valid : _T_4746 ? _Queue16_UInt8_25_io_deq_valid : _T_4745 ? _Queue16_UInt8_24_io_deq_valid : _T_4744 ? _Queue16_UInt8_23_io_deq_valid : _T_4743 ? _Queue16_UInt8_22_io_deq_valid : _T_4742 ? _Queue16_UInt8_21_io_deq_valid : _T_4741 ? _Queue16_UInt8_20_io_deq_valid : _T_4740 ? _Queue16_UInt8_19_io_deq_valid : _T_4739 ? _Queue16_UInt8_18_io_deq_valid : _T_4738 ? _Queue16_UInt8_17_io_deq_valid : _T_4737 ? _Queue16_UInt8_16_io_deq_valid : _T_4736 ? _Queue16_UInt8_15_io_deq_valid : _T_4735 ? _Queue16_UInt8_14_io_deq_valid : _T_4734 ? _Queue16_UInt8_13_io_deq_valid : _T_4733 ? _Queue16_UInt8_12_io_deq_valid : _T_4732 ? _Queue16_UInt8_11_io_deq_valid : _T_4731 ? _Queue16_UInt8_10_io_deq_valid : _T_4730 ? _Queue16_UInt8_9_io_deq_valid : _T_4729 ? _Queue16_UInt8_8_io_deq_valid : _T_4728 ? _Queue16_UInt8_7_io_deq_valid : _T_4727 ? _Queue16_UInt8_6_io_deq_valid : _T_4726 ? _Queue16_UInt8_5_io_deq_valid : _T_4725 ? _Queue16_UInt8_4_io_deq_valid : _T_4724 ? _Queue16_UInt8_3_io_deq_valid : _T_4723 ? _Queue16_UInt8_2_io_deq_valid : _T_4722 ? _Queue16_UInt8_1_io_deq_valid : _T_4721 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_13 = _remapindex_T + 7'hD; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_103 = _remapindex_T_13 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_13 = _GEN_103[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4753 = remapindex_13 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4754 = remapindex_13 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4755 = remapindex_13 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4756 = remapindex_13 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4757 = remapindex_13 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4758 = remapindex_13 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4759 = remapindex_13 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4760 = remapindex_13 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4761 = remapindex_13 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4762 = remapindex_13 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4763 = remapindex_13 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4764 = remapindex_13 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4765 = remapindex_13 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4766 = remapindex_13 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4767 = remapindex_13 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4768 = remapindex_13 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4769 = remapindex_13 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4770 = remapindex_13 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4771 = remapindex_13 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4772 = remapindex_13 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4773 = remapindex_13 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4774 = remapindex_13 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4775 = remapindex_13 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4776 = remapindex_13 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4777 = remapindex_13 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4778 = remapindex_13 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4779 = remapindex_13 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4780 = remapindex_13 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4781 = remapindex_13 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4782 = remapindex_13 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4783 = remapindex_13 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4784 = remapindex_13 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_13 = _T_4784 ? _Queue16_UInt8_31_io_deq_bits : _T_4783 ? _Queue16_UInt8_30_io_deq_bits : _T_4782 ? _Queue16_UInt8_29_io_deq_bits : _T_4781 ? _Queue16_UInt8_28_io_deq_bits : _T_4780 ? _Queue16_UInt8_27_io_deq_bits : _T_4779 ? _Queue16_UInt8_26_io_deq_bits : _T_4778 ? _Queue16_UInt8_25_io_deq_bits : _T_4777 ? _Queue16_UInt8_24_io_deq_bits : _T_4776 ? _Queue16_UInt8_23_io_deq_bits : _T_4775 ? _Queue16_UInt8_22_io_deq_bits : _T_4774 ? _Queue16_UInt8_21_io_deq_bits : _T_4773 ? _Queue16_UInt8_20_io_deq_bits : _T_4772 ? _Queue16_UInt8_19_io_deq_bits : _T_4771 ? _Queue16_UInt8_18_io_deq_bits : _T_4770 ? _Queue16_UInt8_17_io_deq_bits : _T_4769 ? _Queue16_UInt8_16_io_deq_bits : _T_4768 ? _Queue16_UInt8_15_io_deq_bits : _T_4767 ? _Queue16_UInt8_14_io_deq_bits : _T_4766 ? _Queue16_UInt8_13_io_deq_bits : _T_4765 ? _Queue16_UInt8_12_io_deq_bits : _T_4764 ? _Queue16_UInt8_11_io_deq_bits : _T_4763 ? _Queue16_UInt8_10_io_deq_bits : _T_4762 ? _Queue16_UInt8_9_io_deq_bits : _T_4761 ? _Queue16_UInt8_8_io_deq_bits : _T_4760 ? _Queue16_UInt8_7_io_deq_bits : _T_4759 ? _Queue16_UInt8_6_io_deq_bits : _T_4758 ? _Queue16_UInt8_5_io_deq_bits : _T_4757 ? _Queue16_UInt8_4_io_deq_bits : _T_4756 ? _Queue16_UInt8_3_io_deq_bits : _T_4755 ? _Queue16_UInt8_2_io_deq_bits : _T_4754 ? _Queue16_UInt8_1_io_deq_bits : _T_4753 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_13 = _T_4784 ? _Queue16_UInt8_31_io_deq_valid : _T_4783 ? _Queue16_UInt8_30_io_deq_valid : _T_4782 ? _Queue16_UInt8_29_io_deq_valid : _T_4781 ? _Queue16_UInt8_28_io_deq_valid : _T_4780 ? _Queue16_UInt8_27_io_deq_valid : _T_4779 ? _Queue16_UInt8_26_io_deq_valid : _T_4778 ? _Queue16_UInt8_25_io_deq_valid : _T_4777 ? _Queue16_UInt8_24_io_deq_valid : _T_4776 ? _Queue16_UInt8_23_io_deq_valid : _T_4775 ? _Queue16_UInt8_22_io_deq_valid : _T_4774 ? _Queue16_UInt8_21_io_deq_valid : _T_4773 ? _Queue16_UInt8_20_io_deq_valid : _T_4772 ? _Queue16_UInt8_19_io_deq_valid : _T_4771 ? _Queue16_UInt8_18_io_deq_valid : _T_4770 ? _Queue16_UInt8_17_io_deq_valid : _T_4769 ? _Queue16_UInt8_16_io_deq_valid : _T_4768 ? _Queue16_UInt8_15_io_deq_valid : _T_4767 ? _Queue16_UInt8_14_io_deq_valid : _T_4766 ? _Queue16_UInt8_13_io_deq_valid : _T_4765 ? _Queue16_UInt8_12_io_deq_valid : _T_4764 ? _Queue16_UInt8_11_io_deq_valid : _T_4763 ? _Queue16_UInt8_10_io_deq_valid : _T_4762 ? _Queue16_UInt8_9_io_deq_valid : _T_4761 ? _Queue16_UInt8_8_io_deq_valid : _T_4760 ? _Queue16_UInt8_7_io_deq_valid : _T_4759 ? _Queue16_UInt8_6_io_deq_valid : _T_4758 ? _Queue16_UInt8_5_io_deq_valid : _T_4757 ? _Queue16_UInt8_4_io_deq_valid : _T_4756 ? _Queue16_UInt8_3_io_deq_valid : _T_4755 ? _Queue16_UInt8_2_io_deq_valid : _T_4754 ? _Queue16_UInt8_1_io_deq_valid : _T_4753 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_14 = _remapindex_T + 7'hE; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_104 = _remapindex_T_14 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_14 = _GEN_104[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4785 = remapindex_14 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4786 = remapindex_14 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4787 = remapindex_14 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4788 = remapindex_14 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4789 = remapindex_14 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4790 = remapindex_14 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4791 = remapindex_14 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4792 = remapindex_14 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4793 = remapindex_14 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4794 = remapindex_14 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4795 = remapindex_14 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4796 = remapindex_14 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4797 = remapindex_14 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4798 = remapindex_14 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4799 = remapindex_14 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4800 = remapindex_14 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4801 = remapindex_14 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4802 = remapindex_14 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4803 = remapindex_14 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4804 = remapindex_14 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4805 = remapindex_14 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4806 = remapindex_14 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4807 = remapindex_14 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4808 = remapindex_14 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4809 = remapindex_14 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4810 = remapindex_14 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4811 = remapindex_14 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4812 = remapindex_14 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4813 = remapindex_14 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4814 = remapindex_14 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4815 = remapindex_14 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4816 = remapindex_14 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_14 = _T_4816 ? _Queue16_UInt8_31_io_deq_bits : _T_4815 ? _Queue16_UInt8_30_io_deq_bits : _T_4814 ? _Queue16_UInt8_29_io_deq_bits : _T_4813 ? _Queue16_UInt8_28_io_deq_bits : _T_4812 ? _Queue16_UInt8_27_io_deq_bits : _T_4811 ? _Queue16_UInt8_26_io_deq_bits : _T_4810 ? _Queue16_UInt8_25_io_deq_bits : _T_4809 ? _Queue16_UInt8_24_io_deq_bits : _T_4808 ? _Queue16_UInt8_23_io_deq_bits : _T_4807 ? _Queue16_UInt8_22_io_deq_bits : _T_4806 ? _Queue16_UInt8_21_io_deq_bits : _T_4805 ? _Queue16_UInt8_20_io_deq_bits : _T_4804 ? _Queue16_UInt8_19_io_deq_bits : _T_4803 ? _Queue16_UInt8_18_io_deq_bits : _T_4802 ? _Queue16_UInt8_17_io_deq_bits : _T_4801 ? _Queue16_UInt8_16_io_deq_bits : _T_4800 ? _Queue16_UInt8_15_io_deq_bits : _T_4799 ? _Queue16_UInt8_14_io_deq_bits : _T_4798 ? _Queue16_UInt8_13_io_deq_bits : _T_4797 ? _Queue16_UInt8_12_io_deq_bits : _T_4796 ? _Queue16_UInt8_11_io_deq_bits : _T_4795 ? _Queue16_UInt8_10_io_deq_bits : _T_4794 ? _Queue16_UInt8_9_io_deq_bits : _T_4793 ? _Queue16_UInt8_8_io_deq_bits : _T_4792 ? _Queue16_UInt8_7_io_deq_bits : _T_4791 ? _Queue16_UInt8_6_io_deq_bits : _T_4790 ? _Queue16_UInt8_5_io_deq_bits : _T_4789 ? _Queue16_UInt8_4_io_deq_bits : _T_4788 ? _Queue16_UInt8_3_io_deq_bits : _T_4787 ? _Queue16_UInt8_2_io_deq_bits : _T_4786 ? _Queue16_UInt8_1_io_deq_bits : _T_4785 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_14 = _T_4816 ? _Queue16_UInt8_31_io_deq_valid : _T_4815 ? _Queue16_UInt8_30_io_deq_valid : _T_4814 ? _Queue16_UInt8_29_io_deq_valid : _T_4813 ? _Queue16_UInt8_28_io_deq_valid : _T_4812 ? _Queue16_UInt8_27_io_deq_valid : _T_4811 ? _Queue16_UInt8_26_io_deq_valid : _T_4810 ? _Queue16_UInt8_25_io_deq_valid : _T_4809 ? _Queue16_UInt8_24_io_deq_valid : _T_4808 ? _Queue16_UInt8_23_io_deq_valid : _T_4807 ? _Queue16_UInt8_22_io_deq_valid : _T_4806 ? _Queue16_UInt8_21_io_deq_valid : _T_4805 ? _Queue16_UInt8_20_io_deq_valid : _T_4804 ? _Queue16_UInt8_19_io_deq_valid : _T_4803 ? _Queue16_UInt8_18_io_deq_valid : _T_4802 ? _Queue16_UInt8_17_io_deq_valid : _T_4801 ? _Queue16_UInt8_16_io_deq_valid : _T_4800 ? _Queue16_UInt8_15_io_deq_valid : _T_4799 ? _Queue16_UInt8_14_io_deq_valid : _T_4798 ? _Queue16_UInt8_13_io_deq_valid : _T_4797 ? _Queue16_UInt8_12_io_deq_valid : _T_4796 ? _Queue16_UInt8_11_io_deq_valid : _T_4795 ? _Queue16_UInt8_10_io_deq_valid : _T_4794 ? _Queue16_UInt8_9_io_deq_valid : _T_4793 ? _Queue16_UInt8_8_io_deq_valid : _T_4792 ? _Queue16_UInt8_7_io_deq_valid : _T_4791 ? _Queue16_UInt8_6_io_deq_valid : _T_4790 ? _Queue16_UInt8_5_io_deq_valid : _T_4789 ? _Queue16_UInt8_4_io_deq_valid : _T_4788 ? _Queue16_UInt8_3_io_deq_valid : _T_4787 ? _Queue16_UInt8_2_io_deq_valid : _T_4786 ? _Queue16_UInt8_1_io_deq_valid : _T_4785 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_15 = _remapindex_T + 7'hF; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_105 = _remapindex_T_15 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_15 = _GEN_105[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4817 = remapindex_15 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4818 = remapindex_15 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4819 = remapindex_15 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4820 = remapindex_15 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4821 = remapindex_15 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4822 = remapindex_15 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4823 = remapindex_15 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4824 = remapindex_15 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4825 = remapindex_15 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4826 = remapindex_15 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4827 = remapindex_15 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4828 = remapindex_15 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4829 = remapindex_15 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4830 = remapindex_15 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4831 = remapindex_15 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4832 = remapindex_15 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4833 = remapindex_15 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4834 = remapindex_15 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4835 = remapindex_15 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4836 = remapindex_15 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4837 = remapindex_15 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4838 = remapindex_15 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4839 = remapindex_15 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4840 = remapindex_15 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4841 = remapindex_15 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4842 = remapindex_15 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4843 = remapindex_15 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4844 = remapindex_15 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4845 = remapindex_15 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4846 = remapindex_15 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4847 = remapindex_15 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4848 = remapindex_15 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_15 = _T_4848 ? _Queue16_UInt8_31_io_deq_bits : _T_4847 ? _Queue16_UInt8_30_io_deq_bits : _T_4846 ? _Queue16_UInt8_29_io_deq_bits : _T_4845 ? _Queue16_UInt8_28_io_deq_bits : _T_4844 ? _Queue16_UInt8_27_io_deq_bits : _T_4843 ? _Queue16_UInt8_26_io_deq_bits : _T_4842 ? _Queue16_UInt8_25_io_deq_bits : _T_4841 ? _Queue16_UInt8_24_io_deq_bits : _T_4840 ? _Queue16_UInt8_23_io_deq_bits : _T_4839 ? _Queue16_UInt8_22_io_deq_bits : _T_4838 ? _Queue16_UInt8_21_io_deq_bits : _T_4837 ? _Queue16_UInt8_20_io_deq_bits : _T_4836 ? _Queue16_UInt8_19_io_deq_bits : _T_4835 ? _Queue16_UInt8_18_io_deq_bits : _T_4834 ? _Queue16_UInt8_17_io_deq_bits : _T_4833 ? _Queue16_UInt8_16_io_deq_bits : _T_4832 ? _Queue16_UInt8_15_io_deq_bits : _T_4831 ? _Queue16_UInt8_14_io_deq_bits : _T_4830 ? _Queue16_UInt8_13_io_deq_bits : _T_4829 ? _Queue16_UInt8_12_io_deq_bits : _T_4828 ? _Queue16_UInt8_11_io_deq_bits : _T_4827 ? _Queue16_UInt8_10_io_deq_bits : _T_4826 ? _Queue16_UInt8_9_io_deq_bits : _T_4825 ? _Queue16_UInt8_8_io_deq_bits : _T_4824 ? _Queue16_UInt8_7_io_deq_bits : _T_4823 ? _Queue16_UInt8_6_io_deq_bits : _T_4822 ? _Queue16_UInt8_5_io_deq_bits : _T_4821 ? _Queue16_UInt8_4_io_deq_bits : _T_4820 ? _Queue16_UInt8_3_io_deq_bits : _T_4819 ? _Queue16_UInt8_2_io_deq_bits : _T_4818 ? _Queue16_UInt8_1_io_deq_bits : _T_4817 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_15 = _T_4848 ? _Queue16_UInt8_31_io_deq_valid : _T_4847 ? _Queue16_UInt8_30_io_deq_valid : _T_4846 ? _Queue16_UInt8_29_io_deq_valid : _T_4845 ? _Queue16_UInt8_28_io_deq_valid : _T_4844 ? _Queue16_UInt8_27_io_deq_valid : _T_4843 ? _Queue16_UInt8_26_io_deq_valid : _T_4842 ? _Queue16_UInt8_25_io_deq_valid : _T_4841 ? _Queue16_UInt8_24_io_deq_valid : _T_4840 ? _Queue16_UInt8_23_io_deq_valid : _T_4839 ? _Queue16_UInt8_22_io_deq_valid : _T_4838 ? _Queue16_UInt8_21_io_deq_valid : _T_4837 ? _Queue16_UInt8_20_io_deq_valid : _T_4836 ? _Queue16_UInt8_19_io_deq_valid : _T_4835 ? _Queue16_UInt8_18_io_deq_valid : _T_4834 ? _Queue16_UInt8_17_io_deq_valid : _T_4833 ? _Queue16_UInt8_16_io_deq_valid : _T_4832 ? _Queue16_UInt8_15_io_deq_valid : _T_4831 ? _Queue16_UInt8_14_io_deq_valid : _T_4830 ? _Queue16_UInt8_13_io_deq_valid : _T_4829 ? _Queue16_UInt8_12_io_deq_valid : _T_4828 ? _Queue16_UInt8_11_io_deq_valid : _T_4827 ? _Queue16_UInt8_10_io_deq_valid : _T_4826 ? _Queue16_UInt8_9_io_deq_valid : _T_4825 ? _Queue16_UInt8_8_io_deq_valid : _T_4824 ? _Queue16_UInt8_7_io_deq_valid : _T_4823 ? _Queue16_UInt8_6_io_deq_valid : _T_4822 ? _Queue16_UInt8_5_io_deq_valid : _T_4821 ? _Queue16_UInt8_4_io_deq_valid : _T_4820 ? _Queue16_UInt8_3_io_deq_valid : _T_4819 ? _Queue16_UInt8_2_io_deq_valid : _T_4818 ? _Queue16_UInt8_1_io_deq_valid : _T_4817 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_16 = _remapindex_T + 7'h10; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_106 = _remapindex_T_16 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_16 = _GEN_106[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4849 = remapindex_16 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4850 = remapindex_16 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4851 = remapindex_16 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4852 = remapindex_16 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4853 = remapindex_16 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4854 = remapindex_16 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4855 = remapindex_16 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4856 = remapindex_16 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4857 = remapindex_16 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4858 = remapindex_16 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4859 = remapindex_16 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4860 = remapindex_16 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4861 = remapindex_16 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4862 = remapindex_16 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4863 = remapindex_16 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4864 = remapindex_16 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4865 = remapindex_16 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4866 = remapindex_16 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4867 = remapindex_16 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4868 = remapindex_16 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4869 = remapindex_16 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4870 = remapindex_16 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4871 = remapindex_16 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4872 = remapindex_16 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4873 = remapindex_16 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4874 = remapindex_16 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4875 = remapindex_16 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4876 = remapindex_16 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4877 = remapindex_16 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4878 = remapindex_16 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4879 = remapindex_16 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4880 = remapindex_16 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_16 = _T_4880 ? _Queue16_UInt8_31_io_deq_bits : _T_4879 ? _Queue16_UInt8_30_io_deq_bits : _T_4878 ? _Queue16_UInt8_29_io_deq_bits : _T_4877 ? _Queue16_UInt8_28_io_deq_bits : _T_4876 ? _Queue16_UInt8_27_io_deq_bits : _T_4875 ? _Queue16_UInt8_26_io_deq_bits : _T_4874 ? _Queue16_UInt8_25_io_deq_bits : _T_4873 ? _Queue16_UInt8_24_io_deq_bits : _T_4872 ? _Queue16_UInt8_23_io_deq_bits : _T_4871 ? _Queue16_UInt8_22_io_deq_bits : _T_4870 ? _Queue16_UInt8_21_io_deq_bits : _T_4869 ? _Queue16_UInt8_20_io_deq_bits : _T_4868 ? _Queue16_UInt8_19_io_deq_bits : _T_4867 ? _Queue16_UInt8_18_io_deq_bits : _T_4866 ? _Queue16_UInt8_17_io_deq_bits : _T_4865 ? _Queue16_UInt8_16_io_deq_bits : _T_4864 ? _Queue16_UInt8_15_io_deq_bits : _T_4863 ? _Queue16_UInt8_14_io_deq_bits : _T_4862 ? _Queue16_UInt8_13_io_deq_bits : _T_4861 ? _Queue16_UInt8_12_io_deq_bits : _T_4860 ? _Queue16_UInt8_11_io_deq_bits : _T_4859 ? _Queue16_UInt8_10_io_deq_bits : _T_4858 ? _Queue16_UInt8_9_io_deq_bits : _T_4857 ? _Queue16_UInt8_8_io_deq_bits : _T_4856 ? _Queue16_UInt8_7_io_deq_bits : _T_4855 ? _Queue16_UInt8_6_io_deq_bits : _T_4854 ? _Queue16_UInt8_5_io_deq_bits : _T_4853 ? _Queue16_UInt8_4_io_deq_bits : _T_4852 ? _Queue16_UInt8_3_io_deq_bits : _T_4851 ? _Queue16_UInt8_2_io_deq_bits : _T_4850 ? _Queue16_UInt8_1_io_deq_bits : _T_4849 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_16 = _T_4880 ? _Queue16_UInt8_31_io_deq_valid : _T_4879 ? _Queue16_UInt8_30_io_deq_valid : _T_4878 ? _Queue16_UInt8_29_io_deq_valid : _T_4877 ? _Queue16_UInt8_28_io_deq_valid : _T_4876 ? _Queue16_UInt8_27_io_deq_valid : _T_4875 ? _Queue16_UInt8_26_io_deq_valid : _T_4874 ? _Queue16_UInt8_25_io_deq_valid : _T_4873 ? _Queue16_UInt8_24_io_deq_valid : _T_4872 ? _Queue16_UInt8_23_io_deq_valid : _T_4871 ? _Queue16_UInt8_22_io_deq_valid : _T_4870 ? _Queue16_UInt8_21_io_deq_valid : _T_4869 ? _Queue16_UInt8_20_io_deq_valid : _T_4868 ? _Queue16_UInt8_19_io_deq_valid : _T_4867 ? _Queue16_UInt8_18_io_deq_valid : _T_4866 ? _Queue16_UInt8_17_io_deq_valid : _T_4865 ? _Queue16_UInt8_16_io_deq_valid : _T_4864 ? _Queue16_UInt8_15_io_deq_valid : _T_4863 ? _Queue16_UInt8_14_io_deq_valid : _T_4862 ? _Queue16_UInt8_13_io_deq_valid : _T_4861 ? _Queue16_UInt8_12_io_deq_valid : _T_4860 ? _Queue16_UInt8_11_io_deq_valid : _T_4859 ? _Queue16_UInt8_10_io_deq_valid : _T_4858 ? _Queue16_UInt8_9_io_deq_valid : _T_4857 ? _Queue16_UInt8_8_io_deq_valid : _T_4856 ? _Queue16_UInt8_7_io_deq_valid : _T_4855 ? _Queue16_UInt8_6_io_deq_valid : _T_4854 ? _Queue16_UInt8_5_io_deq_valid : _T_4853 ? _Queue16_UInt8_4_io_deq_valid : _T_4852 ? _Queue16_UInt8_3_io_deq_valid : _T_4851 ? _Queue16_UInt8_2_io_deq_valid : _T_4850 ? _Queue16_UInt8_1_io_deq_valid : _T_4849 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_17 = _remapindex_T + 7'h11; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_107 = _remapindex_T_17 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_17 = _GEN_107[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4881 = remapindex_17 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4882 = remapindex_17 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4883 = remapindex_17 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4884 = remapindex_17 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4885 = remapindex_17 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4886 = remapindex_17 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4887 = remapindex_17 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4888 = remapindex_17 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4889 = remapindex_17 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4890 = remapindex_17 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4891 = remapindex_17 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4892 = remapindex_17 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4893 = remapindex_17 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4894 = remapindex_17 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4895 = remapindex_17 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4896 = remapindex_17 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4897 = remapindex_17 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4898 = remapindex_17 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4899 = remapindex_17 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4900 = remapindex_17 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4901 = remapindex_17 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4902 = remapindex_17 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4903 = remapindex_17 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4904 = remapindex_17 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4905 = remapindex_17 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4906 = remapindex_17 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4907 = remapindex_17 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4908 = remapindex_17 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4909 = remapindex_17 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4910 = remapindex_17 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4911 = remapindex_17 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4912 = remapindex_17 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_17 = _T_4912 ? _Queue16_UInt8_31_io_deq_bits : _T_4911 ? _Queue16_UInt8_30_io_deq_bits : _T_4910 ? _Queue16_UInt8_29_io_deq_bits : _T_4909 ? _Queue16_UInt8_28_io_deq_bits : _T_4908 ? _Queue16_UInt8_27_io_deq_bits : _T_4907 ? _Queue16_UInt8_26_io_deq_bits : _T_4906 ? _Queue16_UInt8_25_io_deq_bits : _T_4905 ? _Queue16_UInt8_24_io_deq_bits : _T_4904 ? _Queue16_UInt8_23_io_deq_bits : _T_4903 ? _Queue16_UInt8_22_io_deq_bits : _T_4902 ? _Queue16_UInt8_21_io_deq_bits : _T_4901 ? _Queue16_UInt8_20_io_deq_bits : _T_4900 ? _Queue16_UInt8_19_io_deq_bits : _T_4899 ? _Queue16_UInt8_18_io_deq_bits : _T_4898 ? _Queue16_UInt8_17_io_deq_bits : _T_4897 ? _Queue16_UInt8_16_io_deq_bits : _T_4896 ? _Queue16_UInt8_15_io_deq_bits : _T_4895 ? _Queue16_UInt8_14_io_deq_bits : _T_4894 ? _Queue16_UInt8_13_io_deq_bits : _T_4893 ? _Queue16_UInt8_12_io_deq_bits : _T_4892 ? _Queue16_UInt8_11_io_deq_bits : _T_4891 ? _Queue16_UInt8_10_io_deq_bits : _T_4890 ? _Queue16_UInt8_9_io_deq_bits : _T_4889 ? _Queue16_UInt8_8_io_deq_bits : _T_4888 ? _Queue16_UInt8_7_io_deq_bits : _T_4887 ? _Queue16_UInt8_6_io_deq_bits : _T_4886 ? _Queue16_UInt8_5_io_deq_bits : _T_4885 ? _Queue16_UInt8_4_io_deq_bits : _T_4884 ? _Queue16_UInt8_3_io_deq_bits : _T_4883 ? _Queue16_UInt8_2_io_deq_bits : _T_4882 ? _Queue16_UInt8_1_io_deq_bits : _T_4881 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_17 = _T_4912 ? _Queue16_UInt8_31_io_deq_valid : _T_4911 ? _Queue16_UInt8_30_io_deq_valid : _T_4910 ? _Queue16_UInt8_29_io_deq_valid : _T_4909 ? _Queue16_UInt8_28_io_deq_valid : _T_4908 ? _Queue16_UInt8_27_io_deq_valid : _T_4907 ? _Queue16_UInt8_26_io_deq_valid : _T_4906 ? _Queue16_UInt8_25_io_deq_valid : _T_4905 ? _Queue16_UInt8_24_io_deq_valid : _T_4904 ? _Queue16_UInt8_23_io_deq_valid : _T_4903 ? _Queue16_UInt8_22_io_deq_valid : _T_4902 ? _Queue16_UInt8_21_io_deq_valid : _T_4901 ? _Queue16_UInt8_20_io_deq_valid : _T_4900 ? _Queue16_UInt8_19_io_deq_valid : _T_4899 ? _Queue16_UInt8_18_io_deq_valid : _T_4898 ? _Queue16_UInt8_17_io_deq_valid : _T_4897 ? _Queue16_UInt8_16_io_deq_valid : _T_4896 ? _Queue16_UInt8_15_io_deq_valid : _T_4895 ? _Queue16_UInt8_14_io_deq_valid : _T_4894 ? _Queue16_UInt8_13_io_deq_valid : _T_4893 ? _Queue16_UInt8_12_io_deq_valid : _T_4892 ? _Queue16_UInt8_11_io_deq_valid : _T_4891 ? _Queue16_UInt8_10_io_deq_valid : _T_4890 ? _Queue16_UInt8_9_io_deq_valid : _T_4889 ? _Queue16_UInt8_8_io_deq_valid : _T_4888 ? _Queue16_UInt8_7_io_deq_valid : _T_4887 ? _Queue16_UInt8_6_io_deq_valid : _T_4886 ? _Queue16_UInt8_5_io_deq_valid : _T_4885 ? _Queue16_UInt8_4_io_deq_valid : _T_4884 ? _Queue16_UInt8_3_io_deq_valid : _T_4883 ? _Queue16_UInt8_2_io_deq_valid : _T_4882 ? _Queue16_UInt8_1_io_deq_valid : _T_4881 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_18 = _remapindex_T + 7'h12; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_108 = _remapindex_T_18 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_18 = _GEN_108[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4913 = remapindex_18 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4914 = remapindex_18 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4915 = remapindex_18 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4916 = remapindex_18 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4917 = remapindex_18 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4918 = remapindex_18 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4919 = remapindex_18 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4920 = remapindex_18 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4921 = remapindex_18 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4922 = remapindex_18 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4923 = remapindex_18 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4924 = remapindex_18 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4925 = remapindex_18 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4926 = remapindex_18 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4927 = remapindex_18 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4928 = remapindex_18 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4929 = remapindex_18 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4930 = remapindex_18 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4931 = remapindex_18 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4932 = remapindex_18 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4933 = remapindex_18 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4934 = remapindex_18 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4935 = remapindex_18 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4936 = remapindex_18 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4937 = remapindex_18 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4938 = remapindex_18 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4939 = remapindex_18 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4940 = remapindex_18 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4941 = remapindex_18 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4942 = remapindex_18 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4943 = remapindex_18 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4944 = remapindex_18 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_18 = _T_4944 ? _Queue16_UInt8_31_io_deq_bits : _T_4943 ? _Queue16_UInt8_30_io_deq_bits : _T_4942 ? _Queue16_UInt8_29_io_deq_bits : _T_4941 ? _Queue16_UInt8_28_io_deq_bits : _T_4940 ? _Queue16_UInt8_27_io_deq_bits : _T_4939 ? _Queue16_UInt8_26_io_deq_bits : _T_4938 ? _Queue16_UInt8_25_io_deq_bits : _T_4937 ? _Queue16_UInt8_24_io_deq_bits : _T_4936 ? _Queue16_UInt8_23_io_deq_bits : _T_4935 ? _Queue16_UInt8_22_io_deq_bits : _T_4934 ? _Queue16_UInt8_21_io_deq_bits : _T_4933 ? _Queue16_UInt8_20_io_deq_bits : _T_4932 ? _Queue16_UInt8_19_io_deq_bits : _T_4931 ? _Queue16_UInt8_18_io_deq_bits : _T_4930 ? _Queue16_UInt8_17_io_deq_bits : _T_4929 ? _Queue16_UInt8_16_io_deq_bits : _T_4928 ? _Queue16_UInt8_15_io_deq_bits : _T_4927 ? _Queue16_UInt8_14_io_deq_bits : _T_4926 ? _Queue16_UInt8_13_io_deq_bits : _T_4925 ? _Queue16_UInt8_12_io_deq_bits : _T_4924 ? _Queue16_UInt8_11_io_deq_bits : _T_4923 ? _Queue16_UInt8_10_io_deq_bits : _T_4922 ? _Queue16_UInt8_9_io_deq_bits : _T_4921 ? _Queue16_UInt8_8_io_deq_bits : _T_4920 ? _Queue16_UInt8_7_io_deq_bits : _T_4919 ? _Queue16_UInt8_6_io_deq_bits : _T_4918 ? _Queue16_UInt8_5_io_deq_bits : _T_4917 ? _Queue16_UInt8_4_io_deq_bits : _T_4916 ? _Queue16_UInt8_3_io_deq_bits : _T_4915 ? _Queue16_UInt8_2_io_deq_bits : _T_4914 ? _Queue16_UInt8_1_io_deq_bits : _T_4913 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_18 = _T_4944 ? _Queue16_UInt8_31_io_deq_valid : _T_4943 ? _Queue16_UInt8_30_io_deq_valid : _T_4942 ? _Queue16_UInt8_29_io_deq_valid : _T_4941 ? _Queue16_UInt8_28_io_deq_valid : _T_4940 ? _Queue16_UInt8_27_io_deq_valid : _T_4939 ? _Queue16_UInt8_26_io_deq_valid : _T_4938 ? _Queue16_UInt8_25_io_deq_valid : _T_4937 ? _Queue16_UInt8_24_io_deq_valid : _T_4936 ? _Queue16_UInt8_23_io_deq_valid : _T_4935 ? _Queue16_UInt8_22_io_deq_valid : _T_4934 ? _Queue16_UInt8_21_io_deq_valid : _T_4933 ? _Queue16_UInt8_20_io_deq_valid : _T_4932 ? _Queue16_UInt8_19_io_deq_valid : _T_4931 ? _Queue16_UInt8_18_io_deq_valid : _T_4930 ? _Queue16_UInt8_17_io_deq_valid : _T_4929 ? _Queue16_UInt8_16_io_deq_valid : _T_4928 ? _Queue16_UInt8_15_io_deq_valid : _T_4927 ? _Queue16_UInt8_14_io_deq_valid : _T_4926 ? _Queue16_UInt8_13_io_deq_valid : _T_4925 ? _Queue16_UInt8_12_io_deq_valid : _T_4924 ? _Queue16_UInt8_11_io_deq_valid : _T_4923 ? _Queue16_UInt8_10_io_deq_valid : _T_4922 ? _Queue16_UInt8_9_io_deq_valid : _T_4921 ? _Queue16_UInt8_8_io_deq_valid : _T_4920 ? _Queue16_UInt8_7_io_deq_valid : _T_4919 ? _Queue16_UInt8_6_io_deq_valid : _T_4918 ? _Queue16_UInt8_5_io_deq_valid : _T_4917 ? _Queue16_UInt8_4_io_deq_valid : _T_4916 ? _Queue16_UInt8_3_io_deq_valid : _T_4915 ? _Queue16_UInt8_2_io_deq_valid : _T_4914 ? _Queue16_UInt8_1_io_deq_valid : _T_4913 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_19 = _remapindex_T + 7'h13; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_109 = _remapindex_T_19 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_19 = _GEN_109[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4945 = remapindex_19 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4946 = remapindex_19 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4947 = remapindex_19 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4948 = remapindex_19 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4949 = remapindex_19 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4950 = remapindex_19 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4951 = remapindex_19 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4952 = remapindex_19 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4953 = remapindex_19 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4954 = remapindex_19 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4955 = remapindex_19 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4956 = remapindex_19 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4957 = remapindex_19 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4958 = remapindex_19 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4959 = remapindex_19 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4960 = remapindex_19 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4961 = remapindex_19 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4962 = remapindex_19 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4963 = remapindex_19 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4964 = remapindex_19 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4965 = remapindex_19 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4966 = remapindex_19 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4967 = remapindex_19 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4968 = remapindex_19 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4969 = remapindex_19 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4970 = remapindex_19 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4971 = remapindex_19 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4972 = remapindex_19 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4973 = remapindex_19 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4974 = remapindex_19 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4975 = remapindex_19 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4976 = remapindex_19 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_19 = _T_4976 ? _Queue16_UInt8_31_io_deq_bits : _T_4975 ? _Queue16_UInt8_30_io_deq_bits : _T_4974 ? _Queue16_UInt8_29_io_deq_bits : _T_4973 ? _Queue16_UInt8_28_io_deq_bits : _T_4972 ? _Queue16_UInt8_27_io_deq_bits : _T_4971 ? _Queue16_UInt8_26_io_deq_bits : _T_4970 ? _Queue16_UInt8_25_io_deq_bits : _T_4969 ? _Queue16_UInt8_24_io_deq_bits : _T_4968 ? _Queue16_UInt8_23_io_deq_bits : _T_4967 ? _Queue16_UInt8_22_io_deq_bits : _T_4966 ? _Queue16_UInt8_21_io_deq_bits : _T_4965 ? _Queue16_UInt8_20_io_deq_bits : _T_4964 ? _Queue16_UInt8_19_io_deq_bits : _T_4963 ? _Queue16_UInt8_18_io_deq_bits : _T_4962 ? _Queue16_UInt8_17_io_deq_bits : _T_4961 ? _Queue16_UInt8_16_io_deq_bits : _T_4960 ? _Queue16_UInt8_15_io_deq_bits : _T_4959 ? _Queue16_UInt8_14_io_deq_bits : _T_4958 ? _Queue16_UInt8_13_io_deq_bits : _T_4957 ? _Queue16_UInt8_12_io_deq_bits : _T_4956 ? _Queue16_UInt8_11_io_deq_bits : _T_4955 ? _Queue16_UInt8_10_io_deq_bits : _T_4954 ? _Queue16_UInt8_9_io_deq_bits : _T_4953 ? _Queue16_UInt8_8_io_deq_bits : _T_4952 ? _Queue16_UInt8_7_io_deq_bits : _T_4951 ? _Queue16_UInt8_6_io_deq_bits : _T_4950 ? _Queue16_UInt8_5_io_deq_bits : _T_4949 ? _Queue16_UInt8_4_io_deq_bits : _T_4948 ? _Queue16_UInt8_3_io_deq_bits : _T_4947 ? _Queue16_UInt8_2_io_deq_bits : _T_4946 ? _Queue16_UInt8_1_io_deq_bits : _T_4945 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_19 = _T_4976 ? _Queue16_UInt8_31_io_deq_valid : _T_4975 ? _Queue16_UInt8_30_io_deq_valid : _T_4974 ? _Queue16_UInt8_29_io_deq_valid : _T_4973 ? _Queue16_UInt8_28_io_deq_valid : _T_4972 ? _Queue16_UInt8_27_io_deq_valid : _T_4971 ? _Queue16_UInt8_26_io_deq_valid : _T_4970 ? _Queue16_UInt8_25_io_deq_valid : _T_4969 ? _Queue16_UInt8_24_io_deq_valid : _T_4968 ? _Queue16_UInt8_23_io_deq_valid : _T_4967 ? _Queue16_UInt8_22_io_deq_valid : _T_4966 ? _Queue16_UInt8_21_io_deq_valid : _T_4965 ? _Queue16_UInt8_20_io_deq_valid : _T_4964 ? _Queue16_UInt8_19_io_deq_valid : _T_4963 ? _Queue16_UInt8_18_io_deq_valid : _T_4962 ? _Queue16_UInt8_17_io_deq_valid : _T_4961 ? _Queue16_UInt8_16_io_deq_valid : _T_4960 ? _Queue16_UInt8_15_io_deq_valid : _T_4959 ? _Queue16_UInt8_14_io_deq_valid : _T_4958 ? _Queue16_UInt8_13_io_deq_valid : _T_4957 ? _Queue16_UInt8_12_io_deq_valid : _T_4956 ? _Queue16_UInt8_11_io_deq_valid : _T_4955 ? _Queue16_UInt8_10_io_deq_valid : _T_4954 ? _Queue16_UInt8_9_io_deq_valid : _T_4953 ? _Queue16_UInt8_8_io_deq_valid : _T_4952 ? _Queue16_UInt8_7_io_deq_valid : _T_4951 ? _Queue16_UInt8_6_io_deq_valid : _T_4950 ? _Queue16_UInt8_5_io_deq_valid : _T_4949 ? _Queue16_UInt8_4_io_deq_valid : _T_4948 ? _Queue16_UInt8_3_io_deq_valid : _T_4947 ? _Queue16_UInt8_2_io_deq_valid : _T_4946 ? _Queue16_UInt8_1_io_deq_valid : _T_4945 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_20 = _remapindex_T + 7'h14; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_110 = _remapindex_T_20 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_20 = _GEN_110[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4977 = remapindex_20 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4978 = remapindex_20 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4979 = remapindex_20 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4980 = remapindex_20 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4981 = remapindex_20 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4982 = remapindex_20 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4983 = remapindex_20 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4984 = remapindex_20 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4985 = remapindex_20 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4986 = remapindex_20 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4987 = remapindex_20 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4988 = remapindex_20 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4989 = remapindex_20 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4990 = remapindex_20 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4991 = remapindex_20 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4992 = remapindex_20 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4993 = remapindex_20 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4994 = remapindex_20 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4995 = remapindex_20 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4996 = remapindex_20 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4997 = remapindex_20 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4998 = remapindex_20 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4999 = remapindex_20 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5000 = remapindex_20 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5001 = remapindex_20 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5002 = remapindex_20 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5003 = remapindex_20 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5004 = remapindex_20 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5005 = remapindex_20 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5006 = remapindex_20 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5007 = remapindex_20 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5008 = remapindex_20 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_20 = _T_5008 ? _Queue16_UInt8_31_io_deq_bits : _T_5007 ? _Queue16_UInt8_30_io_deq_bits : _T_5006 ? _Queue16_UInt8_29_io_deq_bits : _T_5005 ? _Queue16_UInt8_28_io_deq_bits : _T_5004 ? _Queue16_UInt8_27_io_deq_bits : _T_5003 ? _Queue16_UInt8_26_io_deq_bits : _T_5002 ? _Queue16_UInt8_25_io_deq_bits : _T_5001 ? _Queue16_UInt8_24_io_deq_bits : _T_5000 ? _Queue16_UInt8_23_io_deq_bits : _T_4999 ? _Queue16_UInt8_22_io_deq_bits : _T_4998 ? _Queue16_UInt8_21_io_deq_bits : _T_4997 ? _Queue16_UInt8_20_io_deq_bits : _T_4996 ? _Queue16_UInt8_19_io_deq_bits : _T_4995 ? _Queue16_UInt8_18_io_deq_bits : _T_4994 ? _Queue16_UInt8_17_io_deq_bits : _T_4993 ? _Queue16_UInt8_16_io_deq_bits : _T_4992 ? _Queue16_UInt8_15_io_deq_bits : _T_4991 ? _Queue16_UInt8_14_io_deq_bits : _T_4990 ? _Queue16_UInt8_13_io_deq_bits : _T_4989 ? _Queue16_UInt8_12_io_deq_bits : _T_4988 ? _Queue16_UInt8_11_io_deq_bits : _T_4987 ? _Queue16_UInt8_10_io_deq_bits : _T_4986 ? _Queue16_UInt8_9_io_deq_bits : _T_4985 ? _Queue16_UInt8_8_io_deq_bits : _T_4984 ? _Queue16_UInt8_7_io_deq_bits : _T_4983 ? _Queue16_UInt8_6_io_deq_bits : _T_4982 ? _Queue16_UInt8_5_io_deq_bits : _T_4981 ? _Queue16_UInt8_4_io_deq_bits : _T_4980 ? _Queue16_UInt8_3_io_deq_bits : _T_4979 ? _Queue16_UInt8_2_io_deq_bits : _T_4978 ? _Queue16_UInt8_1_io_deq_bits : _T_4977 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_20 = _T_5008 ? _Queue16_UInt8_31_io_deq_valid : _T_5007 ? _Queue16_UInt8_30_io_deq_valid : _T_5006 ? _Queue16_UInt8_29_io_deq_valid : _T_5005 ? _Queue16_UInt8_28_io_deq_valid : _T_5004 ? _Queue16_UInt8_27_io_deq_valid : _T_5003 ? _Queue16_UInt8_26_io_deq_valid : _T_5002 ? _Queue16_UInt8_25_io_deq_valid : _T_5001 ? _Queue16_UInt8_24_io_deq_valid : _T_5000 ? _Queue16_UInt8_23_io_deq_valid : _T_4999 ? _Queue16_UInt8_22_io_deq_valid : _T_4998 ? _Queue16_UInt8_21_io_deq_valid : _T_4997 ? _Queue16_UInt8_20_io_deq_valid : _T_4996 ? _Queue16_UInt8_19_io_deq_valid : _T_4995 ? _Queue16_UInt8_18_io_deq_valid : _T_4994 ? _Queue16_UInt8_17_io_deq_valid : _T_4993 ? _Queue16_UInt8_16_io_deq_valid : _T_4992 ? _Queue16_UInt8_15_io_deq_valid : _T_4991 ? _Queue16_UInt8_14_io_deq_valid : _T_4990 ? _Queue16_UInt8_13_io_deq_valid : _T_4989 ? _Queue16_UInt8_12_io_deq_valid : _T_4988 ? _Queue16_UInt8_11_io_deq_valid : _T_4987 ? _Queue16_UInt8_10_io_deq_valid : _T_4986 ? _Queue16_UInt8_9_io_deq_valid : _T_4985 ? _Queue16_UInt8_8_io_deq_valid : _T_4984 ? _Queue16_UInt8_7_io_deq_valid : _T_4983 ? _Queue16_UInt8_6_io_deq_valid : _T_4982 ? _Queue16_UInt8_5_io_deq_valid : _T_4981 ? _Queue16_UInt8_4_io_deq_valid : _T_4980 ? _Queue16_UInt8_3_io_deq_valid : _T_4979 ? _Queue16_UInt8_2_io_deq_valid : _T_4978 ? _Queue16_UInt8_1_io_deq_valid : _T_4977 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_21 = _remapindex_T + 7'h15; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_111 = _remapindex_T_21 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_21 = _GEN_111[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5009 = remapindex_21 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5010 = remapindex_21 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5011 = remapindex_21 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5012 = remapindex_21 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5013 = remapindex_21 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5014 = remapindex_21 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5015 = remapindex_21 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5016 = remapindex_21 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5017 = remapindex_21 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5018 = remapindex_21 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5019 = remapindex_21 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5020 = remapindex_21 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5021 = remapindex_21 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5022 = remapindex_21 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5023 = remapindex_21 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5024 = remapindex_21 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5025 = remapindex_21 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5026 = remapindex_21 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5027 = remapindex_21 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5028 = remapindex_21 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5029 = remapindex_21 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5030 = remapindex_21 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5031 = remapindex_21 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5032 = remapindex_21 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5033 = remapindex_21 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5034 = remapindex_21 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5035 = remapindex_21 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5036 = remapindex_21 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5037 = remapindex_21 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5038 = remapindex_21 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5039 = remapindex_21 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5040 = remapindex_21 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_21 = _T_5040 ? _Queue16_UInt8_31_io_deq_bits : _T_5039 ? _Queue16_UInt8_30_io_deq_bits : _T_5038 ? _Queue16_UInt8_29_io_deq_bits : _T_5037 ? _Queue16_UInt8_28_io_deq_bits : _T_5036 ? _Queue16_UInt8_27_io_deq_bits : _T_5035 ? _Queue16_UInt8_26_io_deq_bits : _T_5034 ? _Queue16_UInt8_25_io_deq_bits : _T_5033 ? _Queue16_UInt8_24_io_deq_bits : _T_5032 ? _Queue16_UInt8_23_io_deq_bits : _T_5031 ? _Queue16_UInt8_22_io_deq_bits : _T_5030 ? _Queue16_UInt8_21_io_deq_bits : _T_5029 ? _Queue16_UInt8_20_io_deq_bits : _T_5028 ? _Queue16_UInt8_19_io_deq_bits : _T_5027 ? _Queue16_UInt8_18_io_deq_bits : _T_5026 ? _Queue16_UInt8_17_io_deq_bits : _T_5025 ? _Queue16_UInt8_16_io_deq_bits : _T_5024 ? _Queue16_UInt8_15_io_deq_bits : _T_5023 ? _Queue16_UInt8_14_io_deq_bits : _T_5022 ? _Queue16_UInt8_13_io_deq_bits : _T_5021 ? _Queue16_UInt8_12_io_deq_bits : _T_5020 ? _Queue16_UInt8_11_io_deq_bits : _T_5019 ? _Queue16_UInt8_10_io_deq_bits : _T_5018 ? _Queue16_UInt8_9_io_deq_bits : _T_5017 ? _Queue16_UInt8_8_io_deq_bits : _T_5016 ? _Queue16_UInt8_7_io_deq_bits : _T_5015 ? _Queue16_UInt8_6_io_deq_bits : _T_5014 ? _Queue16_UInt8_5_io_deq_bits : _T_5013 ? _Queue16_UInt8_4_io_deq_bits : _T_5012 ? _Queue16_UInt8_3_io_deq_bits : _T_5011 ? _Queue16_UInt8_2_io_deq_bits : _T_5010 ? _Queue16_UInt8_1_io_deq_bits : _T_5009 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_21 = _T_5040 ? _Queue16_UInt8_31_io_deq_valid : _T_5039 ? _Queue16_UInt8_30_io_deq_valid : _T_5038 ? _Queue16_UInt8_29_io_deq_valid : _T_5037 ? _Queue16_UInt8_28_io_deq_valid : _T_5036 ? _Queue16_UInt8_27_io_deq_valid : _T_5035 ? _Queue16_UInt8_26_io_deq_valid : _T_5034 ? _Queue16_UInt8_25_io_deq_valid : _T_5033 ? _Queue16_UInt8_24_io_deq_valid : _T_5032 ? _Queue16_UInt8_23_io_deq_valid : _T_5031 ? _Queue16_UInt8_22_io_deq_valid : _T_5030 ? _Queue16_UInt8_21_io_deq_valid : _T_5029 ? _Queue16_UInt8_20_io_deq_valid : _T_5028 ? _Queue16_UInt8_19_io_deq_valid : _T_5027 ? _Queue16_UInt8_18_io_deq_valid : _T_5026 ? _Queue16_UInt8_17_io_deq_valid : _T_5025 ? _Queue16_UInt8_16_io_deq_valid : _T_5024 ? _Queue16_UInt8_15_io_deq_valid : _T_5023 ? _Queue16_UInt8_14_io_deq_valid : _T_5022 ? _Queue16_UInt8_13_io_deq_valid : _T_5021 ? _Queue16_UInt8_12_io_deq_valid : _T_5020 ? _Queue16_UInt8_11_io_deq_valid : _T_5019 ? _Queue16_UInt8_10_io_deq_valid : _T_5018 ? _Queue16_UInt8_9_io_deq_valid : _T_5017 ? _Queue16_UInt8_8_io_deq_valid : _T_5016 ? _Queue16_UInt8_7_io_deq_valid : _T_5015 ? _Queue16_UInt8_6_io_deq_valid : _T_5014 ? _Queue16_UInt8_5_io_deq_valid : _T_5013 ? _Queue16_UInt8_4_io_deq_valid : _T_5012 ? _Queue16_UInt8_3_io_deq_valid : _T_5011 ? _Queue16_UInt8_2_io_deq_valid : _T_5010 ? _Queue16_UInt8_1_io_deq_valid : _T_5009 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_22 = _remapindex_T + 7'h16; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_112 = _remapindex_T_22 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_22 = _GEN_112[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5041 = remapindex_22 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5042 = remapindex_22 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5043 = remapindex_22 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5044 = remapindex_22 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5045 = remapindex_22 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5046 = remapindex_22 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5047 = remapindex_22 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5048 = remapindex_22 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5049 = remapindex_22 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5050 = remapindex_22 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5051 = remapindex_22 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5052 = remapindex_22 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5053 = remapindex_22 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5054 = remapindex_22 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5055 = remapindex_22 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5056 = remapindex_22 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5057 = remapindex_22 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5058 = remapindex_22 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5059 = remapindex_22 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5060 = remapindex_22 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5061 = remapindex_22 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5062 = remapindex_22 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5063 = remapindex_22 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5064 = remapindex_22 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5065 = remapindex_22 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5066 = remapindex_22 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5067 = remapindex_22 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5068 = remapindex_22 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5069 = remapindex_22 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5070 = remapindex_22 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5071 = remapindex_22 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5072 = remapindex_22 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_22 = _T_5072 ? _Queue16_UInt8_31_io_deq_bits : _T_5071 ? _Queue16_UInt8_30_io_deq_bits : _T_5070 ? _Queue16_UInt8_29_io_deq_bits : _T_5069 ? _Queue16_UInt8_28_io_deq_bits : _T_5068 ? _Queue16_UInt8_27_io_deq_bits : _T_5067 ? _Queue16_UInt8_26_io_deq_bits : _T_5066 ? _Queue16_UInt8_25_io_deq_bits : _T_5065 ? _Queue16_UInt8_24_io_deq_bits : _T_5064 ? _Queue16_UInt8_23_io_deq_bits : _T_5063 ? _Queue16_UInt8_22_io_deq_bits : _T_5062 ? _Queue16_UInt8_21_io_deq_bits : _T_5061 ? _Queue16_UInt8_20_io_deq_bits : _T_5060 ? _Queue16_UInt8_19_io_deq_bits : _T_5059 ? _Queue16_UInt8_18_io_deq_bits : _T_5058 ? _Queue16_UInt8_17_io_deq_bits : _T_5057 ? _Queue16_UInt8_16_io_deq_bits : _T_5056 ? _Queue16_UInt8_15_io_deq_bits : _T_5055 ? _Queue16_UInt8_14_io_deq_bits : _T_5054 ? _Queue16_UInt8_13_io_deq_bits : _T_5053 ? _Queue16_UInt8_12_io_deq_bits : _T_5052 ? _Queue16_UInt8_11_io_deq_bits : _T_5051 ? _Queue16_UInt8_10_io_deq_bits : _T_5050 ? _Queue16_UInt8_9_io_deq_bits : _T_5049 ? _Queue16_UInt8_8_io_deq_bits : _T_5048 ? _Queue16_UInt8_7_io_deq_bits : _T_5047 ? _Queue16_UInt8_6_io_deq_bits : _T_5046 ? _Queue16_UInt8_5_io_deq_bits : _T_5045 ? _Queue16_UInt8_4_io_deq_bits : _T_5044 ? _Queue16_UInt8_3_io_deq_bits : _T_5043 ? _Queue16_UInt8_2_io_deq_bits : _T_5042 ? _Queue16_UInt8_1_io_deq_bits : _T_5041 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_22 = _T_5072 ? _Queue16_UInt8_31_io_deq_valid : _T_5071 ? _Queue16_UInt8_30_io_deq_valid : _T_5070 ? _Queue16_UInt8_29_io_deq_valid : _T_5069 ? _Queue16_UInt8_28_io_deq_valid : _T_5068 ? _Queue16_UInt8_27_io_deq_valid : _T_5067 ? _Queue16_UInt8_26_io_deq_valid : _T_5066 ? _Queue16_UInt8_25_io_deq_valid : _T_5065 ? _Queue16_UInt8_24_io_deq_valid : _T_5064 ? _Queue16_UInt8_23_io_deq_valid : _T_5063 ? _Queue16_UInt8_22_io_deq_valid : _T_5062 ? _Queue16_UInt8_21_io_deq_valid : _T_5061 ? _Queue16_UInt8_20_io_deq_valid : _T_5060 ? _Queue16_UInt8_19_io_deq_valid : _T_5059 ? _Queue16_UInt8_18_io_deq_valid : _T_5058 ? _Queue16_UInt8_17_io_deq_valid : _T_5057 ? _Queue16_UInt8_16_io_deq_valid : _T_5056 ? _Queue16_UInt8_15_io_deq_valid : _T_5055 ? _Queue16_UInt8_14_io_deq_valid : _T_5054 ? _Queue16_UInt8_13_io_deq_valid : _T_5053 ? _Queue16_UInt8_12_io_deq_valid : _T_5052 ? _Queue16_UInt8_11_io_deq_valid : _T_5051 ? _Queue16_UInt8_10_io_deq_valid : _T_5050 ? _Queue16_UInt8_9_io_deq_valid : _T_5049 ? _Queue16_UInt8_8_io_deq_valid : _T_5048 ? _Queue16_UInt8_7_io_deq_valid : _T_5047 ? _Queue16_UInt8_6_io_deq_valid : _T_5046 ? _Queue16_UInt8_5_io_deq_valid : _T_5045 ? _Queue16_UInt8_4_io_deq_valid : _T_5044 ? _Queue16_UInt8_3_io_deq_valid : _T_5043 ? _Queue16_UInt8_2_io_deq_valid : _T_5042 ? _Queue16_UInt8_1_io_deq_valid : _T_5041 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_23 = _remapindex_T + 7'h17; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_113 = _remapindex_T_23 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_23 = _GEN_113[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5073 = remapindex_23 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5074 = remapindex_23 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5075 = remapindex_23 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5076 = remapindex_23 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5077 = remapindex_23 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5078 = remapindex_23 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5079 = remapindex_23 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5080 = remapindex_23 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5081 = remapindex_23 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5082 = remapindex_23 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5083 = remapindex_23 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5084 = remapindex_23 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5085 = remapindex_23 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5086 = remapindex_23 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5087 = remapindex_23 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5088 = remapindex_23 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5089 = remapindex_23 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5090 = remapindex_23 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5091 = remapindex_23 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5092 = remapindex_23 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5093 = remapindex_23 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5094 = remapindex_23 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5095 = remapindex_23 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5096 = remapindex_23 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5097 = remapindex_23 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5098 = remapindex_23 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5099 = remapindex_23 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5100 = remapindex_23 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5101 = remapindex_23 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5102 = remapindex_23 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5103 = remapindex_23 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5104 = remapindex_23 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_23 = _T_5104 ? _Queue16_UInt8_31_io_deq_bits : _T_5103 ? _Queue16_UInt8_30_io_deq_bits : _T_5102 ? _Queue16_UInt8_29_io_deq_bits : _T_5101 ? _Queue16_UInt8_28_io_deq_bits : _T_5100 ? _Queue16_UInt8_27_io_deq_bits : _T_5099 ? _Queue16_UInt8_26_io_deq_bits : _T_5098 ? _Queue16_UInt8_25_io_deq_bits : _T_5097 ? _Queue16_UInt8_24_io_deq_bits : _T_5096 ? _Queue16_UInt8_23_io_deq_bits : _T_5095 ? _Queue16_UInt8_22_io_deq_bits : _T_5094 ? _Queue16_UInt8_21_io_deq_bits : _T_5093 ? _Queue16_UInt8_20_io_deq_bits : _T_5092 ? _Queue16_UInt8_19_io_deq_bits : _T_5091 ? _Queue16_UInt8_18_io_deq_bits : _T_5090 ? _Queue16_UInt8_17_io_deq_bits : _T_5089 ? _Queue16_UInt8_16_io_deq_bits : _T_5088 ? _Queue16_UInt8_15_io_deq_bits : _T_5087 ? _Queue16_UInt8_14_io_deq_bits : _T_5086 ? _Queue16_UInt8_13_io_deq_bits : _T_5085 ? _Queue16_UInt8_12_io_deq_bits : _T_5084 ? _Queue16_UInt8_11_io_deq_bits : _T_5083 ? _Queue16_UInt8_10_io_deq_bits : _T_5082 ? _Queue16_UInt8_9_io_deq_bits : _T_5081 ? _Queue16_UInt8_8_io_deq_bits : _T_5080 ? _Queue16_UInt8_7_io_deq_bits : _T_5079 ? _Queue16_UInt8_6_io_deq_bits : _T_5078 ? _Queue16_UInt8_5_io_deq_bits : _T_5077 ? _Queue16_UInt8_4_io_deq_bits : _T_5076 ? _Queue16_UInt8_3_io_deq_bits : _T_5075 ? _Queue16_UInt8_2_io_deq_bits : _T_5074 ? _Queue16_UInt8_1_io_deq_bits : _T_5073 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_23 = _T_5104 ? _Queue16_UInt8_31_io_deq_valid : _T_5103 ? _Queue16_UInt8_30_io_deq_valid : _T_5102 ? _Queue16_UInt8_29_io_deq_valid : _T_5101 ? _Queue16_UInt8_28_io_deq_valid : _T_5100 ? _Queue16_UInt8_27_io_deq_valid : _T_5099 ? _Queue16_UInt8_26_io_deq_valid : _T_5098 ? _Queue16_UInt8_25_io_deq_valid : _T_5097 ? _Queue16_UInt8_24_io_deq_valid : _T_5096 ? _Queue16_UInt8_23_io_deq_valid : _T_5095 ? _Queue16_UInt8_22_io_deq_valid : _T_5094 ? _Queue16_UInt8_21_io_deq_valid : _T_5093 ? _Queue16_UInt8_20_io_deq_valid : _T_5092 ? _Queue16_UInt8_19_io_deq_valid : _T_5091 ? _Queue16_UInt8_18_io_deq_valid : _T_5090 ? _Queue16_UInt8_17_io_deq_valid : _T_5089 ? _Queue16_UInt8_16_io_deq_valid : _T_5088 ? _Queue16_UInt8_15_io_deq_valid : _T_5087 ? _Queue16_UInt8_14_io_deq_valid : _T_5086 ? _Queue16_UInt8_13_io_deq_valid : _T_5085 ? _Queue16_UInt8_12_io_deq_valid : _T_5084 ? _Queue16_UInt8_11_io_deq_valid : _T_5083 ? _Queue16_UInt8_10_io_deq_valid : _T_5082 ? _Queue16_UInt8_9_io_deq_valid : _T_5081 ? _Queue16_UInt8_8_io_deq_valid : _T_5080 ? _Queue16_UInt8_7_io_deq_valid : _T_5079 ? _Queue16_UInt8_6_io_deq_valid : _T_5078 ? _Queue16_UInt8_5_io_deq_valid : _T_5077 ? _Queue16_UInt8_4_io_deq_valid : _T_5076 ? _Queue16_UInt8_3_io_deq_valid : _T_5075 ? _Queue16_UInt8_2_io_deq_valid : _T_5074 ? _Queue16_UInt8_1_io_deq_valid : _T_5073 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_24 = _remapindex_T + 7'h18; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_114 = _remapindex_T_24 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_24 = _GEN_114[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5105 = remapindex_24 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5106 = remapindex_24 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5107 = remapindex_24 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5108 = remapindex_24 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5109 = remapindex_24 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5110 = remapindex_24 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5111 = remapindex_24 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5112 = remapindex_24 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5113 = remapindex_24 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5114 = remapindex_24 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5115 = remapindex_24 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5116 = remapindex_24 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5117 = remapindex_24 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5118 = remapindex_24 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5119 = remapindex_24 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5120 = remapindex_24 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5121 = remapindex_24 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5122 = remapindex_24 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5123 = remapindex_24 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5124 = remapindex_24 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5125 = remapindex_24 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5126 = remapindex_24 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5127 = remapindex_24 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5128 = remapindex_24 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5129 = remapindex_24 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5130 = remapindex_24 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5131 = remapindex_24 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5132 = remapindex_24 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5133 = remapindex_24 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5134 = remapindex_24 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5135 = remapindex_24 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5136 = remapindex_24 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_24 = _T_5136 ? _Queue16_UInt8_31_io_deq_bits : _T_5135 ? _Queue16_UInt8_30_io_deq_bits : _T_5134 ? _Queue16_UInt8_29_io_deq_bits : _T_5133 ? _Queue16_UInt8_28_io_deq_bits : _T_5132 ? _Queue16_UInt8_27_io_deq_bits : _T_5131 ? _Queue16_UInt8_26_io_deq_bits : _T_5130 ? _Queue16_UInt8_25_io_deq_bits : _T_5129 ? _Queue16_UInt8_24_io_deq_bits : _T_5128 ? _Queue16_UInt8_23_io_deq_bits : _T_5127 ? _Queue16_UInt8_22_io_deq_bits : _T_5126 ? _Queue16_UInt8_21_io_deq_bits : _T_5125 ? _Queue16_UInt8_20_io_deq_bits : _T_5124 ? _Queue16_UInt8_19_io_deq_bits : _T_5123 ? _Queue16_UInt8_18_io_deq_bits : _T_5122 ? _Queue16_UInt8_17_io_deq_bits : _T_5121 ? _Queue16_UInt8_16_io_deq_bits : _T_5120 ? _Queue16_UInt8_15_io_deq_bits : _T_5119 ? _Queue16_UInt8_14_io_deq_bits : _T_5118 ? _Queue16_UInt8_13_io_deq_bits : _T_5117 ? _Queue16_UInt8_12_io_deq_bits : _T_5116 ? _Queue16_UInt8_11_io_deq_bits : _T_5115 ? _Queue16_UInt8_10_io_deq_bits : _T_5114 ? _Queue16_UInt8_9_io_deq_bits : _T_5113 ? _Queue16_UInt8_8_io_deq_bits : _T_5112 ? _Queue16_UInt8_7_io_deq_bits : _T_5111 ? _Queue16_UInt8_6_io_deq_bits : _T_5110 ? _Queue16_UInt8_5_io_deq_bits : _T_5109 ? _Queue16_UInt8_4_io_deq_bits : _T_5108 ? _Queue16_UInt8_3_io_deq_bits : _T_5107 ? _Queue16_UInt8_2_io_deq_bits : _T_5106 ? _Queue16_UInt8_1_io_deq_bits : _T_5105 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_24 = _T_5136 ? _Queue16_UInt8_31_io_deq_valid : _T_5135 ? _Queue16_UInt8_30_io_deq_valid : _T_5134 ? _Queue16_UInt8_29_io_deq_valid : _T_5133 ? _Queue16_UInt8_28_io_deq_valid : _T_5132 ? _Queue16_UInt8_27_io_deq_valid : _T_5131 ? _Queue16_UInt8_26_io_deq_valid : _T_5130 ? _Queue16_UInt8_25_io_deq_valid : _T_5129 ? _Queue16_UInt8_24_io_deq_valid : _T_5128 ? _Queue16_UInt8_23_io_deq_valid : _T_5127 ? _Queue16_UInt8_22_io_deq_valid : _T_5126 ? _Queue16_UInt8_21_io_deq_valid : _T_5125 ? _Queue16_UInt8_20_io_deq_valid : _T_5124 ? _Queue16_UInt8_19_io_deq_valid : _T_5123 ? _Queue16_UInt8_18_io_deq_valid : _T_5122 ? _Queue16_UInt8_17_io_deq_valid : _T_5121 ? _Queue16_UInt8_16_io_deq_valid : _T_5120 ? _Queue16_UInt8_15_io_deq_valid : _T_5119 ? _Queue16_UInt8_14_io_deq_valid : _T_5118 ? _Queue16_UInt8_13_io_deq_valid : _T_5117 ? _Queue16_UInt8_12_io_deq_valid : _T_5116 ? _Queue16_UInt8_11_io_deq_valid : _T_5115 ? _Queue16_UInt8_10_io_deq_valid : _T_5114 ? _Queue16_UInt8_9_io_deq_valid : _T_5113 ? _Queue16_UInt8_8_io_deq_valid : _T_5112 ? _Queue16_UInt8_7_io_deq_valid : _T_5111 ? _Queue16_UInt8_6_io_deq_valid : _T_5110 ? _Queue16_UInt8_5_io_deq_valid : _T_5109 ? _Queue16_UInt8_4_io_deq_valid : _T_5108 ? _Queue16_UInt8_3_io_deq_valid : _T_5107 ? _Queue16_UInt8_2_io_deq_valid : _T_5106 ? _Queue16_UInt8_1_io_deq_valid : _T_5105 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_25 = _remapindex_T + 7'h19; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_115 = _remapindex_T_25 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_25 = _GEN_115[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5137 = remapindex_25 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5138 = remapindex_25 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5139 = remapindex_25 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5140 = remapindex_25 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5141 = remapindex_25 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5142 = remapindex_25 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5143 = remapindex_25 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5144 = remapindex_25 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5145 = remapindex_25 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5146 = remapindex_25 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5147 = remapindex_25 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5148 = remapindex_25 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5149 = remapindex_25 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5150 = remapindex_25 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5151 = remapindex_25 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5152 = remapindex_25 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5153 = remapindex_25 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5154 = remapindex_25 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5155 = remapindex_25 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5156 = remapindex_25 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5157 = remapindex_25 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5158 = remapindex_25 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5159 = remapindex_25 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5160 = remapindex_25 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5161 = remapindex_25 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5162 = remapindex_25 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5163 = remapindex_25 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5164 = remapindex_25 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5165 = remapindex_25 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5166 = remapindex_25 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5167 = remapindex_25 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5168 = remapindex_25 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_25 = _T_5168 ? _Queue16_UInt8_31_io_deq_bits : _T_5167 ? _Queue16_UInt8_30_io_deq_bits : _T_5166 ? _Queue16_UInt8_29_io_deq_bits : _T_5165 ? _Queue16_UInt8_28_io_deq_bits : _T_5164 ? _Queue16_UInt8_27_io_deq_bits : _T_5163 ? _Queue16_UInt8_26_io_deq_bits : _T_5162 ? _Queue16_UInt8_25_io_deq_bits : _T_5161 ? _Queue16_UInt8_24_io_deq_bits : _T_5160 ? _Queue16_UInt8_23_io_deq_bits : _T_5159 ? _Queue16_UInt8_22_io_deq_bits : _T_5158 ? _Queue16_UInt8_21_io_deq_bits : _T_5157 ? _Queue16_UInt8_20_io_deq_bits : _T_5156 ? _Queue16_UInt8_19_io_deq_bits : _T_5155 ? _Queue16_UInt8_18_io_deq_bits : _T_5154 ? _Queue16_UInt8_17_io_deq_bits : _T_5153 ? _Queue16_UInt8_16_io_deq_bits : _T_5152 ? _Queue16_UInt8_15_io_deq_bits : _T_5151 ? _Queue16_UInt8_14_io_deq_bits : _T_5150 ? _Queue16_UInt8_13_io_deq_bits : _T_5149 ? _Queue16_UInt8_12_io_deq_bits : _T_5148 ? _Queue16_UInt8_11_io_deq_bits : _T_5147 ? _Queue16_UInt8_10_io_deq_bits : _T_5146 ? _Queue16_UInt8_9_io_deq_bits : _T_5145 ? _Queue16_UInt8_8_io_deq_bits : _T_5144 ? _Queue16_UInt8_7_io_deq_bits : _T_5143 ? _Queue16_UInt8_6_io_deq_bits : _T_5142 ? _Queue16_UInt8_5_io_deq_bits : _T_5141 ? _Queue16_UInt8_4_io_deq_bits : _T_5140 ? _Queue16_UInt8_3_io_deq_bits : _T_5139 ? _Queue16_UInt8_2_io_deq_bits : _T_5138 ? _Queue16_UInt8_1_io_deq_bits : _T_5137 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_25 = _T_5168 ? _Queue16_UInt8_31_io_deq_valid : _T_5167 ? _Queue16_UInt8_30_io_deq_valid : _T_5166 ? _Queue16_UInt8_29_io_deq_valid : _T_5165 ? _Queue16_UInt8_28_io_deq_valid : _T_5164 ? _Queue16_UInt8_27_io_deq_valid : _T_5163 ? _Queue16_UInt8_26_io_deq_valid : _T_5162 ? _Queue16_UInt8_25_io_deq_valid : _T_5161 ? _Queue16_UInt8_24_io_deq_valid : _T_5160 ? _Queue16_UInt8_23_io_deq_valid : _T_5159 ? _Queue16_UInt8_22_io_deq_valid : _T_5158 ? _Queue16_UInt8_21_io_deq_valid : _T_5157 ? _Queue16_UInt8_20_io_deq_valid : _T_5156 ? _Queue16_UInt8_19_io_deq_valid : _T_5155 ? _Queue16_UInt8_18_io_deq_valid : _T_5154 ? _Queue16_UInt8_17_io_deq_valid : _T_5153 ? _Queue16_UInt8_16_io_deq_valid : _T_5152 ? _Queue16_UInt8_15_io_deq_valid : _T_5151 ? _Queue16_UInt8_14_io_deq_valid : _T_5150 ? _Queue16_UInt8_13_io_deq_valid : _T_5149 ? _Queue16_UInt8_12_io_deq_valid : _T_5148 ? _Queue16_UInt8_11_io_deq_valid : _T_5147 ? _Queue16_UInt8_10_io_deq_valid : _T_5146 ? _Queue16_UInt8_9_io_deq_valid : _T_5145 ? _Queue16_UInt8_8_io_deq_valid : _T_5144 ? _Queue16_UInt8_7_io_deq_valid : _T_5143 ? _Queue16_UInt8_6_io_deq_valid : _T_5142 ? _Queue16_UInt8_5_io_deq_valid : _T_5141 ? _Queue16_UInt8_4_io_deq_valid : _T_5140 ? _Queue16_UInt8_3_io_deq_valid : _T_5139 ? _Queue16_UInt8_2_io_deq_valid : _T_5138 ? _Queue16_UInt8_1_io_deq_valid : _T_5137 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_26 = _remapindex_T + 7'h1A; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_116 = _remapindex_T_26 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_26 = _GEN_116[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5169 = remapindex_26 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5170 = remapindex_26 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5171 = remapindex_26 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5172 = remapindex_26 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5173 = remapindex_26 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5174 = remapindex_26 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5175 = remapindex_26 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5176 = remapindex_26 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5177 = remapindex_26 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5178 = remapindex_26 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5179 = remapindex_26 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5180 = remapindex_26 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5181 = remapindex_26 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5182 = remapindex_26 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5183 = remapindex_26 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5184 = remapindex_26 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5185 = remapindex_26 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5186 = remapindex_26 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5187 = remapindex_26 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5188 = remapindex_26 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5189 = remapindex_26 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5190 = remapindex_26 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5191 = remapindex_26 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5192 = remapindex_26 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5193 = remapindex_26 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5194 = remapindex_26 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5195 = remapindex_26 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5196 = remapindex_26 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5197 = remapindex_26 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5198 = remapindex_26 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5199 = remapindex_26 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5200 = remapindex_26 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_26 = _T_5200 ? _Queue16_UInt8_31_io_deq_bits : _T_5199 ? _Queue16_UInt8_30_io_deq_bits : _T_5198 ? _Queue16_UInt8_29_io_deq_bits : _T_5197 ? _Queue16_UInt8_28_io_deq_bits : _T_5196 ? _Queue16_UInt8_27_io_deq_bits : _T_5195 ? _Queue16_UInt8_26_io_deq_bits : _T_5194 ? _Queue16_UInt8_25_io_deq_bits : _T_5193 ? _Queue16_UInt8_24_io_deq_bits : _T_5192 ? _Queue16_UInt8_23_io_deq_bits : _T_5191 ? _Queue16_UInt8_22_io_deq_bits : _T_5190 ? _Queue16_UInt8_21_io_deq_bits : _T_5189 ? _Queue16_UInt8_20_io_deq_bits : _T_5188 ? _Queue16_UInt8_19_io_deq_bits : _T_5187 ? _Queue16_UInt8_18_io_deq_bits : _T_5186 ? _Queue16_UInt8_17_io_deq_bits : _T_5185 ? _Queue16_UInt8_16_io_deq_bits : _T_5184 ? _Queue16_UInt8_15_io_deq_bits : _T_5183 ? _Queue16_UInt8_14_io_deq_bits : _T_5182 ? _Queue16_UInt8_13_io_deq_bits : _T_5181 ? _Queue16_UInt8_12_io_deq_bits : _T_5180 ? _Queue16_UInt8_11_io_deq_bits : _T_5179 ? _Queue16_UInt8_10_io_deq_bits : _T_5178 ? _Queue16_UInt8_9_io_deq_bits : _T_5177 ? _Queue16_UInt8_8_io_deq_bits : _T_5176 ? _Queue16_UInt8_7_io_deq_bits : _T_5175 ? _Queue16_UInt8_6_io_deq_bits : _T_5174 ? _Queue16_UInt8_5_io_deq_bits : _T_5173 ? _Queue16_UInt8_4_io_deq_bits : _T_5172 ? _Queue16_UInt8_3_io_deq_bits : _T_5171 ? _Queue16_UInt8_2_io_deq_bits : _T_5170 ? _Queue16_UInt8_1_io_deq_bits : _T_5169 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_26 = _T_5200 ? _Queue16_UInt8_31_io_deq_valid : _T_5199 ? _Queue16_UInt8_30_io_deq_valid : _T_5198 ? _Queue16_UInt8_29_io_deq_valid : _T_5197 ? _Queue16_UInt8_28_io_deq_valid : _T_5196 ? _Queue16_UInt8_27_io_deq_valid : _T_5195 ? _Queue16_UInt8_26_io_deq_valid : _T_5194 ? _Queue16_UInt8_25_io_deq_valid : _T_5193 ? _Queue16_UInt8_24_io_deq_valid : _T_5192 ? _Queue16_UInt8_23_io_deq_valid : _T_5191 ? _Queue16_UInt8_22_io_deq_valid : _T_5190 ? _Queue16_UInt8_21_io_deq_valid : _T_5189 ? _Queue16_UInt8_20_io_deq_valid : _T_5188 ? _Queue16_UInt8_19_io_deq_valid : _T_5187 ? _Queue16_UInt8_18_io_deq_valid : _T_5186 ? _Queue16_UInt8_17_io_deq_valid : _T_5185 ? _Queue16_UInt8_16_io_deq_valid : _T_5184 ? _Queue16_UInt8_15_io_deq_valid : _T_5183 ? _Queue16_UInt8_14_io_deq_valid : _T_5182 ? _Queue16_UInt8_13_io_deq_valid : _T_5181 ? _Queue16_UInt8_12_io_deq_valid : _T_5180 ? _Queue16_UInt8_11_io_deq_valid : _T_5179 ? _Queue16_UInt8_10_io_deq_valid : _T_5178 ? _Queue16_UInt8_9_io_deq_valid : _T_5177 ? _Queue16_UInt8_8_io_deq_valid : _T_5176 ? _Queue16_UInt8_7_io_deq_valid : _T_5175 ? _Queue16_UInt8_6_io_deq_valid : _T_5174 ? _Queue16_UInt8_5_io_deq_valid : _T_5173 ? _Queue16_UInt8_4_io_deq_valid : _T_5172 ? _Queue16_UInt8_3_io_deq_valid : _T_5171 ? _Queue16_UInt8_2_io_deq_valid : _T_5170 ? _Queue16_UInt8_1_io_deq_valid : _T_5169 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_27 = _remapindex_T + 7'h1B; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_117 = _remapindex_T_27 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_27 = _GEN_117[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5201 = remapindex_27 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5202 = remapindex_27 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5203 = remapindex_27 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5204 = remapindex_27 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5205 = remapindex_27 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5206 = remapindex_27 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5207 = remapindex_27 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5208 = remapindex_27 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5209 = remapindex_27 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5210 = remapindex_27 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5211 = remapindex_27 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5212 = remapindex_27 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5213 = remapindex_27 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5214 = remapindex_27 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5215 = remapindex_27 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5216 = remapindex_27 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5217 = remapindex_27 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5218 = remapindex_27 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5219 = remapindex_27 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5220 = remapindex_27 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5221 = remapindex_27 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5222 = remapindex_27 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5223 = remapindex_27 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5224 = remapindex_27 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5225 = remapindex_27 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5226 = remapindex_27 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5227 = remapindex_27 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5228 = remapindex_27 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5229 = remapindex_27 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5230 = remapindex_27 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5231 = remapindex_27 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5232 = remapindex_27 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_27 = _T_5232 ? _Queue16_UInt8_31_io_deq_bits : _T_5231 ? _Queue16_UInt8_30_io_deq_bits : _T_5230 ? _Queue16_UInt8_29_io_deq_bits : _T_5229 ? _Queue16_UInt8_28_io_deq_bits : _T_5228 ? _Queue16_UInt8_27_io_deq_bits : _T_5227 ? _Queue16_UInt8_26_io_deq_bits : _T_5226 ? _Queue16_UInt8_25_io_deq_bits : _T_5225 ? _Queue16_UInt8_24_io_deq_bits : _T_5224 ? _Queue16_UInt8_23_io_deq_bits : _T_5223 ? _Queue16_UInt8_22_io_deq_bits : _T_5222 ? _Queue16_UInt8_21_io_deq_bits : _T_5221 ? _Queue16_UInt8_20_io_deq_bits : _T_5220 ? _Queue16_UInt8_19_io_deq_bits : _T_5219 ? _Queue16_UInt8_18_io_deq_bits : _T_5218 ? _Queue16_UInt8_17_io_deq_bits : _T_5217 ? _Queue16_UInt8_16_io_deq_bits : _T_5216 ? _Queue16_UInt8_15_io_deq_bits : _T_5215 ? _Queue16_UInt8_14_io_deq_bits : _T_5214 ? _Queue16_UInt8_13_io_deq_bits : _T_5213 ? _Queue16_UInt8_12_io_deq_bits : _T_5212 ? _Queue16_UInt8_11_io_deq_bits : _T_5211 ? _Queue16_UInt8_10_io_deq_bits : _T_5210 ? _Queue16_UInt8_9_io_deq_bits : _T_5209 ? _Queue16_UInt8_8_io_deq_bits : _T_5208 ? _Queue16_UInt8_7_io_deq_bits : _T_5207 ? _Queue16_UInt8_6_io_deq_bits : _T_5206 ? _Queue16_UInt8_5_io_deq_bits : _T_5205 ? _Queue16_UInt8_4_io_deq_bits : _T_5204 ? _Queue16_UInt8_3_io_deq_bits : _T_5203 ? _Queue16_UInt8_2_io_deq_bits : _T_5202 ? _Queue16_UInt8_1_io_deq_bits : _T_5201 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_27 = _T_5232 ? _Queue16_UInt8_31_io_deq_valid : _T_5231 ? _Queue16_UInt8_30_io_deq_valid : _T_5230 ? _Queue16_UInt8_29_io_deq_valid : _T_5229 ? _Queue16_UInt8_28_io_deq_valid : _T_5228 ? _Queue16_UInt8_27_io_deq_valid : _T_5227 ? _Queue16_UInt8_26_io_deq_valid : _T_5226 ? _Queue16_UInt8_25_io_deq_valid : _T_5225 ? _Queue16_UInt8_24_io_deq_valid : _T_5224 ? _Queue16_UInt8_23_io_deq_valid : _T_5223 ? _Queue16_UInt8_22_io_deq_valid : _T_5222 ? _Queue16_UInt8_21_io_deq_valid : _T_5221 ? _Queue16_UInt8_20_io_deq_valid : _T_5220 ? _Queue16_UInt8_19_io_deq_valid : _T_5219 ? _Queue16_UInt8_18_io_deq_valid : _T_5218 ? _Queue16_UInt8_17_io_deq_valid : _T_5217 ? _Queue16_UInt8_16_io_deq_valid : _T_5216 ? _Queue16_UInt8_15_io_deq_valid : _T_5215 ? _Queue16_UInt8_14_io_deq_valid : _T_5214 ? _Queue16_UInt8_13_io_deq_valid : _T_5213 ? _Queue16_UInt8_12_io_deq_valid : _T_5212 ? _Queue16_UInt8_11_io_deq_valid : _T_5211 ? _Queue16_UInt8_10_io_deq_valid : _T_5210 ? _Queue16_UInt8_9_io_deq_valid : _T_5209 ? _Queue16_UInt8_8_io_deq_valid : _T_5208 ? _Queue16_UInt8_7_io_deq_valid : _T_5207 ? _Queue16_UInt8_6_io_deq_valid : _T_5206 ? _Queue16_UInt8_5_io_deq_valid : _T_5205 ? _Queue16_UInt8_4_io_deq_valid : _T_5204 ? _Queue16_UInt8_3_io_deq_valid : _T_5203 ? _Queue16_UInt8_2_io_deq_valid : _T_5202 ? _Queue16_UInt8_1_io_deq_valid : _T_5201 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_28 = _remapindex_T + 7'h1C; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_118 = _remapindex_T_28 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_28 = _GEN_118[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5233 = remapindex_28 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5234 = remapindex_28 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5235 = remapindex_28 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5236 = remapindex_28 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5237 = remapindex_28 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5238 = remapindex_28 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5239 = remapindex_28 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5240 = remapindex_28 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5241 = remapindex_28 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5242 = remapindex_28 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5243 = remapindex_28 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5244 = remapindex_28 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5245 = remapindex_28 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5246 = remapindex_28 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5247 = remapindex_28 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5248 = remapindex_28 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5249 = remapindex_28 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5250 = remapindex_28 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5251 = remapindex_28 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5252 = remapindex_28 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5253 = remapindex_28 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5254 = remapindex_28 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5255 = remapindex_28 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5256 = remapindex_28 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5257 = remapindex_28 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5258 = remapindex_28 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5259 = remapindex_28 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5260 = remapindex_28 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5261 = remapindex_28 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5262 = remapindex_28 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5263 = remapindex_28 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5264 = remapindex_28 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_28 = _T_5264 ? _Queue16_UInt8_31_io_deq_bits : _T_5263 ? _Queue16_UInt8_30_io_deq_bits : _T_5262 ? _Queue16_UInt8_29_io_deq_bits : _T_5261 ? _Queue16_UInt8_28_io_deq_bits : _T_5260 ? _Queue16_UInt8_27_io_deq_bits : _T_5259 ? _Queue16_UInt8_26_io_deq_bits : _T_5258 ? _Queue16_UInt8_25_io_deq_bits : _T_5257 ? _Queue16_UInt8_24_io_deq_bits : _T_5256 ? _Queue16_UInt8_23_io_deq_bits : _T_5255 ? _Queue16_UInt8_22_io_deq_bits : _T_5254 ? _Queue16_UInt8_21_io_deq_bits : _T_5253 ? _Queue16_UInt8_20_io_deq_bits : _T_5252 ? _Queue16_UInt8_19_io_deq_bits : _T_5251 ? _Queue16_UInt8_18_io_deq_bits : _T_5250 ? _Queue16_UInt8_17_io_deq_bits : _T_5249 ? _Queue16_UInt8_16_io_deq_bits : _T_5248 ? _Queue16_UInt8_15_io_deq_bits : _T_5247 ? _Queue16_UInt8_14_io_deq_bits : _T_5246 ? _Queue16_UInt8_13_io_deq_bits : _T_5245 ? _Queue16_UInt8_12_io_deq_bits : _T_5244 ? _Queue16_UInt8_11_io_deq_bits : _T_5243 ? _Queue16_UInt8_10_io_deq_bits : _T_5242 ? _Queue16_UInt8_9_io_deq_bits : _T_5241 ? _Queue16_UInt8_8_io_deq_bits : _T_5240 ? _Queue16_UInt8_7_io_deq_bits : _T_5239 ? _Queue16_UInt8_6_io_deq_bits : _T_5238 ? _Queue16_UInt8_5_io_deq_bits : _T_5237 ? _Queue16_UInt8_4_io_deq_bits : _T_5236 ? _Queue16_UInt8_3_io_deq_bits : _T_5235 ? _Queue16_UInt8_2_io_deq_bits : _T_5234 ? _Queue16_UInt8_1_io_deq_bits : _T_5233 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_28 = _T_5264 ? _Queue16_UInt8_31_io_deq_valid : _T_5263 ? _Queue16_UInt8_30_io_deq_valid : _T_5262 ? _Queue16_UInt8_29_io_deq_valid : _T_5261 ? _Queue16_UInt8_28_io_deq_valid : _T_5260 ? _Queue16_UInt8_27_io_deq_valid : _T_5259 ? _Queue16_UInt8_26_io_deq_valid : _T_5258 ? _Queue16_UInt8_25_io_deq_valid : _T_5257 ? _Queue16_UInt8_24_io_deq_valid : _T_5256 ? _Queue16_UInt8_23_io_deq_valid : _T_5255 ? _Queue16_UInt8_22_io_deq_valid : _T_5254 ? _Queue16_UInt8_21_io_deq_valid : _T_5253 ? _Queue16_UInt8_20_io_deq_valid : _T_5252 ? _Queue16_UInt8_19_io_deq_valid : _T_5251 ? _Queue16_UInt8_18_io_deq_valid : _T_5250 ? _Queue16_UInt8_17_io_deq_valid : _T_5249 ? _Queue16_UInt8_16_io_deq_valid : _T_5248 ? _Queue16_UInt8_15_io_deq_valid : _T_5247 ? _Queue16_UInt8_14_io_deq_valid : _T_5246 ? _Queue16_UInt8_13_io_deq_valid : _T_5245 ? _Queue16_UInt8_12_io_deq_valid : _T_5244 ? _Queue16_UInt8_11_io_deq_valid : _T_5243 ? _Queue16_UInt8_10_io_deq_valid : _T_5242 ? _Queue16_UInt8_9_io_deq_valid : _T_5241 ? _Queue16_UInt8_8_io_deq_valid : _T_5240 ? _Queue16_UInt8_7_io_deq_valid : _T_5239 ? _Queue16_UInt8_6_io_deq_valid : _T_5238 ? _Queue16_UInt8_5_io_deq_valid : _T_5237 ? _Queue16_UInt8_4_io_deq_valid : _T_5236 ? _Queue16_UInt8_3_io_deq_valid : _T_5235 ? _Queue16_UInt8_2_io_deq_valid : _T_5234 ? _Queue16_UInt8_1_io_deq_valid : _T_5233 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_29 = _remapindex_T + 7'h1D; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_119 = _remapindex_T_29 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_29 = _GEN_119[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5265 = remapindex_29 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5266 = remapindex_29 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5267 = remapindex_29 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5268 = remapindex_29 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5269 = remapindex_29 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5270 = remapindex_29 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5271 = remapindex_29 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5272 = remapindex_29 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5273 = remapindex_29 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5274 = remapindex_29 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5275 = remapindex_29 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5276 = remapindex_29 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5277 = remapindex_29 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5278 = remapindex_29 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5279 = remapindex_29 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5280 = remapindex_29 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5281 = remapindex_29 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5282 = remapindex_29 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5283 = remapindex_29 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5284 = remapindex_29 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5285 = remapindex_29 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5286 = remapindex_29 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5287 = remapindex_29 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5288 = remapindex_29 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5289 = remapindex_29 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5290 = remapindex_29 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5291 = remapindex_29 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5292 = remapindex_29 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5293 = remapindex_29 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5294 = remapindex_29 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5295 = remapindex_29 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5296 = remapindex_29 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_29 = _T_5296 ? _Queue16_UInt8_31_io_deq_bits : _T_5295 ? _Queue16_UInt8_30_io_deq_bits : _T_5294 ? _Queue16_UInt8_29_io_deq_bits : _T_5293 ? _Queue16_UInt8_28_io_deq_bits : _T_5292 ? _Queue16_UInt8_27_io_deq_bits : _T_5291 ? _Queue16_UInt8_26_io_deq_bits : _T_5290 ? _Queue16_UInt8_25_io_deq_bits : _T_5289 ? _Queue16_UInt8_24_io_deq_bits : _T_5288 ? _Queue16_UInt8_23_io_deq_bits : _T_5287 ? _Queue16_UInt8_22_io_deq_bits : _T_5286 ? _Queue16_UInt8_21_io_deq_bits : _T_5285 ? _Queue16_UInt8_20_io_deq_bits : _T_5284 ? _Queue16_UInt8_19_io_deq_bits : _T_5283 ? _Queue16_UInt8_18_io_deq_bits : _T_5282 ? _Queue16_UInt8_17_io_deq_bits : _T_5281 ? _Queue16_UInt8_16_io_deq_bits : _T_5280 ? _Queue16_UInt8_15_io_deq_bits : _T_5279 ? _Queue16_UInt8_14_io_deq_bits : _T_5278 ? _Queue16_UInt8_13_io_deq_bits : _T_5277 ? _Queue16_UInt8_12_io_deq_bits : _T_5276 ? _Queue16_UInt8_11_io_deq_bits : _T_5275 ? _Queue16_UInt8_10_io_deq_bits : _T_5274 ? _Queue16_UInt8_9_io_deq_bits : _T_5273 ? _Queue16_UInt8_8_io_deq_bits : _T_5272 ? _Queue16_UInt8_7_io_deq_bits : _T_5271 ? _Queue16_UInt8_6_io_deq_bits : _T_5270 ? _Queue16_UInt8_5_io_deq_bits : _T_5269 ? _Queue16_UInt8_4_io_deq_bits : _T_5268 ? _Queue16_UInt8_3_io_deq_bits : _T_5267 ? _Queue16_UInt8_2_io_deq_bits : _T_5266 ? _Queue16_UInt8_1_io_deq_bits : _T_5265 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_29 = _T_5296 ? _Queue16_UInt8_31_io_deq_valid : _T_5295 ? _Queue16_UInt8_30_io_deq_valid : _T_5294 ? _Queue16_UInt8_29_io_deq_valid : _T_5293 ? _Queue16_UInt8_28_io_deq_valid : _T_5292 ? _Queue16_UInt8_27_io_deq_valid : _T_5291 ? _Queue16_UInt8_26_io_deq_valid : _T_5290 ? _Queue16_UInt8_25_io_deq_valid : _T_5289 ? _Queue16_UInt8_24_io_deq_valid : _T_5288 ? _Queue16_UInt8_23_io_deq_valid : _T_5287 ? _Queue16_UInt8_22_io_deq_valid : _T_5286 ? _Queue16_UInt8_21_io_deq_valid : _T_5285 ? _Queue16_UInt8_20_io_deq_valid : _T_5284 ? _Queue16_UInt8_19_io_deq_valid : _T_5283 ? _Queue16_UInt8_18_io_deq_valid : _T_5282 ? _Queue16_UInt8_17_io_deq_valid : _T_5281 ? _Queue16_UInt8_16_io_deq_valid : _T_5280 ? _Queue16_UInt8_15_io_deq_valid : _T_5279 ? _Queue16_UInt8_14_io_deq_valid : _T_5278 ? _Queue16_UInt8_13_io_deq_valid : _T_5277 ? _Queue16_UInt8_12_io_deq_valid : _T_5276 ? _Queue16_UInt8_11_io_deq_valid : _T_5275 ? _Queue16_UInt8_10_io_deq_valid : _T_5274 ? _Queue16_UInt8_9_io_deq_valid : _T_5273 ? _Queue16_UInt8_8_io_deq_valid : _T_5272 ? _Queue16_UInt8_7_io_deq_valid : _T_5271 ? _Queue16_UInt8_6_io_deq_valid : _T_5270 ? _Queue16_UInt8_5_io_deq_valid : _T_5269 ? _Queue16_UInt8_4_io_deq_valid : _T_5268 ? _Queue16_UInt8_3_io_deq_valid : _T_5267 ? _Queue16_UInt8_2_io_deq_valid : _T_5266 ? _Queue16_UInt8_1_io_deq_valid : _T_5265 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_30 = _remapindex_T + 7'h1E; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_120 = _remapindex_T_30 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_30 = _GEN_120[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5297 = remapindex_30 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5298 = remapindex_30 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5299 = remapindex_30 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5300 = remapindex_30 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5301 = remapindex_30 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5302 = remapindex_30 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5303 = remapindex_30 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5304 = remapindex_30 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5305 = remapindex_30 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5306 = remapindex_30 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5307 = remapindex_30 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5308 = remapindex_30 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5309 = remapindex_30 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5310 = remapindex_30 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5311 = remapindex_30 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5312 = remapindex_30 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5313 = remapindex_30 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5314 = remapindex_30 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5315 = remapindex_30 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5316 = remapindex_30 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5317 = remapindex_30 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5318 = remapindex_30 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5319 = remapindex_30 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5320 = remapindex_30 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5321 = remapindex_30 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5322 = remapindex_30 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5323 = remapindex_30 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5324 = remapindex_30 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5325 = remapindex_30 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5326 = remapindex_30 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5327 = remapindex_30 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5328 = remapindex_30 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_30 = _T_5328 ? _Queue16_UInt8_31_io_deq_bits : _T_5327 ? _Queue16_UInt8_30_io_deq_bits : _T_5326 ? _Queue16_UInt8_29_io_deq_bits : _T_5325 ? _Queue16_UInt8_28_io_deq_bits : _T_5324 ? _Queue16_UInt8_27_io_deq_bits : _T_5323 ? _Queue16_UInt8_26_io_deq_bits : _T_5322 ? _Queue16_UInt8_25_io_deq_bits : _T_5321 ? _Queue16_UInt8_24_io_deq_bits : _T_5320 ? _Queue16_UInt8_23_io_deq_bits : _T_5319 ? _Queue16_UInt8_22_io_deq_bits : _T_5318 ? _Queue16_UInt8_21_io_deq_bits : _T_5317 ? _Queue16_UInt8_20_io_deq_bits : _T_5316 ? _Queue16_UInt8_19_io_deq_bits : _T_5315 ? _Queue16_UInt8_18_io_deq_bits : _T_5314 ? _Queue16_UInt8_17_io_deq_bits : _T_5313 ? _Queue16_UInt8_16_io_deq_bits : _T_5312 ? _Queue16_UInt8_15_io_deq_bits : _T_5311 ? _Queue16_UInt8_14_io_deq_bits : _T_5310 ? _Queue16_UInt8_13_io_deq_bits : _T_5309 ? _Queue16_UInt8_12_io_deq_bits : _T_5308 ? _Queue16_UInt8_11_io_deq_bits : _T_5307 ? _Queue16_UInt8_10_io_deq_bits : _T_5306 ? _Queue16_UInt8_9_io_deq_bits : _T_5305 ? _Queue16_UInt8_8_io_deq_bits : _T_5304 ? _Queue16_UInt8_7_io_deq_bits : _T_5303 ? _Queue16_UInt8_6_io_deq_bits : _T_5302 ? _Queue16_UInt8_5_io_deq_bits : _T_5301 ? _Queue16_UInt8_4_io_deq_bits : _T_5300 ? _Queue16_UInt8_3_io_deq_bits : _T_5299 ? _Queue16_UInt8_2_io_deq_bits : _T_5298 ? _Queue16_UInt8_1_io_deq_bits : _T_5297 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_30 = _T_5328 ? _Queue16_UInt8_31_io_deq_valid : _T_5327 ? _Queue16_UInt8_30_io_deq_valid : _T_5326 ? _Queue16_UInt8_29_io_deq_valid : _T_5325 ? _Queue16_UInt8_28_io_deq_valid : _T_5324 ? _Queue16_UInt8_27_io_deq_valid : _T_5323 ? _Queue16_UInt8_26_io_deq_valid : _T_5322 ? _Queue16_UInt8_25_io_deq_valid : _T_5321 ? _Queue16_UInt8_24_io_deq_valid : _T_5320 ? _Queue16_UInt8_23_io_deq_valid : _T_5319 ? _Queue16_UInt8_22_io_deq_valid : _T_5318 ? _Queue16_UInt8_21_io_deq_valid : _T_5317 ? _Queue16_UInt8_20_io_deq_valid : _T_5316 ? _Queue16_UInt8_19_io_deq_valid : _T_5315 ? _Queue16_UInt8_18_io_deq_valid : _T_5314 ? _Queue16_UInt8_17_io_deq_valid : _T_5313 ? _Queue16_UInt8_16_io_deq_valid : _T_5312 ? _Queue16_UInt8_15_io_deq_valid : _T_5311 ? _Queue16_UInt8_14_io_deq_valid : _T_5310 ? _Queue16_UInt8_13_io_deq_valid : _T_5309 ? _Queue16_UInt8_12_io_deq_valid : _T_5308 ? _Queue16_UInt8_11_io_deq_valid : _T_5307 ? _Queue16_UInt8_10_io_deq_valid : _T_5306 ? _Queue16_UInt8_9_io_deq_valid : _T_5305 ? _Queue16_UInt8_8_io_deq_valid : _T_5304 ? _Queue16_UInt8_7_io_deq_valid : _T_5303 ? _Queue16_UInt8_6_io_deq_valid : _T_5302 ? _Queue16_UInt8_5_io_deq_valid : _T_5301 ? _Queue16_UInt8_4_io_deq_valid : _T_5300 ? _Queue16_UInt8_3_io_deq_valid : _T_5299 ? _Queue16_UInt8_2_io_deq_valid : _T_5298 ? _Queue16_UInt8_1_io_deq_valid : _T_5297 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_31 = _remapindex_T + 7'h1F; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_121 = _remapindex_T_31 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_31 = _GEN_121[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5329 = remapindex_31 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5330 = remapindex_31 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5331 = remapindex_31 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5332 = remapindex_31 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5333 = remapindex_31 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5334 = remapindex_31 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5335 = remapindex_31 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5336 = remapindex_31 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5337 = remapindex_31 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5338 = remapindex_31 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5339 = remapindex_31 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5340 = remapindex_31 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5341 = remapindex_31 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5342 = remapindex_31 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5343 = remapindex_31 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5344 = remapindex_31 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5345 = remapindex_31 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5346 = remapindex_31 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5347 = remapindex_31 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5348 = remapindex_31 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5349 = remapindex_31 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5350 = remapindex_31 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5351 = remapindex_31 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5352 = remapindex_31 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5353 = remapindex_31 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5354 = remapindex_31 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5355 = remapindex_31 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5356 = remapindex_31 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5357 = remapindex_31 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5358 = remapindex_31 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5359 = remapindex_31 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5360 = remapindex_31 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_31 = _T_5360 ? _Queue16_UInt8_31_io_deq_bits : _T_5359 ? _Queue16_UInt8_30_io_deq_bits : _T_5358 ? _Queue16_UInt8_29_io_deq_bits : _T_5357 ? _Queue16_UInt8_28_io_deq_bits : _T_5356 ? _Queue16_UInt8_27_io_deq_bits : _T_5355 ? _Queue16_UInt8_26_io_deq_bits : _T_5354 ? _Queue16_UInt8_25_io_deq_bits : _T_5353 ? _Queue16_UInt8_24_io_deq_bits : _T_5352 ? _Queue16_UInt8_23_io_deq_bits : _T_5351 ? _Queue16_UInt8_22_io_deq_bits : _T_5350 ? _Queue16_UInt8_21_io_deq_bits : _T_5349 ? _Queue16_UInt8_20_io_deq_bits : _T_5348 ? _Queue16_UInt8_19_io_deq_bits : _T_5347 ? _Queue16_UInt8_18_io_deq_bits : _T_5346 ? _Queue16_UInt8_17_io_deq_bits : _T_5345 ? _Queue16_UInt8_16_io_deq_bits : _T_5344 ? _Queue16_UInt8_15_io_deq_bits : _T_5343 ? _Queue16_UInt8_14_io_deq_bits : _T_5342 ? _Queue16_UInt8_13_io_deq_bits : _T_5341 ? _Queue16_UInt8_12_io_deq_bits : _T_5340 ? _Queue16_UInt8_11_io_deq_bits : _T_5339 ? _Queue16_UInt8_10_io_deq_bits : _T_5338 ? _Queue16_UInt8_9_io_deq_bits : _T_5337 ? _Queue16_UInt8_8_io_deq_bits : _T_5336 ? _Queue16_UInt8_7_io_deq_bits : _T_5335 ? _Queue16_UInt8_6_io_deq_bits : _T_5334 ? _Queue16_UInt8_5_io_deq_bits : _T_5333 ? _Queue16_UInt8_4_io_deq_bits : _T_5332 ? _Queue16_UInt8_3_io_deq_bits : _T_5331 ? _Queue16_UInt8_2_io_deq_bits : _T_5330 ? _Queue16_UInt8_1_io_deq_bits : _T_5329 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_31 = _T_5360 ? _Queue16_UInt8_31_io_deq_valid : _T_5359 ? _Queue16_UInt8_30_io_deq_valid : _T_5358 ? _Queue16_UInt8_29_io_deq_valid : _T_5357 ? _Queue16_UInt8_28_io_deq_valid : _T_5356 ? _Queue16_UInt8_27_io_deq_valid : _T_5355 ? _Queue16_UInt8_26_io_deq_valid : _T_5354 ? _Queue16_UInt8_25_io_deq_valid : _T_5353 ? _Queue16_UInt8_24_io_deq_valid : _T_5352 ? _Queue16_UInt8_23_io_deq_valid : _T_5351 ? _Queue16_UInt8_22_io_deq_valid : _T_5350 ? _Queue16_UInt8_21_io_deq_valid : _T_5349 ? _Queue16_UInt8_20_io_deq_valid : _T_5348 ? _Queue16_UInt8_19_io_deq_valid : _T_5347 ? _Queue16_UInt8_18_io_deq_valid : _T_5346 ? _Queue16_UInt8_17_io_deq_valid : _T_5345 ? _Queue16_UInt8_16_io_deq_valid : _T_5344 ? _Queue16_UInt8_15_io_deq_valid : _T_5343 ? _Queue16_UInt8_14_io_deq_valid : _T_5342 ? _Queue16_UInt8_13_io_deq_valid : _T_5341 ? _Queue16_UInt8_12_io_deq_valid : _T_5340 ? _Queue16_UInt8_11_io_deq_valid : _T_5339 ? _Queue16_UInt8_10_io_deq_valid : _T_5338 ? _Queue16_UInt8_9_io_deq_valid : _T_5337 ? _Queue16_UInt8_8_io_deq_valid : _T_5336 ? _Queue16_UInt8_7_io_deq_valid : _T_5335 ? _Queue16_UInt8_6_io_deq_valid : _T_5334 ? _Queue16_UInt8_5_io_deq_valid : _T_5333 ? _Queue16_UInt8_4_io_deq_valid : _T_5332 ? _Queue16_UInt8_3_io_deq_valid : _T_5331 ? _Queue16_UInt8_2_io_deq_valid : _T_5330 ? _Queue16_UInt8_1_io_deq_valid : _T_5329 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [1:0] _count_valids_T = {1'h0, remapVecValids_0} + {1'h0, remapVecValids_1}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [2:0] _count_valids_T_1 = {1'h0, _count_valids_T} + {2'h0, remapVecValids_2}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [3:0] _count_valids_T_2 = {1'h0, _count_valids_T_1} + {3'h0, remapVecValids_3}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [4:0] _count_valids_T_3 = {1'h0, _count_valids_T_2} + {4'h0, remapVecValids_4}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [5:0] _count_valids_T_4 = {1'h0, _count_valids_T_3} + {5'h0, remapVecValids_5}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [6:0] _count_valids_T_5 = {1'h0, _count_valids_T_4} + {6'h0, remapVecValids_6}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [7:0] _count_valids_T_6 = {1'h0, _count_valids_T_5} + {7'h0, remapVecValids_7}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [8:0] _count_valids_T_7 = {1'h0, _count_valids_T_6} + {8'h0, remapVecValids_8}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [9:0] _count_valids_T_8 = {1'h0, _count_valids_T_7} + {9'h0, remapVecValids_9}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [10:0] _count_valids_T_9 = {1'h0, _count_valids_T_8} + {10'h0, remapVecValids_10}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [11:0] _count_valids_T_10 = {1'h0, _count_valids_T_9} + {11'h0, remapVecValids_11}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [12:0] _count_valids_T_11 = {1'h0, _count_valids_T_10} + {12'h0, remapVecValids_12}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [13:0] _count_valids_T_12 = {1'h0, _count_valids_T_11} + {13'h0, remapVecValids_13}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [14:0] _count_valids_T_13 = {1'h0, _count_valids_T_12} + {14'h0, remapVecValids_14}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [15:0] _count_valids_T_14 = {1'h0, _count_valids_T_13} + {15'h0, remapVecValids_15}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [16:0] _count_valids_T_15 = {1'h0, _count_valids_T_14} + {16'h0, remapVecValids_16}; // @[ZstdCompressorMemWriter.scala:89:{76,90}, :142:28, :163:60] wire [17:0] _count_valids_T_16 = {1'h0, _count_valids_T_15} + {17'h0, remapVecValids_17}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [18:0] _count_valids_T_17 = {1'h0, _count_valids_T_16} + {18'h0, remapVecValids_18}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [19:0] _count_valids_T_18 = {1'h0, _count_valids_T_17} + {19'h0, remapVecValids_19}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [20:0] _count_valids_T_19 = {1'h0, _count_valids_T_18} + {20'h0, remapVecValids_20}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [21:0] _count_valids_T_20 = {1'h0, _count_valids_T_19} + {21'h0, remapVecValids_21}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [22:0] _count_valids_T_21 = {1'h0, _count_valids_T_20} + {22'h0, remapVecValids_22}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [23:0] _count_valids_T_22 = {1'h0, _count_valids_T_21} + {23'h0, remapVecValids_23}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [24:0] _count_valids_T_23 = {1'h0, _count_valids_T_22} + {24'h0, remapVecValids_24}; // @[ZstdCompressorMemWriter.scala:89:{76,90}, :142:28, :163:60] wire [25:0] _count_valids_T_24 = {1'h0, _count_valids_T_23} + {25'h0, remapVecValids_25}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [26:0] _count_valids_T_25 = {1'h0, _count_valids_T_24} + {26'h0, remapVecValids_26}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [27:0] _count_valids_T_26 = {1'h0, _count_valids_T_25} + {27'h0, remapVecValids_27}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [28:0] _count_valids_T_27 = {1'h0, _count_valids_T_26} + {28'h0, remapVecValids_28}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [29:0] _count_valids_T_28 = {1'h0, _count_valids_T_27} + {29'h0, remapVecValids_29}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [30:0] _count_valids_T_29 = {1'h0, _count_valids_T_28} + {30'h0, remapVecValids_30}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [31:0] count_valids = {1'h0, _count_valids_T_29} + {31'h0, remapVecValids_31}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] reg [63:0] backend_bytes_written; // @[ZstdCompressorMemWriter.scala:167:38] wire [64:0] _GEN_122 = {1'h0, backend_bytes_written}; // @[ZstdCompressorMemWriter.scala:167:38, :168:60] wire [64:0] _backend_next_write_addr_T = {1'h0, _dest_info_Q_io_deq_bits_op} + _GEN_122; // @[ZstdCompressorMemWriter.scala:39:27, :168:60] wire [63:0] backend_next_write_addr = _backend_next_write_addr_T[63:0]; // @[ZstdCompressorMemWriter.scala:168:60] wire [64:0] _throttle_end_T = {1'h0, _buf_lens_Q_io_deq_bits} - _GEN_122; // @[ZstdCompressorMemWriter.scala:52:26, :168:60, :171:28] wire [63:0] _throttle_end_T_1 = _throttle_end_T[63:0]; // @[ZstdCompressorMemWriter.scala:171:28] wire [63:0] throttle_end = _buf_lens_Q_io_deq_valid ? _throttle_end_T_1 : 64'h20; // @[ZstdCompressorMemWriter.scala:52:26, :170:25, :171:28] wire _throttle_end_writeable_T = \|(throttle_end[63:5]); // @[ZstdCompressorMemWriter.scala:170:25, :174:49] wire _throttle_end_writeable_T_1 = throttle_end[4]; // @[ZstdCompressorMemWriter.scala:170:25, :175:53] wire _throttle_end_writeable_log2_T_1 = throttle_end[4]; // @[ZstdCompressorMemWriter.scala:170:25, :175:53, :183:55] wire _throttle_end_writeable_T_2 = throttle_end[3]; // @[ZstdCompressorMemWriter.scala:170:25, :176:55] wire _throttle_end_writeable_log2_T_2 = throttle_end[3]; // @[ZstdCompressorMemWriter.scala:170:25, :176:55, :184:57] wire _throttle_end_writeable_T_3 = throttle_end[2]; // @[ZstdCompressorMemWriter.scala:170:25, :177:57] wire _throttle_end_writeable_log2_T_3 = throttle_end[2]; // @[ZstdCompressorMemWriter.scala:170:25, :177:57, :185:59] wire _throttle_end_writeable_T_4 = throttle_end[1]; // @[ZstdCompressorMemWriter.scala:170:25, :178:59] wire _throttle_end_writeable_log2_T_4 = throttle_end[1]; // @[ZstdCompressorMemWriter.scala:170:25, :178:59, :186:61] wire _throttle_end_writeable_T_5 = throttle_end[0]; // @[ZstdCompressorMemWriter.scala:170:25, :179:61] wire _throttle_end_writeable_log2_T_5 = throttle_end[0]; // @[ZstdCompressorMemWriter.scala:170:25, :179:61, :187:63] wire _throttle_end_writeable_T_6 = _throttle_end_writeable_T_5; // @[ZstdCompressorMemWriter.scala:179:{48,61}] wire [1:0] _throttle_end_writeable_T_7 = _throttle_end_writeable_T_4 ? 2'h2 : {1'h0, _throttle_end_writeable_T_6}; // @[ZstdCompressorMemWriter.scala:178:{46,59}, :179:48] wire [2:0] _throttle_end_writeable_T_8 = _throttle_end_writeable_T_3 ? 3'h4 : {1'h0, _throttle_end_writeable_T_7}; // @[ZstdCompressorMemWriter.scala:177:{44,57}, :178:46] wire [3:0] _throttle_end_writeable_T_9 = _throttle_end_writeable_T_2 ? 4'h8 : {1'h0, _throttle_end_writeable_T_8}; // @[ZstdCompressorMemWriter.scala:176:{42,55}, :177:44] wire [4:0] _throttle_end_writeable_T_10 = _throttle_end_writeable_T_1 ? 5'h10 : {1'h0, _throttle_end_writeable_T_9}; // @[ZstdCompressorMemWriter.scala:175:{40,53}, :176:42] wire [5:0] throttle_end_writeable = _throttle_end_writeable_T ? 6'h20 : {1'h0, _throttle_end_writeable_T_10}; // @[ZstdCompressorMemWriter.scala:174:{35,49}, :175:40] wire _throttle_end_writeable_log2_T = \|(throttle_end[63:5]); // @[ZstdCompressorMemWriter.scala:170:25, :174:49, :182:54] wire _throttle_end_writeable_log2_T_7 = _throttle_end_writeable_log2_T_4; // @[ZstdCompressorMemWriter.scala:186:{48,61}] wire [1:0] _throttle_end_writeable_log2_T_8 = _throttle_end_writeable_log2_T_3 ? 2'h2 : {1'h0, _throttle_end_writeable_log2_T_7}; // @[ZstdCompressorMemWriter.scala:185:{46,59}, :186:48] wire [1:0] _throttle_end_writeable_log2_T_9 = _throttle_end_writeable_log2_T_2 ? 2'h3 : _throttle_end_writeable_log2_T_8; // @[ZstdCompressorMemWriter.scala:184:{44,57}, :185:46] wire [2:0] _throttle_end_writeable_log2_T_10 = _throttle_end_writeable_log2_T_1 ? 3'h4 : {1'h0, _throttle_end_writeable_log2_T_9}; // @[ZstdCompressorMemWriter.scala:183:{42,55}, :184:44] wire [2:0] throttle_end_writeable_log2 = _throttle_end_writeable_log2_T ? 3'h5 : _throttle_end_writeable_log2_T_10; // @[ZstdCompressorMemWriter.scala:182:{40,54}, :183:42] wire _ptr_align_max_bytes_writeable_T = backend_next_write_addr[0]; // @[ZstdCompressorMemWriter.scala:168:60, :191:66] wire _ptr_align_max_bytes_writeable_log2_T = backend_next_write_addr[0]; // @[ZstdCompressorMemWriter.scala:168:60, :191:66, :198:71] wire _ptr_align_max_bytes_writeable_T_1 = backend_next_write_addr[1]; // @[ZstdCompressorMemWriter.scala:168:60, :192:68] wire _ptr_align_max_bytes_writeable_log2_T_1 = backend_next_write_addr[1]; // @[ZstdCompressorMemWriter.scala:168:60, :192:68, :199:72] wire _ptr_align_max_bytes_writeable_T_2 = backend_next_write_addr[2]; // @[ZstdCompressorMemWriter.scala:168:60, :193:70] wire _ptr_align_max_bytes_writeable_log2_T_2 = backend_next_write_addr[2]; // @[ZstdCompressorMemWriter.scala:168:60, :193:70, :200:74] wire _ptr_align_max_bytes_writeable_T_3 = backend_next_write_addr[3]; // @[ZstdCompressorMemWriter.scala:168:60, :194:72] wire _ptr_align_max_bytes_writeable_log2_T_3 = backend_next_write_addr[3]; // @[ZstdCompressorMemWriter.scala:168:60, :194:72, :201:76] wire _ptr_align_max_bytes_writeable_T_4 = backend_next_write_addr[4]; // @[ZstdCompressorMemWriter.scala:168:60, :195:74] wire _ptr_align_max_bytes_writeable_log2_T_4 = backend_next_write_addr[4]; // @[ZstdCompressorMemWriter.scala:168:60, :195:74, :202:78] wire [5:0] _ptr_align_max_bytes_writeable_T_5 = _ptr_align_max_bytes_writeable_T_4 ? 6'h10 : 6'h20; // @[ZstdCompressorMemWriter.scala:195:{50,74}] wire [5:0] _ptr_align_max_bytes_writeable_T_6 = _ptr_align_max_bytes_writeable_T_3 ? 6'h8 : _ptr_align_max_bytes_writeable_T_5; // @[ZstdCompressorMemWriter.scala:194:{48,72}, :195:50] wire [5:0] _ptr_align_max_bytes_writeable_T_7 = _ptr_align_max_bytes_writeable_T_2 ? 6'h4 : _ptr_align_max_bytes_writeable_T_6; // @[ZstdCompressorMemWriter.scala:193:{46,70}, :194:48] wire [5:0] _ptr_align_max_bytes_writeable_T_8 = _ptr_align_max_bytes_writeable_T_1 ? 6'h2 : _ptr_align_max_bytes_writeable_T_7; // @[ZstdCompressorMemWriter.scala:192:{44,68}, :193:46] wire [5:0] ptr_align_max_bytes_writeable = _ptr_align_max_bytes_writeable_T ? 6'h1 : _ptr_align_max_bytes_writeable_T_8; // @[ZstdCompressorMemWriter.scala:191:{42,66}, :192:44] wire [2:0] _ptr_align_max_bytes_writeable_log2_T_5 = {2'h2, ~_ptr_align_max_bytes_writeable_log2_T_4}; // @[ZstdCompressorMemWriter.scala:202:{54,78}] wire [2:0] _ptr_align_max_bytes_writeable_log2_T_6 = _ptr_align_max_bytes_writeable_log2_T_3 ? 3'h3 : _ptr_align_max_bytes_writeable_log2_T_5; // @[ZstdCompressorMemWriter.scala:201:{52,76}, :202:54] wire [2:0] _ptr_align_max_bytes_writeable_log2_T_7 = _ptr_align_max_bytes_writeable_log2_T_2 ? 3'h2 : _ptr_align_max_bytes_writeable_log2_T_6; // @[ZstdCompressorMemWriter.scala:200:{50,74}, :201:52] wire [2:0] _ptr_align_max_bytes_writeable_log2_T_8 = _ptr_align_max_bytes_writeable_log2_T_1 ? 3'h1 : _ptr_align_max_bytes_writeable_log2_T_7; // @[ZstdCompressorMemWriter.scala:199:{48,72}, :200:50] wire [2:0] ptr_align_max_bytes_writeable_log2 = _ptr_align_max_bytes_writeable_log2_T ? 3'h0 : _ptr_align_max_bytes_writeable_log2_T_8; // @[ZstdCompressorMemWriter.scala:198:{47,71}, :199:48] wire _count_valids_largest_aligned_T = count_valids[5]; // @[ZstdCompressorMemWriter.scala:163:60, :205:54] wire _count_valids_largest_aligned_log2_T = count_valids[5]; // @[ZstdCompressorMemWriter.scala:163:60, :205:54, :213:59] wire _count_valids_largest_aligned_T_1 = count_valids[4]; // @[ZstdCompressorMemWriter.scala:163:60, :206:55] wire _count_valids_largest_aligned_log2_T_1 = count_valids[4]; // @[ZstdCompressorMemWriter.scala:163:60, :206:55, :214:61] wire _count_valids_largest_aligned_T_2 = count_valids[3]; // @[ZstdCompressorMemWriter.scala:163:60, :207:57] wire _count_valids_largest_aligned_log2_T_2 = count_valids[3]; // @[ZstdCompressorMemWriter.scala:163:60, :207:57, :215:63] wire _count_valids_largest_aligned_T_3 = count_valids[2]; // @[ZstdCompressorMemWriter.scala:163:60, :208:59] wire _count_valids_largest_aligned_log2_T_3 = count_valids[2]; // @[ZstdCompressorMemWriter.scala:163:60, :208:59, :216:65] wire _count_valids_largest_aligned_T_4 = count_valids[1]; // @[ZstdCompressorMemWriter.scala:163:60, :209:61] wire _count_valids_largest_aligned_log2_T_4 = count_valids[1]; // @[ZstdCompressorMemWriter.scala:163:60, :209:61, :217:67] wire _count_valids_largest_aligned_T_5 = count_valids[0]; // @[ZstdCompressorMemWriter.scala:163:60, :210:63] wire _count_valids_largest_aligned_log2_T_5 = count_valids[0]; // @[ZstdCompressorMemWriter.scala:163:60, :210:63, :218:69] wire _count_valids_largest_aligned_T_6 = _count_valids_largest_aligned_T_5; // @[ZstdCompressorMemWriter.scala:210:{50,63}] wire [1:0] _count_valids_largest_aligned_T_7 = _count_valids_largest_aligned_T_4 ? 2'h2 : {1'h0, _count_valids_largest_aligned_T_6}; // @[ZstdCompressorMemWriter.scala:209:{48,61}, :210:50] wire [2:0] _count_valids_largest_aligned_T_8 = _count_valids_largest_aligned_T_3 ? 3'h4 : {1'h0, _count_valids_largest_aligned_T_7}; // @[ZstdCompressorMemWriter.scala:208:{46,59}, :209:48] wire [3:0] _count_valids_largest_aligned_T_9 = _count_valids_largest_aligned_T_2 ? 4'h8 : {1'h0, _count_valids_largest_aligned_T_8}; // @[ZstdCompressorMemWriter.scala:207:{44,57}, :208:46] wire [4:0] _count_valids_largest_aligned_T_10 = _count_valids_largest_aligned_T_1 ? 5'h10 : {1'h0, _count_valids_largest_aligned_T_9}; // @[ZstdCompressorMemWriter.scala:206:{42,55}, :207:44] wire [5:0] count_valids_largest_aligned = _count_valids_largest_aligned_T ? 6'h20 : {1'h0, _count_valids_largest_aligned_T_10}; // @[ZstdCompressorMemWriter.scala:205:{41,54}, :206:42] wire _count_valids_largest_aligned_log2_T_7 = _count_valids_largest_aligned_log2_T_4; // @[ZstdCompressorMemWriter.scala:217:{54,67}] wire [1:0] _count_valids_largest_aligned_log2_T_8 = _count_valids_largest_aligned_log2_T_3 ? 2'h2 : {1'h0, _count_valids_largest_aligned_log2_T_7}; // @[ZstdCompressorMemWriter.scala:216:{52,65}, :217:54] wire [1:0] _count_valids_largest_aligned_log2_T_9 = _count_valids_largest_aligned_log2_T_2 ? 2'h3 : _count_valids_largest_aligned_log2_T_8; // @[ZstdCompressorMemWriter.scala:215:{50,63}, :216:52] wire [2:0] _count_valids_largest_aligned_log2_T_10 = _count_valids_largest_aligned_log2_T_1 ? 3'h4 : {1'h0, _count_valids_largest_aligned_log2_T_9}; // @[ZstdCompressorMemWriter.scala:214:{48,61}, :215:50] wire [2:0] count_valids_largest_aligned_log2 = _count_valids_largest_aligned_log2_T ? 3'h5 : _count_valids_largest_aligned_log2_T_10; // @[ZstdCompressorMemWriter.scala:213:{46,59}, :214:48] wire _bytes_to_write_T = ptr_align_max_bytes_writeable < count_valids_largest_aligned; // @[ZstdCompressorMemWriter.scala:191:42, :205:41, :225:35] wire _bytes_to_write_T_1 = ptr_align_max_bytes_writeable < throttle_end_writeable; // @[ZstdCompressorMemWriter.scala:174:35, :191:42, :226:39] wire [5:0] _bytes_to_write_T_2 = _bytes_to_write_T_1 ? ptr_align_max_bytes_writeable : throttle_end_writeable; // @[ZstdCompressorMemWriter.scala:174:35, :191:42, :226:{8,39}] wire _bytes_to_write_T_3 = count_valids_largest_aligned < throttle_end_writeable; // @[ZstdCompressorMemWriter.scala:174:35, :205:41, :229:38] wire [5:0] _bytes_to_write_T_4 = _bytes_to_write_T_3 ? count_valids_largest_aligned : throttle_end_writeable; // @[ZstdCompressorMemWriter.scala:174:35, :205:41, :229:{8,38}] wire [5:0] bytes_to_write = _bytes_to_write_T ? _bytes_to_write_T_2 : _bytes_to_write_T_4; // @[ZstdCompressorMemWriter.scala:224:27, :225:35, :226:8, :229:8] wire [15:0] remapped_write_data_lo_lo_lo_lo = {remapVecData_1, remapVecData_0}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_lo_lo_lo_hi = {remapVecData_3, remapVecData_2}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_lo_lo_lo = {remapped_write_data_lo_lo_lo_hi, remapped_write_data_lo_lo_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [15:0] remapped_write_data_lo_lo_hi_lo = {remapVecData_5, remapVecData_4}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_lo_lo_hi_hi = {remapVecData_7, remapVecData_6}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_lo_lo_hi = {remapped_write_data_lo_lo_hi_hi, remapped_write_data_lo_lo_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [63:0] remapped_write_data_lo_lo = {remapped_write_data_lo_lo_hi, remapped_write_data_lo_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [15:0] remapped_write_data_lo_hi_lo_lo = {remapVecData_9, remapVecData_8}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_lo_hi_lo_hi = {remapVecData_11, remapVecData_10}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_lo_hi_lo = {remapped_write_data_lo_hi_lo_hi, remapped_write_data_lo_hi_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [15:0] remapped_write_data_lo_hi_hi_lo = {remapVecData_13, remapVecData_12}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_lo_hi_hi_hi = {remapVecData_15, remapVecData_14}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_lo_hi_hi = {remapped_write_data_lo_hi_hi_hi, remapped_write_data_lo_hi_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [63:0] remapped_write_data_lo_hi = {remapped_write_data_lo_hi_hi, remapped_write_data_lo_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [127:0] remapped_write_data_lo = {remapped_write_data_lo_hi, remapped_write_data_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [15:0] remapped_write_data_hi_lo_lo_lo = {remapVecData_17, remapVecData_16}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_hi_lo_lo_hi = {remapVecData_19, remapVecData_18}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_hi_lo_lo = {remapped_write_data_hi_lo_lo_hi, remapped_write_data_hi_lo_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [15:0] remapped_write_data_hi_lo_hi_lo = {remapVecData_21, remapVecData_20}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_hi_lo_hi_hi = {remapVecData_23, remapVecData_22}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_hi_lo_hi = {remapped_write_data_hi_lo_hi_hi, remapped_write_data_hi_lo_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [63:0] remapped_write_data_hi_lo = {remapped_write_data_hi_lo_hi, remapped_write_data_hi_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [15:0] remapped_write_data_hi_hi_lo_lo = {remapVecData_25, remapVecData_24}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_hi_hi_lo_hi = {remapVecData_27, remapVecData_26}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_hi_hi_lo = {remapped_write_data_hi_hi_lo_hi, remapped_write_data_hi_hi_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [15:0] remapped_write_data_hi_hi_hi_lo = {remapVecData_29, remapVecData_28}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_hi_hi_hi_hi = {remapVecData_31, remapVecData_30}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_hi_hi_hi = {remapped_write_data_hi_hi_hi_hi, remapped_write_data_hi_hi_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [63:0] remapped_write_data_hi_hi = {remapped_write_data_hi_hi_hi, remapped_write_data_hi_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [127:0] remapped_write_data_hi = {remapped_write_data_hi_hi, remapped_write_data_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [255:0] remapped_write_data = {remapped_write_data_hi, remapped_write_data_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire enough_data = \|bytes_to_write; // @[ZstdCompressorMemWriter.scala:224:27, :235:36] wire _bytes_to_write_log2_T = ptr_align_max_bytes_writeable_log2 < count_valids_largest_aligned_log2; // @[ZstdCompressorMemWriter.scala:198:47, :213:46, :238:40] wire _bytes_to_write_log2_T_1 = ptr_align_max_bytes_writeable_log2 < throttle_end_writeable_log2; // @[ZstdCompressorMemWriter.scala:182:40, :198:47, :239:44] wire [2:0] _bytes_to_write_log2_T_2 = _bytes_to_write_log2_T_1 ? ptr_align_max_bytes_writeable_log2 : throttle_end_writeable_log2; // @[ZstdCompressorMemWriter.scala:182:40, :198:47, :239:{8,44}] wire _bytes_to_write_log2_T_3 = count_valids_largest_aligned_log2 < throttle_end_writeable_log2; // @[ZstdCompressorMemWriter.scala:182:40, :213:46, :242:43] wire [2:0] _bytes_to_write_log2_T_4 = _bytes_to_write_log2_T_3 ? count_valids_largest_aligned_log2 : throttle_end_writeable_log2; // @[ZstdCompressorMemWriter.scala:182:40, :213:46, :242:{8,43}] wire [2:0] bytes_to_write_log2 = _bytes_to_write_log2_T ? _bytes_to_write_log2_T_2 : _bytes_to_write_log2_T_4; // @[ZstdCompressorMemWriter.scala:237:32, :238:40, :239:8, :242:8] wire _write_ptr_override_T = _buf_lens_Q_io_deq_bits == backend_bytes_written; // @[ZstdCompressorMemWriter.scala:52:26, :167:38, :247:79] wire write_ptr_override = _buf_lens_Q_io_deq_valid & _write_ptr_override_T; // @[ZstdCompressorMemWriter.scala:52:26, :247:{52,79}] wire _remapVecReadys_0_T = \|bytes_to_write; // @[ZstdCompressorMemWriter.scala:224:27, :235:36, :264:43] wire _T_5363 = io_l2io_req_ready_0 & enough_data; // @[Misc.scala:29:18] wire _remapVecReadys_0_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_0_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_1_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_1_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_2_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_2_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_3_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_3_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_4_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_4_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_5_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_5_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_6_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_6_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_7_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_7_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_8_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_8_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_9_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_9_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_10_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_10_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_11_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_11_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_12_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_12_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_13_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_13_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_14_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_14_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_15_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_15_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_16_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_16_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_17_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_17_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_18_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_18_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_19_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_19_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_20_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_20_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_21_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_21_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_22_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_22_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_23_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_23_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_24_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_24_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_25_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_25_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_26_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_26_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_27_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_27_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_28_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_28_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_29_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_29_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_30_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_30_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_31_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_31_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_0_T_2 = _remapVecReadys_0_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_0_T_3 = _remapVecReadys_0_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_0_T_4 = _remapVecReadys_0_T & _remapVecReadys_0_T_3; // @[Misc.scala:29:18] assign remapVecReadys_0 = _remapVecReadys_0_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_1_T = \|(bytes_to_write[5:1]); // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_1_T_2 = _remapVecReadys_1_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_1_T_3 = _remapVecReadys_1_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_1_T_4 = _remapVecReadys_1_T & _remapVecReadys_1_T_3; // @[Misc.scala:29:18] assign remapVecReadys_1 = _remapVecReadys_1_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_2_T = bytes_to_write > 6'h2; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_2_T_2 = _remapVecReadys_2_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_2_T_3 = _remapVecReadys_2_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_2_T_4 = _remapVecReadys_2_T & _remapVecReadys_2_T_3; // @[Misc.scala:29:18] assign remapVecReadys_2 = _remapVecReadys_2_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_3_T = \|(bytes_to_write[5:2]); // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_3_T_2 = _remapVecReadys_3_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_3_T_3 = _remapVecReadys_3_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_3_T_4 = _remapVecReadys_3_T & _remapVecReadys_3_T_3; // @[Misc.scala:29:18] assign remapVecReadys_3 = _remapVecReadys_3_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_4_T = bytes_to_write > 6'h4; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_4_T_2 = _remapVecReadys_4_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_4_T_3 = _remapVecReadys_4_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_4_T_4 = _remapVecReadys_4_T & _remapVecReadys_4_T_3; // @[Misc.scala:29:18] assign remapVecReadys_4 = _remapVecReadys_4_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_5_T = bytes_to_write > 6'h5; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_5_T_2 = _remapVecReadys_5_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_5_T_3 = _remapVecReadys_5_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_5_T_4 = _remapVecReadys_5_T & _remapVecReadys_5_T_3; // @[Misc.scala:29:18] assign remapVecReadys_5 = _remapVecReadys_5_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_6_T = bytes_to_write > 6'h6; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_6_T_2 = _remapVecReadys_6_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_6_T_3 = _remapVecReadys_6_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_6_T_4 = _remapVecReadys_6_T & _remapVecReadys_6_T_3; // @[Misc.scala:29:18] assign remapVecReadys_6 = _remapVecReadys_6_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_7_T = \|(bytes_to_write[5:3]); // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_7_T_2 = _remapVecReadys_7_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_7_T_3 = _remapVecReadys_7_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_7_T_4 = _remapVecReadys_7_T & _remapVecReadys_7_T_3; // @[Misc.scala:29:18] assign remapVecReadys_7 = _remapVecReadys_7_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_8_T = bytes_to_write > 6'h8; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_8_T_2 = _remapVecReadys_8_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_8_T_3 = _remapVecReadys_8_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_8_T_4 = _remapVecReadys_8_T & _remapVecReadys_8_T_3; // @[Misc.scala:29:18] assign remapVecReadys_8 = _remapVecReadys_8_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_9_T = bytes_to_write > 6'h9; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_9_T_2 = _remapVecReadys_9_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_9_T_3 = _remapVecReadys_9_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_9_T_4 = _remapVecReadys_9_T & _remapVecReadys_9_T_3; // @[Misc.scala:29:18] assign remapVecReadys_9 = _remapVecReadys_9_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_10_T = bytes_to_write > 6'hA; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_10_T_2 = _remapVecReadys_10_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_10_T_3 = _remapVecReadys_10_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_10_T_4 = _remapVecReadys_10_T & _remapVecReadys_10_T_3; // @[Misc.scala:29:18] assign remapVecReadys_10 = _remapVecReadys_10_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_11_T = bytes_to_write > 6'hB; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_11_T_2 = _remapVecReadys_11_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_11_T_3 = _remapVecReadys_11_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_11_T_4 = _remapVecReadys_11_T & _remapVecReadys_11_T_3; // @[Misc.scala:29:18] assign remapVecReadys_11 = _remapVecReadys_11_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_12_T = bytes_to_write > 6'hC; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_12_T_2 = _remapVecReadys_12_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_12_T_3 = _remapVecReadys_12_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_12_T_4 = _remapVecReadys_12_T & _remapVecReadys_12_T_3; // @[Misc.scala:29:18] assign remapVecReadys_12 = _remapVecReadys_12_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_13_T = bytes_to_write > 6'hD; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_13_T_2 = _remapVecReadys_13_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_13_T_3 = _remapVecReadys_13_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_13_T_4 = _remapVecReadys_13_T & _remapVecReadys_13_T_3; // @[Misc.scala:29:18] assign remapVecReadys_13 = _remapVecReadys_13_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_14_T = bytes_to_write > 6'hE; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_14_T_2 = _remapVecReadys_14_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_14_T_3 = _remapVecReadys_14_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_14_T_4 = _remapVecReadys_14_T & _remapVecReadys_14_T_3; // @[Misc.scala:29:18] assign remapVecReadys_14 = _remapVecReadys_14_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_15_T = \|(bytes_to_write[5:4]); // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_15_T_2 = _remapVecReadys_15_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_15_T_3 = _remapVecReadys_15_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_15_T_4 = _remapVecReadys_15_T & _remapVecReadys_15_T_3; // @[Misc.scala:29:18] assign remapVecReadys_15 = _remapVecReadys_15_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_16_T = bytes_to_write > 6'h10; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_16_T_2 = _remapVecReadys_16_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_16_T_3 = _remapVecReadys_16_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_16_T_4 = _remapVecReadys_16_T & _remapVecReadys_16_T_3; // @[Misc.scala:29:18] assign remapVecReadys_16 = _remapVecReadys_16_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_17_T = bytes_to_write > 6'h11; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_17_T_2 = _remapVecReadys_17_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_17_T_3 = _remapVecReadys_17_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_17_T_4 = _remapVecReadys_17_T & _remapVecReadys_17_T_3; // @[Misc.scala:29:18] assign remapVecReadys_17 = _remapVecReadys_17_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_18_T = bytes_to_write > 6'h12; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_18_T_2 = _remapVecReadys_18_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_18_T_3 = _remapVecReadys_18_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_18_T_4 = _remapVecReadys_18_T & _remapVecReadys_18_T_3; // @[Misc.scala:29:18] assign remapVecReadys_18 = _remapVecReadys_18_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_19_T = bytes_to_write > 6'h13; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_19_T_2 = _remapVecReadys_19_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_19_T_3 = _remapVecReadys_19_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_19_T_4 = _remapVecReadys_19_T & _remapVecReadys_19_T_3; // @[Misc.scala:29:18] assign remapVecReadys_19 = _remapVecReadys_19_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_20_T = bytes_to_write > 6'h14; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_20_T_2 = _remapVecReadys_20_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_20_T_3 = _remapVecReadys_20_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_20_T_4 = _remapVecReadys_20_T & _remapVecReadys_20_T_3; // @[Misc.scala:29:18] assign remapVecReadys_20 = _remapVecReadys_20_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_21_T = bytes_to_write > 6'h15; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_21_T_2 = _remapVecReadys_21_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_21_T_3 = _remapVecReadys_21_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_21_T_4 = _remapVecReadys_21_T & _remapVecReadys_21_T_3; // @[Misc.scala:29:18] assign remapVecReadys_21 = _remapVecReadys_21_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_22_T = bytes_to_write > 6'h16; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_22_T_2 = _remapVecReadys_22_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_22_T_3 = _remapVecReadys_22_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_22_T_4 = _remapVecReadys_22_T & _remapVecReadys_22_T_3; // @[Misc.scala:29:18] assign remapVecReadys_22 = _remapVecReadys_22_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_23_T = bytes_to_write > 6'h17; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_23_T_2 = _remapVecReadys_23_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_23_T_3 = _remapVecReadys_23_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_23_T_4 = _remapVecReadys_23_T & _remapVecReadys_23_T_3; // @[Misc.scala:29:18] assign remapVecReadys_23 = _remapVecReadys_23_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_24_T = bytes_to_write > 6'h18; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_24_T_2 = _remapVecReadys_24_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_24_T_3 = _remapVecReadys_24_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_24_T_4 = _remapVecReadys_24_T & _remapVecReadys_24_T_3; // @[Misc.scala:29:18] assign remapVecReadys_24 = _remapVecReadys_24_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_25_T = bytes_to_write > 6'h19; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_25_T_2 = _remapVecReadys_25_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_25_T_3 = _remapVecReadys_25_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_25_T_4 = _remapVecReadys_25_T & _remapVecReadys_25_T_3; // @[Misc.scala:29:18] assign remapVecReadys_25 = _remapVecReadys_25_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_26_T = bytes_to_write > 6'h1A; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_26_T_2 = _remapVecReadys_26_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_26_T_3 = _remapVecReadys_26_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_26_T_4 = _remapVecReadys_26_T & _remapVecReadys_26_T_3; // @[Misc.scala:29:18] assign remapVecReadys_26 = _remapVecReadys_26_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_27_T = bytes_to_write > 6'h1B; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_27_T_2 = _remapVecReadys_27_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_27_T_3 = _remapVecReadys_27_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_27_T_4 = _remapVecReadys_27_T & _remapVecReadys_27_T_3; // @[Misc.scala:29:18] assign remapVecReadys_27 = _remapVecReadys_27_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_28_T = bytes_to_write > 6'h1C; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_28_T_2 = _remapVecReadys_28_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_28_T_3 = _remapVecReadys_28_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_28_T_4 = _remapVecReadys_28_T & _remapVecReadys_28_T_3; // @[Misc.scala:29:18] assign remapVecReadys_28 = _remapVecReadys_28_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_29_T = bytes_to_write > 6'h1D; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_29_T_2 = _remapVecReadys_29_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_29_T_3 = _remapVecReadys_29_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_29_T_4 = _remapVecReadys_29_T & _remapVecReadys_29_T_3; // @[Misc.scala:29:18] assign remapVecReadys_29 = _remapVecReadys_29_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_30_T = bytes_to_write > 6'h1E; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_30_T_2 = _remapVecReadys_30_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_30_T_3 = _remapVecReadys_30_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_30_T_4 = _remapVecReadys_30_T & _remapVecReadys_30_T_3; // @[Misc.scala:29:18] assign remapVecReadys_30 = _remapVecReadys_30_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_31_T = bytes_to_write[5]; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_31_T_2 = _remapVecReadys_31_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_31_T_3 = _remapVecReadys_31_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_31_T_4 = _remapVecReadys_31_T & _remapVecReadys_31_T_3; // @[Misc.scala:29:18] assign remapVecReadys_31 = _remapVecReadys_31_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _T_5365 = _T_5363 & ~write_ptr_override & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] wire [6:0] _read_start_index_T = _remapindex_T + {1'h0, bytes_to_write}; // @[ZstdCompressorMemWriter.scala:153:33, :224:27, :268:43] wire [6:0] _GEN_123 = _read_start_index_T % 7'h20; // @[ZstdCompressorMemWriter.scala:268:{43,62}] wire [5:0] _read_start_index_T_1 = _GEN_123[5:0]; // @[ZstdCompressorMemWriter.scala:268:62] wire [64:0] _backend_bytes_written_T = _GEN_122 + {59'h0, bytes_to_write}; // @[ZstdCompressorMemWriter.scala:168:60, :224:27, :269:52] wire [63:0] _backend_bytes_written_T_1 = _backend_bytes_written_T[63:0]; // @[ZstdCompressorMemWriter.scala:269:52] reg [63:0] loginfo_cycles_35; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_70 = {1'h0, loginfo_cycles_35} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_71 = _loginfo_cycles_T_70[63:0]; // @[Util.scala:19:38] wire _io_l2io_req_valid_T = enough_data & ~write_ptr_override; // @[Misc.scala:26:53] assign _io_l2io_req_valid_T_1 = _io_l2io_req_valid_T & _dest_info_Q_io_deq_valid; // @[Misc.scala:26:53] assign io_l2io_req_valid_0 = _io_l2io_req_valid_T_1; // @[Misc.scala:26:53] assign _io_l2io_req_bits_size_T = write_ptr_override ? 3'h2 : bytes_to_write_log2; // @[ZstdCompressorMemWriter.scala:237:32, :247:52, :282:31] assign io_l2io_req_bits_size_0 = _io_l2io_req_bits_size_T; // @[ZstdCompressorMemWriter.scala:23:7, :282:31] assign _io_l2io_req_bits_addr_T = write_ptr_override ? _dest_info_Q_io_deq_bits_cmpflag : backend_next_write_addr; // @[ZstdCompressorMemWriter.scala:39:27, :168:60, :247:52, :283:31] assign io_l2io_req_bits_addr_0 = _io_l2io_req_bits_addr_T; // @[ZstdCompressorMemWriter.scala:23:7, :283:31] assign _io_l2io_req_bits_data_T = write_ptr_override ? {192'h0, _dest_info_Q_io_deq_bits_cmpval} : remapped_write_data; // @[ZstdCompressorMemWriter.scala:39:27, :89:{76,90}, :233:32, :247:52, :284:31] assign io_l2io_req_bits_data_0 = _io_l2io_req_bits_data_T; // @[ZstdCompressorMemWriter.scala:23:7, :284:31] wire _buf_lens_Q_io_deq_ready_T = io_l2io_req_ready_0 & _write_ptr_override_T; // @[Misc.scala:26:53] wire _buf_lens_Q_io_deq_ready_T_1 = _buf_lens_Q_io_deq_ready_T & _dest_info_Q_io_deq_valid; // @[Misc.scala:26:53] wire _dest_info_Q_io_deq_ready_T = io_l2io_req_ready_0 & _buf_lens_Q_io_deq_valid; // @[Misc.scala:26:53] assign _dest_info_Q_io_deq_ready_T_1 = _dest_info_Q_io_deq_ready_T & _write_ptr_override_T; // @[Misc.scala:26:53] reg [63:0] bufs_completed; // @[ZstdCompressorMemWriter.scala:290:31] assign io_bufs_completed_0 = bufs_completed; // @[ZstdCompressorMemWriter.scala:23:7, :290:31] wire _T_5372 = _dest_info_Q_io_deq_ready_T & _write_ptr_override_T & _dest_info_Q_io_deq_valid; // @[Misc.scala:26:53, :29:18] wire [64:0] _bufs_completed_T = {1'h0, bufs_completed} + 65'h1; // @[ZstdCompressorMemWriter.scala:290:31, :298:38] wire [63:0] _bufs_completed_T_1 = _bufs_completed_T[63:0]; // @[ZstdCompressorMemWriter.scala:298:38] reg [63:0] loginfo_cycles_36; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_72 = {1'h0, loginfo_cycles_36} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_73 = _loginfo_cycles_T_72[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_37; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_74 = {1'h0, loginfo_cycles_37} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_75 = _loginfo_cycles_T_74[63:0]; // @[Util.scala:19:38]
Generate the Verilog code corresponding to the following Chisel files. File FPU.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util._ import chisel3.{DontCare, WireInit, withClock, withReset} import chisel3.experimental.SourceInfo import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property case class FPUParams( minFLen: Int = 32, fLen: Int = 64, divSqrt: Boolean = true, sfmaLatency: Int = 3, dfmaLatency: Int = 4, fpmuLatency: Int = 2, ifpuLatency: Int = 2 ) object FPConstants { val RM_SZ = 3 val FLAGS_SZ = 5 } trait HasFPUCtrlSigs { val ldst = Bool() val wen = Bool() val ren1 = Bool() val ren2 = Bool() val ren3 = Bool() val swap12 = Bool() val swap23 = Bool() val typeTagIn = UInt(2.W) val typeTagOut = UInt(2.W) val fromint = Bool() val toint = Bool() val fastpipe = Bool() val fma = Bool() val div = Bool() val sqrt = Bool() val wflags = Bool() val vec = Bool() } class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new Bundle { val inst = Input(Bits(32.W)) val sigs = Output(new FPUCtrlSigs()) }) private val X2 = BitPat.dontCare(2) val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N) val h: Array[(BitPat, List[BitPat])] = Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N), FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N), FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N), FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N), FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N), FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N), FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N), FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N), FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N)) val f: Array[(BitPat, List[BitPat])] = Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N), FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N), FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N), FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N), FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N), FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N), FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N)) val d: Array[(BitPat, List[BitPat])] = Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N), FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N), FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N), FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N), FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N), FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N), FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N), FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N), FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N)) val fcvt_hd: Array[(BitPat, List[BitPat])] = Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N), FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N)) val vfmv_f_s: Array[(BitPat, List[BitPat])] = Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y)) val insns = ((minFLen, fLen) match { case (32, 32) => f case (16, 32) => h ++ f case (32, 64) => f ++ d case (16, 64) => h ++ f ++ d ++ fcvt_hd case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration") }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]()) val decoder = DecodeLogic(io.inst, default, insns) val s = io.sigs val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec) sigs zip decoder map {case(s,d) => s := d} } class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val time = Input(UInt(xLen.W)) val inst = Input(Bits(32.W)) val fromint_data = Input(Bits(xLen.W)) val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W)) val v_sew = Input(UInt(3.W)) val store_data = Output(Bits(fLen.W)) val toint_data = Output(Bits(xLen.W)) val ll_resp_val = Input(Bool()) val ll_resp_type = Input(Bits(3.W)) val ll_resp_tag = Input(UInt(5.W)) val ll_resp_data = Input(Bits(fLen.W)) val valid = Input(Bool()) val fcsr_rdy = Output(Bool()) val nack_mem = Output(Bool()) val illegal_rm = Output(Bool()) val killx = Input(Bool()) val killm = Input(Bool()) val dec = Output(new FPUCtrlSigs()) val sboard_set = Output(Bool()) val sboard_clr = Output(Bool()) val sboard_clra = Output(UInt(5.W)) val keep_clock_enabled = Input(Bool()) } class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) { val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs val cp_resp = Decoupled(new FPResult()) } class FPResult(implicit p: Parameters) extends CoreBundle()(p) { val data = Bits((fLen+1).W) val exc = Bits(FPConstants.FLAGS_SZ.W) } class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val typ = Bits(2.W) val in1 = Bits(xLen.W) } class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val fmaCmd = Bits(2.W) val typ = Bits(2.W) val fmt = Bits(2.W) val in1 = Bits((fLen+1).W) val in2 = Bits((fLen+1).W) val in3 = Bits((fLen+1).W) } case class FType(exp: Int, sig: Int) { def ieeeWidth = exp + sig def recodedWidth = ieeeWidth + 1 def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W) def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W) def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2) def classify(x: UInt) = { val sign = x(sig + exp) val code = x(exp + sig - 1, exp + sig - 3) val codeHi = code(2, 1) val isSpecial = codeHi === 3.U val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U val isSubnormal = code === 1.U \|\| codeHi === 1.U && isHighSubnormalIn val isNormal = codeHi === 1.U && !isHighSubnormalIn \|\| codeHi === 2.U val isZero = code === 0.U val isInf = isSpecial && !code(0) val isNaN = code.andR val isSNaN = isNaN && !x(sig-2) val isQNaN = isNaN && x(sig-2) Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign, isSubnormal && !sign, isZero && !sign, isZero && sign, isSubnormal && sign, isNormal && sign, isInf && sign) } // convert between formats, ignoring rounding, range, NaN def unsafeConvert(x: UInt, to: FType) = if (this == to) x else { val sign = x(sig + exp) val fractIn = x(sig - 2, 0) val expIn = x(sig + exp - 1, sig - 1) val fractOut = fractIn << to.sig >> sig val expOut = { val expCode = expIn(exp, exp - 2) val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U Mux(expCode === 0.U \|\| expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0)) } Cat(sign, expOut, fractOut) } private def ieeeBundle = { val expWidth = exp class IEEEBundle extends Bundle { val sign = Bool() val exp = UInt(expWidth.W) val sig = UInt((ieeeWidth-expWidth-1).W) } new IEEEBundle } def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle) def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x) def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x) } object FType { val H = new FType(5, 11) val S = new FType(8, 24) val D = new FType(11, 53) val all = List(H, S, D) } trait HasFPUParameters { require(fLen == 0 \|\| FType.all.exists(_.ieeeWidth == fLen)) val minFLen: Int val fLen: Int def xLen: Int val minXLen = 32 val nIntTypes = log2Ceil(xLen/minXLen) + 1 def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen) def minType = floatTypes.head def maxType = floatTypes.last def prevType(t: FType) = floatTypes(typeTag(t) - 1) def maxExpWidth = maxType.exp def maxSigWidth = maxType.sig def typeTag(t: FType) = floatTypes.indexOf(t) def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U // typeTag def H = typeTagGroup(FType.H) def S = typeTagGroup(FType.S) def D = typeTagGroup(FType.D) def I = typeTag(maxType).U private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = { require(xt.ieeeWidth == 2 * yt.ieeeWidth) val swizzledNaN = Cat( x(xt.sig + xt.exp, xt.sig + xt.exp - 3), x(xt.sig - 2, yt.recodedWidth - 1).andR, x(xt.sig + xt.exp - 5, xt.sig), y(yt.recodedWidth - 2), x(xt.sig - 2, yt.recodedWidth - 1), y(yt.recodedWidth - 1), y(yt.recodedWidth - 3, 0)) Mux(xt.isNaN(x), swizzledNaN, x) } // implement NaN unboxing for FU inputs def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = { val outType = exactType.getOrElse(maxType) def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = { val prev = if (t == minType) { Seq() } else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prev = helper(unswizzled, prevT) val isbox = isBox(x, t) prev.map(p => (isbox && p._1, p._2)) } prev :+ (true.B, t.unsafeConvert(x, outType)) } val (oks, floats) = helper(x, maxType).unzip if (exactType.isEmpty \|\| floatTypes.size == 1) { Mux(oks(tag), floats(tag), maxType.qNaN) } else { val t = exactType.get floats(typeTag(t)) \| Mux(oks(typeTag(t)), 0.U, t.qNaN) } } // make sure that the redundant bits in the NaN-boxed encoding are consistent def consistent(x: UInt): Bool = { def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prevOK = !isBox(x, t) \|\| helper(unswizzled, prevT) val curOK = !t.isNaN(x) \|\| x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR prevOK && curOK } helper(x, maxType) } // generate a NaN box from an FU result def box(x: UInt, t: FType): UInt = { if (t == maxType) { x } else { val nt = floatTypes(typeTag(t) + 1) val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t) bigger \| ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U } } // generate a NaN box from an FU result def box(x: UInt, tag: UInt): UInt = { val opts = floatTypes.map(t => box(x, t)) opts(tag) } // zap bits that hardfloat thinks are don't-cares, but we do care about def sanitizeNaN(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { x } else { val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) \| (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W) Mux(t.isNaN(x), maskedNaN, x) } } // implement NaN boxing and recoding for FL/fmv..x def recode(x: UInt, tag: UInt): UInt = { def helper(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { t.recode(x) } else { val prevT = prevType(t) box(t.recode(x), t, helper(x, prevT), prevT) } } // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U) helper(boxes(tag) \| x, maxType) } // implement NaN unboxing and un-recoding for FS/fmv.x. def ieee(x: UInt, t: FType = maxType): UInt = { if (typeTag(t) == 0) { t.ieee(x) } else { val unrecoded = t.ieee(x) val prevT = prevType(t) val prevRecoded = Cat( x(prevT.recodedWidth-2), x(t.sig-1), x(prevT.recodedWidth-3, 0)) val prevUnrecoded = ieee(prevRecoded, prevT) Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0))) } } } abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { class Output extends Bundle { val in = new FPInput val lt = Bool() val store = Bits(fLen.W) val toint = Bits(xLen.W) val exc = Bits(FPConstants.FLAGS_SZ.W) } val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new Output) }) val in = RegEnable(io.in.bits, io.in.valid) val valid = RegNext(io.in.valid) val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth)) dcmp.io.a := in.in1 dcmp.io.b := in.in2 dcmp.io.signaling := !in.rm(1) val tag = in.typeTagOut val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen)) else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) val toint = WireDefault(toint_ieee) val intType = WireDefault(in.fmt(0)) io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType) io.out.bits.exc := 0.U when (in.rm(0)) { val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag) toint := classify_out \| (toint_ieee >> minXLen << minXLen) intType := false.B } when (in.wflags) { // feq/flt/fle, fcvt toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR \| (toint_ieee >> minXLen << minXLen) io.out.bits.exc := dcmp.io.exceptionFlags intType := false.B when (!in.ren2) { // fcvt val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1) intType := cvtType val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen)) conv.io.in := in.in1 conv.io.roundingMode := in.rm conv.io.signedOut := ~in.typ(0) toint := conv.io.out io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0)) for (i <- 0 until nIntTypes-1) { val w = minXLen << i when (cvtType === i.U) { val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w)) narrow.io.in := in.in1 narrow.io.roundingMode := in.rm narrow.io.signedOut := ~in.typ(0) val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1) val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign)) val invalid = conv.io.intExceptionFlags(2) \|\| narrow.io.intExceptionFlags(1) when (invalid) { toint := Cat(conv.io.out >> w, excOut) } io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0)) } } } } io.out.valid := valid io.out.bits.lt := dcmp.io.lt \|\| (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S) io.out.bits.in := in } class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new IntToFPInput)) val out = Valid(new FPResult) }) val in = Pipe(io.in) val tag = in.bits.typeTagIn val mux = Wire(new FPResult) mux.exc := 0.U mux.data := recode(in.bits.in1, tag) val intValue = { val res = WireDefault(in.bits.in1.asSInt) for (i <- 0 until nIntTypes-1) { val smallInt = in.bits.in1((minXLen << i) - 1, 0) when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) { res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt) } } res.asUInt } when (in.bits.wflags) { // fcvt // could be improved for RVD/RVQ with a single variable-position rounding // unit, rather than N fixed-position ones val i2fResults = for (t <- floatTypes) yield { val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig)) i2f.io.signedIn := ~in.bits.typ(0) i2f.io.in := intValue i2f.io.roundingMode := in.bits.rm i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags) } val (data, exc) = i2fResults.unzip val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last mux.data := dataPadded(tag) mux.exc := exc(tag) } io.out <> Pipe(in.valid, mux, latency-1) } class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) val lt = Input(Bool()) // from FPToInt }) val in = Pipe(io.in) val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2)) val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0)) val fsgnjMux = Wire(new FPResult) fsgnjMux.exc := 0.U fsgnjMux.data := fsgnj when (in.bits.wflags) { // fmin/fmax val isnan1 = maxType.isNaN(in.bits.in1) val isnan2 = maxType.isNaN(in.bits.in2) val isInvalid = maxType.isSNaN(in.bits.in1) \|\| maxType.isSNaN(in.bits.in2) val isNaNOut = isnan1 && isnan2 val isLHS = isnan2 \|\| in.bits.rm(0) =/= io.lt && !isnan1 fsgnjMux.exc := isInvalid << 4 fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2)) } val inTag = in.bits.typeTagIn val outTag = in.bits.typeTagOut val mux = WireDefault(fsgnjMux) for (t <- floatTypes.init) { when (outTag === typeTag(t).U) { mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t)) } } when (in.bits.wflags && !in.bits.ren2) { // fcvt if (floatTypes.size > 1) { // widening conversions simply canonicalize NaN operands val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1) fsgnjMux.data := widened fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4 // narrowing conversions require rounding (for RVQ, this could be // optimized to use a single variable-position rounding unit, rather // than two fixed-position ones) for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B \|\| outTag < inTag)) { val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig)) narrower.io.in := in.bits.in1 narrower.io.roundingMode := in.bits.rm narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding val narrowed = sanitizeNaN(narrower.io.out, outType) mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed) mux.exc := narrower.io.exceptionFlags } } } io.out <> Pipe(in.valid, mux, latency-1) } class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module { override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}" require(latency<=2) val io = IO(new Bundle { val validin = Input(Bool()) val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) val validout = Output(Bool()) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC val valid_stage0 = Wire(Bool()) val roundingMode_stage0 = Wire(UInt(3.W)) val detectTininess_stage0 = Wire(UInt(1.W)) val postmul_regs = if(latency>0) 1 else 0 mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0)) val round_regs = if(latency==2) 1 else 0 roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits io.validout := Pipe(valid_stage0, false.B, round_regs).valid roundRawFNToRecFN.io.infiniteExc := false.B io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } class FPUFMAPipe(val latency: Int, val t: FType) (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}" require(latency>0) val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) }) val valid = RegNext(io.in.valid) val in = Reg(new FPInput) when (io.in.valid) { val one = 1.U << (t.sig + t.exp - 1) val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp)) val cmd_fma = io.in.bits.ren3 val cmd_addsub = io.in.bits.swap23 in := io.in.bits when (cmd_addsub) { in.in2 := one } when (!(cmd_fma \|\| cmd_addsub)) { in.in3 := zero } } val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig)) fma.io.validin := valid fma.io.op := in.fmaCmd fma.io.roundingMode := in.rm fma.io.detectTininess := hardfloat.consts.tininess_afterRounding fma.io.a := in.in1 fma.io.b := in.in2 fma.io.c := in.in3 val res = Wire(new FPResult) res.data := sanitizeNaN(fma.io.out, t) res.exc := fma.io.exceptionFlags io.out := Pipe(fma.io.validout, res, (latency-3) max 0) } class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new FPUIO) val (useClockGating, useDebugROB) = coreParams match { case r: RocketCoreParams => val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1 (r.clockGate, sz < 1) case _ => (false, false) } val clock_en_reg = Reg(Bool()) val clock_en = clock_en_reg \|\| io.cp_req.valid val gated_clock = if (!useClockGating) clock else ClockGate(clock, clock_en, "fpu_clock_gate") val fp_decoder = Module(new FPUDecoder) fp_decoder.io.inst := io.inst val id_ctrl = WireInit(fp_decoder.io.sigs) coreParams match { case r: RocketCoreParams => r.vector.map(v => { val v_decode = v.decoder(p) // Only need to get ren1 v_decode.io.inst := io.inst v_decode.io.vconfig := DontCare // core deals with this when (v_decode.io.legal && v_decode.io.read_frs1) { id_ctrl.ren1 := true.B id_ctrl.swap12 := false.B id_ctrl.toint := true.B id_ctrl.typeTagIn := I id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S) } when (v_decode.io.write_frd) { id_ctrl.wen := true.B } })} val ex_reg_valid = RegNext(io.valid, false.B) val ex_reg_inst = RegEnable(io.inst, io.valid) val ex_reg_ctrl = RegEnable(id_ctrl, io.valid) val ex_ra = List.fill(3)(Reg(UInt())) // load/vector response val load_wb = RegNext(io.ll_resp_val) val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val) val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val) val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val) class FPUImpl { // entering gated-clock domain val req_valid = ex_reg_valid \|\| io.cp_req.valid val ex_cp_valid = io.cp_req.fire val mem_cp_valid = RegNext(ex_cp_valid, false.B) val wb_cp_valid = RegNext(mem_cp_valid, false.B) val mem_reg_valid = RegInit(false.B) val killm = (io.killm \|\| io.nack_mem) && !mem_cp_valid // Kill X-stage instruction if M-stage is killed. This prevents it from // speculatively being sent to the div-sqrt unit, which can cause priority // inversion for two back-to-back divides, the first of which is killed. val killx = io.killx \|\| mem_reg_valid && killm mem_reg_valid := ex_reg_valid && !killx \|\| ex_cp_valid val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid) val wb_reg_valid = RegNext(mem_reg_valid && (!killm \|\| mem_cp_valid), false.B) val cp_ctrl = Wire(new FPUCtrlSigs) cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs) io.cp_resp.valid := false.B io.cp_resp.bits.data := 0.U io.cp_resp.bits.exc := DontCare val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl) val mem_ctrl = RegEnable(ex_ctrl, req_valid) val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid) // CoreMonitorBundle to monitor fp register file writes val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare)) frfWriteBundle.foreach { i => i.clock := clock i.reset := reset i.hartid := io.hartid i.timer := io.time(31,0) i.valid := false.B i.wrenx := false.B i.wrenf := false.B i.excpt := false.B } // regfile val regfile = Mem(32, Bits((fLen+1).W)) when (load_wb) { val wdata = recode(load_wb_data, load_wb_typeTag) regfile(load_wb_tag) := wdata assert(consistent(wdata)) if (enableCommitLog) printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata)) if (useDebugROB) DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata)) frfWriteBundle(0).wrdst := load_wb_tag frfWriteBundle(0).wrenf := true.B frfWriteBundle(0).wrdata := ieee(wdata) } val ex_rs = ex_ra.map(a => regfile(a)) when (io.valid) { when (id_ctrl.ren1) { when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) } when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) } } when (id_ctrl.ren2) { when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) } when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) } when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) } } when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) } } val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12)) def fuInput(minT: Option[FType]): FPInput = { val req = Wire(new FPInput) val tag = ex_ctrl.typeTagIn req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs) req.rm := ex_rm req.in1 := unbox(ex_rs(0), tag, minT) req.in2 := unbox(ex_rs(1), tag, minT) req.in3 := unbox(ex_rs(2), tag, minT) req.typ := ex_reg_inst(21,20) req.fmt := ex_reg_inst(26,25) req.fmaCmd := ex_reg_inst(3,2) \| (!ex_ctrl.ren3 && ex_reg_inst(27)) when (ex_cp_valid) { req := io.cp_req.bits when (io.cp_req.bits.swap12) { req.in1 := io.cp_req.bits.in2 req.in2 := io.cp_req.bits.in1 } when (io.cp_req.bits.swap23) { req.in2 := io.cp_req.bits.in3 req.in3 := io.cp_req.bits.in2 } } req } val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S)) sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S sfma.io.in.bits := fuInput(Some(sfma.t)) val fpiu = Module(new FPToInt) fpiu.io.in.valid := req_valid && (ex_ctrl.toint \|\| ex_ctrl.div \|\| ex_ctrl.sqrt \|\| (ex_ctrl.fastpipe && ex_ctrl.wflags)) fpiu.io.in.bits := fuInput(None) io.store_data := fpiu.io.out.bits.store io.toint_data := fpiu.io.out.bits.toint when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){ io.cp_resp.bits.data := fpiu.io.out.bits.toint io.cp_resp.valid := true.B } val ifpu = Module(new IntToFP(cfg.ifpuLatency)) ifpu.io.in.valid := req_valid && ex_ctrl.fromint ifpu.io.in.bits := fpiu.io.in.bits ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) val fpmu = Module(new FPToFP(cfg.fpmuLatency)) fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe fpmu.io.in.bits := fpiu.io.in.bits fpmu.io.lt := fpiu.io.out.bits.lt val divSqrt_wen = WireDefault(false.B) val divSqrt_inFlight = WireDefault(false.B) val divSqrt_waddr = Reg(UInt(5.W)) val divSqrt_cp = Reg(Bool()) val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W)) val divSqrt_wdata = Wire(UInt((fLen+1).W)) val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W)) divSqrt_typeTag := DontCare divSqrt_wdata := DontCare divSqrt_flags := DontCare // writeback arbitration case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult) val pipes = List( Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits), Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits), Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++ (fLen > 32).option({ val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D)) dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D dfma.io.in.bits := fuInput(Some(dfma.t)) Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits) }) ++ (minFLen == 16).option({ val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H)) hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H hfma.io.in.bits := fuInput(Some(hfma.t)) Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits) }) def latencyMask(c: FPUCtrlSigs, offset: Int) = { require(pipes.forall(_.lat >= offset)) pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_\|_) } def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_\|_) val maxLatency = pipes.map(_.lat).max val memLatencyMask = latencyMask(mem_ctrl, 2) class WBInfo extends Bundle { val rd = UInt(5.W) val typeTag = UInt(log2Up(floatTypes.size).W) val cp = Bool() val pipeid = UInt(log2Ceil(pipes.size).W) } val wen = RegInit(0.U((maxLatency-1).W)) val wbInfo = Reg(Vec(maxLatency-1, new WBInfo)) val mem_wen = mem_reg_valid && (mem_ctrl.fma \|\| mem_ctrl.fastpipe \|\| mem_ctrl.fromint) val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR \|\| (wen & latencyMask(ex_ctrl, 0)).orR, req_valid) ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback") for (i <- 0 until maxLatency-2) { when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) } } wen := wen >> 1 when (mem_wen) { when (!killm) { wen := wen >> 1 \| memLatencyMask } for (i <- 0 until maxLatency-1) { when (!write_port_busy && memLatencyMask(i)) { wbInfo(i).cp := mem_cp_valid wbInfo(i).typeTag := mem_ctrl.typeTagOut wbInfo(i).pipeid := pipeid(mem_ctrl) wbInfo(i).rd := mem_reg_inst(11,7) } } } val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd) val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp) val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag) val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag) val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid) when ((!wbInfo(0).cp && wen(0)) \|\| divSqrt_wen) { assert(consistent(wdata)) regfile(waddr) := wdata if (enableCommitLog) { printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata)) } frfWriteBundle(1).wrdst := waddr frfWriteBundle(1).wrenf := true.B frfWriteBundle(1).wrdata := ieee(wdata) } if (useDebugROB) { DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) \|\| divSqrt_wen, waddr + 32.U, ieee(wdata)) } when (wb_cp && (wen(0) \|\| divSqrt_wen)) { io.cp_resp.bits.data := wdata io.cp_resp.valid := true.B } assert(!io.cp_req.valid \|\| pipes.forall(_.lat == pipes.head.lat).B, s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}") // Avoid structural hazards and nacking of external requests // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight val wb_toint_valid = wb_reg_valid && wb_ctrl.toint val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint) io.fcsr_flags.valid := wb_toint_valid \|\| divSqrt_wen \|\| wen(0) io.fcsr_flags.bits := Mux(wb_toint_valid, wb_toint_exc, 0.U) \| Mux(divSqrt_wen, divSqrt_flags, 0.U) \| Mux(wen(0), wexc, 0.U) val divSqrt_write_port_busy = (mem_ctrl.div \|\| mem_ctrl.sqrt) && wen.orR io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags \|\| mem_reg_valid && mem_ctrl.wflags \|\| wb_reg_valid && wb_ctrl.toint \|\| wen.orR \|\| divSqrt_inFlight) io.nack_mem := (write_port_busy \|\| divSqrt_write_port_busy \|\| divSqrt_inFlight) && !mem_cp_valid io.dec <> id_ctrl def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_\|\|_) io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) \|\| mem_ctrl.div \|\| mem_ctrl.sqrt \|\| mem_ctrl.vec) io.sboard_clr := !wb_cp_valid && (divSqrt_wen \|\| (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U))) io.sboard_clra := waddr ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle") // we don't currently support round-max-magnitude (rm=4) io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) \|\| io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U if (cfg.divSqrt) { val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div \|\| mem_ctrl.sqrt) && !divSqrt_inFlight val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B) when (divSqrt_inValid) { divSqrt_waddr := mem_reg_inst(11,7) divSqrt_cp := mem_cp_valid } ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider") ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div \|\| mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard") ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback") for (t <- floatTypes) { val tag = mem_ctrl.typeTagOut val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) } divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U divSqrt.io.sqrtOp := mem_ctrl.sqrt divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t) divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t) divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight when (divSqrt.io.outValid_div \|\| divSqrt.io.outValid_sqrt) { divSqrt_wen := !divSqrt_killed divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t) divSqrt_flags := divSqrt.io.exceptionFlags divSqrt_typeTag := typeTag(t).U } } when (divSqrt_killed) { divSqrt_inFlight := false.B } } else { when (id_ctrl.div \|\| id_ctrl.sqrt) { io.illegal_rm := true.B } } // gate the clock clock_en_reg := !useClockGating.B \|\| io.keep_clock_enabled \|\| // chicken bit io.valid \|\| // ID stage req_valid \|\| // EX stage mem_reg_valid \|\| mem_cp_valid \|\| // MEM stage wb_reg_valid \|\| wb_cp_valid \|\| // WB stage wen.orR \|\| divSqrt_inFlight \|\| // post-WB stage io.ll_resp_val // load writeback } // leaving gated-clock domain val fpuImpl = withClock (gated_clock) { new FPUImpl } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"FPU_$label", "Core;;" + desc) }	module FPToFP_2( // @[FPU.scala:573:7] input clock, // @[FPU.scala:573:7] input reset, // @[FPU.scala:573:7] input io_in_valid, // @[FPU.scala:574:14] input io_in_bits_ldst, // @[FPU.scala:574:14] input io_in_bits_wen, // @[FPU.scala:574:14] input io_in_bits_ren1, // @[FPU.scala:574:14] input io_in_bits_ren2, // @[FPU.scala:574:14] input io_in_bits_ren3, // @[FPU.scala:574:14] input io_in_bits_swap12, // @[FPU.scala:574:14] input io_in_bits_swap23, // @[FPU.scala:574:14] input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:574:14] input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:574:14] input io_in_bits_fromint, // @[FPU.scala:574:14] input io_in_bits_toint, // @[FPU.scala:574:14] input io_in_bits_fastpipe, // @[FPU.scala:574:14] input io_in_bits_fma, // @[FPU.scala:574:14] input io_in_bits_div, // @[FPU.scala:574:14] input io_in_bits_sqrt, // @[FPU.scala:574:14] input io_in_bits_wflags, // @[FPU.scala:574:14] input io_in_bits_vec, // @[FPU.scala:574:14] input [2:0] io_in_bits_rm, // @[FPU.scala:574:14] input [1:0] io_in_bits_fmaCmd, // @[FPU.scala:574:14] input [1:0] io_in_bits_typ, // @[FPU.scala:574:14] input [1:0] io_in_bits_fmt, // @[FPU.scala:574:14] input [64:0] io_in_bits_in1, // @[FPU.scala:574:14] input [64:0] io_in_bits_in2, // @[FPU.scala:574:14] input [64:0] io_in_bits_in3, // @[FPU.scala:574:14] output [64:0] io_out_bits_data, // @[FPU.scala:574:14] output [4:0] io_out_bits_exc, // @[FPU.scala:574:14] input io_lt // @[FPU.scala:574:14] ); wire [32:0] _narrower_1_io_out; // @[FPU.scala:619:30] wire [4:0] _narrower_1_io_exceptionFlags; // @[FPU.scala:619:30] wire [16:0] _narrower_io_out; // @[FPU.scala:619:30] wire [4:0] _narrower_io_exceptionFlags; // @[FPU.scala:619:30] wire io_in_valid_0 = io_in_valid; // @[FPU.scala:573:7] wire io_in_bits_ldst_0 = io_in_bits_ldst; // @[FPU.scala:573:7] wire io_in_bits_wen_0 = io_in_bits_wen; // @[FPU.scala:573:7] wire io_in_bits_ren1_0 = io_in_bits_ren1; // @[FPU.scala:573:7] wire io_in_bits_ren2_0 = io_in_bits_ren2; // @[FPU.scala:573:7] wire io_in_bits_ren3_0 = io_in_bits_ren3; // @[FPU.scala:573:7] wire io_in_bits_swap12_0 = io_in_bits_swap12; // @[FPU.scala:573:7] wire io_in_bits_swap23_0 = io_in_bits_swap23; // @[FPU.scala:573:7] wire [1:0] io_in_bits_typeTagIn_0 = io_in_bits_typeTagIn; // @[FPU.scala:573:7] wire [1:0] io_in_bits_typeTagOut_0 = io_in_bits_typeTagOut; // @[FPU.scala:573:7] wire io_in_bits_fromint_0 = io_in_bits_fromint; // @[FPU.scala:573:7] wire io_in_bits_toint_0 = io_in_bits_toint; // @[FPU.scala:573:7] wire io_in_bits_fastpipe_0 = io_in_bits_fastpipe; // @[FPU.scala:573:7] wire io_in_bits_fma_0 = io_in_bits_fma; // @[FPU.scala:573:7] wire io_in_bits_div_0 = io_in_bits_div; // @[FPU.scala:573:7] wire io_in_bits_sqrt_0 = io_in_bits_sqrt; // @[FPU.scala:573:7] wire io_in_bits_wflags_0 = io_in_bits_wflags; // @[FPU.scala:573:7] wire io_in_bits_vec_0 = io_in_bits_vec; // @[FPU.scala:573:7] wire [2:0] io_in_bits_rm_0 = io_in_bits_rm; // @[FPU.scala:573:7] wire [1:0] io_in_bits_fmaCmd_0 = io_in_bits_fmaCmd; // @[FPU.scala:573:7] wire [1:0] io_in_bits_typ_0 = io_in_bits_typ; // @[FPU.scala:573:7] wire [1:0] io_in_bits_fmt_0 = io_in_bits_fmt; // @[FPU.scala:573:7] wire [64:0] io_in_bits_in1_0 = io_in_bits_in1; // @[FPU.scala:573:7] wire [64:0] io_in_bits_in2_0 = io_in_bits_in2; // @[FPU.scala:573:7] wire [64:0] io_in_bits_in3_0 = io_in_bits_in3; // @[FPU.scala:573:7] wire io_lt_0 = io_lt; // @[FPU.scala:573:7] wire [32:0] _narrowed_maskedNaN_T = 33'h1EF7FFFFF; // @[FPU.scala:413:27] wire io_out_pipe_out_valid; // @[Valid.scala:135:21] wire [64:0] io_out_pipe_out_bits_data; // @[Valid.scala:135:21] wire [4:0] io_out_pipe_out_bits_exc; // @[Valid.scala:135:21] wire [64:0] io_out_bits_data_0; // @[FPU.scala:573:7] wire [4:0] io_out_bits_exc_0; // @[FPU.scala:573:7] wire io_out_valid; // @[FPU.scala:573:7] reg in_pipe_v; // @[Valid.scala:141:24] wire in_valid = in_pipe_v; // @[Valid.scala:135:21, :141:24] reg in_pipe_b_ldst; // @[Valid.scala:142:26] wire in_bits_ldst = in_pipe_b_ldst; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_wen; // @[Valid.scala:142:26] wire in_bits_wen = in_pipe_b_wen; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_ren1; // @[Valid.scala:142:26] wire in_bits_ren1 = in_pipe_b_ren1; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_ren2; // @[Valid.scala:142:26] wire in_bits_ren2 = in_pipe_b_ren2; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_ren3; // @[Valid.scala:142:26] wire in_bits_ren3 = in_pipe_b_ren3; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_swap12; // @[Valid.scala:142:26] wire in_bits_swap12 = in_pipe_b_swap12; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_swap23; // @[Valid.scala:142:26] wire in_bits_swap23 = in_pipe_b_swap23; // @[Valid.scala:135:21, :142:26] reg [1:0] in_pipe_b_typeTagIn; // @[Valid.scala:142:26] wire [1:0] in_bits_typeTagIn = in_pipe_b_typeTagIn; // @[Valid.scala:135:21, :142:26] reg [1:0] in_pipe_b_typeTagOut; // @[Valid.scala:142:26] wire [1:0] in_bits_typeTagOut = in_pipe_b_typeTagOut; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_fromint; // @[Valid.scala:142:26] wire in_bits_fromint = in_pipe_b_fromint; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_toint; // @[Valid.scala:142:26] wire in_bits_toint = in_pipe_b_toint; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_fastpipe; // @[Valid.scala:142:26] wire in_bits_fastpipe = in_pipe_b_fastpipe; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_fma; // @[Valid.scala:142:26] wire in_bits_fma = in_pipe_b_fma; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_div; // @[Valid.scala:142:26] wire in_bits_div = in_pipe_b_div; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_sqrt; // @[Valid.scala:142:26] wire in_bits_sqrt = in_pipe_b_sqrt; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_wflags; // @[Valid.scala:142:26] wire in_bits_wflags = in_pipe_b_wflags; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_vec; // @[Valid.scala:142:26] wire in_bits_vec = in_pipe_b_vec; // @[Valid.scala:135:21, :142:26] reg [2:0] in_pipe_b_rm; // @[Valid.scala:142:26] wire [2:0] in_bits_rm = in_pipe_b_rm; // @[Valid.scala:135:21, :142:26] reg [1:0] in_pipe_b_fmaCmd; // @[Valid.scala:142:26] wire [1:0] in_bits_fmaCmd = in_pipe_b_fmaCmd; // @[Valid.scala:135:21, :142:26] reg [1:0] in_pipe_b_typ; // @[Valid.scala:142:26] wire [1:0] in_bits_typ = in_pipe_b_typ; // @[Valid.scala:135:21, :142:26] reg [1:0] in_pipe_b_fmt; // @[Valid.scala:142:26] wire [1:0] in_bits_fmt = in_pipe_b_fmt; // @[Valid.scala:135:21, :142:26] reg [64:0] in_pipe_b_in1; // @[Valid.scala:142:26] wire [64:0] in_bits_in1 = in_pipe_b_in1; // @[Valid.scala:135:21, :142:26] reg [64:0] in_pipe_b_in2; // @[Valid.scala:142:26] wire [64:0] in_bits_in2 = in_pipe_b_in2; // @[Valid.scala:135:21, :142:26] reg [64:0] in_pipe_b_in3; // @[Valid.scala:142:26] wire [64:0] in_bits_in3 = in_pipe_b_in3; // @[Valid.scala:135:21, :142:26] wire _signNum_T = in_bits_rm[1]; // @[Valid.scala:135:21] wire [64:0] _signNum_T_1 = in_bits_in1 ^ in_bits_in2; // @[Valid.scala:135:21] wire _signNum_T_2 = in_bits_rm[0]; // @[Valid.scala:135:21] wire _isLHS_T = in_bits_rm[0]; // @[Valid.scala:135:21] wire [64:0] _signNum_T_3 = ~in_bits_in2; // @[Valid.scala:135:21] wire [64:0] _signNum_T_4 = _signNum_T_2 ? _signNum_T_3 : in_bits_in2; // @[Valid.scala:135:21] wire [64:0] signNum = _signNum_T ? _signNum_T_1 : _signNum_T_4; // @[FPU.scala:582:{20,31,48,66}] wire _fsgnj_T = signNum[64]; // @[FPU.scala:582:20, :583:26] wire [63:0] _fsgnj_T_1 = in_bits_in1[63:0]; // @[Valid.scala:135:21] wire [64:0] fsgnj = {_fsgnj_T, _fsgnj_T_1}; // @[FPU.scala:583:{18,26,45}] wire [64:0] fsgnjMux_data; // @[FPU.scala:585:22] wire [4:0] fsgnjMux_exc; // @[FPU.scala:585:22] wire [2:0] _isnan1_T = in_bits_in1[63:61]; // @[Valid.scala:135:21] wire [2:0] _isInvalid_T = in_bits_in1[63:61]; // @[Valid.scala:135:21] wire [2:0] _widened_T = in_bits_in1[63:61]; // @[Valid.scala:135:21] wire [2:0] _fsgnjMux_exc_T_1 = in_bits_in1[63:61]; // @[Valid.scala:135:21] wire isnan1 = &_isnan1_T; // @[FPU.scala:249:{25,56}] wire [2:0] _isnan2_T = in_bits_in2[63:61]; // @[Valid.scala:135:21] wire [2:0] _isInvalid_T_5 = in_bits_in2[63:61]; // @[Valid.scala:135:21] wire isnan2 = &_isnan2_T; // @[FPU.scala:249:{25,56}] wire _isInvalid_T_1 = &_isInvalid_T; // @[FPU.scala:249:{25,56}] wire _isInvalid_T_2 = in_bits_in1[51]; // @[Valid.scala:135:21] wire _fsgnjMux_exc_T_3 = in_bits_in1[51]; // @[Valid.scala:135:21] wire _isInvalid_T_3 = ~_isInvalid_T_2; // @[FPU.scala:250:{37,39}] wire _isInvalid_T_4 = _isInvalid_T_1 & _isInvalid_T_3; // @[FPU.scala:249:56, :250:{34,37}] wire _isInvalid_T_6 = &_isInvalid_T_5; // @[FPU.scala:249:{25,56}] wire _isInvalid_T_7 = in_bits_in2[51]; // @[Valid.scala:135:21] wire _isInvalid_T_8 = ~_isInvalid_T_7; // @[FPU.scala:250:{37,39}] wire _isInvalid_T_9 = _isInvalid_T_6 & _isInvalid_T_8; // @[FPU.scala:249:56, :250:{34,37}] wire isInvalid = _isInvalid_T_4 \| _isInvalid_T_9; // @[FPU.scala:250:34, :592:49] wire isNaNOut = isnan1 & isnan2; // @[FPU.scala:249:56, :593:27] wire _isLHS_T_1 = _isLHS_T != io_lt_0; // @[FPU.scala:573:7, :594:{37,41}] wire _isLHS_T_2 = ~isnan1; // @[FPU.scala:249:56, :594:54] wire _isLHS_T_3 = _isLHS_T_1 & _isLHS_T_2; // @[FPU.scala:594:{41,51,54}] wire isLHS = isnan2 \| _isLHS_T_3; // @[FPU.scala:249:56, :594:{24,51}] wire [4:0] _fsgnjMux_exc_T = {isInvalid, 4'h0}; // @[FPU.scala:592:49, :595:31] wire [64:0] _fsgnjMux_data_T = isLHS ? in_bits_in1 : in_bits_in2; // @[Valid.scala:135:21] wire [64:0] _fsgnjMux_data_T_1 = isNaNOut ? 65'hE008000000000000 : _fsgnjMux_data_T; // @[FPU.scala:593:27, :596:{25,53}] wire [64:0] mux_data; // @[FPU.scala:601:24] wire [4:0] mux_exc; // @[FPU.scala:601:24] wire _T_7 = in_bits_typeTagOut == 2'h0; // @[Valid.scala:135:21] wire [47:0] _mux_data_T = fsgnjMux_data[64:17]; // @[FPU.scala:585:22, :604:37] wire [47:0] _mux_data_T_6 = fsgnjMux_data[64:17]; // @[FPU.scala:585:22, :604:37, :624:39] wire mux_data_sign = fsgnjMux_data[64]; // @[FPU.scala:274:17, :585:22] wire mux_data_sign_1 = fsgnjMux_data[64]; // @[FPU.scala:274:17, :585:22] wire [51:0] mux_data_fractIn = fsgnjMux_data[51:0]; // @[FPU.scala:275:20, :585:22] wire [51:0] mux_data_fractIn_1 = fsgnjMux_data[51:0]; // @[FPU.scala:275:20, :585:22] wire [11:0] mux_data_expIn = fsgnjMux_data[63:52]; // @[FPU.scala:276:18, :585:22] wire [11:0] mux_data_expIn_1 = fsgnjMux_data[63:52]; // @[FPU.scala:276:18, :585:22] wire [62:0] _mux_data_fractOut_T = {mux_data_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28] wire [9:0] mux_data_fractOut = _mux_data_fractOut_T[62:53]; // @[FPU.scala:277:{28,38}] wire [2:0] mux_data_expOut_expCode = mux_data_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _mux_data_expOut_commonCase_T = {1'h0, mux_data_expIn} + 13'h20; // @[FPU.scala:276:18, :280:31] wire [11:0] _mux_data_expOut_commonCase_T_1 = _mux_data_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _mux_data_expOut_commonCase_T_2 = {1'h0, _mux_data_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] mux_data_expOut_commonCase = _mux_data_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _mux_data_expOut_T = mux_data_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _mux_data_expOut_T_1 = mux_data_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _mux_data_expOut_T_2 = _mux_data_expOut_T \| _mux_data_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [2:0] _mux_data_expOut_T_3 = mux_data_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69] wire [5:0] _mux_data_expOut_T_4 = {mux_data_expOut_expCode, _mux_data_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [5:0] _mux_data_expOut_T_5 = mux_data_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97] wire [5:0] mux_data_expOut = _mux_data_expOut_T_2 ? _mux_data_expOut_T_4 : _mux_data_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [6:0] mux_data_hi = {mux_data_sign, mux_data_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [16:0] _mux_data_T_1 = {mux_data_hi, mux_data_fractOut}; // @[FPU.scala:277:38, :283:8] wire [64:0] _mux_data_T_2 = {_mux_data_T, _mux_data_T_1}; // @[FPU.scala:283:8, :604:{22,37}] wire _T_8 = in_bits_typeTagOut == 2'h1; // @[Valid.scala:135:21] wire [31:0] _mux_data_T_3 = fsgnjMux_data[64:33]; // @[FPU.scala:585:22, :604:37] wire [31:0] _mux_data_T_8 = fsgnjMux_data[64:33]; // @[FPU.scala:585:22, :604:37, :624:39] wire [75:0] _mux_data_fractOut_T_1 = {mux_data_fractIn_1, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] mux_data_fractOut_1 = _mux_data_fractOut_T_1[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] mux_data_expOut_expCode_1 = mux_data_expIn_1[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _mux_data_expOut_commonCase_T_3 = {1'h0, mux_data_expIn_1} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _mux_data_expOut_commonCase_T_4 = _mux_data_expOut_commonCase_T_3[11:0]; // @[FPU.scala:280:31] wire [12:0] _mux_data_expOut_commonCase_T_5 = {1'h0, _mux_data_expOut_commonCase_T_4} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] mux_data_expOut_commonCase_1 = _mux_data_expOut_commonCase_T_5[11:0]; // @[FPU.scala:280:50] wire _mux_data_expOut_T_6 = mux_data_expOut_expCode_1 == 3'h0; // @[FPU.scala:279:26, :281:19] wire _mux_data_expOut_T_7 = mux_data_expOut_expCode_1 > 3'h5; // @[FPU.scala:279:26, :281:38] wire _mux_data_expOut_T_8 = _mux_data_expOut_T_6 \| _mux_data_expOut_T_7; // @[FPU.scala:281:{19,27,38}] wire [5:0] _mux_data_expOut_T_9 = mux_data_expOut_commonCase_1[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _mux_data_expOut_T_10 = {mux_data_expOut_expCode_1, _mux_data_expOut_T_9}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _mux_data_expOut_T_11 = mux_data_expOut_commonCase_1[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] mux_data_expOut_1 = _mux_data_expOut_T_8 ? _mux_data_expOut_T_10 : _mux_data_expOut_T_11; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] mux_data_hi_1 = {mux_data_sign_1, mux_data_expOut_1}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] _mux_data_T_4 = {mux_data_hi_1, mux_data_fractOut_1}; // @[FPU.scala:277:38, :283:8] wire [64:0] _mux_data_T_5 = {_mux_data_T_3, _mux_data_T_4}; // @[FPU.scala:283:8, :604:{22,37}] wire _T_3 = in_bits_wflags & ~in_bits_ren2; // @[Valid.scala:135:21] wire _widened_T_1 = &_widened_T; // @[FPU.scala:249:{25,56}] wire [64:0] widened = _widened_T_1 ? 65'hE008000000000000 : in_bits_in1; // @[Valid.scala:135:21] assign fsgnjMux_data = _T_3 ? widened : in_bits_wflags ? _fsgnjMux_data_T_1 : fsgnj; // @[Valid.scala:135:21] wire _fsgnjMux_exc_T_2 = &_fsgnjMux_exc_T_1; // @[FPU.scala:249:{25,56}] wire _fsgnjMux_exc_T_4 = ~_fsgnjMux_exc_T_3; // @[FPU.scala:250:{37,39}] wire _fsgnjMux_exc_T_5 = _fsgnjMux_exc_T_2 & _fsgnjMux_exc_T_4; // @[FPU.scala:249:56, :250:{34,37}] wire [4:0] _fsgnjMux_exc_T_6 = {_fsgnjMux_exc_T_5, 4'h0}; // @[FPU.scala:250:34, :595:31, :613:51] assign fsgnjMux_exc = _T_3 ? _fsgnjMux_exc_T_6 : in_bits_wflags ? _fsgnjMux_exc_T : 5'h0; // @[Valid.scala:135:21] wire [64:0] _mux_data_T_7 = {_mux_data_T_6, _narrower_io_out}; // @[FPU.scala:619:30, :624:{24,39}] wire _T_11 = _T_8 & in_bits_typeTagOut < in_bits_typeTagIn; // @[Valid.scala:135:21] wire [32:0] narrowed_maskedNaN = _narrower_1_io_out & 33'h1EF7FFFFF; // @[FPU.scala:413:25, :619:30] wire [2:0] _narrowed_T = _narrower_1_io_out[31:29]; // @[FPU.scala:249:25, :619:30] wire _narrowed_T_1 = &_narrowed_T; // @[FPU.scala:249:{25,56}] wire [32:0] narrowed = _narrowed_T_1 ? narrowed_maskedNaN : _narrower_1_io_out; // @[FPU.scala:249:56, :413:25, :414:10, :619:30] wire [64:0] _mux_data_T_9 = {_mux_data_T_8, narrowed}; // @[FPU.scala:414:10, :624:{24,39}] assign mux_data = _T_3 ? (_T_11 ? _mux_data_T_9 : _T_7 ? _mux_data_T_7 : _T_8 ? _mux_data_T_5 : fsgnjMux_data) : _T_8 ? _mux_data_T_5 : _T_7 ? _mux_data_T_2 : fsgnjMux_data; // @[FPU.scala:585:22, :601:24, :603:{18,36}, :604:{16,22}, :608:{24,42}, :618:{76,126}, :624:{18,24}] assign mux_exc = _T_3 ? (_T_11 ? _narrower_1_io_exceptionFlags : _T_7 ? _narrower_io_exceptionFlags : fsgnjMux_exc) : fsgnjMux_exc; // @[FPU.scala:585:22, :601:24, :603:18, :608:{24,42}, :618:{76,126}, :619:30, :625:17] reg io_out_pipe_v; // @[Valid.scala:141:24] assign io_out_pipe_out_valid = io_out_pipe_v; // @[Valid.scala:135:21, :141:24] reg [64:0] io_out_pipe_b_data; // @[Valid.scala:142:26] assign io_out_pipe_out_bits_data = io_out_pipe_b_data; // @[Valid.scala:135:21, :142:26] reg [4:0] io_out_pipe_b_exc; // @[Valid.scala:142:26] assign io_out_pipe_out_bits_exc = io_out_pipe_b_exc; // @[Valid.scala:135:21, :142:26] assign io_out_valid = io_out_pipe_out_valid; // @[Valid.scala:135:21] assign io_out_bits_data_0 = io_out_pipe_out_bits_data; // @[Valid.scala:135:21] assign io_out_bits_exc_0 = io_out_pipe_out_bits_exc; // @[Valid.scala:135:21] always @(posedge clock) begin // @[FPU.scala:573:7] if (reset) begin // @[FPU.scala:573:7] in_pipe_v <= 1'h0; // @[Valid.scala:141:24] io_out_pipe_v <= 1'h0; // @[Valid.scala:141:24] end else begin // @[FPU.scala:573:7] in_pipe_v <= io_in_valid_0; // @[Valid.scala:141:24] io_out_pipe_v <= in_valid; // @[Valid.scala:135:21, :141:24] end if (io_in_valid_0) begin // @[FPU.scala:573:7] in_pipe_b_ldst <= io_in_bits_ldst_0; // @[Valid.scala:142:26] in_pipe_b_wen <= io_in_bits_wen_0; // @[Valid.scala:142:26] in_pipe_b_ren1 <= io_in_bits_ren1_0; // @[Valid.scala:142:26] in_pipe_b_ren2 <= io_in_bits_ren2_0; // @[Valid.scala:142:26] in_pipe_b_ren3 <= io_in_bits_ren3_0; // @[Valid.scala:142:26] in_pipe_b_swap12 <= io_in_bits_swap12_0; // @[Valid.scala:142:26] in_pipe_b_swap23 <= io_in_bits_swap23_0; // @[Valid.scala:142:26] in_pipe_b_typeTagIn <= io_in_bits_typeTagIn_0; // @[Valid.scala:142:26] in_pipe_b_typeTagOut <= io_in_bits_typeTagOut_0; // @[Valid.scala:142:26] in_pipe_b_fromint <= io_in_bits_fromint_0; // @[Valid.scala:142:26] in_pipe_b_toint <= io_in_bits_toint_0; // @[Valid.scala:142:26] in_pipe_b_fastpipe <= io_in_bits_fastpipe_0; // @[Valid.scala:142:26] in_pipe_b_fma <= io_in_bits_fma_0; // @[Valid.scala:142:26] in_pipe_b_div <= io_in_bits_div_0; // @[Valid.scala:142:26] in_pipe_b_sqrt <= io_in_bits_sqrt_0; // @[Valid.scala:142:26] in_pipe_b_wflags <= io_in_bits_wflags_0; // @[Valid.scala:142:26] in_pipe_b_vec <= io_in_bits_vec_0; // @[Valid.scala:142:26] in_pipe_b_rm <= io_in_bits_rm_0; // @[Valid.scala:142:26] in_pipe_b_fmaCmd <= io_in_bits_fmaCmd_0; // @[Valid.scala:142:26] in_pipe_b_typ <= io_in_bits_typ_0; // @[Valid.scala:142:26] in_pipe_b_fmt <= io_in_bits_fmt_0; // @[Valid.scala:142:26] in_pipe_b_in1 <= io_in_bits_in1_0; // @[Valid.scala:142:26] in_pipe_b_in2 <= io_in_bits_in2_0; // @[Valid.scala:142:26] in_pipe_b_in3 <= io_in_bits_in3_0; // @[Valid.scala:142:26] end if (in_valid) begin // @[Valid.scala:135:21] io_out_pipe_b_data <= mux_data; // @[Valid.scala:142:26] io_out_pipe_b_exc <= mux_exc; // @[Valid.scala:142:26] end always @(posedge) RecFNToRecFN_4 narrower ( // @[FPU.scala:619:30] .io_in (in_bits_in1), // @[Valid.scala:135:21] .io_roundingMode (in_bits_rm), // @[Valid.scala:135:21] .io_out (_narrower_io_out), .io_exceptionFlags (_narrower_io_exceptionFlags) ); // @[FPU.scala:619:30] RecFNToRecFN_5 narrower_1 ( // @[FPU.scala:619:30] .io_in (in_bits_in1), // @[Valid.scala:135:21] .io_roundingMode (in_bits_rm), // @[Valid.scala:135:21] .io_out (_narrower_1_io_out), .io_exceptionFlags (_narrower_1_io_exceptionFlags) ); // @[FPU.scala:619:30] assign io_out_bits_data = io_out_bits_data_0; // @[FPU.scala:573:7] assign io_out_bits_exc = io_out_bits_exc_0; // @[FPU.scala:573:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File DMACommandTracker.scala: package gemmini import chisel3._ import chisel3.util._ // This module is meant to go inside the Load controller, where it can track which commands are currently // in flight and which are completed class DMACommandTracker[T <: Data](val nCmds: Int, val maxBytes: Int, tag_t: => T) extends Module { def cmd_id_t = UInt((log2Ceil(nCmds) max 1).W) val io = IO(new Bundle { // TODO is there an existing decoupled interface in the standard library which matches this use-case? val alloc = new Bundle { val valid = Input(Bool()) val ready = Output(Bool()) class BitsT(tag_t: => T, cmd_id_t: UInt) extends Bundle { // This was only spun off as its own class to resolve CloneType errors val tag = Input(tag_t.cloneType) val bytes_to_read = Input(UInt(log2Up(maxBytes+1).W)) val cmd_id = Output(cmd_id_t.cloneType) } val bits = new BitsT(tag_t.cloneType, cmd_id_t.cloneType) def fire(dummy: Int = 0) = valid && ready } class RequestReturnedT(cmd_id_t: UInt) extends Bundle { // This was only spun off as its own class to resolve CloneType errors val bytes_read = UInt(log2Up(maxBytes+1).W) val cmd_id = cmd_id_t.cloneType } val request_returned = Flipped(Valid(new RequestReturnedT(cmd_id_t.cloneType))) class CmdCompletedT(cmd_id_t: UInt, tag_t: T) extends Bundle { val cmd_id = cmd_id_t.cloneType val tag = tag_t.cloneType } val cmd_completed = Decoupled(new CmdCompletedT(cmd_id_t.cloneType, tag_t.cloneType)) val busy = Output(Bool()) }) class Entry extends Bundle { val valid = Bool() val tag = tag_t.cloneType val bytes_left = UInt(log2Up(maxBytes+1).W) def init(dummy: Int = 0): Unit = { valid := false.B } } // val cmds = RegInit(VecInit(Seq.fill(nCmds)(entry_init))) val cmds = Reg(Vec(nCmds, new Entry)) val cmd_valids = cmds.map(_.valid) val next_empty_alloc = MuxCase(0.U, cmd_valids.zipWithIndex.map { case (v, i) => (!v) -> i.U }) io.alloc.ready := !cmd_valids.reduce(_ && _) io.alloc.bits.cmd_id := next_empty_alloc io.busy := cmd_valids.reduce(_ \|\| _) val cmd_completed_id = MuxCase(0.U, cmds.zipWithIndex.map { case (cmd, i) => (cmd.valid && cmd.bytes_left === 0.U) -> i.U }) io.cmd_completed.valid := cmds.map(cmd => cmd.valid && cmd.bytes_left === 0.U).reduce(_ \|\| _) io.cmd_completed.bits.cmd_id := cmd_completed_id io.cmd_completed.bits.tag := cmds(cmd_completed_id).tag when (io.alloc.fire()) { cmds(next_empty_alloc).valid := true.B cmds(next_empty_alloc).tag := io.alloc.bits.tag cmds(next_empty_alloc).bytes_left := io.alloc.bits.bytes_to_read } when (io.request_returned.fire) { val cmd_id = io.request_returned.bits.cmd_id cmds(cmd_id).bytes_left := cmds(cmd_id).bytes_left - io.request_returned.bits.bytes_read assert(cmds(cmd_id).valid) assert(cmds(cmd_id).bytes_left >= io.request_returned.bits.bytes_read) } when (io.cmd_completed.fire) { cmds(io.cmd_completed.bits.cmd_id).valid := false.B } when (reset.asBool) { cmds.foreach(_.init()) } } File LocalAddr.scala: package gemmini import chisel3._ import chisel3.util._ class LocalAddr(sp_banks: Int, sp_bank_entries: Int, acc_banks: Int, acc_bank_entries: Int) extends Bundle { private val localAddrBits = 32 // TODO magic number private val spAddrBits = log2Ceil(sp_banks * sp_bank_entries) private val accAddrBits = log2Ceil(acc_banks * acc_bank_entries) private val maxAddrBits = spAddrBits max accAddrBits private val spBankBits = log2Up(sp_banks) private val spBankRowBits = log2Up(sp_bank_entries) private val accBankBits = log2Up(acc_banks) val accBankRowBits = log2Up(acc_bank_entries) val spRows = sp_banks * sp_bank_entries val is_acc_addr = Bool() val accumulate = Bool() val read_full_acc_row = Bool() val norm_cmd = NormCmd() private val metadata_w = is_acc_addr.getWidth + accumulate.getWidth + read_full_acc_row.getWidth + norm_cmd.getWidth assert(maxAddrBits + metadata_w < 32) val garbage = UInt(((localAddrBits - maxAddrBits - metadata_w - 1) max 0).W) val garbage_bit = if (localAddrBits - maxAddrBits >= metadata_w + 1) UInt(1.W) else UInt(0.W) val data = UInt(maxAddrBits.W) def sp_bank(dummy: Int = 0) = if (spAddrBits == spBankRowBits) 0.U else data(spAddrBits - 1, spBankRowBits) def sp_row(dummy: Int = 0) = data(spBankRowBits - 1, 0) def acc_bank(dummy: Int = 0) = if (accAddrBits == accBankRowBits) 0.U else data(accAddrBits - 1, accBankRowBits) def acc_row(dummy: Int = 0) = data(accBankRowBits - 1, 0) def full_sp_addr(dummy: Int = 0) = data(spAddrBits - 1, 0) def full_acc_addr(dummy: Int = 0) = data(accAddrBits - 1, 0) def is_same_address(other: LocalAddr): Bool = is_acc_addr === other.is_acc_addr && data === other.data def is_same_address(other: UInt): Bool = is_same_address(other.asTypeOf(this)) def is_garbage(dummy: Int = 0) = is_acc_addr && accumulate && read_full_acc_row && data.andR && (if (garbage_bit.getWidth > 0) garbage_bit.asBool else true.B) def +(other: UInt) = { require(isPow2(sp_bank_entries)) // TODO remove this requirement require(isPow2(acc_bank_entries)) // TODO remove this requirement val result = WireInit(this) result.data := data + other result } def <=(other: LocalAddr) = is_acc_addr === other.is_acc_addr && Mux(is_acc_addr, full_acc_addr() <= other.full_acc_addr(), full_sp_addr() <= other.full_sp_addr()) def <(other: LocalAddr) = is_acc_addr === other.is_acc_addr && Mux(is_acc_addr, full_acc_addr() < other.full_acc_addr(), full_sp_addr() < other.full_sp_addr()) def >(other: LocalAddr) = is_acc_addr === other.is_acc_addr && Mux(is_acc_addr, full_acc_addr() > other.full_acc_addr(), full_sp_addr() > other.full_sp_addr()) def add_with_overflow(other: UInt): Tuple2[LocalAddr, Bool] = { require(isPow2(sp_bank_entries)) // TODO remove this requirement require(isPow2(acc_bank_entries)) // TODO remove this requirement val sum = data +& other val overflow = Mux(is_acc_addr, sum(accAddrBits), sum(spAddrBits)) val result = WireInit(this) result.data := sum(maxAddrBits - 1, 0) (result, overflow) } // This function can only be used with non-accumulator addresses. Returns both new address and underflow def floorSub(other: UInt, floor: UInt): (LocalAddr, Bool) = { require(isPow2(sp_bank_entries)) // TODO remove this requirement require(isPow2(acc_bank_entries)) // TODO remove this requirement val underflow = data < (floor +& other) val result = WireInit(this) result.data := Mux(underflow, floor, data - other) (result, underflow) } def make_this_garbage(dummy: Int = 0): Unit = { is_acc_addr := true.B accumulate := true.B read_full_acc_row := true.B garbage_bit := 1.U data := ~(0.U(maxAddrBits.W)) } } object LocalAddr { def cast_to_local_addr[T <: Data](local_addr_t: LocalAddr, t: T): LocalAddr = { // This convenience function is basically the same as calling "asTypeOf(local_addr_t)". However, this convenience // function will also cast unnecessary garbage bits to 0, which may help reduce multiplier/adder bitwidths val result = WireInit(t.asTypeOf(local_addr_t)) if (result.garbage_bit.getWidth > 0) result.garbage := 0.U result } def cast_to_sp_addr[T <: Data](local_addr_t: LocalAddr, t: T): LocalAddr = { // This function is a wrapper around cast_to_local_addr, but it assumes that the input will not be the garbage // address val result = WireInit(cast_to_local_addr(local_addr_t, t)) result.is_acc_addr := false.B result.accumulate := false.B result.read_full_acc_row := false.B // assert(!result.garbage_bit, "cast_to_sp_addr doesn't work on garbage addresses") result } def cast_to_acc_addr[T <: Data](local_addr_t: LocalAddr, t: T, accumulate: Bool, read_full: Bool): LocalAddr = { // This function is a wrapper around cast_to_local_addr, but it assumes that the input will not be the garbage // address val result = WireInit(cast_to_local_addr(local_addr_t, t)) result.is_acc_addr := true.B result.accumulate := accumulate result.read_full_acc_row := read_full // assert(!result.garbage_bit, "cast_to_acc_addr doesn't work on garbage addresses") result } def garbage_addr(local_addr_t: LocalAddr): LocalAddr = { val result = Wire(chiselTypeOf(local_addr_t)) result := DontCare result.make_this_garbage() result } } File Util.scala: package gemmini import chisel3._ import chisel3.util._ object Util { def wrappingAdd(u: UInt, n: UInt, max_plus_one: Int): UInt = { val max = max_plus_one - 1 if (max == 0) { 0.U } else { assert(n <= max.U, "cannot wrapAdd when n is larger than max") Mux(u >= max.U - n + 1.U && n =/= 0.U, n - (max.U - u) - 1.U, u + n) } } def wrappingAdd(u: UInt, n: UInt, max_plus_one: UInt, en: Bool = true.B): UInt = { val max = max_plus_one - 1.U assert(n <= max \|\| max === 0.U, "cannot wrapAdd when n is larger than max, unless max is 0") /* Mux(!en, u, Mux (max === 0.U, 0.U, Mux(u >= max - n + 1.U && n =/= 0.U, n - (max - u) - 1.U, u + n))) / MuxCase(u + n, Seq( (!en) -> u, (max === 0.U) -> 0.U, (u >= max - n + 1.U && n =/= 0.U) -> (n - (max - u) - 1.U) )) } def satAdd(u: UInt, v: UInt, max: UInt): UInt = { Mux(u +& v > max, max, u + v) } def floorAdd(u: UInt, n: UInt, max_plus_one: UInt, en: Bool = true.B): UInt = { val max = max_plus_one - 1.U MuxCase(u + n, Seq( (!en) -> u, ((u +& n) > max) -> 0.U )) } def sFloorAdd(s: SInt, n: UInt, max_plus_one: SInt, min: SInt, en: Bool = true.B): SInt = { val max = max_plus_one - 1.S MuxCase(s + n.zext, Seq( (!en) -> s, ((s +& n.zext) > max) -> min )) } def wrappingSub(u: UInt, n: UInt, max_plus_one: Int): UInt = { val max = max_plus_one - 1 assert(n <= max.U, "cannot wrapSub when n is larger than max") Mux(u < n, max.U - (n-u) + 1.U, u - n) } def ceilingDivide(numer: Int, denom: Int): Int = { if (numer % denom == 0) { numer / denom } else { numer / denom + 1} } def closestLowerPowerOf2(u: UInt): UInt = { // TODO figure out a more efficient way of doing this. Is this many muxes really necessary? val exp = u.asBools.zipWithIndex.map { case (b, i) => Mux(b, i.U, 0.U) }.reduce((acc, u) => Mux(acc > u, acc, u)) (1.U << exp).asUInt } def closestAlignedLowerPowerOf2(u: UInt, addr: UInt, stride: UInt, rowBytes: Int): UInt = { val lgRowBytes = log2Ceil(rowBytes) // TODO figure out a more efficient way of doing this. Is this many muxes really necessary? val exp = u.asBools.zipWithIndex.map { case (b, i) => Mux(b && addr(i + lgRowBytes - 1, 0) === 0.U && stride(i + lgRowBytes - 1, 0) === 0.U, i.U, 0.U) }.reduce((acc, u) => Mux(acc > u, acc, u)) (1.U << exp).asUInt } // This function will return "next" with a 0-cycle delay when the "enable" signal is high. It's like a queue with // the "pipe" and "flow" parameters set to "true" def RegEnableThru[T <: Data](next: T, enable: Bool): T = { val buf = RegEnable(next, enable) Mux(enable, next, buf) } def RegEnableThru[T <: Data](next: T, init: T, enable: Bool): T = { val buf = RegEnable(next, init, enable) Mux(enable, next, buf) } def maxOf(u1: UInt, u2: UInt): UInt = { Mux(u1 > u2, u1, u2) } def maxOf[T <: Data](x: T, y: T)(implicit ev: Arithmetic[T]): T = { import ev._ Mux(x > y, x, y) } def minOf(u1: UInt, u2: UInt): UInt = { Mux(u1 < u2, u1, u2) } def accumulateTree[T <: Data](xs: Seq[T])(implicit ev: Arithmetic[T]): T = { import ev._ assert(xs.nonEmpty, "can't accumulate 0 elements") if (xs.length == 1) { xs.head } else { val upperRowLen = 1 << log2Ceil(xs.length) val upperRow = xs.padTo(upperRowLen, xs.head.zero) val pairs = upperRow.grouped(2) val lowerRow = pairs.map { case Seq(a, b) => a + b } accumulateTree(lowerRow.toSeq) } } // An undirectioned Valid bundle class UDValid[T <: Data](t: T) extends Bundle { val valid = Bool() val bits = t.cloneType def push(b: T): Unit = { valid := true.B bits := b } def pop(dummy: Int = 0): T = { valid := false.B bits } } object UDValid { def apply[T <: Data](t: T): UDValid[T] = new UDValid(t) } // creates a Reg and the next-state Wire, and returns both def regwire(bits: Int) = { val wire = Wire(UInt(bits.W)) val reg = RegNext(wire) wire := reg // default wire to read from reg (reg, wire) } } File LoadController.scala: package gemmini import chisel3._ import chisel3.util._ import GemminiISA._ import Util._ import org.chipsalliance.cde.config.Parameters import midas.targetutils.PerfCounter // TODO we need to check for WAW errors here // TODO deal with errors when reading scratchpad responses class LoadController[T <: Data, U <: Data, V <: Data](config: GemminiArrayConfig[T, U, V], coreMaxAddrBits: Int, local_addr_t: LocalAddr) (implicit p: Parameters) extends Module { import config._ val io = IO(new Bundle { val cmd = Flipped(Decoupled(new GemminiCmd(reservation_station_entries))) val dma = new ScratchpadReadMemIO(local_addr_t, mvin_scale_t_bits) val completed = Decoupled(UInt(log2Up(reservation_station_entries).W)) val busy = Output(Bool()) val counter = new CounterEventIO() }) val waiting_for_command :: waiting_for_dma_req_ready :: sending_rows :: Nil = Enum(3) val control_state = RegInit(waiting_for_command) val strides = Reg(Vec(load_states, UInt(coreMaxAddrBits.W))) val scales = Reg(Vec(load_states, UInt(mvin_scale_t_bits.W))) val shrinks = Reg(Vec(load_states, Bool())) // Shrink inputs to accumulator val block_strides = Reg(Vec(load_states, UInt(block_stride_bits.W))) // Spad stride during block move-ins val pixel_repeats = Reg(Vec(load_states, UInt(pixel_repeats_bits.W))) val block_rows = meshRows tileRows val block_cols = meshColumns * tileColumns val row_counter = RegInit(0.U(log2Ceil(block_rows).W)) val cmd = Queue(io.cmd, ld_queue_length) val vaddr = cmd.bits.cmd.rs1 val mvin_rs2 = cmd.bits.cmd.rs2.asTypeOf(new MvinRs2(mvin_rows_bits, mvin_cols_bits, local_addr_t)) val localaddr = mvin_rs2.local_addr val cols = mvin_rs2.num_cols val rows = mvin_rs2.num_rows val config_stride = cmd.bits.cmd.rs2 val config_mvin_rs1 = cmd.bits.cmd.rs1.asTypeOf(new ConfigMvinRs1(mvin_scale_t_bits, block_stride_bits, pixel_repeats_bits)) val config_scale = config_mvin_rs1.scale val config_shrink = config_mvin_rs1.shrink val config_block_stride = config_mvin_rs1.stride val config_pixel_repeats = config_mvin_rs1.pixel_repeats val mstatus = cmd.bits.cmd.status val load_state_id = MuxCase(0.U, Seq((cmd.bits.cmd.inst.funct === LOAD2_CMD) -> 1.U, (cmd.bits.cmd.inst.funct === LOAD3_CMD) -> 2.U)) val config_state_id = config_mvin_rs1.state_id val state_id = Mux(cmd.bits.cmd.inst.funct === CONFIG_CMD, config_state_id, load_state_id) val stride = strides(state_id) val scale = scales(state_id) val shrink = shrinks(state_id) val block_stride = block_strides(state_id) val pixel_repeat = pixel_repeats(state_id) val all_zeros = vaddr === 0.U val localaddr_plus_row_counter = localaddr + row_counter val actual_rows_read = Mux(stride === 0.U && !all_zeros, 1.U, rows) val DoConfig = cmd.bits.cmd.inst.funct === CONFIG_CMD val DoLoad = !DoConfig // TODO change this if more commands are added cmd.ready := false.B // Command tracker instantiation val nCmds = (max_in_flight_mem_reqs / block_rows) + 1 val deps_t = new Bundle { val rob_id = UInt(log2Up(reservation_station_entries).W) } val maxBytesInRowRequest = config.dma_maxbytes max (block_cols * config.inputType.getWidth / 8) max (block_cols * config.accType.getWidth / 8) val maxBytesInMatRequest = block_rows * maxBytesInRowRequest val cmd_tracker = Module(new DMACommandTracker(nCmds, maxBytesInMatRequest, deps_t)) io.busy := cmd.valid \|\| cmd_tracker.io.busy // DMA IO wiring io.dma.req.valid := (control_state === waiting_for_command && cmd.valid && DoLoad && cmd_tracker.io.alloc.ready) \|\| control_state === waiting_for_dma_req_ready \|\| (control_state === sending_rows && row_counter =/= 0.U) io.dma.req.bits.vaddr := vaddr + row_counter * stride io.dma.req.bits.laddr := localaddr_plus_row_counter io.dma.req.bits.cols := cols io.dma.req.bits.repeats := Mux(stride === 0.U && !all_zeros, rows - 1.U, 0.U) io.dma.req.bits.block_stride := block_stride io.dma.req.bits.scale := scale io.dma.req.bits.has_acc_bitwidth := localaddr_plus_row_counter.is_acc_addr && !shrink io.dma.req.bits.all_zeros := all_zeros io.dma.req.bits.status := mstatus io.dma.req.bits.pixel_repeats := pixel_repeat // Command tracker IO cmd_tracker.io.alloc.valid := control_state === waiting_for_command && cmd.valid && DoLoad cmd_tracker.io.alloc.bits.bytes_to_read := Mux(io.dma.req.bits.has_acc_bitwidth, cols * actual_rows_read * config.accType.getWidth.U, cols * actual_rows_read * config.inputType.getWidth.U) >> 3 // We replaced a very clear "/ 8.U" operation here with a ">> 3" operation, solely to satisfy Verilator's linter cmd_tracker.io.alloc.bits.tag.rob_id := cmd.bits.rob_id.bits cmd_tracker.io.request_returned.valid := io.dma.resp.fire // TODO use a bundle connect cmd_tracker.io.request_returned.bits.cmd_id := io.dma.resp.bits.cmd_id // TODO use a bundle connect cmd_tracker.io.request_returned.bits.bytes_read := io.dma.resp.bits.bytesRead cmd_tracker.io.cmd_completed.ready := io.completed.ready val cmd_id = RegEnableThru(cmd_tracker.io.alloc.bits.cmd_id, cmd_tracker.io.alloc.fire()) // TODO is this really better than a simple RegEnable? io.dma.req.bits.cmd_id := cmd_id io.completed.valid := cmd_tracker.io.cmd_completed.valid io.completed.bits := cmd_tracker.io.cmd_completed.bits.tag.rob_id io.busy := cmd.valid \|\| cmd_tracker.io.busy // Row counter when (io.dma.req.fire) { row_counter := wrappingAdd(row_counter, 1.U, actual_rows_read) assert(block_stride >= rows) } // Control logic switch (control_state) { is (waiting_for_command) { when (cmd.valid) { when(DoConfig) { stride := config_stride scale := config_scale shrink := config_shrink block_stride := config_block_stride pixel_repeat := Mux(config_pixel_repeats === 0.U, 1.U, config_pixel_repeats) // TODO this default value was just added to maintain backwards compatibility. we should deprecate and remove it later cmd.ready := true.B } .elsewhen(DoLoad && cmd_tracker.io.alloc.fire()) { control_state := Mux(io.dma.req.fire, sending_rows, waiting_for_dma_req_ready) } } } is (waiting_for_dma_req_ready) { when (io.dma.req.fire) { control_state := sending_rows } } is (sending_rows) { val last_row = row_counter === 0.U \|\| (row_counter === actual_rows_read-1.U && io.dma.req.fire) when (last_row) { control_state := waiting_for_command cmd.ready := true.B } } } // Optimizations based on config parameters if (!has_first_layer_optimizations) pixel_repeats.foreach(_ := 1.U) // Performance counter CounterEventIO.init(io.counter) io.counter.connectEventSignal(CounterEvent.LOAD_ACTIVE_CYCLE, control_state === sending_rows) io.counter.connectEventSignal(CounterEvent.LOAD_DMA_WAIT_CYCLE, control_state === waiting_for_dma_req_ready) io.counter.connectEventSignal(CounterEvent.LOAD_SCRATCHPAD_WAIT_CYCLE, io.dma.req.valid && !io.dma.req.ready) if (use_firesim_simulation_counters) { PerfCounter(io.dma.req.valid && !io.dma.req.ready, "load_dma_wait_cycle", "cycles during which load controller is waiting for DMA to be available") } // Assertions assert(!(cmd_tracker.io.alloc.fire() && cmd_tracker.io.alloc.bits.bytes_to_read === 0.U), "A single mvin instruction must load more than 0 bytes") assert(has_first_layer_optimizations.B \|\| !(cmd.valid && DoConfig && config_pixel_repeats > 1.U), "If first-layer optimizations are not enabled, then pixel-repeats cannot be greater than 1") }	module LoadController( // @[LoadController.scala:13:7] input clock, // @[LoadController.scala:13:7] input reset, // @[LoadController.scala:13:7] output io_cmd_ready, // @[LoadController.scala:18:14] input io_cmd_valid, // @[LoadController.scala:18:14] input [6:0] io_cmd_bits_cmd_inst_funct, // @[LoadController.scala:18:14] input [4:0] io_cmd_bits_cmd_inst_rs2, // @[LoadController.scala:18:14] input [4:0] io_cmd_bits_cmd_inst_rs1, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_inst_xd, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_inst_xs1, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_inst_xs2, // @[LoadController.scala:18:14] input [4:0] io_cmd_bits_cmd_inst_rd, // @[LoadController.scala:18:14] input [6:0] io_cmd_bits_cmd_inst_opcode, // @[LoadController.scala:18:14] input [63:0] io_cmd_bits_cmd_rs1, // @[LoadController.scala:18:14] input [63:0] io_cmd_bits_cmd_rs2, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_debug, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_cease, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_wfi, // @[LoadController.scala:18:14] input [31:0] io_cmd_bits_cmd_status_isa, // @[LoadController.scala:18:14] input [1:0] io_cmd_bits_cmd_status_dprv, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_dv, // @[LoadController.scala:18:14] input [1:0] io_cmd_bits_cmd_status_prv, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_v, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_sd, // @[LoadController.scala:18:14] input [22:0] io_cmd_bits_cmd_status_zero2, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_mpv, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_gva, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_mbe, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_sbe, // @[LoadController.scala:18:14] input [1:0] io_cmd_bits_cmd_status_sxl, // @[LoadController.scala:18:14] input [1:0] io_cmd_bits_cmd_status_uxl, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_sd_rv32, // @[LoadController.scala:18:14] input [7:0] io_cmd_bits_cmd_status_zero1, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_tsr, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_tw, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_tvm, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_mxr, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_sum, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_mprv, // @[LoadController.scala:18:14] input [1:0] io_cmd_bits_cmd_status_xs, // @[LoadController.scala:18:14] input [1:0] io_cmd_bits_cmd_status_fs, // @[LoadController.scala:18:14] input [1:0] io_cmd_bits_cmd_status_mpp, // @[LoadController.scala:18:14] input [1:0] io_cmd_bits_cmd_status_vs, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_spp, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_mpie, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_ube, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_spie, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_upie, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_mie, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_hie, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_sie, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_uie, // @[LoadController.scala:18:14] input [5:0] io_cmd_bits_rob_id_bits, // @[LoadController.scala:18:14] input io_cmd_bits_from_matmul_fsm, // @[LoadController.scala:18:14] input io_cmd_bits_from_conv_fsm, // @[LoadController.scala:18:14] input io_dma_req_ready, // @[LoadController.scala:18:14] output io_dma_req_valid, // @[LoadController.scala:18:14] output [39:0] io_dma_req_bits_vaddr, // @[LoadController.scala:18:14] output io_dma_req_bits_laddr_is_acc_addr, // @[LoadController.scala:18:14] output io_dma_req_bits_laddr_accumulate, // @[LoadController.scala:18:14] output io_dma_req_bits_laddr_read_full_acc_row, // @[LoadController.scala:18:14] output [2:0] io_dma_req_bits_laddr_norm_cmd, // @[LoadController.scala:18:14] output [10:0] io_dma_req_bits_laddr_garbage, // @[LoadController.scala:18:14] output io_dma_req_bits_laddr_garbage_bit, // @[LoadController.scala:18:14] output [13:0] io_dma_req_bits_laddr_data, // @[LoadController.scala:18:14] output [15:0] io_dma_req_bits_cols, // @[LoadController.scala:18:14] output [15:0] io_dma_req_bits_repeats, // @[LoadController.scala:18:14] output [31:0] io_dma_req_bits_scale, // @[LoadController.scala:18:14] output io_dma_req_bits_has_acc_bitwidth, // @[LoadController.scala:18:14] output io_dma_req_bits_all_zeros, // @[LoadController.scala:18:14] output [15:0] io_dma_req_bits_block_stride, // @[LoadController.scala:18:14] output [7:0] io_dma_req_bits_pixel_repeats, // @[LoadController.scala:18:14] output [7:0] io_dma_req_bits_cmd_id, // @[LoadController.scala:18:14] output io_dma_req_bits_status_debug, // @[LoadController.scala:18:14] output io_dma_req_bits_status_cease, // @[LoadController.scala:18:14] output io_dma_req_bits_status_wfi, // @[LoadController.scala:18:14] output [31:0] io_dma_req_bits_status_isa, // @[LoadController.scala:18:14] output [1:0] io_dma_req_bits_status_dprv, // @[LoadController.scala:18:14] output io_dma_req_bits_status_dv, // @[LoadController.scala:18:14] output [1:0] io_dma_req_bits_status_prv, // @[LoadController.scala:18:14] output io_dma_req_bits_status_v, // @[LoadController.scala:18:14] output io_dma_req_bits_status_sd, // @[LoadController.scala:18:14] output [22:0] io_dma_req_bits_status_zero2, // @[LoadController.scala:18:14] output io_dma_req_bits_status_mpv, // @[LoadController.scala:18:14] output io_dma_req_bits_status_gva, // @[LoadController.scala:18:14] output io_dma_req_bits_status_mbe, // @[LoadController.scala:18:14] output io_dma_req_bits_status_sbe, // @[LoadController.scala:18:14] output [1:0] io_dma_req_bits_status_sxl, // @[LoadController.scala:18:14] output [1:0] io_dma_req_bits_status_uxl, // @[LoadController.scala:18:14] output io_dma_req_bits_status_sd_rv32, // @[LoadController.scala:18:14] output [7:0] io_dma_req_bits_status_zero1, // @[LoadController.scala:18:14] output io_dma_req_bits_status_tsr, // @[LoadController.scala:18:14] output io_dma_req_bits_status_tw, // @[LoadController.scala:18:14] output io_dma_req_bits_status_tvm, // @[LoadController.scala:18:14] output io_dma_req_bits_status_mxr, // @[LoadController.scala:18:14] output io_dma_req_bits_status_sum, // @[LoadController.scala:18:14] output io_dma_req_bits_status_mprv, // @[LoadController.scala:18:14] output [1:0] io_dma_req_bits_status_xs, // @[LoadController.scala:18:14] output [1:0] io_dma_req_bits_status_fs, // @[LoadController.scala:18:14] output [1:0] io_dma_req_bits_status_mpp, // @[LoadController.scala:18:14] output [1:0] io_dma_req_bits_status_vs, // @[LoadController.scala:18:14] output io_dma_req_bits_status_spp, // @[LoadController.scala:18:14] output io_dma_req_bits_status_mpie, // @[LoadController.scala:18:14] output io_dma_req_bits_status_ube, // @[LoadController.scala:18:14] output io_dma_req_bits_status_spie, // @[LoadController.scala:18:14] output io_dma_req_bits_status_upie, // @[LoadController.scala:18:14] output io_dma_req_bits_status_mie, // @[LoadController.scala:18:14] output io_dma_req_bits_status_hie, // @[LoadController.scala:18:14] output io_dma_req_bits_status_sie, // @[LoadController.scala:18:14] output io_dma_req_bits_status_uie, // @[LoadController.scala:18:14] input io_dma_resp_valid, // @[LoadController.scala:18:14] input [15:0] io_dma_resp_bits_bytesRead, // @[LoadController.scala:18:14] input [7:0] io_dma_resp_bits_cmd_id, // @[LoadController.scala:18:14] input io_completed_ready, // @[LoadController.scala:18:14] output io_completed_valid, // @[LoadController.scala:18:14] output [5:0] io_completed_bits, // @[LoadController.scala:18:14] output io_busy, // @[LoadController.scala:18:14] output io_counter_event_signal_8, // @[LoadController.scala:18:14] output io_counter_event_signal_9, // @[LoadController.scala:18:14] output io_counter_event_signal_10, // @[LoadController.scala:18:14] input io_counter_external_reset // @[LoadController.scala:18:14] ); wire mvin_rs2_local_addr_garbage_bit; // @[LoadController.scala:45:43] wire [10:0] mvin_rs2_local_addr_garbage; // @[LoadController.scala:45:43] wire [2:0] mvin_rs2_local_addr_norm_cmd; // @[LoadController.scala:45:43] wire mvin_rs2_local_addr_read_full_acc_row; // @[LoadController.scala:45:43] wire mvin_rs2_local_addr_accumulate; // @[LoadController.scala:45:43] wire mvin_rs2_local_addr_is_acc_addr; // @[LoadController.scala:45:43] wire _cmd_tracker_io_alloc_ready; // @[LoadController.scala:94:27] wire [2:0] _cmd_tracker_io_alloc_bits_cmd_id; // @[LoadController.scala:94:27] wire _cmd_tracker_io_busy; // @[LoadController.scala:94:27] wire _cmd_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [6:0] _cmd_q_io_deq_bits_cmd_inst_funct; // @[Decoupled.scala:362:21] wire [63:0] _cmd_q_io_deq_bits_cmd_rs1; // @[Decoupled.scala:362:21] wire [63:0] _cmd_q_io_deq_bits_cmd_rs2; // @[Decoupled.scala:362:21] wire [5:0] _cmd_q_io_deq_bits_rob_id_bits; // @[Decoupled.scala:362:21] wire io_cmd_valid_0 = io_cmd_valid; // @[LoadController.scala:13:7] wire [6:0] io_cmd_bits_cmd_inst_funct_0 = io_cmd_bits_cmd_inst_funct; // @[LoadController.scala:13:7] wire [4:0] io_cmd_bits_cmd_inst_rs2_0 = io_cmd_bits_cmd_inst_rs2; // @[LoadController.scala:13:7] wire [4:0] io_cmd_bits_cmd_inst_rs1_0 = io_cmd_bits_cmd_inst_rs1; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_inst_xd_0 = io_cmd_bits_cmd_inst_xd; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_inst_xs1_0 = io_cmd_bits_cmd_inst_xs1; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_inst_xs2_0 = io_cmd_bits_cmd_inst_xs2; // @[LoadController.scala:13:7] wire [4:0] io_cmd_bits_cmd_inst_rd_0 = io_cmd_bits_cmd_inst_rd; // @[LoadController.scala:13:7] wire [6:0] io_cmd_bits_cmd_inst_opcode_0 = io_cmd_bits_cmd_inst_opcode; // @[LoadController.scala:13:7] wire [63:0] io_cmd_bits_cmd_rs1_0 = io_cmd_bits_cmd_rs1; // @[LoadController.scala:13:7] wire [63:0] io_cmd_bits_cmd_rs2_0 = io_cmd_bits_cmd_rs2; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_debug_0 = io_cmd_bits_cmd_status_debug; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_cease_0 = io_cmd_bits_cmd_status_cease; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_wfi_0 = io_cmd_bits_cmd_status_wfi; // @[LoadController.scala:13:7] wire [31:0] io_cmd_bits_cmd_status_isa_0 = io_cmd_bits_cmd_status_isa; // @[LoadController.scala:13:7] wire [1:0] io_cmd_bits_cmd_status_dprv_0 = io_cmd_bits_cmd_status_dprv; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_dv_0 = io_cmd_bits_cmd_status_dv; // @[LoadController.scala:13:7] wire [1:0] io_cmd_bits_cmd_status_prv_0 = io_cmd_bits_cmd_status_prv; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_v_0 = io_cmd_bits_cmd_status_v; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_sd_0 = io_cmd_bits_cmd_status_sd; // @[LoadController.scala:13:7] wire [22:0] io_cmd_bits_cmd_status_zero2_0 = io_cmd_bits_cmd_status_zero2; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_mpv_0 = io_cmd_bits_cmd_status_mpv; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_gva_0 = io_cmd_bits_cmd_status_gva; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_mbe_0 = io_cmd_bits_cmd_status_mbe; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_sbe_0 = io_cmd_bits_cmd_status_sbe; // @[LoadController.scala:13:7] wire [1:0] io_cmd_bits_cmd_status_sxl_0 = io_cmd_bits_cmd_status_sxl; // @[LoadController.scala:13:7] wire [1:0] io_cmd_bits_cmd_status_uxl_0 = io_cmd_bits_cmd_status_uxl; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_sd_rv32_0 = io_cmd_bits_cmd_status_sd_rv32; // @[LoadController.scala:13:7] wire [7:0] io_cmd_bits_cmd_status_zero1_0 = io_cmd_bits_cmd_status_zero1; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_tsr_0 = io_cmd_bits_cmd_status_tsr; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_tw_0 = io_cmd_bits_cmd_status_tw; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_tvm_0 = io_cmd_bits_cmd_status_tvm; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_mxr_0 = io_cmd_bits_cmd_status_mxr; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_sum_0 = io_cmd_bits_cmd_status_sum; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_mprv_0 = io_cmd_bits_cmd_status_mprv; // @[LoadController.scala:13:7] wire [1:0] io_cmd_bits_cmd_status_xs_0 = io_cmd_bits_cmd_status_xs; // @[LoadController.scala:13:7] wire [1:0] io_cmd_bits_cmd_status_fs_0 = io_cmd_bits_cmd_status_fs; // @[LoadController.scala:13:7] wire [1:0] io_cmd_bits_cmd_status_mpp_0 = io_cmd_bits_cmd_status_mpp; // @[LoadController.scala:13:7] wire [1:0] io_cmd_bits_cmd_status_vs_0 = io_cmd_bits_cmd_status_vs; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_spp_0 = io_cmd_bits_cmd_status_spp; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_mpie_0 = io_cmd_bits_cmd_status_mpie; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_ube_0 = io_cmd_bits_cmd_status_ube; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_spie_0 = io_cmd_bits_cmd_status_spie; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_upie_0 = io_cmd_bits_cmd_status_upie; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_mie_0 = io_cmd_bits_cmd_status_mie; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_hie_0 = io_cmd_bits_cmd_status_hie; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_sie_0 = io_cmd_bits_cmd_status_sie; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_uie_0 = io_cmd_bits_cmd_status_uie; // @[LoadController.scala:13:7] wire [5:0] io_cmd_bits_rob_id_bits_0 = io_cmd_bits_rob_id_bits; // @[LoadController.scala:13:7] wire io_cmd_bits_from_matmul_fsm_0 = io_cmd_bits_from_matmul_fsm; // @[LoadController.scala:13:7] wire io_cmd_bits_from_conv_fsm_0 = io_cmd_bits_from_conv_fsm; // @[LoadController.scala:13:7] wire io_dma_req_ready_0 = io_dma_req_ready; // @[LoadController.scala:13:7] wire io_dma_resp_valid_0 = io_dma_resp_valid; // @[LoadController.scala:13:7] wire [15:0] io_dma_resp_bits_bytesRead_0 = io_dma_resp_bits_bytesRead; // @[LoadController.scala:13:7] wire [7:0] io_dma_resp_bits_cmd_id_0 = io_dma_resp_bits_cmd_id; // @[LoadController.scala:13:7] wire io_completed_ready_0 = io_completed_ready; // @[LoadController.scala:13:7] wire io_counter_external_reset_0 = io_counter_external_reset; // @[LoadController.scala:13:7] wire _row_counter_T_3 = reset; // @[Util.scala:19:11] wire io_cmd_bits_rob_id_valid = 1'h1; // @[LoadController.scala:13:7] wire _row_counter_T_15 = 1'h1; // @[Util.scala:30:32] wire io_counter_event_signal_0 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_1 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_2 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_3 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_4 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_5 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_6 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_7 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_11 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_12 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_13 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_14 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_15 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_16 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_17 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_18 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_19 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_20 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_21 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_22 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_23 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_24 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_25 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_26 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_27 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_28 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_29 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_30 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_31 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_32 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_33 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_34 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_35 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_36 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_37 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_38 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_39 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_40 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_41 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_42 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_43 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_44 = 1'h0; // @[LoadController.scala:13:7] wire _row_counter_T_8 = 1'h0; // @[Util.scala:28:8] wire [31:0] io_counter_external_values_0 = 32'h0; // @[LoadController.scala:13:7] wire [31:0] io_counter_external_values_1 = 32'h0; // @[LoadController.scala:13:7] wire [31:0] io_counter_external_values_2 = 32'h0; // @[LoadController.scala:13:7] wire [31:0] io_counter_external_values_3 = 32'h0; // @[LoadController.scala:13:7] wire [31:0] io_counter_external_values_4 = 32'h0; // @[LoadController.scala:13:7] wire [31:0] io_counter_external_values_5 = 32'h0; // @[LoadController.scala:13:7] wire [31:0] io_counter_external_values_6 = 32'h0; // @[LoadController.scala:13:7] wire [31:0] io_counter_external_values_7 = 32'h0; // @[LoadController.scala:13:7] wire _io_dma_req_valid_T_9; // @[LoadController.scala:100:49] wire localaddr_plus_row_counter_is_acc_addr; // @[LocalAddr.scala:50:26] wire localaddr_plus_row_counter_accumulate; // @[LocalAddr.scala:50:26] wire localaddr_plus_row_counter_read_full_acc_row; // @[LocalAddr.scala:50:26] wire [2:0] localaddr_plus_row_counter_norm_cmd; // @[LocalAddr.scala:50:26] wire [10:0] localaddr_plus_row_counter_garbage; // @[LocalAddr.scala:50:26] wire localaddr_plus_row_counter_garbage_bit; // @[LocalAddr.scala:50:26] wire [13:0] localaddr_plus_row_counter_data; // @[LocalAddr.scala:50:26] wire _io_dma_req_bits_has_acc_bitwidth_T_1; // @[LoadController.scala:108:78] wire all_zeros; // @[LoadController.scala:72:25] wire _io_busy_T_1; // @[LoadController.scala:130:24] wire io_cmd_ready_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_laddr_is_acc_addr_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_laddr_accumulate_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_laddr_read_full_acc_row_0; // @[LoadController.scala:13:7] wire [2:0] io_dma_req_bits_laddr_norm_cmd_0; // @[LoadController.scala:13:7] wire [10:0] io_dma_req_bits_laddr_garbage_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_laddr_garbage_bit_0; // @[LoadController.scala:13:7] wire [13:0] io_dma_req_bits_laddr_data_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_debug_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_cease_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_wfi_0; // @[LoadController.scala:13:7] wire [31:0] io_dma_req_bits_status_isa_0; // @[LoadController.scala:13:7] wire [1:0] io_dma_req_bits_status_dprv_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_dv_0; // @[LoadController.scala:13:7] wire [1:0] io_dma_req_bits_status_prv_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_v_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_sd_0; // @[LoadController.scala:13:7] wire [22:0] io_dma_req_bits_status_zero2_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_mpv_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_gva_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_mbe_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_sbe_0; // @[LoadController.scala:13:7] wire [1:0] io_dma_req_bits_status_sxl_0; // @[LoadController.scala:13:7] wire [1:0] io_dma_req_bits_status_uxl_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_sd_rv32_0; // @[LoadController.scala:13:7] wire [7:0] io_dma_req_bits_status_zero1_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_tsr_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_tw_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_tvm_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_mxr_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_sum_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_mprv_0; // @[LoadController.scala:13:7] wire [1:0] io_dma_req_bits_status_xs_0; // @[LoadController.scala:13:7] wire [1:0] io_dma_req_bits_status_fs_0; // @[LoadController.scala:13:7] wire [1:0] io_dma_req_bits_status_mpp_0; // @[LoadController.scala:13:7] wire [1:0] io_dma_req_bits_status_vs_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_spp_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_mpie_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_ube_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_spie_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_upie_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_mie_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_hie_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_sie_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_uie_0; // @[LoadController.scala:13:7] wire [39:0] io_dma_req_bits_vaddr_0; // @[LoadController.scala:13:7] wire [15:0] io_dma_req_bits_cols_0; // @[LoadController.scala:13:7] wire [15:0] io_dma_req_bits_repeats_0; // @[LoadController.scala:13:7] wire [31:0] io_dma_req_bits_scale_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_has_acc_bitwidth_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_all_zeros_0; // @[LoadController.scala:13:7] wire [15:0] io_dma_req_bits_block_stride_0; // @[LoadController.scala:13:7] wire [7:0] io_dma_req_bits_pixel_repeats_0; // @[LoadController.scala:13:7] wire [7:0] io_dma_req_bits_cmd_id_0; // @[LoadController.scala:13:7] wire io_dma_req_valid_0; // @[LoadController.scala:13:7] wire io_completed_valid_0; // @[LoadController.scala:13:7] wire [5:0] io_completed_bits_0; // @[LoadController.scala:13:7] wire io_counter_event_signal_8_0; // @[LoadController.scala:13:7] wire io_counter_event_signal_9_0; // @[LoadController.scala:13:7] wire io_counter_event_signal_10_0; // @[LoadController.scala:13:7] wire io_busy_0; // @[LoadController.scala:13:7] reg [1:0] control_state; // @[LoadController.scala:31:30] reg [39:0] strides_0; // @[LoadController.scala:33:20] reg [39:0] strides_1; // @[LoadController.scala:33:20] reg [39:0] strides_2; // @[LoadController.scala:33:20] reg [31:0] scales_0; // @[LoadController.scala:34:19] reg [31:0] scales_1; // @[LoadController.scala:34:19] reg [31:0] scales_2; // @[LoadController.scala:34:19] reg shrinks_0; // @[LoadController.scala:35:20] reg shrinks_1; // @[LoadController.scala:35:20] reg shrinks_2; // @[LoadController.scala:35:20] reg [13:0] block_strides_0; // @[LoadController.scala:36:26] reg [13:0] block_strides_1; // @[LoadController.scala:36:26] reg [13:0] block_strides_2; // @[LoadController.scala:36:26] reg [2:0] pixel_repeats_0; // @[LoadController.scala:37:26] reg [2:0] pixel_repeats_1; // @[LoadController.scala:37:26] reg [2:0] pixel_repeats_2; // @[LoadController.scala:37:26] reg [1:0] row_counter; // @[LoadController.scala:40:28] wire [12:0] _mvin_rs2_T_10; // @[LoadController.scala:45:43] wire [2:0] _mvin_rs2_T_9; // @[LoadController.scala:45:43] wire [10:0] _mvin_rs2_T_8; // @[LoadController.scala:45:43] wire [4:0] _mvin_rs2_T_7; // @[LoadController.scala:45:43] wire _mvin_rs2_T_6; // @[LoadController.scala:45:43] wire _mvin_rs2_T_5; // @[LoadController.scala:45:43] assign localaddr_plus_row_counter_is_acc_addr = mvin_rs2_local_addr_is_acc_addr; // @[LocalAddr.scala:50:26] wire _mvin_rs2_T_4; // @[LoadController.scala:45:43] assign localaddr_plus_row_counter_accumulate = mvin_rs2_local_addr_accumulate; // @[LocalAddr.scala:50:26] wire [2:0] _mvin_rs2_WIRE_2; // @[LoadController.scala:45:43] assign localaddr_plus_row_counter_read_full_acc_row = mvin_rs2_local_addr_read_full_acc_row; // @[LocalAddr.scala:50:26] wire [10:0] _mvin_rs2_T_2; // @[LoadController.scala:45:43] assign localaddr_plus_row_counter_norm_cmd = mvin_rs2_local_addr_norm_cmd; // @[LocalAddr.scala:50:26] wire _mvin_rs2_T_1; // @[LoadController.scala:45:43] assign localaddr_plus_row_counter_garbage = mvin_rs2_local_addr_garbage; // @[LocalAddr.scala:50:26] wire [13:0] _mvin_rs2_T; // @[LoadController.scala:45:43] assign localaddr_plus_row_counter_garbage_bit = mvin_rs2_local_addr_garbage_bit; // @[LocalAddr.scala:50:26] wire [13:0] mvin_rs2_local_addr_data; // @[LoadController.scala:45:43] wire [12:0] mvin_rs2__spacer2; // @[LoadController.scala:45:43] wire [2:0] mvin_rs2_num_rows; // @[LoadController.scala:45:43] wire [10:0] mvin_rs2__spacer1; // @[LoadController.scala:45:43] wire [4:0] mvin_rs2_num_cols; // @[LoadController.scala:45:43] wire [63:0] _mvin_rs2_WIRE; // @[LoadController.scala:45:43] assign _mvin_rs2_T = _mvin_rs2_WIRE[13:0]; // @[LoadController.scala:45:43] assign mvin_rs2_local_addr_data = _mvin_rs2_T; // @[LoadController.scala:45:43] assign _mvin_rs2_T_1 = _mvin_rs2_WIRE[14]; // @[LoadController.scala:45:43] assign mvin_rs2_local_addr_garbage_bit = _mvin_rs2_T_1; // @[LoadController.scala:45:43] assign _mvin_rs2_T_2 = _mvin_rs2_WIRE[25:15]; // @[LoadController.scala:45:43] assign mvin_rs2_local_addr_garbage = _mvin_rs2_T_2; // @[LoadController.scala:45:43] wire [2:0] _mvin_rs2_T_3 = _mvin_rs2_WIRE[28:26]; // @[LoadController.scala:45:43] wire [2:0] _mvin_rs2_WIRE_1 = _mvin_rs2_T_3; // @[LoadController.scala:45:43] assign _mvin_rs2_WIRE_2 = _mvin_rs2_WIRE_1; // @[LoadController.scala:45:43] assign mvin_rs2_local_addr_norm_cmd = _mvin_rs2_WIRE_2; // @[LoadController.scala:45:43] assign _mvin_rs2_T_4 = _mvin_rs2_WIRE[29]; // @[LoadController.scala:45:43] assign mvin_rs2_local_addr_read_full_acc_row = _mvin_rs2_T_4; // @[LoadController.scala:45:43] assign _mvin_rs2_T_5 = _mvin_rs2_WIRE[30]; // @[LoadController.scala:45:43] assign mvin_rs2_local_addr_accumulate = _mvin_rs2_T_5; // @[LoadController.scala:45:43] assign _mvin_rs2_T_6 = _mvin_rs2_WIRE[31]; // @[LoadController.scala:45:43] assign mvin_rs2_local_addr_is_acc_addr = _mvin_rs2_T_6; // @[LoadController.scala:45:43] assign _mvin_rs2_T_7 = _mvin_rs2_WIRE[36:32]; // @[LoadController.scala:45:43] assign mvin_rs2_num_cols = _mvin_rs2_T_7; // @[LoadController.scala:45:43] assign _mvin_rs2_T_8 = _mvin_rs2_WIRE[47:37]; // @[LoadController.scala:45:43] assign mvin_rs2__spacer1 = _mvin_rs2_T_8; // @[LoadController.scala:45:43] assign _mvin_rs2_T_9 = _mvin_rs2_WIRE[50:48]; // @[LoadController.scala:45:43] assign mvin_rs2_num_rows = _mvin_rs2_T_9; // @[LoadController.scala:45:43] assign _mvin_rs2_T_10 = _mvin_rs2_WIRE[63:51]; // @[LoadController.scala:45:43] assign mvin_rs2__spacer2 = _mvin_rs2_T_10; // @[LoadController.scala:45:43] wire [31:0] _config_mvin_rs1_T_8; // @[LoadController.scala:52:50] wire [1:0] _config_mvin_rs1_T_7; // @[LoadController.scala:52:50] wire [13:0] _config_mvin_rs1_T_6; // @[LoadController.scala:52:50] wire [4:0] _config_mvin_rs1_T_5; // @[LoadController.scala:52:50] wire [2:0] _config_mvin_rs1_T_4; // @[LoadController.scala:52:50] wire [2:0] _config_mvin_rs1_T_3; // @[LoadController.scala:52:50] wire [1:0] _config_mvin_rs1_T_2; // @[LoadController.scala:52:50] wire _config_mvin_rs1_T_1; // @[LoadController.scala:52:50] wire [1:0] _config_mvin_rs1_T; // @[LoadController.scala:52:50] wire [31:0] config_mvin_rs1_scale; // @[LoadController.scala:52:50] wire [1:0] config_mvin_rs1__spacer2; // @[LoadController.scala:52:50] wire [13:0] config_mvin_rs1_stride; // @[LoadController.scala:52:50] wire [4:0] config_mvin_rs1__spacer1; // @[LoadController.scala:52:50] wire [2:0] config_mvin_rs1_pixel_repeats; // @[LoadController.scala:52:50] wire [2:0] config_mvin_rs1__spacer0; // @[LoadController.scala:52:50] wire [1:0] config_mvin_rs1_state_id; // @[LoadController.scala:52:50] wire config_mvin_rs1_shrink; // @[LoadController.scala:52:50] wire [1:0] config_mvin_rs1__unused; // @[LoadController.scala:52:50] wire [63:0] _config_mvin_rs1_WIRE; // @[LoadController.scala:52:50] assign _config_mvin_rs1_T = _config_mvin_rs1_WIRE[1:0]; // @[LoadController.scala:52:50] assign config_mvin_rs1__unused = _config_mvin_rs1_T; // @[LoadController.scala:52:50] assign _config_mvin_rs1_T_1 = _config_mvin_rs1_WIRE[2]; // @[LoadController.scala:52:50] assign config_mvin_rs1_shrink = _config_mvin_rs1_T_1; // @[LoadController.scala:52:50] assign _config_mvin_rs1_T_2 = _config_mvin_rs1_WIRE[4:3]; // @[LoadController.scala:52:50] assign config_mvin_rs1_state_id = _config_mvin_rs1_T_2; // @[LoadController.scala:52:50] assign _config_mvin_rs1_T_3 = _config_mvin_rs1_WIRE[7:5]; // @[LoadController.scala:52:50] assign config_mvin_rs1__spacer0 = _config_mvin_rs1_T_3; // @[LoadController.scala:52:50] assign _config_mvin_rs1_T_4 = _config_mvin_rs1_WIRE[10:8]; // @[LoadController.scala:52:50] assign config_mvin_rs1_pixel_repeats = _config_mvin_rs1_T_4; // @[LoadController.scala:52:50] assign _config_mvin_rs1_T_5 = _config_mvin_rs1_WIRE[15:11]; // @[LoadController.scala:52:50] assign config_mvin_rs1__spacer1 = _config_mvin_rs1_T_5; // @[LoadController.scala:52:50] assign _config_mvin_rs1_T_6 = _config_mvin_rs1_WIRE[29:16]; // @[LoadController.scala:52:50] assign config_mvin_rs1_stride = _config_mvin_rs1_T_6; // @[LoadController.scala:52:50] assign _config_mvin_rs1_T_7 = _config_mvin_rs1_WIRE[31:30]; // @[LoadController.scala:52:50] assign config_mvin_rs1__spacer2 = _config_mvin_rs1_T_7; // @[LoadController.scala:52:50] assign _config_mvin_rs1_T_8 = _config_mvin_rs1_WIRE[63:32]; // @[LoadController.scala:52:50] assign config_mvin_rs1_scale = _config_mvin_rs1_T_8; // @[LoadController.scala:52:50] wire _load_state_id_T = _cmd_q_io_deq_bits_cmd_inst_funct == 7'h1; // @[Decoupled.scala:362:21] wire _load_state_id_T_1 = _cmd_q_io_deq_bits_cmd_inst_funct == 7'hE; // @[Decoupled.scala:362:21] wire [1:0] _load_state_id_T_2 = {_load_state_id_T_1, 1'h0}; // @[Mux.scala:126:16] wire [1:0] load_state_id = _load_state_id_T ? 2'h1 : _load_state_id_T_2; // @[Mux.scala:126:16] wire _GEN = _cmd_q_io_deq_bits_cmd_inst_funct == 7'h0; // @[Decoupled.scala:362:21] wire _state_id_T; // @[LoadController.scala:64:46] assign _state_id_T = _GEN; // @[LoadController.scala:64:46] wire DoConfig; // @[LoadController.scala:78:42] assign DoConfig = _GEN; // @[LoadController.scala:64:46, :78:42] wire [1:0] state_id = _state_id_T ? config_mvin_rs1_state_id : load_state_id; // @[Mux.scala:126:16] assign all_zeros = _cmd_q_io_deq_bits_cmd_rs1 == 64'h0; // @[Decoupled.scala:362:21] assign io_dma_req_bits_all_zeros_0 = all_zeros; // @[LoadController.scala:13:7, :72:25] assign io_dma_req_bits_laddr_is_acc_addr_0 = localaddr_plus_row_counter_is_acc_addr; // @[LocalAddr.scala:50:26] assign io_dma_req_bits_laddr_accumulate_0 = localaddr_plus_row_counter_accumulate; // @[LocalAddr.scala:50:26] assign io_dma_req_bits_laddr_read_full_acc_row_0 = localaddr_plus_row_counter_read_full_acc_row; // @[LocalAddr.scala:50:26] assign io_dma_req_bits_laddr_norm_cmd_0 = localaddr_plus_row_counter_norm_cmd; // @[LocalAddr.scala:50:26] assign io_dma_req_bits_laddr_garbage_0 = localaddr_plus_row_counter_garbage; // @[LocalAddr.scala:50:26] assign io_dma_req_bits_laddr_garbage_bit_0 = localaddr_plus_row_counter_garbage_bit; // @[LocalAddr.scala:50:26] wire [13:0] _localaddr_plus_row_counter_result_data_T_1; // @[LocalAddr.scala:51:25] assign io_dma_req_bits_laddr_data_0 = localaddr_plus_row_counter_data; // @[LocalAddr.scala:50:26] wire [14:0] _localaddr_plus_row_counter_result_data_T = {1'h0, mvin_rs2_local_addr_data} + {13'h0, row_counter}; // @[LocalAddr.scala:51:25] assign _localaddr_plus_row_counter_result_data_T_1 = _localaddr_plus_row_counter_result_data_T[13:0]; // @[LocalAddr.scala:51:25] assign localaddr_plus_row_counter_data = _localaddr_plus_row_counter_result_data_T_1; // @[LocalAddr.scala:50:26, :51:25] wire [3:0][39:0] _GEN_0 = {{strides_0}, {strides_2}, {strides_1}, {strides_0}}; // @[LoadController.scala:33:20, :76:37] wire _GEN_1 = _GEN_0[state_id] == 40'h0; // @[LoadController.scala:64:21, :76:37] wire _actual_rows_read_T; // @[LoadController.scala:76:37] assign _actual_rows_read_T = _GEN_1; // @[LoadController.scala:76:37] wire _io_dma_req_bits_repeats_T; // @[LoadController.scala:105:41] assign _io_dma_req_bits_repeats_T = _GEN_1; // @[LoadController.scala:76:37, :105:41] wire _actual_rows_read_T_1 = ~all_zeros; // @[LoadController.scala:72:25, :76:48] wire _actual_rows_read_T_2 = _actual_rows_read_T & _actual_rows_read_T_1; // @[LoadController.scala:76:{37,45,48}] wire [2:0] actual_rows_read = _actual_rows_read_T_2 ? 3'h1 : mvin_rs2_num_rows; // @[LoadController.scala:45:43, :76:{29,45}] wire DoLoad = ~DoConfig; // @[LoadController.scala:78:42, :79:16] wire _GEN_2 = _cmd_q_io_deq_valid \| _cmd_tracker_io_busy; // @[Decoupled.scala:362:21] wire _io_busy_T; // @[LoadController.scala:96:24] assign _io_busy_T = _GEN_2; // @[LoadController.scala:96:24] assign _io_busy_T_1 = _GEN_2; // @[LoadController.scala:96:24, :130:24] wire _T_5 = control_state == 2'h0; // @[LoadController.scala:31:30, :99:38] wire _io_dma_req_valid_T; // @[LoadController.scala:99:38] assign _io_dma_req_valid_T = _T_5; // @[LoadController.scala:99:38] wire _cmd_tracker_io_alloc_valid_T; // @[LoadController.scala:114:47] assign _cmd_tracker_io_alloc_valid_T = _T_5; // @[LoadController.scala:99:38, :114:47] wire _io_dma_req_valid_T_1 = _io_dma_req_valid_T & _cmd_q_io_deq_valid; // @[Decoupled.scala:362:21] wire _io_dma_req_valid_T_2 = _io_dma_req_valid_T_1 & DoLoad; // @[LoadController.scala:79:16, :99:{62,75}] wire _io_dma_req_valid_T_3 = _io_dma_req_valid_T_2 & _cmd_tracker_io_alloc_ready; // @[LoadController.scala:94:27, :99:{75,85}] wire _T_12 = control_state == 2'h1; // @[LoadController.scala:31:30, :100:19] assign io_counter_event_signal_8_0 = _T_12; // @[LoadController.scala:13:7, :100:19] wire _io_dma_req_valid_T_4; // @[LoadController.scala:100:19] assign _io_dma_req_valid_T_4 = _T_12; // @[LoadController.scala:100:19] wire _io_dma_req_valid_T_5 = _io_dma_req_valid_T_3 \| _io_dma_req_valid_T_4; // @[LoadController.scala:99:{85,116}, :100:19] wire _T_11 = control_state == 2'h2; // @[LoadController.scala:31:30, :101:20] assign io_counter_event_signal_9_0 = _T_11; // @[LoadController.scala:13:7, :101:20] wire _io_dma_req_valid_T_6; // @[LoadController.scala:101:20] assign _io_dma_req_valid_T_6 = _T_11; // @[LoadController.scala:101:20] wire _io_dma_req_valid_T_7 = \|row_counter; // @[LoadController.scala:40:28, :101:52] wire _io_dma_req_valid_T_8 = _io_dma_req_valid_T_6 & _io_dma_req_valid_T_7; // @[LoadController.scala:101:{20,37,52}] assign _io_dma_req_valid_T_9 = _io_dma_req_valid_T_5 \| _io_dma_req_valid_T_8; // @[LoadController.scala:99:116, :100:49, :101:37] assign io_dma_req_valid_0 = _io_dma_req_valid_T_9; // @[LoadController.scala:13:7, :100:49] wire [41:0] _io_dma_req_bits_vaddr_T = {40'h0, row_counter} * {2'h0, _GEN_0[state_id]}; // @[LoadController.scala:40:28, :64:21, :76:37, :102:48] wire [64:0] _io_dma_req_bits_vaddr_T_1 = {1'h0, _cmd_q_io_deq_bits_cmd_rs1} + {23'h0, _io_dma_req_bits_vaddr_T}; // @[Decoupled.scala:362:21] wire [63:0] _io_dma_req_bits_vaddr_T_2 = _io_dma_req_bits_vaddr_T_1[63:0]; // @[LoadController.scala:102:34] assign io_dma_req_bits_vaddr_0 = _io_dma_req_bits_vaddr_T_2[39:0]; // @[LoadController.scala:13:7, :102:{25,34}] assign io_dma_req_bits_cols_0 = {11'h0, mvin_rs2_num_cols}; // @[LoadController.scala:13:7, :45:43, :104:24] wire _io_dma_req_bits_repeats_T_1 = ~all_zeros; // @[LoadController.scala:72:25, :76:48, :105:52] wire _io_dma_req_bits_repeats_T_2 = _io_dma_req_bits_repeats_T & _io_dma_req_bits_repeats_T_1; // @[LoadController.scala:105:{41,49,52}] wire [3:0] _io_dma_req_bits_repeats_T_3 = {1'h0, mvin_rs2_num_rows} - 4'h1; // @[LoadController.scala:45:43, :105:69] wire [2:0] _io_dma_req_bits_repeats_T_4 = _io_dma_req_bits_repeats_T_3[2:0]; // @[LoadController.scala:105:69] wire [2:0] _io_dma_req_bits_repeats_T_5 = _io_dma_req_bits_repeats_T_2 ? _io_dma_req_bits_repeats_T_4 : 3'h0; // @[LoadController.scala:105:{33,49,69}] assign io_dma_req_bits_repeats_0 = {13'h0, _io_dma_req_bits_repeats_T_5}; // @[LoadController.scala:13:7, :105:{27,33}] wire [3:0][13:0] _GEN_3 = {{block_strides_0}, {block_strides_2}, {block_strides_1}, {block_strides_0}}; // @[LoadController.scala:36:26, :106:32] assign io_dma_req_bits_block_stride_0 = {2'h0, _GEN_3[state_id]}; // @[LoadController.scala:13:7, :64:21, :106:32] wire [3:0][31:0] _GEN_4 = {{scales_0}, {scales_2}, {scales_1}, {scales_0}}; // @[LoadController.scala:34:19, :107:25] assign io_dma_req_bits_scale_0 = _GEN_4[state_id]; // @[LoadController.scala:13:7, :64:21, :107:25] wire [3:0] _GEN_5 = {{shrinks_0}, {shrinks_2}, {shrinks_1}, {shrinks_0}}; // @[LoadController.scala:35:20, :108:81] wire _io_dma_req_bits_has_acc_bitwidth_T = ~_GEN_5[state_id]; // @[LoadController.scala:64:21, :108:81] assign _io_dma_req_bits_has_acc_bitwidth_T_1 = localaddr_plus_row_counter_is_acc_addr & _io_dma_req_bits_has_acc_bitwidth_T; // @[LocalAddr.scala:50:26] assign io_dma_req_bits_has_acc_bitwidth_0 = _io_dma_req_bits_has_acc_bitwidth_T_1; // @[LoadController.scala:13:7, :108:78] wire [3:0][2:0] _GEN_6 = {{pixel_repeats_0}, {pixel_repeats_2}, {pixel_repeats_1}, {pixel_repeats_0}}; // @[LoadController.scala:37:26, :111:33] assign io_dma_req_bits_pixel_repeats_0 = {5'h0, _GEN_6[state_id]}; // @[LoadController.scala:13:7, :64:21, :111:33] wire _cmd_tracker_io_alloc_valid_T_1 = _cmd_tracker_io_alloc_valid_T & _cmd_q_io_deq_valid; // @[Decoupled.scala:362:21] wire _cmd_tracker_io_alloc_valid_T_2 = _cmd_tracker_io_alloc_valid_T_1 & DoLoad; // @[LoadController.scala:79:16, :114:{71,84}] wire [7:0] _GEN_7 = {3'h0, mvin_rs2_num_cols} * {5'h0, actual_rows_read}; // @[LoadController.scala:45:43, :76:29, :116:48] wire [7:0] _cmd_tracker_io_alloc_bits_bytes_to_read_T; // @[LoadController.scala:116:48] assign _cmd_tracker_io_alloc_bits_bytes_to_read_T = _GEN_7; // @[LoadController.scala:116:48] wire [7:0] _cmd_tracker_io_alloc_bits_bytes_to_read_T_2; // @[LoadController.scala:117:12] assign _cmd_tracker_io_alloc_bits_bytes_to_read_T_2 = _GEN_7; // @[LoadController.scala:116:48, :117:12] wire [13:0] _cmd_tracker_io_alloc_bits_bytes_to_read_T_1 = {1'h0, _cmd_tracker_io_alloc_bits_bytes_to_read_T, 5'h0}; // @[LoadController.scala:116:{48,67}] wire [13:0] _cmd_tracker_io_alloc_bits_bytes_to_read_T_3 = {1'h0, _cmd_tracker_io_alloc_bits_bytes_to_read_T_2, 5'h0}; // @[LoadController.scala:117:{12,31}] wire [13:0] _cmd_tracker_io_alloc_bits_bytes_to_read_T_4 = io_dma_req_bits_has_acc_bitwidth_0 ? _cmd_tracker_io_alloc_bits_bytes_to_read_T_1 : _cmd_tracker_io_alloc_bits_bytes_to_read_T_3; // @[LoadController.scala:13:7, :116:{8,67}, :117:31] wire [10:0] _cmd_tracker_io_alloc_bits_bytes_to_read_T_5 = _cmd_tracker_io_alloc_bits_bytes_to_read_T_4[13:3]; // @[LoadController.scala:116:8, :117:62] wire _cmd_id_T = _cmd_tracker_io_alloc_valid_T_2 & _cmd_tracker_io_alloc_ready; // @[LoadController.scala:94:27, :114:84] reg [2:0] cmd_id_buf; // @[Util.scala:90:24] wire [2:0] cmd_id = _cmd_id_T ? _cmd_tracker_io_alloc_bits_cmd_id : cmd_id_buf; // @[Util.scala:90:24, :91:8] assign io_dma_req_bits_cmd_id_0 = {5'h0, cmd_id}; // @[Util.scala:91:8] assign io_busy_0 = _io_busy_T_1; // @[LoadController.scala:13:7, :130:24] wire _T_9 = io_dma_req_ready_0 & io_dma_req_valid_0; // @[Decoupled.scala:51:35] wire _control_state_T; // @[Decoupled.scala:51:35] assign _control_state_T = _T_9; // @[Decoupled.scala:51:35] wire _last_row_T_4; // @[Decoupled.scala:51:35] assign _last_row_T_4 = _T_9; // @[Decoupled.scala:51:35] wire [3:0] _GEN_8 = {1'h0, actual_rows_read} - 4'h1; // @[Util.scala:18:28] wire [3:0] _row_counter_max_T; // @[Util.scala:18:28] assign _row_counter_max_T = _GEN_8; // @[Util.scala:18:28] wire [3:0] _last_row_T_1; // @[LoadController.scala:165:78] assign _last_row_T_1 = _GEN_8; // @[Util.scala:18:28] wire [2:0] row_counter_max = _row_counter_max_T[2:0]; // @[Util.scala:18:28] wire _row_counter_T = \|row_counter_max; // @[Util.scala:18:28, :19:14] wire _GEN_9 = row_counter_max == 3'h0; // @[Util.scala:18:28, :19:28] wire _row_counter_T_1; // @[Util.scala:19:28] assign _row_counter_T_1 = _GEN_9; // @[Util.scala:19:28] wire _row_counter_T_9; // @[Util.scala:29:12] assign _row_counter_T_9 = _GEN_9; // @[Util.scala:19:28, :29:12] wire _row_counter_T_2 = _row_counter_T \| _row_counter_T_1; // @[Util.scala:19:{14,21,28}] wire _row_counter_T_4 = ~_row_counter_T_3; // @[Util.scala:19:11] wire _row_counter_T_5 = ~_row_counter_T_2; // @[Util.scala:19:{11,21}] wire [2:0] _GEN_10 = {1'h0, row_counter}; // @[Util.scala:27:15] wire [2:0] _row_counter_T_6 = _GEN_10 + 3'h1; // @[Util.scala:27:15] wire [1:0] _row_counter_T_7 = _row_counter_T_6[1:0]; // @[Util.scala:27:15] wire [3:0] _GEN_11 = {1'h0, row_counter_max}; // @[Util.scala:18:28, :30:17] wire [3:0] _row_counter_T_10 = _GEN_11 - 4'h1; // @[Util.scala:30:17] wire [2:0] _row_counter_T_11 = _row_counter_T_10[2:0]; // @[Util.scala:30:17] wire [3:0] _row_counter_T_12 = {1'h0, _row_counter_T_11} + 4'h1; // @[Util.scala:30:{17,21}] wire [2:0] _row_counter_T_13 = _row_counter_T_12[2:0]; // @[Util.scala:30:21] wire _row_counter_T_14 = _GEN_10 >= _row_counter_T_13; // @[Util.scala:27:15, :30:{10,21}] wire _row_counter_T_16 = _row_counter_T_14; // @[Util.scala:30:{10,27}] wire [3:0] _row_counter_T_17 = _GEN_11 - {2'h0, row_counter}; // @[Util.scala:30:{17,54}] wire [2:0] _row_counter_T_18 = _row_counter_T_17[2:0]; // @[Util.scala:30:54] wire [3:0] _row_counter_T_19 = 4'h1 - {1'h0, _row_counter_T_18}; // @[Util.scala:30:{47,54}] wire [2:0] _row_counter_T_20 = _row_counter_T_19[2:0]; // @[Util.scala:30:47] wire [3:0] _row_counter_T_21 = {1'h0, _row_counter_T_20} - 4'h1; // @[Util.scala:30:{47,59}] wire [2:0] _row_counter_T_22 = _row_counter_T_21[2:0]; // @[Util.scala:30:59] wire [2:0] _row_counter_T_23 = _row_counter_T_16 ? _row_counter_T_22 : {1'h0, _row_counter_T_7}; // @[Mux.scala:126:16] wire [2:0] _row_counter_T_24 = _row_counter_T_9 ? 3'h0 : _row_counter_T_23; // @[Mux.scala:126:16] wire [2:0] _row_counter_T_25 = _row_counter_T_24; // @[Mux.scala:126:16] wire _pixel_repeats_T = config_mvin_rs1_pixel_repeats == 3'h0; // @[LoadController.scala:52:50, :148:52] wire [2:0] _pixel_repeats_T_1 = _pixel_repeats_T ? 3'h1 : config_mvin_rs1_pixel_repeats; // @[LoadController.scala:52:50, :148:{30,52}] wire [1:0] _control_state_T_1 = _control_state_T ? 2'h2 : 2'h1; // @[Decoupled.scala:51:35] wire _last_row_T = ~(\|row_counter); // @[LoadController.scala:40:28, :101:52, :165:34] wire [2:0] _last_row_T_2 = _last_row_T_1[2:0]; // @[LoadController.scala:165:78] wire _last_row_T_3 = _GEN_10 == _last_row_T_2; // @[Util.scala:27:15] wire _last_row_T_5 = _last_row_T_3 & _last_row_T_4; // @[Decoupled.scala:51:35] wire last_row = _last_row_T \| _last_row_T_5; // @[LoadController.scala:165:{34,42,83}] assign io_counter_event_signal_10_0 = io_dma_req_valid_0 & ~io_dma_req_ready_0; // @[LoadController.scala:13:7, :182:{91,94}]
Generate the Verilog code corresponding to the following Chisel files. File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relListscache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_\|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x \| 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ \|\| _) (matches, bits.U) } expanded \| Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) \|\| (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) \|\| ((opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm \|\| opcode === TLMessages.Get \|\| (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN \|\| param === TLPermissions.BtoN \|\| param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB \|\| param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle File SourceC.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink._ class SourceCRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val opcode = UInt(3.W) val param = UInt(3.W) val source = UInt(params.outer.bundle.sourceBits.W) val tag = UInt(params.tagBits.W) val set = UInt(params.setBits.W) val way = UInt(params.wayBits.W) val dirty = Bool() } class SourceC(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val req = Flipped(Decoupled(new SourceCRequest(params))) val c = Decoupled(new TLBundleC(params.outer.bundle)) // BankedStore port val bs_adr = Decoupled(new BankedStoreOuterAddress(params)) val bs_dat = Flipped(new BankedStoreOuterDecoded(params)) // RaW hazard val evict_req = new SourceDHazard(params) val evict_safe = Flipped(Bool()) }) // We ignore the depth and pipe is useless here (we have to provision for worst-case=stall) require (!params.micro.outerBuf.c.pipe) val beatBytes = params.outer.manager.beatBytes val beats = params.cache.blockBytes / beatBytes val flow = params.micro.outerBuf.c.flow val queue = Module(new Queue(chiselTypeOf(io.c.bits), beats + 3 + (if (flow) 0 else 1), flow = flow)) // queue.io.count is far too slow val fillBits = log2Up(beats + 4) val fill = RegInit(0.U(fillBits.W)) val room = RegInit(true.B) when (queue.io.enq.fire =/= queue.io.deq.fire) { fill := fill + Mux(queue.io.enq.fire, 1.U, ~0.U(fillBits.W)) room := fill === 0.U \|\| ((fill === 1.U \|\| fill === 2.U) && !queue.io.enq.fire) } assert (room === queue.io.count <= 1.U) val busy = RegInit(false.B) val beat = RegInit(0.U(params.outerBeatBits.W)) val last = if (params.cache.blockBytes == params.outer.manager.beatBytes) true.B else (beat === ~(0.U(params.outerBeatBits.W))) val req = Mux(!busy, io.req.bits, RegEnable(io.req.bits, !busy && io.req.valid)) val want_data = busy \|\| (io.req.valid && room && io.req.bits.dirty) io.req.ready := !busy && room io.evict_req.set := req.set io.evict_req.way := req.way io.bs_adr.valid := (beat.orR \|\| io.evict_safe) && want_data io.bs_adr.bits.noop := false.B io.bs_adr.bits.way := req.way io.bs_adr.bits.set := req.set io.bs_adr.bits.beat := beat io.bs_adr.bits.mask := ~0.U(params.outerMaskBits.W) params.ccover(io.req.valid && io.req.bits.dirty && room && !io.evict_safe, "SOURCEC_HAZARD", "Prevented Eviction data hazard with backpressure") params.ccover(io.bs_adr.valid && !io.bs_adr.ready, "SOURCEC_SRAM_STALL", "Data SRAM busy") when (io.req.valid && room && io.req.bits.dirty) { busy := true.B } when (io.bs_adr.fire) { beat := beat + 1.U when (last) { busy := false.B beat := 0.U } } val s2_latch = Mux(want_data, io.bs_adr.fire, io.req.fire) val s2_valid = RegNext(s2_latch) val s2_req = RegEnable(req, s2_latch) val s2_beat = RegEnable(beat, s2_latch) val s2_last = RegEnable(last, s2_latch) val s3_latch = s2_valid val s3_valid = RegNext(s3_latch) val s3_req = RegEnable(s2_req, s3_latch) val s3_beat = RegEnable(s2_beat, s3_latch) val s3_last = RegEnable(s2_last, s3_latch) val c = Wire(chiselTypeOf(io.c)) c.valid := s3_valid c.bits.opcode := s3_req.opcode c.bits.param := s3_req.param c.bits.size := params.offsetBits.U c.bits.source := s3_req.source c.bits.address := params.expandAddress(s3_req.tag, s3_req.set, 0.U) c.bits.data := io.bs_dat.data c.bits.corrupt := false.B // We never accept at the front-end unless we're sure things will fit assert(!c.valid \|\| c.ready) params.ccover(!c.ready, "SOURCEC_QUEUE_FULL", "Eviction queue fully utilized") queue.io.enq <> c io.c <> queue.io.deq }	module SourceC( // @[SourceC.scala:35:7] input clock, // @[SourceC.scala:35:7] input reset, // @[SourceC.scala:35:7] output io_req_ready, // @[SourceC.scala:37:14] input io_req_valid, // @[SourceC.scala:37:14] input [2:0] io_req_bits_opcode, // @[SourceC.scala:37:14] input [2:0] io_req_bits_param, // @[SourceC.scala:37:14] input [4:0] io_req_bits_source, // @[SourceC.scala:37:14] input [12:0] io_req_bits_tag, // @[SourceC.scala:37:14] input [9:0] io_req_bits_set, // @[SourceC.scala:37:14] input [2:0] io_req_bits_way, // @[SourceC.scala:37:14] input io_req_bits_dirty, // @[SourceC.scala:37:14] input io_c_ready, // @[SourceC.scala:37:14] output io_c_valid, // @[SourceC.scala:37:14] output [2:0] io_c_bits_opcode, // @[SourceC.scala:37:14] output [2:0] io_c_bits_param, // @[SourceC.scala:37:14] output [2:0] io_c_bits_size, // @[SourceC.scala:37:14] output [4:0] io_c_bits_source, // @[SourceC.scala:37:14] output [31:0] io_c_bits_address, // @[SourceC.scala:37:14] output [63:0] io_c_bits_data, // @[SourceC.scala:37:14] output io_c_bits_corrupt, // @[SourceC.scala:37:14] input io_bs_adr_ready, // @[SourceC.scala:37:14] output io_bs_adr_valid, // @[SourceC.scala:37:14] output [2:0] io_bs_adr_bits_way, // @[SourceC.scala:37:14] output [9:0] io_bs_adr_bits_set, // @[SourceC.scala:37:14] output [2:0] io_bs_adr_bits_beat, // @[SourceC.scala:37:14] input [63:0] io_bs_dat_data, // @[SourceC.scala:37:14] output [9:0] io_evict_req_set, // @[SourceC.scala:37:14] output [2:0] io_evict_req_way, // @[SourceC.scala:37:14] input io_evict_safe // @[SourceC.scala:37:14] ); wire _queue_io_enq_ready; // @[SourceC.scala:54:21] wire _queue_io_deq_valid; // @[SourceC.scala:54:21] wire [3:0] _queue_io_count; // @[SourceC.scala:54:21] wire io_req_valid_0 = io_req_valid; // @[SourceC.scala:35:7] wire [2:0] io_req_bits_opcode_0 = io_req_bits_opcode; // @[SourceC.scala:35:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceC.scala:35:7] wire [4:0] io_req_bits_source_0 = io_req_bits_source; // @[SourceC.scala:35:7] wire [12:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceC.scala:35:7] wire [9:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceC.scala:35:7] wire [2:0] io_req_bits_way_0 = io_req_bits_way; // @[SourceC.scala:35:7] wire io_req_bits_dirty_0 = io_req_bits_dirty; // @[SourceC.scala:35:7] wire io_c_ready_0 = io_c_ready; // @[SourceC.scala:35:7] wire io_bs_adr_ready_0 = io_bs_adr_ready; // @[SourceC.scala:35:7] wire [63:0] io_bs_dat_data_0 = io_bs_dat_data; // @[SourceC.scala:35:7] wire io_evict_safe_0 = io_evict_safe; // @[SourceC.scala:35:7] wire _c_bits_address_base_T_2 = reset; // @[Parameters.scala:222:12] wire _c_bits_address_base_T_8 = reset; // @[Parameters.scala:222:12] wire _c_bits_address_base_T_14 = reset; // @[Parameters.scala:222:12] wire io_bs_adr_bits_noop = 1'h0; // @[SourceC.scala:35:7] wire c_bits_corrupt = 1'h0; // @[SourceC.scala:108:15] wire _c_bits_address_base_T = 1'h0; // @[Parameters.scala:222:15] wire _c_bits_address_base_T_4 = 1'h0; // @[Parameters.scala:222:12] wire _c_bits_address_base_T_6 = 1'h0; // @[Parameters.scala:222:15] wire _c_bits_address_base_T_10 = 1'h0; // @[Parameters.scala:222:12] wire _c_bits_address_base_T_12 = 1'h0; // @[Parameters.scala:222:15] wire _c_bits_address_base_T_16 = 1'h0; // @[Parameters.scala:222:12] wire io_bs_adr_bits_mask = 1'h1; // @[SourceC.scala:35:7] wire _io_bs_adr_bits_mask_T = 1'h1; // @[SourceC.scala:82:26] wire _c_bits_address_base_T_1 = 1'h1; // @[Parameters.scala:222:24] wire _c_bits_address_base_T_7 = 1'h1; // @[Parameters.scala:222:24] wire _c_bits_address_base_T_13 = 1'h1; // @[Parameters.scala:222:24] wire [1:0] c_bits_address_hi_hi_hi_lo = 2'h0; // @[Parameters.scala:230:8] wire [5:0] c_bits_address_base_y_2 = 6'h0; // @[Parameters.scala:221:15] wire [5:0] _c_bits_address_base_T_17 = 6'h0; // @[Parameters.scala:223:6] wire [2:0] c_bits_size = 3'h6; // @[SourceC.scala:108:15] wire [2:0] _last_T = 3'h7; // @[SourceC.scala:68:99] wire [3:0] _fill_T_1 = 4'hF; // @[SourceC.scala:61:48] wire _io_req_ready_T_1; // @[SourceC.scala:72:25] wire _io_bs_adr_valid_T_2; // @[SourceC.scala:77:50] wire [2:0] req_way; // @[SourceC.scala:69:17] wire [9:0] req_set; // @[SourceC.scala:69:17] wire [63:0] c_bits_data = io_bs_dat_data_0; // @[SourceC.scala:35:7, :108:15] wire io_req_ready_0; // @[SourceC.scala:35:7] wire [2:0] io_c_bits_opcode_0; // @[SourceC.scala:35:7] wire [2:0] io_c_bits_param_0; // @[SourceC.scala:35:7] wire [2:0] io_c_bits_size_0; // @[SourceC.scala:35:7] wire [4:0] io_c_bits_source_0; // @[SourceC.scala:35:7] wire [31:0] io_c_bits_address_0; // @[SourceC.scala:35:7] wire [63:0] io_c_bits_data_0; // @[SourceC.scala:35:7] wire io_c_bits_corrupt_0; // @[SourceC.scala:35:7] wire io_c_valid_0; // @[SourceC.scala:35:7] wire [2:0] io_bs_adr_bits_way_0; // @[SourceC.scala:35:7] wire [9:0] io_bs_adr_bits_set_0; // @[SourceC.scala:35:7] wire [2:0] io_bs_adr_bits_beat_0; // @[SourceC.scala:35:7] wire io_bs_adr_valid_0; // @[SourceC.scala:35:7] wire [9:0] io_evict_req_set_0; // @[SourceC.scala:35:7] wire [2:0] io_evict_req_way_0; // @[SourceC.scala:35:7] reg [3:0] fill; // @[SourceC.scala:58:21] reg room; // @[SourceC.scala:59:21] wire c_valid; // @[SourceC.scala:108:15] wire _T = _queue_io_enq_ready & c_valid; // @[Decoupled.scala:51:35] wire _fill_T; // @[Decoupled.scala:51:35] assign _fill_T = _T; // @[Decoupled.scala:51:35] wire _room_T_4; // @[Decoupled.scala:51:35] assign _room_T_4 = _T; // @[Decoupled.scala:51:35] wire [3:0] _fill_T_2 = _fill_T ? 4'h1 : 4'hF; // @[Decoupled.scala:51:35] wire [4:0] _fill_T_3 = {1'h0, fill} + {1'h0, _fill_T_2}; // @[SourceC.scala:58:21, :61:{18,23}] wire [3:0] _fill_T_4 = _fill_T_3[3:0]; // @[SourceC.scala:61:18] wire _room_T = fill == 4'h0; // @[SourceC.scala:58:21, :62:18] wire _room_T_1 = fill == 4'h1; // @[SourceC.scala:58:21, :62:36] wire _room_T_2 = fill == 4'h2; // @[SourceC.scala:58:21, :62:52] wire _room_T_3 = _room_T_1 \| _room_T_2; // @[SourceC.scala:62:{36,44,52}] wire _room_T_5 = ~_room_T_4; // @[Decoupled.scala:51:35] wire _room_T_6 = _room_T_3 & _room_T_5; // @[SourceC.scala:62:{44,61,64}] wire _room_T_7 = _room_T \| _room_T_6; // @[SourceC.scala:62:{18,26,61}] reg busy; // @[SourceC.scala:66:21] reg [2:0] beat; // @[SourceC.scala:67:21] assign io_bs_adr_bits_beat_0 = beat; // @[SourceC.scala:35:7, :67:21] wire last = &beat; // @[SourceC.scala:67:21, :68:95] wire _req_T = ~busy; // @[SourceC.scala:66:21, :69:18] wire _req_T_1 = ~busy; // @[SourceC.scala:66:21, :69:{18,61}] wire _req_T_2 = _req_T_1 & io_req_valid_0; // @[SourceC.scala:35:7, :69:{61,67}] reg [2:0] req_r_opcode; // @[SourceC.scala:69:47] reg [2:0] req_r_param; // @[SourceC.scala:69:47] reg [4:0] req_r_source; // @[SourceC.scala:69:47] reg [12:0] req_r_tag; // @[SourceC.scala:69:47] reg [9:0] req_r_set; // @[SourceC.scala:69:47] reg [2:0] req_r_way; // @[SourceC.scala:69:47] reg req_r_dirty; // @[SourceC.scala:69:47] wire [2:0] req_opcode = _req_T ? io_req_bits_opcode_0 : req_r_opcode; // @[SourceC.scala:35:7, :69:{17,18,47}] wire [2:0] req_param = _req_T ? io_req_bits_param_0 : req_r_param; // @[SourceC.scala:35:7, :69:{17,18,47}] wire [4:0] req_source = _req_T ? io_req_bits_source_0 : req_r_source; // @[SourceC.scala:35:7, :69:{17,18,47}] wire [12:0] req_tag = _req_T ? io_req_bits_tag_0 : req_r_tag; // @[SourceC.scala:35:7, :69:{17,18,47}] assign req_set = _req_T ? io_req_bits_set_0 : req_r_set; // @[SourceC.scala:35:7, :69:{17,18,47}] assign req_way = _req_T ? io_req_bits_way_0 : req_r_way; // @[SourceC.scala:35:7, :69:{17,18,47}] wire req_dirty = _req_T ? io_req_bits_dirty_0 : req_r_dirty; // @[SourceC.scala:35:7, :69:{17,18,47}] assign io_bs_adr_bits_set_0 = req_set; // @[SourceC.scala:35:7, :69:17] assign io_evict_req_set_0 = req_set; // @[SourceC.scala:35:7, :69:17] assign io_bs_adr_bits_way_0 = req_way; // @[SourceC.scala:35:7, :69:17] assign io_evict_req_way_0 = req_way; // @[SourceC.scala:35:7, :69:17] wire _want_data_T = io_req_valid_0 & room; // @[SourceC.scala:35:7, :59:21, :70:41] wire _want_data_T_1 = _want_data_T & io_req_bits_dirty_0; // @[SourceC.scala:35:7, :70:{41,49}] wire want_data = busy \| _want_data_T_1; // @[SourceC.scala:66:21, :70:{24,49}] wire _io_req_ready_T = ~busy; // @[SourceC.scala:66:21, :69:18, :72:19] assign _io_req_ready_T_1 = _io_req_ready_T & room; // @[SourceC.scala:59:21, :72:{19,25}] assign io_req_ready_0 = _io_req_ready_T_1; // @[SourceC.scala:35:7, :72:25] wire _io_bs_adr_valid_T = \|beat; // @[SourceC.scala:67:21, :77:28] wire _io_bs_adr_valid_T_1 = _io_bs_adr_valid_T \| io_evict_safe_0; // @[SourceC.scala:35:7, :77:{28,32}] assign _io_bs_adr_valid_T_2 = _io_bs_adr_valid_T_1 & want_data; // @[SourceC.scala:70:24, :77:{32,50}] assign io_bs_adr_valid_0 = _io_bs_adr_valid_T_2; // @[SourceC.scala:35:7, :77:50] wire _s2_latch_T = io_bs_adr_ready_0 & io_bs_adr_valid_0; // @[Decoupled.scala:51:35] wire [3:0] _beat_T = {1'h0, beat} + 4'h1; // @[SourceC.scala:67:21, :89:18] wire [2:0] _beat_T_1 = _beat_T[2:0]; // @[SourceC.scala:89:18] wire _s2_latch_T_1 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] wire s2_latch = want_data ? _s2_latch_T : _s2_latch_T_1; // @[Decoupled.scala:51:35] reg s2_valid; // @[SourceC.scala:97:25] reg [2:0] s2_req_opcode; // @[SourceC.scala:98:25] reg [2:0] s2_req_param; // @[SourceC.scala:98:25] reg [4:0] s2_req_source; // @[SourceC.scala:98:25] reg [12:0] s2_req_tag; // @[SourceC.scala:98:25] reg [9:0] s2_req_set; // @[SourceC.scala:98:25] reg [2:0] s2_req_way; // @[SourceC.scala:98:25] reg s2_req_dirty; // @[SourceC.scala:98:25] reg [2:0] s2_beat; // @[SourceC.scala:99:26] reg s2_last; // @[SourceC.scala:100:26] reg s3_valid; // @[SourceC.scala:103:25] assign c_valid = s3_valid; // @[SourceC.scala:103:25, :108:15] reg [2:0] s3_req_opcode; // @[SourceC.scala:104:25] wire [2:0] c_bits_opcode = s3_req_opcode; // @[SourceC.scala:104:25, :108:15] reg [2:0] s3_req_param; // @[SourceC.scala:104:25] wire [2:0] c_bits_param = s3_req_param; // @[SourceC.scala:104:25, :108:15] reg [4:0] s3_req_source; // @[SourceC.scala:104:25] wire [4:0] c_bits_source = s3_req_source; // @[SourceC.scala:104:25, :108:15] reg [12:0] s3_req_tag; // @[SourceC.scala:104:25] wire [12:0] c_bits_address_base_y = s3_req_tag; // @[SourceC.scala:104:25] reg [9:0] s3_req_set; // @[SourceC.scala:104:25] wire [9:0] c_bits_address_base_y_1 = s3_req_set; // @[SourceC.scala:104:25] reg [2:0] s3_req_way; // @[SourceC.scala:104:25] reg s3_req_dirty; // @[SourceC.scala:104:25] reg [2:0] s3_beat; // @[SourceC.scala:105:26] reg s3_last; // @[SourceC.scala:106:26] wire [31:0] _c_bits_address_T_29; // @[Parameters.scala:230:8] wire [31:0] c_bits_address; // @[SourceC.scala:108:15] wire c_ready; // @[SourceC.scala:108:15] wire [12:0] _c_bits_address_base_T_5 = c_bits_address_base_y; // @[Parameters.scala:221:15, :223:6] wire _c_bits_address_base_T_3 = ~_c_bits_address_base_T_2; // @[Parameters.scala:222:12] wire [9:0] _c_bits_address_base_T_11 = c_bits_address_base_y_1; // @[Parameters.scala:221:15, :223:6] wire _c_bits_address_base_T_9 = ~_c_bits_address_base_T_8; // @[Parameters.scala:222:12] wire _c_bits_address_base_T_15 = ~_c_bits_address_base_T_14; // @[Parameters.scala:222:12] wire [22:0] c_bits_address_base_hi = {_c_bits_address_base_T_5, _c_bits_address_base_T_11}; // @[Parameters.scala:223:6, :227:19] wire [28:0] c_bits_address_base = {c_bits_address_base_hi, 6'h0}; // @[Parameters.scala:227:19] wire _c_bits_address_T = c_bits_address_base[0]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_1 = c_bits_address_base[1]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_2 = c_bits_address_base[2]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_3 = c_bits_address_base[3]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_4 = c_bits_address_base[4]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_5 = c_bits_address_base[5]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_6 = c_bits_address_base[6]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_7 = c_bits_address_base[7]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_8 = c_bits_address_base[8]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_9 = c_bits_address_base[9]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_10 = c_bits_address_base[10]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_11 = c_bits_address_base[11]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_12 = c_bits_address_base[12]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_13 = c_bits_address_base[13]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_14 = c_bits_address_base[14]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_15 = c_bits_address_base[15]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_16 = c_bits_address_base[16]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_17 = c_bits_address_base[17]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_18 = c_bits_address_base[18]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_19 = c_bits_address_base[19]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_20 = c_bits_address_base[20]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_21 = c_bits_address_base[21]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_22 = c_bits_address_base[22]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_23 = c_bits_address_base[23]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_24 = c_bits_address_base[24]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_25 = c_bits_address_base[25]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_26 = c_bits_address_base[26]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_27 = c_bits_address_base[27]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_28 = c_bits_address_base[28]; // @[Parameters.scala:227:19, :229:72] wire [1:0] c_bits_address_lo_lo_lo_lo = {_c_bits_address_T_1, _c_bits_address_T}; // @[Parameters.scala:229:72, :230:8] wire [1:0] c_bits_address_lo_lo_lo_hi = {_c_bits_address_T_3, _c_bits_address_T_2}; // @[Parameters.scala:229:72, :230:8] wire [3:0] c_bits_address_lo_lo_lo = {c_bits_address_lo_lo_lo_hi, c_bits_address_lo_lo_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] c_bits_address_lo_lo_hi_lo = {_c_bits_address_T_5, _c_bits_address_T_4}; // @[Parameters.scala:229:72, :230:8] wire [1:0] c_bits_address_lo_lo_hi_hi = {_c_bits_address_T_7, _c_bits_address_T_6}; // @[Parameters.scala:229:72, :230:8] wire [3:0] c_bits_address_lo_lo_hi = {c_bits_address_lo_lo_hi_hi, c_bits_address_lo_lo_hi_lo}; // @[Parameters.scala:230:8] wire [7:0] c_bits_address_lo_lo = {c_bits_address_lo_lo_hi, c_bits_address_lo_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] c_bits_address_lo_hi_lo_lo = {_c_bits_address_T_9, _c_bits_address_T_8}; // @[Parameters.scala:229:72, :230:8] wire [1:0] c_bits_address_lo_hi_lo_hi = {_c_bits_address_T_11, _c_bits_address_T_10}; // @[Parameters.scala:229:72, :230:8] wire [3:0] c_bits_address_lo_hi_lo = {c_bits_address_lo_hi_lo_hi, c_bits_address_lo_hi_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] c_bits_address_lo_hi_hi_lo = {_c_bits_address_T_13, _c_bits_address_T_12}; // @[Parameters.scala:229:72, :230:8] wire [1:0] c_bits_address_lo_hi_hi_hi = {_c_bits_address_T_15, _c_bits_address_T_14}; // @[Parameters.scala:229:72, :230:8] wire [3:0] c_bits_address_lo_hi_hi = {c_bits_address_lo_hi_hi_hi, c_bits_address_lo_hi_hi_lo}; // @[Parameters.scala:230:8] wire [7:0] c_bits_address_lo_hi = {c_bits_address_lo_hi_hi, c_bits_address_lo_hi_lo}; // @[Parameters.scala:230:8] wire [15:0] c_bits_address_lo = {c_bits_address_lo_hi, c_bits_address_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] c_bits_address_hi_lo_lo_lo = {_c_bits_address_T_17, _c_bits_address_T_16}; // @[Parameters.scala:229:72, :230:8] wire [1:0] c_bits_address_hi_lo_lo_hi = {_c_bits_address_T_19, _c_bits_address_T_18}; // @[Parameters.scala:229:72, :230:8] wire [3:0] c_bits_address_hi_lo_lo = {c_bits_address_hi_lo_lo_hi, c_bits_address_hi_lo_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] c_bits_address_hi_lo_hi_lo = {_c_bits_address_T_21, _c_bits_address_T_20}; // @[Parameters.scala:229:72, :230:8] wire [1:0] c_bits_address_hi_lo_hi_hi = {_c_bits_address_T_23, _c_bits_address_T_22}; // @[Parameters.scala:229:72, :230:8] wire [3:0] c_bits_address_hi_lo_hi = {c_bits_address_hi_lo_hi_hi, c_bits_address_hi_lo_hi_lo}; // @[Parameters.scala:230:8] wire [7:0] c_bits_address_hi_lo = {c_bits_address_hi_lo_hi, c_bits_address_hi_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] c_bits_address_hi_hi_lo_lo = {_c_bits_address_T_25, _c_bits_address_T_24}; // @[Parameters.scala:229:72, :230:8] wire [1:0] c_bits_address_hi_hi_lo_hi = {_c_bits_address_T_27, _c_bits_address_T_26}; // @[Parameters.scala:229:72, :230:8] wire [3:0] c_bits_address_hi_hi_lo = {c_bits_address_hi_hi_lo_hi, c_bits_address_hi_hi_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] c_bits_address_hi_hi_hi_hi = {_c_bits_address_T_28, 1'h0}; // @[Parameters.scala:229:72, :230:8] wire [3:0] c_bits_address_hi_hi_hi = {c_bits_address_hi_hi_hi_hi, 2'h0}; // @[Parameters.scala:230:8] wire [7:0] c_bits_address_hi_hi = {c_bits_address_hi_hi_hi, c_bits_address_hi_hi_lo}; // @[Parameters.scala:230:8] wire [15:0] c_bits_address_hi = {c_bits_address_hi_hi, c_bits_address_hi_lo}; // @[Parameters.scala:230:8] assign _c_bits_address_T_29 = {c_bits_address_hi, c_bits_address_lo}; // @[Parameters.scala:230:8] assign c_bits_address = _c_bits_address_T_29; // @[SourceC.scala:108:15]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_190( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_346 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_142( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_163 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Periphery.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.debug import chisel3._ import chisel3.experimental.{noPrefix, IntParam} import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.apb.{APBBundle, APBBundleParameters, APBMasterNode, APBMasterParameters, APBMasterPortParameters} import freechips.rocketchip.interrupts.{IntSyncXbar, NullIntSyncSource} import freechips.rocketchip.jtag.JTAGIO import freechips.rocketchip.prci.{ClockSinkNode, ClockSinkParameters} import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, FBUS, ResetSynchronous, SubsystemResetSchemeKey, TLBusWrapperLocation} import freechips.rocketchip.tilelink.{TLFragmenter, TLWidthWidget} import freechips.rocketchip.util.{AsyncResetSynchronizerShiftReg, CanHavePSDTestModeIO, ClockGate, PSDTestMode, PlusArg, ResetSynchronizerShiftReg} import freechips.rocketchip.util.BooleanToAugmentedBoolean /** Protocols used for communicating with external debugging tools / sealed trait DebugExportProtocol case object DMI extends DebugExportProtocol case object JTAG extends DebugExportProtocol case object CJTAG extends DebugExportProtocol case object APB extends DebugExportProtocol /* Options for possible debug interfaces / case class DebugAttachParams( protocols: Set[DebugExportProtocol] = Set(DMI), externalDisable: Boolean = false, masterWhere: TLBusWrapperLocation = FBUS, slaveWhere: TLBusWrapperLocation = CBUS ) { def dmi = protocols.contains(DMI) def jtag = protocols.contains(JTAG) def cjtag = protocols.contains(CJTAG) def apb = protocols.contains(APB) } case object ExportDebug extends Field(DebugAttachParams()) class ClockedAPBBundle(params: APBBundleParameters) extends APBBundle(params) { val clock = Clock() val reset = Reset() } class DebugIO(implicit val p: Parameters) extends Bundle { val clock = Input(Clock()) val reset = Input(Reset()) val clockeddmi = p(ExportDebug).dmi.option(Flipped(new ClockedDMIIO())) val systemjtag = p(ExportDebug).jtag.option(new SystemJTAGIO) val apb = p(ExportDebug).apb.option(Flipped(new ClockedAPBBundle(APBBundleParameters(addrBits=12, dataBits=32)))) //------------------------------ val ndreset = Output(Bool()) val dmactive = Output(Bool()) val dmactiveAck = Input(Bool()) val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO()) val disableDebug = p(ExportDebug).externalDisable.option(Input(Bool())) } class PSDIO(implicit val p: Parameters) extends Bundle with CanHavePSDTestModeIO { } class ResetCtrlIO(val nComponents: Int)(implicit val p: Parameters) extends Bundle { val hartResetReq = (p(DebugModuleKey).exists(x=>x.hasHartResets)).option(Output(Vec(nComponents, Bool()))) val hartIsInReset = Input(Vec(nComponents, Bool())) } /* Either adds a JTAG DTM to system, and exports a JTAG interface, * or exports the Debug Module Interface (DMI), or exports and hooks up APB, * based on a global parameter. / trait HasPeripheryDebug { this: BaseSubsystem => private lazy val tlbus = locateTLBusWrapper(p(ExportDebug).slaveWhere) lazy val debugCustomXbarOpt = p(DebugModuleKey).map(params => LazyModule( new DebugCustomXbar(outputRequiresInput = false))) lazy val apbDebugNodeOpt = p(ExportDebug).apb.option(APBMasterNode(Seq(APBMasterPortParameters(Seq(APBMasterParameters("debugAPB")))))) val debugTLDomainOpt = p(DebugModuleKey).map { _ => val domain = ClockSinkNode(Seq(ClockSinkParameters())) domain := tlbus.fixedClockNode domain } lazy val debugOpt = p(DebugModuleKey).map { params => val tlDM = LazyModule(new TLDebugModule(tlbus.beatBytes)) tlDM.node := tlbus.coupleTo("debug"){ TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("Debug")) := _ } tlDM.dmInner.dmInner.customNode := debugCustomXbarOpt.get.node (apbDebugNodeOpt zip tlDM.apbNodeOpt) foreach { case (master, slave) => slave := master } tlDM.dmInner.dmInner.sb2tlOpt.foreach { sb2tl => locateTLBusWrapper(p(ExportDebug).masterWhere).coupleFrom("debug_sb") { _ := TLWidthWidget(1) := sb2tl.node } } tlDM } val debugNode = debugOpt.map(_.intnode) val psd = InModuleBody { val psd = IO(new PSDIO) psd } val resetctrl = InModuleBody { debugOpt.map { debug => debug.module.io.tl_reset := debugTLDomainOpt.get.in.head._1.reset debug.module.io.tl_clock := debugTLDomainOpt.get.in.head._1.clock val resetctrl = IO(new ResetCtrlIO(debug.dmOuter.dmOuter.intnode.edges.out.size)) debug.module.io.hartIsInReset := resetctrl.hartIsInReset resetctrl.hartResetReq.foreach { rcio => debug.module.io.hartResetReq.foreach { rcdm => rcio := rcdm }} resetctrl } } // noPrefix is workaround https://github.com/freechipsproject/chisel3/issues/1603 val debug = InModuleBody { noPrefix(debugOpt.map { debugmod => val debug = IO(new DebugIO) require(!(debug.clockeddmi.isDefined && debug.systemjtag.isDefined), "You cannot have both DMI and JTAG interface in HasPeripheryDebug") require(!(debug.clockeddmi.isDefined && debug.apb.isDefined), "You cannot have both DMI and APB interface in HasPeripheryDebug") require(!(debug.systemjtag.isDefined && debug.apb.isDefined), "You cannot have both APB and JTAG interface in HasPeripheryDebug") debug.clockeddmi.foreach { dbg => debugmod.module.io.dmi.get <> dbg } (debug.apb zip apbDebugNodeOpt zip debugmod.module.io.apb_clock zip debugmod.module.io.apb_reset).foreach { case (((io, apb), c ), r) => apb.out(0)._1 <> io c:= io.clock r:= io.reset } debugmod.module.io.debug_reset := debug.reset debugmod.module.io.debug_clock := debug.clock debug.ndreset := debugmod.module.io.ctrl.ndreset debug.dmactive := debugmod.module.io.ctrl.dmactive debugmod.module.io.ctrl.dmactiveAck := debug.dmactiveAck debug.extTrigger.foreach { x => debugmod.module.io.extTrigger.foreach {y => x <> y}} // TODO in inheriting traits: Set this to something meaningful, e.g. "component is in reset or powered down" debugmod.module.io.ctrl.debugUnavail.foreach { _ := false.B } debug })} val dtm = InModuleBody { debug.flatMap(_.systemjtag.map(instantiateJtagDTM(_))) } def instantiateJtagDTM(sj: SystemJTAGIO): DebugTransportModuleJTAG = { val dtm = Module(new DebugTransportModuleJTAG(p(DebugModuleKey).get.nDMIAddrSize, p(JtagDTMKey))) dtm.io.jtag <> sj.jtag debug.map(_.disableDebug.foreach { x => dtm.io.jtag.TMS := sj.jtag.TMS \| x }) // force TMS high when debug is disabled dtm.io.jtag_clock := sj.jtag.TCK dtm.io.jtag_reset := sj.reset dtm.io.jtag_mfr_id := sj.mfr_id dtm.io.jtag_part_number := sj.part_number dtm.io.jtag_version := sj.version dtm.rf_reset := sj.reset debugOpt.map { outerdebug => outerdebug.module.io.dmi.get.dmi <> dtm.io.dmi outerdebug.module.io.dmi.get.dmiClock := sj.jtag.TCK outerdebug.module.io.dmi.get.dmiReset := sj.reset } dtm } } /* BlackBox to export DMI interface / class SimDTM(implicit p: Parameters) extends BlackBox with HasBlackBoxResource { val io = IO(new Bundle { val clk = Input(Clock()) val reset = Input(Bool()) val debug = new DMIIO val exit = Output(UInt(32.W)) }) def connect(tbclk: Clock, tbreset: Bool, dutio: ClockedDMIIO, tbsuccess: Bool) = { io.clk := tbclk io.reset := tbreset dutio.dmi <> io.debug dutio.dmiClock := tbclk dutio.dmiReset := tbreset tbsuccess := io.exit === 1.U assert(io.exit < 2.U, " FAILED * (exit code = %d)\n", io.exit >> 1.U) } addResource("/vsrc/SimDTM.v") addResource("/csrc/SimDTM.cc") } /** BlackBox to export JTAG interface / class SimJTAG(tickDelay: Int = 50) extends BlackBox(Map("TICK_DELAY" -> IntParam(tickDelay))) with HasBlackBoxResource { val io = IO(new Bundle { val clock = Input(Clock()) val reset = Input(Bool()) val jtag = new JTAGIO(hasTRSTn = true) val enable = Input(Bool()) val init_done = Input(Bool()) val exit = Output(UInt(32.W)) }) def connect(dutio: JTAGIO, tbclock: Clock, tbreset: Bool, init_done: Bool, tbsuccess: Bool) = { dutio.TCK := io.jtag.TCK dutio.TMS := io.jtag.TMS dutio.TDI := io.jtag.TDI io.jtag.TDO := dutio.TDO io.clock := tbclock io.reset := tbreset io.enable := PlusArg("jtag_rbb_enable", 0, "Enable SimJTAG for JTAG Connections. Simulation will pause until connection is made.") io.init_done := init_done // Success is determined by the gdbserver // which is controlling this simulation. tbsuccess := io.exit === 1.U assert(io.exit < 2.U, " FAILED * (exit code = %d)\n", io.exit >> 1.U) } addResource("/vsrc/SimJTAG.v") addResource("/csrc/SimJTAG.cc") addResource("/csrc/remote_bitbang.h") addResource("/csrc/remote_bitbang.cc") } object Debug { def connectDebug( debugOpt: Option[DebugIO], resetctrlOpt: Option[ResetCtrlIO], psdio: PSDIO, c: Clock, r: Bool, out: Bool, tckHalfPeriod: Int = 2, cmdDelay: Int = 2, psd: PSDTestMode = 0.U.asTypeOf(new PSDTestMode())) (implicit p: Parameters): Unit = { connectDebugClockAndReset(debugOpt, c) resetctrlOpt.map { rcio => rcio.hartIsInReset.map { _ := r }} debugOpt.map { debug => debug.clockeddmi.foreach { d => val dtm = Module(new SimDTM).connect(c, r, d, out) } debug.systemjtag.foreach { sj => val jtag = Module(new SimJTAG(tickDelay=3)).connect(sj.jtag, c, r, ~r, out) sj.reset := r.asAsyncReset sj.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) sj.part_number := p(JtagDTMKey).idcodePartNum.U(16.W) sj.version := p(JtagDTMKey).idcodeVersion.U(4.W) } debug.apb.foreach { apb => require(false, "No support for connectDebug for an APB debug connection.") } psdio.psd.foreach { _ <> psd } debug.disableDebug.foreach { x => x := false.B } } } def connectDebugClockAndReset(debugOpt: Option[DebugIO], c: Clock, sync: Boolean = true)(implicit p: Parameters): Unit = { debugOpt.foreach { debug => val dmi_reset = debug.clockeddmi.map(_.dmiReset.asBool).getOrElse(false.B) \| debug.systemjtag.map(_.reset.asBool).getOrElse(false.B) \| debug.apb.map(_.reset.asBool).getOrElse(false.B) connectDebugClockHelper(debug, dmi_reset, c, sync) } } def connectDebugClockHelper(debug: DebugIO, dmi_reset: Reset, c: Clock, sync: Boolean = true)(implicit p: Parameters): Unit = { val debug_reset = Wire(Bool()) withClockAndReset(c, dmi_reset) { val debug_reset_syncd = if(sync) ~AsyncResetSynchronizerShiftReg(in=true.B, sync=3, name=Some("debug_reset_sync")) else dmi_reset debug_reset := debug_reset_syncd } // Need to clock DM during debug_reset because of synchronous reset, so keep // the clock alive for one cycle after debug_reset asserts to action this behavior. // The unit should also be clocked when dmactive is high. withClockAndReset(c, debug_reset.asAsyncReset) { val dmactiveAck = if (sync) ResetSynchronizerShiftReg(in=debug.dmactive, sync=3, name=Some("dmactiveAck")) else debug.dmactive val clock_en = RegNext(next=dmactiveAck, init=true.B) val gated_clock = if (!p(DebugModuleKey).get.clockGate) c else ClockGate(c, clock_en, "debug_clock_gate") debug.clock := gated_clock debug.reset := (if (p(SubsystemResetSchemeKey)==ResetSynchronous) debug_reset else debug_reset.asAsyncReset) debug.dmactiveAck := dmactiveAck } } def tieoffDebug(debugOpt: Option[DebugIO], resetctrlOpt: Option[ResetCtrlIO] = None, psdio: Option[PSDIO] = None)(implicit p: Parameters): Bool = { psdio.foreach(_.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode()) } ) resetctrlOpt.map { rcio => rcio.hartIsInReset.map { _ := false.B }} debugOpt.map { debug => debug.clock := true.B.asClock debug.reset := (if (p(SubsystemResetSchemeKey)==ResetSynchronous) true.B else true.B.asAsyncReset) debug.systemjtag.foreach { sj => sj.jtag.TCK := true.B.asClock sj.jtag.TMS := true.B sj.jtag.TDI := true.B sj.jtag.TRSTn.foreach { r => r := true.B } sj.reset := true.B.asAsyncReset sj.mfr_id := 0.U sj.part_number := 0.U sj.version := 0.U } debug.clockeddmi.foreach { d => d.dmi.req.valid := false.B d.dmi.req.bits.addr := 0.U d.dmi.req.bits.data := 0.U d.dmi.req.bits.op := 0.U d.dmi.resp.ready := true.B d.dmiClock := false.B.asClock d.dmiReset := true.B.asAsyncReset } debug.apb.foreach { apb => apb.clock := false.B.asClock apb.reset := true.B.asAsyncReset apb.pready := false.B apb.pslverr := false.B apb.prdata := 0.U apb.pduser := 0.U.asTypeOf(chiselTypeOf(apb.pduser)) apb.psel := false.B apb.penable := false.B } debug.extTrigger.foreach { t => t.in.req := false.B t.out.ack := t.out.req } debug.disableDebug.foreach { x => x := false.B } debug.dmactiveAck := false.B debug.ndreset }.getOrElse(false.B) } } File HasChipyardPRCI.scala: package chipyard.clocking import chisel3._ import scala.collection.mutable.{ArrayBuffer} import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.prci._ import testchipip.boot.{TLTileResetCtrl} import testchipip.clocking.{ClockGroupFakeResetSynchronizer} case class ChipyardPRCIControlParams( slaveWhere: TLBusWrapperLocation = CBUS, baseAddress: BigInt = 0x100000, enableTileClockGating: Boolean = true, enableTileResetSetting: Boolean = true, enableResetSynchronizers: Boolean = true // this should only be disabled to work around verilator async-reset initialization problems ) { def generatePRCIXBar = enableTileClockGating \|\| enableTileResetSetting } case object ChipyardPRCIControlKey extends Field[ChipyardPRCIControlParams](ChipyardPRCIControlParams()) trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElements => require(!p(SubsystemDriveClockGroupsFromIO), "Subsystem allClockGroups cannot be driven from implicit clocks") val prciParams = p(ChipyardPRCIControlKey) // Set up clock domain private val tlbus = locateTLBusWrapper(prciParams.slaveWhere) val prci_ctrl_domain = tlbus.generateSynchronousDomain("ChipyardPRCICtrl") .suggestName("chipyard_prcictrl_domain") val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar(nameSuffix = Some("prcibus")) } } prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar := TLFIFOFixer(TLFIFOFixer.all) := TLBuffer() := _) }) // Aggregate all the clock groups into a single node val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node // The diplomatic clocks in the subsystem are routed to this allClockGroupsNode val clockNamePrefixer = ClockGroupNamePrefixer() (allClockGroupsNode := clockNamePrefixer := aggregator) // Once all the clocks are gathered in the aggregator node, several steps remain // 1. Assign frequencies to any clock groups which did not specify a frequency. // 2. Combine duplicated clock groups (clock groups which physically should be in the same clock domain) // 3. Synchronize reset to each clock group // 4. Clock gate the clock groups corresponding to Tiles (if desired). // 5. Add reset control registers to the tiles (if desired) // The final clock group here contains physically distinct clock domains, which some PRCI node in a // diplomatic IOBinder should drive val frequencySpecifier = ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey)) val clockGroupCombiner = ClockGroupCombiner() val resetSynchronizer = prci_ctrl_domain { if (prciParams.enableResetSynchronizers) ClockGroupResetSynchronizer() else ClockGroupFakeResetSynchronizer() } val tileClockGater = Option.when(prciParams.enableTileClockGating) { prci_ctrl_domain { val clock_gater = LazyModule(new TileClockGater(prciParams.baseAddress + 0x00000, tlbus.beatBytes)) clock_gater.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileClockGater")) := prci_ctrl_bus.get clock_gater } } val tileResetSetter = Option.when(prciParams.enableTileResetSetting) { prci_ctrl_domain { val reset_setter = LazyModule(new TileResetSetter(prciParams.baseAddress + 0x10000, tlbus.beatBytes, tile_prci_domains.map(_._2.tile_reset_domain.clockNode.portParams(0).name.get).toSeq, Nil)) reset_setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileResetSetter")) := prci_ctrl_bus.get reset_setter } } if (!prciParams.enableResetSynchronizers) { println(Console.RED + s""" !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! WARNING: DISABLING THE RESET SYNCHRONIZERS RESULTS IN A BROKEN DESIGN THAT WILL NOT BEHAVE PROPERLY AS ASIC OR FPGA. THESE SHOULD ONLY BE DISABLED TO WORK AROUND LIMITATIONS IN ASYNC RESET INITIALIZATION IN RTL SIMULATORS, NAMELY VERILATOR. !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! """ + Console.RESET) } // The chiptopClockGroupsNode shouuld be what ClockBinders attach to val chiptopClockGroupsNode = ClockGroupEphemeralNode() (aggregator := frequencySpecifier := clockGroupCombiner := resetSynchronizer := tileClockGater.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp"))) := tileResetSetter.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp"))) := chiptopClockGroupsNode) } File UART.scala: package sifive.blocks.devices.uart import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.interrupts._ import freechips.rocketchip.prci._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.util._ import sifive.blocks.util._ /** UART parameters * * @param address uart device TL base address * @param dataBits number of bits in data frame * @param stopBits number of stop bits * @param divisorBits width of baud rate divisor * @param oversample constructs the times of sampling for every data bit * @param nSamples number of reserved Rx sampling result for decide one data bit * @param nTxEntries number of entries in fifo between TL bus and Tx * @param nRxEntries number of entries in fifo between TL bus and Rx * @param includeFourWire additional CTS/RTS ports for flow control * @param includeParity parity support * @param includeIndependentParity Tx and Rx have opposite parity modes * @param initBaudRate initial baud rate * * @note baud rate divisor = clk frequency / baud rate. It means the number of clk period for one data bit. * Calculated in [[UARTAttachParams.attachTo()]] * * @example To configure a 8N1 UART with features below: * {{{ * 8 entries of Tx and Rx fifo * Baud rate = 115200 * Rx samples each data bit 16 times * Uses 3 sample result for each data bit * }}} * Set the stopBits as below and keep the other parameter unchanged * {{{ * stopBits = 1 * }}} * / case class UARTParams( address: BigInt, dataBits: Int = 8, stopBits: Int = 2, divisorBits: Int = 16, oversample: Int = 4, nSamples: Int = 3, nTxEntries: Int = 8, nRxEntries: Int = 8, includeFourWire: Boolean = false, includeParity: Boolean = false, includeIndependentParity: Boolean = false, // Tx and Rx have opposite parity modes initBaudRate: BigInt = BigInt(115200), ) extends DeviceParams { def oversampleFactor = 1 << oversample require(divisorBits > oversample) require(oversampleFactor > nSamples) require((dataBits == 8) \|\| (dataBits == 9)) } class UARTPortIO(val c: UARTParams) extends Bundle { val txd = Output(Bool()) val rxd = Input(Bool()) val cts_n = c.includeFourWire.option(Input(Bool())) val rts_n = c.includeFourWire.option(Output(Bool())) } class UARTInterrupts extends Bundle { val rxwm = Bool() val txwm = Bool() } //abstract class UART(busWidthBytes: Int, val c: UARTParams, divisorInit: Int = 0) /* UART Module organizes Tx and Rx module with fifo and generates control signals for them according to CSRs and UART parameters. * * ==Component== * - Tx * - Tx fifo * - Rx * - Rx fifo * - TL bus to soc * * ==IO== * [[UARTPortIO]] * * ==Datapass== * {{{ * TL bus -> Tx fifo -> Tx * TL bus <- Rx fifo <- Rx * }}} * * @param divisorInit: number of clk period for one data bit / class UART(busWidthBytes: Int, val c: UARTParams, divisorInit: Int = 0) (implicit p: Parameters) extends IORegisterRouter( RegisterRouterParams( name = "serial", compat = Seq("sifive,uart0"), base = c.address, beatBytes = busWidthBytes), new UARTPortIO(c)) //with HasInterruptSources { with HasInterruptSources with HasTLControlRegMap { def nInterrupts = 1 + c.includeParity.toInt ResourceBinding { Resource(ResourceAnchors.aliases, "uart").bind(ResourceAlias(device.label)) } require(divisorInit != 0, "UART divisor wasn't initialized during instantiation") require(divisorInit >> c.divisorBits == 0, s"UART divisor reg (width $c.divisorBits) not wide enough to hold $divisorInit") lazy val module = new LazyModuleImp(this) { val txm = Module(new UARTTx(c)) val txq = Module(new Queue(UInt(c.dataBits.W), c.nTxEntries)) val rxm = Module(new UARTRx(c)) val rxq = Module(new Queue(UInt(c.dataBits.W), c.nRxEntries)) val div = RegInit(divisorInit.U(c.divisorBits.W)) private val stopCountBits = log2Up(c.stopBits) private val txCountBits = log2Floor(c.nTxEntries) + 1 private val rxCountBits = log2Floor(c.nRxEntries) + 1 val txen = RegInit(false.B) val rxen = RegInit(false.B) val enwire4 = RegInit(false.B) val invpol = RegInit(false.B) val enparity = RegInit(false.B) val parity = RegInit(false.B) // Odd parity - 1 , Even parity - 0 val errorparity = RegInit(false.B) val errie = RegInit(false.B) val txwm = RegInit(0.U(txCountBits.W)) val rxwm = RegInit(0.U(rxCountBits.W)) val nstop = RegInit(0.U(stopCountBits.W)) val data8or9 = RegInit(true.B) if (c.includeFourWire){ txm.io.en := txen && (!port.cts_n.get \|\| !enwire4) txm.io.cts_n.get := port.cts_n.get } else txm.io.en := txen txm.io.in <> txq.io.deq txm.io.div := div txm.io.nstop := nstop port.txd := txm.io.out if (c.dataBits == 9) { txm.io.data8or9.get := data8or9 rxm.io.data8or9.get := data8or9 } rxm.io.en := rxen rxm.io.in := port.rxd rxq.io.enq.valid := rxm.io.out.valid rxq.io.enq.bits := rxm.io.out.bits rxm.io.div := div val tx_busy = (txm.io.tx_busy \|\| txq.io.count.orR) && txen port.rts_n.foreach { r => r := Mux(enwire4, !(rxq.io.count < c.nRxEntries.U), tx_busy ^ invpol) } if (c.includeParity) { txm.io.enparity.get := enparity txm.io.parity.get := parity rxm.io.parity.get := parity ^ c.includeIndependentParity.B // independent parity on tx and rx rxm.io.enparity.get := enparity errorparity := rxm.io.errorparity.get \|\| errorparity interrupts(1) := errorparity && errie } val ie = RegInit(0.U.asTypeOf(new UARTInterrupts())) val ip = Wire(new UARTInterrupts) ip.txwm := (txq.io.count < txwm) ip.rxwm := (rxq.io.count > rxwm) interrupts(0) := (ip.txwm && ie.txwm) \|\| (ip.rxwm && ie.rxwm) val mapping = Seq( UARTCtrlRegs.txfifo -> RegFieldGroup("txdata",Some("Transmit data"), NonBlockingEnqueue(txq.io.enq)), UARTCtrlRegs.rxfifo -> RegFieldGroup("rxdata",Some("Receive data"), NonBlockingDequeue(rxq.io.deq)), UARTCtrlRegs.txctrl -> RegFieldGroup("txctrl",Some("Serial transmit control"),Seq( RegField(1, txen, RegFieldDesc("txen","Transmit enable", reset=Some(0))), RegField(stopCountBits, nstop, RegFieldDesc("nstop","Number of stop bits", reset=Some(0))))), UARTCtrlRegs.rxctrl -> Seq(RegField(1, rxen, RegFieldDesc("rxen","Receive enable", reset=Some(0)))), UARTCtrlRegs.txmark -> Seq(RegField(txCountBits, txwm, RegFieldDesc("txcnt","Transmit watermark level", reset=Some(0)))), UARTCtrlRegs.rxmark -> Seq(RegField(rxCountBits, rxwm, RegFieldDesc("rxcnt","Receive watermark level", reset=Some(0)))), UARTCtrlRegs.ie -> RegFieldGroup("ie",Some("Serial interrupt enable"),Seq( RegField(1, ie.txwm, RegFieldDesc("txwm_ie","Transmit watermark interrupt enable", reset=Some(0))), RegField(1, ie.rxwm, RegFieldDesc("rxwm_ie","Receive watermark interrupt enable", reset=Some(0))))), UARTCtrlRegs.ip -> RegFieldGroup("ip",Some("Serial interrupt pending"),Seq( RegField.r(1, ip.txwm, RegFieldDesc("txwm_ip","Transmit watermark interrupt pending", volatile=true)), RegField.r(1, ip.rxwm, RegFieldDesc("rxwm_ip","Receive watermark interrupt pending", volatile=true)))), UARTCtrlRegs.div -> Seq( RegField(c.divisorBits, div, RegFieldDesc("div","Baud rate divisor",reset=Some(divisorInit)))) ) val optionalparity = if (c.includeParity) Seq( UARTCtrlRegs.parity -> RegFieldGroup("paritygenandcheck",Some("Odd/Even Parity Generation/Checking"),Seq( RegField(1, enparity, RegFieldDesc("enparity","Enable Parity Generation/Checking", reset=Some(0))), RegField(1, parity, RegFieldDesc("parity","Odd(1)/Even(0) Parity", reset=Some(0))), RegField(1, errorparity, RegFieldDesc("errorparity","Parity Status Sticky Bit", reset=Some(0))), RegField(1, errie, RegFieldDesc("errie","Interrupt on error in parity enable", reset=Some(0)))))) else Nil val optionalwire4 = if (c.includeFourWire) Seq( UARTCtrlRegs.wire4 -> RegFieldGroup("wire4",Some("Configure Clear-to-send / Request-to-send ports / RS-485"),Seq( RegField(1, enwire4, RegFieldDesc("enwire4","Enable CTS/RTS(1) or RS-485(0)", reset=Some(0))), RegField(1, invpol, RegFieldDesc("invpol","Invert polarity of RTS in RS-485 mode", reset=Some(0))) ))) else Nil val optional8or9 = if (c.dataBits == 9) Seq( UARTCtrlRegs.either8or9 -> RegFieldGroup("ConfigurableDataBits",Some("Configure number of data bits to be transmitted"),Seq( RegField(1, data8or9, RegFieldDesc("databits8or9","Data Bits to be 8(1) or 9(0)", reset=Some(1)))))) else Nil regmap(mapping ++ optionalparity ++ optionalwire4 ++ optional8or9:_) } } class TLUART(busWidthBytes: Int, params: UARTParams, divinit: Int)(implicit p: Parameters) extends UART(busWidthBytes, params, divinit) with HasTLControlRegMap case class UARTLocated(loc: HierarchicalLocation) extends Field[Seq[UARTAttachParams]](Nil) case class UARTAttachParams( device: UARTParams, controlWhere: TLBusWrapperLocation = PBUS, blockerAddr: Option[BigInt] = None, controlXType: ClockCrossingType = NoCrossing, intXType: ClockCrossingType = NoCrossing) extends DeviceAttachParams { def attachTo(where: Attachable)(implicit p: Parameters): TLUART = where { val name = s"uart_${UART.nextId()}" val tlbus = where.locateTLBusWrapper(controlWhere) val divinit = (tlbus.dtsFrequency.get / device.initBaudRate).toInt val uartClockDomainWrapper = LazyModule(new ClockSinkDomain(take = None, name = Some("TLUART"))) val uart = uartClockDomainWrapper { LazyModule(new TLUART(tlbus.beatBytes, device, divinit)) } uart.suggestName(name) tlbus.coupleTo(s"device_named_$name") { bus => val blockerOpt = blockerAddr.map { a => val blocker = LazyModule(new TLClockBlocker(BasicBusBlockerParams(a, tlbus.beatBytes, tlbus.beatBytes))) tlbus.coupleTo(s"bus_blocker_for_$name") { blocker.controlNode := TLFragmenter(tlbus, Some("UART_Blocker")) := _ } blocker } uartClockDomainWrapper.clockNode := (controlXType match { case _: SynchronousCrossing => tlbus.dtsClk.map(_.bind(uart.device)) tlbus.fixedClockNode case _: RationalCrossing => tlbus.clockNode case _: AsynchronousCrossing => val uartClockGroup = ClockGroup() uartClockGroup := where.allClockGroupsNode blockerOpt.map { _.clockNode := uartClockGroup } .getOrElse { uartClockGroup } }) (uart.controlXing(controlXType) := TLFragmenter(tlbus, Some("UART")) := blockerOpt.map { _.node := bus } .getOrElse { bus }) } (intXType match { case _: SynchronousCrossing => where.ibus.fromSync case _: RationalCrossing => where.ibus.fromRational case _: AsynchronousCrossing => where.ibus.fromAsync }) := uart.intXing(intXType) uart } } object UART { val nextId = { var i = -1; () => { i += 1; i} } def makePort(node: BundleBridgeSource[UARTPortIO], name: String)(implicit p: Parameters): ModuleValue[UARTPortIO] = { val uartNode = node.makeSink() InModuleBody { uartNode.makeIO()(ValName(name)) } } def tieoff(port: UARTPortIO) { port.rxd := 1.U if (port.c.includeFourWire) { port.cts_n.foreach { ct => ct := false.B } // active-low } } def loopback(port: UARTPortIO) { port.rxd := port.txd if (port.c.includeFourWire) { port.cts_n.get := port.rts_n.get } } } /* Copyright 2016 SiFive, Inc. Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. / File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File MemoryBus.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.{BuiltInDevices, HasBuiltInDeviceParams, BuiltInErrorDeviceParams, BuiltInZeroDeviceParams} import freechips.rocketchip.tilelink.{ ReplicatedRegion, HasTLBusParams, HasRegionReplicatorParams, TLBusWrapper, TLBusWrapperInstantiationLike, RegionReplicator, TLXbar, TLInwardNode, TLOutwardNode, ProbePicker, TLEdge, TLFIFOFixer } import freechips.rocketchip.util.Location /* Parameterization of the memory-side bus created for each memory channel / case class MemoryBusParams( beatBytes: Int, blockBytes: Int, dtsFrequency: Option[BigInt] = None, zeroDevice: Option[BuiltInZeroDeviceParams] = None, errorDevice: Option[BuiltInErrorDeviceParams] = None, replication: Option[ReplicatedRegion] = None) extends HasTLBusParams with HasBuiltInDeviceParams with HasRegionReplicatorParams with TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): MemoryBus = { val mbus = LazyModule(new MemoryBus(this, loc.name)) mbus.suggestName(loc.name) context.tlBusWrapperLocationMap += (loc -> mbus) mbus } } /* Wrapper for creating TL nodes from a bus connected to the back of each mem channel / class MemoryBus(params: MemoryBusParams, name: String = "memory_bus")(implicit p: Parameters) extends TLBusWrapper(params, name)(p) { private val replicator = params.replication.map(r => LazyModule(new RegionReplicator(r))) val prefixNode = replicator.map { r => r.prefix := addressPrefixNexusNode addressPrefixNexusNode } private val xbar = LazyModule(new TLXbar(nameSuffix = Some(name))).suggestName(busName + "_xbar") val inwardNode: TLInwardNode = replicator.map(xbar.node :=* TLFIFOFixer(TLFIFOFixer.all) := _.node) .getOrElse(xbar.node := TLFIFOFixer(TLFIFOFixer.all)) val outwardNode: TLOutwardNode = ProbePicker() := xbar.node def busView: TLEdge = xbar.node.edges.in.head val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode) } File CanHaveClockTap.scala: package chipyard.clocking import chisel3._ import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.prci._ case object ClockTapKey extends Field[Boolean](true) trait CanHaveClockTap { this: BaseSubsystem => require(!p(SubsystemDriveClockGroupsFromIO), "Subsystem must not drive clocks from IO") val clockTapNode = Option.when(p(ClockTapKey)) { val clockTap = ClockSinkNode(Seq(ClockSinkParameters(name=Some("clock_tap")))) clockTap := ClockGroup() := allClockGroupsNode clockTap } val clockTapIO = clockTapNode.map { node => InModuleBody { val clock_tap = IO(Output(Clock())) clock_tap := node.in.head._1.clock clock_tap }} } File PeripheryBus.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.{BuiltInZeroDeviceParams, BuiltInErrorDeviceParams, HasBuiltInDeviceParams, BuiltInDevices} import freechips.rocketchip.diplomacy.BufferParams import freechips.rocketchip.tilelink.{ RegionReplicator, ReplicatedRegion, HasTLBusParams, HasRegionReplicatorParams, TLBusWrapper, TLBusWrapperInstantiationLike, TLFIFOFixer, TLNode, TLXbar, TLInwardNode, TLOutwardNode, TLBuffer, TLWidthWidget, TLAtomicAutomata, TLEdge } import freechips.rocketchip.util.Location case class BusAtomics( arithmetic: Boolean = true, buffer: BufferParams = BufferParams.default, widenBytes: Option[Int] = None ) case class PeripheryBusParams( beatBytes: Int, blockBytes: Int, atomics: Option[BusAtomics] = Some(BusAtomics()), dtsFrequency: Option[BigInt] = None, zeroDevice: Option[BuiltInZeroDeviceParams] = None, errorDevice: Option[BuiltInErrorDeviceParams] = None, replication: Option[ReplicatedRegion] = None) extends HasTLBusParams with HasBuiltInDeviceParams with HasRegionReplicatorParams with TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): PeripheryBus = { val pbus = LazyModule(new PeripheryBus(this, loc.name)) pbus.suggestName(loc.name) context.tlBusWrapperLocationMap += (loc -> pbus) pbus } } class PeripheryBus(params: PeripheryBusParams, name: String)(implicit p: Parameters) extends TLBusWrapper(params, name) { override lazy val desiredName = s"PeripheryBus_$name" private val replicator = params.replication.map(r => LazyModule(new RegionReplicator(r))) val prefixNode = replicator.map { r => r.prefix := addressPrefixNexusNode addressPrefixNexusNode } private val fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all)) private val node: TLNode = params.atomics.map { pa => val in_xbar = LazyModule(new TLXbar(nameSuffix = Some(s"${name}_in"))) val out_xbar = LazyModule(new TLXbar(nameSuffix = Some(s"${name}_out"))) val fixer_node = replicator.map(fixer.node := _.node).getOrElse(fixer.node) (out_xbar.node := fixer_node := TLBuffer(pa.buffer) := (pa.widenBytes.filter(_ > beatBytes).map { w => TLWidthWidget(w) := TLAtomicAutomata(arithmetic = pa.arithmetic, nameSuffix = Some(name)) } .getOrElse { TLAtomicAutomata(arithmetic = pa.arithmetic, nameSuffix = Some(name)) }) := in_xbar.node) } .getOrElse { TLXbar() := fixer.node } def inwardNode: TLInwardNode = node def outwardNode: TLOutwardNode = node def busView: TLEdge = fixer.node.edges.in.head val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode) } File BankedCoherenceParams.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.BuiltInDevices import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.interrupts.IntOutwardNode import freechips.rocketchip.tilelink.{ TLBroadcast, HasTLBusParams, BroadcastFilter, TLBusWrapper, TLBusWrapperInstantiationLike, TLJbar, TLEdge, TLOutwardNode, TLTempNode, TLInwardNode, BankBinder, TLBroadcastParams, TLBroadcastControlParams, TLBuffer, TLFragmenter, TLNameNode } import freechips.rocketchip.util.Location import CoherenceManagerWrapper._ /** Global cache coherence granularity, which applies to all caches, for now. / case object CacheBlockBytes extends Field[Int](64) /* LLC Broadcast Hub configuration / case object BroadcastKey extends Field(BroadcastParams()) case class BroadcastParams( nTrackers: Int = 4, bufferless: Boolean = false, controlAddress: Option[BigInt] = None, filterFactory: TLBroadcast.ProbeFilterFactory = BroadcastFilter.factory) /* Coherence manager configuration / case object SubsystemBankedCoherenceKey extends Field(BankedCoherenceParams()) case class ClusterBankedCoherenceKey(clusterId: Int) extends Field(BankedCoherenceParams(nBanks=0)) case class BankedCoherenceParams( nBanks: Int = 1, coherenceManager: CoherenceManagerInstantiationFn = broadcastManager ) { require (isPow2(nBanks) \|\| nBanks == 0) } case class CoherenceManagerWrapperParams( blockBytes: Int, beatBytes: Int, nBanks: Int, name: String, dtsFrequency: Option[BigInt] = None) (val coherenceManager: CoherenceManagerInstantiationFn) extends HasTLBusParams with TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): CoherenceManagerWrapper = { val cmWrapper = LazyModule(new CoherenceManagerWrapper(this, context)) cmWrapper.suggestName(loc.name + "_wrapper") cmWrapper.halt.foreach { context.anyLocationMap += loc.halt(_) } context.tlBusWrapperLocationMap += (loc -> cmWrapper) cmWrapper } } class CoherenceManagerWrapper(params: CoherenceManagerWrapperParams, context: HasTileLinkLocations)(implicit p: Parameters) extends TLBusWrapper(params, params.name) { val (tempIn, tempOut, halt) = params.coherenceManager(context) private val coherent_jbar = LazyModule(new TLJbar) def busView: TLEdge = coherent_jbar.node.edges.out.head val inwardNode = tempIn := coherent_jbar.node val builtInDevices = BuiltInDevices.none val prefixNode = None private def banked(node: TLOutwardNode): TLOutwardNode = if (params.nBanks == 0) node else { TLTempNode() :=* BankBinder(params.nBanks, params.blockBytes) := node } val outwardNode = banked(tempOut) } object CoherenceManagerWrapper { type CoherenceManagerInstantiationFn = HasTileLinkLocations => (TLInwardNode, TLOutwardNode, Option[IntOutwardNode]) def broadcastManagerFn( name: String, location: HierarchicalLocation, controlPortsSlaveWhere: TLBusWrapperLocation ): CoherenceManagerInstantiationFn = { context => implicit val p = context.p val cbus = context.locateTLBusWrapper(controlPortsSlaveWhere) val BroadcastParams(nTrackers, bufferless, controlAddress, filterFactory) = p(BroadcastKey) val bh = LazyModule(new TLBroadcast(TLBroadcastParams( lineBytes = p(CacheBlockBytes), numTrackers = nTrackers, bufferless = bufferless, control = controlAddress.map(x => TLBroadcastControlParams(AddressSet(x, 0xfff), cbus.beatBytes)), filterFactory = filterFactory))) bh.suggestName(name) bh.controlNode.foreach { _ := cbus.coupleTo(s"${name}_ctrl") { TLBuffer(1) := TLFragmenter(cbus) := _ } } bh.intNode.foreach { context.ibus.fromSync := _ } (bh.node, bh.node, None) } val broadcastManager = broadcastManagerFn("broadcast", InSystem, CBUS) val incoherentManager: CoherenceManagerInstantiationFn = { _ => val node = TLNameNode("no_coherence_manager") (node, node, None) } } File HasTiles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.debug.TLDebugModule import freechips.rocketchip.diplomacy.{DisableMonitors, FlipRendering} import freechips.rocketchip.interrupts.{IntXbar, IntSinkNode, IntSinkPortSimple, IntSyncAsyncCrossingSink} import freechips.rocketchip.tile.{MaxHartIdBits, BaseTile, InstantiableTileParams, TileParams, TilePRCIDomain, TraceBundle, PriorityMuxHartIdFromSeq} import freechips.rocketchip.tilelink.TLWidthWidget import freechips.rocketchip.prci.{ClockGroup, BundleBridgeBlockDuringReset, NoCrossing, SynchronousCrossing, CreditedCrossing, RationalCrossing, AsynchronousCrossing} import freechips.rocketchip.rocket.TracedInstruction import freechips.rocketchip.util.TraceCoreInterface import scala.collection.immutable.SortedMap /* Entry point for Config-uring the presence of Tiles / case class TilesLocated(loc: HierarchicalLocation) extends Field[Seq[CanAttachTile]](Nil) /* List of HierarchicalLocations which might contain a Tile / case object PossibleTileLocations extends Field[Seq[HierarchicalLocation]](Nil) /* For determining static tile id / case object NumTiles extends Field[Int](0) /* Whether to add timing-closure registers along the path of the hart id * as it propagates through the subsystem and into the tile. * * These are typically only desirable when a dynamically programmable prefix is being combined * with the static hart id via [[freechips.rocketchip.subsystem.HasTiles.tileHartIdNexusNode]]. / case object InsertTimingClosureRegistersOnHartIds extends Field[Boolean](false) /* Whether per-tile hart ids are going to be driven as inputs into a HasTiles block, * and if so, what their width should be. / case object HasTilesExternalHartIdWidthKey extends Field[Option[Int]](None) /* Whether per-tile reset vectors are going to be driven as inputs into a HasTiles block. * * Unlike the hart ids, the reset vector width is determined by the sinks within the tiles, * based on the size of the address map visible to the tiles. / case object HasTilesExternalResetVectorKey extends Field[Boolean](true) /* These are sources of "constants" that are driven into the tile. * * While they are not expected to change dyanmically while the tile is executing code, * they may be either tied to a contant value or programmed during boot or reset. * They need to be instantiated before tiles are attached within the subsystem containing them. / trait HasTileInputConstants { this: LazyModule with Attachable with InstantiatesHierarchicalElements => /* tileHartIdNode is used to collect publishers and subscribers of hartids. / val tileHartIdNodes: SortedMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i => (i, BundleBridgeEphemeralNode[UInt]()) }.to(SortedMap) /* tileHartIdNexusNode is a BundleBridgeNexus that collects dynamic hart prefixes. * * Each "prefix" input is actually the same full width as the outer hart id; the expected usage * is that each prefix source would set only some non-overlapping portion of the bits to non-zero values. * This node orReduces them, and further combines the reduction with the static ids assigned to each tile, * producing a unique, dynamic hart id for each tile. * * If p(InsertTimingClosureRegistersOnHartIds) is set, the input and output values are registered. * * The output values are [[dontTouch]]'d to prevent constant propagation from pulling the values into * the tiles if they are constant, which would ruin deduplication of tiles that are otherwise homogeneous. / val tileHartIdNexusNode = LazyModule(new BundleBridgeNexus[UInt]( inputFn = BundleBridgeNexus.orReduction[UInt](registered = p(InsertTimingClosureRegistersOnHartIds)) _, outputFn = (prefix: UInt, n: Int) => Seq.tabulate(n) { i => val y = dontTouch(prefix \| totalTileIdList(i).U(p(MaxHartIdBits).W)) // dontTouch to keep constant prop from breaking tile dedup if (p(InsertTimingClosureRegistersOnHartIds)) BundleBridgeNexus.safeRegNext(y) else y }, default = Some(() => 0.U(p(MaxHartIdBits).W)), inputRequiresOutput = true, // guard against this being driven but then ignored in tileHartIdIONodes below shouldBeInlined = false // can't inline something whose output we are are dontTouching )).node // TODO: Replace the DebugModuleHartSelFuncs config key with logic to consume the dynamic hart IDs /* tileResetVectorNode is used to collect publishers and subscribers of tile reset vector addresses. / val tileResetVectorNodes: SortedMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i => (i, BundleBridgeEphemeralNode[UInt]()) }.to(SortedMap) /* tileResetVectorNexusNode is a BundleBridgeNexus that accepts a single reset vector source, and broadcasts it to all tiles. / val tileResetVectorNexusNode = BundleBroadcast[UInt]( inputRequiresOutput = true // guard against this being driven but ignored in tileResetVectorIONodes below ) /* tileHartIdIONodes may generate subsystem IOs, one per tile, allowing the parent to assign unique hart ids. * * Or, if such IOs are not configured to exist, tileHartIdNexusNode is used to supply an id to each tile. / val tileHartIdIONodes: Seq[BundleBridgeSource[UInt]] = p(HasTilesExternalHartIdWidthKey) match { case Some(w) => (0 until nTotalTiles).map { i => val hartIdSource = BundleBridgeSource(() => UInt(w.W)) tileHartIdNodes(i) := hartIdSource hartIdSource } case None => { (0 until nTotalTiles).map { i => tileHartIdNodes(i) := tileHartIdNexusNode } Nil } } /** tileResetVectorIONodes may generate subsystem IOs, one per tile, allowing the parent to assign unique reset vectors. * * Or, if such IOs are not configured to exist, tileResetVectorNexusNode is used to supply a single reset vector to every tile. / val tileResetVectorIONodes: Seq[BundleBridgeSource[UInt]] = p(HasTilesExternalResetVectorKey) match { case true => (0 until nTotalTiles).map { i => val resetVectorSource = BundleBridgeSource[UInt]() tileResetVectorNodes(i) := resetVectorSource resetVectorSource } case false => { (0 until nTotalTiles).map { i => tileResetVectorNodes(i) := tileResetVectorNexusNode } Nil } } } /** These are sinks of notifications that are driven out from the tile. * * They need to be instantiated before tiles are attached to the subsystem containing them. / trait HasTileNotificationSinks { this: LazyModule => val tileHaltXbarNode = IntXbar() val tileHaltSinkNode = IntSinkNode(IntSinkPortSimple()) tileHaltSinkNode := tileHaltXbarNode val tileWFIXbarNode = IntXbar() val tileWFISinkNode = IntSinkNode(IntSinkPortSimple()) tileWFISinkNode := tileWFIXbarNode val tileCeaseXbarNode = IntXbar() val tileCeaseSinkNode = IntSinkNode(IntSinkPortSimple()) tileCeaseSinkNode := tileCeaseXbarNode } /* Standardized interface by which parameterized tiles can be attached to contexts containing interconnect resources. * * Sub-classes of this trait can optionally override the individual connect functions in order to specialize * their attachment behaviors, but most use cases should be be handled simply by changing the implementation * of the injectNode functions in crossingParams. / trait CanAttachTile { type TileType <: BaseTile type TileContextType <: DefaultHierarchicalElementContextType def tileParams: InstantiableTileParams[TileType] def crossingParams: HierarchicalElementCrossingParamsLike /* Narrow waist through which all tiles are intended to pass while being instantiated. / def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: SortedMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = { val clockSinkParams = tileParams.clockSinkParams.copy(name = Some(tileParams.uniqueName)) val tile_prci_domain = LazyModule(new TilePRCIDomain[TileType](clockSinkParams, crossingParams) { self => val element = self.element_reset_domain { LazyModule(tileParams.instantiate(crossingParams, PriorityMuxHartIdFromSeq(allTileParams))) } }) tile_prci_domain } /* A default set of connections that need to occur for most tile types / def connect(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { connectMasterPorts(domain, context) connectSlavePorts(domain, context) connectInterrupts(domain, context) connectPRC(domain, context) connectOutputNotifications(domain, context) connectInputConstants(domain, context) connectTrace(domain, context) } /* Connect the port where the tile is the master to a TileLink interconnect. / def connectMasterPorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = { implicit val p = context.p val dataBus = context.locateTLBusWrapper(crossingParams.master.where) dataBus.coupleFrom(tileParams.baseName) { bus => bus := crossingParams.master.injectNode(context) :=* domain.crossMasterPort(crossingParams.crossingType) } } /** Connect the port where the tile is the slave to a TileLink interconnect. / def connectSlavePorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = { implicit val p = context.p DisableMonitors { implicit p => val controlBus = context.locateTLBusWrapper(crossingParams.slave.where) controlBus.coupleTo(tileParams.baseName) { bus => domain.crossSlavePort(crossingParams.crossingType) := crossingParams.slave.injectNode(context) := TLWidthWidget(controlBus.beatBytes) := bus } } } /** Connect the various interrupts sent to and and raised by the tile. / def connectInterrupts(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p // NOTE: The order of calls to := matters! They must match how interrupts // are decoded from tile.intInwardNode inside the tile. For this reason, // we stub out missing interrupts with constant sources here. // 1. Debug interrupt is definitely asynchronous in all cases. domain.element.intInwardNode := domain { IntSyncAsyncCrossingSink(3) } := context.debugNodes(domain.element.tileId) // 2. The CLINT and PLIC output interrupts are synchronous to the CLINT/PLIC respectively, // so might need to be synchronized depending on the Tile's crossing type. // From CLINT: "msip" and "mtip" context.msipDomain { domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) := context.msipNodes(domain.element.tileId) } // From PLIC: "meip" context.meipDomain { domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) := context.meipNodes(domain.element.tileId) } // From PLIC: "seip" (only if supervisor mode is enabled) if (domain.element.tileParams.core.hasSupervisorMode) { context.seipDomain { domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) := context.seipNodes(domain.element.tileId) } } // 3. Local Interrupts ("lip") are required to already be synchronous to the Tile's clock. // (they are connected to domain.element.intInwardNode in a seperate trait) // 4. Interrupts coming out of the tile are sent to the PLIC, // so might need to be synchronized depending on the Tile's crossing type. context.tileToPlicNodes.get(domain.element.tileId).foreach { node => FlipRendering { implicit p => domain.element.intOutwardNode.foreach { out => context.toPlicDomain { node := domain.crossIntOut(crossingParams.crossingType, out) } }} } // 5. Connect NMI inputs to the tile. These inputs are synchronous to the respective core_clock. domain.element.nmiNode.foreach(_ := context.nmiNodes(domain.element.tileId)) } /* Notifications of tile status are connected to be broadcast without needing to be clock-crossed. / def connectOutputNotifications(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p domain { context.tileHaltXbarNode := domain.crossIntOut(NoCrossing, domain.element.haltNode) context.tileWFIXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.wfiNode) context.tileCeaseXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.ceaseNode) } // TODO should context be forced to have a trace sink connected here? // for now this just ensures domain.trace[Core]Node has been crossed without connecting it externally } /** Connect inputs to the tile that are assumed to be constant during normal operation, and so are not clock-crossed. / def connectInputConstants(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p val tlBusToGetPrefixFrom = context.locateTLBusWrapper(crossingParams.mmioBaseAddressPrefixWhere) domain.element.hartIdNode := context.tileHartIdNodes(domain.element.tileId) domain.element.resetVectorNode := context.tileResetVectorNodes(domain.element.tileId) tlBusToGetPrefixFrom.prefixNode.foreach { domain.element.mmioAddressPrefixNode := _ } } /* Connect power/reset/clock resources. / def connectPRC(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p val tlBusToGetClockDriverFrom = context.locateTLBusWrapper(crossingParams.master.where) (crossingParams.crossingType match { case _: SynchronousCrossing \| _: CreditedCrossing => if (crossingParams.forceSeparateClockReset) { domain.clockNode := tlBusToGetClockDriverFrom.clockNode } else { domain.clockNode := tlBusToGetClockDriverFrom.fixedClockNode } case _: RationalCrossing => domain.clockNode := tlBusToGetClockDriverFrom.clockNode case _: AsynchronousCrossing => { val tileClockGroup = ClockGroup() tileClockGroup := context.allClockGroupsNode domain.clockNode := tileClockGroup } }) domain { domain.element_reset_domain.clockNode := crossingParams.resetCrossingType.injectClockNode := domain.clockNode } } /* Function to handle all trace crossings when tile is instantiated inside domains / def connectTrace(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p val traceCrossingNode = BundleBridgeBlockDuringReset[TraceBundle]( resetCrossingType = crossingParams.resetCrossingType) context.traceNodes(domain.element.tileId) := traceCrossingNode := domain.element.traceNode val traceCoreCrossingNode = BundleBridgeBlockDuringReset[TraceCoreInterface]( resetCrossingType = crossingParams.resetCrossingType) context.traceCoreNodes(domain.element.tileId) := traceCoreCrossingNode := domain.element.traceCoreNode } } case class CloneTileAttachParams( sourceTileId: Int, cloneParams: CanAttachTile ) extends CanAttachTile { type TileType = cloneParams.TileType type TileContextType = cloneParams.TileContextType def tileParams = cloneParams.tileParams def crossingParams = cloneParams.crossingParams override def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: SortedMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = { require(instantiatedTiles.contains(sourceTileId)) val clockSinkParams = tileParams.clockSinkParams.copy(name = Some(tileParams.uniqueName)) val tile_prci_domain = CloneLazyModule( new TilePRCIDomain[TileType](clockSinkParams, crossingParams) { self => val element = self.element_reset_domain { LazyModule(tileParams.instantiate(crossingParams, PriorityMuxHartIdFromSeq(allTileParams))) } }, instantiatedTiles(sourceTileId).asInstanceOf[TilePRCIDomain[TileType]] ) tile_prci_domain } } File BusWrapper.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, NoHandle, NodeHandle, NodeBinding} // TODO This class should be moved to package subsystem to resolve // the dependency awkwardness of the following imports import freechips.rocketchip.devices.tilelink.{BuiltInDevices, CanHaveBuiltInDevices} import freechips.rocketchip.prci.{ ClockParameters, ClockDomain, ClockGroup, ClockGroupAggregator, ClockSinkNode, FixedClockBroadcast, ClockGroupEdgeParameters, ClockSinkParameters, ClockSinkDomain, ClockGroupEphemeralNode, asyncMux, ClockCrossingType, NoCrossing } import freechips.rocketchip.subsystem.{ HasTileLinkLocations, CanConnectWithinContextThatHasTileLinkLocations, CanInstantiateWithinContextThatHasTileLinkLocations } import freechips.rocketchip.util.Location /** Specifies widths of various attachement points in the SoC / trait HasTLBusParams { def beatBytes: Int def blockBytes: Int def beatBits: Int = beatBytes 8 def blockBits: Int = blockBytes * 8 def blockBeats: Int = blockBytes / beatBytes def blockOffset: Int = log2Up(blockBytes) def dtsFrequency: Option[BigInt] def fixedClockOpt = dtsFrequency.map(f => ClockParameters(freqMHz = f.toDouble / 1000000.0)) require (isPow2(beatBytes)) require (isPow2(blockBytes)) } abstract class TLBusWrapper(params: HasTLBusParams, val busName: String)(implicit p: Parameters) extends ClockDomain with HasTLBusParams with CanHaveBuiltInDevices { private val clockGroupAggregator = LazyModule(new ClockGroupAggregator(busName){ override def shouldBeInlined = true }).suggestName(busName + "_clock_groups") private val clockGroup = LazyModule(new ClockGroup(busName){ override def shouldBeInlined = true }) val clockGroupNode = clockGroupAggregator.node // other bus clock groups attach here val clockNode = clockGroup.node val fixedClockNode = FixedClockBroadcast(fixedClockOpt) // device clocks attach here private val clockSinkNode = ClockSinkNode(List(ClockSinkParameters(take = fixedClockOpt))) clockGroup.node := clockGroupAggregator.node fixedClockNode := clockGroup.node // first member of group is always domain's own clock clockSinkNode := fixedClockNode InModuleBody { // make sure the above connections work properly because mismatched-by-name signals will just be ignored. (clockGroup.node.edges.in zip clockGroupAggregator.node.edges.out).zipWithIndex map { case ((in: ClockGroupEdgeParameters , out: ClockGroupEdgeParameters), i) => require(in.members.keys == out.members.keys, s"clockGroup := clockGroupAggregator not working as you expect for index ${i}, becuase clockGroup has ${in.members.keys} and clockGroupAggregator has ${out.members.keys}") } } def clockBundle = clockSinkNode.in.head._1 def beatBytes = params.beatBytes def blockBytes = params.blockBytes def dtsFrequency = params.dtsFrequency val dtsClk = fixedClockNode.fixedClockResources(s"${busName}_clock").flatten.headOption /* If you violate this requirement, you will have a rough time. * The codebase is riddled with the assumption that this is true. / require(blockBytes >= beatBytes) def inwardNode: TLInwardNode def outwardNode: TLOutwardNode def busView: TLEdge def prefixNode: Option[BundleBridgeNode[UInt]] def unifyManagers: List[TLManagerParameters] = ManagerUnification(busView.manager.managers) def crossOutHelper = this.crossOut(outwardNode)(ValName("bus_xing")) def crossInHelper = this.crossIn(inwardNode)(ValName("bus_xing")) def generateSynchronousDomain(domainName: String): ClockSinkDomain = { val domain = LazyModule(new ClockSinkDomain(take = fixedClockOpt, name = Some(domainName))) domain.clockNode := fixedClockNode domain } def generateSynchronousDomain: ClockSinkDomain = generateSynchronousDomain("") protected val addressPrefixNexusNode = BundleBroadcast[UInt](registered = false, default = Some(() => 0.U(1.W))) def to[T](name: String)(body: => T): T = { this { LazyScope(s"coupler_to_${name}", s"TLInterconnectCoupler_${busName}_to_${name}") { body } } } def from[T](name: String)(body: => T): T = { this { LazyScope(s"coupler_from_${name}", s"TLInterconnectCoupler_${busName}_from_${name}") { body } } } def coupleTo[T](name: String)(gen: TLOutwardNode => T): T = to(name) { gen(TLNameNode("tl") :=* outwardNode) } def coupleFrom[T](name: String)(gen: TLInwardNode => T): T = from(name) { gen(inwardNode := TLNameNode("tl")) } def crossToBus(bus: TLBusWrapper, xType: ClockCrossingType, allClockGroupNode: ClockGroupEphemeralNode): NoHandle = { bus.clockGroupNode := asyncMux(xType, allClockGroupNode, this.clockGroupNode) coupleTo(s"bus_named_${bus.busName}") { bus.crossInHelper(xType) := TLWidthWidget(beatBytes) := _ } } def crossFromBus(bus: TLBusWrapper, xType: ClockCrossingType, allClockGroupNode: ClockGroupEphemeralNode): NoHandle = { bus.clockGroupNode := asyncMux(xType, allClockGroupNode, this.clockGroupNode) coupleFrom(s"bus_named_${bus.busName}") { _ :=* TLWidthWidget(bus.beatBytes) :=* bus.crossOutHelper(xType) } } } trait TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): TLBusWrapper } trait TLBusWrapperConnectionLike { val xType: ClockCrossingType def connect(context: HasTileLinkLocations, master: Location[TLBusWrapper], slave: Location[TLBusWrapper])(implicit p: Parameters): Unit } object TLBusWrapperConnection { /** Backwards compatibility factory for master driving clock and slave setting cardinality / def crossTo( xType: ClockCrossingType, driveClockFromMaster: Option[Boolean] = Some(true), nodeBinding: NodeBinding = BIND_STAR, flipRendering: Boolean = false) = { apply(xType, driveClockFromMaster, nodeBinding, flipRendering)( slaveNodeView = { case(w, p) => w.crossInHelper(xType)(p) }) } /* Backwards compatibility factory for slave driving clock and master setting cardinality / def crossFrom( xType: ClockCrossingType, driveClockFromMaster: Option[Boolean] = Some(false), nodeBinding: NodeBinding = BIND_QUERY, flipRendering: Boolean = true) = { apply(xType, driveClockFromMaster, nodeBinding, flipRendering)( masterNodeView = { case(w, p) => w.crossOutHelper(xType)(p) }) } /* Factory for making generic connections between TLBusWrappers / def apply (xType: ClockCrossingType = NoCrossing, driveClockFromMaster: Option[Boolean] = None, nodeBinding: NodeBinding = BIND_ONCE, flipRendering: Boolean = false)( slaveNodeView: (TLBusWrapper, Parameters) => TLInwardNode = { case(w, _) => w.inwardNode }, masterNodeView: (TLBusWrapper, Parameters) => TLOutwardNode = { case(w, _) => w.outwardNode }, inject: Parameters => TLNode = { _ => TLTempNode() }) = { new TLBusWrapperConnection( xType, driveClockFromMaster, nodeBinding, flipRendering)( slaveNodeView, masterNodeView, inject) } } /* TLBusWrapperConnection is a parameterization of a connection between two TLBusWrappers. * It has the following serializable parameters: * - xType: What type of TL clock crossing adapter to insert between the buses. * The appropriate half of the crossing adapter ends up inside each bus. * - driveClockFromMaster: if None, don't bind the bus's diplomatic clockGroupNode, * otherwise have either the master or the slave bus bind the other one's clockGroupNode, * assuming the inserted crossing type is not asynchronous. * - nodeBinding: fine-grained control of multi-edge cardinality resolution for diplomatic bindings within the connection. * - flipRendering: fine-grained control of the graphML rendering of the connection. * If has the following non-serializable parameters: * - slaveNodeView: programmatic control of the specific attachment point within the slave bus. * - masterNodeView: programmatic control of the specific attachment point within the master bus. * - injectNode: programmatic injection of additional nodes into the middle of the connection. * The connect method applies all these parameters to create a diplomatic connection between two Location[TLBusWrapper]s. / class TLBusWrapperConnection (val xType: ClockCrossingType, val driveClockFromMaster: Option[Boolean], val nodeBinding: NodeBinding, val flipRendering: Boolean) (slaveNodeView: (TLBusWrapper, Parameters) => TLInwardNode, masterNodeView: (TLBusWrapper, Parameters) => TLOutwardNode, inject: Parameters => TLNode) extends TLBusWrapperConnectionLike { def connect(context: HasTileLinkLocations, master: Location[TLBusWrapper], slave: Location[TLBusWrapper])(implicit p: Parameters): Unit = { val masterTLBus = context.locateTLBusWrapper(master) val slaveTLBus = context.locateTLBusWrapper(slave) def bindClocks(implicit p: Parameters) = driveClockFromMaster match { case Some(true) => slaveTLBus.clockGroupNode := asyncMux(xType, context.allClockGroupsNode, masterTLBus.clockGroupNode) case Some(false) => masterTLBus.clockGroupNode := asyncMux(xType, context.allClockGroupsNode, slaveTLBus.clockGroupNode) case None => } def bindTLNodes(implicit p: Parameters) = nodeBinding match { case BIND_ONCE => slaveNodeView(slaveTLBus, p) := TLWidthWidget(masterTLBus.beatBytes) := inject(p) := masterNodeView(masterTLBus, p) case BIND_QUERY => slaveNodeView(slaveTLBus, p) := TLWidthWidget(masterTLBus.beatBytes) :=* inject(p) :=* masterNodeView(masterTLBus, p) case BIND_STAR => slaveNodeView(slaveTLBus, p) := TLWidthWidget(masterTLBus.beatBytes) := inject(p) := masterNodeView(masterTLBus, p) case BIND_FLEX => slaveNodeView(slaveTLBus, p) :=* TLWidthWidget(masterTLBus.beatBytes) := inject(p) := masterNodeView(masterTLBus, p) } if (flipRendering) { FlipRendering { implicit p => bindClocks(implicitly[Parameters]) slaveTLBus.from(s"bus_named_${masterTLBus.busName}") { bindTLNodes(implicitly[Parameters]) } } } else { bindClocks(implicitly[Parameters]) masterTLBus.to (s"bus_named_${slaveTLBus.busName}") { bindTLNodes(implicitly[Parameters]) } } } } class TLBusWrapperTopology( val instantiations: Seq[(Location[TLBusWrapper], TLBusWrapperInstantiationLike)], val connections: Seq[(Location[TLBusWrapper], Location[TLBusWrapper], TLBusWrapperConnectionLike)] ) extends CanInstantiateWithinContextThatHasTileLinkLocations with CanConnectWithinContextThatHasTileLinkLocations { def instantiate(context: HasTileLinkLocations)(implicit p: Parameters): Unit = { instantiations.foreach { case (loc, params) => context { params.instantiate(context, loc) } } } def connect(context: HasTileLinkLocations)(implicit p: Parameters): Unit = { connections.foreach { case (master, slave, params) => context { params.connect(context, master, slave) } } } } trait HasTLXbarPhy { this: TLBusWrapper => private val xbar = LazyModule(new TLXbar(nameSuffix = Some(busName))).suggestName(busName + "_xbar") override def shouldBeInlined = xbar.node.circuitIdentity def inwardNode: TLInwardNode = xbar.node def outwardNode: TLOutwardNode = xbar.node def busView: TLEdge = xbar.node.edges.in.head } case class AddressAdjusterWrapperParams( blockBytes: Int, beatBytes: Int, replication: Option[ReplicatedRegion], forceLocal: Seq[AddressSet] = Nil, localBaseAddressDefault: Option[BigInt] = None, policy: TLFIFOFixer.Policy = TLFIFOFixer.allVolatile, ordered: Boolean = true ) extends HasTLBusParams with TLBusWrapperInstantiationLike { val dtsFrequency = None def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): AddressAdjusterWrapper = { val aaWrapper = LazyModule(new AddressAdjusterWrapper(this, context.busContextName + "_" + loc.name)) aaWrapper.suggestName(context.busContextName + "_" + loc.name + "_wrapper") context.tlBusWrapperLocationMap += (loc -> aaWrapper) aaWrapper } } class AddressAdjusterWrapper(params: AddressAdjusterWrapperParams, name: String)(implicit p: Parameters) extends TLBusWrapper(params, name) { private val address_adjuster = params.replication.map { r => LazyModule(new AddressAdjuster(r, params.forceLocal, params.localBaseAddressDefault, params.ordered)) } private val viewNode = TLIdentityNode() val inwardNode: TLInwardNode = address_adjuster.map(_.node := TLFIFOFixer(params.policy) := viewNode).getOrElse(viewNode) def outwardNode: TLOutwardNode = address_adjuster.map(_.node).getOrElse(viewNode) def busView: TLEdge = viewNode.edges.in.head val prefixNode = address_adjuster.map { a => a.prefix := addressPrefixNexusNode addressPrefixNexusNode } val builtInDevices = BuiltInDevices.none override def shouldBeInlined = !params.replication.isDefined } case class TLJBarWrapperParams( blockBytes: Int, beatBytes: Int ) extends HasTLBusParams with TLBusWrapperInstantiationLike { val dtsFrequency = None def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): TLJBarWrapper = { val jbarWrapper = LazyModule(new TLJBarWrapper(this, context.busContextName + "_" + loc.name)) jbarWrapper.suggestName(context.busContextName + "_" + loc.name + "_wrapper") context.tlBusWrapperLocationMap += (loc -> jbarWrapper) jbarWrapper } } class TLJBarWrapper(params: TLJBarWrapperParams, name: String)(implicit p: Parameters) extends TLBusWrapper(params, name) { private val jbar = LazyModule(new TLJbar) val inwardNode: TLInwardNode = jbar.node val outwardNode: TLOutwardNode = jbar.node def busView: TLEdge = jbar.node.edges.in.head val prefixNode = None val builtInDevices = BuiltInDevices.none override def shouldBeInlined = jbar.node.circuitIdentity } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Scratchpad.scala: package testchipip.soc import chisel3._ import freechips.rocketchip.subsystem._ import org.chipsalliance.cde.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.resources.{DiplomacyUtils} import freechips.rocketchip.prci.{ClockSinkDomain, ClockSinkParameters} import scala.collection.immutable.{ListMap} case class BankedScratchpadParams( base: BigInt, size: BigInt, busWhere: TLBusWrapperLocation = SBUS, banks: Int = 4, subBanks: Int = 2, name: String = "banked-scratchpad", disableMonitors: Boolean = false, buffer: BufferParams = BufferParams.none, outerBuffer: BufferParams = BufferParams.none, dtsEnabled: Boolean = false ) case object BankedScratchpadKey extends Field[Seq[BankedScratchpadParams]](Nil) class ScratchpadBank(subBanks: Int, address: AddressSet, beatBytes: Int, devOverride: MemoryDevice, buffer: BufferParams)(implicit p: Parameters) extends ClockSinkDomain(ClockSinkParameters())(p) { val mask = (subBanks - 1) p(CacheBlockBytes) val xbar = TLXbar() (0 until subBanks).map { sb => val ram = LazyModule(new TLRAM( address = AddressSet(address.base + sb * p(CacheBlockBytes), address.mask - mask), beatBytes = beatBytes, devOverride = Some(devOverride)) { override lazy val desiredName = s"TLRAM_ScratchpadBank" }) ram.node := TLFragmenter(beatBytes, p(CacheBlockBytes), nameSuffix = Some("ScratchpadBank")) := TLBuffer(buffer) := xbar } override lazy val desiredName = "ScratchpadBank" } trait CanHaveBankedScratchpad { this: BaseSubsystem => p(BankedScratchpadKey).zipWithIndex.foreach { case (params, si) => val bus = locateTLBusWrapper(params.busWhere) require (params.subBanks >= 1) val name = params.name val banks = params.banks val bankStripe = p(CacheBlockBytes)params.subBanks val mask = (params.banks-1)bankStripe val device = new MemoryDevice { override def describe(resources: ResourceBindings): Description = { Description(describeName("memory", resources), ListMap( "reg" -> resources.map.filterKeys(DiplomacyUtils.regFilter).flatMap(_._2).map(_.value).toList, "device_type" -> Seq(ResourceString("memory")), "status" -> Seq(ResourceString(if (params.dtsEnabled) "okay" else "disabled")) )) } } def genBanks()(implicit p: Parameters) = (0 until banks).map { b => val bank = LazyModule(new ScratchpadBank( params.subBanks, AddressSet(params.base + bankStripe * b, params.size - 1 - mask), bus.beatBytes, device, params.buffer)) bank.clockNode := bus.fixedClockNode bus.coupleTo(s"$name-$si-$b") { bank.xbar := bus { TLBuffer(params.outerBuffer) } := _ } } if (params.disableMonitors) DisableMonitors { implicit p => genBanks()(p) } else genBanks() } } File ClockGroupCombiner.scala: package chipyard.clocking import chisel3._ import chisel3.util._ import chisel3.experimental.Analog import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.prci._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ object ClockGroupCombiner { def apply()(implicit p: Parameters, valName: ValName): ClockGroupAdapterNode = { LazyModule(new ClockGroupCombiner()).node } } case object ClockGroupCombinerKey extends Field[Seq[(String, ClockSinkParameters => Boolean)]](Nil) // All clock groups with a name containing any substring in names will be combined into a single clock group class WithClockGroupsCombinedByName(groups: (String, Seq[String], Seq[String])) extends Config((site, here, up) => { case ClockGroupCombinerKey => groups.map { case (grouped_name, matched_names, unmatched_names) => (grouped_name, (m: ClockSinkParameters) => matched_names.exists(n => m.name.get.contains(n)) && !unmatched_names.exists(n => m.name.get.contains(n))) } }) /* This node combines sets of clock groups according to functions provided in the ClockGroupCombinerKey * The ClockGroupCombinersKey contains a list of tuples of: * - The name of the combined group * - A function on the ClockSinkParameters, returning True if the associated clock group should be grouped by this node * This node will fail if * - Multiple grouping functions match a single clock group * - A grouping function matches zero clock groups * - A grouping function matches clock groups with different requested frequncies / class ClockGroupCombiner(implicit p: Parameters, v: ValName) extends LazyModule { val combiners = p(ClockGroupCombinerKey) val sourceFn: ClockGroupSourceParameters => ClockGroupSourceParameters = { m => m } val sinkFn: ClockGroupSinkParameters => ClockGroupSinkParameters = { u => var i = 0 val (grouped, rest) = combiners.map(_._2).foldLeft((Seq[ClockSinkParameters](), u.members)) { case ((grouped, rest), c) => val (g, r) = rest.partition(c(_)) val name = combiners(i)._1 i = i + 1 require(g.size >= 1) val names = g.map(_.name.getOrElse("unamed")) val takes = g.map(_.take).flatten require(takes.distinct.size <= 1, s"Clock group '$name' has non-homogeneous requested ClockParameters ${names.zip(takes)}") require(takes.size > 0, s"Clock group '$name' has no inheritable frequencies") (grouped ++ Seq(ClockSinkParameters(take = takes.headOption, name = Some(name))), r) } ClockGroupSinkParameters( name = u.name, members = grouped ++ rest ) } val node = ClockGroupAdapterNode(sourceFn, sinkFn) lazy val module = new LazyRawModuleImp(this) { (node.out zip node.in).map { case ((o, oe), (i, ie)) => { val inMap = (i.member.data zip ie.sink.members).map { case (id, im) => im.name.get -> id }.toMap (o.member.data zip oe.sink.members).map { case (od, om) => val matches = combiners.filter(c => c._2(om)) require(matches.size <= 1) if (matches.size == 0) { od := inMap(om.name.get) } else { od := inMap(matches(0)._1) } } } } } } File SinkNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, IO} import org.chipsalliance.diplomacy.ValName /* A node which represents a node in the graph which has only inward edges, no outward edges. * * A [[SinkNode]] cannot appear cannot appear right of a `:=`, `:=`, `:=`, or `:=` * * There are no "Mixed" [[SinkNode]]s because each one only has an inward side. / class SinkNode[D, U, EO, EI, B <: Data]( imp: NodeImp[D, U, EO, EI, B] )(pi: Seq[U] )( implicit valName: ValName) extends MixedNode(imp, imp) { override def description = "sink" protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = { def resolveStarInfo: String = s"""$context \|$bindingInfo \|number of known := bindings to inward nodes: $iKnown \|number of known := bindings to outward nodes: $oKnown \|number of binding queries from inward nodes: $iStars \|number of binding queries from outward nodes: $oStars \|${pi.size} inward parameters: [${pi.map(_.toString).mkString(",")}] \|""".stripMargin require( iStars <= 1, s"""Diplomacy has detected a problem with your graph: \|The following node appears left of a := $iStars times; at most once is allowed. \|$resolveStarInfo \|""".stripMargin ) require( oStars == 0, s"""Diplomacy has detected a problem with your graph: \|The following node cannot appear right of a :=* \|$resolveStarInfo \|""".stripMargin ) require( oKnown == 0, s"""Diplomacy has detected a problem with your graph: \|The following node cannot appear right of a := \|$resolveStarInfo \|""".stripMargin ) if (iStars == 0) require( pi.size == iKnown, s"""Diplomacy has detected a problem with your graph: \|The following node has $iKnown inward bindings connected to it, but ${pi.size} sinks were specified to the node constructor. \|Either the number of inward := bindings should be exactly equal to the number of sink, or connect this node on the left-hand side of a := \|$resolveStarInfo \|""".stripMargin ) else require( pi.size >= iKnown, s"""Diplomacy has detected a problem with your graph: \|The following node has $iKnown inward bindings connected to it, but ${pi.size} sinks were specified to the node constructor. \|To resolve :=, size of inward parameters can not be less than bindings. \|$resolveStarInfo \|""".stripMargin ) (pi.size - iKnown, 0) } protected[diplomacy] def mapParamsD(n: Int, p: Seq[D]): Seq[D] = Seq() protected[diplomacy] def mapParamsU(n: Int, p: Seq[U]): Seq[U] = pi def makeIOs( )( implicit valName: ValName ): HeterogeneousBag[B] = { val bundles = this.in.map(_._1) val ios = IO(new HeterogeneousBag(bundles)) ios.suggestName(valName.value) bundles.zip(ios).foreach { case (bundle, io) => io <> bundle } ios } } File DigitalTop.scala: package chipyard import chisel3._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.system._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.devices.tilelink._ // ------------------------------------ // BOOM and/or Rocket Top Level Systems // ------------------------------------ // DOC include start: DigitalTop class DigitalTop(implicit p: Parameters) extends ChipyardSystem with testchipip.tsi.CanHavePeripheryUARTTSI // Enables optional UART-based TSI transport with testchipip.boot.CanHavePeripheryCustomBootPin // Enables optional custom boot pin with testchipip.boot.CanHavePeripheryBootAddrReg // Use programmable boot address register with testchipip.cosim.CanHaveTraceIO // Enables optionally adding trace IO with testchipip.soc.CanHaveBankedScratchpad // Enables optionally adding a banked scratchpad with testchipip.iceblk.CanHavePeripheryBlockDevice // Enables optionally adding the block device with testchipip.serdes.CanHavePeripheryTLSerial // Enables optionally adding the tl-serial interface with testchipip.serdes.old.CanHavePeripheryTLSerial // Enables optionally adding the DEPRECATED tl-serial interface with testchipip.soc.CanHavePeripheryChipIdPin // Enables optional pin to set chip id for multi-chip configs with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C with sifive.blocks.devices.timer.HasPeripheryTimer // Enables optionally adding the timer device with sifive.blocks.devices.pwm.HasPeripheryPWM // Enables optionally adding the sifive PWM with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI port with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget with chipyard.example.CanHavePeripheryStreamingFIR // Enables optionally adding the DSPTools FIR example widget with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA with chipyard.clocking.HasChipyardPRCI // Use Chipyard reset/clock distribution with chipyard.clocking.CanHaveClockTap // Enables optionally adding a clock tap output port with fftgenerator.CanHavePeripheryFFT // Enables optionally having an MMIO-based FFT block with constellation.soc.CanHaveGlobalNoC // Support instantiating a global NoC interconnect with rerocc.CanHaveReRoCCTiles // Support tiles that instantiate rerocc-attached accelerators { override lazy val module = new DigitalTopModule(this) } class DigitalTopModule(l: DigitalTop) extends ChipyardSystemModule(l) with freechips.rocketchip.util.DontTouch // DOC include end: DigitalTop File FrontBus.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.{BuiltInErrorDeviceParams, BuiltInZeroDeviceParams, BuiltInDevices, HasBuiltInDeviceParams} import freechips.rocketchip.tilelink.{HasTLBusParams, TLBusWrapper, TLBusWrapperInstantiationLike, HasTLXbarPhy} import freechips.rocketchip.util.{Location} case class FrontBusParams( beatBytes: Int, blockBytes: Int, dtsFrequency: Option[BigInt] = None, zeroDevice: Option[BuiltInZeroDeviceParams] = None, errorDevice: Option[BuiltInErrorDeviceParams] = None) extends HasTLBusParams with HasBuiltInDeviceParams with TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): FrontBus = { val fbus = LazyModule(new FrontBus(this, loc.name)) fbus.suggestName(loc.name) context.tlBusWrapperLocationMap += (loc -> fbus) fbus } } class FrontBus(params: FrontBusParams, name: String = "front_bus")(implicit p: Parameters) extends TLBusWrapper(params, name) with HasTLXbarPhy { val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode) val prefixNode = None } File PeripheryTLSerial.scala: package testchipip.serdes import chisel3._ import chisel3.util._ import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.prci._ import testchipip.util.{ClockedIO} import testchipip.soc.{OBUS} // Parameters for a read-only-memory that appears over serial-TL case class ManagerROMParams( address: BigInt = 0x20000, size: Int = 0x10000, contentFileName: Option[String] = None) // If unset, generates a JALR to DRAM_BASE // Parameters for a read/write memory that appears over serial-TL case class ManagerRAMParams( address: BigInt, size: BigInt) // Parameters for a coherent cacheable read/write memory that appears over serial-TL case class ManagerCOHParams( address: BigInt, size: BigInt) // Parameters for a set of memory regions that appear over serial-TL case class SerialTLManagerParams( memParams: Seq[ManagerRAMParams] = Nil, romParams: Seq[ManagerROMParams] = Nil, cohParams: Seq[ManagerCOHParams] = Nil, isMemoryDevice: Boolean = false, sinkIdBits: Int = 8, totalIdBits: Int = 8, cacheIdBits: Int = 2, slaveWhere: TLBusWrapperLocation = OBUS ) // Parameters for a TL client which may probe this system over serial-TL case class SerialTLClientParams( totalIdBits: Int = 8, cacheIdBits: Int = 2, masterWhere: TLBusWrapperLocation = FBUS, supportsProbe: Boolean = false ) // The SerialTL can be configured to be bidirectional if serialTLManagerParams is set case class SerialTLParams( client: Option[SerialTLClientParams] = None, manager: Option[SerialTLManagerParams] = None, phyParams: SerialPhyParams = ExternalSyncSerialPhyParams(), bundleParams: TLBundleParameters = TLSerdesser.STANDARD_TLBUNDLE_PARAMS) case object SerialTLKey extends Field[Seq[SerialTLParams]](Nil) trait CanHavePeripheryTLSerial { this: BaseSubsystem => private val portName = "serial-tl" val tlChannels = 5 val (serdessers, serial_tls, serial_tl_debugs) = p(SerialTLKey).zipWithIndex.map { case (params, sid) => val name = s"serial_tl_$sid" lazy val manager_bus = params.manager.map(m => locateTLBusWrapper(m.slaveWhere)) lazy val client_bus = params.client.map(c => locateTLBusWrapper(c.masterWhere)) val clientPortParams = params.client.map { c => TLMasterPortParameters.v1( clients = Seq.tabulate(1 << c.cacheIdBits){ i => TLMasterParameters.v1( name = s"serial_tl_${sid}_${i}", sourceId = IdRange(i << (c.totalIdBits - c.cacheIdBits), (i + 1) << (c.totalIdBits - c.cacheIdBits)), supportsProbe = if (c.supportsProbe) TransferSizes(client_bus.get.blockBytes, client_bus.get.blockBytes) else TransferSizes.none )} )} val managerPortParams = params.manager.map { m => val memParams = m.memParams val romParams = m.romParams val cohParams = m.cohParams val memDevice = if (m.isMemoryDevice) new MemoryDevice else new SimpleDevice("lbwif-readwrite", Nil) val romDevice = new SimpleDevice("lbwif-readonly", Nil) val blockBytes = manager_bus.get.blockBytes TLSlavePortParameters.v1( managers = memParams.map { memParams => TLSlaveParameters.v1( address = AddressSet.misaligned(memParams.address, memParams.size), resources = memDevice.reg, regionType = RegionType.UNCACHED, // cacheable executable = true, supportsGet = TransferSizes(1, blockBytes), supportsPutFull = TransferSizes(1, blockBytes), supportsPutPartial = TransferSizes(1, blockBytes) )} ++ romParams.map { romParams => TLSlaveParameters.v1( address = List(AddressSet(romParams.address, romParams.size-1)), resources = romDevice.reg, regionType = RegionType.UNCACHED, // cacheable executable = true, supportsGet = TransferSizes(1, blockBytes), fifoId = Some(0) )} ++ cohParams.map { cohParams => TLSlaveParameters.v1( address = AddressSet.misaligned(cohParams.address, cohParams.size), regionType = RegionType.TRACKED, // cacheable executable = true, supportsAcquireT = TransferSizes(1, blockBytes), supportsAcquireB = TransferSizes(1, blockBytes), supportsGet = TransferSizes(1, blockBytes), supportsPutFull = TransferSizes(1, blockBytes), supportsPutPartial = TransferSizes(1, blockBytes) )}, beatBytes = manager_bus.get.beatBytes, endSinkId = if (cohParams.isEmpty) 0 else (1 << m.sinkIdBits), minLatency = 1 ) } val serial_tl_domain = LazyModule(new ClockSinkDomain(name=Some(s"SerialTL$sid"))) serial_tl_domain.clockNode := manager_bus.getOrElse(client_bus.get).fixedClockNode if (manager_bus.isDefined) require(manager_bus.get.dtsFrequency.isDefined, s"Manager bus ${manager_bus.get.busName} must provide a frequency") if (client_bus.isDefined) require(client_bus.get.dtsFrequency.isDefined, s"Client bus ${client_bus.get.busName} must provide a frequency") if (manager_bus.isDefined && client_bus.isDefined) { val managerFreq = manager_bus.get.dtsFrequency.get val clientFreq = client_bus.get.dtsFrequency.get require(managerFreq == clientFreq, s"Mismatching manager freq $managerFreq != client freq $clientFreq") } val serdesser = serial_tl_domain { LazyModule(new TLSerdesser( flitWidth = params.phyParams.flitWidth, clientPortParams = clientPortParams, managerPortParams = managerPortParams, bundleParams = params.bundleParams, nameSuffix = Some(name) )) } serdesser.managerNode.foreach { managerNode => val maxClients = 1 << params.manager.get.cacheIdBits val maxIdsPerClient = 1 << (params.manager.get.totalIdBits - params.manager.get.cacheIdBits) manager_bus.get.coupleTo(s"port_named_${name}_out") { (managerNode := TLProbeBlocker(p(CacheBlockBytes)) := TLSourceAdjuster(maxClients, maxIdsPerClient) := TLSourceCombiner(maxIdsPerClient) := TLWidthWidget(manager_bus.get.beatBytes) := _) } } serdesser.clientNode.foreach { clientNode => client_bus.get.coupleFrom(s"port_named_${name}_in") { _ := TLBuffer() := clientNode } } // If we provide a clock, generate a clock domain for the outgoing clock val serial_tl_clock_freqMHz = params.phyParams match { case params: InternalSyncSerialPhyParams => Some(params.freqMHz) case params: ExternalSyncSerialPhyParams => None case params: SourceSyncSerialPhyParams => Some(params.freqMHz) } val serial_tl_clock_node = serial_tl_clock_freqMHz.map { f => serial_tl_domain { ClockSinkNode(Seq(ClockSinkParameters(take=Some(ClockParameters(f))))) } } serial_tl_clock_node.foreach(_ := ClockGroup()(p, ValName(s"${name}_clock")) := allClockGroupsNode) val inner_io = serial_tl_domain { InModuleBody { val inner_io = IO(params.phyParams.genIO).suggestName(name) inner_io match { case io: InternalSyncPhitIO => { // Outer clock comes from the clock node. Synchronize the serdesser's reset to that // clock to get the outer reset val outer_clock = serial_tl_clock_node.get.in.head._1.clock io.clock_out := outer_clock val phy = Module(new DecoupledSerialPhy(tlChannels, params.phyParams)) phy.io.outer_clock := outer_clock phy.io.outer_reset := ResetCatchAndSync(outer_clock, serdesser.module.reset.asBool) phy.io.inner_clock := serdesser.module.clock phy.io.inner_reset := serdesser.module.reset phy.io.outer_ser <> io.viewAsSupertype(new DecoupledPhitIO(io.phitWidth)) phy.io.inner_ser <> serdesser.module.io.ser } case io: ExternalSyncPhitIO => { // Outer clock comes from the IO. Synchronize the serdesser's reset to that // clock to get the outer reset val outer_clock = io.clock_in val outer_reset = ResetCatchAndSync(outer_clock, serdesser.module.reset.asBool) val phy = Module(new DecoupledSerialPhy(tlChannels, params.phyParams)) phy.io.outer_clock := outer_clock phy.io.outer_reset := ResetCatchAndSync(outer_clock, serdesser.module.reset.asBool) phy.io.inner_clock := serdesser.module.clock phy.io.inner_reset := serdesser.module.reset phy.io.outer_ser <> io.viewAsSupertype(new DecoupledPhitIO(params.phyParams.phitWidth)) phy.io.inner_ser <> serdesser.module.io.ser } case io: SourceSyncPhitIO => { // 3 clock domains - // - serdesser's "Inner clock": synchronizes signals going to the digital logic // - outgoing clock: synchronizes signals going out // - incoming clock: synchronizes signals coming in val outgoing_clock = serial_tl_clock_node.get.in.head._1.clock val outgoing_reset = ResetCatchAndSync(outgoing_clock, serdesser.module.reset.asBool) val incoming_clock = io.clock_in val incoming_reset = ResetCatchAndSync(incoming_clock, io.reset_in.asBool) io.clock_out := outgoing_clock io.reset_out := outgoing_reset.asAsyncReset val phy = Module(new CreditedSerialPhy(tlChannels, params.phyParams)) phy.io.incoming_clock := incoming_clock phy.io.incoming_reset := incoming_reset phy.io.outgoing_clock := outgoing_clock phy.io.outgoing_reset := outgoing_reset phy.io.inner_clock := serdesser.module.clock phy.io.inner_reset := serdesser.module.reset phy.io.inner_ser <> serdesser.module.io.ser phy.io.outer_ser <> io.viewAsSupertype(new ValidPhitIO(params.phyParams.phitWidth)) } } inner_io }} val outer_io = InModuleBody { val outer_io = IO(params.phyParams.genIO).suggestName(name) outer_io <> inner_io outer_io } val inner_debug_io = serial_tl_domain { InModuleBody { val inner_debug_io = IO(new SerdesDebugIO).suggestName(s"${name}_debug") inner_debug_io := serdesser.module.io.debug inner_debug_io }} val outer_debug_io = InModuleBody { val outer_debug_io = IO(new SerdesDebugIO).suggestName(s"${name}_debug") outer_debug_io := inner_debug_io outer_debug_io } (serdesser, outer_io, outer_debug_io) }.unzip3 } File CustomBootPin.scala: package testchipip.boot import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ case class CustomBootPinParams( customBootAddress: BigInt = 0x80000000L, // Default is DRAM_BASE masterWhere: TLBusWrapperLocation = CBUS // This needs to write to clint and bootaddrreg, which are on CBUS/PBUS ) case object CustomBootPinKey extends Field[Option[CustomBootPinParams]](None) trait CanHavePeripheryCustomBootPin { this: BaseSubsystem => val custom_boot_pin = p(CustomBootPinKey).map { params => require(p(BootAddrRegKey).isDefined, "CustomBootPin relies on existence of BootAddrReg") val tlbus = locateTLBusWrapper(params.masterWhere) val clientParams = TLMasterPortParameters.v1( clients = Seq(TLMasterParameters.v1( name = "custom-boot", sourceId = IdRange(0, 1), )), minLatency = 1 ) val inner_io = tlbus { val node = TLClientNode(Seq(clientParams)) tlbus.coupleFrom(s"port_named_custom_boot_pin") ({ _ := node }) InModuleBody { val custom_boot = IO(Input(Bool())).suggestName("custom_boot") val (tl, edge) = node.out(0) val inactive :: waiting_bootaddr_reg_a :: waiting_bootaddr_reg_d :: waiting_msip_a :: waiting_msip_d :: dead :: Nil = Enum(6) val state = RegInit(inactive) tl.a.valid := false.B tl.a.bits := DontCare tl.d.ready := true.B switch (state) { is (inactive) { when (custom_boot) { state := waiting_bootaddr_reg_a } } is (waiting_bootaddr_reg_a) { tl.a.valid := true.B tl.a.bits := edge.Put( toAddress = p(BootAddrRegKey).get.bootRegAddress.U, fromSource = 0.U, lgSize = 2.U, data = params.customBootAddress.U )._2 when (tl.a.fire) { state := waiting_bootaddr_reg_d } } is (waiting_bootaddr_reg_d) { when (tl.d.fire) { state := waiting_msip_a } } is (waiting_msip_a) { tl.a.valid := true.B tl.a.bits := edge.Put( toAddress = (p(CLINTKey).get.baseAddress + CLINTConsts.msipOffset(0)).U, // msip for hart0 fromSource = 0.U, lgSize = log2Ceil(CLINTConsts.msipBytes).U, data = 1.U )._2 when (tl.a.fire) { state := waiting_msip_d } } is (waiting_msip_d) { when (tl.d.fire) { state := dead } } is (dead) { when (!custom_boot) { state := inactive } } } custom_boot } } val outer_io = InModuleBody { val custom_boot = IO(Input(Bool())).suggestName("custom_boot") inner_io := custom_boot custom_boot } outer_io } } File SystemBus.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.{ BuiltInDevices, BuiltInZeroDeviceParams, BuiltInErrorDeviceParams, HasBuiltInDeviceParams } import freechips.rocketchip.tilelink.{ TLArbiter, RegionReplicator, ReplicatedRegion, HasTLBusParams, TLBusWrapper, TLBusWrapperInstantiationLike, TLXbar, TLEdge, TLInwardNode, TLOutwardNode, TLFIFOFixer, TLTempNode } import freechips.rocketchip.util.Location case class SystemBusParams( beatBytes: Int, blockBytes: Int, policy: TLArbiter.Policy = TLArbiter.roundRobin, dtsFrequency: Option[BigInt] = None, zeroDevice: Option[BuiltInZeroDeviceParams] = None, errorDevice: Option[BuiltInErrorDeviceParams] = None, replication: Option[ReplicatedRegion] = None) extends HasTLBusParams with HasBuiltInDeviceParams with TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): SystemBus = { val sbus = LazyModule(new SystemBus(this, loc.name)) sbus.suggestName(loc.name) context.tlBusWrapperLocationMap += (loc -> sbus) sbus } } class SystemBus(params: SystemBusParams, name: String = "system_bus")(implicit p: Parameters) extends TLBusWrapper(params, name) { private val replicator = params.replication.map(r => LazyModule(new RegionReplicator(r))) val prefixNode = replicator.map { r => r.prefix := addressPrefixNexusNode addressPrefixNexusNode } private val system_bus_xbar = LazyModule(new TLXbar(policy = params.policy, nameSuffix = Some(name))) val inwardNode: TLInwardNode = system_bus_xbar.node :=* TLFIFOFixer(TLFIFOFixer.allVolatile) :=* replicator.map(_.node).getOrElse(TLTempNode()) val outwardNode: TLOutwardNode = system_bus_xbar.node def busView: TLEdge = system_bus_xbar.node.edges.in.head val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode) } File InterruptBus.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.resources.{Device, DeviceInterrupts, Description, ResourceBindings} import freechips.rocketchip.interrupts.{IntInwardNode, IntOutwardNode, IntXbar, IntNameNode, IntSourceNode, IntSourcePortSimple} import freechips.rocketchip.prci.{ClockCrossingType, AsynchronousCrossing, RationalCrossing, ClockSinkDomain} import freechips.rocketchip.interrupts.IntClockDomainCrossing /** Collects interrupts from internal and external devices and feeds them into the PLIC / class InterruptBusWrapper(implicit p: Parameters) extends ClockSinkDomain { override def shouldBeInlined = true val int_bus = LazyModule(new IntXbar) // Interrupt crossbar private val int_in_xing = this.crossIn(int_bus.intnode) private val int_out_xing = this.crossOut(int_bus.intnode) def from(name: Option[String])(xing: ClockCrossingType) = int_in_xing(xing) := IntNameNode(name) def to(name: Option[String])(xing: ClockCrossingType) = IntNameNode(name) := int_out_xing(xing) def fromAsync: IntInwardNode = from(None)(AsynchronousCrossing(8,3)) def fromRational: IntInwardNode = from(None)(RationalCrossing()) def fromSync: IntInwardNode = int_bus.intnode def toPLIC: IntOutwardNode = int_bus.intnode } /* Specifies the number of external interrupts / case object NExtTopInterrupts extends Field[Int](0) /* This trait adds externally driven interrupts to the system. * However, it should not be used directly; instead one of the below * synchronization wiring child traits should be used. / abstract trait HasExtInterrupts { this: BaseSubsystem => private val device = new Device with DeviceInterrupts { def describe(resources: ResourceBindings): Description = { Description("soc/external-interrupts", describeInterrupts(resources)) } } val nExtInterrupts = p(NExtTopInterrupts) val extInterrupts = IntSourceNode(IntSourcePortSimple(num = nExtInterrupts, resources = device.int)) } /* This trait should be used if the External Interrupts have NOT * already been synchronized to the Periphery (PLIC) Clock. / trait HasAsyncExtInterrupts extends HasExtInterrupts { this: BaseSubsystem => if (nExtInterrupts > 0) { ibus { ibus.fromAsync := extInterrupts } } } /* This trait can be used if the External Interrupts have already been synchronized * to the Periphery (PLIC) Clock. / trait HasSyncExtInterrupts extends HasExtInterrupts { this: BaseSubsystem => if (nExtInterrupts > 0) { ibus { ibus.fromSync := extInterrupts } } } /* Common io name and methods for propagating or tying off the port bundle / trait HasExtInterruptsBundle { val interrupts: UInt def tieOffInterrupts(dummy: Int = 1): Unit = { interrupts := 0.U } } /* This trait performs the translation from a UInt IO into Diplomatic Interrupts. * The wiring must be done in the concrete LazyModuleImp. */ trait HasExtInterruptsModuleImp extends LazyRawModuleImp with HasExtInterruptsBundle { val outer: HasExtInterrupts val interrupts = IO(Input(UInt(outer.nExtInterrupts.W))) outer.extInterrupts.out.map(_._1).flatten.zipWithIndex.foreach { case(o, i) => o := interrupts(i) } } File BundleBridgeSink.scala: package org.chipsalliance.diplomacy.bundlebridge import chisel3.{chiselTypeOf, ActualDirection, Data, IO, Output} import chisel3.reflect.DataMirror import chisel3.reflect.DataMirror.internal.chiselTypeClone import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.nodes.SinkNode case class BundleBridgeSink[T <: Data]( genOpt: Option[() => T] = None )( implicit valName: ValName) extends SinkNode(new BundleBridgeImp[T])(Seq(BundleBridgeParams(genOpt))) { def bundle: T = in(0)._1 private def inferOutput = getElements(bundle).forall { elt => DataMirror.directionOf(elt) == ActualDirection.Unspecified } def makeIO( )( implicit valName: ValName ): T = { val io: T = IO( if (inferOutput) Output(chiselTypeOf(bundle)) else chiselTypeClone(bundle) ) io.suggestName(valName.value) io <> bundle io } def makeIO(name: String): T = makeIO()(ValName(name)) } object BundleBridgeSink { def apply[T <: Data]( )( implicit valName: ValName ): BundleBridgeSink[T] = { BundleBridgeSink(None) } }	module DigitalTop( // @[DigitalTop.scala:47:7] input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_mbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_cbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_cbus_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25] input resetctrl_hartIsInReset_0, // @[Periphery.scala:116:25] input debug_clock, // @[Periphery.scala:125:19] input debug_reset, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TCK, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TMS, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TDI, // @[Periphery.scala:125:19] output debug_systemjtag_jtag_TDO_data, // @[Periphery.scala:125:19] input debug_systemjtag_reset, // @[Periphery.scala:125:19] output debug_dmactive, // @[Periphery.scala:125:19] input debug_dmactiveAck, // @[Periphery.scala:125:19] input mem_axi4_0_aw_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_aw_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_0_aw_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_aw_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_aw_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_0_aw_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_0_aw_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_aw_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_qos, // @[SinkNode.scala:76:21] input mem_axi4_0_w_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_w_valid, // @[SinkNode.scala:76:21] output [63:0] mem_axi4_0_w_bits_data, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_w_bits_strb, // @[SinkNode.scala:76:21] output mem_axi4_0_w_bits_last, // @[SinkNode.scala:76:21] output mem_axi4_0_b_ready, // @[SinkNode.scala:76:21] input mem_axi4_0_b_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_0_b_bits_id, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_0_b_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_0_ar_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_ar_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_0_ar_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_ar_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_ar_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_0_ar_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_0_ar_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_ar_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_qos, // @[SinkNode.scala:76:21] output mem_axi4_0_r_ready, // @[SinkNode.scala:76:21] input mem_axi4_0_r_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_0_r_bits_id, // @[SinkNode.scala:76:21] input [63:0] mem_axi4_0_r_bits_data, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_0_r_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_0_r_bits_last, // @[SinkNode.scala:76:21] input custom_boot, // @[CustomBootPin.scala:73:27] output serial_tl_0_in_ready, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_in_valid, // @[PeripheryTLSerial.scala:220:24] input [31:0] serial_tl_0_in_bits_phit, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_out_ready, // @[PeripheryTLSerial.scala:220:24] output serial_tl_0_out_valid, // @[PeripheryTLSerial.scala:220:24] output [31:0] serial_tl_0_out_bits_phit, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_clock_in, // @[PeripheryTLSerial.scala:220:24] output uart_0_txd, // @[BundleBridgeSink.scala:25:19] input uart_0_rxd, // @[BundleBridgeSink.scala:25:19] output clock_tap // @[CanHaveClockTap.scala:23:23] ); wire _dtm_io_dmi_req_valid; // @[Periphery.scala:166:21] wire [6:0] _dtm_io_dmi_req_bits_addr; // @[Periphery.scala:166:21] wire [31:0] _dtm_io_dmi_req_bits_data; // @[Periphery.scala:166:21] wire [1:0] _dtm_io_dmi_req_bits_op; // @[Periphery.scala:166:21] wire _dtm_io_dmi_resp_ready; // @[Periphery.scala:166:21] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_cbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_cbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_mbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_mbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_fbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_fbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_pbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_pbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_1_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_1_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _aggregator_auto_out_4_member_cbus_cbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_4_member_cbus_cbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_3_member_mbus_mbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_3_member_mbus_mbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_2_member_fbus_fbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_2_member_fbus_fbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_1_member_pbus_pbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_1_member_pbus_pbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_0_member_sbus_sbus_1_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_0_member_sbus_sbus_1_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_0_member_sbus_sbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_0_member_sbus_sbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [7:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _intsink_auto_out_0; // @[Crossing.scala:109:29] wire _uartClockDomainWrapper_auto_uart_0_int_xing_out_sync_0; // @[UART.scala:270:44] wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready; // @[UART.scala:270:44] wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid; // @[UART.scala:270:44] wire [2:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode; // @[UART.scala:270:44] wire [1:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size; // @[UART.scala:270:44] wire [11:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source; // @[UART.scala:270:44] wire [63:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data; // @[UART.scala:270:44] wire _serial_tl_domain_auto_serdesser_client_out_a_valid; // @[PeripheryTLSerial.scala:116:38] wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_opcode; // @[PeripheryTLSerial.scala:116:38] wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_param; // @[PeripheryTLSerial.scala:116:38] wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_size; // @[PeripheryTLSerial.scala:116:38] wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_source; // @[PeripheryTLSerial.scala:116:38] wire [31:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_address; // @[PeripheryTLSerial.scala:116:38] wire [7:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_mask; // @[PeripheryTLSerial.scala:116:38] wire [63:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_data; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_auto_serdesser_client_out_d_ready; // @[PeripheryTLSerial.scala:116:38] wire _bank_auto_xbar_anon_in_a_ready; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_valid; // @[Scratchpad.scala:65:28] wire [2:0] _bank_auto_xbar_anon_in_d_bits_opcode; // @[Scratchpad.scala:65:28] wire [1:0] _bank_auto_xbar_anon_in_d_bits_param; // @[Scratchpad.scala:65:28] wire [2:0] _bank_auto_xbar_anon_in_d_bits_size; // @[Scratchpad.scala:65:28] wire [3:0] _bank_auto_xbar_anon_in_d_bits_source; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_sink; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_denied; // @[Scratchpad.scala:65:28] wire [63:0] _bank_auto_xbar_anon_in_d_bits_data; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_corrupt; // @[Scratchpad.scala:65:28] wire _bootrom_domain_auto_bootrom_in_a_ready; // @[BusWrapper.scala:89:28] wire _bootrom_domain_auto_bootrom_in_d_valid; // @[BusWrapper.scala:89:28] wire [1:0] _bootrom_domain_auto_bootrom_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [11:0] _bootrom_domain_auto_bootrom_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _bootrom_domain_auto_bootrom_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid; // @[Periphery.scala:88:26] wire [2:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode; // @[Periphery.scala:88:26] wire [3:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size; // @[Periphery.scala:88:26] wire [31:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address; // @[Periphery.scala:88:26] wire [7:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_tl_in_a_ready; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_tl_in_d_valid; // @[Periphery.scala:88:26] wire [2:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode; // @[Periphery.scala:88:26] wire [1:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_size; // @[Periphery.scala:88:26] wire [11:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_source; // @[Periphery.scala:88:26] wire [63:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_data; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_sync_0; // @[Periphery.scala:88:26] wire _tlDM_io_dmi_dmi_req_ready; // @[Periphery.scala:88:26] wire _tlDM_io_dmi_dmi_resp_valid; // @[Periphery.scala:88:26] wire [31:0] _tlDM_io_dmi_dmi_resp_bits_data; // @[Periphery.scala:88:26] wire [1:0] _tlDM_io_dmi_dmi_resp_bits_resp; // @[Periphery.scala:88:26] wire _plic_domain_auto_plic_in_a_ready; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_plic_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _plic_domain_auto_plic_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [1:0] _plic_domain_auto_plic_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [11:0] _plic_domain_auto_plic_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _plic_domain_auto_plic_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_1_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_0_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_clint_in_a_ready; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_clint_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _clint_domain_auto_clint_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [1:0] _clint_domain_auto_clint_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [11:0] _clint_domain_auto_clint_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _clint_domain_auto_clint_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_clock; // @[BusWrapper.scala:89:28] wire _clint_domain_reset; // @[BusWrapper.scala:89:28] wire _tileHartIdNexusNode_auto_out; // @[HasTiles.scala:75:39] wire _tile_prci_domain_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [7:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [3:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address; // @[BankedCoherenceParams.scala:56:31] wire [7:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_b_valid; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_b_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coherent_jbar_anon_in_b_bits_address; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_c_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [6:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_sink; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_denied; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [11:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _mbus_auto_buffer_out_a_valid; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_opcode; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_param; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_size; // @[MemoryBus.scala:30:26] wire [3:0] _mbus_auto_buffer_out_a_bits_source; // @[MemoryBus.scala:30:26] wire [27:0] _mbus_auto_buffer_out_a_bits_address; // @[MemoryBus.scala:30:26] wire [7:0] _mbus_auto_buffer_out_a_bits_mask; // @[MemoryBus.scala:30:26] wire [63:0] _mbus_auto_buffer_out_a_bits_data; // @[MemoryBus.scala:30:26] wire _mbus_auto_buffer_out_a_bits_corrupt; // @[MemoryBus.scala:30:26] wire _mbus_auto_buffer_out_d_ready; // @[MemoryBus.scala:30:26] wire _mbus_auto_fixedClockNode_anon_out_0_clock; // @[MemoryBus.scala:30:26] wire _mbus_auto_fixedClockNode_anon_out_0_reset; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_a_ready; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_valid; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_d_bits_opcode; // @[MemoryBus.scala:30:26] wire [1:0] _mbus_auto_bus_xing_in_d_bits_param; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_d_bits_size; // @[MemoryBus.scala:30:26] wire [3:0] _mbus_auto_bus_xing_in_d_bits_source; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_bits_sink; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_bits_denied; // @[MemoryBus.scala:30:26] wire [63:0] _mbus_auto_bus_xing_in_d_bits_data; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_bits_corrupt; // @[MemoryBus.scala:30:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [20:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [16:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [27:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [25:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [28:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [25:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_4_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_4_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_3_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_3_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_2_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_2_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_1_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_1_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_0_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_0_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26] wire [3:0] _cbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26] wire [6:0] _cbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode; // @[FrontBus.scala:23:26] wire [1:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied; // @[FrontBus.scala:23:26] wire [63:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode; // @[FrontBus.scala:23:26] wire [1:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied; // @[FrontBus.scala:23:26] wire [7:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_fixedClockNode_anon_out_clock; // @[FrontBus.scala:23:26] wire _fbus_auto_fixedClockNode_anon_out_reset; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_a_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_bus_xing_out_a_bits_opcode; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_bus_xing_out_a_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_bus_xing_out_a_bits_size; // @[FrontBus.scala:23:26] wire [4:0] _fbus_auto_bus_xing_out_a_bits_source; // @[FrontBus.scala:23:26] wire [31:0] _fbus_auto_bus_xing_out_a_bits_address; // @[FrontBus.scala:23:26] wire [7:0] _fbus_auto_bus_xing_out_a_bits_mask; // @[FrontBus.scala:23:26] wire [63:0] _fbus_auto_bus_xing_out_a_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_a_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_d_ready; // @[FrontBus.scala:23:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [28:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready; // @[PeripheryBus.scala:37:26] wire _pbus_auto_fixedClockNode_anon_out_clock; // @[PeripheryBus.scala:37:26] wire _pbus_auto_fixedClockNode_anon_out_reset; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26] wire [1:0] _pbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26] wire [7:0] _pbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26] wire [63:0] _pbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_b_valid; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_param; // @[SystemBus.scala:31:26] wire [31:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_address; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_c_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_size; // @[SystemBus.scala:31:26] wire [5:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_source; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size; // @[SystemBus.scala:31:26] wire [6:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source; // @[SystemBus.scala:31:26] wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address; // @[SystemBus.scala:31:26] wire [7:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_b_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size; // @[SystemBus.scala:31:26] wire [6:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source; // @[SystemBus.scala:31:26] wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_d_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size; // @[SystemBus.scala:31:26] wire [4:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size; // @[SystemBus.scala:31:26] wire [6:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source; // @[SystemBus.scala:31:26] wire [28:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address; // @[SystemBus.scala:31:26] wire [7:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_1_clock; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_1_reset; // @[SystemBus.scala:31:26] wire _sbus_auto_sbus_clock_groups_out_member_coh_0_clock; // @[SystemBus.scala:31:26] wire _sbus_auto_sbus_clock_groups_out_member_coh_0_reset; // @[SystemBus.scala:31:26] wire _ibus_int_bus_auto_anon_out_0; // @[InterruptBus.scala:19:27] reg [9:0] int_rtc_tick_c_value; // @[Counter.scala:61:40] wire int_rtc_tick = int_rtc_tick_c_value == 10'h3E7; // @[Counter.scala:61:40, :73:24] always @(posedge _clint_domain_clock) begin // @[BusWrapper.scala:89:28] if (_clint_domain_reset) // @[BusWrapper.scala:89:28] int_rtc_tick_c_value <= 10'h0; // @[Counter.scala:61:40] else // @[BusWrapper.scala:89:28] int_rtc_tick_c_value <= int_rtc_tick ? 10'h0 : int_rtc_tick_c_value + 10'h1; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_74( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_87 io_out_sink_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File loop.scala: package boom.v4.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v4.common._ import boom.v4.util.{BoomCoreStringPrefix} import scala.math.min case class BoomLoopPredictorParams( nWays: Int = 4, threshold: Int = 7 ) class LoopBranchPredictorBank(implicit p: Parameters) extends BranchPredictorBank()(p) { val tagSz = 10 override val nSets = 16 class LoopMeta extends Bundle { val s_cnt = UInt(10.W) } class LoopEntry extends Bundle { val tag = UInt(tagSz.W) val conf = UInt(3.W) val age = UInt(3.W) val p_cnt = UInt(10.W) val s_cnt = UInt(10.W) } class LoopBranchPredictorColumn extends Module { val io = IO(new Bundle { val f2_req_valid = Input(Bool()) val f2_req_idx = Input(UInt()) val f3_req_fire = Input(Bool()) val f3_pred_in = Input(Bool()) val f3_pred = Output(Bool()) val f3_meta = Output(new LoopMeta) val update_mispredict = Input(Bool()) val update_repair = Input(Bool()) val update_idx = Input(UInt()) val update_resolve_dir = Input(Bool()) val update_meta = Input(new LoopMeta) }) val doing_reset = RegInit(true.B) val reset_idx = RegInit(0.U(log2Ceil(nSets).W)) reset_idx := reset_idx + doing_reset when (reset_idx === (nSets-1).U) { doing_reset := false.B } val entries = Reg(Vec(nSets, new LoopEntry)) val f2_entry = WireInit(entries(io.f2_req_idx)) when (io.update_repair && io.update_idx === io.f2_req_idx) { f2_entry.s_cnt := io.update_meta.s_cnt } .elsewhen (io.update_mispredict && io.update_idx === io.f2_req_idx) { f2_entry.s_cnt := 0.U } val f3_entry = RegNext(f2_entry) val f3_scnt = Mux(io.update_repair && io.update_idx === RegNext(io.f2_req_idx), io.update_meta.s_cnt, f3_entry.s_cnt) val f3_tag = RegNext(io.f2_req_idx(tagSz+log2Ceil(nSets)-1,log2Ceil(nSets))) io.f3_pred := io.f3_pred_in io.f3_meta.s_cnt := f3_scnt when (f3_entry.tag === f3_tag) { when (f3_scnt === f3_entry.p_cnt && f3_entry.conf === 7.U) { io.f3_pred := !io.f3_pred_in } } val f4_fire = RegNext(io.f3_req_fire) val f4_entry = RegNext(f3_entry) val f4_tag = RegNext(f3_tag) val f4_scnt = RegNext(f3_scnt) val f4_idx = RegNext(RegNext(io.f2_req_idx)) when (f4_fire) { when (f4_entry.tag === f4_tag) { when (f4_scnt === f4_entry.p_cnt && f4_entry.conf === 7.U) { entries(f4_idx).age := 7.U entries(f4_idx).s_cnt := 0.U } .otherwise { entries(f4_idx).s_cnt := f4_scnt + 1.U entries(f4_idx).age := Mux(f4_entry.age === 7.U, 7.U, f4_entry.age + 1.U) } } } val entry = entries(io.update_idx) val tag = io.update_idx(tagSz+log2Ceil(nSets)-1,log2Ceil(nSets)) val tag_match = entry.tag === tag val ctr_match = entry.p_cnt === io.update_meta.s_cnt val wentry = WireInit(entry) when (io.update_mispredict && !doing_reset) { // Learned, tag match -> decrement confidence when (entry.conf === 7.U && tag_match) { wentry.s_cnt := 0.U wentry.conf := entry.conf - 1.U // Learned, no tag match -> do nothing? Don't evict super-confident entries? } .elsewhen (entry.conf === 7.U && !tag_match) { // Confident, tag match, ctr_match -> increment confidence, reset counter } .elsewhen (entry.conf =/= 0.U && tag_match && ctr_match) { wentry.conf := entry.conf + 1.U wentry.s_cnt := 0.U // Confident, tag match, no ctr match -> zero confidence, reset counter, set previous counter } .elsewhen (entry.conf =/= 0.U && tag_match && !ctr_match) { wentry.conf := 0.U wentry.s_cnt := 0.U wentry.p_cnt := io.update_meta.s_cnt // Confident, no tag match, age is 0 -> replace this entry with our own, set our age high to avoid ping-pong } .elsewhen (entry.conf =/= 0.U && !tag_match && entry.age === 0.U) { wentry.tag := tag wentry.conf := 1.U wentry.s_cnt := 0.U wentry.p_cnt := io.update_meta.s_cnt // Confident, no tag match, age > 0 -> decrement age } .elsewhen (entry.conf =/= 0.U && !tag_match && entry.age =/= 0.U) { wentry.age := entry.age - 1.U // Unconfident, tag match, ctr match -> increment confidence } .elsewhen (entry.conf === 0.U && tag_match && ctr_match) { wentry.conf := 1.U wentry.age := 7.U wentry.s_cnt := 0.U // Unconfident, tag match, no ctr match -> set previous counter } .elsewhen (entry.conf === 0.U && tag_match && !ctr_match) { wentry.p_cnt := io.update_meta.s_cnt wentry.age := 7.U wentry.s_cnt := 0.U // Unconfident, no tag match -> set previous counter and tag } .elsewhen (entry.conf === 0.U && !tag_match) { wentry.tag := tag wentry.conf := 1.U wentry.age := 7.U wentry.s_cnt := 0.U wentry.p_cnt := io.update_meta.s_cnt } entries(io.update_idx) := wentry } .elsewhen (io.update_repair && !doing_reset) { when (tag_match && !(f4_fire && io.update_idx === f4_idx)) { wentry.s_cnt := io.update_meta.s_cnt entries(io.update_idx) := wentry } } when (doing_reset) { entries(reset_idx) := (0.U).asTypeOf(new LoopEntry) } } val columns = Seq.fill(bankWidth) { Module(new LoopBranchPredictorColumn) } val mems = Nil // TODO fix val f3_meta = Wire(Vec(bankWidth, new LoopMeta)) override val metaSz = f3_meta.asUInt.getWidth val update_meta = s1_update.bits.meta.asTypeOf(Vec(bankWidth, new LoopMeta)) for (w <- 0 until bankWidth) { columns(w).io.f2_req_valid := s2_valid columns(w).io.f2_req_idx := s2_idx columns(w).io.f3_req_fire := (s3_valid && s3_mask(w) && io.f3_fire && RegNext(io.resp_in(0).f2(w).predicted_pc.valid && io.resp_in(0).f2(w).is_br)) columns(w).io.f3_pred_in := io.resp_in(0).f3(w).taken io.resp.f3(w).taken := columns(w).io.f3_pred columns(w).io.update_mispredict := (s1_update.valid && s1_update.bits.br_mask(w) && s1_update.bits.is_mispredict_update && s1_update.bits.cfi_mispredicted) columns(w).io.update_repair := (s1_update.valid && s1_update.bits.br_mask(w) && s1_update.bits.is_repair_update) columns(w).io.update_idx := s1_update_idx columns(w).io.update_resolve_dir := s1_update.bits.cfi_taken columns(w).io.update_meta := update_meta(w) f3_meta(w) := columns(w).io.f3_meta } io.f3_meta := f3_meta.asUInt }	module LoopBranchPredictorColumn_6( // @[loop.scala:39:9] input clock, // @[loop.scala:39:9] input reset, // @[loop.scala:39:9] input io_f2_req_valid, // @[loop.scala:43:16] input [35:0] io_f2_req_idx, // @[loop.scala:43:16] input io_f3_req_fire, // @[loop.scala:43:16] input io_f3_pred_in, // @[loop.scala:43:16] output io_f3_pred, // @[loop.scala:43:16] output [9:0] io_f3_meta_s_cnt, // @[loop.scala:43:16] input io_update_mispredict, // @[loop.scala:43:16] input io_update_repair, // @[loop.scala:43:16] input [35:0] io_update_idx, // @[loop.scala:43:16] input io_update_resolve_dir, // @[loop.scala:43:16] input [9:0] io_update_meta_s_cnt // @[loop.scala:43:16] ); wire io_f2_req_valid_0 = io_f2_req_valid; // @[loop.scala:39:9] wire [35:0] io_f2_req_idx_0 = io_f2_req_idx; // @[loop.scala:39:9] wire io_f3_req_fire_0 = io_f3_req_fire; // @[loop.scala:39:9] wire io_f3_pred_in_0 = io_f3_pred_in; // @[loop.scala:39:9] wire io_update_mispredict_0 = io_update_mispredict; // @[loop.scala:39:9] wire io_update_repair_0 = io_update_repair; // @[loop.scala:39:9] wire [35:0] io_update_idx_0 = io_update_idx; // @[loop.scala:39:9] wire io_update_resolve_dir_0 = io_update_resolve_dir; // @[loop.scala:39:9] wire [9:0] io_update_meta_s_cnt_0 = io_update_meta_s_cnt; // @[loop.scala:39:9] wire [2:0] _entries_WIRE_conf = 3'h0; // @[loop.scala:176:43] wire [2:0] _entries_WIRE_age = 3'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_tag = 10'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_p_cnt = 10'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_s_cnt = 10'h0; // @[loop.scala:176:43] wire [35:0] _f2_entry_T = io_f2_req_idx_0; // @[loop.scala:39:9] wire [9:0] f3_scnt; // @[loop.scala:73:23] wire [35:0] _entry_T = io_update_idx_0; // @[loop.scala:39:9] wire [9:0] io_f3_meta_s_cnt_0; // @[loop.scala:39:9] wire io_f3_pred_0; // @[loop.scala:39:9] reg doing_reset; // @[loop.scala:59:30] reg [3:0] reset_idx; // @[loop.scala:60:28] wire [4:0] _reset_idx_T = {1'h0, reset_idx} + {4'h0, doing_reset}; // @[loop.scala:59:30, :60:28, :61:28] wire [3:0] _reset_idx_T_1 = _reset_idx_T[3:0]; // @[loop.scala:61:28] reg [9:0] entries_0_tag; // @[loop.scala:65:22] reg [2:0] entries_0_conf; // @[loop.scala:65:22] reg [2:0] entries_0_age; // @[loop.scala:65:22] reg [9:0] entries_0_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_0_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_1_tag; // @[loop.scala:65:22] reg [2:0] entries_1_conf; // @[loop.scala:65:22] reg [2:0] entries_1_age; // @[loop.scala:65:22] reg [9:0] entries_1_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_1_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_2_tag; // @[loop.scala:65:22] reg [2:0] entries_2_conf; // @[loop.scala:65:22] reg [2:0] entries_2_age; // @[loop.scala:65:22] reg [9:0] entries_2_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_2_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_3_tag; // @[loop.scala:65:22] reg [2:0] entries_3_conf; // @[loop.scala:65:22] reg [2:0] entries_3_age; // @[loop.scala:65:22] reg [9:0] entries_3_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_3_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_4_tag; // @[loop.scala:65:22] reg [2:0] entries_4_conf; // @[loop.scala:65:22] reg [2:0] entries_4_age; // @[loop.scala:65:22] reg [9:0] entries_4_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_4_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_5_tag; // @[loop.scala:65:22] reg [2:0] entries_5_conf; // @[loop.scala:65:22] reg [2:0] entries_5_age; // @[loop.scala:65:22] reg [9:0] entries_5_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_5_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_6_tag; // @[loop.scala:65:22] reg [2:0] entries_6_conf; // @[loop.scala:65:22] reg [2:0] entries_6_age; // @[loop.scala:65:22] reg [9:0] entries_6_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_6_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_7_tag; // @[loop.scala:65:22] reg [2:0] entries_7_conf; // @[loop.scala:65:22] reg [2:0] entries_7_age; // @[loop.scala:65:22] reg [9:0] entries_7_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_7_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_8_tag; // @[loop.scala:65:22] reg [2:0] entries_8_conf; // @[loop.scala:65:22] reg [2:0] entries_8_age; // @[loop.scala:65:22] reg [9:0] entries_8_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_8_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_9_tag; // @[loop.scala:65:22] reg [2:0] entries_9_conf; // @[loop.scala:65:22] reg [2:0] entries_9_age; // @[loop.scala:65:22] reg [9:0] entries_9_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_9_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_10_tag; // @[loop.scala:65:22] reg [2:0] entries_10_conf; // @[loop.scala:65:22] reg [2:0] entries_10_age; // @[loop.scala:65:22] reg [9:0] entries_10_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_10_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_11_tag; // @[loop.scala:65:22] reg [2:0] entries_11_conf; // @[loop.scala:65:22] reg [2:0] entries_11_age; // @[loop.scala:65:22] reg [9:0] entries_11_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_11_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_12_tag; // @[loop.scala:65:22] reg [2:0] entries_12_conf; // @[loop.scala:65:22] reg [2:0] entries_12_age; // @[loop.scala:65:22] reg [9:0] entries_12_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_12_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_13_tag; // @[loop.scala:65:22] reg [2:0] entries_13_conf; // @[loop.scala:65:22] reg [2:0] entries_13_age; // @[loop.scala:65:22] reg [9:0] entries_13_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_13_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_14_tag; // @[loop.scala:65:22] reg [2:0] entries_14_conf; // @[loop.scala:65:22] reg [2:0] entries_14_age; // @[loop.scala:65:22] reg [9:0] entries_14_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_14_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_15_tag; // @[loop.scala:65:22] reg [2:0] entries_15_conf; // @[loop.scala:65:22] reg [2:0] entries_15_age; // @[loop.scala:65:22] reg [9:0] entries_15_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_15_s_cnt; // @[loop.scala:65:22] wire [3:0] _f2_entry_T_1 = _f2_entry_T[3:0]; wire [9:0] f2_entry_tag; // @[loop.scala:66:28] wire [2:0] f2_entry_conf; // @[loop.scala:66:28] wire [2:0] f2_entry_age; // @[loop.scala:66:28] wire [9:0] f2_entry_p_cnt; // @[loop.scala:66:28] wire [9:0] f2_entry_s_cnt; // @[loop.scala:66:28] wire [15:0][9:0] _GEN = {{entries_15_tag}, {entries_14_tag}, {entries_13_tag}, {entries_12_tag}, {entries_11_tag}, {entries_10_tag}, {entries_9_tag}, {entries_8_tag}, {entries_7_tag}, {entries_6_tag}, {entries_5_tag}, {entries_4_tag}, {entries_3_tag}, {entries_2_tag}, {entries_1_tag}, {entries_0_tag}}; // @[loop.scala:65:22, :66:28] assign f2_entry_tag = _GEN[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][2:0] _GEN_0 = {{entries_15_conf}, {entries_14_conf}, {entries_13_conf}, {entries_12_conf}, {entries_11_conf}, {entries_10_conf}, {entries_9_conf}, {entries_8_conf}, {entries_7_conf}, {entries_6_conf}, {entries_5_conf}, {entries_4_conf}, {entries_3_conf}, {entries_2_conf}, {entries_1_conf}, {entries_0_conf}}; // @[loop.scala:65:22, :66:28] assign f2_entry_conf = _GEN_0[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][2:0] _GEN_1 = {{entries_15_age}, {entries_14_age}, {entries_13_age}, {entries_12_age}, {entries_11_age}, {entries_10_age}, {entries_9_age}, {entries_8_age}, {entries_7_age}, {entries_6_age}, {entries_5_age}, {entries_4_age}, {entries_3_age}, {entries_2_age}, {entries_1_age}, {entries_0_age}}; // @[loop.scala:65:22, :66:28] assign f2_entry_age = _GEN_1[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][9:0] _GEN_2 = {{entries_15_p_cnt}, {entries_14_p_cnt}, {entries_13_p_cnt}, {entries_12_p_cnt}, {entries_11_p_cnt}, {entries_10_p_cnt}, {entries_9_p_cnt}, {entries_8_p_cnt}, {entries_7_p_cnt}, {entries_6_p_cnt}, {entries_5_p_cnt}, {entries_4_p_cnt}, {entries_3_p_cnt}, {entries_2_p_cnt}, {entries_1_p_cnt}, {entries_0_p_cnt}}; // @[loop.scala:65:22, :66:28] assign f2_entry_p_cnt = _GEN_2[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][9:0] _GEN_3 = {{entries_15_s_cnt}, {entries_14_s_cnt}, {entries_13_s_cnt}, {entries_12_s_cnt}, {entries_11_s_cnt}, {entries_10_s_cnt}, {entries_9_s_cnt}, {entries_8_s_cnt}, {entries_7_s_cnt}, {entries_6_s_cnt}, {entries_5_s_cnt}, {entries_4_s_cnt}, {entries_3_s_cnt}, {entries_2_s_cnt}, {entries_1_s_cnt}, {entries_0_s_cnt}}; // @[loop.scala:65:22, :66:28] wire _T_3 = io_update_idx_0 == io_f2_req_idx_0; // @[loop.scala:39:9, :67:45] assign f2_entry_s_cnt = io_update_repair_0 & _T_3 ? io_update_meta_s_cnt_0 : io_update_mispredict_0 & _T_3 ? 10'h0 : _GEN_3[_f2_entry_T_1]; // @[loop.scala:39:9, :66:28, :67:{28,45,64}, :68:22, :69:{39,75}, :70:22] reg [9:0] f3_entry_tag; // @[loop.scala:72:27] reg [2:0] f3_entry_conf; // @[loop.scala:72:27] reg [2:0] f3_entry_age; // @[loop.scala:72:27] reg [9:0] f3_entry_p_cnt; // @[loop.scala:72:27] reg [9:0] f3_entry_s_cnt; // @[loop.scala:72:27] reg [35:0] f3_scnt_REG; // @[loop.scala:73:69] wire _f3_scnt_T = io_update_idx_0 == f3_scnt_REG; // @[loop.scala:39:9, :73:{58,69}] wire _f3_scnt_T_1 = io_update_repair_0 & _f3_scnt_T; // @[loop.scala:39:9, :73:{41,58}] assign f3_scnt = _f3_scnt_T_1 ? io_update_meta_s_cnt_0 : f3_entry_s_cnt; // @[loop.scala:39:9, :72:27, :73:{23,41}] assign io_f3_meta_s_cnt_0 = f3_scnt; // @[loop.scala:39:9, :73:23] wire [9:0] _f3_tag_T = io_f2_req_idx_0[13:4]; // @[loop.scala:39:9, :76:41] reg [9:0] f3_tag; // @[loop.scala:76:27] wire _io_f3_pred_T = ~io_f3_pred_in_0; // @[loop.scala:39:9, :83:23] assign io_f3_pred_0 = f3_entry_tag == f3_tag & f3_scnt == f3_entry_p_cnt & (&f3_entry_conf) ? _io_f3_pred_T : io_f3_pred_in_0; // @[loop.scala:39:9, :72:27, :73:23, :76:27, :78:16, :81:{24,36}, :82:{21,40,57,66}, :83:{20,23}] reg f4_fire; // @[loop.scala:88:27] reg [9:0] f4_entry_tag; // @[loop.scala:89:27] reg [2:0] f4_entry_conf; // @[loop.scala:89:27] reg [2:0] f4_entry_age; // @[loop.scala:89:27] reg [9:0] f4_entry_p_cnt; // @[loop.scala:89:27] reg [9:0] f4_entry_s_cnt; // @[loop.scala:89:27] reg [9:0] f4_tag; // @[loop.scala:90:27] reg [9:0] f4_scnt; // @[loop.scala:91:27] reg [35:0] f4_idx_REG; // @[loop.scala:92:35] reg [35:0] f4_idx; // @[loop.scala:92:27] wire [10:0] _entries_s_cnt_T = {1'h0, f4_scnt} + 11'h1; // @[loop.scala:91:27, :101:44] wire [9:0] _entries_s_cnt_T_1 = _entries_s_cnt_T[9:0]; // @[loop.scala:101:44] wire _entries_age_T = &f4_entry_age; // @[loop.scala:89:27, :102:53] wire [3:0] _entries_age_T_1 = {1'h0, f4_entry_age} + 4'h1; // @[loop.scala:89:27, :102:80] wire [2:0] _entries_age_T_2 = _entries_age_T_1[2:0]; // @[loop.scala:102:80] wire [2:0] _entries_age_T_3 = _entries_age_T ? 3'h7 : _entries_age_T_2; // @[loop.scala:102:{39,53,80}] wire [3:0] _entry_T_1 = _entry_T[3:0]; wire [9:0] tag = io_update_idx_0[13:4]; // @[loop.scala:39:9, :109:28] wire tag_match = _GEN[_entry_T_1] == tag; // @[loop.scala:66:28, :109:28, :110:31] wire ctr_match = _GEN_2[_entry_T_1] == io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :111:33] wire [9:0] wentry_tag; // @[loop.scala:112:26] wire [2:0] wentry_conf; // @[loop.scala:112:26] wire [2:0] wentry_age; // @[loop.scala:112:26] wire [9:0] wentry_p_cnt; // @[loop.scala:112:26] wire [9:0] wentry_s_cnt; // @[loop.scala:112:26] wire _T_22 = io_update_mispredict_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:{32,35}] wire _T_24 = (&_GEN_0[_entry_T_1]) & tag_match; // @[loop.scala:66:28, :110:31, :117:{24,32}] wire [3:0] _GEN_4 = {1'h0, _GEN_0[_entry_T_1]}; // @[loop.scala:66:28, :110:31, :119:36] wire [3:0] _wentry_conf_T = _GEN_4 - 4'h1; // @[loop.scala:119:36] wire [2:0] _wentry_conf_T_1 = _wentry_conf_T[2:0]; // @[loop.scala:119:36] wire _T_27 = (&_GEN_0[_entry_T_1]) & ~tag_match; // @[loop.scala:66:28, :110:31, :117:24, :122:{39,42}] wire _T_30 = (\|_GEN_0[_entry_T_1]) & tag_match & ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:{31,39,52}] wire [3:0] _wentry_conf_T_2 = _GEN_4 + 4'h1; // @[loop.scala:102:80, :119:36, :126:36] wire [2:0] _wentry_conf_T_3 = _wentry_conf_T_2[2:0]; // @[loop.scala:126:36] wire _T_34 = (\|_GEN_0[_entry_T_1]) & tag_match & ~ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:31, :130:{39,52,55}] wire _T_39 = (\|_GEN_0[_entry_T_1]) & ~tag_match & _GEN_1[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :122:42, :125:31, :136:{39,53,66}] wire _T_44 = (\|_GEN_0[_entry_T_1]) & ~tag_match & (\|_GEN_1[_entry_T_1]); // @[loop.scala:66:28, :110:31, :122:42, :125:31, :143:{39,53,66}] wire [3:0] _wentry_age_T = {1'h0, _GEN_1[_entry_T_1]} - 4'h1; // @[loop.scala:66:28, :110:31, :144:33] wire [2:0] _wentry_age_T_1 = _wentry_age_T[2:0]; // @[loop.scala:144:33] wire _T_52 = _GEN_0[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :147:31] wire _T_47 = _T_52 & tag_match & ctr_match; // @[loop.scala:110:31, :111:33, :147:{31,39,52}] wire _T_51 = _T_52 & tag_match & ~ctr_match; // @[loop.scala:110:31, :111:33, :130:55, :147:31, :153:{39,52}] wire _T_54 = _T_52 & ~tag_match; // @[loop.scala:110:31, :122:42, :147:31, :159:39] wire _GEN_5 = _T_47 \| _T_51; // @[loop.scala:112:26, :147:{39,52,66}, :153:{39,52,67}, :159:54] wire _GEN_6 = _T_30 \| _T_34; // @[loop.scala:112:26, :125:{39,52,66}, :130:{39,52,67}, :136:75] assign wentry_tag = ~_T_22 \| _T_24 \| _T_27 \| _GEN_6 \| ~(_T_39 \| ~(_T_44 \| _GEN_5 \| ~_T_54)) ? _GEN[_entry_T_1] : tag; // @[loop.scala:66:28, :109:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:66, :130:67, :136:{39,53,75}, :137:22, :143:{39,53,75}, :147:66, :153:67, :159:{39,54}] assign wentry_conf = _T_22 ? (_T_24 ? _wentry_conf_T_1 : _T_27 ? _GEN_0[_entry_T_1] : _T_30 ? _wentry_conf_T_3 : _T_34 ? 3'h0 : _T_39 \| ~(_T_44 \| ~(_T_47 \| ~(_T_51 \| ~_T_54))) ? 3'h1 : _GEN_0[_entry_T_1]) : _GEN_0[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :119:{22,36}, :122:{39,54}, :125:{39,52,66}, :126:{22,36}, :130:{39,52,67}, :131:22, :136:{39,53,75}, :138:22, :143:{39,53,75}, :147:{39,52,66}, :148:22, :153:{39,52,67}, :159:{39,54}] wire _GEN_7 = _T_51 \| _T_54; // @[loop.scala:112:26, :153:{39,52,67}, :155:22, :159:{39,54}, :162:22] wire _GEN_8 = _T_34 \| _T_39; // @[loop.scala:112:26, :130:{39,52,67}, :136:{39,53,75}, :143:75] assign wentry_age = ~_T_22 \| _T_24 \| _T_27 \| _T_30 \| _GEN_8 ? _GEN_1[_entry_T_1] : _T_44 ? _wentry_age_T_1 : _T_47 \| _GEN_7 ? 3'h7 : _GEN_1[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :136:75, :143:{39,53,75}, :144:{20,33}, :147:{39,52,66}, :149:22, :153:67, :155:22, :159:54, :162:22] assign wentry_p_cnt = ~_T_22 \| _T_24 \| _T_27 \| _T_30 \| ~(_GEN_8 \| ~(_T_44 \| _T_47 \| ~_GEN_7)) ? _GEN_2[_entry_T_1] : io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :133:22, :136:75, :140:22, :143:{39,53,75}, :147:{39,52,66}, :153:67, :155:22, :159:54, :162:22] wire _T_58 = io_update_repair_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:35, :168:35] wire _T_62 = tag_match & ~(f4_fire & io_update_idx_0 == f4_idx); // @[loop.scala:39:9, :88:27, :92:27, :110:31, :169:{23,26,36,53}] assign wentry_s_cnt = _T_22 ? (_T_24 \| ~(_T_27 \| ~(_GEN_6 \| _T_39 \| ~(_T_44 \| ~(_GEN_5 \| _T_54)))) ? 10'h0 : _GEN_3[_entry_T_1]) : _T_58 & _T_62 ? io_update_meta_s_cnt_0 : _GEN_3[_entry_T_1]; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :118:22, :122:{39,54}, :125:66, :127:22, :130:67, :132:22, :136:{39,53,75}, :139:22, :143:{39,53,75}, :147:66, :150:22, :153:67, :156:22, :159:{39,54}, :163:22, :168:{35,52}, :169:{23,66}, :170:22] wire _T_12 = f4_scnt == f4_entry_p_cnt & (&f4_entry_conf); // @[loop.scala:89:27, :91:27, :97:{23,42,59}] wire _GEN_9 = f4_fire & f4_entry_tag == f4_tag; // @[loop.scala:65:22, :88:27, :89:27, :90:27, :95:20, :96:{26,38}, :97:68] always @(posedge clock) begin // @[loop.scala:39:9] if (reset) begin // @[loop.scala:39:9] doing_reset <= 1'h1; // @[loop.scala:59:30] reset_idx <= 4'h0; // @[loop.scala:60:28] end else begin // @[loop.scala:39:9] doing_reset <= reset_idx != 4'hF & doing_reset; // @[loop.scala:59:30, :60:28, :62:{21,38,52}] reset_idx <= _reset_idx_T_1; // @[loop.scala:60:28, :61:28] end if (doing_reset & reset_idx == 4'h0) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_0_tag <= 10'h0; // @[loop.scala:65:22] entries_0_conf <= 3'h0; // @[loop.scala:65:22] entries_0_age <= 3'h0; // @[loop.scala:65:22] entries_0_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h0 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h0) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_0_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_0_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_0_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_0_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_0_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :98:33] entries_0_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :99:33] entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :102:33] entries_0_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :101:33] entries_0_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h1) begin // @[loop.scala:59:30, :60:28, :102:80, :114:49, :175:24, :176:26] entries_1_tag <= 10'h0; // @[loop.scala:65:22] entries_1_conf <= 3'h0; // @[loop.scala:65:22] entries_1_age <= 3'h0; // @[loop.scala:65:22] entries_1_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h1 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h1) begin // @[loop.scala:39:9, :65:22, :95:20, :102:80, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_1_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_1_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_1_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_1_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_1_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :98:33, :102:80] entries_1_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :99:33, :102:80] entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :102:{33,80}] entries_1_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :101:33, :102:80] entries_1_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h2) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_2_tag <= 10'h0; // @[loop.scala:65:22] entries_2_conf <= 3'h0; // @[loop.scala:65:22] entries_2_age <= 3'h0; // @[loop.scala:65:22] entries_2_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h2 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h2) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_2_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_2_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_2_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_2_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_2_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :98:33] entries_2_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :99:33] entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :102:33] entries_2_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :101:33] entries_2_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h3) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_3_tag <= 10'h0; // @[loop.scala:65:22] entries_3_conf <= 3'h0; // @[loop.scala:65:22] entries_3_age <= 3'h0; // @[loop.scala:65:22] entries_3_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h3 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h3) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_3_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_3_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_3_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_3_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_3_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :98:33] entries_3_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :99:33] entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :102:33] entries_3_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :101:33] entries_3_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h4) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_4_tag <= 10'h0; // @[loop.scala:65:22] entries_4_conf <= 3'h0; // @[loop.scala:65:22] entries_4_age <= 3'h0; // @[loop.scala:65:22] entries_4_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h4 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h4) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_4_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_4_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_4_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_4_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_4_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :98:33] entries_4_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :99:33] entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :102:33] entries_4_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :101:33] entries_4_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h5) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_5_tag <= 10'h0; // @[loop.scala:65:22] entries_5_conf <= 3'h0; // @[loop.scala:65:22] entries_5_age <= 3'h0; // @[loop.scala:65:22] entries_5_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h5 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h5) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_5_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_5_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_5_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_5_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_5_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :98:33] entries_5_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :99:33] entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :102:33] entries_5_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :101:33] entries_5_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h6) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_6_tag <= 10'h0; // @[loop.scala:65:22] entries_6_conf <= 3'h0; // @[loop.scala:65:22] entries_6_age <= 3'h0; // @[loop.scala:65:22] entries_6_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h6 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h6) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_6_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_6_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_6_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_6_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_6_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :98:33] entries_6_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :99:33] entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :102:33] entries_6_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :101:33] entries_6_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h7) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_7_tag <= 10'h0; // @[loop.scala:65:22] entries_7_conf <= 3'h0; // @[loop.scala:65:22] entries_7_age <= 3'h0; // @[loop.scala:65:22] entries_7_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h7 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h7) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_7_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_7_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_7_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_7_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_7_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :98:33] entries_7_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :99:33] entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :102:33] entries_7_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :101:33] entries_7_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h8) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_8_tag <= 10'h0; // @[loop.scala:65:22] entries_8_conf <= 3'h0; // @[loop.scala:65:22] entries_8_age <= 3'h0; // @[loop.scala:65:22] entries_8_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h8 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h8) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_8_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_8_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_8_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_8_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_8_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :98:33] entries_8_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :99:33] entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :102:33] entries_8_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :101:33] entries_8_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h9) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_9_tag <= 10'h0; // @[loop.scala:65:22] entries_9_conf <= 3'h0; // @[loop.scala:65:22] entries_9_age <= 3'h0; // @[loop.scala:65:22] entries_9_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h9 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h9) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_9_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_9_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_9_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_9_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_9_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :98:33] entries_9_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :99:33] entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :102:33] entries_9_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :101:33] entries_9_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hA) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_10_tag <= 10'h0; // @[loop.scala:65:22] entries_10_conf <= 3'h0; // @[loop.scala:65:22] entries_10_age <= 3'h0; // @[loop.scala:65:22] entries_10_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hA : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hA) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_10_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_10_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_10_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_10_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_10_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :98:33] entries_10_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :99:33] entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :102:33] entries_10_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :101:33] entries_10_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hB) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_11_tag <= 10'h0; // @[loop.scala:65:22] entries_11_conf <= 3'h0; // @[loop.scala:65:22] entries_11_age <= 3'h0; // @[loop.scala:65:22] entries_11_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hB : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hB) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_11_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_11_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_11_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_11_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_11_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :98:33] entries_11_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :99:33] entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :102:33] entries_11_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :101:33] entries_11_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hC) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_12_tag <= 10'h0; // @[loop.scala:65:22] entries_12_conf <= 3'h0; // @[loop.scala:65:22] entries_12_age <= 3'h0; // @[loop.scala:65:22] entries_12_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hC : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hC) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_12_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_12_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_12_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_12_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_12_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :98:33] entries_12_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :99:33] entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :102:33] entries_12_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :101:33] entries_12_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hD) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_13_tag <= 10'h0; // @[loop.scala:65:22] entries_13_conf <= 3'h0; // @[loop.scala:65:22] entries_13_age <= 3'h0; // @[loop.scala:65:22] entries_13_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hD : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hD) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_13_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_13_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_13_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_13_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_13_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :98:33] entries_13_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :99:33] entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :102:33] entries_13_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :101:33] entries_13_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hE) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_14_tag <= 10'h0; // @[loop.scala:65:22] entries_14_conf <= 3'h0; // @[loop.scala:65:22] entries_14_age <= 3'h0; // @[loop.scala:65:22] entries_14_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hE : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hE) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_14_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_14_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_14_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_14_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_14_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :98:33] entries_14_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :99:33] entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :102:33] entries_14_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :101:33] entries_14_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & (&reset_idx)) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_15_tag <= 10'h0; // @[loop.scala:65:22] entries_15_conf <= 3'h0; // @[loop.scala:65:22] entries_15_age <= 3'h0; // @[loop.scala:65:22] entries_15_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? (&(io_update_idx_0[3:0])) : _T_58 & _T_62 & (&(io_update_idx_0[3:0]))) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_15_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_15_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_15_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_15_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_15_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :98:33] entries_15_age <= 3'h7; // @[loop.scala:65:22] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :99:33] entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :102:33] entries_15_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :101:33] entries_15_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end f3_entry_tag <= f2_entry_tag; // @[loop.scala:66:28, :72:27] f3_entry_conf <= f2_entry_conf; // @[loop.scala:66:28, :72:27] f3_entry_age <= f2_entry_age; // @[loop.scala:66:28, :72:27] f3_entry_p_cnt <= f2_entry_p_cnt; // @[loop.scala:66:28, :72:27] f3_entry_s_cnt <= f2_entry_s_cnt; // @[loop.scala:66:28, :72:27] f3_scnt_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :73:69] f3_tag <= _f3_tag_T; // @[loop.scala:76:{27,41}] f4_fire <= io_f3_req_fire_0; // @[loop.scala:39:9, :88:27] f4_entry_tag <= f3_entry_tag; // @[loop.scala:72:27, :89:27] f4_entry_conf <= f3_entry_conf; // @[loop.scala:72:27, :89:27] f4_entry_age <= f3_entry_age; // @[loop.scala:72:27, :89:27] f4_entry_p_cnt <= f3_entry_p_cnt; // @[loop.scala:72:27, :89:27] f4_entry_s_cnt <= f3_entry_s_cnt; // @[loop.scala:72:27, :89:27] f4_tag <= f3_tag; // @[loop.scala:76:27, :90:27] f4_scnt <= f3_scnt; // @[loop.scala:73:23, :91:27] f4_idx_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :92:35] f4_idx <= f4_idx_REG; // @[loop.scala:92:{27,35}] always @(posedge) assign io_f3_pred = io_f3_pred_0; // @[loop.scala:39:9] assign io_f3_meta_s_cnt = io_f3_meta_s_cnt_0; // @[loop.scala:39:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_145( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_401 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module PE_330( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 \| io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_74 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File tracegen.scala: package boom.v4.lsu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy.{SimpleDevice, LazyModule, BundleBridgeSource} import freechips.rocketchip.prci.{SynchronousCrossing, ClockCrossingType} import freechips.rocketchip.groundtest._ import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket.constants.{MemoryOpConstants} import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink.{TLInwardNode, TLIdentityNode, TLOutwardNode, TLTempNode} import freechips.rocketchip.interrupts._ import freechips.rocketchip.subsystem._ import boom.v4.lsu.{BoomNonBlockingDCache, LSU, LSUCoreIO} import boom.v4.common.{BoomTileParams, MicroOp, BoomCoreParams, BoomModule} import freechips.rocketchip.prci.ClockSinkParameters class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p) with MemoryOpConstants { val io = IO(new Bundle { val lsu = Flipped(new LSUCoreIO) val tracegen = Flipped(new HellaCacheIO) }) io.lsu := DontCare io.lsu.tsc_reg := 0.U(1.W) val rob_sz = numRobEntries val rob = Reg(Vec(rob_sz, new HellaCacheReq)) val rob_respd = RegInit(VecInit((~(0.U(rob_sz.W))).asBools)) val rob_uop = Reg(Vec(rob_sz, new MicroOp)) val rob_bsy = RegInit(VecInit(0.U(rob_sz.W).asBools)) val rob_head = RegInit(0.U(log2Up(rob_sz).W)) val rob_tail = RegInit(0.U(log2Up(rob_sz).W)) val rob_wait_till_empty = RegInit(false.B) val ready_for_amo = rob_tail === rob_head && io.lsu.fencei_rdy when (ready_for_amo) { rob_wait_till_empty := false.B } def WrapInc(idx: UInt, max: Int): UInt = { Mux(idx === (max-1).U, 0.U, idx + 1.U) } io.tracegen := DontCare io.tracegen.req.ready := (!rob_bsy(rob_tail) && !rob_wait_till_empty && (ready_for_amo \|\| !(isAMO(io.tracegen.req.bits.cmd) \|\| io.tracegen.req.bits.cmd === M_XLR \|\| io.tracegen.req.bits.cmd === M_XSC)) && (WrapInc(rob_tail, rob_sz) =/= rob_head) && !(io.lsu.ldq_full(0) && isRead(io.tracegen.req.bits.cmd)) && !(io.lsu.stq_full(0) && isWrite(io.tracegen.req.bits.cmd)) ) val tracegen_uop = WireInit((0.U).asTypeOf(new MicroOp)) tracegen_uop.uses_ldq := isRead(io.tracegen.req.bits.cmd) && !isWrite(io.tracegen.req.bits.cmd) tracegen_uop.uses_stq := isWrite(io.tracegen.req.bits.cmd) tracegen_uop.rob_idx := rob_tail tracegen_uop.debug_inst := io.tracegen.req.bits.tag tracegen_uop.mem_size := io.tracegen.req.bits.size tracegen_uop.mem_cmd := io.tracegen.req.bits.cmd tracegen_uop.mem_signed := io.tracegen.req.bits.signed tracegen_uop.ldq_idx := io.lsu.dis_ldq_idx(0) tracegen_uop.stq_idx := io.lsu.dis_stq_idx(0) tracegen_uop.is_amo := isAMO(io.tracegen.req.bits.cmd) \|\| io.tracegen.req.bits.cmd === M_XSC tracegen_uop.uses_ldq := isRead(io.tracegen.req.bits.cmd) && !isWrite(io.tracegen.req.bits.cmd) tracegen_uop.uses_stq := isWrite(io.tracegen.req.bits.cmd) io.lsu.dis_uops(0).valid := io.tracegen.req.fire io.lsu.dis_uops(0).bits := tracegen_uop when (io.tracegen.req.fire) { rob_tail := WrapInc(rob_tail, rob_sz) rob_bsy(rob_tail) := true.B rob_uop(rob_tail) := tracegen_uop rob_respd(rob_tail) := false.B rob(rob_tail) := io.tracegen.req.bits when ( isAMO(io.tracegen.req.bits.cmd) \|\| io.tracegen.req.bits.cmd === M_XLR \|\| io.tracegen.req.bits.cmd === M_XSC ) { rob_wait_till_empty := true.B } } io.lsu.dgen(1).valid := false.B io.lsu.dgen(1).bits := DontCare io.lsu.commit.valids(0) := (!rob_bsy(rob_head) && rob_head =/= rob_tail && rob_respd(rob_head)) io.lsu.commit.uops(0) := rob_uop(rob_head) io.lsu.commit.fflags := DontCare when (io.lsu.commit.valids(0)) { rob_head := WrapInc(rob_head, rob_sz) } when (io.lsu.clr_bsy(0).valid) { rob_bsy(io.lsu.clr_bsy(0).bits) := false.B } when (io.lsu.clr_unsafe(0).valid && rob(io.lsu.clr_unsafe(0).bits).cmd =/= M_XLR) { rob_bsy(io.lsu.clr_unsafe(0).bits) := false.B } when (io.lsu.iresp(0).valid) { rob_bsy(io.lsu.iresp(0).bits.uop.rob_idx) := false.B } assert(!io.lsu.lxcpt.valid) io.lsu.agen(0).valid := ShiftRegister(io.tracegen.req.fire, 2) io.lsu.agen(0).bits := DontCare io.lsu.agen(0).bits.uop := ShiftRegister(tracegen_uop, 2) io.lsu.agen(0).bits.data := ShiftRegister(io.tracegen.req.bits.addr, 2) io.lsu.dgen(0).valid := ShiftRegister(io.tracegen.req.fire && tracegen_uop.uses_stq, 2) io.lsu.dgen(0).bits := DontCare io.lsu.dgen(0).bits.uop := ShiftRegister(tracegen_uop, 2) io.lsu.dgen(0).bits.data := ShiftRegister(io.tracegen.req.bits.data, 2) io.tracegen.resp.valid := io.lsu.iresp(0).valid io.tracegen.resp.bits := DontCare io.tracegen.resp.bits.tag := io.lsu.iresp(0).bits.uop.debug_inst io.tracegen.resp.bits.size := io.lsu.iresp(0).bits.uop.mem_size io.tracegen.resp.bits.data := io.lsu.iresp(0).bits.data val store_resp_idx = PriorityEncoder((0 until rob_sz) map {i => !rob_respd(i) && isWrite(rob(i).cmd) }) val can_do_store_resp = ~rob_respd(store_resp_idx) && isWrite(rob(store_resp_idx).cmd) && !isRead(rob(store_resp_idx).cmd) when (can_do_store_resp && !io.lsu.iresp(0).valid) { rob_respd(store_resp_idx) := true.B io.tracegen.resp.valid := true.B io.tracegen.resp.bits.tag := rob(store_resp_idx).tag } when (io.lsu.iresp(0).valid) { rob_respd(io.lsu.iresp(0).bits.uop.rob_idx) := true.B } io.lsu.exception := false.B io.lsu.fence_dmem := false.B io.lsu.rob_pnr_idx := rob_tail io.lsu.commit_load_at_rob_head := false.B io.lsu.brupdate.b1 := (0.U).asTypeOf(new boom.v4.exu.BrUpdateMasks) io.lsu.brupdate.b2.uop := DontCare io.lsu.brupdate.b2.mispredict := false.B io.lsu.brupdate.b2.taken := false.B io.lsu.brupdate.b2.cfi_type := 0.U io.lsu.brupdate.b2.pc_sel := 0.U io.lsu.brupdate.b2.jalr_target := 0.U io.lsu.brupdate.b2.target_offset := 0.S(2.W) io.lsu.rob_head_idx := rob_head io.tracegen.ordered := ready_for_amo && io.lsu.fencei_rdy io.lsu.mcontext := 0.U(1.W) io.lsu.scontext := 0.U(1.W) } case class BoomTraceGenTileAttachParams( tileParams: BoomTraceGenParams, crossingParams: HierarchicalElementCrossingParamsLike ) extends CanAttachTile { type TileType = BoomTraceGenTile val lookup: LookupByHartIdImpl = HartsWontDeduplicate(tileParams) } case class BoomTraceGenParams( wordBits: Int, addrBits: Int, addrBag: List[BigInt], maxRequests: Int, memStart: BigInt, numGens: Int, dcache: Option[DCacheParams] = Some(DCacheParams()), tileId: Int = 0 ) extends InstantiableTileParams[BoomTraceGenTile] { def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): BoomTraceGenTile = { new BoomTraceGenTile(this, crossing, lookup) } val core = RocketCoreParams(nPMPs = 0) //TODO remove this val btb = None val icache = Some(ICacheParams()) val beuAddr = None val blockerCtrlAddr = None val name = None val traceParams = TraceGenParams(wordBits, addrBits, addrBag, maxRequests, memStart, numGens, dcache, tileId) val clockSinkParams: ClockSinkParameters = ClockSinkParameters() val baseName = "boom_l1_tracegen" val uniqueName = s"${baseName}_$tileId" } class BoomTraceGenTile private( val params: BoomTraceGenParams, crossing: ClockCrossingType, lookup: LookupByHartIdImpl, q: Parameters) extends BaseTile(params, crossing, lookup, q) with SinksExternalInterrupts with SourcesExternalNotifications { def this(params: BoomTraceGenParams, crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) = this(params, crossing.crossingType, lookup, p) val cpuDevice: SimpleDevice = new SimpleDevice("groundtest", Nil) val intOutwardNode = None val slaveNode: TLInwardNode = TLIdentityNode() val statusNode = BundleBridgeSource(() => new GroundTestStatus) val boom_params = p.alterMap(Map(TileKey -> BoomTileParams( dcache=params.dcache, core=BoomCoreParams(nPMPs=0, numLdqEntries=16, numStqEntries=16, useVM=false)))) val dcache = LazyModule(new BoomNonBlockingDCache(tileId)(boom_params)) val masterNode: TLOutwardNode = TLIdentityNode() := visibilityNode := dcache.node override lazy val module = new BoomTraceGenTileModuleImp(this) } class BoomTraceGenTileModuleImp(outer: BoomTraceGenTile) extends BaseTileModuleImp(outer){ val status = outer.statusNode.bundle val halt_and_catch_fire = None val tracegen = Module(new TraceGenerator(outer.params.traceParams)) tracegen.io.hartid := outer.hartIdSinkNode.bundle val ptw = Module(new DummyPTW(1)) val lsu = Module(new LSU()(outer.boom_params, outer.dcache.module.edge)) val boom_shim = Module(new BoomLSUShim()(outer.boom_params)) ptw.io.requestors.head <> lsu.io.ptw outer.dcache.module.io.lsu <> lsu.io.dmem boom_shim.io.tracegen <> tracegen.io.mem tracegen.io.fence_rdy := boom_shim.io.tracegen.ordered boom_shim.io.lsu <> lsu.io.core // Normally the PTW would use this port lsu.io.hellacache := DontCare lsu.io.hellacache.req.valid := false.B outer.reportCease(Some(tracegen.io.finished)) outer.reportHalt(Some(tracegen.io.timeout)) outer.reportWFI(None) status.timeout.valid := tracegen.io.timeout status.timeout.bits := 0.U status.error.valid := false.B assert(!tracegen.io.timeout, s"TraceGen tile ${outer.tileParams.tileId}: request timed out") } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) \|\| isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR \|\| cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) \|\| isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR \|\| cmd === M_PWR \|\| cmd === M_XSC \|\| isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) \|\| cmd === M_PFW \|\| cmd === M_XLR }	module BoomLSUShim( // @[tracegen.scala:19:7] input clock, // @[tracegen.scala:19:7] input reset, // @[tracegen.scala:19:7] output io_lsu_agen_0_valid, // @[tracegen.scala:21:14] output [31:0] io_lsu_agen_0_bits_uop_debug_inst, // @[tracegen.scala:21:14] output io_lsu_agen_0_bits_uop_is_amo, // @[tracegen.scala:21:14] output [4:0] io_lsu_agen_0_bits_uop_rob_idx, // @[tracegen.scala:21:14] output [3:0] io_lsu_agen_0_bits_uop_ldq_idx, // @[tracegen.scala:21:14] output [3:0] io_lsu_agen_0_bits_uop_stq_idx, // @[tracegen.scala:21:14] output [4:0] io_lsu_agen_0_bits_uop_mem_cmd, // @[tracegen.scala:21:14] output io_lsu_agen_0_bits_uop_uses_ldq, // @[tracegen.scala:21:14] output io_lsu_agen_0_bits_uop_uses_stq, // @[tracegen.scala:21:14] output [63:0] io_lsu_agen_0_bits_data, // @[tracegen.scala:21:14] output io_lsu_dgen_0_valid, // @[tracegen.scala:21:14] output [31:0] io_lsu_dgen_0_bits_uop_debug_inst, // @[tracegen.scala:21:14] output io_lsu_dgen_0_bits_uop_is_amo, // @[tracegen.scala:21:14] output [4:0] io_lsu_dgen_0_bits_uop_rob_idx, // @[tracegen.scala:21:14] output [3:0] io_lsu_dgen_0_bits_uop_ldq_idx, // @[tracegen.scala:21:14] output [3:0] io_lsu_dgen_0_bits_uop_stq_idx, // @[tracegen.scala:21:14] output [4:0] io_lsu_dgen_0_bits_uop_mem_cmd, // @[tracegen.scala:21:14] output io_lsu_dgen_0_bits_uop_uses_ldq, // @[tracegen.scala:21:14] output io_lsu_dgen_0_bits_uop_uses_stq, // @[tracegen.scala:21:14] output [63:0] io_lsu_dgen_0_bits_data, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_valid, // @[tracegen.scala:21:14] input [31:0] io_lsu_iwakeups_0_bits_uop_inst, // @[tracegen.scala:21:14] input [31:0] io_lsu_iwakeups_0_bits_uop_debug_inst, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_is_rvc, // @[tracegen.scala:21:14] input [33:0] io_lsu_iwakeups_0_bits_uop_debug_pc, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_iq_type_0, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_iq_type_1, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_iq_type_2, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_iq_type_3, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fu_code_0, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fu_code_1, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fu_code_2, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fu_code_3, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fu_code_4, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fu_code_5, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fu_code_6, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fu_code_7, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fu_code_8, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fu_code_9, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_iw_issued, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_iw_issued_partial_agen, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_iw_issued_partial_dgen, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_iw_p1_speculative_child, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_iw_p2_speculative_child, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_iw_p1_bypass_hint, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_iw_p2_bypass_hint, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_iw_p3_bypass_hint, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_dis_col_sel, // @[tracegen.scala:21:14] input [3:0] io_lsu_iwakeups_0_bits_uop_br_mask, // @[tracegen.scala:21:14] input [1:0] io_lsu_iwakeups_0_bits_uop_br_tag, // @[tracegen.scala:21:14] input [3:0] io_lsu_iwakeups_0_bits_uop_br_type, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_is_sfb, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_is_fence, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_is_fencei, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_is_sfence, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_is_amo, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_is_eret, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_is_sys_pc2epc, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_is_rocc, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_is_mov, // @[tracegen.scala:21:14] input [3:0] io_lsu_iwakeups_0_bits_uop_ftq_idx, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_edge_inst, // @[tracegen.scala:21:14] input [5:0] io_lsu_iwakeups_0_bits_uop_pc_lob, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_taken, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_imm_rename, // @[tracegen.scala:21:14] input [2:0] io_lsu_iwakeups_0_bits_uop_imm_sel, // @[tracegen.scala:21:14] input [4:0] io_lsu_iwakeups_0_bits_uop_pimm, // @[tracegen.scala:21:14] input [19:0] io_lsu_iwakeups_0_bits_uop_imm_packed, // @[tracegen.scala:21:14] input [1:0] io_lsu_iwakeups_0_bits_uop_op1_sel, // @[tracegen.scala:21:14] input [2:0] io_lsu_iwakeups_0_bits_uop_op2_sel, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_ldst, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_wen, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren1, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren2, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren3, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_swap12, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_swap23, // @[tracegen.scala:21:14] input [1:0] io_lsu_iwakeups_0_bits_uop_fp_ctrl_typeTagIn, // @[tracegen.scala:21:14] input [1:0] io_lsu_iwakeups_0_bits_uop_fp_ctrl_typeTagOut, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_fromint, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_toint, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_fastpipe, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_fma, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_div, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_sqrt, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_wflags, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_vec, // @[tracegen.scala:21:14] input [4:0] io_lsu_iwakeups_0_bits_uop_rob_idx, // @[tracegen.scala:21:14] input [3:0] io_lsu_iwakeups_0_bits_uop_ldq_idx, // @[tracegen.scala:21:14] input [3:0] io_lsu_iwakeups_0_bits_uop_stq_idx, // @[tracegen.scala:21:14] input [1:0] io_lsu_iwakeups_0_bits_uop_rxq_idx, // @[tracegen.scala:21:14] input [5:0] io_lsu_iwakeups_0_bits_uop_pdst, // @[tracegen.scala:21:14] input [5:0] io_lsu_iwakeups_0_bits_uop_prs1, // @[tracegen.scala:21:14] input [5:0] io_lsu_iwakeups_0_bits_uop_prs2, // @[tracegen.scala:21:14] input [5:0] io_lsu_iwakeups_0_bits_uop_prs3, // @[tracegen.scala:21:14] input [3:0] io_lsu_iwakeups_0_bits_uop_ppred, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_prs1_busy, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_prs2_busy, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_prs3_busy, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_ppred_busy, // @[tracegen.scala:21:14] input [5:0] io_lsu_iwakeups_0_bits_uop_stale_pdst, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_exception, // @[tracegen.scala:21:14] input [63:0] io_lsu_iwakeups_0_bits_uop_exc_cause, // @[tracegen.scala:21:14] input [4:0] io_lsu_iwakeups_0_bits_uop_mem_cmd, // @[tracegen.scala:21:14] input [1:0] io_lsu_iwakeups_0_bits_uop_mem_size, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_mem_signed, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_uses_ldq, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_uses_stq, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_is_unique, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_flush_on_commit, // @[tracegen.scala:21:14] input [2:0] io_lsu_iwakeups_0_bits_uop_csr_cmd, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_ldst_is_rs1, // @[tracegen.scala:21:14] input [5:0] io_lsu_iwakeups_0_bits_uop_ldst, // @[tracegen.scala:21:14] input [5:0] io_lsu_iwakeups_0_bits_uop_lrs1, // @[tracegen.scala:21:14] input [5:0] io_lsu_iwakeups_0_bits_uop_lrs2, // @[tracegen.scala:21:14] input [5:0] io_lsu_iwakeups_0_bits_uop_lrs3, // @[tracegen.scala:21:14] input [1:0] io_lsu_iwakeups_0_bits_uop_dst_rtype, // @[tracegen.scala:21:14] input [1:0] io_lsu_iwakeups_0_bits_uop_lrs1_rtype, // @[tracegen.scala:21:14] input [1:0] io_lsu_iwakeups_0_bits_uop_lrs2_rtype, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_frs3_en, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fcn_dw, // @[tracegen.scala:21:14] input [4:0] io_lsu_iwakeups_0_bits_uop_fcn_op, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_val, // @[tracegen.scala:21:14] input [2:0] io_lsu_iwakeups_0_bits_uop_fp_rm, // @[tracegen.scala:21:14] input [1:0] io_lsu_iwakeups_0_bits_uop_fp_typ, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_xcpt_pf_if, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_xcpt_ae_if, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_xcpt_ma_if, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_bp_debug_if, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_bp_xcpt_if, // @[tracegen.scala:21:14] input [2:0] io_lsu_iwakeups_0_bits_uop_debug_fsrc, // @[tracegen.scala:21:14] input [2:0] io_lsu_iwakeups_0_bits_uop_debug_tsrc, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_bypassable, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_speculative_mask, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_rebusy, // @[tracegen.scala:21:14] input io_lsu_iresp_0_valid, // @[tracegen.scala:21:14] input [31:0] io_lsu_iresp_0_bits_uop_inst, // @[tracegen.scala:21:14] input [31:0] io_lsu_iresp_0_bits_uop_debug_inst, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_is_rvc, // @[tracegen.scala:21:14] input [33:0] io_lsu_iresp_0_bits_uop_debug_pc, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_iq_type_0, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_iq_type_1, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_iq_type_2, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_iq_type_3, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fu_code_0, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fu_code_1, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fu_code_2, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fu_code_3, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fu_code_4, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fu_code_5, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fu_code_6, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fu_code_7, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fu_code_8, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fu_code_9, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_iw_issued, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_iw_issued_partial_agen, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_iw_issued_partial_dgen, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_iw_p1_speculative_child, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_iw_p2_speculative_child, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_iw_p1_bypass_hint, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_iw_p2_bypass_hint, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_iw_p3_bypass_hint, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_dis_col_sel, // @[tracegen.scala:21:14] input [3:0] io_lsu_iresp_0_bits_uop_br_mask, // @[tracegen.scala:21:14] input [1:0] io_lsu_iresp_0_bits_uop_br_tag, // @[tracegen.scala:21:14] input [3:0] io_lsu_iresp_0_bits_uop_br_type, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_is_sfb, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_is_fence, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_is_fencei, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_is_sfence, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_is_amo, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_is_eret, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_is_sys_pc2epc, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_is_rocc, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_is_mov, // @[tracegen.scala:21:14] input [3:0] io_lsu_iresp_0_bits_uop_ftq_idx, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_edge_inst, // @[tracegen.scala:21:14] input [5:0] io_lsu_iresp_0_bits_uop_pc_lob, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_taken, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_imm_rename, // @[tracegen.scala:21:14] input [2:0] io_lsu_iresp_0_bits_uop_imm_sel, // @[tracegen.scala:21:14] input [4:0] io_lsu_iresp_0_bits_uop_pimm, // @[tracegen.scala:21:14] input [19:0] io_lsu_iresp_0_bits_uop_imm_packed, // @[tracegen.scala:21:14] input [1:0] io_lsu_iresp_0_bits_uop_op1_sel, // @[tracegen.scala:21:14] input [2:0] io_lsu_iresp_0_bits_uop_op2_sel, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_ldst, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_wen, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_ren1, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_ren2, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_ren3, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_swap12, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_swap23, // @[tracegen.scala:21:14] input [1:0] io_lsu_iresp_0_bits_uop_fp_ctrl_typeTagIn, // @[tracegen.scala:21:14] input [1:0] io_lsu_iresp_0_bits_uop_fp_ctrl_typeTagOut, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_fromint, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_toint, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_fastpipe, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_fma, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_div, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_sqrt, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_wflags, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_vec, // @[tracegen.scala:21:14] input [4:0] io_lsu_iresp_0_bits_uop_rob_idx, // @[tracegen.scala:21:14] input [3:0] io_lsu_iresp_0_bits_uop_ldq_idx, // @[tracegen.scala:21:14] input [3:0] io_lsu_iresp_0_bits_uop_stq_idx, // @[tracegen.scala:21:14] input [1:0] io_lsu_iresp_0_bits_uop_rxq_idx, // @[tracegen.scala:21:14] input [5:0] io_lsu_iresp_0_bits_uop_pdst, // @[tracegen.scala:21:14] input [5:0] io_lsu_iresp_0_bits_uop_prs1, // @[tracegen.scala:21:14] input [5:0] io_lsu_iresp_0_bits_uop_prs2, // @[tracegen.scala:21:14] input [5:0] io_lsu_iresp_0_bits_uop_prs3, // @[tracegen.scala:21:14] input [3:0] io_lsu_iresp_0_bits_uop_ppred, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_prs1_busy, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_prs2_busy, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_prs3_busy, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_ppred_busy, // @[tracegen.scala:21:14] input [5:0] io_lsu_iresp_0_bits_uop_stale_pdst, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_exception, // @[tracegen.scala:21:14] input [63:0] io_lsu_iresp_0_bits_uop_exc_cause, // @[tracegen.scala:21:14] input [4:0] io_lsu_iresp_0_bits_uop_mem_cmd, // @[tracegen.scala:21:14] input [1:0] io_lsu_iresp_0_bits_uop_mem_size, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_mem_signed, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_uses_ldq, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_uses_stq, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_is_unique, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_flush_on_commit, // @[tracegen.scala:21:14] input [2:0] io_lsu_iresp_0_bits_uop_csr_cmd, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_ldst_is_rs1, // @[tracegen.scala:21:14] input [5:0] io_lsu_iresp_0_bits_uop_ldst, // @[tracegen.scala:21:14] input [5:0] io_lsu_iresp_0_bits_uop_lrs1, // @[tracegen.scala:21:14] input [5:0] io_lsu_iresp_0_bits_uop_lrs2, // @[tracegen.scala:21:14] input [5:0] io_lsu_iresp_0_bits_uop_lrs3, // @[tracegen.scala:21:14] input [1:0] io_lsu_iresp_0_bits_uop_dst_rtype, // @[tracegen.scala:21:14] input [1:0] io_lsu_iresp_0_bits_uop_lrs1_rtype, // @[tracegen.scala:21:14] input [1:0] io_lsu_iresp_0_bits_uop_lrs2_rtype, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_frs3_en, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fcn_dw, // @[tracegen.scala:21:14] input [4:0] io_lsu_iresp_0_bits_uop_fcn_op, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_val, // @[tracegen.scala:21:14] input [2:0] io_lsu_iresp_0_bits_uop_fp_rm, // @[tracegen.scala:21:14] input [1:0] io_lsu_iresp_0_bits_uop_fp_typ, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_xcpt_pf_if, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_xcpt_ae_if, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_xcpt_ma_if, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_bp_debug_if, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_bp_xcpt_if, // @[tracegen.scala:21:14] input [2:0] io_lsu_iresp_0_bits_uop_debug_fsrc, // @[tracegen.scala:21:14] input [2:0] io_lsu_iresp_0_bits_uop_debug_tsrc, // @[tracegen.scala:21:14] input [63:0] io_lsu_iresp_0_bits_data, // @[tracegen.scala:21:14] input io_lsu_fresp_0_valid, // @[tracegen.scala:21:14] input [31:0] io_lsu_fresp_0_bits_uop_inst, // @[tracegen.scala:21:14] input [31:0] io_lsu_fresp_0_bits_uop_debug_inst, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_is_rvc, // @[tracegen.scala:21:14] input [33:0] io_lsu_fresp_0_bits_uop_debug_pc, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_iq_type_0, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_iq_type_1, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_iq_type_2, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_iq_type_3, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fu_code_0, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fu_code_1, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fu_code_2, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fu_code_3, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fu_code_4, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fu_code_5, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fu_code_6, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fu_code_7, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fu_code_8, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fu_code_9, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_iw_issued, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_iw_issued_partial_agen, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_iw_issued_partial_dgen, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_iw_p1_speculative_child, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_iw_p2_speculative_child, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_iw_p1_bypass_hint, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_iw_p2_bypass_hint, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_iw_p3_bypass_hint, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_dis_col_sel, // @[tracegen.scala:21:14] input [3:0] io_lsu_fresp_0_bits_uop_br_mask, // @[tracegen.scala:21:14] input [1:0] io_lsu_fresp_0_bits_uop_br_tag, // @[tracegen.scala:21:14] input [3:0] io_lsu_fresp_0_bits_uop_br_type, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_is_sfb, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_is_fence, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_is_fencei, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_is_sfence, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_is_amo, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_is_eret, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_is_sys_pc2epc, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_is_rocc, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_is_mov, // @[tracegen.scala:21:14] input [3:0] io_lsu_fresp_0_bits_uop_ftq_idx, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_edge_inst, // @[tracegen.scala:21:14] input [5:0] io_lsu_fresp_0_bits_uop_pc_lob, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_taken, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_imm_rename, // @[tracegen.scala:21:14] input [2:0] io_lsu_fresp_0_bits_uop_imm_sel, // @[tracegen.scala:21:14] input [4:0] io_lsu_fresp_0_bits_uop_pimm, // @[tracegen.scala:21:14] input [19:0] io_lsu_fresp_0_bits_uop_imm_packed, // @[tracegen.scala:21:14] input [1:0] io_lsu_fresp_0_bits_uop_op1_sel, // @[tracegen.scala:21:14] input [2:0] io_lsu_fresp_0_bits_uop_op2_sel, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_ldst, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_wen, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_ren1, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_ren2, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_ren3, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_swap12, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_swap23, // @[tracegen.scala:21:14] input [1:0] io_lsu_fresp_0_bits_uop_fp_ctrl_typeTagIn, // @[tracegen.scala:21:14] input [1:0] io_lsu_fresp_0_bits_uop_fp_ctrl_typeTagOut, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_fromint, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_toint, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_fastpipe, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_fma, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_div, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_sqrt, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_wflags, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_vec, // @[tracegen.scala:21:14] input [4:0] io_lsu_fresp_0_bits_uop_rob_idx, // @[tracegen.scala:21:14] input [3:0] io_lsu_fresp_0_bits_uop_ldq_idx, // @[tracegen.scala:21:14] input [3:0] io_lsu_fresp_0_bits_uop_stq_idx, // @[tracegen.scala:21:14] input [1:0] io_lsu_fresp_0_bits_uop_rxq_idx, // @[tracegen.scala:21:14] input [5:0] io_lsu_fresp_0_bits_uop_pdst, // @[tracegen.scala:21:14] input [5:0] io_lsu_fresp_0_bits_uop_prs1, // @[tracegen.scala:21:14] input [5:0] io_lsu_fresp_0_bits_uop_prs2, // @[tracegen.scala:21:14] input [5:0] io_lsu_fresp_0_bits_uop_prs3, // @[tracegen.scala:21:14] input [3:0] io_lsu_fresp_0_bits_uop_ppred, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_prs1_busy, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_prs2_busy, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_prs3_busy, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_ppred_busy, // @[tracegen.scala:21:14] input [5:0] io_lsu_fresp_0_bits_uop_stale_pdst, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_exception, // @[tracegen.scala:21:14] input [63:0] io_lsu_fresp_0_bits_uop_exc_cause, // @[tracegen.scala:21:14] input [4:0] io_lsu_fresp_0_bits_uop_mem_cmd, // @[tracegen.scala:21:14] input [1:0] io_lsu_fresp_0_bits_uop_mem_size, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_mem_signed, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_uses_ldq, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_uses_stq, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_is_unique, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_flush_on_commit, // @[tracegen.scala:21:14] input [2:0] io_lsu_fresp_0_bits_uop_csr_cmd, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_ldst_is_rs1, // @[tracegen.scala:21:14] input [5:0] io_lsu_fresp_0_bits_uop_ldst, // @[tracegen.scala:21:14] input [5:0] io_lsu_fresp_0_bits_uop_lrs1, // @[tracegen.scala:21:14] input [5:0] io_lsu_fresp_0_bits_uop_lrs2, // @[tracegen.scala:21:14] input [5:0] io_lsu_fresp_0_bits_uop_lrs3, // @[tracegen.scala:21:14] input [1:0] io_lsu_fresp_0_bits_uop_dst_rtype, // @[tracegen.scala:21:14] input [1:0] io_lsu_fresp_0_bits_uop_lrs1_rtype, // @[tracegen.scala:21:14] input [1:0] io_lsu_fresp_0_bits_uop_lrs2_rtype, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_frs3_en, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fcn_dw, // @[tracegen.scala:21:14] input [4:0] io_lsu_fresp_0_bits_uop_fcn_op, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_val, // @[tracegen.scala:21:14] input [2:0] io_lsu_fresp_0_bits_uop_fp_rm, // @[tracegen.scala:21:14] input [1:0] io_lsu_fresp_0_bits_uop_fp_typ, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_xcpt_pf_if, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_xcpt_ae_if, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_xcpt_ma_if, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_bp_debug_if, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_bp_xcpt_if, // @[tracegen.scala:21:14] input [2:0] io_lsu_fresp_0_bits_uop_debug_fsrc, // @[tracegen.scala:21:14] input [2:0] io_lsu_fresp_0_bits_uop_debug_tsrc, // @[tracegen.scala:21:14] input [63:0] io_lsu_fresp_0_bits_data, // @[tracegen.scala:21:14] output io_lsu_dis_uops_0_valid, // @[tracegen.scala:21:14] output [31:0] io_lsu_dis_uops_0_bits_debug_inst, // @[tracegen.scala:21:14] output io_lsu_dis_uops_0_bits_is_amo, // @[tracegen.scala:21:14] output [4:0] io_lsu_dis_uops_0_bits_rob_idx, // @[tracegen.scala:21:14] output [3:0] io_lsu_dis_uops_0_bits_ldq_idx, // @[tracegen.scala:21:14] output [3:0] io_lsu_dis_uops_0_bits_stq_idx, // @[tracegen.scala:21:14] output [4:0] io_lsu_dis_uops_0_bits_mem_cmd, // @[tracegen.scala:21:14] output io_lsu_dis_uops_0_bits_uses_ldq, // @[tracegen.scala:21:14] output io_lsu_dis_uops_0_bits_uses_stq, // @[tracegen.scala:21:14] input [3:0] io_lsu_dis_ldq_idx_0, // @[tracegen.scala:21:14] input [3:0] io_lsu_dis_stq_idx_0, // @[tracegen.scala:21:14] input io_lsu_ldq_full_0, // @[tracegen.scala:21:14] input io_lsu_stq_full_0, // @[tracegen.scala:21:14] output io_lsu_commit_valids_0, // @[tracegen.scala:21:14] output [31:0] io_lsu_commit_uops_0_inst, // @[tracegen.scala:21:14] output [31:0] io_lsu_commit_uops_0_debug_inst, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_is_rvc, // @[tracegen.scala:21:14] output [33:0] io_lsu_commit_uops_0_debug_pc, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_iq_type_0, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_iq_type_1, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_iq_type_2, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_iq_type_3, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fu_code_0, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fu_code_1, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fu_code_2, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fu_code_3, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fu_code_4, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fu_code_5, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fu_code_6, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fu_code_7, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fu_code_8, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fu_code_9, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_iw_issued, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_iw_issued_partial_agen, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_iw_issued_partial_dgen, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_iw_p1_speculative_child, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_iw_p2_speculative_child, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_iw_p1_bypass_hint, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_iw_p2_bypass_hint, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_iw_p3_bypass_hint, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_dis_col_sel, // @[tracegen.scala:21:14] output [3:0] io_lsu_commit_uops_0_br_mask, // @[tracegen.scala:21:14] output [1:0] io_lsu_commit_uops_0_br_tag, // @[tracegen.scala:21:14] output [3:0] io_lsu_commit_uops_0_br_type, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_is_sfb, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_is_fence, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_is_fencei, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_is_sfence, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_is_amo, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_is_eret, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_is_sys_pc2epc, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_is_rocc, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_is_mov, // @[tracegen.scala:21:14] output [3:0] io_lsu_commit_uops_0_ftq_idx, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_edge_inst, // @[tracegen.scala:21:14] output [5:0] io_lsu_commit_uops_0_pc_lob, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_taken, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_imm_rename, // @[tracegen.scala:21:14] output [2:0] io_lsu_commit_uops_0_imm_sel, // @[tracegen.scala:21:14] output [4:0] io_lsu_commit_uops_0_pimm, // @[tracegen.scala:21:14] output [19:0] io_lsu_commit_uops_0_imm_packed, // @[tracegen.scala:21:14] output [1:0] io_lsu_commit_uops_0_op1_sel, // @[tracegen.scala:21:14] output [2:0] io_lsu_commit_uops_0_op2_sel, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_ctrl_ldst, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_ctrl_wen, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_ctrl_ren1, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_ctrl_ren2, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_ctrl_ren3, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_ctrl_swap12, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_ctrl_swap23, // @[tracegen.scala:21:14] output [1:0] io_lsu_commit_uops_0_fp_ctrl_typeTagIn, // @[tracegen.scala:21:14] output [1:0] io_lsu_commit_uops_0_fp_ctrl_typeTagOut, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_ctrl_fromint, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_ctrl_toint, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_ctrl_fastpipe, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_ctrl_fma, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_ctrl_div, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_ctrl_sqrt, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_ctrl_wflags, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_ctrl_vec, // @[tracegen.scala:21:14] output [4:0] io_lsu_commit_uops_0_rob_idx, // @[tracegen.scala:21:14] output [3:0] io_lsu_commit_uops_0_ldq_idx, // @[tracegen.scala:21:14] output [3:0] io_lsu_commit_uops_0_stq_idx, // @[tracegen.scala:21:14] output [1:0] io_lsu_commit_uops_0_rxq_idx, // @[tracegen.scala:21:14] output [5:0] io_lsu_commit_uops_0_pdst, // @[tracegen.scala:21:14] output [5:0] io_lsu_commit_uops_0_prs1, // @[tracegen.scala:21:14] output [5:0] io_lsu_commit_uops_0_prs2, // @[tracegen.scala:21:14] output [5:0] io_lsu_commit_uops_0_prs3, // @[tracegen.scala:21:14] output [3:0] io_lsu_commit_uops_0_ppred, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_prs1_busy, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_prs2_busy, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_prs3_busy, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_ppred_busy, // @[tracegen.scala:21:14] output [5:0] io_lsu_commit_uops_0_stale_pdst, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_exception, // @[tracegen.scala:21:14] output [63:0] io_lsu_commit_uops_0_exc_cause, // @[tracegen.scala:21:14] output [4:0] io_lsu_commit_uops_0_mem_cmd, // @[tracegen.scala:21:14] output [1:0] io_lsu_commit_uops_0_mem_size, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_mem_signed, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_uses_ldq, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_uses_stq, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_is_unique, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_flush_on_commit, // @[tracegen.scala:21:14] output [2:0] io_lsu_commit_uops_0_csr_cmd, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_ldst_is_rs1, // @[tracegen.scala:21:14] output [5:0] io_lsu_commit_uops_0_ldst, // @[tracegen.scala:21:14] output [5:0] io_lsu_commit_uops_0_lrs1, // @[tracegen.scala:21:14] output [5:0] io_lsu_commit_uops_0_lrs2, // @[tracegen.scala:21:14] output [5:0] io_lsu_commit_uops_0_lrs3, // @[tracegen.scala:21:14] output [1:0] io_lsu_commit_uops_0_dst_rtype, // @[tracegen.scala:21:14] output [1:0] io_lsu_commit_uops_0_lrs1_rtype, // @[tracegen.scala:21:14] output [1:0] io_lsu_commit_uops_0_lrs2_rtype, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_frs3_en, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fcn_dw, // @[tracegen.scala:21:14] output [4:0] io_lsu_commit_uops_0_fcn_op, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_val, // @[tracegen.scala:21:14] output [2:0] io_lsu_commit_uops_0_fp_rm, // @[tracegen.scala:21:14] output [1:0] io_lsu_commit_uops_0_fp_typ, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_xcpt_pf_if, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_xcpt_ae_if, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_xcpt_ma_if, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_bp_debug_if, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_bp_xcpt_if, // @[tracegen.scala:21:14] output [2:0] io_lsu_commit_uops_0_debug_fsrc, // @[tracegen.scala:21:14] output [2:0] io_lsu_commit_uops_0_debug_tsrc, // @[tracegen.scala:21:14] input io_lsu_clr_bsy_0_valid, // @[tracegen.scala:21:14] input [4:0] io_lsu_clr_bsy_0_bits, // @[tracegen.scala:21:14] input io_lsu_clr_unsafe_0_valid, // @[tracegen.scala:21:14] input [4:0] io_lsu_clr_unsafe_0_bits, // @[tracegen.scala:21:14] output [4:0] io_lsu_rob_pnr_idx, // @[tracegen.scala:21:14] output [4:0] io_lsu_rob_head_idx, // @[tracegen.scala:21:14] input io_lsu_fencei_rdy, // @[tracegen.scala:21:14] input io_lsu_lxcpt_valid, // @[tracegen.scala:21:14] input [31:0] io_lsu_lxcpt_bits_uop_inst, // @[tracegen.scala:21:14] input [31:0] io_lsu_lxcpt_bits_uop_debug_inst, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_is_rvc, // @[tracegen.scala:21:14] input [33:0] io_lsu_lxcpt_bits_uop_debug_pc, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_iq_type_0, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_iq_type_1, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_iq_type_2, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_iq_type_3, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fu_code_0, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fu_code_1, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fu_code_2, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fu_code_3, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fu_code_4, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fu_code_5, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fu_code_6, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fu_code_7, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fu_code_8, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fu_code_9, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_iw_issued, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_iw_issued_partial_agen, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_iw_issued_partial_dgen, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_iw_p1_speculative_child, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_iw_p2_speculative_child, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_iw_p1_bypass_hint, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_iw_p2_bypass_hint, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_iw_p3_bypass_hint, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_dis_col_sel, // @[tracegen.scala:21:14] input [3:0] io_lsu_lxcpt_bits_uop_br_mask, // @[tracegen.scala:21:14] input [1:0] io_lsu_lxcpt_bits_uop_br_tag, // @[tracegen.scala:21:14] input [3:0] io_lsu_lxcpt_bits_uop_br_type, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_is_sfb, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_is_fence, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_is_fencei, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_is_sfence, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_is_amo, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_is_eret, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_is_sys_pc2epc, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_is_rocc, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_is_mov, // @[tracegen.scala:21:14] input [3:0] io_lsu_lxcpt_bits_uop_ftq_idx, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_edge_inst, // @[tracegen.scala:21:14] input [5:0] io_lsu_lxcpt_bits_uop_pc_lob, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_taken, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_imm_rename, // @[tracegen.scala:21:14] input [2:0] io_lsu_lxcpt_bits_uop_imm_sel, // @[tracegen.scala:21:14] input [4:0] io_lsu_lxcpt_bits_uop_pimm, // @[tracegen.scala:21:14] input [19:0] io_lsu_lxcpt_bits_uop_imm_packed, // @[tracegen.scala:21:14] input [1:0] io_lsu_lxcpt_bits_uop_op1_sel, // @[tracegen.scala:21:14] input [2:0] io_lsu_lxcpt_bits_uop_op2_sel, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_ldst, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_wen, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_ren1, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_ren2, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_ren3, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_swap12, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_swap23, // @[tracegen.scala:21:14] input [1:0] io_lsu_lxcpt_bits_uop_fp_ctrl_typeTagIn, // @[tracegen.scala:21:14] input [1:0] io_lsu_lxcpt_bits_uop_fp_ctrl_typeTagOut, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_fromint, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_toint, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_fastpipe, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_fma, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_div, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_sqrt, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_wflags, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_vec, // @[tracegen.scala:21:14] input [4:0] io_lsu_lxcpt_bits_uop_rob_idx, // @[tracegen.scala:21:14] input [3:0] io_lsu_lxcpt_bits_uop_ldq_idx, // @[tracegen.scala:21:14] input [3:0] io_lsu_lxcpt_bits_uop_stq_idx, // @[tracegen.scala:21:14] input [1:0] io_lsu_lxcpt_bits_uop_rxq_idx, // @[tracegen.scala:21:14] input [5:0] io_lsu_lxcpt_bits_uop_pdst, // @[tracegen.scala:21:14] input [5:0] io_lsu_lxcpt_bits_uop_prs1, // @[tracegen.scala:21:14] input [5:0] io_lsu_lxcpt_bits_uop_prs2, // @[tracegen.scala:21:14] input [5:0] io_lsu_lxcpt_bits_uop_prs3, // @[tracegen.scala:21:14] input [3:0] io_lsu_lxcpt_bits_uop_ppred, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_prs1_busy, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_prs2_busy, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_prs3_busy, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_ppred_busy, // @[tracegen.scala:21:14] input [5:0] io_lsu_lxcpt_bits_uop_stale_pdst, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_exception, // @[tracegen.scala:21:14] input [63:0] io_lsu_lxcpt_bits_uop_exc_cause, // @[tracegen.scala:21:14] input [4:0] io_lsu_lxcpt_bits_uop_mem_cmd, // @[tracegen.scala:21:14] input [1:0] io_lsu_lxcpt_bits_uop_mem_size, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_mem_signed, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_uses_ldq, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_uses_stq, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_is_unique, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_flush_on_commit, // @[tracegen.scala:21:14] input [2:0] io_lsu_lxcpt_bits_uop_csr_cmd, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_ldst_is_rs1, // @[tracegen.scala:21:14] input [5:0] io_lsu_lxcpt_bits_uop_ldst, // @[tracegen.scala:21:14] input [5:0] io_lsu_lxcpt_bits_uop_lrs1, // @[tracegen.scala:21:14] input [5:0] io_lsu_lxcpt_bits_uop_lrs2, // @[tracegen.scala:21:14] input [5:0] io_lsu_lxcpt_bits_uop_lrs3, // @[tracegen.scala:21:14] input [1:0] io_lsu_lxcpt_bits_uop_dst_rtype, // @[tracegen.scala:21:14] input [1:0] io_lsu_lxcpt_bits_uop_lrs1_rtype, // @[tracegen.scala:21:14] input [1:0] io_lsu_lxcpt_bits_uop_lrs2_rtype, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_frs3_en, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fcn_dw, // @[tracegen.scala:21:14] input [4:0] io_lsu_lxcpt_bits_uop_fcn_op, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_val, // @[tracegen.scala:21:14] input [2:0] io_lsu_lxcpt_bits_uop_fp_rm, // @[tracegen.scala:21:14] input [1:0] io_lsu_lxcpt_bits_uop_fp_typ, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_xcpt_pf_if, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_xcpt_ae_if, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_xcpt_ma_if, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_bp_debug_if, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_bp_xcpt_if, // @[tracegen.scala:21:14] input [2:0] io_lsu_lxcpt_bits_uop_debug_fsrc, // @[tracegen.scala:21:14] input [2:0] io_lsu_lxcpt_bits_uop_debug_tsrc, // @[tracegen.scala:21:14] input [4:0] io_lsu_lxcpt_bits_cause, // @[tracegen.scala:21:14] input [33:0] io_lsu_lxcpt_bits_badvaddr, // @[tracegen.scala:21:14] input io_lsu_perf_acquire, // @[tracegen.scala:21:14] input io_lsu_perf_release, // @[tracegen.scala:21:14] output io_tracegen_req_ready, // @[tracegen.scala:21:14] input io_tracegen_req_valid, // @[tracegen.scala:21:14] input [33:0] io_tracegen_req_bits_addr, // @[tracegen.scala:21:14] input [5:0] io_tracegen_req_bits_tag, // @[tracegen.scala:21:14] input [4:0] io_tracegen_req_bits_cmd, // @[tracegen.scala:21:14] input [63:0] io_tracegen_req_bits_data, // @[tracegen.scala:21:14] input [63:0] io_tracegen_s1_data_data, // @[tracegen.scala:21:14] output io_tracegen_resp_valid, // @[tracegen.scala:21:14] output [5:0] io_tracegen_resp_bits_tag, // @[tracegen.scala:21:14] output [1:0] io_tracegen_resp_bits_size, // @[tracegen.scala:21:14] output [63:0] io_tracegen_resp_bits_data, // @[tracegen.scala:21:14] output io_tracegen_ordered // @[tracegen.scala:21:14] ); wire io_lsu_iwakeups_0_valid_0 = io_lsu_iwakeups_0_valid; // @[tracegen.scala:19:7] wire [31:0] io_lsu_iwakeups_0_bits_uop_inst_0 = io_lsu_iwakeups_0_bits_uop_inst; // @[tracegen.scala:19:7] wire [31:0] io_lsu_iwakeups_0_bits_uop_debug_inst_0 = io_lsu_iwakeups_0_bits_uop_debug_inst; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_is_rvc_0 = io_lsu_iwakeups_0_bits_uop_is_rvc; // @[tracegen.scala:19:7] wire [33:0] io_lsu_iwakeups_0_bits_uop_debug_pc_0 = io_lsu_iwakeups_0_bits_uop_debug_pc; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_iq_type_0_0 = io_lsu_iwakeups_0_bits_uop_iq_type_0; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_iq_type_1_0 = io_lsu_iwakeups_0_bits_uop_iq_type_1; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_iq_type_2_0 = io_lsu_iwakeups_0_bits_uop_iq_type_2; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_iq_type_3_0 = io_lsu_iwakeups_0_bits_uop_iq_type_3; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fu_code_0_0 = io_lsu_iwakeups_0_bits_uop_fu_code_0; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fu_code_1_0 = io_lsu_iwakeups_0_bits_uop_fu_code_1; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fu_code_2_0 = io_lsu_iwakeups_0_bits_uop_fu_code_2; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fu_code_3_0 = io_lsu_iwakeups_0_bits_uop_fu_code_3; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fu_code_4_0 = io_lsu_iwakeups_0_bits_uop_fu_code_4; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fu_code_5_0 = io_lsu_iwakeups_0_bits_uop_fu_code_5; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fu_code_6_0 = io_lsu_iwakeups_0_bits_uop_fu_code_6; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fu_code_7_0 = io_lsu_iwakeups_0_bits_uop_fu_code_7; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fu_code_8_0 = io_lsu_iwakeups_0_bits_uop_fu_code_8; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fu_code_9_0 = io_lsu_iwakeups_0_bits_uop_fu_code_9; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_iw_issued_0 = io_lsu_iwakeups_0_bits_uop_iw_issued; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_iw_issued_partial_agen_0 = io_lsu_iwakeups_0_bits_uop_iw_issued_partial_agen; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_iw_issued_partial_dgen_0 = io_lsu_iwakeups_0_bits_uop_iw_issued_partial_dgen; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_iw_p1_speculative_child_0 = io_lsu_iwakeups_0_bits_uop_iw_p1_speculative_child; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_iw_p2_speculative_child_0 = io_lsu_iwakeups_0_bits_uop_iw_p2_speculative_child; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_iw_p1_bypass_hint_0 = io_lsu_iwakeups_0_bits_uop_iw_p1_bypass_hint; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_iw_p2_bypass_hint_0 = io_lsu_iwakeups_0_bits_uop_iw_p2_bypass_hint; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_iw_p3_bypass_hint_0 = io_lsu_iwakeups_0_bits_uop_iw_p3_bypass_hint; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_dis_col_sel_0 = io_lsu_iwakeups_0_bits_uop_dis_col_sel; // @[tracegen.scala:19:7] wire [3:0] io_lsu_iwakeups_0_bits_uop_br_mask_0 = io_lsu_iwakeups_0_bits_uop_br_mask; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_br_tag_0 = io_lsu_iwakeups_0_bits_uop_br_tag; // @[tracegen.scala:19:7] wire [3:0] io_lsu_iwakeups_0_bits_uop_br_type_0 = io_lsu_iwakeups_0_bits_uop_br_type; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_is_sfb_0 = io_lsu_iwakeups_0_bits_uop_is_sfb; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_is_fence_0 = io_lsu_iwakeups_0_bits_uop_is_fence; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_is_fencei_0 = io_lsu_iwakeups_0_bits_uop_is_fencei; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_is_sfence_0 = io_lsu_iwakeups_0_bits_uop_is_sfence; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_is_amo_0 = io_lsu_iwakeups_0_bits_uop_is_amo; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_is_eret_0 = io_lsu_iwakeups_0_bits_uop_is_eret; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_is_sys_pc2epc_0 = io_lsu_iwakeups_0_bits_uop_is_sys_pc2epc; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_is_rocc_0 = io_lsu_iwakeups_0_bits_uop_is_rocc; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_is_mov_0 = io_lsu_iwakeups_0_bits_uop_is_mov; // @[tracegen.scala:19:7] wire [3:0] io_lsu_iwakeups_0_bits_uop_ftq_idx_0 = io_lsu_iwakeups_0_bits_uop_ftq_idx; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_edge_inst_0 = io_lsu_iwakeups_0_bits_uop_edge_inst; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iwakeups_0_bits_uop_pc_lob_0 = io_lsu_iwakeups_0_bits_uop_pc_lob; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_taken_0 = io_lsu_iwakeups_0_bits_uop_taken; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_imm_rename_0 = io_lsu_iwakeups_0_bits_uop_imm_rename; // @[tracegen.scala:19:7] wire [2:0] io_lsu_iwakeups_0_bits_uop_imm_sel_0 = io_lsu_iwakeups_0_bits_uop_imm_sel; // @[tracegen.scala:19:7] wire [4:0] io_lsu_iwakeups_0_bits_uop_pimm_0 = io_lsu_iwakeups_0_bits_uop_pimm; // @[tracegen.scala:19:7] wire [19:0] io_lsu_iwakeups_0_bits_uop_imm_packed_0 = io_lsu_iwakeups_0_bits_uop_imm_packed; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_op1_sel_0 = io_lsu_iwakeups_0_bits_uop_op1_sel; // @[tracegen.scala:19:7] wire [2:0] io_lsu_iwakeups_0_bits_uop_op2_sel_0 = io_lsu_iwakeups_0_bits_uop_op2_sel; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_ldst_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_ldst; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_wen_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_wen; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren1_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren1; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren2_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren2; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren3_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren3; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_swap12_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_swap12; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_swap23_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_swap23; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_fp_ctrl_typeTagIn_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_fp_ctrl_typeTagOut_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_fromint_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_fromint; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_toint_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_toint; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_fastpipe_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_fastpipe; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_fma_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_fma; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_div_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_div; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_sqrt_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_sqrt; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_wflags_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_wflags; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_vec_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_vec; // @[tracegen.scala:19:7] wire [4:0] io_lsu_iwakeups_0_bits_uop_rob_idx_0 = io_lsu_iwakeups_0_bits_uop_rob_idx; // @[tracegen.scala:19:7] wire [3:0] io_lsu_iwakeups_0_bits_uop_ldq_idx_0 = io_lsu_iwakeups_0_bits_uop_ldq_idx; // @[tracegen.scala:19:7] wire [3:0] io_lsu_iwakeups_0_bits_uop_stq_idx_0 = io_lsu_iwakeups_0_bits_uop_stq_idx; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_rxq_idx_0 = io_lsu_iwakeups_0_bits_uop_rxq_idx; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iwakeups_0_bits_uop_pdst_0 = io_lsu_iwakeups_0_bits_uop_pdst; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iwakeups_0_bits_uop_prs1_0 = io_lsu_iwakeups_0_bits_uop_prs1; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iwakeups_0_bits_uop_prs2_0 = io_lsu_iwakeups_0_bits_uop_prs2; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iwakeups_0_bits_uop_prs3_0 = io_lsu_iwakeups_0_bits_uop_prs3; // @[tracegen.scala:19:7] wire [3:0] io_lsu_iwakeups_0_bits_uop_ppred_0 = io_lsu_iwakeups_0_bits_uop_ppred; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_prs1_busy_0 = io_lsu_iwakeups_0_bits_uop_prs1_busy; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_prs2_busy_0 = io_lsu_iwakeups_0_bits_uop_prs2_busy; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_prs3_busy_0 = io_lsu_iwakeups_0_bits_uop_prs3_busy; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_ppred_busy_0 = io_lsu_iwakeups_0_bits_uop_ppred_busy; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iwakeups_0_bits_uop_stale_pdst_0 = io_lsu_iwakeups_0_bits_uop_stale_pdst; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_exception_0 = io_lsu_iwakeups_0_bits_uop_exception; // @[tracegen.scala:19:7] wire [63:0] io_lsu_iwakeups_0_bits_uop_exc_cause_0 = io_lsu_iwakeups_0_bits_uop_exc_cause; // @[tracegen.scala:19:7] wire [4:0] io_lsu_iwakeups_0_bits_uop_mem_cmd_0 = io_lsu_iwakeups_0_bits_uop_mem_cmd; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_mem_size_0 = io_lsu_iwakeups_0_bits_uop_mem_size; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_mem_signed_0 = io_lsu_iwakeups_0_bits_uop_mem_signed; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_uses_ldq_0 = io_lsu_iwakeups_0_bits_uop_uses_ldq; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_uses_stq_0 = io_lsu_iwakeups_0_bits_uop_uses_stq; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_is_unique_0 = io_lsu_iwakeups_0_bits_uop_is_unique; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_flush_on_commit_0 = io_lsu_iwakeups_0_bits_uop_flush_on_commit; // @[tracegen.scala:19:7] wire [2:0] io_lsu_iwakeups_0_bits_uop_csr_cmd_0 = io_lsu_iwakeups_0_bits_uop_csr_cmd; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_ldst_is_rs1_0 = io_lsu_iwakeups_0_bits_uop_ldst_is_rs1; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iwakeups_0_bits_uop_ldst_0 = io_lsu_iwakeups_0_bits_uop_ldst; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iwakeups_0_bits_uop_lrs1_0 = io_lsu_iwakeups_0_bits_uop_lrs1; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iwakeups_0_bits_uop_lrs2_0 = io_lsu_iwakeups_0_bits_uop_lrs2; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iwakeups_0_bits_uop_lrs3_0 = io_lsu_iwakeups_0_bits_uop_lrs3; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_dst_rtype_0 = io_lsu_iwakeups_0_bits_uop_dst_rtype; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_lrs1_rtype_0 = io_lsu_iwakeups_0_bits_uop_lrs1_rtype; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_lrs2_rtype_0 = io_lsu_iwakeups_0_bits_uop_lrs2_rtype; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_frs3_en_0 = io_lsu_iwakeups_0_bits_uop_frs3_en; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fcn_dw_0 = io_lsu_iwakeups_0_bits_uop_fcn_dw; // @[tracegen.scala:19:7] wire [4:0] io_lsu_iwakeups_0_bits_uop_fcn_op_0 = io_lsu_iwakeups_0_bits_uop_fcn_op; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_val_0 = io_lsu_iwakeups_0_bits_uop_fp_val; // @[tracegen.scala:19:7] wire [2:0] io_lsu_iwakeups_0_bits_uop_fp_rm_0 = io_lsu_iwakeups_0_bits_uop_fp_rm; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_fp_typ_0 = io_lsu_iwakeups_0_bits_uop_fp_typ; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_xcpt_pf_if_0 = io_lsu_iwakeups_0_bits_uop_xcpt_pf_if; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_xcpt_ae_if_0 = io_lsu_iwakeups_0_bits_uop_xcpt_ae_if; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_xcpt_ma_if_0 = io_lsu_iwakeups_0_bits_uop_xcpt_ma_if; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_bp_debug_if_0 = io_lsu_iwakeups_0_bits_uop_bp_debug_if; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_bp_xcpt_if_0 = io_lsu_iwakeups_0_bits_uop_bp_xcpt_if; // @[tracegen.scala:19:7] wire [2:0] io_lsu_iwakeups_0_bits_uop_debug_fsrc_0 = io_lsu_iwakeups_0_bits_uop_debug_fsrc; // @[tracegen.scala:19:7] wire [2:0] io_lsu_iwakeups_0_bits_uop_debug_tsrc_0 = io_lsu_iwakeups_0_bits_uop_debug_tsrc; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_bypassable_0 = io_lsu_iwakeups_0_bits_bypassable; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_speculative_mask_0 = io_lsu_iwakeups_0_bits_speculative_mask; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_rebusy_0 = io_lsu_iwakeups_0_bits_rebusy; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_valid_0 = io_lsu_iresp_0_valid; // @[tracegen.scala:19:7] wire [31:0] io_lsu_iresp_0_bits_uop_inst_0 = io_lsu_iresp_0_bits_uop_inst; // @[tracegen.scala:19:7] wire [31:0] io_lsu_iresp_0_bits_uop_debug_inst_0 = io_lsu_iresp_0_bits_uop_debug_inst; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_is_rvc_0 = io_lsu_iresp_0_bits_uop_is_rvc; // @[tracegen.scala:19:7] wire [33:0] io_lsu_iresp_0_bits_uop_debug_pc_0 = io_lsu_iresp_0_bits_uop_debug_pc; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_iq_type_0_0 = io_lsu_iresp_0_bits_uop_iq_type_0; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_iq_type_1_0 = io_lsu_iresp_0_bits_uop_iq_type_1; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_iq_type_2_0 = io_lsu_iresp_0_bits_uop_iq_type_2; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_iq_type_3_0 = io_lsu_iresp_0_bits_uop_iq_type_3; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fu_code_0_0 = io_lsu_iresp_0_bits_uop_fu_code_0; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fu_code_1_0 = io_lsu_iresp_0_bits_uop_fu_code_1; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fu_code_2_0 = io_lsu_iresp_0_bits_uop_fu_code_2; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fu_code_3_0 = io_lsu_iresp_0_bits_uop_fu_code_3; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fu_code_4_0 = io_lsu_iresp_0_bits_uop_fu_code_4; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fu_code_5_0 = io_lsu_iresp_0_bits_uop_fu_code_5; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fu_code_6_0 = io_lsu_iresp_0_bits_uop_fu_code_6; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fu_code_7_0 = io_lsu_iresp_0_bits_uop_fu_code_7; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fu_code_8_0 = io_lsu_iresp_0_bits_uop_fu_code_8; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fu_code_9_0 = io_lsu_iresp_0_bits_uop_fu_code_9; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_iw_issued_0 = io_lsu_iresp_0_bits_uop_iw_issued; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_iw_issued_partial_agen_0 = io_lsu_iresp_0_bits_uop_iw_issued_partial_agen; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_iw_issued_partial_dgen_0 = io_lsu_iresp_0_bits_uop_iw_issued_partial_dgen; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_iw_p1_speculative_child_0 = io_lsu_iresp_0_bits_uop_iw_p1_speculative_child; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_iw_p2_speculative_child_0 = io_lsu_iresp_0_bits_uop_iw_p2_speculative_child; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_iw_p1_bypass_hint_0 = io_lsu_iresp_0_bits_uop_iw_p1_bypass_hint; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_iw_p2_bypass_hint_0 = io_lsu_iresp_0_bits_uop_iw_p2_bypass_hint; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_iw_p3_bypass_hint_0 = io_lsu_iresp_0_bits_uop_iw_p3_bypass_hint; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_dis_col_sel_0 = io_lsu_iresp_0_bits_uop_dis_col_sel; // @[tracegen.scala:19:7] wire [3:0] io_lsu_iresp_0_bits_uop_br_mask_0 = io_lsu_iresp_0_bits_uop_br_mask; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iresp_0_bits_uop_br_tag_0 = io_lsu_iresp_0_bits_uop_br_tag; // @[tracegen.scala:19:7] wire [3:0] io_lsu_iresp_0_bits_uop_br_type_0 = io_lsu_iresp_0_bits_uop_br_type; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_is_sfb_0 = io_lsu_iresp_0_bits_uop_is_sfb; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_is_fence_0 = io_lsu_iresp_0_bits_uop_is_fence; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_is_fencei_0 = io_lsu_iresp_0_bits_uop_is_fencei; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_is_sfence_0 = io_lsu_iresp_0_bits_uop_is_sfence; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_is_amo_0 = io_lsu_iresp_0_bits_uop_is_amo; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_is_eret_0 = io_lsu_iresp_0_bits_uop_is_eret; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_is_sys_pc2epc_0 = io_lsu_iresp_0_bits_uop_is_sys_pc2epc; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_is_rocc_0 = io_lsu_iresp_0_bits_uop_is_rocc; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_is_mov_0 = io_lsu_iresp_0_bits_uop_is_mov; // @[tracegen.scala:19:7] wire [3:0] io_lsu_iresp_0_bits_uop_ftq_idx_0 = io_lsu_iresp_0_bits_uop_ftq_idx; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_edge_inst_0 = io_lsu_iresp_0_bits_uop_edge_inst; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iresp_0_bits_uop_pc_lob_0 = io_lsu_iresp_0_bits_uop_pc_lob; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_taken_0 = io_lsu_iresp_0_bits_uop_taken; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_imm_rename_0 = io_lsu_iresp_0_bits_uop_imm_rename; // @[tracegen.scala:19:7] wire [2:0] io_lsu_iresp_0_bits_uop_imm_sel_0 = io_lsu_iresp_0_bits_uop_imm_sel; // @[tracegen.scala:19:7] wire [4:0] io_lsu_iresp_0_bits_uop_pimm_0 = io_lsu_iresp_0_bits_uop_pimm; // @[tracegen.scala:19:7] wire [19:0] io_lsu_iresp_0_bits_uop_imm_packed_0 = io_lsu_iresp_0_bits_uop_imm_packed; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iresp_0_bits_uop_op1_sel_0 = io_lsu_iresp_0_bits_uop_op1_sel; // @[tracegen.scala:19:7] wire [2:0] io_lsu_iresp_0_bits_uop_op2_sel_0 = io_lsu_iresp_0_bits_uop_op2_sel; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_ldst_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_ldst; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_wen_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_wen; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_ren1_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_ren1; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_ren2_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_ren2; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_ren3_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_ren3; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_swap12_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_swap12; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_swap23_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_swap23; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iresp_0_bits_uop_fp_ctrl_typeTagIn_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_typeTagIn; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iresp_0_bits_uop_fp_ctrl_typeTagOut_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_typeTagOut; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_fromint_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_fromint; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_toint_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_toint; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_fastpipe_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_fastpipe; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_fma_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_fma; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_div_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_div; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_sqrt_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_sqrt; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_wflags_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_wflags; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_vec_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_vec; // @[tracegen.scala:19:7] wire [4:0] io_lsu_iresp_0_bits_uop_rob_idx_0 = io_lsu_iresp_0_bits_uop_rob_idx; // @[tracegen.scala:19:7] wire [3:0] io_lsu_iresp_0_bits_uop_ldq_idx_0 = io_lsu_iresp_0_bits_uop_ldq_idx; // @[tracegen.scala:19:7] wire [3:0] io_lsu_iresp_0_bits_uop_stq_idx_0 = io_lsu_iresp_0_bits_uop_stq_idx; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iresp_0_bits_uop_rxq_idx_0 = io_lsu_iresp_0_bits_uop_rxq_idx; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iresp_0_bits_uop_pdst_0 = io_lsu_iresp_0_bits_uop_pdst; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iresp_0_bits_uop_prs1_0 = io_lsu_iresp_0_bits_uop_prs1; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iresp_0_bits_uop_prs2_0 = io_lsu_iresp_0_bits_uop_prs2; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iresp_0_bits_uop_prs3_0 = io_lsu_iresp_0_bits_uop_prs3; // @[tracegen.scala:19:7] wire [3:0] io_lsu_iresp_0_bits_uop_ppred_0 = io_lsu_iresp_0_bits_uop_ppred; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_prs1_busy_0 = io_lsu_iresp_0_bits_uop_prs1_busy; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_prs2_busy_0 = io_lsu_iresp_0_bits_uop_prs2_busy; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_prs3_busy_0 = io_lsu_iresp_0_bits_uop_prs3_busy; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_ppred_busy_0 = io_lsu_iresp_0_bits_uop_ppred_busy; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iresp_0_bits_uop_stale_pdst_0 = io_lsu_iresp_0_bits_uop_stale_pdst; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_exception_0 = io_lsu_iresp_0_bits_uop_exception; // @[tracegen.scala:19:7] wire [63:0] io_lsu_iresp_0_bits_uop_exc_cause_0 = io_lsu_iresp_0_bits_uop_exc_cause; // @[tracegen.scala:19:7] wire [4:0] io_lsu_iresp_0_bits_uop_mem_cmd_0 = io_lsu_iresp_0_bits_uop_mem_cmd; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iresp_0_bits_uop_mem_size_0 = io_lsu_iresp_0_bits_uop_mem_size; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_mem_signed_0 = io_lsu_iresp_0_bits_uop_mem_signed; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_uses_ldq_0 = io_lsu_iresp_0_bits_uop_uses_ldq; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_uses_stq_0 = io_lsu_iresp_0_bits_uop_uses_stq; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_is_unique_0 = io_lsu_iresp_0_bits_uop_is_unique; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_flush_on_commit_0 = io_lsu_iresp_0_bits_uop_flush_on_commit; // @[tracegen.scala:19:7] wire [2:0] io_lsu_iresp_0_bits_uop_csr_cmd_0 = io_lsu_iresp_0_bits_uop_csr_cmd; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_ldst_is_rs1_0 = io_lsu_iresp_0_bits_uop_ldst_is_rs1; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iresp_0_bits_uop_ldst_0 = io_lsu_iresp_0_bits_uop_ldst; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iresp_0_bits_uop_lrs1_0 = io_lsu_iresp_0_bits_uop_lrs1; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iresp_0_bits_uop_lrs2_0 = io_lsu_iresp_0_bits_uop_lrs2; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iresp_0_bits_uop_lrs3_0 = io_lsu_iresp_0_bits_uop_lrs3; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iresp_0_bits_uop_dst_rtype_0 = io_lsu_iresp_0_bits_uop_dst_rtype; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iresp_0_bits_uop_lrs1_rtype_0 = io_lsu_iresp_0_bits_uop_lrs1_rtype; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iresp_0_bits_uop_lrs2_rtype_0 = io_lsu_iresp_0_bits_uop_lrs2_rtype; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_frs3_en_0 = io_lsu_iresp_0_bits_uop_frs3_en; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fcn_dw_0 = io_lsu_iresp_0_bits_uop_fcn_dw; // @[tracegen.scala:19:7] wire [4:0] io_lsu_iresp_0_bits_uop_fcn_op_0 = io_lsu_iresp_0_bits_uop_fcn_op; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_val_0 = io_lsu_iresp_0_bits_uop_fp_val; // @[tracegen.scala:19:7] wire [2:0] io_lsu_iresp_0_bits_uop_fp_rm_0 = io_lsu_iresp_0_bits_uop_fp_rm; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iresp_0_bits_uop_fp_typ_0 = io_lsu_iresp_0_bits_uop_fp_typ; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_xcpt_pf_if_0 = io_lsu_iresp_0_bits_uop_xcpt_pf_if; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_xcpt_ae_if_0 = io_lsu_iresp_0_bits_uop_xcpt_ae_if; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_xcpt_ma_if_0 = io_lsu_iresp_0_bits_uop_xcpt_ma_if; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_bp_debug_if_0 = io_lsu_iresp_0_bits_uop_bp_debug_if; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_bp_xcpt_if_0 = io_lsu_iresp_0_bits_uop_bp_xcpt_if; // @[tracegen.scala:19:7] wire [2:0] io_lsu_iresp_0_bits_uop_debug_fsrc_0 = io_lsu_iresp_0_bits_uop_debug_fsrc; // @[tracegen.scala:19:7] wire [2:0] io_lsu_iresp_0_bits_uop_debug_tsrc_0 = io_lsu_iresp_0_bits_uop_debug_tsrc; // @[tracegen.scala:19:7] wire [63:0] io_lsu_iresp_0_bits_data_0 = io_lsu_iresp_0_bits_data; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_valid_0 = io_lsu_fresp_0_valid; // @[tracegen.scala:19:7] wire [31:0] io_lsu_fresp_0_bits_uop_inst_0 = io_lsu_fresp_0_bits_uop_inst; // @[tracegen.scala:19:7] wire [31:0] io_lsu_fresp_0_bits_uop_debug_inst_0 = io_lsu_fresp_0_bits_uop_debug_inst; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_is_rvc_0 = io_lsu_fresp_0_bits_uop_is_rvc; // @[tracegen.scala:19:7] wire [33:0] io_lsu_fresp_0_bits_uop_debug_pc_0 = io_lsu_fresp_0_bits_uop_debug_pc; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_iq_type_0_0 = io_lsu_fresp_0_bits_uop_iq_type_0; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_iq_type_1_0 = io_lsu_fresp_0_bits_uop_iq_type_1; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_iq_type_2_0 = io_lsu_fresp_0_bits_uop_iq_type_2; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_iq_type_3_0 = io_lsu_fresp_0_bits_uop_iq_type_3; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fu_code_0_0 = io_lsu_fresp_0_bits_uop_fu_code_0; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fu_code_1_0 = io_lsu_fresp_0_bits_uop_fu_code_1; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fu_code_2_0 = io_lsu_fresp_0_bits_uop_fu_code_2; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fu_code_3_0 = io_lsu_fresp_0_bits_uop_fu_code_3; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fu_code_4_0 = io_lsu_fresp_0_bits_uop_fu_code_4; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fu_code_5_0 = io_lsu_fresp_0_bits_uop_fu_code_5; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fu_code_6_0 = io_lsu_fresp_0_bits_uop_fu_code_6; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fu_code_7_0 = io_lsu_fresp_0_bits_uop_fu_code_7; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fu_code_8_0 = io_lsu_fresp_0_bits_uop_fu_code_8; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fu_code_9_0 = io_lsu_fresp_0_bits_uop_fu_code_9; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_iw_issued_0 = io_lsu_fresp_0_bits_uop_iw_issued; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_iw_issued_partial_agen_0 = io_lsu_fresp_0_bits_uop_iw_issued_partial_agen; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_iw_issued_partial_dgen_0 = io_lsu_fresp_0_bits_uop_iw_issued_partial_dgen; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_iw_p1_speculative_child_0 = io_lsu_fresp_0_bits_uop_iw_p1_speculative_child; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_iw_p2_speculative_child_0 = io_lsu_fresp_0_bits_uop_iw_p2_speculative_child; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_iw_p1_bypass_hint_0 = io_lsu_fresp_0_bits_uop_iw_p1_bypass_hint; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_iw_p2_bypass_hint_0 = io_lsu_fresp_0_bits_uop_iw_p2_bypass_hint; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_iw_p3_bypass_hint_0 = io_lsu_fresp_0_bits_uop_iw_p3_bypass_hint; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_dis_col_sel_0 = io_lsu_fresp_0_bits_uop_dis_col_sel; // @[tracegen.scala:19:7] wire [3:0] io_lsu_fresp_0_bits_uop_br_mask_0 = io_lsu_fresp_0_bits_uop_br_mask; // @[tracegen.scala:19:7] wire [1:0] io_lsu_fresp_0_bits_uop_br_tag_0 = io_lsu_fresp_0_bits_uop_br_tag; // @[tracegen.scala:19:7] wire [3:0] io_lsu_fresp_0_bits_uop_br_type_0 = io_lsu_fresp_0_bits_uop_br_type; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_is_sfb_0 = io_lsu_fresp_0_bits_uop_is_sfb; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_is_fence_0 = io_lsu_fresp_0_bits_uop_is_fence; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_is_fencei_0 = io_lsu_fresp_0_bits_uop_is_fencei; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_is_sfence_0 = io_lsu_fresp_0_bits_uop_is_sfence; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_is_amo_0 = io_lsu_fresp_0_bits_uop_is_amo; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_is_eret_0 = io_lsu_fresp_0_bits_uop_is_eret; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_is_sys_pc2epc_0 = io_lsu_fresp_0_bits_uop_is_sys_pc2epc; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_is_rocc_0 = io_lsu_fresp_0_bits_uop_is_rocc; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_is_mov_0 = io_lsu_fresp_0_bits_uop_is_mov; // @[tracegen.scala:19:7] wire [3:0] io_lsu_fresp_0_bits_uop_ftq_idx_0 = io_lsu_fresp_0_bits_uop_ftq_idx; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_edge_inst_0 = io_lsu_fresp_0_bits_uop_edge_inst; // @[tracegen.scala:19:7] wire [5:0] io_lsu_fresp_0_bits_uop_pc_lob_0 = io_lsu_fresp_0_bits_uop_pc_lob; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_taken_0 = io_lsu_fresp_0_bits_uop_taken; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_imm_rename_0 = io_lsu_fresp_0_bits_uop_imm_rename; // @[tracegen.scala:19:7] wire [2:0] io_lsu_fresp_0_bits_uop_imm_sel_0 = io_lsu_fresp_0_bits_uop_imm_sel; // @[tracegen.scala:19:7] wire [4:0] io_lsu_fresp_0_bits_uop_pimm_0 = io_lsu_fresp_0_bits_uop_pimm; // @[tracegen.scala:19:7] wire [19:0] io_lsu_fresp_0_bits_uop_imm_packed_0 = io_lsu_fresp_0_bits_uop_imm_packed; // @[tracegen.scala:19:7] wire [1:0] io_lsu_fresp_0_bits_uop_op1_sel_0 = io_lsu_fresp_0_bits_uop_op1_sel; // @[tracegen.scala:19:7] wire [2:0] io_lsu_fresp_0_bits_uop_op2_sel_0 = io_lsu_fresp_0_bits_uop_op2_sel; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_ldst_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_ldst; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_wen_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_wen; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_ren1_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_ren1; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_ren2_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_ren2; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_ren3_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_ren3; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_swap12_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_swap12; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_swap23_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_swap23; // @[tracegen.scala:19:7] wire [1:0] io_lsu_fresp_0_bits_uop_fp_ctrl_typeTagIn_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_typeTagIn; // @[tracegen.scala:19:7] wire [1:0] io_lsu_fresp_0_bits_uop_fp_ctrl_typeTagOut_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_typeTagOut; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_fromint_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_fromint; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_toint_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_toint; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_fastpipe_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_fastpipe; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_fma_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_fma; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_div_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_div; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_sqrt_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_sqrt; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_wflags_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_wflags; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_vec_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_vec; // @[tracegen.scala:19:7] wire [4:0] io_lsu_fresp_0_bits_uop_rob_idx_0 = io_lsu_fresp_0_bits_uop_rob_idx; // @[tracegen.scala:19:7] wire [3:0] io_lsu_fresp_0_bits_uop_ldq_idx_0 = io_lsu_fresp_0_bits_uop_ldq_idx; // @[tracegen.scala:19:7] wire [3:0] io_lsu_fresp_0_bits_uop_stq_idx_0 = io_lsu_fresp_0_bits_uop_stq_idx; // @[tracegen.scala:19:7] wire [1:0] io_lsu_fresp_0_bits_uop_rxq_idx_0 = io_lsu_fresp_0_bits_uop_rxq_idx; // @[tracegen.scala:19:7] wire [5:0] io_lsu_fresp_0_bits_uop_pdst_0 = io_lsu_fresp_0_bits_uop_pdst; // @[tracegen.scala:19:7] wire [5:0] io_lsu_fresp_0_bits_uop_prs1_0 = io_lsu_fresp_0_bits_uop_prs1; // @[tracegen.scala:19:7] wire [5:0] io_lsu_fresp_0_bits_uop_prs2_0 = io_lsu_fresp_0_bits_uop_prs2; // @[tracegen.scala:19:7] wire [5:0] io_lsu_fresp_0_bits_uop_prs3_0 = io_lsu_fresp_0_bits_uop_prs3; // @[tracegen.scala:19:7] wire [3:0] io_lsu_fresp_0_bits_uop_ppred_0 = io_lsu_fresp_0_bits_uop_ppred; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_prs1_busy_0 = io_lsu_fresp_0_bits_uop_prs1_busy; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_prs2_busy_0 = io_lsu_fresp_0_bits_uop_prs2_busy; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_prs3_busy_0 = io_lsu_fresp_0_bits_uop_prs3_busy; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_ppred_busy_0 = io_lsu_fresp_0_bits_uop_ppred_busy; // @[tracegen.scala:19:7] wire [5:0] io_lsu_fresp_0_bits_uop_stale_pdst_0 = io_lsu_fresp_0_bits_uop_stale_pdst; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_exception_0 = io_lsu_fresp_0_bits_uop_exception; // @[tracegen.scala:19:7] wire [63:0] io_lsu_fresp_0_bits_uop_exc_cause_0 = io_lsu_fresp_0_bits_uop_exc_cause; // @[tracegen.scala:19:7] wire [4:0] io_lsu_fresp_0_bits_uop_mem_cmd_0 = io_lsu_fresp_0_bits_uop_mem_cmd; // @[tracegen.scala:19:7] wire [1:0] io_lsu_fresp_0_bits_uop_mem_size_0 = io_lsu_fresp_0_bits_uop_mem_size; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_mem_signed_0 = io_lsu_fresp_0_bits_uop_mem_signed; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_uses_ldq_0 = io_lsu_fresp_0_bits_uop_uses_ldq; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_uses_stq_0 = io_lsu_fresp_0_bits_uop_uses_stq; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_is_unique_0 = io_lsu_fresp_0_bits_uop_is_unique; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_flush_on_commit_0 = io_lsu_fresp_0_bits_uop_flush_on_commit; // @[tracegen.scala:19:7] wire [2:0] io_lsu_fresp_0_bits_uop_csr_cmd_0 = io_lsu_fresp_0_bits_uop_csr_cmd; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_ldst_is_rs1_0 = io_lsu_fresp_0_bits_uop_ldst_is_rs1; // @[tracegen.scala:19:7] wire [5:0] io_lsu_fresp_0_bits_uop_ldst_0 = io_lsu_fresp_0_bits_uop_ldst; // @[tracegen.scala:19:7] wire [5:0] io_lsu_fresp_0_bits_uop_lrs1_0 = io_lsu_fresp_0_bits_uop_lrs1; // @[tracegen.scala:19:7] wire [5:0] io_lsu_fresp_0_bits_uop_lrs2_0 = io_lsu_fresp_0_bits_uop_lrs2; // @[tracegen.scala:19:7] wire [5:0] io_lsu_fresp_0_bits_uop_lrs3_0 = io_lsu_fresp_0_bits_uop_lrs3; // @[tracegen.scala:19:7] wire [1:0] io_lsu_fresp_0_bits_uop_dst_rtype_0 = io_lsu_fresp_0_bits_uop_dst_rtype; // @[tracegen.scala:19:7] wire [1:0] io_lsu_fresp_0_bits_uop_lrs1_rtype_0 = io_lsu_fresp_0_bits_uop_lrs1_rtype; // @[tracegen.scala:19:7] wire [1:0] io_lsu_fresp_0_bits_uop_lrs2_rtype_0 = io_lsu_fresp_0_bits_uop_lrs2_rtype; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_frs3_en_0 = io_lsu_fresp_0_bits_uop_frs3_en; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fcn_dw_0 = io_lsu_fresp_0_bits_uop_fcn_dw; // @[tracegen.scala:19:7] wire [4:0] io_lsu_fresp_0_bits_uop_fcn_op_0 = io_lsu_fresp_0_bits_uop_fcn_op; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_val_0 = io_lsu_fresp_0_bits_uop_fp_val; // @[tracegen.scala:19:7] wire [2:0] io_lsu_fresp_0_bits_uop_fp_rm_0 = io_lsu_fresp_0_bits_uop_fp_rm; // @[tracegen.scala:19:7] wire [1:0] io_lsu_fresp_0_bits_uop_fp_typ_0 = io_lsu_fresp_0_bits_uop_fp_typ; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_xcpt_pf_if_0 = io_lsu_fresp_0_bits_uop_xcpt_pf_if; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_xcpt_ae_if_0 = io_lsu_fresp_0_bits_uop_xcpt_ae_if; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_xcpt_ma_if_0 = io_lsu_fresp_0_bits_uop_xcpt_ma_if; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_bp_debug_if_0 = io_lsu_fresp_0_bits_uop_bp_debug_if; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_bp_xcpt_if_0 = io_lsu_fresp_0_bits_uop_bp_xcpt_if; // @[tracegen.scala:19:7] wire [2:0] io_lsu_fresp_0_bits_uop_debug_fsrc_0 = io_lsu_fresp_0_bits_uop_debug_fsrc; // @[tracegen.scala:19:7] wire [2:0] io_lsu_fresp_0_bits_uop_debug_tsrc_0 = io_lsu_fresp_0_bits_uop_debug_tsrc; // @[tracegen.scala:19:7] wire [63:0] io_lsu_fresp_0_bits_data_0 = io_lsu_fresp_0_bits_data; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dis_ldq_idx_0_0 = io_lsu_dis_ldq_idx_0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dis_stq_idx_0_0 = io_lsu_dis_stq_idx_0; // @[tracegen.scala:19:7] wire io_lsu_ldq_full_0_0 = io_lsu_ldq_full_0; // @[tracegen.scala:19:7] wire io_lsu_stq_full_0_0 = io_lsu_stq_full_0; // @[tracegen.scala:19:7] wire io_lsu_clr_bsy_0_valid_0 = io_lsu_clr_bsy_0_valid; // @[tracegen.scala:19:7] wire [4:0] io_lsu_clr_bsy_0_bits_0 = io_lsu_clr_bsy_0_bits; // @[tracegen.scala:19:7] wire io_lsu_clr_unsafe_0_valid_0 = io_lsu_clr_unsafe_0_valid; // @[tracegen.scala:19:7] wire [4:0] io_lsu_clr_unsafe_0_bits_0 = io_lsu_clr_unsafe_0_bits; // @[tracegen.scala:19:7] wire io_lsu_fencei_rdy_0 = io_lsu_fencei_rdy; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_valid_0 = io_lsu_lxcpt_valid; // @[tracegen.scala:19:7] wire [31:0] io_lsu_lxcpt_bits_uop_inst_0 = io_lsu_lxcpt_bits_uop_inst; // @[tracegen.scala:19:7] wire [31:0] io_lsu_lxcpt_bits_uop_debug_inst_0 = io_lsu_lxcpt_bits_uop_debug_inst; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_is_rvc_0 = io_lsu_lxcpt_bits_uop_is_rvc; // @[tracegen.scala:19:7] wire [33:0] io_lsu_lxcpt_bits_uop_debug_pc_0 = io_lsu_lxcpt_bits_uop_debug_pc; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_iq_type_0_0 = io_lsu_lxcpt_bits_uop_iq_type_0; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_iq_type_1_0 = io_lsu_lxcpt_bits_uop_iq_type_1; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_iq_type_2_0 = io_lsu_lxcpt_bits_uop_iq_type_2; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_iq_type_3_0 = io_lsu_lxcpt_bits_uop_iq_type_3; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fu_code_0_0 = io_lsu_lxcpt_bits_uop_fu_code_0; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fu_code_1_0 = io_lsu_lxcpt_bits_uop_fu_code_1; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fu_code_2_0 = io_lsu_lxcpt_bits_uop_fu_code_2; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fu_code_3_0 = io_lsu_lxcpt_bits_uop_fu_code_3; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fu_code_4_0 = io_lsu_lxcpt_bits_uop_fu_code_4; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fu_code_5_0 = io_lsu_lxcpt_bits_uop_fu_code_5; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fu_code_6_0 = io_lsu_lxcpt_bits_uop_fu_code_6; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fu_code_7_0 = io_lsu_lxcpt_bits_uop_fu_code_7; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fu_code_8_0 = io_lsu_lxcpt_bits_uop_fu_code_8; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fu_code_9_0 = io_lsu_lxcpt_bits_uop_fu_code_9; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_iw_issued_0 = io_lsu_lxcpt_bits_uop_iw_issued; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_iw_issued_partial_agen_0 = io_lsu_lxcpt_bits_uop_iw_issued_partial_agen; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_iw_issued_partial_dgen_0 = io_lsu_lxcpt_bits_uop_iw_issued_partial_dgen; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_iw_p1_speculative_child_0 = io_lsu_lxcpt_bits_uop_iw_p1_speculative_child; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_iw_p2_speculative_child_0 = io_lsu_lxcpt_bits_uop_iw_p2_speculative_child; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_iw_p1_bypass_hint_0 = io_lsu_lxcpt_bits_uop_iw_p1_bypass_hint; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_iw_p2_bypass_hint_0 = io_lsu_lxcpt_bits_uop_iw_p2_bypass_hint; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_iw_p3_bypass_hint_0 = io_lsu_lxcpt_bits_uop_iw_p3_bypass_hint; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_dis_col_sel_0 = io_lsu_lxcpt_bits_uop_dis_col_sel; // @[tracegen.scala:19:7] wire [3:0] io_lsu_lxcpt_bits_uop_br_mask_0 = io_lsu_lxcpt_bits_uop_br_mask; // @[tracegen.scala:19:7] wire [1:0] io_lsu_lxcpt_bits_uop_br_tag_0 = io_lsu_lxcpt_bits_uop_br_tag; // @[tracegen.scala:19:7] wire [3:0] io_lsu_lxcpt_bits_uop_br_type_0 = io_lsu_lxcpt_bits_uop_br_type; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_is_sfb_0 = io_lsu_lxcpt_bits_uop_is_sfb; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_is_fence_0 = io_lsu_lxcpt_bits_uop_is_fence; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_is_fencei_0 = io_lsu_lxcpt_bits_uop_is_fencei; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_is_sfence_0 = io_lsu_lxcpt_bits_uop_is_sfence; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_is_amo_0 = io_lsu_lxcpt_bits_uop_is_amo; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_is_eret_0 = io_lsu_lxcpt_bits_uop_is_eret; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_is_sys_pc2epc_0 = io_lsu_lxcpt_bits_uop_is_sys_pc2epc; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_is_rocc_0 = io_lsu_lxcpt_bits_uop_is_rocc; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_is_mov_0 = io_lsu_lxcpt_bits_uop_is_mov; // @[tracegen.scala:19:7] wire [3:0] io_lsu_lxcpt_bits_uop_ftq_idx_0 = io_lsu_lxcpt_bits_uop_ftq_idx; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_edge_inst_0 = io_lsu_lxcpt_bits_uop_edge_inst; // @[tracegen.scala:19:7] wire [5:0] io_lsu_lxcpt_bits_uop_pc_lob_0 = io_lsu_lxcpt_bits_uop_pc_lob; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_taken_0 = io_lsu_lxcpt_bits_uop_taken; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_imm_rename_0 = io_lsu_lxcpt_bits_uop_imm_rename; // @[tracegen.scala:19:7] wire [2:0] io_lsu_lxcpt_bits_uop_imm_sel_0 = io_lsu_lxcpt_bits_uop_imm_sel; // @[tracegen.scala:19:7] wire [4:0] io_lsu_lxcpt_bits_uop_pimm_0 = io_lsu_lxcpt_bits_uop_pimm; // @[tracegen.scala:19:7] wire [19:0] io_lsu_lxcpt_bits_uop_imm_packed_0 = io_lsu_lxcpt_bits_uop_imm_packed; // @[tracegen.scala:19:7] wire [1:0] io_lsu_lxcpt_bits_uop_op1_sel_0 = io_lsu_lxcpt_bits_uop_op1_sel; // @[tracegen.scala:19:7] wire [2:0] io_lsu_lxcpt_bits_uop_op2_sel_0 = io_lsu_lxcpt_bits_uop_op2_sel; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_ldst_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_ldst; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_wen_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_wen; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_ren1_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_ren1; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_ren2_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_ren2; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_ren3_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_ren3; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_swap12_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_swap12; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_swap23_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_swap23; // @[tracegen.scala:19:7] wire [1:0] io_lsu_lxcpt_bits_uop_fp_ctrl_typeTagIn_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_typeTagIn; // @[tracegen.scala:19:7] wire [1:0] io_lsu_lxcpt_bits_uop_fp_ctrl_typeTagOut_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_typeTagOut; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_fromint_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_fromint; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_toint_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_toint; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_fastpipe_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_fastpipe; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_fma_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_fma; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_div_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_div; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_sqrt_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_sqrt; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_wflags_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_wflags; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_vec_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_vec; // @[tracegen.scala:19:7] wire [4:0] io_lsu_lxcpt_bits_uop_rob_idx_0 = io_lsu_lxcpt_bits_uop_rob_idx; // @[tracegen.scala:19:7] wire [3:0] io_lsu_lxcpt_bits_uop_ldq_idx_0 = io_lsu_lxcpt_bits_uop_ldq_idx; // @[tracegen.scala:19:7] wire [3:0] io_lsu_lxcpt_bits_uop_stq_idx_0 = io_lsu_lxcpt_bits_uop_stq_idx; // @[tracegen.scala:19:7] wire [1:0] io_lsu_lxcpt_bits_uop_rxq_idx_0 = io_lsu_lxcpt_bits_uop_rxq_idx; // @[tracegen.scala:19:7] wire [5:0] io_lsu_lxcpt_bits_uop_pdst_0 = io_lsu_lxcpt_bits_uop_pdst; // @[tracegen.scala:19:7] wire [5:0] io_lsu_lxcpt_bits_uop_prs1_0 = io_lsu_lxcpt_bits_uop_prs1; // @[tracegen.scala:19:7] wire [5:0] io_lsu_lxcpt_bits_uop_prs2_0 = io_lsu_lxcpt_bits_uop_prs2; // @[tracegen.scala:19:7] wire [5:0] io_lsu_lxcpt_bits_uop_prs3_0 = io_lsu_lxcpt_bits_uop_prs3; // @[tracegen.scala:19:7] wire [3:0] io_lsu_lxcpt_bits_uop_ppred_0 = io_lsu_lxcpt_bits_uop_ppred; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_prs1_busy_0 = io_lsu_lxcpt_bits_uop_prs1_busy; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_prs2_busy_0 = io_lsu_lxcpt_bits_uop_prs2_busy; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_prs3_busy_0 = io_lsu_lxcpt_bits_uop_prs3_busy; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_ppred_busy_0 = io_lsu_lxcpt_bits_uop_ppred_busy; // @[tracegen.scala:19:7] wire [5:0] io_lsu_lxcpt_bits_uop_stale_pdst_0 = io_lsu_lxcpt_bits_uop_stale_pdst; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_exception_0 = io_lsu_lxcpt_bits_uop_exception; // @[tracegen.scala:19:7] wire [63:0] io_lsu_lxcpt_bits_uop_exc_cause_0 = io_lsu_lxcpt_bits_uop_exc_cause; // @[tracegen.scala:19:7] wire [4:0] io_lsu_lxcpt_bits_uop_mem_cmd_0 = io_lsu_lxcpt_bits_uop_mem_cmd; // @[tracegen.scala:19:7] wire [1:0] io_lsu_lxcpt_bits_uop_mem_size_0 = io_lsu_lxcpt_bits_uop_mem_size; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_mem_signed_0 = io_lsu_lxcpt_bits_uop_mem_signed; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_uses_ldq_0 = io_lsu_lxcpt_bits_uop_uses_ldq; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_uses_stq_0 = io_lsu_lxcpt_bits_uop_uses_stq; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_is_unique_0 = io_lsu_lxcpt_bits_uop_is_unique; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_flush_on_commit_0 = io_lsu_lxcpt_bits_uop_flush_on_commit; // @[tracegen.scala:19:7] wire [2:0] io_lsu_lxcpt_bits_uop_csr_cmd_0 = io_lsu_lxcpt_bits_uop_csr_cmd; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_ldst_is_rs1_0 = io_lsu_lxcpt_bits_uop_ldst_is_rs1; // @[tracegen.scala:19:7] wire [5:0] io_lsu_lxcpt_bits_uop_ldst_0 = io_lsu_lxcpt_bits_uop_ldst; // @[tracegen.scala:19:7] wire [5:0] io_lsu_lxcpt_bits_uop_lrs1_0 = io_lsu_lxcpt_bits_uop_lrs1; // @[tracegen.scala:19:7] wire [5:0] io_lsu_lxcpt_bits_uop_lrs2_0 = io_lsu_lxcpt_bits_uop_lrs2; // @[tracegen.scala:19:7] wire [5:0] io_lsu_lxcpt_bits_uop_lrs3_0 = io_lsu_lxcpt_bits_uop_lrs3; // @[tracegen.scala:19:7] wire [1:0] io_lsu_lxcpt_bits_uop_dst_rtype_0 = io_lsu_lxcpt_bits_uop_dst_rtype; // @[tracegen.scala:19:7] wire [1:0] io_lsu_lxcpt_bits_uop_lrs1_rtype_0 = io_lsu_lxcpt_bits_uop_lrs1_rtype; // @[tracegen.scala:19:7] wire [1:0] io_lsu_lxcpt_bits_uop_lrs2_rtype_0 = io_lsu_lxcpt_bits_uop_lrs2_rtype; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_frs3_en_0 = io_lsu_lxcpt_bits_uop_frs3_en; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fcn_dw_0 = io_lsu_lxcpt_bits_uop_fcn_dw; // @[tracegen.scala:19:7] wire [4:0] io_lsu_lxcpt_bits_uop_fcn_op_0 = io_lsu_lxcpt_bits_uop_fcn_op; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_val_0 = io_lsu_lxcpt_bits_uop_fp_val; // @[tracegen.scala:19:7] wire [2:0] io_lsu_lxcpt_bits_uop_fp_rm_0 = io_lsu_lxcpt_bits_uop_fp_rm; // @[tracegen.scala:19:7] wire [1:0] io_lsu_lxcpt_bits_uop_fp_typ_0 = io_lsu_lxcpt_bits_uop_fp_typ; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_xcpt_pf_if_0 = io_lsu_lxcpt_bits_uop_xcpt_pf_if; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_xcpt_ae_if_0 = io_lsu_lxcpt_bits_uop_xcpt_ae_if; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_xcpt_ma_if_0 = io_lsu_lxcpt_bits_uop_xcpt_ma_if; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_bp_debug_if_0 = io_lsu_lxcpt_bits_uop_bp_debug_if; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_bp_xcpt_if_0 = io_lsu_lxcpt_bits_uop_bp_xcpt_if; // @[tracegen.scala:19:7] wire [2:0] io_lsu_lxcpt_bits_uop_debug_fsrc_0 = io_lsu_lxcpt_bits_uop_debug_fsrc; // @[tracegen.scala:19:7] wire [2:0] io_lsu_lxcpt_bits_uop_debug_tsrc_0 = io_lsu_lxcpt_bits_uop_debug_tsrc; // @[tracegen.scala:19:7] wire [4:0] io_lsu_lxcpt_bits_cause_0 = io_lsu_lxcpt_bits_cause; // @[tracegen.scala:19:7] wire [33:0] io_lsu_lxcpt_bits_badvaddr_0 = io_lsu_lxcpt_bits_badvaddr; // @[tracegen.scala:19:7] wire io_lsu_perf_acquire_0 = io_lsu_perf_acquire; // @[tracegen.scala:19:7] wire io_lsu_perf_release_0 = io_lsu_perf_release; // @[tracegen.scala:19:7] wire io_tracegen_req_valid_0 = io_tracegen_req_valid; // @[tracegen.scala:19:7] wire [33:0] io_tracegen_req_bits_addr_0 = io_tracegen_req_bits_addr; // @[tracegen.scala:19:7] wire [5:0] io_tracegen_req_bits_tag_0 = io_tracegen_req_bits_tag; // @[tracegen.scala:19:7] wire [4:0] io_tracegen_req_bits_cmd_0 = io_tracegen_req_bits_cmd; // @[tracegen.scala:19:7] wire [63:0] io_tracegen_req_bits_data_0 = io_tracegen_req_bits_data; // @[tracegen.scala:19:7] wire [63:0] io_tracegen_s1_data_data_0 = io_tracegen_s1_data_data; // @[tracegen.scala:19:7] wire [31:0] io_lsu_agen_0_bits_uop_inst = 32'h0; // @[tracegen.scala:19:7] wire [31:0] io_lsu_dgen_0_bits_uop_inst = 32'h0; // @[tracegen.scala:19:7] wire [31:0] io_lsu_dgen_1_bits_uop_inst = 32'h0; // @[tracegen.scala:19:7] wire [31:0] io_lsu_dgen_1_bits_uop_debug_inst = 32'h0; // @[tracegen.scala:19:7] wire [31:0] io_lsu_dgen_2_bits_uop_inst = 32'h0; // @[tracegen.scala:19:7] wire [31:0] io_lsu_dgen_2_bits_uop_debug_inst = 32'h0; // @[tracegen.scala:19:7] wire [31:0] io_lsu_dis_uops_0_bits_inst = 32'h0; // @[tracegen.scala:19:7] wire [31:0] io_lsu_commit_uops_0_inst_0 = 32'h0; // @[tracegen.scala:19:7] wire [31:0] io_lsu_commit_debug_insts_0 = 32'h0; // @[tracegen.scala:19:7] wire [31:0] io_lsu_brupdate_b2_uop_inst = 32'h0; // @[tracegen.scala:19:7] wire [31:0] io_lsu_brupdate_b2_uop_debug_inst = 32'h0; // @[tracegen.scala:19:7] wire [31:0] io_lsu_status_isa = 32'h0; // @[tracegen.scala:19:7] wire [31:0] io_tracegen_s2_paddr = 32'h0; // @[tracegen.scala:19:7] wire [31:0] _tracegen_uop_WIRE_inst = 32'h0; // @[tracegen.scala:55:45] wire [31:0] _tracegen_uop_WIRE_debug_inst = 32'h0; // @[tracegen.scala:55:45] wire [31:0] tracegen_uop_inst = 32'h0; // @[tracegen.scala:55:30] wire io_lsu_agen_0_bits_uop_is_rvc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_iq_type_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_iq_type_1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_iq_type_2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_iq_type_3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fu_code_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fu_code_1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fu_code_2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fu_code_3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fu_code_4 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fu_code_5 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fu_code_6 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fu_code_7 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fu_code_8 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fu_code_9 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_iw_issued = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_iw_issued_partial_agen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_iw_issued_partial_dgen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_iw_p1_speculative_child = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_iw_p2_speculative_child = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_iw_p1_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_iw_p2_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_iw_p3_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_dis_col_sel = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_is_sfb = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_is_fence = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_is_fencei = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_is_sfence = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_is_eret = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_is_rocc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_is_mov = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_edge_inst = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_taken = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_imm_rename = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_ldst = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_wen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_ren1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_ren2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_ren3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_swap12 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_swap23 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_fromint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_toint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_fastpipe = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_fma = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_div = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_sqrt = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_wflags = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_vec = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_prs1_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_prs2_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_prs3_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_ppred_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_exception = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_mem_signed = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_is_unique = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_flush_on_commit = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_frs3_en = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fcn_dw = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_val = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_bp_debug_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_is_rvc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_iq_type_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_iq_type_1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_iq_type_2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_iq_type_3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fu_code_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fu_code_1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fu_code_2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fu_code_3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fu_code_4 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fu_code_5 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fu_code_6 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fu_code_7 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fu_code_8 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fu_code_9 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_iw_issued = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_iw_issued_partial_agen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_iw_issued_partial_dgen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_iw_p1_speculative_child = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_iw_p2_speculative_child = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_iw_p1_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_iw_p2_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_iw_p3_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_dis_col_sel = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_is_sfb = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_is_fence = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_is_fencei = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_is_sfence = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_is_eret = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_is_rocc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_is_mov = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_edge_inst = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_taken = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_imm_rename = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_ldst = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_wen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_ren1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_ren2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_ren3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_swap12 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_swap23 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_fromint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_toint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_fastpipe = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_fma = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_div = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_sqrt = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_wflags = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_vec = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_prs1_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_prs2_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_prs3_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_ppred_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_exception = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_mem_signed = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_is_unique = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_flush_on_commit = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_frs3_en = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fcn_dw = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_val = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_bp_debug_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_valid = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_is_rvc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_iq_type_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_iq_type_1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_iq_type_2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_iq_type_3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fu_code_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fu_code_1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fu_code_2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fu_code_3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fu_code_4 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fu_code_5 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fu_code_6 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fu_code_7 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fu_code_8 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fu_code_9 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_iw_issued = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_iw_issued_partial_agen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_iw_issued_partial_dgen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_iw_p1_speculative_child = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_iw_p2_speculative_child = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_iw_p1_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_iw_p2_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_iw_p3_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_dis_col_sel = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_is_sfb = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_is_fence = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_is_fencei = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_is_sfence = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_is_amo = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_is_eret = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_is_rocc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_is_mov = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_edge_inst = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_taken = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_imm_rename = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_ldst = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_wen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_ren1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_ren2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_ren3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_swap12 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_swap23 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_fromint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_toint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_fastpipe = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_fma = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_div = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_sqrt = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_wflags = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_vec = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_prs1_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_prs2_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_prs3_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_ppred_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_exception = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_mem_signed = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_uses_ldq = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_uses_stq = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_is_unique = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_flush_on_commit = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_frs3_en = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fcn_dw = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_val = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_bp_debug_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_valid = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_is_rvc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_iq_type_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_iq_type_1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_iq_type_2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_iq_type_3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fu_code_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fu_code_1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fu_code_2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fu_code_3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fu_code_4 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fu_code_5 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fu_code_6 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fu_code_7 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fu_code_8 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fu_code_9 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_iw_issued = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_iw_p1_speculative_child = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_iw_p2_speculative_child = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_iw_p1_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_iw_p2_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_iw_p3_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_dis_col_sel = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_is_sfb = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_is_fence = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_is_fencei = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_is_sfence = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_is_amo = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_is_eret = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_is_rocc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_is_mov = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_edge_inst = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_taken = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_imm_rename = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_ldst = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_wen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_ren1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_ren2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_ren3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_swap12 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_swap23 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_fromint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_toint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_fastpipe = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_fma = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_div = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_sqrt = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_wflags = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_vec = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_prs1_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_prs2_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_prs3_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_ppred_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_exception = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_mem_signed = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_uses_ldq = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_uses_stq = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_is_unique = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_flush_on_commit = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_frs3_en = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fcn_dw = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_val = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_bp_debug_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_predicated = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_fflags_valid = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_predicated = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_fflags_valid = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_sfence_valid = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_sfence_bits_rs1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_sfence_bits_rs2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_sfence_bits_asid = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_sfence_bits_hv = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_sfence_bits_hg = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_is_rvc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_iq_type_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_iq_type_1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_iq_type_2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_iq_type_3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fu_code_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fu_code_1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fu_code_2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fu_code_3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fu_code_4 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fu_code_5 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fu_code_6 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fu_code_7 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fu_code_8 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fu_code_9 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_iw_issued = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_iw_issued_partial_agen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_iw_issued_partial_dgen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_iw_p1_speculative_child = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_iw_p2_speculative_child = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_iw_p1_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_iw_p2_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_iw_p3_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_dis_col_sel = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_is_sfb = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_is_fence = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_is_fencei = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_is_sfence = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_is_eret = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_is_sys_pc2epc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_is_rocc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_is_mov = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_edge_inst = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_taken = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_imm_rename = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_ldst = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_wen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_ren1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_ren2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_ren3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_swap12 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_swap23 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_fromint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_toint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_fastpipe = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_fma = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_div = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_sqrt = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_wflags = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_vec = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_prs1_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_prs2_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_prs3_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_ppred_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_exception = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_mem_signed = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_is_unique = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_flush_on_commit = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_ldst_is_rs1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_frs3_en = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fcn_dw = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_val = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_xcpt_pf_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_xcpt_ae_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_xcpt_ma_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_bp_debug_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_bp_xcpt_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_arch_valids_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_is_rvc_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_iq_type_0_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_iq_type_1_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_iq_type_2_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_iq_type_3_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fu_code_0_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fu_code_1_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fu_code_2_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fu_code_3_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fu_code_4_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fu_code_5_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fu_code_6_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fu_code_7_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fu_code_8_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fu_code_9_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_iw_issued_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_iw_issued_partial_agen_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_iw_issued_partial_dgen_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_iw_p1_speculative_child_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_iw_p2_speculative_child_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_iw_p1_bypass_hint_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_iw_p2_bypass_hint_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_iw_p3_bypass_hint_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_dis_col_sel_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_is_sfb_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_is_fence_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_is_fencei_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_is_sfence_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_is_eret_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_is_sys_pc2epc_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_is_rocc_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_is_mov_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_edge_inst_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_taken_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_imm_rename_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_ctrl_ldst_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_ctrl_wen_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_ctrl_ren1_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_ctrl_ren2_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_ctrl_ren3_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_ctrl_swap12_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_ctrl_swap23_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_ctrl_fromint_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_ctrl_toint_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_ctrl_fastpipe_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_ctrl_fma_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_ctrl_div_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_ctrl_sqrt_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_ctrl_wflags_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_ctrl_vec_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_prs1_busy_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_prs2_busy_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_prs3_busy_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_ppred_busy_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_exception_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_mem_signed_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_is_unique_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_flush_on_commit_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_ldst_is_rs1_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_frs3_en_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fcn_dw_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_val_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_xcpt_pf_if_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_xcpt_ae_if_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_xcpt_ma_if_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_bp_debug_if_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_bp_xcpt_if_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_fflags_valid = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_load_at_rob_head = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_fence_dmem = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_is_rvc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_iq_type_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_iq_type_1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_iq_type_2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_iq_type_3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fu_code_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fu_code_1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fu_code_2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fu_code_3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fu_code_4 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fu_code_5 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fu_code_6 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fu_code_7 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fu_code_8 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fu_code_9 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_iw_issued = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_iw_issued_partial_agen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_iw_issued_partial_dgen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_iw_p1_speculative_child = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_iw_p2_speculative_child = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_iw_p1_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_iw_p2_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_iw_p3_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_dis_col_sel = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_is_sfb = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_is_fence = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_is_fencei = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_is_sfence = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_is_amo = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_is_eret = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_is_rocc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_is_mov = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_edge_inst = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_taken = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_imm_rename = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_ldst = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_wen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_ren1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_ren2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_ren3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_swap12 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_swap23 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_fromint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_toint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_fastpipe = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_fma = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_div = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_sqrt = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_wflags = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_vec = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_prs1_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_prs2_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_prs3_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_ppred_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_exception = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_mem_signed = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_uses_ldq = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_uses_stq = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_is_unique = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_flush_on_commit = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_frs3_en = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fcn_dw = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_val = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_bp_debug_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_mispredict = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_taken = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_exception = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_tsc_reg = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_debug = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_cease = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_wfi = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_dv = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_v = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_sd = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_mpv = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_gva = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_mbe = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_sbe = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_sd_rv32 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_tsr = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_tw = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_tvm = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_mxr = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_sum = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_mprv = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_spp = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_mpie = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_ube = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_spie = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_upie = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_mie = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_hie = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_sie = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_uie = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_mcontext = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_scontext = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_perf_tlbMiss = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_req_bits_signed = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_req_bits_dv = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_req_bits_phys = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_req_bits_no_resp = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_req_bits_no_alloc = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_req_bits_no_xcpt = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_s1_kill = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_s2_nack = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_s2_nack_cause_raw = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_s2_kill = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_s2_uncached = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_resp_bits_signed = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_resp_bits_dv = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_resp_bits_replay = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_resp_bits_has_data = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_replay_next = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_s2_xcpt_ma_ld = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_s2_xcpt_ma_st = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_s2_xcpt_pf_ld = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_s2_xcpt_pf_st = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_s2_xcpt_gf_ld = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_s2_xcpt_gf_st = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_s2_xcpt_ae_ld = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_s2_xcpt_ae_st = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_s2_gpa_is_pte = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_store_pending = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_perf_acquire = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_perf_release = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_perf_grant = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_perf_tlbMiss = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_perf_blocked = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_perf_canAcceptStoreThenLoad = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_perf_canAcceptStoreThenRMW = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_perf_canAcceptLoadThenLoad = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_perf_storeBufferEmptyAfterLoad = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_perf_storeBufferEmptyAfterStore = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_clock_enabled = 1'h0; // @[tracegen.scala:19:7] wire _rob_bsy_WIRE_0 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_1 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_2 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_3 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_4 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_5 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_6 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_7 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_8 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_9 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_10 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_11 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_12 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_13 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_14 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_15 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_16 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_17 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_18 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_19 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_20 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_21 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_22 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_23 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_24 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_25 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_26 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_27 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_28 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_29 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_30 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_31 = 1'h0; // @[tracegen.scala:33:33] wire _tracegen_uop_WIRE_is_rvc = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_iq_type_0 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_iq_type_1 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_iq_type_2 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_iq_type_3 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fu_code_0 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fu_code_1 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fu_code_2 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fu_code_3 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fu_code_4 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fu_code_5 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fu_code_6 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fu_code_7 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fu_code_8 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fu_code_9 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_iw_issued = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_iw_issued_partial_agen = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_iw_issued_partial_dgen = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_iw_p1_speculative_child = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_iw_p2_speculative_child = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_iw_p1_bypass_hint = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_iw_p2_bypass_hint = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_iw_p3_bypass_hint = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_dis_col_sel = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_is_sfb = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_is_fence = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_is_fencei = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_is_sfence = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_is_amo = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_is_eret = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_is_sys_pc2epc = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_is_rocc = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_is_mov = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_edge_inst = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_taken = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_imm_rename = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_ctrl_ldst = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_ctrl_wen = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_ctrl_ren1 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_ctrl_ren2 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_ctrl_ren3 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_ctrl_swap12 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_ctrl_swap23 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_ctrl_fromint = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_ctrl_toint = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_ctrl_fastpipe = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_ctrl_fma = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_ctrl_div = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_ctrl_sqrt = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_ctrl_wflags = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_ctrl_vec = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_prs1_busy = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_prs2_busy = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_prs3_busy = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_ppred_busy = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_exception = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_mem_signed = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_uses_ldq = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_uses_stq = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_is_unique = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_flush_on_commit = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_ldst_is_rs1 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_frs3_en = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fcn_dw = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_val = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_xcpt_pf_if = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_xcpt_ae_if = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_xcpt_ma_if = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_bp_debug_if = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_bp_xcpt_if = 1'h0; // @[tracegen.scala:55:45] wire tracegen_uop_is_rvc = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_iq_type_0 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_iq_type_1 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_iq_type_2 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_iq_type_3 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fu_code_0 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fu_code_1 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fu_code_2 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fu_code_3 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fu_code_4 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fu_code_5 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fu_code_6 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fu_code_7 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fu_code_8 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fu_code_9 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_iw_issued = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_iw_issued_partial_agen = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_iw_issued_partial_dgen = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_iw_p1_speculative_child = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_iw_p2_speculative_child = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_iw_p1_bypass_hint = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_iw_p2_bypass_hint = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_iw_p3_bypass_hint = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_dis_col_sel = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_is_sfb = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_is_fence = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_is_fencei = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_is_sfence = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_is_eret = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_is_rocc = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_is_mov = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_edge_inst = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_taken = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_imm_rename = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_ctrl_ldst = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_ctrl_wen = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_ctrl_ren1 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_ctrl_ren2 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_ctrl_ren3 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_ctrl_swap12 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_ctrl_swap23 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_ctrl_fromint = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_ctrl_toint = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_ctrl_fastpipe = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_ctrl_fma = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_ctrl_div = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_ctrl_sqrt = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_ctrl_wflags = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_ctrl_vec = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_prs1_busy = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_prs2_busy = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_prs3_busy = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_ppred_busy = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_exception = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_mem_signed = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_is_unique = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_flush_on_commit = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_frs3_en = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fcn_dw = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_val = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_bp_debug_if = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:55:30] wire [33:0] io_lsu_agen_0_bits_uop_debug_pc = 34'h0; // @[tracegen.scala:19:7] wire [33:0] io_lsu_dgen_0_bits_uop_debug_pc = 34'h0; // @[tracegen.scala:19:7] wire [33:0] io_lsu_dgen_1_bits_uop_debug_pc = 34'h0; // @[tracegen.scala:19:7] wire [33:0] io_lsu_dgen_2_bits_uop_debug_pc = 34'h0; // @[tracegen.scala:19:7] wire [33:0] io_lsu_dis_uops_0_bits_debug_pc = 34'h0; // @[tracegen.scala:19:7] wire [33:0] io_lsu_commit_uops_0_debug_pc_0 = 34'h0; // @[tracegen.scala:19:7] wire [33:0] io_lsu_brupdate_b2_uop_debug_pc = 34'h0; // @[tracegen.scala:19:7] wire [33:0] io_lsu_brupdate_b2_jalr_target = 34'h0; // @[tracegen.scala:19:7] wire [33:0] io_tracegen_resp_bits_addr = 34'h0; // @[tracegen.scala:19:7] wire [33:0] io_tracegen_s2_gpa = 34'h0; // @[tracegen.scala:19:7] wire [33:0] _tracegen_uop_WIRE_debug_pc = 34'h0; // @[tracegen.scala:55:45] wire [33:0] tracegen_uop_debug_pc = 34'h0; // @[tracegen.scala:55:30] wire [3:0] io_lsu_agen_0_bits_uop_br_mask = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_agen_0_bits_uop_br_type = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_agen_0_bits_uop_ftq_idx = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_agen_0_bits_uop_ppred = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_0_bits_uop_br_mask = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_0_bits_uop_br_type = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_0_bits_uop_ftq_idx = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_0_bits_uop_ppred = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_1_bits_uop_br_mask = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_1_bits_uop_br_type = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_1_bits_uop_ftq_idx = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_1_bits_uop_ldq_idx = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_1_bits_uop_stq_idx = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_1_bits_uop_ppred = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_2_bits_uop_br_mask = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_2_bits_uop_br_type = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_2_bits_uop_ftq_idx = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_2_bits_uop_ldq_idx = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_2_bits_uop_stq_idx = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_2_bits_uop_ppred = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dis_uops_0_bits_br_mask = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dis_uops_0_bits_br_type = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dis_uops_0_bits_ftq_idx = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dis_uops_0_bits_ppred = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_commit_uops_0_br_mask_0 = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_commit_uops_0_br_type_0 = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_commit_uops_0_ftq_idx_0 = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_commit_uops_0_ppred_0 = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_brupdate_b1_resolve_mask = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_brupdate_b1_mispredict_mask = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_brupdate_b2_uop_br_mask = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_brupdate_b2_uop_br_type = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_brupdate_b2_uop_ftq_idx = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_brupdate_b2_uop_ldq_idx = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_brupdate_b2_uop_stq_idx = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_brupdate_b2_uop_ppred = 4'h0; // @[tracegen.scala:19:7] wire [3:0] _tracegen_uop_WIRE_br_mask = 4'h0; // @[tracegen.scala:55:45] wire [3:0] _tracegen_uop_WIRE_br_type = 4'h0; // @[tracegen.scala:55:45] wire [3:0] _tracegen_uop_WIRE_ftq_idx = 4'h0; // @[tracegen.scala:55:45] wire [3:0] _tracegen_uop_WIRE_ldq_idx = 4'h0; // @[tracegen.scala:55:45] wire [3:0] _tracegen_uop_WIRE_stq_idx = 4'h0; // @[tracegen.scala:55:45] wire [3:0] _tracegen_uop_WIRE_ppred = 4'h0; // @[tracegen.scala:55:45] wire [3:0] tracegen_uop_br_mask = 4'h0; // @[tracegen.scala:55:30] wire [3:0] tracegen_uop_br_type = 4'h0; // @[tracegen.scala:55:30] wire [3:0] tracegen_uop_ftq_idx = 4'h0; // @[tracegen.scala:55:30] wire [3:0] tracegen_uop_ppred = 4'h0; // @[tracegen.scala:55:30] wire [3:0] _io_lsu_brupdate_b1_WIRE_resolve_mask = 4'h0; // @[tracegen.scala:151:39] wire [3:0] _io_lsu_brupdate_b1_WIRE_mispredict_mask = 4'h0; // @[tracegen.scala:151:39] wire [1:0] io_lsu_agen_0_bits_uop_br_tag = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_agen_0_bits_uop_op1_sel = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_agen_0_bits_uop_fp_ctrl_typeTagIn = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_agen_0_bits_uop_fp_ctrl_typeTagOut = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_agen_0_bits_uop_rxq_idx = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_agen_0_bits_uop_dst_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_agen_0_bits_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_agen_0_bits_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_agen_0_bits_uop_fp_typ = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_0_bits_uop_br_tag = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_0_bits_uop_op1_sel = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_0_bits_uop_fp_ctrl_typeTagIn = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_0_bits_uop_fp_ctrl_typeTagOut = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_0_bits_uop_rxq_idx = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_0_bits_uop_dst_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_0_bits_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_0_bits_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_0_bits_uop_fp_typ = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_1_bits_uop_br_tag = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_1_bits_uop_op1_sel = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_1_bits_uop_fp_ctrl_typeTagIn = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_1_bits_uop_fp_ctrl_typeTagOut = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_1_bits_uop_rxq_idx = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_1_bits_uop_mem_size = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_1_bits_uop_dst_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_1_bits_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_1_bits_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_1_bits_uop_fp_typ = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_2_bits_uop_br_tag = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_2_bits_uop_op1_sel = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_2_bits_uop_fp_ctrl_typeTagIn = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_2_bits_uop_fp_ctrl_typeTagOut = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_2_bits_uop_rxq_idx = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_2_bits_uop_mem_size = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_2_bits_uop_dst_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_2_bits_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_2_bits_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_2_bits_uop_fp_typ = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dis_uops_0_bits_br_tag = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dis_uops_0_bits_op1_sel = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dis_uops_0_bits_fp_ctrl_typeTagIn = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dis_uops_0_bits_fp_ctrl_typeTagOut = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dis_uops_0_bits_rxq_idx = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dis_uops_0_bits_dst_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dis_uops_0_bits_lrs1_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dis_uops_0_bits_lrs2_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dis_uops_0_bits_fp_typ = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_commit_uops_0_br_tag_0 = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_commit_uops_0_op1_sel_0 = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_commit_uops_0_fp_ctrl_typeTagIn_0 = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_commit_uops_0_fp_ctrl_typeTagOut_0 = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_commit_uops_0_rxq_idx_0 = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_commit_uops_0_dst_rtype_0 = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_commit_uops_0_lrs1_rtype_0 = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_commit_uops_0_lrs2_rtype_0 = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_commit_uops_0_fp_typ_0 = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_brupdate_b2_uop_br_tag = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_brupdate_b2_uop_op1_sel = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_brupdate_b2_uop_fp_ctrl_typeTagIn = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_brupdate_b2_uop_fp_ctrl_typeTagOut = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_brupdate_b2_uop_rxq_idx = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_brupdate_b2_uop_mem_size = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_brupdate_b2_uop_dst_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_brupdate_b2_uop_fp_typ = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_brupdate_b2_pc_sel = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_status_dprv = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_status_prv = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_status_sxl = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_status_uxl = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_status_xs = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_status_fs = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_status_mpp = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_status_vs = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_tracegen_resp_bits_dprv = 2'h0; // @[tracegen.scala:19:7] wire [1:0] _tracegen_uop_WIRE_br_tag = 2'h0; // @[tracegen.scala:55:45] wire [1:0] _tracegen_uop_WIRE_op1_sel = 2'h0; // @[tracegen.scala:55:45] wire [1:0] _tracegen_uop_WIRE_fp_ctrl_typeTagIn = 2'h0; // @[tracegen.scala:55:45] wire [1:0] _tracegen_uop_WIRE_fp_ctrl_typeTagOut = 2'h0; // @[tracegen.scala:55:45] wire [1:0] _tracegen_uop_WIRE_rxq_idx = 2'h0; // @[tracegen.scala:55:45] wire [1:0] _tracegen_uop_WIRE_mem_size = 2'h0; // @[tracegen.scala:55:45] wire [1:0] _tracegen_uop_WIRE_dst_rtype = 2'h0; // @[tracegen.scala:55:45] wire [1:0] _tracegen_uop_WIRE_lrs1_rtype = 2'h0; // @[tracegen.scala:55:45] wire [1:0] _tracegen_uop_WIRE_lrs2_rtype = 2'h0; // @[tracegen.scala:55:45] wire [1:0] _tracegen_uop_WIRE_fp_typ = 2'h0; // @[tracegen.scala:55:45] wire [1:0] tracegen_uop_br_tag = 2'h0; // @[tracegen.scala:55:30] wire [1:0] tracegen_uop_op1_sel = 2'h0; // @[tracegen.scala:55:30] wire [1:0] tracegen_uop_fp_ctrl_typeTagIn = 2'h0; // @[tracegen.scala:55:30] wire [1:0] tracegen_uop_fp_ctrl_typeTagOut = 2'h0; // @[tracegen.scala:55:30] wire [1:0] tracegen_uop_rxq_idx = 2'h0; // @[tracegen.scala:55:30] wire [1:0] tracegen_uop_dst_rtype = 2'h0; // @[tracegen.scala:55:30] wire [1:0] tracegen_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:55:30] wire [1:0] tracegen_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:55:30] wire [1:0] tracegen_uop_fp_typ = 2'h0; // @[tracegen.scala:55:30] wire [5:0] io_lsu_agen_0_bits_uop_pc_lob = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_agen_0_bits_uop_pdst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_agen_0_bits_uop_prs1 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_agen_0_bits_uop_prs2 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_agen_0_bits_uop_prs3 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_agen_0_bits_uop_stale_pdst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_agen_0_bits_uop_ldst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_agen_0_bits_uop_lrs1 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_agen_0_bits_uop_lrs2 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_agen_0_bits_uop_lrs3 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_0_bits_uop_pc_lob = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_0_bits_uop_pdst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_0_bits_uop_prs1 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_0_bits_uop_prs2 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_0_bits_uop_prs3 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_0_bits_uop_stale_pdst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_0_bits_uop_ldst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_0_bits_uop_lrs1 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_0_bits_uop_lrs2 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_0_bits_uop_lrs3 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_1_bits_uop_pc_lob = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_1_bits_uop_pdst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_1_bits_uop_prs1 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_1_bits_uop_prs2 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_1_bits_uop_prs3 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_1_bits_uop_stale_pdst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_1_bits_uop_ldst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_1_bits_uop_lrs1 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_1_bits_uop_lrs2 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_1_bits_uop_lrs3 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_2_bits_uop_pc_lob = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_2_bits_uop_pdst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_2_bits_uop_prs1 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_2_bits_uop_prs2 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_2_bits_uop_prs3 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_2_bits_uop_stale_pdst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_2_bits_uop_ldst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_2_bits_uop_lrs1 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_2_bits_uop_lrs2 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_2_bits_uop_lrs3 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dis_uops_0_bits_pc_lob = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dis_uops_0_bits_pdst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dis_uops_0_bits_prs1 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dis_uops_0_bits_prs2 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dis_uops_0_bits_prs3 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dis_uops_0_bits_stale_pdst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dis_uops_0_bits_ldst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dis_uops_0_bits_lrs1 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dis_uops_0_bits_lrs2 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dis_uops_0_bits_lrs3 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_commit_uops_0_pc_lob_0 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_commit_uops_0_pdst_0 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_commit_uops_0_prs1_0 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_commit_uops_0_prs2_0 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_commit_uops_0_prs3_0 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_commit_uops_0_stale_pdst_0 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_commit_uops_0_ldst_0 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_commit_uops_0_lrs1_0 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_commit_uops_0_lrs2_0 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_commit_uops_0_lrs3_0 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_brupdate_b2_uop_pc_lob = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_brupdate_b2_uop_pdst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_brupdate_b2_uop_prs1 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_brupdate_b2_uop_prs2 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_brupdate_b2_uop_prs3 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_brupdate_b2_uop_stale_pdst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_brupdate_b2_uop_ldst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_brupdate_b2_uop_lrs1 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_brupdate_b2_uop_lrs2 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_brupdate_b2_uop_lrs3 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] _tracegen_uop_WIRE_pc_lob = 6'h0; // @[tracegen.scala:55:45] wire [5:0] _tracegen_uop_WIRE_pdst = 6'h0; // @[tracegen.scala:55:45] wire [5:0] _tracegen_uop_WIRE_prs1 = 6'h0; // @[tracegen.scala:55:45] wire [5:0] _tracegen_uop_WIRE_prs2 = 6'h0; // @[tracegen.scala:55:45] wire [5:0] _tracegen_uop_WIRE_prs3 = 6'h0; // @[tracegen.scala:55:45] wire [5:0] _tracegen_uop_WIRE_stale_pdst = 6'h0; // @[tracegen.scala:55:45] wire [5:0] _tracegen_uop_WIRE_ldst = 6'h0; // @[tracegen.scala:55:45] wire [5:0] _tracegen_uop_WIRE_lrs1 = 6'h0; // @[tracegen.scala:55:45] wire [5:0] _tracegen_uop_WIRE_lrs2 = 6'h0; // @[tracegen.scala:55:45] wire [5:0] _tracegen_uop_WIRE_lrs3 = 6'h0; // @[tracegen.scala:55:45] wire [5:0] tracegen_uop_pc_lob = 6'h0; // @[tracegen.scala:55:30] wire [5:0] tracegen_uop_pdst = 6'h0; // @[tracegen.scala:55:30] wire [5:0] tracegen_uop_prs1 = 6'h0; // @[tracegen.scala:55:30] wire [5:0] tracegen_uop_prs2 = 6'h0; // @[tracegen.scala:55:30] wire [5:0] tracegen_uop_prs3 = 6'h0; // @[tracegen.scala:55:30] wire [5:0] tracegen_uop_stale_pdst = 6'h0; // @[tracegen.scala:55:30] wire [5:0] tracegen_uop_ldst = 6'h0; // @[tracegen.scala:55:30] wire [5:0] tracegen_uop_lrs1 = 6'h0; // @[tracegen.scala:55:30] wire [5:0] tracegen_uop_lrs2 = 6'h0; // @[tracegen.scala:55:30] wire [5:0] tracegen_uop_lrs3 = 6'h0; // @[tracegen.scala:55:30] wire [2:0] io_lsu_agen_0_bits_uop_imm_sel = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_agen_0_bits_uop_op2_sel = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_agen_0_bits_uop_csr_cmd = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_agen_0_bits_uop_fp_rm = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_agen_0_bits_uop_debug_fsrc = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_agen_0_bits_uop_debug_tsrc = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_0_bits_uop_imm_sel = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_0_bits_uop_op2_sel = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_0_bits_uop_csr_cmd = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_0_bits_uop_fp_rm = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_0_bits_uop_debug_fsrc = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_0_bits_uop_debug_tsrc = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_1_bits_uop_imm_sel = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_1_bits_uop_op2_sel = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_1_bits_uop_csr_cmd = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_1_bits_uop_fp_rm = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_1_bits_uop_debug_fsrc = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_1_bits_uop_debug_tsrc = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_2_bits_uop_imm_sel = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_2_bits_uop_op2_sel = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_2_bits_uop_csr_cmd = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_2_bits_uop_fp_rm = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_2_bits_uop_debug_fsrc = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_2_bits_uop_debug_tsrc = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dis_uops_0_bits_imm_sel = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dis_uops_0_bits_op2_sel = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dis_uops_0_bits_csr_cmd = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dis_uops_0_bits_fp_rm = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dis_uops_0_bits_debug_fsrc = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dis_uops_0_bits_debug_tsrc = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_commit_uops_0_imm_sel_0 = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_commit_uops_0_op2_sel_0 = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_commit_uops_0_csr_cmd_0 = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_commit_uops_0_fp_rm_0 = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_commit_uops_0_debug_fsrc_0 = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_commit_uops_0_debug_tsrc_0 = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_brupdate_b2_uop_imm_sel = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_brupdate_b2_uop_op2_sel = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_brupdate_b2_uop_csr_cmd = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_brupdate_b2_uop_fp_rm = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_brupdate_b2_uop_debug_fsrc = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_brupdate_b2_uop_debug_tsrc = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_brupdate_b2_cfi_type = 3'h0; // @[tracegen.scala:19:7] wire [2:0] _tracegen_uop_WIRE_imm_sel = 3'h0; // @[tracegen.scala:55:45] wire [2:0] _tracegen_uop_WIRE_op2_sel = 3'h0; // @[tracegen.scala:55:45] wire [2:0] _tracegen_uop_WIRE_csr_cmd = 3'h0; // @[tracegen.scala:55:45] wire [2:0] _tracegen_uop_WIRE_fp_rm = 3'h0; // @[tracegen.scala:55:45] wire [2:0] _tracegen_uop_WIRE_debug_fsrc = 3'h0; // @[tracegen.scala:55:45] wire [2:0] _tracegen_uop_WIRE_debug_tsrc = 3'h0; // @[tracegen.scala:55:45] wire [2:0] tracegen_uop_imm_sel = 3'h0; // @[tracegen.scala:55:30] wire [2:0] tracegen_uop_op2_sel = 3'h0; // @[tracegen.scala:55:30] wire [2:0] tracegen_uop_csr_cmd = 3'h0; // @[tracegen.scala:55:30] wire [2:0] tracegen_uop_fp_rm = 3'h0; // @[tracegen.scala:55:30] wire [2:0] tracegen_uop_debug_fsrc = 3'h0; // @[tracegen.scala:55:30] wire [2:0] tracegen_uop_debug_tsrc = 3'h0; // @[tracegen.scala:55:30] wire [4:0] io_lsu_agen_0_bits_uop_pimm = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_agen_0_bits_uop_fcn_op = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dgen_0_bits_uop_pimm = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dgen_0_bits_uop_fcn_op = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dgen_1_bits_uop_pimm = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dgen_1_bits_uop_rob_idx = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dgen_1_bits_uop_mem_cmd = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dgen_1_bits_uop_fcn_op = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dgen_2_bits_uop_pimm = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dgen_2_bits_uop_rob_idx = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dgen_2_bits_uop_mem_cmd = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dgen_2_bits_uop_fcn_op = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_iresp_0_bits_fflags_bits = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_fresp_0_bits_fflags_bits = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dis_uops_0_bits_pimm = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dis_uops_0_bits_fcn_op = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_commit_uops_0_pimm_0 = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_commit_uops_0_fcn_op_0 = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_commit_fflags_bits = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_brupdate_b2_uop_pimm = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_brupdate_b2_uop_rob_idx = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_brupdate_b2_uop_mem_cmd = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_brupdate_b2_uop_fcn_op = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_tracegen_resp_bits_cmd = 5'h0; // @[tracegen.scala:19:7] wire [4:0] _tracegen_uop_WIRE_pimm = 5'h0; // @[tracegen.scala:55:45] wire [4:0] _tracegen_uop_WIRE_rob_idx = 5'h0; // @[tracegen.scala:55:45] wire [4:0] _tracegen_uop_WIRE_mem_cmd = 5'h0; // @[tracegen.scala:55:45] wire [4:0] _tracegen_uop_WIRE_fcn_op = 5'h0; // @[tracegen.scala:55:45] wire [4:0] tracegen_uop_pimm = 5'h0; // @[tracegen.scala:55:30] wire [4:0] tracegen_uop_fcn_op = 5'h0; // @[tracegen.scala:55:30] wire [19:0] io_lsu_agen_0_bits_uop_imm_packed = 20'h0; // @[tracegen.scala:19:7] wire [19:0] io_lsu_dgen_0_bits_uop_imm_packed = 20'h0; // @[tracegen.scala:19:7] wire [19:0] io_lsu_dgen_1_bits_uop_imm_packed = 20'h0; // @[tracegen.scala:19:7] wire [19:0] io_lsu_dgen_2_bits_uop_imm_packed = 20'h0; // @[tracegen.scala:19:7] wire [19:0] io_lsu_dis_uops_0_bits_imm_packed = 20'h0; // @[tracegen.scala:19:7] wire [19:0] io_lsu_commit_uops_0_imm_packed_0 = 20'h0; // @[tracegen.scala:19:7] wire [19:0] io_lsu_brupdate_b2_uop_imm_packed = 20'h0; // @[tracegen.scala:19:7] wire [19:0] _tracegen_uop_WIRE_imm_packed = 20'h0; // @[tracegen.scala:55:45] wire [19:0] tracegen_uop_imm_packed = 20'h0; // @[tracegen.scala:55:30] wire [63:0] io_lsu_agen_0_bits_uop_exc_cause = 64'h0; // @[tracegen.scala:19:7] wire [63:0] io_lsu_dgen_0_bits_uop_exc_cause = 64'h0; // @[tracegen.scala:19:7] wire [63:0] io_lsu_dgen_1_bits_uop_exc_cause = 64'h0; // @[tracegen.scala:19:7] wire [63:0] io_lsu_dgen_1_bits_data = 64'h0; // @[tracegen.scala:19:7] wire [63:0] io_lsu_dgen_2_bits_uop_exc_cause = 64'h0; // @[tracegen.scala:19:7] wire [63:0] io_lsu_dgen_2_bits_data = 64'h0; // @[tracegen.scala:19:7] wire [63:0] io_lsu_dis_uops_0_bits_exc_cause = 64'h0; // @[tracegen.scala:19:7] wire [63:0] io_lsu_commit_uops_0_exc_cause_0 = 64'h0; // @[tracegen.scala:19:7] wire [63:0] io_lsu_commit_debug_wdata_0 = 64'h0; // @[tracegen.scala:19:7] wire [63:0] io_lsu_brupdate_b2_uop_exc_cause = 64'h0; // @[tracegen.scala:19:7] wire [63:0] io_tracegen_resp_bits_data_word_bypass = 64'h0; // @[tracegen.scala:19:7] wire [63:0] io_tracegen_resp_bits_data_raw = 64'h0; // @[tracegen.scala:19:7] wire [63:0] io_tracegen_resp_bits_store_data = 64'h0; // @[tracegen.scala:19:7] wire [63:0] _tracegen_uop_WIRE_exc_cause = 64'h0; // @[tracegen.scala:55:45] wire [63:0] tracegen_uop_exc_cause = 64'h0; // @[tracegen.scala:55:30] wire [1:0] io_lsu_agen_0_bits_uop_mem_size = 2'h3; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_0_bits_uop_mem_size = 2'h3; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dis_uops_0_bits_mem_size = 2'h3; // @[tracegen.scala:19:7] wire [1:0] io_lsu_commit_uops_0_mem_size_0 = 2'h3; // @[tracegen.scala:19:7] wire [1:0] io_tracegen_req_bits_size = 2'h3; // @[tracegen.scala:19:7] wire [1:0] io_tracegen_req_bits_dprv = 2'h3; // @[tracegen.scala:19:7] wire [1:0] tracegen_uop_mem_size = 2'h3; // @[tracegen.scala:55:30] wire [7:0] io_tracegen_req_bits_mask = 8'hFF; // @[tracegen.scala:19:7] wire [7:0] io_tracegen_s1_data_mask = 8'hFF; // @[tracegen.scala:19:7] wire [32:0] io_lsu_sfence_bits_addr = 33'h0; // @[tracegen.scala:19:7] wire [20:0] io_lsu_brupdate_b2_target_offset = 21'h0; // @[tracegen.scala:19:7] wire [22:0] io_lsu_status_zero2 = 23'h0; // @[tracegen.scala:19:7] wire [7:0] io_lsu_status_zero1 = 8'h0; // @[tracegen.scala:19:7] wire [7:0] io_tracegen_resp_bits_mask = 8'h0; // @[tracegen.scala:19:7] wire io_tracegen_keep_clock_enabled = 1'h1; // @[tracegen.scala:19:7] wire _rob_respd_T_1 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_2 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_3 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_4 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_5 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_6 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_7 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_8 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_9 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_10 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_11 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_12 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_13 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_14 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_15 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_16 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_17 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_18 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_19 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_20 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_21 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_22 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_23 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_24 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_25 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_26 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_27 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_28 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_29 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_30 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_31 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_32 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_WIRE_0 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_1 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_2 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_3 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_4 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_5 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_6 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_7 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_8 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_9 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_10 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_11 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_12 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_13 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_14 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_15 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_16 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_17 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_18 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_19 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_20 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_21 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_22 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_23 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_24 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_25 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_26 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_27 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_28 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_29 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_30 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_31 = 1'h1; // @[tracegen.scala:31:34] wire [31:0] _rob_respd_T = 32'hFFFFFFFF; // @[tracegen.scala:31:36] wire [1:0] io_tracegen_resp_bits_size_0 = io_lsu_iresp_0_bits_uop_mem_size_0; // @[tracegen.scala:19:7] wire [63:0] io_tracegen_resp_bits_data_0 = io_lsu_iresp_0_bits_data_0; // @[tracegen.scala:19:7] wire _io_lsu_dis_uops_0_valid_T; // @[Decoupled.scala:51:35] wire [31:0] tracegen_uop_debug_inst; // @[tracegen.scala:55:30] wire tracegen_uop_is_amo; // @[tracegen.scala:55:30] wire [4:0] tracegen_uop_rob_idx; // @[tracegen.scala:55:30] wire [3:0] tracegen_uop_ldq_idx; // @[tracegen.scala:55:30] wire [3:0] tracegen_uop_stq_idx; // @[tracegen.scala:55:30] wire [4:0] tracegen_uop_mem_cmd; // @[tracegen.scala:55:30] wire tracegen_uop_uses_ldq; // @[tracegen.scala:55:30] wire tracegen_uop_uses_stq; // @[tracegen.scala:55:30] assign tracegen_uop_ldq_idx = io_lsu_dis_ldq_idx_0_0; // @[tracegen.scala:19:7, :55:30] assign tracegen_uop_stq_idx = io_lsu_dis_stq_idx_0_0; // @[tracegen.scala:19:7, :55:30] wire _io_lsu_commit_valids_0_T_3; // @[tracegen.scala:92:75] wire _io_tracegen_req_ready_T_86; // @[tracegen.scala:51:63] assign tracegen_uop_mem_cmd = io_tracegen_req_bits_cmd_0; // @[tracegen.scala:19:7, :55:30] wire _io_tracegen_ordered_T; // @[tracegen.scala:162:40] wire [31:0] io_lsu_agen_0_bits_uop_debug_inst_0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_is_amo_0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_agen_0_bits_uop_rob_idx_0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_agen_0_bits_uop_ldq_idx_0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_agen_0_bits_uop_stq_idx_0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_agen_0_bits_uop_mem_cmd_0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_uses_ldq_0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_uses_stq_0; // @[tracegen.scala:19:7] wire [63:0] io_lsu_agen_0_bits_data_0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_valid_0; // @[tracegen.scala:19:7] wire [31:0] io_lsu_dgen_0_bits_uop_debug_inst_0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_is_amo_0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dgen_0_bits_uop_rob_idx_0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_0_bits_uop_ldq_idx_0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_0_bits_uop_stq_idx_0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dgen_0_bits_uop_mem_cmd_0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_uses_ldq_0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_uses_stq_0; // @[tracegen.scala:19:7] wire [63:0] io_lsu_dgen_0_bits_data_0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_valid_0; // @[tracegen.scala:19:7] wire [31:0] io_lsu_dis_uops_0_bits_debug_inst_0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_is_amo_0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dis_uops_0_bits_rob_idx_0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dis_uops_0_bits_ldq_idx_0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dis_uops_0_bits_stq_idx_0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dis_uops_0_bits_mem_cmd_0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_uses_ldq_0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_uses_stq_0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_valid_0; // @[tracegen.scala:19:7] wire io_lsu_commit_valids_0_0; // @[tracegen.scala:19:7] wire [31:0] io_lsu_commit_uops_0_debug_inst_0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_is_amo_0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_commit_uops_0_rob_idx_0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_commit_uops_0_ldq_idx_0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_commit_uops_0_stq_idx_0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_commit_uops_0_mem_cmd_0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_uses_ldq_0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_uses_stq_0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_rob_pnr_idx_0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_rob_head_idx_0; // @[tracegen.scala:19:7] wire io_tracegen_req_ready_0; // @[tracegen.scala:19:7] wire [5:0] io_tracegen_resp_bits_tag_0; // @[tracegen.scala:19:7] wire io_tracegen_resp_valid_0; // @[tracegen.scala:19:7] wire io_tracegen_ordered_0; // @[tracegen.scala:19:7] reg [33:0] rob_0_addr; // @[tracegen.scala:30:16] reg [5:0] rob_0_tag; // @[tracegen.scala:30:16] reg [4:0] rob_0_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_0_data; // @[tracegen.scala:30:16] reg [33:0] rob_1_addr; // @[tracegen.scala:30:16] reg [5:0] rob_1_tag; // @[tracegen.scala:30:16] reg [4:0] rob_1_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_1_data; // @[tracegen.scala:30:16] reg [33:0] rob_2_addr; // @[tracegen.scala:30:16] reg [5:0] rob_2_tag; // @[tracegen.scala:30:16] reg [4:0] rob_2_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_2_data; // @[tracegen.scala:30:16] reg [33:0] rob_3_addr; // @[tracegen.scala:30:16] reg [5:0] rob_3_tag; // @[tracegen.scala:30:16] reg [4:0] rob_3_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_3_data; // @[tracegen.scala:30:16] reg [33:0] rob_4_addr; // @[tracegen.scala:30:16] reg [5:0] rob_4_tag; // @[tracegen.scala:30:16] reg [4:0] rob_4_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_4_data; // @[tracegen.scala:30:16] reg [33:0] rob_5_addr; // @[tracegen.scala:30:16] reg [5:0] rob_5_tag; // @[tracegen.scala:30:16] reg [4:0] rob_5_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_5_data; // @[tracegen.scala:30:16] reg [33:0] rob_6_addr; // @[tracegen.scala:30:16] reg [5:0] rob_6_tag; // @[tracegen.scala:30:16] reg [4:0] rob_6_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_6_data; // @[tracegen.scala:30:16] reg [33:0] rob_7_addr; // @[tracegen.scala:30:16] reg [5:0] rob_7_tag; // @[tracegen.scala:30:16] reg [4:0] rob_7_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_7_data; // @[tracegen.scala:30:16] reg [33:0] rob_8_addr; // @[tracegen.scala:30:16] reg [5:0] rob_8_tag; // @[tracegen.scala:30:16] reg [4:0] rob_8_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_8_data; // @[tracegen.scala:30:16] reg [33:0] rob_9_addr; // @[tracegen.scala:30:16] reg [5:0] rob_9_tag; // @[tracegen.scala:30:16] reg [4:0] rob_9_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_9_data; // @[tracegen.scala:30:16] reg [33:0] rob_10_addr; // @[tracegen.scala:30:16] reg [5:0] rob_10_tag; // @[tracegen.scala:30:16] reg [4:0] rob_10_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_10_data; // @[tracegen.scala:30:16] reg [33:0] rob_11_addr; // @[tracegen.scala:30:16] reg [5:0] rob_11_tag; // @[tracegen.scala:30:16] reg [4:0] rob_11_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_11_data; // @[tracegen.scala:30:16] reg [33:0] rob_12_addr; // @[tracegen.scala:30:16] reg [5:0] rob_12_tag; // @[tracegen.scala:30:16] reg [4:0] rob_12_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_12_data; // @[tracegen.scala:30:16] reg [33:0] rob_13_addr; // @[tracegen.scala:30:16] reg [5:0] rob_13_tag; // @[tracegen.scala:30:16] reg [4:0] rob_13_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_13_data; // @[tracegen.scala:30:16] reg [33:0] rob_14_addr; // @[tracegen.scala:30:16] reg [5:0] rob_14_tag; // @[tracegen.scala:30:16] reg [4:0] rob_14_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_14_data; // @[tracegen.scala:30:16] reg [33:0] rob_15_addr; // @[tracegen.scala:30:16] reg [5:0] rob_15_tag; // @[tracegen.scala:30:16] reg [4:0] rob_15_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_15_data; // @[tracegen.scala:30:16] reg [33:0] rob_16_addr; // @[tracegen.scala:30:16] reg [5:0] rob_16_tag; // @[tracegen.scala:30:16] reg [4:0] rob_16_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_16_data; // @[tracegen.scala:30:16] reg [33:0] rob_17_addr; // @[tracegen.scala:30:16] reg [5:0] rob_17_tag; // @[tracegen.scala:30:16] reg [4:0] rob_17_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_17_data; // @[tracegen.scala:30:16] reg [33:0] rob_18_addr; // @[tracegen.scala:30:16] reg [5:0] rob_18_tag; // @[tracegen.scala:30:16] reg [4:0] rob_18_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_18_data; // @[tracegen.scala:30:16] reg [33:0] rob_19_addr; // @[tracegen.scala:30:16] reg [5:0] rob_19_tag; // @[tracegen.scala:30:16] reg [4:0] rob_19_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_19_data; // @[tracegen.scala:30:16] reg [33:0] rob_20_addr; // @[tracegen.scala:30:16] reg [5:0] rob_20_tag; // @[tracegen.scala:30:16] reg [4:0] rob_20_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_20_data; // @[tracegen.scala:30:16] reg [33:0] rob_21_addr; // @[tracegen.scala:30:16] reg [5:0] rob_21_tag; // @[tracegen.scala:30:16] reg [4:0] rob_21_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_21_data; // @[tracegen.scala:30:16] reg [33:0] rob_22_addr; // @[tracegen.scala:30:16] reg [5:0] rob_22_tag; // @[tracegen.scala:30:16] reg [4:0] rob_22_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_22_data; // @[tracegen.scala:30:16] reg [33:0] rob_23_addr; // @[tracegen.scala:30:16] reg [5:0] rob_23_tag; // @[tracegen.scala:30:16] reg [4:0] rob_23_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_23_data; // @[tracegen.scala:30:16] reg [33:0] rob_24_addr; // @[tracegen.scala:30:16] reg [5:0] rob_24_tag; // @[tracegen.scala:30:16] reg [4:0] rob_24_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_24_data; // @[tracegen.scala:30:16] reg [33:0] rob_25_addr; // @[tracegen.scala:30:16] reg [5:0] rob_25_tag; // @[tracegen.scala:30:16] reg [4:0] rob_25_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_25_data; // @[tracegen.scala:30:16] reg [33:0] rob_26_addr; // @[tracegen.scala:30:16] reg [5:0] rob_26_tag; // @[tracegen.scala:30:16] reg [4:0] rob_26_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_26_data; // @[tracegen.scala:30:16] reg [33:0] rob_27_addr; // @[tracegen.scala:30:16] reg [5:0] rob_27_tag; // @[tracegen.scala:30:16] reg [4:0] rob_27_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_27_data; // @[tracegen.scala:30:16] reg [33:0] rob_28_addr; // @[tracegen.scala:30:16] reg [5:0] rob_28_tag; // @[tracegen.scala:30:16] reg [4:0] rob_28_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_28_data; // @[tracegen.scala:30:16] reg [33:0] rob_29_addr; // @[tracegen.scala:30:16] reg [5:0] rob_29_tag; // @[tracegen.scala:30:16] reg [4:0] rob_29_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_29_data; // @[tracegen.scala:30:16] reg [33:0] rob_30_addr; // @[tracegen.scala:30:16] reg [5:0] rob_30_tag; // @[tracegen.scala:30:16] reg [4:0] rob_30_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_30_data; // @[tracegen.scala:30:16] reg [33:0] rob_31_addr; // @[tracegen.scala:30:16] reg [5:0] rob_31_tag; // @[tracegen.scala:30:16] reg [4:0] rob_31_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_31_data; // @[tracegen.scala:30:16] reg rob_respd_0; // @[tracegen.scala:31:26] reg rob_respd_1; // @[tracegen.scala:31:26] reg rob_respd_2; // @[tracegen.scala:31:26] reg rob_respd_3; // @[tracegen.scala:31:26] reg rob_respd_4; // @[tracegen.scala:31:26] reg rob_respd_5; // @[tracegen.scala:31:26] reg rob_respd_6; // @[tracegen.scala:31:26] reg rob_respd_7; // @[tracegen.scala:31:26] reg rob_respd_8; // @[tracegen.scala:31:26] reg rob_respd_9; // @[tracegen.scala:31:26] reg rob_respd_10; // @[tracegen.scala:31:26] reg rob_respd_11; // @[tracegen.scala:31:26] reg rob_respd_12; // @[tracegen.scala:31:26] reg rob_respd_13; // @[tracegen.scala:31:26] reg rob_respd_14; // @[tracegen.scala:31:26] reg rob_respd_15; // @[tracegen.scala:31:26] reg rob_respd_16; // @[tracegen.scala:31:26] reg rob_respd_17; // @[tracegen.scala:31:26] reg rob_respd_18; // @[tracegen.scala:31:26] reg rob_respd_19; // @[tracegen.scala:31:26] reg rob_respd_20; // @[tracegen.scala:31:26] reg rob_respd_21; // @[tracegen.scala:31:26] reg rob_respd_22; // @[tracegen.scala:31:26] reg rob_respd_23; // @[tracegen.scala:31:26] reg rob_respd_24; // @[tracegen.scala:31:26] reg rob_respd_25; // @[tracegen.scala:31:26] reg rob_respd_26; // @[tracegen.scala:31:26] reg rob_respd_27; // @[tracegen.scala:31:26] reg rob_respd_28; // @[tracegen.scala:31:26] reg rob_respd_29; // @[tracegen.scala:31:26] reg rob_respd_30; // @[tracegen.scala:31:26] reg rob_respd_31; // @[tracegen.scala:31:26] reg [31:0] rob_uop_0_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_0_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_0_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_0_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_0_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_0_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_0_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_0_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_1_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_1_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_1_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_1_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_1_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_1_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_1_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_1_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_2_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_2_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_2_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_2_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_2_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_2_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_2_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_2_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_3_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_3_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_3_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_3_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_3_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_3_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_3_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_3_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_4_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_4_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_4_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_4_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_4_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_4_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_4_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_4_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_5_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_5_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_5_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_5_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_5_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_5_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_5_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_5_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_6_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_6_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_6_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_6_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_6_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_6_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_6_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_6_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_7_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_7_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_7_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_7_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_7_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_7_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_7_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_7_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_8_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_8_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_8_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_8_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_8_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_8_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_8_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_8_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_9_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_9_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_9_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_9_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_9_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_9_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_9_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_9_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_10_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_10_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_10_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_10_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_10_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_10_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_10_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_10_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_11_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_11_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_11_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_11_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_11_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_11_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_11_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_11_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_12_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_12_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_12_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_12_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_12_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_12_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_12_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_12_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_13_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_13_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_13_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_13_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_13_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_13_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_13_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_13_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_14_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_14_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_14_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_14_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_14_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_14_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_14_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_14_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_15_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_15_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_15_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_15_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_15_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_15_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_15_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_15_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_16_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_16_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_16_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_16_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_16_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_16_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_16_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_16_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_17_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_17_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_17_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_17_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_17_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_17_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_17_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_17_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_18_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_18_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_18_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_18_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_18_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_18_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_18_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_18_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_19_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_19_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_19_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_19_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_19_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_19_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_19_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_19_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_20_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_20_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_20_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_20_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_20_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_20_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_20_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_20_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_21_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_21_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_21_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_21_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_21_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_21_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_21_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_21_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_22_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_22_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_22_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_22_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_22_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_22_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_22_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_22_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_23_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_23_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_23_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_23_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_23_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_23_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_23_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_23_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_24_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_24_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_24_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_24_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_24_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_24_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_24_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_24_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_25_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_25_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_25_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_25_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_25_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_25_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_25_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_25_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_26_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_26_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_26_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_26_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_26_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_26_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_26_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_26_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_27_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_27_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_27_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_27_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_27_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_27_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_27_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_27_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_28_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_28_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_28_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_28_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_28_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_28_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_28_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_28_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_29_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_29_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_29_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_29_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_29_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_29_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_29_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_29_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_30_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_30_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_30_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_30_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_30_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_30_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_30_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_30_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_31_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_31_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_31_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_31_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_31_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_31_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_31_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_31_uses_stq; // @[tracegen.scala:32:20] reg rob_bsy_0; // @[tracegen.scala:33:25] reg rob_bsy_1; // @[tracegen.scala:33:25] reg rob_bsy_2; // @[tracegen.scala:33:25] reg rob_bsy_3; // @[tracegen.scala:33:25] reg rob_bsy_4; // @[tracegen.scala:33:25] reg rob_bsy_5; // @[tracegen.scala:33:25] reg rob_bsy_6; // @[tracegen.scala:33:25] reg rob_bsy_7; // @[tracegen.scala:33:25] reg rob_bsy_8; // @[tracegen.scala:33:25] reg rob_bsy_9; // @[tracegen.scala:33:25] reg rob_bsy_10; // @[tracegen.scala:33:25] reg rob_bsy_11; // @[tracegen.scala:33:25] reg rob_bsy_12; // @[tracegen.scala:33:25] reg rob_bsy_13; // @[tracegen.scala:33:25] reg rob_bsy_14; // @[tracegen.scala:33:25] reg rob_bsy_15; // @[tracegen.scala:33:25] reg rob_bsy_16; // @[tracegen.scala:33:25] reg rob_bsy_17; // @[tracegen.scala:33:25] reg rob_bsy_18; // @[tracegen.scala:33:25] reg rob_bsy_19; // @[tracegen.scala:33:25] reg rob_bsy_20; // @[tracegen.scala:33:25] reg rob_bsy_21; // @[tracegen.scala:33:25] reg rob_bsy_22; // @[tracegen.scala:33:25] reg rob_bsy_23; // @[tracegen.scala:33:25] reg rob_bsy_24; // @[tracegen.scala:33:25] reg rob_bsy_25; // @[tracegen.scala:33:25] reg rob_bsy_26; // @[tracegen.scala:33:25] reg rob_bsy_27; // @[tracegen.scala:33:25] reg rob_bsy_28; // @[tracegen.scala:33:25] reg rob_bsy_29; // @[tracegen.scala:33:25] reg rob_bsy_30; // @[tracegen.scala:33:25] reg rob_bsy_31; // @[tracegen.scala:33:25] reg [4:0] rob_head; // @[tracegen.scala:34:25] assign io_lsu_rob_head_idx_0 = rob_head; // @[tracegen.scala:19:7, :34:25] reg [4:0] rob_tail; // @[tracegen.scala:35:25] assign io_lsu_rob_pnr_idx_0 = rob_tail; // @[tracegen.scala:19:7, :35:25] assign tracegen_uop_rob_idx = rob_tail; // @[tracegen.scala:35:25, :55:30] reg rob_wait_till_empty; // @[tracegen.scala:36:36] wire _ready_for_amo_T = rob_tail == rob_head; // @[tracegen.scala:34:25, :35:25, :37:32] wire ready_for_amo = _ready_for_amo_T & io_lsu_fencei_rdy_0; // @[tracegen.scala:19:7, :37:{32,45}] wire [31:0] _GEN = {{rob_bsy_31}, {rob_bsy_30}, {rob_bsy_29}, {rob_bsy_28}, {rob_bsy_27}, {rob_bsy_26}, {rob_bsy_25}, {rob_bsy_24}, {rob_bsy_23}, {rob_bsy_22}, {rob_bsy_21}, {rob_bsy_20}, {rob_bsy_19}, {rob_bsy_18}, {rob_bsy_17}, {rob_bsy_16}, {rob_bsy_15}, {rob_bsy_14}, {rob_bsy_13}, {rob_bsy_12}, {rob_bsy_11}, {rob_bsy_10}, {rob_bsy_9}, {rob_bsy_8}, {rob_bsy_7}, {rob_bsy_6}, {rob_bsy_5}, {rob_bsy_4}, {rob_bsy_3}, {rob_bsy_2}, {rob_bsy_1}, {rob_bsy_0}}; // @[tracegen.scala:33:25, :47:29] wire _io_tracegen_req_ready_T = ~_GEN[rob_tail]; // @[tracegen.scala:35:25, :47:29] wire _io_tracegen_req_ready_T_1 = ~rob_wait_till_empty; // @[tracegen.scala:36:36, :48:5] wire _io_tracegen_req_ready_T_2 = _io_tracegen_req_ready_T & _io_tracegen_req_ready_T_1; // @[tracegen.scala:47:{29,48}, :48:5] wire _T_1 = io_tracegen_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_3; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_3 = _T_1; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_40; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_40 = _T_1; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_66; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_66 = _T_1; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_7; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_7 = _T_1; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_30; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_30 = _T_1; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_5; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_5 = _T_1; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T = _T_1; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_57; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_57 = _T_1; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_80; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_80 = _T_1; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_28; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_28 = _T_1; // @[package.scala:16:47] wire _T_2 = io_tracegen_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_4; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_4 = _T_2; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_41; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_41 = _T_2; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_67; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_67 = _T_2; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_8; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_8 = _T_2; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_31; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_31 = _T_2; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_6; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_6 = _T_2; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_1; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_1 = _T_2; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_58; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_58 = _T_2; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_81; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_81 = _T_2; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_29; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_29 = _T_2; // @[package.scala:16:47] wire _T_3 = io_tracegen_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_5; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_5 = _T_3; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_42; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_42 = _T_3; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_68; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_68 = _T_3; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_9; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_9 = _T_3; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_32; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_32 = _T_3; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_7; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_7 = _T_3; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_2; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_2 = _T_3; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_59; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_59 = _T_3; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_82; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_82 = _T_3; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_30; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_30 = _T_3; // @[package.scala:16:47] wire _T_4 = io_tracegen_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_6; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_6 = _T_4; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_43; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_43 = _T_4; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_69; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_69 = _T_4; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_10; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_10 = _T_4; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_33; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_33 = _T_4; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_8; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_8 = _T_4; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_3; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_3 = _T_4; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_60; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_60 = _T_4; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_83; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_83 = _T_4; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_31; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_31 = _T_4; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_7 = _io_tracegen_req_ready_T_3 \| _io_tracegen_req_ready_T_4; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_8 = _io_tracegen_req_ready_T_7 \| _io_tracegen_req_ready_T_5; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_9 = _io_tracegen_req_ready_T_8 \| _io_tracegen_req_ready_T_6; // @[package.scala:16:47, :81:59] wire _T_8 = io_tracegen_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_10; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_10 = _T_8; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_47; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_47 = _T_8; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_73; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_73 = _T_8; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_14; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_14 = _T_8; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_37; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_37 = _T_8; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_12; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_12 = _T_8; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_7; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_7 = _T_8; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_64; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_64 = _T_8; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_87; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_87 = _T_8; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_35; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_35 = _T_8; // @[package.scala:16:47] wire _T_9 = io_tracegen_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_11; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_11 = _T_9; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_48; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_48 = _T_9; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_74; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_74 = _T_9; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_15; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_15 = _T_9; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_38; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_38 = _T_9; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_13; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_13 = _T_9; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_8; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_8 = _T_9; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_65; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_65 = _T_9; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_88; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_88 = _T_9; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_36; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_36 = _T_9; // @[package.scala:16:47] wire _T_10 = io_tracegen_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_12; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_12 = _T_10; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_49; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_49 = _T_10; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_75; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_75 = _T_10; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_16; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_16 = _T_10; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_39; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_39 = _T_10; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_14; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_14 = _T_10; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_9; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_9 = _T_10; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_66; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_66 = _T_10; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_89; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_89 = _T_10; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_37; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_37 = _T_10; // @[package.scala:16:47] wire _T_11 = io_tracegen_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_13; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_13 = _T_11; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_50; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_50 = _T_11; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_76; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_76 = _T_11; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_17; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_17 = _T_11; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_40; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_40 = _T_11; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_15; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_15 = _T_11; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_10; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_10 = _T_11; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_67; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_67 = _T_11; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_90; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_90 = _T_11; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_38; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_38 = _T_11; // @[package.scala:16:47] wire _T_12 = io_tracegen_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_14; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_14 = _T_12; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_51; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_51 = _T_12; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_77; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_77 = _T_12; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_18; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_18 = _T_12; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_41; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_41 = _T_12; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_16; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_16 = _T_12; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_11; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_11 = _T_12; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_68; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_68 = _T_12; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_91; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_91 = _T_12; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_39; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_39 = _T_12; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_15 = _io_tracegen_req_ready_T_10 \| _io_tracegen_req_ready_T_11; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_16 = _io_tracegen_req_ready_T_15 \| _io_tracegen_req_ready_T_12; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_17 = _io_tracegen_req_ready_T_16 \| _io_tracegen_req_ready_T_13; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_18 = _io_tracegen_req_ready_T_17 \| _io_tracegen_req_ready_T_14; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_19 = _io_tracegen_req_ready_T_9 \| _io_tracegen_req_ready_T_18; // @[package.scala:81:59] wire _T_18 = io_tracegen_req_bits_cmd_0 == 5'h6; // @[tracegen.scala:19:7, :49:85] wire _io_tracegen_req_ready_T_20; // @[tracegen.scala:49:85] assign _io_tracegen_req_ready_T_20 = _T_18; // @[tracegen.scala:49:85] wire _io_tracegen_req_ready_T_35; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_35 = _T_18; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_2; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_2 = _T_18; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_52; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_52 = _T_18; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_21 = _io_tracegen_req_ready_T_19 \| _io_tracegen_req_ready_T_20; // @[Consts.scala:87:44] wire _T_20 = io_tracegen_req_bits_cmd_0 == 5'h7; // @[tracegen.scala:19:7, :49:123] wire _io_tracegen_req_ready_T_22; // @[tracegen.scala:49:123] assign _io_tracegen_req_ready_T_22 = _T_20; // @[tracegen.scala:49:123] wire _io_tracegen_req_ready_T_36; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_36 = _T_20; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_64; // @[Consts.scala:90:66] assign _io_tracegen_req_ready_T_64 = _T_20; // @[Consts.scala:90:66] wire _tracegen_uop_uses_ldq_T_3; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_3 = _T_20; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_28; // @[Consts.scala:90:66] assign _tracegen_uop_uses_ldq_T_28 = _T_20; // @[Consts.scala:90:66] wire _tracegen_uop_uses_stq_T_3; // @[Consts.scala:90:66] assign _tracegen_uop_uses_stq_T_3 = _T_20; // @[Consts.scala:90:66] wire _tracegen_uop_is_amo_T_17; // @[tracegen.scala:65:92] assign _tracegen_uop_is_amo_T_17 = _T_20; // @[tracegen.scala:49:123, :65:92] wire _tracegen_uop_uses_ldq_T_53; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_53 = _T_20; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_78; // @[Consts.scala:90:66] assign _tracegen_uop_uses_ldq_T_78 = _T_20; // @[Consts.scala:90:66] wire _tracegen_uop_uses_stq_T_26; // @[Consts.scala:90:66] assign _tracegen_uop_uses_stq_T_26 = _T_20; // @[Consts.scala:90:66] wire _io_tracegen_req_ready_T_23 = _io_tracegen_req_ready_T_21 \| _io_tracegen_req_ready_T_22; // @[tracegen.scala:49:{57,95,123}] wire _io_tracegen_req_ready_T_24 = ~_io_tracegen_req_ready_T_23; // @[tracegen.scala:49:{23,95}] wire _io_tracegen_req_ready_T_25 = ready_for_amo \| _io_tracegen_req_ready_T_24; // @[tracegen.scala:37:45, :49:{20,23}] wire _io_tracegen_req_ready_T_26 = _io_tracegen_req_ready_T_2 & _io_tracegen_req_ready_T_25; // @[tracegen.scala:47:48, :48:26, :49:20] wire _io_tracegen_req_ready_T_27 = &rob_tail; // @[tracegen.scala:35:25, :43:13] wire [5:0] _GEN_0 = {1'h0, rob_tail} + 6'h1; // @[tracegen.scala:35:25, :43:37] wire [5:0] _io_tracegen_req_ready_T_28; // @[tracegen.scala:43:37] assign _io_tracegen_req_ready_T_28 = _GEN_0; // @[tracegen.scala:43:37] wire [5:0] _rob_tail_T_1; // @[tracegen.scala:43:37] assign _rob_tail_T_1 = _GEN_0; // @[tracegen.scala:43:37] wire [4:0] _io_tracegen_req_ready_T_29 = _io_tracegen_req_ready_T_28[4:0]; // @[tracegen.scala:43:37] wire [4:0] _io_tracegen_req_ready_T_30 = _io_tracegen_req_ready_T_27 ? 5'h0 : _io_tracegen_req_ready_T_29; // @[tracegen.scala:43:{8,13,37}] wire _io_tracegen_req_ready_T_31 = _io_tracegen_req_ready_T_30 != rob_head; // @[tracegen.scala:34:25, :43:8, :50:32] wire _io_tracegen_req_ready_T_32 = _io_tracegen_req_ready_T_26 & _io_tracegen_req_ready_T_31; // @[tracegen.scala:48:26, :49:135, :50:32] wire _GEN_1 = io_tracegen_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_33; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_33 = _GEN_1; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T = _GEN_1; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_50; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_50 = _GEN_1; // @[package.scala:16:47] wire _GEN_2 = io_tracegen_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_34; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_34 = _GEN_2; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_1; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_1 = _GEN_2; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_51; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_51 = _GEN_2; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_37 = _io_tracegen_req_ready_T_33 \| _io_tracegen_req_ready_T_34; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_38 = _io_tracegen_req_ready_T_37 \| _io_tracegen_req_ready_T_35; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_39 = _io_tracegen_req_ready_T_38 \| _io_tracegen_req_ready_T_36; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_44 = _io_tracegen_req_ready_T_40 \| _io_tracegen_req_ready_T_41; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_45 = _io_tracegen_req_ready_T_44 \| _io_tracegen_req_ready_T_42; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_46 = _io_tracegen_req_ready_T_45 \| _io_tracegen_req_ready_T_43; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_52 = _io_tracegen_req_ready_T_47 \| _io_tracegen_req_ready_T_48; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_53 = _io_tracegen_req_ready_T_52 \| _io_tracegen_req_ready_T_49; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_54 = _io_tracegen_req_ready_T_53 \| _io_tracegen_req_ready_T_50; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_55 = _io_tracegen_req_ready_T_54 \| _io_tracegen_req_ready_T_51; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_56 = _io_tracegen_req_ready_T_46 \| _io_tracegen_req_ready_T_55; // @[package.scala:81:59] wire _io_tracegen_req_ready_T_57 = _io_tracegen_req_ready_T_39 \| _io_tracegen_req_ready_T_56; // @[package.scala:81:59] wire _io_tracegen_req_ready_T_58 = io_lsu_ldq_full_0_0 & _io_tracegen_req_ready_T_57; // @[Consts.scala:89:68] wire _io_tracegen_req_ready_T_59 = ~_io_tracegen_req_ready_T_58; // @[tracegen.scala:51:{5,26}] wire _io_tracegen_req_ready_T_60 = _io_tracegen_req_ready_T_32 & _io_tracegen_req_ready_T_59; // @[tracegen.scala:49:135, :50:46, :51:5] wire _GEN_3 = io_tracegen_req_bits_cmd_0 == 5'h1; // @[Consts.scala:90:32] wire _io_tracegen_req_ready_T_61; // @[Consts.scala:90:32] assign _io_tracegen_req_ready_T_61 = _GEN_3; // @[Consts.scala:90:32] wire _tracegen_uop_uses_ldq_T_25; // @[Consts.scala:90:32] assign _tracegen_uop_uses_ldq_T_25 = _GEN_3; // @[Consts.scala:90:32] wire _tracegen_uop_uses_stq_T; // @[Consts.scala:90:32] assign _tracegen_uop_uses_stq_T = _GEN_3; // @[Consts.scala:90:32] wire _tracegen_uop_uses_ldq_T_75; // @[Consts.scala:90:32] assign _tracegen_uop_uses_ldq_T_75 = _GEN_3; // @[Consts.scala:90:32] wire _tracegen_uop_uses_stq_T_23; // @[Consts.scala:90:32] assign _tracegen_uop_uses_stq_T_23 = _GEN_3; // @[Consts.scala:90:32] wire _GEN_4 = io_tracegen_req_bits_cmd_0 == 5'h11; // @[Consts.scala:90:49] wire _io_tracegen_req_ready_T_62; // @[Consts.scala:90:49] assign _io_tracegen_req_ready_T_62 = _GEN_4; // @[Consts.scala:90:49] wire _tracegen_uop_uses_ldq_T_26; // @[Consts.scala:90:49] assign _tracegen_uop_uses_ldq_T_26 = _GEN_4; // @[Consts.scala:90:49] wire _tracegen_uop_uses_stq_T_1; // @[Consts.scala:90:49] assign _tracegen_uop_uses_stq_T_1 = _GEN_4; // @[Consts.scala:90:49] wire _tracegen_uop_uses_ldq_T_76; // @[Consts.scala:90:49] assign _tracegen_uop_uses_ldq_T_76 = _GEN_4; // @[Consts.scala:90:49] wire _tracegen_uop_uses_stq_T_24; // @[Consts.scala:90:49] assign _tracegen_uop_uses_stq_T_24 = _GEN_4; // @[Consts.scala:90:49] wire _io_tracegen_req_ready_T_63 = _io_tracegen_req_ready_T_61 \| _io_tracegen_req_ready_T_62; // @[Consts.scala:90:{32,42,49}] wire _io_tracegen_req_ready_T_65 = _io_tracegen_req_ready_T_63 \| _io_tracegen_req_ready_T_64; // @[Consts.scala:90:{42,59,66}] wire _io_tracegen_req_ready_T_70 = _io_tracegen_req_ready_T_66 \| _io_tracegen_req_ready_T_67; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_71 = _io_tracegen_req_ready_T_70 \| _io_tracegen_req_ready_T_68; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_72 = _io_tracegen_req_ready_T_71 \| _io_tracegen_req_ready_T_69; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_78 = _io_tracegen_req_ready_T_73 \| _io_tracegen_req_ready_T_74; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_79 = _io_tracegen_req_ready_T_78 \| _io_tracegen_req_ready_T_75; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_80 = _io_tracegen_req_ready_T_79 \| _io_tracegen_req_ready_T_76; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_81 = _io_tracegen_req_ready_T_80 \| _io_tracegen_req_ready_T_77; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_82 = _io_tracegen_req_ready_T_72 \| _io_tracegen_req_ready_T_81; // @[package.scala:81:59] wire _io_tracegen_req_ready_T_83 = _io_tracegen_req_ready_T_65 \| _io_tracegen_req_ready_T_82; // @[Consts.scala:87:44, :90:{59,76}] wire _io_tracegen_req_ready_T_84 = io_lsu_stq_full_0_0 & _io_tracegen_req_ready_T_83; // @[Consts.scala:90:76] wire _io_tracegen_req_ready_T_85 = ~_io_tracegen_req_ready_T_84; // @[tracegen.scala:52:{5,26}] assign _io_tracegen_req_ready_T_86 = _io_tracegen_req_ready_T_60 & _io_tracegen_req_ready_T_85; // @[tracegen.scala:50:46, :51:63, :52:5] assign io_tracegen_req_ready_0 = _io_tracegen_req_ready_T_86; // @[tracegen.scala:19:7, :51:63] assign io_lsu_dis_uops_0_bits_debug_inst_0 = tracegen_uop_debug_inst; // @[tracegen.scala:19:7, :55:30] wire _tracegen_uop_is_amo_T_18; // @[tracegen.scala:65:64] assign io_lsu_dis_uops_0_bits_is_amo_0 = tracegen_uop_is_amo; // @[tracegen.scala:19:7, :55:30] assign io_lsu_dis_uops_0_bits_rob_idx_0 = tracegen_uop_rob_idx; // @[tracegen.scala:19:7, :55:30] assign io_lsu_dis_uops_0_bits_ldq_idx_0 = tracegen_uop_ldq_idx; // @[tracegen.scala:19:7, :55:30] assign io_lsu_dis_uops_0_bits_stq_idx_0 = tracegen_uop_stq_idx; // @[tracegen.scala:19:7, :55:30] assign io_lsu_dis_uops_0_bits_mem_cmd_0 = tracegen_uop_mem_cmd; // @[tracegen.scala:19:7, :55:30] wire _tracegen_uop_uses_ldq_T_99; // @[tracegen.scala:66:65] assign io_lsu_dis_uops_0_bits_uses_ldq_0 = tracegen_uop_uses_ldq; // @[tracegen.scala:19:7, :55:30] wire _tracegen_uop_uses_stq_T_45; // @[Consts.scala:90:76] assign io_lsu_dis_uops_0_bits_uses_stq_0 = tracegen_uop_uses_stq; // @[tracegen.scala:19:7, :55:30] wire _tracegen_uop_uses_ldq_T_4 = _tracegen_uop_uses_ldq_T \| _tracegen_uop_uses_ldq_T_1; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_5 = _tracegen_uop_uses_ldq_T_4 \| _tracegen_uop_uses_ldq_T_2; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_6 = _tracegen_uop_uses_ldq_T_5 \| _tracegen_uop_uses_ldq_T_3; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_11 = _tracegen_uop_uses_ldq_T_7 \| _tracegen_uop_uses_ldq_T_8; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_12 = _tracegen_uop_uses_ldq_T_11 \| _tracegen_uop_uses_ldq_T_9; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_13 = _tracegen_uop_uses_ldq_T_12 \| _tracegen_uop_uses_ldq_T_10; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_19 = _tracegen_uop_uses_ldq_T_14 \| _tracegen_uop_uses_ldq_T_15; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_20 = _tracegen_uop_uses_ldq_T_19 \| _tracegen_uop_uses_ldq_T_16; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_21 = _tracegen_uop_uses_ldq_T_20 \| _tracegen_uop_uses_ldq_T_17; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_22 = _tracegen_uop_uses_ldq_T_21 \| _tracegen_uop_uses_ldq_T_18; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_23 = _tracegen_uop_uses_ldq_T_13 \| _tracegen_uop_uses_ldq_T_22; // @[package.scala:81:59] wire _tracegen_uop_uses_ldq_T_24 = _tracegen_uop_uses_ldq_T_6 \| _tracegen_uop_uses_ldq_T_23; // @[package.scala:81:59] wire _tracegen_uop_uses_ldq_T_27 = _tracegen_uop_uses_ldq_T_25 \| _tracegen_uop_uses_ldq_T_26; // @[Consts.scala:90:{32,42,49}] wire _tracegen_uop_uses_ldq_T_29 = _tracegen_uop_uses_ldq_T_27 \| _tracegen_uop_uses_ldq_T_28; // @[Consts.scala:90:{42,59,66}] wire _tracegen_uop_uses_ldq_T_34 = _tracegen_uop_uses_ldq_T_30 \| _tracegen_uop_uses_ldq_T_31; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_35 = _tracegen_uop_uses_ldq_T_34 \| _tracegen_uop_uses_ldq_T_32; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_36 = _tracegen_uop_uses_ldq_T_35 \| _tracegen_uop_uses_ldq_T_33; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_42 = _tracegen_uop_uses_ldq_T_37 \| _tracegen_uop_uses_ldq_T_38; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_43 = _tracegen_uop_uses_ldq_T_42 \| _tracegen_uop_uses_ldq_T_39; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_44 = _tracegen_uop_uses_ldq_T_43 \| _tracegen_uop_uses_ldq_T_40; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_45 = _tracegen_uop_uses_ldq_T_44 \| _tracegen_uop_uses_ldq_T_41; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_46 = _tracegen_uop_uses_ldq_T_36 \| _tracegen_uop_uses_ldq_T_45; // @[package.scala:81:59] wire _tracegen_uop_uses_ldq_T_47 = _tracegen_uop_uses_ldq_T_29 \| _tracegen_uop_uses_ldq_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _tracegen_uop_uses_ldq_T_48 = ~_tracegen_uop_uses_ldq_T_47; // @[Consts.scala:90:76] wire _tracegen_uop_uses_ldq_T_49 = _tracegen_uop_uses_ldq_T_24 & _tracegen_uop_uses_ldq_T_48; // @[Consts.scala:89:68] wire _tracegen_uop_uses_stq_T_2 = _tracegen_uop_uses_stq_T \| _tracegen_uop_uses_stq_T_1; // @[Consts.scala:90:{32,42,49}] wire _tracegen_uop_uses_stq_T_4 = _tracegen_uop_uses_stq_T_2 \| _tracegen_uop_uses_stq_T_3; // @[Consts.scala:90:{42,59,66}] wire _tracegen_uop_uses_stq_T_9 = _tracegen_uop_uses_stq_T_5 \| _tracegen_uop_uses_stq_T_6; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_10 = _tracegen_uop_uses_stq_T_9 \| _tracegen_uop_uses_stq_T_7; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_11 = _tracegen_uop_uses_stq_T_10 \| _tracegen_uop_uses_stq_T_8; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_17 = _tracegen_uop_uses_stq_T_12 \| _tracegen_uop_uses_stq_T_13; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_18 = _tracegen_uop_uses_stq_T_17 \| _tracegen_uop_uses_stq_T_14; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_19 = _tracegen_uop_uses_stq_T_18 \| _tracegen_uop_uses_stq_T_15; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_20 = _tracegen_uop_uses_stq_T_19 \| _tracegen_uop_uses_stq_T_16; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_21 = _tracegen_uop_uses_stq_T_11 \| _tracegen_uop_uses_stq_T_20; // @[package.scala:81:59] wire _tracegen_uop_uses_stq_T_22 = _tracegen_uop_uses_stq_T_4 \| _tracegen_uop_uses_stq_T_21; // @[Consts.scala:87:44, :90:{59,76}] assign tracegen_uop_debug_inst = {26'h0, io_tracegen_req_bits_tag_0}; // @[tracegen.scala:19:7, :55:30, :59:29] wire _tracegen_uop_is_amo_T_4 = _tracegen_uop_is_amo_T \| _tracegen_uop_is_amo_T_1; // @[package.scala:16:47, :81:59] wire _tracegen_uop_is_amo_T_5 = _tracegen_uop_is_amo_T_4 \| _tracegen_uop_is_amo_T_2; // @[package.scala:16:47, :81:59] wire _tracegen_uop_is_amo_T_6 = _tracegen_uop_is_amo_T_5 \| _tracegen_uop_is_amo_T_3; // @[package.scala:16:47, :81:59] wire _tracegen_uop_is_amo_T_12 = _tracegen_uop_is_amo_T_7 \| _tracegen_uop_is_amo_T_8; // @[package.scala:16:47, :81:59] wire _tracegen_uop_is_amo_T_13 = _tracegen_uop_is_amo_T_12 \| _tracegen_uop_is_amo_T_9; // @[package.scala:16:47, :81:59] wire _tracegen_uop_is_amo_T_14 = _tracegen_uop_is_amo_T_13 \| _tracegen_uop_is_amo_T_10; // @[package.scala:16:47, :81:59] wire _tracegen_uop_is_amo_T_15 = _tracegen_uop_is_amo_T_14 \| _tracegen_uop_is_amo_T_11; // @[package.scala:16:47, :81:59] wire _tracegen_uop_is_amo_T_16 = _tracegen_uop_is_amo_T_6 \| _tracegen_uop_is_amo_T_15; // @[package.scala:81:59] assign _tracegen_uop_is_amo_T_18 = _tracegen_uop_is_amo_T_16 \| _tracegen_uop_is_amo_T_17; // @[Consts.scala:87:44] assign tracegen_uop_is_amo = _tracegen_uop_is_amo_T_18; // @[tracegen.scala:55:30, :65:64] wire _tracegen_uop_uses_ldq_T_54 = _tracegen_uop_uses_ldq_T_50 \| _tracegen_uop_uses_ldq_T_51; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_55 = _tracegen_uop_uses_ldq_T_54 \| _tracegen_uop_uses_ldq_T_52; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_56 = _tracegen_uop_uses_ldq_T_55 \| _tracegen_uop_uses_ldq_T_53; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_61 = _tracegen_uop_uses_ldq_T_57 \| _tracegen_uop_uses_ldq_T_58; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_62 = _tracegen_uop_uses_ldq_T_61 \| _tracegen_uop_uses_ldq_T_59; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_63 = _tracegen_uop_uses_ldq_T_62 \| _tracegen_uop_uses_ldq_T_60; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_69 = _tracegen_uop_uses_ldq_T_64 \| _tracegen_uop_uses_ldq_T_65; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_70 = _tracegen_uop_uses_ldq_T_69 \| _tracegen_uop_uses_ldq_T_66; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_71 = _tracegen_uop_uses_ldq_T_70 \| _tracegen_uop_uses_ldq_T_67; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_72 = _tracegen_uop_uses_ldq_T_71 \| _tracegen_uop_uses_ldq_T_68; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_73 = _tracegen_uop_uses_ldq_T_63 \| _tracegen_uop_uses_ldq_T_72; // @[package.scala:81:59] wire _tracegen_uop_uses_ldq_T_74 = _tracegen_uop_uses_ldq_T_56 \| _tracegen_uop_uses_ldq_T_73; // @[package.scala:81:59] wire _tracegen_uop_uses_ldq_T_77 = _tracegen_uop_uses_ldq_T_75 \| _tracegen_uop_uses_ldq_T_76; // @[Consts.scala:90:{32,42,49}] wire _tracegen_uop_uses_ldq_T_79 = _tracegen_uop_uses_ldq_T_77 \| _tracegen_uop_uses_ldq_T_78; // @[Consts.scala:90:{42,59,66}] wire _tracegen_uop_uses_ldq_T_84 = _tracegen_uop_uses_ldq_T_80 \| _tracegen_uop_uses_ldq_T_81; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_85 = _tracegen_uop_uses_ldq_T_84 \| _tracegen_uop_uses_ldq_T_82; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_86 = _tracegen_uop_uses_ldq_T_85 \| _tracegen_uop_uses_ldq_T_83; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_92 = _tracegen_uop_uses_ldq_T_87 \| _tracegen_uop_uses_ldq_T_88; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_93 = _tracegen_uop_uses_ldq_T_92 \| _tracegen_uop_uses_ldq_T_89; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_94 = _tracegen_uop_uses_ldq_T_93 \| _tracegen_uop_uses_ldq_T_90; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_95 = _tracegen_uop_uses_ldq_T_94 \| _tracegen_uop_uses_ldq_T_91; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_96 = _tracegen_uop_uses_ldq_T_86 \| _tracegen_uop_uses_ldq_T_95; // @[package.scala:81:59] wire _tracegen_uop_uses_ldq_T_97 = _tracegen_uop_uses_ldq_T_79 \| _tracegen_uop_uses_ldq_T_96; // @[Consts.scala:87:44, :90:{59,76}] wire _tracegen_uop_uses_ldq_T_98 = ~_tracegen_uop_uses_ldq_T_97; // @[Consts.scala:90:76] assign _tracegen_uop_uses_ldq_T_99 = _tracegen_uop_uses_ldq_T_74 & _tracegen_uop_uses_ldq_T_98; // @[Consts.scala:89:68] assign tracegen_uop_uses_ldq = _tracegen_uop_uses_ldq_T_99; // @[tracegen.scala:55:30, :66:65] wire _tracegen_uop_uses_stq_T_25 = _tracegen_uop_uses_stq_T_23 \| _tracegen_uop_uses_stq_T_24; // @[Consts.scala:90:{32,42,49}] wire _tracegen_uop_uses_stq_T_27 = _tracegen_uop_uses_stq_T_25 \| _tracegen_uop_uses_stq_T_26; // @[Consts.scala:90:{42,59,66}] wire _tracegen_uop_uses_stq_T_32 = _tracegen_uop_uses_stq_T_28 \| _tracegen_uop_uses_stq_T_29; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_33 = _tracegen_uop_uses_stq_T_32 \| _tracegen_uop_uses_stq_T_30; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_34 = _tracegen_uop_uses_stq_T_33 \| _tracegen_uop_uses_stq_T_31; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_40 = _tracegen_uop_uses_stq_T_35 \| _tracegen_uop_uses_stq_T_36; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_41 = _tracegen_uop_uses_stq_T_40 \| _tracegen_uop_uses_stq_T_37; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_42 = _tracegen_uop_uses_stq_T_41 \| _tracegen_uop_uses_stq_T_38; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_43 = _tracegen_uop_uses_stq_T_42 \| _tracegen_uop_uses_stq_T_39; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_44 = _tracegen_uop_uses_stq_T_34 \| _tracegen_uop_uses_stq_T_43; // @[package.scala:81:59] assign _tracegen_uop_uses_stq_T_45 = _tracegen_uop_uses_stq_T_27 \| _tracegen_uop_uses_stq_T_44; // @[Consts.scala:87:44, :90:{59,76}] assign tracegen_uop_uses_stq = _tracegen_uop_uses_stq_T_45; // @[Consts.scala:90:76] wire _T = io_tracegen_req_ready_0 & io_tracegen_req_valid_0; // @[Decoupled.scala:51:35] assign _io_lsu_dis_uops_0_valid_T = _T; // @[Decoupled.scala:51:35] wire _io_lsu_agen_0_valid_T; // @[Decoupled.scala:51:35] assign _io_lsu_agen_0_valid_T = _T; // @[Decoupled.scala:51:35] wire _io_lsu_dgen_0_valid_T; // @[Decoupled.scala:51:35] assign _io_lsu_dgen_0_valid_T = _T; // @[Decoupled.scala:51:35] assign io_lsu_dis_uops_0_valid_0 = _io_lsu_dis_uops_0_valid_T; // @[Decoupled.scala:51:35] wire _rob_tail_T = &rob_tail; // @[tracegen.scala:35:25, :43:13] wire [4:0] _rob_tail_T_2 = _rob_tail_T_1[4:0]; // @[tracegen.scala:43:37] wire [4:0] _rob_tail_T_3 = _rob_tail_T ? 5'h0 : _rob_tail_T_2; // @[tracegen.scala:43:{8,13,37}] wire _io_lsu_commit_valids_0_T = ~_GEN[rob_head]; // @[tracegen.scala:34:25, :47:29, :92:31] wire _io_lsu_commit_valids_0_T_1 = rob_head != rob_tail; // @[tracegen.scala:34:25, :35:25, :92:62] wire _io_lsu_commit_valids_0_T_2 = _io_lsu_commit_valids_0_T & _io_lsu_commit_valids_0_T_1; // @[tracegen.scala:92:{31,50,62}] wire [31:0] _GEN_5 = {{rob_respd_31}, {rob_respd_30}, {rob_respd_29}, {rob_respd_28}, {rob_respd_27}, {rob_respd_26}, {rob_respd_25}, {rob_respd_24}, {rob_respd_23}, {rob_respd_22}, {rob_respd_21}, {rob_respd_20}, {rob_respd_19}, {rob_respd_18}, {rob_respd_17}, {rob_respd_16}, {rob_respd_15}, {rob_respd_14}, {rob_respd_13}, {rob_respd_12}, {rob_respd_11}, {rob_respd_10}, {rob_respd_9}, {rob_respd_8}, {rob_respd_7}, {rob_respd_6}, {rob_respd_5}, {rob_respd_4}, {rob_respd_3}, {rob_respd_2}, {rob_respd_1}, {rob_respd_0}}; // @[tracegen.scala:31:26, :92:75] assign _io_lsu_commit_valids_0_T_3 = _io_lsu_commit_valids_0_T_2 & _GEN_5[rob_head]; // @[tracegen.scala:34:25, :92:{50,75}] assign io_lsu_commit_valids_0_0 = _io_lsu_commit_valids_0_T_3; // @[tracegen.scala:19:7, :92:75] wire [31:0][31:0] _GEN_6 = {{rob_uop_31_debug_inst}, {rob_uop_30_debug_inst}, {rob_uop_29_debug_inst}, {rob_uop_28_debug_inst}, {rob_uop_27_debug_inst}, {rob_uop_26_debug_inst}, {rob_uop_25_debug_inst}, {rob_uop_24_debug_inst}, {rob_uop_23_debug_inst}, {rob_uop_22_debug_inst}, {rob_uop_21_debug_inst}, {rob_uop_20_debug_inst}, {rob_uop_19_debug_inst}, {rob_uop_18_debug_inst}, {rob_uop_17_debug_inst}, {rob_uop_16_debug_inst}, {rob_uop_15_debug_inst}, {rob_uop_14_debug_inst}, {rob_uop_13_debug_inst}, {rob_uop_12_debug_inst}, {rob_uop_11_debug_inst}, {rob_uop_10_debug_inst}, {rob_uop_9_debug_inst}, {rob_uop_8_debug_inst}, {rob_uop_7_debug_inst}, {rob_uop_6_debug_inst}, {rob_uop_5_debug_inst}, {rob_uop_4_debug_inst}, {rob_uop_3_debug_inst}, {rob_uop_2_debug_inst}, {rob_uop_1_debug_inst}, {rob_uop_0_debug_inst}}; // @[tracegen.scala:32:20, :93:27] assign io_lsu_commit_uops_0_debug_inst_0 = _GEN_6[rob_head]; // @[tracegen.scala:19:7, :34:25, :93:27] wire [31:0] _GEN_7 = {{rob_uop_31_is_amo}, {rob_uop_30_is_amo}, {rob_uop_29_is_amo}, {rob_uop_28_is_amo}, {rob_uop_27_is_amo}, {rob_uop_26_is_amo}, {rob_uop_25_is_amo}, {rob_uop_24_is_amo}, {rob_uop_23_is_amo}, {rob_uop_22_is_amo}, {rob_uop_21_is_amo}, {rob_uop_20_is_amo}, {rob_uop_19_is_amo}, {rob_uop_18_is_amo}, {rob_uop_17_is_amo}, {rob_uop_16_is_amo}, {rob_uop_15_is_amo}, {rob_uop_14_is_amo}, {rob_uop_13_is_amo}, {rob_uop_12_is_amo}, {rob_uop_11_is_amo}, {rob_uop_10_is_amo}, {rob_uop_9_is_amo}, {rob_uop_8_is_amo}, {rob_uop_7_is_amo}, {rob_uop_6_is_amo}, {rob_uop_5_is_amo}, {rob_uop_4_is_amo}, {rob_uop_3_is_amo}, {rob_uop_2_is_amo}, {rob_uop_1_is_amo}, {rob_uop_0_is_amo}}; // @[tracegen.scala:32:20, :93:27] assign io_lsu_commit_uops_0_is_amo_0 = _GEN_7[rob_head]; // @[tracegen.scala:19:7, :34:25, :93:27] wire [31:0][4:0] _GEN_8 = {{rob_uop_31_rob_idx}, {rob_uop_30_rob_idx}, {rob_uop_29_rob_idx}, {rob_uop_28_rob_idx}, {rob_uop_27_rob_idx}, {rob_uop_26_rob_idx}, {rob_uop_25_rob_idx}, {rob_uop_24_rob_idx}, {rob_uop_23_rob_idx}, {rob_uop_22_rob_idx}, {rob_uop_21_rob_idx}, {rob_uop_20_rob_idx}, {rob_uop_19_rob_idx}, {rob_uop_18_rob_idx}, {rob_uop_17_rob_idx}, {rob_uop_16_rob_idx}, {rob_uop_15_rob_idx}, {rob_uop_14_rob_idx}, {rob_uop_13_rob_idx}, {rob_uop_12_rob_idx}, {rob_uop_11_rob_idx}, {rob_uop_10_rob_idx}, {rob_uop_9_rob_idx}, {rob_uop_8_rob_idx}, {rob_uop_7_rob_idx}, {rob_uop_6_rob_idx}, {rob_uop_5_rob_idx}, {rob_uop_4_rob_idx}, {rob_uop_3_rob_idx}, {rob_uop_2_rob_idx}, {rob_uop_1_rob_idx}, {rob_uop_0_rob_idx}}; // @[tracegen.scala:32:20, :93:27] assign io_lsu_commit_uops_0_rob_idx_0 = _GEN_8[rob_head]; // @[tracegen.scala:19:7, :34:25, :93:27] wire [31:0][3:0] _GEN_9 = {{rob_uop_31_ldq_idx}, {rob_uop_30_ldq_idx}, {rob_uop_29_ldq_idx}, {rob_uop_28_ldq_idx}, {rob_uop_27_ldq_idx}, {rob_uop_26_ldq_idx}, {rob_uop_25_ldq_idx}, {rob_uop_24_ldq_idx}, {rob_uop_23_ldq_idx}, {rob_uop_22_ldq_idx}, {rob_uop_21_ldq_idx}, {rob_uop_20_ldq_idx}, {rob_uop_19_ldq_idx}, {rob_uop_18_ldq_idx}, {rob_uop_17_ldq_idx}, {rob_uop_16_ldq_idx}, {rob_uop_15_ldq_idx}, {rob_uop_14_ldq_idx}, {rob_uop_13_ldq_idx}, {rob_uop_12_ldq_idx}, {rob_uop_11_ldq_idx}, {rob_uop_10_ldq_idx}, {rob_uop_9_ldq_idx}, {rob_uop_8_ldq_idx}, {rob_uop_7_ldq_idx}, {rob_uop_6_ldq_idx}, {rob_uop_5_ldq_idx}, {rob_uop_4_ldq_idx}, {rob_uop_3_ldq_idx}, {rob_uop_2_ldq_idx}, {rob_uop_1_ldq_idx}, {rob_uop_0_ldq_idx}}; // @[tracegen.scala:32:20, :93:27] assign io_lsu_commit_uops_0_ldq_idx_0 = _GEN_9[rob_head]; // @[tracegen.scala:19:7, :34:25, :93:27] wire [31:0][3:0] _GEN_10 = {{rob_uop_31_stq_idx}, {rob_uop_30_stq_idx}, {rob_uop_29_stq_idx}, {rob_uop_28_stq_idx}, {rob_uop_27_stq_idx}, {rob_uop_26_stq_idx}, {rob_uop_25_stq_idx}, {rob_uop_24_stq_idx}, {rob_uop_23_stq_idx}, {rob_uop_22_stq_idx}, {rob_uop_21_stq_idx}, {rob_uop_20_stq_idx}, {rob_uop_19_stq_idx}, {rob_uop_18_stq_idx}, {rob_uop_17_stq_idx}, {rob_uop_16_stq_idx}, {rob_uop_15_stq_idx}, {rob_uop_14_stq_idx}, {rob_uop_13_stq_idx}, {rob_uop_12_stq_idx}, {rob_uop_11_stq_idx}, {rob_uop_10_stq_idx}, {rob_uop_9_stq_idx}, {rob_uop_8_stq_idx}, {rob_uop_7_stq_idx}, {rob_uop_6_stq_idx}, {rob_uop_5_stq_idx}, {rob_uop_4_stq_idx}, {rob_uop_3_stq_idx}, {rob_uop_2_stq_idx}, {rob_uop_1_stq_idx}, {rob_uop_0_stq_idx}}; // @[tracegen.scala:32:20, :93:27] assign io_lsu_commit_uops_0_stq_idx_0 = _GEN_10[rob_head]; // @[tracegen.scala:19:7, :34:25, :93:27] wire [31:0][4:0] _GEN_11 = {{rob_uop_31_mem_cmd}, {rob_uop_30_mem_cmd}, {rob_uop_29_mem_cmd}, {rob_uop_28_mem_cmd}, {rob_uop_27_mem_cmd}, {rob_uop_26_mem_cmd}, {rob_uop_25_mem_cmd}, {rob_uop_24_mem_cmd}, {rob_uop_23_mem_cmd}, {rob_uop_22_mem_cmd}, {rob_uop_21_mem_cmd}, {rob_uop_20_mem_cmd}, {rob_uop_19_mem_cmd}, {rob_uop_18_mem_cmd}, {rob_uop_17_mem_cmd}, {rob_uop_16_mem_cmd}, {rob_uop_15_mem_cmd}, {rob_uop_14_mem_cmd}, {rob_uop_13_mem_cmd}, {rob_uop_12_mem_cmd}, {rob_uop_11_mem_cmd}, {rob_uop_10_mem_cmd}, {rob_uop_9_mem_cmd}, {rob_uop_8_mem_cmd}, {rob_uop_7_mem_cmd}, {rob_uop_6_mem_cmd}, {rob_uop_5_mem_cmd}, {rob_uop_4_mem_cmd}, {rob_uop_3_mem_cmd}, {rob_uop_2_mem_cmd}, {rob_uop_1_mem_cmd}, {rob_uop_0_mem_cmd}}; // @[tracegen.scala:32:20, :93:27] assign io_lsu_commit_uops_0_mem_cmd_0 = _GEN_11[rob_head]; // @[tracegen.scala:19:7, :34:25, :93:27] wire [31:0] _GEN_12 = {{rob_uop_31_uses_ldq}, {rob_uop_30_uses_ldq}, {rob_uop_29_uses_ldq}, {rob_uop_28_uses_ldq}, {rob_uop_27_uses_ldq}, {rob_uop_26_uses_ldq}, {rob_uop_25_uses_ldq}, {rob_uop_24_uses_ldq}, {rob_uop_23_uses_ldq}, {rob_uop_22_uses_ldq}, {rob_uop_21_uses_ldq}, {rob_uop_20_uses_ldq}, {rob_uop_19_uses_ldq}, {rob_uop_18_uses_ldq}, {rob_uop_17_uses_ldq}, {rob_uop_16_uses_ldq}, {rob_uop_15_uses_ldq}, {rob_uop_14_uses_ldq}, {rob_uop_13_uses_ldq}, {rob_uop_12_uses_ldq}, {rob_uop_11_uses_ldq}, {rob_uop_10_uses_ldq}, {rob_uop_9_uses_ldq}, {rob_uop_8_uses_ldq}, {rob_uop_7_uses_ldq}, {rob_uop_6_uses_ldq}, {rob_uop_5_uses_ldq}, {rob_uop_4_uses_ldq}, {rob_uop_3_uses_ldq}, {rob_uop_2_uses_ldq}, {rob_uop_1_uses_ldq}, {rob_uop_0_uses_ldq}}; // @[tracegen.scala:32:20, :93:27] assign io_lsu_commit_uops_0_uses_ldq_0 = _GEN_12[rob_head]; // @[tracegen.scala:19:7, :34:25, :93:27] wire [31:0] _GEN_13 = {{rob_uop_31_uses_stq}, {rob_uop_30_uses_stq}, {rob_uop_29_uses_stq}, {rob_uop_28_uses_stq}, {rob_uop_27_uses_stq}, {rob_uop_26_uses_stq}, {rob_uop_25_uses_stq}, {rob_uop_24_uses_stq}, {rob_uop_23_uses_stq}, {rob_uop_22_uses_stq}, {rob_uop_21_uses_stq}, {rob_uop_20_uses_stq}, {rob_uop_19_uses_stq}, {rob_uop_18_uses_stq}, {rob_uop_17_uses_stq}, {rob_uop_16_uses_stq}, {rob_uop_15_uses_stq}, {rob_uop_14_uses_stq}, {rob_uop_13_uses_stq}, {rob_uop_12_uses_stq}, {rob_uop_11_uses_stq}, {rob_uop_10_uses_stq}, {rob_uop_9_uses_stq}, {rob_uop_8_uses_stq}, {rob_uop_7_uses_stq}, {rob_uop_6_uses_stq}, {rob_uop_5_uses_stq}, {rob_uop_4_uses_stq}, {rob_uop_3_uses_stq}, {rob_uop_2_uses_stq}, {rob_uop_1_uses_stq}, {rob_uop_0_uses_stq}}; // @[tracegen.scala:32:20, :93:27] assign io_lsu_commit_uops_0_uses_stq_0 = _GEN_13[rob_head]; // @[tracegen.scala:19:7, :34:25, :93:27] wire _rob_head_T = &rob_head; // @[tracegen.scala:34:25, :43:13] wire [5:0] _rob_head_T_1 = {1'h0, rob_head} + 6'h1; // @[tracegen.scala:34:25, :43:37] wire [4:0] _rob_head_T_2 = _rob_head_T_1[4:0]; // @[tracegen.scala:43:37] wire [4:0] _rob_head_T_3 = _rob_head_T ? 5'h0 : _rob_head_T_2; // @[tracegen.scala:43:{8,13,37}] wire [31:0][4:0] _GEN_14 = {{rob_31_cmd}, {rob_30_cmd}, {rob_29_cmd}, {rob_28_cmd}, {rob_27_cmd}, {rob_26_cmd}, {rob_25_cmd}, {rob_24_cmd}, {rob_23_cmd}, {rob_22_cmd}, {rob_21_cmd}, {rob_20_cmd}, {rob_19_cmd}, {rob_18_cmd}, {rob_17_cmd}, {rob_16_cmd}, {rob_15_cmd}, {rob_14_cmd}, {rob_13_cmd}, {rob_12_cmd}, {rob_11_cmd}, {rob_10_cmd}, {rob_9_cmd}, {rob_8_cmd}, {rob_7_cmd}, {rob_6_cmd}, {rob_5_cmd}, {rob_4_cmd}, {rob_3_cmd}, {rob_2_cmd}, {rob_1_cmd}, {rob_0_cmd}}; // @[tracegen.scala:30:16, :102:74]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }	module OptimizationBarrier_TLBEntryData_303( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RecFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import consts._ class RecFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val in = Input(Bits((inExpWidth + inSigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in); if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- io.out := io.in<<(outSigWidth - inSigWidth) io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W) } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( inExpWidth, inSigWidth, outExpWidth, outSigWidth, flRoundOpt_sigMSBitAlwaysZero )) roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn) roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := rawIn roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } } File rawFloatFromRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ /---------------------------------------------------------------------------- \| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be \| set. ----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }	module RecFNToRecFN_187( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_62( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_90 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File HasChipyardPRCI.scala: package chipyard.clocking import chisel3._ import scala.collection.mutable.{ArrayBuffer} import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.prci._ import testchipip.boot.{TLTileResetCtrl} import testchipip.clocking.{ClockGroupFakeResetSynchronizer} case class ChipyardPRCIControlParams( slaveWhere: TLBusWrapperLocation = CBUS, baseAddress: BigInt = 0x100000, enableTileClockGating: Boolean = true, enableTileResetSetting: Boolean = true, enableResetSynchronizers: Boolean = true // this should only be disabled to work around verilator async-reset initialization problems ) { def generatePRCIXBar = enableTileClockGating \|\| enableTileResetSetting } case object ChipyardPRCIControlKey extends Field[ChipyardPRCIControlParams](ChipyardPRCIControlParams()) trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElements => require(!p(SubsystemDriveClockGroupsFromIO), "Subsystem allClockGroups cannot be driven from implicit clocks") val prciParams = p(ChipyardPRCIControlKey) // Set up clock domain private val tlbus = locateTLBusWrapper(prciParams.slaveWhere) val prci_ctrl_domain = tlbus.generateSynchronousDomain("ChipyardPRCICtrl") .suggestName("chipyard_prcictrl_domain") val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar(nameSuffix = Some("prcibus")) } } prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar := TLFIFOFixer(TLFIFOFixer.all) := TLBuffer() := _) }) // Aggregate all the clock groups into a single node val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node // The diplomatic clocks in the subsystem are routed to this allClockGroupsNode val clockNamePrefixer = ClockGroupNamePrefixer() (allClockGroupsNode := clockNamePrefixer := aggregator) // Once all the clocks are gathered in the aggregator node, several steps remain // 1. Assign frequencies to any clock groups which did not specify a frequency. // 2. Combine duplicated clock groups (clock groups which physically should be in the same clock domain) // 3. Synchronize reset to each clock group // 4. Clock gate the clock groups corresponding to Tiles (if desired). // 5. Add reset control registers to the tiles (if desired) // The final clock group here contains physically distinct clock domains, which some PRCI node in a // diplomatic IOBinder should drive val frequencySpecifier = ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey)) val clockGroupCombiner = ClockGroupCombiner() val resetSynchronizer = prci_ctrl_domain { if (prciParams.enableResetSynchronizers) ClockGroupResetSynchronizer() else ClockGroupFakeResetSynchronizer() } val tileClockGater = Option.when(prciParams.enableTileClockGating) { prci_ctrl_domain { val clock_gater = LazyModule(new TileClockGater(prciParams.baseAddress + 0x00000, tlbus.beatBytes)) clock_gater.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileClockGater")) := prci_ctrl_bus.get clock_gater } } val tileResetSetter = Option.when(prciParams.enableTileResetSetting) { prci_ctrl_domain { val reset_setter = LazyModule(new TileResetSetter(prciParams.baseAddress + 0x10000, tlbus.beatBytes, tile_prci_domains.map(_._2.tile_reset_domain.clockNode.portParams(0).name.get).toSeq, Nil)) reset_setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileResetSetter")) := prci_ctrl_bus.get reset_setter } } if (!prciParams.enableResetSynchronizers) { println(Console.RED + s""" !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! WARNING: DISABLING THE RESET SYNCHRONIZERS RESULTS IN A BROKEN DESIGN THAT WILL NOT BEHAVE PROPERLY AS ASIC OR FPGA. THESE SHOULD ONLY BE DISABLED TO WORK AROUND LIMITATIONS IN ASYNC RESET INITIALIZATION IN RTL SIMULATORS, NAMELY VERILATOR. !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! """ + Console.RESET) } // The chiptopClockGroupsNode shouuld be what ClockBinders attach to val chiptopClockGroupsNode = ClockGroupEphemeralNode() (aggregator := frequencySpecifier := clockGroupCombiner := resetSynchronizer := tileClockGater.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp"))) := tileResetSetter.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp"))) := chiptopClockGroupsNode) } File Fragmenter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} import scala.math.min import freechips.rocketchip.util.DataToAugmentedData object EarlyAck { sealed trait T case object AllPuts extends T case object PutFulls extends T case object None extends T } // minSize: minimum size of transfers supported by all outward managers // maxSize: maximum size of transfers supported after the Fragmenter is applied // alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager) // earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat // holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst // nameSuffix: appends a suffix to the module name // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize") require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize") require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize") val fragmentBits = log2Ceil(maxSize / minSize) val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0 val toggleBits = 1 val addedBits = fragmentBits + toggleBits + fullBits def expandTransfer(x: TransferSizes, op: String) = if (!x) x else { // validate that we can apply the fragmenter correctly require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})") TransferSizes(x.min, maxSize) } private def noChangeRequired = minSize == maxSize private def shrinkTransfer(x: TransferSizes) = if (!alwaysMin) x else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none private def mapManager(m: TLSlaveParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"), supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"), supportsHint = expandTransfer(m.supportsHint, "Hint")) val node = new TLAdapterNode( // We require that all the responses are mutually FIFO // Thus we need to compact all of the masters into one big master clientFn = { c => (if (noChangeRequired) c else c.v2copy( masters = Seq(TLMasterParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => if (noChangeRequired) { out <> in } else { // All managers must share a common FIFO domain (responses might end up interleaved) val manager = edgeOut.manager val managers = manager.managers val beatBytes = manager.beatBytes val fifoId = managers(0).fifoId require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _)) require (!manager.anySupportAcquireB \|\| !edgeOut.client.anySupportProbe, s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region") require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses") // We can't support devices which are cached on both sides of us require (!edgeOut.manager.anySupportAcquireB \|\| !edgeIn.client.anySupportProbe) // We can't support denied because we reassemble fragments require (!edgeOut.manager.mayDenyGet \|\| holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true") require (!edgeOut.manager.mayDenyPut \|\| earlyAck == EarlyAck.None) /* The Fragmenter is a bit tricky, because there are 5 sizes in play: * max size -- the maximum transfer size possible * orig size -- the original pre-fragmenter size * frag size -- the modified post-fragmenter size * min size -- the threshold below which frag=orig * beat size -- the amount transfered on any given beat * * The relationships are as follows: * max >= orig >= frag * max > min >= beat * It IS possible that orig <= min (then frag=orig; ie: no fragmentation) * * The fragment# (sent via TL.source) is measured in multiples of min size. * Meanwhile, to track the progress, counters measure in multiples of beat size. * * Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16. * * in.A out.A (frag#) out.D (frag#) in.D gen# ack# * get64 get16 6 ackD16 6 ackD64 12 15 * ackD16 6 ackD64 14 * ackD16 6 ackD64 13 * ackD16 6 ackD64 12 * get16 4 ackD16 4 ackD64 8 11 * ackD16 4 ackD64 10 * ackD16 4 ackD64 9 * ackD16 4 ackD64 8 * get16 2 ackD16 2 ackD64 4 7 * ackD16 2 ackD64 6 * ackD16 2 ackD64 5 * ackD16 2 ackD64 4 * get16 0 ackD16 0 ackD64 0 3 * ackD16 0 ackD64 2 * ackD16 0 ackD64 1 * ackD16 0 ackD64 0 * * get8 get8 0 ackD8 0 ackD8 0 1 * ackD8 0 ackD8 0 * * get4 get4 0 ackD4 0 ackD4 0 0 * get1 get1 0 ackD1 0 ackD1 0 0 * * put64 put16 6 15 * put64 put16 6 14 * put64 put16 6 13 * put64 put16 6 ack16 6 12 12 * put64 put16 4 11 * put64 put16 4 10 * put64 put16 4 9 * put64 put16 4 ack16 4 8 8 * put64 put16 2 7 * put64 put16 2 6 * put64 put16 2 5 * put64 put16 2 ack16 2 4 4 * put64 put16 0 3 * put64 put16 0 2 * put64 put16 0 1 * put64 put16 0 ack16 0 ack64 0 0 * * put8 put8 0 1 * put8 put8 0 ack8 0 ack8 0 0 * * put4 put4 0 ack4 0 ack4 0 0 * put1 put1 0 ack1 0 ack1 0 0 / val counterBits = log2Up(maxSize/beatBytes) val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize) // Consider the following waveform for two 4-beat bursts: // ---A----A------------ // -------D-----DDD-DDDD // Under TL rules, the second A can use the same source as the first A, // because the source is released for reuse on the first response beat. // // However, if we fragment the requests, it looks like this: // ---3210-3210--------- // -------3-----210-3210 // ... now we've broken the rules because 210 are twice inflight. // // This phenomenon means we can have essentially 2maxSize/minSize-1 // fragmented transactions in flight per original transaction source. // // To keep the source unique, we encode the beat counter in the low // bits of the source. To solve the overlap, we use a toggle bit. // Whatever toggle bit the D is reassembling, A will use the opposite. // First, handle the return path val acknum = RegInit(0.U(counterBits.W)) val dOrig = Reg(UInt()) val dToggle = RegInit(false.B) val dFragnum = out.d.bits.source(fragmentBits-1, 0) val dFirst = acknum === 0.U val dLast = dFragnum === 0.U // only for AccessAck (!Data) val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1) val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize)) val dHasData = edgeOut.hasData(out.d.bits) // calculate new acknum val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes) val acknum_size = dsizeOH1 >> log2Ceil(beatBytes) assert (!out.d.valid \|\| (acknum_fragment & acknum_size) === 0.U) val dFirst_acknum = acknum_fragment \| Mux(dHasData, acknum_size, 0.U) val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes)) // calculate the original size val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) \| dsizeOH1) when (out.d.fire) { acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement) when (dFirst) { dOrig := dFirst_size dToggle := out.d.bits.source(fragmentBits) } } // Swallow up non-data ack fragments val doEarlyAck = earlyAck match { case EarlyAck.AllPuts => true.B case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1) case EarlyAck.None => false.B } val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast) out.d.ready := in.d.ready \|\| drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged in.d.bits.source := out.d.bits.source >> addedBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig) if (edgeOut.manager.mayDenyPut) { val r_denied = Reg(Bool()) val d_denied = (!dFirst && r_denied) \|\| out.d.bits.denied when (out.d.fire) { r_denied := d_denied } in.d.bits.denied := d_denied } if (edgeOut.manager.mayDenyGet) { // Take denied only from the first beat and hold that value val d_denied = out.d.bits.denied holdUnless dFirst when (dHasData) { in.d.bits.denied := d_denied in.d.bits.corrupt := d_denied \|\| out.d.bits.corrupt } } // What maximum transfer sizes do downstream devices support? val maxArithmetics = managers.map(_.supportsArithmetic.max) val maxLogicals = managers.map(_.supportsLogical.max) val maxGets = managers.map(_.supportsGet.max) val maxPutFulls = managers.map(_.supportsPutFull.max) val maxPutPartials = managers.map(_.supportsPutPartial.max) val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0) // We assume that the request is valid => size 0 is impossible val lgMinSize = log2Ceil(minSize).U val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) // Make the request repeatable val repeater = Module(new Repeater(in.a.bits)) repeater.io.enq <> in.a val in_a = repeater.io.deq // If this is infront of a single manager, these become constants val find = manager.findFast(edgeIn.address(in_a.bits)) val maxLgArithmetic = Mux1H(find, maxLgArithmetics) val maxLgLogical = Mux1H(find, maxLgLogicals) val maxLgGet = Mux1H(find, maxLgGets) val maxLgPutFull = Mux1H(find, maxLgPutFulls) val maxLgPutPartial = Mux1H(find, maxLgPutPartials) val maxLgHint = Mux1H(find, maxLgHints) val limit = if (alwaysMin) lgMinSize else MuxLookup(in_a.bits.opcode, lgMinSize)(Array( TLMessages.PutFullData -> maxLgPutFull, TLMessages.PutPartialData -> maxLgPutPartial, TLMessages.ArithmeticData -> maxLgArithmetic, TLMessages.LogicalData -> maxLgLogical, TLMessages.Get -> maxLgGet, TLMessages.Hint -> maxLgHint)) val aOrig = in_a.bits.size val aFrag = Mux(aOrig > limit, limit, aOrig) val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize)) val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize)) val aHasData = edgeIn.hasData(in_a.bits) val aMask = Mux(aHasData, 0.U, aFragOH1) val gennum = RegInit(0.U(counterBits.W)) val aFirst = gennum === 0.U val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U) val new_gennum = ~(~old_gennum1 \| (aMask >> log2Ceil(beatBytes))) // ~(~x\|y) is width safe val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) \| (aFragOH1 >> log2Ceil(minSize))) val aLast = aFragnum === 0.U val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst)) val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None when (out.a.fire) { gennum := new_gennum } repeater.io.repeat := !aHasData && aFragnum =/= 0.U out.a <> in_a out.a.bits.address := in_a.bits.address \| ~(old_gennum1 << log2Ceil(beatBytes) \| ~aOrigOH1 \| aFragOH1 \| (minSize-1).U) out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum)) out.a.bits.size := aFrag // Optimize away some of the Repeater's registers assert (!repeater.io.full \|\| !aHasData) out.a.bits.data := in.a.bits.data val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full \|\| in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFragmenter { def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { if (minSize <= maxSize) { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix)) fragmenter.node } else { TLEphemeralNode()(ValName("no_fragmenter")) } } def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix) def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) (ram.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.1) := TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLFragmenter(ramBeatBytes, maxSize/2) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File ResetSynchronizer.scala: // See LICENSE for license details. package freechips.rocketchip.prci import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.ResetCatchAndSync /** * Synchronizes the reset of a diplomatic clock-reset pair to its accompanying clock. / class ResetSynchronizer(implicit p: Parameters) extends LazyModule { val node = ClockAdapterNode() lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { (node.out zip node.in).map { case ((o, _), (i, _)) => o.clock := i.clock o.reset := ResetCatchAndSync(i.clock, i.reset.asBool) } } } object ResetSynchronizer { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ResetSynchronizer()).node } /* * Instantiates a reset synchronizer on all clock-reset pairs in a clock group. / class ClockGroupResetSynchronizer(implicit p: Parameters) extends LazyModule { val node = ClockGroupAdapterNode() lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { (node.out zip node.in).map { case ((oG, _), (iG, _)) => (oG.member.data zip iG.member.data).foreach { case (o, i) => o.clock := i.clock o.reset := ResetCatchAndSync(i.clock, i.reset.asBool) } } } } object ClockGroupResetSynchronizer { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupResetSynchronizer()).node } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size node.out.size) > (832)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source \| r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source \| r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink \| r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ \|\| _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) \|\| o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) \|\| o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) \|\| (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }	module ChipyardPRCICtrlClockSinkDomain( // @[ClockDomain.scala:14:9] input auto_reset_setter_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_reset_setter_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_resetSynchronizer_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] output auto_resetSynchronizer_out_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_xbar_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_xbar_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_xbar_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_xbar_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_xbar_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_xbar_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_xbar_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_xbar_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_xbar_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_xbar_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_xbar_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_xbar_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_xbar_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_xbar_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_xbar_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_xbar_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire _fragmenter_1_auto_anon_out_a_valid; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_1_auto_anon_out_a_bits_opcode; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_1_auto_anon_out_a_bits_param; // @[Fragmenter.scala:345:34] wire [1:0] _fragmenter_1_auto_anon_out_a_bits_size; // @[Fragmenter.scala:345:34] wire [10:0] _fragmenter_1_auto_anon_out_a_bits_source; // @[Fragmenter.scala:345:34] wire [20:0] _fragmenter_1_auto_anon_out_a_bits_address; // @[Fragmenter.scala:345:34] wire [7:0] _fragmenter_1_auto_anon_out_a_bits_mask; // @[Fragmenter.scala:345:34] wire [63:0] _fragmenter_1_auto_anon_out_a_bits_data; // @[Fragmenter.scala:345:34] wire _fragmenter_1_auto_anon_out_a_bits_corrupt; // @[Fragmenter.scala:345:34] wire _fragmenter_1_auto_anon_out_d_ready; // @[Fragmenter.scala:345:34] wire _reset_setter_auto_clock_out_member_allClocks_uncore_clock; // @[HasChipyardPRCI.scala:78:34] wire _reset_setter_auto_clock_out_member_allClocks_uncore_reset; // @[HasChipyardPRCI.scala:78:34] wire _fragmenter_auto_anon_in_a_ready; // @[Fragmenter.scala:345:34] wire _fragmenter_auto_anon_in_d_valid; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_auto_anon_in_d_bits_opcode; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_auto_anon_in_d_bits_size; // @[Fragmenter.scala:345:34] wire [6:0] _fragmenter_auto_anon_in_d_bits_source; // @[Fragmenter.scala:345:34] wire [63:0] _fragmenter_auto_anon_in_d_bits_data; // @[Fragmenter.scala:345:34] wire _fragmenter_auto_anon_out_a_valid; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_auto_anon_out_a_bits_opcode; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_auto_anon_out_a_bits_param; // @[Fragmenter.scala:345:34] wire [1:0] _fragmenter_auto_anon_out_a_bits_size; // @[Fragmenter.scala:345:34] wire [10:0] _fragmenter_auto_anon_out_a_bits_source; // @[Fragmenter.scala:345:34] wire [20:0] _fragmenter_auto_anon_out_a_bits_address; // @[Fragmenter.scala:345:34] wire [7:0] _fragmenter_auto_anon_out_a_bits_mask; // @[Fragmenter.scala:345:34] wire [63:0] _fragmenter_auto_anon_out_a_bits_data; // @[Fragmenter.scala:345:34] wire _fragmenter_auto_anon_out_a_bits_corrupt; // @[Fragmenter.scala:345:34] wire _fragmenter_auto_anon_out_d_ready; // @[Fragmenter.scala:345:34] wire _clock_gater_auto_clock_gater_in_1_a_ready; // @[HasChipyardPRCI.scala:73:33] wire _clock_gater_auto_clock_gater_in_1_d_valid; // @[HasChipyardPRCI.scala:73:33] wire [2:0] _clock_gater_auto_clock_gater_in_1_d_bits_opcode; // @[HasChipyardPRCI.scala:73:33] wire [1:0] _clock_gater_auto_clock_gater_in_1_d_bits_size; // @[HasChipyardPRCI.scala:73:33] wire [10:0] _clock_gater_auto_clock_gater_in_1_d_bits_source; // @[HasChipyardPRCI.scala:73:33] wire [63:0] _clock_gater_auto_clock_gater_in_1_d_bits_data; // @[HasChipyardPRCI.scala:73:33] wire _clock_gater_auto_clock_gater_out_member_allClocks_uncore_clock; // @[HasChipyardPRCI.scala:73:33] wire _clock_gater_auto_clock_gater_out_member_allClocks_uncore_reset; // @[HasChipyardPRCI.scala:73:33] wire _xbar_auto_anon_out_1_a_valid; // @[Xbar.scala:346:26] wire [2:0] _xbar_auto_anon_out_1_a_bits_opcode; // @[Xbar.scala:346:26] wire [2:0] _xbar_auto_anon_out_1_a_bits_param; // @[Xbar.scala:346:26] wire [2:0] _xbar_auto_anon_out_1_a_bits_size; // @[Xbar.scala:346:26] wire [6:0] _xbar_auto_anon_out_1_a_bits_source; // @[Xbar.scala:346:26] wire [20:0] _xbar_auto_anon_out_1_a_bits_address; // @[Xbar.scala:346:26] wire [7:0] _xbar_auto_anon_out_1_a_bits_mask; // @[Xbar.scala:346:26] wire [63:0] _xbar_auto_anon_out_1_a_bits_data; // @[Xbar.scala:346:26] wire _xbar_auto_anon_out_1_a_bits_corrupt; // @[Xbar.scala:346:26] wire _xbar_auto_anon_out_1_d_ready; // @[Xbar.scala:346:26] wire _xbar_auto_anon_out_0_a_valid; // @[Xbar.scala:346:26] wire [2:0] _xbar_auto_anon_out_0_a_bits_opcode; // @[Xbar.scala:346:26] wire [2:0] _xbar_auto_anon_out_0_a_bits_param; // @[Xbar.scala:346:26] wire [2:0] _xbar_auto_anon_out_0_a_bits_size; // @[Xbar.scala:346:26] wire [6:0] _xbar_auto_anon_out_0_a_bits_source; // @[Xbar.scala:346:26] wire [20:0] _xbar_auto_anon_out_0_a_bits_address; // @[Xbar.scala:346:26] wire [7:0] _xbar_auto_anon_out_0_a_bits_mask; // @[Xbar.scala:346:26] wire [63:0] _xbar_auto_anon_out_0_a_bits_data; // @[Xbar.scala:346:26] wire _xbar_auto_anon_out_0_a_bits_corrupt; // @[Xbar.scala:346:26] wire _xbar_auto_anon_out_0_d_ready; // @[Xbar.scala:346:26] wire auto_reset_setter_clock_in_member_allClocks_uncore_clock_0 = auto_reset_setter_clock_in_member_allClocks_uncore_clock; // @[ClockDomain.scala:14:9] wire auto_reset_setter_clock_in_member_allClocks_uncore_reset_0 = auto_reset_setter_clock_in_member_allClocks_uncore_reset; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_a_valid_0 = auto_xbar_anon_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_xbar_anon_in_a_bits_opcode_0 = auto_xbar_anon_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_xbar_anon_in_a_bits_param_0 = auto_xbar_anon_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_xbar_anon_in_a_bits_size_0 = auto_xbar_anon_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [6:0] auto_xbar_anon_in_a_bits_source_0 = auto_xbar_anon_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [20:0] auto_xbar_anon_in_a_bits_address_0 = auto_xbar_anon_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_xbar_anon_in_a_bits_mask_0 = auto_xbar_anon_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_xbar_anon_in_a_bits_data_0 = auto_xbar_anon_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_a_bits_corrupt_0 = auto_xbar_anon_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_d_ready_0 = auto_xbar_anon_in_d_ready; // @[ClockDomain.scala:14:9] wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire [1:0] auto_xbar_anon_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9] wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9] wire auto_resetSynchronizer_out_member_allClocks_uncore_clock_0; // @[ClockDomain.scala:14:9] wire auto_resetSynchronizer_out_member_allClocks_uncore_reset_0; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_xbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_xbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [6:0] auto_xbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_xbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17] TLXbar_prcibus_i1_o2_a21d64s7k1z3u xbar ( // @[Xbar.scala:346:26] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_a_ready (auto_xbar_anon_in_a_ready_0), .auto_anon_in_a_valid (auto_xbar_anon_in_a_valid_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_opcode (auto_xbar_anon_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_param (auto_xbar_anon_in_a_bits_param_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_size (auto_xbar_anon_in_a_bits_size_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_source (auto_xbar_anon_in_a_bits_source_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_address (auto_xbar_anon_in_a_bits_address_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_mask (auto_xbar_anon_in_a_bits_mask_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_data (auto_xbar_anon_in_a_bits_data_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_corrupt (auto_xbar_anon_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_anon_in_d_ready (auto_xbar_anon_in_d_ready_0), // @[ClockDomain.scala:14:9] .auto_anon_in_d_valid (auto_xbar_anon_in_d_valid_0), .auto_anon_in_d_bits_opcode (auto_xbar_anon_in_d_bits_opcode_0), .auto_anon_in_d_bits_size (auto_xbar_anon_in_d_bits_size_0), .auto_anon_in_d_bits_source (auto_xbar_anon_in_d_bits_source_0), .auto_anon_in_d_bits_data (auto_xbar_anon_in_d_bits_data_0), .auto_anon_out_1_a_valid (_xbar_auto_anon_out_1_a_valid), .auto_anon_out_1_a_bits_opcode (_xbar_auto_anon_out_1_a_bits_opcode), .auto_anon_out_1_a_bits_param (_xbar_auto_anon_out_1_a_bits_param), .auto_anon_out_1_a_bits_size (_xbar_auto_anon_out_1_a_bits_size), .auto_anon_out_1_a_bits_source (_xbar_auto_anon_out_1_a_bits_source), .auto_anon_out_1_a_bits_address (_xbar_auto_anon_out_1_a_bits_address), .auto_anon_out_1_a_bits_mask (_xbar_auto_anon_out_1_a_bits_mask), .auto_anon_out_1_a_bits_data (_xbar_auto_anon_out_1_a_bits_data), .auto_anon_out_1_a_bits_corrupt (_xbar_auto_anon_out_1_a_bits_corrupt), .auto_anon_out_1_d_ready (_xbar_auto_anon_out_1_d_ready), .auto_anon_out_0_a_ready (_fragmenter_auto_anon_in_a_ready), // @[Fragmenter.scala:345:34] .auto_anon_out_0_a_valid (_xbar_auto_anon_out_0_a_valid), .auto_anon_out_0_a_bits_opcode (_xbar_auto_anon_out_0_a_bits_opcode), .auto_anon_out_0_a_bits_param (_xbar_auto_anon_out_0_a_bits_param), .auto_anon_out_0_a_bits_size (_xbar_auto_anon_out_0_a_bits_size), .auto_anon_out_0_a_bits_source (_xbar_auto_anon_out_0_a_bits_source), .auto_anon_out_0_a_bits_address (_xbar_auto_anon_out_0_a_bits_address), .auto_anon_out_0_a_bits_mask (_xbar_auto_anon_out_0_a_bits_mask), .auto_anon_out_0_a_bits_data (_xbar_auto_anon_out_0_a_bits_data), .auto_anon_out_0_a_bits_corrupt (_xbar_auto_anon_out_0_a_bits_corrupt), .auto_anon_out_0_d_ready (_xbar_auto_anon_out_0_d_ready), .auto_anon_out_0_d_valid (_fragmenter_auto_anon_in_d_valid), // @[Fragmenter.scala:345:34] .auto_anon_out_0_d_bits_opcode (_fragmenter_auto_anon_in_d_bits_opcode), // @[Fragmenter.scala:345:34] .auto_anon_out_0_d_bits_size (_fragmenter_auto_anon_in_d_bits_size), // @[Fragmenter.scala:345:34] .auto_anon_out_0_d_bits_source (_fragmenter_auto_anon_in_d_bits_source), // @[Fragmenter.scala:345:34] .auto_anon_out_0_d_bits_data (_fragmenter_auto_anon_in_d_bits_data) // @[Fragmenter.scala:345:34] ); // @[Xbar.scala:346:26] ClockGroupResetSynchronizer resetSynchronizer ( // @[ResetSynchronizer.scala:46:69] .auto_in_member_allClocks_uncore_clock (_clock_gater_auto_clock_gater_out_member_allClocks_uncore_clock), // @[HasChipyardPRCI.scala:73:33] .auto_in_member_allClocks_uncore_reset (_clock_gater_auto_clock_gater_out_member_allClocks_uncore_reset), // @[HasChipyardPRCI.scala:73:33] .auto_out_member_allClocks_uncore_clock (auto_resetSynchronizer_out_member_allClocks_uncore_clock_0), .auto_out_member_allClocks_uncore_reset (auto_resetSynchronizer_out_member_allClocks_uncore_reset_0) ); // @[ResetSynchronizer.scala:46:69] TileClockGater clock_gater ( // @[HasChipyardPRCI.scala:73:33] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_clock_gater_in_1_a_ready (_clock_gater_auto_clock_gater_in_1_a_ready), .auto_clock_gater_in_1_a_valid (_fragmenter_auto_anon_out_a_valid), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_param (_fragmenter_auto_anon_out_a_bits_param), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_size (_fragmenter_auto_anon_out_a_bits_size), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_source (_fragmenter_auto_anon_out_a_bits_source), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_address (_fragmenter_auto_anon_out_a_bits_address), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_data (_fragmenter_auto_anon_out_a_bits_data), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_d_ready (_fragmenter_auto_anon_out_d_ready), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_d_valid (_clock_gater_auto_clock_gater_in_1_d_valid), .auto_clock_gater_in_1_d_bits_opcode (_clock_gater_auto_clock_gater_in_1_d_bits_opcode), .auto_clock_gater_in_1_d_bits_size (_clock_gater_auto_clock_gater_in_1_d_bits_size), .auto_clock_gater_in_1_d_bits_source (_clock_gater_auto_clock_gater_in_1_d_bits_source), .auto_clock_gater_in_1_d_bits_data (_clock_gater_auto_clock_gater_in_1_d_bits_data), .auto_clock_gater_in_0_member_allClocks_uncore_clock (_reset_setter_auto_clock_out_member_allClocks_uncore_clock), // @[HasChipyardPRCI.scala:78:34] .auto_clock_gater_in_0_member_allClocks_uncore_reset (_reset_setter_auto_clock_out_member_allClocks_uncore_reset), // @[HasChipyardPRCI.scala:78:34] .auto_clock_gater_out_member_allClocks_uncore_clock (_clock_gater_auto_clock_gater_out_member_allClocks_uncore_clock), .auto_clock_gater_out_member_allClocks_uncore_reset (_clock_gater_auto_clock_gater_out_member_allClocks_uncore_reset) ); // @[HasChipyardPRCI.scala:73:33] TLFragmenter_TileClockGater fragmenter ( // @[Fragmenter.scala:345:34] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_a_ready (_fragmenter_auto_anon_in_a_ready), .auto_anon_in_a_valid (_xbar_auto_anon_out_0_a_valid), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_opcode (_xbar_auto_anon_out_0_a_bits_opcode), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_param (_xbar_auto_anon_out_0_a_bits_param), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_size (_xbar_auto_anon_out_0_a_bits_size), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_source (_xbar_auto_anon_out_0_a_bits_source), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_address (_xbar_auto_anon_out_0_a_bits_address), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_mask (_xbar_auto_anon_out_0_a_bits_mask), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_data (_xbar_auto_anon_out_0_a_bits_data), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_corrupt (_xbar_auto_anon_out_0_a_bits_corrupt), // @[Xbar.scala:346:26] .auto_anon_in_d_ready (_xbar_auto_anon_out_0_d_ready), // @[Xbar.scala:346:26] .auto_anon_in_d_valid (_fragmenter_auto_anon_in_d_valid), .auto_anon_in_d_bits_opcode (_fragmenter_auto_anon_in_d_bits_opcode), .auto_anon_in_d_bits_size (_fragmenter_auto_anon_in_d_bits_size), .auto_anon_in_d_bits_source (_fragmenter_auto_anon_in_d_bits_source), .auto_anon_in_d_bits_data (_fragmenter_auto_anon_in_d_bits_data), .auto_anon_out_a_ready (_clock_gater_auto_clock_gater_in_1_a_ready), // @[HasChipyardPRCI.scala:73:33] .auto_anon_out_a_valid (_fragmenter_auto_anon_out_a_valid), .auto_anon_out_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (_fragmenter_auto_anon_out_a_bits_param), .auto_anon_out_a_bits_size (_fragmenter_auto_anon_out_a_bits_size), .auto_anon_out_a_bits_source (_fragmenter_auto_anon_out_a_bits_source), .auto_anon_out_a_bits_address (_fragmenter_auto_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (_fragmenter_auto_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (_fragmenter_auto_anon_out_d_ready), .auto_anon_out_d_valid (_clock_gater_auto_clock_gater_in_1_d_valid), // @[HasChipyardPRCI.scala:73:33] .auto_anon_out_d_bits_opcode (_clock_gater_auto_clock_gater_in_1_d_bits_opcode), // @[HasChipyardPRCI.scala:73:33] .auto_anon_out_d_bits_size (_clock_gater_auto_clock_gater_in_1_d_bits_size), // @[HasChipyardPRCI.scala:73:33] .auto_anon_out_d_bits_source (_clock_gater_auto_clock_gater_in_1_d_bits_source), // @[HasChipyardPRCI.scala:73:33] .auto_anon_out_d_bits_data (_clock_gater_auto_clock_gater_in_1_d_bits_data) // @[HasChipyardPRCI.scala:73:33] ); // @[Fragmenter.scala:345:34] TileResetSetter reset_setter ( // @[HasChipyardPRCI.scala:78:34] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_clock_in_member_allClocks_uncore_clock (auto_reset_setter_clock_in_member_allClocks_uncore_clock_0), // @[ClockDomain.scala:14:9] .auto_clock_in_member_allClocks_uncore_reset (auto_reset_setter_clock_in_member_allClocks_uncore_reset_0), // @[ClockDomain.scala:14:9] .auto_clock_out_member_allClocks_uncore_clock (_reset_setter_auto_clock_out_member_allClocks_uncore_clock), .auto_clock_out_member_allClocks_uncore_reset (_reset_setter_auto_clock_out_member_allClocks_uncore_reset), .auto_tl_in_a_valid (_fragmenter_1_auto_anon_out_a_valid), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_opcode (_fragmenter_1_auto_anon_out_a_bits_opcode), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_param (_fragmenter_1_auto_anon_out_a_bits_param), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_size (_fragmenter_1_auto_anon_out_a_bits_size), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_source (_fragmenter_1_auto_anon_out_a_bits_source), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_address (_fragmenter_1_auto_anon_out_a_bits_address), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_mask (_fragmenter_1_auto_anon_out_a_bits_mask), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_data (_fragmenter_1_auto_anon_out_a_bits_data), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_corrupt (_fragmenter_1_auto_anon_out_a_bits_corrupt), // @[Fragmenter.scala:345:34] .auto_tl_in_d_ready (_fragmenter_1_auto_anon_out_d_ready) // @[Fragmenter.scala:345:34] ); // @[HasChipyardPRCI.scala:78:34] TLFragmenter_TileResetSetter fragmenter_1 ( // @[Fragmenter.scala:345:34] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_a_valid (_xbar_auto_anon_out_1_a_valid), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_opcode (_xbar_auto_anon_out_1_a_bits_opcode), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_param (_xbar_auto_anon_out_1_a_bits_param), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_size (_xbar_auto_anon_out_1_a_bits_size), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_source (_xbar_auto_anon_out_1_a_bits_source), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_address (_xbar_auto_anon_out_1_a_bits_address), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_mask (_xbar_auto_anon_out_1_a_bits_mask), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_data (_xbar_auto_anon_out_1_a_bits_data), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_corrupt (_xbar_auto_anon_out_1_a_bits_corrupt), // @[Xbar.scala:346:26] .auto_anon_in_d_ready (_xbar_auto_anon_out_1_d_ready), // @[Xbar.scala:346:26] .auto_anon_out_a_valid (_fragmenter_1_auto_anon_out_a_valid), .auto_anon_out_a_bits_opcode (_fragmenter_1_auto_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (_fragmenter_1_auto_anon_out_a_bits_param), .auto_anon_out_a_bits_size (_fragmenter_1_auto_anon_out_a_bits_size), .auto_anon_out_a_bits_source (_fragmenter_1_auto_anon_out_a_bits_source), .auto_anon_out_a_bits_address (_fragmenter_1_auto_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (_fragmenter_1_auto_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (_fragmenter_1_auto_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (_fragmenter_1_auto_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (_fragmenter_1_auto_anon_out_d_ready) ); // @[Fragmenter.scala:345:34] assign auto_resetSynchronizer_out_member_allClocks_uncore_clock = auto_resetSynchronizer_out_member_allClocks_uncore_clock_0; // @[ClockDomain.scala:14:9] assign auto_resetSynchronizer_out_member_allClocks_uncore_reset = auto_resetSynchronizer_out_member_allClocks_uncore_reset_0; // @[ClockDomain.scala:14:9] assign auto_xbar_anon_in_a_ready = auto_xbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_xbar_anon_in_d_valid = auto_xbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_xbar_anon_in_d_bits_opcode = auto_xbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_xbar_anon_in_d_bits_size = auto_xbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_xbar_anon_in_d_bits_source = auto_xbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_xbar_anon_in_d_bits_data = auto_xbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Rounding.scala: package saturn.exu import chisel3._ import chisel3.util._ object RoundingIncrement { def apply(vxrm: UInt, v_d: Bool, v_d1: Bool, v_d20: Option[UInt]): Bool = MuxLookup(vxrm(1,0), false.B)(Seq( (0.U -> (v_d1)), (1.U -> (v_d1 && (v_d20.map(_ =/= 0.U).getOrElse(false.B) \|\| v_d))), (2.U -> (false.B)), (3.U -> (!v_d && Cat(v_d1, v_d20.getOrElse(false.B)) =/= 0.U)) )) def apply(vxrm: UInt, bits: UInt): UInt = { val w = bits.getWidth val d = w - 1 require(w >= 2) apply(vxrm, bits(d), bits(d-1), if (w > 2) Some(bits(d-2,0)) else None) } } File IntegerPipe.scala: package saturn.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import saturn.common._ import saturn.insns._ class AdderArray(dLenB: Int) extends Module { val io = IO(new Bundle { val in1 = Input(Vec(dLenB, UInt(8.W))) val in2 = Input(Vec(dLenB, UInt(8.W))) val incr = Input(Vec(dLenB, Bool())) val mask_carry = Input(UInt(dLenB.W)) val signed = Input(Bool()) val eew = Input(UInt(2.W)) val avg = Input(Bool()) val rm = Input(UInt(2.W)) val sub = Input(Bool()) val cmask = Input(Bool()) val out = Output(Vec(dLenB, UInt(8.W))) val carry = Output(Vec(dLenB, Bool())) }) val use_carry = VecInit.tabulate(4)({ eew => Fill(dLenB >> eew, ~(1.U((1 << eew).W))) })(io.eew) val carry_clear = Mux(io.avg, use_carry.asBools.map(Cat(~(0.U(8.W)), _)).asUInt, ~(0.U(73.W))) val carry_restore = Mux(io.avg, use_carry.asBools.map(Cat(0.U(8.W), _)).asUInt, 0.U(73.W)) val avg_in1 = VecInit.tabulate(4) { eew => VecInit(io.in1.asTypeOf(Vec(dLenB >> eew, UInt((8 << eew).W))).map(e => Cat(io.signed && e((8<<eew)-1), e) >> 1)).asUInt }(io.eew).asTypeOf(Vec(dLenB, UInt(8.W))) val avg_in2 = VecInit.tabulate(4) { eew => VecInit(io.in2.asTypeOf(Vec(dLenB >> eew, UInt((8 << eew).W))).map(e => Cat(io.signed && e((8<<eew)-1), e) >> 1)).asUInt }(io.eew).asTypeOf(Vec(dLenB, UInt(8.W))) val in1 = Mux(io.avg, avg_in1, io.in1) val in2 = Mux(io.avg, avg_in2, io.in2) for (i <- 0 until (dLenB >> 3)) { val h = (i+1)8-1 val l = i8 val io_in1_slice = io.in1.slice(l,h+1) val io_in2_slice = io.in2.slice(l,h+1) val in1_slice = in1.slice(l,h+1) val in2_slice = in2.slice(l,h+1) val use_carry_slice = use_carry(h,l).asBools val mask_carry_slice = io.mask_carry(h,l).asBools val incr_slice = io.incr.slice(l,h+1) val in1_dummy_bits = (io_in1_slice .zip(io_in2_slice) .zip(use_carry_slice) .zip(mask_carry_slice).map { case(((i1, i2), carry), mask_bit) => { val avg_bit = ((io.sub ^ i1(0)) & i2(0)) \| (((io.sub ^ i1(0)) ^ i2(0)) & io.sub) val bit = (!io.cmask & io.sub) \| (io.cmask & (io.sub ^ mask_bit)) Mux(carry, 1.U(1.W), Mux(io.avg, avg_bit, bit)) }}) val in2_dummy_bits = (io_in1_slice .zip(io_in2_slice) .zip(use_carry_slice) .zip(mask_carry_slice).map { case(((i1, i2), carry), mask_bit) => { val avg_bit = ((io.sub ^ i1(0)) & i2(0)) \| (((io.sub ^ i1(0)) ^ i2(0)) & io.sub) val bit = (!io.cmask & io.sub) \| (io.cmask & (io.sub ^ mask_bit)) Mux(carry, 0.U(1.W), Mux(io.avg, avg_bit, bit)) }}) val round_incrs = (io_in1_slice .zip(io_in2_slice) .zipWithIndex.map { case((l, r), i) => { val sum = r(1,0) +& ((l(1,0) ^ Fill(2, io.sub)) +& io.sub) Cat(0.U(7.W), Cat(Mux(io.avg, RoundingIncrement(io.rm, sum(1), sum(0), None) & !use_carry_slice(i), 0.U), 0.U(1.W))) }} .asUInt) val in1_constructed = in1_slice.zip(in1_dummy_bits).map { case(i1, dummy_bit) => (i1 ^ Fill(8, io.sub)) ## dummy_bit }.asUInt val in2_constructed = in2_slice.zip(in2_dummy_bits).map { case(i2, dummy_bit) => i2 ## dummy_bit }.asUInt val incr_constructed = incr_slice.zip(use_carry_slice).map { case(incr, masking) => Cat(0.U(7.W), Cat(Mux(!masking, incr, 0.U(1.W)), 0.U(1.W))) }.asUInt val sum = (((in1_constructed +& in2_constructed) & carry_clear) \| carry_restore) +& round_incrs +& incr_constructed for (j <- 0 until 8) { io.out((i8) + j) := sum(((j+1)9)-1, (j9) + 1) io.carry((i8) + j) := sum((j+1)9) } } } class CompareArray(dLenB: Int) extends Module { val io = IO(new Bundle { val in1 = Input(Vec(dLenB, UInt(8.W))) val in2 = Input(Vec(dLenB, UInt(8.W))) val eew = Input(UInt(2.W)) val signed = Input(Bool()) val less = Input(Bool()) val sle = Input(Bool()) val inv = Input(Bool()) val minmax = Output(UInt(dLenB.W)) val result = Output(UInt(dLenB.W)) }) val eq = io.in2.zip(io.in1).map { x => x._1 === x._2 } val lt = io.in2.zip(io.in1).map { x => x._1 < x._2 } val minmax_bits = Wire(Vec(4, UInt(dLenB.W))) val result_bits = Wire(Vec(4, UInt(dLenB.W))) io.minmax := minmax_bits(io.eew) io.result := result_bits(io.eew) for (eew <- 0 until 4) { val lts = lt.grouped(1 << eew) val eqs = eq.grouped(1 << eew) val bits = VecInit(lts.zip(eqs).zipWithIndex.map { case ((e_lts, e_eqs), i) => val eq = e_eqs.andR val in1_hi = io.in1((i+1)(1<<eew)-1)(7) val in2_hi = io.in2((i+1)(1<<eew)-1)(7) val hi_lt = Mux(io.signed, in2_hi & !in1_hi, !in2_hi & in1_hi) val hi_eq = in1_hi === in2_hi val lt = (e_lts :+ hi_lt).zip(e_eqs :+ hi_eq).foldLeft(false.B) { case (p, (l, e)) => l \|\| (e && p) } Mux(io.less, lt \|\| (io.sle && eq), io.inv ^ eq) }.toSeq).asUInt minmax_bits(eew) := FillInterleaved(1 << eew, bits) result_bits(eew) := Fill(1 << eew, bits) } } class SaturatedSumArray(dLenB: Int) extends Module { val dLen = dLenB 8 val io = IO(new Bundle { val sum = Input(Vec(dLenB, UInt(8.W))) val carry = Input(Vec(dLenB, Bool())) val in1_sign = Input(Vec(dLenB, Bool())) val in2_sign = Input(Vec(dLenB, Bool())) val sub = Input(Bool()) val eew = Input(UInt(2.W)) val signed = Input(Bool()) val set_vxsat = Output(UInt(dLenB.W)) val out = Output(Vec(dLenB, UInt(8.W))) }) val unsigned_mask = VecInit.tabulate(4)({ eew => FillInterleaved(1 << eew, VecInit.tabulate(dLenB >> eew)(i => io.sub ^ io.carry(((i+1) << eew)-1)).asUInt) })(io.eew) val unsigned_clip = Mux(io.sub, 0.U(dLen.W), ~(0.U(dLen.W))).asTypeOf(Vec(dLenB, UInt(8.W))) val (signed_masks, signed_clips): (Seq[UInt], Seq[UInt]) = Seq.tabulate(4)({ eew => val out_sign = VecInit.tabulate(dLenB >> eew)(i => io.sum(((i+1)<<eew)-1)(7)).asUInt val vs2_sign = VecInit.tabulate(dLenB >> eew)(i => io.in2_sign(((i+1)<<eew)-1) ).asUInt val vs1_sign = VecInit.tabulate(dLenB >> eew)(i => io.in1_sign(((i+1)<<eew)-1) ).asUInt val input_xor = vs2_sign ^ vs1_sign val may_clip = Mux(io.sub, input_xor, ~input_xor) // add clips when signs match, sub clips when signs mismatch val clip = (vs2_sign ^ out_sign) & may_clip // clips if the output sign doesn't match the input sign val clip_neg = Cat(1.U, 0.U(((8 << eew)-1).W)) val clip_pos = ~clip_neg val clip_value = VecInit(vs2_sign.asBools.map(sign => Mux(sign, clip_neg, clip_pos))).asUInt (FillInterleaved((1 << eew), clip), clip_value) }).unzip val signed_mask = VecInit(signed_masks)(io.eew) val signed_clip = VecInit(signed_clips)(io.eew).asTypeOf(Vec(dLenB, UInt(8.W))) val mask = Mux(io.signed, signed_mask, unsigned_mask) val clip = Mux(io.signed, signed_clip, unsigned_clip) io.out := io.sum.zipWithIndex.map { case (o,i) => Mux(mask(i), clip(i), o) } io.set_vxsat := mask } case object IntegerPipeFactory extends FunctionalUnitFactory { def insns = Seq( ADD.VV, ADD.VX, ADD.VI, SUB.VV, SUB.VX, RSUB.VX, RSUB.VI, WADDU.VV, WADDU.VX, WADD.VV, WADD.VX, WSUBU.VV, WSUBU.VX, WSUB.VV, WSUB.VX, WADDUW.VV, WADDUW.VX, WADDW.VV, WADDW.VX, WSUBUW.VV, WSUBUW.VX, WSUBW.VV, WSUBW.VX, ADC.VV, ADC.VX, ADC.VI, MADC.VV, MADC.VX, MADC.VI, SBC.VV, SBC.VX, MSBC.VV, MSBC.VX, NEXT.VV, MSEQ.VV, MSEQ.VX, MSEQ.VI, MSNE.VV, MSNE.VX, MSNE.VI, MSLTU.VV, MSLTU.VX, MSLT.VV, MSLT.VX, MSLEU.VV, MSLEU.VX, MSLEU.VI, MSLE.VV, MSLE.VX, MSLE.VI, MSGTU.VX, MSGTU.VI, MSGT.VX, MSGT.VI, MINU.VV, MINU.VX, MIN.VV, MIN.VX, MAXU.VV, MAXU.VX, MAX.VV, MAX.VX, MERGE.VV, MERGE.VX, MERGE.VI, SADDU.VV, SADDU.VX, SADDU.VI, SADD.VV, SADD.VX, SADD.VI, SSUBU.VV, SSUBU.VX, SSUB.VV, SSUB.VX, AADDU.VV, AADDU.VX, AADD.VV, AADD.VX, ASUBU.VV, ASUBU.VX, ASUB.VV, ASUB.VX, REDSUM.VV, WREDSUM.VV, WREDSUMU.VV, REDMINU.VV, REDMIN.VV, REDMAXU.VV, REDMAX.VV, FMERGE.VF, // zvbb BREV8.VV, BREV.VV, REV8.VV, CLZ.VV, CTZ.VV, CPOP.VV ) def generate(implicit p: Parameters) = new IntegerPipe()(p) } class IntegerPipe(implicit p: Parameters) extends PipelinedFunctionalUnit(1)(p) { val supported_insns = IntegerPipeFactory.insns val rvs1_eew = io.pipe(0).bits.rvs1_eew val rvs2_eew = io.pipe(0).bits.rvs2_eew val vd_eew = io.pipe(0).bits.vd_eew val ctrl = new VectorDecoder( io.pipe(0).bits.funct3, io.pipe(0).bits.funct6, io.pipe(0).bits.rs1, io.pipe(0).bits.rs2, supported_insns, Seq(UsesCmp, UsesNarrowingSext, UsesMinMax, UsesMerge, UsesSat, DoSub, WideningSext, Averaging, CarryIn, AlwaysCarryIn, CmpLess, Swap12, WritesAsMask, UsesBitSwap, UsesCountZeros)) io.iss.ready := new VectorDecoder(io.iss.op.funct3, io.iss.op.funct6, 0.U, 0.U, supported_insns, Nil).matched val carry_in = ctrl.bool(CarryIn) && (!io.pipe(0).bits.vm \|\| ctrl.bool(AlwaysCarryIn)) val sat_signed = io.pipe(0).bits.funct6(0) val sat_addu = io.pipe(0).bits.funct6(1,0) === 0.U val sat_subu = io.pipe(0).bits.funct6(1,0) === 2.U val rvs1_bytes = io.pipe(0).bits.rvs1_data.asTypeOf(Vec(dLenB, UInt(8.W))) val rvs2_bytes = io.pipe(0).bits.rvs2_data.asTypeOf(Vec(dLenB, UInt(8.W))) val in1_bytes = Mux(ctrl.bool(Swap12), rvs2_bytes, rvs1_bytes) val in2_bytes = Mux(ctrl.bool(Swap12), rvs1_bytes, rvs2_bytes) val narrow_vs1 = narrow2_expand(rvs1_bytes, rvs1_eew, (io.pipe(0).bits.eidx >> (dLenOffBits.U - vd_eew))(0), ctrl.bool(WideningSext)) val narrow_vs2 = narrow2_expand(rvs2_bytes, rvs2_eew, (io.pipe(0).bits.eidx >> (dLenOffBits.U - vd_eew))(0), ctrl.bool(WideningSext)) val add_mask_carry = VecInit.tabulate(4)({ eew => VecInit((0 until dLenB >> eew).map { i => io.pipe(0).bits.rmask(i) \| 0.U((1 << eew).W) }).asUInt })(rvs2_eew) val add_carry = Wire(Vec(dLenB, UInt(1.W))) val add_out = Wire(Vec(dLenB, UInt(8.W))) val merge_mask = VecInit.tabulate(4)({eew => FillInterleaved(1 << eew, io.pipe(0).bits.rmask((dLenB >> eew)-1,0))})(rvs2_eew) val merge_out = VecInit((0 until dLenB).map { i => Mux(merge_mask(i), rvs1_bytes(i), rvs2_bytes(i)) }).asUInt val carryborrow_res = VecInit.tabulate(4)({ eew => Fill(1 << eew, VecInit(add_carry.grouped(1 << eew).map(_.last).toSeq).asUInt) })(rvs1_eew) val adder_arr = Module(new AdderArray(dLenB)) adder_arr.io.in1 := Mux(rvs1_eew < vd_eew, narrow_vs1, in1_bytes) adder_arr.io.in2 := Mux(rvs2_eew < vd_eew, narrow_vs2, in2_bytes) adder_arr.io.incr.foreach(_ := false.B) adder_arr.io.avg := ctrl.bool(Averaging) adder_arr.io.eew := vd_eew adder_arr.io.rm := io.pipe(0).bits.vxrm adder_arr.io.mask_carry := add_mask_carry adder_arr.io.sub := ctrl.bool(DoSub) adder_arr.io.cmask := carry_in adder_arr.io.signed := io.pipe(0).bits.funct6(0) add_out := adder_arr.io.out add_carry := adder_arr.io.carry val cmp_arr = Module(new CompareArray(dLenB)) cmp_arr.io.in1 := in1_bytes cmp_arr.io.in2 := in2_bytes cmp_arr.io.eew := rvs1_eew cmp_arr.io.signed := io.pipe(0).bits.funct6(0) cmp_arr.io.less := ctrl.bool(CmpLess) cmp_arr.io.sle := io.pipe(0).bits.funct6(2,1) === 2.U cmp_arr.io.inv := io.pipe(0).bits.funct6(0) val minmax_out = VecInit(rvs1_bytes.zip(rvs2_bytes).zip(cmp_arr.io.minmax.asBools).map { case ((v1, v2), s) => Mux(s, v2, v1) }).asUInt val mask_out = Fill(8, Mux(ctrl.bool(UsesCmp), cmp_arr.io.result, carryborrow_res ^ Fill(dLenB, ctrl.bool(DoSub)))) val sat_arr = Module(new SaturatedSumArray(dLenB)) sat_arr.io.sum := add_out sat_arr.io.carry := add_carry sat_arr.io.in1_sign := rvs1_bytes.map(_(7)) sat_arr.io.in2_sign := rvs2_bytes.map(_(7)) sat_arr.io.sub := ctrl.bool(DoSub) sat_arr.io.eew := vd_eew sat_arr.io.signed := io.pipe(0).bits.funct6(0) val sat_out = sat_arr.io.out.asUInt val narrowing_ext_eew_mul = io.pipe(0).bits.vd_eew - rvs2_eew val narrowing_ext_in = (1 until 4).map { m => val w = dLen >> m val in = Wire(UInt(w.W)) val in_mul = io.pipe(0).bits.rvs2_data.asTypeOf(Vec(1 << m, UInt(w.W))) val sel = (io.pipe(0).bits.eidx >> (dLenOffBits.U - vd_eew))(m-1,0) in := in_mul(sel) in } val narrowing_ext_out = Mux1H((1 until 4).map { eew => (0 until eew).map { vs2_eew => (vd_eew === eew.U && rvs2_eew === vs2_eew.U) -> { val mul = eew - vs2_eew val in = narrowing_ext_in(mul-1).asTypeOf(Vec(dLenB >> eew, UInt((8 << vs2_eew).W))) val out = Wire(Vec(dLenB >> eew, UInt((8 << eew).W))) out.zip(in).foreach { case (l, r) => l := Cat( Fill((8 << eew) - (8 << vs2_eew), io.pipe(0).bits.rs1(0) && r((8 << vs2_eew)-1)), r) } out.asUInt } }}.flatten) val brev_bytes = VecInit(in2_bytes.map(b => Reverse(b))).asUInt val brev_elements = VecInit((0 until 4).map { eew => VecInit(in2_bytes.asTypeOf(Vec(dLenB >> eew, UInt((8 << eew).W))).map(b => Reverse(b))).asUInt })(vd_eew) val rev8_elements = VecInit((0 until 4).map { eew => VecInit(in2_bytes.asTypeOf(Vec(dLenB >> eew, Vec(1 << eew, UInt(8.W)))).map(b => VecInit(b.reverse))).asUInt })(vd_eew) val swap_out = Mux1H(Seq( (io.pipe(0).bits.rs1(1,0) === 0.U) -> brev_bytes, (io.pipe(0).bits.rs1(1,0) === 1.U) -> rev8_elements, (io.pipe(0).bits.rs1(1,0) === 2.U) -> brev_elements )) val tz_in = Mux(io.pipe(0).bits.rs1(0), in2_bytes, brev_elements.asTypeOf(Vec(dLenB, UInt(8.W)))) val tz_8b = tz_in.map(b => (b === 0.U, (PriorityEncoderOH(1.U ## b) - 1.U)(7,0))) val tz_16b = tz_8b.grouped(2).toSeq.map(t => (t.map(_._1).andR, Mux(t(0)._1, t(1)._2 ## ~(0.U(8.W)), t(0)._2)) ) val tz_32b = tz_16b.grouped(2).toSeq.map(t => (t.map(_._1).andR, Mux(t(0)._1, t(1)._2 ## ~(0.U(16.W)), t(0)._2)) ) val tz_64b = tz_32b.grouped(2).toSeq.map(t => (t.map(_._1).andR, Mux(t(0)._1, t(1)._2 ## ~(0.U(32.W)), t(0)._2)) ) val tz_out = WireInit(VecInit( VecInit(tz_8b.map(_._2)).asUInt, VecInit(tz_16b.map(_._2)).asUInt, VecInit(tz_32b.map(_._2)).asUInt, VecInit(tz_64b.map(_._2)).asUInt )(vd_eew).asTypeOf(Vec(dLenB, UInt(8.W)))) val cpop_in = Mux(io.pipe(0).bits.rs1(1), in2_bytes, tz_out) val cpop_8b = cpop_in.map(b => PopCount(b)) val cpop_16b = cpop_8b.grouped(2).toSeq.map(_.reduce(_ +& _)) val cpop_32b = cpop_16b.grouped(2).toSeq.map(_.reduce(_ +& _)) val cpop_64b = cpop_32b.grouped(2).toSeq.map(_.reduce(_ +& _)) val cpops = Seq(cpop_8b, cpop_16b, cpop_32b, cpop_64b) val count_out = WireInit(VecInit((0 until 4).map { eew => val out = Wire(Vec(dLenB >> eew, UInt((8 << eew).W))) out := VecInit(cpops(eew)) out.asUInt })(vd_eew)) val outs = Seq( (ctrl.bool(UsesNarrowingSext) , narrowing_ext_out), (ctrl.bool(WritesAsMask) , mask_out), (ctrl.bool(UsesMinMax) , minmax_out), (ctrl.bool(UsesMerge) , merge_out), (ctrl.bool(UsesSat) , sat_out), (ctrl.bool(UsesBitSwap) , swap_out), (ctrl.bool(UsesCountZeros) , count_out) ) val out = Mux(outs.map(_._1).orR, Mux1H(outs), add_out.asUInt) val mask_write_offset = VecInit.tabulate(4)({ eew => Cat(io.pipe(0).bits.eidx(log2Ceil(dLen)-1, dLenOffBits-eew), 0.U((dLenOffBits-eew).W)) })(rvs1_eew) val mask_write_mask = (VecInit.tabulate(4)({ eew => VecInit(io.pipe(0).bits.wmask.asBools.grouped(1 << eew).map(_.head).toSeq).asUInt })(rvs1_eew) << mask_write_offset)(dLen-1,0) io.pipe0_stall := false.B io.write.valid := io.pipe(0).valid io.write.bits.eg := io.pipe(0).bits.wvd_eg io.write.bits.mask := Mux(ctrl.bool(WritesAsMask), mask_write_mask, FillInterleaved(8, io.pipe(0).bits.wmask)) io.write.bits.data := out val sat_vxsat = Mux(ctrl.bool(UsesSat) , sat_arr.io.set_vxsat , 0.U) & io.pipe(0).bits.wmask io.set_vxsat := io.pipe(0).valid && (sat_vxsat =/= 0.U) io.set_fflags.valid := false.B io.set_fflags.bits := DontCare io.scalar_write.valid := false.B io.scalar_write.bits := DontCare }	module AdderArray( // @[IntegerPipe.scala:12:7] input [7:0] io_in1_0, // @[IntegerPipe.scala:13:14] input [7:0] io_in1_1, // @[IntegerPipe.scala:13:14] input [7:0] io_in1_2, // @[IntegerPipe.scala:13:14] input [7:0] io_in1_3, // @[IntegerPipe.scala:13:14] input [7:0] io_in1_4, // @[IntegerPipe.scala:13:14] input [7:0] io_in1_5, // @[IntegerPipe.scala:13:14] input [7:0] io_in1_6, // @[IntegerPipe.scala:13:14] input [7:0] io_in1_7, // @[IntegerPipe.scala:13:14] input [7:0] io_in1_8, // @[IntegerPipe.scala:13:14] input [7:0] io_in1_9, // @[IntegerPipe.scala:13:14] input [7:0] io_in1_10, // @[IntegerPipe.scala:13:14] input [7:0] io_in1_11, // @[IntegerPipe.scala:13:14] input [7:0] io_in1_12, // @[IntegerPipe.scala:13:14] input [7:0] io_in1_13, // @[IntegerPipe.scala:13:14] input [7:0] io_in1_14, // @[IntegerPipe.scala:13:14] input [7:0] io_in1_15, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_0, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_1, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_2, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_3, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_4, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_5, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_6, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_7, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_8, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_9, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_10, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_11, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_12, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_13, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_14, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_15, // @[IntegerPipe.scala:13:14] input io_incr_0, // @[IntegerPipe.scala:13:14] input io_incr_1, // @[IntegerPipe.scala:13:14] input io_incr_2, // @[IntegerPipe.scala:13:14] input io_incr_3, // @[IntegerPipe.scala:13:14] input io_incr_4, // @[IntegerPipe.scala:13:14] input io_incr_5, // @[IntegerPipe.scala:13:14] input io_incr_6, // @[IntegerPipe.scala:13:14] input io_incr_7, // @[IntegerPipe.scala:13:14] input io_incr_8, // @[IntegerPipe.scala:13:14] input io_incr_9, // @[IntegerPipe.scala:13:14] input io_incr_10, // @[IntegerPipe.scala:13:14] input io_incr_11, // @[IntegerPipe.scala:13:14] input io_incr_12, // @[IntegerPipe.scala:13:14] input io_incr_13, // @[IntegerPipe.scala:13:14] input io_incr_14, // @[IntegerPipe.scala:13:14] input io_incr_15, // @[IntegerPipe.scala:13:14] input [15:0] io_mask_carry, // @[IntegerPipe.scala:13:14] input io_signed, // @[IntegerPipe.scala:13:14] input [1:0] io_eew, // @[IntegerPipe.scala:13:14] input io_avg, // @[IntegerPipe.scala:13:14] input [1:0] io_rm, // @[IntegerPipe.scala:13:14] input io_sub, // @[IntegerPipe.scala:13:14] input io_cmask, // @[IntegerPipe.scala:13:14] output [7:0] io_out_0, // @[IntegerPipe.scala:13:14] output [7:0] io_out_1, // @[IntegerPipe.scala:13:14] output [7:0] io_out_2, // @[IntegerPipe.scala:13:14] output [7:0] io_out_3, // @[IntegerPipe.scala:13:14] output [7:0] io_out_4, // @[IntegerPipe.scala:13:14] output [7:0] io_out_5, // @[IntegerPipe.scala:13:14] output [7:0] io_out_6, // @[IntegerPipe.scala:13:14] output [7:0] io_out_7, // @[IntegerPipe.scala:13:14] output [7:0] io_out_8, // @[IntegerPipe.scala:13:14] output [7:0] io_out_9, // @[IntegerPipe.scala:13:14] output [7:0] io_out_10, // @[IntegerPipe.scala:13:14] output [7:0] io_out_11, // @[IntegerPipe.scala:13:14] output [7:0] io_out_12, // @[IntegerPipe.scala:13:14] output [7:0] io_out_13, // @[IntegerPipe.scala:13:14] output [7:0] io_out_14, // @[IntegerPipe.scala:13:14] output [7:0] io_out_15, // @[IntegerPipe.scala:13:14] output io_carry_0, // @[IntegerPipe.scala:13:14] output io_carry_1, // @[IntegerPipe.scala:13:14] output io_carry_2, // @[IntegerPipe.scala:13:14] output io_carry_3, // @[IntegerPipe.scala:13:14] output io_carry_4, // @[IntegerPipe.scala:13:14] output io_carry_5, // @[IntegerPipe.scala:13:14] output io_carry_6, // @[IntegerPipe.scala:13:14] output io_carry_7, // @[IntegerPipe.scala:13:14] output io_carry_8, // @[IntegerPipe.scala:13:14] output io_carry_9, // @[IntegerPipe.scala:13:14] output io_carry_10, // @[IntegerPipe.scala:13:14] output io_carry_11, // @[IntegerPipe.scala:13:14] output io_carry_12, // @[IntegerPipe.scala:13:14] output io_carry_13, // @[IntegerPipe.scala:13:14] output io_carry_14, // @[IntegerPipe.scala:13:14] output io_carry_15 // @[IntegerPipe.scala:13:14] ); wire [3:0][15:0] _GEN = '{16'hFEFE, 16'hEEEE, 16'hAAAA, 16'h0}; // @[IntegerPipe.scala:33:43] wire [72:0] carry_clear = io_avg ? {_GEN[io_eew][8], 8'hFF, _GEN[io_eew][7], 8'hFF, _GEN[io_eew][6], 8'hFF, _GEN[io_eew][5], 8'hFF, _GEN[io_eew][4], 8'hFF, _GEN[io_eew][3], 8'hFF, _GEN[io_eew][2], 8'hFF, _GEN[io_eew][1], 8'hFF, _GEN[io_eew][0]} : 73'h1FFFFFFFFFFFFFFFFFF; // @[IntegerPipe.scala:33:{24,43}] wire [72:0] carry_restore = io_avg ? {_GEN[io_eew][8], 8'h0, _GEN[io_eew][7], 8'h0, _GEN[io_eew][6], 8'h0, _GEN[io_eew][5], 8'h0, _GEN[io_eew][4], 8'h0, _GEN[io_eew][3], 8'h0, _GEN[io_eew][2], 8'h0, _GEN[io_eew][1], 8'h0, _GEN[io_eew][0]} : 73'h0; // @[IntegerPipe.scala:33:43, :34:26] wire [3:0][127:0] _GEN_0 = {{{io_signed & io_in1_15[7], io_in1_15, io_in1_14, io_in1_13, io_in1_12, io_in1_11, io_in1_10, io_in1_9, io_in1_8[7:1], io_signed & io_in1_7[7], io_in1_7, io_in1_6, io_in1_5, io_in1_4, io_in1_3, io_in1_2, io_in1_1, io_in1_0[7:1]}}, {{io_signed & io_in1_15[7], io_in1_15, io_in1_14, io_in1_13, io_in1_12[7:1], io_signed & io_in1_11[7], io_in1_11, io_in1_10, io_in1_9, io_in1_8[7:1], io_signed & io_in1_7[7], io_in1_7, io_in1_6, io_in1_5, io_in1_4[7:1], io_signed & io_in1_3[7], io_in1_3, io_in1_2, io_in1_1, io_in1_0[7:1]}}, {{io_signed & io_in1_15[7], io_in1_15, io_in1_14[7:1], io_signed & io_in1_13[7], io_in1_13, io_in1_12[7:1], io_signed & io_in1_11[7], io_in1_11, io_in1_10[7:1], io_signed & io_in1_9[7], io_in1_9, io_in1_8[7:1], io_signed & io_in1_7[7], io_in1_7, io_in1_6[7:1], io_signed & io_in1_5[7], io_in1_5, io_in1_4[7:1], io_signed & io_in1_3[7], io_in1_3, io_in1_2[7:1], io_signed & io_in1_1[7], io_in1_1, io_in1_0[7:1]}}, {{io_signed & io_in1_15[7], io_in1_15[7:1], io_signed & io_in1_14[7], io_in1_14[7:1], io_signed & io_in1_13[7], io_in1_13[7:1], io_signed & io_in1_12[7], io_in1_12[7:1], io_signed & io_in1_11[7], io_in1_11[7:1], io_signed & io_in1_10[7], io_in1_10[7:1], io_signed & io_in1_9[7], io_in1_9[7:1], io_signed & io_in1_8[7], io_in1_8[7:1], io_signed & io_in1_7[7], io_in1_7[7:1], io_signed & io_in1_6[7], io_in1_6[7:1], io_signed & io_in1_5[7], io_in1_5[7:1], io_signed & io_in1_4[7], io_in1_4[7:1], io_signed & io_in1_3[7], io_in1_3[7:1], io_signed & io_in1_2[7], io_in1_2[7:1], io_signed & io_in1_1[7], io_in1_1[7:1], io_signed & io_in1_0[7], io_in1_0[7:1]}}}; // @[IntegerPipe.scala:37:{91,95,112,119}, :38:21] wire [3:0][127:0] _GEN_1 = {{{io_signed & io_in2_15[7], io_in2_15, io_in2_14, io_in2_13, io_in2_12, io_in2_11, io_in2_10, io_in2_9, io_in2_8[7:1], io_signed & io_in2_7[7], io_in2_7, io_in2_6, io_in2_5, io_in2_4, io_in2_3, io_in2_2, io_in2_1, io_in2_0[7:1]}}, {{io_signed & io_in2_15[7], io_in2_15, io_in2_14, io_in2_13, io_in2_12[7:1], io_signed & io_in2_11[7], io_in2_11, io_in2_10, io_in2_9, io_in2_8[7:1], io_signed & io_in2_7[7], io_in2_7, io_in2_6, io_in2_5, io_in2_4[7:1], io_signed & io_in2_3[7], io_in2_3, io_in2_2, io_in2_1, io_in2_0[7:1]}}, {{io_signed & io_in2_15[7], io_in2_15, io_in2_14[7:1], io_signed & io_in2_13[7], io_in2_13, io_in2_12[7:1], io_signed & io_in2_11[7], io_in2_11, io_in2_10[7:1], io_signed & io_in2_9[7], io_in2_9, io_in2_8[7:1], io_signed & io_in2_7[7], io_in2_7, io_in2_6[7:1], io_signed & io_in2_5[7], io_in2_5, io_in2_4[7:1], io_signed & io_in2_3[7], io_in2_3, io_in2_2[7:1], io_signed & io_in2_1[7], io_in2_1, io_in2_0[7:1]}}, {{io_signed & io_in2_15[7], io_in2_15[7:1], io_signed & io_in2_14[7], io_in2_14[7:1], io_signed & io_in2_13[7], io_in2_13[7:1], io_signed & io_in2_12[7], io_in2_12[7:1], io_signed & io_in2_11[7], io_in2_11[7:1], io_signed & io_in2_10[7], io_in2_10[7:1], io_signed & io_in2_9[7], io_in2_9[7:1], io_signed & io_in2_8[7], io_in2_8[7:1], io_signed & io_in2_7[7], io_in2_7[7:1], io_signed & io_in2_6[7], io_in2_6[7:1], io_signed & io_in2_5[7], io_in2_5[7:1], io_signed & io_in2_4[7], io_in2_4[7:1], io_signed & io_in2_3[7], io_in2_3[7:1], io_signed & io_in2_2[7], io_in2_2[7:1], io_signed & io_in2_1[7], io_in2_1[7:1], io_signed & io_in2_0[7], io_in2_0[7:1]}}}; // @[IntegerPipe.scala:40:{91,95,112,119}, :41:21] wire _in2_dummy_bits_bit_T_2 = io_sub ^ io_mask_carry[0]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire _in2_dummy_bits_bit_T_6 = io_sub ^ io_mask_carry[1]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire _in2_dummy_bits_bit_T_10 = io_sub ^ io_mask_carry[2]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire _in2_dummy_bits_bit_T_14 = io_sub ^ io_mask_carry[3]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire _in2_dummy_bits_bit_T_18 = io_sub ^ io_mask_carry[4]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire _in2_dummy_bits_bit_T_22 = io_sub ^ io_mask_carry[5]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire _in2_dummy_bits_bit_T_26 = io_sub ^ io_mask_carry[6]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire _in2_dummy_bits_bit_T_30 = io_sub ^ io_mask_carry[7]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire [1:0] _round_incrs_sum_T_77 = {2{io_sub}}; // @[IntegerPipe.scala:76:44] wire [1:0] _GEN_2 = {1'h0, io_sub}; // @[IntegerPipe.scala:76:57] wire [1:0] round_incrs_sum = io_in2_0[1:0] + (io_in1_0[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire _GEN_3 = io_rm != 2'h2; // @[Rounding.scala:8:106] wire [1:0] round_incrs_sum_1 = io_in2_1[1:0] + (io_in1_1[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire [1:0] round_incrs_sum_2 = io_in2_2[1:0] + (io_in1_2[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire [1:0] round_incrs_sum_3 = io_in2_3[1:0] + (io_in1_3[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire [1:0] round_incrs_sum_4 = io_in2_4[1:0] + (io_in1_4[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire [1:0] round_incrs_sum_5 = io_in2_5[1:0] + (io_in1_5[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire [1:0] round_incrs_sum_6 = io_in2_6[1:0] + (io_in1_6[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire [1:0] round_incrs_sum_7 = io_in2_7[1:0] + (io_in1_7[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire [7:0] _in1_constructed_T_45 = {8{io_sub}}; // @[IntegerPipe.scala:82:96] wire [72:0] _sum_T = {1'h0, (io_avg ? _GEN_0[io_eew][63:56] : io_in1_7) ^ _in1_constructed_T_45, _GEN[io_eew][7] \| (io_avg ? (io_sub ^ io_in1_7[0]) & io_in2_7[0] \| (io_sub ^ io_in1_7[0] ^ io_in2_7[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_30), (io_avg ? _GEN_0[io_eew][55:48] : io_in1_6) ^ _in1_constructed_T_45, _GEN[io_eew][6] \| (io_avg ? (io_sub ^ io_in1_6[0]) & io_in2_6[0] \| (io_sub ^ io_in1_6[0] ^ io_in2_6[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_26), (io_avg ? _GEN_0[io_eew][47:40] : io_in1_5) ^ _in1_constructed_T_45, _GEN[io_eew][5] \| (io_avg ? (io_sub ^ io_in1_5[0]) & io_in2_5[0] \| (io_sub ^ io_in1_5[0] ^ io_in2_5[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_22), (io_avg ? _GEN_0[io_eew][39:32] : io_in1_4) ^ _in1_constructed_T_45, _GEN[io_eew][4] \| (io_avg ? (io_sub ^ io_in1_4[0]) & io_in2_4[0] \| (io_sub ^ io_in1_4[0] ^ io_in2_4[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_18), (io_avg ? _GEN_0[io_eew][31:24] : io_in1_3) ^ _in1_constructed_T_45, _GEN[io_eew][3] \| (io_avg ? (io_sub ^ io_in1_3[0]) & io_in2_3[0] \| (io_sub ^ io_in1_3[0] ^ io_in2_3[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_14), (io_avg ? _GEN_0[io_eew][23:16] : io_in1_2) ^ _in1_constructed_T_45, _GEN[io_eew][2] \| (io_avg ? (io_sub ^ io_in1_2[0]) & io_in2_2[0] \| (io_sub ^ io_in1_2[0] ^ io_in2_2[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_10), (io_avg ? _GEN_0[io_eew][15:8] : io_in1_1) ^ _in1_constructed_T_45, _GEN[io_eew][1] \| (io_avg ? (io_sub ^ io_in1_1[0]) & io_in2_1[0] \| (io_sub ^ io_in1_1[0] ^ io_in2_1[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_6), (io_avg ? _GEN_0[io_eew][7:0] : io_in1_0) ^ _in1_constructed_T_45, _GEN[io_eew][0] \| (io_avg ? (io_sub ^ io_in1_0[0]) & io_in2_0[0] \| (io_sub ^ io_in1_0[0] ^ io_in2_0[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_2)} + {1'h0, io_avg ? _GEN_1[io_eew][63:56] : io_in2_7, ~(_GEN[io_eew][7]) & (io_avg ? (io_sub ^ io_in1_7[0]) & io_in2_7[0] \| (io_sub ^ io_in1_7[0] ^ io_in2_7[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_30), io_avg ? _GEN_1[io_eew][55:48] : io_in2_6, ~(_GEN[io_eew][6]) & (io_avg ? (io_sub ^ io_in1_6[0]) & io_in2_6[0] \| (io_sub ^ io_in1_6[0] ^ io_in2_6[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_26), io_avg ? _GEN_1[io_eew][47:40] : io_in2_5, ~(_GEN[io_eew][5]) & (io_avg ? (io_sub ^ io_in1_5[0]) & io_in2_5[0] \| (io_sub ^ io_in1_5[0] ^ io_in2_5[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_22), io_avg ? _GEN_1[io_eew][39:32] : io_in2_4, ~(_GEN[io_eew][4]) & (io_avg ? (io_sub ^ io_in1_4[0]) & io_in2_4[0] \| (io_sub ^ io_in1_4[0] ^ io_in2_4[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_18), io_avg ? _GEN_1[io_eew][31:24] : io_in2_3, ~(_GEN[io_eew][3]) & (io_avg ? (io_sub ^ io_in1_3[0]) & io_in2_3[0] \| (io_sub ^ io_in1_3[0] ^ io_in2_3[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_14), io_avg ? _GEN_1[io_eew][23:16] : io_in2_2, ~(_GEN[io_eew][2]) & (io_avg ? (io_sub ^ io_in1_2[0]) & io_in2_2[0] \| (io_sub ^ io_in1_2[0] ^ io_in2_2[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_10), io_avg ? _GEN_1[io_eew][15:8] : io_in2_1, ~(_GEN[io_eew][1]) & (io_avg ? (io_sub ^ io_in1_1[0]) & io_in2_1[0] \| (io_sub ^ io_in1_1[0] ^ io_in2_1[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_6), io_avg ? _GEN_1[io_eew][7:0] : io_in2_0, ~(_GEN[io_eew][0]) & (io_avg ? (io_sub ^ io_in1_0[0]) & io_in2_0[0] \| (io_sub ^ io_in1_0[0] ^ io_in2_0[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_2)}; // @[IntegerPipe.scala:33:43, :38:21, :41:21, :43:16, :44:16, :53:{36,42}, :61:{32,36,41,45,50,62,71,80}, :62:{20,30,40,52,62}, :63:{12,33}, :69:{32,41,50,62,71,80}, :70:{30,40,52}, :71:{12,33}, :82:{90,96}, :87:34] wire [72:0] sum = (carry_clear & _sum_T \| carry_restore) + {8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum_7[1]) & round_incrs_sum_7[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum_7) : round_incrs_sum_7[0])) & ~(_GEN[io_eew][7]), 8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum_6[1]) & round_incrs_sum_6[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum_6) : round_incrs_sum_6[0])) & ~(_GEN[io_eew][6]), 8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum_5[1]) & round_incrs_sum_5[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum_5) : round_incrs_sum_5[0])) & ~(_GEN[io_eew][5]), 8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum_4[1]) & round_incrs_sum_4[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum_4) : round_incrs_sum_4[0])) & ~(_GEN[io_eew][4]), 8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum_3[1]) & round_incrs_sum_3[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum_3) : round_incrs_sum_3[0])) & ~(_GEN[io_eew][3]), 8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum_2[1]) & round_incrs_sum_2[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum_2) : round_incrs_sum_2[0])) & ~(_GEN[io_eew][2]), 8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum_1[1]) & round_incrs_sum_1[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum_1) : round_incrs_sum_1[0])) & ~(_GEN[io_eew][1]), 8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum[1]) & round_incrs_sum[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum) : round_incrs_sum[0])) & ~(_GEN[io_eew][0]), 1'h0} + {8'h0, ~(_GEN[io_eew][7]) & io_incr_7, 8'h0, ~(_GEN[io_eew][6]) & io_incr_6, 8'h0, ~(_GEN[io_eew][5]) & io_incr_5, 8'h0, ~(_GEN[io_eew][4]) & io_incr_4, 8'h0, ~(_GEN[io_eew][3]) & io_incr_3, 8'h0, ~(_GEN[io_eew][2]) & io_incr_2, 8'h0, ~(_GEN[io_eew][1]) & io_incr_1, 8'h0, ~(_GEN[io_eew][0]) & io_incr_0, 1'h0}; // @[IntegerPipe.scala:33:{24,43}, :34:26, :53:{36,42}, :76:{26,57}, :77:{30,67,75,86,88}, :85:110, :87:{34,54,69,86,101}] wire _in2_dummy_bits_bit_T_34 = io_sub ^ io_mask_carry[8]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire _in2_dummy_bits_bit_T_38 = io_sub ^ io_mask_carry[9]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire _in2_dummy_bits_bit_T_42 = io_sub ^ io_mask_carry[10]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire _in2_dummy_bits_bit_T_46 = io_sub ^ io_mask_carry[11]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire _in2_dummy_bits_bit_T_50 = io_sub ^ io_mask_carry[12]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire _in2_dummy_bits_bit_T_54 = io_sub ^ io_mask_carry[13]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire _in2_dummy_bits_bit_T_58 = io_sub ^ io_mask_carry[14]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire _in2_dummy_bits_bit_T_62 = io_sub ^ io_mask_carry[15]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire [1:0] round_incrs_sum_8 = io_in2_8[1:0] + (io_in1_8[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire [1:0] round_incrs_sum_9 = io_in2_9[1:0] + (io_in1_9[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire [1:0] round_incrs_sum_10 = io_in2_10[1:0] + (io_in1_10[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire [1:0] round_incrs_sum_11 = io_in2_11[1:0] + (io_in1_11[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire [1:0] round_incrs_sum_12 = io_in2_12[1:0] + (io_in1_12[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire [1:0] round_incrs_sum_13 = io_in2_13[1:0] + (io_in1_13[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire [1:0] round_incrs_sum_14 = io_in2_14[1:0] + (io_in1_14[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire [1:0] round_incrs_sum_15 = io_in2_15[1:0] + (io_in1_15[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire [72:0] _sum_T_4 = {1'h0, (io_avg ? _GEN_0[io_eew][127:120] : io_in1_15) ^ _in1_constructed_T_45, _GEN[io_eew][15] \| (io_avg ? (io_sub ^ io_in1_15[0]) & io_in2_15[0] \| (io_sub ^ io_in1_15[0] ^ io_in2_15[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_62), (io_avg ? _GEN_0[io_eew][119:112] : io_in1_14) ^ _in1_constructed_T_45, _GEN[io_eew][14] \| (io_avg ? (io_sub ^ io_in1_14[0]) & io_in2_14[0] \| (io_sub ^ io_in1_14[0] ^ io_in2_14[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_58), (io_avg ? _GEN_0[io_eew][111:104] : io_in1_13) ^ _in1_constructed_T_45, _GEN[io_eew][13] \| (io_avg ? (io_sub ^ io_in1_13[0]) & io_in2_13[0] \| (io_sub ^ io_in1_13[0] ^ io_in2_13[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_54), (io_avg ? _GEN_0[io_eew][103:96] : io_in1_12) ^ _in1_constructed_T_45, _GEN[io_eew][12] \| (io_avg ? (io_sub ^ io_in1_12[0]) & io_in2_12[0] \| (io_sub ^ io_in1_12[0] ^ io_in2_12[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_50), (io_avg ? _GEN_0[io_eew][95:88] : io_in1_11) ^ _in1_constructed_T_45, _GEN[io_eew][11] \| (io_avg ? (io_sub ^ io_in1_11[0]) & io_in2_11[0] \| (io_sub ^ io_in1_11[0] ^ io_in2_11[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_46), (io_avg ? _GEN_0[io_eew][87:80] : io_in1_10) ^ _in1_constructed_T_45, _GEN[io_eew][10] \| (io_avg ? (io_sub ^ io_in1_10[0]) & io_in2_10[0] \| (io_sub ^ io_in1_10[0] ^ io_in2_10[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_42), (io_avg ? _GEN_0[io_eew][79:72] : io_in1_9) ^ _in1_constructed_T_45, _GEN[io_eew][9] \| (io_avg ? (io_sub ^ io_in1_9[0]) & io_in2_9[0] \| (io_sub ^ io_in1_9[0] ^ io_in2_9[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_38), (io_avg ? _GEN_0[io_eew][71:64] : io_in1_8) ^ _in1_constructed_T_45, _GEN[io_eew][8] \| (io_avg ? (io_sub ^ io_in1_8[0]) & io_in2_8[0] \| (io_sub ^ io_in1_8[0] ^ io_in2_8[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_34)} + {1'h0, io_avg ? _GEN_1[io_eew][127:120] : io_in2_15, ~(_GEN[io_eew][15]) & (io_avg ? (io_sub ^ io_in1_15[0]) & io_in2_15[0] \| (io_sub ^ io_in1_15[0] ^ io_in2_15[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_62), io_avg ? _GEN_1[io_eew][119:112] : io_in2_14, ~(_GEN[io_eew][14]) & (io_avg ? (io_sub ^ io_in1_14[0]) & io_in2_14[0] \| (io_sub ^ io_in1_14[0] ^ io_in2_14[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_58), io_avg ? _GEN_1[io_eew][111:104] : io_in2_13, ~(_GEN[io_eew][13]) & (io_avg ? (io_sub ^ io_in1_13[0]) & io_in2_13[0] \| (io_sub ^ io_in1_13[0] ^ io_in2_13[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_54), io_avg ? _GEN_1[io_eew][103:96] : io_in2_12, ~(_GEN[io_eew][12]) & (io_avg ? (io_sub ^ io_in1_12[0]) & io_in2_12[0] \| (io_sub ^ io_in1_12[0] ^ io_in2_12[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_50), io_avg ? _GEN_1[io_eew][95:88] : io_in2_11, ~(_GEN[io_eew][11]) & (io_avg ? (io_sub ^ io_in1_11[0]) & io_in2_11[0] \| (io_sub ^ io_in1_11[0] ^ io_in2_11[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_46), io_avg ? _GEN_1[io_eew][87:80] : io_in2_10, ~(_GEN[io_eew][10]) & (io_avg ? (io_sub ^ io_in1_10[0]) & io_in2_10[0] \| (io_sub ^ io_in1_10[0] ^ io_in2_10[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_42), io_avg ? _GEN_1[io_eew][79:72] : io_in2_9, ~(_GEN[io_eew][9]) & (io_avg ? (io_sub ^ io_in1_9[0]) & io_in2_9[0] \| (io_sub ^ io_in1_9[0] ^ io_in2_9[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_38), io_avg ? _GEN_1[io_eew][71:64] : io_in2_8, ~(_GEN[io_eew][8]) & (io_avg ? (io_sub ^ io_in1_8[0]) & io_in2_8[0] \| (io_sub ^ io_in1_8[0] ^ io_in2_8[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_34)}; // @[IntegerPipe.scala:33:43, :38:21, :41:21, :43:16, :44:16, :53:{36,42}, :61:{32,36,41,45,50,62,71,80}, :62:{20,30,40,52,62}, :63:{12,33}, :69:{32,41,50,62,71,80}, :70:{30,40,52}, :71:{12,33}, :82:{90,96}, :87:34] wire [72:0] sum_1 = (carry_clear & _sum_T_4 \| carry_restore) + {8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum_15[1]) & round_incrs_sum_15[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum_15) : round_incrs_sum_15[0])) & ~(_GEN[io_eew][15]), 8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum_14[1]) & round_incrs_sum_14[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum_14) : round_incrs_sum_14[0])) & ~(_GEN[io_eew][14]), 8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum_13[1]) & round_incrs_sum_13[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum_13) : round_incrs_sum_13[0])) & ~(_GEN[io_eew][13]), 8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum_12[1]) & round_incrs_sum_12[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum_12) : round_incrs_sum_12[0])) & ~(_GEN[io_eew][12]), 8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum_11[1]) & round_incrs_sum_11[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum_11) : round_incrs_sum_11[0])) & ~(_GEN[io_eew][11]), 8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum_10[1]) & round_incrs_sum_10[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum_10) : round_incrs_sum_10[0])) & ~(_GEN[io_eew][10]), 8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum_9[1]) & round_incrs_sum_9[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum_9) : round_incrs_sum_9[0])) & ~(_GEN[io_eew][9]), 8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum_8[1]) & round_incrs_sum_8[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum_8) : round_incrs_sum_8[0])) & ~(_GEN[io_eew][8]), 1'h0} + {8'h0, ~(_GEN[io_eew][15]) & io_incr_15, 8'h0, ~(_GEN[io_eew][14]) & io_incr_14, 8'h0, ~(_GEN[io_eew][13]) & io_incr_13, 8'h0, ~(_GEN[io_eew][12]) & io_incr_12, 8'h0, ~(_GEN[io_eew][11]) & io_incr_11, 8'h0, ~(_GEN[io_eew][10]) & io_incr_10, 8'h0, ~(_GEN[io_eew][9]) & io_incr_9, 8'h0, ~(_GEN[io_eew][8]) & io_incr_8, 1'h0}; // @[IntegerPipe.scala:33:{24,43}, :34:26, :53:{36,42}, :76:{26,57}, :77:{30,67,75,86,88}, :85:110, :87:{34,54,69,86,101}] assign io_out_0 = sum[8:1]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_out_1 = sum[17:10]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_out_2 = sum[26:19]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_out_3 = sum[35:28]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_out_4 = sum[44:37]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_out_5 = sum[53:46]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_out_6 = sum[62:55]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_out_7 = sum[71:64]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_out_8 = sum_1[8:1]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_out_9 = sum_1[17:10]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_out_10 = sum_1[26:19]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_out_11 = sum_1[35:28]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_out_12 = sum_1[44:37]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_out_13 = sum_1[53:46]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_out_14 = sum_1[62:55]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_out_15 = sum_1[71:64]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_carry_0 = sum[9]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] assign io_carry_1 = sum[18]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] assign io_carry_2 = sum[27]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] assign io_carry_3 = sum[36]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] assign io_carry_4 = sum[45]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] assign io_carry_5 = sum[54]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] assign io_carry_6 = sum[63]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] assign io_carry_7 = sum[72]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] assign io_carry_8 = sum_1[9]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] assign io_carry_9 = sum_1[18]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] assign io_carry_10 = sum_1[27]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] assign io_carry_11 = sum_1[36]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] assign io_carry_12 = sum_1[45]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] assign io_carry_13 = sum_1[54]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] assign io_carry_14 = sum_1[63]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] assign io_carry_15 = sum_1[72]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module IntSyncSyncCrossingSink_n1x1_3( // @[Crossing.scala:96:9] input auto_in_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_0 // @[LazyModuleImp.scala:107:25] ); wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:96:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:96:9] wire nodeOut_0; // @[MixedNode.scala:542:17] wire auto_out_0_0; // @[Crossing.scala:96:9] assign nodeOut_0 = nodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:96:9] assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:96:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async } File AsyncCrossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, NodeHandle} import freechips.rocketchip.prci.{AsynchronousCrossing} import freechips.rocketchip.subsystem.CrossingWrapper import freechips.rocketchip.util.{AsyncQueueParams, ToAsyncBundle, FromAsyncBundle, Pow2ClockDivider, property} class TLAsyncCrossingSource(sync: Option[Int])(implicit p: Parameters) extends LazyModule { def this(x: Int)(implicit p: Parameters) = this(Some(x)) def this()(implicit p: Parameters) = this(None) val node = TLAsyncSourceNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLAsyncCrossingSource") ++ node.in.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val bce = edgeIn.manager.anySupportAcquireB && edgeIn.client.anySupportProbe val psync = sync.getOrElse(edgeOut.manager.async.sync) val params = edgeOut.manager.async.copy(sync = psync) out.a <> ToAsyncBundle(in.a, params) in.d <> FromAsyncBundle(out.d, psync) property.cover(in.a, "TL_ASYNC_CROSSING_SOURCE_A", "MemorySystem;;TLAsyncCrossingSource Channel A") property.cover(in.d, "TL_ASYNC_CROSSING_SOURCE_D", "MemorySystem;;TLAsyncCrossingSource Channel D") if (bce) { in.b <> FromAsyncBundle(out.b, psync) out.c <> ToAsyncBundle(in.c, params) out.e <> ToAsyncBundle(in.e, params) property.cover(in.b, "TL_ASYNC_CROSSING_SOURCE_B", "MemorySystem;;TLAsyncCrossingSource Channel B") property.cover(in.c, "TL_ASYNC_CROSSING_SOURCE_C", "MemorySystem;;TLAsyncCrossingSource Channel C") property.cover(in.e, "TL_ASYNC_CROSSING_SOURCE_E", "MemorySystem;;TLAsyncCrossingSource Channel E") } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ridx := 0.U out.c.widx := 0.U out.e.widx := 0.U } } } } class TLAsyncCrossingSink(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) extends LazyModule { val node = TLAsyncSinkNode(params) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLAsyncCrossingSink") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val bce = edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe out.a <> FromAsyncBundle(in.a, params.sync) in.d <> ToAsyncBundle(out.d, params) property.cover(out.a, "TL_ASYNC_CROSSING_SINK_A", "MemorySystem;;TLAsyncCrossingSink Channel A") property.cover(out.d, "TL_ASYNC_CROSSING_SINK_D", "MemorySystem;;TLAsyncCrossingSink Channel D") if (bce) { in.b <> ToAsyncBundle(out.b, params) out.c <> FromAsyncBundle(in.c, params.sync) out.e <> FromAsyncBundle(in.e, params.sync) property.cover(out.b, "TL_ASYNC_CROSSING_SINK_B", "MemorySystem;;TLAsyncCrossingSinkChannel B") property.cover(out.c, "TL_ASYNC_CROSSING_SINK_C", "MemorySystem;;TLAsyncCrossingSink Channel C") property.cover(out.e, "TL_ASYNC_CROSSING_SINK_E", "MemorySystem;;TLAsyncCrossingSink Channel E") } else { in.b.widx := 0.U in.c.ridx := 0.U in.e.ridx := 0.U out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLAsyncCrossingSource { def apply()(implicit p: Parameters): TLAsyncSourceNode = apply(None) def apply(sync: Int)(implicit p: Parameters): TLAsyncSourceNode = apply(Some(sync)) def apply(sync: Option[Int])(implicit p: Parameters): TLAsyncSourceNode = { val asource = LazyModule(new TLAsyncCrossingSource(sync)) asource.node } } object TLAsyncCrossingSink { def apply(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) = { val asink = LazyModule(new TLAsyncCrossingSink(params)) asink.node } } @deprecated("TLAsyncCrossing is fragile. Use TLAsyncCrossingSource and TLAsyncCrossingSink", "rocket-chip 1.2") class TLAsyncCrossing(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) extends LazyModule { val source = LazyModule(new TLAsyncCrossingSource()) val sink = LazyModule(new TLAsyncCrossingSink(params)) val node = NodeHandle(source.node, sink.node) sink.node := source.node lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val in_clock = Input(Clock()) val in_reset = Input(Bool()) val out_clock = Input(Clock()) val out_reset = Input(Bool()) }) source.module.clock := io.in_clock source.module.reset := io.in_reset sink.module.clock := io.out_clock sink.module.reset := io.out_reset } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMAsyncCrossing(txns: Int, params: AsynchronousCrossing = AsynchronousCrossing())(implicit p: Parameters) extends LazyModule { val model = LazyModule(new TLRAMModel("AsyncCrossing")) val fuzz = LazyModule(new TLFuzzer(txns)) val island = LazyModule(new CrossingWrapper(params)) val ram = island { LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) } island.crossTLIn(ram.node) := TLFragmenter(4, 256) := TLDelayer(0.1) := model.node := fuzz.node lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished // Shove the RAM into another clock domain val clocks = Module(new Pow2ClockDivider(2)) island.module.clock := clocks.io.clock_out } } class TLRAMAsyncCrossingTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut_wide = Module(LazyModule(new TLRAMAsyncCrossing(txns)).module) val dut_narrow = Module(LazyModule(new TLRAMAsyncCrossing(txns, AsynchronousCrossing(safe = false, narrow = true))).module) io.finished := dut_wide.io.finished && dut_narrow.io.finished dut_wide.io.start := io.start dut_narrow.io.start := io.start } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }	module TLAsyncCrossingSource_a9d32s1k1z2u( // @[AsyncCrossing.scala:23:9] input clock, // @[AsyncCrossing.scala:23:9] input reset, // @[AsyncCrossing.scala:23:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_a_mem_0_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_mem_0_data, // @[LazyModuleImp.scala:107:25] input auto_out_a_ridx, // @[LazyModuleImp.scala:107:25] output auto_out_a_widx, // @[LazyModuleImp.scala:107:25] input auto_out_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] output auto_out_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25] output auto_out_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] input auto_out_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_mem_0_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_mem_0_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_d_mem_0_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ridx, // @[LazyModuleImp.scala:107:25] input auto_out_d_widx, // @[LazyModuleImp.scala:107:25] output auto_out_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] input auto_out_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25] input auto_out_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] output auto_out_d_safe_sink_reset_n // @[LazyModuleImp.scala:107:25] ); wire _nodeIn_d_sink_io_deq_valid; // @[AsyncQueue.scala:211:22] wire [2:0] _nodeIn_d_sink_io_deq_bits_opcode; // @[AsyncQueue.scala:211:22] wire [1:0] _nodeIn_d_sink_io_deq_bits_param; // @[AsyncQueue.scala:211:22] wire [1:0] _nodeIn_d_sink_io_deq_bits_size; // @[AsyncQueue.scala:211:22] wire _nodeIn_d_sink_io_deq_bits_source; // @[AsyncQueue.scala:211:22] wire _nodeIn_d_sink_io_deq_bits_sink; // @[AsyncQueue.scala:211:22] wire _nodeIn_d_sink_io_deq_bits_denied; // @[AsyncQueue.scala:211:22] wire _nodeIn_d_sink_io_deq_bits_corrupt; // @[AsyncQueue.scala:211:22] wire _nodeOut_a_source_io_enq_ready; // @[AsyncQueue.scala:220:24] TLMonitor_74 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_nodeOut_a_source_io_enq_ready), // @[AsyncQueue.scala:220:24] .io_in_a_valid (auto_in_a_valid), .io_in_a_bits_opcode (auto_in_a_bits_opcode), .io_in_a_bits_address (auto_in_a_bits_address), .io_in_d_ready (auto_in_d_ready), .io_in_d_valid (_nodeIn_d_sink_io_deq_valid), // @[AsyncQueue.scala:211:22] .io_in_d_bits_opcode (_nodeIn_d_sink_io_deq_bits_opcode), // @[AsyncQueue.scala:211:22] .io_in_d_bits_param (_nodeIn_d_sink_io_deq_bits_param), // @[AsyncQueue.scala:211:22] .io_in_d_bits_size (_nodeIn_d_sink_io_deq_bits_size), // @[AsyncQueue.scala:211:22] .io_in_d_bits_source (_nodeIn_d_sink_io_deq_bits_source), // @[AsyncQueue.scala:211:22] .io_in_d_bits_sink (_nodeIn_d_sink_io_deq_bits_sink), // @[AsyncQueue.scala:211:22] .io_in_d_bits_denied (_nodeIn_d_sink_io_deq_bits_denied), // @[AsyncQueue.scala:211:22] .io_in_d_bits_corrupt (_nodeIn_d_sink_io_deq_bits_corrupt) // @[AsyncQueue.scala:211:22] ); // @[Nodes.scala:27:25] AsyncQueueSource_TLBundleA_a9d32s1k1z2u nodeOut_a_source ( // @[AsyncQueue.scala:220:24] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_a_source_io_enq_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_opcode (auto_in_a_bits_opcode), .io_enq_bits_address (auto_in_a_bits_address), .io_enq_bits_data (auto_in_a_bits_data), .io_async_mem_0_opcode (auto_out_a_mem_0_opcode), .io_async_mem_0_address (auto_out_a_mem_0_address), .io_async_mem_0_data (auto_out_a_mem_0_data), .io_async_ridx (auto_out_a_ridx), .io_async_widx (auto_out_a_widx), .io_async_safe_ridx_valid (auto_out_a_safe_ridx_valid), .io_async_safe_widx_valid (auto_out_a_safe_widx_valid), .io_async_safe_source_reset_n (auto_out_a_safe_source_reset_n), .io_async_safe_sink_reset_n (auto_out_a_safe_sink_reset_n) ); // @[AsyncQueue.scala:220:24] AsyncQueueSink_TLBundleD_a9d32s1k1z2u nodeIn_d_sink ( // @[AsyncQueue.scala:211:22] .clock (clock), .reset (reset), .io_deq_ready (auto_in_d_ready), .io_deq_valid (_nodeIn_d_sink_io_deq_valid), .io_deq_bits_opcode (_nodeIn_d_sink_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_d_sink_io_deq_bits_param), .io_deq_bits_size (_nodeIn_d_sink_io_deq_bits_size), .io_deq_bits_source (_nodeIn_d_sink_io_deq_bits_source), .io_deq_bits_sink (_nodeIn_d_sink_io_deq_bits_sink), .io_deq_bits_denied (_nodeIn_d_sink_io_deq_bits_denied), .io_deq_bits_data (auto_in_d_bits_data), .io_deq_bits_corrupt (_nodeIn_d_sink_io_deq_bits_corrupt), .io_async_mem_0_opcode (auto_out_d_mem_0_opcode), .io_async_mem_0_size (auto_out_d_mem_0_size), .io_async_mem_0_source (auto_out_d_mem_0_source), .io_async_mem_0_data (auto_out_d_mem_0_data), .io_async_ridx (auto_out_d_ridx), .io_async_widx (auto_out_d_widx), .io_async_safe_ridx_valid (auto_out_d_safe_ridx_valid), .io_async_safe_widx_valid (auto_out_d_safe_widx_valid), .io_async_safe_source_reset_n (auto_out_d_safe_source_reset_n), .io_async_safe_sink_reset_n (auto_out_d_safe_sink_reset_n) ); // @[AsyncQueue.scala:211:22] assign auto_in_a_ready = _nodeOut_a_source_io_enq_ready; // @[AsyncQueue.scala:220:24] assign auto_in_d_valid = _nodeIn_d_sink_io_deq_valid; // @[AsyncQueue.scala:211:22] assign auto_in_d_bits_opcode = _nodeIn_d_sink_io_deq_bits_opcode; // @[AsyncQueue.scala:211:22] assign auto_in_d_bits_param = _nodeIn_d_sink_io_deq_bits_param; // @[AsyncQueue.scala:211:22] assign auto_in_d_bits_size = _nodeIn_d_sink_io_deq_bits_size; // @[AsyncQueue.scala:211:22] assign auto_in_d_bits_source = _nodeIn_d_sink_io_deq_bits_source; // @[AsyncQueue.scala:211:22] assign auto_in_d_bits_sink = _nodeIn_d_sink_io_deq_bits_sink; // @[AsyncQueue.scala:211:22] assign auto_in_d_bits_denied = _nodeIn_d_sink_io_deq_bits_denied; // @[AsyncQueue.scala:211:22] assign auto_in_d_bits_corrupt = _nodeIn_d_sink_io_deq_bits_corrupt; // @[AsyncQueue.scala:211:22] endmodule
Generate the Verilog code corresponding to the following Chisel files. File TilelinkAdapters.scala: package constellation.protocol import chisel3._ import chisel3.util._ import constellation.channel._ import constellation.noc._ import constellation.soc.{CanAttachToGlobalNoC} import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import scala.collection.immutable.{ListMap} abstract class TLChannelToNoC[T <: TLChannel](gen: => T, edge: TLEdge, idToEgress: Int => Int)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Flipped(Decoupled(gen)) val flit = Decoupled(new IngressFlit(flitWidth)) }) def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B // convert decoupled to irrevocable val q = Module(new Queue(gen, 1, pipe=true, flow=true)) val protocol = q.io.deq val has_body = Wire(Bool()) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val head = edge.first(protocol.bits, protocol.fire) val tail = edge.last(protocol.bits, protocol.fire) def requestOH: Seq[Bool] val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt)) val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt)) val is_body = RegInit(false.B) io.flit.valid := protocol.valid protocol.ready := io.flit.ready && (is_body \|\| !has_body) io.flit.bits.head := head && !is_body io.flit.bits.tail := tail && (is_body \|\| !has_body) io.flit.bits.egress_id := Mux1H(requestOH.zipWithIndex.map { case (r, i) => r -> idToEgress(i).U }) io.flit.bits.payload := Mux(is_body, body, const) when (io.flit.fire && io.flit.bits.head) { is_body := true.B } when (io.flit.fire && io.flit.bits.tail) { is_body := false.B } } abstract class TLChannelFromNoC[T <: TLChannel](gen: => T)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Decoupled(gen) val flit = Flipped(Decoupled(new EgressFlit(flitWidth))) }) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) val protocol = Wire(Decoupled(gen)) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val is_const = RegInit(true.B) val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W)) val const = Mux(io.flit.bits.head, io.flit.bits.payload, const_reg) io.flit.ready := (is_const && !io.flit.bits.tail) \|\| protocol.ready protocol.valid := (!is_const \|\| io.flit.bits.tail) && io.flit.valid def assign(i: UInt, sigs: Seq[Data]) = { var t = i for (s <- sigs.reverse) { s := t.asTypeOf(s.cloneType) t = t >> s.getWidth } } assign(const, const_fields) assign(io.flit.bits.payload, body_fields) when (io.flit.fire && io.flit.bits.head) { is_const := false.B; const_reg := io.flit.bits.payload } when (io.flit.fire && io.flit.bits.tail) { is_const := true.B } } trait HasAddressDecoder { // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) val edgeIn: TLEdge val edgesOut: Seq[TLEdge] lazy val reacheableIO = edgesOut.map { mp => edgeIn.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} }.toVector lazy val releaseIO = (edgesOut zip reacheableIO).map { case (mp, reachable) => reachable && edgeIn.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector def outputPortFn(connectIO: Seq[Boolean]) = { val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectIO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_\|\|_)) } } class TLAToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToAEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleA(bundle), edgeIn, slaveToAEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) \|\| (~protocol.bits.mask =/= 0.U) lazy val connectAIO = reacheableIO lazy val requestOH = outputPortFn(connectAIO).zipWithIndex.map { case (o, j) => connectAIO(j).B && (unique(connectAIO) \|\| o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source \| sourceStart.U } class TLAFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleA(bundle))(p) { io.protocol <> protocol when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLBToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToBIngress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleB(bundle), edgeOut, masterToBIngress)(p) { has_body := edgeOut.hasData(protocol.bits) \|\| (~protocol.bits.mask =/= 0.U) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol } class TLBFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleB(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLCToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToCEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleC(bundle), edgeIn, slaveToCEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) lazy val connectCIO = releaseIO lazy val requestOH = outputPortFn(connectCIO).zipWithIndex.map { case (o, j) => connectCIO(j).B && (unique(connectCIO) \|\| o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source \| sourceStart.U } class TLCFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleC(bundle))(p) { io.protocol <> protocol } class TLDToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToDIngress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleD(bundle), edgeOut, masterToDIngress)(p) { has_body := edgeOut.hasData(protocol.bits) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol q.io.enq.bits.sink := io.protocol.bits.sink \| sourceStart.U } class TLDFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleD(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) } class TLEToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToEEgress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleE(bundle), edgeIn, slaveToEEgress)(p) { has_body := edgeIn.hasData(protocol.bits) lazy val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) lazy val requestOH = outputIdRanges.map { o => o.contains(protocol.bits.sink) } q.io.enq <> io.protocol } class TLEFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleE(bundle))(p) { io.protocol <> protocol io.protocol.bits.sink := trim(protocol.bits.sink, sourceSize) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLCToNoC_11( // @[TilelinkAdapters.scala:151:7] input clock, // @[TilelinkAdapters.scala:151:7] input reset, // @[TilelinkAdapters.scala:151:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14] input [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [64:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [5:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [5:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17] wire [63:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71] reg [8:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire [8:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:3]) : 9'h0; // @[package.scala:243:{46,71,76}] reg [8:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire q_io_deq_ready = io_flit_ready & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 9'h1 \| tail_beats1 == 9'h0) & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36, :221:14, :229:27, :232:{25,33,43}] wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:151:7] if (reset) begin // @[TilelinkAdapters.scala:151:7] head_counter <= 9'h0; // @[Edges.scala:229:27] tail_counter <= 9'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :151:7] end else begin // @[TilelinkAdapters.scala:151:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:3]) : 9'h0) : head_counter - 9'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 9'h0 ? tail_beats1 : tail_counter - 9'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 \| is_body); // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_333( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File SourceB.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class SourceBRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val param = UInt(3.W) val tag = UInt(params.tagBits.W) val set = UInt(params.setBits.W) val clients = UInt(params.clientBits.W) } class SourceB(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val req = Flipped(Decoupled(new SourceBRequest(params))) val b = Decoupled(new TLBundleB(params.inner.bundle)) }) if (params.firstLevel) { // Tie off unused ports io.req.ready := true.B io.b.valid := false.B io.b.bits := DontCare } else { val remain = RegInit(0.U(params.clientBits.W)) val remain_set = WireInit(init = 0.U(params.clientBits.W)) val remain_clr = WireInit(init = 0.U(params.clientBits.W)) remain := (remain \| remain_set) & ~remain_clr val busy = remain.orR val todo = Mux(busy, remain, io.req.bits.clients) val next = ~(leftOR(todo) << 1) & todo if (params.clientBits > 1) { params.ccover(PopCount(remain) > 1.U, "SOURCEB_MULTI_PROBE", "Had to probe more than one client") } assert (!io.req.valid \|\| io.req.bits.clients =/= 0.U) io.req.ready := !busy when (io.req.fire) { remain_set := io.req.bits.clients } // No restrictions on the type of buffer used here val b = Wire(chiselTypeOf(io.b)) io.b <> params.micro.innerBuf.b(b) b.valid := busy \|\| io.req.valid when (b.fire) { remain_clr := next } params.ccover(b.valid && !b.ready, "SOURCEB_STALL", "Backpressured when issuing a probe") val tag = Mux(!busy, io.req.bits.tag, RegEnable(io.req.bits.tag, io.req.fire)) val set = Mux(!busy, io.req.bits.set, RegEnable(io.req.bits.set, io.req.fire)) val param = Mux(!busy, io.req.bits.param, RegEnable(io.req.bits.param, io.req.fire)) b.bits.opcode := TLMessages.Probe b.bits.param := param b.bits.size := params.offsetBits .U b.bits.source := params.clientSource(next) b.bits.address := params.expandAddress(tag, set, 0.U) b.bits.mask := ~0.U(params.inner.manager.beatBytes.W) b.bits.data := 0.U b.bits.corrupt := false.B } } File Parameters.scala: / * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relListscache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_\|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x \| 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ \|\| _) (matches, bits.U) } expanded \| Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) \|\| (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) \|\| ((opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm \|\| opcode === TLMessages.Get \|\| (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN \|\| param === TLPermissions.BtoN \|\| param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB \|\| param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle	module SourceB_1( // @[SourceB.scala:33:7] input clock, // @[SourceB.scala:33:7] input reset, // @[SourceB.scala:33:7] output io_req_ready, // @[SourceB.scala:35:14] input io_req_valid, // @[SourceB.scala:35:14] input [2:0] io_req_bits_param, // @[SourceB.scala:35:14] input [8:0] io_req_bits_tag, // @[SourceB.scala:35:14] input [10:0] io_req_bits_set, // @[SourceB.scala:35:14] input io_req_bits_clients, // @[SourceB.scala:35:14] input io_b_ready, // @[SourceB.scala:35:14] output io_b_valid, // @[SourceB.scala:35:14] output [1:0] io_b_bits_param, // @[SourceB.scala:35:14] output [31:0] io_b_bits_address // @[SourceB.scala:35:14] ); wire io_req_valid_0 = io_req_valid; // @[SourceB.scala:33:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceB.scala:33:7] wire [8:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceB.scala:33:7] wire [10:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceB.scala:33:7] wire io_req_bits_clients_0 = io_req_bits_clients; // @[SourceB.scala:33:7] wire io_b_ready_0 = io_b_ready; // @[SourceB.scala:33:7] wire _b_bits_address_base_T_2 = reset; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_8 = reset; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_14 = reset; // @[Parameters.scala:222:12] wire [2:0] io_b_bits_opcode = 3'h6; // @[SourceB.scala:33:7] wire [2:0] io_b_bits_size = 3'h6; // @[SourceB.scala:33:7] wire [2:0] b_bits_opcode = 3'h6; // @[SourceB.scala:65:17] wire [2:0] b_bits_size = 3'h6; // @[SourceB.scala:65:17] wire [5:0] io_b_bits_source = 6'h28; // @[SourceB.scala:33:7] wire [5:0] b_bits_source = 6'h28; // @[SourceB.scala:65:17] wire [15:0] io_b_bits_mask = 16'hFFFF; // @[SourceB.scala:33:7] wire [15:0] b_bits_mask = 16'hFFFF; // @[SourceB.scala:65:17] wire [15:0] _b_bits_mask_T = 16'hFFFF; // @[SourceB.scala:81:23] wire [127:0] io_b_bits_data = 128'h0; // @[SourceB.scala:33:7] wire [127:0] b_bits_data = 128'h0; // @[SourceB.scala:65:17] wire io_b_bits_corrupt = 1'h0; // @[SourceB.scala:33:7] wire b_bits_corrupt = 1'h0; // @[SourceB.scala:65:17] wire _b_bits_address_base_T = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_4 = 1'h0; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_6 = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_10 = 1'h0; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_12 = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_16 = 1'h0; // @[Parameters.scala:222:12] wire [1:0] b_bits_address_lo_lo_hi_hi = 2'h0; // @[Parameters.scala:230:8] wire [1:0] b_bits_address_hi_hi_hi_lo = 2'h0; // @[Parameters.scala:230:8] wire [5:0] b_bits_address_base_y_2 = 6'h0; // @[Parameters.scala:221:15] wire [5:0] _b_bits_address_base_T_17 = 6'h0; // @[Parameters.scala:223:6] wire _b_bits_address_base_T_1 = 1'h1; // @[Parameters.scala:222:24] wire _b_bits_address_base_T_7 = 1'h1; // @[Parameters.scala:222:24] wire _b_bits_address_base_T_13 = 1'h1; // @[Parameters.scala:222:24] wire _io_req_ready_T; // @[SourceB.scala:61:21] wire b_ready = io_b_ready_0; // @[SourceB.scala:33:7, :65:17] wire b_valid; // @[SourceB.scala:65:17] wire [1:0] b_bits_param; // @[SourceB.scala:65:17] wire [31:0] b_bits_address; // @[SourceB.scala:65:17] wire io_req_ready_0; // @[SourceB.scala:33:7] wire [1:0] io_b_bits_param_0; // @[SourceB.scala:33:7] wire [31:0] io_b_bits_address_0; // @[SourceB.scala:33:7] wire io_b_valid_0; // @[SourceB.scala:33:7] reg remain; // @[SourceB.scala:46:25] wire busy = remain; // @[SourceB.scala:46:25, :51:23] wire remain_set; // @[SourceB.scala:47:30] wire remain_clr; // @[SourceB.scala:48:30] wire _remain_T = remain \| remain_set; // @[SourceB.scala:46:25, :47:30, :49:23] wire _remain_T_1 = ~remain_clr; // @[SourceB.scala:48:30, :49:39] wire _remain_T_2 = _remain_T & _remain_T_1; // @[SourceB.scala:49:{23,37,39}] wire todo = busy ? remain : io_req_bits_clients_0; // @[SourceB.scala:33:7, :46:25, :51:23, :52:19] wire _next_T = todo; // @[package.scala:254:17] wire [1:0] _next_T_1 = {_next_T, 1'h0}; // @[package.scala:254:17] wire [1:0] _next_T_2 = ~_next_T_1; // @[SourceB.scala:53:{16,31}] wire [1:0] next = {1'h0, _next_T_2[0] & todo}; // @[SourceB.scala:52:19, :53:{16,37}]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_148( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_252 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_1( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_d), .io_q (io_q) ); // @[ShiftReg.scala:45:23] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire \|\| io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) \|\| !io.outCol.fire) assert(!(state === 1.U) \|\| !io.inRow.fire) }	module PE_210( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} \|acquireB = ${acquireB} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT \|\| supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB \|\| regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED \|\| supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED \|\| supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB \|\| supportsGet, w = supportsAcquireT \|\| supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} \|Slave Address = ${address} \|supports = ${supports.infoString} \| \|""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ \|\| _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ \|\| _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_\|\|_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ \|\| _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B \|\| s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} \|visibility = ${visibility} \|emits = ${emits.infoString} \|sourceId = ${sourceId} \| \|""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ \|\| _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ \|\| _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ \|\| _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ \|\| _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ \|\| _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ \|\| _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ \|\| _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ \|\| _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE \|\| x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps / class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_78( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46] wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7] wire [3:0] mask = 4'hF; // @[Misc.scala:222:10] wire [31:0] io_in_d_bits_data = 32'h0; // @[Monitor.scala:36:7] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_wo_ready_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [127:0] _is_aligned_T = {126'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 128'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire _T_607 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_607; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_607; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [127:0] address; // @[Monitor.scala:391:22] wire _T_675 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_675; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_675; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_675; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_537 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_537; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_537; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_607 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_586 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_586 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_675 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] wire [3:0] _GEN_1 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_opcodes_clr = _GEN_1; // @[Monitor.scala:668:33, :678:89, :680:21] assign d_sizes_clr = _GEN_1; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_651 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_651 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_675 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] wire [3:0] _GEN_2 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_opcodes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :788:88, :790:21] assign d_sizes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File SwitchAllocator.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ class SwitchAllocReq(val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams]) (implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val tail = Bool() } class SwitchArbiter(inN: Int, outN: Int, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Module { val io = IO(new Bundle { val in = Flipped(Vec(inN, Decoupled(new SwitchAllocReq(outParams, egressParams)))) val out = Vec(outN, Decoupled(new SwitchAllocReq(outParams, egressParams))) val chosen_oh = Vec(outN, Output(UInt(inN.W))) }) val lock = Seq.fill(outN) { RegInit(0.U(inN.W)) } val unassigned = Cat(io.in.map(_.valid).reverse) & ~(lock.reduce(_\|_)) val mask = RegInit(0.U(inN.W)) val choices = Wire(Vec(outN, UInt(inN.W))) var sel = PriorityEncoderOH(Cat(unassigned, unassigned & ~mask)) for (i <- 0 until outN) { choices(i) := sel \| (sel >> inN) sel = PriorityEncoderOH(unassigned & ~choices(i)) } io.in.foreach(_.ready := false.B) var chosens = 0.U(inN.W) val in_tails = Cat(io.in.map(_.bits.tail).reverse) for (i <- 0 until outN) { val in_valids = Cat((0 until inN).map { j => io.in(j).valid && !chosens(j) }.reverse) val chosen = Mux((in_valids & lock(i) & ~chosens).orR, lock(i), choices(i)) io.chosen_oh(i) := chosen io.out(i).valid := (in_valids & chosen).orR io.out(i).bits := Mux1H(chosen, io.in.map(_.bits)) for (j <- 0 until inN) { when (chosen(j) && io.out(i).ready) { io.in(j).ready := true.B } } chosens = chosens \| chosen when (io.out(i).fire) { lock(i) := chosen & ~in_tails } } when (io.out(0).fire) { mask := (0 until inN).map { i => (io.chosen_oh(0) >> i) }.reduce(_\|_) } .otherwise { mask := Mux(~mask === 0.U, 0.U, (mask << 1) \| 1.U(1.W)) } } class SwitchAllocator( val routerParams: RouterParams, val inParams: Seq[ChannelParams], val outParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterParams with HasRouterInputParams with HasRouterOutputParams { val io = IO(new Bundle { val req = MixedVec(allInParams.map(u => Vec(u.destSpeedup, Flipped(Decoupled(new SwitchAllocReq(outParams, egressParams)))))) val credit_alloc = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Output(new OutputCreditAlloc))}) val switch_sel = MixedVec(allOutParams.map { o => Vec(o.srcSpeedup, MixedVec(allInParams.map { i => Vec(i.destSpeedup, Output(Bool())) })) }) }) val nInputChannels = allInParams.map(_.nVirtualChannels).sum val arbs = allOutParams.map { oP => Module(new SwitchArbiter( allInParams.map(_.destSpeedup).reduce(_+_), oP.srcSpeedup, outParams, egressParams ))} arbs.foreach(_.io.out.foreach(_.ready := true.B)) var idx = 0 io.req.foreach(_.foreach { o => val fires = Wire(Vec(arbs.size, Bool())) arbs.zipWithIndex.foreach { case (a,i) => a.io.in(idx).valid := o.valid && o.bits.vc_sel(i).reduce(_\|\|_) a.io.in(idx).bits := o.bits fires(i) := a.io.in(idx).fire } o.ready := fires.reduce(_\|\|_) idx += 1 }) for (i <- 0 until nAllOutputs) { for (j <- 0 until allOutParams(i).srcSpeedup) { idx = 0 for (m <- 0 until nAllInputs) { for (n <- 0 until allInParams(m).destSpeedup) { io.switch_sel(i)(j)(m)(n) := arbs(i).io.in(idx).valid && arbs(i).io.chosen_oh(j)(idx) && arbs(i).io.out(j).valid idx += 1 } } } } io.credit_alloc.foreach(_.foreach(_.alloc := false.B)) io.credit_alloc.foreach(_.foreach(_.tail := false.B)) (arbs zip io.credit_alloc).zipWithIndex.map { case ((a,i),t) => for (j <- 0 until i.size) { for (k <- 0 until a.io.out.size) { when (a.io.out(k).valid && a.io.out(k).bits.vc_sel(t)(j)) { i(j).alloc := true.B i(j).tail := a.io.out(k).bits.tail } } } } }	module SwitchArbiter_330( // @[SwitchAllocator.scala:17:7] input clock, // @[SwitchAllocator.scala:17:7] input reset, // @[SwitchAllocator.scala:17:7] output io_in_0_ready, // @[SwitchAllocator.scala:18:14] input io_in_0_valid, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_8, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_9, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_8, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_9, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_1_ready, // @[SwitchAllocator.scala:18:14] input io_in_1_valid, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_8, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_9, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_8, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_9, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_tail, // @[SwitchAllocator.scala:18:14] output io_out_0_valid, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_8, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_9, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_8, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_9, // @[SwitchAllocator.scala:18:14] output [1:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14] ); reg [1:0] lock_0; // @[SwitchAllocator.scala:24:38] wire [1:0] unassigned = {io_in_1_valid, io_in_0_valid} & ~lock_0; // @[SwitchAllocator.scala:24:38, :25:{23,52,54}] reg [1:0] mask; // @[SwitchAllocator.scala:27:21] wire [1:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}] wire [3:0] sel = _sel_T_1[0] ? 4'h1 : _sel_T_1[1] ? 4'h2 : unassigned[0] ? 4'h4 : {unassigned[1], 3'h0}; // @[OneHot.scala:85:71] wire [1:0] in_valids = {io_in_1_valid, io_in_0_valid}; // @[SwitchAllocator.scala:41:24] wire [1:0] chosen = (\|(in_valids & lock_0)) ? lock_0 : sel[1:0] \| sel[3:2]; // @[Mux.scala:50:70] wire [1:0] _io_out_0_valid_T = in_valids & chosen; // @[SwitchAllocator.scala:41:24, :42:21, :44:35] always @(posedge clock) begin // @[SwitchAllocator.scala:17:7] if (reset) begin // @[SwitchAllocator.scala:17:7] lock_0 <= 2'h0; // @[SwitchAllocator.scala:24:38] mask <= 2'h0; // @[SwitchAllocator.scala:27:21] end else begin // @[SwitchAllocator.scala:17:7] if (\|_io_out_0_valid_T) // @[SwitchAllocator.scala:44:{35,45}] lock_0 <= chosen & ~{io_in_1_bits_tail, io_in_0_bits_tail}; // @[SwitchAllocator.scala:24:38, :39:21, :42:21, :53:{25,27}] mask <= (\|_io_out_0_valid_T) ? {chosen[1], \|chosen} : (&mask) ? 2'h0 : {mask[0], 1'h1}; // @[SwitchAllocator.scala:17:7, :27:21, :42:21, :44:{35,45}, :57:25, :58:{10,71}, :60:{10,16,23,49}] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File MulAddRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //* POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //* UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //* REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero \|\| rawB.isZero \|\| (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign \|\| (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //* NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR \|\| reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) \|\| isSigNaNRawFloat(rawB) \|\| isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN \|\| rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR \|\| CDom_reduced4SigExtra \|\| CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR \|\| notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA \|\| io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd \|\| io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA \|\| io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny \|\| (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) \|\| (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) \|\| (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA \|\| io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB \|\| io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros \|\| (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) \|\| (io.fromPreMul.isInfC && opSignC) \|\| (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) \|\| (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd \|\| opSignC)) \|\| (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }	module MulAddRecFN_e8_s24_28( // @[MulAddRecFN.scala:300:7] input [32:0] io_a, // @[MulAddRecFN.scala:303:16] input [32:0] io_c, // @[MulAddRecFN.scala:303:16] output [32:0] io_out // @[MulAddRecFN.scala:303:16] ); wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15] wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15] wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15] wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15] wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[MulAddRecFN.scala:317:15] wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[MulAddRecFN.scala:317:15] wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15] wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15] wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7] wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:300:7] wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :339:15] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15] wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7] wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7] wire [47:0] _mulAddResult_T = {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddA, 23'h0}; // @[MulAddRecFN.scala:317:15, :327:45] wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50] MulAddRecFNToRaw_preMul_e8_s24_28 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15] .io_a (io_a_0), // @[MulAddRecFN.scala:300:7] .io_c (io_c_0), // @[MulAddRecFN.scala:300:7] .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA), .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) ); // @[MulAddRecFN.scala:317:15] MulAddRecFNToRaw_postMul_e8_s24_28 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15] .io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15] .io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) ); // @[MulAddRecFN.scala:319:15] RoundRawFNToRecFN_e8_s24_43 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15] .io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15] .io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15] .io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15] .io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15] .io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15] .io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulAddRecFN.scala:339:15] assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_23( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire [2047:0] _GEN = {2037'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_0 = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [2047:0] _GEN_2 = {2037'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File RecFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import consts._ class RecFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val in = Input(Bits((inExpWidth + inSigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in); if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- io.out := io.in<<(outSigWidth - inSigWidth) io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W) } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( inExpWidth, inSigWidth, outExpWidth, outSigWidth, flRoundOpt_sigMSBitAlwaysZero )) roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn) roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := rawIn roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } } File rawFloatFromRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ /---------------------------------------------------------------------------- \| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be \| set. ----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }	module RecFNToRecFN_145( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File tage.scala: package boom.v3.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc} import scala.math.min class TageResp extends Bundle { val ctr = UInt(3.W) val u = UInt(2.W) } class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int) (implicit p: Parameters) extends BoomModule()(p) with HasBoomFrontendParameters { require(histLength <= globalHistoryLength) val nWrBypassEntries = 2 val io = IO( new Bundle { val f1_req_valid = Input(Bool()) val f1_req_pc = Input(UInt(vaddrBitsExtended.W)) val f1_req_ghist = Input(UInt(globalHistoryLength.W)) val f3_resp = Output(Vec(bankWidth, Valid(new TageResp))) val update_mask = Input(Vec(bankWidth, Bool())) val update_taken = Input(Vec(bankWidth, Bool())) val update_alloc = Input(Vec(bankWidth, Bool())) val update_old_ctr = Input(Vec(bankWidth, UInt(3.W))) val update_pc = Input(UInt()) val update_hist = Input(UInt()) val update_u_mask = Input(Vec(bankWidth, Bool())) val update_u = Input(Vec(bankWidth, UInt(2.W))) }) def compute_folded_hist(hist: UInt, l: Int) = { val nChunks = (histLength + l - 1) / l val hist_chunks = (0 until nChunks) map {i => hist(min((i+1)l, histLength)-1, il) } hist_chunks.reduce(_^_) } def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = { val idx_history = compute_folded_hist(hist, log2Ceil(nRows)) val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0) val tag_history = compute_folded_hist(hist, tagSz) val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0) (idx, tag) } def inc_ctr(ctr: UInt, taken: Bool): UInt = { Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U), Mux(ctr === 7.U, 7.U, ctr + 1.U)) } val doing_reset = RegInit(true.B) val reset_idx = RegInit(0.U(log2Ceil(nRows).W)) reset_idx := reset_idx + doing_reset when (reset_idx === (nRows-1).U) { doing_reset := false.B } class TageEntry extends Bundle { val valid = Bool() // TODO: Remove this valid bit val tag = UInt(tagSz.W) val ctr = UInt(3.W) } val tageEntrySz = 1 + tagSz + 3 val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist) val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool())) val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool())) val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W))) val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz)) val s2_tag = RegNext(s1_tag) val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry))) val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid) val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid) val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset)) for (w <- 0 until bankWidth) { // This bit indicates the TAGE table matched here io.f3_resp(w).valid := RegNext(s2_req_rhits(w)) io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w))) io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr) } val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W)) when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U } val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod) val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist) val update_wdata = Wire(Vec(bankWidth, new TageEntry)) table.write( Mux(doing_reset, reset_idx , update_idx), Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))), Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools ) val update_hi_wdata = Wire(Vec(bankWidth, Bool())) hi_us.write( Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)), Mux(doing_reset \|\| doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata), Mux(doing_reset \|\| doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools ) val update_lo_wdata = Wire(Vec(bankWidth, Bool())) lo_us.write( Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)), Mux(doing_reset \|\| doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata), Mux(doing_reset \|\| doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools ) val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W))) val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W))) val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W)))) val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W)) val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i => !doing_reset && wrbypass_tags(i) === update_tag && wrbypass_idxs(i) === update_idx }) val wrbypass_hit = wrbypass_hits.reduce(_\|\|_) val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits) for (w <- 0 until bankWidth) { update_wdata(w).ctr := Mux(io.update_alloc(w), Mux(io.update_taken(w), 4.U, 3.U ), Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)), inc_ctr(io.update_old_ctr(w), io.update_taken(w)) ) ) update_wdata(w).valid := true.B update_wdata(w).tag := update_tag update_hi_wdata(w) := io.update_u(w)(1) update_lo_wdata(w) := io.update_u(w)(0) } when (io.update_mask.reduce(_\|\|_)) { when (wrbypass_hits.reduce(_\|\|_)) { wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr)) } .otherwise { wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr)) wrbypass_tags(wrbypass_enq_idx) := update_tag wrbypass_idxs(wrbypass_enq_idx) := update_idx wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries) } } } case class BoomTageParams( // nSets, histLen, tagSz tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7), ( 128, 4, 7), ( 256, 8, 8), ( 256, 16, 8), ( 128, 32, 9), ( 128, 64, 9)), uBitPeriod: Int = 2048 ) class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p) { val tageUBitPeriod = params.uBitPeriod val tageNTables = params.tableInfo.size class TageMeta extends Bundle { val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W))) val alt_differs = Vec(bankWidth, Output(Bool())) val provider_u = Vec(bankWidth, Output(UInt(2.W))) val provider_ctr = Vec(bankWidth, Output(UInt(3.W))) val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W))) } val f3_meta = Wire(new TageMeta) override val metaSz = f3_meta.asUInt.getWidth require(metaSz <= bpdMaxMetaLength) def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = { Mux(!alt_differs, u, Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U), Mux(u === 3.U, 3.U, u + 1.U))) } val tt = params.tableInfo map { case (n, l, s) => { val t = Module(new TageTable(n, s, l, params.uBitPeriod)) t.io.f1_req_valid := RegNext(io.f0_valid) t.io.f1_req_pc := RegNext(io.f0_pc) t.io.f1_req_ghist := io.f1_ghist (t, t.mems) } } val tables = tt.map(_._1) val mems = tt.map(_._2).flatten val f3_resps = VecInit(tables.map(_.io.f3_resp)) val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta) val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) & Fill(bankWidth, s1_update.bits.cfi_mispredicted) val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool())))) val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W))))) val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool()))) val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W)))) val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool()))) val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W)))) s1_update_taken := DontCare s1_update_old_ctr := DontCare s1_update_alloc := DontCare s1_update_u := DontCare for (w <- 0 until bankWidth) { var altpred = io.resp_in(0).f3(w).taken val final_altpred = WireInit(io.resp_in(0).f3(w).taken) var provided = false.B var provider = 0.U io.resp.f3(w).taken := io.resp_in(0).f3(w).taken for (i <- 0 until tageNTables) { val hit = f3_resps(i)(w).valid val ctr = f3_resps(i)(w).bits.ctr when (hit) { io.resp.f3(w).taken := Mux(ctr === 3.U \|\| ctr === 4.U, altpred, ctr(2)) final_altpred := altpred } provided = provided \|\| hit provider = Mux(hit, i.U, provider) altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred) } f3_meta.provider(w).valid := provided f3_meta.provider(w).bits := provider f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr // Create a mask of tables which did not hit our query, and also contain useless entries // and also uses a longer history than the provider val allocatable_slots = ( VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt & ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided)) ) val alloc_lfsr = random.LFSR(tageNTables max 2) val first_entry = PriorityEncoder(allocatable_slots) val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr) val alloc_entry = Mux(allocatable_slots(masked_entry), masked_entry, first_entry) f3_meta.allocate(w).valid := allocatable_slots =/= 0.U f3_meta.allocate(w).bits := alloc_entry val update_was_taken = (s1_update.bits.cfi_idx.valid && (s1_update.bits.cfi_idx.bits === w.U) && s1_update.bits.cfi_taken) when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) { when (s1_update_meta.provider(w).valid) { val provider = s1_update_meta.provider(w).bits s1_update_mask(provider)(w) := true.B s1_update_u_mask(provider)(w) := true.B val new_u = inc_u(s1_update_meta.provider_u(w), s1_update_meta.alt_differs(w), s1_update_mispredict_mask(w)) s1_update_u (provider)(w) := new_u s1_update_taken (provider)(w) := update_was_taken s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w) s1_update_alloc (provider)(w) := false.B } } } when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) { val idx = s1_update.bits.cfi_idx.bits val allocate = s1_update_meta.allocate(idx) when (allocate.valid) { s1_update_mask (allocate.bits)(idx) := true.B s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken s1_update_alloc(allocate.bits)(idx) := true.B s1_update_u_mask(allocate.bits)(idx) := true.B s1_update_u (allocate.bits)(idx) := 0.U } .otherwise { val provider = s1_update_meta.provider(idx) val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U) for (i <- 0 until tageNTables) { when (decr_mask(i)) { s1_update_u_mask(i)(idx) := true.B s1_update_u (i)(idx) := 0.U } } } } for (i <- 0 until tageNTables) { for (w <- 0 until bankWidth) { tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w)) tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w)) tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w)) tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w)) tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w)) tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w)) } tables(i).io.update_pc := RegNext(s1_update.bits.pc) tables(i).io.update_hist := RegNext(s1_update.bits.ghist) } //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0)) io.f3_meta := f3_meta.asUInt }	module hi_us( // @[tage.scala:89:27] input [6:0] R0_addr, input R0_en, input R0_clk, output [3:0] R0_data, input [6:0] W0_addr, input W0_clk, input [3:0] W0_data, input [3:0] W0_mask ); hi_us_ext hi_us_ext ( // @[tage.scala:89:27] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (1'h1), // @[tage.scala:89:27] .W0_clk (W0_clk), .W0_data (W0_data), .W0_mask (W0_mask) ); // @[tage.scala:89:27] endmodule
Generate the Verilog code corresponding to the following Chisel files. File FPU.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util._ import chisel3.{DontCare, WireInit, withClock, withReset} import chisel3.experimental.SourceInfo import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property case class FPUParams( minFLen: Int = 32, fLen: Int = 64, divSqrt: Boolean = true, sfmaLatency: Int = 3, dfmaLatency: Int = 4, fpmuLatency: Int = 2, ifpuLatency: Int = 2 ) object FPConstants { val RM_SZ = 3 val FLAGS_SZ = 5 } trait HasFPUCtrlSigs { val ldst = Bool() val wen = Bool() val ren1 = Bool() val ren2 = Bool() val ren3 = Bool() val swap12 = Bool() val swap23 = Bool() val typeTagIn = UInt(2.W) val typeTagOut = UInt(2.W) val fromint = Bool() val toint = Bool() val fastpipe = Bool() val fma = Bool() val div = Bool() val sqrt = Bool() val wflags = Bool() val vec = Bool() } class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new Bundle { val inst = Input(Bits(32.W)) val sigs = Output(new FPUCtrlSigs()) }) private val X2 = BitPat.dontCare(2) val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N) val h: Array[(BitPat, List[BitPat])] = Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N), FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N), FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N), FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N), FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N), FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N), FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N), FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N), FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N)) val f: Array[(BitPat, List[BitPat])] = Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N), FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N), FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N), FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N), FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N), FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N), FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N)) val d: Array[(BitPat, List[BitPat])] = Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N), FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N), FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N), FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N), FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N), FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N), FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N), FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N), FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N)) val fcvt_hd: Array[(BitPat, List[BitPat])] = Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N), FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N)) val vfmv_f_s: Array[(BitPat, List[BitPat])] = Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y)) val insns = ((minFLen, fLen) match { case (32, 32) => f case (16, 32) => h ++ f case (32, 64) => f ++ d case (16, 64) => h ++ f ++ d ++ fcvt_hd case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration") }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]()) val decoder = DecodeLogic(io.inst, default, insns) val s = io.sigs val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec) sigs zip decoder map {case(s,d) => s := d} } class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val time = Input(UInt(xLen.W)) val inst = Input(Bits(32.W)) val fromint_data = Input(Bits(xLen.W)) val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W)) val v_sew = Input(UInt(3.W)) val store_data = Output(Bits(fLen.W)) val toint_data = Output(Bits(xLen.W)) val ll_resp_val = Input(Bool()) val ll_resp_type = Input(Bits(3.W)) val ll_resp_tag = Input(UInt(5.W)) val ll_resp_data = Input(Bits(fLen.W)) val valid = Input(Bool()) val fcsr_rdy = Output(Bool()) val nack_mem = Output(Bool()) val illegal_rm = Output(Bool()) val killx = Input(Bool()) val killm = Input(Bool()) val dec = Output(new FPUCtrlSigs()) val sboard_set = Output(Bool()) val sboard_clr = Output(Bool()) val sboard_clra = Output(UInt(5.W)) val keep_clock_enabled = Input(Bool()) } class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) { val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs val cp_resp = Decoupled(new FPResult()) } class FPResult(implicit p: Parameters) extends CoreBundle()(p) { val data = Bits((fLen+1).W) val exc = Bits(FPConstants.FLAGS_SZ.W) } class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val typ = Bits(2.W) val in1 = Bits(xLen.W) } class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val fmaCmd = Bits(2.W) val typ = Bits(2.W) val fmt = Bits(2.W) val in1 = Bits((fLen+1).W) val in2 = Bits((fLen+1).W) val in3 = Bits((fLen+1).W) } case class FType(exp: Int, sig: Int) { def ieeeWidth = exp + sig def recodedWidth = ieeeWidth + 1 def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W) def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W) def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2) def classify(x: UInt) = { val sign = x(sig + exp) val code = x(exp + sig - 1, exp + sig - 3) val codeHi = code(2, 1) val isSpecial = codeHi === 3.U val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U val isSubnormal = code === 1.U \|\| codeHi === 1.U && isHighSubnormalIn val isNormal = codeHi === 1.U && !isHighSubnormalIn \|\| codeHi === 2.U val isZero = code === 0.U val isInf = isSpecial && !code(0) val isNaN = code.andR val isSNaN = isNaN && !x(sig-2) val isQNaN = isNaN && x(sig-2) Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign, isSubnormal && !sign, isZero && !sign, isZero && sign, isSubnormal && sign, isNormal && sign, isInf && sign) } // convert between formats, ignoring rounding, range, NaN def unsafeConvert(x: UInt, to: FType) = if (this == to) x else { val sign = x(sig + exp) val fractIn = x(sig - 2, 0) val expIn = x(sig + exp - 1, sig - 1) val fractOut = fractIn << to.sig >> sig val expOut = { val expCode = expIn(exp, exp - 2) val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U Mux(expCode === 0.U \|\| expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0)) } Cat(sign, expOut, fractOut) } private def ieeeBundle = { val expWidth = exp class IEEEBundle extends Bundle { val sign = Bool() val exp = UInt(expWidth.W) val sig = UInt((ieeeWidth-expWidth-1).W) } new IEEEBundle } def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle) def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x) def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x) } object FType { val H = new FType(5, 11) val S = new FType(8, 24) val D = new FType(11, 53) val all = List(H, S, D) } trait HasFPUParameters { require(fLen == 0 \|\| FType.all.exists(_.ieeeWidth == fLen)) val minFLen: Int val fLen: Int def xLen: Int val minXLen = 32 val nIntTypes = log2Ceil(xLen/minXLen) + 1 def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen) def minType = floatTypes.head def maxType = floatTypes.last def prevType(t: FType) = floatTypes(typeTag(t) - 1) def maxExpWidth = maxType.exp def maxSigWidth = maxType.sig def typeTag(t: FType) = floatTypes.indexOf(t) def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U // typeTag def H = typeTagGroup(FType.H) def S = typeTagGroup(FType.S) def D = typeTagGroup(FType.D) def I = typeTag(maxType).U private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = { require(xt.ieeeWidth == 2 * yt.ieeeWidth) val swizzledNaN = Cat( x(xt.sig + xt.exp, xt.sig + xt.exp - 3), x(xt.sig - 2, yt.recodedWidth - 1).andR, x(xt.sig + xt.exp - 5, xt.sig), y(yt.recodedWidth - 2), x(xt.sig - 2, yt.recodedWidth - 1), y(yt.recodedWidth - 1), y(yt.recodedWidth - 3, 0)) Mux(xt.isNaN(x), swizzledNaN, x) } // implement NaN unboxing for FU inputs def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = { val outType = exactType.getOrElse(maxType) def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = { val prev = if (t == minType) { Seq() } else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prev = helper(unswizzled, prevT) val isbox = isBox(x, t) prev.map(p => (isbox && p._1, p._2)) } prev :+ (true.B, t.unsafeConvert(x, outType)) } val (oks, floats) = helper(x, maxType).unzip if (exactType.isEmpty \|\| floatTypes.size == 1) { Mux(oks(tag), floats(tag), maxType.qNaN) } else { val t = exactType.get floats(typeTag(t)) \| Mux(oks(typeTag(t)), 0.U, t.qNaN) } } // make sure that the redundant bits in the NaN-boxed encoding are consistent def consistent(x: UInt): Bool = { def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prevOK = !isBox(x, t) \|\| helper(unswizzled, prevT) val curOK = !t.isNaN(x) \|\| x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR prevOK && curOK } helper(x, maxType) } // generate a NaN box from an FU result def box(x: UInt, t: FType): UInt = { if (t == maxType) { x } else { val nt = floatTypes(typeTag(t) + 1) val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t) bigger \| ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U } } // generate a NaN box from an FU result def box(x: UInt, tag: UInt): UInt = { val opts = floatTypes.map(t => box(x, t)) opts(tag) } // zap bits that hardfloat thinks are don't-cares, but we do care about def sanitizeNaN(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { x } else { val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) \| (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W) Mux(t.isNaN(x), maskedNaN, x) } } // implement NaN boxing and recoding for FL/fmv..x def recode(x: UInt, tag: UInt): UInt = { def helper(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { t.recode(x) } else { val prevT = prevType(t) box(t.recode(x), t, helper(x, prevT), prevT) } } // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U) helper(boxes(tag) \| x, maxType) } // implement NaN unboxing and un-recoding for FS/fmv.x. def ieee(x: UInt, t: FType = maxType): UInt = { if (typeTag(t) == 0) { t.ieee(x) } else { val unrecoded = t.ieee(x) val prevT = prevType(t) val prevRecoded = Cat( x(prevT.recodedWidth-2), x(t.sig-1), x(prevT.recodedWidth-3, 0)) val prevUnrecoded = ieee(prevRecoded, prevT) Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0))) } } } abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { class Output extends Bundle { val in = new FPInput val lt = Bool() val store = Bits(fLen.W) val toint = Bits(xLen.W) val exc = Bits(FPConstants.FLAGS_SZ.W) } val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new Output) }) val in = RegEnable(io.in.bits, io.in.valid) val valid = RegNext(io.in.valid) val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth)) dcmp.io.a := in.in1 dcmp.io.b := in.in2 dcmp.io.signaling := !in.rm(1) val tag = in.typeTagOut val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen)) else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) val toint = WireDefault(toint_ieee) val intType = WireDefault(in.fmt(0)) io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType) io.out.bits.exc := 0.U when (in.rm(0)) { val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag) toint := classify_out \| (toint_ieee >> minXLen << minXLen) intType := false.B } when (in.wflags) { // feq/flt/fle, fcvt toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR \| (toint_ieee >> minXLen << minXLen) io.out.bits.exc := dcmp.io.exceptionFlags intType := false.B when (!in.ren2) { // fcvt val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1) intType := cvtType val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen)) conv.io.in := in.in1 conv.io.roundingMode := in.rm conv.io.signedOut := ~in.typ(0) toint := conv.io.out io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0)) for (i <- 0 until nIntTypes-1) { val w = minXLen << i when (cvtType === i.U) { val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w)) narrow.io.in := in.in1 narrow.io.roundingMode := in.rm narrow.io.signedOut := ~in.typ(0) val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1) val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign)) val invalid = conv.io.intExceptionFlags(2) \|\| narrow.io.intExceptionFlags(1) when (invalid) { toint := Cat(conv.io.out >> w, excOut) } io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0)) } } } } io.out.valid := valid io.out.bits.lt := dcmp.io.lt \|\| (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S) io.out.bits.in := in } class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new IntToFPInput)) val out = Valid(new FPResult) }) val in = Pipe(io.in) val tag = in.bits.typeTagIn val mux = Wire(new FPResult) mux.exc := 0.U mux.data := recode(in.bits.in1, tag) val intValue = { val res = WireDefault(in.bits.in1.asSInt) for (i <- 0 until nIntTypes-1) { val smallInt = in.bits.in1((minXLen << i) - 1, 0) when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) { res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt) } } res.asUInt } when (in.bits.wflags) { // fcvt // could be improved for RVD/RVQ with a single variable-position rounding // unit, rather than N fixed-position ones val i2fResults = for (t <- floatTypes) yield { val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig)) i2f.io.signedIn := ~in.bits.typ(0) i2f.io.in := intValue i2f.io.roundingMode := in.bits.rm i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags) } val (data, exc) = i2fResults.unzip val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last mux.data := dataPadded(tag) mux.exc := exc(tag) } io.out <> Pipe(in.valid, mux, latency-1) } class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) val lt = Input(Bool()) // from FPToInt }) val in = Pipe(io.in) val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2)) val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0)) val fsgnjMux = Wire(new FPResult) fsgnjMux.exc := 0.U fsgnjMux.data := fsgnj when (in.bits.wflags) { // fmin/fmax val isnan1 = maxType.isNaN(in.bits.in1) val isnan2 = maxType.isNaN(in.bits.in2) val isInvalid = maxType.isSNaN(in.bits.in1) \|\| maxType.isSNaN(in.bits.in2) val isNaNOut = isnan1 && isnan2 val isLHS = isnan2 \|\| in.bits.rm(0) =/= io.lt && !isnan1 fsgnjMux.exc := isInvalid << 4 fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2)) } val inTag = in.bits.typeTagIn val outTag = in.bits.typeTagOut val mux = WireDefault(fsgnjMux) for (t <- floatTypes.init) { when (outTag === typeTag(t).U) { mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t)) } } when (in.bits.wflags && !in.bits.ren2) { // fcvt if (floatTypes.size > 1) { // widening conversions simply canonicalize NaN operands val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1) fsgnjMux.data := widened fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4 // narrowing conversions require rounding (for RVQ, this could be // optimized to use a single variable-position rounding unit, rather // than two fixed-position ones) for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B \|\| outTag < inTag)) { val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig)) narrower.io.in := in.bits.in1 narrower.io.roundingMode := in.bits.rm narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding val narrowed = sanitizeNaN(narrower.io.out, outType) mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed) mux.exc := narrower.io.exceptionFlags } } } io.out <> Pipe(in.valid, mux, latency-1) } class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module { override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}" require(latency<=2) val io = IO(new Bundle { val validin = Input(Bool()) val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) val validout = Output(Bool()) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC val valid_stage0 = Wire(Bool()) val roundingMode_stage0 = Wire(UInt(3.W)) val detectTininess_stage0 = Wire(UInt(1.W)) val postmul_regs = if(latency>0) 1 else 0 mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0)) val round_regs = if(latency==2) 1 else 0 roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits io.validout := Pipe(valid_stage0, false.B, round_regs).valid roundRawFNToRecFN.io.infiniteExc := false.B io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } class FPUFMAPipe(val latency: Int, val t: FType) (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}" require(latency>0) val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) }) val valid = RegNext(io.in.valid) val in = Reg(new FPInput) when (io.in.valid) { val one = 1.U << (t.sig + t.exp - 1) val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp)) val cmd_fma = io.in.bits.ren3 val cmd_addsub = io.in.bits.swap23 in := io.in.bits when (cmd_addsub) { in.in2 := one } when (!(cmd_fma \|\| cmd_addsub)) { in.in3 := zero } } val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig)) fma.io.validin := valid fma.io.op := in.fmaCmd fma.io.roundingMode := in.rm fma.io.detectTininess := hardfloat.consts.tininess_afterRounding fma.io.a := in.in1 fma.io.b := in.in2 fma.io.c := in.in3 val res = Wire(new FPResult) res.data := sanitizeNaN(fma.io.out, t) res.exc := fma.io.exceptionFlags io.out := Pipe(fma.io.validout, res, (latency-3) max 0) } class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new FPUIO) val (useClockGating, useDebugROB) = coreParams match { case r: RocketCoreParams => val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1 (r.clockGate, sz < 1) case _ => (false, false) } val clock_en_reg = Reg(Bool()) val clock_en = clock_en_reg \|\| io.cp_req.valid val gated_clock = if (!useClockGating) clock else ClockGate(clock, clock_en, "fpu_clock_gate") val fp_decoder = Module(new FPUDecoder) fp_decoder.io.inst := io.inst val id_ctrl = WireInit(fp_decoder.io.sigs) coreParams match { case r: RocketCoreParams => r.vector.map(v => { val v_decode = v.decoder(p) // Only need to get ren1 v_decode.io.inst := io.inst v_decode.io.vconfig := DontCare // core deals with this when (v_decode.io.legal && v_decode.io.read_frs1) { id_ctrl.ren1 := true.B id_ctrl.swap12 := false.B id_ctrl.toint := true.B id_ctrl.typeTagIn := I id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S) } when (v_decode.io.write_frd) { id_ctrl.wen := true.B } })} val ex_reg_valid = RegNext(io.valid, false.B) val ex_reg_inst = RegEnable(io.inst, io.valid) val ex_reg_ctrl = RegEnable(id_ctrl, io.valid) val ex_ra = List.fill(3)(Reg(UInt())) // load/vector response val load_wb = RegNext(io.ll_resp_val) val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val) val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val) val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val) class FPUImpl { // entering gated-clock domain val req_valid = ex_reg_valid \|\| io.cp_req.valid val ex_cp_valid = io.cp_req.fire val mem_cp_valid = RegNext(ex_cp_valid, false.B) val wb_cp_valid = RegNext(mem_cp_valid, false.B) val mem_reg_valid = RegInit(false.B) val killm = (io.killm \|\| io.nack_mem) && !mem_cp_valid // Kill X-stage instruction if M-stage is killed. This prevents it from // speculatively being sent to the div-sqrt unit, which can cause priority // inversion for two back-to-back divides, the first of which is killed. val killx = io.killx \|\| mem_reg_valid && killm mem_reg_valid := ex_reg_valid && !killx \|\| ex_cp_valid val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid) val wb_reg_valid = RegNext(mem_reg_valid && (!killm \|\| mem_cp_valid), false.B) val cp_ctrl = Wire(new FPUCtrlSigs) cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs) io.cp_resp.valid := false.B io.cp_resp.bits.data := 0.U io.cp_resp.bits.exc := DontCare val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl) val mem_ctrl = RegEnable(ex_ctrl, req_valid) val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid) // CoreMonitorBundle to monitor fp register file writes val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare)) frfWriteBundle.foreach { i => i.clock := clock i.reset := reset i.hartid := io.hartid i.timer := io.time(31,0) i.valid := false.B i.wrenx := false.B i.wrenf := false.B i.excpt := false.B } // regfile val regfile = Mem(32, Bits((fLen+1).W)) when (load_wb) { val wdata = recode(load_wb_data, load_wb_typeTag) regfile(load_wb_tag) := wdata assert(consistent(wdata)) if (enableCommitLog) printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata)) if (useDebugROB) DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata)) frfWriteBundle(0).wrdst := load_wb_tag frfWriteBundle(0).wrenf := true.B frfWriteBundle(0).wrdata := ieee(wdata) } val ex_rs = ex_ra.map(a => regfile(a)) when (io.valid) { when (id_ctrl.ren1) { when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) } when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) } } when (id_ctrl.ren2) { when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) } when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) } when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) } } when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) } } val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12)) def fuInput(minT: Option[FType]): FPInput = { val req = Wire(new FPInput) val tag = ex_ctrl.typeTagIn req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs) req.rm := ex_rm req.in1 := unbox(ex_rs(0), tag, minT) req.in2 := unbox(ex_rs(1), tag, minT) req.in3 := unbox(ex_rs(2), tag, minT) req.typ := ex_reg_inst(21,20) req.fmt := ex_reg_inst(26,25) req.fmaCmd := ex_reg_inst(3,2) \| (!ex_ctrl.ren3 && ex_reg_inst(27)) when (ex_cp_valid) { req := io.cp_req.bits when (io.cp_req.bits.swap12) { req.in1 := io.cp_req.bits.in2 req.in2 := io.cp_req.bits.in1 } when (io.cp_req.bits.swap23) { req.in2 := io.cp_req.bits.in3 req.in3 := io.cp_req.bits.in2 } } req } val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S)) sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S sfma.io.in.bits := fuInput(Some(sfma.t)) val fpiu = Module(new FPToInt) fpiu.io.in.valid := req_valid && (ex_ctrl.toint \|\| ex_ctrl.div \|\| ex_ctrl.sqrt \|\| (ex_ctrl.fastpipe && ex_ctrl.wflags)) fpiu.io.in.bits := fuInput(None) io.store_data := fpiu.io.out.bits.store io.toint_data := fpiu.io.out.bits.toint when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){ io.cp_resp.bits.data := fpiu.io.out.bits.toint io.cp_resp.valid := true.B } val ifpu = Module(new IntToFP(cfg.ifpuLatency)) ifpu.io.in.valid := req_valid && ex_ctrl.fromint ifpu.io.in.bits := fpiu.io.in.bits ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) val fpmu = Module(new FPToFP(cfg.fpmuLatency)) fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe fpmu.io.in.bits := fpiu.io.in.bits fpmu.io.lt := fpiu.io.out.bits.lt val divSqrt_wen = WireDefault(false.B) val divSqrt_inFlight = WireDefault(false.B) val divSqrt_waddr = Reg(UInt(5.W)) val divSqrt_cp = Reg(Bool()) val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W)) val divSqrt_wdata = Wire(UInt((fLen+1).W)) val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W)) divSqrt_typeTag := DontCare divSqrt_wdata := DontCare divSqrt_flags := DontCare // writeback arbitration case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult) val pipes = List( Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits), Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits), Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++ (fLen > 32).option({ val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D)) dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D dfma.io.in.bits := fuInput(Some(dfma.t)) Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits) }) ++ (minFLen == 16).option({ val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H)) hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H hfma.io.in.bits := fuInput(Some(hfma.t)) Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits) }) def latencyMask(c: FPUCtrlSigs, offset: Int) = { require(pipes.forall(_.lat >= offset)) pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_\|_) } def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_\|_) val maxLatency = pipes.map(_.lat).max val memLatencyMask = latencyMask(mem_ctrl, 2) class WBInfo extends Bundle { val rd = UInt(5.W) val typeTag = UInt(log2Up(floatTypes.size).W) val cp = Bool() val pipeid = UInt(log2Ceil(pipes.size).W) } val wen = RegInit(0.U((maxLatency-1).W)) val wbInfo = Reg(Vec(maxLatency-1, new WBInfo)) val mem_wen = mem_reg_valid && (mem_ctrl.fma \|\| mem_ctrl.fastpipe \|\| mem_ctrl.fromint) val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR \|\| (wen & latencyMask(ex_ctrl, 0)).orR, req_valid) ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback") for (i <- 0 until maxLatency-2) { when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) } } wen := wen >> 1 when (mem_wen) { when (!killm) { wen := wen >> 1 \| memLatencyMask } for (i <- 0 until maxLatency-1) { when (!write_port_busy && memLatencyMask(i)) { wbInfo(i).cp := mem_cp_valid wbInfo(i).typeTag := mem_ctrl.typeTagOut wbInfo(i).pipeid := pipeid(mem_ctrl) wbInfo(i).rd := mem_reg_inst(11,7) } } } val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd) val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp) val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag) val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag) val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid) when ((!wbInfo(0).cp && wen(0)) \|\| divSqrt_wen) { assert(consistent(wdata)) regfile(waddr) := wdata if (enableCommitLog) { printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata)) } frfWriteBundle(1).wrdst := waddr frfWriteBundle(1).wrenf := true.B frfWriteBundle(1).wrdata := ieee(wdata) } if (useDebugROB) { DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) \|\| divSqrt_wen, waddr + 32.U, ieee(wdata)) } when (wb_cp && (wen(0) \|\| divSqrt_wen)) { io.cp_resp.bits.data := wdata io.cp_resp.valid := true.B } assert(!io.cp_req.valid \|\| pipes.forall(_.lat == pipes.head.lat).B, s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}") // Avoid structural hazards and nacking of external requests // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight val wb_toint_valid = wb_reg_valid && wb_ctrl.toint val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint) io.fcsr_flags.valid := wb_toint_valid \|\| divSqrt_wen \|\| wen(0) io.fcsr_flags.bits := Mux(wb_toint_valid, wb_toint_exc, 0.U) \| Mux(divSqrt_wen, divSqrt_flags, 0.U) \| Mux(wen(0), wexc, 0.U) val divSqrt_write_port_busy = (mem_ctrl.div \|\| mem_ctrl.sqrt) && wen.orR io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags \|\| mem_reg_valid && mem_ctrl.wflags \|\| wb_reg_valid && wb_ctrl.toint \|\| wen.orR \|\| divSqrt_inFlight) io.nack_mem := (write_port_busy \|\| divSqrt_write_port_busy \|\| divSqrt_inFlight) && !mem_cp_valid io.dec <> id_ctrl def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_\|\|_) io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) \|\| mem_ctrl.div \|\| mem_ctrl.sqrt \|\| mem_ctrl.vec) io.sboard_clr := !wb_cp_valid && (divSqrt_wen \|\| (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U))) io.sboard_clra := waddr ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle") // we don't currently support round-max-magnitude (rm=4) io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) \|\| io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U if (cfg.divSqrt) { val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div \|\| mem_ctrl.sqrt) && !divSqrt_inFlight val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B) when (divSqrt_inValid) { divSqrt_waddr := mem_reg_inst(11,7) divSqrt_cp := mem_cp_valid } ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider") ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div \|\| mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard") ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback") for (t <- floatTypes) { val tag = mem_ctrl.typeTagOut val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) } divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U divSqrt.io.sqrtOp := mem_ctrl.sqrt divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t) divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t) divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight when (divSqrt.io.outValid_div \|\| divSqrt.io.outValid_sqrt) { divSqrt_wen := !divSqrt_killed divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t) divSqrt_flags := divSqrt.io.exceptionFlags divSqrt_typeTag := typeTag(t).U } } when (divSqrt_killed) { divSqrt_inFlight := false.B } } else { when (id_ctrl.div \|\| id_ctrl.sqrt) { io.illegal_rm := true.B } } // gate the clock clock_en_reg := !useClockGating.B \|\| io.keep_clock_enabled \|\| // chicken bit io.valid \|\| // ID stage req_valid \|\| // EX stage mem_reg_valid \|\| mem_cp_valid \|\| // MEM stage wb_reg_valid \|\| wb_cp_valid \|\| // WB stage wen.orR \|\| divSqrt_inFlight \|\| // post-WB stage io.ll_resp_val // load writeback } // leaving gated-clock domain val fpuImpl = withClock (gated_clock) { new FPUImpl } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"FPU_$label", "Core;;" + desc) }	module FPToFP( // @[FPU.scala:573:7] input clock, // @[FPU.scala:573:7] input reset, // @[FPU.scala:573:7] input io_in_valid, // @[FPU.scala:574:14] input io_in_bits_ren2, // @[FPU.scala:574:14] input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:574:14] input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:574:14] input io_in_bits_wflags, // @[FPU.scala:574:14] input [2:0] io_in_bits_rm, // @[FPU.scala:574:14] input [64:0] io_in_bits_in1, // @[FPU.scala:574:14] input [64:0] io_in_bits_in2, // @[FPU.scala:574:14] output [64:0] io_out_bits_data, // @[FPU.scala:574:14] output [4:0] io_out_bits_exc, // @[FPU.scala:574:14] input io_lt // @[FPU.scala:574:14] ); wire [32:0] _narrower_1_io_out; // @[FPU.scala:619:30] wire [4:0] _narrower_1_io_exceptionFlags; // @[FPU.scala:619:30] wire [16:0] _narrower_io_out; // @[FPU.scala:619:30] wire [4:0] _narrower_io_exceptionFlags; // @[FPU.scala:619:30] reg in_pipe_v; // @[Valid.scala:141:24] reg in_pipe_b_ren2; // @[Valid.scala:142:26] reg [1:0] in_pipe_b_typeTagIn; // @[Valid.scala:142:26] reg [1:0] in_pipe_b_typeTagOut; // @[Valid.scala:142:26] reg in_pipe_b_wflags; // @[Valid.scala:142:26] reg [2:0] in_pipe_b_rm; // @[Valid.scala:142:26] reg [64:0] in_pipe_b_in1; // @[Valid.scala:142:26] reg [64:0] in_pipe_b_in2; // @[Valid.scala:142:26] wire _GEN = in_pipe_b_wflags & ~in_pipe_b_ren2; // @[Valid.scala:142:26] wire [64:0] fsgnjMux_data = _GEN ? ((&(in_pipe_b_in1[63:61])) ? 65'hE008000000000000 : in_pipe_b_in1) : in_pipe_b_wflags ? ((&(in_pipe_b_in1[63:61])) & (&(in_pipe_b_in2[63:61])) ? 65'hE008000000000000 : (&(in_pipe_b_in2[63:61])) \| in_pipe_b_rm[0] != io_lt & ~(&(in_pipe_b_in1[63:61])) ? in_pipe_b_in1 : in_pipe_b_in2) : {in_pipe_b_rm[1] ? in_pipe_b_in1[64] ^ in_pipe_b_in2[64] : in_pipe_b_rm[0] ^ in_pipe_b_in2[64], in_pipe_b_in1[63:0]}; // @[Valid.scala:142:26] reg [64:0] io_out_pipe_b_data; // @[Valid.scala:142:26] reg [4:0] io_out_pipe_b_exc; // @[Valid.scala:142:26] wire [4:0] _GEN_0 = in_pipe_b_wflags ? {(&(in_pipe_b_in1[63:61])) & ~(in_pipe_b_in1[51]) \| (&(in_pipe_b_in2[63:61])) & ~(in_pipe_b_in2[51]), 4'h0} : 5'h0; // @[Valid.scala:142:26] wire _GEN_1 = in_pipe_b_typeTagOut == 2'h0; // @[Valid.scala:142:26] wire [5:0] _mux_data_expOut_commonCase_T = fsgnjMux_data[57:52] - 6'h20; // @[FPU.scala:276:18, :280:31, :589:25, :608:42, :612:21] wire _GEN_2 = in_pipe_b_typeTagOut == 2'h1; // @[Valid.scala:142:26] wire [8:0] _mux_data_expOut_commonCase_T_3 = fsgnjMux_data[60:52] - 9'h100; // @[FPU.scala:276:18, :280:31, :589:25, :608:42, :612:21] wire [64:0] _mux_data_T_5 = {fsgnjMux_data[64:33], fsgnjMux_data[64], fsgnjMux_data[63:61] == 3'h0 \| fsgnjMux_data[63:61] > 3'h5 ? {fsgnjMux_data[63:61], _mux_data_expOut_commonCase_T_3[5:0]} : _mux_data_expOut_commonCase_T_3, fsgnjMux_data[51:29]}; // @[FPU.scala:274:17, :276:18, :277:38, :279:26, :280:{31,50}, :281:{10,19,27,38,49,69}, :589:25, :604:{22,37}, :608:42, :612:21] wire _GEN_3 = _GEN_2 & in_pipe_b_typeTagOut < in_pipe_b_typeTagIn; // @[Valid.scala:142:26] always @(posedge clock) begin // @[FPU.scala:573:7] if (reset) // @[FPU.scala:573:7] in_pipe_v <= 1'h0; // @[Valid.scala:141:24] else // @[FPU.scala:573:7] in_pipe_v <= io_in_valid; // @[Valid.scala:141:24] if (io_in_valid) begin // @[FPU.scala:574:14] in_pipe_b_ren2 <= io_in_bits_ren2; // @[Valid.scala:142:26] in_pipe_b_typeTagIn <= io_in_bits_typeTagIn; // @[Valid.scala:142:26] in_pipe_b_typeTagOut <= io_in_bits_typeTagOut; // @[Valid.scala:142:26] in_pipe_b_wflags <= io_in_bits_wflags; // @[Valid.scala:142:26] in_pipe_b_rm <= io_in_bits_rm; // @[Valid.scala:142:26] in_pipe_b_in1 <= io_in_bits_in1; // @[Valid.scala:142:26] in_pipe_b_in2 <= io_in_bits_in2; // @[Valid.scala:142:26] end if (in_pipe_v) begin // @[Valid.scala:141:24] io_out_pipe_b_data <= _GEN ? (_GEN_3 ? {fsgnjMux_data[64:33], ({33{_narrower_1_io_out[31:29] != 3'h7}} \| 33'h1EF7FFFFF) & _narrower_1_io_out} : _GEN_1 ? {fsgnjMux_data[64:17], _narrower_io_out} : _GEN_2 ? _mux_data_T_5 : fsgnjMux_data) : _GEN_2 ? _mux_data_T_5 : _GEN_1 ? {fsgnjMux_data[64:17], fsgnjMux_data[64], fsgnjMux_data[63:61] == 3'h0 \| fsgnjMux_data[63:61] > 3'h5 ? {fsgnjMux_data[63:61], _mux_data_expOut_commonCase_T[2:0]} : _mux_data_expOut_commonCase_T, fsgnjMux_data[51:42]} : fsgnjMux_data; // @[Valid.scala:142:26] io_out_pipe_b_exc <= _GEN ? (_GEN_3 ? _narrower_1_io_exceptionFlags : _GEN_1 ? _narrower_io_exceptionFlags : _GEN ? {(&(in_pipe_b_in1[63:61])) & ~(in_pipe_b_in1[51]), 4'h0} : _GEN_0) : _GEN_0; // @[Valid.scala:142:26] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_246( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_263 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File BusBypass.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.tilelink import chisel3._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ abstract class TLBusBypassBase(beatBytes: Int, deadlock: Boolean = false, bufferError: Boolean = true, maxAtomic: Int = 16, maxTransfer: Int = 4096) (implicit p: Parameters) extends LazyModule { protected val nodeIn = TLIdentityNode() protected val nodeOut = TLIdentityNode() val node = NodeHandle(nodeIn, nodeOut) protected val bar = LazyModule(new TLBusBypassBar(dFn = { mp => mp.v1copy(managers = mp.managers.map { m => m.v1copy( mayDenyPut = m.mayDenyPut \|\| !deadlock, mayDenyGet = m.mayDenyGet \|\| !deadlock) }) })) protected val everything = Seq(AddressSet(0, BigInt("ffffffffffffffffffffffffffffffff", 16))) // 128-bit protected val params = DevNullParams(everything, maxAtomic, maxTransfer, region=RegionType.TRACKED) protected val error = if (deadlock) LazyModule(new TLDeadlock(params, beatBytes)) else LazyModule(new TLError(params, bufferError, beatBytes)) // order matters because the parameters and bypass // assume that the non-bypassed connection is // the last connection to the bar, so keep nodeOut last. bar.node := nodeIn error.node := bar.node nodeOut := bar.node } class TLBusBypass(beatBytes: Int, bufferError: Boolean = false, maxAtomic: Int = 16, maxTransfer: Int = 4096)(implicit p: Parameters) extends TLBusBypassBase(beatBytes, deadlock = false, bufferError = bufferError, maxAtomic = maxAtomic, maxTransfer = maxTransfer) { lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val bypass = Input(Bool()) }) bar.module.io.bypass := io.bypass } } class TLBypassNode(dFn: TLSlavePortParameters => TLSlavePortParameters)(implicit valName: ValName) extends TLCustomNode { def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = { require (iStars == 0 && oStars == 0, "TLBypass node does not support := or :=") require (iKnown == 1, "TLBypass node expects exactly one input") require (oKnown == 2, "TLBypass node expects exactly two outputs") (0, 0) } def mapParamsD(n: Int, p: Seq[TLMasterPortParameters]): Seq[TLMasterPortParameters] = { p ++ p } def mapParamsU(n: Int, p: Seq[TLSlavePortParameters]): Seq[TLSlavePortParameters] = { Seq(dFn(p.last).v1copy(minLatency = p.map(_.minLatency).min))} } class TLBusBypassBar(dFn: TLSlavePortParameters => TLSlavePortParameters)(implicit p: Parameters) extends LazyModule { val node = new TLBypassNode(dFn) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val bypass = Input(Bool()) val pending = Output(Bool()) }) val (in, edgeIn) = node.in(0) val Seq((out0, edgeOut0), (out1, edgeOut1)) = node.out require (edgeOut0.manager.beatBytes == edgeOut1.manager.beatBytes, s"BusBypass slave device widths mismatch (${edgeOut0.manager.managers.map(_.name)} has ${edgeOut0.manager.beatBytes}B vs ${edgeOut1.manager.managers.map(_.name)} has ${edgeOut1.manager.beatBytes}B)") // We need to be locked to the given bypass direction until all transactions stop val in_reset = RegNext(false.B, init = true.B) val bypass_reg = Reg(Bool()) val bypass = Mux(in_reset, io.bypass, bypass_reg) val (flight, next_flight) = edgeIn.inFlight(in) io.pending := (flight > 0.U) when (in_reset \|\| (next_flight === 0.U)) { bypass_reg := io.bypass } val stall = (bypass =/= io.bypass) && edgeIn.first(in.a) out0.a.valid := !stall && in.a.valid && bypass out1.a.valid := !stall && in.a.valid && !bypass in.a.ready := !stall && Mux(bypass, out0.a.ready, out1.a.ready) out0.a.bits := in.a.bits out1.a.bits := in.a.bits out0.d.ready := in.d.ready && bypass out1.d.ready := in.d.ready && !bypass in.d.valid := Mux(bypass, out0.d.valid, out1.d.valid) def cast(x: TLBundleD) = { val out = WireDefault(in.d.bits); out <> x; out } in.d.bits := Mux(bypass, cast(out0.d.bits), cast(out1.d.bits)) if (edgeIn.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { out0.b.ready := in.b.ready && bypass out1.b.ready := in.b.ready && !bypass in.b.valid := Mux(bypass, out0.b.valid, out1.b.valid) def cast(x: TLBundleB) = { val out = Wire(in.b.bits); out <> x; out } in.b.bits := Mux(bypass, cast(out0.b.bits), cast(out1.b.bits)) out0.c.valid := in.c.valid && bypass out1.c.valid := in.c.valid && !bypass in.c.ready := Mux(bypass, out0.c.ready, out1.c.ready) out0.c.bits := in.c.bits out1.c.bits := in.c.bits out0.e.valid := in.e.valid && bypass out1.e.valid := in.e.valid && !bypass in.e.ready := Mux(bypass, out0.e.ready, out1.e.ready) out0.e.bits := in.e.bits out1.e.bits := in.e.bits } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out0.b.ready := true.B out0.c.valid := false.B out0.e.valid := false.B out1.b.ready := true.B out1.c.valid := false.B out1.e.valid := false.B } } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLBusBypassBar( // @[BusBypass.scala:66:9] input clock, // @[BusBypass.scala:66:9] input reset, // @[BusBypass.scala:66:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_bypass // @[BusBypass.scala:67:16] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BusBypass.scala:66:9] wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BusBypass.scala:66:9] wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BusBypass.scala:66:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[BusBypass.scala:66:9] wire auto_out_1_a_ready_0 = auto_out_1_a_ready; // @[BusBypass.scala:66:9] wire auto_out_1_d_valid_0 = auto_out_1_d_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_d_bits_opcode_0 = auto_out_1_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] auto_out_1_d_bits_param_0 = auto_out_1_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] auto_out_1_d_bits_size_0 = auto_out_1_d_bits_size; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_source_0 = auto_out_1_d_bits_source; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_sink_0 = auto_out_1_d_bits_sink; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_denied_0 = auto_out_1_d_bits_denied; // @[BusBypass.scala:66:9] wire [31:0] auto_out_1_d_bits_data_0 = auto_out_1_d_bits_data; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_corrupt_0 = auto_out_1_d_bits_corrupt; // @[BusBypass.scala:66:9] wire auto_out_0_a_ready_0 = auto_out_0_a_ready; // @[BusBypass.scala:66:9] wire auto_out_0_d_valid_0 = auto_out_0_d_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_d_bits_opcode_0 = auto_out_0_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] auto_out_0_d_bits_param_0 = auto_out_0_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] auto_out_0_d_bits_size_0 = auto_out_0_d_bits_size; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_denied_0 = auto_out_0_d_bits_denied; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_corrupt_0 = auto_out_0_d_bits_corrupt; // @[BusBypass.scala:66:9] wire io_bypass_0 = io_bypass; // @[BusBypass.scala:66:9] wire [4:0] _r_beats1_decode_T_3 = 5'h3; // @[package.scala:243:71] wire [4:0] _r_beats1_decode_T_6 = 5'h3; // @[package.scala:243:71] wire [3:0] _b_inc_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _b_inc_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _b_dec_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _b_dec_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [8:0] _b_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74] wire [8:0] _b_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61] wire [8:0] _c_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _b_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74] wire [8:0] _b_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61] wire [8:0] _c_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [4:0] _r_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _stall_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [1:0] _r_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _r_beats1_decode_T_5 = 2'h0; // @[package.scala:243:46] wire [1:0] _r_beats1_decode_T_8 = 2'h0; // @[package.scala:243:46] wire [1:0] _b_inc_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_inc_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _b_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _c_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _b_dec_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_dec_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _b_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _c_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _stall_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [31:0] auto_out_0_d_bits_data = 32'h0; // @[BusBypass.scala:66:9] wire [31:0] nodeOut_d_bits_data = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] _b_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _b_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _c_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _b_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _b_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _c_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] nodeIn_d_bits_out_data = 32'h0; // @[BusBypass.scala:97:53] wire [3:0] auto_in_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] auto_out_1_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] auto_out_0_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] nodeIn_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] x1_nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [1:0] auto_in_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] auto_out_1_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] auto_out_0_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] nodeIn_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] x1_nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [2:0] auto_in_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] _b_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _b_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _c_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_inc_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_inc_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _b_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _b_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _c_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_dec_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_dec_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [1:0] _r_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _r_beats1_decode_T_4 = 2'h3; // @[package.scala:243:76] wire [1:0] _r_counter1_T_1 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _r_beats1_decode_T_7 = 2'h3; // @[package.scala:243:76] wire [1:0] _r_counter1_T_2 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _r_counter1_T_4 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _stall_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire _r_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_last = 1'h1; // @[Edges.scala:232:33] wire r_beats1_opdata_1 = 1'h1; // @[Edges.scala:97:28] wire r_counter1_1 = 1'h1; // @[Edges.scala:230:28] wire b_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire b_last = 1'h1; // @[Edges.scala:232:33] wire r_counter1_2 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire c_last = 1'h1; // @[Edges.scala:232:33] wire _r_last_T_7 = 1'h1; // @[Edges.scala:232:43] wire d_last = 1'h1; // @[Edges.scala:232:33] wire r_counter1_4 = 1'h1; // @[Edges.scala:230:28] wire e_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_9 = 1'h1; // @[Edges.scala:232:43] wire e_last = 1'h1; // @[Edges.scala:232:33] wire c_response = 1'h1; // @[Edges.scala:82:41] wire _stall_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire stall_last = 1'h1; // @[Edges.scala:232:33] wire auto_in_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_in_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_1_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_1_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_sink = 1'h0; // @[BusBypass.scala:66:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire r_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire r_beats1 = 1'h0; // @[Edges.scala:221:14] wire r_4 = 1'h0; // @[Edges.scala:234:25] wire r_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire _r_beats1_opdata_T_1 = 1'h0; // @[Edges.scala:97:37] wire r_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire _r_last_T_2 = 1'h0; // @[Edges.scala:232:25] wire r_3_1 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_1 = 1'h0; // @[Edges.scala:234:27] wire r_4_1 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_1 = 1'h0; // @[Edges.scala:236:21] wire r_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire r_beats1_opdata_2 = 1'h0; // @[Edges.scala:102:36] wire r_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire _r_last_T_4 = 1'h0; // @[Edges.scala:232:25] wire r_3_2 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_2 = 1'h0; // @[Edges.scala:234:27] wire r_4_2 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_2 = 1'h0; // @[Edges.scala:236:21] wire r_beats1_decode_3 = 1'h0; // @[Edges.scala:220:59] wire r_beats1_3 = 1'h0; // @[Edges.scala:221:14] wire r_4_3 = 1'h0; // @[Edges.scala:234:25] wire _r_last_T_8 = 1'h0; // @[Edges.scala:232:25] wire r_3_4 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_4 = 1'h0; // @[Edges.scala:234:27] wire r_4_4 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_4 = 1'h0; // @[Edges.scala:236:21] wire c_request = 1'h0; // @[Edges.scala:68:40] wire _b_inc_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _b_inc_T_1 = 1'h0; // @[Edges.scala:311:26] wire b_inc = 1'h0; // @[Edges.scala:311:37] wire _c_inc_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _c_inc_T_1 = 1'h0; // @[Edges.scala:312:26] wire c_inc = 1'h0; // @[Edges.scala:312:37] wire _e_inc_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _e_inc_T_1 = 1'h0; // @[Edges.scala:314:26] wire e_inc = 1'h0; // @[Edges.scala:314:37] wire a_dec = 1'h0; // @[Edges.scala:317:36] wire _b_dec_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _b_dec_T_1 = 1'h0; // @[Edges.scala:318:26] wire b_dec = 1'h0; // @[Edges.scala:318:36] wire _c_dec_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _c_dec_T_1 = 1'h0; // @[Edges.scala:319:26] wire c_dec = 1'h0; // @[Edges.scala:319:36] wire _e_dec_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _e_dec_T_1 = 1'h0; // @[Edges.scala:321:26] wire e_dec = 1'h0; // @[Edges.scala:321:36] wire stall_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire stall_beats1 = 1'h0; // @[Edges.scala:221:14] wire stall_count = 1'h0; // @[Edges.scala:234:25] wire nodeIn_d_bits_out_source = 1'h0; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_sink = 1'h0; // @[BusBypass.scala:97:53] wire nodeIn_a_valid = auto_in_a_valid_0; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BusBypass.scala:66:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[BusBypass.scala:66:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire x1_nodeOut_a_ready = auto_out_1_a_ready_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [8:0] x1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_valid = auto_out_1_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] x1_nodeOut_d_bits_opcode = auto_out_1_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] x1_nodeOut_d_bits_param = auto_out_1_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] x1_nodeOut_d_bits_size = auto_out_1_d_bits_size_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_source = auto_out_1_d_bits_source_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_sink = auto_out_1_d_bits_sink_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_denied = auto_out_1_d_bits_denied_0; // @[BusBypass.scala:66:9] wire [31:0] x1_nodeOut_d_bits_data = auto_out_1_d_bits_data_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_corrupt = auto_out_1_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire nodeOut_a_ready = auto_out_0_a_ready_0; // @[BusBypass.scala:66:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_0_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_0_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] nodeOut_d_bits_param = auto_out_0_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] nodeOut_d_bits_size = auto_out_0_d_bits_size_0; // @[BusBypass.scala:66:9] wire nodeOut_d_bits_denied = auto_out_0_d_bits_denied_0; // @[BusBypass.scala:66:9] wire nodeOut_d_bits_corrupt = auto_out_0_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire _io_pending_T; // @[BusBypass.scala:84:27] wire auto_in_a_ready_0; // @[BusBypass.scala:66:9] wire [2:0] auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] auto_in_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] auto_in_d_bits_size_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_source_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9] wire [31:0] auto_in_d_bits_data_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire auto_in_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [8:0] auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9] wire auto_out_1_a_valid_0; // @[BusBypass.scala:66:9] wire auto_out_1_d_ready_0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [127:0] auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9] wire auto_out_0_a_valid_0; // @[BusBypass.scala:66:9] wire auto_out_0_d_ready_0; // @[BusBypass.scala:66:9] wire io_pending; // @[BusBypass.scala:66:9] wire _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BusBypass.scala:66:9] assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire _nodeIn_d_valid_T; // @[BusBypass.scala:96:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BusBypass.scala:66:9] wire [2:0] _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[BusBypass.scala:66:9] wire [31:0] _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[BusBypass.scala:66:9] wire _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42] assign auto_out_0_a_valid_0 = nodeOut_a_valid; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_address_0 = nodeOut_a_bits_address; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_data_0 = nodeOut_a_bits_data; // @[BusBypass.scala:66:9] wire _nodeOut_d_ready_T; // @[BusBypass.scala:94:32] assign auto_out_0_d_ready_0 = nodeOut_d_ready; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_d_bits_out_opcode = nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_param = nodeOut_d_bits_param; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_size = nodeOut_d_bits_size; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_denied = nodeOut_d_bits_denied; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_corrupt = nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53] wire _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42] assign auto_out_1_a_valid_0 = x1_nodeOut_a_valid; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_opcode_0 = x1_nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_address_0 = x1_nodeOut_a_bits_address; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_data_0 = x1_nodeOut_a_bits_data; // @[BusBypass.scala:66:9] wire _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32] assign auto_out_1_d_ready_0 = x1_nodeOut_d_ready; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_d_bits_out_1_opcode = x1_nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_1_param = x1_nodeOut_d_bits_param; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_1_size = x1_nodeOut_d_bits_size; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_source = x1_nodeOut_d_bits_source; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_sink = x1_nodeOut_d_bits_sink; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_denied = x1_nodeOut_d_bits_denied; // @[BusBypass.scala:97:53] wire [31:0] nodeIn_d_bits_out_1_data = x1_nodeOut_d_bits_data; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_corrupt = x1_nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53] reg in_reset; // @[BusBypass.scala:79:27] reg bypass_reg; // @[BusBypass.scala:80:25] wire bypass = in_reset ? io_bypass_0 : bypass_reg; // @[BusBypass.scala:66:9, :79:27, :80:25, :81:21] reg [1:0] flight; // @[Edges.scala:295:25] wire _T = nodeIn_a_ready & nodeIn_a_valid; // @[Decoupled.scala:51:35] wire r_3; // @[Edges.scala:233:22] assign r_3 = _T; // @[Decoupled.scala:51:35] wire _a_inc_T; // @[Decoupled.scala:51:35] assign _a_inc_T = _T; // @[Decoupled.scala:51:35] wire _a_dec_T; // @[Decoupled.scala:51:35] assign _a_dec_T = _T; // @[Decoupled.scala:51:35] wire _stall_T_1; // @[Decoupled.scala:51:35] assign _stall_T_1 = _T; // @[Decoupled.scala:51:35] wire _r_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire _stall_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire r_beats1_opdata = ~_r_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg r_counter; // @[Edges.scala:229:27] wire _r_last_T = r_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _r_counter1_T = {1'h0, r_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire r_counter1 = _r_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~r_counter; // @[Edges.scala:229:27, :231:25] wire _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire _r_counter_T = ~a_first & r_counter1; // @[Edges.scala:230:28, :231:25, :236:21] wire _T_3 = nodeIn_d_ready & nodeIn_d_valid; // @[Decoupled.scala:51:35] wire r_3_3; // @[Edges.scala:233:22] assign r_3_3 = _T_3; // @[Decoupled.scala:51:35] wire _d_inc_T; // @[Decoupled.scala:51:35] assign _d_inc_T = _T_3; // @[Decoupled.scala:51:35] wire _d_dec_T; // @[Decoupled.scala:51:35] assign _d_dec_T = _T_3; // @[Decoupled.scala:51:35] wire [4:0] _r_beats1_decode_T_9 = 5'h3 << nodeIn_d_bits_size; // @[package.scala:243:71] wire [1:0] _r_beats1_decode_T_10 = _r_beats1_decode_T_9[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _r_beats1_decode_T_11 = ~_r_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire r_beats1_opdata_3 = nodeIn_d_bits_opcode[0]; // @[Edges.scala:106:36] reg r_counter_3; // @[Edges.scala:229:27] wire _r_last_T_6 = r_counter_3; // @[Edges.scala:229:27, :232:25] wire [1:0] _r_counter1_T_3 = {1'h0, r_counter_3} - 2'h1; // @[Edges.scala:229:27, :230:28] wire r_counter1_3 = _r_counter1_T_3[0]; // @[Edges.scala:230:28] wire d_first = ~r_counter_3; // @[Edges.scala:229:27, :231:25] wire _r_count_T_3 = ~r_counter1_3; // @[Edges.scala:230:28, :234:27] wire _r_counter_T_3 = ~d_first & r_counter1_3; // @[Edges.scala:230:28, :231:25, :236:21] wire d_request = nodeIn_d_bits_opcode[2] & ~(nodeIn_d_bits_opcode[1]); // @[Edges.scala:71:{36,40,43,52}] wire _a_inc_T_1 = _a_inc_T & a_first; // @[Decoupled.scala:51:35] wire a_inc = _a_inc_T_1; // @[Edges.scala:310:{26,37}] wire _d_inc_T_1 = _d_inc_T & d_first; // @[Decoupled.scala:51:35] wire d_inc = _d_inc_T_1 & d_request; // @[Edges.scala:71:40, :313:{26,37}] wire [1:0] inc = {a_inc, d_inc}; // @[Edges.scala:310:37, :313:37, :315:18] wire _a_dec_T_1 = _a_dec_T; // @[Decoupled.scala:51:35] wire _d_dec_T_1 = _d_dec_T; // @[Decoupled.scala:51:35] wire d_dec = _d_dec_T_1; // @[Edges.scala:320:{26,36}] wire [1:0] dec = {1'h0, d_dec}; // @[Edges.scala:320:36, :322:18] wire _next_flight_T = inc[0]; // @[Edges.scala:315:18, :324:40] wire _next_flight_T_1 = inc[1]; // @[Edges.scala:315:18, :324:40] wire [1:0] _next_flight_T_2 = {1'h0, _next_flight_T} + {1'h0, _next_flight_T_1}; // @[Edges.scala:324:40] wire [1:0] _next_flight_T_3 = _next_flight_T_2; // @[Edges.scala:324:40] wire [2:0] _next_flight_T_4 = {1'h0, flight} + {1'h0, _next_flight_T_3}; // @[Edges.scala:295:25, :324:{30,40}] wire [1:0] _next_flight_T_5 = _next_flight_T_4[1:0]; // @[Edges.scala:324:30] wire _next_flight_T_6 = dec[0]; // @[Edges.scala:322:18, :324:56] wire _next_flight_T_7 = dec[1]; // @[Edges.scala:322:18, :324:56] wire [1:0] _next_flight_T_8 = {1'h0, _next_flight_T_6} + {1'h0, _next_flight_T_7}; // @[Edges.scala:324:56] wire [1:0] _next_flight_T_9 = _next_flight_T_8; // @[Edges.scala:324:56] wire [2:0] _next_flight_T_10 = {1'h0, _next_flight_T_5} - {1'h0, _next_flight_T_9}; // @[Edges.scala:324:{30,46,56}] wire [1:0] next_flight = _next_flight_T_10[1:0]; // @[Edges.scala:324:46] assign _io_pending_T = \|flight; // @[Edges.scala:295:25] assign io_pending = _io_pending_T; // @[BusBypass.scala:66:9, :84:27] wire _stall_T = bypass != io_bypass_0; // @[BusBypass.scala:66:9, :81:21, :86:25] wire stall_done = _stall_T_1; // @[Decoupled.scala:51:35] wire stall_beats1_opdata = ~_stall_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg stall_counter; // @[Edges.scala:229:27] wire _stall_last_T = stall_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _stall_counter1_T = {1'h0, stall_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire stall_counter1 = _stall_counter1_T[0]; // @[Edges.scala:230:28] wire stall_first = ~stall_counter; // @[Edges.scala:229:27, :231:25] wire _stall_count_T = ~stall_counter1; // @[Edges.scala:230:28, :234:27] wire _stall_counter_T = ~stall_first & stall_counter1; // @[Edges.scala:230:28, :231:25, :236:21] wire stall = _stall_T & stall_first; // @[Edges.scala:231:25] wire _nodeOut_a_valid_T = ~stall; // @[BusBypass.scala:86:40, :88:21] wire _nodeOut_a_valid_T_1 = _nodeOut_a_valid_T & nodeIn_a_valid; // @[BusBypass.scala:88:{21,28}] assign _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T_1 & bypass; // @[BusBypass.scala:81:21, :88:{28,42}] assign nodeOut_a_valid = _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42] wire _nodeOut_a_valid_T_3 = ~stall; // @[BusBypass.scala:86:40, :88:21, :89:21] wire _nodeOut_a_valid_T_4 = _nodeOut_a_valid_T_3 & nodeIn_a_valid; // @[BusBypass.scala:89:{21,28}] wire _nodeOut_a_valid_T_5 = ~bypass; // @[BusBypass.scala:81:21, :89:45] assign _nodeOut_a_valid_T_6 = _nodeOut_a_valid_T_4 & _nodeOut_a_valid_T_5; // @[BusBypass.scala:89:{28,42,45}] assign x1_nodeOut_a_valid = _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42] wire _nodeIn_a_ready_T = ~stall; // @[BusBypass.scala:86:40, :88:21, :90:21] wire _nodeIn_a_ready_T_1 = bypass ? nodeOut_a_ready : x1_nodeOut_a_ready; // @[BusBypass.scala:81:21, :90:34] assign _nodeIn_a_ready_T_2 = _nodeIn_a_ready_T & _nodeIn_a_ready_T_1; // @[BusBypass.scala:90:{21,28,34}] assign nodeIn_a_ready = _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28] assign nodeOut_a_bits_address = {119'h0, nodeIn_a_bits_address}; // @[BusBypass.scala:91:18] assign _nodeOut_d_ready_T = nodeIn_d_ready & bypass; // @[BusBypass.scala:81:21, :94:32] assign nodeOut_d_ready = _nodeOut_d_ready_T; // @[BusBypass.scala:94:32] wire _nodeOut_d_ready_T_1 = ~bypass; // @[BusBypass.scala:81:21, :89:45, :95:35] assign _nodeOut_d_ready_T_2 = nodeIn_d_ready & _nodeOut_d_ready_T_1; // @[BusBypass.scala:95:{32,35}] assign x1_nodeOut_d_ready = _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32] assign _nodeIn_d_valid_T = bypass ? nodeOut_d_valid : x1_nodeOut_d_valid; // @[BusBypass.scala:81:21, :96:24] assign nodeIn_d_valid = _nodeIn_d_valid_T; // @[BusBypass.scala:96:24] assign _nodeIn_d_bits_T_opcode = bypass ? nodeIn_d_bits_out_opcode : nodeIn_d_bits_out_1_opcode; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_param = bypass ? nodeIn_d_bits_out_param : nodeIn_d_bits_out_1_param; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_size = bypass ? nodeIn_d_bits_out_size : nodeIn_d_bits_out_1_size; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_source = ~bypass & nodeIn_d_bits_out_1_source; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_sink = ~bypass & nodeIn_d_bits_out_1_sink; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_denied = bypass ? nodeIn_d_bits_out_denied : nodeIn_d_bits_out_1_denied; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_data = bypass ? 32'h0 : nodeIn_d_bits_out_1_data; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_corrupt = bypass ? nodeIn_d_bits_out_corrupt : nodeIn_d_bits_out_1_corrupt; // @[BusBypass.scala:81:21, :97:53, :98:21] assign nodeIn_d_bits_opcode = _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_param = _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_size = _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_source = _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_sink = _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_denied = _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_data = _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_corrupt = _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21] always @(posedge clock) begin // @[BusBypass.scala:66:9] if (reset) begin // @[BusBypass.scala:66:9] in_reset <= 1'h1; // @[BusBypass.scala:79:27] flight <= 2'h0; // @[Edges.scala:295:25] r_counter <= 1'h0; // @[Edges.scala:229:27] r_counter_3 <= 1'h0; // @[Edges.scala:229:27] stall_counter <= 1'h0; // @[Edges.scala:229:27] end else begin // @[BusBypass.scala:66:9] in_reset <= 1'h0; // @[BusBypass.scala:79:27] flight <= next_flight; // @[Edges.scala:295:25, :324:46] if (_T) // @[Decoupled.scala:51:35] r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21] if (_T_3) // @[Decoupled.scala:51:35] r_counter_3 <= _r_counter_T_3; // @[Edges.scala:229:27, :236:21] if (_stall_T_1) // @[Decoupled.scala:51:35] stall_counter <= _stall_counter_T; // @[Edges.scala:229:27, :236:21] end if (in_reset \| next_flight == 2'h0) // @[Edges.scala:324:46] bypass_reg <= io_bypass_0; // @[BusBypass.scala:66:9, :80:25] always @(posedge) TLMonitor_59 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_in_a_ready = auto_in_a_ready_0; // @[BusBypass.scala:66:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_valid = auto_out_1_a_valid_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_opcode = auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_address = auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_data = auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9] assign auto_out_1_d_ready = auto_out_1_d_ready_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_valid = auto_out_0_a_valid_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_opcode = auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_address = auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_data = auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9] assign auto_out_0_d_ready = auto_out_0_d_ready_0; // @[BusBypass.scala:66:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Metadata.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.constants.MemoryOpConstants import freechips.rocketchip.util._ object ClientStates { val width = 2 def Nothing = 0.U(width.W) def Branch = 1.U(width.W) def Trunk = 2.U(width.W) def Dirty = 3.U(width.W) def hasReadPermission(state: UInt): Bool = state > Nothing def hasWritePermission(state: UInt): Bool = state > Branch } object MemoryOpCategories extends MemoryOpConstants { def wr = Cat(true.B, true.B) // Op actually writes def wi = Cat(false.B, true.B) // Future op will write def rd = Cat(false.B, false.B) // Op only reads def categorize(cmd: UInt): UInt = { val cat = Cat(isWrite(cmd), isWriteIntent(cmd)) //assert(cat.isOneOf(wr,wi,rd), "Could not categorize command.") cat } } /* Stores the client-side coherence information, * such as permissions on the data and whether the data is dirty. * Its API can be used to make TileLink messages in response to * memory operations, cache control oeprations, or Probe messages. / class ClientMetadata extends Bundle { /* Actual state information stored in this bundle / val state = UInt(ClientStates.width.W) /* Metadata equality / def ===(rhs: UInt): Bool = state === rhs def ===(rhs: ClientMetadata): Bool = state === rhs.state def =/=(rhs: ClientMetadata): Bool = !this.===(rhs) /* Is the block's data present in this cache / def isValid(dummy: Int = 0): Bool = state > ClientStates.Nothing /* Determine whether this cmd misses, and the new state (on hit) or param to be sent (on miss) / private def growStarter(cmd: UInt): (Bool, UInt) = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) MuxTLookup(Cat(c, state), (false.B, 0.U), Seq( //(effect, am now) -> (was a hit, next) Cat(rd, Dirty) -> (true.B, Dirty), Cat(rd, Trunk) -> (true.B, Trunk), Cat(rd, Branch) -> (true.B, Branch), Cat(wi, Dirty) -> (true.B, Dirty), Cat(wi, Trunk) -> (true.B, Trunk), Cat(wr, Dirty) -> (true.B, Dirty), Cat(wr, Trunk) -> (true.B, Dirty), //(effect, am now) -> (was a miss, param) Cat(rd, Nothing) -> (false.B, NtoB), Cat(wi, Branch) -> (false.B, BtoT), Cat(wi, Nothing) -> (false.B, NtoT), Cat(wr, Branch) -> (false.B, BtoT), Cat(wr, Nothing) -> (false.B, NtoT))) } /* Determine what state to go to after miss based on Grant param * For now, doesn't depend on state (which may have been Probed). / private def growFinisher(cmd: UInt, param: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) //assert(c === rd \|\| param === toT, "Client was expecting trunk permissions.") MuxLookup(Cat(c, param), Nothing)(Seq( //(effect param) -> (next) Cat(rd, toB) -> Branch, Cat(rd, toT) -> Trunk, Cat(wi, toT) -> Trunk, Cat(wr, toT) -> Dirty)) } /* Does this cache have permissions on this block sufficient to perform op, * and what to do next (Acquire message param or updated metadata). / def onAccess(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = growStarter(cmd) (r._1, r._2, ClientMetadata(r._2)) } /* Does a secondary miss on the block require another Acquire message / def onSecondaryAccess(first_cmd: UInt, second_cmd: UInt): (Bool, Bool, UInt, ClientMetadata, UInt) = { import MemoryOpCategories._ val r1 = growStarter(first_cmd) val r2 = growStarter(second_cmd) val needs_second_acq = isWriteIntent(second_cmd) && !isWriteIntent(first_cmd) val hit_again = r1._1 && r2._1 val dirties = categorize(second_cmd) === wr val biggest_grow_param = Mux(dirties, r2._2, r1._2) val dirtiest_state = ClientMetadata(biggest_grow_param) val dirtiest_cmd = Mux(dirties, second_cmd, first_cmd) (needs_second_acq, hit_again, biggest_grow_param, dirtiest_state, dirtiest_cmd) } /* Metadata change on a returned Grant / def onGrant(cmd: UInt, param: UInt): ClientMetadata = ClientMetadata(growFinisher(cmd, param)) /* Determine what state to go to based on Probe param / private def shrinkHelper(param: UInt): (Bool, UInt, UInt) = { import ClientStates._ import TLPermissions._ MuxTLookup(Cat(param, state), (false.B, 0.U, 0.U), Seq( //(wanted, am now) -> (hasDirtyData resp, next) Cat(toT, Dirty) -> (true.B, TtoT, Trunk), Cat(toT, Trunk) -> (false.B, TtoT, Trunk), Cat(toT, Branch) -> (false.B, BtoB, Branch), Cat(toT, Nothing) -> (false.B, NtoN, Nothing), Cat(toB, Dirty) -> (true.B, TtoB, Branch), Cat(toB, Trunk) -> (false.B, TtoB, Branch), // Policy: Don't notify on clean downgrade Cat(toB, Branch) -> (false.B, BtoB, Branch), Cat(toB, Nothing) -> (false.B, NtoN, Nothing), Cat(toN, Dirty) -> (true.B, TtoN, Nothing), Cat(toN, Trunk) -> (false.B, TtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Branch) -> (false.B, BtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Nothing) -> (false.B, NtoN, Nothing))) } /* Translate cache control cmds into Probe param / private def cmdToPermCap(cmd: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ MuxLookup(cmd, toN)(Seq( M_FLUSH -> toN, M_PRODUCE -> toB, M_CLEAN -> toT)) } def onCacheControl(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(cmdToPermCap(cmd)) (r._1, r._2, ClientMetadata(r._3)) } def onProbe(param: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(param) (r._1, r._2, ClientMetadata(r._3)) } } /* Factories for ClientMetadata, including on reset / object ClientMetadata { def apply(perm: UInt) = { val meta = Wire(new ClientMetadata) meta.state := perm meta } def onReset = ClientMetadata(ClientStates.Nothing) def maximum = ClientMetadata(ClientStates.Dirty) } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) \|\| isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR \|\| cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) \|\| isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR \|\| cmd === M_PWR \|\| cmd === M_XSC \|\| isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) \|\| cmd === M_PFW \|\| cmd === M_XLR } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File mshrs.scala: //***************************************************************************** // Ported from Rocket-Chip // See LICENSE.Berkeley and LICENSE.SiFive in Rocket-Chip for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.lsu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.rocket._ import boom.v3.common._ import boom.v3.exu.BrUpdateInfo import boom.v3.util.{IsKilledByBranch, GetNewBrMask, BranchKillableQueue, IsOlder, UpdateBrMask, AgePriorityEncoder, WrapInc} class BoomDCacheReqInternal(implicit p: Parameters) extends BoomDCacheReq()(p) with HasL1HellaCacheParameters { // miss info val tag_match = Bool() val old_meta = new L1Metadata val way_en = UInt(nWays.W) // Used in the MSHRs val sdq_id = UInt(log2Ceil(cfg.nSDQ).W) } class BoomMSHR(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p) with HasL1HellaCacheParameters { val io = IO(new Bundle { val id = Input(UInt()) val req_pri_val = Input(Bool()) val req_pri_rdy = Output(Bool()) val req_sec_val = Input(Bool()) val req_sec_rdy = Output(Bool()) val clear_prefetch = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val exception = Input(Bool()) val rob_pnr_idx = Input(UInt(robAddrSz.W)) val rob_head_idx = Input(UInt(robAddrSz.W)) val req = Input(new BoomDCacheReqInternal) val req_is_probe = Input(Bool()) val idx = Output(Valid(UInt())) val way = Output(Valid(UInt())) val tag = Output(Valid(UInt())) val mem_acquire = Decoupled(new TLBundleA(edge.bundle)) val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle))) val mem_finish = Decoupled(new TLBundleE(edge.bundle)) val prober_state = Input(Valid(UInt(coreMaxAddrBits.W))) val refill = Decoupled(new L1DataWriteReq) val meta_write = Decoupled(new L1MetaWriteReq) val meta_read = Decoupled(new L1MetaReadReq) val meta_resp = Input(Valid(new L1Metadata)) val wb_req = Decoupled(new WritebackReq(edge.bundle)) // To inform the prefetcher when we are commiting the fetch of this line val commit_val = Output(Bool()) val commit_addr = Output(UInt(coreMaxAddrBits.W)) val commit_coh = Output(new ClientMetadata) // Reading from the line buffer val lb_read = Decoupled(new LineBufferReadReq) val lb_resp = Input(UInt(encRowBits.W)) val lb_write = Decoupled(new LineBufferWriteReq) // Replays go through the cache pipeline again val replay = Decoupled(new BoomDCacheReqInternal) // Resp go straight out to the core val resp = Decoupled(new BoomDCacheResp) // Writeback unit tells us when it is done processing our wb val wb_resp = Input(Bool()) val probe_rdy = Output(Bool()) }) // TODO: Optimize this. We don't want to mess with cache during speculation // s_refill_req : Make a request for a new cache line // s_refill_resp : Store the refill response into our buffer // s_drain_rpq_loads : Drain out loads from the rpq // : If miss was misspeculated, go to s_invalid // s_wb_req : Write back the evicted cache line // s_wb_resp : Finish writing back the evicted cache line // s_meta_write_req : Write the metadata for new cache lne // s_meta_write_resp : val s_invalid :: s_refill_req :: s_refill_resp :: s_drain_rpq_loads :: s_meta_read :: s_meta_resp_1 :: s_meta_resp_2 :: s_meta_clear :: s_wb_meta_read :: s_wb_req :: s_wb_resp :: s_commit_line :: s_drain_rpq :: s_meta_write_req :: s_mem_finish_1 :: s_mem_finish_2 :: s_prefetched :: s_prefetch :: Nil = Enum(18) val state = RegInit(s_invalid) val req = Reg(new BoomDCacheReqInternal) val req_idx = req.addr(untagBits-1, blockOffBits) val req_tag = req.addr >> untagBits val req_block_addr = (req.addr >> blockOffBits) << blockOffBits val req_needs_wb = RegInit(false.B) val new_coh = RegInit(ClientMetadata.onReset) val (_, shrink_param, coh_on_clear) = req.old_meta.coh.onCacheControl(M_FLUSH) val grow_param = new_coh.onAccess(req.uop.mem_cmd)._2 val coh_on_grant = new_coh.onGrant(req.uop.mem_cmd, io.mem_grant.bits.param) // We only accept secondary misses if the original request had sufficient permissions val (cmd_requires_second_acquire, is_hit_again, _, dirtier_coh, dirtier_cmd) = new_coh.onSecondaryAccess(req.uop.mem_cmd, io.req.uop.mem_cmd) val (_, _, refill_done, refill_address_inc) = edge.addr_inc(io.mem_grant) val sec_rdy = (!cmd_requires_second_acquire && !io.req_is_probe && !state.isOneOf(s_invalid, s_meta_write_req, s_mem_finish_1, s_mem_finish_2))// Always accept secondary misses val rpq = Module(new BranchKillableQueue(new BoomDCacheReqInternal, cfg.nRPQ, u => u.uses_ldq, false)) rpq.io.brupdate := io.brupdate rpq.io.flush := io.exception assert(!(state === s_invalid && !rpq.io.empty)) rpq.io.enq.valid := ((io.req_pri_val && io.req_pri_rdy) \|\| (io.req_sec_val && io.req_sec_rdy)) && !isPrefetch(io.req.uop.mem_cmd) rpq.io.enq.bits := io.req rpq.io.deq.ready := false.B val grantack = Reg(Valid(new TLBundleE(edge.bundle))) val refill_ctr = Reg(UInt(log2Ceil(cacheDataBeats).W)) val commit_line = Reg(Bool()) val grant_had_data = Reg(Bool()) val finish_to_prefetch = Reg(Bool()) // Block probes if a tag write we started is still in the pipeline val meta_hazard = RegInit(0.U(2.W)) when (meta_hazard =/= 0.U) { meta_hazard := meta_hazard + 1.U } when (io.meta_write.fire) { meta_hazard := 1.U } io.probe_rdy := (meta_hazard === 0.U && (state.isOneOf(s_invalid, s_refill_req, s_refill_resp, s_drain_rpq_loads) \|\| (state === s_meta_read && grantack.valid))) io.idx.valid := state =/= s_invalid io.tag.valid := state =/= s_invalid io.way.valid := !state.isOneOf(s_invalid, s_prefetch) io.idx.bits := req_idx io.tag.bits := req_tag io.way.bits := req.way_en io.meta_write.valid := false.B io.meta_write.bits := DontCare io.req_pri_rdy := false.B io.req_sec_rdy := sec_rdy && rpq.io.enq.ready io.mem_acquire.valid := false.B io.mem_acquire.bits := DontCare io.refill.valid := false.B io.refill.bits := DontCare io.replay.valid := false.B io.replay.bits := DontCare io.wb_req.valid := false.B io.wb_req.bits := DontCare io.resp.valid := false.B io.resp.bits := DontCare io.commit_val := false.B io.commit_addr := req.addr io.commit_coh := coh_on_grant io.meta_read.valid := false.B io.meta_read.bits := DontCare io.mem_finish.valid := false.B io.mem_finish.bits := DontCare io.lb_write.valid := false.B io.lb_write.bits := DontCare io.lb_read.valid := false.B io.lb_read.bits := DontCare io.mem_grant.ready := false.B when (io.req_sec_val && io.req_sec_rdy) { req.uop.mem_cmd := dirtier_cmd when (is_hit_again) { new_coh := dirtier_coh } } def handle_pri_req(old_state: UInt): UInt = { val new_state = WireInit(old_state) grantack.valid := false.B refill_ctr := 0.U assert(rpq.io.enq.ready) req := io.req val old_coh = io.req.old_meta.coh req_needs_wb := old_coh.onCacheControl(M_FLUSH)._1 // does the line we are evicting need to be written back when (io.req.tag_match) { val (is_hit, _, coh_on_hit) = old_coh.onAccess(io.req.uop.mem_cmd) when (is_hit) { // set dirty bit assert(isWrite(io.req.uop.mem_cmd)) new_coh := coh_on_hit new_state := s_drain_rpq } .otherwise { // upgrade permissions new_coh := old_coh new_state := s_refill_req } } .otherwise { // refill and writeback if necessary new_coh := ClientMetadata.onReset new_state := s_refill_req } new_state } when (state === s_invalid) { io.req_pri_rdy := true.B grant_had_data := false.B when (io.req_pri_val && io.req_pri_rdy) { state := handle_pri_req(state) } } .elsewhen (state === s_refill_req) { io.mem_acquire.valid := true.B // TODO: Use AcquirePerm if just doing permissions acquire io.mem_acquire.bits := edge.AcquireBlock( fromSource = io.id, toAddress = Cat(req_tag, req_idx) << blockOffBits, lgSize = lgCacheBlockBytes.U, growPermissions = grow_param)._2 when (io.mem_acquire.fire) { state := s_refill_resp } } .elsewhen (state === s_refill_resp) { when (edge.hasData(io.mem_grant.bits)) { io.mem_grant.ready := io.lb_write.ready io.lb_write.valid := io.mem_grant.valid io.lb_write.bits.id := io.id io.lb_write.bits.offset := refill_address_inc >> rowOffBits io.lb_write.bits.data := io.mem_grant.bits.data } .otherwise { io.mem_grant.ready := true.B } when (io.mem_grant.fire) { grant_had_data := edge.hasData(io.mem_grant.bits) } when (refill_done) { grantack.valid := edge.isRequest(io.mem_grant.bits) grantack.bits := edge.GrantAck(io.mem_grant.bits) state := Mux(grant_had_data, s_drain_rpq_loads, s_drain_rpq) assert(!(!grant_had_data && req_needs_wb)) commit_line := false.B new_coh := coh_on_grant } } .elsewhen (state === s_drain_rpq_loads) { val drain_load = (isRead(rpq.io.deq.bits.uop.mem_cmd) && !isWrite(rpq.io.deq.bits.uop.mem_cmd) && (rpq.io.deq.bits.uop.mem_cmd =/= M_XLR)) // LR should go through replay // drain all loads for now val rp_addr = Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)) val word_idx = if (rowWords == 1) 0.U else rp_addr(log2Up(rowWordscoreDataBytes)-1, log2Up(wordBytes)) val data = io.lb_resp val data_word = data >> Cat(word_idx, 0.U(log2Up(coreDataBits).W)) val loadgen = new LoadGen(rpq.io.deq.bits.uop.mem_size, rpq.io.deq.bits.uop.mem_signed, Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)), data_word, false.B, wordBytes) rpq.io.deq.ready := io.resp.ready && io.lb_read.ready && drain_load io.lb_read.valid := rpq.io.deq.valid && drain_load io.lb_read.bits.id := io.id io.lb_read.bits.offset := rpq.io.deq.bits.addr >> rowOffBits io.resp.valid := rpq.io.deq.valid && io.lb_read.fire && drain_load io.resp.bits.uop := rpq.io.deq.bits.uop io.resp.bits.data := loadgen.data io.resp.bits.is_hella := rpq.io.deq.bits.is_hella when (rpq.io.deq.fire) { commit_line := true.B } .elsewhen (rpq.io.empty && !commit_line) { when (!rpq.io.enq.fire) { state := s_mem_finish_1 finish_to_prefetch := enablePrefetching.B } } .elsewhen (rpq.io.empty \|\| (rpq.io.deq.valid && !drain_load)) { // io.commit_val is for the prefetcher. it tells the prefetcher that this line was correctly acquired // The prefetcher should consider fetching the next line io.commit_val := true.B state := s_meta_read } } .elsewhen (state === s_meta_read) { io.meta_read.valid := !io.prober_state.valid \|\| !grantack.valid \|\| (io.prober_state.bits(untagBits-1,blockOffBits) =/= req_idx) io.meta_read.bits.idx := req_idx io.meta_read.bits.tag := req_tag io.meta_read.bits.way_en := req.way_en when (io.meta_read.fire) { state := s_meta_resp_1 } } .elsewhen (state === s_meta_resp_1) { state := s_meta_resp_2 } .elsewhen (state === s_meta_resp_2) { val needs_wb = io.meta_resp.bits.coh.onCacheControl(M_FLUSH)._1 state := Mux(!io.meta_resp.valid, s_meta_read, // Prober could have nack'd this read Mux(needs_wb, s_meta_clear, s_commit_line)) } .elsewhen (state === s_meta_clear) { io.meta_write.valid := true.B io.meta_write.bits.idx := req_idx io.meta_write.bits.data.coh := coh_on_clear io.meta_write.bits.data.tag := req_tag io.meta_write.bits.way_en := req.way_en when (io.meta_write.fire) { state := s_wb_req } } .elsewhen (state === s_wb_req) { io.wb_req.valid := true.B io.wb_req.bits.tag := req.old_meta.tag io.wb_req.bits.idx := req_idx io.wb_req.bits.param := shrink_param io.wb_req.bits.way_en := req.way_en io.wb_req.bits.source := io.id io.wb_req.bits.voluntary := true.B when (io.wb_req.fire) { state := s_wb_resp } } .elsewhen (state === s_wb_resp) { when (io.wb_resp) { state := s_commit_line } } .elsewhen (state === s_commit_line) { io.lb_read.valid := true.B io.lb_read.bits.id := io.id io.lb_read.bits.offset := refill_ctr io.refill.valid := io.lb_read.fire io.refill.bits.addr := req_block_addr \| (refill_ctr << rowOffBits) io.refill.bits.way_en := req.way_en io.refill.bits.wmask := ~(0.U(rowWords.W)) io.refill.bits.data := io.lb_resp when (io.refill.fire) { refill_ctr := refill_ctr + 1.U when (refill_ctr === (cacheDataBeats - 1).U) { state := s_drain_rpq } } } .elsewhen (state === s_drain_rpq) { io.replay <> rpq.io.deq io.replay.bits.way_en := req.way_en io.replay.bits.addr := Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)) when (io.replay.fire && isWrite(rpq.io.deq.bits.uop.mem_cmd)) { // Set dirty bit val (is_hit, _, coh_on_hit) = new_coh.onAccess(rpq.io.deq.bits.uop.mem_cmd) assert(is_hit, "We still don't have permissions for this store") new_coh := coh_on_hit } when (rpq.io.empty && !rpq.io.enq.valid) { state := s_meta_write_req } } .elsewhen (state === s_meta_write_req) { io.meta_write.valid := true.B io.meta_write.bits.idx := req_idx io.meta_write.bits.data.coh := new_coh io.meta_write.bits.data.tag := req_tag io.meta_write.bits.way_en := req.way_en when (io.meta_write.fire) { state := s_mem_finish_1 finish_to_prefetch := false.B } } .elsewhen (state === s_mem_finish_1) { io.mem_finish.valid := grantack.valid io.mem_finish.bits := grantack.bits when (io.mem_finish.fire \|\| !grantack.valid) { grantack.valid := false.B state := s_mem_finish_2 } } .elsewhen (state === s_mem_finish_2) { state := Mux(finish_to_prefetch, s_prefetch, s_invalid) } .elsewhen (state === s_prefetch) { io.req_pri_rdy := true.B when ((io.req_sec_val && !io.req_sec_rdy) \|\| io.clear_prefetch) { state := s_invalid } .elsewhen (io.req_sec_val && io.req_sec_rdy) { val (is_hit, _, coh_on_hit) = new_coh.onAccess(io.req.uop.mem_cmd) when (is_hit) { // Proceed with refill new_coh := coh_on_hit state := s_meta_read } .otherwise { // Reacquire this line new_coh := ClientMetadata.onReset state := s_refill_req } } .elsewhen (io.req_pri_val && io.req_pri_rdy) { grant_had_data := false.B state := handle_pri_req(state) } } } class BoomIOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p) with HasL1HellaCacheParameters { val io = IO(new Bundle { val req = Flipped(Decoupled(new BoomDCacheReq)) val resp = Decoupled(new BoomDCacheResp) val mem_access = Decoupled(new TLBundleA(edge.bundle)) val mem_ack = Flipped(Valid(new TLBundleD(edge.bundle))) // We don't need brupdate in here because uncacheable operations are guaranteed non-speculative }) def beatOffset(addr: UInt) = addr.extract(beatOffBits-1, wordOffBits) def wordFromBeat(addr: UInt, dat: UInt) = { val shift = Cat(beatOffset(addr), 0.U((wordOffBits+log2Ceil(wordBytes)).W)) (dat >> shift)(wordBits-1, 0) } val req = Reg(new BoomDCacheReq) val grant_word = Reg(UInt(wordBits.W)) val s_idle :: s_mem_access :: s_mem_ack :: s_resp :: Nil = Enum(4) val state = RegInit(s_idle) io.req.ready := state === s_idle val loadgen = new LoadGen(req.uop.mem_size, req.uop.mem_signed, req.addr, grant_word, false.B, wordBytes) val a_source = id.U val a_address = req.addr val a_size = req.uop.mem_size val a_data = Fill(beatWords, req.data) val get = edge.Get(a_source, a_address, a_size)._2 val put = edge.Put(a_source, a_address, a_size, a_data)._2 val atomics = if (edge.manager.anySupportLogical) { MuxLookup(req.uop.mem_cmd, (0.U).asTypeOf(new TLBundleA(edge.bundle)))(Array( M_XA_SWAP -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.SWAP)._2, M_XA_XOR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.XOR) ._2, M_XA_OR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.OR) ._2, M_XA_AND -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.AND) ._2, M_XA_ADD -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.ADD)._2, M_XA_MIN -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MIN)._2, M_XA_MAX -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAX)._2, M_XA_MINU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MINU)._2, M_XA_MAXU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAXU)._2)) } else { // If no managers support atomics, assert fail if processor asks for them assert(state === s_idle \|\| !isAMO(req.uop.mem_cmd)) (0.U).asTypeOf(new TLBundleA(edge.bundle)) } assert(state === s_idle \|\| req.uop.mem_cmd =/= M_XSC) io.mem_access.valid := state === s_mem_access io.mem_access.bits := Mux(isAMO(req.uop.mem_cmd), atomics, Mux(isRead(req.uop.mem_cmd), get, put)) val send_resp = isRead(req.uop.mem_cmd) io.resp.valid := (state === s_resp) && send_resp io.resp.bits.is_hella := req.is_hella io.resp.bits.uop := req.uop io.resp.bits.data := loadgen.data when (io.req.fire) { req := io.req.bits state := s_mem_access } when (io.mem_access.fire) { state := s_mem_ack } when (state === s_mem_ack && io.mem_ack.valid) { state := s_resp when (isRead(req.uop.mem_cmd)) { grant_word := wordFromBeat(req.addr, io.mem_ack.bits.data) } } when (state === s_resp) { when (!send_resp \|\| io.resp.fire) { state := s_idle } } } class LineBufferReadReq(implicit p: Parameters) extends BoomBundle()(p) with HasL1HellaCacheParameters { val id = UInt(log2Ceil(nLBEntries).W) val offset = UInt(log2Ceil(cacheDataBeats).W) def lb_addr = Cat(id, offset) } class LineBufferWriteReq(implicit p: Parameters) extends LineBufferReadReq()(p) { val data = UInt(encRowBits.W) } class LineBufferMetaWriteReq(implicit p: Parameters) extends BoomBundle()(p) { val id = UInt(log2Ceil(nLBEntries).W) val coh = new ClientMetadata val addr = UInt(coreMaxAddrBits.W) } class LineBufferMeta(implicit p: Parameters) extends BoomBundle()(p) with HasL1HellaCacheParameters { val coh = new ClientMetadata val addr = UInt(coreMaxAddrBits.W) } class BoomMSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p) with HasL1HellaCacheParameters { val io = IO(new Bundle { val req = Flipped(Vec(memWidth, Decoupled(new BoomDCacheReqInternal))) // Req from s2 of DCache pipe val req_is_probe = Input(Vec(memWidth, Bool())) val resp = Decoupled(new BoomDCacheResp) val secondary_miss = Output(Vec(memWidth, Bool())) val block_hit = Output(Vec(memWidth, Bool())) val brupdate = Input(new BrUpdateInfo) val exception = Input(Bool()) val rob_pnr_idx = Input(UInt(robAddrSz.W)) val rob_head_idx = Input(UInt(robAddrSz.W)) val mem_acquire = Decoupled(new TLBundleA(edge.bundle)) val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle))) val mem_finish = Decoupled(new TLBundleE(edge.bundle)) val refill = Decoupled(new L1DataWriteReq) val meta_write = Decoupled(new L1MetaWriteReq) val meta_read = Decoupled(new L1MetaReadReq) val meta_resp = Input(Valid(new L1Metadata)) val replay = Decoupled(new BoomDCacheReqInternal) val prefetch = Decoupled(new BoomDCacheReq) val wb_req = Decoupled(new WritebackReq(edge.bundle)) val prober_state = Input(Valid(UInt(coreMaxAddrBits.W))) val clear_all = Input(Bool()) // Clears all uncommitted MSHRs to prepare for fence val wb_resp = Input(Bool()) val fence_rdy = Output(Bool()) val probe_rdy = Output(Bool()) }) val req_idx = OHToUInt(io.req.map(_.valid)) val req = io.req(req_idx) val req_is_probe = io.req_is_probe(0) for (w <- 0 until memWidth) io.req(w).ready := false.B val prefetcher: DataPrefetcher = if (enablePrefetching) Module(new NLPrefetcher) else Module(new NullPrefetcher) io.prefetch <> prefetcher.io.prefetch val cacheable = edge.manager.supportsAcquireBFast(req.bits.addr, lgCacheBlockBytes.U) // -------------------- // The MSHR SDQ val sdq_val = RegInit(0.U(cfg.nSDQ.W)) val sdq_alloc_id = PriorityEncoder(~sdq_val(cfg.nSDQ-1,0)) val sdq_rdy = !sdq_val.andR val sdq_enq = req.fire && cacheable && isWrite(req.bits.uop.mem_cmd) val sdq = Mem(cfg.nSDQ, UInt(coreDataBits.W)) when (sdq_enq) { sdq(sdq_alloc_id) := req.bits.data } // -------------------- // The LineBuffer Data // Holds refilling lines, prefetched lines val lb = Mem(nLBEntries cacheDataBeats, UInt(encRowBits.W)) val lb_read_arb = Module(new Arbiter(new LineBufferReadReq, cfg.nMSHRs)) val lb_write_arb = Module(new Arbiter(new LineBufferWriteReq, cfg.nMSHRs)) lb_read_arb.io.out.ready := false.B lb_write_arb.io.out.ready := true.B val lb_read_data = WireInit(0.U(encRowBits.W)) when (lb_write_arb.io.out.fire) { lb.write(lb_write_arb.io.out.bits.lb_addr, lb_write_arb.io.out.bits.data) } .otherwise { lb_read_arb.io.out.ready := true.B when (lb_read_arb.io.out.fire) { lb_read_data := lb.read(lb_read_arb.io.out.bits.lb_addr) } } def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f)) val idx_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool()))) val tag_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool()))) val way_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool()))) val tag_match = widthMap(w => Mux1H(idx_matches(w), tag_matches(w))) val idx_match = widthMap(w => idx_matches(w).reduce(_\|\|_)) val way_match = widthMap(w => Mux1H(idx_matches(w), way_matches(w))) val wb_tag_list = Wire(Vec(cfg.nMSHRs, UInt(tagBits.W))) val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq , cfg.nMSHRs)) val meta_read_arb = Module(new Arbiter(new L1MetaReadReq , cfg.nMSHRs)) val wb_req_arb = Module(new Arbiter(new WritebackReq(edge.bundle), cfg.nMSHRs)) val replay_arb = Module(new Arbiter(new BoomDCacheReqInternal , cfg.nMSHRs)) val resp_arb = Module(new Arbiter(new BoomDCacheResp , cfg.nMSHRs + nIOMSHRs)) val refill_arb = Module(new Arbiter(new L1DataWriteReq , cfg.nMSHRs)) val commit_vals = Wire(Vec(cfg.nMSHRs, Bool())) val commit_addrs = Wire(Vec(cfg.nMSHRs, UInt(coreMaxAddrBits.W))) val commit_cohs = Wire(Vec(cfg.nMSHRs, new ClientMetadata)) var sec_rdy = false.B io.fence_rdy := true.B io.probe_rdy := true.B io.mem_grant.ready := false.B val mshr_alloc_idx = Wire(UInt()) val pri_rdy = WireInit(false.B) val pri_val = req.valid && sdq_rdy && cacheable && !idx_match(req_idx) val mshrs = (0 until cfg.nMSHRs) map { i => val mshr = Module(new BoomMSHR) mshr.io.id := i.U(log2Ceil(cfg.nMSHRs).W) for (w <- 0 until memWidth) { idx_matches(w)(i) := mshr.io.idx.valid && mshr.io.idx.bits === io.req(w).bits.addr(untagBits-1,blockOffBits) tag_matches(w)(i) := mshr.io.tag.valid && mshr.io.tag.bits === io.req(w).bits.addr >> untagBits way_matches(w)(i) := mshr.io.way.valid && mshr.io.way.bits === io.req(w).bits.way_en } wb_tag_list(i) := mshr.io.wb_req.bits.tag mshr.io.req_pri_val := (i.U === mshr_alloc_idx) && pri_val when (i.U === mshr_alloc_idx) { pri_rdy := mshr.io.req_pri_rdy } mshr.io.req_sec_val := req.valid && sdq_rdy && tag_match(req_idx) && idx_matches(req_idx)(i) && cacheable mshr.io.req := req.bits mshr.io.req_is_probe := req_is_probe mshr.io.req.sdq_id := sdq_alloc_id // Clear because of a FENCE, a request to the same idx as a prefetched line, // a probe to that prefetched line, all mshrs are in use mshr.io.clear_prefetch := ((io.clear_all && !req.valid)\|\| (req.valid && idx_matches(req_idx)(i) && cacheable && !tag_match(req_idx)) \|\| (req_is_probe && idx_matches(req_idx)(i))) mshr.io.brupdate := io.brupdate mshr.io.exception := io.exception mshr.io.rob_pnr_idx := io.rob_pnr_idx mshr.io.rob_head_idx := io.rob_head_idx mshr.io.prober_state := io.prober_state mshr.io.wb_resp := io.wb_resp meta_write_arb.io.in(i) <> mshr.io.meta_write meta_read_arb.io.in(i) <> mshr.io.meta_read mshr.io.meta_resp := io.meta_resp wb_req_arb.io.in(i) <> mshr.io.wb_req replay_arb.io.in(i) <> mshr.io.replay refill_arb.io.in(i) <> mshr.io.refill lb_read_arb.io.in(i) <> mshr.io.lb_read mshr.io.lb_resp := lb_read_data lb_write_arb.io.in(i) <> mshr.io.lb_write commit_vals(i) := mshr.io.commit_val commit_addrs(i) := mshr.io.commit_addr commit_cohs(i) := mshr.io.commit_coh mshr.io.mem_grant.valid := false.B mshr.io.mem_grant.bits := DontCare when (io.mem_grant.bits.source === i.U) { mshr.io.mem_grant <> io.mem_grant } sec_rdy = sec_rdy \|\| (mshr.io.req_sec_rdy && mshr.io.req_sec_val) resp_arb.io.in(i) <> mshr.io.resp when (!mshr.io.req_pri_rdy) { io.fence_rdy := false.B } for (w <- 0 until memWidth) { when (!mshr.io.probe_rdy && idx_matches(w)(i) && io.req_is_probe(w)) { io.probe_rdy := false.B } } mshr } // Try to round-robin the MSHRs val mshr_head = RegInit(0.U(log2Ceil(cfg.nMSHRs).W)) mshr_alloc_idx := RegNext(AgePriorityEncoder(mshrs.map(m=>m.io.req_pri_rdy), mshr_head)) when (pri_rdy && pri_val) { mshr_head := WrapInc(mshr_head, cfg.nMSHRs) } io.meta_write <> meta_write_arb.io.out io.meta_read <> meta_read_arb.io.out io.wb_req <> wb_req_arb.io.out val mmio_alloc_arb = Module(new Arbiter(Bool(), nIOMSHRs)) var mmio_rdy = false.B val mmios = (0 until nIOMSHRs) map { i => val id = cfg.nMSHRs + 1 + i // +1 for wb unit val mshr = Module(new BoomIOMSHR(id)) mmio_alloc_arb.io.in(i).valid := mshr.io.req.ready mmio_alloc_arb.io.in(i).bits := DontCare mshr.io.req.valid := mmio_alloc_arb.io.in(i).ready mshr.io.req.bits := req.bits mmio_rdy = mmio_rdy \|\| mshr.io.req.ready mshr.io.mem_ack.bits := io.mem_grant.bits mshr.io.mem_ack.valid := io.mem_grant.valid && io.mem_grant.bits.source === id.U when (io.mem_grant.bits.source === id.U) { io.mem_grant.ready := true.B } resp_arb.io.in(cfg.nMSHRs + i) <> mshr.io.resp when (!mshr.io.req.ready) { io.fence_rdy := false.B } mshr } mmio_alloc_arb.io.out.ready := req.valid && !cacheable TLArbiter.lowestFromSeq(edge, io.mem_acquire, mshrs.map(_.io.mem_acquire) ++ mmios.map(_.io.mem_access)) TLArbiter.lowestFromSeq(edge, io.mem_finish, mshrs.map(_.io.mem_finish)) val respq = Module(new BranchKillableQueue(new BoomDCacheResp, 4, u => u.uses_ldq, flow = false)) respq.io.brupdate := io.brupdate respq.io.flush := io.exception respq.io.enq <> resp_arb.io.out io.resp <> respq.io.deq for (w <- 0 until memWidth) { io.req(w).ready := (w.U === req_idx) && Mux(!cacheable, mmio_rdy, sdq_rdy && Mux(idx_match(w), tag_match(w) && sec_rdy, pri_rdy)) io.secondary_miss(w) := idx_match(w) && way_match(w) && !tag_match(w) io.block_hit(w) := idx_match(w) && tag_match(w) } io.refill <> refill_arb.io.out val free_sdq = io.replay.fire && isWrite(io.replay.bits.uop.mem_cmd) io.replay <> replay_arb.io.out io.replay.bits.data := sdq(replay_arb.io.out.bits.sdq_id) when (io.replay.valid \|\| sdq_enq) { sdq_val := sdq_val & ~(UIntToOH(replay_arb.io.out.bits.sdq_id) & Fill(cfg.nSDQ, free_sdq)) \| PriorityEncoderOH(~sdq_val(cfg.nSDQ-1,0)) & Fill(cfg.nSDQ, sdq_enq) } prefetcher.io.mshr_avail := RegNext(pri_rdy) prefetcher.io.req_val := RegNext(commit_vals.reduce(_\|\|_)) prefetcher.io.req_addr := RegNext(Mux1H(commit_vals, commit_addrs)) prefetcher.io.req_coh := RegNext(Mux1H(commit_vals, commit_cohs)) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File AMOALU.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) { val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W)) size := typ val dat_padded = dat.pad(maxSize8) def misaligned: Bool = (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR def mask = { var res = 1.U for (i <- 0 until log2Up(maxSize)) { val upper = Mux(addr(i), res, 0.U) \| Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U) val lower = Mux(addr(i), 0.U, res) res = Cat(upper, lower) } res } protected def genData(i: Int): UInt = if (i >= log2Up(maxSize)) dat_padded else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1)) def data = genData(0) def wordData = genData(2) } class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { private val size = new StoreGen(typ, addr, dat, maxSize).size private def genData(logMinSize: Int): UInt = { var res = dat for (i <- log2Up(maxSize)-1 to logMinSize by -1) { val pos = 8 << i val shifted = Mux(addr(i), res(2pos-1,pos), res(pos-1,0)) val doZero = (i == 0).B && zero val zeroed = Mux(doZero, 0.U, shifted) res = Cat(Mux(size === i.U \|\| doZero, Fill(8maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed) } res } def wordData = genData(2) def data = genData(0) } class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module { val minXLen = 32 val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _) val io = IO(new Bundle { val mask = Input(UInt((operandBits / 8).W)) val cmd = Input(UInt(M_SZ.W)) val lhs = Input(UInt(operandBits.W)) val rhs = Input(UInt(operandBits.W)) val out = Output(UInt(operandBits.W)) val out_unmasked = Output(UInt(operandBits.W)) }) val max = io.cmd === M_XA_MAX \|\| io.cmd === M_XA_MAXU val min = io.cmd === M_XA_MIN \|\| io.cmd === M_XA_MINU val add = io.cmd === M_XA_ADD val logic_and = io.cmd === M_XA_OR \|\| io.cmd === M_XA_AND val logic_xor = io.cmd === M_XA_XOR \|\| io.cmd === M_XA_OR val adder_out = { // partition the carry chain to support sub-xLen addition val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_\|_) (io.lhs & mask) + (io.rhs & mask) } val less = { // break up the comparator so the lower parts will be CSE'd def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = { if (n == minXLen) x(n-1, 0) < y(n-1, 0) else x(n-1, n/2) < y(n-1, n/2) \|\| x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2) } def isLess(x: UInt, y: UInt, n: Int): Bool = { val signed = { val mask = M_XA_MIN ^ M_XA_MINU (io.cmd & mask) === (M_XA_MIN & mask) } Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1))) } PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w)))) } val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs) val logic = Mux(logic_and, io.lhs & io.rhs, 0.U) \| Mux(logic_xor, io.lhs ^ io.rhs, 0.U) val out = Mux(add, adder_out, Mux(logic_and \|\| logic_xor, logic, minmax)) val wmask = FillInterleaved(8, io.mask) io.out := wmask & out \| ~wmask & io.lhs io.out_unmasked := out }	module BoomMSHR_9( // @[mshrs.scala:36:7] input clock, // @[mshrs.scala:36:7] input reset, // @[mshrs.scala:36:7] input io_req_pri_val, // @[mshrs.scala:39:14] output io_req_pri_rdy, // @[mshrs.scala:39:14] input io_req_sec_val, // @[mshrs.scala:39:14] output io_req_sec_rdy, // @[mshrs.scala:39:14] input io_clear_prefetch, // @[mshrs.scala:39:14] input [5:0] io_rob_pnr_idx, // @[mshrs.scala:39:14] input [5:0] io_rob_head_idx, // @[mshrs.scala:39:14] input [6:0] io_req_uop_uopc, // @[mshrs.scala:39:14] input [31:0] io_req_uop_inst, // @[mshrs.scala:39:14] input [31:0] io_req_uop_debug_inst, // @[mshrs.scala:39:14] input io_req_uop_is_rvc, // @[mshrs.scala:39:14] input [33:0] io_req_uop_debug_pc, // @[mshrs.scala:39:14] input [2:0] io_req_uop_iq_type, // @[mshrs.scala:39:14] input [9:0] io_req_uop_fu_code, // @[mshrs.scala:39:14] input [3:0] io_req_uop_ctrl_br_type, // @[mshrs.scala:39:14] input [1:0] io_req_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] input [2:0] io_req_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] input [2:0] io_req_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] input [4:0] io_req_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] input io_req_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] input [2:0] io_req_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] input io_req_uop_ctrl_is_load, // @[mshrs.scala:39:14] input io_req_uop_ctrl_is_sta, // @[mshrs.scala:39:14] input io_req_uop_ctrl_is_std, // @[mshrs.scala:39:14] input [1:0] io_req_uop_iw_state, // @[mshrs.scala:39:14] input io_req_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] input io_req_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] input io_req_uop_is_br, // @[mshrs.scala:39:14] input io_req_uop_is_jalr, // @[mshrs.scala:39:14] input io_req_uop_is_jal, // @[mshrs.scala:39:14] input io_req_uop_is_sfb, // @[mshrs.scala:39:14] input [3:0] io_req_uop_br_mask, // @[mshrs.scala:39:14] input [1:0] io_req_uop_br_tag, // @[mshrs.scala:39:14] input [3:0] io_req_uop_ftq_idx, // @[mshrs.scala:39:14] input io_req_uop_edge_inst, // @[mshrs.scala:39:14] input [5:0] io_req_uop_pc_lob, // @[mshrs.scala:39:14] input io_req_uop_taken, // @[mshrs.scala:39:14] input [19:0] io_req_uop_imm_packed, // @[mshrs.scala:39:14] input [11:0] io_req_uop_csr_addr, // @[mshrs.scala:39:14] input [5:0] io_req_uop_rob_idx, // @[mshrs.scala:39:14] input [3:0] io_req_uop_ldq_idx, // @[mshrs.scala:39:14] input [3:0] io_req_uop_stq_idx, // @[mshrs.scala:39:14] input [1:0] io_req_uop_rxq_idx, // @[mshrs.scala:39:14] input [6:0] io_req_uop_pdst, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs1, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs2, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs3, // @[mshrs.scala:39:14] input [3:0] io_req_uop_ppred, // @[mshrs.scala:39:14] input io_req_uop_prs1_busy, // @[mshrs.scala:39:14] input io_req_uop_prs2_busy, // @[mshrs.scala:39:14] input io_req_uop_prs3_busy, // @[mshrs.scala:39:14] input io_req_uop_ppred_busy, // @[mshrs.scala:39:14] input [6:0] io_req_uop_stale_pdst, // @[mshrs.scala:39:14] input io_req_uop_exception, // @[mshrs.scala:39:14] input [63:0] io_req_uop_exc_cause, // @[mshrs.scala:39:14] input io_req_uop_bypassable, // @[mshrs.scala:39:14] input [4:0] io_req_uop_mem_cmd, // @[mshrs.scala:39:14] input [1:0] io_req_uop_mem_size, // @[mshrs.scala:39:14] input io_req_uop_mem_signed, // @[mshrs.scala:39:14] input io_req_uop_is_fence, // @[mshrs.scala:39:14] input io_req_uop_is_fencei, // @[mshrs.scala:39:14] input io_req_uop_is_amo, // @[mshrs.scala:39:14] input io_req_uop_uses_ldq, // @[mshrs.scala:39:14] input io_req_uop_uses_stq, // @[mshrs.scala:39:14] input io_req_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] input io_req_uop_is_unique, // @[mshrs.scala:39:14] input io_req_uop_flush_on_commit, // @[mshrs.scala:39:14] input io_req_uop_ldst_is_rs1, // @[mshrs.scala:39:14] input [5:0] io_req_uop_ldst, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs1, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs2, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs3, // @[mshrs.scala:39:14] input io_req_uop_ldst_val, // @[mshrs.scala:39:14] input [1:0] io_req_uop_dst_rtype, // @[mshrs.scala:39:14] input [1:0] io_req_uop_lrs1_rtype, // @[mshrs.scala:39:14] input [1:0] io_req_uop_lrs2_rtype, // @[mshrs.scala:39:14] input io_req_uop_frs3_en, // @[mshrs.scala:39:14] input io_req_uop_fp_val, // @[mshrs.scala:39:14] input io_req_uop_fp_single, // @[mshrs.scala:39:14] input io_req_uop_xcpt_pf_if, // @[mshrs.scala:39:14] input io_req_uop_xcpt_ae_if, // @[mshrs.scala:39:14] input io_req_uop_xcpt_ma_if, // @[mshrs.scala:39:14] input io_req_uop_bp_debug_if, // @[mshrs.scala:39:14] input io_req_uop_bp_xcpt_if, // @[mshrs.scala:39:14] input [1:0] io_req_uop_debug_fsrc, // @[mshrs.scala:39:14] input [1:0] io_req_uop_debug_tsrc, // @[mshrs.scala:39:14] input [33:0] io_req_addr, // @[mshrs.scala:39:14] input [63:0] io_req_data, // @[mshrs.scala:39:14] input io_req_is_hella, // @[mshrs.scala:39:14] input io_req_tag_match, // @[mshrs.scala:39:14] input [1:0] io_req_old_meta_coh_state, // @[mshrs.scala:39:14] input [21:0] io_req_old_meta_tag, // @[mshrs.scala:39:14] input [1:0] io_req_way_en, // @[mshrs.scala:39:14] input [4:0] io_req_sdq_id, // @[mshrs.scala:39:14] input io_req_is_probe, // @[mshrs.scala:39:14] output io_idx_valid, // @[mshrs.scala:39:14] output [3:0] io_idx_bits, // @[mshrs.scala:39:14] output io_way_valid, // @[mshrs.scala:39:14] output [1:0] io_way_bits, // @[mshrs.scala:39:14] output io_tag_valid, // @[mshrs.scala:39:14] output [23:0] io_tag_bits, // @[mshrs.scala:39:14] input io_mem_acquire_ready, // @[mshrs.scala:39:14] output io_mem_acquire_valid, // @[mshrs.scala:39:14] output [2:0] io_mem_acquire_bits_param, // @[mshrs.scala:39:14] output [31:0] io_mem_acquire_bits_address, // @[mshrs.scala:39:14] output io_mem_grant_ready, // @[mshrs.scala:39:14] input io_mem_grant_valid, // @[mshrs.scala:39:14] input [2:0] io_mem_grant_bits_opcode, // @[mshrs.scala:39:14] input [1:0] io_mem_grant_bits_param, // @[mshrs.scala:39:14] input [3:0] io_mem_grant_bits_size, // @[mshrs.scala:39:14] input [3:0] io_mem_grant_bits_source, // @[mshrs.scala:39:14] input [2:0] io_mem_grant_bits_sink, // @[mshrs.scala:39:14] input io_mem_grant_bits_denied, // @[mshrs.scala:39:14] input [63:0] io_mem_grant_bits_data, // @[mshrs.scala:39:14] input io_mem_grant_bits_corrupt, // @[mshrs.scala:39:14] input io_mem_finish_ready, // @[mshrs.scala:39:14] output io_mem_finish_valid, // @[mshrs.scala:39:14] output [2:0] io_mem_finish_bits_sink, // @[mshrs.scala:39:14] input io_prober_state_valid, // @[mshrs.scala:39:14] input [33:0] io_prober_state_bits, // @[mshrs.scala:39:14] input io_refill_ready, // @[mshrs.scala:39:14] output io_refill_valid, // @[mshrs.scala:39:14] output [1:0] io_refill_bits_way_en, // @[mshrs.scala:39:14] output [9:0] io_refill_bits_addr, // @[mshrs.scala:39:14] output [63:0] io_refill_bits_data, // @[mshrs.scala:39:14] input io_meta_write_ready, // @[mshrs.scala:39:14] output io_meta_write_valid, // @[mshrs.scala:39:14] output [3:0] io_meta_write_bits_idx, // @[mshrs.scala:39:14] output [1:0] io_meta_write_bits_way_en, // @[mshrs.scala:39:14] output [1:0] io_meta_write_bits_data_coh_state, // @[mshrs.scala:39:14] output [21:0] io_meta_write_bits_data_tag, // @[mshrs.scala:39:14] input io_meta_read_ready, // @[mshrs.scala:39:14] output io_meta_read_valid, // @[mshrs.scala:39:14] output [3:0] io_meta_read_bits_idx, // @[mshrs.scala:39:14] output [1:0] io_meta_read_bits_way_en, // @[mshrs.scala:39:14] output [21:0] io_meta_read_bits_tag, // @[mshrs.scala:39:14] input io_meta_resp_valid, // @[mshrs.scala:39:14] input [1:0] io_meta_resp_bits_coh_state, // @[mshrs.scala:39:14] input [21:0] io_meta_resp_bits_tag, // @[mshrs.scala:39:14] input io_wb_req_ready, // @[mshrs.scala:39:14] output io_wb_req_valid, // @[mshrs.scala:39:14] output [21:0] io_wb_req_bits_tag, // @[mshrs.scala:39:14] output [3:0] io_wb_req_bits_idx, // @[mshrs.scala:39:14] output [2:0] io_wb_req_bits_param, // @[mshrs.scala:39:14] output [1:0] io_wb_req_bits_way_en, // @[mshrs.scala:39:14] output io_commit_val, // @[mshrs.scala:39:14] output [33:0] io_commit_addr, // @[mshrs.scala:39:14] output [1:0] io_commit_coh_state, // @[mshrs.scala:39:14] input io_lb_read_ready, // @[mshrs.scala:39:14] output io_lb_read_valid, // @[mshrs.scala:39:14] output [2:0] io_lb_read_bits_offset, // @[mshrs.scala:39:14] input [63:0] io_lb_resp, // @[mshrs.scala:39:14] input io_lb_write_ready, // @[mshrs.scala:39:14] output io_lb_write_valid, // @[mshrs.scala:39:14] output [2:0] io_lb_write_bits_offset, // @[mshrs.scala:39:14] output [63:0] io_lb_write_bits_data, // @[mshrs.scala:39:14] input io_replay_ready, // @[mshrs.scala:39:14] output io_replay_valid, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_uopc, // @[mshrs.scala:39:14] output [31:0] io_replay_bits_uop_inst, // @[mshrs.scala:39:14] output [31:0] io_replay_bits_uop_debug_inst, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_rvc, // @[mshrs.scala:39:14] output [33:0] io_replay_bits_uop_debug_pc, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_iq_type, // @[mshrs.scala:39:14] output [9:0] io_replay_bits_uop_fu_code, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_iw_state, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_br, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_jalr, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_jal, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_sfb, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_br_mask, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_br_tag, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_ftq_idx, // @[mshrs.scala:39:14] output io_replay_bits_uop_edge_inst, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_pc_lob, // @[mshrs.scala:39:14] output io_replay_bits_uop_taken, // @[mshrs.scala:39:14] output [19:0] io_replay_bits_uop_imm_packed, // @[mshrs.scala:39:14] output [11:0] io_replay_bits_uop_csr_addr, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_rob_idx, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_ldq_idx, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_stq_idx, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_rxq_idx, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_pdst, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs1, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs2, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs3, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_ppred, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs1_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs2_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs3_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_ppred_busy, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_stale_pdst, // @[mshrs.scala:39:14] output io_replay_bits_uop_exception, // @[mshrs.scala:39:14] output [63:0] io_replay_bits_uop_exc_cause, // @[mshrs.scala:39:14] output io_replay_bits_uop_bypassable, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_mem_cmd, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_mem_size, // @[mshrs.scala:39:14] output io_replay_bits_uop_mem_signed, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_fence, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_fencei, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_amo, // @[mshrs.scala:39:14] output io_replay_bits_uop_uses_ldq, // @[mshrs.scala:39:14] output io_replay_bits_uop_uses_stq, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_unique, // @[mshrs.scala:39:14] output io_replay_bits_uop_flush_on_commit, // @[mshrs.scala:39:14] output io_replay_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_ldst, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs1, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs2, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs3, // @[mshrs.scala:39:14] output io_replay_bits_uop_ldst_val, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_dst_rtype, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14] output io_replay_bits_uop_frs3_en, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_val, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_single, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_bp_debug_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_debug_fsrc, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_debug_tsrc, // @[mshrs.scala:39:14] output [33:0] io_replay_bits_addr, // @[mshrs.scala:39:14] output [63:0] io_replay_bits_data, // @[mshrs.scala:39:14] output io_replay_bits_is_hella, // @[mshrs.scala:39:14] output io_replay_bits_tag_match, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_old_meta_coh_state, // @[mshrs.scala:39:14] output [21:0] io_replay_bits_old_meta_tag, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_way_en, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_sdq_id, // @[mshrs.scala:39:14] input io_resp_ready, // @[mshrs.scala:39:14] output io_resp_valid, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_uopc, // @[mshrs.scala:39:14] output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:39:14] output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_rvc, // @[mshrs.scala:39:14] output [33:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_iq_type, // @[mshrs.scala:39:14] output [9:0] io_resp_bits_uop_fu_code, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_iw_state, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_br, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_jalr, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_jal, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_sfb, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:39:14] output io_resp_bits_uop_edge_inst, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:39:14] output io_resp_bits_uop_taken, // @[mshrs.scala:39:14] output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:39:14] output [11:0] io_resp_bits_uop_csr_addr, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_pdst, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs1, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs2, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs3, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_ppred, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:39:14] output io_resp_bits_uop_exception, // @[mshrs.scala:39:14] output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:39:14] output io_resp_bits_uop_bypassable, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:39:14] output io_resp_bits_uop_mem_signed, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_fence, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_fencei, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_amo, // @[mshrs.scala:39:14] output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:39:14] output io_resp_bits_uop_uses_stq, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_unique, // @[mshrs.scala:39:14] output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:39:14] output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:39:14] output io_resp_bits_uop_ldst_val, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14] output io_resp_bits_uop_frs3_en, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_val, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_single, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:39:14] output [63:0] io_resp_bits_data, // @[mshrs.scala:39:14] output io_resp_bits_is_hella, // @[mshrs.scala:39:14] input io_wb_resp, // @[mshrs.scala:39:14] output io_probe_rdy // @[mshrs.scala:39:14] ); wire rpq_io_deq_ready; // @[mshrs.scala:135:20, :215:30, :222:40, :233:41, :256:45] wire _rpq_io_enq_ready; // @[mshrs.scala:128:19] wire _rpq_io_deq_valid; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_uopc; // @[mshrs.scala:128:19] wire [31:0] _rpq_io_deq_bits_uop_inst; // @[mshrs.scala:128:19] wire [31:0] _rpq_io_deq_bits_uop_debug_inst; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_rvc; // @[mshrs.scala:128:19] wire [33:0] _rpq_io_deq_bits_uop_debug_pc; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_iq_type; // @[mshrs.scala:128:19] wire [9:0] _rpq_io_deq_bits_uop_fu_code; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_ctrl_br_type; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_ctrl_op1_sel; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_ctrl_op2_sel; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_ctrl_imm_sel; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_ctrl_op_fcn; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_fcn_dw; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_ctrl_csr_cmd; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_is_load; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_is_sta; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_is_std; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_iw_state; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_p1_poisoned; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_p2_poisoned; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_br; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_jalr; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_jal; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_sfb; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_br_mask; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_br_tag; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_ftq_idx; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_edge_inst; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_pc_lob; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_taken; // @[mshrs.scala:128:19] wire [19:0] _rpq_io_deq_bits_uop_imm_packed; // @[mshrs.scala:128:19] wire [11:0] _rpq_io_deq_bits_uop_csr_addr; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_rob_idx; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_ldq_idx; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_stq_idx; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_rxq_idx; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_pdst; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs1; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs2; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs3; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_ppred; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs1_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs2_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs3_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ppred_busy; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_stale_pdst; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_exception; // @[mshrs.scala:128:19] wire [63:0] _rpq_io_deq_bits_uop_exc_cause; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bypassable; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_mem_cmd; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_mem_size; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_mem_signed; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_fence; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_fencei; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_amo; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_uses_ldq; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_uses_stq; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_sys_pc2epc; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_unique; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_flush_on_commit; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ldst_is_rs1; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_ldst; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs1; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs2; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs3; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ldst_val; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_dst_rtype; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_lrs1_rtype; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_lrs2_rtype; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_frs3_en; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_val; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_single; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_pf_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_ae_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_ma_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bp_debug_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bp_xcpt_if; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_debug_fsrc; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_debug_tsrc; // @[mshrs.scala:128:19] wire [33:0] _rpq_io_deq_bits_addr; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_is_hella; // @[mshrs.scala:128:19] wire _rpq_io_empty; // @[mshrs.scala:128:19] wire io_req_pri_val_0 = io_req_pri_val; // @[mshrs.scala:36:7] wire io_req_sec_val_0 = io_req_sec_val; // @[mshrs.scala:36:7] wire io_clear_prefetch_0 = io_clear_prefetch; // @[mshrs.scala:36:7] wire [5:0] io_rob_pnr_idx_0 = io_rob_pnr_idx; // @[mshrs.scala:36:7] wire [5:0] io_rob_head_idx_0 = io_rob_head_idx; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_uopc_0 = io_req_uop_uopc; // @[mshrs.scala:36:7] wire [31:0] io_req_uop_inst_0 = io_req_uop_inst; // @[mshrs.scala:36:7] wire [31:0] io_req_uop_debug_inst_0 = io_req_uop_debug_inst; // @[mshrs.scala:36:7] wire io_req_uop_is_rvc_0 = io_req_uop_is_rvc; // @[mshrs.scala:36:7] wire [33:0] io_req_uop_debug_pc_0 = io_req_uop_debug_pc; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_iq_type_0 = io_req_uop_iq_type; // @[mshrs.scala:36:7] wire [9:0] io_req_uop_fu_code_0 = io_req_uop_fu_code; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_ctrl_br_type_0 = io_req_uop_ctrl_br_type; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_ctrl_op1_sel_0 = io_req_uop_ctrl_op1_sel; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_ctrl_op2_sel_0 = io_req_uop_ctrl_op2_sel; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_ctrl_imm_sel_0 = io_req_uop_ctrl_imm_sel; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_ctrl_op_fcn_0 = io_req_uop_ctrl_op_fcn; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_fcn_dw_0 = io_req_uop_ctrl_fcn_dw; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_ctrl_csr_cmd_0 = io_req_uop_ctrl_csr_cmd; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_is_load_0 = io_req_uop_ctrl_is_load; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_is_sta_0 = io_req_uop_ctrl_is_sta; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_is_std_0 = io_req_uop_ctrl_is_std; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_iw_state_0 = io_req_uop_iw_state; // @[mshrs.scala:36:7] wire io_req_uop_iw_p1_poisoned_0 = io_req_uop_iw_p1_poisoned; // @[mshrs.scala:36:7] wire io_req_uop_iw_p2_poisoned_0 = io_req_uop_iw_p2_poisoned; // @[mshrs.scala:36:7] wire io_req_uop_is_br_0 = io_req_uop_is_br; // @[mshrs.scala:36:7] wire io_req_uop_is_jalr_0 = io_req_uop_is_jalr; // @[mshrs.scala:36:7] wire io_req_uop_is_jal_0 = io_req_uop_is_jal; // @[mshrs.scala:36:7] wire io_req_uop_is_sfb_0 = io_req_uop_is_sfb; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_br_mask_0 = io_req_uop_br_mask; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_br_tag_0 = io_req_uop_br_tag; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_ftq_idx_0 = io_req_uop_ftq_idx; // @[mshrs.scala:36:7] wire io_req_uop_edge_inst_0 = io_req_uop_edge_inst; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_pc_lob_0 = io_req_uop_pc_lob; // @[mshrs.scala:36:7] wire io_req_uop_taken_0 = io_req_uop_taken; // @[mshrs.scala:36:7] wire [19:0] io_req_uop_imm_packed_0 = io_req_uop_imm_packed; // @[mshrs.scala:36:7] wire [11:0] io_req_uop_csr_addr_0 = io_req_uop_csr_addr; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_rob_idx_0 = io_req_uop_rob_idx; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_ldq_idx_0 = io_req_uop_ldq_idx; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_stq_idx_0 = io_req_uop_stq_idx; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_rxq_idx_0 = io_req_uop_rxq_idx; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_pdst_0 = io_req_uop_pdst; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs1_0 = io_req_uop_prs1; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs2_0 = io_req_uop_prs2; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs3_0 = io_req_uop_prs3; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_ppred_0 = io_req_uop_ppred; // @[mshrs.scala:36:7] wire io_req_uop_prs1_busy_0 = io_req_uop_prs1_busy; // @[mshrs.scala:36:7] wire io_req_uop_prs2_busy_0 = io_req_uop_prs2_busy; // @[mshrs.scala:36:7] wire io_req_uop_prs3_busy_0 = io_req_uop_prs3_busy; // @[mshrs.scala:36:7] wire io_req_uop_ppred_busy_0 = io_req_uop_ppred_busy; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_stale_pdst_0 = io_req_uop_stale_pdst; // @[mshrs.scala:36:7] wire io_req_uop_exception_0 = io_req_uop_exception; // @[mshrs.scala:36:7] wire [63:0] io_req_uop_exc_cause_0 = io_req_uop_exc_cause; // @[mshrs.scala:36:7] wire io_req_uop_bypassable_0 = io_req_uop_bypassable; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_mem_cmd_0 = io_req_uop_mem_cmd; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_mem_size_0 = io_req_uop_mem_size; // @[mshrs.scala:36:7] wire io_req_uop_mem_signed_0 = io_req_uop_mem_signed; // @[mshrs.scala:36:7] wire io_req_uop_is_fence_0 = io_req_uop_is_fence; // @[mshrs.scala:36:7] wire io_req_uop_is_fencei_0 = io_req_uop_is_fencei; // @[mshrs.scala:36:7] wire io_req_uop_is_amo_0 = io_req_uop_is_amo; // @[mshrs.scala:36:7] wire io_req_uop_uses_ldq_0 = io_req_uop_uses_ldq; // @[mshrs.scala:36:7] wire io_req_uop_uses_stq_0 = io_req_uop_uses_stq; // @[mshrs.scala:36:7] wire io_req_uop_is_sys_pc2epc_0 = io_req_uop_is_sys_pc2epc; // @[mshrs.scala:36:7] wire io_req_uop_is_unique_0 = io_req_uop_is_unique; // @[mshrs.scala:36:7] wire io_req_uop_flush_on_commit_0 = io_req_uop_flush_on_commit; // @[mshrs.scala:36:7] wire io_req_uop_ldst_is_rs1_0 = io_req_uop_ldst_is_rs1; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_ldst_0 = io_req_uop_ldst; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs1_0 = io_req_uop_lrs1; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs2_0 = io_req_uop_lrs2; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs3_0 = io_req_uop_lrs3; // @[mshrs.scala:36:7] wire io_req_uop_ldst_val_0 = io_req_uop_ldst_val; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_dst_rtype_0 = io_req_uop_dst_rtype; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_lrs1_rtype_0 = io_req_uop_lrs1_rtype; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_lrs2_rtype_0 = io_req_uop_lrs2_rtype; // @[mshrs.scala:36:7] wire io_req_uop_frs3_en_0 = io_req_uop_frs3_en; // @[mshrs.scala:36:7] wire io_req_uop_fp_val_0 = io_req_uop_fp_val; // @[mshrs.scala:36:7] wire io_req_uop_fp_single_0 = io_req_uop_fp_single; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_pf_if_0 = io_req_uop_xcpt_pf_if; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_ae_if_0 = io_req_uop_xcpt_ae_if; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_ma_if_0 = io_req_uop_xcpt_ma_if; // @[mshrs.scala:36:7] wire io_req_uop_bp_debug_if_0 = io_req_uop_bp_debug_if; // @[mshrs.scala:36:7] wire io_req_uop_bp_xcpt_if_0 = io_req_uop_bp_xcpt_if; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_debug_fsrc_0 = io_req_uop_debug_fsrc; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_debug_tsrc_0 = io_req_uop_debug_tsrc; // @[mshrs.scala:36:7] wire [33:0] io_req_addr_0 = io_req_addr; // @[mshrs.scala:36:7] wire [63:0] io_req_data_0 = io_req_data; // @[mshrs.scala:36:7] wire io_req_is_hella_0 = io_req_is_hella; // @[mshrs.scala:36:7] wire io_req_tag_match_0 = io_req_tag_match; // @[mshrs.scala:36:7] wire [1:0] io_req_old_meta_coh_state_0 = io_req_old_meta_coh_state; // @[mshrs.scala:36:7] wire [21:0] io_req_old_meta_tag_0 = io_req_old_meta_tag; // @[mshrs.scala:36:7] wire [1:0] io_req_way_en_0 = io_req_way_en; // @[mshrs.scala:36:7] wire [4:0] io_req_sdq_id_0 = io_req_sdq_id; // @[mshrs.scala:36:7] wire io_req_is_probe_0 = io_req_is_probe; // @[mshrs.scala:36:7] wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[mshrs.scala:36:7] wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[mshrs.scala:36:7] wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[mshrs.scala:36:7] wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[mshrs.scala:36:7] wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[mshrs.scala:36:7] wire [3:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[mshrs.scala:36:7] wire [2:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[mshrs.scala:36:7] wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[mshrs.scala:36:7] wire [63:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[mshrs.scala:36:7] wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[mshrs.scala:36:7] wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[mshrs.scala:36:7] wire io_prober_state_valid_0 = io_prober_state_valid; // @[mshrs.scala:36:7] wire [33:0] io_prober_state_bits_0 = io_prober_state_bits; // @[mshrs.scala:36:7] wire io_refill_ready_0 = io_refill_ready; // @[mshrs.scala:36:7] wire io_meta_write_ready_0 = io_meta_write_ready; // @[mshrs.scala:36:7] wire io_meta_read_ready_0 = io_meta_read_ready; // @[mshrs.scala:36:7] wire io_meta_resp_valid_0 = io_meta_resp_valid; // @[mshrs.scala:36:7] wire [1:0] io_meta_resp_bits_coh_state_0 = io_meta_resp_bits_coh_state; // @[mshrs.scala:36:7] wire [21:0] io_meta_resp_bits_tag_0 = io_meta_resp_bits_tag; // @[mshrs.scala:36:7] wire io_wb_req_ready_0 = io_wb_req_ready; // @[mshrs.scala:36:7] wire io_lb_read_ready_0 = io_lb_read_ready; // @[mshrs.scala:36:7] wire [63:0] io_lb_resp_0 = io_lb_resp; // @[mshrs.scala:36:7] wire io_lb_write_ready_0 = io_lb_write_ready; // @[mshrs.scala:36:7] wire io_replay_ready_0 = io_replay_ready; // @[mshrs.scala:36:7] wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:36:7] wire io_wb_resp_0 = io_wb_resp; // @[mshrs.scala:36:7] wire _state_T = reset; // @[mshrs.scala:194:11] wire _state_T_26 = reset; // @[mshrs.scala:201:15] wire _state_T_34 = reset; // @[mshrs.scala:194:11] wire _state_T_60 = reset; // @[mshrs.scala:201:15] wire [2:0] io_id = 3'h1; // @[mshrs.scala:36:7] wire [2:0] io_lb_read_bits_id = 3'h1; // @[mshrs.scala:36:7] wire [2:0] io_lb_write_bits_id = 3'h1; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[mshrs.scala:36:7] wire [3:0] _r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _grow_param_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _coh_on_grant_T_4 = 4'h0; // @[Metadata.scala:87:10] wire [3:0] _r1_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r2_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _state_req_needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _state_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _r_T_80 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r_T_139 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _state_req_needs_wb_r_T_74 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _state_r_T_75 = 4'h0; // @[Metadata.scala:68:10] wire [6:0] io_brupdate_b2_uop_uopc = 7'h0; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_pdst = 7'h0; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs1 = 7'h0; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs2 = 7'h0; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs3 = 7'h0; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_stale_pdst = 7'h0; // @[mshrs.scala:36:7] wire [6:0] _data_word_T = 7'h0; // @[mshrs.scala:264:32] wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[mshrs.scala:36:7] wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_fcn_dw = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_is_load = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_is_sta = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_is_std = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_p1_poisoned = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_p2_poisoned = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_br = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_jalr = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_jal = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_taken = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_exception = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bypassable = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_fence = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_amo = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_unique = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ldst_val = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_val = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_single = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_valid = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_mispredict = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_taken = 1'h0; // @[mshrs.scala:36:7] wire io_exception = 1'h0; // @[mshrs.scala:36:7] wire io_mem_acquire_bits_corrupt = 1'h0; // @[mshrs.scala:36:7] wire _r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _grow_param_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_38 = 1'h0; // @[Misc.scala:35:9] wire _state_req_needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _state_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _io_mem_acquire_bits_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _io_mem_acquire_bits_legal_T_6 = 1'h0; // @[Parameters.scala:684:54] wire _io_mem_acquire_bits_legal_T_15 = 1'h0; // @[Parameters.scala:686:26] wire io_mem_acquire_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17] wire io_mem_acquire_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _io_mem_acquire_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire _needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _r_T_90 = 1'h0; // @[Misc.scala:35:9] wire _r_T_93 = 1'h0; // @[Misc.scala:35:9] wire _r_T_96 = 1'h0; // @[Misc.scala:35:9] wire _r_T_99 = 1'h0; // @[Misc.scala:35:9] wire _r_T_102 = 1'h0; // @[Misc.scala:35:9] wire _r_T_149 = 1'h0; // @[Misc.scala:35:9] wire _r_T_152 = 1'h0; // @[Misc.scala:35:9] wire _r_T_155 = 1'h0; // @[Misc.scala:35:9] wire _r_T_158 = 1'h0; // @[Misc.scala:35:9] wire _r_T_161 = 1'h0; // @[Misc.scala:35:9] wire _state_req_needs_wb_r_T_66 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_68 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_84 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_88 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_92 = 1'h0; // @[Misc.scala:38:9] wire _state_r_T_85 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_88 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_91 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_94 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_97 = 1'h0; // @[Misc.scala:35:9] wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[mshrs.scala:36:7] wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_iq_type = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[mshrs.scala:36:7] wire [9:0] io_brupdate_b2_uop_fu_code = 10'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_iw_state = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_target_offset = 2'h0; // @[mshrs.scala:36:7] wire [1:0] new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _grow_param_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_req_needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] state_new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_65 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_67 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_69 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_79 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_124 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_126 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_128 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_138 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _state_req_needs_wb_r_T_86 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_90 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_94 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_98 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_102 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_r_T_60 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_62 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_64 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_74 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] state_new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn = 5'h0; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_rob_idx = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[mshrs.scala:36:7] wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[mshrs.scala:36:7] wire [11:0] io_brupdate_b2_uop_csr_addr = 12'h0; // @[mshrs.scala:36:7] wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[mshrs.scala:36:7] wire [63:0] io_mem_acquire_bits_data = 64'h0; // @[mshrs.scala:36:7] wire [63:0] io_mem_acquire_bits_a_data = 64'h0; // @[Edges.scala:346:17] wire [2:0] io_mem_acquire_bits_opcode = 3'h6; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_a_opcode = 3'h6; // @[Edges.scala:346:17] wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34] wire [3:0] io_mem_acquire_bits_size = 4'h6; // @[mshrs.scala:36:7] wire [3:0] _r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _grow_param_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r1_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r2_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _state_req_needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _state_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] io_mem_acquire_bits_a_size = 4'h6; // @[Edges.scala:346:17] wire [3:0] _needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _r_T_74 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r_T_133 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _state_req_needs_wb_r_T_76 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _state_r_T_69 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] io_mem_acquire_bits_source = 4'h1; // @[mshrs.scala:36:7] wire [3:0] io_wb_req_bits_source = 4'h1; // @[mshrs.scala:36:7] wire [3:0] _r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _grow_param_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _coh_on_grant_T_2 = 4'h1; // @[Metadata.scala:86:10] wire [3:0] _r1_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r2_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _state_req_needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _state_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] io_mem_acquire_bits_a_source = 4'h1; // @[Edges.scala:346:17] wire [3:0] _needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _r_T_70 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_129 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _state_req_needs_wb_r_T_73 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _state_r_T_65 = 4'h1; // @[Metadata.scala:62:10] wire [7:0] io_mem_acquire_bits_mask = 8'hFF; // @[mshrs.scala:36:7] wire [7:0] io_mem_acquire_bits_a_mask = 8'hFF; // @[Edges.scala:346:17] wire [7:0] _io_mem_acquire_bits_a_mask_T = 8'hFF; // @[Misc.scala:222:10] wire io_refill_bits_wmask = 1'h1; // @[mshrs.scala:36:7] wire io_wb_req_bits_voluntary = 1'h1; // @[mshrs.scala:36:7] wire _r_T = 1'h1; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _io_mem_acquire_bits_legal_T_7 = 1'h1; // @[Parameters.scala:91:44] wire _io_mem_acquire_bits_legal_T_8 = 1'h1; // @[Parameters.scala:684:29] wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire io_mem_acquire_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire _needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _io_refill_bits_wmask_T = 1'h1; // @[mshrs.scala:342:30] wire _state_req_needs_wb_r_T_64 = 1'h1; // @[Metadata.scala:140:24] wire [21:0] io_meta_write_bits_tag = 22'h0; // @[mshrs.scala:36:7] wire [3:0] _grow_param_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _coh_on_grant_T_8 = 4'hC; // @[Metadata.scala:89:10] wire [3:0] _r1_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r2_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _state_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_88 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_147 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _state_r_T_83 = 4'hC; // @[Metadata.scala:72:10] wire [1:0] _grow_param_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _coh_on_grant_T_7 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _dirties_T = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] io_mem_acquire_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _r_T_75 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_77 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_85 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_87 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_134 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_136 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_144 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_146 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_70 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_72 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_80 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_82 = 2'h3; // @[Metadata.scala:24:15] wire [3:0] _grow_param_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r1_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r2_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _state_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_86 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_145 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _state_r_T_81 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _grow_param_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _coh_on_grant_T_6 = 4'h4; // @[Metadata.scala:88:10] wire [3:0] _r1_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r2_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _state_req_needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _state_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _r_T_84 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r_T_143 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _state_req_needs_wb_r_T_78 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _state_r_T_79 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _grow_param_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r1_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r2_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _state_req_needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _state_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_82 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r_T_141 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _state_req_needs_wb_r_T_77 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _state_r_T_77 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _grow_param_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r1_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r2_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _state_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_78 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_137 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _state_r_T_73 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _grow_param_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r1_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r2_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _state_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] io_mem_acquire_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] io_mem_acquire_bits_a_mask_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] _r_T_76 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_135 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _state_r_T_71 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _grow_param_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r1_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r2_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _state_req_needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _state_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_72 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r_T_131 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _state_req_needs_wb_r_T_75 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _state_r_T_67 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _grow_param_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r1_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r2_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _state_req_needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _state_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_68 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_127 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _state_req_needs_wb_r_T_72 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _state_r_T_63 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _grow_param_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r1_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r2_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _state_req_needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _state_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_66 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_125 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _state_req_needs_wb_r_T_71 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _state_r_T_61 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _state_req_needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _state_req_needs_wb_r_T_82 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _state_req_needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _state_req_needs_wb_r_T_81 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _state_req_needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _state_req_needs_wb_r_T_80 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _state_req_needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _state_req_needs_wb_r_T_79 = 4'hB; // @[Metadata.scala:130:10] wire [1:0] _r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [1:0] _needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_65 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_67 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_69 = 2'h2; // @[Metadata.scala:140:24] wire [2:0] io_mem_acquire_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [1:0] _grow_param_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _coh_on_grant_T_5 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_71 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_73 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_81 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_83 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_130 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_132 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_140 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_142 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_66 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_68 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_76 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_78 = 2'h1; // @[Metadata.scala:25:15] wire _io_req_sec_rdy_T; // @[mshrs.scala:159:37] wire _io_idx_valid_T; // @[mshrs.scala:149:25] wire [3:0] req_idx; // @[mshrs.scala:110:25] wire _io_way_valid_T_3; // @[mshrs.scala:151:19] wire _io_tag_valid_T; // @[mshrs.scala:150:25] wire [23:0] req_tag; // @[mshrs.scala:111:26] wire [2:0] io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] wire [31:0] io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] wire [2:0] grantack_bits_e_sink = io_mem_grant_bits_sink_0; // @[Edges.scala:451:17] wire [63:0] io_lb_write_bits_data_0 = io_mem_grant_bits_data_0; // @[mshrs.scala:36:7] wire [2:0] shrink_param; // @[Misc.scala:38:36] wire [1:0] coh_on_grant_state; // @[Metadata.scala:160:20] wire [63:0] io_refill_bits_data_0 = io_lb_resp_0; // @[mshrs.scala:36:7] wire [63:0] data_word = io_lb_resp_0; // @[mshrs.scala:36:7, :264:26] wire [33:0] _io_replay_bits_addr_T_1; // @[mshrs.scala:353:31] wire [63:0] _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16] wire _io_probe_rdy_T_11; // @[mshrs.scala:148:42] wire io_idx_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_idx_bits_0; // @[mshrs.scala:36:7] wire io_way_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_way_bits_0; // @[mshrs.scala:36:7] wire io_tag_valid_0; // @[mshrs.scala:36:7] wire [23:0] io_tag_bits_0; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_param_0; // @[mshrs.scala:36:7] wire [31:0] io_mem_acquire_bits_address_0; // @[mshrs.scala:36:7] wire io_mem_acquire_valid_0; // @[mshrs.scala:36:7] wire io_mem_grant_ready_0; // @[mshrs.scala:36:7] wire [2:0] io_mem_finish_bits_sink_0; // @[mshrs.scala:36:7] wire io_mem_finish_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_refill_bits_way_en_0; // @[mshrs.scala:36:7] wire [9:0] io_refill_bits_addr_0; // @[mshrs.scala:36:7] wire io_refill_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_meta_write_bits_data_coh_state_0; // @[mshrs.scala:36:7] wire [21:0] io_meta_write_bits_data_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_meta_write_bits_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_meta_write_bits_way_en_0; // @[mshrs.scala:36:7] wire io_meta_write_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_meta_read_bits_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_meta_read_bits_way_en_0; // @[mshrs.scala:36:7] wire [21:0] io_meta_read_bits_tag_0; // @[mshrs.scala:36:7] wire io_meta_read_valid_0; // @[mshrs.scala:36:7] wire [21:0] io_wb_req_bits_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_wb_req_bits_idx_0; // @[mshrs.scala:36:7] wire [2:0] io_wb_req_bits_param_0; // @[mshrs.scala:36:7] wire [1:0] io_wb_req_bits_way_en_0; // @[mshrs.scala:36:7] wire io_wb_req_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_commit_coh_state_0; // @[mshrs.scala:36:7] wire [2:0] io_lb_read_bits_offset_0; // @[mshrs.scala:36:7] wire io_lb_read_valid_0; // @[mshrs.scala:36:7] wire [2:0] io_lb_write_bits_offset_0; // @[mshrs.scala:36:7] wire io_lb_write_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_uopc_0; // @[mshrs.scala:36:7] wire [31:0] io_replay_bits_uop_inst_0; // @[mshrs.scala:36:7] wire [31:0] io_replay_bits_uop_debug_inst_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_rvc_0; // @[mshrs.scala:36:7] wire [33:0] io_replay_bits_uop_debug_pc_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_iq_type_0; // @[mshrs.scala:36:7] wire [9:0] io_replay_bits_uop_fu_code_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_iw_state_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_br_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_jalr_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_jal_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_sfb_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_br_mask_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_br_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_edge_inst_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_pc_lob_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_taken_0; // @[mshrs.scala:36:7] wire [19:0] io_replay_bits_uop_imm_packed_0; // @[mshrs.scala:36:7] wire [11:0] io_replay_bits_uop_csr_addr_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_rob_idx_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_stq_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_pdst_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs1_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs2_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs3_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_ppred_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_exception_0; // @[mshrs.scala:36:7] wire [63:0] io_replay_bits_uop_exc_cause_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bypassable_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_mem_size_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_mem_signed_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_fence_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_fencei_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_amo_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_uses_stq_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_unique_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_ldst_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs1_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs2_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs3_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ldst_val_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_frs3_en_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_val_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_single_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_old_meta_coh_state_0; // @[mshrs.scala:36:7] wire [21:0] io_replay_bits_old_meta_tag_0; // @[mshrs.scala:36:7] wire [33:0] io_replay_bits_addr_0; // @[mshrs.scala:36:7] wire [63:0] io_replay_bits_data_0; // @[mshrs.scala:36:7] wire io_replay_bits_is_hella_0; // @[mshrs.scala:36:7] wire io_replay_bits_tag_match_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_way_en_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_sdq_id_0; // @[mshrs.scala:36:7] wire io_replay_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_uopc_0; // @[mshrs.scala:36:7] wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:36:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:36:7] wire [33:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_iq_type_0; // @[mshrs.scala:36:7] wire [9:0] io_resp_bits_uop_fu_code_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_iw_state_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_br_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_jalr_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_jal_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_taken_0; // @[mshrs.scala:36:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:36:7] wire [11:0] io_resp_bits_uop_csr_addr_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_exception_0; // @[mshrs.scala:36:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bypassable_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ldst_val_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_single_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7] wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:36:7] wire io_resp_bits_is_hella_0; // @[mshrs.scala:36:7] wire io_resp_valid_0; // @[mshrs.scala:36:7] wire io_req_pri_rdy_0; // @[mshrs.scala:36:7] wire io_req_sec_rdy_0; // @[mshrs.scala:36:7] wire io_commit_val_0; // @[mshrs.scala:36:7] wire [33:0] io_commit_addr_0; // @[mshrs.scala:36:7] wire io_probe_rdy_0; // @[mshrs.scala:36:7] reg [4:0] state; // @[mshrs.scala:107:22] reg [6:0] req_uop_uopc; // @[mshrs.scala:109:20] reg [31:0] req_uop_inst; // @[mshrs.scala:109:20] reg [31:0] req_uop_debug_inst; // @[mshrs.scala:109:20] reg req_uop_is_rvc; // @[mshrs.scala:109:20] reg [33:0] req_uop_debug_pc; // @[mshrs.scala:109:20] reg [2:0] req_uop_iq_type; // @[mshrs.scala:109:20] reg [9:0] req_uop_fu_code; // @[mshrs.scala:109:20] reg [3:0] req_uop_ctrl_br_type; // @[mshrs.scala:109:20] reg [1:0] req_uop_ctrl_op1_sel; // @[mshrs.scala:109:20] reg [2:0] req_uop_ctrl_op2_sel; // @[mshrs.scala:109:20] reg [2:0] req_uop_ctrl_imm_sel; // @[mshrs.scala:109:20] reg [4:0] req_uop_ctrl_op_fcn; // @[mshrs.scala:109:20] reg req_uop_ctrl_fcn_dw; // @[mshrs.scala:109:20] reg [2:0] req_uop_ctrl_csr_cmd; // @[mshrs.scala:109:20] reg req_uop_ctrl_is_load; // @[mshrs.scala:109:20] reg req_uop_ctrl_is_sta; // @[mshrs.scala:109:20] reg req_uop_ctrl_is_std; // @[mshrs.scala:109:20] reg [1:0] req_uop_iw_state; // @[mshrs.scala:109:20] reg req_uop_iw_p1_poisoned; // @[mshrs.scala:109:20] reg req_uop_iw_p2_poisoned; // @[mshrs.scala:109:20] reg req_uop_is_br; // @[mshrs.scala:109:20] reg req_uop_is_jalr; // @[mshrs.scala:109:20] reg req_uop_is_jal; // @[mshrs.scala:109:20] reg req_uop_is_sfb; // @[mshrs.scala:109:20] reg [3:0] req_uop_br_mask; // @[mshrs.scala:109:20] reg [1:0] req_uop_br_tag; // @[mshrs.scala:109:20] reg [3:0] req_uop_ftq_idx; // @[mshrs.scala:109:20] reg req_uop_edge_inst; // @[mshrs.scala:109:20] reg [5:0] req_uop_pc_lob; // @[mshrs.scala:109:20] reg req_uop_taken; // @[mshrs.scala:109:20] reg [19:0] req_uop_imm_packed; // @[mshrs.scala:109:20] reg [11:0] req_uop_csr_addr; // @[mshrs.scala:109:20] reg [5:0] req_uop_rob_idx; // @[mshrs.scala:109:20] reg [3:0] req_uop_ldq_idx; // @[mshrs.scala:109:20] reg [3:0] req_uop_stq_idx; // @[mshrs.scala:109:20] reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:109:20] reg [6:0] req_uop_pdst; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs1; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs2; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs3; // @[mshrs.scala:109:20] reg [3:0] req_uop_ppred; // @[mshrs.scala:109:20] reg req_uop_prs1_busy; // @[mshrs.scala:109:20] reg req_uop_prs2_busy; // @[mshrs.scala:109:20] reg req_uop_prs3_busy; // @[mshrs.scala:109:20] reg req_uop_ppred_busy; // @[mshrs.scala:109:20] reg [6:0] req_uop_stale_pdst; // @[mshrs.scala:109:20] reg req_uop_exception; // @[mshrs.scala:109:20] reg [63:0] req_uop_exc_cause; // @[mshrs.scala:109:20] reg req_uop_bypassable; // @[mshrs.scala:109:20] reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:109:20] reg [1:0] req_uop_mem_size; // @[mshrs.scala:109:20] reg req_uop_mem_signed; // @[mshrs.scala:109:20] reg req_uop_is_fence; // @[mshrs.scala:109:20] reg req_uop_is_fencei; // @[mshrs.scala:109:20] reg req_uop_is_amo; // @[mshrs.scala:109:20] reg req_uop_uses_ldq; // @[mshrs.scala:109:20] reg req_uop_uses_stq; // @[mshrs.scala:109:20] reg req_uop_is_sys_pc2epc; // @[mshrs.scala:109:20] reg req_uop_is_unique; // @[mshrs.scala:109:20] reg req_uop_flush_on_commit; // @[mshrs.scala:109:20] reg req_uop_ldst_is_rs1; // @[mshrs.scala:109:20] reg [5:0] req_uop_ldst; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs1; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs2; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs3; // @[mshrs.scala:109:20] reg req_uop_ldst_val; // @[mshrs.scala:109:20] reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:109:20] reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:109:20] reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:109:20] reg req_uop_frs3_en; // @[mshrs.scala:109:20] reg req_uop_fp_val; // @[mshrs.scala:109:20] reg req_uop_fp_single; // @[mshrs.scala:109:20] reg req_uop_xcpt_pf_if; // @[mshrs.scala:109:20] reg req_uop_xcpt_ae_if; // @[mshrs.scala:109:20] reg req_uop_xcpt_ma_if; // @[mshrs.scala:109:20] reg req_uop_bp_debug_if; // @[mshrs.scala:109:20] reg req_uop_bp_xcpt_if; // @[mshrs.scala:109:20] reg [1:0] req_uop_debug_fsrc; // @[mshrs.scala:109:20] reg [1:0] req_uop_debug_tsrc; // @[mshrs.scala:109:20] reg [33:0] req_addr; // @[mshrs.scala:109:20] assign io_commit_addr_0 = req_addr; // @[mshrs.scala:36:7, :109:20] reg [63:0] req_data; // @[mshrs.scala:109:20] reg req_is_hella; // @[mshrs.scala:109:20] reg req_tag_match; // @[mshrs.scala:109:20] reg [1:0] req_old_meta_coh_state; // @[mshrs.scala:109:20] reg [21:0] req_old_meta_tag; // @[mshrs.scala:109:20] assign io_wb_req_bits_tag_0 = req_old_meta_tag; // @[mshrs.scala:36:7, :109:20] reg [1:0] req_way_en; // @[mshrs.scala:109:20] assign io_way_bits_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_refill_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_meta_write_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_meta_read_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_wb_req_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_replay_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] reg [4:0] req_sdq_id; // @[mshrs.scala:109:20] assign req_idx = req_addr[9:6]; // @[mshrs.scala:109:20, :110:25] assign io_idx_bits_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_meta_write_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_meta_read_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_wb_req_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign req_tag = req_addr[33:10]; // @[mshrs.scala:109:20, :111:26] assign io_tag_bits_0 = req_tag; // @[mshrs.scala:36:7, :111:26] wire [27:0] _req_block_addr_T = req_addr[33:6]; // @[mshrs.scala:109:20, :112:34] wire [33:0] req_block_addr = {_req_block_addr_T, 6'h0}; // @[mshrs.scala:112:{34,51}] reg req_needs_wb; // @[mshrs.scala:113:29] reg [1:0] new_coh_state; // @[mshrs.scala:115:24] wire [3:0] _r_T_6 = {2'h2, req_old_meta_coh_state}; // @[Metadata.scala:120:19] wire _r_T_19 = _r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_21 = _r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_23 = _r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_25 = _r_T_23 ? 3'h2 : _r_T_21; // @[Misc.scala:38:36, :56:20] wire _r_T_27 = _r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_29 = _r_T_27 ? 3'h1 : _r_T_25; // @[Misc.scala:38:36, :56:20] wire _r_T_31 = _r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _r_T_32 = _r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_33 = _r_T_31 ? 3'h1 : _r_T_29; // @[Misc.scala:38:36, :56:20] wire _r_T_35 = _r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _r_T_36 = ~_r_T_35 & _r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_37 = _r_T_35 ? 3'h5 : _r_T_33; // @[Misc.scala:38:36, :56:20] wire _r_T_39 = _r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _r_T_40 = ~_r_T_39 & _r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_41 = _r_T_39 ? 3'h4 : _r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_42 = {1'h0, _r_T_39}; // @[Misc.scala:38:63, :56:20] wire _r_T_43 = _r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _r_T_44 = ~_r_T_43 & _r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_45 = _r_T_43 ? 3'h0 : _r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_46 = _r_T_43 ? 2'h1 : _r_T_42; // @[Misc.scala:38:63, :56:20] wire _r_T_47 = _r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _r_T_48 = _r_T_47 \| _r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_49 = _r_T_47 ? 3'h0 : _r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_50 = _r_T_47 ? 2'h1 : _r_T_46; // @[Misc.scala:38:63, :56:20] wire _r_T_51 = _r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _r_T_52 = ~_r_T_51 & _r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_53 = _r_T_51 ? 3'h5 : _r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_54 = _r_T_51 ? 2'h0 : _r_T_50; // @[Misc.scala:38:63, :56:20] wire _r_T_55 = _r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _r_T_56 = ~_r_T_55 & _r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_57 = _r_T_55 ? 3'h4 : _r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_58 = _r_T_55 ? 2'h1 : _r_T_54; // @[Misc.scala:38:63, :56:20] wire _r_T_59 = _r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _r_T_60 = ~_r_T_59 & _r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_61 = _r_T_59 ? 3'h3 : _r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_62 = _r_T_59 ? 2'h2 : _r_T_58; // @[Misc.scala:38:63, :56:20] wire _r_T_63 = _r_T_6 == 4'h3; // @[Misc.scala:56:20] wire r_1 = _r_T_63 \| _r_T_60; // @[Misc.scala:38:9, :56:20] assign shrink_param = _r_T_63 ? 3'h3 : _r_T_61; // @[Misc.scala:38:36, :56:20] assign io_wb_req_bits_param_0 = shrink_param; // @[Misc.scala:38:36] wire [1:0] r_3 = _r_T_63 ? 2'h2 : _r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] coh_on_clear_state = r_3; // @[Misc.scala:38:63] wire _GEN = req_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T_23; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T_23; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T; // @[Consts.scala:90:32] assign _r1_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T_23; // @[Consts.scala:90:32] assign _r1_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _needs_second_acq_T_27; // @[Consts.scala:90:32] assign _needs_second_acq_T_27 = _GEN; // @[Consts.scala:90:32] wire _GEN_0 = req_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_1; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_24; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_1; // @[Consts.scala:90:49] assign _r1_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_24; // @[Consts.scala:90:49] assign _r1_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _needs_second_acq_T_28; // @[Consts.scala:90:49] assign _needs_second_acq_T_28 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_2 = _grow_param_r_c_cat_T \| _grow_param_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_1 = req_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_3; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_26; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_3; // @[Consts.scala:90:66] assign _r1_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_26; // @[Consts.scala:90:66] assign _r1_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _needs_second_acq_T_30; // @[Consts.scala:90:66] assign _needs_second_acq_T_30 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_4 = _grow_param_r_c_cat_T_2 \| _grow_param_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_2 = req_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_5; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_28; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_5; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_28; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_5; // @[package.scala:16:47] assign _r1_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_28; // @[package.scala:16:47] assign _r1_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _needs_second_acq_T_32; // @[package.scala:16:47] assign _needs_second_acq_T_32 = _GEN_2; // @[package.scala:16:47] wire _GEN_3 = req_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_6; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_29; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_6; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_29; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_6; // @[package.scala:16:47] assign _r1_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_29; // @[package.scala:16:47] assign _r1_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _needs_second_acq_T_33; // @[package.scala:16:47] assign _needs_second_acq_T_33 = _GEN_3; // @[package.scala:16:47] wire _GEN_4 = req_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_7; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_30; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_7; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_30; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_7; // @[package.scala:16:47] assign _r1_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_30; // @[package.scala:16:47] assign _r1_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _needs_second_acq_T_34; // @[package.scala:16:47] assign _needs_second_acq_T_34 = _GEN_4; // @[package.scala:16:47] wire _GEN_5 = req_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_8; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_31; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_8; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_31; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_8; // @[package.scala:16:47] assign _r1_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_31; // @[package.scala:16:47] assign _r1_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _needs_second_acq_T_35; // @[package.scala:16:47] assign _needs_second_acq_T_35 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_9 = _grow_param_r_c_cat_T_5 \| _grow_param_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_10 = _grow_param_r_c_cat_T_9 \| _grow_param_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_11 = _grow_param_r_c_cat_T_10 \| _grow_param_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_6 = req_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_12; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_35; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_12; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_35; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_12; // @[package.scala:16:47] assign _r1_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_35; // @[package.scala:16:47] assign _r1_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _needs_second_acq_T_39; // @[package.scala:16:47] assign _needs_second_acq_T_39 = _GEN_6; // @[package.scala:16:47] wire _GEN_7 = req_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_13; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_36; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_13; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_36; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_13; // @[package.scala:16:47] assign _r1_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_36; // @[package.scala:16:47] assign _r1_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _needs_second_acq_T_40; // @[package.scala:16:47] assign _needs_second_acq_T_40 = _GEN_7; // @[package.scala:16:47] wire _GEN_8 = req_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_14; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_37; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_14; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_37; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_14; // @[package.scala:16:47] assign _r1_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_37; // @[package.scala:16:47] assign _r1_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _needs_second_acq_T_41; // @[package.scala:16:47] assign _needs_second_acq_T_41 = _GEN_8; // @[package.scala:16:47] wire _GEN_9 = req_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_15; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_38; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_15; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_38; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_15; // @[package.scala:16:47] assign _r1_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_38; // @[package.scala:16:47] assign _r1_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _needs_second_acq_T_42; // @[package.scala:16:47] assign _needs_second_acq_T_42 = _GEN_9; // @[package.scala:16:47] wire _GEN_10 = req_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_16; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_39; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_16; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_39; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_16; // @[package.scala:16:47] assign _r1_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_39; // @[package.scala:16:47] assign _r1_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _needs_second_acq_T_43; // @[package.scala:16:47] assign _needs_second_acq_T_43 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_17 = _grow_param_r_c_cat_T_12 \| _grow_param_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_18 = _grow_param_r_c_cat_T_17 \| _grow_param_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_19 = _grow_param_r_c_cat_T_18 \| _grow_param_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_20 = _grow_param_r_c_cat_T_19 \| _grow_param_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_21 = _grow_param_r_c_cat_T_11 \| _grow_param_r_c_cat_T_20; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_22 = _grow_param_r_c_cat_T_4 \| _grow_param_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _grow_param_r_c_cat_T_25 = _grow_param_r_c_cat_T_23 \| _grow_param_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _grow_param_r_c_cat_T_27 = _grow_param_r_c_cat_T_25 \| _grow_param_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _grow_param_r_c_cat_T_32 = _grow_param_r_c_cat_T_28 \| _grow_param_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_33 = _grow_param_r_c_cat_T_32 \| _grow_param_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_34 = _grow_param_r_c_cat_T_33 \| _grow_param_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_40 = _grow_param_r_c_cat_T_35 \| _grow_param_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_41 = _grow_param_r_c_cat_T_40 \| _grow_param_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_42 = _grow_param_r_c_cat_T_41 \| _grow_param_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_43 = _grow_param_r_c_cat_T_42 \| _grow_param_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_44 = _grow_param_r_c_cat_T_34 \| _grow_param_r_c_cat_T_43; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_45 = _grow_param_r_c_cat_T_27 \| _grow_param_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_11 = req_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_46; // @[Consts.scala:91:54] assign _grow_param_r_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _coh_on_grant_c_cat_T_46; // @[Consts.scala:91:54] assign _coh_on_grant_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _r1_c_cat_T_46; // @[Consts.scala:91:54] assign _r1_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _needs_second_acq_T_50; // @[Consts.scala:91:54] assign _needs_second_acq_T_50 = _GEN_11; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_47 = _grow_param_r_c_cat_T_45 \| _grow_param_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_12 = req_uop_mem_cmd == 5'h6; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_48; // @[Consts.scala:91:71] assign _grow_param_r_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:71] assign _coh_on_grant_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _r1_c_cat_T_48; // @[Consts.scala:91:71] assign _r1_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _needs_second_acq_T_52; // @[Consts.scala:91:71] assign _needs_second_acq_T_52 = _GEN_12; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_49 = _grow_param_r_c_cat_T_47 \| _grow_param_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] grow_param_r_c = {_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _grow_param_r_T = {grow_param_r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _grow_param_r_T_25 = _grow_param_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_27 = {1'h0, _grow_param_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_28 = _grow_param_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_30 = _grow_param_r_T_28 ? 2'h2 : _grow_param_r_T_27; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_31 = _grow_param_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_33 = _grow_param_r_T_31 ? 2'h1 : _grow_param_r_T_30; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_34 = _grow_param_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_36 = _grow_param_r_T_34 ? 2'h2 : _grow_param_r_T_33; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_37 = _grow_param_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_39 = _grow_param_r_T_37 ? 2'h0 : _grow_param_r_T_36; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_40 = _grow_param_r_T == 4'hE; // @[Misc.scala:49:20] wire _grow_param_r_T_41 = _grow_param_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_42 = _grow_param_r_T_40 ? 2'h3 : _grow_param_r_T_39; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_43 = &_grow_param_r_T; // @[Misc.scala:49:20] wire _grow_param_r_T_44 = _grow_param_r_T_43 \| _grow_param_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_45 = _grow_param_r_T_43 ? 2'h3 : _grow_param_r_T_42; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_46 = _grow_param_r_T == 4'h6; // @[Misc.scala:49:20] wire _grow_param_r_T_47 = _grow_param_r_T_46 \| _grow_param_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_48 = _grow_param_r_T_46 ? 2'h2 : _grow_param_r_T_45; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_49 = _grow_param_r_T == 4'h7; // @[Misc.scala:49:20] wire _grow_param_r_T_50 = _grow_param_r_T_49 \| _grow_param_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_51 = _grow_param_r_T_49 ? 2'h3 : _grow_param_r_T_48; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_52 = _grow_param_r_T == 4'h1; // @[Misc.scala:49:20] wire _grow_param_r_T_53 = _grow_param_r_T_52 \| _grow_param_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_54 = _grow_param_r_T_52 ? 2'h1 : _grow_param_r_T_51; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_55 = _grow_param_r_T == 4'h2; // @[Misc.scala:49:20] wire _grow_param_r_T_56 = _grow_param_r_T_55 \| _grow_param_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_57 = _grow_param_r_T_55 ? 2'h2 : _grow_param_r_T_54; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_58 = _grow_param_r_T == 4'h3; // @[Misc.scala:49:20] wire grow_param_r_1 = _grow_param_r_T_58 \| _grow_param_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] grow_param = _grow_param_r_T_58 ? 2'h3 : _grow_param_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] grow_param_meta_state = grow_param; // @[Misc.scala:35:36] wire _coh_on_grant_c_cat_T_2 = _coh_on_grant_c_cat_T \| _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_4 = _coh_on_grant_c_cat_T_2 \| _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_9 = _coh_on_grant_c_cat_T_5 \| _coh_on_grant_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_10 = _coh_on_grant_c_cat_T_9 \| _coh_on_grant_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_11 = _coh_on_grant_c_cat_T_10 \| _coh_on_grant_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_17 = _coh_on_grant_c_cat_T_12 \| _coh_on_grant_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_18 = _coh_on_grant_c_cat_T_17 \| _coh_on_grant_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_19 = _coh_on_grant_c_cat_T_18 \| _coh_on_grant_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_20 = _coh_on_grant_c_cat_T_19 \| _coh_on_grant_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_21 = _coh_on_grant_c_cat_T_11 \| _coh_on_grant_c_cat_T_20; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_22 = _coh_on_grant_c_cat_T_4 \| _coh_on_grant_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_25 = _coh_on_grant_c_cat_T_23 \| _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_27 = _coh_on_grant_c_cat_T_25 \| _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_32 = _coh_on_grant_c_cat_T_28 \| _coh_on_grant_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_33 = _coh_on_grant_c_cat_T_32 \| _coh_on_grant_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_34 = _coh_on_grant_c_cat_T_33 \| _coh_on_grant_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_40 = _coh_on_grant_c_cat_T_35 \| _coh_on_grant_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_41 = _coh_on_grant_c_cat_T_40 \| _coh_on_grant_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_42 = _coh_on_grant_c_cat_T_41 \| _coh_on_grant_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_43 = _coh_on_grant_c_cat_T_42 \| _coh_on_grant_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_44 = _coh_on_grant_c_cat_T_34 \| _coh_on_grant_c_cat_T_43; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_45 = _coh_on_grant_c_cat_T_27 \| _coh_on_grant_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_47 = _coh_on_grant_c_cat_T_45 \| _coh_on_grant_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _coh_on_grant_c_cat_T_49 = _coh_on_grant_c_cat_T_47 \| _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] coh_on_grant_c = {_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _coh_on_grant_T = {coh_on_grant_c, io_mem_grant_bits_param_0}; // @[Metadata.scala:29:18, :84:18] wire _coh_on_grant_T_9 = _coh_on_grant_T == 4'h1; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_10 = {1'h0, _coh_on_grant_T_9}; // @[Metadata.scala:84:38] wire _coh_on_grant_T_11 = _coh_on_grant_T == 4'h0; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_12 = _coh_on_grant_T_11 ? 2'h2 : _coh_on_grant_T_10; // @[Metadata.scala:84:38] wire _coh_on_grant_T_13 = _coh_on_grant_T == 4'h4; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_14 = _coh_on_grant_T_13 ? 2'h2 : _coh_on_grant_T_12; // @[Metadata.scala:84:38] wire _coh_on_grant_T_15 = _coh_on_grant_T == 4'hC; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_16 = _coh_on_grant_T_15 ? 2'h3 : _coh_on_grant_T_14; // @[Metadata.scala:84:38] assign coh_on_grant_state = _coh_on_grant_T_16; // @[Metadata.scala:84:38, :160:20] assign io_commit_coh_state_0 = coh_on_grant_state; // @[Metadata.scala:160:20] wire _r1_c_cat_T_2 = _r1_c_cat_T \| _r1_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_4 = _r1_c_cat_T_2 \| _r1_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_9 = _r1_c_cat_T_5 \| _r1_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_10 = _r1_c_cat_T_9 \| _r1_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_11 = _r1_c_cat_T_10 \| _r1_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_17 = _r1_c_cat_T_12 \| _r1_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_18 = _r1_c_cat_T_17 \| _r1_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_19 = _r1_c_cat_T_18 \| _r1_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_20 = _r1_c_cat_T_19 \| _r1_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_21 = _r1_c_cat_T_11 \| _r1_c_cat_T_20; // @[package.scala:81:59] wire _r1_c_cat_T_22 = _r1_c_cat_T_4 \| _r1_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_25 = _r1_c_cat_T_23 \| _r1_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_27 = _r1_c_cat_T_25 \| _r1_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_32 = _r1_c_cat_T_28 \| _r1_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_33 = _r1_c_cat_T_32 \| _r1_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_34 = _r1_c_cat_T_33 \| _r1_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_40 = _r1_c_cat_T_35 \| _r1_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_41 = _r1_c_cat_T_40 \| _r1_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_42 = _r1_c_cat_T_41 \| _r1_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_43 = _r1_c_cat_T_42 \| _r1_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_44 = _r1_c_cat_T_34 \| _r1_c_cat_T_43; // @[package.scala:81:59] wire _r1_c_cat_T_45 = _r1_c_cat_T_27 \| _r1_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_47 = _r1_c_cat_T_45 \| _r1_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r1_c_cat_T_49 = _r1_c_cat_T_47 \| _r1_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r1_c = {_r1_c_cat_T_22, _r1_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r1_T = {r1_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r1_T_25 = _r1_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r1_T_27 = {1'h0, _r1_T_25}; // @[Misc.scala:35:36, :49:20] wire _r1_T_28 = _r1_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r1_T_30 = _r1_T_28 ? 2'h2 : _r1_T_27; // @[Misc.scala:35:36, :49:20] wire _r1_T_31 = _r1_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r1_T_33 = _r1_T_31 ? 2'h1 : _r1_T_30; // @[Misc.scala:35:36, :49:20] wire _r1_T_34 = _r1_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r1_T_36 = _r1_T_34 ? 2'h2 : _r1_T_33; // @[Misc.scala:35:36, :49:20] wire _r1_T_37 = _r1_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r1_T_39 = _r1_T_37 ? 2'h0 : _r1_T_36; // @[Misc.scala:35:36, :49:20] wire _r1_T_40 = _r1_T == 4'hE; // @[Misc.scala:49:20] wire _r1_T_41 = _r1_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_42 = _r1_T_40 ? 2'h3 : _r1_T_39; // @[Misc.scala:35:36, :49:20] wire _r1_T_43 = &_r1_T; // @[Misc.scala:49:20] wire _r1_T_44 = _r1_T_43 \| _r1_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_45 = _r1_T_43 ? 2'h3 : _r1_T_42; // @[Misc.scala:35:36, :49:20] wire _r1_T_46 = _r1_T == 4'h6; // @[Misc.scala:49:20] wire _r1_T_47 = _r1_T_46 \| _r1_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_48 = _r1_T_46 ? 2'h2 : _r1_T_45; // @[Misc.scala:35:36, :49:20] wire _r1_T_49 = _r1_T == 4'h7; // @[Misc.scala:49:20] wire _r1_T_50 = _r1_T_49 \| _r1_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_51 = _r1_T_49 ? 2'h3 : _r1_T_48; // @[Misc.scala:35:36, :49:20] wire _r1_T_52 = _r1_T == 4'h1; // @[Misc.scala:49:20] wire _r1_T_53 = _r1_T_52 \| _r1_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_54 = _r1_T_52 ? 2'h1 : _r1_T_51; // @[Misc.scala:35:36, :49:20] wire _r1_T_55 = _r1_T == 4'h2; // @[Misc.scala:49:20] wire _r1_T_56 = _r1_T_55 \| _r1_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_57 = _r1_T_55 ? 2'h2 : _r1_T_54; // @[Misc.scala:35:36, :49:20] wire _r1_T_58 = _r1_T == 4'h3; // @[Misc.scala:49:20] wire r1_1 = _r1_T_58 \| _r1_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r1_2 = _r1_T_58 ? 2'h3 : _r1_T_57; // @[Misc.scala:35:36, :49:20] wire _GEN_13 = io_req_uop_mem_cmd_0 == 5'h1; // @[Consts.scala:90:32] wire _r2_c_cat_T; // @[Consts.scala:90:32] assign _r2_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _r2_c_cat_T_23; // @[Consts.scala:90:32] assign _r2_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _needs_second_acq_T; // @[Consts.scala:90:32] assign _needs_second_acq_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T; // @[Consts.scala:90:32] assign _dirties_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T_23; // @[Consts.scala:90:32] assign _dirties_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T; // @[Consts.scala:90:32] assign _state_r_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_23; // @[Consts.scala:90:32] assign _state_r_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _state_T_3; // @[Consts.scala:90:32] assign _state_T_3 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_50; // @[Consts.scala:90:32] assign _r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_73; // @[Consts.scala:90:32] assign _r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_50; // @[Consts.scala:90:32] assign _state_r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_73; // @[Consts.scala:90:32] assign _state_r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32] wire _state_T_37; // @[Consts.scala:90:32] assign _state_T_37 = _GEN_13; // @[Consts.scala:90:32] wire _GEN_14 = io_req_uop_mem_cmd_0 == 5'h11; // @[Consts.scala:90:49] wire _r2_c_cat_T_1; // @[Consts.scala:90:49] assign _r2_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_24; // @[Consts.scala:90:49] assign _r2_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _needs_second_acq_T_1; // @[Consts.scala:90:49] assign _needs_second_acq_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_1; // @[Consts.scala:90:49] assign _dirties_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_24; // @[Consts.scala:90:49] assign _dirties_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_1; // @[Consts.scala:90:49] assign _state_r_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_24; // @[Consts.scala:90:49] assign _state_r_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _state_T_4; // @[Consts.scala:90:49] assign _state_T_4 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_51; // @[Consts.scala:90:49] assign _r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_74; // @[Consts.scala:90:49] assign _r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_51; // @[Consts.scala:90:49] assign _state_r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_74; // @[Consts.scala:90:49] assign _state_r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49] wire _state_T_38; // @[Consts.scala:90:49] assign _state_T_38 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_2 = _r2_c_cat_T \| _r2_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_15 = io_req_uop_mem_cmd_0 == 5'h7; // @[Consts.scala:90:66] wire _r2_c_cat_T_3; // @[Consts.scala:90:66] assign _r2_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_26; // @[Consts.scala:90:66] assign _r2_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _needs_second_acq_T_3; // @[Consts.scala:90:66] assign _needs_second_acq_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_3; // @[Consts.scala:90:66] assign _dirties_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_26; // @[Consts.scala:90:66] assign _dirties_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_3; // @[Consts.scala:90:66] assign _state_r_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_26; // @[Consts.scala:90:66] assign _state_r_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _state_T_6; // @[Consts.scala:90:66] assign _state_T_6 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_53; // @[Consts.scala:90:66] assign _r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_76; // @[Consts.scala:90:66] assign _r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_53; // @[Consts.scala:90:66] assign _state_r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_76; // @[Consts.scala:90:66] assign _state_r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66] wire _state_T_40; // @[Consts.scala:90:66] assign _state_T_40 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_4 = _r2_c_cat_T_2 \| _r2_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_16 = io_req_uop_mem_cmd_0 == 5'h4; // @[package.scala:16:47] wire _r2_c_cat_T_5; // @[package.scala:16:47] assign _r2_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _r2_c_cat_T_28; // @[package.scala:16:47] assign _r2_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _needs_second_acq_T_5; // @[package.scala:16:47] assign _needs_second_acq_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_5; // @[package.scala:16:47] assign _dirties_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_28; // @[package.scala:16:47] assign _dirties_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_5; // @[package.scala:16:47] assign _state_r_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_28; // @[package.scala:16:47] assign _state_r_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _state_T_8; // @[package.scala:16:47] assign _state_T_8 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_55; // @[package.scala:16:47] assign _r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_78; // @[package.scala:16:47] assign _r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_55; // @[package.scala:16:47] assign _state_r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_78; // @[package.scala:16:47] assign _state_r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47] wire _state_T_42; // @[package.scala:16:47] assign _state_T_42 = _GEN_16; // @[package.scala:16:47] wire _GEN_17 = io_req_uop_mem_cmd_0 == 5'h9; // @[package.scala:16:47] wire _r2_c_cat_T_6; // @[package.scala:16:47] assign _r2_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _r2_c_cat_T_29; // @[package.scala:16:47] assign _r2_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _needs_second_acq_T_6; // @[package.scala:16:47] assign _needs_second_acq_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_6; // @[package.scala:16:47] assign _dirties_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_29; // @[package.scala:16:47] assign _dirties_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_6; // @[package.scala:16:47] assign _state_r_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_29; // @[package.scala:16:47] assign _state_r_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _state_T_9; // @[package.scala:16:47] assign _state_T_9 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_56; // @[package.scala:16:47] assign _r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_79; // @[package.scala:16:47] assign _r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_56; // @[package.scala:16:47] assign _state_r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_79; // @[package.scala:16:47] assign _state_r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47] wire _state_T_43; // @[package.scala:16:47] assign _state_T_43 = _GEN_17; // @[package.scala:16:47] wire _GEN_18 = io_req_uop_mem_cmd_0 == 5'hA; // @[package.scala:16:47] wire _r2_c_cat_T_7; // @[package.scala:16:47] assign _r2_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _r2_c_cat_T_30; // @[package.scala:16:47] assign _r2_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _needs_second_acq_T_7; // @[package.scala:16:47] assign _needs_second_acq_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_7; // @[package.scala:16:47] assign _dirties_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_30; // @[package.scala:16:47] assign _dirties_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_7; // @[package.scala:16:47] assign _state_r_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_30; // @[package.scala:16:47] assign _state_r_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _state_T_10; // @[package.scala:16:47] assign _state_T_10 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_57; // @[package.scala:16:47] assign _r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_80; // @[package.scala:16:47] assign _r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_57; // @[package.scala:16:47] assign _state_r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_80; // @[package.scala:16:47] assign _state_r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47] wire _state_T_44; // @[package.scala:16:47] assign _state_T_44 = _GEN_18; // @[package.scala:16:47] wire _GEN_19 = io_req_uop_mem_cmd_0 == 5'hB; // @[package.scala:16:47] wire _r2_c_cat_T_8; // @[package.scala:16:47] assign _r2_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_31; // @[package.scala:16:47] assign _r2_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _needs_second_acq_T_8; // @[package.scala:16:47] assign _needs_second_acq_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_8; // @[package.scala:16:47] assign _dirties_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_31; // @[package.scala:16:47] assign _dirties_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_8; // @[package.scala:16:47] assign _state_r_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_31; // @[package.scala:16:47] assign _state_r_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _state_T_11; // @[package.scala:16:47] assign _state_T_11 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_58; // @[package.scala:16:47] assign _r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_81; // @[package.scala:16:47] assign _r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_58; // @[package.scala:16:47] assign _state_r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_81; // @[package.scala:16:47] assign _state_r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47] wire _state_T_45; // @[package.scala:16:47] assign _state_T_45 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_9 = _r2_c_cat_T_5 \| _r2_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_10 = _r2_c_cat_T_9 \| _r2_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_11 = _r2_c_cat_T_10 \| _r2_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_20 = io_req_uop_mem_cmd_0 == 5'h8; // @[package.scala:16:47] wire _r2_c_cat_T_12; // @[package.scala:16:47] assign _r2_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _r2_c_cat_T_35; // @[package.scala:16:47] assign _r2_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _needs_second_acq_T_12; // @[package.scala:16:47] assign _needs_second_acq_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_12; // @[package.scala:16:47] assign _dirties_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_35; // @[package.scala:16:47] assign _dirties_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_12; // @[package.scala:16:47] assign _state_r_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_35; // @[package.scala:16:47] assign _state_r_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _state_T_15; // @[package.scala:16:47] assign _state_T_15 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_62; // @[package.scala:16:47] assign _r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_85; // @[package.scala:16:47] assign _r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_62; // @[package.scala:16:47] assign _state_r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_85; // @[package.scala:16:47] assign _state_r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47] wire _state_T_49; // @[package.scala:16:47] assign _state_T_49 = _GEN_20; // @[package.scala:16:47] wire _GEN_21 = io_req_uop_mem_cmd_0 == 5'hC; // @[package.scala:16:47] wire _r2_c_cat_T_13; // @[package.scala:16:47] assign _r2_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _r2_c_cat_T_36; // @[package.scala:16:47] assign _r2_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _needs_second_acq_T_13; // @[package.scala:16:47] assign _needs_second_acq_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_13; // @[package.scala:16:47] assign _dirties_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_36; // @[package.scala:16:47] assign _dirties_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_13; // @[package.scala:16:47] assign _state_r_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_36; // @[package.scala:16:47] assign _state_r_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _state_T_16; // @[package.scala:16:47] assign _state_T_16 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_63; // @[package.scala:16:47] assign _r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_86; // @[package.scala:16:47] assign _r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_63; // @[package.scala:16:47] assign _state_r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_86; // @[package.scala:16:47] assign _state_r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47] wire _state_T_50; // @[package.scala:16:47] assign _state_T_50 = _GEN_21; // @[package.scala:16:47] wire _GEN_22 = io_req_uop_mem_cmd_0 == 5'hD; // @[package.scala:16:47] wire _r2_c_cat_T_14; // @[package.scala:16:47] assign _r2_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _r2_c_cat_T_37; // @[package.scala:16:47] assign _r2_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _needs_second_acq_T_14; // @[package.scala:16:47] assign _needs_second_acq_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_14; // @[package.scala:16:47] assign _dirties_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_37; // @[package.scala:16:47] assign _dirties_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_14; // @[package.scala:16:47] assign _state_r_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_37; // @[package.scala:16:47] assign _state_r_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _state_T_17; // @[package.scala:16:47] assign _state_T_17 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_64; // @[package.scala:16:47] assign _r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_87; // @[package.scala:16:47] assign _r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_64; // @[package.scala:16:47] assign _state_r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_87; // @[package.scala:16:47] assign _state_r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47] wire _state_T_51; // @[package.scala:16:47] assign _state_T_51 = _GEN_22; // @[package.scala:16:47] wire _GEN_23 = io_req_uop_mem_cmd_0 == 5'hE; // @[package.scala:16:47] wire _r2_c_cat_T_15; // @[package.scala:16:47] assign _r2_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _r2_c_cat_T_38; // @[package.scala:16:47] assign _r2_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _needs_second_acq_T_15; // @[package.scala:16:47] assign _needs_second_acq_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_15; // @[package.scala:16:47] assign _dirties_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_38; // @[package.scala:16:47] assign _dirties_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_15; // @[package.scala:16:47] assign _state_r_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_38; // @[package.scala:16:47] assign _state_r_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _state_T_18; // @[package.scala:16:47] assign _state_T_18 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_65; // @[package.scala:16:47] assign _r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_88; // @[package.scala:16:47] assign _r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_65; // @[package.scala:16:47] assign _state_r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_88; // @[package.scala:16:47] assign _state_r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47] wire _state_T_52; // @[package.scala:16:47] assign _state_T_52 = _GEN_23; // @[package.scala:16:47] wire _GEN_24 = io_req_uop_mem_cmd_0 == 5'hF; // @[package.scala:16:47] wire _r2_c_cat_T_16; // @[package.scala:16:47] assign _r2_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_39; // @[package.scala:16:47] assign _r2_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _needs_second_acq_T_16; // @[package.scala:16:47] assign _needs_second_acq_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_16; // @[package.scala:16:47] assign _dirties_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_39; // @[package.scala:16:47] assign _dirties_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_16; // @[package.scala:16:47] assign _state_r_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_39; // @[package.scala:16:47] assign _state_r_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _state_T_19; // @[package.scala:16:47] assign _state_T_19 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_66; // @[package.scala:16:47] assign _r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_89; // @[package.scala:16:47] assign _r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_66; // @[package.scala:16:47] assign _state_r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_89; // @[package.scala:16:47] assign _state_r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47] wire _state_T_53; // @[package.scala:16:47] assign _state_T_53 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_17 = _r2_c_cat_T_12 \| _r2_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_18 = _r2_c_cat_T_17 \| _r2_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_19 = _r2_c_cat_T_18 \| _r2_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_20 = _r2_c_cat_T_19 \| _r2_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_21 = _r2_c_cat_T_11 \| _r2_c_cat_T_20; // @[package.scala:81:59] wire _r2_c_cat_T_22 = _r2_c_cat_T_4 \| _r2_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r2_c_cat_T_25 = _r2_c_cat_T_23 \| _r2_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r2_c_cat_T_27 = _r2_c_cat_T_25 \| _r2_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r2_c_cat_T_32 = _r2_c_cat_T_28 \| _r2_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_33 = _r2_c_cat_T_32 \| _r2_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_34 = _r2_c_cat_T_33 \| _r2_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_40 = _r2_c_cat_T_35 \| _r2_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_41 = _r2_c_cat_T_40 \| _r2_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_42 = _r2_c_cat_T_41 \| _r2_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_43 = _r2_c_cat_T_42 \| _r2_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_44 = _r2_c_cat_T_34 \| _r2_c_cat_T_43; // @[package.scala:81:59] wire _r2_c_cat_T_45 = _r2_c_cat_T_27 \| _r2_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_25 = io_req_uop_mem_cmd_0 == 5'h3; // @[Consts.scala:91:54] wire _r2_c_cat_T_46; // @[Consts.scala:91:54] assign _r2_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _needs_second_acq_T_23; // @[Consts.scala:91:54] assign _needs_second_acq_T_23 = _GEN_25; // @[Consts.scala:91:54] wire _dirties_cat_T_46; // @[Consts.scala:91:54] assign _dirties_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _rpq_io_enq_valid_T_4; // @[Consts.scala:88:52] assign _rpq_io_enq_valid_T_4 = _GEN_25; // @[Consts.scala:88:52, :91:54] wire _state_r_c_cat_T_46; // @[Consts.scala:91:54] assign _state_r_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _r_c_cat_T_96; // @[Consts.scala:91:54] assign _r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54] wire _state_r_c_cat_T_96; // @[Consts.scala:91:54] assign _state_r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54] wire _r2_c_cat_T_47 = _r2_c_cat_T_45 \| _r2_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_26 = io_req_uop_mem_cmd_0 == 5'h6; // @[Consts.scala:91:71] wire _r2_c_cat_T_48; // @[Consts.scala:91:71] assign _r2_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _needs_second_acq_T_25; // @[Consts.scala:91:71] assign _needs_second_acq_T_25 = _GEN_26; // @[Consts.scala:91:71] wire _dirties_cat_T_48; // @[Consts.scala:91:71] assign _dirties_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _state_r_c_cat_T_48; // @[Consts.scala:91:71] assign _state_r_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _r_c_cat_T_98; // @[Consts.scala:91:71] assign _r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71] wire _state_r_c_cat_T_98; // @[Consts.scala:91:71] assign _state_r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71] wire _r2_c_cat_T_49 = _r2_c_cat_T_47 \| _r2_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r2_c = {_r2_c_cat_T_22, _r2_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r2_T = {r2_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r2_T_25 = _r2_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r2_T_27 = {1'h0, _r2_T_25}; // @[Misc.scala:35:36, :49:20] wire _r2_T_28 = _r2_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r2_T_30 = _r2_T_28 ? 2'h2 : _r2_T_27; // @[Misc.scala:35:36, :49:20] wire _r2_T_31 = _r2_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r2_T_33 = _r2_T_31 ? 2'h1 : _r2_T_30; // @[Misc.scala:35:36, :49:20] wire _r2_T_34 = _r2_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r2_T_36 = _r2_T_34 ? 2'h2 : _r2_T_33; // @[Misc.scala:35:36, :49:20] wire _r2_T_37 = _r2_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r2_T_39 = _r2_T_37 ? 2'h0 : _r2_T_36; // @[Misc.scala:35:36, :49:20] wire _r2_T_40 = _r2_T == 4'hE; // @[Misc.scala:49:20] wire _r2_T_41 = _r2_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_42 = _r2_T_40 ? 2'h3 : _r2_T_39; // @[Misc.scala:35:36, :49:20] wire _r2_T_43 = &_r2_T; // @[Misc.scala:49:20] wire _r2_T_44 = _r2_T_43 \| _r2_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_45 = _r2_T_43 ? 2'h3 : _r2_T_42; // @[Misc.scala:35:36, :49:20] wire _r2_T_46 = _r2_T == 4'h6; // @[Misc.scala:49:20] wire _r2_T_47 = _r2_T_46 \| _r2_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_48 = _r2_T_46 ? 2'h2 : _r2_T_45; // @[Misc.scala:35:36, :49:20] wire _r2_T_49 = _r2_T == 4'h7; // @[Misc.scala:49:20] wire _r2_T_50 = _r2_T_49 \| _r2_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_51 = _r2_T_49 ? 2'h3 : _r2_T_48; // @[Misc.scala:35:36, :49:20] wire _r2_T_52 = _r2_T == 4'h1; // @[Misc.scala:49:20] wire _r2_T_53 = _r2_T_52 \| _r2_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_54 = _r2_T_52 ? 2'h1 : _r2_T_51; // @[Misc.scala:35:36, :49:20] wire _r2_T_55 = _r2_T == 4'h2; // @[Misc.scala:49:20] wire _r2_T_56 = _r2_T_55 \| _r2_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_57 = _r2_T_55 ? 2'h2 : _r2_T_54; // @[Misc.scala:35:36, :49:20] wire _r2_T_58 = _r2_T == 4'h3; // @[Misc.scala:49:20] wire r2_1 = _r2_T_58 \| _r2_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r2_2 = _r2_T_58 ? 2'h3 : _r2_T_57; // @[Misc.scala:35:36, :49:20] wire _needs_second_acq_T_2 = _needs_second_acq_T \| _needs_second_acq_T_1; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_4 = _needs_second_acq_T_2 \| _needs_second_acq_T_3; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_9 = _needs_second_acq_T_5 \| _needs_second_acq_T_6; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_10 = _needs_second_acq_T_9 \| _needs_second_acq_T_7; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_11 = _needs_second_acq_T_10 \| _needs_second_acq_T_8; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_17 = _needs_second_acq_T_12 \| _needs_second_acq_T_13; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_18 = _needs_second_acq_T_17 \| _needs_second_acq_T_14; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_19 = _needs_second_acq_T_18 \| _needs_second_acq_T_15; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_20 = _needs_second_acq_T_19 \| _needs_second_acq_T_16; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_21 = _needs_second_acq_T_11 \| _needs_second_acq_T_20; // @[package.scala:81:59] wire _needs_second_acq_T_22 = _needs_second_acq_T_4 \| _needs_second_acq_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_24 = _needs_second_acq_T_22 \| _needs_second_acq_T_23; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_26 = _needs_second_acq_T_24 \| _needs_second_acq_T_25; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_29 = _needs_second_acq_T_27 \| _needs_second_acq_T_28; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_31 = _needs_second_acq_T_29 \| _needs_second_acq_T_30; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_36 = _needs_second_acq_T_32 \| _needs_second_acq_T_33; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_37 = _needs_second_acq_T_36 \| _needs_second_acq_T_34; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_38 = _needs_second_acq_T_37 \| _needs_second_acq_T_35; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_44 = _needs_second_acq_T_39 \| _needs_second_acq_T_40; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_45 = _needs_second_acq_T_44 \| _needs_second_acq_T_41; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_46 = _needs_second_acq_T_45 \| _needs_second_acq_T_42; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_47 = _needs_second_acq_T_46 \| _needs_second_acq_T_43; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_48 = _needs_second_acq_T_38 \| _needs_second_acq_T_47; // @[package.scala:81:59] wire _needs_second_acq_T_49 = _needs_second_acq_T_31 \| _needs_second_acq_T_48; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_51 = _needs_second_acq_T_49 \| _needs_second_acq_T_50; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_53 = _needs_second_acq_T_51 \| _needs_second_acq_T_52; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_54 = ~_needs_second_acq_T_53; // @[Metadata.scala:104:57] wire cmd_requires_second_acquire = _needs_second_acq_T_26 & _needs_second_acq_T_54; // @[Metadata.scala:104:{54,57}] wire is_hit_again = r1_1 & r2_1; // @[Misc.scala:35:9] wire _dirties_cat_T_2 = _dirties_cat_T \| _dirties_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_4 = _dirties_cat_T_2 \| _dirties_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_9 = _dirties_cat_T_5 \| _dirties_cat_T_6; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_10 = _dirties_cat_T_9 \| _dirties_cat_T_7; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_11 = _dirties_cat_T_10 \| _dirties_cat_T_8; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_17 = _dirties_cat_T_12 \| _dirties_cat_T_13; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_18 = _dirties_cat_T_17 \| _dirties_cat_T_14; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_19 = _dirties_cat_T_18 \| _dirties_cat_T_15; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_20 = _dirties_cat_T_19 \| _dirties_cat_T_16; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_21 = _dirties_cat_T_11 \| _dirties_cat_T_20; // @[package.scala:81:59] wire _dirties_cat_T_22 = _dirties_cat_T_4 \| _dirties_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_25 = _dirties_cat_T_23 \| _dirties_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_27 = _dirties_cat_T_25 \| _dirties_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_32 = _dirties_cat_T_28 \| _dirties_cat_T_29; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_33 = _dirties_cat_T_32 \| _dirties_cat_T_30; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_34 = _dirties_cat_T_33 \| _dirties_cat_T_31; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_40 = _dirties_cat_T_35 \| _dirties_cat_T_36; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_41 = _dirties_cat_T_40 \| _dirties_cat_T_37; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_42 = _dirties_cat_T_41 \| _dirties_cat_T_38; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_43 = _dirties_cat_T_42 \| _dirties_cat_T_39; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_44 = _dirties_cat_T_34 \| _dirties_cat_T_43; // @[package.scala:81:59] wire _dirties_cat_T_45 = _dirties_cat_T_27 \| _dirties_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_47 = _dirties_cat_T_45 \| _dirties_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _dirties_cat_T_49 = _dirties_cat_T_47 \| _dirties_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] dirties_cat = {_dirties_cat_T_22, _dirties_cat_T_49}; // @[Metadata.scala:29:18] wire dirties = &dirties_cat; // @[Metadata.scala:29:18, :106:42] wire [1:0] biggest_grow_param = dirties ? r2_2 : r1_2; // @[Misc.scala:35:36] wire [1:0] dirtier_coh_state = biggest_grow_param; // @[Metadata.scala:107:33, :160:20] wire [4:0] dirtier_cmd = dirties ? io_req_uop_mem_cmd_0 : req_uop_mem_cmd; // @[Metadata.scala:106:42, :109:27] wire _T_16 = io_mem_grant_ready_0 & io_mem_grant_valid_0; // @[Decoupled.scala:51:35] wire [26:0] _r_beats1_decode_T = 27'hFFF << io_mem_grant_bits_size_0; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire r_beats1_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire grant_had_data_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] r_counter; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28] wire r_1_1 = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire r_2 = _r_last_T \| _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire refill_done = r_2 & _T_16; // @[Decoupled.scala:51:35] wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T = r_1_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] refill_address_inc = {r_4, 3'h0}; // @[Edges.scala:234:25, :269:29] wire _sec_rdy_T = ~cmd_requires_second_acquire; // @[Metadata.scala:104:54] wire _sec_rdy_T_1 = ~io_req_is_probe_0; // @[mshrs.scala:36:7, :125:50] wire _sec_rdy_T_2 = _sec_rdy_T & _sec_rdy_T_1; // @[mshrs.scala:125:{18,47,50}] wire _sec_rdy_T_3 = ~(\|state); // @[package.scala:16:47] wire _sec_rdy_T_4 = state == 5'hD; // @[package.scala:16:47] wire _sec_rdy_T_5 = state == 5'hE; // @[package.scala:16:47] wire _sec_rdy_T_6 = state == 5'hF; // @[package.scala:16:47] wire _sec_rdy_T_7 = _sec_rdy_T_3 \| _sec_rdy_T_4; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_8 = _sec_rdy_T_7 \| _sec_rdy_T_5; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_9 = _sec_rdy_T_8 \| _sec_rdy_T_6; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_10 = ~_sec_rdy_T_9; // @[package.scala:81:59] wire sec_rdy = _sec_rdy_T_2 & _sec_rdy_T_10; // @[mshrs.scala:125:{47,67}, :126:18] wire _rpq_io_enq_valid_T = io_req_pri_val_0 & io_req_pri_rdy_0; // @[mshrs.scala:36:7, :133:40] wire _rpq_io_enq_valid_T_1 = io_req_sec_val_0 & io_req_sec_rdy_0; // @[mshrs.scala:36:7, :133:78] wire _rpq_io_enq_valid_T_2 = _rpq_io_enq_valid_T \| _rpq_io_enq_valid_T_1; // @[mshrs.scala:133:{40,59,78}] wire _rpq_io_enq_valid_T_3 = io_req_uop_mem_cmd_0 == 5'h2; // @[Consts.scala:88:35] wire _rpq_io_enq_valid_T_5 = _rpq_io_enq_valid_T_3 \| _rpq_io_enq_valid_T_4; // @[Consts.scala:88:{35,45,52}] wire _rpq_io_enq_valid_T_6 = ~_rpq_io_enq_valid_T_5; // @[Consts.scala:88:45] wire _rpq_io_enq_valid_T_7 = _rpq_io_enq_valid_T_2 & _rpq_io_enq_valid_T_6; // @[mshrs.scala:133:{59,98,101}] reg grantack_valid; // @[mshrs.scala:138:21] reg [2:0] grantack_bits_sink; // @[mshrs.scala:138:21] assign io_mem_finish_bits_sink_0 = grantack_bits_sink; // @[mshrs.scala:36:7, :138:21] reg [2:0] refill_ctr; // @[mshrs.scala:139:24] reg commit_line; // @[mshrs.scala:140:24] reg grant_had_data; // @[mshrs.scala:141:27] reg finish_to_prefetch; // @[mshrs.scala:142:31] reg [1:0] meta_hazard; // @[mshrs.scala:145:28] wire [2:0] _meta_hazard_T = {1'h0, meta_hazard} + 3'h1; // @[mshrs.scala:145:28, :146:59] wire [1:0] _meta_hazard_T_1 = _meta_hazard_T[1:0]; // @[mshrs.scala:146:59] wire _io_probe_rdy_T = meta_hazard == 2'h0; // @[mshrs.scala:145:28, :148:34] wire _io_probe_rdy_T_1 = ~(\|state); // @[package.scala:16:47] wire _io_probe_rdy_T_2 = state == 5'h1; // @[package.scala:16:47] wire _io_probe_rdy_T_3 = state == 5'h2; // @[package.scala:16:47] wire _io_probe_rdy_T_4 = state == 5'h3; // @[package.scala:16:47] wire _io_probe_rdy_T_5 = _io_probe_rdy_T_1 \| _io_probe_rdy_T_2; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_6 = _io_probe_rdy_T_5 \| _io_probe_rdy_T_3; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_7 = _io_probe_rdy_T_6 \| _io_probe_rdy_T_4; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_8 = state == 5'h4; // @[mshrs.scala:107:22, :148:129] wire _io_probe_rdy_T_9 = _io_probe_rdy_T_8 & grantack_valid; // @[mshrs.scala:138:21, :148:{129,145}] wire _io_probe_rdy_T_10 = _io_probe_rdy_T_7 \| _io_probe_rdy_T_9; // @[package.scala:81:59] assign _io_probe_rdy_T_11 = _io_probe_rdy_T & _io_probe_rdy_T_10; // @[mshrs.scala:148:{34,42,119}] assign io_probe_rdy_0 = _io_probe_rdy_T_11; // @[mshrs.scala:36:7, :148:42] assign _io_idx_valid_T = \|state; // @[package.scala:16:47] assign io_idx_valid_0 = _io_idx_valid_T; // @[mshrs.scala:36:7, :149:25] assign _io_tag_valid_T = \|state; // @[package.scala:16:47] assign io_tag_valid_0 = _io_tag_valid_T; // @[mshrs.scala:36:7, :150:25] wire _io_way_valid_T = ~(\|state); // @[package.scala:16:47] wire _io_way_valid_T_1 = state == 5'h11; // @[package.scala:16:47] wire _io_way_valid_T_2 = _io_way_valid_T \| _io_way_valid_T_1; // @[package.scala:16:47, :81:59] assign _io_way_valid_T_3 = ~_io_way_valid_T_2; // @[package.scala:81:59] assign io_way_valid_0 = _io_way_valid_T_3; // @[mshrs.scala:36:7, :151:19] assign _io_req_sec_rdy_T = sec_rdy & _rpq_io_enq_ready; // @[mshrs.scala:125:67, :128:19, :159:37] assign io_req_sec_rdy_0 = _io_req_sec_rdy_T; // @[mshrs.scala:36:7, :159:37] wire [4:0] state_new_state; // @[mshrs.scala:191:29] wire _state_T_1 = ~_state_T; // @[mshrs.scala:194:11] wire _state_T_2 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11] wire [3:0] _GEN_27 = {2'h2, io_req_old_meta_coh_state_0}; // @[Metadata.scala:120:19] wire [3:0] _state_req_needs_wb_r_T_6; // @[Metadata.scala:120:19] assign _state_req_needs_wb_r_T_6 = _GEN_27; // @[Metadata.scala:120:19] wire [3:0] _state_req_needs_wb_r_T_70; // @[Metadata.scala:120:19] assign _state_req_needs_wb_r_T_70 = _GEN_27; // @[Metadata.scala:120:19] wire _state_req_needs_wb_r_T_19 = _state_req_needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_21 = _state_req_needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_23 = _state_req_needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_25 = _state_req_needs_wb_r_T_23 ? 3'h2 : _state_req_needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_27 = _state_req_needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_29 = _state_req_needs_wb_r_T_27 ? 3'h1 : _state_req_needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_31 = _state_req_needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_32 = _state_req_needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_33 = _state_req_needs_wb_r_T_31 ? 3'h1 : _state_req_needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_35 = _state_req_needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_36 = ~_state_req_needs_wb_r_T_35 & _state_req_needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_37 = _state_req_needs_wb_r_T_35 ? 3'h5 : _state_req_needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_39 = _state_req_needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_40 = ~_state_req_needs_wb_r_T_39 & _state_req_needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_41 = _state_req_needs_wb_r_T_39 ? 3'h4 : _state_req_needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_42 = {1'h0, _state_req_needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_43 = _state_req_needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_44 = ~_state_req_needs_wb_r_T_43 & _state_req_needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_45 = _state_req_needs_wb_r_T_43 ? 3'h0 : _state_req_needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_46 = _state_req_needs_wb_r_T_43 ? 2'h1 : _state_req_needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_47 = _state_req_needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_48 = _state_req_needs_wb_r_T_47 \| _state_req_needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_49 = _state_req_needs_wb_r_T_47 ? 3'h0 : _state_req_needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_50 = _state_req_needs_wb_r_T_47 ? 2'h1 : _state_req_needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_51 = _state_req_needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_52 = ~_state_req_needs_wb_r_T_51 & _state_req_needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_53 = _state_req_needs_wb_r_T_51 ? 3'h5 : _state_req_needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_54 = _state_req_needs_wb_r_T_51 ? 2'h0 : _state_req_needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_55 = _state_req_needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_56 = ~_state_req_needs_wb_r_T_55 & _state_req_needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_57 = _state_req_needs_wb_r_T_55 ? 3'h4 : _state_req_needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_58 = _state_req_needs_wb_r_T_55 ? 2'h1 : _state_req_needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_59 = _state_req_needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_60 = ~_state_req_needs_wb_r_T_59 & _state_req_needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_61 = _state_req_needs_wb_r_T_59 ? 3'h3 : _state_req_needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_62 = _state_req_needs_wb_r_T_59 ? 2'h2 : _state_req_needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_63 = _state_req_needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire state_req_needs_wb_r_1 = _state_req_needs_wb_r_T_63 \| _state_req_needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] state_req_needs_wb_r_2 = _state_req_needs_wb_r_T_63 ? 3'h3 : _state_req_needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] state_req_needs_wb_r_3 = _state_req_needs_wb_r_T_63 ? 2'h2 : _state_req_needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] state_req_needs_wb_meta_state = state_req_needs_wb_r_3; // @[Misc.scala:38:63] wire _state_r_c_cat_T_2 = _state_r_c_cat_T \| _state_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_4 = _state_r_c_cat_T_2 \| _state_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_9 = _state_r_c_cat_T_5 \| _state_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_10 = _state_r_c_cat_T_9 \| _state_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_11 = _state_r_c_cat_T_10 \| _state_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_17 = _state_r_c_cat_T_12 \| _state_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_18 = _state_r_c_cat_T_17 \| _state_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_19 = _state_r_c_cat_T_18 \| _state_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_20 = _state_r_c_cat_T_19 \| _state_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_21 = _state_r_c_cat_T_11 \| _state_r_c_cat_T_20; // @[package.scala:81:59] wire _state_r_c_cat_T_22 = _state_r_c_cat_T_4 \| _state_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_25 = _state_r_c_cat_T_23 \| _state_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_27 = _state_r_c_cat_T_25 \| _state_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_32 = _state_r_c_cat_T_28 \| _state_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_33 = _state_r_c_cat_T_32 \| _state_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_34 = _state_r_c_cat_T_33 \| _state_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_40 = _state_r_c_cat_T_35 \| _state_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_41 = _state_r_c_cat_T_40 \| _state_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_42 = _state_r_c_cat_T_41 \| _state_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_43 = _state_r_c_cat_T_42 \| _state_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_44 = _state_r_c_cat_T_34 \| _state_r_c_cat_T_43; // @[package.scala:81:59] wire _state_r_c_cat_T_45 = _state_r_c_cat_T_27 \| _state_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_47 = _state_r_c_cat_T_45 \| _state_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _state_r_c_cat_T_49 = _state_r_c_cat_T_47 \| _state_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] state_r_c = {_state_r_c_cat_T_22, _state_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _state_r_T = {state_r_c, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19] wire _state_r_T_25 = _state_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _state_r_T_27 = {1'h0, _state_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _state_r_T_28 = _state_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _state_r_T_30 = _state_r_T_28 ? 2'h2 : _state_r_T_27; // @[Misc.scala:35:36, :49:20] wire _state_r_T_31 = _state_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _state_r_T_33 = _state_r_T_31 ? 2'h1 : _state_r_T_30; // @[Misc.scala:35:36, :49:20] wire _state_r_T_34 = _state_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _state_r_T_36 = _state_r_T_34 ? 2'h2 : _state_r_T_33; // @[Misc.scala:35:36, :49:20] wire _state_r_T_37 = _state_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _state_r_T_39 = _state_r_T_37 ? 2'h0 : _state_r_T_36; // @[Misc.scala:35:36, :49:20] wire _state_r_T_40 = _state_r_T == 4'hE; // @[Misc.scala:49:20] wire _state_r_T_41 = _state_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_42 = _state_r_T_40 ? 2'h3 : _state_r_T_39; // @[Misc.scala:35:36, :49:20] wire _state_r_T_43 = &_state_r_T; // @[Misc.scala:49:20] wire _state_r_T_44 = _state_r_T_43 \| _state_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_45 = _state_r_T_43 ? 2'h3 : _state_r_T_42; // @[Misc.scala:35:36, :49:20] wire _state_r_T_46 = _state_r_T == 4'h6; // @[Misc.scala:49:20] wire _state_r_T_47 = _state_r_T_46 \| _state_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_48 = _state_r_T_46 ? 2'h2 : _state_r_T_45; // @[Misc.scala:35:36, :49:20] wire _state_r_T_49 = _state_r_T == 4'h7; // @[Misc.scala:49:20] wire _state_r_T_50 = _state_r_T_49 \| _state_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_51 = _state_r_T_49 ? 2'h3 : _state_r_T_48; // @[Misc.scala:35:36, :49:20] wire _state_r_T_52 = _state_r_T == 4'h1; // @[Misc.scala:49:20] wire _state_r_T_53 = _state_r_T_52 \| _state_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_54 = _state_r_T_52 ? 2'h1 : _state_r_T_51; // @[Misc.scala:35:36, :49:20] wire _state_r_T_55 = _state_r_T == 4'h2; // @[Misc.scala:49:20] wire _state_r_T_56 = _state_r_T_55 \| _state_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_57 = _state_r_T_55 ? 2'h2 : _state_r_T_54; // @[Misc.scala:35:36, :49:20] wire _state_r_T_58 = _state_r_T == 4'h3; // @[Misc.scala:49:20] wire state_is_hit = _state_r_T_58 \| _state_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] state_r_2 = _state_r_T_58 ? 2'h3 : _state_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] state_coh_on_hit_state = state_r_2; // @[Misc.scala:35:36] wire _state_T_5 = _state_T_3 \| _state_T_4; // @[Consts.scala:90:{32,42,49}] wire _state_T_7 = _state_T_5 \| _state_T_6; // @[Consts.scala:90:{42,59,66}] wire _state_T_12 = _state_T_8 \| _state_T_9; // @[package.scala:16:47, :81:59] wire _state_T_13 = _state_T_12 \| _state_T_10; // @[package.scala:16:47, :81:59] wire _state_T_14 = _state_T_13 \| _state_T_11; // @[package.scala:16:47, :81:59] wire _state_T_20 = _state_T_15 \| _state_T_16; // @[package.scala:16:47, :81:59] wire _state_T_21 = _state_T_20 \| _state_T_17; // @[package.scala:16:47, :81:59] wire _state_T_22 = _state_T_21 \| _state_T_18; // @[package.scala:16:47, :81:59] wire _state_T_23 = _state_T_22 \| _state_T_19; // @[package.scala:16:47, :81:59] wire _state_T_24 = _state_T_14 \| _state_T_23; // @[package.scala:81:59] wire _state_T_25 = _state_T_7 \| _state_T_24; // @[Consts.scala:87:44, :90:{59,76}] wire _state_T_27 = ~_state_T_26; // @[mshrs.scala:201:15] wire _state_T_28 = ~_state_T_25; // @[Consts.scala:90:76] assign state_new_state = io_req_tag_match_0 & state_is_hit ? 5'hC : 5'h1; // @[Misc.scala:35:9] assign io_mem_acquire_valid_0 = (\|state) & _io_probe_rdy_T_2; // @[package.scala:16:47] wire [27:0] _GEN_28 = {req_tag, req_idx}; // @[mshrs.scala:110:25, :111:26, :227:28] wire [27:0] _io_mem_acquire_bits_T; // @[mshrs.scala:227:28] assign _io_mem_acquire_bits_T = _GEN_28; // @[mshrs.scala:227:28] wire [27:0] rp_addr_hi; // @[mshrs.scala:261:22] assign rp_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :261:22] wire [27:0] hi; // @[mshrs.scala:266:10] assign hi = _GEN_28; // @[mshrs.scala:227:28, :266:10] wire [27:0] io_replay_bits_addr_hi; // @[mshrs.scala:353:31] assign io_replay_bits_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :353:31] wire [33:0] _io_mem_acquire_bits_T_1 = {_io_mem_acquire_bits_T, 6'h0}; // @[mshrs.scala:227:{28,47}] wire [33:0] _io_mem_acquire_bits_legal_T_1 = _io_mem_acquire_bits_T_1; // @[Parameters.scala:137:31] wire [34:0] _io_mem_acquire_bits_legal_T_2 = {1'h0, _io_mem_acquire_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_mem_acquire_bits_legal_T_3 = _io_mem_acquire_bits_legal_T_2 & 35'h80000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_mem_acquire_bits_legal_T_4 = _io_mem_acquire_bits_legal_T_3; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_5 = _io_mem_acquire_bits_legal_T_4 == 35'h0; // @[Parameters.scala:137:{46,59}] assign io_mem_acquire_bits_a_address = _io_mem_acquire_bits_T_1[31:0]; // @[Edges.scala:346:17] wire [33:0] _io_mem_acquire_bits_legal_T_9 = {_io_mem_acquire_bits_T_1[33:32], io_mem_acquire_bits_a_address ^ 32'h80000000}; // @[Edges.scala:346:17] wire [34:0] _io_mem_acquire_bits_legal_T_10 = {1'h0, _io_mem_acquire_bits_legal_T_9}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_mem_acquire_bits_legal_T_11 = _io_mem_acquire_bits_legal_T_10 & 35'h80000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_mem_acquire_bits_legal_T_12 = _io_mem_acquire_bits_legal_T_11; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_13 = _io_mem_acquire_bits_legal_T_12 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _io_mem_acquire_bits_legal_T_14 = _io_mem_acquire_bits_legal_T_13; // @[Parameters.scala:684:54] wire io_mem_acquire_bits_legal = _io_mem_acquire_bits_legal_T_14; // @[Parameters.scala:684:54, :686:26] assign io_mem_acquire_bits_param_0 = io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] assign io_mem_acquire_bits_address_0 = io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] assign io_mem_acquire_bits_a_param = {1'h0, grow_param}; // @[Misc.scala:35:36] wire io_mem_acquire_bits_a_mask_sub_sub_bit = _io_mem_acquire_bits_T_1[2]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T = io_mem_acquire_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = io_mem_acquire_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_bit = _io_mem_acquire_bits_T_1[1]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_bit = _io_mem_acquire_bits_T_1[0]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_nbit = ~io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_eq = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T = io_mem_acquire_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_1 = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_1 = io_mem_acquire_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_2 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_2 = io_mem_acquire_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_3 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_3 = io_mem_acquire_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_4 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_4 = io_mem_acquire_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_5 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_5 = io_mem_acquire_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_6 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_6 = io_mem_acquire_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_7 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_7 = io_mem_acquire_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38] wire _GEN_29 = ~(\|state) \| _io_probe_rdy_T_2; // @[package.scala:16:47] assign io_lb_write_valid_0 = ~_GEN_29 & _io_probe_rdy_T_3 & opdata & io_mem_grant_valid_0; // @[package.scala:16:47] wire [8:0] _io_lb_write_bits_offset_T = refill_address_inc[11:3]; // @[Edges.scala:269:29] assign io_lb_write_bits_offset_0 = _io_lb_write_bits_offset_T[2:0]; // @[mshrs.scala:36:7, :238:{31,53}] assign io_mem_grant_ready_0 = ~_GEN_29 & _io_probe_rdy_T_3 & (~opdata \| io_lb_write_ready_0); // @[package.scala:16:47] wire _grantack_valid_T = io_mem_grant_bits_opcode_0[2]; // @[Edges.scala:71:36] wire _grantack_valid_T_1 = io_mem_grant_bits_opcode_0[1]; // @[Edges.scala:71:52] wire _grantack_valid_T_2 = ~_grantack_valid_T_1; // @[Edges.scala:71:{43,52}] wire _grantack_valid_T_3 = _grantack_valid_T & _grantack_valid_T_2; // @[Edges.scala:71:{36,40,43}] wire [4:0] _state_T_29 = grant_had_data ? 5'h3 : 5'hC; // @[mshrs.scala:141:27, :250:19] wire _drain_load_T = _rpq_io_deq_bits_uop_mem_cmd == 5'h0; // @[package.scala:16:47] wire _drain_load_T_1 = _rpq_io_deq_bits_uop_mem_cmd == 5'h10; // @[package.scala:16:47] wire _GEN_30 = _rpq_io_deq_bits_uop_mem_cmd == 5'h6; // @[package.scala:16:47] wire _drain_load_T_2; // @[package.scala:16:47] assign _drain_load_T_2 = _GEN_30; // @[package.scala:16:47] wire _r_c_cat_T_48; // @[Consts.scala:91:71] assign _r_c_cat_T_48 = _GEN_30; // @[package.scala:16:47] wire _GEN_31 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[package.scala:16:47] wire _drain_load_T_3; // @[package.scala:16:47] assign _drain_load_T_3 = _GEN_31; // @[package.scala:16:47] wire _drain_load_T_28; // @[Consts.scala:90:66] assign _drain_load_T_28 = _GEN_31; // @[package.scala:16:47] wire _drain_load_T_4 = _drain_load_T \| _drain_load_T_1; // @[package.scala:16:47, :81:59] wire _drain_load_T_5 = _drain_load_T_4 \| _drain_load_T_2; // @[package.scala:16:47, :81:59] wire _drain_load_T_6 = _drain_load_T_5 \| _drain_load_T_3; // @[package.scala:16:47, :81:59] wire _GEN_32 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _drain_load_T_7; // @[package.scala:16:47] assign _drain_load_T_7 = _GEN_32; // @[package.scala:16:47] wire _drain_load_T_30; // @[package.scala:16:47] assign _drain_load_T_30 = _GEN_32; // @[package.scala:16:47] wire _GEN_33 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _drain_load_T_8; // @[package.scala:16:47] assign _drain_load_T_8 = _GEN_33; // @[package.scala:16:47] wire _drain_load_T_31; // @[package.scala:16:47] assign _drain_load_T_31 = _GEN_33; // @[package.scala:16:47] wire _GEN_34 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _drain_load_T_9; // @[package.scala:16:47] assign _drain_load_T_9 = _GEN_34; // @[package.scala:16:47] wire _drain_load_T_32; // @[package.scala:16:47] assign _drain_load_T_32 = _GEN_34; // @[package.scala:16:47] wire _GEN_35 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _drain_load_T_10; // @[package.scala:16:47] assign _drain_load_T_10 = _GEN_35; // @[package.scala:16:47] wire _drain_load_T_33; // @[package.scala:16:47] assign _drain_load_T_33 = _GEN_35; // @[package.scala:16:47] wire _drain_load_T_11 = _drain_load_T_7 \| _drain_load_T_8; // @[package.scala:16:47, :81:59] wire _drain_load_T_12 = _drain_load_T_11 \| _drain_load_T_9; // @[package.scala:16:47, :81:59] wire _drain_load_T_13 = _drain_load_T_12 \| _drain_load_T_10; // @[package.scala:16:47, :81:59] wire _GEN_36 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _drain_load_T_14; // @[package.scala:16:47] assign _drain_load_T_14 = _GEN_36; // @[package.scala:16:47] wire _drain_load_T_37; // @[package.scala:16:47] assign _drain_load_T_37 = _GEN_36; // @[package.scala:16:47] wire _GEN_37 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _drain_load_T_15; // @[package.scala:16:47] assign _drain_load_T_15 = _GEN_37; // @[package.scala:16:47] wire _drain_load_T_38; // @[package.scala:16:47] assign _drain_load_T_38 = _GEN_37; // @[package.scala:16:47] wire _GEN_38 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _drain_load_T_16; // @[package.scala:16:47] assign _drain_load_T_16 = _GEN_38; // @[package.scala:16:47] wire _drain_load_T_39; // @[package.scala:16:47] assign _drain_load_T_39 = _GEN_38; // @[package.scala:16:47] wire _GEN_39 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _drain_load_T_17; // @[package.scala:16:47] assign _drain_load_T_17 = _GEN_39; // @[package.scala:16:47] wire _drain_load_T_40; // @[package.scala:16:47] assign _drain_load_T_40 = _GEN_39; // @[package.scala:16:47] wire _GEN_40 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _drain_load_T_18; // @[package.scala:16:47] assign _drain_load_T_18 = _GEN_40; // @[package.scala:16:47] wire _drain_load_T_41; // @[package.scala:16:47] assign _drain_load_T_41 = _GEN_40; // @[package.scala:16:47] wire _drain_load_T_19 = _drain_load_T_14 \| _drain_load_T_15; // @[package.scala:16:47, :81:59] wire _drain_load_T_20 = _drain_load_T_19 \| _drain_load_T_16; // @[package.scala:16:47, :81:59] wire _drain_load_T_21 = _drain_load_T_20 \| _drain_load_T_17; // @[package.scala:16:47, :81:59] wire _drain_load_T_22 = _drain_load_T_21 \| _drain_load_T_18; // @[package.scala:16:47, :81:59] wire _drain_load_T_23 = _drain_load_T_13 \| _drain_load_T_22; // @[package.scala:81:59] wire _drain_load_T_24 = _drain_load_T_6 \| _drain_load_T_23; // @[package.scala:81:59] wire _drain_load_T_25 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _drain_load_T_26 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _drain_load_T_27 = _drain_load_T_25 \| _drain_load_T_26; // @[Consts.scala:90:{32,42,49}] wire _drain_load_T_29 = _drain_load_T_27 \| _drain_load_T_28; // @[Consts.scala:90:{42,59,66}] wire _drain_load_T_34 = _drain_load_T_30 \| _drain_load_T_31; // @[package.scala:16:47, :81:59] wire _drain_load_T_35 = _drain_load_T_34 \| _drain_load_T_32; // @[package.scala:16:47, :81:59] wire _drain_load_T_36 = _drain_load_T_35 \| _drain_load_T_33; // @[package.scala:16:47, :81:59] wire _drain_load_T_42 = _drain_load_T_37 \| _drain_load_T_38; // @[package.scala:16:47, :81:59] wire _drain_load_T_43 = _drain_load_T_42 \| _drain_load_T_39; // @[package.scala:16:47, :81:59] wire _drain_load_T_44 = _drain_load_T_43 \| _drain_load_T_40; // @[package.scala:16:47, :81:59] wire _drain_load_T_45 = _drain_load_T_44 \| _drain_load_T_41; // @[package.scala:16:47, :81:59] wire _drain_load_T_46 = _drain_load_T_36 \| _drain_load_T_45; // @[package.scala:81:59] wire _drain_load_T_47 = _drain_load_T_29 \| _drain_load_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _drain_load_T_48 = ~_drain_load_T_47; // @[Consts.scala:90:76] wire _drain_load_T_49 = _drain_load_T_24 & _drain_load_T_48; // @[Consts.scala:89:68] wire _drain_load_T_50 = _rpq_io_deq_bits_uop_mem_cmd != 5'h6; // @[mshrs.scala:128:19, :259:51] wire drain_load = _drain_load_T_49 & _drain_load_T_50; // @[mshrs.scala:257:59, :258:60, :259:51] wire [5:0] _rp_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :261:61] wire [33:0] rp_addr = {rp_addr_hi, _rp_addr_T}; // @[mshrs.scala:261:{22,61}] wire [1:0] size; // @[AMOALU.scala:11:18] wire _rpq_io_deq_ready_T = io_resp_ready_0 & io_lb_read_ready_0; // @[mshrs.scala:36:7, :270:45] wire _rpq_io_deq_ready_T_1 = _rpq_io_deq_ready_T & drain_load; // @[mshrs.scala:258:60, :270:{45,65}] wire _io_lb_read_valid_T = _rpq_io_deq_valid & drain_load; // @[mshrs.scala:128:19, :258:60, :271:48] wire [30:0] _io_lb_read_bits_offset_T = _rpq_io_deq_bits_addr[33:3]; // @[mshrs.scala:128:19, :273:52] wire _GEN_41 = io_lb_read_ready_0 & io_lb_read_valid_0; // @[Decoupled.scala:51:35] wire _io_resp_valid_T; // @[Decoupled.scala:51:35] assign _io_resp_valid_T = _GEN_41; // @[Decoupled.scala:51:35] wire _io_refill_valid_T; // @[Decoupled.scala:51:35] assign _io_refill_valid_T = _GEN_41; // @[Decoupled.scala:51:35] wire _io_resp_valid_T_1 = _rpq_io_deq_valid & _io_resp_valid_T; // @[Decoupled.scala:51:35] wire _io_resp_valid_T_2 = _io_resp_valid_T_1 & drain_load; // @[mshrs.scala:258:60, :275:{43,62}] wire _GEN_42 = ~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3; // @[package.scala:16:47] assign io_resp_valid_0 = ~_GEN_42 & _io_probe_rdy_T_4 & _io_resp_valid_T_2; // @[package.scala:16:47] wire _io_resp_bits_data_shifted_T = _rpq_io_deq_bits_addr[2]; // @[AMOALU.scala:42:29] wire [31:0] _io_resp_bits_data_shifted_T_1 = data_word[63:32]; // @[AMOALU.scala:42:37] wire [31:0] _io_resp_bits_data_T_5 = data_word[63:32]; // @[AMOALU.scala:42:37, :45:94] wire [31:0] _io_resp_bits_data_shifted_T_2 = data_word[31:0]; // @[AMOALU.scala:42:55] wire [31:0] io_resp_bits_data_shifted = _io_resp_bits_data_shifted_T ? _io_resp_bits_data_shifted_T_1 : _io_resp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] io_resp_bits_data_zeroed = io_resp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T = size == 2'h2; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_1 = _io_resp_bits_data_T; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_2 = io_resp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_3 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _io_resp_bits_data_T_4 = {32{_io_resp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _io_resp_bits_data_T_6 = _io_resp_bits_data_T_1 ? _io_resp_bits_data_T_4 : _io_resp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_resp_bits_data_T_7 = {_io_resp_bits_data_T_6, io_resp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_resp_bits_data_shifted_T_3 = _rpq_io_deq_bits_addr[1]; // @[AMOALU.scala:42:29] wire [15:0] _io_resp_bits_data_shifted_T_4 = _io_resp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _io_resp_bits_data_shifted_T_5 = _io_resp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] io_resp_bits_data_shifted_1 = _io_resp_bits_data_shifted_T_3 ? _io_resp_bits_data_shifted_T_4 : _io_resp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] io_resp_bits_data_zeroed_1 = io_resp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T_8 = size == 2'h1; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_9 = _io_resp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_10 = io_resp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_11 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _io_resp_bits_data_T_12 = {48{_io_resp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _io_resp_bits_data_T_13 = _io_resp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _io_resp_bits_data_T_14 = _io_resp_bits_data_T_9 ? _io_resp_bits_data_T_12 : _io_resp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_resp_bits_data_T_15 = {_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_resp_bits_data_shifted_T_6 = _rpq_io_deq_bits_addr[0]; // @[AMOALU.scala:42:29] wire [7:0] _io_resp_bits_data_shifted_T_7 = _io_resp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _io_resp_bits_data_shifted_T_8 = _io_resp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] io_resp_bits_data_shifted_2 = _io_resp_bits_data_shifted_T_6 ? _io_resp_bits_data_shifted_T_7 : _io_resp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] io_resp_bits_data_zeroed_2 = io_resp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T_16 = size == 2'h0; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_17 = _io_resp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_18 = io_resp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_19 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _io_resp_bits_data_T_20 = {56{_io_resp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _io_resp_bits_data_T_21 = _io_resp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _io_resp_bits_data_T_22 = _io_resp_bits_data_T_17 ? _io_resp_bits_data_T_20 : _io_resp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] assign _io_resp_bits_data_T_23 = {_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] assign io_resp_bits_data_0 = _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16] wire _T_26 = rpq_io_deq_ready & _rpq_io_deq_valid; // @[Decoupled.scala:51:35] wire _T_28 = _rpq_io_empty & ~commit_line; // @[mshrs.scala:128:19, :140:24, :282:{31,34}] wire _T_33 = _rpq_io_empty \| _rpq_io_deq_valid & ~drain_load; // @[mshrs.scala:128:19, :258:60, :288:{31,52,55}] assign io_commit_val_0 = ~_GEN_42 & _io_probe_rdy_T_4 & ~(_T_26 \| _T_28) & _T_33; // @[Decoupled.scala:51:35] wire _io_meta_read_valid_T = ~io_prober_state_valid_0; // @[mshrs.scala:36:7, :295:27] wire _io_meta_read_valid_T_1 = ~grantack_valid; // @[mshrs.scala:138:21, :295:53] wire _io_meta_read_valid_T_2 = _io_meta_read_valid_T \| _io_meta_read_valid_T_1; // @[mshrs.scala:295:{27,50,53}] wire [3:0] _io_meta_read_valid_T_3 = io_prober_state_bits_0[9:6]; // @[mshrs.scala:36:7, :295:93] wire _io_meta_read_valid_T_4 = _io_meta_read_valid_T_3 != req_idx; // @[mshrs.scala:110:25, :295:{93,120}] wire _io_meta_read_valid_T_5 = _io_meta_read_valid_T_2 \| _io_meta_read_valid_T_4; // @[mshrs.scala:295:{50,69,120}] assign io_meta_read_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4) & _io_probe_rdy_T_8 & _io_meta_read_valid_T_5; // @[package.scala:16:47] assign io_meta_write_bits_data_tag_0 = req_tag[21:0]; // @[mshrs.scala:36:7, :111:26, :297:27] assign io_meta_read_bits_tag_0 = req_tag[21:0]; // @[mshrs.scala:36:7, :111:26, :297:27] wire _T_36 = state == 5'h5; // @[mshrs.scala:107:22, :302:22] wire _T_37 = state == 5'h6; // @[mshrs.scala:107:22, :304:22] wire [3:0] _needs_wb_r_T_6 = {2'h2, io_meta_resp_bits_coh_state_0}; // @[Metadata.scala:120:19] wire _needs_wb_r_T_19 = _needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_21 = _needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_23 = _needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_25 = _needs_wb_r_T_23 ? 3'h2 : _needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_27 = _needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_29 = _needs_wb_r_T_27 ? 3'h1 : _needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_31 = _needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _needs_wb_r_T_32 = _needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_33 = _needs_wb_r_T_31 ? 3'h1 : _needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_35 = _needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _needs_wb_r_T_36 = ~_needs_wb_r_T_35 & _needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_37 = _needs_wb_r_T_35 ? 3'h5 : _needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_39 = _needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _needs_wb_r_T_40 = ~_needs_wb_r_T_39 & _needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_41 = _needs_wb_r_T_39 ? 3'h4 : _needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_42 = {1'h0, _needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_43 = _needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _needs_wb_r_T_44 = ~_needs_wb_r_T_43 & _needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_45 = _needs_wb_r_T_43 ? 3'h0 : _needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_46 = _needs_wb_r_T_43 ? 2'h1 : _needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_47 = _needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _needs_wb_r_T_48 = _needs_wb_r_T_47 \| _needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_49 = _needs_wb_r_T_47 ? 3'h0 : _needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_50 = _needs_wb_r_T_47 ? 2'h1 : _needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_51 = _needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _needs_wb_r_T_52 = ~_needs_wb_r_T_51 & _needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_53 = _needs_wb_r_T_51 ? 3'h5 : _needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_54 = _needs_wb_r_T_51 ? 2'h0 : _needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_55 = _needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _needs_wb_r_T_56 = ~_needs_wb_r_T_55 & _needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_57 = _needs_wb_r_T_55 ? 3'h4 : _needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_58 = _needs_wb_r_T_55 ? 2'h1 : _needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_59 = _needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _needs_wb_r_T_60 = ~_needs_wb_r_T_59 & _needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_61 = _needs_wb_r_T_59 ? 3'h3 : _needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_62 = _needs_wb_r_T_59 ? 2'h2 : _needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_63 = _needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire needs_wb = _needs_wb_r_T_63 \| _needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] needs_wb_r_2 = _needs_wb_r_T_63 ? 3'h3 : _needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] needs_wb_r_3 = _needs_wb_r_T_63 ? 2'h2 : _needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] needs_wb_meta_state = needs_wb_r_3; // @[Misc.scala:38:63] wire _state_T_30 = ~io_meta_resp_valid_0; // @[mshrs.scala:36:7, :306:18] wire [4:0] _state_T_31 = needs_wb ? 5'h7 : 5'hB; // @[Misc.scala:38:9] wire [4:0] _state_T_32 = _state_T_30 ? 5'h4 : _state_T_31; // @[mshrs.scala:306:{17,18}, :307:17] wire _T_38 = state == 5'h7; // @[mshrs.scala:107:22, :308:22] wire _T_40 = state == 5'h9; // @[mshrs.scala:107:22, :318:22] assign io_wb_req_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38) & _T_40; // @[package.scala:16:47] wire _T_42 = state == 5'hA; // @[mshrs.scala:107:22, :330:22] wire _T_43 = state == 5'hB; // @[mshrs.scala:107:22, :334:22] wire _GEN_43 = _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42; // @[mshrs.scala:148:129, :179:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:41] assign io_lb_read_valid_0 = ~_GEN_42 & (_io_probe_rdy_T_4 ? _io_lb_read_valid_T : ~_GEN_43 & _T_43); // @[package.scala:16:47] assign io_lb_read_bits_offset_0 = _io_probe_rdy_T_4 ? _io_lb_read_bits_offset_T[2:0] : refill_ctr; // @[package.scala:16:47] wire _GEN_44 = _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4 \| _GEN_43; // @[package.scala:16:47] assign io_refill_valid_0 = ~(~(\|state) \| _GEN_44) & _T_43 & _io_refill_valid_T; // @[Decoupled.scala:51:35] wire [5:0] _io_refill_bits_addr_T = {refill_ctr, 3'h0}; // @[mshrs.scala:139:24, :340:59] wire [33:0] _io_refill_bits_addr_T_1 = {req_block_addr[33:6], req_block_addr[5:0] \| _io_refill_bits_addr_T}; // @[mshrs.scala:112:51, :340:{45,59}] assign io_refill_bits_addr_0 = _io_refill_bits_addr_T_1[9:0]; // @[mshrs.scala:36:7, :340:{27,45}] wire [3:0] _refill_ctr_T = {1'h0, refill_ctr} + 4'h1; // @[mshrs.scala:139:24, :345:32] wire [2:0] _refill_ctr_T_1 = _refill_ctr_T[2:0]; // @[mshrs.scala:345:32] wire _T_46 = state == 5'hC; // @[mshrs.scala:107:22, :350:22] wire _GEN_45 = _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42 \| _T_43; // @[mshrs.scala:148:129, :164:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:39] wire _GEN_46 = _io_probe_rdy_T_4 \| _GEN_45; // @[package.scala:16:47] assign io_replay_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _GEN_46) & _T_46 & _rpq_io_deq_valid; // @[package.scala:16:47] assign rpq_io_deq_ready = ~_GEN_42 & (_io_probe_rdy_T_4 ? _rpq_io_deq_ready_T_1 : ~_GEN_45 & _T_46 & io_replay_ready_0); // @[package.scala:16:47] wire [5:0] _io_replay_bits_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :353:70] assign _io_replay_bits_addr_T_1 = {io_replay_bits_addr_hi, _io_replay_bits_addr_T}; // @[mshrs.scala:353:{31,70}] assign io_replay_bits_addr_0 = _io_replay_bits_addr_T_1; // @[mshrs.scala:36:7, :353:31] wire _T_48 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _r_c_cat_T; // @[Consts.scala:90:32] assign _r_c_cat_T = _T_48; // @[Consts.scala:90:32] wire _r_c_cat_T_23; // @[Consts.scala:90:32] assign _r_c_cat_T_23 = _T_48; // @[Consts.scala:90:32] wire _T_49 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _r_c_cat_T_1; // @[Consts.scala:90:49] assign _r_c_cat_T_1 = _T_49; // @[Consts.scala:90:49] wire _r_c_cat_T_24; // @[Consts.scala:90:49] assign _r_c_cat_T_24 = _T_49; // @[Consts.scala:90:49] wire _T_51 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66] wire _r_c_cat_T_3; // @[Consts.scala:90:66] assign _r_c_cat_T_3 = _T_51; // @[Consts.scala:90:66] wire _r_c_cat_T_26; // @[Consts.scala:90:66] assign _r_c_cat_T_26 = _T_51; // @[Consts.scala:90:66] wire _T_53 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _r_c_cat_T_5; // @[package.scala:16:47] assign _r_c_cat_T_5 = _T_53; // @[package.scala:16:47] wire _r_c_cat_T_28; // @[package.scala:16:47] assign _r_c_cat_T_28 = _T_53; // @[package.scala:16:47] wire _T_54 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _r_c_cat_T_6; // @[package.scala:16:47] assign _r_c_cat_T_6 = _T_54; // @[package.scala:16:47] wire _r_c_cat_T_29; // @[package.scala:16:47] assign _r_c_cat_T_29 = _T_54; // @[package.scala:16:47] wire _T_55 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _r_c_cat_T_7; // @[package.scala:16:47] assign _r_c_cat_T_7 = _T_55; // @[package.scala:16:47] wire _r_c_cat_T_30; // @[package.scala:16:47] assign _r_c_cat_T_30 = _T_55; // @[package.scala:16:47] wire _T_56 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _r_c_cat_T_8; // @[package.scala:16:47] assign _r_c_cat_T_8 = _T_56; // @[package.scala:16:47] wire _r_c_cat_T_31; // @[package.scala:16:47] assign _r_c_cat_T_31 = _T_56; // @[package.scala:16:47] wire _T_60 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _r_c_cat_T_12; // @[package.scala:16:47] assign _r_c_cat_T_12 = _T_60; // @[package.scala:16:47] wire _r_c_cat_T_35; // @[package.scala:16:47] assign _r_c_cat_T_35 = _T_60; // @[package.scala:16:47] wire _T_61 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _r_c_cat_T_13; // @[package.scala:16:47] assign _r_c_cat_T_13 = _T_61; // @[package.scala:16:47] wire _r_c_cat_T_36; // @[package.scala:16:47] assign _r_c_cat_T_36 = _T_61; // @[package.scala:16:47] wire _T_62 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _r_c_cat_T_14; // @[package.scala:16:47] assign _r_c_cat_T_14 = _T_62; // @[package.scala:16:47] wire _r_c_cat_T_37; // @[package.scala:16:47] assign _r_c_cat_T_37 = _T_62; // @[package.scala:16:47] wire _T_63 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _r_c_cat_T_15; // @[package.scala:16:47] assign _r_c_cat_T_15 = _T_63; // @[package.scala:16:47] wire _r_c_cat_T_38; // @[package.scala:16:47] assign _r_c_cat_T_38 = _T_63; // @[package.scala:16:47] wire _T_64 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _r_c_cat_T_16; // @[package.scala:16:47] assign _r_c_cat_T_16 = _T_64; // @[package.scala:16:47] wire _r_c_cat_T_39; // @[package.scala:16:47] assign _r_c_cat_T_39 = _T_64; // @[package.scala:16:47] wire _T_71 = io_replay_ready_0 & io_replay_valid_0 & (_T_48 \| _T_49 \| _T_51 \| _T_53 \| _T_54 \| _T_55 \| _T_56 \| _T_60 \| _T_61 \| _T_62 \| _T_63 \| _T_64); // @[Decoupled.scala:51:35] wire _r_c_cat_T_2 = _r_c_cat_T \| _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_4 = _r_c_cat_T_2 \| _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_9 = _r_c_cat_T_5 \| _r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_10 = _r_c_cat_T_9 \| _r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_11 = _r_c_cat_T_10 \| _r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_17 = _r_c_cat_T_12 \| _r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_18 = _r_c_cat_T_17 \| _r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_19 = _r_c_cat_T_18 \| _r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_20 = _r_c_cat_T_19 \| _r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_21 = _r_c_cat_T_11 \| _r_c_cat_T_20; // @[package.scala:81:59] wire _r_c_cat_T_22 = _r_c_cat_T_4 \| _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_25 = _r_c_cat_T_23 \| _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_27 = _r_c_cat_T_25 \| _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_32 = _r_c_cat_T_28 \| _r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_33 = _r_c_cat_T_32 \| _r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_34 = _r_c_cat_T_33 \| _r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_40 = _r_c_cat_T_35 \| _r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_41 = _r_c_cat_T_40 \| _r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_42 = _r_c_cat_T_41 \| _r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_43 = _r_c_cat_T_42 \| _r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_44 = _r_c_cat_T_34 \| _r_c_cat_T_43; // @[package.scala:81:59] wire _r_c_cat_T_45 = _r_c_cat_T_27 \| _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_46 = _rpq_io_deq_bits_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54] wire _r_c_cat_T_47 = _r_c_cat_T_45 \| _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_49 = _r_c_cat_T_47 \| _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r_T_64 = {r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_89 = _r_T_64 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_91 = {1'h0, _r_T_89}; // @[Misc.scala:35:36, :49:20] wire _r_T_92 = _r_T_64 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_94 = _r_T_92 ? 2'h2 : _r_T_91; // @[Misc.scala:35:36, :49:20] wire _r_T_95 = _r_T_64 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_97 = _r_T_95 ? 2'h1 : _r_T_94; // @[Misc.scala:35:36, :49:20] wire _r_T_98 = _r_T_64 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_100 = _r_T_98 ? 2'h2 : _r_T_97; // @[Misc.scala:35:36, :49:20] wire _r_T_101 = _r_T_64 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_103 = _r_T_101 ? 2'h0 : _r_T_100; // @[Misc.scala:35:36, :49:20] wire _r_T_104 = _r_T_64 == 4'hE; // @[Misc.scala:49:20] wire _r_T_105 = _r_T_104; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_106 = _r_T_104 ? 2'h3 : _r_T_103; // @[Misc.scala:35:36, :49:20] wire _r_T_107 = &_r_T_64; // @[Misc.scala:49:20] wire _r_T_108 = _r_T_107 \| _r_T_105; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_109 = _r_T_107 ? 2'h3 : _r_T_106; // @[Misc.scala:35:36, :49:20] wire _r_T_110 = _r_T_64 == 4'h6; // @[Misc.scala:49:20] wire _r_T_111 = _r_T_110 \| _r_T_108; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_112 = _r_T_110 ? 2'h2 : _r_T_109; // @[Misc.scala:35:36, :49:20] wire _r_T_113 = _r_T_64 == 4'h7; // @[Misc.scala:49:20] wire _r_T_114 = _r_T_113 \| _r_T_111; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_115 = _r_T_113 ? 2'h3 : _r_T_112; // @[Misc.scala:35:36, :49:20] wire _r_T_116 = _r_T_64 == 4'h1; // @[Misc.scala:49:20] wire _r_T_117 = _r_T_116 \| _r_T_114; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_118 = _r_T_116 ? 2'h1 : _r_T_115; // @[Misc.scala:35:36, :49:20] wire _r_T_119 = _r_T_64 == 4'h2; // @[Misc.scala:49:20] wire _r_T_120 = _r_T_119 \| _r_T_117; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_121 = _r_T_119 ? 2'h2 : _r_T_118; // @[Misc.scala:35:36, :49:20] wire _r_T_122 = _r_T_64 == 4'h3; // @[Misc.scala:49:20] wire is_hit = _r_T_122 \| _r_T_120; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_1 = _r_T_122 ? 2'h3 : _r_T_121; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_state = r_2_1; // @[Misc.scala:35:36] wire _GEN_47 = _T_40 \| _T_42 \| _T_43 \| _T_46; // @[mshrs.scala:156:26, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:{22,39}, :363:44] assign io_meta_write_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37) & (_T_38 \| ~_GEN_47 & _sec_rdy_T_4); // @[package.scala:16:47] assign io_meta_write_bits_data_coh_state_0 = _T_38 ? coh_on_clear_state : new_coh_state; // @[Metadata.scala:160:20] wire _GEN_48 = _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42 \| _T_43 \| _T_46 \| _sec_rdy_T_4; // @[package.scala:16:47] assign io_mem_finish_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _GEN_48) & _sec_rdy_T_5 & grantack_valid; // @[package.scala:16:47] wire [4:0] _state_T_33 = finish_to_prefetch ? 5'h11 : 5'h0; // @[mshrs.scala:142:31, :381:17] wire _GEN_49 = _sec_rdy_T_4 \| _sec_rdy_T_5 \| _sec_rdy_T_6; // @[package.scala:16:47] wire _GEN_50 = _T_46 \| _GEN_49; // @[mshrs.scala:158:26, :350:{22,39}, :363:44, :373:42, :380:42, :382:38] wire _GEN_51 = _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42 \| _T_43 \| _GEN_50; // @[package.scala:16:47] wire _GEN_52 = _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _GEN_51; // @[package.scala:16:47] assign io_req_pri_rdy_0 = ~(\|state) \| ~_GEN_52 & _io_way_valid_T_1; // @[package.scala:16:47] wire _T_87 = io_req_sec_val_0 & ~io_req_sec_rdy_0 \| io_clear_prefetch_0; // @[mshrs.scala:36:7, :384:{27,30,47}] wire _r_c_cat_T_52 = _r_c_cat_T_50 \| _r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_54 = _r_c_cat_T_52 \| _r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_59 = _r_c_cat_T_55 \| _r_c_cat_T_56; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_60 = _r_c_cat_T_59 \| _r_c_cat_T_57; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_61 = _r_c_cat_T_60 \| _r_c_cat_T_58; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_67 = _r_c_cat_T_62 \| _r_c_cat_T_63; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_68 = _r_c_cat_T_67 \| _r_c_cat_T_64; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_69 = _r_c_cat_T_68 \| _r_c_cat_T_65; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_70 = _r_c_cat_T_69 \| _r_c_cat_T_66; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_71 = _r_c_cat_T_61 \| _r_c_cat_T_70; // @[package.scala:81:59] wire _r_c_cat_T_72 = _r_c_cat_T_54 \| _r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_75 = _r_c_cat_T_73 \| _r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_77 = _r_c_cat_T_75 \| _r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_82 = _r_c_cat_T_78 \| _r_c_cat_T_79; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_83 = _r_c_cat_T_82 \| _r_c_cat_T_80; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_84 = _r_c_cat_T_83 \| _r_c_cat_T_81; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_90 = _r_c_cat_T_85 \| _r_c_cat_T_86; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_91 = _r_c_cat_T_90 \| _r_c_cat_T_87; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_92 = _r_c_cat_T_91 \| _r_c_cat_T_88; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_93 = _r_c_cat_T_92 \| _r_c_cat_T_89; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_94 = _r_c_cat_T_84 \| _r_c_cat_T_93; // @[package.scala:81:59] wire _r_c_cat_T_95 = _r_c_cat_T_77 \| _r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_97 = _r_c_cat_T_95 \| _r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_99 = _r_c_cat_T_97 \| _r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c_1 = {_r_c_cat_T_72, _r_c_cat_T_99}; // @[Metadata.scala:29:18] wire [3:0] _r_T_123 = {r_c_1, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_148 = _r_T_123 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_150 = {1'h0, _r_T_148}; // @[Misc.scala:35:36, :49:20] wire _r_T_151 = _r_T_123 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_153 = _r_T_151 ? 2'h2 : _r_T_150; // @[Misc.scala:35:36, :49:20] wire _r_T_154 = _r_T_123 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_156 = _r_T_154 ? 2'h1 : _r_T_153; // @[Misc.scala:35:36, :49:20] wire _r_T_157 = _r_T_123 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_159 = _r_T_157 ? 2'h2 : _r_T_156; // @[Misc.scala:35:36, :49:20] wire _r_T_160 = _r_T_123 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_162 = _r_T_160 ? 2'h0 : _r_T_159; // @[Misc.scala:35:36, :49:20] wire _r_T_163 = _r_T_123 == 4'hE; // @[Misc.scala:49:20] wire _r_T_164 = _r_T_163; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_165 = _r_T_163 ? 2'h3 : _r_T_162; // @[Misc.scala:35:36, :49:20] wire _r_T_166 = &_r_T_123; // @[Misc.scala:49:20] wire _r_T_167 = _r_T_166 \| _r_T_164; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_168 = _r_T_166 ? 2'h3 : _r_T_165; // @[Misc.scala:35:36, :49:20] wire _r_T_169 = _r_T_123 == 4'h6; // @[Misc.scala:49:20] wire _r_T_170 = _r_T_169 \| _r_T_167; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_171 = _r_T_169 ? 2'h2 : _r_T_168; // @[Misc.scala:35:36, :49:20] wire _r_T_172 = _r_T_123 == 4'h7; // @[Misc.scala:49:20] wire _r_T_173 = _r_T_172 \| _r_T_170; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_174 = _r_T_172 ? 2'h3 : _r_T_171; // @[Misc.scala:35:36, :49:20] wire _r_T_175 = _r_T_123 == 4'h1; // @[Misc.scala:49:20] wire _r_T_176 = _r_T_175 \| _r_T_173; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_177 = _r_T_175 ? 2'h1 : _r_T_174; // @[Misc.scala:35:36, :49:20] wire _r_T_178 = _r_T_123 == 4'h2; // @[Misc.scala:49:20] wire _r_T_179 = _r_T_178 \| _r_T_176; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_180 = _r_T_178 ? 2'h2 : _r_T_177; // @[Misc.scala:35:36, :49:20] wire _r_T_181 = _r_T_123 == 4'h3; // @[Misc.scala:49:20] wire is_hit_1 = _r_T_181 \| _r_T_179; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_2 = _r_T_181 ? 2'h3 : _r_T_180; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_1_state = r_2_2; // @[Misc.scala:35:36] wire [4:0] state_new_state_1; // @[mshrs.scala:191:29] wire _state_T_35 = ~_state_T_34; // @[mshrs.scala:194:11] wire _state_T_36 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11] wire _state_req_needs_wb_r_T_83 = _state_req_needs_wb_r_T_70 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_85 = _state_req_needs_wb_r_T_83 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_87 = _state_req_needs_wb_r_T_70 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_89 = _state_req_needs_wb_r_T_87 ? 3'h2 : _state_req_needs_wb_r_T_85; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_91 = _state_req_needs_wb_r_T_70 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_93 = _state_req_needs_wb_r_T_91 ? 3'h1 : _state_req_needs_wb_r_T_89; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_95 = _state_req_needs_wb_r_T_70 == 4'hB; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_96 = _state_req_needs_wb_r_T_95; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_97 = _state_req_needs_wb_r_T_95 ? 3'h1 : _state_req_needs_wb_r_T_93; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_99 = _state_req_needs_wb_r_T_70 == 4'h4; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_100 = ~_state_req_needs_wb_r_T_99 & _state_req_needs_wb_r_T_96; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_101 = _state_req_needs_wb_r_T_99 ? 3'h5 : _state_req_needs_wb_r_T_97; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_103 = _state_req_needs_wb_r_T_70 == 4'h5; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_104 = ~_state_req_needs_wb_r_T_103 & _state_req_needs_wb_r_T_100; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_105 = _state_req_needs_wb_r_T_103 ? 3'h4 : _state_req_needs_wb_r_T_101; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_106 = {1'h0, _state_req_needs_wb_r_T_103}; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_107 = _state_req_needs_wb_r_T_70 == 4'h6; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_108 = ~_state_req_needs_wb_r_T_107 & _state_req_needs_wb_r_T_104; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_109 = _state_req_needs_wb_r_T_107 ? 3'h0 : _state_req_needs_wb_r_T_105; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_110 = _state_req_needs_wb_r_T_107 ? 2'h1 : _state_req_needs_wb_r_T_106; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_111 = _state_req_needs_wb_r_T_70 == 4'h7; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_112 = _state_req_needs_wb_r_T_111 \| _state_req_needs_wb_r_T_108; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_113 = _state_req_needs_wb_r_T_111 ? 3'h0 : _state_req_needs_wb_r_T_109; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_114 = _state_req_needs_wb_r_T_111 ? 2'h1 : _state_req_needs_wb_r_T_110; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_115 = _state_req_needs_wb_r_T_70 == 4'h0; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_116 = ~_state_req_needs_wb_r_T_115 & _state_req_needs_wb_r_T_112; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_117 = _state_req_needs_wb_r_T_115 ? 3'h5 : _state_req_needs_wb_r_T_113; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_118 = _state_req_needs_wb_r_T_115 ? 2'h0 : _state_req_needs_wb_r_T_114; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_119 = _state_req_needs_wb_r_T_70 == 4'h1; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_120 = ~_state_req_needs_wb_r_T_119 & _state_req_needs_wb_r_T_116; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_121 = _state_req_needs_wb_r_T_119 ? 3'h4 : _state_req_needs_wb_r_T_117; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_122 = _state_req_needs_wb_r_T_119 ? 2'h1 : _state_req_needs_wb_r_T_118; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_123 = _state_req_needs_wb_r_T_70 == 4'h2; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_124 = ~_state_req_needs_wb_r_T_123 & _state_req_needs_wb_r_T_120; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_125 = _state_req_needs_wb_r_T_123 ? 3'h3 : _state_req_needs_wb_r_T_121; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_126 = _state_req_needs_wb_r_T_123 ? 2'h2 : _state_req_needs_wb_r_T_122; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_127 = _state_req_needs_wb_r_T_70 == 4'h3; // @[Misc.scala:56:20] wire state_req_needs_wb_r_1_1 = _state_req_needs_wb_r_T_127 \| _state_req_needs_wb_r_T_124; // @[Misc.scala:38:9, :56:20] wire [2:0] state_req_needs_wb_r_2_1 = _state_req_needs_wb_r_T_127 ? 3'h3 : _state_req_needs_wb_r_T_125; // @[Misc.scala:38:36, :56:20] wire [1:0] state_req_needs_wb_r_3_1 = _state_req_needs_wb_r_T_127 ? 2'h2 : _state_req_needs_wb_r_T_126; // @[Misc.scala:38:63, :56:20] wire [1:0] state_req_needs_wb_meta_1_state = state_req_needs_wb_r_3_1; // @[Misc.scala:38:63] wire _state_r_c_cat_T_52 = _state_r_c_cat_T_50 \| _state_r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_54 = _state_r_c_cat_T_52 \| _state_r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_59 = _state_r_c_cat_T_55 \| _state_r_c_cat_T_56; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_60 = _state_r_c_cat_T_59 \| _state_r_c_cat_T_57; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_61 = _state_r_c_cat_T_60 \| _state_r_c_cat_T_58; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_67 = _state_r_c_cat_T_62 \| _state_r_c_cat_T_63; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_68 = _state_r_c_cat_T_67 \| _state_r_c_cat_T_64; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_69 = _state_r_c_cat_T_68 \| _state_r_c_cat_T_65; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_70 = _state_r_c_cat_T_69 \| _state_r_c_cat_T_66; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_71 = _state_r_c_cat_T_61 \| _state_r_c_cat_T_70; // @[package.scala:81:59] wire _state_r_c_cat_T_72 = _state_r_c_cat_T_54 \| _state_r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_75 = _state_r_c_cat_T_73 \| _state_r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_77 = _state_r_c_cat_T_75 \| _state_r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_82 = _state_r_c_cat_T_78 \| _state_r_c_cat_T_79; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_83 = _state_r_c_cat_T_82 \| _state_r_c_cat_T_80; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_84 = _state_r_c_cat_T_83 \| _state_r_c_cat_T_81; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_90 = _state_r_c_cat_T_85 \| _state_r_c_cat_T_86; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_91 = _state_r_c_cat_T_90 \| _state_r_c_cat_T_87; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_92 = _state_r_c_cat_T_91 \| _state_r_c_cat_T_88; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_93 = _state_r_c_cat_T_92 \| _state_r_c_cat_T_89; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_94 = _state_r_c_cat_T_84 \| _state_r_c_cat_T_93; // @[package.scala:81:59] wire _state_r_c_cat_T_95 = _state_r_c_cat_T_77 \| _state_r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_97 = _state_r_c_cat_T_95 \| _state_r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}] wire _state_r_c_cat_T_99 = _state_r_c_cat_T_97 \| _state_r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}] wire [1:0] state_r_c_1 = {_state_r_c_cat_T_72, _state_r_c_cat_T_99}; // @[Metadata.scala:29:18] wire [3:0] _state_r_T_59 = {state_r_c_1, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19] wire _state_r_T_84 = _state_r_T_59 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _state_r_T_86 = {1'h0, _state_r_T_84}; // @[Misc.scala:35:36, :49:20] wire _state_r_T_87 = _state_r_T_59 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _state_r_T_89 = _state_r_T_87 ? 2'h2 : _state_r_T_86; // @[Misc.scala:35:36, :49:20] wire _state_r_T_90 = _state_r_T_59 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _state_r_T_92 = _state_r_T_90 ? 2'h1 : _state_r_T_89; // @[Misc.scala:35:36, :49:20] wire _state_r_T_93 = _state_r_T_59 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _state_r_T_95 = _state_r_T_93 ? 2'h2 : _state_r_T_92; // @[Misc.scala:35:36, :49:20] wire _state_r_T_96 = _state_r_T_59 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _state_r_T_98 = _state_r_T_96 ? 2'h0 : _state_r_T_95; // @[Misc.scala:35:36, :49:20] wire _state_r_T_99 = _state_r_T_59 == 4'hE; // @[Misc.scala:49:20] wire _state_r_T_100 = _state_r_T_99; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_101 = _state_r_T_99 ? 2'h3 : _state_r_T_98; // @[Misc.scala:35:36, :49:20] wire _state_r_T_102 = &_state_r_T_59; // @[Misc.scala:49:20] wire _state_r_T_103 = _state_r_T_102 \| _state_r_T_100; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_104 = _state_r_T_102 ? 2'h3 : _state_r_T_101; // @[Misc.scala:35:36, :49:20] wire _state_r_T_105 = _state_r_T_59 == 4'h6; // @[Misc.scala:49:20] wire _state_r_T_106 = _state_r_T_105 \| _state_r_T_103; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_107 = _state_r_T_105 ? 2'h2 : _state_r_T_104; // @[Misc.scala:35:36, :49:20] wire _state_r_T_108 = _state_r_T_59 == 4'h7; // @[Misc.scala:49:20] wire _state_r_T_109 = _state_r_T_108 \| _state_r_T_106; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_110 = _state_r_T_108 ? 2'h3 : _state_r_T_107; // @[Misc.scala:35:36, :49:20] wire _state_r_T_111 = _state_r_T_59 == 4'h1; // @[Misc.scala:49:20] wire _state_r_T_112 = _state_r_T_111 \| _state_r_T_109; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_113 = _state_r_T_111 ? 2'h1 : _state_r_T_110; // @[Misc.scala:35:36, :49:20] wire _state_r_T_114 = _state_r_T_59 == 4'h2; // @[Misc.scala:49:20] wire _state_r_T_115 = _state_r_T_114 \| _state_r_T_112; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_116 = _state_r_T_114 ? 2'h2 : _state_r_T_113; // @[Misc.scala:35:36, :49:20] wire _state_r_T_117 = _state_r_T_59 == 4'h3; // @[Misc.scala:49:20] wire state_is_hit_1 = _state_r_T_117 \| _state_r_T_115; // @[Misc.scala:35:9, :49:20] wire [1:0] state_r_2_1 = _state_r_T_117 ? 2'h3 : _state_r_T_116; // @[Misc.scala:35:36, :49:20] wire [1:0] state_coh_on_hit_1_state = state_r_2_1; // @[Misc.scala:35:36] wire _state_T_39 = _state_T_37 \| _state_T_38; // @[Consts.scala:90:{32,42,49}] wire _state_T_41 = _state_T_39 \| _state_T_40; // @[Consts.scala:90:{42,59,66}] wire _state_T_46 = _state_T_42 \| _state_T_43; // @[package.scala:16:47, :81:59] wire _state_T_47 = _state_T_46 \| _state_T_44; // @[package.scala:16:47, :81:59] wire _state_T_48 = _state_T_47 \| _state_T_45; // @[package.scala:16:47, :81:59] wire _state_T_54 = _state_T_49 \| _state_T_50; // @[package.scala:16:47, :81:59] wire _state_T_55 = _state_T_54 \| _state_T_51; // @[package.scala:16:47, :81:59] wire _state_T_56 = _state_T_55 \| _state_T_52; // @[package.scala:16:47, :81:59] wire _state_T_57 = _state_T_56 \| _state_T_53; // @[package.scala:16:47, :81:59] wire _state_T_58 = _state_T_48 \| _state_T_57; // @[package.scala:81:59] wire _state_T_59 = _state_T_41 \| _state_T_58; // @[Consts.scala:87:44, :90:{59,76}] wire _state_T_61 = ~_state_T_60; // @[mshrs.scala:201:15] wire _state_T_62 = ~_state_T_59; // @[Consts.scala:90:76]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File Arbiter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ object TLArbiter { // (valids, select) => readys type Policy = (Integer, UInt, Bool) => UInt val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0) val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width)) val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else { val valid = valids(width-1, 0) assert (valid === valids) val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0)) val filter = Cat(valid & ~mask, valid) val unready = (rightOR(filter, width2, width) >> 1) \| (mask << width) val readys = ~((unready >> width) & unready(width-1, 0)) when (select && valid.orR) { mask := leftOR(readys & valid, width) } readys(width-1, 0) } def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = { apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_) } def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])): Unit = { if (sources.isEmpty) { sink.bits := DontCare } else if (sources.size == 1) { sink :<>= sources.head._2 } else { val pairs = sources.toList val beatsIn = pairs.map(_._1) val sourcesIn = pairs.map(_._2) // The number of beats which remain to be sent val beatsLeft = RegInit(0.U) val idle = beatsLeft === 0.U val latch = idle && sink.ready // winner (if any) claims sink // Who wants access to the sink? val valids = sourcesIn.map(_.valid) // Arbitrate amongst the requests val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools) // Which request wins arbitration? val winner = VecInit((readys zip valids) map { case (r,v) => r&&v }) // Confirm the policy works properly require (readys.size == valids.size) // Never two winners val prefixOR = winner.scanLeft(false.B)(_\|\|_).init assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _}) // If there was any request, there is a winner assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_)) // Track remaining beats val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) } val initBeats = maskedBeats.reduce(_ \| _) // no winner => 0 beats beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire) // The one-hot source granted access in the previous cycle val state = RegInit(VecInit(Seq.fill(sources.size)(false.B))) val muxState = Mux(idle, winner, state) state := muxState val allowed = Mux(idle, readys, state) (sourcesIn zip allowed) foreach { case (s, r) => s.ready := sink.ready && r } sink.valid := Mux(idle, valids.reduce(_\|\|_), Mux1H(state, valids)) sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits)) } } } // Synthesizable unit tests import freechips.rocketchip.unittest._ abstract class DecoupledArbiterTest( policy: TLArbiter.Policy, txns: Int, timeout: Int, val numSources: Int, beatsLeftFromIdx: Int => UInt) (implicit p: Parameters) extends UnitTest(timeout) { val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W)))) dontTouch(sources.suggestName("sources")) val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W))) dontTouch(sink.suggestName("sink")) val count = RegInit(0.U(log2Ceil(txns).W)) val lfsr = LFSR(16, true.B) sources.zipWithIndex.map { case (z, i) => z.bits := i.U } TLArbiter(policy)(sink, sources.zipWithIndex.map { case (z, i) => (beatsLeftFromIdx(i), z) }:_) count := count + 1.U io.finished := count >= txns.U } /** This tests that when a specific pattern of source valids are driven, * a new index from amongst that pattern is always selected, * unless one of those sources takes multiple beats, * in which case the same index should be selected until the arbiter goes idle. / class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false) (implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U) { val lastWinner = RegInit((numSources+1).U) val beatsLeft = RegInit(0.U(log2Ceil(numSources).W)) val first = lastWinner > numSources.U val valid = lfsr(0) val ready = lfsr(15) sink.ready := ready sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid) } when (sink.fire) { if (print) { printf("TestRobin: %d\n", sink.bits) } when (beatsLeft === 0.U) { assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.") lastWinner := sink.bits beatsLeft := sink.bits } .otherwise { assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats") beatsLeft := beatsLeft - 1.U } } if (print) { when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) } } } /* This tests that the lowest index is always selected across random single cycle transactions. / class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertLowest(id: Int): Unit = { when (sources(id).valid) { assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) } } /* This tests that the highest index is always selected across random single cycle transactions. / class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertHighest(id: Int): Unit = { when (sources(id).valid) { assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size node.out.size) > (832)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source \| r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source \| r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink \| r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ \|\| _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) \|\| o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) \|\| o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) \|\| (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }	module TLXbar_mbus_i1_o2_a32d64s3k1z3u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire out_1_d_bits_sink; // @[Xbar.scala:216:19] wire [2:0] in_0_d_bits_source; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_source; // @[Xbar.scala:159:18] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_ready_0 = auto_anon_out_1_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_valid_0 = auto_anon_out_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_opcode_0 = auto_anon_out_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_1_d_bits_param_0 = auto_anon_out_1_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_size_0 = auto_anon_out_1_d_bits_size; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_source_0 = auto_anon_out_1_d_bits_source; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_sink_0 = auto_anon_out_1_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_denied_0 = auto_anon_out_1_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_1_d_bits_data_0 = auto_anon_out_1_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_corrupt_0 = auto_anon_out_1_d_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_ready_0 = auto_anon_out_0_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_valid_0 = auto_anon_out_0_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_opcode_0 = auto_anon_out_0_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_size_0 = auto_anon_out_0_d_bits_size; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_source_0 = auto_anon_out_0_d_bits_source; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_denied_0 = auto_anon_out_0_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_0_d_bits_data_0 = auto_anon_out_0_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_corrupt_0 = auto_anon_out_0_d_bits_corrupt; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire [1:0] auto_anon_out_0_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] out_0_d_bits_param = 2'h0; // @[Xbar.scala:216:19] wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _portsBIO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_1_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsDIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _in_0_d_bits_T_18 = 2'h0; // @[Mux.scala:30:73] wire auto_anon_out_0_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire out_0_d_bits_sink = 1'h0; // @[Xbar.scala:216:19] wire _out_0_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53] wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire _beatsBO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T_1 = 1'h0; // @[Edges.scala:97:37] wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire portsDIO_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_filtered_1_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _in_0_d_bits_T_9 = 1'h0; // @[Mux.scala:30:73] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_1 = 1'h1; // @[Xbar.scala:308:107] wire _requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestBOI_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_1_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_1_0 = 1'h1; // @[Parameters.scala:56:48] wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire beatsBO_opdata_1 = 1'h1; // @[Edges.scala:97:28] wire _portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsBIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire [63:0] _addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _requestBOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsBIO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsCOI_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [31:0] _addressC_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _addressC_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _requestCIO_T = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestBOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsCI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _beatsCI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _portsBIO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] portsBIO_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsBIO_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] portsBIO_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsCOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _portsCOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] portsCOI_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_source = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_source = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_bits_source = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_1_bits_source = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_uncommonBits_T = 3'h0; // @[Parameters.scala:52:29] wire [2:0] requestBOI_uncommonBits = 3'h0; // @[Parameters.scala:52:56] wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_2_bits_source = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_3_bits_source = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_uncommonBits_T_1 = 3'h0; // @[Parameters.scala:52:29] wire [2:0] requestBOI_uncommonBits_1 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_bits_source = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_1_bits_source = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsBO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_2_bits_source = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_3_bits_source = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode_1 = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_source = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_source = 3'h0; // @[Bundles.scala:265:61] wire [2:0] beatsCI_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsCI_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_bits_source = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _portsBIO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _portsBIO_WIRE_1_bits_source = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_0_bits_source = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsBIO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_2_bits_source = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _portsBIO_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _portsBIO_WIRE_3_bits_source = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_0_bits_source = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_source = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_source = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_source = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_source = 3'h0; // @[Xbar.scala:352:24] wire [7:0] _requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _requestBOI_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [7:0] _portsBIO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_1_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [5:0] _beatsBO_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsBO_decode_T_5 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsCI_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsBO_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsBO_decode_T_4 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsCI_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _beatsBO_decode_T = 13'h3F; // @[package.scala:243:71] wire [12:0] _beatsBO_decode_T_3 = 13'h3F; // @[package.scala:243:71] wire [12:0] _beatsCI_decode_T = 13'h3F; // @[package.scala:243:71] wire [32:0] _requestCIO_T_1 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire x1_anonOut_a_ready = auto_anon_out_1_a_ready_0; // @[Xbar.scala:74:9] wire x1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [27:0] x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_anonOut_d_ready; // @[MixedNode.scala:542:17] wire x1_anonOut_d_valid = auto_anon_out_1_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_opcode = auto_anon_out_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] x1_anonOut_d_bits_param = auto_anon_out_1_d_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_size = auto_anon_out_1_d_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_source = auto_anon_out_1_d_bits_source_0; // @[Xbar.scala:74:9] wire x1_anonOut_d_bits_sink = auto_anon_out_1_d_bits_sink_0; // @[Xbar.scala:74:9] wire x1_anonOut_d_bits_denied = auto_anon_out_1_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] x1_anonOut_d_bits_data = auto_anon_out_1_d_bits_data_0; // @[Xbar.scala:74:9] wire x1_anonOut_d_bits_corrupt = auto_anon_out_1_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonOut_a_ready = auto_anon_out_0_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_0_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_size = auto_anon_out_0_d_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_source = auto_anon_out_0_d_bits_source_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_denied = auto_anon_out_0_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_0_d_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_corrupt = auto_anon_out_0_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_d_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_d_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_d_bits_source_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_source_0; // @[Xbar.scala:74:9] wire [27:0] auto_anon_out_1_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_1_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_1_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_0_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_ready_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [2:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [2:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9] wire in_0_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_0_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_0_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire out_1_a_ready = x1_anonOut_a_ready; // @[Xbar.scala:216:19] wire out_1_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_valid_0 = x1_anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_opcode_0 = x1_anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_param_0 = x1_anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_size_0 = x1_anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_source_0 = x1_anonOut_a_bits_source; // @[Xbar.scala:74:9] assign auto_anon_out_1_a_bits_address_0 = x1_anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_1_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_mask_0 = x1_anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_1_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_data_0 = x1_anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_1_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_corrupt_0 = x1_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_1_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_1_d_ready_0 = x1_anonOut_d_ready; // @[Xbar.scala:74:9] wire out_1_d_valid = x1_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_opcode = x1_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_1_d_bits_param = x1_anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_size = x1_anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_source = x1_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire _out_1_d_bits_sink_T = x1_anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire out_1_d_bits_denied = x1_anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] out_1_d_bits_data = x1_anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_1_d_bits_corrupt = x1_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T_5 = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_1_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_1_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_1_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _in_0_d_valid_T_4; // @[Arbiter.scala:96:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] _in_0_d_bits_WIRE_param; // @[Mux.scala:30:73] assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_size; // @[Mux.scala:30:73] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_source; // @[Mux.scala:30:73] assign _anonIn_d_bits_source_T = in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18] wire _in_0_d_bits_WIRE_sink; // @[Mux.scala:30:73] assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18] wire _in_0_d_bits_WIRE_denied; // @[Mux.scala:30:73] assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] _in_0_d_bits_WIRE_data; // @[Mux.scala:30:73] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] wire _in_0_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign in_0_a_bits_source = _in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] wire portsAOI_filtered_0_ready = out_0_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_0_ready; // @[Xbar.scala:352:24] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_1 = out_0_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [2:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19] wire [2:0] portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_1_ready = out_1_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_1_valid; // @[Xbar.scala:352:24] assign x1_anonOut_a_valid = out_1_a_valid; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_opcode = out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_param = out_1_a_bits_param; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_size = out_1_a_bits_size; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_source = out_1_a_bits_source; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_mask = out_1_a_bits_mask; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_data = out_1_a_bits_data; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_corrupt = out_1_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_1_0_ready; // @[Xbar.scala:352:24] assign x1_anonOut_d_ready = out_1_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_3 = out_1_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_1_0_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_1_0_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_0_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [2:0] _requestDOI_uncommonBits_T_1 = out_1_d_bits_source; // @[Xbar.scala:216:19] wire [2:0] portsDIO_filtered_1_0_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_1_0_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire [31:0] out_1_a_bits_address; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_address = out_1_a_bits_address[27:0]; // @[Xbar.scala:216:19, :222:41] assign out_1_d_bits_sink = _out_1_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] wire [31:0] _requestAIO_T = in_0_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_2 = _requestAIO_T_1 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_3 = _requestAIO_T_2; // @[Parameters.scala:137:46] wire _requestAIO_T_4 = _requestAIO_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_0 = _requestAIO_T_4; // @[Xbar.scala:307:107] wire _portsAOI_filtered_0_valid_T = requestAIO_0_0; // @[Xbar.scala:307:107, :355:54] wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_7 = _requestAIO_T_6 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_8 = _requestAIO_T_7; // @[Parameters.scala:137:46] wire _requestAIO_T_9 = _requestAIO_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_1 = _requestAIO_T_9; // @[Xbar.scala:307:107] wire _portsAOI_filtered_1_valid_T = requestAIO_0_1; // @[Xbar.scala:307:107, :355:54] wire [2:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [2:0] requestDOI_uncommonBits_1 = _requestDOI_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [12:0] _beatsAI_decode_T = 13'h3F << in_0_a_bits_size; // @[package.scala:243:71] wire [5:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] beatsAI_decode = _beatsAI_decode_T_2[5:3]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [12:0] _beatsDO_decode_T = 13'h3F << out_0_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode = _beatsDO_decode_T_2[5:3]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire [12:0] _beatsDO_decode_T_3 = 13'h3F << out_1_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_4 = _beatsDO_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_5 = ~_beatsDO_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode_1 = _beatsDO_decode_T_5[5:3]; // @[package.scala:243:46] wire beatsDO_opdata_1 = out_1_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_1 = beatsDO_opdata_1 ? beatsDO_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign out_0_a_valid = portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_opcode = portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_param = portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_size = portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_source = portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_address = portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_mask = portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_data = portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_corrupt = portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:355:40] assign out_1_a_valid = portsAOI_filtered_1_valid; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_opcode = portsAOI_filtered_1_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_param = portsAOI_filtered_1_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_size = portsAOI_filtered_1_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_source = portsAOI_filtered_1_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_address = portsAOI_filtered_1_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_mask = portsAOI_filtered_1_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_data = portsAOI_filtered_1_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_corrupt = portsAOI_filtered_1_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign _portsAOI_filtered_0_valid_T_1 = in_0_a_valid & _portsAOI_filtered_0_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_1_valid_T_1 = in_0_a_valid & _portsAOI_filtered_1_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_1_valid = _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsAOI_in_0_a_ready_T = requestAIO_0_0 & portsAOI_filtered_0_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_1 = requestAIO_0_1 & portsAOI_filtered_1_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_2 = _portsAOI_in_0_a_ready_T \| _portsAOI_in_0_a_ready_T_1; // @[Mux.scala:30:73] assign _portsAOI_in_0_a_ready_WIRE = _portsAOI_in_0_a_ready_T_2; // @[Mux.scala:30:73] assign in_0_a_ready = _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] assign out_0_d_ready = portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] assign out_1_d_ready = portsDIO_filtered_1_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_1_0_valid = _portsDIO_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] reg [2:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 3'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & in_0_d_ready; // @[Xbar.scala:159:18] wire [1:0] _readys_T = {portsDIO_filtered_1_0_valid, portsDIO_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] \| _readys_unready_T}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} \| _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = \|readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_3 = _readys_mask_T \| _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 \| winner_1; // @[Arbiter.scala:71:27, :76:48] wire _in_0_d_valid_T = portsDIO_filtered_0_valid \| portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24]
Generate the Verilog code corresponding to the following Chisel files. File MSHR.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import freechips.rocketchip.tilelink._ import TLPermissions._ import TLMessages._ import MetaData._ import chisel3.PrintableHelper import chisel3.experimental.dataview._ class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val a = Valid(new SourceARequest(params)) val b = Valid(new SourceBRequest(params)) val c = Valid(new SourceCRequest(params)) val d = Valid(new SourceDRequest(params)) val e = Valid(new SourceERequest(params)) val x = Valid(new SourceXRequest(params)) val dir = Valid(new DirectoryWrite(params)) val reload = Bool() // get next request via allocate (if any) } class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val way = UInt(params.wayBits.W) val blockB = Bool() val nestB = Bool() val blockC = Bool() val nestC = Bool() } class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val b_toN = Bool() // nested Probes may unhit us val b_toB = Bool() // nested Probes may demote us val b_clr_dirty = Bool() // nested Probes clear dirty val c_set_dirty = Bool() // nested Releases MAY set dirty } sealed trait CacheState { val code = CacheState.index.U CacheState.index = CacheState.index + 1 } object CacheState { var index = 0 } case object S_INVALID extends CacheState case object S_BRANCH extends CacheState case object S_BRANCH_C extends CacheState case object S_TIP extends CacheState case object S_TIP_C extends CacheState case object S_TIP_CD extends CacheState case object S_TIP_D extends CacheState case object S_TRUNK_C extends CacheState case object S_TRUNK_CD extends CacheState class MSHR(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup val status = Valid(new MSHRStatus(params)) val schedule = Decoupled(new ScheduleRequest(params)) val sinkc = Flipped(Valid(new SinkCResponse(params))) val sinkd = Flipped(Valid(new SinkDResponse(params))) val sinke = Flipped(Valid(new SinkEResponse(params))) val nestedwb = Flipped(new NestedWriteback(params)) }) val request_valid = RegInit(false.B) val request = Reg(new FullRequest(params)) val meta_valid = RegInit(false.B) val meta = Reg(new DirectoryResult(params)) // Define which states are valid when (meta_valid) { when (meta.state === INVALID) { assert (!meta.clients.orR) assert (!meta.dirty) } when (meta.state === BRANCH) { assert (!meta.dirty) } when (meta.state === TRUNK) { assert (meta.clients.orR) assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one } when (meta.state === TIP) { // noop } } // Completed transitions (s_ = scheduled), (w_ = waiting) val s_rprobe = RegInit(true.B) // B val w_rprobeackfirst = RegInit(true.B) val w_rprobeacklast = RegInit(true.B) val s_release = RegInit(true.B) // CW w_rprobeackfirst val w_releaseack = RegInit(true.B) val s_pprobe = RegInit(true.B) // B val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1] val s_flush = RegInit(true.B) // X w_releaseack val w_grantfirst = RegInit(true.B) val w_grantlast = RegInit(true.B) val w_grant = RegInit(true.B) // first \| last depending on wormhole val w_pprobeackfirst = RegInit(true.B) val w_pprobeacklast = RegInit(true.B) val w_pprobeack = RegInit(true.B) // first \| last depending on wormhole val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_) val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD val s_execute = RegInit(true.B) // D w_pprobeack, w_grant val w_grantack = RegInit(true.B) val s_writeback = RegInit(true.B) // W w_* // [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall) // However, inB and outC are higher priority than outB, so s_release and s_pprobe // may be safely issued while blockB. Thus we must NOT try to schedule the // potentially stuck s_acquire with either of them (scheduler is all or none). // Meta-data that we discover underway val sink = Reg(UInt(params.outer.bundle.sinkBits.W)) val gotT = Reg(Bool()) val bad_grant = Reg(Bool()) val probes_done = Reg(UInt(params.clientBits.W)) val probes_toN = Reg(UInt(params.clientBits.W)) val probes_noT = Reg(Bool()) // When a nested transaction completes, update our meta data when (meta_valid && meta.state =/= INVALID && io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) { when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B } when (io.nestedwb.c_set_dirty) { meta.dirty := true.B } when (io.nestedwb.b_toB) { meta.state := BRANCH } when (io.nestedwb.b_toN) { meta.hit := false.B } } // Scheduler status io.status.valid := request_valid io.status.bits.set := request.set io.status.bits.tag := request.tag io.status.bits.way := meta.way io.status.bits.blockB := !meta_valid \|\| ((!w_releaseack \|\| !w_rprobeacklast \|\| !w_pprobeacklast) && !w_grantfirst) io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst // The above rules ensure we will block and not nest an outer probe while still doing our // own inner probes. Thus every probe wakes exactly one MSHR. io.status.bits.blockC := !meta_valid io.status.bits.nestC := meta_valid && (!w_rprobeackfirst \|\| !w_pprobeackfirst \|\| !w_grantfirst) // The w_grantfirst in nestC is necessary to deal with: // acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock // ... this is possible because the release+probe can be for same set, but different tag // We can only demand: block, nest, or queue assert (!io.status.bits.nestB \|\| !io.status.bits.blockB) assert (!io.status.bits.nestC \|\| !io.status.bits.blockC) // Scheduler requests val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe io.schedule.bits.b.valid := !s_rprobe \|\| !s_pprobe io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) \|\| (!s_probeack && w_pprobeackfirst) io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant io.schedule.bits.e.valid := !s_grantack && w_grantfirst io.schedule.bits.x.valid := !s_flush && w_releaseack io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) \|\| (!s_writeback && no_wait) io.schedule.bits.reload := no_wait io.schedule.valid := io.schedule.bits.a.valid \|\| io.schedule.bits.b.valid \|\| io.schedule.bits.c.valid \|\| io.schedule.bits.d.valid \|\| io.schedule.bits.e.valid \|\| io.schedule.bits.x.valid \|\| io.schedule.bits.dir.valid // Schedule completions when (io.schedule.ready) { s_rprobe := true.B when (w_rprobeackfirst) { s_release := true.B } s_pprobe := true.B when (s_release && s_pprobe) { s_acquire := true.B } when (w_releaseack) { s_flush := true.B } when (w_pprobeackfirst) { s_probeack := true.B } when (w_grantfirst) { s_grantack := true.B } when (w_pprobeack && w_grant) { s_execute := true.B } when (no_wait) { s_writeback := true.B } // Await the next operation when (no_wait) { request_valid := false.B meta_valid := false.B } } // Resulting meta-data val final_meta_writeback = WireInit(meta) val req_clientBit = params.clientBit(request.source) val req_needT = needT(request.opcode, request.param) val req_acquire = request.opcode === AcquireBlock \|\| request.opcode === AcquirePerm val meta_no_clients = !meta.clients.orR val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT) when (request.prio(2) && (!params.firstLevel).B) { // always a hit final_meta_writeback.dirty := meta.dirty \|\| request.opcode(0) final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state) final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U) final_meta_writeback.hit := true.B // chained requests are hits } .elsewhen (request.control && params.control.B) { // request.prio(0) when (meta.hit) { final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := meta.clients & ~probes_toN } final_meta_writeback.hit := false.B } .otherwise { final_meta_writeback.dirty := (meta.hit && meta.dirty) \|\| !request.opcode(2) final_meta_writeback.state := Mux(req_needT, Mux(req_acquire, TRUNK, TIP), Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH), MuxLookup(meta.state, 0.U(2.W))(Seq( INVALID -> BRANCH, BRANCH -> BRANCH, TRUNK -> TIP, TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP))))) final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) \| Mux(req_acquire, req_clientBit, 0.U) final_meta_writeback.tag := request.tag final_meta_writeback.hit := true.B } when (bad_grant) { when (meta.hit) { // upgrade failed (B -> T) assert (!meta_valid \|\| meta.state === BRANCH) final_meta_writeback.hit := true.B final_meta_writeback.dirty := false.B final_meta_writeback.state := BRANCH final_meta_writeback.clients := meta.clients & ~probes_toN } .otherwise { // failed N -> (T or B) final_meta_writeback.hit := false.B final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := 0.U } } val invalid = Wire(new DirectoryEntry(params)) invalid.dirty := false.B invalid.state := INVALID invalid.clients := 0.U invalid.tag := 0.U // Just because a client says BtoT, by the time we process the request he may be N. // Therefore, we must consult our own meta-data state to confirm he owns the line still. val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR // The client asking us to act is proof they don't have permissions. val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U) io.schedule.bits.a.bits.tag := request.tag io.schedule.bits.a.bits.set := request.set io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB) io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U \|\| !(request.opcode === PutFullData \|\| request.opcode === AcquirePerm) io.schedule.bits.a.bits.source := 0.U io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB))) io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag) io.schedule.bits.b.bits.set := request.set io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release) io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN) io.schedule.bits.c.bits.source := 0.U io.schedule.bits.c.bits.tag := meta.tag io.schedule.bits.c.bits.set := request.set io.schedule.bits.c.bits.way := meta.way io.schedule.bits.c.bits.dirty := meta.dirty io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param, MuxLookup(request.param, request.param)(Seq( NtoB -> Mux(req_promoteT, NtoT, NtoB), BtoT -> Mux(honour_BtoT, BtoT, NtoT), NtoT -> NtoT))) io.schedule.bits.d.bits.sink := 0.U io.schedule.bits.d.bits.way := meta.way io.schedule.bits.d.bits.bad := bad_grant io.schedule.bits.e.bits.sink := sink io.schedule.bits.x.bits.fail := false.B io.schedule.bits.dir.bits.set := request.set io.schedule.bits.dir.bits.way := meta.way io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback)) // Coverage of state transitions def cacheState(entry: DirectoryEntry, hit: Bool) = { val out = WireDefault(0.U) val c = entry.clients.orR val d = entry.dirty switch (entry.state) { is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) } is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) } is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) } is (INVALID) { out := S_INVALID.code } } when (!hit) { out := S_INVALID.code } out } val p = !params.lastLevel // can be probed val c = !params.firstLevel // can be acquired val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read) val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist val f = params.control // flush control register exists val cfg = (p, c, m, r, f) val b = r \|\| p // can reach branch state (via probe downgrade or read-only device) // The cache must be used for something or we would not be here require(c \|\| m) val evict = cacheState(meta, !meta.hit) val before = cacheState(meta, meta.hit) val after = cacheState(final_meta_writeback, true.B) def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}") } else { assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}") } if (cover && f) { params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}") } else { assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}") } } def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}") } else { assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}") } } when ((!s_release && w_rprobeackfirst) && io.schedule.ready) { eviction(S_BRANCH, b) // MMIO read to read-only device eviction(S_BRANCH_C, b && c) // you need children to become C eviction(S_TIP, true) // MMIO read \|\| clean release can lead to this state eviction(S_TIP_C, c) // needs two clients \|\| client + mmio \|\| downgrading client eviction(S_TIP_CD, c) // needs two clients \|\| client + mmio \|\| downgrading client eviction(S_TIP_D, true) // MMIO write \|\| dirty release lead here eviction(S_TRUNK_C, c) // acquire for write eviction(S_TRUNK_CD, c) // dirty release then reacquire } when ((!s_writeback && no_wait) && io.schedule.ready) { transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches transition(S_INVALID, S_TIP, m) // MMIO read transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_INVALID, S_TIP_D, m) // MMIO write transition(S_INVALID, S_TRUNK_C, c) // acquire transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions) transition(S_BRANCH, S_BRANCH_C, b && c) // acquire transition(S_BRANCH, S_TIP, b && m) // prefetch write transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_TIP_D, b && m) // MMIO write transition(S_BRANCH, S_TRUNK_C, b && c) // acquire transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH_C, S_INVALID, b && c && p) transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional) transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_TIP, S_INVALID, p) transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately transition(S_TIP, S_TRUNK_C, c) // acquire transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately transition(S_TIP_C, S_INVALID, c && p) transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_TIP, c) // probed while MMIO read \|\| clean release (optional) transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_TIP_C, S_TRUNK_C, c) // acquire transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty transition(S_TIP_D, S_INVALID, p) transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared transition(S_TIP_D, S_TIP, p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired transition(S_TIP_D, S_TRUNK_CD, c) // acquire transition(S_TIP_CD, S_INVALID, c && p) transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_CD, S_TIP_D, c) // MMIO write \|\| clean release (optional) transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire transition(S_TIP_CD, S_TRUNK_CD, c) // acquire transition(S_TRUNK_C, S_INVALID, c && p) transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_TIP, c) // MMIO read \|\| clean release (optional) transition(S_TRUNK_C, S_TIP_C, c) // bounce shared transition(S_TRUNK_C, S_TIP_D, c) // dirty release transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce transition(S_TRUNK_CD, S_INVALID, c && p) transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TRUNK_CD, S_TIP_D, c) // dirty release transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire } // Handle response messages val probe_bit = params.clientBit(io.sinkc.bits.source) val last_probe = (probes_done \| probe_bit) === (meta.clients & ~excluded_client) val probe_toN = isToN(io.sinkc.bits.param) if (!params.firstLevel) when (io.sinkc.valid) { params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B") params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B") // Caution: the probe matches us only in set. // We would never allow an outer probe to nest until both w_[rp]probeack complete, so // it is safe to just unguardedly update the probe FSM. probes_done := probes_done \| probe_bit probes_toN := probes_toN \| Mux(probe_toN, probe_bit, 0.U) probes_noT := probes_noT \|\| io.sinkc.bits.param =/= TtoT w_rprobeackfirst := w_rprobeackfirst \|\| last_probe w_rprobeacklast := w_rprobeacklast \|\| (last_probe && io.sinkc.bits.last) w_pprobeackfirst := w_pprobeackfirst \|\| last_probe w_pprobeacklast := w_pprobeacklast \|\| (last_probe && io.sinkc.bits.last) // Allow wormhole routing from sinkC if the first request beat has offset 0 val set_pprobeack = last_probe && (io.sinkc.bits.last \|\| request.offset === 0.U) w_pprobeack := w_pprobeack \|\| set_pprobeack params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data") params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data") // However, meta-data updates need to be done more cautiously when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!! } when (io.sinkd.valid) { when (io.sinkd.bits.opcode === Grant \|\| io.sinkd.bits.opcode === GrantData) { sink := io.sinkd.bits.sink w_grantfirst := true.B w_grantlast := io.sinkd.bits.last // Record if we need to prevent taking ownership bad_grant := io.sinkd.bits.denied // Allow wormhole routing for requests whose first beat has offset 0 w_grant := request.offset === 0.U \|\| io.sinkd.bits.last params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data") params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data") gotT := io.sinkd.bits.param === toT } .elsewhen (io.sinkd.bits.opcode === ReleaseAck) { w_releaseack := true.B } } when (io.sinke.valid) { w_grantack := true.B } // Bootstrap new requests val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits) val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits) val new_request = Mux(io.allocate.valid, allocate_as_full, request) val new_needT = needT(new_request.opcode, new_request.param) val new_clientBit = params.clientBit(new_request.source) val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U) val prior = cacheState(final_meta_writeback, true.B) def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}") } else { assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}") } } when (io.allocate.valid && io.allocate.bits.repeat) { bypass(S_INVALID, f \|\| p) // Can lose permissions (probe/flush) bypass(S_BRANCH, b) // MMIO read to read-only device bypass(S_BRANCH_C, b && c) // you need children to become C bypass(S_TIP, true) // MMIO read \|\| clean release can lead to this state bypass(S_TIP_C, c) // needs two clients \|\| client + mmio \|\| downgrading client bypass(S_TIP_CD, c) // needs two clients \|\| client + mmio \|\| downgrading client bypass(S_TIP_D, true) // MMIO write \|\| dirty release lead here bypass(S_TRUNK_C, c) // acquire for write bypass(S_TRUNK_CD, c) // dirty release then reacquire } when (io.allocate.valid) { assert (!request_valid \|\| (no_wait && io.schedule.fire)) request_valid := true.B request := io.allocate.bits } // Create execution plan when (io.directory.valid \|\| (io.allocate.valid && io.allocate.bits.repeat)) { meta_valid := true.B meta := new_meta probes_done := 0.U probes_toN := 0.U probes_noT := false.B gotT := false.B bad_grant := false.B // These should already be either true or turning true // We clear them here explicitly to simplify the mux tree s_rprobe := true.B w_rprobeackfirst := true.B w_rprobeacklast := true.B s_release := true.B w_releaseack := true.B s_pprobe := true.B s_acquire := true.B s_flush := true.B w_grantfirst := true.B w_grantlast := true.B w_grant := true.B w_pprobeackfirst := true.B w_pprobeacklast := true.B w_pprobeack := true.B s_probeack := true.B s_grantack := true.B s_execute := true.B w_grantack := true.B s_writeback := true.B // For C channel requests (ie: Release[Data]) when (new_request.prio(2) && (!params.firstLevel).B) { s_execute := false.B // Do we need to go dirty? when (new_request.opcode(0) && !new_meta.dirty) { s_writeback := false.B } // Does our state change? when (isToB(new_request.param) && new_meta.state === TRUNK) { s_writeback := false.B } // Do our clients change? when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) { s_writeback := false.B } assert (new_meta.hit) } // For X channel requests (ie: flush) .elsewhen (new_request.control && params.control.B) { // new_request.prio(0) s_flush := false.B // Do we need to actually do something? when (new_meta.hit) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } } // For A channel requests .otherwise { // new_request.prio(0) && !new_request.control s_execute := false.B // Do we need an eviction? when (!new_meta.hit && new_meta.state =/= INVALID) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } // Do we need an acquire? when (!new_meta.hit \|\| (new_meta.state === BRANCH && new_needT)) { s_acquire := false.B w_grantfirst := false.B w_grantlast := false.B w_grant := false.B s_grantack := false.B s_writeback := false.B } // Do we need a probe? when ((!params.firstLevel).B && (new_meta.hit && (new_needT \|\| new_meta.state === TRUNK) && (new_meta.clients & ~new_skipProbe) =/= 0.U)) { s_pprobe := false.B w_pprobeackfirst := false.B w_pprobeacklast := false.B w_pprobeack := false.B s_writeback := false.B } // Do we need a grantack? when (new_request.opcode === AcquireBlock \|\| new_request.opcode === AcquirePerm) { w_grantack := false.B s_writeback := false.B } // Becomes dirty? when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) { s_writeback := false.B } } } } File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relListscache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_\|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x \| 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ \|\| _) (matches, bits.U) } expanded \| Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) \|\| (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) \|\| ((opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm \|\| opcode === TLMessages.Get \|\| (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN \|\| param === TLPermissions.BtoN \|\| param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB \|\| param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle	module MSHR_4( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input [5:0] io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire [5:0] final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire [5:0] io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [5:0] invalid_clients = 6'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire [5:0] _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire [5:0] _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg [5:0] meta_clients; // @[MSHR.scala:100:17] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg [5:0] probes_done; // @[MSHR.scala:150:24] reg [5:0] probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire [5:0] _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire _req_clientBit_T = request_source == 6'h24; // @[Parameters.scala:46:9] wire _req_clientBit_T_1 = request_source == 6'h2E; // @[Parameters.scala:46:9] wire _req_clientBit_T_2 = request_source == 6'h2C; // @[Parameters.scala:46:9] wire _req_clientBit_T_3 = request_source == 6'h2A; // @[Parameters.scala:46:9] wire _req_clientBit_T_4 = request_source == 6'h28; // @[Parameters.scala:46:9] wire _req_clientBit_T_5 = request_source == 6'h20; // @[Parameters.scala:46:9] wire [1:0] req_clientBit_lo_hi = {_req_clientBit_T_2, _req_clientBit_T_1}; // @[Parameters.scala:46:9] wire [2:0] req_clientBit_lo = {req_clientBit_lo_hi, _req_clientBit_T}; // @[Parameters.scala:46:9] wire [1:0] req_clientBit_hi_hi = {_req_clientBit_T_5, _req_clientBit_T_4}; // @[Parameters.scala:46:9] wire [2:0] req_clientBit_hi = {req_clientBit_hi_hi, _req_clientBit_T_3}; // @[Parameters.scala:46:9] wire [5:0] req_clientBit = {req_clientBit_hi, req_clientBit_lo}; // @[Parameters.scala:201:10] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire _meta_no_clients_T = \|meta_clients; // @[MSHR.scala:100:17, :220:39] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire [5:0] _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 ? req_clientBit : 6'h0; // @[Parameters.scala:201:10, :282:66] wire [5:0] _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire [5:0] _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire [5:0] _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire [5:0] _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire [5:0] _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire [5:0] _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire [5:0] _final_meta_writeback_clients_T_12 = meta_hit ? _final_meta_writeback_clients_T_11 : 6'h0; // @[MSHR.scala:100:17, :245:{40,64}] wire [5:0] _final_meta_writeback_clients_T_13 = req_acquire ? req_clientBit : 6'h0; // @[Parameters.scala:201:10] wire [5:0] _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire [5:0] _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire [5:0] _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? (meta_hit ? _final_meta_writeback_clients_T_16 : 6'h0) : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire [5:0] _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:201:10] wire _honour_BtoT_T_1 = \|_honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire [5:0] excluded_client = _excluded_client_T_9 ? req_clientBit : 6'h0; // @[Parameters.scala:201:10] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire [5:0] _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = _io_schedule_bits_dir_bits_data_T ? 6'h0 : _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire evict_c = \|meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire before_c = \|meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire after_c = \|final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _probe_bit_T = io_sinkc_bits_source_0 == 6'h24; // @[Parameters.scala:46:9] wire _probe_bit_T_1 = io_sinkc_bits_source_0 == 6'h2E; // @[Parameters.scala:46:9] wire _probe_bit_T_2 = io_sinkc_bits_source_0 == 6'h2C; // @[Parameters.scala:46:9] wire _probe_bit_T_3 = io_sinkc_bits_source_0 == 6'h2A; // @[Parameters.scala:46:9] wire _probe_bit_T_4 = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9] wire _probe_bit_T_5 = io_sinkc_bits_source_0 == 6'h20; // @[Parameters.scala:46:9] wire [1:0] probe_bit_lo_hi = {_probe_bit_T_2, _probe_bit_T_1}; // @[Parameters.scala:46:9] wire [2:0] probe_bit_lo = {probe_bit_lo_hi, _probe_bit_T}; // @[Parameters.scala:46:9] wire [1:0] probe_bit_hi_hi = {_probe_bit_T_5, _probe_bit_T_4}; // @[Parameters.scala:46:9] wire [2:0] probe_bit_hi = {probe_bit_hi_hi, _probe_bit_T_3}; // @[Parameters.scala:46:9] wire [5:0] probe_bit = {probe_bit_hi, probe_bit_lo}; // @[Parameters.scala:201:10] wire [5:0] _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:201:10] wire [5:0] _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire [5:0] _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire [5:0] _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire [5:0] _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire [5:0] _probes_toN_T = probe_toN ? probe_bit : 6'h0; // @[Parameters.scala:201:10, :282:66] wire [5:0] _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [5:0] new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _new_clientBit_T = new_request_source == 6'h24; // @[Parameters.scala:46:9] wire _new_clientBit_T_1 = new_request_source == 6'h2E; // @[Parameters.scala:46:9] wire _new_clientBit_T_2 = new_request_source == 6'h2C; // @[Parameters.scala:46:9] wire _new_clientBit_T_3 = new_request_source == 6'h2A; // @[Parameters.scala:46:9] wire _new_clientBit_T_4 = new_request_source == 6'h28; // @[Parameters.scala:46:9] wire _new_clientBit_T_5 = new_request_source == 6'h20; // @[Parameters.scala:46:9] wire [1:0] new_clientBit_lo_hi = {_new_clientBit_T_2, _new_clientBit_T_1}; // @[Parameters.scala:46:9] wire [2:0] new_clientBit_lo = {new_clientBit_lo_hi, _new_clientBit_T}; // @[Parameters.scala:46:9] wire [1:0] new_clientBit_hi_hi = {_new_clientBit_T_5, _new_clientBit_T_4}; // @[Parameters.scala:46:9] wire [2:0] new_clientBit_hi = {new_clientBit_hi_hi, _new_clientBit_T_3}; // @[Parameters.scala:46:9] wire [5:0] new_clientBit = {new_clientBit_hi, new_clientBit_lo}; // @[Parameters.scala:201:10] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire [5:0] new_skipProbe = _new_skipProbe_T_7 ? new_clientBit : 6'h0; // @[Parameters.scala:201:10, :279:106] wire [3:0] prior; // @[MSHR.scala:314:26] wire prior_c = \|final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry / case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic / val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U \| in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } / Write request logic / // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) \| usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U \| in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) / Read/write response logic / val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied \|\| out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B / Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. / def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } / ReservableListBuffer logic, and associated classes. / class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /* Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. / abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /* A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index / class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) \| validSet used := (used & ~usedClr) \| usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) \| dataIsPresentSet / Reservation logic signals / val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) / Response logic signals / val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) / Reservation logic / reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } / Response logic / // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } / Response unwind logic / // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent \|\| isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind \|\| (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind \|\| (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready \|\| !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire \|\| unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /* Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) \| usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }	module dataMems_97( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File MSHR.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import freechips.rocketchip.tilelink._ import TLPermissions._ import TLMessages._ import MetaData._ import chisel3.PrintableHelper import chisel3.experimental.dataview._ class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val a = Valid(new SourceARequest(params)) val b = Valid(new SourceBRequest(params)) val c = Valid(new SourceCRequest(params)) val d = Valid(new SourceDRequest(params)) val e = Valid(new SourceERequest(params)) val x = Valid(new SourceXRequest(params)) val dir = Valid(new DirectoryWrite(params)) val reload = Bool() // get next request via allocate (if any) } class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val way = UInt(params.wayBits.W) val blockB = Bool() val nestB = Bool() val blockC = Bool() val nestC = Bool() } class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val b_toN = Bool() // nested Probes may unhit us val b_toB = Bool() // nested Probes may demote us val b_clr_dirty = Bool() // nested Probes clear dirty val c_set_dirty = Bool() // nested Releases MAY set dirty } sealed trait CacheState { val code = CacheState.index.U CacheState.index = CacheState.index + 1 } object CacheState { var index = 0 } case object S_INVALID extends CacheState case object S_BRANCH extends CacheState case object S_BRANCH_C extends CacheState case object S_TIP extends CacheState case object S_TIP_C extends CacheState case object S_TIP_CD extends CacheState case object S_TIP_D extends CacheState case object S_TRUNK_C extends CacheState case object S_TRUNK_CD extends CacheState class MSHR(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup val status = Valid(new MSHRStatus(params)) val schedule = Decoupled(new ScheduleRequest(params)) val sinkc = Flipped(Valid(new SinkCResponse(params))) val sinkd = Flipped(Valid(new SinkDResponse(params))) val sinke = Flipped(Valid(new SinkEResponse(params))) val nestedwb = Flipped(new NestedWriteback(params)) }) val request_valid = RegInit(false.B) val request = Reg(new FullRequest(params)) val meta_valid = RegInit(false.B) val meta = Reg(new DirectoryResult(params)) // Define which states are valid when (meta_valid) { when (meta.state === INVALID) { assert (!meta.clients.orR) assert (!meta.dirty) } when (meta.state === BRANCH) { assert (!meta.dirty) } when (meta.state === TRUNK) { assert (meta.clients.orR) assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one } when (meta.state === TIP) { // noop } } // Completed transitions (s_ = scheduled), (w_ = waiting) val s_rprobe = RegInit(true.B) // B val w_rprobeackfirst = RegInit(true.B) val w_rprobeacklast = RegInit(true.B) val s_release = RegInit(true.B) // CW w_rprobeackfirst val w_releaseack = RegInit(true.B) val s_pprobe = RegInit(true.B) // B val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1] val s_flush = RegInit(true.B) // X w_releaseack val w_grantfirst = RegInit(true.B) val w_grantlast = RegInit(true.B) val w_grant = RegInit(true.B) // first \| last depending on wormhole val w_pprobeackfirst = RegInit(true.B) val w_pprobeacklast = RegInit(true.B) val w_pprobeack = RegInit(true.B) // first \| last depending on wormhole val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_) val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD val s_execute = RegInit(true.B) // D w_pprobeack, w_grant val w_grantack = RegInit(true.B) val s_writeback = RegInit(true.B) // W w_* // [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall) // However, inB and outC are higher priority than outB, so s_release and s_pprobe // may be safely issued while blockB. Thus we must NOT try to schedule the // potentially stuck s_acquire with either of them (scheduler is all or none). // Meta-data that we discover underway val sink = Reg(UInt(params.outer.bundle.sinkBits.W)) val gotT = Reg(Bool()) val bad_grant = Reg(Bool()) val probes_done = Reg(UInt(params.clientBits.W)) val probes_toN = Reg(UInt(params.clientBits.W)) val probes_noT = Reg(Bool()) // When a nested transaction completes, update our meta data when (meta_valid && meta.state =/= INVALID && io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) { when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B } when (io.nestedwb.c_set_dirty) { meta.dirty := true.B } when (io.nestedwb.b_toB) { meta.state := BRANCH } when (io.nestedwb.b_toN) { meta.hit := false.B } } // Scheduler status io.status.valid := request_valid io.status.bits.set := request.set io.status.bits.tag := request.tag io.status.bits.way := meta.way io.status.bits.blockB := !meta_valid \|\| ((!w_releaseack \|\| !w_rprobeacklast \|\| !w_pprobeacklast) && !w_grantfirst) io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst // The above rules ensure we will block and not nest an outer probe while still doing our // own inner probes. Thus every probe wakes exactly one MSHR. io.status.bits.blockC := !meta_valid io.status.bits.nestC := meta_valid && (!w_rprobeackfirst \|\| !w_pprobeackfirst \|\| !w_grantfirst) // The w_grantfirst in nestC is necessary to deal with: // acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock // ... this is possible because the release+probe can be for same set, but different tag // We can only demand: block, nest, or queue assert (!io.status.bits.nestB \|\| !io.status.bits.blockB) assert (!io.status.bits.nestC \|\| !io.status.bits.blockC) // Scheduler requests val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe io.schedule.bits.b.valid := !s_rprobe \|\| !s_pprobe io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) \|\| (!s_probeack && w_pprobeackfirst) io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant io.schedule.bits.e.valid := !s_grantack && w_grantfirst io.schedule.bits.x.valid := !s_flush && w_releaseack io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) \|\| (!s_writeback && no_wait) io.schedule.bits.reload := no_wait io.schedule.valid := io.schedule.bits.a.valid \|\| io.schedule.bits.b.valid \|\| io.schedule.bits.c.valid \|\| io.schedule.bits.d.valid \|\| io.schedule.bits.e.valid \|\| io.schedule.bits.x.valid \|\| io.schedule.bits.dir.valid // Schedule completions when (io.schedule.ready) { s_rprobe := true.B when (w_rprobeackfirst) { s_release := true.B } s_pprobe := true.B when (s_release && s_pprobe) { s_acquire := true.B } when (w_releaseack) { s_flush := true.B } when (w_pprobeackfirst) { s_probeack := true.B } when (w_grantfirst) { s_grantack := true.B } when (w_pprobeack && w_grant) { s_execute := true.B } when (no_wait) { s_writeback := true.B } // Await the next operation when (no_wait) { request_valid := false.B meta_valid := false.B } } // Resulting meta-data val final_meta_writeback = WireInit(meta) val req_clientBit = params.clientBit(request.source) val req_needT = needT(request.opcode, request.param) val req_acquire = request.opcode === AcquireBlock \|\| request.opcode === AcquirePerm val meta_no_clients = !meta.clients.orR val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT) when (request.prio(2) && (!params.firstLevel).B) { // always a hit final_meta_writeback.dirty := meta.dirty \|\| request.opcode(0) final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state) final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U) final_meta_writeback.hit := true.B // chained requests are hits } .elsewhen (request.control && params.control.B) { // request.prio(0) when (meta.hit) { final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := meta.clients & ~probes_toN } final_meta_writeback.hit := false.B } .otherwise { final_meta_writeback.dirty := (meta.hit && meta.dirty) \|\| !request.opcode(2) final_meta_writeback.state := Mux(req_needT, Mux(req_acquire, TRUNK, TIP), Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH), MuxLookup(meta.state, 0.U(2.W))(Seq( INVALID -> BRANCH, BRANCH -> BRANCH, TRUNK -> TIP, TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP))))) final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) \| Mux(req_acquire, req_clientBit, 0.U) final_meta_writeback.tag := request.tag final_meta_writeback.hit := true.B } when (bad_grant) { when (meta.hit) { // upgrade failed (B -> T) assert (!meta_valid \|\| meta.state === BRANCH) final_meta_writeback.hit := true.B final_meta_writeback.dirty := false.B final_meta_writeback.state := BRANCH final_meta_writeback.clients := meta.clients & ~probes_toN } .otherwise { // failed N -> (T or B) final_meta_writeback.hit := false.B final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := 0.U } } val invalid = Wire(new DirectoryEntry(params)) invalid.dirty := false.B invalid.state := INVALID invalid.clients := 0.U invalid.tag := 0.U // Just because a client says BtoT, by the time we process the request he may be N. // Therefore, we must consult our own meta-data state to confirm he owns the line still. val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR // The client asking us to act is proof they don't have permissions. val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U) io.schedule.bits.a.bits.tag := request.tag io.schedule.bits.a.bits.set := request.set io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB) io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U \|\| !(request.opcode === PutFullData \|\| request.opcode === AcquirePerm) io.schedule.bits.a.bits.source := 0.U io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB))) io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag) io.schedule.bits.b.bits.set := request.set io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release) io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN) io.schedule.bits.c.bits.source := 0.U io.schedule.bits.c.bits.tag := meta.tag io.schedule.bits.c.bits.set := request.set io.schedule.bits.c.bits.way := meta.way io.schedule.bits.c.bits.dirty := meta.dirty io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param, MuxLookup(request.param, request.param)(Seq( NtoB -> Mux(req_promoteT, NtoT, NtoB), BtoT -> Mux(honour_BtoT, BtoT, NtoT), NtoT -> NtoT))) io.schedule.bits.d.bits.sink := 0.U io.schedule.bits.d.bits.way := meta.way io.schedule.bits.d.bits.bad := bad_grant io.schedule.bits.e.bits.sink := sink io.schedule.bits.x.bits.fail := false.B io.schedule.bits.dir.bits.set := request.set io.schedule.bits.dir.bits.way := meta.way io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback)) // Coverage of state transitions def cacheState(entry: DirectoryEntry, hit: Bool) = { val out = WireDefault(0.U) val c = entry.clients.orR val d = entry.dirty switch (entry.state) { is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) } is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) } is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) } is (INVALID) { out := S_INVALID.code } } when (!hit) { out := S_INVALID.code } out } val p = !params.lastLevel // can be probed val c = !params.firstLevel // can be acquired val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read) val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist val f = params.control // flush control register exists val cfg = (p, c, m, r, f) val b = r \|\| p // can reach branch state (via probe downgrade or read-only device) // The cache must be used for something or we would not be here require(c \|\| m) val evict = cacheState(meta, !meta.hit) val before = cacheState(meta, meta.hit) val after = cacheState(final_meta_writeback, true.B) def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}") } else { assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}") } if (cover && f) { params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}") } else { assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}") } } def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}") } else { assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}") } } when ((!s_release && w_rprobeackfirst) && io.schedule.ready) { eviction(S_BRANCH, b) // MMIO read to read-only device eviction(S_BRANCH_C, b && c) // you need children to become C eviction(S_TIP, true) // MMIO read \|\| clean release can lead to this state eviction(S_TIP_C, c) // needs two clients \|\| client + mmio \|\| downgrading client eviction(S_TIP_CD, c) // needs two clients \|\| client + mmio \|\| downgrading client eviction(S_TIP_D, true) // MMIO write \|\| dirty release lead here eviction(S_TRUNK_C, c) // acquire for write eviction(S_TRUNK_CD, c) // dirty release then reacquire } when ((!s_writeback && no_wait) && io.schedule.ready) { transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches transition(S_INVALID, S_TIP, m) // MMIO read transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_INVALID, S_TIP_D, m) // MMIO write transition(S_INVALID, S_TRUNK_C, c) // acquire transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions) transition(S_BRANCH, S_BRANCH_C, b && c) // acquire transition(S_BRANCH, S_TIP, b && m) // prefetch write transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_TIP_D, b && m) // MMIO write transition(S_BRANCH, S_TRUNK_C, b && c) // acquire transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH_C, S_INVALID, b && c && p) transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional) transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_TIP, S_INVALID, p) transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately transition(S_TIP, S_TRUNK_C, c) // acquire transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately transition(S_TIP_C, S_INVALID, c && p) transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_TIP, c) // probed while MMIO read \|\| clean release (optional) transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_TIP_C, S_TRUNK_C, c) // acquire transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty transition(S_TIP_D, S_INVALID, p) transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared transition(S_TIP_D, S_TIP, p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired transition(S_TIP_D, S_TRUNK_CD, c) // acquire transition(S_TIP_CD, S_INVALID, c && p) transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_CD, S_TIP_D, c) // MMIO write \|\| clean release (optional) transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire transition(S_TIP_CD, S_TRUNK_CD, c) // acquire transition(S_TRUNK_C, S_INVALID, c && p) transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_TIP, c) // MMIO read \|\| clean release (optional) transition(S_TRUNK_C, S_TIP_C, c) // bounce shared transition(S_TRUNK_C, S_TIP_D, c) // dirty release transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce transition(S_TRUNK_CD, S_INVALID, c && p) transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TRUNK_CD, S_TIP_D, c) // dirty release transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire } // Handle response messages val probe_bit = params.clientBit(io.sinkc.bits.source) val last_probe = (probes_done \| probe_bit) === (meta.clients & ~excluded_client) val probe_toN = isToN(io.sinkc.bits.param) if (!params.firstLevel) when (io.sinkc.valid) { params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B") params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B") // Caution: the probe matches us only in set. // We would never allow an outer probe to nest until both w_[rp]probeack complete, so // it is safe to just unguardedly update the probe FSM. probes_done := probes_done \| probe_bit probes_toN := probes_toN \| Mux(probe_toN, probe_bit, 0.U) probes_noT := probes_noT \|\| io.sinkc.bits.param =/= TtoT w_rprobeackfirst := w_rprobeackfirst \|\| last_probe w_rprobeacklast := w_rprobeacklast \|\| (last_probe && io.sinkc.bits.last) w_pprobeackfirst := w_pprobeackfirst \|\| last_probe w_pprobeacklast := w_pprobeacklast \|\| (last_probe && io.sinkc.bits.last) // Allow wormhole routing from sinkC if the first request beat has offset 0 val set_pprobeack = last_probe && (io.sinkc.bits.last \|\| request.offset === 0.U) w_pprobeack := w_pprobeack \|\| set_pprobeack params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data") params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data") // However, meta-data updates need to be done more cautiously when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!! } when (io.sinkd.valid) { when (io.sinkd.bits.opcode === Grant \|\| io.sinkd.bits.opcode === GrantData) { sink := io.sinkd.bits.sink w_grantfirst := true.B w_grantlast := io.sinkd.bits.last // Record if we need to prevent taking ownership bad_grant := io.sinkd.bits.denied // Allow wormhole routing for requests whose first beat has offset 0 w_grant := request.offset === 0.U \|\| io.sinkd.bits.last params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data") params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data") gotT := io.sinkd.bits.param === toT } .elsewhen (io.sinkd.bits.opcode === ReleaseAck) { w_releaseack := true.B } } when (io.sinke.valid) { w_grantack := true.B } // Bootstrap new requests val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits) val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits) val new_request = Mux(io.allocate.valid, allocate_as_full, request) val new_needT = needT(new_request.opcode, new_request.param) val new_clientBit = params.clientBit(new_request.source) val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U) val prior = cacheState(final_meta_writeback, true.B) def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}") } else { assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}") } } when (io.allocate.valid && io.allocate.bits.repeat) { bypass(S_INVALID, f \|\| p) // Can lose permissions (probe/flush) bypass(S_BRANCH, b) // MMIO read to read-only device bypass(S_BRANCH_C, b && c) // you need children to become C bypass(S_TIP, true) // MMIO read \|\| clean release can lead to this state bypass(S_TIP_C, c) // needs two clients \|\| client + mmio \|\| downgrading client bypass(S_TIP_CD, c) // needs two clients \|\| client + mmio \|\| downgrading client bypass(S_TIP_D, true) // MMIO write \|\| dirty release lead here bypass(S_TRUNK_C, c) // acquire for write bypass(S_TRUNK_CD, c) // dirty release then reacquire } when (io.allocate.valid) { assert (!request_valid \|\| (no_wait && io.schedule.fire)) request_valid := true.B request := io.allocate.bits } // Create execution plan when (io.directory.valid \|\| (io.allocate.valid && io.allocate.bits.repeat)) { meta_valid := true.B meta := new_meta probes_done := 0.U probes_toN := 0.U probes_noT := false.B gotT := false.B bad_grant := false.B // These should already be either true or turning true // We clear them here explicitly to simplify the mux tree s_rprobe := true.B w_rprobeackfirst := true.B w_rprobeacklast := true.B s_release := true.B w_releaseack := true.B s_pprobe := true.B s_acquire := true.B s_flush := true.B w_grantfirst := true.B w_grantlast := true.B w_grant := true.B w_pprobeackfirst := true.B w_pprobeacklast := true.B w_pprobeack := true.B s_probeack := true.B s_grantack := true.B s_execute := true.B w_grantack := true.B s_writeback := true.B // For C channel requests (ie: Release[Data]) when (new_request.prio(2) && (!params.firstLevel).B) { s_execute := false.B // Do we need to go dirty? when (new_request.opcode(0) && !new_meta.dirty) { s_writeback := false.B } // Does our state change? when (isToB(new_request.param) && new_meta.state === TRUNK) { s_writeback := false.B } // Do our clients change? when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) { s_writeback := false.B } assert (new_meta.hit) } // For X channel requests (ie: flush) .elsewhen (new_request.control && params.control.B) { // new_request.prio(0) s_flush := false.B // Do we need to actually do something? when (new_meta.hit) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } } // For A channel requests .otherwise { // new_request.prio(0) && !new_request.control s_execute := false.B // Do we need an eviction? when (!new_meta.hit && new_meta.state =/= INVALID) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } // Do we need an acquire? when (!new_meta.hit \|\| (new_meta.state === BRANCH && new_needT)) { s_acquire := false.B w_grantfirst := false.B w_grantlast := false.B w_grant := false.B s_grantack := false.B s_writeback := false.B } // Do we need a probe? when ((!params.firstLevel).B && (new_meta.hit && (new_needT \|\| new_meta.state === TRUNK) && (new_meta.clients & ~new_skipProbe) =/= 0.U)) { s_pprobe := false.B w_pprobeackfirst := false.B w_pprobeacklast := false.B w_pprobeack := false.B s_writeback := false.B } // Do we need a grantack? when (new_request.opcode === AcquireBlock \|\| new_request.opcode === AcquirePerm) { w_grantack := false.B s_writeback := false.B } // Becomes dirty? when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) { s_writeback := false.B } } } } File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relListscache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_\|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x \| 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ \|\| _) (matches, bits.U) } expanded \| Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) \|\| (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) \|\| ((opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm \|\| opcode === TLMessages.Get \|\| (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN \|\| param === TLPermissions.BtoN \|\| param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB \|\| param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle	module MSHR_4( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input [7:0] io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output [7:0] io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output [7:0] io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire [7:0] final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire [7:0] io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [7:0] invalid_clients = 8'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire [7:0] _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire [7:0] _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire [7:0] io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire [7:0] io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg [7:0] meta_clients; // @[MSHR.scala:100:17] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg [7:0] probes_done; // @[MSHR.scala:150:24] reg [7:0] probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire [7:0] _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire _req_clientBit_T = request_source == 6'h3C; // @[Parameters.scala:46:9] wire _req_clientBit_T_1 = request_source == 6'h38; // @[Parameters.scala:46:9] wire _req_clientBit_T_2 = request_source == 6'h34; // @[Parameters.scala:46:9] wire _req_clientBit_T_3 = request_source == 6'h30; // @[Parameters.scala:46:9] wire _req_clientBit_T_4 = request_source == 6'h2C; // @[Parameters.scala:46:9] wire _req_clientBit_T_5 = request_source == 6'h28; // @[Parameters.scala:46:9] wire _req_clientBit_T_6 = request_source == 6'h24; // @[Parameters.scala:46:9] wire _req_clientBit_T_7 = request_source == 6'h20; // @[Parameters.scala:46:9] wire [1:0] req_clientBit_lo_lo = {_req_clientBit_T_1, _req_clientBit_T}; // @[Parameters.scala:46:9] wire [1:0] req_clientBit_lo_hi = {_req_clientBit_T_3, _req_clientBit_T_2}; // @[Parameters.scala:46:9] wire [3:0] req_clientBit_lo = {req_clientBit_lo_hi, req_clientBit_lo_lo}; // @[Parameters.scala:201:10] wire [1:0] req_clientBit_hi_lo = {_req_clientBit_T_5, _req_clientBit_T_4}; // @[Parameters.scala:46:9] wire [1:0] req_clientBit_hi_hi = {_req_clientBit_T_7, _req_clientBit_T_6}; // @[Parameters.scala:46:9] wire [3:0] req_clientBit_hi = {req_clientBit_hi_hi, req_clientBit_hi_lo}; // @[Parameters.scala:201:10] wire [7:0] req_clientBit = {req_clientBit_hi, req_clientBit_lo}; // @[Parameters.scala:201:10] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire _meta_no_clients_T = \|meta_clients; // @[MSHR.scala:100:17, :220:39] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire [7:0] _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 ? req_clientBit : 8'h0; // @[Parameters.scala:201:10, :282:66] wire [7:0] _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire [7:0] _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire [7:0] _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire [7:0] _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire [7:0] _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire [7:0] _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire [7:0] _final_meta_writeback_clients_T_12 = meta_hit ? _final_meta_writeback_clients_T_11 : 8'h0; // @[MSHR.scala:100:17, :245:{40,64}] wire [7:0] _final_meta_writeback_clients_T_13 = req_acquire ? req_clientBit : 8'h0; // @[Parameters.scala:201:10] wire [7:0] _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire [7:0] _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire [7:0] _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? (meta_hit ? _final_meta_writeback_clients_T_16 : 8'h0) : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire [7:0] _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:201:10] wire _honour_BtoT_T_1 = \|_honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire [7:0] excluded_client = _excluded_client_T_9 ? req_clientBit : 8'h0; // @[Parameters.scala:201:10] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire [7:0] _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = _io_schedule_bits_dir_bits_data_T ? 8'h0 : _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire evict_c = \|meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire before_c = \|meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire after_c = \|final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _probe_bit_T = io_sinkc_bits_source_0 == 6'h3C; // @[Parameters.scala:46:9] wire _probe_bit_T_1 = io_sinkc_bits_source_0 == 6'h38; // @[Parameters.scala:46:9] wire _probe_bit_T_2 = io_sinkc_bits_source_0 == 6'h34; // @[Parameters.scala:46:9] wire _probe_bit_T_3 = io_sinkc_bits_source_0 == 6'h30; // @[Parameters.scala:46:9] wire _probe_bit_T_4 = io_sinkc_bits_source_0 == 6'h2C; // @[Parameters.scala:46:9] wire _probe_bit_T_5 = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9] wire _probe_bit_T_6 = io_sinkc_bits_source_0 == 6'h24; // @[Parameters.scala:46:9] wire _probe_bit_T_7 = io_sinkc_bits_source_0 == 6'h20; // @[Parameters.scala:46:9] wire [1:0] probe_bit_lo_lo = {_probe_bit_T_1, _probe_bit_T}; // @[Parameters.scala:46:9] wire [1:0] probe_bit_lo_hi = {_probe_bit_T_3, _probe_bit_T_2}; // @[Parameters.scala:46:9] wire [3:0] probe_bit_lo = {probe_bit_lo_hi, probe_bit_lo_lo}; // @[Parameters.scala:201:10] wire [1:0] probe_bit_hi_lo = {_probe_bit_T_5, _probe_bit_T_4}; // @[Parameters.scala:46:9] wire [1:0] probe_bit_hi_hi = {_probe_bit_T_7, _probe_bit_T_6}; // @[Parameters.scala:46:9] wire [3:0] probe_bit_hi = {probe_bit_hi_hi, probe_bit_hi_lo}; // @[Parameters.scala:201:10] wire [7:0] probe_bit = {probe_bit_hi, probe_bit_lo}; // @[Parameters.scala:201:10] wire [7:0] _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:201:10] wire [7:0] _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire [7:0] _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire [7:0] _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire [7:0] _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire [7:0] _probes_toN_T = probe_toN ? probe_bit : 8'h0; // @[Parameters.scala:201:10, :282:66] wire [7:0] _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [7:0] new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _new_clientBit_T = new_request_source == 6'h3C; // @[Parameters.scala:46:9] wire _new_clientBit_T_1 = new_request_source == 6'h38; // @[Parameters.scala:46:9] wire _new_clientBit_T_2 = new_request_source == 6'h34; // @[Parameters.scala:46:9] wire _new_clientBit_T_3 = new_request_source == 6'h30; // @[Parameters.scala:46:9] wire _new_clientBit_T_4 = new_request_source == 6'h2C; // @[Parameters.scala:46:9] wire _new_clientBit_T_5 = new_request_source == 6'h28; // @[Parameters.scala:46:9] wire _new_clientBit_T_6 = new_request_source == 6'h24; // @[Parameters.scala:46:9] wire _new_clientBit_T_7 = new_request_source == 6'h20; // @[Parameters.scala:46:9] wire [1:0] new_clientBit_lo_lo = {_new_clientBit_T_1, _new_clientBit_T}; // @[Parameters.scala:46:9] wire [1:0] new_clientBit_lo_hi = {_new_clientBit_T_3, _new_clientBit_T_2}; // @[Parameters.scala:46:9] wire [3:0] new_clientBit_lo = {new_clientBit_lo_hi, new_clientBit_lo_lo}; // @[Parameters.scala:201:10] wire [1:0] new_clientBit_hi_lo = {_new_clientBit_T_5, _new_clientBit_T_4}; // @[Parameters.scala:46:9] wire [1:0] new_clientBit_hi_hi = {_new_clientBit_T_7, _new_clientBit_T_6}; // @[Parameters.scala:46:9] wire [3:0] new_clientBit_hi = {new_clientBit_hi_hi, new_clientBit_hi_lo}; // @[Parameters.scala:201:10] wire [7:0] new_clientBit = {new_clientBit_hi, new_clientBit_lo}; // @[Parameters.scala:201:10] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire [7:0] new_skipProbe = _new_skipProbe_T_7 ? new_clientBit : 8'h0; // @[Parameters.scala:201:10, :279:106] wire [3:0] prior; // @[MSHR.scala:314:26] wire prior_c = \|final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_45( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire [26:0] _GEN_0 = {23'h0, io_in_c_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [7:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [2:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35] reg [7:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [2:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [7:0] b_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg [2:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35] reg [7:0] c_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [2:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [4:0] inflight; // @[Monitor.scala:614:27] reg [19:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire [7:0] _GEN_1 = {5'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [7:0] _GEN_4 = {5'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [4:0] inflight_1; // @[Monitor.scala:726:35] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [7:0] c_first_counter_1; // @[Edges.scala:229:27] wire c_first_1 = c_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}] wire [7:0] _GEN_6 = {5'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35] wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] reg [15:0] inflight_2; // @[Monitor.scala:828:27] reg [7:0] d_first_counter_3; // @[Edges.scala:229:27] wire d_first_3 = d_first_counter_3 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35] wire [15:0] _GEN_9 = {12'h0, io_in_d_bits_sink}; // @[OneHot.scala:58:35] wire [15:0] d_set = _GEN_8 ? 16'h1 << _GEN_9 : 16'h0; // @[OneHot.scala:58:35] wire _GEN_10 = io_in_e_ready & io_in_e_valid; // @[Decoupled.scala:51:35] wire [15:0] _GEN_11 = {12'h0, io_in_e_bits_sink}; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to the following Chisel files. File issue-unit-age-ordered.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Logic //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import boom.v4.common._ class IssueUnitCollapsing( params: IssueParams, numWakeupPorts: Int) (implicit p: Parameters) extends IssueUnit(params, numWakeupPorts) { //------------------------------------------------------------- // Set up the dispatch uops // special case "storing" 2 uops within one issue slot. val dis_uops = Array.fill(dispatchWidth) {Wire(new MicroOp())} for (w <- 0 until dispatchWidth) { dis_uops(w) := io.dis_uops(w).bits dis_uops(w).iw_issued := false.B dis_uops(w).iw_issued_partial_agen := false.B dis_uops(w).iw_issued_partial_dgen := false.B dis_uops(w).iw_p1_bypass_hint := false.B dis_uops(w).iw_p2_bypass_hint := false.B dis_uops(w).iw_p3_bypass_hint := false.B // Handle wakeups on dispatch val prs1_matches = io.wakeup_ports.map { wu => wu.bits.uop.pdst === io.dis_uops(w).bits.prs1 } val prs2_matches = io.wakeup_ports.map { wu => wu.bits.uop.pdst === io.dis_uops(w).bits.prs2 } val prs3_matches = io.wakeup_ports.map { wu => wu.bits.uop.pdst === io.dis_uops(w).bits.prs3 } val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (wu,m) => wu.valid && m } val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (wu,m) => wu.valid && m } val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (wu,m) => wu.valid && m } val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (wu,m) => wu.bits.rebusy && m } val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (wu,m) => wu.bits.rebusy && m } val bypassables = io.wakeup_ports.map { wu => wu.bits.bypassable } val speculative_masks = io.wakeup_ports.map { wu => wu.bits.speculative_mask } when (prs1_wakeups.reduce(_\|\|_)) { dis_uops(w).prs1_busy := false.B dis_uops(w).iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks) dis_uops(w).iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables) } when (prs1_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & io.dis_uops(w).bits.iw_p1_speculative_child) =/= 0.U)) { dis_uops(w).prs1_busy := io.dis_uops(w).bits.lrs1_rtype === RT_FIX } when (prs2_wakeups.reduce(_\|\|_)) { dis_uops(w).prs2_busy := false.B dis_uops(w).iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks) dis_uops(w).iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables) } when (prs2_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & io.dis_uops(w).bits.iw_p2_speculative_child) =/= 0.U)) { dis_uops(w).prs2_busy := io.dis_uops(w).bits.lrs2_rtype === RT_FIX } when (prs3_wakeups.reduce(_\|\|_)) { dis_uops(w).prs3_busy := false.B dis_uops(w).iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables) } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === io.dis_uops(w).bits.ppred) { dis_uops(w).ppred_busy := false.B } if (iqType == IQ_UNQ) { when (io.dis_uops(w).bits.fu_code(FC_I2F)) { dis_uops(w).prs2 := Cat(io.dis_uops(w).bits.fp_rm, io.dis_uops(w).bits.fp_typ) } when (io.dis_uops(w).bits.is_sfence) { dis_uops(w).pimm := io.dis_uops(w).bits.mem_size } } if (iqType == IQ_MEM) { // For store addr gen for FP, rs2 is the FP register, and we don't wait for that here when (io.dis_uops(w).bits.uses_stq && io.dis_uops(w).bits.lrs2_rtype === RT_FLT) { dis_uops(w).lrs2_rtype := RT_X dis_uops(w).prs2_busy := false.B } dis_uops(w).prs3_busy := false.B } else if (iqType == IQ_FP) { // FP "StoreAddrGen" is really storeDataGen, and rs1 is the integer address register when (io.dis_uops(w).bits.uses_stq) { dis_uops(w).lrs1_rtype := RT_X dis_uops(w).prs1_busy := false.B } } if (iqType != IQ_ALU) { assert(!(io.dis_uops(w).bits.ppred_busy && io.dis_uops(w).valid)) dis_uops(w).ppred_busy := false.B } } //------------------------------------------------------------- // Issue Table val slots = (0 until numIssueSlots) map { w => Module(new IssueSlot(numWakeupPorts, iqType == IQ_MEM, iqType == IQ_FP)) } val issue_slots = VecInit(slots.map(_.io)) for (i <- 0 until numIssueSlots) { issue_slots(i).wakeup_ports := io.wakeup_ports issue_slots(i).pred_wakeup_port := io.pred_wakeup_port issue_slots(i).child_rebusys := io.child_rebusys issue_slots(i).squash_grant := io.squash_grant issue_slots(i).brupdate := io.brupdate issue_slots(i).kill := io.flush_pipeline } for (w <- 0 until issueWidth) { io.iss_uops(w).valid := false.B } //------------------------------------------------------------- assert (PopCount(issue_slots.map(s => s.grant)) <= issueWidth.U, "[issue] window giving out too many grants.") //------------------------------------------------------------- // Figure out how much to shift entries by // Slow slots only shift 1 per cycle, these reduce critical path val nSlowSlots = params.numSlowEntries // Fast slots can shift up to dispatchWidth per cycle, so they can handle full dispatch throughput val nFastSlots = numIssueSlots - nSlowSlots require (nFastSlots >= dispatchWidth) require (nFastSlots <= numIssueSlots) val vacants = issue_slots.map(s => !(s.valid)) ++ io.dis_uops.map(_.valid).map(!_.asBool) val shamts_oh = Wire(Vec(numIssueSlots+dispatchWidth, UInt(width=dispatchWidth.W))) // track how many to shift up this entry by by counting previous vacant spots def SaturatingCounterOH(count_oh:UInt, inc: Bool, max: Int): UInt = { val next = Wire(UInt(width=max.W)) next := count_oh when (count_oh === 0.U && inc) { next := 1.U } .elsewhen (!count_oh(max-1) && inc) { next := (count_oh << 1.U) } next } shamts_oh(0) := 0.U for (i <- 1 until numIssueSlots + dispatchWidth) { val shift = if (i < nSlowSlots) (dispatchWidth min 1 + (i * (dispatchWidth-1)/nSlowSlots).toInt) else dispatchWidth if (dispatchWidth == 1 \|\| shift == 1) { shamts_oh(i) := vacants.take(i).reduce(_\|\|_) } else { shamts_oh(i) := SaturatingCounterOH(shamts_oh(i-1), vacants(i-1), shift) } } //------------------------------------------------------------- // which entries' uops will still be next cycle? (not being issued and vacated) val will_be_valid = (0 until numIssueSlots).map(i => issue_slots(i).will_be_valid) ++ (0 until dispatchWidth).map(i => io.dis_uops(i).valid && !dis_uops(i).exception && !dis_uops(i).is_fence && !dis_uops(i).is_fencei) val uops = issue_slots.map(s=>s.out_uop) ++ dis_uops.map(s=>s) for (i <- 0 until numIssueSlots) { issue_slots(i).in_uop.valid := false.B issue_slots(i).in_uop.bits := uops(i+1) for (j <- 1 to dispatchWidth by 1) { when (shamts_oh(i+j) === (1 << (j-1)).U) { issue_slots(i).in_uop.valid := will_be_valid(i+j) issue_slots(i).in_uop.bits := uops(i+j) } } issue_slots(i).clear := shamts_oh(i) =/= 0.U } //------------------------------------------------------------- // Dispatch/Entry Logic // did we find a spot to slide the new dispatched uops into? // Only look at the fast slots to determine readiness to dispatch. // Slow slot do not compact fast enough to make this calculation valid val is_available = Reg(Vec(nFastSlots, Bool())) is_available := VecInit((nSlowSlots until numIssueSlots).map(i => (!issue_slots(i).will_be_valid \|\| issue_slots(i).clear) && !(issue_slots(i).in_uop.valid))) for (w <- 0 until dispatchWidth) { io.dis_uops(w).ready := RegNext(PopCount(is_available) > w.U(log2Ceil(nFastSlots).W) + PopCount(io.dis_uops.map(_.fire))) // io.dis_uops(w).ready := RegNext(PopCount(will_be_available) > w.U) assert (!io.dis_uops(w).ready \|\| (shamts_oh(w+numIssueSlots) >> w) =/= 0.U) } //------------------------------------------------------------- // Issue Select Logic val requests = issue_slots.map(s => s.request) val port_issued = Array.fill(issueWidth){Bool()} for (w <- 0 until issueWidth) { port_issued(w) = false.B } val iss_select_mask = Array.ofDim[Boolean](issueWidth, numIssueSlots) if (params.useFullIssueSel) { for (w <- 0 until issueWidth) { for (i <- 0 until numIssueSlots) { iss_select_mask(w)(i) = true } } } else { for (w <- 0 until issueWidth) { for (i <- 0 until numIssueSlots) { iss_select_mask(w)(i) = (w % 2) == (i % 2) } iss_select_mask(w)(0) = true } } val iss_uops = Wire(Vec(issueWidth, Valid(new MicroOp))) for (w <- 0 until issueWidth) { iss_uops(w).valid := false.B iss_uops(w).bits := DontCare } for (i <- 0 until numIssueSlots) { issue_slots(i).grant := false.B var uop_issued = false.B for (w <- 0 until issueWidth) { val fu_code_match = (issue_slots(i).iss_uop.fu_code zip io.fu_types(w)).map { case (r,c) => r && c } .reduce(_\|\|_) val can_allocate = fu_code_match && iss_select_mask(w)(i).B when (requests(i) && !uop_issued && can_allocate && !port_issued(w)) { issue_slots(i).grant := true.B iss_uops(w).valid := true.B iss_uops(w).bits := issue_slots(i).iss_uop } val was_port_issued_yet = port_issued(w) port_issued(w) = (requests(i) && !uop_issued && can_allocate) \| port_issued(w) uop_issued = (requests(i) && can_allocate && !was_port_issued_yet) \| uop_issued } } io.iss_uops := iss_uops when (io.squash_grant) { io.iss_uops.map { u => u.valid := false.B } } } File issue-unit.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Logic //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.{Str} import boom.v4.common._ import boom.v4.util.{BoolToChar} case class IssueParams( dispatchWidth: Int = 1, issueWidth: Int = 1, numEntries: Int = 8, useFullIssueSel: Boolean = true, numSlowEntries: Int = 0, iqType: Int ) abstract class IssueUnit( val params: IssueParams, val numWakeupPorts: Int )(implicit p: Parameters) extends BoomModule { val numIssueSlots = params.numEntries val issueWidth = params.issueWidth val iqType = params.iqType val dispatchWidth = params.dispatchWidth val io = IO(new Bundle { val dis_uops = Vec(dispatchWidth, Flipped(Decoupled(new MicroOp))) val iss_uops = Output(Vec(issueWidth, Valid(new MicroOp()))) val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val child_rebusys = Input(UInt(aluWidth.W)) // tell the issue unit what each execution pipeline has in terms of functional units val fu_types = Input(Vec(issueWidth, Vec(FC_SZ, Bool()))) val brupdate = Input(new BrUpdateInfo()) val flush_pipeline = Input(Bool()) val squash_grant = Input(Bool()) val tsc_reg = Input(UInt(xLen.W)) }) //------------------------------------------------------------- def getType: String = if (iqType == IQ_ALU) "alu" else if (iqType == IQ_MEM) "mem" else if (iqType == IQ_FP) " fp" else if (iqType == IQ_UNQ) "unique" else "unknown" } object IssueUnit { def apply(params: IssueParams, numWakeupPorts: Int, useColumnIssueUnit: Boolean, useSingleWideDispatch: Boolean)(implicit p: Parameters): IssueUnit = { if (useColumnIssueUnit) Module(new IssueUnitBanked(params, numWakeupPorts, useSingleWideDispatch)) else Module(new IssueUnitCollapsing(params, numWakeupPorts)) } }	module IssueUnitCollapsing( // @[issue-unit-age-ordered.scala:22:7] input clock, // @[issue-unit-age-ordered.scala:22:7] input reset, // @[issue-unit-age-ordered.scala:22:7] output io_dis_uops_0_ready, // @[issue-unit.scala:44:14] input io_dis_uops_0_valid, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_0_bits_inst, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_0_bits_debug_inst, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_dis_uops_0_bits_debug_pc, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iq_type_0, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iq_type_1, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iq_type_2, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iq_type_3, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_0, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_1, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_2, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_3, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_4, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_5, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_6, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_7, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_8, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_9, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_issued, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_dis_uops_0_bits_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_0_bits_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_0_bits_br_type, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_sfb, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_fence, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_fencei, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_sfence, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_amo, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_eret, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_rocc, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_ftq_idx, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_pc_lob, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_taken, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_pimm, // @[issue-unit.scala:44:14] input [19:0] io_dis_uops_0_bits_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_op2_sel, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_pdst, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_prs1, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_prs2, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_prs3, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_ppred, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_prs1_busy, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_prs2_busy, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_prs3_busy, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_stale_pdst, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_exception, // @[issue-unit.scala:44:14] input [63:0] io_dis_uops_0_bits_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_mem_size, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_mem_signed, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_uses_ldq, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_uses_stq, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_unique, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_csr_cmd, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_ldst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_lrs2_rtype, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_frs3_en, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_fcn_op, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_fp_typ, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_bp_debug_if, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_debug_tsrc, // @[issue-unit.scala:44:14] output io_dis_uops_1_ready, // @[issue-unit.scala:44:14] input io_dis_uops_1_valid, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_1_bits_inst, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_1_bits_debug_inst, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_dis_uops_1_bits_debug_pc, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iq_type_0, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iq_type_1, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iq_type_2, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iq_type_3, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_0, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_1, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_2, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_3, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_4, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_5, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_6, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_7, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_8, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_9, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_issued, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_dis_uops_1_bits_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_1_bits_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_1_bits_br_type, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_sfb, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_fence, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_fencei, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_sfence, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_amo, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_eret, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_rocc, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_ftq_idx, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_pc_lob, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_taken, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_pimm, // @[issue-unit.scala:44:14] input [19:0] io_dis_uops_1_bits_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_op2_sel, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_pdst, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_prs1, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_prs2, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_prs3, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_ppred, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_prs1_busy, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_prs2_busy, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_prs3_busy, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_stale_pdst, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_exception, // @[issue-unit.scala:44:14] input [63:0] io_dis_uops_1_bits_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_mem_size, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_mem_signed, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_uses_ldq, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_uses_stq, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_unique, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_csr_cmd, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_ldst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_lrs2_rtype, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_frs3_en, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_fcn_op, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_fp_typ, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_bp_debug_if, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_debug_tsrc, // @[issue-unit.scala:44:14] output io_dis_uops_2_ready, // @[issue-unit.scala:44:14] input io_dis_uops_2_valid, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_2_bits_inst, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_2_bits_debug_inst, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_dis_uops_2_bits_debug_pc, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iq_type_0, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iq_type_1, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iq_type_2, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iq_type_3, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_0, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_1, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_2, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_3, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_4, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_5, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_6, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_7, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_8, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_9, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iw_issued, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_dis_uops_2_bits_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_2_bits_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_2_bits_br_type, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_sfb, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_fence, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_fencei, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_sfence, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_amo, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_eret, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_rocc, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_ftq_idx, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_2_bits_pc_lob, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_taken, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_pimm, // @[issue-unit.scala:44:14] input [19:0] io_dis_uops_2_bits_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_op2_sel, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_2_bits_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_2_bits_pdst, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_2_bits_prs1, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_2_bits_prs2, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_2_bits_prs3, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_ppred, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_prs1_busy, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_prs2_busy, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_prs3_busy, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_2_bits_stale_pdst, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_exception, // @[issue-unit.scala:44:14] input [63:0] io_dis_uops_2_bits_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_mem_size, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_mem_signed, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_uses_ldq, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_uses_stq, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_unique, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_csr_cmd, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_2_bits_ldst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_2_bits_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_2_bits_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_2_bits_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_lrs2_rtype, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_frs3_en, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_fcn_op, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_fp_typ, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_bp_debug_if, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_debug_tsrc, // @[issue-unit.scala:44:14] output io_iss_uops_0_valid, // @[issue-unit.scala:44:14] output [31:0] io_iss_uops_0_bits_inst, // @[issue-unit.scala:44:14] output [31:0] io_iss_uops_0_bits_debug_inst, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_rvc, // @[issue-unit.scala:44:14] output [39:0] io_iss_uops_0_bits_debug_pc, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iq_type_0, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iq_type_1, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iq_type_2, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iq_type_3, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_0, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_1, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_2, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_3, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_4, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_5, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_6, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_7, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_8, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_9, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iw_issued, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_iw_p1_speculative_child, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_iw_p2_speculative_child, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_dis_col_sel, // @[issue-unit.scala:44:14] output [15:0] io_iss_uops_0_bits_br_mask, // @[issue-unit.scala:44:14] output [3:0] io_iss_uops_0_bits_br_tag, // @[issue-unit.scala:44:14] output [3:0] io_iss_uops_0_bits_br_type, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_sfb, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_fence, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_fencei, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_sfence, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_amo, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_eret, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_sys_pc2epc, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_rocc, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_mov, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_ftq_idx, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_edge_inst, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_pc_lob, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_taken, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_imm_rename, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_imm_sel, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_pimm, // @[issue-unit.scala:44:14] output [19:0] io_iss_uops_0_bits_imm_packed, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_op1_sel, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_op2_sel, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_ldst, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_wen, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_ren1, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_ren2, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_ren3, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_swap12, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_swap23, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_fromint, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_toint, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_fma, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_div, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_wflags, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_vec, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_rob_idx, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_ldq_idx, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_stq_idx, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_rxq_idx, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_pdst, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_prs1, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_prs2, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_prs3, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_ppred, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_prs1_busy, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_prs2_busy, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_prs3_busy, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_ppred_busy, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_stale_pdst, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_exception, // @[issue-unit.scala:44:14] output [63:0] io_iss_uops_0_bits_exc_cause, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_mem_cmd, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_mem_size, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_mem_signed, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_uses_ldq, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_uses_stq, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_unique, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_flush_on_commit, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_csr_cmd, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_ldst_is_rs1, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_ldst, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_lrs1, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_lrs2, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_lrs3, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_dst_rtype, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_lrs1_rtype, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_lrs2_rtype, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_frs3_en, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fcn_dw, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_fcn_op, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_val, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_fp_rm, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_fp_typ, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_xcpt_pf_if, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_xcpt_ae_if, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_xcpt_ma_if, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_bp_debug_if, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_bp_xcpt_if, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_debug_fsrc, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_debug_tsrc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_valid, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_valid, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-unit.scala:44:14] input io_fu_types_0_7, // @[issue-unit.scala:44:14] input io_fu_types_0_9, // @[issue-unit.scala:44:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-unit.scala:44:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-unit.scala:44:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_issued, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_sfb, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_fence, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_fencei, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_sfence, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_amo, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_eret, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_rocc, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_taken, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_mem_signed, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_uses_stq, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_unique, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_frs3_en, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-unit.scala:44:14] input io_brupdate_b2_mispredict, // @[issue-unit.scala:44:14] input io_brupdate_b2_taken, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-unit.scala:44:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-unit.scala:44:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-unit.scala:44:14] input io_flush_pipeline, // @[issue-unit.scala:44:14] input io_squash_grant, // @[issue-unit.scala:44:14] input [63:0] io_tsc_reg // @[issue-unit.scala:44:14] ); wire issue_slots_23_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire io_dis_uops_0_valid_0 = io_dis_uops_0_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_0_bits_inst_0 = io_dis_uops_0_bits_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_0_bits_debug_inst_0 = io_dis_uops_0_bits_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_rvc_0 = io_dis_uops_0_bits_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_dis_uops_0_bits_debug_pc_0 = io_dis_uops_0_bits_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iq_type_0_0 = io_dis_uops_0_bits_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iq_type_1_0 = io_dis_uops_0_bits_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iq_type_2_0 = io_dis_uops_0_bits_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iq_type_3_0 = io_dis_uops_0_bits_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_0_0 = io_dis_uops_0_bits_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_1_0 = io_dis_uops_0_bits_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_2_0 = io_dis_uops_0_bits_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_3_0 = io_dis_uops_0_bits_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_4_0 = io_dis_uops_0_bits_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_5_0 = io_dis_uops_0_bits_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_6_0 = io_dis_uops_0_bits_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_7_0 = io_dis_uops_0_bits_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_8_0 = io_dis_uops_0_bits_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_9_0 = io_dis_uops_0_bits_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_issued_0 = io_dis_uops_0_bits_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_issued_partial_agen_0 = io_dis_uops_0_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_issued_partial_dgen_0 = io_dis_uops_0_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_iw_p1_speculative_child_0 = io_dis_uops_0_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_iw_p2_speculative_child_0 = io_dis_uops_0_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_p1_bypass_hint_0 = io_dis_uops_0_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_p2_bypass_hint_0 = io_dis_uops_0_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_p3_bypass_hint_0 = io_dis_uops_0_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_dis_col_sel_0 = io_dis_uops_0_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_dis_uops_0_bits_br_mask_0 = io_dis_uops_0_bits_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_0_bits_br_tag_0 = io_dis_uops_0_bits_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_0_bits_br_type_0 = io_dis_uops_0_bits_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_sfb_0 = io_dis_uops_0_bits_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_fence_0 = io_dis_uops_0_bits_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_fencei_0 = io_dis_uops_0_bits_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_sfence_0 = io_dis_uops_0_bits_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_amo_0 = io_dis_uops_0_bits_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_eret_0 = io_dis_uops_0_bits_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_sys_pc2epc_0 = io_dis_uops_0_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_rocc_0 = io_dis_uops_0_bits_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_mov_0 = io_dis_uops_0_bits_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_ftq_idx_0 = io_dis_uops_0_bits_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_edge_inst_0 = io_dis_uops_0_bits_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_pc_lob_0 = io_dis_uops_0_bits_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_taken_0 = io_dis_uops_0_bits_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_imm_rename_0 = io_dis_uops_0_bits_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_imm_sel_0 = io_dis_uops_0_bits_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_pimm_0 = io_dis_uops_0_bits_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_dis_uops_0_bits_imm_packed_0 = io_dis_uops_0_bits_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_op1_sel_0 = io_dis_uops_0_bits_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_op2_sel_0 = io_dis_uops_0_bits_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_ldst_0 = io_dis_uops_0_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_wen_0 = io_dis_uops_0_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_ren1_0 = io_dis_uops_0_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_ren2_0 = io_dis_uops_0_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_ren3_0 = io_dis_uops_0_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_swap12_0 = io_dis_uops_0_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_swap23_0 = io_dis_uops_0_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagIn_0 = io_dis_uops_0_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagOut_0 = io_dis_uops_0_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_fromint_0 = io_dis_uops_0_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_toint_0 = io_dis_uops_0_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_fastpipe_0 = io_dis_uops_0_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_fma_0 = io_dis_uops_0_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_div_0 = io_dis_uops_0_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_sqrt_0 = io_dis_uops_0_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_wflags_0 = io_dis_uops_0_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_vec_0 = io_dis_uops_0_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_rob_idx_0 = io_dis_uops_0_bits_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_ldq_idx_0 = io_dis_uops_0_bits_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_stq_idx_0 = io_dis_uops_0_bits_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_rxq_idx_0 = io_dis_uops_0_bits_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_pdst_0 = io_dis_uops_0_bits_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_prs1_0 = io_dis_uops_0_bits_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_prs2_0 = io_dis_uops_0_bits_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_prs3_0 = io_dis_uops_0_bits_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_ppred_0 = io_dis_uops_0_bits_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_prs1_busy_0 = io_dis_uops_0_bits_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_prs2_busy_0 = io_dis_uops_0_bits_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_prs3_busy_0 = io_dis_uops_0_bits_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_ppred_busy_0 = io_dis_uops_0_bits_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_stale_pdst_0 = io_dis_uops_0_bits_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_exception_0 = io_dis_uops_0_bits_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_dis_uops_0_bits_exc_cause_0 = io_dis_uops_0_bits_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_mem_cmd_0 = io_dis_uops_0_bits_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_mem_size_0 = io_dis_uops_0_bits_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_mem_signed_0 = io_dis_uops_0_bits_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_uses_ldq_0 = io_dis_uops_0_bits_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_uses_stq_0 = io_dis_uops_0_bits_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_unique_0 = io_dis_uops_0_bits_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_flush_on_commit_0 = io_dis_uops_0_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_csr_cmd_0 = io_dis_uops_0_bits_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_ldst_is_rs1_0 = io_dis_uops_0_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_ldst_0 = io_dis_uops_0_bits_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_lrs1_0 = io_dis_uops_0_bits_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_lrs2_0 = io_dis_uops_0_bits_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_lrs3_0 = io_dis_uops_0_bits_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_dst_rtype_0 = io_dis_uops_0_bits_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_lrs1_rtype_0 = io_dis_uops_0_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_lrs2_rtype_0 = io_dis_uops_0_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_frs3_en_0 = io_dis_uops_0_bits_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fcn_dw_0 = io_dis_uops_0_bits_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_fcn_op_0 = io_dis_uops_0_bits_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_val_0 = io_dis_uops_0_bits_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_fp_rm_0 = io_dis_uops_0_bits_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_fp_typ_0 = io_dis_uops_0_bits_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_xcpt_pf_if_0 = io_dis_uops_0_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_xcpt_ae_if_0 = io_dis_uops_0_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_xcpt_ma_if_0 = io_dis_uops_0_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_bp_debug_if_0 = io_dis_uops_0_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_bp_xcpt_if_0 = io_dis_uops_0_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_debug_fsrc_0 = io_dis_uops_0_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_debug_tsrc_0 = io_dis_uops_0_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_valid_0 = io_dis_uops_1_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_1_bits_inst_0 = io_dis_uops_1_bits_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_1_bits_debug_inst_0 = io_dis_uops_1_bits_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_rvc_0 = io_dis_uops_1_bits_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_dis_uops_1_bits_debug_pc_0 = io_dis_uops_1_bits_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iq_type_0_0 = io_dis_uops_1_bits_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iq_type_1_0 = io_dis_uops_1_bits_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iq_type_2_0 = io_dis_uops_1_bits_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iq_type_3_0 = io_dis_uops_1_bits_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_0_0 = io_dis_uops_1_bits_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_1_0 = io_dis_uops_1_bits_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_2_0 = io_dis_uops_1_bits_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_3_0 = io_dis_uops_1_bits_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_4_0 = io_dis_uops_1_bits_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_5_0 = io_dis_uops_1_bits_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_6_0 = io_dis_uops_1_bits_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_7_0 = io_dis_uops_1_bits_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_8_0 = io_dis_uops_1_bits_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_9_0 = io_dis_uops_1_bits_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_issued_0 = io_dis_uops_1_bits_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_issued_partial_agen_0 = io_dis_uops_1_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_issued_partial_dgen_0 = io_dis_uops_1_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_iw_p1_speculative_child_0 = io_dis_uops_1_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_iw_p2_speculative_child_0 = io_dis_uops_1_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_p1_bypass_hint_0 = io_dis_uops_1_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_p2_bypass_hint_0 = io_dis_uops_1_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_p3_bypass_hint_0 = io_dis_uops_1_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_dis_col_sel_0 = io_dis_uops_1_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_dis_uops_1_bits_br_mask_0 = io_dis_uops_1_bits_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_1_bits_br_tag_0 = io_dis_uops_1_bits_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_1_bits_br_type_0 = io_dis_uops_1_bits_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_sfb_0 = io_dis_uops_1_bits_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_fence_0 = io_dis_uops_1_bits_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_fencei_0 = io_dis_uops_1_bits_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_sfence_0 = io_dis_uops_1_bits_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_amo_0 = io_dis_uops_1_bits_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_eret_0 = io_dis_uops_1_bits_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_sys_pc2epc_0 = io_dis_uops_1_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_rocc_0 = io_dis_uops_1_bits_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_mov_0 = io_dis_uops_1_bits_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_ftq_idx_0 = io_dis_uops_1_bits_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_edge_inst_0 = io_dis_uops_1_bits_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_pc_lob_0 = io_dis_uops_1_bits_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_taken_0 = io_dis_uops_1_bits_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_imm_rename_0 = io_dis_uops_1_bits_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_imm_sel_0 = io_dis_uops_1_bits_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_pimm_0 = io_dis_uops_1_bits_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_dis_uops_1_bits_imm_packed_0 = io_dis_uops_1_bits_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_op1_sel_0 = io_dis_uops_1_bits_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_op2_sel_0 = io_dis_uops_1_bits_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_ldst_0 = io_dis_uops_1_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_wen_0 = io_dis_uops_1_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_ren1_0 = io_dis_uops_1_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_ren2_0 = io_dis_uops_1_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_ren3_0 = io_dis_uops_1_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_swap12_0 = io_dis_uops_1_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_swap23_0 = io_dis_uops_1_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagIn_0 = io_dis_uops_1_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagOut_0 = io_dis_uops_1_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_fromint_0 = io_dis_uops_1_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_toint_0 = io_dis_uops_1_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_fastpipe_0 = io_dis_uops_1_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_fma_0 = io_dis_uops_1_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_div_0 = io_dis_uops_1_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_sqrt_0 = io_dis_uops_1_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_wflags_0 = io_dis_uops_1_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_vec_0 = io_dis_uops_1_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_rob_idx_0 = io_dis_uops_1_bits_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_ldq_idx_0 = io_dis_uops_1_bits_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_stq_idx_0 = io_dis_uops_1_bits_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_rxq_idx_0 = io_dis_uops_1_bits_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_pdst_0 = io_dis_uops_1_bits_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_prs1_0 = io_dis_uops_1_bits_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_prs2_0 = io_dis_uops_1_bits_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_prs3_0 = io_dis_uops_1_bits_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_ppred_0 = io_dis_uops_1_bits_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_prs1_busy_0 = io_dis_uops_1_bits_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_prs2_busy_0 = io_dis_uops_1_bits_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_prs3_busy_0 = io_dis_uops_1_bits_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_ppred_busy_0 = io_dis_uops_1_bits_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_stale_pdst_0 = io_dis_uops_1_bits_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_exception_0 = io_dis_uops_1_bits_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_dis_uops_1_bits_exc_cause_0 = io_dis_uops_1_bits_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_mem_cmd_0 = io_dis_uops_1_bits_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_mem_size_0 = io_dis_uops_1_bits_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_mem_signed_0 = io_dis_uops_1_bits_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_uses_ldq_0 = io_dis_uops_1_bits_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_uses_stq_0 = io_dis_uops_1_bits_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_unique_0 = io_dis_uops_1_bits_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_flush_on_commit_0 = io_dis_uops_1_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_csr_cmd_0 = io_dis_uops_1_bits_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_ldst_is_rs1_0 = io_dis_uops_1_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_ldst_0 = io_dis_uops_1_bits_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_lrs1_0 = io_dis_uops_1_bits_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_lrs2_0 = io_dis_uops_1_bits_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_lrs3_0 = io_dis_uops_1_bits_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_dst_rtype_0 = io_dis_uops_1_bits_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_lrs1_rtype_0 = io_dis_uops_1_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_lrs2_rtype_0 = io_dis_uops_1_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_frs3_en_0 = io_dis_uops_1_bits_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fcn_dw_0 = io_dis_uops_1_bits_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_fcn_op_0 = io_dis_uops_1_bits_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_val_0 = io_dis_uops_1_bits_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_fp_rm_0 = io_dis_uops_1_bits_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_fp_typ_0 = io_dis_uops_1_bits_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_xcpt_pf_if_0 = io_dis_uops_1_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_xcpt_ae_if_0 = io_dis_uops_1_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_xcpt_ma_if_0 = io_dis_uops_1_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_bp_debug_if_0 = io_dis_uops_1_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_bp_xcpt_if_0 = io_dis_uops_1_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_debug_fsrc_0 = io_dis_uops_1_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_debug_tsrc_0 = io_dis_uops_1_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_valid_0 = io_dis_uops_2_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_2_bits_inst_0 = io_dis_uops_2_bits_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_2_bits_debug_inst_0 = io_dis_uops_2_bits_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_rvc_0 = io_dis_uops_2_bits_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_dis_uops_2_bits_debug_pc_0 = io_dis_uops_2_bits_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iq_type_0_0 = io_dis_uops_2_bits_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iq_type_1_0 = io_dis_uops_2_bits_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iq_type_2_0 = io_dis_uops_2_bits_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iq_type_3_0 = io_dis_uops_2_bits_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_0_0 = io_dis_uops_2_bits_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_1_0 = io_dis_uops_2_bits_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_2_0 = io_dis_uops_2_bits_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_3_0 = io_dis_uops_2_bits_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_4_0 = io_dis_uops_2_bits_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_5_0 = io_dis_uops_2_bits_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_6_0 = io_dis_uops_2_bits_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_7_0 = io_dis_uops_2_bits_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_8_0 = io_dis_uops_2_bits_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_9_0 = io_dis_uops_2_bits_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iw_issued_0 = io_dis_uops_2_bits_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iw_issued_partial_agen_0 = io_dis_uops_2_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iw_issued_partial_dgen_0 = io_dis_uops_2_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_iw_p1_speculative_child_0 = io_dis_uops_2_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_iw_p2_speculative_child_0 = io_dis_uops_2_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iw_p1_bypass_hint_0 = io_dis_uops_2_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iw_p2_bypass_hint_0 = io_dis_uops_2_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iw_p3_bypass_hint_0 = io_dis_uops_2_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_dis_col_sel_0 = io_dis_uops_2_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_dis_uops_2_bits_br_mask_0 = io_dis_uops_2_bits_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_2_bits_br_tag_0 = io_dis_uops_2_bits_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_2_bits_br_type_0 = io_dis_uops_2_bits_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_sfb_0 = io_dis_uops_2_bits_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_fence_0 = io_dis_uops_2_bits_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_fencei_0 = io_dis_uops_2_bits_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_sfence_0 = io_dis_uops_2_bits_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_amo_0 = io_dis_uops_2_bits_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_eret_0 = io_dis_uops_2_bits_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_sys_pc2epc_0 = io_dis_uops_2_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_rocc_0 = io_dis_uops_2_bits_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_mov_0 = io_dis_uops_2_bits_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_ftq_idx_0 = io_dis_uops_2_bits_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_edge_inst_0 = io_dis_uops_2_bits_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_2_bits_pc_lob_0 = io_dis_uops_2_bits_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_taken_0 = io_dis_uops_2_bits_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_imm_rename_0 = io_dis_uops_2_bits_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_imm_sel_0 = io_dis_uops_2_bits_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_pimm_0 = io_dis_uops_2_bits_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_dis_uops_2_bits_imm_packed_0 = io_dis_uops_2_bits_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_op1_sel_0 = io_dis_uops_2_bits_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_op2_sel_0 = io_dis_uops_2_bits_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_ldst_0 = io_dis_uops_2_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_wen_0 = io_dis_uops_2_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_ren1_0 = io_dis_uops_2_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_ren2_0 = io_dis_uops_2_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_ren3_0 = io_dis_uops_2_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_swap12_0 = io_dis_uops_2_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_swap23_0 = io_dis_uops_2_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_fp_ctrl_typeTagIn_0 = io_dis_uops_2_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_fp_ctrl_typeTagOut_0 = io_dis_uops_2_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_fromint_0 = io_dis_uops_2_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_toint_0 = io_dis_uops_2_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_fastpipe_0 = io_dis_uops_2_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_fma_0 = io_dis_uops_2_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_div_0 = io_dis_uops_2_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_sqrt_0 = io_dis_uops_2_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_wflags_0 = io_dis_uops_2_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_vec_0 = io_dis_uops_2_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_2_bits_rob_idx_0 = io_dis_uops_2_bits_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_ldq_idx_0 = io_dis_uops_2_bits_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_stq_idx_0 = io_dis_uops_2_bits_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_rxq_idx_0 = io_dis_uops_2_bits_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_2_bits_pdst_0 = io_dis_uops_2_bits_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_2_bits_prs1_0 = io_dis_uops_2_bits_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_2_bits_prs2_0 = io_dis_uops_2_bits_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_2_bits_prs3_0 = io_dis_uops_2_bits_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_ppred_0 = io_dis_uops_2_bits_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_prs1_busy_0 = io_dis_uops_2_bits_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_prs2_busy_0 = io_dis_uops_2_bits_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_prs3_busy_0 = io_dis_uops_2_bits_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_ppred_busy_0 = io_dis_uops_2_bits_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_2_bits_stale_pdst_0 = io_dis_uops_2_bits_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_exception_0 = io_dis_uops_2_bits_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_dis_uops_2_bits_exc_cause_0 = io_dis_uops_2_bits_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_mem_cmd_0 = io_dis_uops_2_bits_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_mem_size_0 = io_dis_uops_2_bits_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_mem_signed_0 = io_dis_uops_2_bits_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_uses_ldq_0 = io_dis_uops_2_bits_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_uses_stq_0 = io_dis_uops_2_bits_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_unique_0 = io_dis_uops_2_bits_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_flush_on_commit_0 = io_dis_uops_2_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_csr_cmd_0 = io_dis_uops_2_bits_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_ldst_is_rs1_0 = io_dis_uops_2_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_2_bits_ldst_0 = io_dis_uops_2_bits_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_2_bits_lrs1_0 = io_dis_uops_2_bits_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_2_bits_lrs2_0 = io_dis_uops_2_bits_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_2_bits_lrs3_0 = io_dis_uops_2_bits_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_dst_rtype_0 = io_dis_uops_2_bits_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_lrs1_rtype_0 = io_dis_uops_2_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_lrs2_rtype_0 = io_dis_uops_2_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_frs3_en_0 = io_dis_uops_2_bits_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fcn_dw_0 = io_dis_uops_2_bits_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_fcn_op_0 = io_dis_uops_2_bits_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_val_0 = io_dis_uops_2_bits_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_fp_rm_0 = io_dis_uops_2_bits_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_fp_typ_0 = io_dis_uops_2_bits_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_xcpt_pf_if_0 = io_dis_uops_2_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_xcpt_ae_if_0 = io_dis_uops_2_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_xcpt_ma_if_0 = io_dis_uops_2_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_bp_debug_if_0 = io_dis_uops_2_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_bp_xcpt_if_0 = io_dis_uops_2_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_debug_fsrc_0 = io_dis_uops_2_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_debug_tsrc_0 = io_dis_uops_2_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_7_0 = io_fu_types_0_7; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_9_0 = io_fu_types_0_9; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-unit-age-ordered.scala:22:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-unit-age-ordered.scala:22:7] wire io_flush_pipeline_0 = io_flush_pipeline; // @[issue-unit-age-ordered.scala:22:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_tsc_reg_0 = io_tsc_reg; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_0 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_1 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_2 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_3 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_4 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_5 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_8 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire prs1_rebusys_0 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs2_rebusys_0 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs1_rebusys_0_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_1_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs2_rebusys_0_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_1_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs1_rebusys_0_2 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_1_2 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs2_rebusys_0_2 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_1_2 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire issue_slots_0_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_clear = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_iw_issued = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_ppred_busy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire _issue_slots_0_clear_T = 1'h0; // @[issue-unit-age-ordered.scala:199:49] wire iss_uops_0_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:241:22] wire _fu_code_match_T = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_1 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_2 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_3 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_4 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_5 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_8 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_10 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_11 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_12 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_13 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_14 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_18 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_19 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_20 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_21 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_22 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_23 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_26 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_28 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_29 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_30 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_31 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_32 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_36 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_37 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_38 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_39 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_40 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_41 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_44 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_46 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_47 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_48 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_49 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_50 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_54 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_55 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_56 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_57 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_58 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_59 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_62 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_64 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_65 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_66 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_67 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_68 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_72 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_73 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_74 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_75 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_76 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_77 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_80 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_82 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_83 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_84 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_85 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_86 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_90 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_91 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_92 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_93 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_94 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_95 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_98 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_100 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_101 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_102 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_103 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_104 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_108 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_109 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_110 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_111 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_112 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_113 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_116 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_118 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_119 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_120 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_121 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_122 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_126 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_127 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_128 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_129 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_130 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_131 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_134 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_136 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_137 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_138 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_139 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_140 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_144 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_145 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_146 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_147 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_148 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_149 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_152 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_154 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_155 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_156 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_157 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_158 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_162 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_163 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_164 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_165 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_166 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_167 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_170 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_172 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_173 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_174 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_175 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_176 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_180 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_181 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_182 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_183 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_184 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_185 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_188 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_190 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_191 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_192 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_193 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_194 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_198 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_199 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_200 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_201 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_202 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_203 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_206 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_208 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_209 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_210 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_211 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_212 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_216 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_217 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_218 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_219 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_220 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_221 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_224 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_226 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_227 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_228 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_229 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_230 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_234 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_235 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_236 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_237 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_238 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_239 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_242 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_244 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_245 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_246 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_247 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_248 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_252 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_253 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_254 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_255 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_256 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_257 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_260 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_262 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_263 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_264 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_265 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_266 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_270 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_271 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_272 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_273 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_274 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_275 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_278 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_280 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_281 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_282 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_283 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_284 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_288 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_289 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_290 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_291 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_292 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_293 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_296 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_298 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_299 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_300 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_301 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_302 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_306 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_307 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_308 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_309 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_310 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_311 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_314 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_316 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_317 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_318 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_319 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_320 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_324 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_325 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_326 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_327 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_328 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_329 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_332 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_334 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_335 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_336 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_337 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_338 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_342 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_343 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_344 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_345 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_346 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_347 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_350 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_352 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_353 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_354 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_355 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_356 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_360 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_361 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_362 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_363 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_364 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_365 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_368 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_370 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_371 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_372 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_373 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_374 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_378 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_379 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_380 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_381 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_382 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_383 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_386 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_388 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_389 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_390 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_391 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_392 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_396 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_397 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_398 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_399 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_400 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_401 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_404 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_406 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_407 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_408 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_409 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_410 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_414 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_415 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_416 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_417 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_418 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_419 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_422 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_424 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_425 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_426 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_427 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_428 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire io_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_6 = 1'h1; // @[issue-unit-age-ordered.scala:22:7] wire issue_slots_0_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] io_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] issue_slots_0_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] shamts_oh_0 = 3'h0; // @[issue-unit-age-ordered.scala:158:23] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] issue_slots_0_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] iss_uops_0_bits_inst; // @[issue-unit-age-ordered.scala:241:22] wire [31:0] iss_uops_0_bits_debug_inst; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_rvc; // @[issue-unit-age-ordered.scala:241:22] wire [39:0] iss_uops_0_bits_debug_pc; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iq_type_0; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iq_type_1; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iq_type_2; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iq_type_3; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_0; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_1; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_2; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_3; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_4; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_5; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_6; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_7; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_8; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_9; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_issued; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:241:22] wire [15:0] iss_uops_0_bits_br_mask; // @[issue-unit-age-ordered.scala:241:22] wire [3:0] iss_uops_0_bits_br_tag; // @[issue-unit-age-ordered.scala:241:22] wire [3:0] iss_uops_0_bits_br_type; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_sfb; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_fence; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_fencei; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_sfence; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_amo; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_eret; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_rocc; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_mov; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_ftq_idx; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_edge_inst; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_pc_lob; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_taken; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_imm_rename; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_imm_sel; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_pimm; // @[issue-unit-age-ordered.scala:241:22] wire [19:0] iss_uops_0_bits_imm_packed; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_op1_sel; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_op2_sel; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_rob_idx; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_ldq_idx; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_stq_idx; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_rxq_idx; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_pdst; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_prs1; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_prs2; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_prs3; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_ppred; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_prs1_busy; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_prs2_busy; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_prs3_busy; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_ppred_busy; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_stale_pdst; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_exception; // @[issue-unit-age-ordered.scala:241:22] wire [63:0] iss_uops_0_bits_exc_cause; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_mem_cmd; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_mem_size; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_mem_signed; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_uses_ldq; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_uses_stq; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_unique; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_csr_cmd; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_ldst; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_lrs1; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_lrs2; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_lrs3; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_dst_rtype; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_frs3_en; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fcn_dw; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_fcn_op; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_val; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_fp_rm; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_fp_typ; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:241:22] wire issue_slots_0_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_16_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_17_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_18_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_19_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_20_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_21_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_22_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_23_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_16_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_17_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_18_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_19_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_20_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_21_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_22_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_23_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_12_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_13_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_14_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_15_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_16_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_17_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_18_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_19_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_20_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_21_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_22_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_23_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_16_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_17_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_18_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_19_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_20_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_21_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_22_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_23_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_16_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_17_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_18_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_19_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_20_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_21_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_22_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_23_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_16_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_17_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_18_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_19_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_20_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_21_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_22_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_23_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_16_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_17_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_18_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_19_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_20_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_21_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_22_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_23_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_12_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_13_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_14_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_15_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_16_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_17_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_18_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_19_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_20_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_21_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_22_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_23_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_12_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_13_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_14_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_15_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_16_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_17_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_18_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_19_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_20_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_21_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_22_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_23_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_16_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_17_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_18_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_19_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_20_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_21_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_22_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_23_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_16_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_17_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_18_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_19_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_20_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_21_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_22_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_23_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_16_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_17_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_18_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_19_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_20_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_21_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_22_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_23_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_16_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_17_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_18_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_19_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_20_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_21_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_22_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_23_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_16_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_17_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_18_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_19_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_20_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_21_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_22_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_23_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_16_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_17_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_18_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_19_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_20_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_21_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_22_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_23_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_12_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_13_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_14_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_15_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_16_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_17_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_18_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_19_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_20_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_21_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_22_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_23_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_16_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_17_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_18_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_19_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_20_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_21_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_22_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_23_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_16_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_17_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_18_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_19_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_20_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_21_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_22_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_23_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_16_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_17_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_18_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_19_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_20_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_21_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_22_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_23_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_16_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_17_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_18_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_19_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_20_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_21_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_22_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_23_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_12_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_13_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_14_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_15_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_16_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_17_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_18_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_19_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_20_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_21_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_22_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_23_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_12_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_13_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_14_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_15_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_16_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_17_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_18_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_19_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_20_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_21_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_22_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_23_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_16_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_17_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_18_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_19_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_20_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_21_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_22_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_23_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_16_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_17_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_18_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_19_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_20_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_21_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_22_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_23_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_16_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_17_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_18_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_19_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_20_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_21_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_22_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_23_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_16_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_17_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_18_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_19_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_20_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_21_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_22_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_23_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_16_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_17_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_18_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_19_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_20_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_21_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_22_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_23_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_16_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_17_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_18_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_19_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_20_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_21_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_22_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_23_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_16_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_17_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_18_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_19_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_20_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_21_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_22_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_23_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_16_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_17_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_18_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_19_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_20_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_21_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_22_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_23_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_12_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_13_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_14_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_15_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_16_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_17_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_18_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_19_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_20_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_21_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_22_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_23_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_16_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_17_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_18_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_19_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_20_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_21_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_22_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_23_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_16_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_17_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_18_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_19_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_20_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_21_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_22_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_23_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_16_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_17_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_18_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_19_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_20_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_21_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_22_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_23_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_16_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_17_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_18_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_19_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_20_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_21_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_22_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_23_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_12_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_13_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_14_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_15_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_16_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_17_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_18_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_19_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_20_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_21_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_22_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_23_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_12_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_13_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_14_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_15_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_16_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_17_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_18_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_19_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_20_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_21_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_22_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_23_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_16_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_17_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_18_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_19_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_20_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_21_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_22_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_23_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_16_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_17_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_18_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_19_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_20_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_21_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_22_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_23_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_16_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_17_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_18_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_19_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_20_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_21_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_22_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_23_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_16_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_17_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_18_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_19_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_20_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_21_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_22_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_23_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_12_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_13_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_14_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_15_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_16_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_17_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_18_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_19_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_20_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_21_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_22_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_23_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_0_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_1_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_2_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_3_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_4_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_5_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_6_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_7_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_8_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_9_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_10_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_11_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_12_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_13_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_14_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_15_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_16_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_17_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_18_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_19_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_20_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_21_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_22_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_23_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire io_dis_uops_0_ready_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_ready_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_ready_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_iss_uops_0_bits_inst_0; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_iss_uops_0_bits_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_iss_uops_0_bits_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_iss_uops_0_bits_br_mask_0; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_iss_uops_0_bits_br_tag_0; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_iss_uops_0_bits_br_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_amo_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_eret_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_mov_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_taken_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_pimm_0; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_iss_uops_0_bits_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_pdst_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_ppred_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_iss_uops_0_bits_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_mem_size_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_unique_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_ldst_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_lrs1_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_lrs2_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_lrs3_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_val_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_valid_0; // @[issue-unit-age-ordered.scala:22:7] wire prs1_matches_0 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs2_matches_0 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs3_matches_0 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs1_wakeups_0 = io_wakeup_ports_0_valid_0 & prs1_matches_0; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_1 = io_wakeup_ports_1_valid_0 & prs1_matches_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs2_wakeups_0 = io_wakeup_ports_0_valid_0 & prs2_matches_0; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_1 = io_wakeup_ports_1_valid_0 & prs2_matches_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs3_wakeups_0 = io_wakeup_ports_0_valid_0 & prs3_matches_0; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_1 = io_wakeup_ports_1_valid_0 & prs3_matches_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire _T = prs1_wakeups_0 \| prs1_wakeups_1; // @[issue-unit-age-ordered.scala:47:89, :57:32] wire _WIRE_iw_p1_bypass_hint = _T & prs1_wakeups_0; // @[issue-unit-age-ordered.scala:39:35, :47:89, :57:{32,38}, :60:37] wire _T_12 = prs2_wakeups_0 \| prs2_wakeups_1; // @[issue-unit-age-ordered.scala:48:89, :65:32] wire _WIRE_prs2_busy = ~_T_12 & io_dis_uops_0_bits_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :65:{32,38}, :66:29] wire _WIRE_iw_p2_bypass_hint = _T_12 & prs2_wakeups_0; // @[issue-unit-age-ordered.scala:40:35, :48:89, :65:{32,38}, :68:37] wire _T_24 = prs3_wakeups_0 \| prs3_wakeups_1; // @[issue-unit-age-ordered.scala:49:89, :76:32] wire _WIRE_prs3_busy = ~_T_24 & io_dis_uops_0_bits_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :76:{32,38}, :77:29] wire _WIRE_iw_p3_bypass_hint = _T_24 & prs3_wakeups_0; // @[issue-unit-age-ordered.scala:41:35, :49:89, :76:{32,38}, :78:37] wire [1:0] _WIRE_lrs1_rtype = io_dis_uops_0_bits_uses_stq_0 ? 2'h2 : io_dis_uops_0_bits_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :103:43, :104:32] wire _WIRE_prs1_busy = ~io_dis_uops_0_bits_uses_stq_0 & ~_T & io_dis_uops_0_bits_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :57:{32,38}, :58:29, :62:116, :103:43, :105:32] wire prs1_matches_0_1 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_1_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs2_matches_0_1 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_1_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs3_matches_0_1 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_1_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs1_wakeups_0_1 = io_wakeup_ports_0_valid_0 & prs1_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_1_1 = io_wakeup_ports_1_valid_0 & prs1_matches_1_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs2_wakeups_0_1 = io_wakeup_ports_0_valid_0 & prs2_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_1_1 = io_wakeup_ports_1_valid_0 & prs2_matches_1_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs3_wakeups_0_1 = io_wakeup_ports_0_valid_0 & prs3_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_1_1 = io_wakeup_ports_1_valid_0 & prs3_matches_1_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire _T_35 = prs1_wakeups_0_1 \| prs1_wakeups_1_1; // @[issue-unit-age-ordered.scala:47:89, :57:32] wire [2:0] _WIRE_1_iw_p1_speculative_child = _T_35 ? 3'h0 : io_dis_uops_1_bits_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :57:{32,38}, :59:43] wire _WIRE_1_iw_p1_bypass_hint = _T_35 & prs1_wakeups_0_1; // @[issue-unit-age-ordered.scala:39:35, :47:89, :57:{32,38}, :60:37] wire _T_47 = prs2_wakeups_0_1 \| prs2_wakeups_1_1; // @[issue-unit-age-ordered.scala:48:89, :65:32] wire _WIRE_1_prs2_busy = ~_T_47 & io_dis_uops_1_bits_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :65:{32,38}, :66:29] wire [2:0] _WIRE_1_iw_p2_speculative_child = _T_47 ? 3'h0 : io_dis_uops_1_bits_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :65:{32,38}, :67:43] wire _WIRE_1_iw_p2_bypass_hint = _T_47 & prs2_wakeups_0_1; // @[issue-unit-age-ordered.scala:40:35, :48:89, :65:{32,38}, :68:37] wire _T_59 = prs3_wakeups_0_1 \| prs3_wakeups_1_1; // @[issue-unit-age-ordered.scala:49:89, :76:32] wire _WIRE_1_prs3_busy = ~_T_59 & io_dis_uops_1_bits_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :76:{32,38}, :77:29] wire _WIRE_1_iw_p3_bypass_hint = _T_59 & prs3_wakeups_0_1; // @[issue-unit-age-ordered.scala:41:35, :49:89, :76:{32,38}, :78:37] wire [1:0] _WIRE_1_lrs1_rtype = io_dis_uops_1_bits_uses_stq_0 ? 2'h2 : io_dis_uops_1_bits_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :103:43, :104:32] wire _WIRE_1_prs1_busy = ~io_dis_uops_1_bits_uses_stq_0 & ~_T_35 & io_dis_uops_1_bits_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :57:{32,38}, :58:29, :62:116, :103:43, :105:32] wire prs1_matches_0_2 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_2_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_1_2 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_2_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs2_matches_0_2 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_2_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_1_2 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_2_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs3_matches_0_2 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_2_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_1_2 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_2_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs1_wakeups_0_2 = io_wakeup_ports_0_valid_0 & prs1_matches_0_2; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_1_2 = io_wakeup_ports_1_valid_0 & prs1_matches_1_2; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs2_wakeups_0_2 = io_wakeup_ports_0_valid_0 & prs2_matches_0_2; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_1_2 = io_wakeup_ports_1_valid_0 & prs2_matches_1_2; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs3_wakeups_0_2 = io_wakeup_ports_0_valid_0 & prs3_matches_0_2; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_1_2 = io_wakeup_ports_1_valid_0 & prs3_matches_1_2; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire _T_70 = prs1_wakeups_0_2 \| prs1_wakeups_1_2; // @[issue-unit-age-ordered.scala:47:89, :57:32] wire _T_82 = prs2_wakeups_0_2 \| prs2_wakeups_1_2; // @[issue-unit-age-ordered.scala:48:89, :65:32] wire _T_94 = prs3_wakeups_0_2 \| prs3_wakeups_1_2; // @[issue-unit-age-ordered.scala:49:89, :76:32] wire _fu_code_match_T_6 = issue_slots_0_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_24 = issue_slots_1_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_1_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_42 = issue_slots_2_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_2_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_60 = issue_slots_3_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_3_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_78 = issue_slots_4_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_4_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_96 = issue_slots_5_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_5_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_114 = issue_slots_6_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_6_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_132 = issue_slots_7_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_7_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_150 = issue_slots_8_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_8_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_168 = issue_slots_9_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_9_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_186 = issue_slots_10_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_10_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_204 = issue_slots_11_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_11_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_222 = issue_slots_12_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_12_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_240 = issue_slots_13_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_13_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_258 = issue_slots_14_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_14_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_276 = issue_slots_15_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_15_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_294 = issue_slots_16_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_16_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_312 = issue_slots_17_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_17_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_330 = issue_slots_18_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_18_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_348 = issue_slots_19_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_19_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_366 = issue_slots_20_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_20_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_384 = issue_slots_21_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_21_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_402 = issue_slots_22_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_22_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_420 = issue_slots_23_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_23_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire issue_slots_0_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_0_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_0_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_0_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_0_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_0_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_0_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_0_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_0_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_0_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_0_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_0_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_0_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_1_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_1_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_1_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_1_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_1_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_1_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_1_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_1_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_1_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_1_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_1_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_1_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_2_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_2_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_2_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_2_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_2_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_2_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_2_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_2_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_2_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_2_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_2_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_2_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_3_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_3_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_3_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_3_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_3_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_3_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_3_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_3_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_3_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_3_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_3_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_3_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_4_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_4_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_4_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_4_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_4_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_4_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_4_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_4_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_4_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_4_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_4_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_4_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_5_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_5_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_5_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_5_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_5_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_5_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_5_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_5_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_5_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_5_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_5_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_5_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_6_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_6_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_6_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_6_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_6_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_6_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_6_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_6_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_6_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_6_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_6_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_6_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_7_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_7_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_7_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_7_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_7_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_7_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_7_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_7_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_7_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_7_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_7_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_7_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_8_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_8_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_8_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_8_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_8_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_8_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_8_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_8_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_8_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_8_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_8_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_8_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_9_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_9_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_9_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_9_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_9_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_9_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_9_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_9_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_9_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_9_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_9_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_9_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_10_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_10_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_10_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_10_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_10_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_10_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_10_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_10_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_10_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_10_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_10_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_10_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_11_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_11_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_11_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_11_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_11_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_11_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_11_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_11_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_11_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_11_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_11_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_11_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_12_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_12_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_12_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_12_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_12_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_12_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_12_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_12_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_12_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_12_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_12_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_12_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_12_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_12_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_12_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_12_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_12_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_12_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_12_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_12_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_12_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_12_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_12_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_12_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_13_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_13_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_13_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_13_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_13_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_13_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_13_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_13_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_13_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_13_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_13_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_13_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_13_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_13_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_13_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_13_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_13_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_13_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_13_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_13_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_13_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_13_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_13_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_13_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_14_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_14_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_14_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_14_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_14_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_14_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_14_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_14_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_14_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_14_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_14_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_14_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_14_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_14_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_14_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_14_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_14_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_14_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_14_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_14_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_14_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_14_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_14_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_14_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_15_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_15_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_15_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_15_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_15_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_15_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_15_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_15_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_15_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_15_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_15_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_15_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_15_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_15_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_15_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_15_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_15_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_15_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_15_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_15_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_15_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_15_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_15_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_15_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_16_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_16_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_16_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_16_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_16_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_16_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_16_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_16_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_16_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_16_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_16_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_16_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_16_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_16_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_16_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_16_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_16_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_16_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_16_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_16_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_16_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_16_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_16_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_16_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_16_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_16_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_16_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_16_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_16_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_16_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_16_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_16_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_16_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_16_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_16_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_16_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_16_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_16_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_16_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_17_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_17_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_17_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_17_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_17_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_17_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_17_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_17_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_17_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_17_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_17_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_17_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_17_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_17_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_17_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_17_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_17_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_17_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_17_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_17_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_17_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_17_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_17_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_17_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_17_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_17_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_17_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_17_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_17_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_17_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_17_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_17_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_17_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_17_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_17_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_17_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_17_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_17_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_17_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_18_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_18_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_18_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_18_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_18_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_18_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_18_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_18_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_18_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_18_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_18_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_18_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_18_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_18_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_18_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_18_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_18_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_18_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_18_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_18_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_18_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_18_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_18_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_18_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_18_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_18_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_18_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_18_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_18_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_18_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_18_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_18_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_18_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_18_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_18_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_18_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_18_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_18_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_18_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_19_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_19_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_19_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_19_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_19_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_19_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_19_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_19_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_19_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_19_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_19_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_19_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_19_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_19_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_19_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_19_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_19_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_19_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_19_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_19_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_19_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_19_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_19_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_19_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_19_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_19_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_19_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_19_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_19_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_19_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_19_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_19_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_19_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_19_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_19_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_19_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_19_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_19_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_19_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_20_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_20_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_20_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_20_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_20_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_20_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_20_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_20_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_20_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_20_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_20_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_20_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_20_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_20_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_20_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_20_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_20_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_20_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_20_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_20_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_20_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_20_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_20_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_20_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_20_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_20_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_20_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_20_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_20_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_20_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_20_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_20_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_20_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_20_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_20_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_20_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_20_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_20_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_20_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_21_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_21_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_21_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_21_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_21_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_21_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_21_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_21_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_21_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_21_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_21_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_21_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_21_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_21_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_21_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_21_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_21_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_21_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_21_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_21_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_21_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_21_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_21_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_21_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_21_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_21_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_21_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_21_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_21_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_21_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_21_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_21_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_21_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_21_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_21_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_21_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_21_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_21_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_21_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_22_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_22_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_22_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_22_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_22_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_22_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_22_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_22_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_22_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_22_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_22_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_22_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_22_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_22_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_22_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_22_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_22_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_22_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_22_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_22_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_22_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_22_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_22_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_22_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_22_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_22_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_22_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_22_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_22_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_22_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_22_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_22_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_22_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_22_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_22_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_22_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_22_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_22_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_22_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_23_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_23_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_23_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_23_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_23_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_23_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_23_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_23_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_23_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_23_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_23_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_23_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_23_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_23_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_23_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_23_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_23_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_23_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_23_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_23_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_23_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_23_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_23_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_23_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_23_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_23_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_23_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_23_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_23_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_23_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_23_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_23_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_23_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_23_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_23_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_23_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_23_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_23_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_23_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_clear; // @[issue-unit-age-ordered.scala:122:28] wire vacants_0 = ~issue_slots_0_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_1 = ~issue_slots_1_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_2 = ~issue_slots_2_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_3 = ~issue_slots_3_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_4 = ~issue_slots_4_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_5 = ~issue_slots_5_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_6 = ~issue_slots_6_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_7 = ~issue_slots_7_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_8 = ~issue_slots_8_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_9 = ~issue_slots_9_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_10 = ~issue_slots_10_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_11 = ~issue_slots_11_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_12 = ~issue_slots_12_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_13 = ~issue_slots_13_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_14 = ~issue_slots_14_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_15 = ~issue_slots_15_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_16 = ~issue_slots_16_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_17 = ~issue_slots_17_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_18 = ~issue_slots_18_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_19 = ~issue_slots_19_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_20 = ~issue_slots_20_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_21 = ~issue_slots_21_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_22 = ~issue_slots_22_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_23 = ~issue_slots_23_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_24 = ~io_dis_uops_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :157:82] wire vacants_25 = ~io_dis_uops_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :157:82] wire vacants_26 = ~io_dis_uops_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :157:82] wire [2:0] shamts_oh_12_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_13_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_14_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_15_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_16_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_17_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_18_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_19_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_20_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_21_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_22_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_23_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_24_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_25_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_26_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_1; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_2; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_3; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_4; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_5; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_6; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_7; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_8; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_9; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_10; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_11; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_12; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_13; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_14; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_15; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_16; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_17; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_18; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_19; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_20; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_21; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_22; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_23; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_24; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_25; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_26; // @[issue-unit-age-ordered.scala:158:23] assign shamts_oh_1 = {2'h0, vacants_0}; // @[issue-unit-age-ordered.scala:141:19, :157:38, :158:23, :174:20] wire _GEN = vacants_0 \| vacants_1; // @[issue-unit-age-ordered.scala:157:38, :174:47] wire _shamts_oh_2_T; // @[issue-unit-age-ordered.scala:174:47] assign _shamts_oh_2_T = _GEN; // @[issue-unit-age-ordered.scala:174:47] wire _shamts_oh_3_T; // @[issue-unit-age-ordered.scala:174:47] assign _shamts_oh_3_T = _GEN; // @[issue-unit-age-ordered.scala:174:47] wire _shamts_oh_4_T; // @[issue-unit-age-ordered.scala:174:47] assign _shamts_oh_4_T = _GEN; // @[issue-unit-age-ordered.scala:174:47] wire _shamts_oh_5_T; // @[issue-unit-age-ordered.scala:174:47] assign _shamts_oh_5_T = _GEN; // @[issue-unit-age-ordered.scala:174:47] assign shamts_oh_2 = {2'h0, _shamts_oh_2_T}; // @[issue-unit-age-ordered.scala:141:19, :158:23, :174:{20,47}] wire _shamts_oh_3_T_1 = _shamts_oh_3_T \| vacants_2; // @[issue-unit-age-ordered.scala:157:38, :174:47] assign shamts_oh_3 = {2'h0, _shamts_oh_3_T_1}; // @[issue-unit-age-ordered.scala:141:19, :158:23, :174:{20,47}] wire _shamts_oh_4_T_1 = _shamts_oh_4_T \| vacants_2; // @[issue-unit-age-ordered.scala:157:38, :174:47] wire _shamts_oh_4_T_2 = _shamts_oh_4_T_1 \| vacants_3; // @[issue-unit-age-ordered.scala:157:38, :174:47] assign shamts_oh_4 = {2'h0, _shamts_oh_4_T_2}; // @[issue-unit-age-ordered.scala:141:19, :158:23, :174:{20,47}] wire _shamts_oh_5_T_1 = _shamts_oh_5_T \| vacants_2; // @[issue-unit-age-ordered.scala:157:38, :174:47] wire _shamts_oh_5_T_2 = _shamts_oh_5_T_1 \| vacants_3; // @[issue-unit-age-ordered.scala:157:38, :174:47] wire _shamts_oh_5_T_3 = _shamts_oh_5_T_2 \| vacants_4; // @[issue-unit-age-ordered.scala:157:38, :174:47] assign shamts_oh_5 = {2'h0, _shamts_oh_5_T_3}; // @[issue-unit-age-ordered.scala:141:19, :158:23, :174:{20,47}] wire [1:0] shamts_oh_6_next; // @[issue-unit-age-ordered.scala:161:21] wire _shamts_oh_6_T = ~(\|shamts_oh_5); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_6_T_1 = _shamts_oh_6_T & vacants_5; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_6_T_2 = shamts_oh_5[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_6_T_3 = ~_shamts_oh_6_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_6_T_4 = _shamts_oh_6_T_3 & vacants_5; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_6_next_T = {shamts_oh_5, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_6_next = _shamts_oh_6_T_1 ? 2'h1 : _shamts_oh_6_T_4 ? _shamts_oh_6_next_T[1:0] : shamts_oh_5[1:0]; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_6 = {1'h0, shamts_oh_6_next}; // @[issue-unit-age-ordered.scala:158:23, :161:21, :176:20] wire [1:0] shamts_oh_7_next; // @[issue-unit-age-ordered.scala:161:21] wire _shamts_oh_7_T = ~(\|shamts_oh_6); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_7_T_1 = _shamts_oh_7_T & vacants_6; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_7_T_2 = shamts_oh_6[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_7_T_3 = ~_shamts_oh_7_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_7_T_4 = _shamts_oh_7_T_3 & vacants_6; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_7_next_T = {shamts_oh_6, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_7_next = _shamts_oh_7_T_1 ? 2'h1 : _shamts_oh_7_T_4 ? _shamts_oh_7_next_T[1:0] : shamts_oh_6[1:0]; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_7 = {1'h0, shamts_oh_7_next}; // @[issue-unit-age-ordered.scala:158:23, :161:21, :176:20] wire [1:0] shamts_oh_8_next; // @[issue-unit-age-ordered.scala:161:21] wire _shamts_oh_8_T = ~(\|shamts_oh_7); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_8_T_1 = _shamts_oh_8_T & vacants_7; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_8_T_2 = shamts_oh_7[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_8_T_3 = ~_shamts_oh_8_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_8_T_4 = _shamts_oh_8_T_3 & vacants_7; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_8_next_T = {shamts_oh_7, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_8_next = _shamts_oh_8_T_1 ? 2'h1 : _shamts_oh_8_T_4 ? _shamts_oh_8_next_T[1:0] : shamts_oh_7[1:0]; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_8 = {1'h0, shamts_oh_8_next}; // @[issue-unit-age-ordered.scala:158:23, :161:21, :176:20] wire [1:0] shamts_oh_9_next; // @[issue-unit-age-ordered.scala:161:21] wire _shamts_oh_9_T = ~(\|shamts_oh_8); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_9_T_1 = _shamts_oh_9_T & vacants_8; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_9_T_2 = shamts_oh_8[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_9_T_3 = ~_shamts_oh_9_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_9_T_4 = _shamts_oh_9_T_3 & vacants_8; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_9_next_T = {shamts_oh_8, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_9_next = _shamts_oh_9_T_1 ? 2'h1 : _shamts_oh_9_T_4 ? _shamts_oh_9_next_T[1:0] : shamts_oh_8[1:0]; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_9 = {1'h0, shamts_oh_9_next}; // @[issue-unit-age-ordered.scala:158:23, :161:21, :176:20] wire [1:0] shamts_oh_10_next; // @[issue-unit-age-ordered.scala:161:21] wire _shamts_oh_10_T = ~(\|shamts_oh_9); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_10_T_1 = _shamts_oh_10_T & vacants_9; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_10_T_2 = shamts_oh_9[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_10_T_3 = ~_shamts_oh_10_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_10_T_4 = _shamts_oh_10_T_3 & vacants_9; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_10_next_T = {shamts_oh_9, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_10_next = _shamts_oh_10_T_1 ? 2'h1 : _shamts_oh_10_T_4 ? _shamts_oh_10_next_T[1:0] : shamts_oh_9[1:0]; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_10 = {1'h0, shamts_oh_10_next}; // @[issue-unit-age-ordered.scala:158:23, :161:21, :176:20] wire [1:0] shamts_oh_11_next; // @[issue-unit-age-ordered.scala:161:21] wire _shamts_oh_11_T = ~(\|shamts_oh_10); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_11_T_1 = _shamts_oh_11_T & vacants_10; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_11_T_2 = shamts_oh_10[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_11_T_3 = ~_shamts_oh_11_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_11_T_4 = _shamts_oh_11_T_3 & vacants_10; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_11_next_T = {shamts_oh_10, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_11_next = _shamts_oh_11_T_1 ? 2'h1 : _shamts_oh_11_T_4 ? _shamts_oh_11_next_T[1:0] : shamts_oh_10[1:0]; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_11 = {1'h0, shamts_oh_11_next}; // @[issue-unit-age-ordered.scala:158:23, :161:21, :176:20] assign shamts_oh_12 = shamts_oh_12_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_12_T = ~(\|shamts_oh_11); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_12_T_1 = _shamts_oh_12_T & vacants_11; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_12_T_2 = shamts_oh_11[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_12_T_3 = ~_shamts_oh_12_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_12_T_4 = _shamts_oh_12_T_3 & vacants_11; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_12_next_T = {shamts_oh_11, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_12_next = _shamts_oh_12_T_1 ? 3'h1 : _shamts_oh_12_T_4 ? _shamts_oh_12_next_T[2:0] : shamts_oh_11; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_13 = shamts_oh_13_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_13_T = ~(\|shamts_oh_12); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_13_T_1 = _shamts_oh_13_T & vacants_12; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_13_T_2 = shamts_oh_12[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_13_T_3 = ~_shamts_oh_13_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_13_T_4 = _shamts_oh_13_T_3 & vacants_12; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_13_next_T = {shamts_oh_12, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_13_next = _shamts_oh_13_T_1 ? 3'h1 : _shamts_oh_13_T_4 ? _shamts_oh_13_next_T[2:0] : shamts_oh_12; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_14 = shamts_oh_14_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_14_T = ~(\|shamts_oh_13); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_14_T_1 = _shamts_oh_14_T & vacants_13; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_14_T_2 = shamts_oh_13[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_14_T_3 = ~_shamts_oh_14_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_14_T_4 = _shamts_oh_14_T_3 & vacants_13; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_14_next_T = {shamts_oh_13, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_14_next = _shamts_oh_14_T_1 ? 3'h1 : _shamts_oh_14_T_4 ? _shamts_oh_14_next_T[2:0] : shamts_oh_13; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_15 = shamts_oh_15_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_15_T = ~(\|shamts_oh_14); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_15_T_1 = _shamts_oh_15_T & vacants_14; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_15_T_2 = shamts_oh_14[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_15_T_3 = ~_shamts_oh_15_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_15_T_4 = _shamts_oh_15_T_3 & vacants_14; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_15_next_T = {shamts_oh_14, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_15_next = _shamts_oh_15_T_1 ? 3'h1 : _shamts_oh_15_T_4 ? _shamts_oh_15_next_T[2:0] : shamts_oh_14; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_16 = shamts_oh_16_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_16_T = ~(\|shamts_oh_15); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_16_T_1 = _shamts_oh_16_T & vacants_15; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_16_T_2 = shamts_oh_15[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_16_T_3 = ~_shamts_oh_16_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_16_T_4 = _shamts_oh_16_T_3 & vacants_15; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_16_next_T = {shamts_oh_15, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_16_next = _shamts_oh_16_T_1 ? 3'h1 : _shamts_oh_16_T_4 ? _shamts_oh_16_next_T[2:0] : shamts_oh_15; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_17 = shamts_oh_17_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_17_T = ~(\|shamts_oh_16); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_17_T_1 = _shamts_oh_17_T & vacants_16; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_17_T_2 = shamts_oh_16[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_17_T_3 = ~_shamts_oh_17_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_17_T_4 = _shamts_oh_17_T_3 & vacants_16; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_17_next_T = {shamts_oh_16, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_17_next = _shamts_oh_17_T_1 ? 3'h1 : _shamts_oh_17_T_4 ? _shamts_oh_17_next_T[2:0] : shamts_oh_16; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_18 = shamts_oh_18_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_18_T = ~(\|shamts_oh_17); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_18_T_1 = _shamts_oh_18_T & vacants_17; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_18_T_2 = shamts_oh_17[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_18_T_3 = ~_shamts_oh_18_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_18_T_4 = _shamts_oh_18_T_3 & vacants_17; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_18_next_T = {shamts_oh_17, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_18_next = _shamts_oh_18_T_1 ? 3'h1 : _shamts_oh_18_T_4 ? _shamts_oh_18_next_T[2:0] : shamts_oh_17; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_19 = shamts_oh_19_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_19_T = ~(\|shamts_oh_18); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_19_T_1 = _shamts_oh_19_T & vacants_18; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_19_T_2 = shamts_oh_18[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_19_T_3 = ~_shamts_oh_19_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_19_T_4 = _shamts_oh_19_T_3 & vacants_18; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_19_next_T = {shamts_oh_18, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_19_next = _shamts_oh_19_T_1 ? 3'h1 : _shamts_oh_19_T_4 ? _shamts_oh_19_next_T[2:0] : shamts_oh_18; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_20 = shamts_oh_20_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_20_T = ~(\|shamts_oh_19); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_20_T_1 = _shamts_oh_20_T & vacants_19; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_20_T_2 = shamts_oh_19[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_20_T_3 = ~_shamts_oh_20_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_20_T_4 = _shamts_oh_20_T_3 & vacants_19; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_20_next_T = {shamts_oh_19, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_20_next = _shamts_oh_20_T_1 ? 3'h1 : _shamts_oh_20_T_4 ? _shamts_oh_20_next_T[2:0] : shamts_oh_19; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_21 = shamts_oh_21_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_21_T = ~(\|shamts_oh_20); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_21_T_1 = _shamts_oh_21_T & vacants_20; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_21_T_2 = shamts_oh_20[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_21_T_3 = ~_shamts_oh_21_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_21_T_4 = _shamts_oh_21_T_3 & vacants_20; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_21_next_T = {shamts_oh_20, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_21_next = _shamts_oh_21_T_1 ? 3'h1 : _shamts_oh_21_T_4 ? _shamts_oh_21_next_T[2:0] : shamts_oh_20; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_22 = shamts_oh_22_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_22_T = ~(\|shamts_oh_21); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_22_T_1 = _shamts_oh_22_T & vacants_21; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_22_T_2 = shamts_oh_21[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_22_T_3 = ~_shamts_oh_22_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_22_T_4 = _shamts_oh_22_T_3 & vacants_21; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_22_next_T = {shamts_oh_21, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_22_next = _shamts_oh_22_T_1 ? 3'h1 : _shamts_oh_22_T_4 ? _shamts_oh_22_next_T[2:0] : shamts_oh_21; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_23 = shamts_oh_23_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_23_T = ~(\|shamts_oh_22); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_23_T_1 = _shamts_oh_23_T & vacants_22; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_23_T_2 = shamts_oh_22[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_23_T_3 = ~_shamts_oh_23_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_23_T_4 = _shamts_oh_23_T_3 & vacants_22; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_23_next_T = {shamts_oh_22, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_23_next = _shamts_oh_23_T_1 ? 3'h1 : _shamts_oh_23_T_4 ? _shamts_oh_23_next_T[2:0] : shamts_oh_22; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_24 = shamts_oh_24_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_24_T = ~(\|shamts_oh_23); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_24_T_1 = _shamts_oh_24_T & vacants_23; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_24_T_2 = shamts_oh_23[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_24_T_3 = ~_shamts_oh_24_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_24_T_4 = _shamts_oh_24_T_3 & vacants_23; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_24_next_T = {shamts_oh_23, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_24_next = _shamts_oh_24_T_1 ? 3'h1 : _shamts_oh_24_T_4 ? _shamts_oh_24_next_T[2:0] : shamts_oh_23; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_25 = shamts_oh_25_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_25_T = shamts_oh_24 == 3'h0; // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_25_T_1 = _shamts_oh_25_T & vacants_24; // @[issue-unit-age-ordered.scala:157:82, :163:{21,29}] wire _shamts_oh_25_T_2 = shamts_oh_24[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_25_T_3 = ~_shamts_oh_25_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_25_T_4 = _shamts_oh_25_T_3 & vacants_24; // @[issue-unit-age-ordered.scala:157:82, :165:{19,36}] wire [3:0] _shamts_oh_25_next_T = {shamts_oh_24, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_25_next = _shamts_oh_25_T_1 ? 3'h1 : _shamts_oh_25_T_4 ? _shamts_oh_25_next_T[2:0] : shamts_oh_24; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_26 = shamts_oh_26_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_26_T = shamts_oh_25 == 3'h0; // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_26_T_1 = _shamts_oh_26_T & vacants_25; // @[issue-unit-age-ordered.scala:157:82, :163:{21,29}] wire _shamts_oh_26_T_2 = shamts_oh_25[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_26_T_3 = ~_shamts_oh_26_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_26_T_4 = _shamts_oh_26_T_3 & vacants_25; // @[issue-unit-age-ordered.scala:157:82, :165:{19,36}] wire [3:0] _shamts_oh_26_next_T = {shamts_oh_25, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_26_next = _shamts_oh_26_T_1 ? 3'h1 : _shamts_oh_26_T_4 ? _shamts_oh_26_next_T[2:0] : shamts_oh_25; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] wire _will_be_valid_T = ~io_dis_uops_0_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7, :185:57] wire _will_be_valid_T_1 = io_dis_uops_0_valid_0 & _will_be_valid_T; // @[issue-unit-age-ordered.scala:22:7, :184:77, :185:57] wire _will_be_valid_T_2 = ~io_dis_uops_0_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :186:57] wire _will_be_valid_T_3 = _will_be_valid_T_1 & _will_be_valid_T_2; // @[issue-unit-age-ordered.scala:184:77, :185:80, :186:57] wire _will_be_valid_T_4 = ~io_dis_uops_0_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :187:57] wire will_be_valid_24 = _will_be_valid_T_3 & _will_be_valid_T_4; // @[issue-unit-age-ordered.scala:185:80, :186:79, :187:57] wire _will_be_valid_T_5 = ~io_dis_uops_1_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7, :185:57] wire _will_be_valid_T_6 = io_dis_uops_1_valid_0 & _will_be_valid_T_5; // @[issue-unit-age-ordered.scala:22:7, :184:77, :185:57] wire _will_be_valid_T_7 = ~io_dis_uops_1_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :186:57] wire _will_be_valid_T_8 = _will_be_valid_T_6 & _will_be_valid_T_7; // @[issue-unit-age-ordered.scala:184:77, :185:80, :186:57] wire _will_be_valid_T_9 = ~io_dis_uops_1_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :187:57] wire will_be_valid_25 = _will_be_valid_T_8 & _will_be_valid_T_9; // @[issue-unit-age-ordered.scala:185:80, :186:79, :187:57] wire _will_be_valid_T_10 = ~io_dis_uops_2_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7, :185:57] wire _will_be_valid_T_11 = io_dis_uops_2_valid_0 & _will_be_valid_T_10; // @[issue-unit-age-ordered.scala:22:7, :184:77, :185:57] wire _will_be_valid_T_12 = ~io_dis_uops_2_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :186:57] wire _will_be_valid_T_13 = _will_be_valid_T_11 & _will_be_valid_T_12; // @[issue-unit-age-ordered.scala:184:77, :185:80, :186:57] wire _will_be_valid_T_14 = ~io_dis_uops_2_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :187:57] wire will_be_valid_26 = _will_be_valid_T_13 & _will_be_valid_T_14; // @[issue-unit-age-ordered.scala:185:80, :186:79, :187:57] wire _T_156 = shamts_oh_2 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_157 = shamts_oh_3 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_0_in_uop_valid = _T_157 ? issue_slots_3_will_be_valid : _T_156 ? issue_slots_2_will_be_valid : shamts_oh_1 == 3'h1 & issue_slots_1_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_0_in_uop_bits_debug_tsrc = _T_157 ? issue_slots_3_out_uop_debug_tsrc : _T_156 ? issue_slots_2_out_uop_debug_tsrc : issue_slots_1_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_debug_fsrc = _T_157 ? issue_slots_3_out_uop_debug_fsrc : _T_156 ? issue_slots_2_out_uop_debug_fsrc : issue_slots_1_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_bp_xcpt_if = _T_157 ? issue_slots_3_out_uop_bp_xcpt_if : _T_156 ? issue_slots_2_out_uop_bp_xcpt_if : issue_slots_1_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_bp_debug_if = _T_157 ? issue_slots_3_out_uop_bp_debug_if : _T_156 ? issue_slots_2_out_uop_bp_debug_if : issue_slots_1_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_xcpt_ma_if = _T_157 ? issue_slots_3_out_uop_xcpt_ma_if : _T_156 ? issue_slots_2_out_uop_xcpt_ma_if : issue_slots_1_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_xcpt_ae_if = _T_157 ? issue_slots_3_out_uop_xcpt_ae_if : _T_156 ? issue_slots_2_out_uop_xcpt_ae_if : issue_slots_1_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_xcpt_pf_if = _T_157 ? issue_slots_3_out_uop_xcpt_pf_if : _T_156 ? issue_slots_2_out_uop_xcpt_pf_if : issue_slots_1_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_typ = _T_157 ? issue_slots_3_out_uop_fp_typ : _T_156 ? issue_slots_2_out_uop_fp_typ : issue_slots_1_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_rm = _T_157 ? issue_slots_3_out_uop_fp_rm : _T_156 ? issue_slots_2_out_uop_fp_rm : issue_slots_1_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_val = _T_157 ? issue_slots_3_out_uop_fp_val : _T_156 ? issue_slots_2_out_uop_fp_val : issue_slots_1_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fcn_op = _T_157 ? issue_slots_3_out_uop_fcn_op : _T_156 ? issue_slots_2_out_uop_fcn_op : issue_slots_1_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fcn_dw = _T_157 ? issue_slots_3_out_uop_fcn_dw : _T_156 ? issue_slots_2_out_uop_fcn_dw : issue_slots_1_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_frs3_en = _T_157 ? issue_slots_3_out_uop_frs3_en : _T_156 ? issue_slots_2_out_uop_frs3_en : issue_slots_1_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs2_rtype = _T_157 ? issue_slots_3_out_uop_lrs2_rtype : _T_156 ? issue_slots_2_out_uop_lrs2_rtype : issue_slots_1_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs1_rtype = _T_157 ? issue_slots_3_out_uop_lrs1_rtype : _T_156 ? issue_slots_2_out_uop_lrs1_rtype : issue_slots_1_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_dst_rtype = _T_157 ? issue_slots_3_out_uop_dst_rtype : _T_156 ? issue_slots_2_out_uop_dst_rtype : issue_slots_1_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs3 = _T_157 ? issue_slots_3_out_uop_lrs3 : _T_156 ? issue_slots_2_out_uop_lrs3 : issue_slots_1_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs2 = _T_157 ? issue_slots_3_out_uop_lrs2 : _T_156 ? issue_slots_2_out_uop_lrs2 : issue_slots_1_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs1 = _T_157 ? issue_slots_3_out_uop_lrs1 : _T_156 ? issue_slots_2_out_uop_lrs1 : issue_slots_1_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ldst = _T_157 ? issue_slots_3_out_uop_ldst : _T_156 ? issue_slots_2_out_uop_ldst : issue_slots_1_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ldst_is_rs1 = _T_157 ? issue_slots_3_out_uop_ldst_is_rs1 : _T_156 ? issue_slots_2_out_uop_ldst_is_rs1 : issue_slots_1_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_csr_cmd = _T_157 ? issue_slots_3_out_uop_csr_cmd : _T_156 ? issue_slots_2_out_uop_csr_cmd : issue_slots_1_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_flush_on_commit = _T_157 ? issue_slots_3_out_uop_flush_on_commit : _T_156 ? issue_slots_2_out_uop_flush_on_commit : issue_slots_1_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_unique = _T_157 ? issue_slots_3_out_uop_is_unique : _T_156 ? issue_slots_2_out_uop_is_unique : issue_slots_1_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_uses_stq = _T_157 ? issue_slots_3_out_uop_uses_stq : _T_156 ? issue_slots_2_out_uop_uses_stq : issue_slots_1_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_uses_ldq = _T_157 ? issue_slots_3_out_uop_uses_ldq : _T_156 ? issue_slots_2_out_uop_uses_ldq : issue_slots_1_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_mem_signed = _T_157 ? issue_slots_3_out_uop_mem_signed : _T_156 ? issue_slots_2_out_uop_mem_signed : issue_slots_1_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_mem_size = _T_157 ? issue_slots_3_out_uop_mem_size : _T_156 ? issue_slots_2_out_uop_mem_size : issue_slots_1_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_mem_cmd = _T_157 ? issue_slots_3_out_uop_mem_cmd : _T_156 ? issue_slots_2_out_uop_mem_cmd : issue_slots_1_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_exc_cause = _T_157 ? issue_slots_3_out_uop_exc_cause : _T_156 ? issue_slots_2_out_uop_exc_cause : issue_slots_1_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_exception = _T_157 ? issue_slots_3_out_uop_exception : _T_156 ? issue_slots_2_out_uop_exception : issue_slots_1_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_stale_pdst = _T_157 ? issue_slots_3_out_uop_stale_pdst : _T_156 ? issue_slots_2_out_uop_stale_pdst : issue_slots_1_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ppred_busy = _T_157 ? issue_slots_3_out_uop_ppred_busy : _T_156 ? issue_slots_2_out_uop_ppred_busy : issue_slots_1_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs3_busy = _T_157 ? issue_slots_3_out_uop_prs3_busy : _T_156 ? issue_slots_2_out_uop_prs3_busy : issue_slots_1_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs2_busy = _T_157 ? issue_slots_3_out_uop_prs2_busy : _T_156 ? issue_slots_2_out_uop_prs2_busy : issue_slots_1_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs1_busy = _T_157 ? issue_slots_3_out_uop_prs1_busy : _T_156 ? issue_slots_2_out_uop_prs1_busy : issue_slots_1_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ppred = _T_157 ? issue_slots_3_out_uop_ppred : _T_156 ? issue_slots_2_out_uop_ppred : issue_slots_1_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs3 = _T_157 ? issue_slots_3_out_uop_prs3 : _T_156 ? issue_slots_2_out_uop_prs3 : issue_slots_1_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs2 = _T_157 ? issue_slots_3_out_uop_prs2 : _T_156 ? issue_slots_2_out_uop_prs2 : issue_slots_1_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs1 = _T_157 ? issue_slots_3_out_uop_prs1 : _T_156 ? issue_slots_2_out_uop_prs1 : issue_slots_1_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_pdst = _T_157 ? issue_slots_3_out_uop_pdst : _T_156 ? issue_slots_2_out_uop_pdst : issue_slots_1_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_rxq_idx = _T_157 ? issue_slots_3_out_uop_rxq_idx : _T_156 ? issue_slots_2_out_uop_rxq_idx : issue_slots_1_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_stq_idx = _T_157 ? issue_slots_3_out_uop_stq_idx : _T_156 ? issue_slots_2_out_uop_stq_idx : issue_slots_1_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ldq_idx = _T_157 ? issue_slots_3_out_uop_ldq_idx : _T_156 ? issue_slots_2_out_uop_ldq_idx : issue_slots_1_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_rob_idx = _T_157 ? issue_slots_3_out_uop_rob_idx : _T_156 ? issue_slots_2_out_uop_rob_idx : issue_slots_1_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_vec = _T_157 ? issue_slots_3_out_uop_fp_ctrl_vec : _T_156 ? issue_slots_2_out_uop_fp_ctrl_vec : issue_slots_1_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_wflags = _T_157 ? issue_slots_3_out_uop_fp_ctrl_wflags : _T_156 ? issue_slots_2_out_uop_fp_ctrl_wflags : issue_slots_1_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_sqrt = _T_157 ? issue_slots_3_out_uop_fp_ctrl_sqrt : _T_156 ? issue_slots_2_out_uop_fp_ctrl_sqrt : issue_slots_1_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_div = _T_157 ? issue_slots_3_out_uop_fp_ctrl_div : _T_156 ? issue_slots_2_out_uop_fp_ctrl_div : issue_slots_1_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_fma = _T_157 ? issue_slots_3_out_uop_fp_ctrl_fma : _T_156 ? issue_slots_2_out_uop_fp_ctrl_fma : issue_slots_1_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_fastpipe = _T_157 ? issue_slots_3_out_uop_fp_ctrl_fastpipe : _T_156 ? issue_slots_2_out_uop_fp_ctrl_fastpipe : issue_slots_1_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_toint = _T_157 ? issue_slots_3_out_uop_fp_ctrl_toint : _T_156 ? issue_slots_2_out_uop_fp_ctrl_toint : issue_slots_1_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_fromint = _T_157 ? issue_slots_3_out_uop_fp_ctrl_fromint : _T_156 ? issue_slots_2_out_uop_fp_ctrl_fromint : issue_slots_1_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_typeTagOut = _T_157 ? issue_slots_3_out_uop_fp_ctrl_typeTagOut : _T_156 ? issue_slots_2_out_uop_fp_ctrl_typeTagOut : issue_slots_1_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_typeTagIn = _T_157 ? issue_slots_3_out_uop_fp_ctrl_typeTagIn : _T_156 ? issue_slots_2_out_uop_fp_ctrl_typeTagIn : issue_slots_1_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_swap23 = _T_157 ? issue_slots_3_out_uop_fp_ctrl_swap23 : _T_156 ? issue_slots_2_out_uop_fp_ctrl_swap23 : issue_slots_1_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_swap12 = _T_157 ? issue_slots_3_out_uop_fp_ctrl_swap12 : _T_156 ? issue_slots_2_out_uop_fp_ctrl_swap12 : issue_slots_1_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_ren3 = _T_157 ? issue_slots_3_out_uop_fp_ctrl_ren3 : _T_156 ? issue_slots_2_out_uop_fp_ctrl_ren3 : issue_slots_1_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_ren2 = _T_157 ? issue_slots_3_out_uop_fp_ctrl_ren2 : _T_156 ? issue_slots_2_out_uop_fp_ctrl_ren2 : issue_slots_1_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_ren1 = _T_157 ? issue_slots_3_out_uop_fp_ctrl_ren1 : _T_156 ? issue_slots_2_out_uop_fp_ctrl_ren1 : issue_slots_1_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_wen = _T_157 ? issue_slots_3_out_uop_fp_ctrl_wen : _T_156 ? issue_slots_2_out_uop_fp_ctrl_wen : issue_slots_1_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_ldst = _T_157 ? issue_slots_3_out_uop_fp_ctrl_ldst : _T_156 ? issue_slots_2_out_uop_fp_ctrl_ldst : issue_slots_1_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_op2_sel = _T_157 ? issue_slots_3_out_uop_op2_sel : _T_156 ? issue_slots_2_out_uop_op2_sel : issue_slots_1_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_op1_sel = _T_157 ? issue_slots_3_out_uop_op1_sel : _T_156 ? issue_slots_2_out_uop_op1_sel : issue_slots_1_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_imm_packed = _T_157 ? issue_slots_3_out_uop_imm_packed : _T_156 ? issue_slots_2_out_uop_imm_packed : issue_slots_1_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_pimm = _T_157 ? issue_slots_3_out_uop_pimm : _T_156 ? issue_slots_2_out_uop_pimm : issue_slots_1_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_imm_sel = _T_157 ? issue_slots_3_out_uop_imm_sel : _T_156 ? issue_slots_2_out_uop_imm_sel : issue_slots_1_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_imm_rename = _T_157 ? issue_slots_3_out_uop_imm_rename : _T_156 ? issue_slots_2_out_uop_imm_rename : issue_slots_1_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_taken = _T_157 ? issue_slots_3_out_uop_taken : _T_156 ? issue_slots_2_out_uop_taken : issue_slots_1_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_pc_lob = _T_157 ? issue_slots_3_out_uop_pc_lob : _T_156 ? issue_slots_2_out_uop_pc_lob : issue_slots_1_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_edge_inst = _T_157 ? issue_slots_3_out_uop_edge_inst : _T_156 ? issue_slots_2_out_uop_edge_inst : issue_slots_1_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ftq_idx = _T_157 ? issue_slots_3_out_uop_ftq_idx : _T_156 ? issue_slots_2_out_uop_ftq_idx : issue_slots_1_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_mov = _T_157 ? issue_slots_3_out_uop_is_mov : _T_156 ? issue_slots_2_out_uop_is_mov : issue_slots_1_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_rocc = _T_157 ? issue_slots_3_out_uop_is_rocc : _T_156 ? issue_slots_2_out_uop_is_rocc : issue_slots_1_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_sys_pc2epc = _T_157 ? issue_slots_3_out_uop_is_sys_pc2epc : _T_156 ? issue_slots_2_out_uop_is_sys_pc2epc : issue_slots_1_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_eret = _T_157 ? issue_slots_3_out_uop_is_eret : _T_156 ? issue_slots_2_out_uop_is_eret : issue_slots_1_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_amo = _T_157 ? issue_slots_3_out_uop_is_amo : _T_156 ? issue_slots_2_out_uop_is_amo : issue_slots_1_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_sfence = _T_157 ? issue_slots_3_out_uop_is_sfence : _T_156 ? issue_slots_2_out_uop_is_sfence : issue_slots_1_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_fencei = _T_157 ? issue_slots_3_out_uop_is_fencei : _T_156 ? issue_slots_2_out_uop_is_fencei : issue_slots_1_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_fence = _T_157 ? issue_slots_3_out_uop_is_fence : _T_156 ? issue_slots_2_out_uop_is_fence : issue_slots_1_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_sfb = _T_157 ? issue_slots_3_out_uop_is_sfb : _T_156 ? issue_slots_2_out_uop_is_sfb : issue_slots_1_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_br_type = _T_157 ? issue_slots_3_out_uop_br_type : _T_156 ? issue_slots_2_out_uop_br_type : issue_slots_1_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_br_tag = _T_157 ? issue_slots_3_out_uop_br_tag : _T_156 ? issue_slots_2_out_uop_br_tag : issue_slots_1_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_br_mask = _T_157 ? issue_slots_3_out_uop_br_mask : _T_156 ? issue_slots_2_out_uop_br_mask : issue_slots_1_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_dis_col_sel = _T_157 ? issue_slots_3_out_uop_dis_col_sel : _T_156 ? issue_slots_2_out_uop_dis_col_sel : issue_slots_1_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_p3_bypass_hint = _T_157 ? issue_slots_3_out_uop_iw_p3_bypass_hint : _T_156 ? issue_slots_2_out_uop_iw_p3_bypass_hint : issue_slots_1_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_p2_bypass_hint = _T_157 ? issue_slots_3_out_uop_iw_p2_bypass_hint : _T_156 ? issue_slots_2_out_uop_iw_p2_bypass_hint : issue_slots_1_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_p1_bypass_hint = _T_157 ? issue_slots_3_out_uop_iw_p1_bypass_hint : _T_156 ? issue_slots_2_out_uop_iw_p1_bypass_hint : issue_slots_1_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_issued = _T_157 ? issue_slots_3_out_uop_iw_issued : _T_156 ? issue_slots_2_out_uop_iw_issued : issue_slots_1_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_0 = _T_157 ? issue_slots_3_out_uop_fu_code_0 : _T_156 ? issue_slots_2_out_uop_fu_code_0 : issue_slots_1_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_1 = _T_157 ? issue_slots_3_out_uop_fu_code_1 : _T_156 ? issue_slots_2_out_uop_fu_code_1 : issue_slots_1_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_2 = _T_157 ? issue_slots_3_out_uop_fu_code_2 : _T_156 ? issue_slots_2_out_uop_fu_code_2 : issue_slots_1_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_3 = _T_157 ? issue_slots_3_out_uop_fu_code_3 : _T_156 ? issue_slots_2_out_uop_fu_code_3 : issue_slots_1_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_4 = _T_157 ? issue_slots_3_out_uop_fu_code_4 : _T_156 ? issue_slots_2_out_uop_fu_code_4 : issue_slots_1_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_5 = _T_157 ? issue_slots_3_out_uop_fu_code_5 : _T_156 ? issue_slots_2_out_uop_fu_code_5 : issue_slots_1_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_6 = _T_157 ? issue_slots_3_out_uop_fu_code_6 : _T_156 ? issue_slots_2_out_uop_fu_code_6 : issue_slots_1_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_7 = _T_157 ? issue_slots_3_out_uop_fu_code_7 : _T_156 ? issue_slots_2_out_uop_fu_code_7 : issue_slots_1_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_8 = _T_157 ? issue_slots_3_out_uop_fu_code_8 : _T_156 ? issue_slots_2_out_uop_fu_code_8 : issue_slots_1_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_9 = _T_157 ? issue_slots_3_out_uop_fu_code_9 : _T_156 ? issue_slots_2_out_uop_fu_code_9 : issue_slots_1_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iq_type_0 = _T_157 ? issue_slots_3_out_uop_iq_type_0 : _T_156 ? issue_slots_2_out_uop_iq_type_0 : issue_slots_1_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iq_type_1 = _T_157 ? issue_slots_3_out_uop_iq_type_1 : _T_156 ? issue_slots_2_out_uop_iq_type_1 : issue_slots_1_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iq_type_2 = _T_157 ? issue_slots_3_out_uop_iq_type_2 : _T_156 ? issue_slots_2_out_uop_iq_type_2 : issue_slots_1_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iq_type_3 = _T_157 ? issue_slots_3_out_uop_iq_type_3 : _T_156 ? issue_slots_2_out_uop_iq_type_3 : issue_slots_1_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_debug_pc = _T_157 ? issue_slots_3_out_uop_debug_pc : _T_156 ? issue_slots_2_out_uop_debug_pc : issue_slots_1_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_rvc = _T_157 ? issue_slots_3_out_uop_is_rvc : _T_156 ? issue_slots_2_out_uop_is_rvc : issue_slots_1_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_debug_inst = _T_157 ? issue_slots_3_out_uop_debug_inst : _T_156 ? issue_slots_2_out_uop_debug_inst : issue_slots_1_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_inst = _T_157 ? issue_slots_3_out_uop_inst : _T_156 ? issue_slots_2_out_uop_inst : issue_slots_1_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] wire _T_159 = shamts_oh_3 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_160 = shamts_oh_4 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_1_in_uop_valid = _T_160 ? issue_slots_4_will_be_valid : _T_159 ? issue_slots_3_will_be_valid : shamts_oh_2 == 3'h1 & issue_slots_2_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_1_in_uop_bits_debug_tsrc = _T_160 ? issue_slots_4_out_uop_debug_tsrc : _T_159 ? issue_slots_3_out_uop_debug_tsrc : issue_slots_2_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_debug_fsrc = _T_160 ? issue_slots_4_out_uop_debug_fsrc : _T_159 ? issue_slots_3_out_uop_debug_fsrc : issue_slots_2_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_bp_xcpt_if = _T_160 ? issue_slots_4_out_uop_bp_xcpt_if : _T_159 ? issue_slots_3_out_uop_bp_xcpt_if : issue_slots_2_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_bp_debug_if = _T_160 ? issue_slots_4_out_uop_bp_debug_if : _T_159 ? issue_slots_3_out_uop_bp_debug_if : issue_slots_2_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_xcpt_ma_if = _T_160 ? issue_slots_4_out_uop_xcpt_ma_if : _T_159 ? issue_slots_3_out_uop_xcpt_ma_if : issue_slots_2_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_xcpt_ae_if = _T_160 ? issue_slots_4_out_uop_xcpt_ae_if : _T_159 ? issue_slots_3_out_uop_xcpt_ae_if : issue_slots_2_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_xcpt_pf_if = _T_160 ? issue_slots_4_out_uop_xcpt_pf_if : _T_159 ? issue_slots_3_out_uop_xcpt_pf_if : issue_slots_2_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_typ = _T_160 ? issue_slots_4_out_uop_fp_typ : _T_159 ? issue_slots_3_out_uop_fp_typ : issue_slots_2_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_rm = _T_160 ? issue_slots_4_out_uop_fp_rm : _T_159 ? issue_slots_3_out_uop_fp_rm : issue_slots_2_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_val = _T_160 ? issue_slots_4_out_uop_fp_val : _T_159 ? issue_slots_3_out_uop_fp_val : issue_slots_2_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fcn_op = _T_160 ? issue_slots_4_out_uop_fcn_op : _T_159 ? issue_slots_3_out_uop_fcn_op : issue_slots_2_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fcn_dw = _T_160 ? issue_slots_4_out_uop_fcn_dw : _T_159 ? issue_slots_3_out_uop_fcn_dw : issue_slots_2_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_frs3_en = _T_160 ? issue_slots_4_out_uop_frs3_en : _T_159 ? issue_slots_3_out_uop_frs3_en : issue_slots_2_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs2_rtype = _T_160 ? issue_slots_4_out_uop_lrs2_rtype : _T_159 ? issue_slots_3_out_uop_lrs2_rtype : issue_slots_2_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs1_rtype = _T_160 ? issue_slots_4_out_uop_lrs1_rtype : _T_159 ? issue_slots_3_out_uop_lrs1_rtype : issue_slots_2_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_dst_rtype = _T_160 ? issue_slots_4_out_uop_dst_rtype : _T_159 ? issue_slots_3_out_uop_dst_rtype : issue_slots_2_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs3 = _T_160 ? issue_slots_4_out_uop_lrs3 : _T_159 ? issue_slots_3_out_uop_lrs3 : issue_slots_2_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs2 = _T_160 ? issue_slots_4_out_uop_lrs2 : _T_159 ? issue_slots_3_out_uop_lrs2 : issue_slots_2_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs1 = _T_160 ? issue_slots_4_out_uop_lrs1 : _T_159 ? issue_slots_3_out_uop_lrs1 : issue_slots_2_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ldst = _T_160 ? issue_slots_4_out_uop_ldst : _T_159 ? issue_slots_3_out_uop_ldst : issue_slots_2_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ldst_is_rs1 = _T_160 ? issue_slots_4_out_uop_ldst_is_rs1 : _T_159 ? issue_slots_3_out_uop_ldst_is_rs1 : issue_slots_2_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_csr_cmd = _T_160 ? issue_slots_4_out_uop_csr_cmd : _T_159 ? issue_slots_3_out_uop_csr_cmd : issue_slots_2_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_flush_on_commit = _T_160 ? issue_slots_4_out_uop_flush_on_commit : _T_159 ? issue_slots_3_out_uop_flush_on_commit : issue_slots_2_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_unique = _T_160 ? issue_slots_4_out_uop_is_unique : _T_159 ? issue_slots_3_out_uop_is_unique : issue_slots_2_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_uses_stq = _T_160 ? issue_slots_4_out_uop_uses_stq : _T_159 ? issue_slots_3_out_uop_uses_stq : issue_slots_2_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_uses_ldq = _T_160 ? issue_slots_4_out_uop_uses_ldq : _T_159 ? issue_slots_3_out_uop_uses_ldq : issue_slots_2_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_mem_signed = _T_160 ? issue_slots_4_out_uop_mem_signed : _T_159 ? issue_slots_3_out_uop_mem_signed : issue_slots_2_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_mem_size = _T_160 ? issue_slots_4_out_uop_mem_size : _T_159 ? issue_slots_3_out_uop_mem_size : issue_slots_2_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_mem_cmd = _T_160 ? issue_slots_4_out_uop_mem_cmd : _T_159 ? issue_slots_3_out_uop_mem_cmd : issue_slots_2_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_exc_cause = _T_160 ? issue_slots_4_out_uop_exc_cause : _T_159 ? issue_slots_3_out_uop_exc_cause : issue_slots_2_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_exception = _T_160 ? issue_slots_4_out_uop_exception : _T_159 ? issue_slots_3_out_uop_exception : issue_slots_2_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_stale_pdst = _T_160 ? issue_slots_4_out_uop_stale_pdst : _T_159 ? issue_slots_3_out_uop_stale_pdst : issue_slots_2_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ppred_busy = _T_160 ? issue_slots_4_out_uop_ppred_busy : _T_159 ? issue_slots_3_out_uop_ppred_busy : issue_slots_2_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs3_busy = _T_160 ? issue_slots_4_out_uop_prs3_busy : _T_159 ? issue_slots_3_out_uop_prs3_busy : issue_slots_2_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs2_busy = _T_160 ? issue_slots_4_out_uop_prs2_busy : _T_159 ? issue_slots_3_out_uop_prs2_busy : issue_slots_2_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs1_busy = _T_160 ? issue_slots_4_out_uop_prs1_busy : _T_159 ? issue_slots_3_out_uop_prs1_busy : issue_slots_2_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ppred = _T_160 ? issue_slots_4_out_uop_ppred : _T_159 ? issue_slots_3_out_uop_ppred : issue_slots_2_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs3 = _T_160 ? issue_slots_4_out_uop_prs3 : _T_159 ? issue_slots_3_out_uop_prs3 : issue_slots_2_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs2 = _T_160 ? issue_slots_4_out_uop_prs2 : _T_159 ? issue_slots_3_out_uop_prs2 : issue_slots_2_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs1 = _T_160 ? issue_slots_4_out_uop_prs1 : _T_159 ? issue_slots_3_out_uop_prs1 : issue_slots_2_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_pdst = _T_160 ? issue_slots_4_out_uop_pdst : _T_159 ? issue_slots_3_out_uop_pdst : issue_slots_2_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_rxq_idx = _T_160 ? issue_slots_4_out_uop_rxq_idx : _T_159 ? issue_slots_3_out_uop_rxq_idx : issue_slots_2_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_stq_idx = _T_160 ? issue_slots_4_out_uop_stq_idx : _T_159 ? issue_slots_3_out_uop_stq_idx : issue_slots_2_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ldq_idx = _T_160 ? issue_slots_4_out_uop_ldq_idx : _T_159 ? issue_slots_3_out_uop_ldq_idx : issue_slots_2_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_rob_idx = _T_160 ? issue_slots_4_out_uop_rob_idx : _T_159 ? issue_slots_3_out_uop_rob_idx : issue_slots_2_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_vec = _T_160 ? issue_slots_4_out_uop_fp_ctrl_vec : _T_159 ? issue_slots_3_out_uop_fp_ctrl_vec : issue_slots_2_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_wflags = _T_160 ? issue_slots_4_out_uop_fp_ctrl_wflags : _T_159 ? issue_slots_3_out_uop_fp_ctrl_wflags : issue_slots_2_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_sqrt = _T_160 ? issue_slots_4_out_uop_fp_ctrl_sqrt : _T_159 ? issue_slots_3_out_uop_fp_ctrl_sqrt : issue_slots_2_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_div = _T_160 ? issue_slots_4_out_uop_fp_ctrl_div : _T_159 ? issue_slots_3_out_uop_fp_ctrl_div : issue_slots_2_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_fma = _T_160 ? issue_slots_4_out_uop_fp_ctrl_fma : _T_159 ? issue_slots_3_out_uop_fp_ctrl_fma : issue_slots_2_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_fastpipe = _T_160 ? issue_slots_4_out_uop_fp_ctrl_fastpipe : _T_159 ? issue_slots_3_out_uop_fp_ctrl_fastpipe : issue_slots_2_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_toint = _T_160 ? issue_slots_4_out_uop_fp_ctrl_toint : _T_159 ? issue_slots_3_out_uop_fp_ctrl_toint : issue_slots_2_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_fromint = _T_160 ? issue_slots_4_out_uop_fp_ctrl_fromint : _T_159 ? issue_slots_3_out_uop_fp_ctrl_fromint : issue_slots_2_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_typeTagOut = _T_160 ? issue_slots_4_out_uop_fp_ctrl_typeTagOut : _T_159 ? issue_slots_3_out_uop_fp_ctrl_typeTagOut : issue_slots_2_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_typeTagIn = _T_160 ? issue_slots_4_out_uop_fp_ctrl_typeTagIn : _T_159 ? issue_slots_3_out_uop_fp_ctrl_typeTagIn : issue_slots_2_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_swap23 = _T_160 ? issue_slots_4_out_uop_fp_ctrl_swap23 : _T_159 ? issue_slots_3_out_uop_fp_ctrl_swap23 : issue_slots_2_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_swap12 = _T_160 ? issue_slots_4_out_uop_fp_ctrl_swap12 : _T_159 ? issue_slots_3_out_uop_fp_ctrl_swap12 : issue_slots_2_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_ren3 = _T_160 ? issue_slots_4_out_uop_fp_ctrl_ren3 : _T_159 ? issue_slots_3_out_uop_fp_ctrl_ren3 : issue_slots_2_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_ren2 = _T_160 ? issue_slots_4_out_uop_fp_ctrl_ren2 : _T_159 ? issue_slots_3_out_uop_fp_ctrl_ren2 : issue_slots_2_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_ren1 = _T_160 ? issue_slots_4_out_uop_fp_ctrl_ren1 : _T_159 ? issue_slots_3_out_uop_fp_ctrl_ren1 : issue_slots_2_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_wen = _T_160 ? issue_slots_4_out_uop_fp_ctrl_wen : _T_159 ? issue_slots_3_out_uop_fp_ctrl_wen : issue_slots_2_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_ldst = _T_160 ? issue_slots_4_out_uop_fp_ctrl_ldst : _T_159 ? issue_slots_3_out_uop_fp_ctrl_ldst : issue_slots_2_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_op2_sel = _T_160 ? issue_slots_4_out_uop_op2_sel : _T_159 ? issue_slots_3_out_uop_op2_sel : issue_slots_2_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_op1_sel = _T_160 ? issue_slots_4_out_uop_op1_sel : _T_159 ? issue_slots_3_out_uop_op1_sel : issue_slots_2_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_imm_packed = _T_160 ? issue_slots_4_out_uop_imm_packed : _T_159 ? issue_slots_3_out_uop_imm_packed : issue_slots_2_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_pimm = _T_160 ? issue_slots_4_out_uop_pimm : _T_159 ? issue_slots_3_out_uop_pimm : issue_slots_2_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_imm_sel = _T_160 ? issue_slots_4_out_uop_imm_sel : _T_159 ? issue_slots_3_out_uop_imm_sel : issue_slots_2_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_imm_rename = _T_160 ? issue_slots_4_out_uop_imm_rename : _T_159 ? issue_slots_3_out_uop_imm_rename : issue_slots_2_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_taken = _T_160 ? issue_slots_4_out_uop_taken : _T_159 ? issue_slots_3_out_uop_taken : issue_slots_2_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_pc_lob = _T_160 ? issue_slots_4_out_uop_pc_lob : _T_159 ? issue_slots_3_out_uop_pc_lob : issue_slots_2_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_edge_inst = _T_160 ? issue_slots_4_out_uop_edge_inst : _T_159 ? issue_slots_3_out_uop_edge_inst : issue_slots_2_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ftq_idx = _T_160 ? issue_slots_4_out_uop_ftq_idx : _T_159 ? issue_slots_3_out_uop_ftq_idx : issue_slots_2_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_mov = _T_160 ? issue_slots_4_out_uop_is_mov : _T_159 ? issue_slots_3_out_uop_is_mov : issue_slots_2_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_rocc = _T_160 ? issue_slots_4_out_uop_is_rocc : _T_159 ? issue_slots_3_out_uop_is_rocc : issue_slots_2_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_sys_pc2epc = _T_160 ? issue_slots_4_out_uop_is_sys_pc2epc : _T_159 ? issue_slots_3_out_uop_is_sys_pc2epc : issue_slots_2_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_eret = _T_160 ? issue_slots_4_out_uop_is_eret : _T_159 ? issue_slots_3_out_uop_is_eret : issue_slots_2_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_amo = _T_160 ? issue_slots_4_out_uop_is_amo : _T_159 ? issue_slots_3_out_uop_is_amo : issue_slots_2_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_sfence = _T_160 ? issue_slots_4_out_uop_is_sfence : _T_159 ? issue_slots_3_out_uop_is_sfence : issue_slots_2_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_fencei = _T_160 ? issue_slots_4_out_uop_is_fencei : _T_159 ? issue_slots_3_out_uop_is_fencei : issue_slots_2_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_fence = _T_160 ? issue_slots_4_out_uop_is_fence : _T_159 ? issue_slots_3_out_uop_is_fence : issue_slots_2_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_sfb = _T_160 ? issue_slots_4_out_uop_is_sfb : _T_159 ? issue_slots_3_out_uop_is_sfb : issue_slots_2_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_br_type = _T_160 ? issue_slots_4_out_uop_br_type : _T_159 ? issue_slots_3_out_uop_br_type : issue_slots_2_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_br_tag = _T_160 ? issue_slots_4_out_uop_br_tag : _T_159 ? issue_slots_3_out_uop_br_tag : issue_slots_2_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_br_mask = _T_160 ? issue_slots_4_out_uop_br_mask : _T_159 ? issue_slots_3_out_uop_br_mask : issue_slots_2_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_dis_col_sel = _T_160 ? issue_slots_4_out_uop_dis_col_sel : _T_159 ? issue_slots_3_out_uop_dis_col_sel : issue_slots_2_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_p3_bypass_hint = _T_160 ? issue_slots_4_out_uop_iw_p3_bypass_hint : _T_159 ? issue_slots_3_out_uop_iw_p3_bypass_hint : issue_slots_2_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_p2_bypass_hint = _T_160 ? issue_slots_4_out_uop_iw_p2_bypass_hint : _T_159 ? issue_slots_3_out_uop_iw_p2_bypass_hint : issue_slots_2_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_p1_bypass_hint = _T_160 ? issue_slots_4_out_uop_iw_p1_bypass_hint : _T_159 ? issue_slots_3_out_uop_iw_p1_bypass_hint : issue_slots_2_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_issued = _T_160 ? issue_slots_4_out_uop_iw_issued : _T_159 ? issue_slots_3_out_uop_iw_issued : issue_slots_2_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_0 = _T_160 ? issue_slots_4_out_uop_fu_code_0 : _T_159 ? issue_slots_3_out_uop_fu_code_0 : issue_slots_2_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_1 = _T_160 ? issue_slots_4_out_uop_fu_code_1 : _T_159 ? issue_slots_3_out_uop_fu_code_1 : issue_slots_2_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_2 = _T_160 ? issue_slots_4_out_uop_fu_code_2 : _T_159 ? issue_slots_3_out_uop_fu_code_2 : issue_slots_2_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_3 = _T_160 ? issue_slots_4_out_uop_fu_code_3 : _T_159 ? issue_slots_3_out_uop_fu_code_3 : issue_slots_2_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_4 = _T_160 ? issue_slots_4_out_uop_fu_code_4 : _T_159 ? issue_slots_3_out_uop_fu_code_4 : issue_slots_2_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_5 = _T_160 ? issue_slots_4_out_uop_fu_code_5 : _T_159 ? issue_slots_3_out_uop_fu_code_5 : issue_slots_2_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_6 = _T_160 ? issue_slots_4_out_uop_fu_code_6 : _T_159 ? issue_slots_3_out_uop_fu_code_6 : issue_slots_2_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_7 = _T_160 ? issue_slots_4_out_uop_fu_code_7 : _T_159 ? issue_slots_3_out_uop_fu_code_7 : issue_slots_2_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_8 = _T_160 ? issue_slots_4_out_uop_fu_code_8 : _T_159 ? issue_slots_3_out_uop_fu_code_8 : issue_slots_2_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_9 = _T_160 ? issue_slots_4_out_uop_fu_code_9 : _T_159 ? issue_slots_3_out_uop_fu_code_9 : issue_slots_2_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iq_type_0 = _T_160 ? issue_slots_4_out_uop_iq_type_0 : _T_159 ? issue_slots_3_out_uop_iq_type_0 : issue_slots_2_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iq_type_1 = _T_160 ? issue_slots_4_out_uop_iq_type_1 : _T_159 ? issue_slots_3_out_uop_iq_type_1 : issue_slots_2_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iq_type_2 = _T_160 ? issue_slots_4_out_uop_iq_type_2 : _T_159 ? issue_slots_3_out_uop_iq_type_2 : issue_slots_2_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iq_type_3 = _T_160 ? issue_slots_4_out_uop_iq_type_3 : _T_159 ? issue_slots_3_out_uop_iq_type_3 : issue_slots_2_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_debug_pc = _T_160 ? issue_slots_4_out_uop_debug_pc : _T_159 ? issue_slots_3_out_uop_debug_pc : issue_slots_2_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_rvc = _T_160 ? issue_slots_4_out_uop_is_rvc : _T_159 ? issue_slots_3_out_uop_is_rvc : issue_slots_2_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_debug_inst = _T_160 ? issue_slots_4_out_uop_debug_inst : _T_159 ? issue_slots_3_out_uop_debug_inst : issue_slots_2_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_inst = _T_160 ? issue_slots_4_out_uop_inst : _T_159 ? issue_slots_3_out_uop_inst : issue_slots_2_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_1_clear_T = \|shamts_oh_1; // @[issue-unit-age-ordered.scala:158:23, :199:49] assign issue_slots_1_clear = _issue_slots_1_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_162 = shamts_oh_4 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_163 = shamts_oh_5 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_2_in_uop_valid = _T_163 ? issue_slots_5_will_be_valid : _T_162 ? issue_slots_4_will_be_valid : shamts_oh_3 == 3'h1 & issue_slots_3_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_2_in_uop_bits_debug_tsrc = _T_163 ? issue_slots_5_out_uop_debug_tsrc : _T_162 ? issue_slots_4_out_uop_debug_tsrc : issue_slots_3_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_debug_fsrc = _T_163 ? issue_slots_5_out_uop_debug_fsrc : _T_162 ? issue_slots_4_out_uop_debug_fsrc : issue_slots_3_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_bp_xcpt_if = _T_163 ? issue_slots_5_out_uop_bp_xcpt_if : _T_162 ? issue_slots_4_out_uop_bp_xcpt_if : issue_slots_3_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_bp_debug_if = _T_163 ? issue_slots_5_out_uop_bp_debug_if : _T_162 ? issue_slots_4_out_uop_bp_debug_if : issue_slots_3_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_xcpt_ma_if = _T_163 ? issue_slots_5_out_uop_xcpt_ma_if : _T_162 ? issue_slots_4_out_uop_xcpt_ma_if : issue_slots_3_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_xcpt_ae_if = _T_163 ? issue_slots_5_out_uop_xcpt_ae_if : _T_162 ? issue_slots_4_out_uop_xcpt_ae_if : issue_slots_3_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_xcpt_pf_if = _T_163 ? issue_slots_5_out_uop_xcpt_pf_if : _T_162 ? issue_slots_4_out_uop_xcpt_pf_if : issue_slots_3_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_typ = _T_163 ? issue_slots_5_out_uop_fp_typ : _T_162 ? issue_slots_4_out_uop_fp_typ : issue_slots_3_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_rm = _T_163 ? issue_slots_5_out_uop_fp_rm : _T_162 ? issue_slots_4_out_uop_fp_rm : issue_slots_3_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_val = _T_163 ? issue_slots_5_out_uop_fp_val : _T_162 ? issue_slots_4_out_uop_fp_val : issue_slots_3_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fcn_op = _T_163 ? issue_slots_5_out_uop_fcn_op : _T_162 ? issue_slots_4_out_uop_fcn_op : issue_slots_3_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fcn_dw = _T_163 ? issue_slots_5_out_uop_fcn_dw : _T_162 ? issue_slots_4_out_uop_fcn_dw : issue_slots_3_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_frs3_en = _T_163 ? issue_slots_5_out_uop_frs3_en : _T_162 ? issue_slots_4_out_uop_frs3_en : issue_slots_3_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs2_rtype = _T_163 ? issue_slots_5_out_uop_lrs2_rtype : _T_162 ? issue_slots_4_out_uop_lrs2_rtype : issue_slots_3_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs1_rtype = _T_163 ? issue_slots_5_out_uop_lrs1_rtype : _T_162 ? issue_slots_4_out_uop_lrs1_rtype : issue_slots_3_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_dst_rtype = _T_163 ? issue_slots_5_out_uop_dst_rtype : _T_162 ? issue_slots_4_out_uop_dst_rtype : issue_slots_3_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs3 = _T_163 ? issue_slots_5_out_uop_lrs3 : _T_162 ? issue_slots_4_out_uop_lrs3 : issue_slots_3_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs2 = _T_163 ? issue_slots_5_out_uop_lrs2 : _T_162 ? issue_slots_4_out_uop_lrs2 : issue_slots_3_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs1 = _T_163 ? issue_slots_5_out_uop_lrs1 : _T_162 ? issue_slots_4_out_uop_lrs1 : issue_slots_3_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ldst = _T_163 ? issue_slots_5_out_uop_ldst : _T_162 ? issue_slots_4_out_uop_ldst : issue_slots_3_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ldst_is_rs1 = _T_163 ? issue_slots_5_out_uop_ldst_is_rs1 : _T_162 ? issue_slots_4_out_uop_ldst_is_rs1 : issue_slots_3_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_csr_cmd = _T_163 ? issue_slots_5_out_uop_csr_cmd : _T_162 ? issue_slots_4_out_uop_csr_cmd : issue_slots_3_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_flush_on_commit = _T_163 ? issue_slots_5_out_uop_flush_on_commit : _T_162 ? issue_slots_4_out_uop_flush_on_commit : issue_slots_3_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_unique = _T_163 ? issue_slots_5_out_uop_is_unique : _T_162 ? issue_slots_4_out_uop_is_unique : issue_slots_3_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_uses_stq = _T_163 ? issue_slots_5_out_uop_uses_stq : _T_162 ? issue_slots_4_out_uop_uses_stq : issue_slots_3_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_uses_ldq = _T_163 ? issue_slots_5_out_uop_uses_ldq : _T_162 ? issue_slots_4_out_uop_uses_ldq : issue_slots_3_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_mem_signed = _T_163 ? issue_slots_5_out_uop_mem_signed : _T_162 ? issue_slots_4_out_uop_mem_signed : issue_slots_3_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_mem_size = _T_163 ? issue_slots_5_out_uop_mem_size : _T_162 ? issue_slots_4_out_uop_mem_size : issue_slots_3_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_mem_cmd = _T_163 ? issue_slots_5_out_uop_mem_cmd : _T_162 ? issue_slots_4_out_uop_mem_cmd : issue_slots_3_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_exc_cause = _T_163 ? issue_slots_5_out_uop_exc_cause : _T_162 ? issue_slots_4_out_uop_exc_cause : issue_slots_3_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_exception = _T_163 ? issue_slots_5_out_uop_exception : _T_162 ? issue_slots_4_out_uop_exception : issue_slots_3_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_stale_pdst = _T_163 ? issue_slots_5_out_uop_stale_pdst : _T_162 ? issue_slots_4_out_uop_stale_pdst : issue_slots_3_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ppred_busy = _T_163 ? issue_slots_5_out_uop_ppred_busy : _T_162 ? issue_slots_4_out_uop_ppred_busy : issue_slots_3_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs3_busy = _T_163 ? issue_slots_5_out_uop_prs3_busy : _T_162 ? issue_slots_4_out_uop_prs3_busy : issue_slots_3_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs2_busy = _T_163 ? issue_slots_5_out_uop_prs2_busy : _T_162 ? issue_slots_4_out_uop_prs2_busy : issue_slots_3_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs1_busy = _T_163 ? issue_slots_5_out_uop_prs1_busy : _T_162 ? issue_slots_4_out_uop_prs1_busy : issue_slots_3_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ppred = _T_163 ? issue_slots_5_out_uop_ppred : _T_162 ? issue_slots_4_out_uop_ppred : issue_slots_3_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs3 = _T_163 ? issue_slots_5_out_uop_prs3 : _T_162 ? issue_slots_4_out_uop_prs3 : issue_slots_3_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs2 = _T_163 ? issue_slots_5_out_uop_prs2 : _T_162 ? issue_slots_4_out_uop_prs2 : issue_slots_3_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs1 = _T_163 ? issue_slots_5_out_uop_prs1 : _T_162 ? issue_slots_4_out_uop_prs1 : issue_slots_3_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_pdst = _T_163 ? issue_slots_5_out_uop_pdst : _T_162 ? issue_slots_4_out_uop_pdst : issue_slots_3_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_rxq_idx = _T_163 ? issue_slots_5_out_uop_rxq_idx : _T_162 ? issue_slots_4_out_uop_rxq_idx : issue_slots_3_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_stq_idx = _T_163 ? issue_slots_5_out_uop_stq_idx : _T_162 ? issue_slots_4_out_uop_stq_idx : issue_slots_3_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ldq_idx = _T_163 ? issue_slots_5_out_uop_ldq_idx : _T_162 ? issue_slots_4_out_uop_ldq_idx : issue_slots_3_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_rob_idx = _T_163 ? issue_slots_5_out_uop_rob_idx : _T_162 ? issue_slots_4_out_uop_rob_idx : issue_slots_3_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_vec = _T_163 ? issue_slots_5_out_uop_fp_ctrl_vec : _T_162 ? issue_slots_4_out_uop_fp_ctrl_vec : issue_slots_3_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_wflags = _T_163 ? issue_slots_5_out_uop_fp_ctrl_wflags : _T_162 ? issue_slots_4_out_uop_fp_ctrl_wflags : issue_slots_3_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_sqrt = _T_163 ? issue_slots_5_out_uop_fp_ctrl_sqrt : _T_162 ? issue_slots_4_out_uop_fp_ctrl_sqrt : issue_slots_3_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_div = _T_163 ? issue_slots_5_out_uop_fp_ctrl_div : _T_162 ? issue_slots_4_out_uop_fp_ctrl_div : issue_slots_3_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_fma = _T_163 ? issue_slots_5_out_uop_fp_ctrl_fma : _T_162 ? issue_slots_4_out_uop_fp_ctrl_fma : issue_slots_3_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_fastpipe = _T_163 ? issue_slots_5_out_uop_fp_ctrl_fastpipe : _T_162 ? issue_slots_4_out_uop_fp_ctrl_fastpipe : issue_slots_3_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_toint = _T_163 ? issue_slots_5_out_uop_fp_ctrl_toint : _T_162 ? issue_slots_4_out_uop_fp_ctrl_toint : issue_slots_3_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_fromint = _T_163 ? issue_slots_5_out_uop_fp_ctrl_fromint : _T_162 ? issue_slots_4_out_uop_fp_ctrl_fromint : issue_slots_3_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_typeTagOut = _T_163 ? issue_slots_5_out_uop_fp_ctrl_typeTagOut : _T_162 ? issue_slots_4_out_uop_fp_ctrl_typeTagOut : issue_slots_3_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_typeTagIn = _T_163 ? issue_slots_5_out_uop_fp_ctrl_typeTagIn : _T_162 ? issue_slots_4_out_uop_fp_ctrl_typeTagIn : issue_slots_3_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_swap23 = _T_163 ? issue_slots_5_out_uop_fp_ctrl_swap23 : _T_162 ? issue_slots_4_out_uop_fp_ctrl_swap23 : issue_slots_3_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_swap12 = _T_163 ? issue_slots_5_out_uop_fp_ctrl_swap12 : _T_162 ? issue_slots_4_out_uop_fp_ctrl_swap12 : issue_slots_3_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_ren3 = _T_163 ? issue_slots_5_out_uop_fp_ctrl_ren3 : _T_162 ? issue_slots_4_out_uop_fp_ctrl_ren3 : issue_slots_3_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_ren2 = _T_163 ? issue_slots_5_out_uop_fp_ctrl_ren2 : _T_162 ? issue_slots_4_out_uop_fp_ctrl_ren2 : issue_slots_3_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_ren1 = _T_163 ? issue_slots_5_out_uop_fp_ctrl_ren1 : _T_162 ? issue_slots_4_out_uop_fp_ctrl_ren1 : issue_slots_3_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_wen = _T_163 ? issue_slots_5_out_uop_fp_ctrl_wen : _T_162 ? issue_slots_4_out_uop_fp_ctrl_wen : issue_slots_3_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_ldst = _T_163 ? issue_slots_5_out_uop_fp_ctrl_ldst : _T_162 ? issue_slots_4_out_uop_fp_ctrl_ldst : issue_slots_3_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_op2_sel = _T_163 ? issue_slots_5_out_uop_op2_sel : _T_162 ? issue_slots_4_out_uop_op2_sel : issue_slots_3_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_op1_sel = _T_163 ? issue_slots_5_out_uop_op1_sel : _T_162 ? issue_slots_4_out_uop_op1_sel : issue_slots_3_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_imm_packed = _T_163 ? issue_slots_5_out_uop_imm_packed : _T_162 ? issue_slots_4_out_uop_imm_packed : issue_slots_3_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_pimm = _T_163 ? issue_slots_5_out_uop_pimm : _T_162 ? issue_slots_4_out_uop_pimm : issue_slots_3_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_imm_sel = _T_163 ? issue_slots_5_out_uop_imm_sel : _T_162 ? issue_slots_4_out_uop_imm_sel : issue_slots_3_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_imm_rename = _T_163 ? issue_slots_5_out_uop_imm_rename : _T_162 ? issue_slots_4_out_uop_imm_rename : issue_slots_3_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_taken = _T_163 ? issue_slots_5_out_uop_taken : _T_162 ? issue_slots_4_out_uop_taken : issue_slots_3_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_pc_lob = _T_163 ? issue_slots_5_out_uop_pc_lob : _T_162 ? issue_slots_4_out_uop_pc_lob : issue_slots_3_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_edge_inst = _T_163 ? issue_slots_5_out_uop_edge_inst : _T_162 ? issue_slots_4_out_uop_edge_inst : issue_slots_3_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ftq_idx = _T_163 ? issue_slots_5_out_uop_ftq_idx : _T_162 ? issue_slots_4_out_uop_ftq_idx : issue_slots_3_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_mov = _T_163 ? issue_slots_5_out_uop_is_mov : _T_162 ? issue_slots_4_out_uop_is_mov : issue_slots_3_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_rocc = _T_163 ? issue_slots_5_out_uop_is_rocc : _T_162 ? issue_slots_4_out_uop_is_rocc : issue_slots_3_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_sys_pc2epc = _T_163 ? issue_slots_5_out_uop_is_sys_pc2epc : _T_162 ? issue_slots_4_out_uop_is_sys_pc2epc : issue_slots_3_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_eret = _T_163 ? issue_slots_5_out_uop_is_eret : _T_162 ? issue_slots_4_out_uop_is_eret : issue_slots_3_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_amo = _T_163 ? issue_slots_5_out_uop_is_amo : _T_162 ? issue_slots_4_out_uop_is_amo : issue_slots_3_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_sfence = _T_163 ? issue_slots_5_out_uop_is_sfence : _T_162 ? issue_slots_4_out_uop_is_sfence : issue_slots_3_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_fencei = _T_163 ? issue_slots_5_out_uop_is_fencei : _T_162 ? issue_slots_4_out_uop_is_fencei : issue_slots_3_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_fence = _T_163 ? issue_slots_5_out_uop_is_fence : _T_162 ? issue_slots_4_out_uop_is_fence : issue_slots_3_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_sfb = _T_163 ? issue_slots_5_out_uop_is_sfb : _T_162 ? issue_slots_4_out_uop_is_sfb : issue_slots_3_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_br_type = _T_163 ? issue_slots_5_out_uop_br_type : _T_162 ? issue_slots_4_out_uop_br_type : issue_slots_3_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_br_tag = _T_163 ? issue_slots_5_out_uop_br_tag : _T_162 ? issue_slots_4_out_uop_br_tag : issue_slots_3_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_br_mask = _T_163 ? issue_slots_5_out_uop_br_mask : _T_162 ? issue_slots_4_out_uop_br_mask : issue_slots_3_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_dis_col_sel = _T_163 ? issue_slots_5_out_uop_dis_col_sel : _T_162 ? issue_slots_4_out_uop_dis_col_sel : issue_slots_3_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_p3_bypass_hint = _T_163 ? issue_slots_5_out_uop_iw_p3_bypass_hint : _T_162 ? issue_slots_4_out_uop_iw_p3_bypass_hint : issue_slots_3_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_p2_bypass_hint = _T_163 ? issue_slots_5_out_uop_iw_p2_bypass_hint : _T_162 ? issue_slots_4_out_uop_iw_p2_bypass_hint : issue_slots_3_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_p1_bypass_hint = _T_163 ? issue_slots_5_out_uop_iw_p1_bypass_hint : _T_162 ? issue_slots_4_out_uop_iw_p1_bypass_hint : issue_slots_3_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_issued = _T_163 ? issue_slots_5_out_uop_iw_issued : _T_162 ? issue_slots_4_out_uop_iw_issued : issue_slots_3_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_0 = _T_163 ? issue_slots_5_out_uop_fu_code_0 : _T_162 ? issue_slots_4_out_uop_fu_code_0 : issue_slots_3_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_1 = _T_163 ? issue_slots_5_out_uop_fu_code_1 : _T_162 ? issue_slots_4_out_uop_fu_code_1 : issue_slots_3_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_2 = _T_163 ? issue_slots_5_out_uop_fu_code_2 : _T_162 ? issue_slots_4_out_uop_fu_code_2 : issue_slots_3_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_3 = _T_163 ? issue_slots_5_out_uop_fu_code_3 : _T_162 ? issue_slots_4_out_uop_fu_code_3 : issue_slots_3_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_4 = _T_163 ? issue_slots_5_out_uop_fu_code_4 : _T_162 ? issue_slots_4_out_uop_fu_code_4 : issue_slots_3_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_5 = _T_163 ? issue_slots_5_out_uop_fu_code_5 : _T_162 ? issue_slots_4_out_uop_fu_code_5 : issue_slots_3_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_6 = _T_163 ? issue_slots_5_out_uop_fu_code_6 : _T_162 ? issue_slots_4_out_uop_fu_code_6 : issue_slots_3_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_7 = _T_163 ? issue_slots_5_out_uop_fu_code_7 : _T_162 ? issue_slots_4_out_uop_fu_code_7 : issue_slots_3_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_8 = _T_163 ? issue_slots_5_out_uop_fu_code_8 : _T_162 ? issue_slots_4_out_uop_fu_code_8 : issue_slots_3_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_9 = _T_163 ? issue_slots_5_out_uop_fu_code_9 : _T_162 ? issue_slots_4_out_uop_fu_code_9 : issue_slots_3_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iq_type_0 = _T_163 ? issue_slots_5_out_uop_iq_type_0 : _T_162 ? issue_slots_4_out_uop_iq_type_0 : issue_slots_3_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iq_type_1 = _T_163 ? issue_slots_5_out_uop_iq_type_1 : _T_162 ? issue_slots_4_out_uop_iq_type_1 : issue_slots_3_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iq_type_2 = _T_163 ? issue_slots_5_out_uop_iq_type_2 : _T_162 ? issue_slots_4_out_uop_iq_type_2 : issue_slots_3_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iq_type_3 = _T_163 ? issue_slots_5_out_uop_iq_type_3 : _T_162 ? issue_slots_4_out_uop_iq_type_3 : issue_slots_3_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_debug_pc = _T_163 ? issue_slots_5_out_uop_debug_pc : _T_162 ? issue_slots_4_out_uop_debug_pc : issue_slots_3_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_rvc = _T_163 ? issue_slots_5_out_uop_is_rvc : _T_162 ? issue_slots_4_out_uop_is_rvc : issue_slots_3_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_debug_inst = _T_163 ? issue_slots_5_out_uop_debug_inst : _T_162 ? issue_slots_4_out_uop_debug_inst : issue_slots_3_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_inst = _T_163 ? issue_slots_5_out_uop_inst : _T_162 ? issue_slots_4_out_uop_inst : issue_slots_3_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_2_clear_T = \|shamts_oh_2; // @[issue-unit-age-ordered.scala:158:23, :199:49] assign issue_slots_2_clear = _issue_slots_2_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_165 = shamts_oh_5 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_166 = shamts_oh_6 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_3_in_uop_valid = _T_166 ? issue_slots_6_will_be_valid : _T_165 ? issue_slots_5_will_be_valid : shamts_oh_4 == 3'h1 & issue_slots_4_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_3_in_uop_bits_debug_tsrc = _T_166 ? issue_slots_6_out_uop_debug_tsrc : _T_165 ? issue_slots_5_out_uop_debug_tsrc : issue_slots_4_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_debug_fsrc = _T_166 ? issue_slots_6_out_uop_debug_fsrc : _T_165 ? issue_slots_5_out_uop_debug_fsrc : issue_slots_4_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_bp_xcpt_if = _T_166 ? issue_slots_6_out_uop_bp_xcpt_if : _T_165 ? issue_slots_5_out_uop_bp_xcpt_if : issue_slots_4_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_bp_debug_if = _T_166 ? issue_slots_6_out_uop_bp_debug_if : _T_165 ? issue_slots_5_out_uop_bp_debug_if : issue_slots_4_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_xcpt_ma_if = _T_166 ? issue_slots_6_out_uop_xcpt_ma_if : _T_165 ? issue_slots_5_out_uop_xcpt_ma_if : issue_slots_4_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_xcpt_ae_if = _T_166 ? issue_slots_6_out_uop_xcpt_ae_if : _T_165 ? issue_slots_5_out_uop_xcpt_ae_if : issue_slots_4_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_xcpt_pf_if = _T_166 ? issue_slots_6_out_uop_xcpt_pf_if : _T_165 ? issue_slots_5_out_uop_xcpt_pf_if : issue_slots_4_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_typ = _T_166 ? issue_slots_6_out_uop_fp_typ : _T_165 ? issue_slots_5_out_uop_fp_typ : issue_slots_4_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_rm = _T_166 ? issue_slots_6_out_uop_fp_rm : _T_165 ? issue_slots_5_out_uop_fp_rm : issue_slots_4_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_val = _T_166 ? issue_slots_6_out_uop_fp_val : _T_165 ? issue_slots_5_out_uop_fp_val : issue_slots_4_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fcn_op = _T_166 ? issue_slots_6_out_uop_fcn_op : _T_165 ? issue_slots_5_out_uop_fcn_op : issue_slots_4_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fcn_dw = _T_166 ? issue_slots_6_out_uop_fcn_dw : _T_165 ? issue_slots_5_out_uop_fcn_dw : issue_slots_4_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_frs3_en = _T_166 ? issue_slots_6_out_uop_frs3_en : _T_165 ? issue_slots_5_out_uop_frs3_en : issue_slots_4_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs2_rtype = _T_166 ? issue_slots_6_out_uop_lrs2_rtype : _T_165 ? issue_slots_5_out_uop_lrs2_rtype : issue_slots_4_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs1_rtype = _T_166 ? issue_slots_6_out_uop_lrs1_rtype : _T_165 ? issue_slots_5_out_uop_lrs1_rtype : issue_slots_4_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_dst_rtype = _T_166 ? issue_slots_6_out_uop_dst_rtype : _T_165 ? issue_slots_5_out_uop_dst_rtype : issue_slots_4_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs3 = _T_166 ? issue_slots_6_out_uop_lrs3 : _T_165 ? issue_slots_5_out_uop_lrs3 : issue_slots_4_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs2 = _T_166 ? issue_slots_6_out_uop_lrs2 : _T_165 ? issue_slots_5_out_uop_lrs2 : issue_slots_4_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs1 = _T_166 ? issue_slots_6_out_uop_lrs1 : _T_165 ? issue_slots_5_out_uop_lrs1 : issue_slots_4_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ldst = _T_166 ? issue_slots_6_out_uop_ldst : _T_165 ? issue_slots_5_out_uop_ldst : issue_slots_4_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ldst_is_rs1 = _T_166 ? issue_slots_6_out_uop_ldst_is_rs1 : _T_165 ? issue_slots_5_out_uop_ldst_is_rs1 : issue_slots_4_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_csr_cmd = _T_166 ? issue_slots_6_out_uop_csr_cmd : _T_165 ? issue_slots_5_out_uop_csr_cmd : issue_slots_4_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_flush_on_commit = _T_166 ? issue_slots_6_out_uop_flush_on_commit : _T_165 ? issue_slots_5_out_uop_flush_on_commit : issue_slots_4_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_unique = _T_166 ? issue_slots_6_out_uop_is_unique : _T_165 ? issue_slots_5_out_uop_is_unique : issue_slots_4_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_uses_stq = _T_166 ? issue_slots_6_out_uop_uses_stq : _T_165 ? issue_slots_5_out_uop_uses_stq : issue_slots_4_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_uses_ldq = _T_166 ? issue_slots_6_out_uop_uses_ldq : _T_165 ? issue_slots_5_out_uop_uses_ldq : issue_slots_4_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_mem_signed = _T_166 ? issue_slots_6_out_uop_mem_signed : _T_165 ? issue_slots_5_out_uop_mem_signed : issue_slots_4_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_mem_size = _T_166 ? issue_slots_6_out_uop_mem_size : _T_165 ? issue_slots_5_out_uop_mem_size : issue_slots_4_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_mem_cmd = _T_166 ? issue_slots_6_out_uop_mem_cmd : _T_165 ? issue_slots_5_out_uop_mem_cmd : issue_slots_4_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_exc_cause = _T_166 ? issue_slots_6_out_uop_exc_cause : _T_165 ? issue_slots_5_out_uop_exc_cause : issue_slots_4_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_exception = _T_166 ? issue_slots_6_out_uop_exception : _T_165 ? issue_slots_5_out_uop_exception : issue_slots_4_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_stale_pdst = _T_166 ? issue_slots_6_out_uop_stale_pdst : _T_165 ? issue_slots_5_out_uop_stale_pdst : issue_slots_4_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ppred_busy = _T_166 ? issue_slots_6_out_uop_ppred_busy : _T_165 ? issue_slots_5_out_uop_ppred_busy : issue_slots_4_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs3_busy = _T_166 ? issue_slots_6_out_uop_prs3_busy : _T_165 ? issue_slots_5_out_uop_prs3_busy : issue_slots_4_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs2_busy = _T_166 ? issue_slots_6_out_uop_prs2_busy : _T_165 ? issue_slots_5_out_uop_prs2_busy : issue_slots_4_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs1_busy = _T_166 ? issue_slots_6_out_uop_prs1_busy : _T_165 ? issue_slots_5_out_uop_prs1_busy : issue_slots_4_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ppred = _T_166 ? issue_slots_6_out_uop_ppred : _T_165 ? issue_slots_5_out_uop_ppred : issue_slots_4_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs3 = _T_166 ? issue_slots_6_out_uop_prs3 : _T_165 ? issue_slots_5_out_uop_prs3 : issue_slots_4_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs2 = _T_166 ? issue_slots_6_out_uop_prs2 : _T_165 ? issue_slots_5_out_uop_prs2 : issue_slots_4_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs1 = _T_166 ? issue_slots_6_out_uop_prs1 : _T_165 ? issue_slots_5_out_uop_prs1 : issue_slots_4_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_pdst = _T_166 ? issue_slots_6_out_uop_pdst : _T_165 ? issue_slots_5_out_uop_pdst : issue_slots_4_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_rxq_idx = _T_166 ? issue_slots_6_out_uop_rxq_idx : _T_165 ? issue_slots_5_out_uop_rxq_idx : issue_slots_4_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_stq_idx = _T_166 ? issue_slots_6_out_uop_stq_idx : _T_165 ? issue_slots_5_out_uop_stq_idx : issue_slots_4_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ldq_idx = _T_166 ? issue_slots_6_out_uop_ldq_idx : _T_165 ? issue_slots_5_out_uop_ldq_idx : issue_slots_4_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_rob_idx = _T_166 ? issue_slots_6_out_uop_rob_idx : _T_165 ? issue_slots_5_out_uop_rob_idx : issue_slots_4_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_vec = _T_166 ? issue_slots_6_out_uop_fp_ctrl_vec : _T_165 ? issue_slots_5_out_uop_fp_ctrl_vec : issue_slots_4_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_wflags = _T_166 ? issue_slots_6_out_uop_fp_ctrl_wflags : _T_165 ? issue_slots_5_out_uop_fp_ctrl_wflags : issue_slots_4_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_sqrt = _T_166 ? issue_slots_6_out_uop_fp_ctrl_sqrt : _T_165 ? issue_slots_5_out_uop_fp_ctrl_sqrt : issue_slots_4_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_div = _T_166 ? issue_slots_6_out_uop_fp_ctrl_div : _T_165 ? issue_slots_5_out_uop_fp_ctrl_div : issue_slots_4_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_fma = _T_166 ? issue_slots_6_out_uop_fp_ctrl_fma : _T_165 ? issue_slots_5_out_uop_fp_ctrl_fma : issue_slots_4_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_fastpipe = _T_166 ? issue_slots_6_out_uop_fp_ctrl_fastpipe : _T_165 ? issue_slots_5_out_uop_fp_ctrl_fastpipe : issue_slots_4_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_toint = _T_166 ? issue_slots_6_out_uop_fp_ctrl_toint : _T_165 ? issue_slots_5_out_uop_fp_ctrl_toint : issue_slots_4_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_fromint = _T_166 ? issue_slots_6_out_uop_fp_ctrl_fromint : _T_165 ? issue_slots_5_out_uop_fp_ctrl_fromint : issue_slots_4_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_typeTagOut = _T_166 ? issue_slots_6_out_uop_fp_ctrl_typeTagOut : _T_165 ? issue_slots_5_out_uop_fp_ctrl_typeTagOut : issue_slots_4_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_typeTagIn = _T_166 ? issue_slots_6_out_uop_fp_ctrl_typeTagIn : _T_165 ? issue_slots_5_out_uop_fp_ctrl_typeTagIn : issue_slots_4_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_swap23 = _T_166 ? issue_slots_6_out_uop_fp_ctrl_swap23 : _T_165 ? issue_slots_5_out_uop_fp_ctrl_swap23 : issue_slots_4_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_swap12 = _T_166 ? issue_slots_6_out_uop_fp_ctrl_swap12 : _T_165 ? issue_slots_5_out_uop_fp_ctrl_swap12 : issue_slots_4_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_ren3 = _T_166 ? issue_slots_6_out_uop_fp_ctrl_ren3 : _T_165 ? issue_slots_5_out_uop_fp_ctrl_ren3 : issue_slots_4_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_ren2 = _T_166 ? issue_slots_6_out_uop_fp_ctrl_ren2 : _T_165 ? issue_slots_5_out_uop_fp_ctrl_ren2 : issue_slots_4_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_ren1 = _T_166 ? issue_slots_6_out_uop_fp_ctrl_ren1 : _T_165 ? issue_slots_5_out_uop_fp_ctrl_ren1 : issue_slots_4_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_wen = _T_166 ? issue_slots_6_out_uop_fp_ctrl_wen : _T_165 ? issue_slots_5_out_uop_fp_ctrl_wen : issue_slots_4_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_ldst = _T_166 ? issue_slots_6_out_uop_fp_ctrl_ldst : _T_165 ? issue_slots_5_out_uop_fp_ctrl_ldst : issue_slots_4_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_op2_sel = _T_166 ? issue_slots_6_out_uop_op2_sel : _T_165 ? issue_slots_5_out_uop_op2_sel : issue_slots_4_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_op1_sel = _T_166 ? issue_slots_6_out_uop_op1_sel : _T_165 ? issue_slots_5_out_uop_op1_sel : issue_slots_4_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_imm_packed = _T_166 ? issue_slots_6_out_uop_imm_packed : _T_165 ? issue_slots_5_out_uop_imm_packed : issue_slots_4_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_pimm = _T_166 ? issue_slots_6_out_uop_pimm : _T_165 ? issue_slots_5_out_uop_pimm : issue_slots_4_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_imm_sel = _T_166 ? issue_slots_6_out_uop_imm_sel : _T_165 ? issue_slots_5_out_uop_imm_sel : issue_slots_4_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_imm_rename = _T_166 ? issue_slots_6_out_uop_imm_rename : _T_165 ? issue_slots_5_out_uop_imm_rename : issue_slots_4_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_taken = _T_166 ? issue_slots_6_out_uop_taken : _T_165 ? issue_slots_5_out_uop_taken : issue_slots_4_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_pc_lob = _T_166 ? issue_slots_6_out_uop_pc_lob : _T_165 ? issue_slots_5_out_uop_pc_lob : issue_slots_4_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_edge_inst = _T_166 ? issue_slots_6_out_uop_edge_inst : _T_165 ? issue_slots_5_out_uop_edge_inst : issue_slots_4_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ftq_idx = _T_166 ? issue_slots_6_out_uop_ftq_idx : _T_165 ? issue_slots_5_out_uop_ftq_idx : issue_slots_4_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_mov = _T_166 ? issue_slots_6_out_uop_is_mov : _T_165 ? issue_slots_5_out_uop_is_mov : issue_slots_4_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_rocc = _T_166 ? issue_slots_6_out_uop_is_rocc : _T_165 ? issue_slots_5_out_uop_is_rocc : issue_slots_4_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_sys_pc2epc = _T_166 ? issue_slots_6_out_uop_is_sys_pc2epc : _T_165 ? issue_slots_5_out_uop_is_sys_pc2epc : issue_slots_4_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_eret = _T_166 ? issue_slots_6_out_uop_is_eret : _T_165 ? issue_slots_5_out_uop_is_eret : issue_slots_4_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_amo = _T_166 ? issue_slots_6_out_uop_is_amo : _T_165 ? issue_slots_5_out_uop_is_amo : issue_slots_4_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_sfence = _T_166 ? issue_slots_6_out_uop_is_sfence : _T_165 ? issue_slots_5_out_uop_is_sfence : issue_slots_4_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_fencei = _T_166 ? issue_slots_6_out_uop_is_fencei : _T_165 ? issue_slots_5_out_uop_is_fencei : issue_slots_4_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_fence = _T_166 ? issue_slots_6_out_uop_is_fence : _T_165 ? issue_slots_5_out_uop_is_fence : issue_slots_4_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_sfb = _T_166 ? issue_slots_6_out_uop_is_sfb : _T_165 ? issue_slots_5_out_uop_is_sfb : issue_slots_4_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_br_type = _T_166 ? issue_slots_6_out_uop_br_type : _T_165 ? issue_slots_5_out_uop_br_type : issue_slots_4_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_br_tag = _T_166 ? issue_slots_6_out_uop_br_tag : _T_165 ? issue_slots_5_out_uop_br_tag : issue_slots_4_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_br_mask = _T_166 ? issue_slots_6_out_uop_br_mask : _T_165 ? issue_slots_5_out_uop_br_mask : issue_slots_4_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_dis_col_sel = _T_166 ? issue_slots_6_out_uop_dis_col_sel : _T_165 ? issue_slots_5_out_uop_dis_col_sel : issue_slots_4_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_p3_bypass_hint = _T_166 ? issue_slots_6_out_uop_iw_p3_bypass_hint : _T_165 ? issue_slots_5_out_uop_iw_p3_bypass_hint : issue_slots_4_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_p2_bypass_hint = _T_166 ? issue_slots_6_out_uop_iw_p2_bypass_hint : _T_165 ? issue_slots_5_out_uop_iw_p2_bypass_hint : issue_slots_4_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_p1_bypass_hint = _T_166 ? issue_slots_6_out_uop_iw_p1_bypass_hint : _T_165 ? issue_slots_5_out_uop_iw_p1_bypass_hint : issue_slots_4_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_issued = _T_166 ? issue_slots_6_out_uop_iw_issued : _T_165 ? issue_slots_5_out_uop_iw_issued : issue_slots_4_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_0 = _T_166 ? issue_slots_6_out_uop_fu_code_0 : _T_165 ? issue_slots_5_out_uop_fu_code_0 : issue_slots_4_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_1 = _T_166 ? issue_slots_6_out_uop_fu_code_1 : _T_165 ? issue_slots_5_out_uop_fu_code_1 : issue_slots_4_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_2 = _T_166 ? issue_slots_6_out_uop_fu_code_2 : _T_165 ? issue_slots_5_out_uop_fu_code_2 : issue_slots_4_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_3 = _T_166 ? issue_slots_6_out_uop_fu_code_3 : _T_165 ? issue_slots_5_out_uop_fu_code_3 : issue_slots_4_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_4 = _T_166 ? issue_slots_6_out_uop_fu_code_4 : _T_165 ? issue_slots_5_out_uop_fu_code_4 : issue_slots_4_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_5 = _T_166 ? issue_slots_6_out_uop_fu_code_5 : _T_165 ? issue_slots_5_out_uop_fu_code_5 : issue_slots_4_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_6 = _T_166 ? issue_slots_6_out_uop_fu_code_6 : _T_165 ? issue_slots_5_out_uop_fu_code_6 : issue_slots_4_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_7 = _T_166 ? issue_slots_6_out_uop_fu_code_7 : _T_165 ? issue_slots_5_out_uop_fu_code_7 : issue_slots_4_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_8 = _T_166 ? issue_slots_6_out_uop_fu_code_8 : _T_165 ? issue_slots_5_out_uop_fu_code_8 : issue_slots_4_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_9 = _T_166 ? issue_slots_6_out_uop_fu_code_9 : _T_165 ? issue_slots_5_out_uop_fu_code_9 : issue_slots_4_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iq_type_0 = _T_166 ? issue_slots_6_out_uop_iq_type_0 : _T_165 ? issue_slots_5_out_uop_iq_type_0 : issue_slots_4_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iq_type_1 = _T_166 ? issue_slots_6_out_uop_iq_type_1 : _T_165 ? issue_slots_5_out_uop_iq_type_1 : issue_slots_4_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iq_type_2 = _T_166 ? issue_slots_6_out_uop_iq_type_2 : _T_165 ? issue_slots_5_out_uop_iq_type_2 : issue_slots_4_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iq_type_3 = _T_166 ? issue_slots_6_out_uop_iq_type_3 : _T_165 ? issue_slots_5_out_uop_iq_type_3 : issue_slots_4_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_debug_pc = _T_166 ? issue_slots_6_out_uop_debug_pc : _T_165 ? issue_slots_5_out_uop_debug_pc : issue_slots_4_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_rvc = _T_166 ? issue_slots_6_out_uop_is_rvc : _T_165 ? issue_slots_5_out_uop_is_rvc : issue_slots_4_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_debug_inst = _T_166 ? issue_slots_6_out_uop_debug_inst : _T_165 ? issue_slots_5_out_uop_debug_inst : issue_slots_4_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_inst = _T_166 ? issue_slots_6_out_uop_inst : _T_165 ? issue_slots_5_out_uop_inst : issue_slots_4_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_3_clear_T = \|shamts_oh_3; // @[issue-unit-age-ordered.scala:158:23, :199:49] assign issue_slots_3_clear = _issue_slots_3_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_168 = shamts_oh_6 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_169 = shamts_oh_7 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_4_in_uop_valid = _T_169 ? issue_slots_7_will_be_valid : _T_168 ? issue_slots_6_will_be_valid : shamts_oh_5 == 3'h1 & issue_slots_5_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_4_in_uop_bits_debug_tsrc = _T_169 ? issue_slots_7_out_uop_debug_tsrc : _T_168 ? issue_slots_6_out_uop_debug_tsrc : issue_slots_5_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_debug_fsrc = _T_169 ? issue_slots_7_out_uop_debug_fsrc : _T_168 ? issue_slots_6_out_uop_debug_fsrc : issue_slots_5_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_bp_xcpt_if = _T_169 ? issue_slots_7_out_uop_bp_xcpt_if : _T_168 ? issue_slots_6_out_uop_bp_xcpt_if : issue_slots_5_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_bp_debug_if = _T_169 ? issue_slots_7_out_uop_bp_debug_if : _T_168 ? issue_slots_6_out_uop_bp_debug_if : issue_slots_5_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_xcpt_ma_if = _T_169 ? issue_slots_7_out_uop_xcpt_ma_if : _T_168 ? issue_slots_6_out_uop_xcpt_ma_if : issue_slots_5_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_xcpt_ae_if = _T_169 ? issue_slots_7_out_uop_xcpt_ae_if : _T_168 ? issue_slots_6_out_uop_xcpt_ae_if : issue_slots_5_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_xcpt_pf_if = _T_169 ? issue_slots_7_out_uop_xcpt_pf_if : _T_168 ? issue_slots_6_out_uop_xcpt_pf_if : issue_slots_5_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_typ = _T_169 ? issue_slots_7_out_uop_fp_typ : _T_168 ? issue_slots_6_out_uop_fp_typ : issue_slots_5_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_rm = _T_169 ? issue_slots_7_out_uop_fp_rm : _T_168 ? issue_slots_6_out_uop_fp_rm : issue_slots_5_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_val = _T_169 ? issue_slots_7_out_uop_fp_val : _T_168 ? issue_slots_6_out_uop_fp_val : issue_slots_5_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fcn_op = _T_169 ? issue_slots_7_out_uop_fcn_op : _T_168 ? issue_slots_6_out_uop_fcn_op : issue_slots_5_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fcn_dw = _T_169 ? issue_slots_7_out_uop_fcn_dw : _T_168 ? issue_slots_6_out_uop_fcn_dw : issue_slots_5_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_frs3_en = _T_169 ? issue_slots_7_out_uop_frs3_en : _T_168 ? issue_slots_6_out_uop_frs3_en : issue_slots_5_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs2_rtype = _T_169 ? issue_slots_7_out_uop_lrs2_rtype : _T_168 ? issue_slots_6_out_uop_lrs2_rtype : issue_slots_5_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs1_rtype = _T_169 ? issue_slots_7_out_uop_lrs1_rtype : _T_168 ? issue_slots_6_out_uop_lrs1_rtype : issue_slots_5_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_dst_rtype = _T_169 ? issue_slots_7_out_uop_dst_rtype : _T_168 ? issue_slots_6_out_uop_dst_rtype : issue_slots_5_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs3 = _T_169 ? issue_slots_7_out_uop_lrs3 : _T_168 ? issue_slots_6_out_uop_lrs3 : issue_slots_5_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs2 = _T_169 ? issue_slots_7_out_uop_lrs2 : _T_168 ? issue_slots_6_out_uop_lrs2 : issue_slots_5_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs1 = _T_169 ? issue_slots_7_out_uop_lrs1 : _T_168 ? issue_slots_6_out_uop_lrs1 : issue_slots_5_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ldst = _T_169 ? issue_slots_7_out_uop_ldst : _T_168 ? issue_slots_6_out_uop_ldst : issue_slots_5_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ldst_is_rs1 = _T_169 ? issue_slots_7_out_uop_ldst_is_rs1 : _T_168 ? issue_slots_6_out_uop_ldst_is_rs1 : issue_slots_5_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_csr_cmd = _T_169 ? issue_slots_7_out_uop_csr_cmd : _T_168 ? issue_slots_6_out_uop_csr_cmd : issue_slots_5_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_flush_on_commit = _T_169 ? issue_slots_7_out_uop_flush_on_commit : _T_168 ? issue_slots_6_out_uop_flush_on_commit : issue_slots_5_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_unique = _T_169 ? issue_slots_7_out_uop_is_unique : _T_168 ? issue_slots_6_out_uop_is_unique : issue_slots_5_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_uses_stq = _T_169 ? issue_slots_7_out_uop_uses_stq : _T_168 ? issue_slots_6_out_uop_uses_stq : issue_slots_5_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_uses_ldq = _T_169 ? issue_slots_7_out_uop_uses_ldq : _T_168 ? issue_slots_6_out_uop_uses_ldq : issue_slots_5_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_mem_signed = _T_169 ? issue_slots_7_out_uop_mem_signed : _T_168 ? issue_slots_6_out_uop_mem_signed : issue_slots_5_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_mem_size = _T_169 ? issue_slots_7_out_uop_mem_size : _T_168 ? issue_slots_6_out_uop_mem_size : issue_slots_5_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_mem_cmd = _T_169 ? issue_slots_7_out_uop_mem_cmd : _T_168 ? issue_slots_6_out_uop_mem_cmd : issue_slots_5_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_exc_cause = _T_169 ? issue_slots_7_out_uop_exc_cause : _T_168 ? issue_slots_6_out_uop_exc_cause : issue_slots_5_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_exception = _T_169 ? issue_slots_7_out_uop_exception : _T_168 ? issue_slots_6_out_uop_exception : issue_slots_5_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_stale_pdst = _T_169 ? issue_slots_7_out_uop_stale_pdst : _T_168 ? issue_slots_6_out_uop_stale_pdst : issue_slots_5_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ppred_busy = _T_169 ? issue_slots_7_out_uop_ppred_busy : _T_168 ? issue_slots_6_out_uop_ppred_busy : issue_slots_5_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs3_busy = _T_169 ? issue_slots_7_out_uop_prs3_busy : _T_168 ? issue_slots_6_out_uop_prs3_busy : issue_slots_5_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs2_busy = _T_169 ? issue_slots_7_out_uop_prs2_busy : _T_168 ? issue_slots_6_out_uop_prs2_busy : issue_slots_5_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs1_busy = _T_169 ? issue_slots_7_out_uop_prs1_busy : _T_168 ? issue_slots_6_out_uop_prs1_busy : issue_slots_5_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ppred = _T_169 ? issue_slots_7_out_uop_ppred : _T_168 ? issue_slots_6_out_uop_ppred : issue_slots_5_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs3 = _T_169 ? issue_slots_7_out_uop_prs3 : _T_168 ? issue_slots_6_out_uop_prs3 : issue_slots_5_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs2 = _T_169 ? issue_slots_7_out_uop_prs2 : _T_168 ? issue_slots_6_out_uop_prs2 : issue_slots_5_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs1 = _T_169 ? issue_slots_7_out_uop_prs1 : _T_168 ? issue_slots_6_out_uop_prs1 : issue_slots_5_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_pdst = _T_169 ? issue_slots_7_out_uop_pdst : _T_168 ? issue_slots_6_out_uop_pdst : issue_slots_5_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_rxq_idx = _T_169 ? issue_slots_7_out_uop_rxq_idx : _T_168 ? issue_slots_6_out_uop_rxq_idx : issue_slots_5_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_stq_idx = _T_169 ? issue_slots_7_out_uop_stq_idx : _T_168 ? issue_slots_6_out_uop_stq_idx : issue_slots_5_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ldq_idx = _T_169 ? issue_slots_7_out_uop_ldq_idx : _T_168 ? issue_slots_6_out_uop_ldq_idx : issue_slots_5_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_rob_idx = _T_169 ? issue_slots_7_out_uop_rob_idx : _T_168 ? issue_slots_6_out_uop_rob_idx : issue_slots_5_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_vec = _T_169 ? issue_slots_7_out_uop_fp_ctrl_vec : _T_168 ? issue_slots_6_out_uop_fp_ctrl_vec : issue_slots_5_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_wflags = _T_169 ? issue_slots_7_out_uop_fp_ctrl_wflags : _T_168 ? issue_slots_6_out_uop_fp_ctrl_wflags : issue_slots_5_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_sqrt = _T_169 ? issue_slots_7_out_uop_fp_ctrl_sqrt : _T_168 ? issue_slots_6_out_uop_fp_ctrl_sqrt : issue_slots_5_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_div = _T_169 ? issue_slots_7_out_uop_fp_ctrl_div : _T_168 ? issue_slots_6_out_uop_fp_ctrl_div : issue_slots_5_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_fma = _T_169 ? issue_slots_7_out_uop_fp_ctrl_fma : _T_168 ? issue_slots_6_out_uop_fp_ctrl_fma : issue_slots_5_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_fastpipe = _T_169 ? issue_slots_7_out_uop_fp_ctrl_fastpipe : _T_168 ? issue_slots_6_out_uop_fp_ctrl_fastpipe : issue_slots_5_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_toint = _T_169 ? issue_slots_7_out_uop_fp_ctrl_toint : _T_168 ? issue_slots_6_out_uop_fp_ctrl_toint : issue_slots_5_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_fromint = _T_169 ? issue_slots_7_out_uop_fp_ctrl_fromint : _T_168 ? issue_slots_6_out_uop_fp_ctrl_fromint : issue_slots_5_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_typeTagOut = _T_169 ? issue_slots_7_out_uop_fp_ctrl_typeTagOut : _T_168 ? issue_slots_6_out_uop_fp_ctrl_typeTagOut : issue_slots_5_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_typeTagIn = _T_169 ? issue_slots_7_out_uop_fp_ctrl_typeTagIn : _T_168 ? issue_slots_6_out_uop_fp_ctrl_typeTagIn : issue_slots_5_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_swap23 = _T_169 ? issue_slots_7_out_uop_fp_ctrl_swap23 : _T_168 ? issue_slots_6_out_uop_fp_ctrl_swap23 : issue_slots_5_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_swap12 = _T_169 ? issue_slots_7_out_uop_fp_ctrl_swap12 : _T_168 ? issue_slots_6_out_uop_fp_ctrl_swap12 : issue_slots_5_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_ren3 = _T_169 ? issue_slots_7_out_uop_fp_ctrl_ren3 : _T_168 ? issue_slots_6_out_uop_fp_ctrl_ren3 : issue_slots_5_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_ren2 = _T_169 ? issue_slots_7_out_uop_fp_ctrl_ren2 : _T_168 ? issue_slots_6_out_uop_fp_ctrl_ren2 : issue_slots_5_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_ren1 = _T_169 ? issue_slots_7_out_uop_fp_ctrl_ren1 : _T_168 ? issue_slots_6_out_uop_fp_ctrl_ren1 : issue_slots_5_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_wen = _T_169 ? issue_slots_7_out_uop_fp_ctrl_wen : _T_168 ? issue_slots_6_out_uop_fp_ctrl_wen : issue_slots_5_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_ldst = _T_169 ? issue_slots_7_out_uop_fp_ctrl_ldst : _T_168 ? issue_slots_6_out_uop_fp_ctrl_ldst : issue_slots_5_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_op2_sel = _T_169 ? issue_slots_7_out_uop_op2_sel : _T_168 ? issue_slots_6_out_uop_op2_sel : issue_slots_5_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_op1_sel = _T_169 ? issue_slots_7_out_uop_op1_sel : _T_168 ? issue_slots_6_out_uop_op1_sel : issue_slots_5_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_imm_packed = _T_169 ? issue_slots_7_out_uop_imm_packed : _T_168 ? issue_slots_6_out_uop_imm_packed : issue_slots_5_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_pimm = _T_169 ? issue_slots_7_out_uop_pimm : _T_168 ? issue_slots_6_out_uop_pimm : issue_slots_5_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_imm_sel = _T_169 ? issue_slots_7_out_uop_imm_sel : _T_168 ? issue_slots_6_out_uop_imm_sel : issue_slots_5_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_imm_rename = _T_169 ? issue_slots_7_out_uop_imm_rename : _T_168 ? issue_slots_6_out_uop_imm_rename : issue_slots_5_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_taken = _T_169 ? issue_slots_7_out_uop_taken : _T_168 ? issue_slots_6_out_uop_taken : issue_slots_5_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_pc_lob = _T_169 ? issue_slots_7_out_uop_pc_lob : _T_168 ? issue_slots_6_out_uop_pc_lob : issue_slots_5_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_edge_inst = _T_169 ? issue_slots_7_out_uop_edge_inst : _T_168 ? issue_slots_6_out_uop_edge_inst : issue_slots_5_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ftq_idx = _T_169 ? issue_slots_7_out_uop_ftq_idx : _T_168 ? issue_slots_6_out_uop_ftq_idx : issue_slots_5_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_mov = _T_169 ? issue_slots_7_out_uop_is_mov : _T_168 ? issue_slots_6_out_uop_is_mov : issue_slots_5_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_rocc = _T_169 ? issue_slots_7_out_uop_is_rocc : _T_168 ? issue_slots_6_out_uop_is_rocc : issue_slots_5_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_sys_pc2epc = _T_169 ? issue_slots_7_out_uop_is_sys_pc2epc : _T_168 ? issue_slots_6_out_uop_is_sys_pc2epc : issue_slots_5_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_eret = _T_169 ? issue_slots_7_out_uop_is_eret : _T_168 ? issue_slots_6_out_uop_is_eret : issue_slots_5_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_amo = _T_169 ? issue_slots_7_out_uop_is_amo : _T_168 ? issue_slots_6_out_uop_is_amo : issue_slots_5_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_sfence = _T_169 ? issue_slots_7_out_uop_is_sfence : _T_168 ? issue_slots_6_out_uop_is_sfence : issue_slots_5_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_fencei = _T_169 ? issue_slots_7_out_uop_is_fencei : _T_168 ? issue_slots_6_out_uop_is_fencei : issue_slots_5_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_fence = _T_169 ? issue_slots_7_out_uop_is_fence : _T_168 ? issue_slots_6_out_uop_is_fence : issue_slots_5_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_sfb = _T_169 ? issue_slots_7_out_uop_is_sfb : _T_168 ? issue_slots_6_out_uop_is_sfb : issue_slots_5_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_br_type = _T_169 ? issue_slots_7_out_uop_br_type : _T_168 ? issue_slots_6_out_uop_br_type : issue_slots_5_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_br_tag = _T_169 ? issue_slots_7_out_uop_br_tag : _T_168 ? issue_slots_6_out_uop_br_tag : issue_slots_5_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_br_mask = _T_169 ? issue_slots_7_out_uop_br_mask : _T_168 ? issue_slots_6_out_uop_br_mask : issue_slots_5_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_dis_col_sel = _T_169 ? issue_slots_7_out_uop_dis_col_sel : _T_168 ? issue_slots_6_out_uop_dis_col_sel : issue_slots_5_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_p3_bypass_hint = _T_169 ? issue_slots_7_out_uop_iw_p3_bypass_hint : _T_168 ? issue_slots_6_out_uop_iw_p3_bypass_hint : issue_slots_5_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_p2_bypass_hint = _T_169 ? issue_slots_7_out_uop_iw_p2_bypass_hint : _T_168 ? issue_slots_6_out_uop_iw_p2_bypass_hint : issue_slots_5_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_p1_bypass_hint = _T_169 ? issue_slots_7_out_uop_iw_p1_bypass_hint : _T_168 ? issue_slots_6_out_uop_iw_p1_bypass_hint : issue_slots_5_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_issued = _T_169 ? issue_slots_7_out_uop_iw_issued : _T_168 ? issue_slots_6_out_uop_iw_issued : issue_slots_5_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_0 = _T_169 ? issue_slots_7_out_uop_fu_code_0 : _T_168 ? issue_slots_6_out_uop_fu_code_0 : issue_slots_5_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_1 = _T_169 ? issue_slots_7_out_uop_fu_code_1 : _T_168 ? issue_slots_6_out_uop_fu_code_1 : issue_slots_5_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_2 = _T_169 ? issue_slots_7_out_uop_fu_code_2 : _T_168 ? issue_slots_6_out_uop_fu_code_2 : issue_slots_5_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_3 = _T_169 ? issue_slots_7_out_uop_fu_code_3 : _T_168 ? issue_slots_6_out_uop_fu_code_3 : issue_slots_5_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_4 = _T_169 ? issue_slots_7_out_uop_fu_code_4 : _T_168 ? issue_slots_6_out_uop_fu_code_4 : issue_slots_5_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_5 = _T_169 ? issue_slots_7_out_uop_fu_code_5 : _T_168 ? issue_slots_6_out_uop_fu_code_5 : issue_slots_5_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_6 = _T_169 ? issue_slots_7_out_uop_fu_code_6 : _T_168 ? issue_slots_6_out_uop_fu_code_6 : issue_slots_5_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_7 = _T_169 ? issue_slots_7_out_uop_fu_code_7 : _T_168 ? issue_slots_6_out_uop_fu_code_7 : issue_slots_5_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_8 = _T_169 ? issue_slots_7_out_uop_fu_code_8 : _T_168 ? issue_slots_6_out_uop_fu_code_8 : issue_slots_5_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_9 = _T_169 ? issue_slots_7_out_uop_fu_code_9 : _T_168 ? issue_slots_6_out_uop_fu_code_9 : issue_slots_5_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iq_type_0 = _T_169 ? issue_slots_7_out_uop_iq_type_0 : _T_168 ? issue_slots_6_out_uop_iq_type_0 : issue_slots_5_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iq_type_1 = _T_169 ? issue_slots_7_out_uop_iq_type_1 : _T_168 ? issue_slots_6_out_uop_iq_type_1 : issue_slots_5_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iq_type_2 = _T_169 ? issue_slots_7_out_uop_iq_type_2 : _T_168 ? issue_slots_6_out_uop_iq_type_2 : issue_slots_5_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iq_type_3 = _T_169 ? issue_slots_7_out_uop_iq_type_3 : _T_168 ? issue_slots_6_out_uop_iq_type_3 : issue_slots_5_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_debug_pc = _T_169 ? issue_slots_7_out_uop_debug_pc : _T_168 ? issue_slots_6_out_uop_debug_pc : issue_slots_5_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_rvc = _T_169 ? issue_slots_7_out_uop_is_rvc : _T_168 ? issue_slots_6_out_uop_is_rvc : issue_slots_5_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_debug_inst = _T_169 ? issue_slots_7_out_uop_debug_inst : _T_168 ? issue_slots_6_out_uop_debug_inst : issue_slots_5_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_inst = _T_169 ? issue_slots_7_out_uop_inst : _T_168 ? issue_slots_6_out_uop_inst : issue_slots_5_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_4_clear_T = \|shamts_oh_4; // @[issue-unit-age-ordered.scala:158:23, :199:49] assign issue_slots_4_clear = _issue_slots_4_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_171 = shamts_oh_7 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_172 = shamts_oh_8 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_5_in_uop_valid = _T_172 ? issue_slots_8_will_be_valid : _T_171 ? issue_slots_7_will_be_valid : shamts_oh_6 == 3'h1 & issue_slots_6_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_5_in_uop_bits_debug_tsrc = _T_172 ? issue_slots_8_out_uop_debug_tsrc : _T_171 ? issue_slots_7_out_uop_debug_tsrc : issue_slots_6_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_debug_fsrc = _T_172 ? issue_slots_8_out_uop_debug_fsrc : _T_171 ? issue_slots_7_out_uop_debug_fsrc : issue_slots_6_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_bp_xcpt_if = _T_172 ? issue_slots_8_out_uop_bp_xcpt_if : _T_171 ? issue_slots_7_out_uop_bp_xcpt_if : issue_slots_6_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_bp_debug_if = _T_172 ? issue_slots_8_out_uop_bp_debug_if : _T_171 ? issue_slots_7_out_uop_bp_debug_if : issue_slots_6_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_xcpt_ma_if = _T_172 ? issue_slots_8_out_uop_xcpt_ma_if : _T_171 ? issue_slots_7_out_uop_xcpt_ma_if : issue_slots_6_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_xcpt_ae_if = _T_172 ? issue_slots_8_out_uop_xcpt_ae_if : _T_171 ? issue_slots_7_out_uop_xcpt_ae_if : issue_slots_6_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_xcpt_pf_if = _T_172 ? issue_slots_8_out_uop_xcpt_pf_if : _T_171 ? issue_slots_7_out_uop_xcpt_pf_if : issue_slots_6_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_typ = _T_172 ? issue_slots_8_out_uop_fp_typ : _T_171 ? issue_slots_7_out_uop_fp_typ : issue_slots_6_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_rm = _T_172 ? issue_slots_8_out_uop_fp_rm : _T_171 ? issue_slots_7_out_uop_fp_rm : issue_slots_6_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_val = _T_172 ? issue_slots_8_out_uop_fp_val : _T_171 ? issue_slots_7_out_uop_fp_val : issue_slots_6_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fcn_op = _T_172 ? issue_slots_8_out_uop_fcn_op : _T_171 ? issue_slots_7_out_uop_fcn_op : issue_slots_6_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fcn_dw = _T_172 ? issue_slots_8_out_uop_fcn_dw : _T_171 ? issue_slots_7_out_uop_fcn_dw : issue_slots_6_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_frs3_en = _T_172 ? issue_slots_8_out_uop_frs3_en : _T_171 ? issue_slots_7_out_uop_frs3_en : issue_slots_6_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs2_rtype = _T_172 ? issue_slots_8_out_uop_lrs2_rtype : _T_171 ? issue_slots_7_out_uop_lrs2_rtype : issue_slots_6_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs1_rtype = _T_172 ? issue_slots_8_out_uop_lrs1_rtype : _T_171 ? issue_slots_7_out_uop_lrs1_rtype : issue_slots_6_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_dst_rtype = _T_172 ? issue_slots_8_out_uop_dst_rtype : _T_171 ? issue_slots_7_out_uop_dst_rtype : issue_slots_6_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs3 = _T_172 ? issue_slots_8_out_uop_lrs3 : _T_171 ? issue_slots_7_out_uop_lrs3 : issue_slots_6_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs2 = _T_172 ? issue_slots_8_out_uop_lrs2 : _T_171 ? issue_slots_7_out_uop_lrs2 : issue_slots_6_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs1 = _T_172 ? issue_slots_8_out_uop_lrs1 : _T_171 ? issue_slots_7_out_uop_lrs1 : issue_slots_6_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ldst = _T_172 ? issue_slots_8_out_uop_ldst : _T_171 ? issue_slots_7_out_uop_ldst : issue_slots_6_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ldst_is_rs1 = _T_172 ? issue_slots_8_out_uop_ldst_is_rs1 : _T_171 ? issue_slots_7_out_uop_ldst_is_rs1 : issue_slots_6_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_csr_cmd = _T_172 ? issue_slots_8_out_uop_csr_cmd : _T_171 ? issue_slots_7_out_uop_csr_cmd : issue_slots_6_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_flush_on_commit = _T_172 ? issue_slots_8_out_uop_flush_on_commit : _T_171 ? issue_slots_7_out_uop_flush_on_commit : issue_slots_6_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_unique = _T_172 ? issue_slots_8_out_uop_is_unique : _T_171 ? issue_slots_7_out_uop_is_unique : issue_slots_6_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_uses_stq = _T_172 ? issue_slots_8_out_uop_uses_stq : _T_171 ? issue_slots_7_out_uop_uses_stq : issue_slots_6_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_uses_ldq = _T_172 ? issue_slots_8_out_uop_uses_ldq : _T_171 ? issue_slots_7_out_uop_uses_ldq : issue_slots_6_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_mem_signed = _T_172 ? issue_slots_8_out_uop_mem_signed : _T_171 ? issue_slots_7_out_uop_mem_signed : issue_slots_6_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_mem_size = _T_172 ? issue_slots_8_out_uop_mem_size : _T_171 ? issue_slots_7_out_uop_mem_size : issue_slots_6_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_mem_cmd = _T_172 ? issue_slots_8_out_uop_mem_cmd : _T_171 ? issue_slots_7_out_uop_mem_cmd : issue_slots_6_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_exc_cause = _T_172 ? issue_slots_8_out_uop_exc_cause : _T_171 ? issue_slots_7_out_uop_exc_cause : issue_slots_6_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_exception = _T_172 ? issue_slots_8_out_uop_exception : _T_171 ? issue_slots_7_out_uop_exception : issue_slots_6_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_stale_pdst = _T_172 ? issue_slots_8_out_uop_stale_pdst : _T_171 ? issue_slots_7_out_uop_stale_pdst : issue_slots_6_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ppred_busy = _T_172 ? issue_slots_8_out_uop_ppred_busy : _T_171 ? issue_slots_7_out_uop_ppred_busy : issue_slots_6_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs3_busy = _T_172 ? issue_slots_8_out_uop_prs3_busy : _T_171 ? issue_slots_7_out_uop_prs3_busy : issue_slots_6_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs2_busy = _T_172 ? issue_slots_8_out_uop_prs2_busy : _T_171 ? issue_slots_7_out_uop_prs2_busy : issue_slots_6_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs1_busy = _T_172 ? issue_slots_8_out_uop_prs1_busy : _T_171 ? issue_slots_7_out_uop_prs1_busy : issue_slots_6_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ppred = _T_172 ? issue_slots_8_out_uop_ppred : _T_171 ? issue_slots_7_out_uop_ppred : issue_slots_6_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs3 = _T_172 ? issue_slots_8_out_uop_prs3 : _T_171 ? issue_slots_7_out_uop_prs3 : issue_slots_6_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs2 = _T_172 ? issue_slots_8_out_uop_prs2 : _T_171 ? issue_slots_7_out_uop_prs2 : issue_slots_6_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs1 = _T_172 ? issue_slots_8_out_uop_prs1 : _T_171 ? issue_slots_7_out_uop_prs1 : issue_slots_6_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_pdst = _T_172 ? issue_slots_8_out_uop_pdst : _T_171 ? issue_slots_7_out_uop_pdst : issue_slots_6_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_rxq_idx = _T_172 ? issue_slots_8_out_uop_rxq_idx : _T_171 ? issue_slots_7_out_uop_rxq_idx : issue_slots_6_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_stq_idx = _T_172 ? issue_slots_8_out_uop_stq_idx : _T_171 ? issue_slots_7_out_uop_stq_idx : issue_slots_6_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ldq_idx = _T_172 ? issue_slots_8_out_uop_ldq_idx : _T_171 ? issue_slots_7_out_uop_ldq_idx : issue_slots_6_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_rob_idx = _T_172 ? issue_slots_8_out_uop_rob_idx : _T_171 ? issue_slots_7_out_uop_rob_idx : issue_slots_6_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_vec = _T_172 ? issue_slots_8_out_uop_fp_ctrl_vec : _T_171 ? issue_slots_7_out_uop_fp_ctrl_vec : issue_slots_6_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_wflags = _T_172 ? issue_slots_8_out_uop_fp_ctrl_wflags : _T_171 ? issue_slots_7_out_uop_fp_ctrl_wflags : issue_slots_6_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_sqrt = _T_172 ? issue_slots_8_out_uop_fp_ctrl_sqrt : _T_171 ? issue_slots_7_out_uop_fp_ctrl_sqrt : issue_slots_6_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_div = _T_172 ? issue_slots_8_out_uop_fp_ctrl_div : _T_171 ? issue_slots_7_out_uop_fp_ctrl_div : issue_slots_6_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_fma = _T_172 ? issue_slots_8_out_uop_fp_ctrl_fma : _T_171 ? issue_slots_7_out_uop_fp_ctrl_fma : issue_slots_6_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_fastpipe = _T_172 ? issue_slots_8_out_uop_fp_ctrl_fastpipe : _T_171 ? issue_slots_7_out_uop_fp_ctrl_fastpipe : issue_slots_6_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_toint = _T_172 ? issue_slots_8_out_uop_fp_ctrl_toint : _T_171 ? issue_slots_7_out_uop_fp_ctrl_toint : issue_slots_6_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_fromint = _T_172 ? issue_slots_8_out_uop_fp_ctrl_fromint : _T_171 ? issue_slots_7_out_uop_fp_ctrl_fromint : issue_slots_6_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_typeTagOut = _T_172 ? issue_slots_8_out_uop_fp_ctrl_typeTagOut : _T_171 ? issue_slots_7_out_uop_fp_ctrl_typeTagOut : issue_slots_6_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_typeTagIn = _T_172 ? issue_slots_8_out_uop_fp_ctrl_typeTagIn : _T_171 ? issue_slots_7_out_uop_fp_ctrl_typeTagIn : issue_slots_6_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_swap23 = _T_172 ? issue_slots_8_out_uop_fp_ctrl_swap23 : _T_171 ? issue_slots_7_out_uop_fp_ctrl_swap23 : issue_slots_6_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_swap12 = _T_172 ? issue_slots_8_out_uop_fp_ctrl_swap12 : _T_171 ? issue_slots_7_out_uop_fp_ctrl_swap12 : issue_slots_6_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_ren3 = _T_172 ? issue_slots_8_out_uop_fp_ctrl_ren3 : _T_171 ? issue_slots_7_out_uop_fp_ctrl_ren3 : issue_slots_6_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_ren2 = _T_172 ? issue_slots_8_out_uop_fp_ctrl_ren2 : _T_171 ? issue_slots_7_out_uop_fp_ctrl_ren2 : issue_slots_6_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_ren1 = _T_172 ? issue_slots_8_out_uop_fp_ctrl_ren1 : _T_171 ? issue_slots_7_out_uop_fp_ctrl_ren1 : issue_slots_6_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_wen = _T_172 ? issue_slots_8_out_uop_fp_ctrl_wen : _T_171 ? issue_slots_7_out_uop_fp_ctrl_wen : issue_slots_6_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_ldst = _T_172 ? issue_slots_8_out_uop_fp_ctrl_ldst : _T_171 ? issue_slots_7_out_uop_fp_ctrl_ldst : issue_slots_6_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_op2_sel = _T_172 ? issue_slots_8_out_uop_op2_sel : _T_171 ? issue_slots_7_out_uop_op2_sel : issue_slots_6_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_op1_sel = _T_172 ? issue_slots_8_out_uop_op1_sel : _T_171 ? issue_slots_7_out_uop_op1_sel : issue_slots_6_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_imm_packed = _T_172 ? issue_slots_8_out_uop_imm_packed : _T_171 ? issue_slots_7_out_uop_imm_packed : issue_slots_6_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_pimm = _T_172 ? issue_slots_8_out_uop_pimm : _T_171 ? issue_slots_7_out_uop_pimm : issue_slots_6_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_imm_sel = _T_172 ? issue_slots_8_out_uop_imm_sel : _T_171 ? issue_slots_7_out_uop_imm_sel : issue_slots_6_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_imm_rename = _T_172 ? issue_slots_8_out_uop_imm_rename : _T_171 ? issue_slots_7_out_uop_imm_rename : issue_slots_6_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_taken = _T_172 ? issue_slots_8_out_uop_taken : _T_171 ? issue_slots_7_out_uop_taken : issue_slots_6_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_pc_lob = _T_172 ? issue_slots_8_out_uop_pc_lob : _T_171 ? issue_slots_7_out_uop_pc_lob : issue_slots_6_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_edge_inst = _T_172 ? issue_slots_8_out_uop_edge_inst : _T_171 ? issue_slots_7_out_uop_edge_inst : issue_slots_6_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ftq_idx = _T_172 ? issue_slots_8_out_uop_ftq_idx : _T_171 ? issue_slots_7_out_uop_ftq_idx : issue_slots_6_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_mov = _T_172 ? issue_slots_8_out_uop_is_mov : _T_171 ? issue_slots_7_out_uop_is_mov : issue_slots_6_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_rocc = _T_172 ? issue_slots_8_out_uop_is_rocc : _T_171 ? issue_slots_7_out_uop_is_rocc : issue_slots_6_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_sys_pc2epc = _T_172 ? issue_slots_8_out_uop_is_sys_pc2epc : _T_171 ? issue_slots_7_out_uop_is_sys_pc2epc : issue_slots_6_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_eret = _T_172 ? issue_slots_8_out_uop_is_eret : _T_171 ? issue_slots_7_out_uop_is_eret : issue_slots_6_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_amo = _T_172 ? issue_slots_8_out_uop_is_amo : _T_171 ? issue_slots_7_out_uop_is_amo : issue_slots_6_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_sfence = _T_172 ? issue_slots_8_out_uop_is_sfence : _T_171 ? issue_slots_7_out_uop_is_sfence : issue_slots_6_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_fencei = _T_172 ? issue_slots_8_out_uop_is_fencei : _T_171 ? issue_slots_7_out_uop_is_fencei : issue_slots_6_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_fence = _T_172 ? issue_slots_8_out_uop_is_fence : _T_171 ? issue_slots_7_out_uop_is_fence : issue_slots_6_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_sfb = _T_172 ? issue_slots_8_out_uop_is_sfb : _T_171 ? issue_slots_7_out_uop_is_sfb : issue_slots_6_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_br_type = _T_172 ? issue_slots_8_out_uop_br_type : _T_171 ? issue_slots_7_out_uop_br_type : issue_slots_6_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_br_tag = _T_172 ? issue_slots_8_out_uop_br_tag : _T_171 ? issue_slots_7_out_uop_br_tag : issue_slots_6_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_br_mask = _T_172 ? issue_slots_8_out_uop_br_mask : _T_171 ? issue_slots_7_out_uop_br_mask : issue_slots_6_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_dis_col_sel = _T_172 ? issue_slots_8_out_uop_dis_col_sel : _T_171 ? issue_slots_7_out_uop_dis_col_sel : issue_slots_6_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_p3_bypass_hint = _T_172 ? issue_slots_8_out_uop_iw_p3_bypass_hint : _T_171 ? issue_slots_7_out_uop_iw_p3_bypass_hint : issue_slots_6_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_p2_bypass_hint = _T_172 ? issue_slots_8_out_uop_iw_p2_bypass_hint : _T_171 ? issue_slots_7_out_uop_iw_p2_bypass_hint : issue_slots_6_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_p1_bypass_hint = _T_172 ? issue_slots_8_out_uop_iw_p1_bypass_hint : _T_171 ? issue_slots_7_out_uop_iw_p1_bypass_hint : issue_slots_6_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_issued = _T_172 ? issue_slots_8_out_uop_iw_issued : _T_171 ? issue_slots_7_out_uop_iw_issued : issue_slots_6_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_0 = _T_172 ? issue_slots_8_out_uop_fu_code_0 : _T_171 ? issue_slots_7_out_uop_fu_code_0 : issue_slots_6_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_1 = _T_172 ? issue_slots_8_out_uop_fu_code_1 : _T_171 ? issue_slots_7_out_uop_fu_code_1 : issue_slots_6_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_2 = _T_172 ? issue_slots_8_out_uop_fu_code_2 : _T_171 ? issue_slots_7_out_uop_fu_code_2 : issue_slots_6_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_3 = _T_172 ? issue_slots_8_out_uop_fu_code_3 : _T_171 ? issue_slots_7_out_uop_fu_code_3 : issue_slots_6_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_4 = _T_172 ? issue_slots_8_out_uop_fu_code_4 : _T_171 ? issue_slots_7_out_uop_fu_code_4 : issue_slots_6_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_5 = _T_172 ? issue_slots_8_out_uop_fu_code_5 : _T_171 ? issue_slots_7_out_uop_fu_code_5 : issue_slots_6_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_6 = _T_172 ? issue_slots_8_out_uop_fu_code_6 : _T_171 ? issue_slots_7_out_uop_fu_code_6 : issue_slots_6_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_7 = _T_172 ? issue_slots_8_out_uop_fu_code_7 : _T_171 ? issue_slots_7_out_uop_fu_code_7 : issue_slots_6_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_8 = _T_172 ? issue_slots_8_out_uop_fu_code_8 : _T_171 ? issue_slots_7_out_uop_fu_code_8 : issue_slots_6_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_9 = _T_172 ? issue_slots_8_out_uop_fu_code_9 : _T_171 ? issue_slots_7_out_uop_fu_code_9 : issue_slots_6_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iq_type_0 = _T_172 ? issue_slots_8_out_uop_iq_type_0 : _T_171 ? issue_slots_7_out_uop_iq_type_0 : issue_slots_6_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iq_type_1 = _T_172 ? issue_slots_8_out_uop_iq_type_1 : _T_171 ? issue_slots_7_out_uop_iq_type_1 : issue_slots_6_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iq_type_2 = _T_172 ? issue_slots_8_out_uop_iq_type_2 : _T_171 ? issue_slots_7_out_uop_iq_type_2 : issue_slots_6_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iq_type_3 = _T_172 ? issue_slots_8_out_uop_iq_type_3 : _T_171 ? issue_slots_7_out_uop_iq_type_3 : issue_slots_6_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_debug_pc = _T_172 ? issue_slots_8_out_uop_debug_pc : _T_171 ? issue_slots_7_out_uop_debug_pc : issue_slots_6_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_rvc = _T_172 ? issue_slots_8_out_uop_is_rvc : _T_171 ? issue_slots_7_out_uop_is_rvc : issue_slots_6_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_debug_inst = _T_172 ? issue_slots_8_out_uop_debug_inst : _T_171 ? issue_slots_7_out_uop_debug_inst : issue_slots_6_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_inst = _T_172 ? issue_slots_8_out_uop_inst : _T_171 ? issue_slots_7_out_uop_inst : issue_slots_6_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_5_clear_T = \|shamts_oh_5; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_5_clear = _issue_slots_5_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_174 = shamts_oh_8 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_175 = shamts_oh_9 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_6_in_uop_valid = _T_175 ? issue_slots_9_will_be_valid : _T_174 ? issue_slots_8_will_be_valid : shamts_oh_7 == 3'h1 & issue_slots_7_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_6_in_uop_bits_debug_tsrc = _T_175 ? issue_slots_9_out_uop_debug_tsrc : _T_174 ? issue_slots_8_out_uop_debug_tsrc : issue_slots_7_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_debug_fsrc = _T_175 ? issue_slots_9_out_uop_debug_fsrc : _T_174 ? issue_slots_8_out_uop_debug_fsrc : issue_slots_7_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_bp_xcpt_if = _T_175 ? issue_slots_9_out_uop_bp_xcpt_if : _T_174 ? issue_slots_8_out_uop_bp_xcpt_if : issue_slots_7_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_bp_debug_if = _T_175 ? issue_slots_9_out_uop_bp_debug_if : _T_174 ? issue_slots_8_out_uop_bp_debug_if : issue_slots_7_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_xcpt_ma_if = _T_175 ? issue_slots_9_out_uop_xcpt_ma_if : _T_174 ? issue_slots_8_out_uop_xcpt_ma_if : issue_slots_7_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_xcpt_ae_if = _T_175 ? issue_slots_9_out_uop_xcpt_ae_if : _T_174 ? issue_slots_8_out_uop_xcpt_ae_if : issue_slots_7_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_xcpt_pf_if = _T_175 ? issue_slots_9_out_uop_xcpt_pf_if : _T_174 ? issue_slots_8_out_uop_xcpt_pf_if : issue_slots_7_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_typ = _T_175 ? issue_slots_9_out_uop_fp_typ : _T_174 ? issue_slots_8_out_uop_fp_typ : issue_slots_7_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_rm = _T_175 ? issue_slots_9_out_uop_fp_rm : _T_174 ? issue_slots_8_out_uop_fp_rm : issue_slots_7_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_val = _T_175 ? issue_slots_9_out_uop_fp_val : _T_174 ? issue_slots_8_out_uop_fp_val : issue_slots_7_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fcn_op = _T_175 ? issue_slots_9_out_uop_fcn_op : _T_174 ? issue_slots_8_out_uop_fcn_op : issue_slots_7_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fcn_dw = _T_175 ? issue_slots_9_out_uop_fcn_dw : _T_174 ? issue_slots_8_out_uop_fcn_dw : issue_slots_7_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_frs3_en = _T_175 ? issue_slots_9_out_uop_frs3_en : _T_174 ? issue_slots_8_out_uop_frs3_en : issue_slots_7_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs2_rtype = _T_175 ? issue_slots_9_out_uop_lrs2_rtype : _T_174 ? issue_slots_8_out_uop_lrs2_rtype : issue_slots_7_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs1_rtype = _T_175 ? issue_slots_9_out_uop_lrs1_rtype : _T_174 ? issue_slots_8_out_uop_lrs1_rtype : issue_slots_7_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_dst_rtype = _T_175 ? issue_slots_9_out_uop_dst_rtype : _T_174 ? issue_slots_8_out_uop_dst_rtype : issue_slots_7_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs3 = _T_175 ? issue_slots_9_out_uop_lrs3 : _T_174 ? issue_slots_8_out_uop_lrs3 : issue_slots_7_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs2 = _T_175 ? issue_slots_9_out_uop_lrs2 : _T_174 ? issue_slots_8_out_uop_lrs2 : issue_slots_7_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs1 = _T_175 ? issue_slots_9_out_uop_lrs1 : _T_174 ? issue_slots_8_out_uop_lrs1 : issue_slots_7_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ldst = _T_175 ? issue_slots_9_out_uop_ldst : _T_174 ? issue_slots_8_out_uop_ldst : issue_slots_7_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ldst_is_rs1 = _T_175 ? issue_slots_9_out_uop_ldst_is_rs1 : _T_174 ? issue_slots_8_out_uop_ldst_is_rs1 : issue_slots_7_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_csr_cmd = _T_175 ? issue_slots_9_out_uop_csr_cmd : _T_174 ? issue_slots_8_out_uop_csr_cmd : issue_slots_7_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_flush_on_commit = _T_175 ? issue_slots_9_out_uop_flush_on_commit : _T_174 ? issue_slots_8_out_uop_flush_on_commit : issue_slots_7_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_unique = _T_175 ? issue_slots_9_out_uop_is_unique : _T_174 ? issue_slots_8_out_uop_is_unique : issue_slots_7_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_uses_stq = _T_175 ? issue_slots_9_out_uop_uses_stq : _T_174 ? issue_slots_8_out_uop_uses_stq : issue_slots_7_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_uses_ldq = _T_175 ? issue_slots_9_out_uop_uses_ldq : _T_174 ? issue_slots_8_out_uop_uses_ldq : issue_slots_7_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_mem_signed = _T_175 ? issue_slots_9_out_uop_mem_signed : _T_174 ? issue_slots_8_out_uop_mem_signed : issue_slots_7_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_mem_size = _T_175 ? issue_slots_9_out_uop_mem_size : _T_174 ? issue_slots_8_out_uop_mem_size : issue_slots_7_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_mem_cmd = _T_175 ? issue_slots_9_out_uop_mem_cmd : _T_174 ? issue_slots_8_out_uop_mem_cmd : issue_slots_7_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_exc_cause = _T_175 ? issue_slots_9_out_uop_exc_cause : _T_174 ? issue_slots_8_out_uop_exc_cause : issue_slots_7_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_exception = _T_175 ? issue_slots_9_out_uop_exception : _T_174 ? issue_slots_8_out_uop_exception : issue_slots_7_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_stale_pdst = _T_175 ? issue_slots_9_out_uop_stale_pdst : _T_174 ? issue_slots_8_out_uop_stale_pdst : issue_slots_7_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ppred_busy = _T_175 ? issue_slots_9_out_uop_ppred_busy : _T_174 ? issue_slots_8_out_uop_ppred_busy : issue_slots_7_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs3_busy = _T_175 ? issue_slots_9_out_uop_prs3_busy : _T_174 ? issue_slots_8_out_uop_prs3_busy : issue_slots_7_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs2_busy = _T_175 ? issue_slots_9_out_uop_prs2_busy : _T_174 ? issue_slots_8_out_uop_prs2_busy : issue_slots_7_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs1_busy = _T_175 ? issue_slots_9_out_uop_prs1_busy : _T_174 ? issue_slots_8_out_uop_prs1_busy : issue_slots_7_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ppred = _T_175 ? issue_slots_9_out_uop_ppred : _T_174 ? issue_slots_8_out_uop_ppred : issue_slots_7_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs3 = _T_175 ? issue_slots_9_out_uop_prs3 : _T_174 ? issue_slots_8_out_uop_prs3 : issue_slots_7_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs2 = _T_175 ? issue_slots_9_out_uop_prs2 : _T_174 ? issue_slots_8_out_uop_prs2 : issue_slots_7_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs1 = _T_175 ? issue_slots_9_out_uop_prs1 : _T_174 ? issue_slots_8_out_uop_prs1 : issue_slots_7_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_pdst = _T_175 ? issue_slots_9_out_uop_pdst : _T_174 ? issue_slots_8_out_uop_pdst : issue_slots_7_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_rxq_idx = _T_175 ? issue_slots_9_out_uop_rxq_idx : _T_174 ? issue_slots_8_out_uop_rxq_idx : issue_slots_7_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_stq_idx = _T_175 ? issue_slots_9_out_uop_stq_idx : _T_174 ? issue_slots_8_out_uop_stq_idx : issue_slots_7_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ldq_idx = _T_175 ? issue_slots_9_out_uop_ldq_idx : _T_174 ? issue_slots_8_out_uop_ldq_idx : issue_slots_7_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_rob_idx = _T_175 ? issue_slots_9_out_uop_rob_idx : _T_174 ? issue_slots_8_out_uop_rob_idx : issue_slots_7_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_vec = _T_175 ? issue_slots_9_out_uop_fp_ctrl_vec : _T_174 ? issue_slots_8_out_uop_fp_ctrl_vec : issue_slots_7_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_wflags = _T_175 ? issue_slots_9_out_uop_fp_ctrl_wflags : _T_174 ? issue_slots_8_out_uop_fp_ctrl_wflags : issue_slots_7_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_sqrt = _T_175 ? issue_slots_9_out_uop_fp_ctrl_sqrt : _T_174 ? issue_slots_8_out_uop_fp_ctrl_sqrt : issue_slots_7_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_div = _T_175 ? issue_slots_9_out_uop_fp_ctrl_div : _T_174 ? issue_slots_8_out_uop_fp_ctrl_div : issue_slots_7_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_fma = _T_175 ? issue_slots_9_out_uop_fp_ctrl_fma : _T_174 ? issue_slots_8_out_uop_fp_ctrl_fma : issue_slots_7_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_fastpipe = _T_175 ? issue_slots_9_out_uop_fp_ctrl_fastpipe : _T_174 ? issue_slots_8_out_uop_fp_ctrl_fastpipe : issue_slots_7_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_toint = _T_175 ? issue_slots_9_out_uop_fp_ctrl_toint : _T_174 ? issue_slots_8_out_uop_fp_ctrl_toint : issue_slots_7_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_fromint = _T_175 ? issue_slots_9_out_uop_fp_ctrl_fromint : _T_174 ? issue_slots_8_out_uop_fp_ctrl_fromint : issue_slots_7_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_typeTagOut = _T_175 ? issue_slots_9_out_uop_fp_ctrl_typeTagOut : _T_174 ? issue_slots_8_out_uop_fp_ctrl_typeTagOut : issue_slots_7_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_typeTagIn = _T_175 ? issue_slots_9_out_uop_fp_ctrl_typeTagIn : _T_174 ? issue_slots_8_out_uop_fp_ctrl_typeTagIn : issue_slots_7_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_swap23 = _T_175 ? issue_slots_9_out_uop_fp_ctrl_swap23 : _T_174 ? issue_slots_8_out_uop_fp_ctrl_swap23 : issue_slots_7_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_swap12 = _T_175 ? issue_slots_9_out_uop_fp_ctrl_swap12 : _T_174 ? issue_slots_8_out_uop_fp_ctrl_swap12 : issue_slots_7_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_ren3 = _T_175 ? issue_slots_9_out_uop_fp_ctrl_ren3 : _T_174 ? issue_slots_8_out_uop_fp_ctrl_ren3 : issue_slots_7_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_ren2 = _T_175 ? issue_slots_9_out_uop_fp_ctrl_ren2 : _T_174 ? issue_slots_8_out_uop_fp_ctrl_ren2 : issue_slots_7_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_ren1 = _T_175 ? issue_slots_9_out_uop_fp_ctrl_ren1 : _T_174 ? issue_slots_8_out_uop_fp_ctrl_ren1 : issue_slots_7_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_wen = _T_175 ? issue_slots_9_out_uop_fp_ctrl_wen : _T_174 ? issue_slots_8_out_uop_fp_ctrl_wen : issue_slots_7_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_ldst = _T_175 ? issue_slots_9_out_uop_fp_ctrl_ldst : _T_174 ? issue_slots_8_out_uop_fp_ctrl_ldst : issue_slots_7_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_op2_sel = _T_175 ? issue_slots_9_out_uop_op2_sel : _T_174 ? issue_slots_8_out_uop_op2_sel : issue_slots_7_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_op1_sel = _T_175 ? issue_slots_9_out_uop_op1_sel : _T_174 ? issue_slots_8_out_uop_op1_sel : issue_slots_7_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_imm_packed = _T_175 ? issue_slots_9_out_uop_imm_packed : _T_174 ? issue_slots_8_out_uop_imm_packed : issue_slots_7_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_pimm = _T_175 ? issue_slots_9_out_uop_pimm : _T_174 ? issue_slots_8_out_uop_pimm : issue_slots_7_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_imm_sel = _T_175 ? issue_slots_9_out_uop_imm_sel : _T_174 ? issue_slots_8_out_uop_imm_sel : issue_slots_7_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_imm_rename = _T_175 ? issue_slots_9_out_uop_imm_rename : _T_174 ? issue_slots_8_out_uop_imm_rename : issue_slots_7_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_taken = _T_175 ? issue_slots_9_out_uop_taken : _T_174 ? issue_slots_8_out_uop_taken : issue_slots_7_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_pc_lob = _T_175 ? issue_slots_9_out_uop_pc_lob : _T_174 ? issue_slots_8_out_uop_pc_lob : issue_slots_7_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_edge_inst = _T_175 ? issue_slots_9_out_uop_edge_inst : _T_174 ? issue_slots_8_out_uop_edge_inst : issue_slots_7_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ftq_idx = _T_175 ? issue_slots_9_out_uop_ftq_idx : _T_174 ? issue_slots_8_out_uop_ftq_idx : issue_slots_7_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_mov = _T_175 ? issue_slots_9_out_uop_is_mov : _T_174 ? issue_slots_8_out_uop_is_mov : issue_slots_7_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_rocc = _T_175 ? issue_slots_9_out_uop_is_rocc : _T_174 ? issue_slots_8_out_uop_is_rocc : issue_slots_7_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_sys_pc2epc = _T_175 ? issue_slots_9_out_uop_is_sys_pc2epc : _T_174 ? issue_slots_8_out_uop_is_sys_pc2epc : issue_slots_7_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_eret = _T_175 ? issue_slots_9_out_uop_is_eret : _T_174 ? issue_slots_8_out_uop_is_eret : issue_slots_7_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_amo = _T_175 ? issue_slots_9_out_uop_is_amo : _T_174 ? issue_slots_8_out_uop_is_amo : issue_slots_7_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_sfence = _T_175 ? issue_slots_9_out_uop_is_sfence : _T_174 ? issue_slots_8_out_uop_is_sfence : issue_slots_7_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_fencei = _T_175 ? issue_slots_9_out_uop_is_fencei : _T_174 ? issue_slots_8_out_uop_is_fencei : issue_slots_7_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_fence = _T_175 ? issue_slots_9_out_uop_is_fence : _T_174 ? issue_slots_8_out_uop_is_fence : issue_slots_7_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_sfb = _T_175 ? issue_slots_9_out_uop_is_sfb : _T_174 ? issue_slots_8_out_uop_is_sfb : issue_slots_7_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_br_type = _T_175 ? issue_slots_9_out_uop_br_type : _T_174 ? issue_slots_8_out_uop_br_type : issue_slots_7_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_br_tag = _T_175 ? issue_slots_9_out_uop_br_tag : _T_174 ? issue_slots_8_out_uop_br_tag : issue_slots_7_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_br_mask = _T_175 ? issue_slots_9_out_uop_br_mask : _T_174 ? issue_slots_8_out_uop_br_mask : issue_slots_7_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_dis_col_sel = _T_175 ? issue_slots_9_out_uop_dis_col_sel : _T_174 ? issue_slots_8_out_uop_dis_col_sel : issue_slots_7_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_p3_bypass_hint = _T_175 ? issue_slots_9_out_uop_iw_p3_bypass_hint : _T_174 ? issue_slots_8_out_uop_iw_p3_bypass_hint : issue_slots_7_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_p2_bypass_hint = _T_175 ? issue_slots_9_out_uop_iw_p2_bypass_hint : _T_174 ? issue_slots_8_out_uop_iw_p2_bypass_hint : issue_slots_7_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_p1_bypass_hint = _T_175 ? issue_slots_9_out_uop_iw_p1_bypass_hint : _T_174 ? issue_slots_8_out_uop_iw_p1_bypass_hint : issue_slots_7_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_issued = _T_175 ? issue_slots_9_out_uop_iw_issued : _T_174 ? issue_slots_8_out_uop_iw_issued : issue_slots_7_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_0 = _T_175 ? issue_slots_9_out_uop_fu_code_0 : _T_174 ? issue_slots_8_out_uop_fu_code_0 : issue_slots_7_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_1 = _T_175 ? issue_slots_9_out_uop_fu_code_1 : _T_174 ? issue_slots_8_out_uop_fu_code_1 : issue_slots_7_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_2 = _T_175 ? issue_slots_9_out_uop_fu_code_2 : _T_174 ? issue_slots_8_out_uop_fu_code_2 : issue_slots_7_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_3 = _T_175 ? issue_slots_9_out_uop_fu_code_3 : _T_174 ? issue_slots_8_out_uop_fu_code_3 : issue_slots_7_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_4 = _T_175 ? issue_slots_9_out_uop_fu_code_4 : _T_174 ? issue_slots_8_out_uop_fu_code_4 : issue_slots_7_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_5 = _T_175 ? issue_slots_9_out_uop_fu_code_5 : _T_174 ? issue_slots_8_out_uop_fu_code_5 : issue_slots_7_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_6 = _T_175 ? issue_slots_9_out_uop_fu_code_6 : _T_174 ? issue_slots_8_out_uop_fu_code_6 : issue_slots_7_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_7 = _T_175 ? issue_slots_9_out_uop_fu_code_7 : _T_174 ? issue_slots_8_out_uop_fu_code_7 : issue_slots_7_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_8 = _T_175 ? issue_slots_9_out_uop_fu_code_8 : _T_174 ? issue_slots_8_out_uop_fu_code_8 : issue_slots_7_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_9 = _T_175 ? issue_slots_9_out_uop_fu_code_9 : _T_174 ? issue_slots_8_out_uop_fu_code_9 : issue_slots_7_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iq_type_0 = _T_175 ? issue_slots_9_out_uop_iq_type_0 : _T_174 ? issue_slots_8_out_uop_iq_type_0 : issue_slots_7_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iq_type_1 = _T_175 ? issue_slots_9_out_uop_iq_type_1 : _T_174 ? issue_slots_8_out_uop_iq_type_1 : issue_slots_7_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iq_type_2 = _T_175 ? issue_slots_9_out_uop_iq_type_2 : _T_174 ? issue_slots_8_out_uop_iq_type_2 : issue_slots_7_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iq_type_3 = _T_175 ? issue_slots_9_out_uop_iq_type_3 : _T_174 ? issue_slots_8_out_uop_iq_type_3 : issue_slots_7_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_debug_pc = _T_175 ? issue_slots_9_out_uop_debug_pc : _T_174 ? issue_slots_8_out_uop_debug_pc : issue_slots_7_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_rvc = _T_175 ? issue_slots_9_out_uop_is_rvc : _T_174 ? issue_slots_8_out_uop_is_rvc : issue_slots_7_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_debug_inst = _T_175 ? issue_slots_9_out_uop_debug_inst : _T_174 ? issue_slots_8_out_uop_debug_inst : issue_slots_7_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_inst = _T_175 ? issue_slots_9_out_uop_inst : _T_174 ? issue_slots_8_out_uop_inst : issue_slots_7_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_6_clear_T = \|shamts_oh_6; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_6_clear = _issue_slots_6_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_177 = shamts_oh_9 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_178 = shamts_oh_10 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_7_in_uop_valid = _T_178 ? issue_slots_10_will_be_valid : _T_177 ? issue_slots_9_will_be_valid : shamts_oh_8 == 3'h1 & issue_slots_8_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_7_in_uop_bits_debug_tsrc = _T_178 ? issue_slots_10_out_uop_debug_tsrc : _T_177 ? issue_slots_9_out_uop_debug_tsrc : issue_slots_8_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_debug_fsrc = _T_178 ? issue_slots_10_out_uop_debug_fsrc : _T_177 ? issue_slots_9_out_uop_debug_fsrc : issue_slots_8_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_bp_xcpt_if = _T_178 ? issue_slots_10_out_uop_bp_xcpt_if : _T_177 ? issue_slots_9_out_uop_bp_xcpt_if : issue_slots_8_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_bp_debug_if = _T_178 ? issue_slots_10_out_uop_bp_debug_if : _T_177 ? issue_slots_9_out_uop_bp_debug_if : issue_slots_8_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_xcpt_ma_if = _T_178 ? issue_slots_10_out_uop_xcpt_ma_if : _T_177 ? issue_slots_9_out_uop_xcpt_ma_if : issue_slots_8_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_xcpt_ae_if = _T_178 ? issue_slots_10_out_uop_xcpt_ae_if : _T_177 ? issue_slots_9_out_uop_xcpt_ae_if : issue_slots_8_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_xcpt_pf_if = _T_178 ? issue_slots_10_out_uop_xcpt_pf_if : _T_177 ? issue_slots_9_out_uop_xcpt_pf_if : issue_slots_8_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_typ = _T_178 ? issue_slots_10_out_uop_fp_typ : _T_177 ? issue_slots_9_out_uop_fp_typ : issue_slots_8_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_rm = _T_178 ? issue_slots_10_out_uop_fp_rm : _T_177 ? issue_slots_9_out_uop_fp_rm : issue_slots_8_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_val = _T_178 ? issue_slots_10_out_uop_fp_val : _T_177 ? issue_slots_9_out_uop_fp_val : issue_slots_8_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fcn_op = _T_178 ? issue_slots_10_out_uop_fcn_op : _T_177 ? issue_slots_9_out_uop_fcn_op : issue_slots_8_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fcn_dw = _T_178 ? issue_slots_10_out_uop_fcn_dw : _T_177 ? issue_slots_9_out_uop_fcn_dw : issue_slots_8_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_frs3_en = _T_178 ? issue_slots_10_out_uop_frs3_en : _T_177 ? issue_slots_9_out_uop_frs3_en : issue_slots_8_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs2_rtype = _T_178 ? issue_slots_10_out_uop_lrs2_rtype : _T_177 ? issue_slots_9_out_uop_lrs2_rtype : issue_slots_8_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs1_rtype = _T_178 ? issue_slots_10_out_uop_lrs1_rtype : _T_177 ? issue_slots_9_out_uop_lrs1_rtype : issue_slots_8_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_dst_rtype = _T_178 ? issue_slots_10_out_uop_dst_rtype : _T_177 ? issue_slots_9_out_uop_dst_rtype : issue_slots_8_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs3 = _T_178 ? issue_slots_10_out_uop_lrs3 : _T_177 ? issue_slots_9_out_uop_lrs3 : issue_slots_8_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs2 = _T_178 ? issue_slots_10_out_uop_lrs2 : _T_177 ? issue_slots_9_out_uop_lrs2 : issue_slots_8_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs1 = _T_178 ? issue_slots_10_out_uop_lrs1 : _T_177 ? issue_slots_9_out_uop_lrs1 : issue_slots_8_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ldst = _T_178 ? issue_slots_10_out_uop_ldst : _T_177 ? issue_slots_9_out_uop_ldst : issue_slots_8_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ldst_is_rs1 = _T_178 ? issue_slots_10_out_uop_ldst_is_rs1 : _T_177 ? issue_slots_9_out_uop_ldst_is_rs1 : issue_slots_8_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_csr_cmd = _T_178 ? issue_slots_10_out_uop_csr_cmd : _T_177 ? issue_slots_9_out_uop_csr_cmd : issue_slots_8_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_flush_on_commit = _T_178 ? issue_slots_10_out_uop_flush_on_commit : _T_177 ? issue_slots_9_out_uop_flush_on_commit : issue_slots_8_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_unique = _T_178 ? issue_slots_10_out_uop_is_unique : _T_177 ? issue_slots_9_out_uop_is_unique : issue_slots_8_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_uses_stq = _T_178 ? issue_slots_10_out_uop_uses_stq : _T_177 ? issue_slots_9_out_uop_uses_stq : issue_slots_8_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_uses_ldq = _T_178 ? issue_slots_10_out_uop_uses_ldq : _T_177 ? issue_slots_9_out_uop_uses_ldq : issue_slots_8_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_mem_signed = _T_178 ? issue_slots_10_out_uop_mem_signed : _T_177 ? issue_slots_9_out_uop_mem_signed : issue_slots_8_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_mem_size = _T_178 ? issue_slots_10_out_uop_mem_size : _T_177 ? issue_slots_9_out_uop_mem_size : issue_slots_8_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_mem_cmd = _T_178 ? issue_slots_10_out_uop_mem_cmd : _T_177 ? issue_slots_9_out_uop_mem_cmd : issue_slots_8_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_exc_cause = _T_178 ? issue_slots_10_out_uop_exc_cause : _T_177 ? issue_slots_9_out_uop_exc_cause : issue_slots_8_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_exception = _T_178 ? issue_slots_10_out_uop_exception : _T_177 ? issue_slots_9_out_uop_exception : issue_slots_8_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_stale_pdst = _T_178 ? issue_slots_10_out_uop_stale_pdst : _T_177 ? issue_slots_9_out_uop_stale_pdst : issue_slots_8_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ppred_busy = _T_178 ? issue_slots_10_out_uop_ppred_busy : _T_177 ? issue_slots_9_out_uop_ppred_busy : issue_slots_8_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs3_busy = _T_178 ? issue_slots_10_out_uop_prs3_busy : _T_177 ? issue_slots_9_out_uop_prs3_busy : issue_slots_8_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs2_busy = _T_178 ? issue_slots_10_out_uop_prs2_busy : _T_177 ? issue_slots_9_out_uop_prs2_busy : issue_slots_8_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs1_busy = _T_178 ? issue_slots_10_out_uop_prs1_busy : _T_177 ? issue_slots_9_out_uop_prs1_busy : issue_slots_8_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ppred = _T_178 ? issue_slots_10_out_uop_ppred : _T_177 ? issue_slots_9_out_uop_ppred : issue_slots_8_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs3 = _T_178 ? issue_slots_10_out_uop_prs3 : _T_177 ? issue_slots_9_out_uop_prs3 : issue_slots_8_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs2 = _T_178 ? issue_slots_10_out_uop_prs2 : _T_177 ? issue_slots_9_out_uop_prs2 : issue_slots_8_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs1 = _T_178 ? issue_slots_10_out_uop_prs1 : _T_177 ? issue_slots_9_out_uop_prs1 : issue_slots_8_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_pdst = _T_178 ? issue_slots_10_out_uop_pdst : _T_177 ? issue_slots_9_out_uop_pdst : issue_slots_8_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_rxq_idx = _T_178 ? issue_slots_10_out_uop_rxq_idx : _T_177 ? issue_slots_9_out_uop_rxq_idx : issue_slots_8_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_stq_idx = _T_178 ? issue_slots_10_out_uop_stq_idx : _T_177 ? issue_slots_9_out_uop_stq_idx : issue_slots_8_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ldq_idx = _T_178 ? issue_slots_10_out_uop_ldq_idx : _T_177 ? issue_slots_9_out_uop_ldq_idx : issue_slots_8_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_rob_idx = _T_178 ? issue_slots_10_out_uop_rob_idx : _T_177 ? issue_slots_9_out_uop_rob_idx : issue_slots_8_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_vec = _T_178 ? issue_slots_10_out_uop_fp_ctrl_vec : _T_177 ? issue_slots_9_out_uop_fp_ctrl_vec : issue_slots_8_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_wflags = _T_178 ? issue_slots_10_out_uop_fp_ctrl_wflags : _T_177 ? issue_slots_9_out_uop_fp_ctrl_wflags : issue_slots_8_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_sqrt = _T_178 ? issue_slots_10_out_uop_fp_ctrl_sqrt : _T_177 ? issue_slots_9_out_uop_fp_ctrl_sqrt : issue_slots_8_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_div = _T_178 ? issue_slots_10_out_uop_fp_ctrl_div : _T_177 ? issue_slots_9_out_uop_fp_ctrl_div : issue_slots_8_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_fma = _T_178 ? issue_slots_10_out_uop_fp_ctrl_fma : _T_177 ? issue_slots_9_out_uop_fp_ctrl_fma : issue_slots_8_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_fastpipe = _T_178 ? issue_slots_10_out_uop_fp_ctrl_fastpipe : _T_177 ? issue_slots_9_out_uop_fp_ctrl_fastpipe : issue_slots_8_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_toint = _T_178 ? issue_slots_10_out_uop_fp_ctrl_toint : _T_177 ? issue_slots_9_out_uop_fp_ctrl_toint : issue_slots_8_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_fromint = _T_178 ? issue_slots_10_out_uop_fp_ctrl_fromint : _T_177 ? issue_slots_9_out_uop_fp_ctrl_fromint : issue_slots_8_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_typeTagOut = _T_178 ? issue_slots_10_out_uop_fp_ctrl_typeTagOut : _T_177 ? issue_slots_9_out_uop_fp_ctrl_typeTagOut : issue_slots_8_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_typeTagIn = _T_178 ? issue_slots_10_out_uop_fp_ctrl_typeTagIn : _T_177 ? issue_slots_9_out_uop_fp_ctrl_typeTagIn : issue_slots_8_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_swap23 = _T_178 ? issue_slots_10_out_uop_fp_ctrl_swap23 : _T_177 ? issue_slots_9_out_uop_fp_ctrl_swap23 : issue_slots_8_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_swap12 = _T_178 ? issue_slots_10_out_uop_fp_ctrl_swap12 : _T_177 ? issue_slots_9_out_uop_fp_ctrl_swap12 : issue_slots_8_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_ren3 = _T_178 ? issue_slots_10_out_uop_fp_ctrl_ren3 : _T_177 ? issue_slots_9_out_uop_fp_ctrl_ren3 : issue_slots_8_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_ren2 = _T_178 ? issue_slots_10_out_uop_fp_ctrl_ren2 : _T_177 ? issue_slots_9_out_uop_fp_ctrl_ren2 : issue_slots_8_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_ren1 = _T_178 ? issue_slots_10_out_uop_fp_ctrl_ren1 : _T_177 ? issue_slots_9_out_uop_fp_ctrl_ren1 : issue_slots_8_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_wen = _T_178 ? issue_slots_10_out_uop_fp_ctrl_wen : _T_177 ? issue_slots_9_out_uop_fp_ctrl_wen : issue_slots_8_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_ldst = _T_178 ? issue_slots_10_out_uop_fp_ctrl_ldst : _T_177 ? issue_slots_9_out_uop_fp_ctrl_ldst : issue_slots_8_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_op2_sel = _T_178 ? issue_slots_10_out_uop_op2_sel : _T_177 ? issue_slots_9_out_uop_op2_sel : issue_slots_8_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_op1_sel = _T_178 ? issue_slots_10_out_uop_op1_sel : _T_177 ? issue_slots_9_out_uop_op1_sel : issue_slots_8_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_imm_packed = _T_178 ? issue_slots_10_out_uop_imm_packed : _T_177 ? issue_slots_9_out_uop_imm_packed : issue_slots_8_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_pimm = _T_178 ? issue_slots_10_out_uop_pimm : _T_177 ? issue_slots_9_out_uop_pimm : issue_slots_8_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_imm_sel = _T_178 ? issue_slots_10_out_uop_imm_sel : _T_177 ? issue_slots_9_out_uop_imm_sel : issue_slots_8_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_imm_rename = _T_178 ? issue_slots_10_out_uop_imm_rename : _T_177 ? issue_slots_9_out_uop_imm_rename : issue_slots_8_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_taken = _T_178 ? issue_slots_10_out_uop_taken : _T_177 ? issue_slots_9_out_uop_taken : issue_slots_8_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_pc_lob = _T_178 ? issue_slots_10_out_uop_pc_lob : _T_177 ? issue_slots_9_out_uop_pc_lob : issue_slots_8_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_edge_inst = _T_178 ? issue_slots_10_out_uop_edge_inst : _T_177 ? issue_slots_9_out_uop_edge_inst : issue_slots_8_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ftq_idx = _T_178 ? issue_slots_10_out_uop_ftq_idx : _T_177 ? issue_slots_9_out_uop_ftq_idx : issue_slots_8_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_mov = _T_178 ? issue_slots_10_out_uop_is_mov : _T_177 ? issue_slots_9_out_uop_is_mov : issue_slots_8_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_rocc = _T_178 ? issue_slots_10_out_uop_is_rocc : _T_177 ? issue_slots_9_out_uop_is_rocc : issue_slots_8_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_sys_pc2epc = _T_178 ? issue_slots_10_out_uop_is_sys_pc2epc : _T_177 ? issue_slots_9_out_uop_is_sys_pc2epc : issue_slots_8_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_eret = _T_178 ? issue_slots_10_out_uop_is_eret : _T_177 ? issue_slots_9_out_uop_is_eret : issue_slots_8_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_amo = _T_178 ? issue_slots_10_out_uop_is_amo : _T_177 ? issue_slots_9_out_uop_is_amo : issue_slots_8_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_sfence = _T_178 ? issue_slots_10_out_uop_is_sfence : _T_177 ? issue_slots_9_out_uop_is_sfence : issue_slots_8_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_fencei = _T_178 ? issue_slots_10_out_uop_is_fencei : _T_177 ? issue_slots_9_out_uop_is_fencei : issue_slots_8_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_fence = _T_178 ? issue_slots_10_out_uop_is_fence : _T_177 ? issue_slots_9_out_uop_is_fence : issue_slots_8_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_sfb = _T_178 ? issue_slots_10_out_uop_is_sfb : _T_177 ? issue_slots_9_out_uop_is_sfb : issue_slots_8_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_br_type = _T_178 ? issue_slots_10_out_uop_br_type : _T_177 ? issue_slots_9_out_uop_br_type : issue_slots_8_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_br_tag = _T_178 ? issue_slots_10_out_uop_br_tag : _T_177 ? issue_slots_9_out_uop_br_tag : issue_slots_8_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_br_mask = _T_178 ? issue_slots_10_out_uop_br_mask : _T_177 ? issue_slots_9_out_uop_br_mask : issue_slots_8_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_dis_col_sel = _T_178 ? issue_slots_10_out_uop_dis_col_sel : _T_177 ? issue_slots_9_out_uop_dis_col_sel : issue_slots_8_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_p3_bypass_hint = _T_178 ? issue_slots_10_out_uop_iw_p3_bypass_hint : _T_177 ? issue_slots_9_out_uop_iw_p3_bypass_hint : issue_slots_8_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_p2_bypass_hint = _T_178 ? issue_slots_10_out_uop_iw_p2_bypass_hint : _T_177 ? issue_slots_9_out_uop_iw_p2_bypass_hint : issue_slots_8_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_p1_bypass_hint = _T_178 ? issue_slots_10_out_uop_iw_p1_bypass_hint : _T_177 ? issue_slots_9_out_uop_iw_p1_bypass_hint : issue_slots_8_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_issued = _T_178 ? issue_slots_10_out_uop_iw_issued : _T_177 ? issue_slots_9_out_uop_iw_issued : issue_slots_8_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_0 = _T_178 ? issue_slots_10_out_uop_fu_code_0 : _T_177 ? issue_slots_9_out_uop_fu_code_0 : issue_slots_8_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_1 = _T_178 ? issue_slots_10_out_uop_fu_code_1 : _T_177 ? issue_slots_9_out_uop_fu_code_1 : issue_slots_8_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_2 = _T_178 ? issue_slots_10_out_uop_fu_code_2 : _T_177 ? issue_slots_9_out_uop_fu_code_2 : issue_slots_8_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_3 = _T_178 ? issue_slots_10_out_uop_fu_code_3 : _T_177 ? issue_slots_9_out_uop_fu_code_3 : issue_slots_8_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_4 = _T_178 ? issue_slots_10_out_uop_fu_code_4 : _T_177 ? issue_slots_9_out_uop_fu_code_4 : issue_slots_8_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_5 = _T_178 ? issue_slots_10_out_uop_fu_code_5 : _T_177 ? issue_slots_9_out_uop_fu_code_5 : issue_slots_8_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_6 = _T_178 ? issue_slots_10_out_uop_fu_code_6 : _T_177 ? issue_slots_9_out_uop_fu_code_6 : issue_slots_8_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_7 = _T_178 ? issue_slots_10_out_uop_fu_code_7 : _T_177 ? issue_slots_9_out_uop_fu_code_7 : issue_slots_8_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_8 = _T_178 ? issue_slots_10_out_uop_fu_code_8 : _T_177 ? issue_slots_9_out_uop_fu_code_8 : issue_slots_8_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_9 = _T_178 ? issue_slots_10_out_uop_fu_code_9 : _T_177 ? issue_slots_9_out_uop_fu_code_9 : issue_slots_8_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iq_type_0 = _T_178 ? issue_slots_10_out_uop_iq_type_0 : _T_177 ? issue_slots_9_out_uop_iq_type_0 : issue_slots_8_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iq_type_1 = _T_178 ? issue_slots_10_out_uop_iq_type_1 : _T_177 ? issue_slots_9_out_uop_iq_type_1 : issue_slots_8_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iq_type_2 = _T_178 ? issue_slots_10_out_uop_iq_type_2 : _T_177 ? issue_slots_9_out_uop_iq_type_2 : issue_slots_8_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iq_type_3 = _T_178 ? issue_slots_10_out_uop_iq_type_3 : _T_177 ? issue_slots_9_out_uop_iq_type_3 : issue_slots_8_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_debug_pc = _T_178 ? issue_slots_10_out_uop_debug_pc : _T_177 ? issue_slots_9_out_uop_debug_pc : issue_slots_8_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_rvc = _T_178 ? issue_slots_10_out_uop_is_rvc : _T_177 ? issue_slots_9_out_uop_is_rvc : issue_slots_8_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_debug_inst = _T_178 ? issue_slots_10_out_uop_debug_inst : _T_177 ? issue_slots_9_out_uop_debug_inst : issue_slots_8_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_inst = _T_178 ? issue_slots_10_out_uop_inst : _T_177 ? issue_slots_9_out_uop_inst : issue_slots_8_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_7_clear_T = \|shamts_oh_7; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_7_clear = _issue_slots_7_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_180 = shamts_oh_10 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_181 = shamts_oh_11 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_8_in_uop_valid = _T_181 ? issue_slots_11_will_be_valid : _T_180 ? issue_slots_10_will_be_valid : shamts_oh_9 == 3'h1 & issue_slots_9_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_8_in_uop_bits_debug_tsrc = _T_181 ? issue_slots_11_out_uop_debug_tsrc : _T_180 ? issue_slots_10_out_uop_debug_tsrc : issue_slots_9_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_debug_fsrc = _T_181 ? issue_slots_11_out_uop_debug_fsrc : _T_180 ? issue_slots_10_out_uop_debug_fsrc : issue_slots_9_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_bp_xcpt_if = _T_181 ? issue_slots_11_out_uop_bp_xcpt_if : _T_180 ? issue_slots_10_out_uop_bp_xcpt_if : issue_slots_9_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_bp_debug_if = _T_181 ? issue_slots_11_out_uop_bp_debug_if : _T_180 ? issue_slots_10_out_uop_bp_debug_if : issue_slots_9_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_xcpt_ma_if = _T_181 ? issue_slots_11_out_uop_xcpt_ma_if : _T_180 ? issue_slots_10_out_uop_xcpt_ma_if : issue_slots_9_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_xcpt_ae_if = _T_181 ? issue_slots_11_out_uop_xcpt_ae_if : _T_180 ? issue_slots_10_out_uop_xcpt_ae_if : issue_slots_9_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_xcpt_pf_if = _T_181 ? issue_slots_11_out_uop_xcpt_pf_if : _T_180 ? issue_slots_10_out_uop_xcpt_pf_if : issue_slots_9_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_typ = _T_181 ? issue_slots_11_out_uop_fp_typ : _T_180 ? issue_slots_10_out_uop_fp_typ : issue_slots_9_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_rm = _T_181 ? issue_slots_11_out_uop_fp_rm : _T_180 ? issue_slots_10_out_uop_fp_rm : issue_slots_9_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_val = _T_181 ? issue_slots_11_out_uop_fp_val : _T_180 ? issue_slots_10_out_uop_fp_val : issue_slots_9_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fcn_op = _T_181 ? issue_slots_11_out_uop_fcn_op : _T_180 ? issue_slots_10_out_uop_fcn_op : issue_slots_9_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fcn_dw = _T_181 ? issue_slots_11_out_uop_fcn_dw : _T_180 ? issue_slots_10_out_uop_fcn_dw : issue_slots_9_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_frs3_en = _T_181 ? issue_slots_11_out_uop_frs3_en : _T_180 ? issue_slots_10_out_uop_frs3_en : issue_slots_9_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs2_rtype = _T_181 ? issue_slots_11_out_uop_lrs2_rtype : _T_180 ? issue_slots_10_out_uop_lrs2_rtype : issue_slots_9_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs1_rtype = _T_181 ? issue_slots_11_out_uop_lrs1_rtype : _T_180 ? issue_slots_10_out_uop_lrs1_rtype : issue_slots_9_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_dst_rtype = _T_181 ? issue_slots_11_out_uop_dst_rtype : _T_180 ? issue_slots_10_out_uop_dst_rtype : issue_slots_9_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs3 = _T_181 ? issue_slots_11_out_uop_lrs3 : _T_180 ? issue_slots_10_out_uop_lrs3 : issue_slots_9_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs2 = _T_181 ? issue_slots_11_out_uop_lrs2 : _T_180 ? issue_slots_10_out_uop_lrs2 : issue_slots_9_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs1 = _T_181 ? issue_slots_11_out_uop_lrs1 : _T_180 ? issue_slots_10_out_uop_lrs1 : issue_slots_9_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ldst = _T_181 ? issue_slots_11_out_uop_ldst : _T_180 ? issue_slots_10_out_uop_ldst : issue_slots_9_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ldst_is_rs1 = _T_181 ? issue_slots_11_out_uop_ldst_is_rs1 : _T_180 ? issue_slots_10_out_uop_ldst_is_rs1 : issue_slots_9_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_csr_cmd = _T_181 ? issue_slots_11_out_uop_csr_cmd : _T_180 ? issue_slots_10_out_uop_csr_cmd : issue_slots_9_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_flush_on_commit = _T_181 ? issue_slots_11_out_uop_flush_on_commit : _T_180 ? issue_slots_10_out_uop_flush_on_commit : issue_slots_9_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_unique = _T_181 ? issue_slots_11_out_uop_is_unique : _T_180 ? issue_slots_10_out_uop_is_unique : issue_slots_9_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_uses_stq = _T_181 ? issue_slots_11_out_uop_uses_stq : _T_180 ? issue_slots_10_out_uop_uses_stq : issue_slots_9_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_uses_ldq = _T_181 ? issue_slots_11_out_uop_uses_ldq : _T_180 ? issue_slots_10_out_uop_uses_ldq : issue_slots_9_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_mem_signed = _T_181 ? issue_slots_11_out_uop_mem_signed : _T_180 ? issue_slots_10_out_uop_mem_signed : issue_slots_9_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_mem_size = _T_181 ? issue_slots_11_out_uop_mem_size : _T_180 ? issue_slots_10_out_uop_mem_size : issue_slots_9_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_mem_cmd = _T_181 ? issue_slots_11_out_uop_mem_cmd : _T_180 ? issue_slots_10_out_uop_mem_cmd : issue_slots_9_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_exc_cause = _T_181 ? issue_slots_11_out_uop_exc_cause : _T_180 ? issue_slots_10_out_uop_exc_cause : issue_slots_9_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_exception = _T_181 ? issue_slots_11_out_uop_exception : _T_180 ? issue_slots_10_out_uop_exception : issue_slots_9_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_stale_pdst = _T_181 ? issue_slots_11_out_uop_stale_pdst : _T_180 ? issue_slots_10_out_uop_stale_pdst : issue_slots_9_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ppred_busy = _T_181 ? issue_slots_11_out_uop_ppred_busy : _T_180 ? issue_slots_10_out_uop_ppred_busy : issue_slots_9_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs3_busy = _T_181 ? issue_slots_11_out_uop_prs3_busy : _T_180 ? issue_slots_10_out_uop_prs3_busy : issue_slots_9_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs2_busy = _T_181 ? issue_slots_11_out_uop_prs2_busy : _T_180 ? issue_slots_10_out_uop_prs2_busy : issue_slots_9_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs1_busy = _T_181 ? issue_slots_11_out_uop_prs1_busy : _T_180 ? issue_slots_10_out_uop_prs1_busy : issue_slots_9_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ppred = _T_181 ? issue_slots_11_out_uop_ppred : _T_180 ? issue_slots_10_out_uop_ppred : issue_slots_9_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs3 = _T_181 ? issue_slots_11_out_uop_prs3 : _T_180 ? issue_slots_10_out_uop_prs3 : issue_slots_9_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs2 = _T_181 ? issue_slots_11_out_uop_prs2 : _T_180 ? issue_slots_10_out_uop_prs2 : issue_slots_9_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs1 = _T_181 ? issue_slots_11_out_uop_prs1 : _T_180 ? issue_slots_10_out_uop_prs1 : issue_slots_9_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_pdst = _T_181 ? issue_slots_11_out_uop_pdst : _T_180 ? issue_slots_10_out_uop_pdst : issue_slots_9_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_rxq_idx = _T_181 ? issue_slots_11_out_uop_rxq_idx : _T_180 ? issue_slots_10_out_uop_rxq_idx : issue_slots_9_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_stq_idx = _T_181 ? issue_slots_11_out_uop_stq_idx : _T_180 ? issue_slots_10_out_uop_stq_idx : issue_slots_9_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ldq_idx = _T_181 ? issue_slots_11_out_uop_ldq_idx : _T_180 ? issue_slots_10_out_uop_ldq_idx : issue_slots_9_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_rob_idx = _T_181 ? issue_slots_11_out_uop_rob_idx : _T_180 ? issue_slots_10_out_uop_rob_idx : issue_slots_9_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_vec = _T_181 ? issue_slots_11_out_uop_fp_ctrl_vec : _T_180 ? issue_slots_10_out_uop_fp_ctrl_vec : issue_slots_9_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_wflags = _T_181 ? issue_slots_11_out_uop_fp_ctrl_wflags : _T_180 ? issue_slots_10_out_uop_fp_ctrl_wflags : issue_slots_9_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_sqrt = _T_181 ? issue_slots_11_out_uop_fp_ctrl_sqrt : _T_180 ? issue_slots_10_out_uop_fp_ctrl_sqrt : issue_slots_9_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_div = _T_181 ? issue_slots_11_out_uop_fp_ctrl_div : _T_180 ? issue_slots_10_out_uop_fp_ctrl_div : issue_slots_9_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_fma = _T_181 ? issue_slots_11_out_uop_fp_ctrl_fma : _T_180 ? issue_slots_10_out_uop_fp_ctrl_fma : issue_slots_9_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_fastpipe = _T_181 ? issue_slots_11_out_uop_fp_ctrl_fastpipe : _T_180 ? issue_slots_10_out_uop_fp_ctrl_fastpipe : issue_slots_9_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_toint = _T_181 ? issue_slots_11_out_uop_fp_ctrl_toint : _T_180 ? issue_slots_10_out_uop_fp_ctrl_toint : issue_slots_9_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_fromint = _T_181 ? issue_slots_11_out_uop_fp_ctrl_fromint : _T_180 ? issue_slots_10_out_uop_fp_ctrl_fromint : issue_slots_9_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_typeTagOut = _T_181 ? issue_slots_11_out_uop_fp_ctrl_typeTagOut : _T_180 ? issue_slots_10_out_uop_fp_ctrl_typeTagOut : issue_slots_9_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_typeTagIn = _T_181 ? issue_slots_11_out_uop_fp_ctrl_typeTagIn : _T_180 ? issue_slots_10_out_uop_fp_ctrl_typeTagIn : issue_slots_9_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_swap23 = _T_181 ? issue_slots_11_out_uop_fp_ctrl_swap23 : _T_180 ? issue_slots_10_out_uop_fp_ctrl_swap23 : issue_slots_9_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_swap12 = _T_181 ? issue_slots_11_out_uop_fp_ctrl_swap12 : _T_180 ? issue_slots_10_out_uop_fp_ctrl_swap12 : issue_slots_9_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_ren3 = _T_181 ? issue_slots_11_out_uop_fp_ctrl_ren3 : _T_180 ? issue_slots_10_out_uop_fp_ctrl_ren3 : issue_slots_9_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_ren2 = _T_181 ? issue_slots_11_out_uop_fp_ctrl_ren2 : _T_180 ? issue_slots_10_out_uop_fp_ctrl_ren2 : issue_slots_9_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_ren1 = _T_181 ? issue_slots_11_out_uop_fp_ctrl_ren1 : _T_180 ? issue_slots_10_out_uop_fp_ctrl_ren1 : issue_slots_9_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_wen = _T_181 ? issue_slots_11_out_uop_fp_ctrl_wen : _T_180 ? issue_slots_10_out_uop_fp_ctrl_wen : issue_slots_9_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_ldst = _T_181 ? issue_slots_11_out_uop_fp_ctrl_ldst : _T_180 ? issue_slots_10_out_uop_fp_ctrl_ldst : issue_slots_9_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_op2_sel = _T_181 ? issue_slots_11_out_uop_op2_sel : _T_180 ? issue_slots_10_out_uop_op2_sel : issue_slots_9_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_op1_sel = _T_181 ? issue_slots_11_out_uop_op1_sel : _T_180 ? issue_slots_10_out_uop_op1_sel : issue_slots_9_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_imm_packed = _T_181 ? issue_slots_11_out_uop_imm_packed : _T_180 ? issue_slots_10_out_uop_imm_packed : issue_slots_9_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_pimm = _T_181 ? issue_slots_11_out_uop_pimm : _T_180 ? issue_slots_10_out_uop_pimm : issue_slots_9_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_imm_sel = _T_181 ? issue_slots_11_out_uop_imm_sel : _T_180 ? issue_slots_10_out_uop_imm_sel : issue_slots_9_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_imm_rename = _T_181 ? issue_slots_11_out_uop_imm_rename : _T_180 ? issue_slots_10_out_uop_imm_rename : issue_slots_9_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_taken = _T_181 ? issue_slots_11_out_uop_taken : _T_180 ? issue_slots_10_out_uop_taken : issue_slots_9_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_pc_lob = _T_181 ? issue_slots_11_out_uop_pc_lob : _T_180 ? issue_slots_10_out_uop_pc_lob : issue_slots_9_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_edge_inst = _T_181 ? issue_slots_11_out_uop_edge_inst : _T_180 ? issue_slots_10_out_uop_edge_inst : issue_slots_9_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ftq_idx = _T_181 ? issue_slots_11_out_uop_ftq_idx : _T_180 ? issue_slots_10_out_uop_ftq_idx : issue_slots_9_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_mov = _T_181 ? issue_slots_11_out_uop_is_mov : _T_180 ? issue_slots_10_out_uop_is_mov : issue_slots_9_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_rocc = _T_181 ? issue_slots_11_out_uop_is_rocc : _T_180 ? issue_slots_10_out_uop_is_rocc : issue_slots_9_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_sys_pc2epc = _T_181 ? issue_slots_11_out_uop_is_sys_pc2epc : _T_180 ? issue_slots_10_out_uop_is_sys_pc2epc : issue_slots_9_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_eret = _T_181 ? issue_slots_11_out_uop_is_eret : _T_180 ? issue_slots_10_out_uop_is_eret : issue_slots_9_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_amo = _T_181 ? issue_slots_11_out_uop_is_amo : _T_180 ? issue_slots_10_out_uop_is_amo : issue_slots_9_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_sfence = _T_181 ? issue_slots_11_out_uop_is_sfence : _T_180 ? issue_slots_10_out_uop_is_sfence : issue_slots_9_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_fencei = _T_181 ? issue_slots_11_out_uop_is_fencei : _T_180 ? issue_slots_10_out_uop_is_fencei : issue_slots_9_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_fence = _T_181 ? issue_slots_11_out_uop_is_fence : _T_180 ? issue_slots_10_out_uop_is_fence : issue_slots_9_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_sfb = _T_181 ? issue_slots_11_out_uop_is_sfb : _T_180 ? issue_slots_10_out_uop_is_sfb : issue_slots_9_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_br_type = _T_181 ? issue_slots_11_out_uop_br_type : _T_180 ? issue_slots_10_out_uop_br_type : issue_slots_9_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_br_tag = _T_181 ? issue_slots_11_out_uop_br_tag : _T_180 ? issue_slots_10_out_uop_br_tag : issue_slots_9_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_br_mask = _T_181 ? issue_slots_11_out_uop_br_mask : _T_180 ? issue_slots_10_out_uop_br_mask : issue_slots_9_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_dis_col_sel = _T_181 ? issue_slots_11_out_uop_dis_col_sel : _T_180 ? issue_slots_10_out_uop_dis_col_sel : issue_slots_9_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_p3_bypass_hint = _T_181 ? issue_slots_11_out_uop_iw_p3_bypass_hint : _T_180 ? issue_slots_10_out_uop_iw_p3_bypass_hint : issue_slots_9_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_p2_bypass_hint = _T_181 ? issue_slots_11_out_uop_iw_p2_bypass_hint : _T_180 ? issue_slots_10_out_uop_iw_p2_bypass_hint : issue_slots_9_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_p1_bypass_hint = _T_181 ? issue_slots_11_out_uop_iw_p1_bypass_hint : _T_180 ? issue_slots_10_out_uop_iw_p1_bypass_hint : issue_slots_9_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_issued = _T_181 ? issue_slots_11_out_uop_iw_issued : _T_180 ? issue_slots_10_out_uop_iw_issued : issue_slots_9_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_0 = _T_181 ? issue_slots_11_out_uop_fu_code_0 : _T_180 ? issue_slots_10_out_uop_fu_code_0 : issue_slots_9_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_1 = _T_181 ? issue_slots_11_out_uop_fu_code_1 : _T_180 ? issue_slots_10_out_uop_fu_code_1 : issue_slots_9_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_2 = _T_181 ? issue_slots_11_out_uop_fu_code_2 : _T_180 ? issue_slots_10_out_uop_fu_code_2 : issue_slots_9_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_3 = _T_181 ? issue_slots_11_out_uop_fu_code_3 : _T_180 ? issue_slots_10_out_uop_fu_code_3 : issue_slots_9_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_4 = _T_181 ? issue_slots_11_out_uop_fu_code_4 : _T_180 ? issue_slots_10_out_uop_fu_code_4 : issue_slots_9_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_5 = _T_181 ? issue_slots_11_out_uop_fu_code_5 : _T_180 ? issue_slots_10_out_uop_fu_code_5 : issue_slots_9_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_6 = _T_181 ? issue_slots_11_out_uop_fu_code_6 : _T_180 ? issue_slots_10_out_uop_fu_code_6 : issue_slots_9_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_7 = _T_181 ? issue_slots_11_out_uop_fu_code_7 : _T_180 ? issue_slots_10_out_uop_fu_code_7 : issue_slots_9_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_8 = _T_181 ? issue_slots_11_out_uop_fu_code_8 : _T_180 ? issue_slots_10_out_uop_fu_code_8 : issue_slots_9_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_9 = _T_181 ? issue_slots_11_out_uop_fu_code_9 : _T_180 ? issue_slots_10_out_uop_fu_code_9 : issue_slots_9_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iq_type_0 = _T_181 ? issue_slots_11_out_uop_iq_type_0 : _T_180 ? issue_slots_10_out_uop_iq_type_0 : issue_slots_9_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iq_type_1 = _T_181 ? issue_slots_11_out_uop_iq_type_1 : _T_180 ? issue_slots_10_out_uop_iq_type_1 : issue_slots_9_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iq_type_2 = _T_181 ? issue_slots_11_out_uop_iq_type_2 : _T_180 ? issue_slots_10_out_uop_iq_type_2 : issue_slots_9_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iq_type_3 = _T_181 ? issue_slots_11_out_uop_iq_type_3 : _T_180 ? issue_slots_10_out_uop_iq_type_3 : issue_slots_9_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_debug_pc = _T_181 ? issue_slots_11_out_uop_debug_pc : _T_180 ? issue_slots_10_out_uop_debug_pc : issue_slots_9_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_rvc = _T_181 ? issue_slots_11_out_uop_is_rvc : _T_180 ? issue_slots_10_out_uop_is_rvc : issue_slots_9_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_debug_inst = _T_181 ? issue_slots_11_out_uop_debug_inst : _T_180 ? issue_slots_10_out_uop_debug_inst : issue_slots_9_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_inst = _T_181 ? issue_slots_11_out_uop_inst : _T_180 ? issue_slots_10_out_uop_inst : issue_slots_9_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_8_clear_T = \|shamts_oh_8; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_8_clear = _issue_slots_8_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_183 = shamts_oh_11 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_184 = shamts_oh_12 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_9_in_uop_valid = _T_184 ? issue_slots_12_will_be_valid : _T_183 ? issue_slots_11_will_be_valid : shamts_oh_10 == 3'h1 & issue_slots_10_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_9_in_uop_bits_debug_tsrc = _T_184 ? issue_slots_12_out_uop_debug_tsrc : _T_183 ? issue_slots_11_out_uop_debug_tsrc : issue_slots_10_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_debug_fsrc = _T_184 ? issue_slots_12_out_uop_debug_fsrc : _T_183 ? issue_slots_11_out_uop_debug_fsrc : issue_slots_10_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_bp_xcpt_if = _T_184 ? issue_slots_12_out_uop_bp_xcpt_if : _T_183 ? issue_slots_11_out_uop_bp_xcpt_if : issue_slots_10_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_bp_debug_if = _T_184 ? issue_slots_12_out_uop_bp_debug_if : _T_183 ? issue_slots_11_out_uop_bp_debug_if : issue_slots_10_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_xcpt_ma_if = _T_184 ? issue_slots_12_out_uop_xcpt_ma_if : _T_183 ? issue_slots_11_out_uop_xcpt_ma_if : issue_slots_10_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_xcpt_ae_if = _T_184 ? issue_slots_12_out_uop_xcpt_ae_if : _T_183 ? issue_slots_11_out_uop_xcpt_ae_if : issue_slots_10_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_xcpt_pf_if = _T_184 ? issue_slots_12_out_uop_xcpt_pf_if : _T_183 ? issue_slots_11_out_uop_xcpt_pf_if : issue_slots_10_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_typ = _T_184 ? issue_slots_12_out_uop_fp_typ : _T_183 ? issue_slots_11_out_uop_fp_typ : issue_slots_10_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_rm = _T_184 ? issue_slots_12_out_uop_fp_rm : _T_183 ? issue_slots_11_out_uop_fp_rm : issue_slots_10_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_val = _T_184 ? issue_slots_12_out_uop_fp_val : _T_183 ? issue_slots_11_out_uop_fp_val : issue_slots_10_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fcn_op = _T_184 ? issue_slots_12_out_uop_fcn_op : _T_183 ? issue_slots_11_out_uop_fcn_op : issue_slots_10_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fcn_dw = _T_184 ? issue_slots_12_out_uop_fcn_dw : _T_183 ? issue_slots_11_out_uop_fcn_dw : issue_slots_10_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_frs3_en = _T_184 ? issue_slots_12_out_uop_frs3_en : _T_183 ? issue_slots_11_out_uop_frs3_en : issue_slots_10_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs2_rtype = _T_184 ? issue_slots_12_out_uop_lrs2_rtype : _T_183 ? issue_slots_11_out_uop_lrs2_rtype : issue_slots_10_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs1_rtype = _T_184 ? issue_slots_12_out_uop_lrs1_rtype : _T_183 ? issue_slots_11_out_uop_lrs1_rtype : issue_slots_10_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_dst_rtype = _T_184 ? issue_slots_12_out_uop_dst_rtype : _T_183 ? issue_slots_11_out_uop_dst_rtype : issue_slots_10_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs3 = _T_184 ? issue_slots_12_out_uop_lrs3 : _T_183 ? issue_slots_11_out_uop_lrs3 : issue_slots_10_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs2 = _T_184 ? issue_slots_12_out_uop_lrs2 : _T_183 ? issue_slots_11_out_uop_lrs2 : issue_slots_10_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs1 = _T_184 ? issue_slots_12_out_uop_lrs1 : _T_183 ? issue_slots_11_out_uop_lrs1 : issue_slots_10_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ldst = _T_184 ? issue_slots_12_out_uop_ldst : _T_183 ? issue_slots_11_out_uop_ldst : issue_slots_10_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ldst_is_rs1 = _T_184 ? issue_slots_12_out_uop_ldst_is_rs1 : _T_183 ? issue_slots_11_out_uop_ldst_is_rs1 : issue_slots_10_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_csr_cmd = _T_184 ? issue_slots_12_out_uop_csr_cmd : _T_183 ? issue_slots_11_out_uop_csr_cmd : issue_slots_10_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_flush_on_commit = _T_184 ? issue_slots_12_out_uop_flush_on_commit : _T_183 ? issue_slots_11_out_uop_flush_on_commit : issue_slots_10_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_unique = _T_184 ? issue_slots_12_out_uop_is_unique : _T_183 ? issue_slots_11_out_uop_is_unique : issue_slots_10_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_uses_stq = _T_184 ? issue_slots_12_out_uop_uses_stq : _T_183 ? issue_slots_11_out_uop_uses_stq : issue_slots_10_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_uses_ldq = _T_184 ? issue_slots_12_out_uop_uses_ldq : _T_183 ? issue_slots_11_out_uop_uses_ldq : issue_slots_10_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_mem_signed = _T_184 ? issue_slots_12_out_uop_mem_signed : _T_183 ? issue_slots_11_out_uop_mem_signed : issue_slots_10_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_mem_size = _T_184 ? issue_slots_12_out_uop_mem_size : _T_183 ? issue_slots_11_out_uop_mem_size : issue_slots_10_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_mem_cmd = _T_184 ? issue_slots_12_out_uop_mem_cmd : _T_183 ? issue_slots_11_out_uop_mem_cmd : issue_slots_10_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_exc_cause = _T_184 ? issue_slots_12_out_uop_exc_cause : _T_183 ? issue_slots_11_out_uop_exc_cause : issue_slots_10_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_exception = _T_184 ? issue_slots_12_out_uop_exception : _T_183 ? issue_slots_11_out_uop_exception : issue_slots_10_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_stale_pdst = _T_184 ? issue_slots_12_out_uop_stale_pdst : _T_183 ? issue_slots_11_out_uop_stale_pdst : issue_slots_10_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ppred_busy = _T_184 ? issue_slots_12_out_uop_ppred_busy : _T_183 ? issue_slots_11_out_uop_ppred_busy : issue_slots_10_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs3_busy = _T_184 ? issue_slots_12_out_uop_prs3_busy : _T_183 ? issue_slots_11_out_uop_prs3_busy : issue_slots_10_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs2_busy = _T_184 ? issue_slots_12_out_uop_prs2_busy : _T_183 ? issue_slots_11_out_uop_prs2_busy : issue_slots_10_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs1_busy = _T_184 ? issue_slots_12_out_uop_prs1_busy : _T_183 ? issue_slots_11_out_uop_prs1_busy : issue_slots_10_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ppred = _T_184 ? issue_slots_12_out_uop_ppred : _T_183 ? issue_slots_11_out_uop_ppred : issue_slots_10_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs3 = _T_184 ? issue_slots_12_out_uop_prs3 : _T_183 ? issue_slots_11_out_uop_prs3 : issue_slots_10_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs2 = _T_184 ? issue_slots_12_out_uop_prs2 : _T_183 ? issue_slots_11_out_uop_prs2 : issue_slots_10_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs1 = _T_184 ? issue_slots_12_out_uop_prs1 : _T_183 ? issue_slots_11_out_uop_prs1 : issue_slots_10_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_pdst = _T_184 ? issue_slots_12_out_uop_pdst : _T_183 ? issue_slots_11_out_uop_pdst : issue_slots_10_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_rxq_idx = _T_184 ? issue_slots_12_out_uop_rxq_idx : _T_183 ? issue_slots_11_out_uop_rxq_idx : issue_slots_10_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_stq_idx = _T_184 ? issue_slots_12_out_uop_stq_idx : _T_183 ? issue_slots_11_out_uop_stq_idx : issue_slots_10_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ldq_idx = _T_184 ? issue_slots_12_out_uop_ldq_idx : _T_183 ? issue_slots_11_out_uop_ldq_idx : issue_slots_10_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_rob_idx = _T_184 ? issue_slots_12_out_uop_rob_idx : _T_183 ? issue_slots_11_out_uop_rob_idx : issue_slots_10_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_vec = _T_184 ? issue_slots_12_out_uop_fp_ctrl_vec : _T_183 ? issue_slots_11_out_uop_fp_ctrl_vec : issue_slots_10_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_wflags = _T_184 ? issue_slots_12_out_uop_fp_ctrl_wflags : _T_183 ? issue_slots_11_out_uop_fp_ctrl_wflags : issue_slots_10_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_sqrt = _T_184 ? issue_slots_12_out_uop_fp_ctrl_sqrt : _T_183 ? issue_slots_11_out_uop_fp_ctrl_sqrt : issue_slots_10_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_div = _T_184 ? issue_slots_12_out_uop_fp_ctrl_div : _T_183 ? issue_slots_11_out_uop_fp_ctrl_div : issue_slots_10_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_fma = _T_184 ? issue_slots_12_out_uop_fp_ctrl_fma : _T_183 ? issue_slots_11_out_uop_fp_ctrl_fma : issue_slots_10_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_fastpipe = _T_184 ? issue_slots_12_out_uop_fp_ctrl_fastpipe : _T_183 ? issue_slots_11_out_uop_fp_ctrl_fastpipe : issue_slots_10_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_toint = _T_184 ? issue_slots_12_out_uop_fp_ctrl_toint : _T_183 ? issue_slots_11_out_uop_fp_ctrl_toint : issue_slots_10_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_fromint = _T_184 ? issue_slots_12_out_uop_fp_ctrl_fromint : _T_183 ? issue_slots_11_out_uop_fp_ctrl_fromint : issue_slots_10_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_typeTagOut = _T_184 ? issue_slots_12_out_uop_fp_ctrl_typeTagOut : _T_183 ? issue_slots_11_out_uop_fp_ctrl_typeTagOut : issue_slots_10_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_typeTagIn = _T_184 ? issue_slots_12_out_uop_fp_ctrl_typeTagIn : _T_183 ? issue_slots_11_out_uop_fp_ctrl_typeTagIn : issue_slots_10_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_swap23 = _T_184 ? issue_slots_12_out_uop_fp_ctrl_swap23 : _T_183 ? issue_slots_11_out_uop_fp_ctrl_swap23 : issue_slots_10_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_swap12 = _T_184 ? issue_slots_12_out_uop_fp_ctrl_swap12 : _T_183 ? issue_slots_11_out_uop_fp_ctrl_swap12 : issue_slots_10_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_ren3 = _T_184 ? issue_slots_12_out_uop_fp_ctrl_ren3 : _T_183 ? issue_slots_11_out_uop_fp_ctrl_ren3 : issue_slots_10_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_ren2 = _T_184 ? issue_slots_12_out_uop_fp_ctrl_ren2 : _T_183 ? issue_slots_11_out_uop_fp_ctrl_ren2 : issue_slots_10_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_ren1 = _T_184 ? issue_slots_12_out_uop_fp_ctrl_ren1 : _T_183 ? issue_slots_11_out_uop_fp_ctrl_ren1 : issue_slots_10_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_wen = _T_184 ? issue_slots_12_out_uop_fp_ctrl_wen : _T_183 ? issue_slots_11_out_uop_fp_ctrl_wen : issue_slots_10_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_ldst = _T_184 ? issue_slots_12_out_uop_fp_ctrl_ldst : _T_183 ? issue_slots_11_out_uop_fp_ctrl_ldst : issue_slots_10_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_op2_sel = _T_184 ? issue_slots_12_out_uop_op2_sel : _T_183 ? issue_slots_11_out_uop_op2_sel : issue_slots_10_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_op1_sel = _T_184 ? issue_slots_12_out_uop_op1_sel : _T_183 ? issue_slots_11_out_uop_op1_sel : issue_slots_10_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_imm_packed = _T_184 ? issue_slots_12_out_uop_imm_packed : _T_183 ? issue_slots_11_out_uop_imm_packed : issue_slots_10_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_pimm = _T_184 ? issue_slots_12_out_uop_pimm : _T_183 ? issue_slots_11_out_uop_pimm : issue_slots_10_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_imm_sel = _T_184 ? issue_slots_12_out_uop_imm_sel : _T_183 ? issue_slots_11_out_uop_imm_sel : issue_slots_10_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_imm_rename = _T_184 ? issue_slots_12_out_uop_imm_rename : _T_183 ? issue_slots_11_out_uop_imm_rename : issue_slots_10_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_taken = _T_184 ? issue_slots_12_out_uop_taken : _T_183 ? issue_slots_11_out_uop_taken : issue_slots_10_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_pc_lob = _T_184 ? issue_slots_12_out_uop_pc_lob : _T_183 ? issue_slots_11_out_uop_pc_lob : issue_slots_10_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_edge_inst = _T_184 ? issue_slots_12_out_uop_edge_inst : _T_183 ? issue_slots_11_out_uop_edge_inst : issue_slots_10_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ftq_idx = _T_184 ? issue_slots_12_out_uop_ftq_idx : _T_183 ? issue_slots_11_out_uop_ftq_idx : issue_slots_10_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_mov = _T_184 ? issue_slots_12_out_uop_is_mov : _T_183 ? issue_slots_11_out_uop_is_mov : issue_slots_10_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_rocc = _T_184 ? issue_slots_12_out_uop_is_rocc : _T_183 ? issue_slots_11_out_uop_is_rocc : issue_slots_10_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_sys_pc2epc = _T_184 ? issue_slots_12_out_uop_is_sys_pc2epc : _T_183 ? issue_slots_11_out_uop_is_sys_pc2epc : issue_slots_10_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_eret = _T_184 ? issue_slots_12_out_uop_is_eret : _T_183 ? issue_slots_11_out_uop_is_eret : issue_slots_10_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_amo = _T_184 ? issue_slots_12_out_uop_is_amo : _T_183 ? issue_slots_11_out_uop_is_amo : issue_slots_10_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_sfence = _T_184 ? issue_slots_12_out_uop_is_sfence : _T_183 ? issue_slots_11_out_uop_is_sfence : issue_slots_10_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_fencei = _T_184 ? issue_slots_12_out_uop_is_fencei : _T_183 ? issue_slots_11_out_uop_is_fencei : issue_slots_10_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_fence = _T_184 ? issue_slots_12_out_uop_is_fence : _T_183 ? issue_slots_11_out_uop_is_fence : issue_slots_10_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_sfb = _T_184 ? issue_slots_12_out_uop_is_sfb : _T_183 ? issue_slots_11_out_uop_is_sfb : issue_slots_10_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_br_type = _T_184 ? issue_slots_12_out_uop_br_type : _T_183 ? issue_slots_11_out_uop_br_type : issue_slots_10_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_br_tag = _T_184 ? issue_slots_12_out_uop_br_tag : _T_183 ? issue_slots_11_out_uop_br_tag : issue_slots_10_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_br_mask = _T_184 ? issue_slots_12_out_uop_br_mask : _T_183 ? issue_slots_11_out_uop_br_mask : issue_slots_10_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_dis_col_sel = _T_184 ? issue_slots_12_out_uop_dis_col_sel : _T_183 ? issue_slots_11_out_uop_dis_col_sel : issue_slots_10_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_p3_bypass_hint = _T_184 ? issue_slots_12_out_uop_iw_p3_bypass_hint : _T_183 ? issue_slots_11_out_uop_iw_p3_bypass_hint : issue_slots_10_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_p2_bypass_hint = _T_184 ? issue_slots_12_out_uop_iw_p2_bypass_hint : _T_183 ? issue_slots_11_out_uop_iw_p2_bypass_hint : issue_slots_10_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_p1_bypass_hint = _T_184 ? issue_slots_12_out_uop_iw_p1_bypass_hint : _T_183 ? issue_slots_11_out_uop_iw_p1_bypass_hint : issue_slots_10_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_issued = _T_184 ? issue_slots_12_out_uop_iw_issued : _T_183 ? issue_slots_11_out_uop_iw_issued : issue_slots_10_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_0 = _T_184 ? issue_slots_12_out_uop_fu_code_0 : _T_183 ? issue_slots_11_out_uop_fu_code_0 : issue_slots_10_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_1 = _T_184 ? issue_slots_12_out_uop_fu_code_1 : _T_183 ? issue_slots_11_out_uop_fu_code_1 : issue_slots_10_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_2 = _T_184 ? issue_slots_12_out_uop_fu_code_2 : _T_183 ? issue_slots_11_out_uop_fu_code_2 : issue_slots_10_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_3 = _T_184 ? issue_slots_12_out_uop_fu_code_3 : _T_183 ? issue_slots_11_out_uop_fu_code_3 : issue_slots_10_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_4 = _T_184 ? issue_slots_12_out_uop_fu_code_4 : _T_183 ? issue_slots_11_out_uop_fu_code_4 : issue_slots_10_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_5 = _T_184 ? issue_slots_12_out_uop_fu_code_5 : _T_183 ? issue_slots_11_out_uop_fu_code_5 : issue_slots_10_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_6 = _T_184 ? issue_slots_12_out_uop_fu_code_6 : _T_183 ? issue_slots_11_out_uop_fu_code_6 : issue_slots_10_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_7 = _T_184 ? issue_slots_12_out_uop_fu_code_7 : _T_183 ? issue_slots_11_out_uop_fu_code_7 : issue_slots_10_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_8 = _T_184 ? issue_slots_12_out_uop_fu_code_8 : _T_183 ? issue_slots_11_out_uop_fu_code_8 : issue_slots_10_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_9 = _T_184 ? issue_slots_12_out_uop_fu_code_9 : _T_183 ? issue_slots_11_out_uop_fu_code_9 : issue_slots_10_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iq_type_0 = _T_184 ? issue_slots_12_out_uop_iq_type_0 : _T_183 ? issue_slots_11_out_uop_iq_type_0 : issue_slots_10_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iq_type_1 = _T_184 ? issue_slots_12_out_uop_iq_type_1 : _T_183 ? issue_slots_11_out_uop_iq_type_1 : issue_slots_10_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iq_type_2 = _T_184 ? issue_slots_12_out_uop_iq_type_2 : _T_183 ? issue_slots_11_out_uop_iq_type_2 : issue_slots_10_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iq_type_3 = _T_184 ? issue_slots_12_out_uop_iq_type_3 : _T_183 ? issue_slots_11_out_uop_iq_type_3 : issue_slots_10_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_debug_pc = _T_184 ? issue_slots_12_out_uop_debug_pc : _T_183 ? issue_slots_11_out_uop_debug_pc : issue_slots_10_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_rvc = _T_184 ? issue_slots_12_out_uop_is_rvc : _T_183 ? issue_slots_11_out_uop_is_rvc : issue_slots_10_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_debug_inst = _T_184 ? issue_slots_12_out_uop_debug_inst : _T_183 ? issue_slots_11_out_uop_debug_inst : issue_slots_10_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_inst = _T_184 ? issue_slots_12_out_uop_inst : _T_183 ? issue_slots_11_out_uop_inst : issue_slots_10_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_9_clear_T = \|shamts_oh_9; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_9_clear = _issue_slots_9_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_186 = shamts_oh_12 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_187 = shamts_oh_13 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_10_in_uop_valid = _T_187 ? issue_slots_13_will_be_valid : _T_186 ? issue_slots_12_will_be_valid : shamts_oh_11 == 3'h1 & issue_slots_11_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_10_in_uop_bits_debug_tsrc = _T_187 ? issue_slots_13_out_uop_debug_tsrc : _T_186 ? issue_slots_12_out_uop_debug_tsrc : issue_slots_11_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_debug_fsrc = _T_187 ? issue_slots_13_out_uop_debug_fsrc : _T_186 ? issue_slots_12_out_uop_debug_fsrc : issue_slots_11_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_bp_xcpt_if = _T_187 ? issue_slots_13_out_uop_bp_xcpt_if : _T_186 ? issue_slots_12_out_uop_bp_xcpt_if : issue_slots_11_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_bp_debug_if = _T_187 ? issue_slots_13_out_uop_bp_debug_if : _T_186 ? issue_slots_12_out_uop_bp_debug_if : issue_slots_11_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_xcpt_ma_if = _T_187 ? issue_slots_13_out_uop_xcpt_ma_if : _T_186 ? issue_slots_12_out_uop_xcpt_ma_if : issue_slots_11_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_xcpt_ae_if = _T_187 ? issue_slots_13_out_uop_xcpt_ae_if : _T_186 ? issue_slots_12_out_uop_xcpt_ae_if : issue_slots_11_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_xcpt_pf_if = _T_187 ? issue_slots_13_out_uop_xcpt_pf_if : _T_186 ? issue_slots_12_out_uop_xcpt_pf_if : issue_slots_11_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_typ = _T_187 ? issue_slots_13_out_uop_fp_typ : _T_186 ? issue_slots_12_out_uop_fp_typ : issue_slots_11_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_rm = _T_187 ? issue_slots_13_out_uop_fp_rm : _T_186 ? issue_slots_12_out_uop_fp_rm : issue_slots_11_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_val = _T_187 ? issue_slots_13_out_uop_fp_val : _T_186 ? issue_slots_12_out_uop_fp_val : issue_slots_11_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fcn_op = _T_187 ? issue_slots_13_out_uop_fcn_op : _T_186 ? issue_slots_12_out_uop_fcn_op : issue_slots_11_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fcn_dw = _T_187 ? issue_slots_13_out_uop_fcn_dw : _T_186 ? issue_slots_12_out_uop_fcn_dw : issue_slots_11_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_frs3_en = _T_187 ? issue_slots_13_out_uop_frs3_en : _T_186 ? issue_slots_12_out_uop_frs3_en : issue_slots_11_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs2_rtype = _T_187 ? issue_slots_13_out_uop_lrs2_rtype : _T_186 ? issue_slots_12_out_uop_lrs2_rtype : issue_slots_11_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs1_rtype = _T_187 ? issue_slots_13_out_uop_lrs1_rtype : _T_186 ? issue_slots_12_out_uop_lrs1_rtype : issue_slots_11_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_dst_rtype = _T_187 ? issue_slots_13_out_uop_dst_rtype : _T_186 ? issue_slots_12_out_uop_dst_rtype : issue_slots_11_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs3 = _T_187 ? issue_slots_13_out_uop_lrs3 : _T_186 ? issue_slots_12_out_uop_lrs3 : issue_slots_11_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs2 = _T_187 ? issue_slots_13_out_uop_lrs2 : _T_186 ? issue_slots_12_out_uop_lrs2 : issue_slots_11_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs1 = _T_187 ? issue_slots_13_out_uop_lrs1 : _T_186 ? issue_slots_12_out_uop_lrs1 : issue_slots_11_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ldst = _T_187 ? issue_slots_13_out_uop_ldst : _T_186 ? issue_slots_12_out_uop_ldst : issue_slots_11_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ldst_is_rs1 = _T_187 ? issue_slots_13_out_uop_ldst_is_rs1 : _T_186 ? issue_slots_12_out_uop_ldst_is_rs1 : issue_slots_11_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_csr_cmd = _T_187 ? issue_slots_13_out_uop_csr_cmd : _T_186 ? issue_slots_12_out_uop_csr_cmd : issue_slots_11_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_flush_on_commit = _T_187 ? issue_slots_13_out_uop_flush_on_commit : _T_186 ? issue_slots_12_out_uop_flush_on_commit : issue_slots_11_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_unique = _T_187 ? issue_slots_13_out_uop_is_unique : _T_186 ? issue_slots_12_out_uop_is_unique : issue_slots_11_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_uses_stq = _T_187 ? issue_slots_13_out_uop_uses_stq : _T_186 ? issue_slots_12_out_uop_uses_stq : issue_slots_11_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_uses_ldq = _T_187 ? issue_slots_13_out_uop_uses_ldq : _T_186 ? issue_slots_12_out_uop_uses_ldq : issue_slots_11_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_mem_signed = _T_187 ? issue_slots_13_out_uop_mem_signed : _T_186 ? issue_slots_12_out_uop_mem_signed : issue_slots_11_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_mem_size = _T_187 ? issue_slots_13_out_uop_mem_size : _T_186 ? issue_slots_12_out_uop_mem_size : issue_slots_11_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_mem_cmd = _T_187 ? issue_slots_13_out_uop_mem_cmd : _T_186 ? issue_slots_12_out_uop_mem_cmd : issue_slots_11_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_exc_cause = _T_187 ? issue_slots_13_out_uop_exc_cause : _T_186 ? issue_slots_12_out_uop_exc_cause : issue_slots_11_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_exception = _T_187 ? issue_slots_13_out_uop_exception : _T_186 ? issue_slots_12_out_uop_exception : issue_slots_11_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_stale_pdst = _T_187 ? issue_slots_13_out_uop_stale_pdst : _T_186 ? issue_slots_12_out_uop_stale_pdst : issue_slots_11_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ppred_busy = _T_187 ? issue_slots_13_out_uop_ppred_busy : _T_186 ? issue_slots_12_out_uop_ppred_busy : issue_slots_11_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs3_busy = _T_187 ? issue_slots_13_out_uop_prs3_busy : _T_186 ? issue_slots_12_out_uop_prs3_busy : issue_slots_11_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs2_busy = _T_187 ? issue_slots_13_out_uop_prs2_busy : _T_186 ? issue_slots_12_out_uop_prs2_busy : issue_slots_11_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs1_busy = _T_187 ? issue_slots_13_out_uop_prs1_busy : _T_186 ? issue_slots_12_out_uop_prs1_busy : issue_slots_11_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ppred = _T_187 ? issue_slots_13_out_uop_ppred : _T_186 ? issue_slots_12_out_uop_ppred : issue_slots_11_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs3 = _T_187 ? issue_slots_13_out_uop_prs3 : _T_186 ? issue_slots_12_out_uop_prs3 : issue_slots_11_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs2 = _T_187 ? issue_slots_13_out_uop_prs2 : _T_186 ? issue_slots_12_out_uop_prs2 : issue_slots_11_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs1 = _T_187 ? issue_slots_13_out_uop_prs1 : _T_186 ? issue_slots_12_out_uop_prs1 : issue_slots_11_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_pdst = _T_187 ? issue_slots_13_out_uop_pdst : _T_186 ? issue_slots_12_out_uop_pdst : issue_slots_11_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_rxq_idx = _T_187 ? issue_slots_13_out_uop_rxq_idx : _T_186 ? issue_slots_12_out_uop_rxq_idx : issue_slots_11_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_stq_idx = _T_187 ? issue_slots_13_out_uop_stq_idx : _T_186 ? issue_slots_12_out_uop_stq_idx : issue_slots_11_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ldq_idx = _T_187 ? issue_slots_13_out_uop_ldq_idx : _T_186 ? issue_slots_12_out_uop_ldq_idx : issue_slots_11_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_rob_idx = _T_187 ? issue_slots_13_out_uop_rob_idx : _T_186 ? issue_slots_12_out_uop_rob_idx : issue_slots_11_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_vec = _T_187 ? issue_slots_13_out_uop_fp_ctrl_vec : _T_186 ? issue_slots_12_out_uop_fp_ctrl_vec : issue_slots_11_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_wflags = _T_187 ? issue_slots_13_out_uop_fp_ctrl_wflags : _T_186 ? issue_slots_12_out_uop_fp_ctrl_wflags : issue_slots_11_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_sqrt = _T_187 ? issue_slots_13_out_uop_fp_ctrl_sqrt : _T_186 ? issue_slots_12_out_uop_fp_ctrl_sqrt : issue_slots_11_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_div = _T_187 ? issue_slots_13_out_uop_fp_ctrl_div : _T_186 ? issue_slots_12_out_uop_fp_ctrl_div : issue_slots_11_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_fma = _T_187 ? issue_slots_13_out_uop_fp_ctrl_fma : _T_186 ? issue_slots_12_out_uop_fp_ctrl_fma : issue_slots_11_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_fastpipe = _T_187 ? issue_slots_13_out_uop_fp_ctrl_fastpipe : _T_186 ? issue_slots_12_out_uop_fp_ctrl_fastpipe : issue_slots_11_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_toint = _T_187 ? issue_slots_13_out_uop_fp_ctrl_toint : _T_186 ? issue_slots_12_out_uop_fp_ctrl_toint : issue_slots_11_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_fromint = _T_187 ? issue_slots_13_out_uop_fp_ctrl_fromint : _T_186 ? issue_slots_12_out_uop_fp_ctrl_fromint : issue_slots_11_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_typeTagOut = _T_187 ? issue_slots_13_out_uop_fp_ctrl_typeTagOut : _T_186 ? issue_slots_12_out_uop_fp_ctrl_typeTagOut : issue_slots_11_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_typeTagIn = _T_187 ? issue_slots_13_out_uop_fp_ctrl_typeTagIn : _T_186 ? issue_slots_12_out_uop_fp_ctrl_typeTagIn : issue_slots_11_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_swap23 = _T_187 ? issue_slots_13_out_uop_fp_ctrl_swap23 : _T_186 ? issue_slots_12_out_uop_fp_ctrl_swap23 : issue_slots_11_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_swap12 = _T_187 ? issue_slots_13_out_uop_fp_ctrl_swap12 : _T_186 ? issue_slots_12_out_uop_fp_ctrl_swap12 : issue_slots_11_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_ren3 = _T_187 ? issue_slots_13_out_uop_fp_ctrl_ren3 : _T_186 ? issue_slots_12_out_uop_fp_ctrl_ren3 : issue_slots_11_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_ren2 = _T_187 ? issue_slots_13_out_uop_fp_ctrl_ren2 : _T_186 ? issue_slots_12_out_uop_fp_ctrl_ren2 : issue_slots_11_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_ren1 = _T_187 ? issue_slots_13_out_uop_fp_ctrl_ren1 : _T_186 ? issue_slots_12_out_uop_fp_ctrl_ren1 : issue_slots_11_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_wen = _T_187 ? issue_slots_13_out_uop_fp_ctrl_wen : _T_186 ? issue_slots_12_out_uop_fp_ctrl_wen : issue_slots_11_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_ldst = _T_187 ? issue_slots_13_out_uop_fp_ctrl_ldst : _T_186 ? issue_slots_12_out_uop_fp_ctrl_ldst : issue_slots_11_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_op2_sel = _T_187 ? issue_slots_13_out_uop_op2_sel : _T_186 ? issue_slots_12_out_uop_op2_sel : issue_slots_11_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_op1_sel = _T_187 ? issue_slots_13_out_uop_op1_sel : _T_186 ? issue_slots_12_out_uop_op1_sel : issue_slots_11_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_imm_packed = _T_187 ? issue_slots_13_out_uop_imm_packed : _T_186 ? issue_slots_12_out_uop_imm_packed : issue_slots_11_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_pimm = _T_187 ? issue_slots_13_out_uop_pimm : _T_186 ? issue_slots_12_out_uop_pimm : issue_slots_11_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_imm_sel = _T_187 ? issue_slots_13_out_uop_imm_sel : _T_186 ? issue_slots_12_out_uop_imm_sel : issue_slots_11_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_imm_rename = _T_187 ? issue_slots_13_out_uop_imm_rename : _T_186 ? issue_slots_12_out_uop_imm_rename : issue_slots_11_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_taken = _T_187 ? issue_slots_13_out_uop_taken : _T_186 ? issue_slots_12_out_uop_taken : issue_slots_11_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_pc_lob = _T_187 ? issue_slots_13_out_uop_pc_lob : _T_186 ? issue_slots_12_out_uop_pc_lob : issue_slots_11_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_edge_inst = _T_187 ? issue_slots_13_out_uop_edge_inst : _T_186 ? issue_slots_12_out_uop_edge_inst : issue_slots_11_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ftq_idx = _T_187 ? issue_slots_13_out_uop_ftq_idx : _T_186 ? issue_slots_12_out_uop_ftq_idx : issue_slots_11_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_mov = _T_187 ? issue_slots_13_out_uop_is_mov : _T_186 ? issue_slots_12_out_uop_is_mov : issue_slots_11_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_rocc = _T_187 ? issue_slots_13_out_uop_is_rocc : _T_186 ? issue_slots_12_out_uop_is_rocc : issue_slots_11_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_sys_pc2epc = _T_187 ? issue_slots_13_out_uop_is_sys_pc2epc : _T_186 ? issue_slots_12_out_uop_is_sys_pc2epc : issue_slots_11_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_eret = _T_187 ? issue_slots_13_out_uop_is_eret : _T_186 ? issue_slots_12_out_uop_is_eret : issue_slots_11_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_amo = _T_187 ? issue_slots_13_out_uop_is_amo : _T_186 ? issue_slots_12_out_uop_is_amo : issue_slots_11_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_sfence = _T_187 ? issue_slots_13_out_uop_is_sfence : _T_186 ? issue_slots_12_out_uop_is_sfence : issue_slots_11_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_fencei = _T_187 ? issue_slots_13_out_uop_is_fencei : _T_186 ? issue_slots_12_out_uop_is_fencei : issue_slots_11_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_fence = _T_187 ? issue_slots_13_out_uop_is_fence : _T_186 ? issue_slots_12_out_uop_is_fence : issue_slots_11_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_sfb = _T_187 ? issue_slots_13_out_uop_is_sfb : _T_186 ? issue_slots_12_out_uop_is_sfb : issue_slots_11_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_br_type = _T_187 ? issue_slots_13_out_uop_br_type : _T_186 ? issue_slots_12_out_uop_br_type : issue_slots_11_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_br_tag = _T_187 ? issue_slots_13_out_uop_br_tag : _T_186 ? issue_slots_12_out_uop_br_tag : issue_slots_11_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_br_mask = _T_187 ? issue_slots_13_out_uop_br_mask : _T_186 ? issue_slots_12_out_uop_br_mask : issue_slots_11_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_dis_col_sel = _T_187 ? issue_slots_13_out_uop_dis_col_sel : _T_186 ? issue_slots_12_out_uop_dis_col_sel : issue_slots_11_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_p3_bypass_hint = _T_187 ? issue_slots_13_out_uop_iw_p3_bypass_hint : _T_186 ? issue_slots_12_out_uop_iw_p3_bypass_hint : issue_slots_11_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_p2_bypass_hint = _T_187 ? issue_slots_13_out_uop_iw_p2_bypass_hint : _T_186 ? issue_slots_12_out_uop_iw_p2_bypass_hint : issue_slots_11_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_p1_bypass_hint = _T_187 ? issue_slots_13_out_uop_iw_p1_bypass_hint : _T_186 ? issue_slots_12_out_uop_iw_p1_bypass_hint : issue_slots_11_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_issued = _T_187 ? issue_slots_13_out_uop_iw_issued : _T_186 ? issue_slots_12_out_uop_iw_issued : issue_slots_11_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_0 = _T_187 ? issue_slots_13_out_uop_fu_code_0 : _T_186 ? issue_slots_12_out_uop_fu_code_0 : issue_slots_11_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_1 = _T_187 ? issue_slots_13_out_uop_fu_code_1 : _T_186 ? issue_slots_12_out_uop_fu_code_1 : issue_slots_11_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_2 = _T_187 ? issue_slots_13_out_uop_fu_code_2 : _T_186 ? issue_slots_12_out_uop_fu_code_2 : issue_slots_11_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_3 = _T_187 ? issue_slots_13_out_uop_fu_code_3 : _T_186 ? issue_slots_12_out_uop_fu_code_3 : issue_slots_11_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_4 = _T_187 ? issue_slots_13_out_uop_fu_code_4 : _T_186 ? issue_slots_12_out_uop_fu_code_4 : issue_slots_11_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_5 = _T_187 ? issue_slots_13_out_uop_fu_code_5 : _T_186 ? issue_slots_12_out_uop_fu_code_5 : issue_slots_11_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_6 = _T_187 ? issue_slots_13_out_uop_fu_code_6 : _T_186 ? issue_slots_12_out_uop_fu_code_6 : issue_slots_11_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_7 = _T_187 ? issue_slots_13_out_uop_fu_code_7 : _T_186 ? issue_slots_12_out_uop_fu_code_7 : issue_slots_11_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_8 = _T_187 ? issue_slots_13_out_uop_fu_code_8 : _T_186 ? issue_slots_12_out_uop_fu_code_8 : issue_slots_11_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_9 = _T_187 ? issue_slots_13_out_uop_fu_code_9 : _T_186 ? issue_slots_12_out_uop_fu_code_9 : issue_slots_11_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iq_type_0 = _T_187 ? issue_slots_13_out_uop_iq_type_0 : _T_186 ? issue_slots_12_out_uop_iq_type_0 : issue_slots_11_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iq_type_1 = _T_187 ? issue_slots_13_out_uop_iq_type_1 : _T_186 ? issue_slots_12_out_uop_iq_type_1 : issue_slots_11_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iq_type_2 = _T_187 ? issue_slots_13_out_uop_iq_type_2 : _T_186 ? issue_slots_12_out_uop_iq_type_2 : issue_slots_11_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iq_type_3 = _T_187 ? issue_slots_13_out_uop_iq_type_3 : _T_186 ? issue_slots_12_out_uop_iq_type_3 : issue_slots_11_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_debug_pc = _T_187 ? issue_slots_13_out_uop_debug_pc : _T_186 ? issue_slots_12_out_uop_debug_pc : issue_slots_11_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_rvc = _T_187 ? issue_slots_13_out_uop_is_rvc : _T_186 ? issue_slots_12_out_uop_is_rvc : issue_slots_11_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_debug_inst = _T_187 ? issue_slots_13_out_uop_debug_inst : _T_186 ? issue_slots_12_out_uop_debug_inst : issue_slots_11_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_inst = _T_187 ? issue_slots_13_out_uop_inst : _T_186 ? issue_slots_12_out_uop_inst : issue_slots_11_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_10_clear_T = \|shamts_oh_10; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_10_clear = _issue_slots_10_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_189 = shamts_oh_13 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_190 = shamts_oh_14 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_11_in_uop_valid = _T_190 ? issue_slots_14_will_be_valid : _T_189 ? issue_slots_13_will_be_valid : shamts_oh_12 == 3'h1 & issue_slots_12_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_11_in_uop_bits_debug_tsrc = _T_190 ? issue_slots_14_out_uop_debug_tsrc : _T_189 ? issue_slots_13_out_uop_debug_tsrc : issue_slots_12_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_debug_fsrc = _T_190 ? issue_slots_14_out_uop_debug_fsrc : _T_189 ? issue_slots_13_out_uop_debug_fsrc : issue_slots_12_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_bp_xcpt_if = _T_190 ? issue_slots_14_out_uop_bp_xcpt_if : _T_189 ? issue_slots_13_out_uop_bp_xcpt_if : issue_slots_12_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_bp_debug_if = _T_190 ? issue_slots_14_out_uop_bp_debug_if : _T_189 ? issue_slots_13_out_uop_bp_debug_if : issue_slots_12_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_xcpt_ma_if = _T_190 ? issue_slots_14_out_uop_xcpt_ma_if : _T_189 ? issue_slots_13_out_uop_xcpt_ma_if : issue_slots_12_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_xcpt_ae_if = _T_190 ? issue_slots_14_out_uop_xcpt_ae_if : _T_189 ? issue_slots_13_out_uop_xcpt_ae_if : issue_slots_12_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_xcpt_pf_if = _T_190 ? issue_slots_14_out_uop_xcpt_pf_if : _T_189 ? issue_slots_13_out_uop_xcpt_pf_if : issue_slots_12_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_typ = _T_190 ? issue_slots_14_out_uop_fp_typ : _T_189 ? issue_slots_13_out_uop_fp_typ : issue_slots_12_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_rm = _T_190 ? issue_slots_14_out_uop_fp_rm : _T_189 ? issue_slots_13_out_uop_fp_rm : issue_slots_12_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_val = _T_190 ? issue_slots_14_out_uop_fp_val : _T_189 ? issue_slots_13_out_uop_fp_val : issue_slots_12_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fcn_op = _T_190 ? issue_slots_14_out_uop_fcn_op : _T_189 ? issue_slots_13_out_uop_fcn_op : issue_slots_12_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fcn_dw = _T_190 ? issue_slots_14_out_uop_fcn_dw : _T_189 ? issue_slots_13_out_uop_fcn_dw : issue_slots_12_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_frs3_en = _T_190 ? issue_slots_14_out_uop_frs3_en : _T_189 ? issue_slots_13_out_uop_frs3_en : issue_slots_12_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs2_rtype = _T_190 ? issue_slots_14_out_uop_lrs2_rtype : _T_189 ? issue_slots_13_out_uop_lrs2_rtype : issue_slots_12_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs1_rtype = _T_190 ? issue_slots_14_out_uop_lrs1_rtype : _T_189 ? issue_slots_13_out_uop_lrs1_rtype : issue_slots_12_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_dst_rtype = _T_190 ? issue_slots_14_out_uop_dst_rtype : _T_189 ? issue_slots_13_out_uop_dst_rtype : issue_slots_12_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs3 = _T_190 ? issue_slots_14_out_uop_lrs3 : _T_189 ? issue_slots_13_out_uop_lrs3 : issue_slots_12_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs2 = _T_190 ? issue_slots_14_out_uop_lrs2 : _T_189 ? issue_slots_13_out_uop_lrs2 : issue_slots_12_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs1 = _T_190 ? issue_slots_14_out_uop_lrs1 : _T_189 ? issue_slots_13_out_uop_lrs1 : issue_slots_12_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ldst = _T_190 ? issue_slots_14_out_uop_ldst : _T_189 ? issue_slots_13_out_uop_ldst : issue_slots_12_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ldst_is_rs1 = _T_190 ? issue_slots_14_out_uop_ldst_is_rs1 : _T_189 ? issue_slots_13_out_uop_ldst_is_rs1 : issue_slots_12_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_csr_cmd = _T_190 ? issue_slots_14_out_uop_csr_cmd : _T_189 ? issue_slots_13_out_uop_csr_cmd : issue_slots_12_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_flush_on_commit = _T_190 ? issue_slots_14_out_uop_flush_on_commit : _T_189 ? issue_slots_13_out_uop_flush_on_commit : issue_slots_12_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_unique = _T_190 ? issue_slots_14_out_uop_is_unique : _T_189 ? issue_slots_13_out_uop_is_unique : issue_slots_12_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_uses_stq = _T_190 ? issue_slots_14_out_uop_uses_stq : _T_189 ? issue_slots_13_out_uop_uses_stq : issue_slots_12_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_uses_ldq = _T_190 ? issue_slots_14_out_uop_uses_ldq : _T_189 ? issue_slots_13_out_uop_uses_ldq : issue_slots_12_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_mem_signed = _T_190 ? issue_slots_14_out_uop_mem_signed : _T_189 ? issue_slots_13_out_uop_mem_signed : issue_slots_12_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_mem_size = _T_190 ? issue_slots_14_out_uop_mem_size : _T_189 ? issue_slots_13_out_uop_mem_size : issue_slots_12_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_mem_cmd = _T_190 ? issue_slots_14_out_uop_mem_cmd : _T_189 ? issue_slots_13_out_uop_mem_cmd : issue_slots_12_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_exc_cause = _T_190 ? issue_slots_14_out_uop_exc_cause : _T_189 ? issue_slots_13_out_uop_exc_cause : issue_slots_12_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_exception = _T_190 ? issue_slots_14_out_uop_exception : _T_189 ? issue_slots_13_out_uop_exception : issue_slots_12_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_stale_pdst = _T_190 ? issue_slots_14_out_uop_stale_pdst : _T_189 ? issue_slots_13_out_uop_stale_pdst : issue_slots_12_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ppred_busy = _T_190 ? issue_slots_14_out_uop_ppred_busy : _T_189 ? issue_slots_13_out_uop_ppred_busy : issue_slots_12_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs3_busy = _T_190 ? issue_slots_14_out_uop_prs3_busy : _T_189 ? issue_slots_13_out_uop_prs3_busy : issue_slots_12_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs2_busy = _T_190 ? issue_slots_14_out_uop_prs2_busy : _T_189 ? issue_slots_13_out_uop_prs2_busy : issue_slots_12_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs1_busy = _T_190 ? issue_slots_14_out_uop_prs1_busy : _T_189 ? issue_slots_13_out_uop_prs1_busy : issue_slots_12_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ppred = _T_190 ? issue_slots_14_out_uop_ppred : _T_189 ? issue_slots_13_out_uop_ppred : issue_slots_12_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs3 = _T_190 ? issue_slots_14_out_uop_prs3 : _T_189 ? issue_slots_13_out_uop_prs3 : issue_slots_12_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs2 = _T_190 ? issue_slots_14_out_uop_prs2 : _T_189 ? issue_slots_13_out_uop_prs2 : issue_slots_12_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs1 = _T_190 ? issue_slots_14_out_uop_prs1 : _T_189 ? issue_slots_13_out_uop_prs1 : issue_slots_12_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_pdst = _T_190 ? issue_slots_14_out_uop_pdst : _T_189 ? issue_slots_13_out_uop_pdst : issue_slots_12_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_rxq_idx = _T_190 ? issue_slots_14_out_uop_rxq_idx : _T_189 ? issue_slots_13_out_uop_rxq_idx : issue_slots_12_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_stq_idx = _T_190 ? issue_slots_14_out_uop_stq_idx : _T_189 ? issue_slots_13_out_uop_stq_idx : issue_slots_12_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ldq_idx = _T_190 ? issue_slots_14_out_uop_ldq_idx : _T_189 ? issue_slots_13_out_uop_ldq_idx : issue_slots_12_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_rob_idx = _T_190 ? issue_slots_14_out_uop_rob_idx : _T_189 ? issue_slots_13_out_uop_rob_idx : issue_slots_12_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_vec = _T_190 ? issue_slots_14_out_uop_fp_ctrl_vec : _T_189 ? issue_slots_13_out_uop_fp_ctrl_vec : issue_slots_12_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_wflags = _T_190 ? issue_slots_14_out_uop_fp_ctrl_wflags : _T_189 ? issue_slots_13_out_uop_fp_ctrl_wflags : issue_slots_12_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_sqrt = _T_190 ? issue_slots_14_out_uop_fp_ctrl_sqrt : _T_189 ? issue_slots_13_out_uop_fp_ctrl_sqrt : issue_slots_12_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_div = _T_190 ? issue_slots_14_out_uop_fp_ctrl_div : _T_189 ? issue_slots_13_out_uop_fp_ctrl_div : issue_slots_12_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_fma = _T_190 ? issue_slots_14_out_uop_fp_ctrl_fma : _T_189 ? issue_slots_13_out_uop_fp_ctrl_fma : issue_slots_12_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_fastpipe = _T_190 ? issue_slots_14_out_uop_fp_ctrl_fastpipe : _T_189 ? issue_slots_13_out_uop_fp_ctrl_fastpipe : issue_slots_12_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_toint = _T_190 ? issue_slots_14_out_uop_fp_ctrl_toint : _T_189 ? issue_slots_13_out_uop_fp_ctrl_toint : issue_slots_12_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_fromint = _T_190 ? issue_slots_14_out_uop_fp_ctrl_fromint : _T_189 ? issue_slots_13_out_uop_fp_ctrl_fromint : issue_slots_12_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_typeTagOut = _T_190 ? issue_slots_14_out_uop_fp_ctrl_typeTagOut : _T_189 ? issue_slots_13_out_uop_fp_ctrl_typeTagOut : issue_slots_12_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_typeTagIn = _T_190 ? issue_slots_14_out_uop_fp_ctrl_typeTagIn : _T_189 ? issue_slots_13_out_uop_fp_ctrl_typeTagIn : issue_slots_12_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_swap23 = _T_190 ? issue_slots_14_out_uop_fp_ctrl_swap23 : _T_189 ? issue_slots_13_out_uop_fp_ctrl_swap23 : issue_slots_12_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_swap12 = _T_190 ? issue_slots_14_out_uop_fp_ctrl_swap12 : _T_189 ? issue_slots_13_out_uop_fp_ctrl_swap12 : issue_slots_12_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_ren3 = _T_190 ? issue_slots_14_out_uop_fp_ctrl_ren3 : _T_189 ? issue_slots_13_out_uop_fp_ctrl_ren3 : issue_slots_12_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_ren2 = _T_190 ? issue_slots_14_out_uop_fp_ctrl_ren2 : _T_189 ? issue_slots_13_out_uop_fp_ctrl_ren2 : issue_slots_12_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_ren1 = _T_190 ? issue_slots_14_out_uop_fp_ctrl_ren1 : _T_189 ? issue_slots_13_out_uop_fp_ctrl_ren1 : issue_slots_12_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_wen = _T_190 ? issue_slots_14_out_uop_fp_ctrl_wen : _T_189 ? issue_slots_13_out_uop_fp_ctrl_wen : issue_slots_12_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_ldst = _T_190 ? issue_slots_14_out_uop_fp_ctrl_ldst : _T_189 ? issue_slots_13_out_uop_fp_ctrl_ldst : issue_slots_12_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_op2_sel = _T_190 ? issue_slots_14_out_uop_op2_sel : _T_189 ? issue_slots_13_out_uop_op2_sel : issue_slots_12_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_op1_sel = _T_190 ? issue_slots_14_out_uop_op1_sel : _T_189 ? issue_slots_13_out_uop_op1_sel : issue_slots_12_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_imm_packed = _T_190 ? issue_slots_14_out_uop_imm_packed : _T_189 ? issue_slots_13_out_uop_imm_packed : issue_slots_12_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_pimm = _T_190 ? issue_slots_14_out_uop_pimm : _T_189 ? issue_slots_13_out_uop_pimm : issue_slots_12_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_imm_sel = _T_190 ? issue_slots_14_out_uop_imm_sel : _T_189 ? issue_slots_13_out_uop_imm_sel : issue_slots_12_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_imm_rename = _T_190 ? issue_slots_14_out_uop_imm_rename : _T_189 ? issue_slots_13_out_uop_imm_rename : issue_slots_12_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_taken = _T_190 ? issue_slots_14_out_uop_taken : _T_189 ? issue_slots_13_out_uop_taken : issue_slots_12_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_pc_lob = _T_190 ? issue_slots_14_out_uop_pc_lob : _T_189 ? issue_slots_13_out_uop_pc_lob : issue_slots_12_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_edge_inst = _T_190 ? issue_slots_14_out_uop_edge_inst : _T_189 ? issue_slots_13_out_uop_edge_inst : issue_slots_12_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ftq_idx = _T_190 ? issue_slots_14_out_uop_ftq_idx : _T_189 ? issue_slots_13_out_uop_ftq_idx : issue_slots_12_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_mov = _T_190 ? issue_slots_14_out_uop_is_mov : _T_189 ? issue_slots_13_out_uop_is_mov : issue_slots_12_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_rocc = _T_190 ? issue_slots_14_out_uop_is_rocc : _T_189 ? issue_slots_13_out_uop_is_rocc : issue_slots_12_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_sys_pc2epc = _T_190 ? issue_slots_14_out_uop_is_sys_pc2epc : _T_189 ? issue_slots_13_out_uop_is_sys_pc2epc : issue_slots_12_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_eret = _T_190 ? issue_slots_14_out_uop_is_eret : _T_189 ? issue_slots_13_out_uop_is_eret : issue_slots_12_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_amo = _T_190 ? issue_slots_14_out_uop_is_amo : _T_189 ? issue_slots_13_out_uop_is_amo : issue_slots_12_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_sfence = _T_190 ? issue_slots_14_out_uop_is_sfence : _T_189 ? issue_slots_13_out_uop_is_sfence : issue_slots_12_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_fencei = _T_190 ? issue_slots_14_out_uop_is_fencei : _T_189 ? issue_slots_13_out_uop_is_fencei : issue_slots_12_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_fence = _T_190 ? issue_slots_14_out_uop_is_fence : _T_189 ? issue_slots_13_out_uop_is_fence : issue_slots_12_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_sfb = _T_190 ? issue_slots_14_out_uop_is_sfb : _T_189 ? issue_slots_13_out_uop_is_sfb : issue_slots_12_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_br_type = _T_190 ? issue_slots_14_out_uop_br_type : _T_189 ? issue_slots_13_out_uop_br_type : issue_slots_12_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_br_tag = _T_190 ? issue_slots_14_out_uop_br_tag : _T_189 ? issue_slots_13_out_uop_br_tag : issue_slots_12_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_br_mask = _T_190 ? issue_slots_14_out_uop_br_mask : _T_189 ? issue_slots_13_out_uop_br_mask : issue_slots_12_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_dis_col_sel = _T_190 ? issue_slots_14_out_uop_dis_col_sel : _T_189 ? issue_slots_13_out_uop_dis_col_sel : issue_slots_12_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_p3_bypass_hint = _T_190 ? issue_slots_14_out_uop_iw_p3_bypass_hint : _T_189 ? issue_slots_13_out_uop_iw_p3_bypass_hint : issue_slots_12_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_p2_bypass_hint = _T_190 ? issue_slots_14_out_uop_iw_p2_bypass_hint : _T_189 ? issue_slots_13_out_uop_iw_p2_bypass_hint : issue_slots_12_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_p1_bypass_hint = _T_190 ? issue_slots_14_out_uop_iw_p1_bypass_hint : _T_189 ? issue_slots_13_out_uop_iw_p1_bypass_hint : issue_slots_12_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_issued = _T_190 ? issue_slots_14_out_uop_iw_issued : _T_189 ? issue_slots_13_out_uop_iw_issued : issue_slots_12_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_0 = _T_190 ? issue_slots_14_out_uop_fu_code_0 : _T_189 ? issue_slots_13_out_uop_fu_code_0 : issue_slots_12_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_1 = _T_190 ? issue_slots_14_out_uop_fu_code_1 : _T_189 ? issue_slots_13_out_uop_fu_code_1 : issue_slots_12_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_2 = _T_190 ? issue_slots_14_out_uop_fu_code_2 : _T_189 ? issue_slots_13_out_uop_fu_code_2 : issue_slots_12_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_3 = _T_190 ? issue_slots_14_out_uop_fu_code_3 : _T_189 ? issue_slots_13_out_uop_fu_code_3 : issue_slots_12_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_4 = _T_190 ? issue_slots_14_out_uop_fu_code_4 : _T_189 ? issue_slots_13_out_uop_fu_code_4 : issue_slots_12_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_5 = _T_190 ? issue_slots_14_out_uop_fu_code_5 : _T_189 ? issue_slots_13_out_uop_fu_code_5 : issue_slots_12_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_6 = _T_190 ? issue_slots_14_out_uop_fu_code_6 : _T_189 ? issue_slots_13_out_uop_fu_code_6 : issue_slots_12_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_7 = _T_190 ? issue_slots_14_out_uop_fu_code_7 : _T_189 ? issue_slots_13_out_uop_fu_code_7 : issue_slots_12_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_8 = _T_190 ? issue_slots_14_out_uop_fu_code_8 : _T_189 ? issue_slots_13_out_uop_fu_code_8 : issue_slots_12_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_9 = _T_190 ? issue_slots_14_out_uop_fu_code_9 : _T_189 ? issue_slots_13_out_uop_fu_code_9 : issue_slots_12_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iq_type_0 = _T_190 ? issue_slots_14_out_uop_iq_type_0 : _T_189 ? issue_slots_13_out_uop_iq_type_0 : issue_slots_12_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iq_type_1 = _T_190 ? issue_slots_14_out_uop_iq_type_1 : _T_189 ? issue_slots_13_out_uop_iq_type_1 : issue_slots_12_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iq_type_2 = _T_190 ? issue_slots_14_out_uop_iq_type_2 : _T_189 ? issue_slots_13_out_uop_iq_type_2 : issue_slots_12_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iq_type_3 = _T_190 ? issue_slots_14_out_uop_iq_type_3 : _T_189 ? issue_slots_13_out_uop_iq_type_3 : issue_slots_12_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_debug_pc = _T_190 ? issue_slots_14_out_uop_debug_pc : _T_189 ? issue_slots_13_out_uop_debug_pc : issue_slots_12_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_rvc = _T_190 ? issue_slots_14_out_uop_is_rvc : _T_189 ? issue_slots_13_out_uop_is_rvc : issue_slots_12_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_debug_inst = _T_190 ? issue_slots_14_out_uop_debug_inst : _T_189 ? issue_slots_13_out_uop_debug_inst : issue_slots_12_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_inst = _T_190 ? issue_slots_14_out_uop_inst : _T_189 ? issue_slots_13_out_uop_inst : issue_slots_12_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_11_clear_T = \|shamts_oh_11; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_11_clear = _issue_slots_11_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_192 = shamts_oh_14 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_193 = shamts_oh_15 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_12_in_uop_valid = _T_193 ? issue_slots_15_will_be_valid : _T_192 ? issue_slots_14_will_be_valid : shamts_oh_13 == 3'h1 & issue_slots_13_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_12_in_uop_bits_debug_tsrc = _T_193 ? issue_slots_15_out_uop_debug_tsrc : _T_192 ? issue_slots_14_out_uop_debug_tsrc : issue_slots_13_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_debug_fsrc = _T_193 ? issue_slots_15_out_uop_debug_fsrc : _T_192 ? issue_slots_14_out_uop_debug_fsrc : issue_slots_13_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_bp_xcpt_if = _T_193 ? issue_slots_15_out_uop_bp_xcpt_if : _T_192 ? issue_slots_14_out_uop_bp_xcpt_if : issue_slots_13_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_bp_debug_if = _T_193 ? issue_slots_15_out_uop_bp_debug_if : _T_192 ? issue_slots_14_out_uop_bp_debug_if : issue_slots_13_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_xcpt_ma_if = _T_193 ? issue_slots_15_out_uop_xcpt_ma_if : _T_192 ? issue_slots_14_out_uop_xcpt_ma_if : issue_slots_13_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_xcpt_ae_if = _T_193 ? issue_slots_15_out_uop_xcpt_ae_if : _T_192 ? issue_slots_14_out_uop_xcpt_ae_if : issue_slots_13_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_xcpt_pf_if = _T_193 ? issue_slots_15_out_uop_xcpt_pf_if : _T_192 ? issue_slots_14_out_uop_xcpt_pf_if : issue_slots_13_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_typ = _T_193 ? issue_slots_15_out_uop_fp_typ : _T_192 ? issue_slots_14_out_uop_fp_typ : issue_slots_13_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_rm = _T_193 ? issue_slots_15_out_uop_fp_rm : _T_192 ? issue_slots_14_out_uop_fp_rm : issue_slots_13_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_val = _T_193 ? issue_slots_15_out_uop_fp_val : _T_192 ? issue_slots_14_out_uop_fp_val : issue_slots_13_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fcn_op = _T_193 ? issue_slots_15_out_uop_fcn_op : _T_192 ? issue_slots_14_out_uop_fcn_op : issue_slots_13_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fcn_dw = _T_193 ? issue_slots_15_out_uop_fcn_dw : _T_192 ? issue_slots_14_out_uop_fcn_dw : issue_slots_13_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_frs3_en = _T_193 ? issue_slots_15_out_uop_frs3_en : _T_192 ? issue_slots_14_out_uop_frs3_en : issue_slots_13_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_lrs2_rtype = _T_193 ? issue_slots_15_out_uop_lrs2_rtype : _T_192 ? issue_slots_14_out_uop_lrs2_rtype : issue_slots_13_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_lrs1_rtype = _T_193 ? issue_slots_15_out_uop_lrs1_rtype : _T_192 ? issue_slots_14_out_uop_lrs1_rtype : issue_slots_13_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_dst_rtype = _T_193 ? issue_slots_15_out_uop_dst_rtype : _T_192 ? issue_slots_14_out_uop_dst_rtype : issue_slots_13_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_lrs3 = _T_193 ? issue_slots_15_out_uop_lrs3 : _T_192 ? issue_slots_14_out_uop_lrs3 : issue_slots_13_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_lrs2 = _T_193 ? issue_slots_15_out_uop_lrs2 : _T_192 ? issue_slots_14_out_uop_lrs2 : issue_slots_13_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_lrs1 = _T_193 ? issue_slots_15_out_uop_lrs1 : _T_192 ? issue_slots_14_out_uop_lrs1 : issue_slots_13_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_ldst = _T_193 ? issue_slots_15_out_uop_ldst : _T_192 ? issue_slots_14_out_uop_ldst : issue_slots_13_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_ldst_is_rs1 = _T_193 ? issue_slots_15_out_uop_ldst_is_rs1 : _T_192 ? issue_slots_14_out_uop_ldst_is_rs1 : issue_slots_13_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_csr_cmd = _T_193 ? issue_slots_15_out_uop_csr_cmd : _T_192 ? issue_slots_14_out_uop_csr_cmd : issue_slots_13_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_flush_on_commit = _T_193 ? issue_slots_15_out_uop_flush_on_commit : _T_192 ? issue_slots_14_out_uop_flush_on_commit : issue_slots_13_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_unique = _T_193 ? issue_slots_15_out_uop_is_unique : _T_192 ? issue_slots_14_out_uop_is_unique : issue_slots_13_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_uses_stq = _T_193 ? issue_slots_15_out_uop_uses_stq : _T_192 ? issue_slots_14_out_uop_uses_stq : issue_slots_13_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_uses_ldq = _T_193 ? issue_slots_15_out_uop_uses_ldq : _T_192 ? issue_slots_14_out_uop_uses_ldq : issue_slots_13_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_mem_signed = _T_193 ? issue_slots_15_out_uop_mem_signed : _T_192 ? issue_slots_14_out_uop_mem_signed : issue_slots_13_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_mem_size = _T_193 ? issue_slots_15_out_uop_mem_size : _T_192 ? issue_slots_14_out_uop_mem_size : issue_slots_13_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_mem_cmd = _T_193 ? issue_slots_15_out_uop_mem_cmd : _T_192 ? issue_slots_14_out_uop_mem_cmd : issue_slots_13_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_exc_cause = _T_193 ? issue_slots_15_out_uop_exc_cause : _T_192 ? issue_slots_14_out_uop_exc_cause : issue_slots_13_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_exception = _T_193 ? issue_slots_15_out_uop_exception : _T_192 ? issue_slots_14_out_uop_exception : issue_slots_13_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_stale_pdst = _T_193 ? issue_slots_15_out_uop_stale_pdst : _T_192 ? issue_slots_14_out_uop_stale_pdst : issue_slots_13_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_ppred_busy = _T_193 ? issue_slots_15_out_uop_ppred_busy : _T_192 ? issue_slots_14_out_uop_ppred_busy : issue_slots_13_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_prs3_busy = _T_193 ? issue_slots_15_out_uop_prs3_busy : _T_192 ? issue_slots_14_out_uop_prs3_busy : issue_slots_13_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_prs2_busy = _T_193 ? issue_slots_15_out_uop_prs2_busy : _T_192 ? issue_slots_14_out_uop_prs2_busy : issue_slots_13_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_prs1_busy = _T_193 ? issue_slots_15_out_uop_prs1_busy : _T_192 ? issue_slots_14_out_uop_prs1_busy : issue_slots_13_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_ppred = _T_193 ? issue_slots_15_out_uop_ppred : _T_192 ? issue_slots_14_out_uop_ppred : issue_slots_13_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_prs3 = _T_193 ? issue_slots_15_out_uop_prs3 : _T_192 ? issue_slots_14_out_uop_prs3 : issue_slots_13_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_prs2 = _T_193 ? issue_slots_15_out_uop_prs2 : _T_192 ? issue_slots_14_out_uop_prs2 : issue_slots_13_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_prs1 = _T_193 ? issue_slots_15_out_uop_prs1 : _T_192 ? issue_slots_14_out_uop_prs1 : issue_slots_13_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_pdst = _T_193 ? issue_slots_15_out_uop_pdst : _T_192 ? issue_slots_14_out_uop_pdst : issue_slots_13_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_rxq_idx = _T_193 ? issue_slots_15_out_uop_rxq_idx : _T_192 ? issue_slots_14_out_uop_rxq_idx : issue_slots_13_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_stq_idx = _T_193 ? issue_slots_15_out_uop_stq_idx : _T_192 ? issue_slots_14_out_uop_stq_idx : issue_slots_13_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_ldq_idx = _T_193 ? issue_slots_15_out_uop_ldq_idx : _T_192 ? issue_slots_14_out_uop_ldq_idx : issue_slots_13_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_rob_idx = _T_193 ? issue_slots_15_out_uop_rob_idx : _T_192 ? issue_slots_14_out_uop_rob_idx : issue_slots_13_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_vec = _T_193 ? issue_slots_15_out_uop_fp_ctrl_vec : _T_192 ? issue_slots_14_out_uop_fp_ctrl_vec : issue_slots_13_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_wflags = _T_193 ? issue_slots_15_out_uop_fp_ctrl_wflags : _T_192 ? issue_slots_14_out_uop_fp_ctrl_wflags : issue_slots_13_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_sqrt = _T_193 ? issue_slots_15_out_uop_fp_ctrl_sqrt : _T_192 ? issue_slots_14_out_uop_fp_ctrl_sqrt : issue_slots_13_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_div = _T_193 ? issue_slots_15_out_uop_fp_ctrl_div : _T_192 ? issue_slots_14_out_uop_fp_ctrl_div : issue_slots_13_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_fma = _T_193 ? issue_slots_15_out_uop_fp_ctrl_fma : _T_192 ? issue_slots_14_out_uop_fp_ctrl_fma : issue_slots_13_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_fastpipe = _T_193 ? issue_slots_15_out_uop_fp_ctrl_fastpipe : _T_192 ? issue_slots_14_out_uop_fp_ctrl_fastpipe : issue_slots_13_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_toint = _T_193 ? issue_slots_15_out_uop_fp_ctrl_toint : _T_192 ? issue_slots_14_out_uop_fp_ctrl_toint : issue_slots_13_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_fromint = _T_193 ? issue_slots_15_out_uop_fp_ctrl_fromint : _T_192 ? issue_slots_14_out_uop_fp_ctrl_fromint : issue_slots_13_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_typeTagOut = _T_193 ? issue_slots_15_out_uop_fp_ctrl_typeTagOut : _T_192 ? issue_slots_14_out_uop_fp_ctrl_typeTagOut : issue_slots_13_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_typeTagIn = _T_193 ? issue_slots_15_out_uop_fp_ctrl_typeTagIn : _T_192 ? issue_slots_14_out_uop_fp_ctrl_typeTagIn : issue_slots_13_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_swap23 = _T_193 ? issue_slots_15_out_uop_fp_ctrl_swap23 : _T_192 ? issue_slots_14_out_uop_fp_ctrl_swap23 : issue_slots_13_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_swap12 = _T_193 ? issue_slots_15_out_uop_fp_ctrl_swap12 : _T_192 ? issue_slots_14_out_uop_fp_ctrl_swap12 : issue_slots_13_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_ren3 = _T_193 ? issue_slots_15_out_uop_fp_ctrl_ren3 : _T_192 ? issue_slots_14_out_uop_fp_ctrl_ren3 : issue_slots_13_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_ren2 = _T_193 ? issue_slots_15_out_uop_fp_ctrl_ren2 : _T_192 ? issue_slots_14_out_uop_fp_ctrl_ren2 : issue_slots_13_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_ren1 = _T_193 ? issue_slots_15_out_uop_fp_ctrl_ren1 : _T_192 ? issue_slots_14_out_uop_fp_ctrl_ren1 : issue_slots_13_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_wen = _T_193 ? issue_slots_15_out_uop_fp_ctrl_wen : _T_192 ? issue_slots_14_out_uop_fp_ctrl_wen : issue_slots_13_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_ldst = _T_193 ? issue_slots_15_out_uop_fp_ctrl_ldst : _T_192 ? issue_slots_14_out_uop_fp_ctrl_ldst : issue_slots_13_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_op2_sel = _T_193 ? issue_slots_15_out_uop_op2_sel : _T_192 ? issue_slots_14_out_uop_op2_sel : issue_slots_13_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_op1_sel = _T_193 ? issue_slots_15_out_uop_op1_sel : _T_192 ? issue_slots_14_out_uop_op1_sel : issue_slots_13_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_imm_packed = _T_193 ? issue_slots_15_out_uop_imm_packed : _T_192 ? issue_slots_14_out_uop_imm_packed : issue_slots_13_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_pimm = _T_193 ? issue_slots_15_out_uop_pimm : _T_192 ? issue_slots_14_out_uop_pimm : issue_slots_13_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_imm_sel = _T_193 ? issue_slots_15_out_uop_imm_sel : _T_192 ? issue_slots_14_out_uop_imm_sel : issue_slots_13_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_imm_rename = _T_193 ? issue_slots_15_out_uop_imm_rename : _T_192 ? issue_slots_14_out_uop_imm_rename : issue_slots_13_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_taken = _T_193 ? issue_slots_15_out_uop_taken : _T_192 ? issue_slots_14_out_uop_taken : issue_slots_13_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_pc_lob = _T_193 ? issue_slots_15_out_uop_pc_lob : _T_192 ? issue_slots_14_out_uop_pc_lob : issue_slots_13_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_edge_inst = _T_193 ? issue_slots_15_out_uop_edge_inst : _T_192 ? issue_slots_14_out_uop_edge_inst : issue_slots_13_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_ftq_idx = _T_193 ? issue_slots_15_out_uop_ftq_idx : _T_192 ? issue_slots_14_out_uop_ftq_idx : issue_slots_13_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_mov = _T_193 ? issue_slots_15_out_uop_is_mov : _T_192 ? issue_slots_14_out_uop_is_mov : issue_slots_13_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_rocc = _T_193 ? issue_slots_15_out_uop_is_rocc : _T_192 ? issue_slots_14_out_uop_is_rocc : issue_slots_13_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_sys_pc2epc = _T_193 ? issue_slots_15_out_uop_is_sys_pc2epc : _T_192 ? issue_slots_14_out_uop_is_sys_pc2epc : issue_slots_13_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_eret = _T_193 ? issue_slots_15_out_uop_is_eret : _T_192 ? issue_slots_14_out_uop_is_eret : issue_slots_13_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_amo = _T_193 ? issue_slots_15_out_uop_is_amo : _T_192 ? issue_slots_14_out_uop_is_amo : issue_slots_13_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_sfence = _T_193 ? issue_slots_15_out_uop_is_sfence : _T_192 ? issue_slots_14_out_uop_is_sfence : issue_slots_13_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_fencei = _T_193 ? issue_slots_15_out_uop_is_fencei : _T_192 ? issue_slots_14_out_uop_is_fencei : issue_slots_13_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_fence = _T_193 ? issue_slots_15_out_uop_is_fence : _T_192 ? issue_slots_14_out_uop_is_fence : issue_slots_13_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_sfb = _T_193 ? issue_slots_15_out_uop_is_sfb : _T_192 ? issue_slots_14_out_uop_is_sfb : issue_slots_13_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_br_type = _T_193 ? issue_slots_15_out_uop_br_type : _T_192 ? issue_slots_14_out_uop_br_type : issue_slots_13_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_br_tag = _T_193 ? issue_slots_15_out_uop_br_tag : _T_192 ? issue_slots_14_out_uop_br_tag : issue_slots_13_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_br_mask = _T_193 ? issue_slots_15_out_uop_br_mask : _T_192 ? issue_slots_14_out_uop_br_mask : issue_slots_13_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_dis_col_sel = _T_193 ? issue_slots_15_out_uop_dis_col_sel : _T_192 ? issue_slots_14_out_uop_dis_col_sel : issue_slots_13_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iw_p3_bypass_hint = _T_193 ? issue_slots_15_out_uop_iw_p3_bypass_hint : _T_192 ? issue_slots_14_out_uop_iw_p3_bypass_hint : issue_slots_13_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iw_p2_bypass_hint = _T_193 ? issue_slots_15_out_uop_iw_p2_bypass_hint : _T_192 ? issue_slots_14_out_uop_iw_p2_bypass_hint : issue_slots_13_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iw_p1_bypass_hint = _T_193 ? issue_slots_15_out_uop_iw_p1_bypass_hint : _T_192 ? issue_slots_14_out_uop_iw_p1_bypass_hint : issue_slots_13_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iw_issued = _T_193 ? issue_slots_15_out_uop_iw_issued : _T_192 ? issue_slots_14_out_uop_iw_issued : issue_slots_13_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_0 = _T_193 ? issue_slots_15_out_uop_fu_code_0 : _T_192 ? issue_slots_14_out_uop_fu_code_0 : issue_slots_13_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_1 = _T_193 ? issue_slots_15_out_uop_fu_code_1 : _T_192 ? issue_slots_14_out_uop_fu_code_1 : issue_slots_13_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_2 = _T_193 ? issue_slots_15_out_uop_fu_code_2 : _T_192 ? issue_slots_14_out_uop_fu_code_2 : issue_slots_13_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_3 = _T_193 ? issue_slots_15_out_uop_fu_code_3 : _T_192 ? issue_slots_14_out_uop_fu_code_3 : issue_slots_13_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_4 = _T_193 ? issue_slots_15_out_uop_fu_code_4 : _T_192 ? issue_slots_14_out_uop_fu_code_4 : issue_slots_13_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_5 = _T_193 ? issue_slots_15_out_uop_fu_code_5 : _T_192 ? issue_slots_14_out_uop_fu_code_5 : issue_slots_13_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_6 = _T_193 ? issue_slots_15_out_uop_fu_code_6 : _T_192 ? issue_slots_14_out_uop_fu_code_6 : issue_slots_13_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_7 = _T_193 ? issue_slots_15_out_uop_fu_code_7 : _T_192 ? issue_slots_14_out_uop_fu_code_7 : issue_slots_13_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_8 = _T_193 ? issue_slots_15_out_uop_fu_code_8 : _T_192 ? issue_slots_14_out_uop_fu_code_8 : issue_slots_13_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_9 = _T_193 ? issue_slots_15_out_uop_fu_code_9 : _T_192 ? issue_slots_14_out_uop_fu_code_9 : issue_slots_13_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iq_type_0 = _T_193 ? issue_slots_15_out_uop_iq_type_0 : _T_192 ? issue_slots_14_out_uop_iq_type_0 : issue_slots_13_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iq_type_1 = _T_193 ? issue_slots_15_out_uop_iq_type_1 : _T_192 ? issue_slots_14_out_uop_iq_type_1 : issue_slots_13_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iq_type_2 = _T_193 ? issue_slots_15_out_uop_iq_type_2 : _T_192 ? issue_slots_14_out_uop_iq_type_2 : issue_slots_13_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iq_type_3 = _T_193 ? issue_slots_15_out_uop_iq_type_3 : _T_192 ? issue_slots_14_out_uop_iq_type_3 : issue_slots_13_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_debug_pc = _T_193 ? issue_slots_15_out_uop_debug_pc : _T_192 ? issue_slots_14_out_uop_debug_pc : issue_slots_13_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_rvc = _T_193 ? issue_slots_15_out_uop_is_rvc : _T_192 ? issue_slots_14_out_uop_is_rvc : issue_slots_13_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_debug_inst = _T_193 ? issue_slots_15_out_uop_debug_inst : _T_192 ? issue_slots_14_out_uop_debug_inst : issue_slots_13_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_inst = _T_193 ? issue_slots_15_out_uop_inst : _T_192 ? issue_slots_14_out_uop_inst : issue_slots_13_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_12_clear_T = \|shamts_oh_12; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_12_clear = _issue_slots_12_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_195 = shamts_oh_15 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_196 = shamts_oh_16 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_13_in_uop_valid = _T_196 ? issue_slots_16_will_be_valid : _T_195 ? issue_slots_15_will_be_valid : shamts_oh_14 == 3'h1 & issue_slots_14_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_13_in_uop_bits_debug_tsrc = _T_196 ? issue_slots_16_out_uop_debug_tsrc : _T_195 ? issue_slots_15_out_uop_debug_tsrc : issue_slots_14_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_debug_fsrc = _T_196 ? issue_slots_16_out_uop_debug_fsrc : _T_195 ? issue_slots_15_out_uop_debug_fsrc : issue_slots_14_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_bp_xcpt_if = _T_196 ? issue_slots_16_out_uop_bp_xcpt_if : _T_195 ? issue_slots_15_out_uop_bp_xcpt_if : issue_slots_14_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_bp_debug_if = _T_196 ? issue_slots_16_out_uop_bp_debug_if : _T_195 ? issue_slots_15_out_uop_bp_debug_if : issue_slots_14_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_xcpt_ma_if = _T_196 ? issue_slots_16_out_uop_xcpt_ma_if : _T_195 ? issue_slots_15_out_uop_xcpt_ma_if : issue_slots_14_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_xcpt_ae_if = _T_196 ? issue_slots_16_out_uop_xcpt_ae_if : _T_195 ? issue_slots_15_out_uop_xcpt_ae_if : issue_slots_14_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_xcpt_pf_if = _T_196 ? issue_slots_16_out_uop_xcpt_pf_if : _T_195 ? issue_slots_15_out_uop_xcpt_pf_if : issue_slots_14_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_typ = _T_196 ? issue_slots_16_out_uop_fp_typ : _T_195 ? issue_slots_15_out_uop_fp_typ : issue_slots_14_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_rm = _T_196 ? issue_slots_16_out_uop_fp_rm : _T_195 ? issue_slots_15_out_uop_fp_rm : issue_slots_14_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_val = _T_196 ? issue_slots_16_out_uop_fp_val : _T_195 ? issue_slots_15_out_uop_fp_val : issue_slots_14_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fcn_op = _T_196 ? issue_slots_16_out_uop_fcn_op : _T_195 ? issue_slots_15_out_uop_fcn_op : issue_slots_14_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fcn_dw = _T_196 ? issue_slots_16_out_uop_fcn_dw : _T_195 ? issue_slots_15_out_uop_fcn_dw : issue_slots_14_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_frs3_en = _T_196 ? issue_slots_16_out_uop_frs3_en : _T_195 ? issue_slots_15_out_uop_frs3_en : issue_slots_14_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_lrs2_rtype = _T_196 ? issue_slots_16_out_uop_lrs2_rtype : _T_195 ? issue_slots_15_out_uop_lrs2_rtype : issue_slots_14_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_lrs1_rtype = _T_196 ? issue_slots_16_out_uop_lrs1_rtype : _T_195 ? issue_slots_15_out_uop_lrs1_rtype : issue_slots_14_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_dst_rtype = _T_196 ? issue_slots_16_out_uop_dst_rtype : _T_195 ? issue_slots_15_out_uop_dst_rtype : issue_slots_14_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_lrs3 = _T_196 ? issue_slots_16_out_uop_lrs3 : _T_195 ? issue_slots_15_out_uop_lrs3 : issue_slots_14_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_lrs2 = _T_196 ? issue_slots_16_out_uop_lrs2 : _T_195 ? issue_slots_15_out_uop_lrs2 : issue_slots_14_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_lrs1 = _T_196 ? issue_slots_16_out_uop_lrs1 : _T_195 ? issue_slots_15_out_uop_lrs1 : issue_slots_14_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_ldst = _T_196 ? issue_slots_16_out_uop_ldst : _T_195 ? issue_slots_15_out_uop_ldst : issue_slots_14_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_ldst_is_rs1 = _T_196 ? issue_slots_16_out_uop_ldst_is_rs1 : _T_195 ? issue_slots_15_out_uop_ldst_is_rs1 : issue_slots_14_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_csr_cmd = _T_196 ? issue_slots_16_out_uop_csr_cmd : _T_195 ? issue_slots_15_out_uop_csr_cmd : issue_slots_14_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_flush_on_commit = _T_196 ? issue_slots_16_out_uop_flush_on_commit : _T_195 ? issue_slots_15_out_uop_flush_on_commit : issue_slots_14_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_unique = _T_196 ? issue_slots_16_out_uop_is_unique : _T_195 ? issue_slots_15_out_uop_is_unique : issue_slots_14_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_uses_stq = _T_196 ? issue_slots_16_out_uop_uses_stq : _T_195 ? issue_slots_15_out_uop_uses_stq : issue_slots_14_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_uses_ldq = _T_196 ? issue_slots_16_out_uop_uses_ldq : _T_195 ? issue_slots_15_out_uop_uses_ldq : issue_slots_14_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_mem_signed = _T_196 ? issue_slots_16_out_uop_mem_signed : _T_195 ? issue_slots_15_out_uop_mem_signed : issue_slots_14_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_mem_size = _T_196 ? issue_slots_16_out_uop_mem_size : _T_195 ? issue_slots_15_out_uop_mem_size : issue_slots_14_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_mem_cmd = _T_196 ? issue_slots_16_out_uop_mem_cmd : _T_195 ? issue_slots_15_out_uop_mem_cmd : issue_slots_14_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_exc_cause = _T_196 ? issue_slots_16_out_uop_exc_cause : _T_195 ? issue_slots_15_out_uop_exc_cause : issue_slots_14_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_exception = _T_196 ? issue_slots_16_out_uop_exception : _T_195 ? issue_slots_15_out_uop_exception : issue_slots_14_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_stale_pdst = _T_196 ? issue_slots_16_out_uop_stale_pdst : _T_195 ? issue_slots_15_out_uop_stale_pdst : issue_slots_14_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_ppred_busy = _T_196 ? issue_slots_16_out_uop_ppred_busy : _T_195 ? issue_slots_15_out_uop_ppred_busy : issue_slots_14_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_prs3_busy = _T_196 ? issue_slots_16_out_uop_prs3_busy : _T_195 ? issue_slots_15_out_uop_prs3_busy : issue_slots_14_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_prs2_busy = _T_196 ? issue_slots_16_out_uop_prs2_busy : _T_195 ? issue_slots_15_out_uop_prs2_busy : issue_slots_14_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_prs1_busy = _T_196 ? issue_slots_16_out_uop_prs1_busy : _T_195 ? issue_slots_15_out_uop_prs1_busy : issue_slots_14_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_ppred = _T_196 ? issue_slots_16_out_uop_ppred : _T_195 ? issue_slots_15_out_uop_ppred : issue_slots_14_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_prs3 = _T_196 ? issue_slots_16_out_uop_prs3 : _T_195 ? issue_slots_15_out_uop_prs3 : issue_slots_14_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_prs2 = _T_196 ? issue_slots_16_out_uop_prs2 : _T_195 ? issue_slots_15_out_uop_prs2 : issue_slots_14_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_prs1 = _T_196 ? issue_slots_16_out_uop_prs1 : _T_195 ? issue_slots_15_out_uop_prs1 : issue_slots_14_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_pdst = _T_196 ? issue_slots_16_out_uop_pdst : _T_195 ? issue_slots_15_out_uop_pdst : issue_slots_14_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_rxq_idx = _T_196 ? issue_slots_16_out_uop_rxq_idx : _T_195 ? issue_slots_15_out_uop_rxq_idx : issue_slots_14_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_stq_idx = _T_196 ? issue_slots_16_out_uop_stq_idx : _T_195 ? issue_slots_15_out_uop_stq_idx : issue_slots_14_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_ldq_idx = _T_196 ? issue_slots_16_out_uop_ldq_idx : _T_195 ? issue_slots_15_out_uop_ldq_idx : issue_slots_14_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_rob_idx = _T_196 ? issue_slots_16_out_uop_rob_idx : _T_195 ? issue_slots_15_out_uop_rob_idx : issue_slots_14_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_vec = _T_196 ? issue_slots_16_out_uop_fp_ctrl_vec : _T_195 ? issue_slots_15_out_uop_fp_ctrl_vec : issue_slots_14_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_wflags = _T_196 ? issue_slots_16_out_uop_fp_ctrl_wflags : _T_195 ? issue_slots_15_out_uop_fp_ctrl_wflags : issue_slots_14_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_sqrt = _T_196 ? issue_slots_16_out_uop_fp_ctrl_sqrt : _T_195 ? issue_slots_15_out_uop_fp_ctrl_sqrt : issue_slots_14_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_div = _T_196 ? issue_slots_16_out_uop_fp_ctrl_div : _T_195 ? issue_slots_15_out_uop_fp_ctrl_div : issue_slots_14_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_fma = _T_196 ? issue_slots_16_out_uop_fp_ctrl_fma : _T_195 ? issue_slots_15_out_uop_fp_ctrl_fma : issue_slots_14_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_fastpipe = _T_196 ? issue_slots_16_out_uop_fp_ctrl_fastpipe : _T_195 ? issue_slots_15_out_uop_fp_ctrl_fastpipe : issue_slots_14_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_toint = _T_196 ? issue_slots_16_out_uop_fp_ctrl_toint : _T_195 ? issue_slots_15_out_uop_fp_ctrl_toint : issue_slots_14_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_fromint = _T_196 ? issue_slots_16_out_uop_fp_ctrl_fromint : _T_195 ? issue_slots_15_out_uop_fp_ctrl_fromint : issue_slots_14_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_typeTagOut = _T_196 ? issue_slots_16_out_uop_fp_ctrl_typeTagOut : _T_195 ? issue_slots_15_out_uop_fp_ctrl_typeTagOut : issue_slots_14_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_typeTagIn = _T_196 ? issue_slots_16_out_uop_fp_ctrl_typeTagIn : _T_195 ? issue_slots_15_out_uop_fp_ctrl_typeTagIn : issue_slots_14_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_swap23 = _T_196 ? issue_slots_16_out_uop_fp_ctrl_swap23 : _T_195 ? issue_slots_15_out_uop_fp_ctrl_swap23 : issue_slots_14_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_swap12 = _T_196 ? issue_slots_16_out_uop_fp_ctrl_swap12 : _T_195 ? issue_slots_15_out_uop_fp_ctrl_swap12 : issue_slots_14_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_ren3 = _T_196 ? issue_slots_16_out_uop_fp_ctrl_ren3 : _T_195 ? issue_slots_15_out_uop_fp_ctrl_ren3 : issue_slots_14_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_ren2 = _T_196 ? issue_slots_16_out_uop_fp_ctrl_ren2 : _T_195 ? issue_slots_15_out_uop_fp_ctrl_ren2 : issue_slots_14_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_ren1 = _T_196 ? issue_slots_16_out_uop_fp_ctrl_ren1 : _T_195 ? issue_slots_15_out_uop_fp_ctrl_ren1 : issue_slots_14_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_wen = _T_196 ? issue_slots_16_out_uop_fp_ctrl_wen : _T_195 ? issue_slots_15_out_uop_fp_ctrl_wen : issue_slots_14_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_ldst = _T_196 ? issue_slots_16_out_uop_fp_ctrl_ldst : _T_195 ? issue_slots_15_out_uop_fp_ctrl_ldst : issue_slots_14_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_op2_sel = _T_196 ? issue_slots_16_out_uop_op2_sel : _T_195 ? issue_slots_15_out_uop_op2_sel : issue_slots_14_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_op1_sel = _T_196 ? issue_slots_16_out_uop_op1_sel : _T_195 ? issue_slots_15_out_uop_op1_sel : issue_slots_14_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_imm_packed = _T_196 ? issue_slots_16_out_uop_imm_packed : _T_195 ? issue_slots_15_out_uop_imm_packed : issue_slots_14_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_pimm = _T_196 ? issue_slots_16_out_uop_pimm : _T_195 ? issue_slots_15_out_uop_pimm : issue_slots_14_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_imm_sel = _T_196 ? issue_slots_16_out_uop_imm_sel : _T_195 ? issue_slots_15_out_uop_imm_sel : issue_slots_14_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_imm_rename = _T_196 ? issue_slots_16_out_uop_imm_rename : _T_195 ? issue_slots_15_out_uop_imm_rename : issue_slots_14_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_taken = _T_196 ? issue_slots_16_out_uop_taken : _T_195 ? issue_slots_15_out_uop_taken : issue_slots_14_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_pc_lob = _T_196 ? issue_slots_16_out_uop_pc_lob : _T_195 ? issue_slots_15_out_uop_pc_lob : issue_slots_14_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_edge_inst = _T_196 ? issue_slots_16_out_uop_edge_inst : _T_195 ? issue_slots_15_out_uop_edge_inst : issue_slots_14_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_ftq_idx = _T_196 ? issue_slots_16_out_uop_ftq_idx : _T_195 ? issue_slots_15_out_uop_ftq_idx : issue_slots_14_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_mov = _T_196 ? issue_slots_16_out_uop_is_mov : _T_195 ? issue_slots_15_out_uop_is_mov : issue_slots_14_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_rocc = _T_196 ? issue_slots_16_out_uop_is_rocc : _T_195 ? issue_slots_15_out_uop_is_rocc : issue_slots_14_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_sys_pc2epc = _T_196 ? issue_slots_16_out_uop_is_sys_pc2epc : _T_195 ? issue_slots_15_out_uop_is_sys_pc2epc : issue_slots_14_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_eret = _T_196 ? issue_slots_16_out_uop_is_eret : _T_195 ? issue_slots_15_out_uop_is_eret : issue_slots_14_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_amo = _T_196 ? issue_slots_16_out_uop_is_amo : _T_195 ? issue_slots_15_out_uop_is_amo : issue_slots_14_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_sfence = _T_196 ? issue_slots_16_out_uop_is_sfence : _T_195 ? issue_slots_15_out_uop_is_sfence : issue_slots_14_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_fencei = _T_196 ? issue_slots_16_out_uop_is_fencei : _T_195 ? issue_slots_15_out_uop_is_fencei : issue_slots_14_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_fence = _T_196 ? issue_slots_16_out_uop_is_fence : _T_195 ? issue_slots_15_out_uop_is_fence : issue_slots_14_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_sfb = _T_196 ? issue_slots_16_out_uop_is_sfb : _T_195 ? issue_slots_15_out_uop_is_sfb : issue_slots_14_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_br_type = _T_196 ? issue_slots_16_out_uop_br_type : _T_195 ? issue_slots_15_out_uop_br_type : issue_slots_14_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_br_tag = _T_196 ? issue_slots_16_out_uop_br_tag : _T_195 ? issue_slots_15_out_uop_br_tag : issue_slots_14_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_br_mask = _T_196 ? issue_slots_16_out_uop_br_mask : _T_195 ? issue_slots_15_out_uop_br_mask : issue_slots_14_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_dis_col_sel = _T_196 ? issue_slots_16_out_uop_dis_col_sel : _T_195 ? issue_slots_15_out_uop_dis_col_sel : issue_slots_14_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iw_p3_bypass_hint = _T_196 ? issue_slots_16_out_uop_iw_p3_bypass_hint : _T_195 ? issue_slots_15_out_uop_iw_p3_bypass_hint : issue_slots_14_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iw_p2_bypass_hint = _T_196 ? issue_slots_16_out_uop_iw_p2_bypass_hint : _T_195 ? issue_slots_15_out_uop_iw_p2_bypass_hint : issue_slots_14_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iw_p1_bypass_hint = _T_196 ? issue_slots_16_out_uop_iw_p1_bypass_hint : _T_195 ? issue_slots_15_out_uop_iw_p1_bypass_hint : issue_slots_14_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iw_issued = _T_196 ? issue_slots_16_out_uop_iw_issued : _T_195 ? issue_slots_15_out_uop_iw_issued : issue_slots_14_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_0 = _T_196 ? issue_slots_16_out_uop_fu_code_0 : _T_195 ? issue_slots_15_out_uop_fu_code_0 : issue_slots_14_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_1 = _T_196 ? issue_slots_16_out_uop_fu_code_1 : _T_195 ? issue_slots_15_out_uop_fu_code_1 : issue_slots_14_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_2 = _T_196 ? issue_slots_16_out_uop_fu_code_2 : _T_195 ? issue_slots_15_out_uop_fu_code_2 : issue_slots_14_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_3 = _T_196 ? issue_slots_16_out_uop_fu_code_3 : _T_195 ? issue_slots_15_out_uop_fu_code_3 : issue_slots_14_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_4 = _T_196 ? issue_slots_16_out_uop_fu_code_4 : _T_195 ? issue_slots_15_out_uop_fu_code_4 : issue_slots_14_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_5 = _T_196 ? issue_slots_16_out_uop_fu_code_5 : _T_195 ? issue_slots_15_out_uop_fu_code_5 : issue_slots_14_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_6 = _T_196 ? issue_slots_16_out_uop_fu_code_6 : _T_195 ? issue_slots_15_out_uop_fu_code_6 : issue_slots_14_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_7 = _T_196 ? issue_slots_16_out_uop_fu_code_7 : _T_195 ? issue_slots_15_out_uop_fu_code_7 : issue_slots_14_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_8 = _T_196 ? issue_slots_16_out_uop_fu_code_8 : _T_195 ? issue_slots_15_out_uop_fu_code_8 : issue_slots_14_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_9 = _T_196 ? issue_slots_16_out_uop_fu_code_9 : _T_195 ? issue_slots_15_out_uop_fu_code_9 : issue_slots_14_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iq_type_0 = _T_196 ? issue_slots_16_out_uop_iq_type_0 : _T_195 ? issue_slots_15_out_uop_iq_type_0 : issue_slots_14_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iq_type_1 = _T_196 ? issue_slots_16_out_uop_iq_type_1 : _T_195 ? issue_slots_15_out_uop_iq_type_1 : issue_slots_14_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iq_type_2 = _T_196 ? issue_slots_16_out_uop_iq_type_2 : _T_195 ? issue_slots_15_out_uop_iq_type_2 : issue_slots_14_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iq_type_3 = _T_196 ? issue_slots_16_out_uop_iq_type_3 : _T_195 ? issue_slots_15_out_uop_iq_type_3 : issue_slots_14_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_debug_pc = _T_196 ? issue_slots_16_out_uop_debug_pc : _T_195 ? issue_slots_15_out_uop_debug_pc : issue_slots_14_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_rvc = _T_196 ? issue_slots_16_out_uop_is_rvc : _T_195 ? issue_slots_15_out_uop_is_rvc : issue_slots_14_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_debug_inst = _T_196 ? issue_slots_16_out_uop_debug_inst : _T_195 ? issue_slots_15_out_uop_debug_inst : issue_slots_14_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_inst = _T_196 ? issue_slots_16_out_uop_inst : _T_195 ? issue_slots_15_out_uop_inst : issue_slots_14_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_13_clear_T = \|shamts_oh_13; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_13_clear = _issue_slots_13_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_198 = shamts_oh_16 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_199 = shamts_oh_17 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_14_in_uop_valid = _T_199 ? issue_slots_17_will_be_valid : _T_198 ? issue_slots_16_will_be_valid : shamts_oh_15 == 3'h1 & issue_slots_15_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_14_in_uop_bits_debug_tsrc = _T_199 ? issue_slots_17_out_uop_debug_tsrc : _T_198 ? issue_slots_16_out_uop_debug_tsrc : issue_slots_15_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_debug_fsrc = _T_199 ? issue_slots_17_out_uop_debug_fsrc : _T_198 ? issue_slots_16_out_uop_debug_fsrc : issue_slots_15_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_bp_xcpt_if = _T_199 ? issue_slots_17_out_uop_bp_xcpt_if : _T_198 ? issue_slots_16_out_uop_bp_xcpt_if : issue_slots_15_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_bp_debug_if = _T_199 ? issue_slots_17_out_uop_bp_debug_if : _T_198 ? issue_slots_16_out_uop_bp_debug_if : issue_slots_15_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_xcpt_ma_if = _T_199 ? issue_slots_17_out_uop_xcpt_ma_if : _T_198 ? issue_slots_16_out_uop_xcpt_ma_if : issue_slots_15_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_xcpt_ae_if = _T_199 ? issue_slots_17_out_uop_xcpt_ae_if : _T_198 ? issue_slots_16_out_uop_xcpt_ae_if : issue_slots_15_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_xcpt_pf_if = _T_199 ? issue_slots_17_out_uop_xcpt_pf_if : _T_198 ? issue_slots_16_out_uop_xcpt_pf_if : issue_slots_15_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_typ = _T_199 ? issue_slots_17_out_uop_fp_typ : _T_198 ? issue_slots_16_out_uop_fp_typ : issue_slots_15_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_rm = _T_199 ? issue_slots_17_out_uop_fp_rm : _T_198 ? issue_slots_16_out_uop_fp_rm : issue_slots_15_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_val = _T_199 ? issue_slots_17_out_uop_fp_val : _T_198 ? issue_slots_16_out_uop_fp_val : issue_slots_15_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fcn_op = _T_199 ? issue_slots_17_out_uop_fcn_op : _T_198 ? issue_slots_16_out_uop_fcn_op : issue_slots_15_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fcn_dw = _T_199 ? issue_slots_17_out_uop_fcn_dw : _T_198 ? issue_slots_16_out_uop_fcn_dw : issue_slots_15_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_frs3_en = _T_199 ? issue_slots_17_out_uop_frs3_en : _T_198 ? issue_slots_16_out_uop_frs3_en : issue_slots_15_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_lrs2_rtype = _T_199 ? issue_slots_17_out_uop_lrs2_rtype : _T_198 ? issue_slots_16_out_uop_lrs2_rtype : issue_slots_15_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_lrs1_rtype = _T_199 ? issue_slots_17_out_uop_lrs1_rtype : _T_198 ? issue_slots_16_out_uop_lrs1_rtype : issue_slots_15_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_dst_rtype = _T_199 ? issue_slots_17_out_uop_dst_rtype : _T_198 ? issue_slots_16_out_uop_dst_rtype : issue_slots_15_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_lrs3 = _T_199 ? issue_slots_17_out_uop_lrs3 : _T_198 ? issue_slots_16_out_uop_lrs3 : issue_slots_15_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_lrs2 = _T_199 ? issue_slots_17_out_uop_lrs2 : _T_198 ? issue_slots_16_out_uop_lrs2 : issue_slots_15_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_lrs1 = _T_199 ? issue_slots_17_out_uop_lrs1 : _T_198 ? issue_slots_16_out_uop_lrs1 : issue_slots_15_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_ldst = _T_199 ? issue_slots_17_out_uop_ldst : _T_198 ? issue_slots_16_out_uop_ldst : issue_slots_15_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_ldst_is_rs1 = _T_199 ? issue_slots_17_out_uop_ldst_is_rs1 : _T_198 ? issue_slots_16_out_uop_ldst_is_rs1 : issue_slots_15_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_csr_cmd = _T_199 ? issue_slots_17_out_uop_csr_cmd : _T_198 ? issue_slots_16_out_uop_csr_cmd : issue_slots_15_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_flush_on_commit = _T_199 ? issue_slots_17_out_uop_flush_on_commit : _T_198 ? issue_slots_16_out_uop_flush_on_commit : issue_slots_15_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_unique = _T_199 ? issue_slots_17_out_uop_is_unique : _T_198 ? issue_slots_16_out_uop_is_unique : issue_slots_15_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_uses_stq = _T_199 ? issue_slots_17_out_uop_uses_stq : _T_198 ? issue_slots_16_out_uop_uses_stq : issue_slots_15_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_uses_ldq = _T_199 ? issue_slots_17_out_uop_uses_ldq : _T_198 ? issue_slots_16_out_uop_uses_ldq : issue_slots_15_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_mem_signed = _T_199 ? issue_slots_17_out_uop_mem_signed : _T_198 ? issue_slots_16_out_uop_mem_signed : issue_slots_15_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_mem_size = _T_199 ? issue_slots_17_out_uop_mem_size : _T_198 ? issue_slots_16_out_uop_mem_size : issue_slots_15_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_mem_cmd = _T_199 ? issue_slots_17_out_uop_mem_cmd : _T_198 ? issue_slots_16_out_uop_mem_cmd : issue_slots_15_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_exc_cause = _T_199 ? issue_slots_17_out_uop_exc_cause : _T_198 ? issue_slots_16_out_uop_exc_cause : issue_slots_15_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_exception = _T_199 ? issue_slots_17_out_uop_exception : _T_198 ? issue_slots_16_out_uop_exception : issue_slots_15_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_stale_pdst = _T_199 ? issue_slots_17_out_uop_stale_pdst : _T_198 ? issue_slots_16_out_uop_stale_pdst : issue_slots_15_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_ppred_busy = _T_199 ? issue_slots_17_out_uop_ppred_busy : _T_198 ? issue_slots_16_out_uop_ppred_busy : issue_slots_15_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_prs3_busy = _T_199 ? issue_slots_17_out_uop_prs3_busy : _T_198 ? issue_slots_16_out_uop_prs3_busy : issue_slots_15_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_prs2_busy = _T_199 ? issue_slots_17_out_uop_prs2_busy : _T_198 ? issue_slots_16_out_uop_prs2_busy : issue_slots_15_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_prs1_busy = _T_199 ? issue_slots_17_out_uop_prs1_busy : _T_198 ? issue_slots_16_out_uop_prs1_busy : issue_slots_15_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_ppred = _T_199 ? issue_slots_17_out_uop_ppred : _T_198 ? issue_slots_16_out_uop_ppred : issue_slots_15_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_prs3 = _T_199 ? issue_slots_17_out_uop_prs3 : _T_198 ? issue_slots_16_out_uop_prs3 : issue_slots_15_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_prs2 = _T_199 ? issue_slots_17_out_uop_prs2 : _T_198 ? issue_slots_16_out_uop_prs2 : issue_slots_15_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_prs1 = _T_199 ? issue_slots_17_out_uop_prs1 : _T_198 ? issue_slots_16_out_uop_prs1 : issue_slots_15_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_pdst = _T_199 ? issue_slots_17_out_uop_pdst : _T_198 ? issue_slots_16_out_uop_pdst : issue_slots_15_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_rxq_idx = _T_199 ? issue_slots_17_out_uop_rxq_idx : _T_198 ? issue_slots_16_out_uop_rxq_idx : issue_slots_15_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_stq_idx = _T_199 ? issue_slots_17_out_uop_stq_idx : _T_198 ? issue_slots_16_out_uop_stq_idx : issue_slots_15_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_ldq_idx = _T_199 ? issue_slots_17_out_uop_ldq_idx : _T_198 ? issue_slots_16_out_uop_ldq_idx : issue_slots_15_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_rob_idx = _T_199 ? issue_slots_17_out_uop_rob_idx : _T_198 ? issue_slots_16_out_uop_rob_idx : issue_slots_15_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_vec = _T_199 ? issue_slots_17_out_uop_fp_ctrl_vec : _T_198 ? issue_slots_16_out_uop_fp_ctrl_vec : issue_slots_15_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_wflags = _T_199 ? issue_slots_17_out_uop_fp_ctrl_wflags : _T_198 ? issue_slots_16_out_uop_fp_ctrl_wflags : issue_slots_15_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_sqrt = _T_199 ? issue_slots_17_out_uop_fp_ctrl_sqrt : _T_198 ? issue_slots_16_out_uop_fp_ctrl_sqrt : issue_slots_15_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_div = _T_199 ? issue_slots_17_out_uop_fp_ctrl_div : _T_198 ? issue_slots_16_out_uop_fp_ctrl_div : issue_slots_15_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_fma = _T_199 ? issue_slots_17_out_uop_fp_ctrl_fma : _T_198 ? issue_slots_16_out_uop_fp_ctrl_fma : issue_slots_15_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_fastpipe = _T_199 ? issue_slots_17_out_uop_fp_ctrl_fastpipe : _T_198 ? issue_slots_16_out_uop_fp_ctrl_fastpipe : issue_slots_15_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_toint = _T_199 ? issue_slots_17_out_uop_fp_ctrl_toint : _T_198 ? issue_slots_16_out_uop_fp_ctrl_toint : issue_slots_15_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_fromint = _T_199 ? issue_slots_17_out_uop_fp_ctrl_fromint : _T_198 ? issue_slots_16_out_uop_fp_ctrl_fromint : issue_slots_15_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_typeTagOut = _T_199 ? issue_slots_17_out_uop_fp_ctrl_typeTagOut : _T_198 ? issue_slots_16_out_uop_fp_ctrl_typeTagOut : issue_slots_15_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_typeTagIn = _T_199 ? issue_slots_17_out_uop_fp_ctrl_typeTagIn : _T_198 ? issue_slots_16_out_uop_fp_ctrl_typeTagIn : issue_slots_15_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_swap23 = _T_199 ? issue_slots_17_out_uop_fp_ctrl_swap23 : _T_198 ? issue_slots_16_out_uop_fp_ctrl_swap23 : issue_slots_15_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_swap12 = _T_199 ? issue_slots_17_out_uop_fp_ctrl_swap12 : _T_198 ? issue_slots_16_out_uop_fp_ctrl_swap12 : issue_slots_15_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_ren3 = _T_199 ? issue_slots_17_out_uop_fp_ctrl_ren3 : _T_198 ? issue_slots_16_out_uop_fp_ctrl_ren3 : issue_slots_15_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_ren2 = _T_199 ? issue_slots_17_out_uop_fp_ctrl_ren2 : _T_198 ? issue_slots_16_out_uop_fp_ctrl_ren2 : issue_slots_15_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_ren1 = _T_199 ? issue_slots_17_out_uop_fp_ctrl_ren1 : _T_198 ? issue_slots_16_out_uop_fp_ctrl_ren1 : issue_slots_15_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_wen = _T_199 ? issue_slots_17_out_uop_fp_ctrl_wen : _T_198 ? issue_slots_16_out_uop_fp_ctrl_wen : issue_slots_15_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_ldst = _T_199 ? issue_slots_17_out_uop_fp_ctrl_ldst : _T_198 ? issue_slots_16_out_uop_fp_ctrl_ldst : issue_slots_15_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_op2_sel = _T_199 ? issue_slots_17_out_uop_op2_sel : _T_198 ? issue_slots_16_out_uop_op2_sel : issue_slots_15_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_op1_sel = _T_199 ? issue_slots_17_out_uop_op1_sel : _T_198 ? issue_slots_16_out_uop_op1_sel : issue_slots_15_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_imm_packed = _T_199 ? issue_slots_17_out_uop_imm_packed : _T_198 ? issue_slots_16_out_uop_imm_packed : issue_slots_15_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_pimm = _T_199 ? issue_slots_17_out_uop_pimm : _T_198 ? issue_slots_16_out_uop_pimm : issue_slots_15_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_imm_sel = _T_199 ? issue_slots_17_out_uop_imm_sel : _T_198 ? issue_slots_16_out_uop_imm_sel : issue_slots_15_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_imm_rename = _T_199 ? issue_slots_17_out_uop_imm_rename : _T_198 ? issue_slots_16_out_uop_imm_rename : issue_slots_15_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_taken = _T_199 ? issue_slots_17_out_uop_taken : _T_198 ? issue_slots_16_out_uop_taken : issue_slots_15_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_pc_lob = _T_199 ? issue_slots_17_out_uop_pc_lob : _T_198 ? issue_slots_16_out_uop_pc_lob : issue_slots_15_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_edge_inst = _T_199 ? issue_slots_17_out_uop_edge_inst : _T_198 ? issue_slots_16_out_uop_edge_inst : issue_slots_15_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_ftq_idx = _T_199 ? issue_slots_17_out_uop_ftq_idx : _T_198 ? issue_slots_16_out_uop_ftq_idx : issue_slots_15_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_mov = _T_199 ? issue_slots_17_out_uop_is_mov : _T_198 ? issue_slots_16_out_uop_is_mov : issue_slots_15_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_rocc = _T_199 ? issue_slots_17_out_uop_is_rocc : _T_198 ? issue_slots_16_out_uop_is_rocc : issue_slots_15_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_sys_pc2epc = _T_199 ? issue_slots_17_out_uop_is_sys_pc2epc : _T_198 ? issue_slots_16_out_uop_is_sys_pc2epc : issue_slots_15_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_eret = _T_199 ? issue_slots_17_out_uop_is_eret : _T_198 ? issue_slots_16_out_uop_is_eret : issue_slots_15_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_amo = _T_199 ? issue_slots_17_out_uop_is_amo : _T_198 ? issue_slots_16_out_uop_is_amo : issue_slots_15_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_sfence = _T_199 ? issue_slots_17_out_uop_is_sfence : _T_198 ? issue_slots_16_out_uop_is_sfence : issue_slots_15_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_fencei = _T_199 ? issue_slots_17_out_uop_is_fencei : _T_198 ? issue_slots_16_out_uop_is_fencei : issue_slots_15_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_fence = _T_199 ? issue_slots_17_out_uop_is_fence : _T_198 ? issue_slots_16_out_uop_is_fence : issue_slots_15_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_sfb = _T_199 ? issue_slots_17_out_uop_is_sfb : _T_198 ? issue_slots_16_out_uop_is_sfb : issue_slots_15_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_br_type = _T_199 ? issue_slots_17_out_uop_br_type : _T_198 ? issue_slots_16_out_uop_br_type : issue_slots_15_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_br_tag = _T_199 ? issue_slots_17_out_uop_br_tag : _T_198 ? issue_slots_16_out_uop_br_tag : issue_slots_15_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_br_mask = _T_199 ? issue_slots_17_out_uop_br_mask : _T_198 ? issue_slots_16_out_uop_br_mask : issue_slots_15_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_dis_col_sel = _T_199 ? issue_slots_17_out_uop_dis_col_sel : _T_198 ? issue_slots_16_out_uop_dis_col_sel : issue_slots_15_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iw_p3_bypass_hint = _T_199 ? issue_slots_17_out_uop_iw_p3_bypass_hint : _T_198 ? issue_slots_16_out_uop_iw_p3_bypass_hint : issue_slots_15_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iw_p2_bypass_hint = _T_199 ? issue_slots_17_out_uop_iw_p2_bypass_hint : _T_198 ? issue_slots_16_out_uop_iw_p2_bypass_hint : issue_slots_15_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iw_p1_bypass_hint = _T_199 ? issue_slots_17_out_uop_iw_p1_bypass_hint : _T_198 ? issue_slots_16_out_uop_iw_p1_bypass_hint : issue_slots_15_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iw_issued = _T_199 ? issue_slots_17_out_uop_iw_issued : _T_198 ? issue_slots_16_out_uop_iw_issued : issue_slots_15_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_0 = _T_199 ? issue_slots_17_out_uop_fu_code_0 : _T_198 ? issue_slots_16_out_uop_fu_code_0 : issue_slots_15_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_1 = _T_199 ? issue_slots_17_out_uop_fu_code_1 : _T_198 ? issue_slots_16_out_uop_fu_code_1 : issue_slots_15_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_2 = _T_199 ? issue_slots_17_out_uop_fu_code_2 : _T_198 ? issue_slots_16_out_uop_fu_code_2 : issue_slots_15_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_3 = _T_199 ? issue_slots_17_out_uop_fu_code_3 : _T_198 ? issue_slots_16_out_uop_fu_code_3 : issue_slots_15_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_4 = _T_199 ? issue_slots_17_out_uop_fu_code_4 : _T_198 ? issue_slots_16_out_uop_fu_code_4 : issue_slots_15_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_5 = _T_199 ? issue_slots_17_out_uop_fu_code_5 : _T_198 ? issue_slots_16_out_uop_fu_code_5 : issue_slots_15_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_6 = _T_199 ? issue_slots_17_out_uop_fu_code_6 : _T_198 ? issue_slots_16_out_uop_fu_code_6 : issue_slots_15_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_7 = _T_199 ? issue_slots_17_out_uop_fu_code_7 : _T_198 ? issue_slots_16_out_uop_fu_code_7 : issue_slots_15_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_8 = _T_199 ? issue_slots_17_out_uop_fu_code_8 : _T_198 ? issue_slots_16_out_uop_fu_code_8 : issue_slots_15_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_9 = _T_199 ? issue_slots_17_out_uop_fu_code_9 : _T_198 ? issue_slots_16_out_uop_fu_code_9 : issue_slots_15_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iq_type_0 = _T_199 ? issue_slots_17_out_uop_iq_type_0 : _T_198 ? issue_slots_16_out_uop_iq_type_0 : issue_slots_15_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iq_type_1 = _T_199 ? issue_slots_17_out_uop_iq_type_1 : _T_198 ? issue_slots_16_out_uop_iq_type_1 : issue_slots_15_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iq_type_2 = _T_199 ? issue_slots_17_out_uop_iq_type_2 : _T_198 ? issue_slots_16_out_uop_iq_type_2 : issue_slots_15_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iq_type_3 = _T_199 ? issue_slots_17_out_uop_iq_type_3 : _T_198 ? issue_slots_16_out_uop_iq_type_3 : issue_slots_15_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_debug_pc = _T_199 ? issue_slots_17_out_uop_debug_pc : _T_198 ? issue_slots_16_out_uop_debug_pc : issue_slots_15_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_rvc = _T_199 ? issue_slots_17_out_uop_is_rvc : _T_198 ? issue_slots_16_out_uop_is_rvc : issue_slots_15_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_debug_inst = _T_199 ? issue_slots_17_out_uop_debug_inst : _T_198 ? issue_slots_16_out_uop_debug_inst : issue_slots_15_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_inst = _T_199 ? issue_slots_17_out_uop_inst : _T_198 ? issue_slots_16_out_uop_inst : issue_slots_15_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_14_clear_T = \|shamts_oh_14; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_14_clear = _issue_slots_14_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_201 = shamts_oh_17 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_202 = shamts_oh_18 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_15_in_uop_valid = _T_202 ? issue_slots_18_will_be_valid : _T_201 ? issue_slots_17_will_be_valid : shamts_oh_16 == 3'h1 & issue_slots_16_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_15_in_uop_bits_debug_tsrc = _T_202 ? issue_slots_18_out_uop_debug_tsrc : _T_201 ? issue_slots_17_out_uop_debug_tsrc : issue_slots_16_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_debug_fsrc = _T_202 ? issue_slots_18_out_uop_debug_fsrc : _T_201 ? issue_slots_17_out_uop_debug_fsrc : issue_slots_16_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_bp_xcpt_if = _T_202 ? issue_slots_18_out_uop_bp_xcpt_if : _T_201 ? issue_slots_17_out_uop_bp_xcpt_if : issue_slots_16_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_bp_debug_if = _T_202 ? issue_slots_18_out_uop_bp_debug_if : _T_201 ? issue_slots_17_out_uop_bp_debug_if : issue_slots_16_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_xcpt_ma_if = _T_202 ? issue_slots_18_out_uop_xcpt_ma_if : _T_201 ? issue_slots_17_out_uop_xcpt_ma_if : issue_slots_16_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_xcpt_ae_if = _T_202 ? issue_slots_18_out_uop_xcpt_ae_if : _T_201 ? issue_slots_17_out_uop_xcpt_ae_if : issue_slots_16_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_xcpt_pf_if = _T_202 ? issue_slots_18_out_uop_xcpt_pf_if : _T_201 ? issue_slots_17_out_uop_xcpt_pf_if : issue_slots_16_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_typ = _T_202 ? issue_slots_18_out_uop_fp_typ : _T_201 ? issue_slots_17_out_uop_fp_typ : issue_slots_16_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_rm = _T_202 ? issue_slots_18_out_uop_fp_rm : _T_201 ? issue_slots_17_out_uop_fp_rm : issue_slots_16_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_val = _T_202 ? issue_slots_18_out_uop_fp_val : _T_201 ? issue_slots_17_out_uop_fp_val : issue_slots_16_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fcn_op = _T_202 ? issue_slots_18_out_uop_fcn_op : _T_201 ? issue_slots_17_out_uop_fcn_op : issue_slots_16_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fcn_dw = _T_202 ? issue_slots_18_out_uop_fcn_dw : _T_201 ? issue_slots_17_out_uop_fcn_dw : issue_slots_16_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_frs3_en = _T_202 ? issue_slots_18_out_uop_frs3_en : _T_201 ? issue_slots_17_out_uop_frs3_en : issue_slots_16_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_lrs2_rtype = _T_202 ? issue_slots_18_out_uop_lrs2_rtype : _T_201 ? issue_slots_17_out_uop_lrs2_rtype : issue_slots_16_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_lrs1_rtype = _T_202 ? issue_slots_18_out_uop_lrs1_rtype : _T_201 ? issue_slots_17_out_uop_lrs1_rtype : issue_slots_16_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_dst_rtype = _T_202 ? issue_slots_18_out_uop_dst_rtype : _T_201 ? issue_slots_17_out_uop_dst_rtype : issue_slots_16_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_lrs3 = _T_202 ? issue_slots_18_out_uop_lrs3 : _T_201 ? issue_slots_17_out_uop_lrs3 : issue_slots_16_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_lrs2 = _T_202 ? issue_slots_18_out_uop_lrs2 : _T_201 ? issue_slots_17_out_uop_lrs2 : issue_slots_16_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_lrs1 = _T_202 ? issue_slots_18_out_uop_lrs1 : _T_201 ? issue_slots_17_out_uop_lrs1 : issue_slots_16_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_ldst = _T_202 ? issue_slots_18_out_uop_ldst : _T_201 ? issue_slots_17_out_uop_ldst : issue_slots_16_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_ldst_is_rs1 = _T_202 ? issue_slots_18_out_uop_ldst_is_rs1 : _T_201 ? issue_slots_17_out_uop_ldst_is_rs1 : issue_slots_16_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_csr_cmd = _T_202 ? issue_slots_18_out_uop_csr_cmd : _T_201 ? issue_slots_17_out_uop_csr_cmd : issue_slots_16_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_flush_on_commit = _T_202 ? issue_slots_18_out_uop_flush_on_commit : _T_201 ? issue_slots_17_out_uop_flush_on_commit : issue_slots_16_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_unique = _T_202 ? issue_slots_18_out_uop_is_unique : _T_201 ? issue_slots_17_out_uop_is_unique : issue_slots_16_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_uses_stq = _T_202 ? issue_slots_18_out_uop_uses_stq : _T_201 ? issue_slots_17_out_uop_uses_stq : issue_slots_16_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_uses_ldq = _T_202 ? issue_slots_18_out_uop_uses_ldq : _T_201 ? issue_slots_17_out_uop_uses_ldq : issue_slots_16_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_mem_signed = _T_202 ? issue_slots_18_out_uop_mem_signed : _T_201 ? issue_slots_17_out_uop_mem_signed : issue_slots_16_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_mem_size = _T_202 ? issue_slots_18_out_uop_mem_size : _T_201 ? issue_slots_17_out_uop_mem_size : issue_slots_16_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_mem_cmd = _T_202 ? issue_slots_18_out_uop_mem_cmd : _T_201 ? issue_slots_17_out_uop_mem_cmd : issue_slots_16_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_exc_cause = _T_202 ? issue_slots_18_out_uop_exc_cause : _T_201 ? issue_slots_17_out_uop_exc_cause : issue_slots_16_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_exception = _T_202 ? issue_slots_18_out_uop_exception : _T_201 ? issue_slots_17_out_uop_exception : issue_slots_16_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_stale_pdst = _T_202 ? issue_slots_18_out_uop_stale_pdst : _T_201 ? issue_slots_17_out_uop_stale_pdst : issue_slots_16_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_ppred_busy = _T_202 ? issue_slots_18_out_uop_ppred_busy : _T_201 ? issue_slots_17_out_uop_ppred_busy : issue_slots_16_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_prs3_busy = _T_202 ? issue_slots_18_out_uop_prs3_busy : _T_201 ? issue_slots_17_out_uop_prs3_busy : issue_slots_16_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_prs2_busy = _T_202 ? issue_slots_18_out_uop_prs2_busy : _T_201 ? issue_slots_17_out_uop_prs2_busy : issue_slots_16_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_prs1_busy = _T_202 ? issue_slots_18_out_uop_prs1_busy : _T_201 ? issue_slots_17_out_uop_prs1_busy : issue_slots_16_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_ppred = _T_202 ? issue_slots_18_out_uop_ppred : _T_201 ? issue_slots_17_out_uop_ppred : issue_slots_16_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_prs3 = _T_202 ? issue_slots_18_out_uop_prs3 : _T_201 ? issue_slots_17_out_uop_prs3 : issue_slots_16_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_prs2 = _T_202 ? issue_slots_18_out_uop_prs2 : _T_201 ? issue_slots_17_out_uop_prs2 : issue_slots_16_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_prs1 = _T_202 ? issue_slots_18_out_uop_prs1 : _T_201 ? issue_slots_17_out_uop_prs1 : issue_slots_16_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_pdst = _T_202 ? issue_slots_18_out_uop_pdst : _T_201 ? issue_slots_17_out_uop_pdst : issue_slots_16_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_rxq_idx = _T_202 ? issue_slots_18_out_uop_rxq_idx : _T_201 ? issue_slots_17_out_uop_rxq_idx : issue_slots_16_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_stq_idx = _T_202 ? issue_slots_18_out_uop_stq_idx : _T_201 ? issue_slots_17_out_uop_stq_idx : issue_slots_16_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_ldq_idx = _T_202 ? issue_slots_18_out_uop_ldq_idx : _T_201 ? issue_slots_17_out_uop_ldq_idx : issue_slots_16_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_rob_idx = _T_202 ? issue_slots_18_out_uop_rob_idx : _T_201 ? issue_slots_17_out_uop_rob_idx : issue_slots_16_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_vec = _T_202 ? issue_slots_18_out_uop_fp_ctrl_vec : _T_201 ? issue_slots_17_out_uop_fp_ctrl_vec : issue_slots_16_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_wflags = _T_202 ? issue_slots_18_out_uop_fp_ctrl_wflags : _T_201 ? issue_slots_17_out_uop_fp_ctrl_wflags : issue_slots_16_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_sqrt = _T_202 ? issue_slots_18_out_uop_fp_ctrl_sqrt : _T_201 ? issue_slots_17_out_uop_fp_ctrl_sqrt : issue_slots_16_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_div = _T_202 ? issue_slots_18_out_uop_fp_ctrl_div : _T_201 ? issue_slots_17_out_uop_fp_ctrl_div : issue_slots_16_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_fma = _T_202 ? issue_slots_18_out_uop_fp_ctrl_fma : _T_201 ? issue_slots_17_out_uop_fp_ctrl_fma : issue_slots_16_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_fastpipe = _T_202 ? issue_slots_18_out_uop_fp_ctrl_fastpipe : _T_201 ? issue_slots_17_out_uop_fp_ctrl_fastpipe : issue_slots_16_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_toint = _T_202 ? issue_slots_18_out_uop_fp_ctrl_toint : _T_201 ? issue_slots_17_out_uop_fp_ctrl_toint : issue_slots_16_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_fromint = _T_202 ? issue_slots_18_out_uop_fp_ctrl_fromint : _T_201 ? issue_slots_17_out_uop_fp_ctrl_fromint : issue_slots_16_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_typeTagOut = _T_202 ? issue_slots_18_out_uop_fp_ctrl_typeTagOut : _T_201 ? issue_slots_17_out_uop_fp_ctrl_typeTagOut : issue_slots_16_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_typeTagIn = _T_202 ? issue_slots_18_out_uop_fp_ctrl_typeTagIn : _T_201 ? issue_slots_17_out_uop_fp_ctrl_typeTagIn : issue_slots_16_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_swap23 = _T_202 ? issue_slots_18_out_uop_fp_ctrl_swap23 : _T_201 ? issue_slots_17_out_uop_fp_ctrl_swap23 : issue_slots_16_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_swap12 = _T_202 ? issue_slots_18_out_uop_fp_ctrl_swap12 : _T_201 ? issue_slots_17_out_uop_fp_ctrl_swap12 : issue_slots_16_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_ren3 = _T_202 ? issue_slots_18_out_uop_fp_ctrl_ren3 : _T_201 ? issue_slots_17_out_uop_fp_ctrl_ren3 : issue_slots_16_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_ren2 = _T_202 ? issue_slots_18_out_uop_fp_ctrl_ren2 : _T_201 ? issue_slots_17_out_uop_fp_ctrl_ren2 : issue_slots_16_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_ren1 = _T_202 ? issue_slots_18_out_uop_fp_ctrl_ren1 : _T_201 ? issue_slots_17_out_uop_fp_ctrl_ren1 : issue_slots_16_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_wen = _T_202 ? issue_slots_18_out_uop_fp_ctrl_wen : _T_201 ? issue_slots_17_out_uop_fp_ctrl_wen : issue_slots_16_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_ldst = _T_202 ? issue_slots_18_out_uop_fp_ctrl_ldst : _T_201 ? issue_slots_17_out_uop_fp_ctrl_ldst : issue_slots_16_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_op2_sel = _T_202 ? issue_slots_18_out_uop_op2_sel : _T_201 ? issue_slots_17_out_uop_op2_sel : issue_slots_16_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_op1_sel = _T_202 ? issue_slots_18_out_uop_op1_sel : _T_201 ? issue_slots_17_out_uop_op1_sel : issue_slots_16_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_imm_packed = _T_202 ? issue_slots_18_out_uop_imm_packed : _T_201 ? issue_slots_17_out_uop_imm_packed : issue_slots_16_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_pimm = _T_202 ? issue_slots_18_out_uop_pimm : _T_201 ? issue_slots_17_out_uop_pimm : issue_slots_16_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_imm_sel = _T_202 ? issue_slots_18_out_uop_imm_sel : _T_201 ? issue_slots_17_out_uop_imm_sel : issue_slots_16_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_imm_rename = _T_202 ? issue_slots_18_out_uop_imm_rename : _T_201 ? issue_slots_17_out_uop_imm_rename : issue_slots_16_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_taken = _T_202 ? issue_slots_18_out_uop_taken : _T_201 ? issue_slots_17_out_uop_taken : issue_slots_16_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_pc_lob = _T_202 ? issue_slots_18_out_uop_pc_lob : _T_201 ? issue_slots_17_out_uop_pc_lob : issue_slots_16_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_edge_inst = _T_202 ? issue_slots_18_out_uop_edge_inst : _T_201 ? issue_slots_17_out_uop_edge_inst : issue_slots_16_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_ftq_idx = _T_202 ? issue_slots_18_out_uop_ftq_idx : _T_201 ? issue_slots_17_out_uop_ftq_idx : issue_slots_16_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_mov = _T_202 ? issue_slots_18_out_uop_is_mov : _T_201 ? issue_slots_17_out_uop_is_mov : issue_slots_16_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_rocc = _T_202 ? issue_slots_18_out_uop_is_rocc : _T_201 ? issue_slots_17_out_uop_is_rocc : issue_slots_16_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_sys_pc2epc = _T_202 ? issue_slots_18_out_uop_is_sys_pc2epc : _T_201 ? issue_slots_17_out_uop_is_sys_pc2epc : issue_slots_16_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_eret = _T_202 ? issue_slots_18_out_uop_is_eret : _T_201 ? issue_slots_17_out_uop_is_eret : issue_slots_16_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_amo = _T_202 ? issue_slots_18_out_uop_is_amo : _T_201 ? issue_slots_17_out_uop_is_amo : issue_slots_16_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_sfence = _T_202 ? issue_slots_18_out_uop_is_sfence : _T_201 ? issue_slots_17_out_uop_is_sfence : issue_slots_16_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_fencei = _T_202 ? issue_slots_18_out_uop_is_fencei : _T_201 ? issue_slots_17_out_uop_is_fencei : issue_slots_16_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_fence = _T_202 ? issue_slots_18_out_uop_is_fence : _T_201 ? issue_slots_17_out_uop_is_fence : issue_slots_16_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_sfb = _T_202 ? issue_slots_18_out_uop_is_sfb : _T_201 ? issue_slots_17_out_uop_is_sfb : issue_slots_16_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_br_type = _T_202 ? issue_slots_18_out_uop_br_type : _T_201 ? issue_slots_17_out_uop_br_type : issue_slots_16_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_br_tag = _T_202 ? issue_slots_18_out_uop_br_tag : _T_201 ? issue_slots_17_out_uop_br_tag : issue_slots_16_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_br_mask = _T_202 ? issue_slots_18_out_uop_br_mask : _T_201 ? issue_slots_17_out_uop_br_mask : issue_slots_16_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_dis_col_sel = _T_202 ? issue_slots_18_out_uop_dis_col_sel : _T_201 ? issue_slots_17_out_uop_dis_col_sel : issue_slots_16_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_iw_p3_bypass_hint = _T_202 ? issue_slots_18_out_uop_iw_p3_bypass_hint : _T_201 ? issue_slots_17_out_uop_iw_p3_bypass_hint : issue_slots_16_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_iw_p2_bypass_hint = _T_202 ? issue_slots_18_out_uop_iw_p2_bypass_hint : _T_201 ? issue_slots_17_out_uop_iw_p2_bypass_hint : issue_slots_16_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_iw_p1_bypass_hint = _T_202 ? issue_slots_18_out_uop_iw_p1_bypass_hint : _T_201 ? issue_slots_17_out_uop_iw_p1_bypass_hint : issue_slots_16_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_iw_issued = _T_202 ? issue_slots_18_out_uop_iw_issued : _T_201 ? issue_slots_17_out_uop_iw_issued : issue_slots_16_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_0 = _T_202 ? issue_slots_18_out_uop_fu_code_0 : _T_201 ? issue_slots_17_out_uop_fu_code_0 : issue_slots_16_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_1 = _T_202 ? issue_slots_18_out_uop_fu_code_1 : _T_201 ? issue_slots_17_out_uop_fu_code_1 : issue_slots_16_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_2 = _T_202 ? issue_slots_18_out_uop_fu_code_2 : _T_201 ? issue_slots_17_out_uop_fu_code_2 : issue_slots_16_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_3 = _T_202 ? issue_slots_18_out_uop_fu_code_3 : _T_201 ? issue_slots_17_out_uop_fu_code_3 : issue_slots_16_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_4 = _T_202 ? issue_slots_18_out_uop_fu_code_4 : _T_201 ? issue_slots_17_out_uop_fu_code_4 : issue_slots_16_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_5 = _T_202 ? issue_slots_18_out_uop_fu_code_5 : _T_201 ? issue_slots_17_out_uop_fu_code_5 : issue_slots_16_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_6 = _T_202 ? issue_slots_18_out_uop_fu_code_6 : _T_201 ? issue_slots_17_out_uop_fu_code_6 : issue_slots_16_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_7 = _T_202 ? issue_slots_18_out_uop_fu_code_7 : _T_201 ? issue_slots_17_out_uop_fu_code_7 : issue_slots_16_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_8 = _T_202 ? issue_slots_18_out_uop_fu_code_8 : _T_201 ? issue_slots_17_out_uop_fu_code_8 : issue_slots_16_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_9 = _T_202 ? issue_slots_18_out_uop_fu_code_9 : _T_201 ? issue_slots_17_out_uop_fu_code_9 : issue_slots_16_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_iq_type_0 = _T_202 ? issue_slots_18_out_uop_iq_type_0 : _T_201 ? issue_slots_17_out_uop_iq_type_0 : issue_slots_16_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_iq_type_1 = _T_202 ? issue_slots_18_out_uop_iq_type_1 : _T_201 ? issue_slots_17_out_uop_iq_type_1 : issue_slots_16_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_iq_type_2 = _T_202 ? issue_slots_18_out_uop_iq_type_2 : _T_201 ? issue_slots_17_out_uop_iq_type_2 : issue_slots_16_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_iq_type_3 = _T_202 ? issue_slots_18_out_uop_iq_type_3 : _T_201 ? issue_slots_17_out_uop_iq_type_3 : issue_slots_16_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_debug_pc = _T_202 ? issue_slots_18_out_uop_debug_pc : _T_201 ? issue_slots_17_out_uop_debug_pc : issue_slots_16_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_rvc = _T_202 ? issue_slots_18_out_uop_is_rvc : _T_201 ? issue_slots_17_out_uop_is_rvc : issue_slots_16_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_debug_inst = _T_202 ? issue_slots_18_out_uop_debug_inst : _T_201 ? issue_slots_17_out_uop_debug_inst : issue_slots_16_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_inst = _T_202 ? issue_slots_18_out_uop_inst : _T_201 ? issue_slots_17_out_uop_inst : issue_slots_16_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_15_clear_T = \|shamts_oh_15; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_15_clear = _issue_slots_15_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_204 = shamts_oh_18 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_205 = shamts_oh_19 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_16_in_uop_valid = _T_205 ? issue_slots_19_will_be_valid : _T_204 ? issue_slots_18_will_be_valid : shamts_oh_17 == 3'h1 & issue_slots_17_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_16_in_uop_bits_debug_tsrc = _T_205 ? issue_slots_19_out_uop_debug_tsrc : _T_204 ? issue_slots_18_out_uop_debug_tsrc : issue_slots_17_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_debug_fsrc = _T_205 ? issue_slots_19_out_uop_debug_fsrc : _T_204 ? issue_slots_18_out_uop_debug_fsrc : issue_slots_17_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_bp_xcpt_if = _T_205 ? issue_slots_19_out_uop_bp_xcpt_if : _T_204 ? issue_slots_18_out_uop_bp_xcpt_if : issue_slots_17_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_bp_debug_if = _T_205 ? issue_slots_19_out_uop_bp_debug_if : _T_204 ? issue_slots_18_out_uop_bp_debug_if : issue_slots_17_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_xcpt_ma_if = _T_205 ? issue_slots_19_out_uop_xcpt_ma_if : _T_204 ? issue_slots_18_out_uop_xcpt_ma_if : issue_slots_17_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_xcpt_ae_if = _T_205 ? issue_slots_19_out_uop_xcpt_ae_if : _T_204 ? issue_slots_18_out_uop_xcpt_ae_if : issue_slots_17_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_xcpt_pf_if = _T_205 ? issue_slots_19_out_uop_xcpt_pf_if : _T_204 ? issue_slots_18_out_uop_xcpt_pf_if : issue_slots_17_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_typ = _T_205 ? issue_slots_19_out_uop_fp_typ : _T_204 ? issue_slots_18_out_uop_fp_typ : issue_slots_17_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_rm = _T_205 ? issue_slots_19_out_uop_fp_rm : _T_204 ? issue_slots_18_out_uop_fp_rm : issue_slots_17_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_val = _T_205 ? issue_slots_19_out_uop_fp_val : _T_204 ? issue_slots_18_out_uop_fp_val : issue_slots_17_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fcn_op = _T_205 ? issue_slots_19_out_uop_fcn_op : _T_204 ? issue_slots_18_out_uop_fcn_op : issue_slots_17_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fcn_dw = _T_205 ? issue_slots_19_out_uop_fcn_dw : _T_204 ? issue_slots_18_out_uop_fcn_dw : issue_slots_17_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_frs3_en = _T_205 ? issue_slots_19_out_uop_frs3_en : _T_204 ? issue_slots_18_out_uop_frs3_en : issue_slots_17_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_lrs2_rtype = _T_205 ? issue_slots_19_out_uop_lrs2_rtype : _T_204 ? issue_slots_18_out_uop_lrs2_rtype : issue_slots_17_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_lrs1_rtype = _T_205 ? issue_slots_19_out_uop_lrs1_rtype : _T_204 ? issue_slots_18_out_uop_lrs1_rtype : issue_slots_17_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_dst_rtype = _T_205 ? issue_slots_19_out_uop_dst_rtype : _T_204 ? issue_slots_18_out_uop_dst_rtype : issue_slots_17_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_lrs3 = _T_205 ? issue_slots_19_out_uop_lrs3 : _T_204 ? issue_slots_18_out_uop_lrs3 : issue_slots_17_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_lrs2 = _T_205 ? issue_slots_19_out_uop_lrs2 : _T_204 ? issue_slots_18_out_uop_lrs2 : issue_slots_17_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_lrs1 = _T_205 ? issue_slots_19_out_uop_lrs1 : _T_204 ? issue_slots_18_out_uop_lrs1 : issue_slots_17_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_ldst = _T_205 ? issue_slots_19_out_uop_ldst : _T_204 ? issue_slots_18_out_uop_ldst : issue_slots_17_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_ldst_is_rs1 = _T_205 ? issue_slots_19_out_uop_ldst_is_rs1 : _T_204 ? issue_slots_18_out_uop_ldst_is_rs1 : issue_slots_17_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_csr_cmd = _T_205 ? issue_slots_19_out_uop_csr_cmd : _T_204 ? issue_slots_18_out_uop_csr_cmd : issue_slots_17_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_flush_on_commit = _T_205 ? issue_slots_19_out_uop_flush_on_commit : _T_204 ? issue_slots_18_out_uop_flush_on_commit : issue_slots_17_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_is_unique = _T_205 ? issue_slots_19_out_uop_is_unique : _T_204 ? issue_slots_18_out_uop_is_unique : issue_slots_17_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_uses_stq = _T_205 ? issue_slots_19_out_uop_uses_stq : _T_204 ? issue_slots_18_out_uop_uses_stq : issue_slots_17_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_uses_ldq = _T_205 ? issue_slots_19_out_uop_uses_ldq : _T_204 ? issue_slots_18_out_uop_uses_ldq : issue_slots_17_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_mem_signed = _T_205 ? issue_slots_19_out_uop_mem_signed : _T_204 ? issue_slots_18_out_uop_mem_signed : issue_slots_17_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_mem_size = _T_205 ? issue_slots_19_out_uop_mem_size : _T_204 ? issue_slots_18_out_uop_mem_size : issue_slots_17_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_mem_cmd = _T_205 ? issue_slots_19_out_uop_mem_cmd : _T_204 ? issue_slots_18_out_uop_mem_cmd : issue_slots_17_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_exc_cause = _T_205 ? issue_slots_19_out_uop_exc_cause : _T_204 ? issue_slots_18_out_uop_exc_cause : issue_slots_17_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_exception = _T_205 ? issue_slots_19_out_uop_exception : _T_204 ? issue_slots_18_out_uop_exception : issue_slots_17_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_stale_pdst = _T_205 ? issue_slots_19_out_uop_stale_pdst : _T_204 ? issue_slots_18_out_uop_stale_pdst : issue_slots_17_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_ppred_busy = _T_205 ? issue_slots_19_out_uop_ppred_busy : _T_204 ? issue_slots_18_out_uop_ppred_busy : issue_slots_17_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_prs3_busy = _T_205 ? issue_slots_19_out_uop_prs3_busy : _T_204 ? issue_slots_18_out_uop_prs3_busy : issue_slots_17_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_prs2_busy = _T_205 ? issue_slots_19_out_uop_prs2_busy : _T_204 ? issue_slots_18_out_uop_prs2_busy : issue_slots_17_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_prs1_busy = _T_205 ? issue_slots_19_out_uop_prs1_busy : _T_204 ? issue_slots_18_out_uop_prs1_busy : issue_slots_17_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_ppred = _T_205 ? issue_slots_19_out_uop_ppred : _T_204 ? issue_slots_18_out_uop_ppred : issue_slots_17_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_prs3 = _T_205 ? issue_slots_19_out_uop_prs3 : _T_204 ? issue_slots_18_out_uop_prs3 : issue_slots_17_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_prs2 = _T_205 ? issue_slots_19_out_uop_prs2 : _T_204 ? issue_slots_18_out_uop_prs2 : issue_slots_17_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_prs1 = _T_205 ? issue_slots_19_out_uop_prs1 : _T_204 ? issue_slots_18_out_uop_prs1 : issue_slots_17_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_pdst = _T_205 ? issue_slots_19_out_uop_pdst : _T_204 ? issue_slots_18_out_uop_pdst : issue_slots_17_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_rxq_idx = _T_205 ? issue_slots_19_out_uop_rxq_idx : _T_204 ? issue_slots_18_out_uop_rxq_idx : issue_slots_17_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_stq_idx = _T_205 ? issue_slots_19_out_uop_stq_idx : _T_204 ? issue_slots_18_out_uop_stq_idx : issue_slots_17_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_ldq_idx = _T_205 ? issue_slots_19_out_uop_ldq_idx : _T_204 ? issue_slots_18_out_uop_ldq_idx : issue_slots_17_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_rob_idx = _T_205 ? issue_slots_19_out_uop_rob_idx : _T_204 ? issue_slots_18_out_uop_rob_idx : issue_slots_17_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_vec = _T_205 ? issue_slots_19_out_uop_fp_ctrl_vec : _T_204 ? issue_slots_18_out_uop_fp_ctrl_vec : issue_slots_17_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_wflags = _T_205 ? issue_slots_19_out_uop_fp_ctrl_wflags : _T_204 ? issue_slots_18_out_uop_fp_ctrl_wflags : issue_slots_17_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_sqrt = _T_205 ? issue_slots_19_out_uop_fp_ctrl_sqrt : _T_204 ? issue_slots_18_out_uop_fp_ctrl_sqrt : issue_slots_17_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_div = _T_205 ? issue_slots_19_out_uop_fp_ctrl_div : _T_204 ? issue_slots_18_out_uop_fp_ctrl_div : issue_slots_17_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_fma = _T_205 ? issue_slots_19_out_uop_fp_ctrl_fma : _T_204 ? issue_slots_18_out_uop_fp_ctrl_fma : issue_slots_17_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_fastpipe = _T_205 ? issue_slots_19_out_uop_fp_ctrl_fastpipe : _T_204 ? issue_slots_18_out_uop_fp_ctrl_fastpipe : issue_slots_17_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_toint = _T_205 ? issue_slots_19_out_uop_fp_ctrl_toint : _T_204 ? issue_slots_18_out_uop_fp_ctrl_toint : issue_slots_17_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_fromint = _T_205 ? issue_slots_19_out_uop_fp_ctrl_fromint : _T_204 ? issue_slots_18_out_uop_fp_ctrl_fromint : issue_slots_17_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_typeTagOut = _T_205 ? issue_slots_19_out_uop_fp_ctrl_typeTagOut : _T_204 ? issue_slots_18_out_uop_fp_ctrl_typeTagOut : issue_slots_17_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_typeTagIn = _T_205 ? issue_slots_19_out_uop_fp_ctrl_typeTagIn : _T_204 ? issue_slots_18_out_uop_fp_ctrl_typeTagIn : issue_slots_17_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_swap23 = _T_205 ? issue_slots_19_out_uop_fp_ctrl_swap23 : _T_204 ? issue_slots_18_out_uop_fp_ctrl_swap23 : issue_slots_17_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_swap12 = _T_205 ? issue_slots_19_out_uop_fp_ctrl_swap12 : _T_204 ? issue_slots_18_out_uop_fp_ctrl_swap12 : issue_slots_17_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_ren3 = _T_205 ? issue_slots_19_out_uop_fp_ctrl_ren3 : _T_204 ? issue_slots_18_out_uop_fp_ctrl_ren3 : issue_slots_17_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_ren2 = _T_205 ? issue_slots_19_out_uop_fp_ctrl_ren2 : _T_204 ? issue_slots_18_out_uop_fp_ctrl_ren2 : issue_slots_17_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_ren1 = _T_205 ? issue_slots_19_out_uop_fp_ctrl_ren1 : _T_204 ? issue_slots_18_out_uop_fp_ctrl_ren1 : issue_slots_17_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_wen = _T_205 ? issue_slots_19_out_uop_fp_ctrl_wen : _T_204 ? issue_slots_18_out_uop_fp_ctrl_wen : issue_slots_17_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_ldst = _T_205 ? issue_slots_19_out_uop_fp_ctrl_ldst : _T_204 ? issue_slots_18_out_uop_fp_ctrl_ldst : issue_slots_17_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_op2_sel = _T_205 ? issue_slots_19_out_uop_op2_sel : _T_204 ? issue_slots_18_out_uop_op2_sel : issue_slots_17_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_op1_sel = _T_205 ? issue_slots_19_out_uop_op1_sel : _T_204 ? issue_slots_18_out_uop_op1_sel : issue_slots_17_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_imm_packed = _T_205 ? issue_slots_19_out_uop_imm_packed : _T_204 ? issue_slots_18_out_uop_imm_packed : issue_slots_17_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_pimm = _T_205 ? issue_slots_19_out_uop_pimm : _T_204 ? issue_slots_18_out_uop_pimm : issue_slots_17_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_imm_sel = _T_205 ? issue_slots_19_out_uop_imm_sel : _T_204 ? issue_slots_18_out_uop_imm_sel : issue_slots_17_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_imm_rename = _T_205 ? issue_slots_19_out_uop_imm_rename : _T_204 ? issue_slots_18_out_uop_imm_rename : issue_slots_17_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_taken = _T_205 ? issue_slots_19_out_uop_taken : _T_204 ? issue_slots_18_out_uop_taken : issue_slots_17_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_pc_lob = _T_205 ? issue_slots_19_out_uop_pc_lob : _T_204 ? issue_slots_18_out_uop_pc_lob : issue_slots_17_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_edge_inst = _T_205 ? issue_slots_19_out_uop_edge_inst : _T_204 ? issue_slots_18_out_uop_edge_inst : issue_slots_17_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_ftq_idx = _T_205 ? issue_slots_19_out_uop_ftq_idx : _T_204 ? issue_slots_18_out_uop_ftq_idx : issue_slots_17_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_is_mov = _T_205 ? issue_slots_19_out_uop_is_mov : _T_204 ? issue_slots_18_out_uop_is_mov : issue_slots_17_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_is_rocc = _T_205 ? issue_slots_19_out_uop_is_rocc : _T_204 ? issue_slots_18_out_uop_is_rocc : issue_slots_17_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_is_sys_pc2epc = _T_205 ? issue_slots_19_out_uop_is_sys_pc2epc : _T_204 ? issue_slots_18_out_uop_is_sys_pc2epc : issue_slots_17_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_is_eret = _T_205 ? issue_slots_19_out_uop_is_eret : _T_204 ? issue_slots_18_out_uop_is_eret : issue_slots_17_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_is_amo = _T_205 ? issue_slots_19_out_uop_is_amo : _T_204 ? issue_slots_18_out_uop_is_amo : issue_slots_17_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_is_sfence = _T_205 ? issue_slots_19_out_uop_is_sfence : _T_204 ? issue_slots_18_out_uop_is_sfence : issue_slots_17_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_is_fencei = _T_205 ? issue_slots_19_out_uop_is_fencei : _T_204 ? issue_slots_18_out_uop_is_fencei : issue_slots_17_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_is_fence = _T_205 ? issue_slots_19_out_uop_is_fence : _T_204 ? issue_slots_18_out_uop_is_fence : issue_slots_17_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_is_sfb = _T_205 ? issue_slots_19_out_uop_is_sfb : _T_204 ? issue_slots_18_out_uop_is_sfb : issue_slots_17_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_br_type = _T_205 ? issue_slots_19_out_uop_br_type : _T_204 ? issue_slots_18_out_uop_br_type : issue_slots_17_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_br_tag = _T_205 ? issue_slots_19_out_uop_br_tag : _T_204 ? issue_slots_18_out_uop_br_tag : issue_slots_17_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_br_mask = _T_205 ? issue_slots_19_out_uop_br_mask : _T_204 ? issue_slots_18_out_uop_br_mask : issue_slots_17_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_dis_col_sel = _T_205 ? issue_slots_19_out_uop_dis_col_sel : _T_204 ? issue_slots_18_out_uop_dis_col_sel : issue_slots_17_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_iw_p3_bypass_hint = _T_205 ? issue_slots_19_out_uop_iw_p3_bypass_hint : _T_204 ? issue_slots_18_out_uop_iw_p3_bypass_hint : issue_slots_17_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_iw_p2_bypass_hint = _T_205 ? issue_slots_19_out_uop_iw_p2_bypass_hint : _T_204 ? issue_slots_18_out_uop_iw_p2_bypass_hint : issue_slots_17_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_iw_p1_bypass_hint = _T_205 ? issue_slots_19_out_uop_iw_p1_bypass_hint : _T_204 ? issue_slots_18_out_uop_iw_p1_bypass_hint : issue_slots_17_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_iw_issued = _T_205 ? issue_slots_19_out_uop_iw_issued : _T_204 ? issue_slots_18_out_uop_iw_issued : issue_slots_17_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fu_code_0 = _T_205 ? issue_slots_19_out_uop_fu_code_0 : _T_204 ? issue_slots_18_out_uop_fu_code_0 : issue_slots_17_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fu_code_1 = _T_205 ? issue_slots_19_out_uop_fu_code_1 : _T_204 ? issue_slots_18_out_uop_fu_code_1 : issue_slots_17_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fu_code_2 = _T_205 ? issue_slots_19_out_uop_fu_code_2 : _T_204 ? issue_slots_18_out_uop_fu_code_2 : issue_slots_17_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fu_code_3 = _T_205 ? issue_slots_19_out_uop_fu_code_3 : _T_204 ? issue_slots_18_out_uop_fu_code_3 : issue_slots_17_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fu_code_4 = _T_205 ? issue_slots_19_out_uop_fu_code_4 : _T_204 ? issue_slots_18_out_uop_fu_code_4 : issue_slots_17_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fu_code_5 = _T_205 ? issue_slots_19_out_uop_fu_code_5 : _T_204 ? issue_slots_18_out_uop_fu_code_5 : issue_slots_17_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fu_code_6 = _T_205 ? issue_slots_19_out_uop_fu_code_6 : _T_204 ? issue_slots_18_out_uop_fu_code_6 : issue_slots_17_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fu_code_7 = _T_205 ? issue_slots_19_out_uop_fu_code_7 : _T_204 ? issue_slots_18_out_uop_fu_code_7 : issue_slots_17_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fu_code_8 = _T_205 ? issue_slots_19_out_uop_fu_code_8 : _T_204 ? issue_slots_18_out_uop_fu_code_8 : issue_slots_17_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fu_code_9 = _T_205 ? issue_slots_19_out_uop_fu_code_9 : _T_204 ? issue_slots_18_out_uop_fu_code_9 : issue_slots_17_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_iq_type_0 = _T_205 ? issue_slots_19_out_uop_iq_type_0 : _T_204 ? issue_slots_18_out_uop_iq_type_0 : issue_slots_17_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_iq_type_1 = _T_205 ? issue_slots_19_out_uop_iq_type_1 : _T_204 ? issue_slots_18_out_uop_iq_type_1 : issue_slots_17_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_iq_type_2 = _T_205 ? issue_slots_19_out_uop_iq_type_2 : _T_204 ? issue_slots_18_out_uop_iq_type_2 : issue_slots_17_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_iq_type_3 = _T_205 ? issue_slots_19_out_uop_iq_type_3 : _T_204 ? issue_slots_18_out_uop_iq_type_3 : issue_slots_17_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_debug_pc = _T_205 ? issue_slots_19_out_uop_debug_pc : _T_204 ? issue_slots_18_out_uop_debug_pc : issue_slots_17_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_is_rvc = _T_205 ? issue_slots_19_out_uop_is_rvc : _T_204 ? issue_slots_18_out_uop_is_rvc : issue_slots_17_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_debug_inst = _T_205 ? issue_slots_19_out_uop_debug_inst : _T_204 ? issue_slots_18_out_uop_debug_inst : issue_slots_17_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_inst = _T_205 ? issue_slots_19_out_uop_inst : _T_204 ? issue_slots_18_out_uop_inst : issue_slots_17_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_16_clear_T = \|shamts_oh_16; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_16_clear = _issue_slots_16_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_207 = shamts_oh_19 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_208 = shamts_oh_20 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_17_in_uop_valid = _T_208 ? issue_slots_20_will_be_valid : _T_207 ? issue_slots_19_will_be_valid : shamts_oh_18 == 3'h1 & issue_slots_18_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_17_in_uop_bits_debug_tsrc = _T_208 ? issue_slots_20_out_uop_debug_tsrc : _T_207 ? issue_slots_19_out_uop_debug_tsrc : issue_slots_18_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_debug_fsrc = _T_208 ? issue_slots_20_out_uop_debug_fsrc : _T_207 ? issue_slots_19_out_uop_debug_fsrc : issue_slots_18_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_bp_xcpt_if = _T_208 ? issue_slots_20_out_uop_bp_xcpt_if : _T_207 ? issue_slots_19_out_uop_bp_xcpt_if : issue_slots_18_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_bp_debug_if = _T_208 ? issue_slots_20_out_uop_bp_debug_if : _T_207 ? issue_slots_19_out_uop_bp_debug_if : issue_slots_18_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_xcpt_ma_if = _T_208 ? issue_slots_20_out_uop_xcpt_ma_if : _T_207 ? issue_slots_19_out_uop_xcpt_ma_if : issue_slots_18_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_xcpt_ae_if = _T_208 ? issue_slots_20_out_uop_xcpt_ae_if : _T_207 ? issue_slots_19_out_uop_xcpt_ae_if : issue_slots_18_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_xcpt_pf_if = _T_208 ? issue_slots_20_out_uop_xcpt_pf_if : _T_207 ? issue_slots_19_out_uop_xcpt_pf_if : issue_slots_18_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_typ = _T_208 ? issue_slots_20_out_uop_fp_typ : _T_207 ? issue_slots_19_out_uop_fp_typ : issue_slots_18_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_rm = _T_208 ? issue_slots_20_out_uop_fp_rm : _T_207 ? issue_slots_19_out_uop_fp_rm : issue_slots_18_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_val = _T_208 ? issue_slots_20_out_uop_fp_val : _T_207 ? issue_slots_19_out_uop_fp_val : issue_slots_18_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fcn_op = _T_208 ? issue_slots_20_out_uop_fcn_op : _T_207 ? issue_slots_19_out_uop_fcn_op : issue_slots_18_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fcn_dw = _T_208 ? issue_slots_20_out_uop_fcn_dw : _T_207 ? issue_slots_19_out_uop_fcn_dw : issue_slots_18_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_frs3_en = _T_208 ? issue_slots_20_out_uop_frs3_en : _T_207 ? issue_slots_19_out_uop_frs3_en : issue_slots_18_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_lrs2_rtype = _T_208 ? issue_slots_20_out_uop_lrs2_rtype : _T_207 ? issue_slots_19_out_uop_lrs2_rtype : issue_slots_18_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_lrs1_rtype = _T_208 ? issue_slots_20_out_uop_lrs1_rtype : _T_207 ? issue_slots_19_out_uop_lrs1_rtype : issue_slots_18_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_dst_rtype = _T_208 ? issue_slots_20_out_uop_dst_rtype : _T_207 ? issue_slots_19_out_uop_dst_rtype : issue_slots_18_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_lrs3 = _T_208 ? issue_slots_20_out_uop_lrs3 : _T_207 ? issue_slots_19_out_uop_lrs3 : issue_slots_18_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_lrs2 = _T_208 ? issue_slots_20_out_uop_lrs2 : _T_207 ? issue_slots_19_out_uop_lrs2 : issue_slots_18_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_lrs1 = _T_208 ? issue_slots_20_out_uop_lrs1 : _T_207 ? issue_slots_19_out_uop_lrs1 : issue_slots_18_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_ldst = _T_208 ? issue_slots_20_out_uop_ldst : _T_207 ? issue_slots_19_out_uop_ldst : issue_slots_18_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_ldst_is_rs1 = _T_208 ? issue_slots_20_out_uop_ldst_is_rs1 : _T_207 ? issue_slots_19_out_uop_ldst_is_rs1 : issue_slots_18_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_csr_cmd = _T_208 ? issue_slots_20_out_uop_csr_cmd : _T_207 ? issue_slots_19_out_uop_csr_cmd : issue_slots_18_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_flush_on_commit = _T_208 ? issue_slots_20_out_uop_flush_on_commit : _T_207 ? issue_slots_19_out_uop_flush_on_commit : issue_slots_18_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_is_unique = _T_208 ? issue_slots_20_out_uop_is_unique : _T_207 ? issue_slots_19_out_uop_is_unique : issue_slots_18_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_uses_stq = _T_208 ? issue_slots_20_out_uop_uses_stq : _T_207 ? issue_slots_19_out_uop_uses_stq : issue_slots_18_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_uses_ldq = _T_208 ? issue_slots_20_out_uop_uses_ldq : _T_207 ? issue_slots_19_out_uop_uses_ldq : issue_slots_18_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_mem_signed = _T_208 ? issue_slots_20_out_uop_mem_signed : _T_207 ? issue_slots_19_out_uop_mem_signed : issue_slots_18_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_mem_size = _T_208 ? issue_slots_20_out_uop_mem_size : _T_207 ? issue_slots_19_out_uop_mem_size : issue_slots_18_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_mem_cmd = _T_208 ? issue_slots_20_out_uop_mem_cmd : _T_207 ? issue_slots_19_out_uop_mem_cmd : issue_slots_18_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_exc_cause = _T_208 ? issue_slots_20_out_uop_exc_cause : _T_207 ? issue_slots_19_out_uop_exc_cause : issue_slots_18_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_exception = _T_208 ? issue_slots_20_out_uop_exception : _T_207 ? issue_slots_19_out_uop_exception : issue_slots_18_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_stale_pdst = _T_208 ? issue_slots_20_out_uop_stale_pdst : _T_207 ? issue_slots_19_out_uop_stale_pdst : issue_slots_18_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_ppred_busy = _T_208 ? issue_slots_20_out_uop_ppred_busy : _T_207 ? issue_slots_19_out_uop_ppred_busy : issue_slots_18_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_prs3_busy = _T_208 ? issue_slots_20_out_uop_prs3_busy : _T_207 ? issue_slots_19_out_uop_prs3_busy : issue_slots_18_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_prs2_busy = _T_208 ? issue_slots_20_out_uop_prs2_busy : _T_207 ? issue_slots_19_out_uop_prs2_busy : issue_slots_18_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_prs1_busy = _T_208 ? issue_slots_20_out_uop_prs1_busy : _T_207 ? issue_slots_19_out_uop_prs1_busy : issue_slots_18_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_ppred = _T_208 ? issue_slots_20_out_uop_ppred : _T_207 ? issue_slots_19_out_uop_ppred : issue_slots_18_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_prs3 = _T_208 ? issue_slots_20_out_uop_prs3 : _T_207 ? issue_slots_19_out_uop_prs3 : issue_slots_18_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_prs2 = _T_208 ? issue_slots_20_out_uop_prs2 : _T_207 ? issue_slots_19_out_uop_prs2 : issue_slots_18_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_prs1 = _T_208 ? issue_slots_20_out_uop_prs1 : _T_207 ? issue_slots_19_out_uop_prs1 : issue_slots_18_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_pdst = _T_208 ? issue_slots_20_out_uop_pdst : _T_207 ? issue_slots_19_out_uop_pdst : issue_slots_18_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_rxq_idx = _T_208 ? issue_slots_20_out_uop_rxq_idx : _T_207 ? issue_slots_19_out_uop_rxq_idx : issue_slots_18_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_stq_idx = _T_208 ? issue_slots_20_out_uop_stq_idx : _T_207 ? issue_slots_19_out_uop_stq_idx : issue_slots_18_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_ldq_idx = _T_208 ? issue_slots_20_out_uop_ldq_idx : _T_207 ? issue_slots_19_out_uop_ldq_idx : issue_slots_18_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_rob_idx = _T_208 ? issue_slots_20_out_uop_rob_idx : _T_207 ? issue_slots_19_out_uop_rob_idx : issue_slots_18_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_vec = _T_208 ? issue_slots_20_out_uop_fp_ctrl_vec : _T_207 ? issue_slots_19_out_uop_fp_ctrl_vec : issue_slots_18_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_wflags = _T_208 ? issue_slots_20_out_uop_fp_ctrl_wflags : _T_207 ? issue_slots_19_out_uop_fp_ctrl_wflags : issue_slots_18_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_sqrt = _T_208 ? issue_slots_20_out_uop_fp_ctrl_sqrt : _T_207 ? issue_slots_19_out_uop_fp_ctrl_sqrt : issue_slots_18_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_div = _T_208 ? issue_slots_20_out_uop_fp_ctrl_div : _T_207 ? issue_slots_19_out_uop_fp_ctrl_div : issue_slots_18_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_fma = _T_208 ? issue_slots_20_out_uop_fp_ctrl_fma : _T_207 ? issue_slots_19_out_uop_fp_ctrl_fma : issue_slots_18_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_fastpipe = _T_208 ? issue_slots_20_out_uop_fp_ctrl_fastpipe : _T_207 ? issue_slots_19_out_uop_fp_ctrl_fastpipe : issue_slots_18_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_toint = _T_208 ? issue_slots_20_out_uop_fp_ctrl_toint : _T_207 ? issue_slots_19_out_uop_fp_ctrl_toint : issue_slots_18_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_fromint = _T_208 ? issue_slots_20_out_uop_fp_ctrl_fromint : _T_207 ? issue_slots_19_out_uop_fp_ctrl_fromint : issue_slots_18_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_typeTagOut = _T_208 ? issue_slots_20_out_uop_fp_ctrl_typeTagOut : _T_207 ? issue_slots_19_out_uop_fp_ctrl_typeTagOut : issue_slots_18_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_typeTagIn = _T_208 ? issue_slots_20_out_uop_fp_ctrl_typeTagIn : _T_207 ? issue_slots_19_out_uop_fp_ctrl_typeTagIn : issue_slots_18_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_swap23 = _T_208 ? issue_slots_20_out_uop_fp_ctrl_swap23 : _T_207 ? issue_slots_19_out_uop_fp_ctrl_swap23 : issue_slots_18_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_swap12 = _T_208 ? issue_slots_20_out_uop_fp_ctrl_swap12 : _T_207 ? issue_slots_19_out_uop_fp_ctrl_swap12 : issue_slots_18_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_ren3 = _T_208 ? issue_slots_20_out_uop_fp_ctrl_ren3 : _T_207 ? issue_slots_19_out_uop_fp_ctrl_ren3 : issue_slots_18_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_ren2 = _T_208 ? issue_slots_20_out_uop_fp_ctrl_ren2 : _T_207 ? issue_slots_19_out_uop_fp_ctrl_ren2 : issue_slots_18_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_ren1 = _T_208 ? issue_slots_20_out_uop_fp_ctrl_ren1 : _T_207 ? issue_slots_19_out_uop_fp_ctrl_ren1 : issue_slots_18_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_wen = _T_208 ? issue_slots_20_out_uop_fp_ctrl_wen : _T_207 ? issue_slots_19_out_uop_fp_ctrl_wen : issue_slots_18_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_ldst = _T_208 ? issue_slots_20_out_uop_fp_ctrl_ldst : _T_207 ? issue_slots_19_out_uop_fp_ctrl_ldst : issue_slots_18_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_op2_sel = _T_208 ? issue_slots_20_out_uop_op2_sel : _T_207 ? issue_slots_19_out_uop_op2_sel : issue_slots_18_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_op1_sel = _T_208 ? issue_slots_20_out_uop_op1_sel : _T_207 ? issue_slots_19_out_uop_op1_sel : issue_slots_18_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_imm_packed = _T_208 ? issue_slots_20_out_uop_imm_packed : _T_207 ? issue_slots_19_out_uop_imm_packed : issue_slots_18_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_pimm = _T_208 ? issue_slots_20_out_uop_pimm : _T_207 ? issue_slots_19_out_uop_pimm : issue_slots_18_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_imm_sel = _T_208 ? issue_slots_20_out_uop_imm_sel : _T_207 ? issue_slots_19_out_uop_imm_sel : issue_slots_18_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_imm_rename = _T_208 ? issue_slots_20_out_uop_imm_rename : _T_207 ? issue_slots_19_out_uop_imm_rename : issue_slots_18_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_taken = _T_208 ? issue_slots_20_out_uop_taken : _T_207 ? issue_slots_19_out_uop_taken : issue_slots_18_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_pc_lob = _T_208 ? issue_slots_20_out_uop_pc_lob : _T_207 ? issue_slots_19_out_uop_pc_lob : issue_slots_18_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_edge_inst = _T_208 ? issue_slots_20_out_uop_edge_inst : _T_207 ? issue_slots_19_out_uop_edge_inst : issue_slots_18_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_ftq_idx = _T_208 ? issue_slots_20_out_uop_ftq_idx : _T_207 ? issue_slots_19_out_uop_ftq_idx : issue_slots_18_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_is_mov = _T_208 ? issue_slots_20_out_uop_is_mov : _T_207 ? issue_slots_19_out_uop_is_mov : issue_slots_18_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_is_rocc = _T_208 ? issue_slots_20_out_uop_is_rocc : _T_207 ? issue_slots_19_out_uop_is_rocc : issue_slots_18_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_is_sys_pc2epc = _T_208 ? issue_slots_20_out_uop_is_sys_pc2epc : _T_207 ? issue_slots_19_out_uop_is_sys_pc2epc : issue_slots_18_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_is_eret = _T_208 ? issue_slots_20_out_uop_is_eret : _T_207 ? issue_slots_19_out_uop_is_eret : issue_slots_18_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_is_amo = _T_208 ? issue_slots_20_out_uop_is_amo : _T_207 ? issue_slots_19_out_uop_is_amo : issue_slots_18_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_is_sfence = _T_208 ? issue_slots_20_out_uop_is_sfence : _T_207 ? issue_slots_19_out_uop_is_sfence : issue_slots_18_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_is_fencei = _T_208 ? issue_slots_20_out_uop_is_fencei : _T_207 ? issue_slots_19_out_uop_is_fencei : issue_slots_18_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_is_fence = _T_208 ? issue_slots_20_out_uop_is_fence : _T_207 ? issue_slots_19_out_uop_is_fence : issue_slots_18_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_is_sfb = _T_208 ? issue_slots_20_out_uop_is_sfb : _T_207 ? issue_slots_19_out_uop_is_sfb : issue_slots_18_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_br_type = _T_208 ? issue_slots_20_out_uop_br_type : _T_207 ? issue_slots_19_out_uop_br_type : issue_slots_18_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_br_tag = _T_208 ? issue_slots_20_out_uop_br_tag : _T_207 ? issue_slots_19_out_uop_br_tag : issue_slots_18_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_br_mask = _T_208 ? issue_slots_20_out_uop_br_mask : _T_207 ? issue_slots_19_out_uop_br_mask : issue_slots_18_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_dis_col_sel = _T_208 ? issue_slots_20_out_uop_dis_col_sel : _T_207 ? issue_slots_19_out_uop_dis_col_sel : issue_slots_18_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_iw_p3_bypass_hint = _T_208 ? issue_slots_20_out_uop_iw_p3_bypass_hint : _T_207 ? issue_slots_19_out_uop_iw_p3_bypass_hint : issue_slots_18_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_iw_p2_bypass_hint = _T_208 ? issue_slots_20_out_uop_iw_p2_bypass_hint : _T_207 ? issue_slots_19_out_uop_iw_p2_bypass_hint : issue_slots_18_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_iw_p1_bypass_hint = _T_208 ? issue_slots_20_out_uop_iw_p1_bypass_hint : _T_207 ? issue_slots_19_out_uop_iw_p1_bypass_hint : issue_slots_18_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_iw_issued = _T_208 ? issue_slots_20_out_uop_iw_issued : _T_207 ? issue_slots_19_out_uop_iw_issued : issue_slots_18_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fu_code_0 = _T_208 ? issue_slots_20_out_uop_fu_code_0 : _T_207 ? issue_slots_19_out_uop_fu_code_0 : issue_slots_18_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fu_code_1 = _T_208 ? issue_slots_20_out_uop_fu_code_1 : _T_207 ? issue_slots_19_out_uop_fu_code_1 : issue_slots_18_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fu_code_2 = _T_208 ? issue_slots_20_out_uop_fu_code_2 : _T_207 ? issue_slots_19_out_uop_fu_code_2 : issue_slots_18_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fu_code_3 = _T_208 ? issue_slots_20_out_uop_fu_code_3 : _T_207 ? issue_slots_19_out_uop_fu_code_3 : issue_slots_18_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fu_code_4 = _T_208 ? issue_slots_20_out_uop_fu_code_4 : _T_207 ? issue_slots_19_out_uop_fu_code_4 : issue_slots_18_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fu_code_5 = _T_208 ? issue_slots_20_out_uop_fu_code_5 : _T_207 ? issue_slots_19_out_uop_fu_code_5 : issue_slots_18_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fu_code_6 = _T_208 ? issue_slots_20_out_uop_fu_code_6 : _T_207 ? issue_slots_19_out_uop_fu_code_6 : issue_slots_18_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fu_code_7 = _T_208 ? issue_slots_20_out_uop_fu_code_7 : _T_207 ? issue_slots_19_out_uop_fu_code_7 : issue_slots_18_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fu_code_8 = _T_208 ? issue_slots_20_out_uop_fu_code_8 : _T_207 ? issue_slots_19_out_uop_fu_code_8 : issue_slots_18_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fu_code_9 = _T_208 ? issue_slots_20_out_uop_fu_code_9 : _T_207 ? issue_slots_19_out_uop_fu_code_9 : issue_slots_18_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_iq_type_0 = _T_208 ? issue_slots_20_out_uop_iq_type_0 : _T_207 ? issue_slots_19_out_uop_iq_type_0 : issue_slots_18_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_iq_type_1 = _T_208 ? issue_slots_20_out_uop_iq_type_1 : _T_207 ? issue_slots_19_out_uop_iq_type_1 : issue_slots_18_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_iq_type_2 = _T_208 ? issue_slots_20_out_uop_iq_type_2 : _T_207 ? issue_slots_19_out_uop_iq_type_2 : issue_slots_18_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_iq_type_3 = _T_208 ? issue_slots_20_out_uop_iq_type_3 : _T_207 ? issue_slots_19_out_uop_iq_type_3 : issue_slots_18_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_debug_pc = _T_208 ? issue_slots_20_out_uop_debug_pc : _T_207 ? issue_slots_19_out_uop_debug_pc : issue_slots_18_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_is_rvc = _T_208 ? issue_slots_20_out_uop_is_rvc : _T_207 ? issue_slots_19_out_uop_is_rvc : issue_slots_18_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_debug_inst = _T_208 ? issue_slots_20_out_uop_debug_inst : _T_207 ? issue_slots_19_out_uop_debug_inst : issue_slots_18_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_inst = _T_208 ? issue_slots_20_out_uop_inst : _T_207 ? issue_slots_19_out_uop_inst : issue_slots_18_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_17_clear_T = \|shamts_oh_17; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_17_clear = _issue_slots_17_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_210 = shamts_oh_20 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_211 = shamts_oh_21 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_18_in_uop_valid = _T_211 ? issue_slots_21_will_be_valid : _T_210 ? issue_slots_20_will_be_valid : shamts_oh_19 == 3'h1 & issue_slots_19_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_18_in_uop_bits_debug_tsrc = _T_211 ? issue_slots_21_out_uop_debug_tsrc : _T_210 ? issue_slots_20_out_uop_debug_tsrc : issue_slots_19_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_debug_fsrc = _T_211 ? issue_slots_21_out_uop_debug_fsrc : _T_210 ? issue_slots_20_out_uop_debug_fsrc : issue_slots_19_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_bp_xcpt_if = _T_211 ? issue_slots_21_out_uop_bp_xcpt_if : _T_210 ? issue_slots_20_out_uop_bp_xcpt_if : issue_slots_19_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_bp_debug_if = _T_211 ? issue_slots_21_out_uop_bp_debug_if : _T_210 ? issue_slots_20_out_uop_bp_debug_if : issue_slots_19_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_xcpt_ma_if = _T_211 ? issue_slots_21_out_uop_xcpt_ma_if : _T_210 ? issue_slots_20_out_uop_xcpt_ma_if : issue_slots_19_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_xcpt_ae_if = _T_211 ? issue_slots_21_out_uop_xcpt_ae_if : _T_210 ? issue_slots_20_out_uop_xcpt_ae_if : issue_slots_19_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_xcpt_pf_if = _T_211 ? issue_slots_21_out_uop_xcpt_pf_if : _T_210 ? issue_slots_20_out_uop_xcpt_pf_if : issue_slots_19_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_typ = _T_211 ? issue_slots_21_out_uop_fp_typ : _T_210 ? issue_slots_20_out_uop_fp_typ : issue_slots_19_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_rm = _T_211 ? issue_slots_21_out_uop_fp_rm : _T_210 ? issue_slots_20_out_uop_fp_rm : issue_slots_19_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_val = _T_211 ? issue_slots_21_out_uop_fp_val : _T_210 ? issue_slots_20_out_uop_fp_val : issue_slots_19_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fcn_op = _T_211 ? issue_slots_21_out_uop_fcn_op : _T_210 ? issue_slots_20_out_uop_fcn_op : issue_slots_19_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fcn_dw = _T_211 ? issue_slots_21_out_uop_fcn_dw : _T_210 ? issue_slots_20_out_uop_fcn_dw : issue_slots_19_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_frs3_en = _T_211 ? issue_slots_21_out_uop_frs3_en : _T_210 ? issue_slots_20_out_uop_frs3_en : issue_slots_19_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_lrs2_rtype = _T_211 ? issue_slots_21_out_uop_lrs2_rtype : _T_210 ? issue_slots_20_out_uop_lrs2_rtype : issue_slots_19_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_lrs1_rtype = _T_211 ? issue_slots_21_out_uop_lrs1_rtype : _T_210 ? issue_slots_20_out_uop_lrs1_rtype : issue_slots_19_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_dst_rtype = _T_211 ? issue_slots_21_out_uop_dst_rtype : _T_210 ? issue_slots_20_out_uop_dst_rtype : issue_slots_19_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_lrs3 = _T_211 ? issue_slots_21_out_uop_lrs3 : _T_210 ? issue_slots_20_out_uop_lrs3 : issue_slots_19_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_lrs2 = _T_211 ? issue_slots_21_out_uop_lrs2 : _T_210 ? issue_slots_20_out_uop_lrs2 : issue_slots_19_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_lrs1 = _T_211 ? issue_slots_21_out_uop_lrs1 : _T_210 ? issue_slots_20_out_uop_lrs1 : issue_slots_19_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_ldst = _T_211 ? issue_slots_21_out_uop_ldst : _T_210 ? issue_slots_20_out_uop_ldst : issue_slots_19_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_ldst_is_rs1 = _T_211 ? issue_slots_21_out_uop_ldst_is_rs1 : _T_210 ? issue_slots_20_out_uop_ldst_is_rs1 : issue_slots_19_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_csr_cmd = _T_211 ? issue_slots_21_out_uop_csr_cmd : _T_210 ? issue_slots_20_out_uop_csr_cmd : issue_slots_19_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_flush_on_commit = _T_211 ? issue_slots_21_out_uop_flush_on_commit : _T_210 ? issue_slots_20_out_uop_flush_on_commit : issue_slots_19_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_is_unique = _T_211 ? issue_slots_21_out_uop_is_unique : _T_210 ? issue_slots_20_out_uop_is_unique : issue_slots_19_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_uses_stq = _T_211 ? issue_slots_21_out_uop_uses_stq : _T_210 ? issue_slots_20_out_uop_uses_stq : issue_slots_19_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_uses_ldq = _T_211 ? issue_slots_21_out_uop_uses_ldq : _T_210 ? issue_slots_20_out_uop_uses_ldq : issue_slots_19_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_mem_signed = _T_211 ? issue_slots_21_out_uop_mem_signed : _T_210 ? issue_slots_20_out_uop_mem_signed : issue_slots_19_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_mem_size = _T_211 ? issue_slots_21_out_uop_mem_size : _T_210 ? issue_slots_20_out_uop_mem_size : issue_slots_19_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_mem_cmd = _T_211 ? issue_slots_21_out_uop_mem_cmd : _T_210 ? issue_slots_20_out_uop_mem_cmd : issue_slots_19_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_exc_cause = _T_211 ? issue_slots_21_out_uop_exc_cause : _T_210 ? issue_slots_20_out_uop_exc_cause : issue_slots_19_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_exception = _T_211 ? issue_slots_21_out_uop_exception : _T_210 ? issue_slots_20_out_uop_exception : issue_slots_19_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_stale_pdst = _T_211 ? issue_slots_21_out_uop_stale_pdst : _T_210 ? issue_slots_20_out_uop_stale_pdst : issue_slots_19_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_ppred_busy = _T_211 ? issue_slots_21_out_uop_ppred_busy : _T_210 ? issue_slots_20_out_uop_ppred_busy : issue_slots_19_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_prs3_busy = _T_211 ? issue_slots_21_out_uop_prs3_busy : _T_210 ? issue_slots_20_out_uop_prs3_busy : issue_slots_19_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_prs2_busy = _T_211 ? issue_slots_21_out_uop_prs2_busy : _T_210 ? issue_slots_20_out_uop_prs2_busy : issue_slots_19_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_prs1_busy = _T_211 ? issue_slots_21_out_uop_prs1_busy : _T_210 ? issue_slots_20_out_uop_prs1_busy : issue_slots_19_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_ppred = _T_211 ? issue_slots_21_out_uop_ppred : _T_210 ? issue_slots_20_out_uop_ppred : issue_slots_19_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_prs3 = _T_211 ? issue_slots_21_out_uop_prs3 : _T_210 ? issue_slots_20_out_uop_prs3 : issue_slots_19_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_prs2 = _T_211 ? issue_slots_21_out_uop_prs2 : _T_210 ? issue_slots_20_out_uop_prs2 : issue_slots_19_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_prs1 = _T_211 ? issue_slots_21_out_uop_prs1 : _T_210 ? issue_slots_20_out_uop_prs1 : issue_slots_19_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_pdst = _T_211 ? issue_slots_21_out_uop_pdst : _T_210 ? issue_slots_20_out_uop_pdst : issue_slots_19_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_rxq_idx = _T_211 ? issue_slots_21_out_uop_rxq_idx : _T_210 ? issue_slots_20_out_uop_rxq_idx : issue_slots_19_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_stq_idx = _T_211 ? issue_slots_21_out_uop_stq_idx : _T_210 ? issue_slots_20_out_uop_stq_idx : issue_slots_19_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_ldq_idx = _T_211 ? issue_slots_21_out_uop_ldq_idx : _T_210 ? issue_slots_20_out_uop_ldq_idx : issue_slots_19_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_rob_idx = _T_211 ? issue_slots_21_out_uop_rob_idx : _T_210 ? issue_slots_20_out_uop_rob_idx : issue_slots_19_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_vec = _T_211 ? issue_slots_21_out_uop_fp_ctrl_vec : _T_210 ? issue_slots_20_out_uop_fp_ctrl_vec : issue_slots_19_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_wflags = _T_211 ? issue_slots_21_out_uop_fp_ctrl_wflags : _T_210 ? issue_slots_20_out_uop_fp_ctrl_wflags : issue_slots_19_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_sqrt = _T_211 ? issue_slots_21_out_uop_fp_ctrl_sqrt : _T_210 ? issue_slots_20_out_uop_fp_ctrl_sqrt : issue_slots_19_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_div = _T_211 ? issue_slots_21_out_uop_fp_ctrl_div : _T_210 ? issue_slots_20_out_uop_fp_ctrl_div : issue_slots_19_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_fma = _T_211 ? issue_slots_21_out_uop_fp_ctrl_fma : _T_210 ? issue_slots_20_out_uop_fp_ctrl_fma : issue_slots_19_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_fastpipe = _T_211 ? issue_slots_21_out_uop_fp_ctrl_fastpipe : _T_210 ? issue_slots_20_out_uop_fp_ctrl_fastpipe : issue_slots_19_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_toint = _T_211 ? issue_slots_21_out_uop_fp_ctrl_toint : _T_210 ? issue_slots_20_out_uop_fp_ctrl_toint : issue_slots_19_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_fromint = _T_211 ? issue_slots_21_out_uop_fp_ctrl_fromint : _T_210 ? issue_slots_20_out_uop_fp_ctrl_fromint : issue_slots_19_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_typeTagOut = _T_211 ? issue_slots_21_out_uop_fp_ctrl_typeTagOut : _T_210 ? issue_slots_20_out_uop_fp_ctrl_typeTagOut : issue_slots_19_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_typeTagIn = _T_211 ? issue_slots_21_out_uop_fp_ctrl_typeTagIn : _T_210 ? issue_slots_20_out_uop_fp_ctrl_typeTagIn : issue_slots_19_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_swap23 = _T_211 ? issue_slots_21_out_uop_fp_ctrl_swap23 : _T_210 ? issue_slots_20_out_uop_fp_ctrl_swap23 : issue_slots_19_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_swap12 = _T_211 ? issue_slots_21_out_uop_fp_ctrl_swap12 : _T_210 ? issue_slots_20_out_uop_fp_ctrl_swap12 : issue_slots_19_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_ren3 = _T_211 ? issue_slots_21_out_uop_fp_ctrl_ren3 : _T_210 ? issue_slots_20_out_uop_fp_ctrl_ren3 : issue_slots_19_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_ren2 = _T_211 ? issue_slots_21_out_uop_fp_ctrl_ren2 : _T_210 ? issue_slots_20_out_uop_fp_ctrl_ren2 : issue_slots_19_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_ren1 = _T_211 ? issue_slots_21_out_uop_fp_ctrl_ren1 : _T_210 ? issue_slots_20_out_uop_fp_ctrl_ren1 : issue_slots_19_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_wen = _T_211 ? issue_slots_21_out_uop_fp_ctrl_wen : _T_210 ? issue_slots_20_out_uop_fp_ctrl_wen : issue_slots_19_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_ldst = _T_211 ? issue_slots_21_out_uop_fp_ctrl_ldst : _T_210 ? issue_slots_20_out_uop_fp_ctrl_ldst : issue_slots_19_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_op2_sel = _T_211 ? issue_slots_21_out_uop_op2_sel : _T_210 ? issue_slots_20_out_uop_op2_sel : issue_slots_19_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_op1_sel = _T_211 ? issue_slots_21_out_uop_op1_sel : _T_210 ? issue_slots_20_out_uop_op1_sel : issue_slots_19_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_imm_packed = _T_211 ? issue_slots_21_out_uop_imm_packed : _T_210 ? issue_slots_20_out_uop_imm_packed : issue_slots_19_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_pimm = _T_211 ? issue_slots_21_out_uop_pimm : _T_210 ? issue_slots_20_out_uop_pimm : issue_slots_19_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_imm_sel = _T_211 ? issue_slots_21_out_uop_imm_sel : _T_210 ? issue_slots_20_out_uop_imm_sel : issue_slots_19_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_imm_rename = _T_211 ? issue_slots_21_out_uop_imm_rename : _T_210 ? issue_slots_20_out_uop_imm_rename : issue_slots_19_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_taken = _T_211 ? issue_slots_21_out_uop_taken : _T_210 ? issue_slots_20_out_uop_taken : issue_slots_19_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_pc_lob = _T_211 ? issue_slots_21_out_uop_pc_lob : _T_210 ? issue_slots_20_out_uop_pc_lob : issue_slots_19_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_edge_inst = _T_211 ? issue_slots_21_out_uop_edge_inst : _T_210 ? issue_slots_20_out_uop_edge_inst : issue_slots_19_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_ftq_idx = _T_211 ? issue_slots_21_out_uop_ftq_idx : _T_210 ? issue_slots_20_out_uop_ftq_idx : issue_slots_19_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_is_mov = _T_211 ? issue_slots_21_out_uop_is_mov : _T_210 ? issue_slots_20_out_uop_is_mov : issue_slots_19_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_is_rocc = _T_211 ? issue_slots_21_out_uop_is_rocc : _T_210 ? issue_slots_20_out_uop_is_rocc : issue_slots_19_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_is_sys_pc2epc = _T_211 ? issue_slots_21_out_uop_is_sys_pc2epc : _T_210 ? issue_slots_20_out_uop_is_sys_pc2epc : issue_slots_19_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_is_eret = _T_211 ? issue_slots_21_out_uop_is_eret : _T_210 ? issue_slots_20_out_uop_is_eret : issue_slots_19_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_is_amo = _T_211 ? issue_slots_21_out_uop_is_amo : _T_210 ? issue_slots_20_out_uop_is_amo : issue_slots_19_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_is_sfence = _T_211 ? issue_slots_21_out_uop_is_sfence : _T_210 ? issue_slots_20_out_uop_is_sfence : issue_slots_19_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_is_fencei = _T_211 ? issue_slots_21_out_uop_is_fencei : _T_210 ? issue_slots_20_out_uop_is_fencei : issue_slots_19_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_is_fence = _T_211 ? issue_slots_21_out_uop_is_fence : _T_210 ? issue_slots_20_out_uop_is_fence : issue_slots_19_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_is_sfb = _T_211 ? issue_slots_21_out_uop_is_sfb : _T_210 ? issue_slots_20_out_uop_is_sfb : issue_slots_19_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_br_type = _T_211 ? issue_slots_21_out_uop_br_type : _T_210 ? issue_slots_20_out_uop_br_type : issue_slots_19_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_br_tag = _T_211 ? issue_slots_21_out_uop_br_tag : _T_210 ? issue_slots_20_out_uop_br_tag : issue_slots_19_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_br_mask = _T_211 ? issue_slots_21_out_uop_br_mask : _T_210 ? issue_slots_20_out_uop_br_mask : issue_slots_19_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_dis_col_sel = _T_211 ? issue_slots_21_out_uop_dis_col_sel : _T_210 ? issue_slots_20_out_uop_dis_col_sel : issue_slots_19_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_iw_p3_bypass_hint = _T_211 ? issue_slots_21_out_uop_iw_p3_bypass_hint : _T_210 ? issue_slots_20_out_uop_iw_p3_bypass_hint : issue_slots_19_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_iw_p2_bypass_hint = _T_211 ? issue_slots_21_out_uop_iw_p2_bypass_hint : _T_210 ? issue_slots_20_out_uop_iw_p2_bypass_hint : issue_slots_19_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_iw_p1_bypass_hint = _T_211 ? issue_slots_21_out_uop_iw_p1_bypass_hint : _T_210 ? issue_slots_20_out_uop_iw_p1_bypass_hint : issue_slots_19_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_iw_issued = _T_211 ? issue_slots_21_out_uop_iw_issued : _T_210 ? issue_slots_20_out_uop_iw_issued : issue_slots_19_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fu_code_0 = _T_211 ? issue_slots_21_out_uop_fu_code_0 : _T_210 ? issue_slots_20_out_uop_fu_code_0 : issue_slots_19_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fu_code_1 = _T_211 ? issue_slots_21_out_uop_fu_code_1 : _T_210 ? issue_slots_20_out_uop_fu_code_1 : issue_slots_19_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fu_code_2 = _T_211 ? issue_slots_21_out_uop_fu_code_2 : _T_210 ? issue_slots_20_out_uop_fu_code_2 : issue_slots_19_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fu_code_3 = _T_211 ? issue_slots_21_out_uop_fu_code_3 : _T_210 ? issue_slots_20_out_uop_fu_code_3 : issue_slots_19_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fu_code_4 = _T_211 ? issue_slots_21_out_uop_fu_code_4 : _T_210 ? issue_slots_20_out_uop_fu_code_4 : issue_slots_19_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fu_code_5 = _T_211 ? issue_slots_21_out_uop_fu_code_5 : _T_210 ? issue_slots_20_out_uop_fu_code_5 : issue_slots_19_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fu_code_6 = _T_211 ? issue_slots_21_out_uop_fu_code_6 : _T_210 ? issue_slots_20_out_uop_fu_code_6 : issue_slots_19_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fu_code_7 = _T_211 ? issue_slots_21_out_uop_fu_code_7 : _T_210 ? issue_slots_20_out_uop_fu_code_7 : issue_slots_19_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fu_code_8 = _T_211 ? issue_slots_21_out_uop_fu_code_8 : _T_210 ? issue_slots_20_out_uop_fu_code_8 : issue_slots_19_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fu_code_9 = _T_211 ? issue_slots_21_out_uop_fu_code_9 : _T_210 ? issue_slots_20_out_uop_fu_code_9 : issue_slots_19_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_iq_type_0 = _T_211 ? issue_slots_21_out_uop_iq_type_0 : _T_210 ? issue_slots_20_out_uop_iq_type_0 : issue_slots_19_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_iq_type_1 = _T_211 ? issue_slots_21_out_uop_iq_type_1 : _T_210 ? issue_slots_20_out_uop_iq_type_1 : issue_slots_19_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_iq_type_2 = _T_211 ? issue_slots_21_out_uop_iq_type_2 : _T_210 ? issue_slots_20_out_uop_iq_type_2 : issue_slots_19_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_iq_type_3 = _T_211 ? issue_slots_21_out_uop_iq_type_3 : _T_210 ? issue_slots_20_out_uop_iq_type_3 : issue_slots_19_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_debug_pc = _T_211 ? issue_slots_21_out_uop_debug_pc : _T_210 ? issue_slots_20_out_uop_debug_pc : issue_slots_19_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_is_rvc = _T_211 ? issue_slots_21_out_uop_is_rvc : _T_210 ? issue_slots_20_out_uop_is_rvc : issue_slots_19_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_debug_inst = _T_211 ? issue_slots_21_out_uop_debug_inst : _T_210 ? issue_slots_20_out_uop_debug_inst : issue_slots_19_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_inst = _T_211 ? issue_slots_21_out_uop_inst : _T_210 ? issue_slots_20_out_uop_inst : issue_slots_19_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_18_clear_T = \|shamts_oh_18; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_18_clear = _issue_slots_18_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_213 = shamts_oh_21 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_214 = shamts_oh_22 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_19_in_uop_valid = _T_214 ? issue_slots_22_will_be_valid : _T_213 ? issue_slots_21_will_be_valid : shamts_oh_20 == 3'h1 & issue_slots_20_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_19_in_uop_bits_debug_tsrc = _T_214 ? issue_slots_22_out_uop_debug_tsrc : _T_213 ? issue_slots_21_out_uop_debug_tsrc : issue_slots_20_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_debug_fsrc = _T_214 ? issue_slots_22_out_uop_debug_fsrc : _T_213 ? issue_slots_21_out_uop_debug_fsrc : issue_slots_20_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_bp_xcpt_if = _T_214 ? issue_slots_22_out_uop_bp_xcpt_if : _T_213 ? issue_slots_21_out_uop_bp_xcpt_if : issue_slots_20_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_bp_debug_if = _T_214 ? issue_slots_22_out_uop_bp_debug_if : _T_213 ? issue_slots_21_out_uop_bp_debug_if : issue_slots_20_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_xcpt_ma_if = _T_214 ? issue_slots_22_out_uop_xcpt_ma_if : _T_213 ? issue_slots_21_out_uop_xcpt_ma_if : issue_slots_20_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_xcpt_ae_if = _T_214 ? issue_slots_22_out_uop_xcpt_ae_if : _T_213 ? issue_slots_21_out_uop_xcpt_ae_if : issue_slots_20_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_xcpt_pf_if = _T_214 ? issue_slots_22_out_uop_xcpt_pf_if : _T_213 ? issue_slots_21_out_uop_xcpt_pf_if : issue_slots_20_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_typ = _T_214 ? issue_slots_22_out_uop_fp_typ : _T_213 ? issue_slots_21_out_uop_fp_typ : issue_slots_20_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_rm = _T_214 ? issue_slots_22_out_uop_fp_rm : _T_213 ? issue_slots_21_out_uop_fp_rm : issue_slots_20_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_val = _T_214 ? issue_slots_22_out_uop_fp_val : _T_213 ? issue_slots_21_out_uop_fp_val : issue_slots_20_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fcn_op = _T_214 ? issue_slots_22_out_uop_fcn_op : _T_213 ? issue_slots_21_out_uop_fcn_op : issue_slots_20_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fcn_dw = _T_214 ? issue_slots_22_out_uop_fcn_dw : _T_213 ? issue_slots_21_out_uop_fcn_dw : issue_slots_20_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_frs3_en = _T_214 ? issue_slots_22_out_uop_frs3_en : _T_213 ? issue_slots_21_out_uop_frs3_en : issue_slots_20_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_lrs2_rtype = _T_214 ? issue_slots_22_out_uop_lrs2_rtype : _T_213 ? issue_slots_21_out_uop_lrs2_rtype : issue_slots_20_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_lrs1_rtype = _T_214 ? issue_slots_22_out_uop_lrs1_rtype : _T_213 ? issue_slots_21_out_uop_lrs1_rtype : issue_slots_20_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_dst_rtype = _T_214 ? issue_slots_22_out_uop_dst_rtype : _T_213 ? issue_slots_21_out_uop_dst_rtype : issue_slots_20_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_lrs3 = _T_214 ? issue_slots_22_out_uop_lrs3 : _T_213 ? issue_slots_21_out_uop_lrs3 : issue_slots_20_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_lrs2 = _T_214 ? issue_slots_22_out_uop_lrs2 : _T_213 ? issue_slots_21_out_uop_lrs2 : issue_slots_20_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_lrs1 = _T_214 ? issue_slots_22_out_uop_lrs1 : _T_213 ? issue_slots_21_out_uop_lrs1 : issue_slots_20_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_ldst = _T_214 ? issue_slots_22_out_uop_ldst : _T_213 ? issue_slots_21_out_uop_ldst : issue_slots_20_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_ldst_is_rs1 = _T_214 ? issue_slots_22_out_uop_ldst_is_rs1 : _T_213 ? issue_slots_21_out_uop_ldst_is_rs1 : issue_slots_20_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_csr_cmd = _T_214 ? issue_slots_22_out_uop_csr_cmd : _T_213 ? issue_slots_21_out_uop_csr_cmd : issue_slots_20_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_flush_on_commit = _T_214 ? issue_slots_22_out_uop_flush_on_commit : _T_213 ? issue_slots_21_out_uop_flush_on_commit : issue_slots_20_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_is_unique = _T_214 ? issue_slots_22_out_uop_is_unique : _T_213 ? issue_slots_21_out_uop_is_unique : issue_slots_20_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_uses_stq = _T_214 ? issue_slots_22_out_uop_uses_stq : _T_213 ? issue_slots_21_out_uop_uses_stq : issue_slots_20_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_uses_ldq = _T_214 ? issue_slots_22_out_uop_uses_ldq : _T_213 ? issue_slots_21_out_uop_uses_ldq : issue_slots_20_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_mem_signed = _T_214 ? issue_slots_22_out_uop_mem_signed : _T_213 ? issue_slots_21_out_uop_mem_signed : issue_slots_20_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_mem_size = _T_214 ? issue_slots_22_out_uop_mem_size : _T_213 ? issue_slots_21_out_uop_mem_size : issue_slots_20_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_mem_cmd = _T_214 ? issue_slots_22_out_uop_mem_cmd : _T_213 ? issue_slots_21_out_uop_mem_cmd : issue_slots_20_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_exc_cause = _T_214 ? issue_slots_22_out_uop_exc_cause : _T_213 ? issue_slots_21_out_uop_exc_cause : issue_slots_20_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_exception = _T_214 ? issue_slots_22_out_uop_exception : _T_213 ? issue_slots_21_out_uop_exception : issue_slots_20_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_stale_pdst = _T_214 ? issue_slots_22_out_uop_stale_pdst : _T_213 ? issue_slots_21_out_uop_stale_pdst : issue_slots_20_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_ppred_busy = _T_214 ? issue_slots_22_out_uop_ppred_busy : _T_213 ? issue_slots_21_out_uop_ppred_busy : issue_slots_20_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_prs3_busy = _T_214 ? issue_slots_22_out_uop_prs3_busy : _T_213 ? issue_slots_21_out_uop_prs3_busy : issue_slots_20_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_prs2_busy = _T_214 ? issue_slots_22_out_uop_prs2_busy : _T_213 ? issue_slots_21_out_uop_prs2_busy : issue_slots_20_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_prs1_busy = _T_214 ? issue_slots_22_out_uop_prs1_busy : _T_213 ? issue_slots_21_out_uop_prs1_busy : issue_slots_20_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_ppred = _T_214 ? issue_slots_22_out_uop_ppred : _T_213 ? issue_slots_21_out_uop_ppred : issue_slots_20_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_prs3 = _T_214 ? issue_slots_22_out_uop_prs3 : _T_213 ? issue_slots_21_out_uop_prs3 : issue_slots_20_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_prs2 = _T_214 ? issue_slots_22_out_uop_prs2 : _T_213 ? issue_slots_21_out_uop_prs2 : issue_slots_20_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_prs1 = _T_214 ? issue_slots_22_out_uop_prs1 : _T_213 ? issue_slots_21_out_uop_prs1 : issue_slots_20_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_pdst = _T_214 ? issue_slots_22_out_uop_pdst : _T_213 ? issue_slots_21_out_uop_pdst : issue_slots_20_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_rxq_idx = _T_214 ? issue_slots_22_out_uop_rxq_idx : _T_213 ? issue_slots_21_out_uop_rxq_idx : issue_slots_20_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_stq_idx = _T_214 ? issue_slots_22_out_uop_stq_idx : _T_213 ? issue_slots_21_out_uop_stq_idx : issue_slots_20_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_ldq_idx = _T_214 ? issue_slots_22_out_uop_ldq_idx : _T_213 ? issue_slots_21_out_uop_ldq_idx : issue_slots_20_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_rob_idx = _T_214 ? issue_slots_22_out_uop_rob_idx : _T_213 ? issue_slots_21_out_uop_rob_idx : issue_slots_20_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_vec = _T_214 ? issue_slots_22_out_uop_fp_ctrl_vec : _T_213 ? issue_slots_21_out_uop_fp_ctrl_vec : issue_slots_20_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_wflags = _T_214 ? issue_slots_22_out_uop_fp_ctrl_wflags : _T_213 ? issue_slots_21_out_uop_fp_ctrl_wflags : issue_slots_20_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_sqrt = _T_214 ? issue_slots_22_out_uop_fp_ctrl_sqrt : _T_213 ? issue_slots_21_out_uop_fp_ctrl_sqrt : issue_slots_20_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_div = _T_214 ? issue_slots_22_out_uop_fp_ctrl_div : _T_213 ? issue_slots_21_out_uop_fp_ctrl_div : issue_slots_20_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_fma = _T_214 ? issue_slots_22_out_uop_fp_ctrl_fma : _T_213 ? issue_slots_21_out_uop_fp_ctrl_fma : issue_slots_20_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_fastpipe = _T_214 ? issue_slots_22_out_uop_fp_ctrl_fastpipe : _T_213 ? issue_slots_21_out_uop_fp_ctrl_fastpipe : issue_slots_20_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_toint = _T_214 ? issue_slots_22_out_uop_fp_ctrl_toint : _T_213 ? issue_slots_21_out_uop_fp_ctrl_toint : issue_slots_20_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_fromint = _T_214 ? issue_slots_22_out_uop_fp_ctrl_fromint : _T_213 ? issue_slots_21_out_uop_fp_ctrl_fromint : issue_slots_20_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_typeTagOut = _T_214 ? issue_slots_22_out_uop_fp_ctrl_typeTagOut : _T_213 ? issue_slots_21_out_uop_fp_ctrl_typeTagOut : issue_slots_20_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_typeTagIn = _T_214 ? issue_slots_22_out_uop_fp_ctrl_typeTagIn : _T_213 ? issue_slots_21_out_uop_fp_ctrl_typeTagIn : issue_slots_20_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_swap23 = _T_214 ? issue_slots_22_out_uop_fp_ctrl_swap23 : _T_213 ? issue_slots_21_out_uop_fp_ctrl_swap23 : issue_slots_20_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_swap12 = _T_214 ? issue_slots_22_out_uop_fp_ctrl_swap12 : _T_213 ? issue_slots_21_out_uop_fp_ctrl_swap12 : issue_slots_20_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_ren3 = _T_214 ? issue_slots_22_out_uop_fp_ctrl_ren3 : _T_213 ? issue_slots_21_out_uop_fp_ctrl_ren3 : issue_slots_20_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_ren2 = _T_214 ? issue_slots_22_out_uop_fp_ctrl_ren2 : _T_213 ? issue_slots_21_out_uop_fp_ctrl_ren2 : issue_slots_20_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_ren1 = _T_214 ? issue_slots_22_out_uop_fp_ctrl_ren1 : _T_213 ? issue_slots_21_out_uop_fp_ctrl_ren1 : issue_slots_20_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_wen = _T_214 ? issue_slots_22_out_uop_fp_ctrl_wen : _T_213 ? issue_slots_21_out_uop_fp_ctrl_wen : issue_slots_20_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_ldst = _T_214 ? issue_slots_22_out_uop_fp_ctrl_ldst : _T_213 ? issue_slots_21_out_uop_fp_ctrl_ldst : issue_slots_20_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_op2_sel = _T_214 ? issue_slots_22_out_uop_op2_sel : _T_213 ? issue_slots_21_out_uop_op2_sel : issue_slots_20_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_op1_sel = _T_214 ? issue_slots_22_out_uop_op1_sel : _T_213 ? issue_slots_21_out_uop_op1_sel : issue_slots_20_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_imm_packed = _T_214 ? issue_slots_22_out_uop_imm_packed : _T_213 ? issue_slots_21_out_uop_imm_packed : issue_slots_20_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_pimm = _T_214 ? issue_slots_22_out_uop_pimm : _T_213 ? issue_slots_21_out_uop_pimm : issue_slots_20_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_imm_sel = _T_214 ? issue_slots_22_out_uop_imm_sel : _T_213 ? issue_slots_21_out_uop_imm_sel : issue_slots_20_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_imm_rename = _T_214 ? issue_slots_22_out_uop_imm_rename : _T_213 ? issue_slots_21_out_uop_imm_rename : issue_slots_20_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_taken = _T_214 ? issue_slots_22_out_uop_taken : _T_213 ? issue_slots_21_out_uop_taken : issue_slots_20_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_pc_lob = _T_214 ? issue_slots_22_out_uop_pc_lob : _T_213 ? issue_slots_21_out_uop_pc_lob : issue_slots_20_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_edge_inst = _T_214 ? issue_slots_22_out_uop_edge_inst : _T_213 ? issue_slots_21_out_uop_edge_inst : issue_slots_20_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_ftq_idx = _T_214 ? issue_slots_22_out_uop_ftq_idx : _T_213 ? issue_slots_21_out_uop_ftq_idx : issue_slots_20_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_is_mov = _T_214 ? issue_slots_22_out_uop_is_mov : _T_213 ? issue_slots_21_out_uop_is_mov : issue_slots_20_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_is_rocc = _T_214 ? issue_slots_22_out_uop_is_rocc : _T_213 ? issue_slots_21_out_uop_is_rocc : issue_slots_20_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_is_sys_pc2epc = _T_214 ? issue_slots_22_out_uop_is_sys_pc2epc : _T_213 ? issue_slots_21_out_uop_is_sys_pc2epc : issue_slots_20_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_is_eret = _T_214 ? issue_slots_22_out_uop_is_eret : _T_213 ? issue_slots_21_out_uop_is_eret : issue_slots_20_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_is_amo = _T_214 ? issue_slots_22_out_uop_is_amo : _T_213 ? issue_slots_21_out_uop_is_amo : issue_slots_20_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_is_sfence = _T_214 ? issue_slots_22_out_uop_is_sfence : _T_213 ? issue_slots_21_out_uop_is_sfence : issue_slots_20_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_is_fencei = _T_214 ? issue_slots_22_out_uop_is_fencei : _T_213 ? issue_slots_21_out_uop_is_fencei : issue_slots_20_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_is_fence = _T_214 ? issue_slots_22_out_uop_is_fence : _T_213 ? issue_slots_21_out_uop_is_fence : issue_slots_20_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_is_sfb = _T_214 ? issue_slots_22_out_uop_is_sfb : _T_213 ? issue_slots_21_out_uop_is_sfb : issue_slots_20_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_br_type = _T_214 ? issue_slots_22_out_uop_br_type : _T_213 ? issue_slots_21_out_uop_br_type : issue_slots_20_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_br_tag = _T_214 ? issue_slots_22_out_uop_br_tag : _T_213 ? issue_slots_21_out_uop_br_tag : issue_slots_20_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_br_mask = _T_214 ? issue_slots_22_out_uop_br_mask : _T_213 ? issue_slots_21_out_uop_br_mask : issue_slots_20_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_dis_col_sel = _T_214 ? issue_slots_22_out_uop_dis_col_sel : _T_213 ? issue_slots_21_out_uop_dis_col_sel : issue_slots_20_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_iw_p3_bypass_hint = _T_214 ? issue_slots_22_out_uop_iw_p3_bypass_hint : _T_213 ? issue_slots_21_out_uop_iw_p3_bypass_hint : issue_slots_20_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_iw_p2_bypass_hint = _T_214 ? issue_slots_22_out_uop_iw_p2_bypass_hint : _T_213 ? issue_slots_21_out_uop_iw_p2_bypass_hint : issue_slots_20_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_iw_p1_bypass_hint = _T_214 ? issue_slots_22_out_uop_iw_p1_bypass_hint : _T_213 ? issue_slots_21_out_uop_iw_p1_bypass_hint : issue_slots_20_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_iw_issued = _T_214 ? issue_slots_22_out_uop_iw_issued : _T_213 ? issue_slots_21_out_uop_iw_issued : issue_slots_20_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fu_code_0 = _T_214 ? issue_slots_22_out_uop_fu_code_0 : _T_213 ? issue_slots_21_out_uop_fu_code_0 : issue_slots_20_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fu_code_1 = _T_214 ? issue_slots_22_out_uop_fu_code_1 : _T_213 ? issue_slots_21_out_uop_fu_code_1 : issue_slots_20_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fu_code_2 = _T_214 ? issue_slots_22_out_uop_fu_code_2 : _T_213 ? issue_slots_21_out_uop_fu_code_2 : issue_slots_20_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fu_code_3 = _T_214 ? issue_slots_22_out_uop_fu_code_3 : _T_213 ? issue_slots_21_out_uop_fu_code_3 : issue_slots_20_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fu_code_4 = _T_214 ? issue_slots_22_out_uop_fu_code_4 : _T_213 ? issue_slots_21_out_uop_fu_code_4 : issue_slots_20_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fu_code_5 = _T_214 ? issue_slots_22_out_uop_fu_code_5 : _T_213 ? issue_slots_21_out_uop_fu_code_5 : issue_slots_20_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fu_code_6 = _T_214 ? issue_slots_22_out_uop_fu_code_6 : _T_213 ? issue_slots_21_out_uop_fu_code_6 : issue_slots_20_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fu_code_7 = _T_214 ? issue_slots_22_out_uop_fu_code_7 : _T_213 ? issue_slots_21_out_uop_fu_code_7 : issue_slots_20_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fu_code_8 = _T_214 ? issue_slots_22_out_uop_fu_code_8 : _T_213 ? issue_slots_21_out_uop_fu_code_8 : issue_slots_20_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fu_code_9 = _T_214 ? issue_slots_22_out_uop_fu_code_9 : _T_213 ? issue_slots_21_out_uop_fu_code_9 : issue_slots_20_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_iq_type_0 = _T_214 ? issue_slots_22_out_uop_iq_type_0 : _T_213 ? issue_slots_21_out_uop_iq_type_0 : issue_slots_20_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_iq_type_1 = _T_214 ? issue_slots_22_out_uop_iq_type_1 : _T_213 ? issue_slots_21_out_uop_iq_type_1 : issue_slots_20_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_iq_type_2 = _T_214 ? issue_slots_22_out_uop_iq_type_2 : _T_213 ? issue_slots_21_out_uop_iq_type_2 : issue_slots_20_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_iq_type_3 = _T_214 ? issue_slots_22_out_uop_iq_type_3 : _T_213 ? issue_slots_21_out_uop_iq_type_3 : issue_slots_20_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_debug_pc = _T_214 ? issue_slots_22_out_uop_debug_pc : _T_213 ? issue_slots_21_out_uop_debug_pc : issue_slots_20_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_is_rvc = _T_214 ? issue_slots_22_out_uop_is_rvc : _T_213 ? issue_slots_21_out_uop_is_rvc : issue_slots_20_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_debug_inst = _T_214 ? issue_slots_22_out_uop_debug_inst : _T_213 ? issue_slots_21_out_uop_debug_inst : issue_slots_20_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_inst = _T_214 ? issue_slots_22_out_uop_inst : _T_213 ? issue_slots_21_out_uop_inst : issue_slots_20_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_19_clear_T = \|shamts_oh_19; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_19_clear = _issue_slots_19_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_216 = shamts_oh_22 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_217 = shamts_oh_23 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_20_in_uop_valid = _T_217 ? issue_slots_23_will_be_valid : _T_216 ? issue_slots_22_will_be_valid : shamts_oh_21 == 3'h1 & issue_slots_21_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_20_in_uop_bits_debug_tsrc = _T_217 ? issue_slots_23_out_uop_debug_tsrc : _T_216 ? issue_slots_22_out_uop_debug_tsrc : issue_slots_21_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_debug_fsrc = _T_217 ? issue_slots_23_out_uop_debug_fsrc : _T_216 ? issue_slots_22_out_uop_debug_fsrc : issue_slots_21_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_bp_xcpt_if = _T_217 ? issue_slots_23_out_uop_bp_xcpt_if : _T_216 ? issue_slots_22_out_uop_bp_xcpt_if : issue_slots_21_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_bp_debug_if = _T_217 ? issue_slots_23_out_uop_bp_debug_if : _T_216 ? issue_slots_22_out_uop_bp_debug_if : issue_slots_21_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_xcpt_ma_if = _T_217 ? issue_slots_23_out_uop_xcpt_ma_if : _T_216 ? issue_slots_22_out_uop_xcpt_ma_if : issue_slots_21_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_xcpt_ae_if = _T_217 ? issue_slots_23_out_uop_xcpt_ae_if : _T_216 ? issue_slots_22_out_uop_xcpt_ae_if : issue_slots_21_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_xcpt_pf_if = _T_217 ? issue_slots_23_out_uop_xcpt_pf_if : _T_216 ? issue_slots_22_out_uop_xcpt_pf_if : issue_slots_21_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_typ = _T_217 ? issue_slots_23_out_uop_fp_typ : _T_216 ? issue_slots_22_out_uop_fp_typ : issue_slots_21_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_rm = _T_217 ? issue_slots_23_out_uop_fp_rm : _T_216 ? issue_slots_22_out_uop_fp_rm : issue_slots_21_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_val = _T_217 ? issue_slots_23_out_uop_fp_val : _T_216 ? issue_slots_22_out_uop_fp_val : issue_slots_21_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fcn_op = _T_217 ? issue_slots_23_out_uop_fcn_op : _T_216 ? issue_slots_22_out_uop_fcn_op : issue_slots_21_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fcn_dw = _T_217 ? issue_slots_23_out_uop_fcn_dw : _T_216 ? issue_slots_22_out_uop_fcn_dw : issue_slots_21_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_frs3_en = _T_217 ? issue_slots_23_out_uop_frs3_en : _T_216 ? issue_slots_22_out_uop_frs3_en : issue_slots_21_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_lrs2_rtype = _T_217 ? issue_slots_23_out_uop_lrs2_rtype : _T_216 ? issue_slots_22_out_uop_lrs2_rtype : issue_slots_21_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_lrs1_rtype = _T_217 ? issue_slots_23_out_uop_lrs1_rtype : _T_216 ? issue_slots_22_out_uop_lrs1_rtype : issue_slots_21_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_dst_rtype = _T_217 ? issue_slots_23_out_uop_dst_rtype : _T_216 ? issue_slots_22_out_uop_dst_rtype : issue_slots_21_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_lrs3 = _T_217 ? issue_slots_23_out_uop_lrs3 : _T_216 ? issue_slots_22_out_uop_lrs3 : issue_slots_21_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_lrs2 = _T_217 ? issue_slots_23_out_uop_lrs2 : _T_216 ? issue_slots_22_out_uop_lrs2 : issue_slots_21_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_lrs1 = _T_217 ? issue_slots_23_out_uop_lrs1 : _T_216 ? issue_slots_22_out_uop_lrs1 : issue_slots_21_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_ldst = _T_217 ? issue_slots_23_out_uop_ldst : _T_216 ? issue_slots_22_out_uop_ldst : issue_slots_21_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_ldst_is_rs1 = _T_217 ? issue_slots_23_out_uop_ldst_is_rs1 : _T_216 ? issue_slots_22_out_uop_ldst_is_rs1 : issue_slots_21_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_csr_cmd = _T_217 ? issue_slots_23_out_uop_csr_cmd : _T_216 ? issue_slots_22_out_uop_csr_cmd : issue_slots_21_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_flush_on_commit = _T_217 ? issue_slots_23_out_uop_flush_on_commit : _T_216 ? issue_slots_22_out_uop_flush_on_commit : issue_slots_21_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_is_unique = _T_217 ? issue_slots_23_out_uop_is_unique : _T_216 ? issue_slots_22_out_uop_is_unique : issue_slots_21_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_uses_stq = _T_217 ? issue_slots_23_out_uop_uses_stq : _T_216 ? issue_slots_22_out_uop_uses_stq : issue_slots_21_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_uses_ldq = _T_217 ? issue_slots_23_out_uop_uses_ldq : _T_216 ? issue_slots_22_out_uop_uses_ldq : issue_slots_21_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_mem_signed = _T_217 ? issue_slots_23_out_uop_mem_signed : _T_216 ? issue_slots_22_out_uop_mem_signed : issue_slots_21_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_mem_size = _T_217 ? issue_slots_23_out_uop_mem_size : _T_216 ? issue_slots_22_out_uop_mem_size : issue_slots_21_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_mem_cmd = _T_217 ? issue_slots_23_out_uop_mem_cmd : _T_216 ? issue_slots_22_out_uop_mem_cmd : issue_slots_21_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_exc_cause = _T_217 ? issue_slots_23_out_uop_exc_cause : _T_216 ? issue_slots_22_out_uop_exc_cause : issue_slots_21_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_exception = _T_217 ? issue_slots_23_out_uop_exception : _T_216 ? issue_slots_22_out_uop_exception : issue_slots_21_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_stale_pdst = _T_217 ? issue_slots_23_out_uop_stale_pdst : _T_216 ? issue_slots_22_out_uop_stale_pdst : issue_slots_21_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_ppred_busy = _T_217 ? issue_slots_23_out_uop_ppred_busy : _T_216 ? issue_slots_22_out_uop_ppred_busy : issue_slots_21_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_prs3_busy = _T_217 ? issue_slots_23_out_uop_prs3_busy : _T_216 ? issue_slots_22_out_uop_prs3_busy : issue_slots_21_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_prs2_busy = _T_217 ? issue_slots_23_out_uop_prs2_busy : _T_216 ? issue_slots_22_out_uop_prs2_busy : issue_slots_21_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_prs1_busy = _T_217 ? issue_slots_23_out_uop_prs1_busy : _T_216 ? issue_slots_22_out_uop_prs1_busy : issue_slots_21_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_ppred = _T_217 ? issue_slots_23_out_uop_ppred : _T_216 ? issue_slots_22_out_uop_ppred : issue_slots_21_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_prs3 = _T_217 ? issue_slots_23_out_uop_prs3 : _T_216 ? issue_slots_22_out_uop_prs3 : issue_slots_21_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_prs2 = _T_217 ? issue_slots_23_out_uop_prs2 : _T_216 ? issue_slots_22_out_uop_prs2 : issue_slots_21_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_prs1 = _T_217 ? issue_slots_23_out_uop_prs1 : _T_216 ? issue_slots_22_out_uop_prs1 : issue_slots_21_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_pdst = _T_217 ? issue_slots_23_out_uop_pdst : _T_216 ? issue_slots_22_out_uop_pdst : issue_slots_21_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_rxq_idx = _T_217 ? issue_slots_23_out_uop_rxq_idx : _T_216 ? issue_slots_22_out_uop_rxq_idx : issue_slots_21_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_stq_idx = _T_217 ? issue_slots_23_out_uop_stq_idx : _T_216 ? issue_slots_22_out_uop_stq_idx : issue_slots_21_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_ldq_idx = _T_217 ? issue_slots_23_out_uop_ldq_idx : _T_216 ? issue_slots_22_out_uop_ldq_idx : issue_slots_21_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_rob_idx = _T_217 ? issue_slots_23_out_uop_rob_idx : _T_216 ? issue_slots_22_out_uop_rob_idx : issue_slots_21_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_vec = _T_217 ? issue_slots_23_out_uop_fp_ctrl_vec : _T_216 ? issue_slots_22_out_uop_fp_ctrl_vec : issue_slots_21_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_wflags = _T_217 ? issue_slots_23_out_uop_fp_ctrl_wflags : _T_216 ? issue_slots_22_out_uop_fp_ctrl_wflags : issue_slots_21_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_sqrt = _T_217 ? issue_slots_23_out_uop_fp_ctrl_sqrt : _T_216 ? issue_slots_22_out_uop_fp_ctrl_sqrt : issue_slots_21_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_div = _T_217 ? issue_slots_23_out_uop_fp_ctrl_div : _T_216 ? issue_slots_22_out_uop_fp_ctrl_div : issue_slots_21_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_fma = _T_217 ? issue_slots_23_out_uop_fp_ctrl_fma : _T_216 ? issue_slots_22_out_uop_fp_ctrl_fma : issue_slots_21_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_fastpipe = _T_217 ? issue_slots_23_out_uop_fp_ctrl_fastpipe : _T_216 ? issue_slots_22_out_uop_fp_ctrl_fastpipe : issue_slots_21_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_toint = _T_217 ? issue_slots_23_out_uop_fp_ctrl_toint : _T_216 ? issue_slots_22_out_uop_fp_ctrl_toint : issue_slots_21_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_fromint = _T_217 ? issue_slots_23_out_uop_fp_ctrl_fromint : _T_216 ? issue_slots_22_out_uop_fp_ctrl_fromint : issue_slots_21_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_typeTagOut = _T_217 ? issue_slots_23_out_uop_fp_ctrl_typeTagOut : _T_216 ? issue_slots_22_out_uop_fp_ctrl_typeTagOut : issue_slots_21_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_typeTagIn = _T_217 ? issue_slots_23_out_uop_fp_ctrl_typeTagIn : _T_216 ? issue_slots_22_out_uop_fp_ctrl_typeTagIn : issue_slots_21_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_swap23 = _T_217 ? issue_slots_23_out_uop_fp_ctrl_swap23 : _T_216 ? issue_slots_22_out_uop_fp_ctrl_swap23 : issue_slots_21_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_swap12 = _T_217 ? issue_slots_23_out_uop_fp_ctrl_swap12 : _T_216 ? issue_slots_22_out_uop_fp_ctrl_swap12 : issue_slots_21_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_ren3 = _T_217 ? issue_slots_23_out_uop_fp_ctrl_ren3 : _T_216 ? issue_slots_22_out_uop_fp_ctrl_ren3 : issue_slots_21_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_ren2 = _T_217 ? issue_slots_23_out_uop_fp_ctrl_ren2 : _T_216 ? issue_slots_22_out_uop_fp_ctrl_ren2 : issue_slots_21_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_ren1 = _T_217 ? issue_slots_23_out_uop_fp_ctrl_ren1 : _T_216 ? issue_slots_22_out_uop_fp_ctrl_ren1 : issue_slots_21_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_wen = _T_217 ? issue_slots_23_out_uop_fp_ctrl_wen : _T_216 ? issue_slots_22_out_uop_fp_ctrl_wen : issue_slots_21_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_ldst = _T_217 ? issue_slots_23_out_uop_fp_ctrl_ldst : _T_216 ? issue_slots_22_out_uop_fp_ctrl_ldst : issue_slots_21_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_op2_sel = _T_217 ? issue_slots_23_out_uop_op2_sel : _T_216 ? issue_slots_22_out_uop_op2_sel : issue_slots_21_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_op1_sel = _T_217 ? issue_slots_23_out_uop_op1_sel : _T_216 ? issue_slots_22_out_uop_op1_sel : issue_slots_21_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_imm_packed = _T_217 ? issue_slots_23_out_uop_imm_packed : _T_216 ? issue_slots_22_out_uop_imm_packed : issue_slots_21_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_pimm = _T_217 ? issue_slots_23_out_uop_pimm : _T_216 ? issue_slots_22_out_uop_pimm : issue_slots_21_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_imm_sel = _T_217 ? issue_slots_23_out_uop_imm_sel : _T_216 ? issue_slots_22_out_uop_imm_sel : issue_slots_21_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_imm_rename = _T_217 ? issue_slots_23_out_uop_imm_rename : _T_216 ? issue_slots_22_out_uop_imm_rename : issue_slots_21_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_taken = _T_217 ? issue_slots_23_out_uop_taken : _T_216 ? issue_slots_22_out_uop_taken : issue_slots_21_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_pc_lob = _T_217 ? issue_slots_23_out_uop_pc_lob : _T_216 ? issue_slots_22_out_uop_pc_lob : issue_slots_21_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_edge_inst = _T_217 ? issue_slots_23_out_uop_edge_inst : _T_216 ? issue_slots_22_out_uop_edge_inst : issue_slots_21_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_ftq_idx = _T_217 ? issue_slots_23_out_uop_ftq_idx : _T_216 ? issue_slots_22_out_uop_ftq_idx : issue_slots_21_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_is_mov = _T_217 ? issue_slots_23_out_uop_is_mov : _T_216 ? issue_slots_22_out_uop_is_mov : issue_slots_21_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_is_rocc = _T_217 ? issue_slots_23_out_uop_is_rocc : _T_216 ? issue_slots_22_out_uop_is_rocc : issue_slots_21_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_is_sys_pc2epc = _T_217 ? issue_slots_23_out_uop_is_sys_pc2epc : _T_216 ? issue_slots_22_out_uop_is_sys_pc2epc : issue_slots_21_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_is_eret = _T_217 ? issue_slots_23_out_uop_is_eret : _T_216 ? issue_slots_22_out_uop_is_eret : issue_slots_21_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_is_amo = _T_217 ? issue_slots_23_out_uop_is_amo : _T_216 ? issue_slots_22_out_uop_is_amo : issue_slots_21_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_is_sfence = _T_217 ? issue_slots_23_out_uop_is_sfence : _T_216 ? issue_slots_22_out_uop_is_sfence : issue_slots_21_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_is_fencei = _T_217 ? issue_slots_23_out_uop_is_fencei : _T_216 ? issue_slots_22_out_uop_is_fencei : issue_slots_21_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_is_fence = _T_217 ? issue_slots_23_out_uop_is_fence : _T_216 ? issue_slots_22_out_uop_is_fence : issue_slots_21_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_is_sfb = _T_217 ? issue_slots_23_out_uop_is_sfb : _T_216 ? issue_slots_22_out_uop_is_sfb : issue_slots_21_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_br_type = _T_217 ? issue_slots_23_out_uop_br_type : _T_216 ? issue_slots_22_out_uop_br_type : issue_slots_21_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_br_tag = _T_217 ? issue_slots_23_out_uop_br_tag : _T_216 ? issue_slots_22_out_uop_br_tag : issue_slots_21_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_br_mask = _T_217 ? issue_slots_23_out_uop_br_mask : _T_216 ? issue_slots_22_out_uop_br_mask : issue_slots_21_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_dis_col_sel = _T_217 ? issue_slots_23_out_uop_dis_col_sel : _T_216 ? issue_slots_22_out_uop_dis_col_sel : issue_slots_21_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_iw_p3_bypass_hint = _T_217 ? issue_slots_23_out_uop_iw_p3_bypass_hint : _T_216 ? issue_slots_22_out_uop_iw_p3_bypass_hint : issue_slots_21_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_iw_p2_bypass_hint = _T_217 ? issue_slots_23_out_uop_iw_p2_bypass_hint : _T_216 ? issue_slots_22_out_uop_iw_p2_bypass_hint : issue_slots_21_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_iw_p1_bypass_hint = _T_217 ? issue_slots_23_out_uop_iw_p1_bypass_hint : _T_216 ? issue_slots_22_out_uop_iw_p1_bypass_hint : issue_slots_21_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_iw_issued = _T_217 ? issue_slots_23_out_uop_iw_issued : _T_216 ? issue_slots_22_out_uop_iw_issued : issue_slots_21_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fu_code_0 = _T_217 ? issue_slots_23_out_uop_fu_code_0 : _T_216 ? issue_slots_22_out_uop_fu_code_0 : issue_slots_21_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fu_code_1 = _T_217 ? issue_slots_23_out_uop_fu_code_1 : _T_216 ? issue_slots_22_out_uop_fu_code_1 : issue_slots_21_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fu_code_2 = _T_217 ? issue_slots_23_out_uop_fu_code_2 : _T_216 ? issue_slots_22_out_uop_fu_code_2 : issue_slots_21_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fu_code_3 = _T_217 ? issue_slots_23_out_uop_fu_code_3 : _T_216 ? issue_slots_22_out_uop_fu_code_3 : issue_slots_21_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fu_code_4 = _T_217 ? issue_slots_23_out_uop_fu_code_4 : _T_216 ? issue_slots_22_out_uop_fu_code_4 : issue_slots_21_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fu_code_5 = _T_217 ? issue_slots_23_out_uop_fu_code_5 : _T_216 ? issue_slots_22_out_uop_fu_code_5 : issue_slots_21_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fu_code_6 = _T_217 ? issue_slots_23_out_uop_fu_code_6 : _T_216 ? issue_slots_22_out_uop_fu_code_6 : issue_slots_21_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fu_code_7 = _T_217 ? issue_slots_23_out_uop_fu_code_7 : _T_216 ? issue_slots_22_out_uop_fu_code_7 : issue_slots_21_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fu_code_8 = _T_217 ? issue_slots_23_out_uop_fu_code_8 : _T_216 ? issue_slots_22_out_uop_fu_code_8 : issue_slots_21_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fu_code_9 = _T_217 ? issue_slots_23_out_uop_fu_code_9 : _T_216 ? issue_slots_22_out_uop_fu_code_9 : issue_slots_21_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_iq_type_0 = _T_217 ? issue_slots_23_out_uop_iq_type_0 : _T_216 ? issue_slots_22_out_uop_iq_type_0 : issue_slots_21_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_iq_type_1 = _T_217 ? issue_slots_23_out_uop_iq_type_1 : _T_216 ? issue_slots_22_out_uop_iq_type_1 : issue_slots_21_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_iq_type_2 = _T_217 ? issue_slots_23_out_uop_iq_type_2 : _T_216 ? issue_slots_22_out_uop_iq_type_2 : issue_slots_21_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_iq_type_3 = _T_217 ? issue_slots_23_out_uop_iq_type_3 : _T_216 ? issue_slots_22_out_uop_iq_type_3 : issue_slots_21_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_debug_pc = _T_217 ? issue_slots_23_out_uop_debug_pc : _T_216 ? issue_slots_22_out_uop_debug_pc : issue_slots_21_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_is_rvc = _T_217 ? issue_slots_23_out_uop_is_rvc : _T_216 ? issue_slots_22_out_uop_is_rvc : issue_slots_21_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_debug_inst = _T_217 ? issue_slots_23_out_uop_debug_inst : _T_216 ? issue_slots_22_out_uop_debug_inst : issue_slots_21_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_inst = _T_217 ? issue_slots_23_out_uop_inst : _T_216 ? issue_slots_22_out_uop_inst : issue_slots_21_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_20_clear_T = \|shamts_oh_20; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_20_clear = _issue_slots_20_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_219 = shamts_oh_23 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_220 = shamts_oh_24 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_21_in_uop_valid = _T_220 ? will_be_valid_24 : _T_219 ? issue_slots_23_will_be_valid : shamts_oh_22 == 3'h1 & issue_slots_22_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :186:79, :191:33, :194:{28,48}, :195:37] assign issue_slots_21_in_uop_bits_debug_tsrc = _T_220 ? io_dis_uops_0_bits_debug_tsrc_0 : _T_219 ? issue_slots_23_out_uop_debug_tsrc : issue_slots_22_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_debug_fsrc = _T_220 ? io_dis_uops_0_bits_debug_fsrc_0 : _T_219 ? issue_slots_23_out_uop_debug_fsrc : issue_slots_22_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_bp_xcpt_if = _T_220 ? io_dis_uops_0_bits_bp_xcpt_if_0 : _T_219 ? issue_slots_23_out_uop_bp_xcpt_if : issue_slots_22_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_bp_debug_if = _T_220 ? io_dis_uops_0_bits_bp_debug_if_0 : _T_219 ? issue_slots_23_out_uop_bp_debug_if : issue_slots_22_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_xcpt_ma_if = _T_220 ? io_dis_uops_0_bits_xcpt_ma_if_0 : _T_219 ? issue_slots_23_out_uop_xcpt_ma_if : issue_slots_22_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_xcpt_ae_if = _T_220 ? io_dis_uops_0_bits_xcpt_ae_if_0 : _T_219 ? issue_slots_23_out_uop_xcpt_ae_if : issue_slots_22_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_xcpt_pf_if = _T_220 ? io_dis_uops_0_bits_xcpt_pf_if_0 : _T_219 ? issue_slots_23_out_uop_xcpt_pf_if : issue_slots_22_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_typ = _T_220 ? io_dis_uops_0_bits_fp_typ_0 : _T_219 ? issue_slots_23_out_uop_fp_typ : issue_slots_22_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_rm = _T_220 ? io_dis_uops_0_bits_fp_rm_0 : _T_219 ? issue_slots_23_out_uop_fp_rm : issue_slots_22_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_val = _T_220 ? io_dis_uops_0_bits_fp_val_0 : _T_219 ? issue_slots_23_out_uop_fp_val : issue_slots_22_out_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fcn_op = _T_220 ? io_dis_uops_0_bits_fcn_op_0 : _T_219 ? issue_slots_23_out_uop_fcn_op : issue_slots_22_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fcn_dw = _T_220 ? io_dis_uops_0_bits_fcn_dw_0 : _T_219 ? issue_slots_23_out_uop_fcn_dw : issue_slots_22_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_frs3_en = _T_220 ? io_dis_uops_0_bits_frs3_en_0 : _T_219 ? issue_slots_23_out_uop_frs3_en : issue_slots_22_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_lrs2_rtype = _T_220 ? io_dis_uops_0_bits_lrs2_rtype_0 : _T_219 ? issue_slots_23_out_uop_lrs2_rtype : issue_slots_22_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_lrs1_rtype = _T_220 ? _WIRE_lrs1_rtype : _T_219 ? issue_slots_23_out_uop_lrs1_rtype : issue_slots_22_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:35:17, :103:43, :104:32, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_dst_rtype = _T_220 ? io_dis_uops_0_bits_dst_rtype_0 : _T_219 ? issue_slots_23_out_uop_dst_rtype : issue_slots_22_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_lrs3 = _T_220 ? io_dis_uops_0_bits_lrs3_0 : _T_219 ? issue_slots_23_out_uop_lrs3 : issue_slots_22_out_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_lrs2 = _T_220 ? io_dis_uops_0_bits_lrs2_0 : _T_219 ? issue_slots_23_out_uop_lrs2 : issue_slots_22_out_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_lrs1 = _T_220 ? io_dis_uops_0_bits_lrs1_0 : _T_219 ? issue_slots_23_out_uop_lrs1 : issue_slots_22_out_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_ldst = _T_220 ? io_dis_uops_0_bits_ldst_0 : _T_219 ? issue_slots_23_out_uop_ldst : issue_slots_22_out_uop_ldst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_ldst_is_rs1 = _T_220 ? io_dis_uops_0_bits_ldst_is_rs1_0 : _T_219 ? issue_slots_23_out_uop_ldst_is_rs1 : issue_slots_22_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_csr_cmd = _T_220 ? io_dis_uops_0_bits_csr_cmd_0 : _T_219 ? issue_slots_23_out_uop_csr_cmd : issue_slots_22_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_flush_on_commit = _T_220 ? io_dis_uops_0_bits_flush_on_commit_0 : _T_219 ? issue_slots_23_out_uop_flush_on_commit : issue_slots_22_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_is_unique = _T_220 ? io_dis_uops_0_bits_is_unique_0 : _T_219 ? issue_slots_23_out_uop_is_unique : issue_slots_22_out_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_uses_stq = _T_220 ? io_dis_uops_0_bits_uses_stq_0 : _T_219 ? issue_slots_23_out_uop_uses_stq : issue_slots_22_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_uses_ldq = _T_220 ? io_dis_uops_0_bits_uses_ldq_0 : _T_219 ? issue_slots_23_out_uop_uses_ldq : issue_slots_22_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_mem_signed = _T_220 ? io_dis_uops_0_bits_mem_signed_0 : _T_219 ? issue_slots_23_out_uop_mem_signed : issue_slots_22_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_mem_size = _T_220 ? io_dis_uops_0_bits_mem_size_0 : _T_219 ? issue_slots_23_out_uop_mem_size : issue_slots_22_out_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_mem_cmd = _T_220 ? io_dis_uops_0_bits_mem_cmd_0 : _T_219 ? issue_slots_23_out_uop_mem_cmd : issue_slots_22_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_exc_cause = _T_220 ? io_dis_uops_0_bits_exc_cause_0 : _T_219 ? issue_slots_23_out_uop_exc_cause : issue_slots_22_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_exception = _T_220 ? io_dis_uops_0_bits_exception_0 : _T_219 ? issue_slots_23_out_uop_exception : issue_slots_22_out_uop_exception; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_stale_pdst = _T_220 ? io_dis_uops_0_bits_stale_pdst_0 : _T_219 ? issue_slots_23_out_uop_stale_pdst : issue_slots_22_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_ppred_busy = ~_T_220 & (_T_219 ? issue_slots_23_out_uop_ppred_busy : issue_slots_22_out_uop_ppred_busy); // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_prs3_busy = _T_220 ? _WIRE_prs3_busy : _T_219 ? issue_slots_23_out_uop_prs3_busy : issue_slots_22_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:35:17, :76:38, :77:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_prs2_busy = _T_220 ? _WIRE_prs2_busy : _T_219 ? issue_slots_23_out_uop_prs2_busy : issue_slots_22_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:35:17, :65:38, :66:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_prs1_busy = _T_220 ? _WIRE_prs1_busy : _T_219 ? issue_slots_23_out_uop_prs1_busy : issue_slots_22_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:35:17, :57:38, :58:29, :62:116, :103:43, :105:32, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_ppred = _T_220 ? io_dis_uops_0_bits_ppred_0 : _T_219 ? issue_slots_23_out_uop_ppred : issue_slots_22_out_uop_ppred; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_prs3 = _T_220 ? io_dis_uops_0_bits_prs3_0 : _T_219 ? issue_slots_23_out_uop_prs3 : issue_slots_22_out_uop_prs3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_prs2 = _T_220 ? io_dis_uops_0_bits_prs2_0 : _T_219 ? issue_slots_23_out_uop_prs2 : issue_slots_22_out_uop_prs2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_prs1 = _T_220 ? io_dis_uops_0_bits_prs1_0 : _T_219 ? issue_slots_23_out_uop_prs1 : issue_slots_22_out_uop_prs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_pdst = _T_220 ? io_dis_uops_0_bits_pdst_0 : _T_219 ? issue_slots_23_out_uop_pdst : issue_slots_22_out_uop_pdst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_rxq_idx = _T_220 ? io_dis_uops_0_bits_rxq_idx_0 : _T_219 ? issue_slots_23_out_uop_rxq_idx : issue_slots_22_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_stq_idx = _T_220 ? io_dis_uops_0_bits_stq_idx_0 : _T_219 ? issue_slots_23_out_uop_stq_idx : issue_slots_22_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_ldq_idx = _T_220 ? io_dis_uops_0_bits_ldq_idx_0 : _T_219 ? issue_slots_23_out_uop_ldq_idx : issue_slots_22_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_rob_idx = _T_220 ? io_dis_uops_0_bits_rob_idx_0 : _T_219 ? issue_slots_23_out_uop_rob_idx : issue_slots_22_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_vec = _T_220 ? io_dis_uops_0_bits_fp_ctrl_vec_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_vec : issue_slots_22_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_wflags = _T_220 ? io_dis_uops_0_bits_fp_ctrl_wflags_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_wflags : issue_slots_22_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_sqrt = _T_220 ? io_dis_uops_0_bits_fp_ctrl_sqrt_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_sqrt : issue_slots_22_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_div = _T_220 ? io_dis_uops_0_bits_fp_ctrl_div_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_div : issue_slots_22_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_fma = _T_220 ? io_dis_uops_0_bits_fp_ctrl_fma_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_fma : issue_slots_22_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_fastpipe = _T_220 ? io_dis_uops_0_bits_fp_ctrl_fastpipe_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_fastpipe : issue_slots_22_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_toint = _T_220 ? io_dis_uops_0_bits_fp_ctrl_toint_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_toint : issue_slots_22_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_fromint = _T_220 ? io_dis_uops_0_bits_fp_ctrl_fromint_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_fromint : issue_slots_22_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_typeTagOut = _T_220 ? io_dis_uops_0_bits_fp_ctrl_typeTagOut_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_typeTagOut : issue_slots_22_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_typeTagIn = _T_220 ? io_dis_uops_0_bits_fp_ctrl_typeTagIn_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_typeTagIn : issue_slots_22_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_swap23 = _T_220 ? io_dis_uops_0_bits_fp_ctrl_swap23_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_swap23 : issue_slots_22_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_swap12 = _T_220 ? io_dis_uops_0_bits_fp_ctrl_swap12_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_swap12 : issue_slots_22_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_ren3 = _T_220 ? io_dis_uops_0_bits_fp_ctrl_ren3_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_ren3 : issue_slots_22_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_ren2 = _T_220 ? io_dis_uops_0_bits_fp_ctrl_ren2_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_ren2 : issue_slots_22_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_ren1 = _T_220 ? io_dis_uops_0_bits_fp_ctrl_ren1_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_ren1 : issue_slots_22_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_wen = _T_220 ? io_dis_uops_0_bits_fp_ctrl_wen_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_wen : issue_slots_22_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_ldst = _T_220 ? io_dis_uops_0_bits_fp_ctrl_ldst_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_ldst : issue_slots_22_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_op2_sel = _T_220 ? io_dis_uops_0_bits_op2_sel_0 : _T_219 ? issue_slots_23_out_uop_op2_sel : issue_slots_22_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_op1_sel = _T_220 ? io_dis_uops_0_bits_op1_sel_0 : _T_219 ? issue_slots_23_out_uop_op1_sel : issue_slots_22_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_imm_packed = _T_220 ? io_dis_uops_0_bits_imm_packed_0 : _T_219 ? issue_slots_23_out_uop_imm_packed : issue_slots_22_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_pimm = _T_220 ? io_dis_uops_0_bits_pimm_0 : _T_219 ? issue_slots_23_out_uop_pimm : issue_slots_22_out_uop_pimm; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_imm_sel = _T_220 ? io_dis_uops_0_bits_imm_sel_0 : _T_219 ? issue_slots_23_out_uop_imm_sel : issue_slots_22_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_imm_rename = _T_220 ? io_dis_uops_0_bits_imm_rename_0 : _T_219 ? issue_slots_23_out_uop_imm_rename : issue_slots_22_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_taken = _T_220 ? io_dis_uops_0_bits_taken_0 : _T_219 ? issue_slots_23_out_uop_taken : issue_slots_22_out_uop_taken; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_pc_lob = _T_220 ? io_dis_uops_0_bits_pc_lob_0 : _T_219 ? issue_slots_23_out_uop_pc_lob : issue_slots_22_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_edge_inst = _T_220 ? io_dis_uops_0_bits_edge_inst_0 : _T_219 ? issue_slots_23_out_uop_edge_inst : issue_slots_22_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_ftq_idx = _T_220 ? io_dis_uops_0_bits_ftq_idx_0 : _T_219 ? issue_slots_23_out_uop_ftq_idx : issue_slots_22_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_is_mov = _T_220 ? io_dis_uops_0_bits_is_mov_0 : _T_219 ? issue_slots_23_out_uop_is_mov : issue_slots_22_out_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_is_rocc = _T_220 ? io_dis_uops_0_bits_is_rocc_0 : _T_219 ? issue_slots_23_out_uop_is_rocc : issue_slots_22_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_is_sys_pc2epc = _T_220 ? io_dis_uops_0_bits_is_sys_pc2epc_0 : _T_219 ? issue_slots_23_out_uop_is_sys_pc2epc : issue_slots_22_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_is_eret = _T_220 ? io_dis_uops_0_bits_is_eret_0 : _T_219 ? issue_slots_23_out_uop_is_eret : issue_slots_22_out_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_is_amo = _T_220 ? io_dis_uops_0_bits_is_amo_0 : _T_219 ? issue_slots_23_out_uop_is_amo : issue_slots_22_out_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_is_sfence = _T_220 ? io_dis_uops_0_bits_is_sfence_0 : _T_219 ? issue_slots_23_out_uop_is_sfence : issue_slots_22_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_is_fencei = _T_220 ? io_dis_uops_0_bits_is_fencei_0 : _T_219 ? issue_slots_23_out_uop_is_fencei : issue_slots_22_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_is_fence = _T_220 ? io_dis_uops_0_bits_is_fence_0 : _T_219 ? issue_slots_23_out_uop_is_fence : issue_slots_22_out_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_is_sfb = _T_220 ? io_dis_uops_0_bits_is_sfb_0 : _T_219 ? issue_slots_23_out_uop_is_sfb : issue_slots_22_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_br_type = _T_220 ? io_dis_uops_0_bits_br_type_0 : _T_219 ? issue_slots_23_out_uop_br_type : issue_slots_22_out_uop_br_type; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_br_tag = _T_220 ? io_dis_uops_0_bits_br_tag_0 : _T_219 ? issue_slots_23_out_uop_br_tag : issue_slots_22_out_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_br_mask = _T_220 ? io_dis_uops_0_bits_br_mask_0 : _T_219 ? issue_slots_23_out_uop_br_mask : issue_slots_22_out_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_dis_col_sel = _T_220 ? io_dis_uops_0_bits_dis_col_sel_0 : _T_219 ? issue_slots_23_out_uop_dis_col_sel : issue_slots_22_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_iw_p3_bypass_hint = _T_220 ? _WIRE_iw_p3_bypass_hint : _T_219 ? issue_slots_23_out_uop_iw_p3_bypass_hint : issue_slots_22_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:41:35, :76:38, :78:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_iw_p2_bypass_hint = _T_220 ? _WIRE_iw_p2_bypass_hint : _T_219 ? issue_slots_23_out_uop_iw_p2_bypass_hint : issue_slots_22_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:40:35, :65:38, :68:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_iw_p1_bypass_hint = _T_220 ? _WIRE_iw_p1_bypass_hint : _T_219 ? issue_slots_23_out_uop_iw_p1_bypass_hint : issue_slots_22_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:39:35, :57:38, :60:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_iw_p2_speculative_child = ~_T_220 \| _T_12 ? 3'h0 : io_dis_uops_0_bits_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :65:32, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_iw_p1_speculative_child = ~_T_220 \| _T ? 3'h0 : io_dis_uops_0_bits_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :57:32, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_iw_issued = ~_T_220 & (_T_219 ? issue_slots_23_out_uop_iw_issued : issue_slots_22_out_uop_iw_issued); // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fu_code_0 = _T_220 ? io_dis_uops_0_bits_fu_code_0_0 : _T_219 ? issue_slots_23_out_uop_fu_code_0 : issue_slots_22_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fu_code_1 = _T_220 ? io_dis_uops_0_bits_fu_code_1_0 : _T_219 ? issue_slots_23_out_uop_fu_code_1 : issue_slots_22_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fu_code_2 = _T_220 ? io_dis_uops_0_bits_fu_code_2_0 : _T_219 ? issue_slots_23_out_uop_fu_code_2 : issue_slots_22_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fu_code_3 = _T_220 ? io_dis_uops_0_bits_fu_code_3_0 : _T_219 ? issue_slots_23_out_uop_fu_code_3 : issue_slots_22_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fu_code_4 = _T_220 ? io_dis_uops_0_bits_fu_code_4_0 : _T_219 ? issue_slots_23_out_uop_fu_code_4 : issue_slots_22_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fu_code_5 = _T_220 ? io_dis_uops_0_bits_fu_code_5_0 : _T_219 ? issue_slots_23_out_uop_fu_code_5 : issue_slots_22_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fu_code_6 = _T_220 ? io_dis_uops_0_bits_fu_code_6_0 : _T_219 ? issue_slots_23_out_uop_fu_code_6 : issue_slots_22_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fu_code_7 = _T_220 ? io_dis_uops_0_bits_fu_code_7_0 : _T_219 ? issue_slots_23_out_uop_fu_code_7 : issue_slots_22_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fu_code_8 = _T_220 ? io_dis_uops_0_bits_fu_code_8_0 : _T_219 ? issue_slots_23_out_uop_fu_code_8 : issue_slots_22_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fu_code_9 = _T_220 ? io_dis_uops_0_bits_fu_code_9_0 : _T_219 ? issue_slots_23_out_uop_fu_code_9 : issue_slots_22_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_iq_type_0 = _T_220 ? io_dis_uops_0_bits_iq_type_0_0 : _T_219 ? issue_slots_23_out_uop_iq_type_0 : issue_slots_22_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_iq_type_1 = _T_220 ? io_dis_uops_0_bits_iq_type_1_0 : _T_219 ? issue_slots_23_out_uop_iq_type_1 : issue_slots_22_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_iq_type_2 = _T_220 ? io_dis_uops_0_bits_iq_type_2_0 : _T_219 ? issue_slots_23_out_uop_iq_type_2 : issue_slots_22_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_iq_type_3 = _T_220 ? io_dis_uops_0_bits_iq_type_3_0 : _T_219 ? issue_slots_23_out_uop_iq_type_3 : issue_slots_22_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_debug_pc = _T_220 ? io_dis_uops_0_bits_debug_pc_0 : _T_219 ? issue_slots_23_out_uop_debug_pc : issue_slots_22_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_is_rvc = _T_220 ? io_dis_uops_0_bits_is_rvc_0 : _T_219 ? issue_slots_23_out_uop_is_rvc : issue_slots_22_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_debug_inst = _T_220 ? io_dis_uops_0_bits_debug_inst_0 : _T_219 ? issue_slots_23_out_uop_debug_inst : issue_slots_22_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_inst = _T_220 ? io_dis_uops_0_bits_inst_0 : _T_219 ? issue_slots_23_out_uop_inst : issue_slots_22_out_uop_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign _issue_slots_21_clear_T = \|shamts_oh_21; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_21_clear = _issue_slots_21_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_222 = shamts_oh_24 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_223 = shamts_oh_25 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_22_in_uop_valid = _T_223 ? will_be_valid_25 : _T_222 ? will_be_valid_24 : shamts_oh_23 == 3'h1 & issue_slots_23_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :186:79, :191:33, :194:{28,48}, :195:37] assign issue_slots_22_in_uop_bits_debug_tsrc = _T_223 ? io_dis_uops_1_bits_debug_tsrc_0 : _T_222 ? io_dis_uops_0_bits_debug_tsrc_0 : issue_slots_23_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_debug_fsrc = _T_223 ? io_dis_uops_1_bits_debug_fsrc_0 : _T_222 ? io_dis_uops_0_bits_debug_fsrc_0 : issue_slots_23_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_bp_xcpt_if = _T_223 ? io_dis_uops_1_bits_bp_xcpt_if_0 : _T_222 ? io_dis_uops_0_bits_bp_xcpt_if_0 : issue_slots_23_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_bp_debug_if = _T_223 ? io_dis_uops_1_bits_bp_debug_if_0 : _T_222 ? io_dis_uops_0_bits_bp_debug_if_0 : issue_slots_23_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_xcpt_ma_if = _T_223 ? io_dis_uops_1_bits_xcpt_ma_if_0 : _T_222 ? io_dis_uops_0_bits_xcpt_ma_if_0 : issue_slots_23_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_xcpt_ae_if = _T_223 ? io_dis_uops_1_bits_xcpt_ae_if_0 : _T_222 ? io_dis_uops_0_bits_xcpt_ae_if_0 : issue_slots_23_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_xcpt_pf_if = _T_223 ? io_dis_uops_1_bits_xcpt_pf_if_0 : _T_222 ? io_dis_uops_0_bits_xcpt_pf_if_0 : issue_slots_23_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_typ = _T_223 ? io_dis_uops_1_bits_fp_typ_0 : _T_222 ? io_dis_uops_0_bits_fp_typ_0 : issue_slots_23_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_rm = _T_223 ? io_dis_uops_1_bits_fp_rm_0 : _T_222 ? io_dis_uops_0_bits_fp_rm_0 : issue_slots_23_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_val = _T_223 ? io_dis_uops_1_bits_fp_val_0 : _T_222 ? io_dis_uops_0_bits_fp_val_0 : issue_slots_23_out_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fcn_op = _T_223 ? io_dis_uops_1_bits_fcn_op_0 : _T_222 ? io_dis_uops_0_bits_fcn_op_0 : issue_slots_23_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fcn_dw = _T_223 ? io_dis_uops_1_bits_fcn_dw_0 : _T_222 ? io_dis_uops_0_bits_fcn_dw_0 : issue_slots_23_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_frs3_en = _T_223 ? io_dis_uops_1_bits_frs3_en_0 : _T_222 ? io_dis_uops_0_bits_frs3_en_0 : issue_slots_23_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_lrs2_rtype = _T_223 ? io_dis_uops_1_bits_lrs2_rtype_0 : _T_222 ? io_dis_uops_0_bits_lrs2_rtype_0 : issue_slots_23_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_lrs1_rtype = _T_223 ? _WIRE_1_lrs1_rtype : _T_222 ? _WIRE_lrs1_rtype : issue_slots_23_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:35:17, :103:43, :104:32, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_dst_rtype = _T_223 ? io_dis_uops_1_bits_dst_rtype_0 : _T_222 ? io_dis_uops_0_bits_dst_rtype_0 : issue_slots_23_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_lrs3 = _T_223 ? io_dis_uops_1_bits_lrs3_0 : _T_222 ? io_dis_uops_0_bits_lrs3_0 : issue_slots_23_out_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_lrs2 = _T_223 ? io_dis_uops_1_bits_lrs2_0 : _T_222 ? io_dis_uops_0_bits_lrs2_0 : issue_slots_23_out_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_lrs1 = _T_223 ? io_dis_uops_1_bits_lrs1_0 : _T_222 ? io_dis_uops_0_bits_lrs1_0 : issue_slots_23_out_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_ldst = _T_223 ? io_dis_uops_1_bits_ldst_0 : _T_222 ? io_dis_uops_0_bits_ldst_0 : issue_slots_23_out_uop_ldst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_ldst_is_rs1 = _T_223 ? io_dis_uops_1_bits_ldst_is_rs1_0 : _T_222 ? io_dis_uops_0_bits_ldst_is_rs1_0 : issue_slots_23_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_csr_cmd = _T_223 ? io_dis_uops_1_bits_csr_cmd_0 : _T_222 ? io_dis_uops_0_bits_csr_cmd_0 : issue_slots_23_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_flush_on_commit = _T_223 ? io_dis_uops_1_bits_flush_on_commit_0 : _T_222 ? io_dis_uops_0_bits_flush_on_commit_0 : issue_slots_23_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_is_unique = _T_223 ? io_dis_uops_1_bits_is_unique_0 : _T_222 ? io_dis_uops_0_bits_is_unique_0 : issue_slots_23_out_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_uses_stq = _T_223 ? io_dis_uops_1_bits_uses_stq_0 : _T_222 ? io_dis_uops_0_bits_uses_stq_0 : issue_slots_23_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_uses_ldq = _T_223 ? io_dis_uops_1_bits_uses_ldq_0 : _T_222 ? io_dis_uops_0_bits_uses_ldq_0 : issue_slots_23_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_mem_signed = _T_223 ? io_dis_uops_1_bits_mem_signed_0 : _T_222 ? io_dis_uops_0_bits_mem_signed_0 : issue_slots_23_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_mem_size = _T_223 ? io_dis_uops_1_bits_mem_size_0 : _T_222 ? io_dis_uops_0_bits_mem_size_0 : issue_slots_23_out_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_mem_cmd = _T_223 ? io_dis_uops_1_bits_mem_cmd_0 : _T_222 ? io_dis_uops_0_bits_mem_cmd_0 : issue_slots_23_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_exc_cause = _T_223 ? io_dis_uops_1_bits_exc_cause_0 : _T_222 ? io_dis_uops_0_bits_exc_cause_0 : issue_slots_23_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_exception = _T_223 ? io_dis_uops_1_bits_exception_0 : _T_222 ? io_dis_uops_0_bits_exception_0 : issue_slots_23_out_uop_exception; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_stale_pdst = _T_223 ? io_dis_uops_1_bits_stale_pdst_0 : _T_222 ? io_dis_uops_0_bits_stale_pdst_0 : issue_slots_23_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] wire _GEN_0 = _T_223 \| _T_222; // @[issue-unit-age-ordered.scala:194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_ppred_busy = ~_GEN_0 & issue_slots_23_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:48, :196:37] assign issue_slots_22_in_uop_bits_prs3_busy = _T_223 ? _WIRE_1_prs3_busy : _T_222 ? _WIRE_prs3_busy : issue_slots_23_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:35:17, :76:38, :77:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_prs2_busy = _T_223 ? _WIRE_1_prs2_busy : _T_222 ? _WIRE_prs2_busy : issue_slots_23_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:35:17, :65:38, :66:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_prs1_busy = _T_223 ? _WIRE_1_prs1_busy : _T_222 ? _WIRE_prs1_busy : issue_slots_23_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:35:17, :57:38, :58:29, :62:116, :103:43, :105:32, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_ppred = _T_223 ? io_dis_uops_1_bits_ppred_0 : _T_222 ? io_dis_uops_0_bits_ppred_0 : issue_slots_23_out_uop_ppred; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_prs3 = _T_223 ? io_dis_uops_1_bits_prs3_0 : _T_222 ? io_dis_uops_0_bits_prs3_0 : issue_slots_23_out_uop_prs3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_prs2 = _T_223 ? io_dis_uops_1_bits_prs2_0 : _T_222 ? io_dis_uops_0_bits_prs2_0 : issue_slots_23_out_uop_prs2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_prs1 = _T_223 ? io_dis_uops_1_bits_prs1_0 : _T_222 ? io_dis_uops_0_bits_prs1_0 : issue_slots_23_out_uop_prs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_pdst = _T_223 ? io_dis_uops_1_bits_pdst_0 : _T_222 ? io_dis_uops_0_bits_pdst_0 : issue_slots_23_out_uop_pdst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_rxq_idx = _T_223 ? io_dis_uops_1_bits_rxq_idx_0 : _T_222 ? io_dis_uops_0_bits_rxq_idx_0 : issue_slots_23_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_stq_idx = _T_223 ? io_dis_uops_1_bits_stq_idx_0 : _T_222 ? io_dis_uops_0_bits_stq_idx_0 : issue_slots_23_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_ldq_idx = _T_223 ? io_dis_uops_1_bits_ldq_idx_0 : _T_222 ? io_dis_uops_0_bits_ldq_idx_0 : issue_slots_23_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_rob_idx = _T_223 ? io_dis_uops_1_bits_rob_idx_0 : _T_222 ? io_dis_uops_0_bits_rob_idx_0 : issue_slots_23_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_vec = _T_223 ? io_dis_uops_1_bits_fp_ctrl_vec_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_vec_0 : issue_slots_23_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_wflags = _T_223 ? io_dis_uops_1_bits_fp_ctrl_wflags_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_wflags_0 : issue_slots_23_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_sqrt = _T_223 ? io_dis_uops_1_bits_fp_ctrl_sqrt_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_sqrt_0 : issue_slots_23_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_div = _T_223 ? io_dis_uops_1_bits_fp_ctrl_div_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_div_0 : issue_slots_23_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_fma = _T_223 ? io_dis_uops_1_bits_fp_ctrl_fma_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_fma_0 : issue_slots_23_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_fastpipe = _T_223 ? io_dis_uops_1_bits_fp_ctrl_fastpipe_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_fastpipe_0 : issue_slots_23_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_toint = _T_223 ? io_dis_uops_1_bits_fp_ctrl_toint_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_toint_0 : issue_slots_23_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_fromint = _T_223 ? io_dis_uops_1_bits_fp_ctrl_fromint_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_fromint_0 : issue_slots_23_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_typeTagOut = _T_223 ? io_dis_uops_1_bits_fp_ctrl_typeTagOut_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_typeTagOut_0 : issue_slots_23_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_typeTagIn = _T_223 ? io_dis_uops_1_bits_fp_ctrl_typeTagIn_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_typeTagIn_0 : issue_slots_23_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_swap23 = _T_223 ? io_dis_uops_1_bits_fp_ctrl_swap23_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_swap23_0 : issue_slots_23_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_swap12 = _T_223 ? io_dis_uops_1_bits_fp_ctrl_swap12_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_swap12_0 : issue_slots_23_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_ren3 = _T_223 ? io_dis_uops_1_bits_fp_ctrl_ren3_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_ren3_0 : issue_slots_23_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_ren2 = _T_223 ? io_dis_uops_1_bits_fp_ctrl_ren2_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_ren2_0 : issue_slots_23_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_ren1 = _T_223 ? io_dis_uops_1_bits_fp_ctrl_ren1_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_ren1_0 : issue_slots_23_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_wen = _T_223 ? io_dis_uops_1_bits_fp_ctrl_wen_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_wen_0 : issue_slots_23_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_ldst = _T_223 ? io_dis_uops_1_bits_fp_ctrl_ldst_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_ldst_0 : issue_slots_23_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_op2_sel = _T_223 ? io_dis_uops_1_bits_op2_sel_0 : _T_222 ? io_dis_uops_0_bits_op2_sel_0 : issue_slots_23_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_op1_sel = _T_223 ? io_dis_uops_1_bits_op1_sel_0 : _T_222 ? io_dis_uops_0_bits_op1_sel_0 : issue_slots_23_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_imm_packed = _T_223 ? io_dis_uops_1_bits_imm_packed_0 : _T_222 ? io_dis_uops_0_bits_imm_packed_0 : issue_slots_23_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_pimm = _T_223 ? io_dis_uops_1_bits_pimm_0 : _T_222 ? io_dis_uops_0_bits_pimm_0 : issue_slots_23_out_uop_pimm; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_imm_sel = _T_223 ? io_dis_uops_1_bits_imm_sel_0 : _T_222 ? io_dis_uops_0_bits_imm_sel_0 : issue_slots_23_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_imm_rename = _T_223 ? io_dis_uops_1_bits_imm_rename_0 : _T_222 ? io_dis_uops_0_bits_imm_rename_0 : issue_slots_23_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_taken = _T_223 ? io_dis_uops_1_bits_taken_0 : _T_222 ? io_dis_uops_0_bits_taken_0 : issue_slots_23_out_uop_taken; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_pc_lob = _T_223 ? io_dis_uops_1_bits_pc_lob_0 : _T_222 ? io_dis_uops_0_bits_pc_lob_0 : issue_slots_23_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_edge_inst = _T_223 ? io_dis_uops_1_bits_edge_inst_0 : _T_222 ? io_dis_uops_0_bits_edge_inst_0 : issue_slots_23_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_ftq_idx = _T_223 ? io_dis_uops_1_bits_ftq_idx_0 : _T_222 ? io_dis_uops_0_bits_ftq_idx_0 : issue_slots_23_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_is_mov = _T_223 ? io_dis_uops_1_bits_is_mov_0 : _T_222 ? io_dis_uops_0_bits_is_mov_0 : issue_slots_23_out_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_is_rocc = _T_223 ? io_dis_uops_1_bits_is_rocc_0 : _T_222 ? io_dis_uops_0_bits_is_rocc_0 : issue_slots_23_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_is_sys_pc2epc = _T_223 ? io_dis_uops_1_bits_is_sys_pc2epc_0 : _T_222 ? io_dis_uops_0_bits_is_sys_pc2epc_0 : issue_slots_23_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_is_eret = _T_223 ? io_dis_uops_1_bits_is_eret_0 : _T_222 ? io_dis_uops_0_bits_is_eret_0 : issue_slots_23_out_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_is_amo = _T_223 ? io_dis_uops_1_bits_is_amo_0 : _T_222 ? io_dis_uops_0_bits_is_amo_0 : issue_slots_23_out_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_is_sfence = _T_223 ? io_dis_uops_1_bits_is_sfence_0 : _T_222 ? io_dis_uops_0_bits_is_sfence_0 : issue_slots_23_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_is_fencei = _T_223 ? io_dis_uops_1_bits_is_fencei_0 : _T_222 ? io_dis_uops_0_bits_is_fencei_0 : issue_slots_23_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_is_fence = _T_223 ? io_dis_uops_1_bits_is_fence_0 : _T_222 ? io_dis_uops_0_bits_is_fence_0 : issue_slots_23_out_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_is_sfb = _T_223 ? io_dis_uops_1_bits_is_sfb_0 : _T_222 ? io_dis_uops_0_bits_is_sfb_0 : issue_slots_23_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_br_type = _T_223 ? io_dis_uops_1_bits_br_type_0 : _T_222 ? io_dis_uops_0_bits_br_type_0 : issue_slots_23_out_uop_br_type; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_br_tag = _T_223 ? io_dis_uops_1_bits_br_tag_0 : _T_222 ? io_dis_uops_0_bits_br_tag_0 : issue_slots_23_out_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_br_mask = _T_223 ? io_dis_uops_1_bits_br_mask_0 : _T_222 ? io_dis_uops_0_bits_br_mask_0 : issue_slots_23_out_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_dis_col_sel = _T_223 ? io_dis_uops_1_bits_dis_col_sel_0 : _T_222 ? io_dis_uops_0_bits_dis_col_sel_0 : issue_slots_23_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_iw_p3_bypass_hint = _T_223 ? _WIRE_1_iw_p3_bypass_hint : _T_222 ? _WIRE_iw_p3_bypass_hint : issue_slots_23_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:41:35, :76:38, :78:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_iw_p2_bypass_hint = _T_223 ? _WIRE_1_iw_p2_bypass_hint : _T_222 ? _WIRE_iw_p2_bypass_hint : issue_slots_23_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:40:35, :65:38, :68:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_iw_p1_bypass_hint = _T_223 ? _WIRE_1_iw_p1_bypass_hint : _T_222 ? _WIRE_iw_p1_bypass_hint : issue_slots_23_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:39:35, :57:38, :60:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_iw_p2_speculative_child = _T_223 ? _WIRE_1_iw_p2_speculative_child : ~_T_222 \| _T_12 ? 3'h0 : io_dis_uops_0_bits_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :65:{32,38}, :67:43, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_iw_p1_speculative_child = _T_223 ? _WIRE_1_iw_p1_speculative_child : ~_T_222 \| _T ? 3'h0 : io_dis_uops_0_bits_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :57:{32,38}, :59:43, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_iw_issued = ~_GEN_0 & issue_slots_23_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:48, :196:37] assign issue_slots_22_in_uop_bits_fu_code_0 = _T_223 ? io_dis_uops_1_bits_fu_code_0_0 : _T_222 ? io_dis_uops_0_bits_fu_code_0_0 : issue_slots_23_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fu_code_1 = _T_223 ? io_dis_uops_1_bits_fu_code_1_0 : _T_222 ? io_dis_uops_0_bits_fu_code_1_0 : issue_slots_23_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fu_code_2 = _T_223 ? io_dis_uops_1_bits_fu_code_2_0 : _T_222 ? io_dis_uops_0_bits_fu_code_2_0 : issue_slots_23_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fu_code_3 = _T_223 ? io_dis_uops_1_bits_fu_code_3_0 : _T_222 ? io_dis_uops_0_bits_fu_code_3_0 : issue_slots_23_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fu_code_4 = _T_223 ? io_dis_uops_1_bits_fu_code_4_0 : _T_222 ? io_dis_uops_0_bits_fu_code_4_0 : issue_slots_23_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fu_code_5 = _T_223 ? io_dis_uops_1_bits_fu_code_5_0 : _T_222 ? io_dis_uops_0_bits_fu_code_5_0 : issue_slots_23_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fu_code_6 = _T_223 ? io_dis_uops_1_bits_fu_code_6_0 : _T_222 ? io_dis_uops_0_bits_fu_code_6_0 : issue_slots_23_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fu_code_7 = _T_223 ? io_dis_uops_1_bits_fu_code_7_0 : _T_222 ? io_dis_uops_0_bits_fu_code_7_0 : issue_slots_23_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fu_code_8 = _T_223 ? io_dis_uops_1_bits_fu_code_8_0 : _T_222 ? io_dis_uops_0_bits_fu_code_8_0 : issue_slots_23_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fu_code_9 = _T_223 ? io_dis_uops_1_bits_fu_code_9_0 : _T_222 ? io_dis_uops_0_bits_fu_code_9_0 : issue_slots_23_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_iq_type_0 = _T_223 ? io_dis_uops_1_bits_iq_type_0_0 : _T_222 ? io_dis_uops_0_bits_iq_type_0_0 : issue_slots_23_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_iq_type_1 = _T_223 ? io_dis_uops_1_bits_iq_type_1_0 : _T_222 ? io_dis_uops_0_bits_iq_type_1_0 : issue_slots_23_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_iq_type_2 = _T_223 ? io_dis_uops_1_bits_iq_type_2_0 : _T_222 ? io_dis_uops_0_bits_iq_type_2_0 : issue_slots_23_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_iq_type_3 = _T_223 ? io_dis_uops_1_bits_iq_type_3_0 : _T_222 ? io_dis_uops_0_bits_iq_type_3_0 : issue_slots_23_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_debug_pc = _T_223 ? io_dis_uops_1_bits_debug_pc_0 : _T_222 ? io_dis_uops_0_bits_debug_pc_0 : issue_slots_23_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_is_rvc = _T_223 ? io_dis_uops_1_bits_is_rvc_0 : _T_222 ? io_dis_uops_0_bits_is_rvc_0 : issue_slots_23_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_debug_inst = _T_223 ? io_dis_uops_1_bits_debug_inst_0 : _T_222 ? io_dis_uops_0_bits_debug_inst_0 : issue_slots_23_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_inst = _T_223 ? io_dis_uops_1_bits_inst_0 : _T_222 ? io_dis_uops_0_bits_inst_0 : issue_slots_23_out_uop_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign _issue_slots_22_clear_T = \|shamts_oh_22; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_22_clear = _issue_slots_22_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_225 = shamts_oh_25 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_226 = shamts_oh_26 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_23_in_uop_valid = _T_226 ? will_be_valid_26 : _T_225 ? will_be_valid_25 : shamts_oh_24 == 3'h1 & will_be_valid_24; // @[issue-unit-age-ordered.scala:122:28, :158:23, :186:79, :191:33, :194:{28,48}, :195:37] assign issue_slots_23_in_uop_bits_debug_tsrc = _T_226 ? io_dis_uops_2_bits_debug_tsrc_0 : _T_225 ? io_dis_uops_1_bits_debug_tsrc_0 : io_dis_uops_0_bits_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_debug_fsrc = _T_226 ? io_dis_uops_2_bits_debug_fsrc_0 : _T_225 ? io_dis_uops_1_bits_debug_fsrc_0 : io_dis_uops_0_bits_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_bp_xcpt_if = _T_226 ? io_dis_uops_2_bits_bp_xcpt_if_0 : _T_225 ? io_dis_uops_1_bits_bp_xcpt_if_0 : io_dis_uops_0_bits_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_bp_debug_if = _T_226 ? io_dis_uops_2_bits_bp_debug_if_0 : _T_225 ? io_dis_uops_1_bits_bp_debug_if_0 : io_dis_uops_0_bits_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_xcpt_ma_if = _T_226 ? io_dis_uops_2_bits_xcpt_ma_if_0 : _T_225 ? io_dis_uops_1_bits_xcpt_ma_if_0 : io_dis_uops_0_bits_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_xcpt_ae_if = _T_226 ? io_dis_uops_2_bits_xcpt_ae_if_0 : _T_225 ? io_dis_uops_1_bits_xcpt_ae_if_0 : io_dis_uops_0_bits_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_xcpt_pf_if = _T_226 ? io_dis_uops_2_bits_xcpt_pf_if_0 : _T_225 ? io_dis_uops_1_bits_xcpt_pf_if_0 : io_dis_uops_0_bits_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_typ = _T_226 ? io_dis_uops_2_bits_fp_typ_0 : _T_225 ? io_dis_uops_1_bits_fp_typ_0 : io_dis_uops_0_bits_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_rm = _T_226 ? io_dis_uops_2_bits_fp_rm_0 : _T_225 ? io_dis_uops_1_bits_fp_rm_0 : io_dis_uops_0_bits_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_val = _T_226 ? io_dis_uops_2_bits_fp_val_0 : _T_225 ? io_dis_uops_1_bits_fp_val_0 : io_dis_uops_0_bits_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fcn_op = _T_226 ? io_dis_uops_2_bits_fcn_op_0 : _T_225 ? io_dis_uops_1_bits_fcn_op_0 : io_dis_uops_0_bits_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fcn_dw = _T_226 ? io_dis_uops_2_bits_fcn_dw_0 : _T_225 ? io_dis_uops_1_bits_fcn_dw_0 : io_dis_uops_0_bits_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_frs3_en = _T_226 ? io_dis_uops_2_bits_frs3_en_0 : _T_225 ? io_dis_uops_1_bits_frs3_en_0 : io_dis_uops_0_bits_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_lrs2_rtype = _T_226 ? io_dis_uops_2_bits_lrs2_rtype_0 : _T_225 ? io_dis_uops_1_bits_lrs2_rtype_0 : io_dis_uops_0_bits_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_lrs1_rtype = _T_226 ? (io_dis_uops_2_bits_uses_stq_0 ? 2'h2 : io_dis_uops_2_bits_lrs1_rtype_0) : _T_225 ? _WIRE_1_lrs1_rtype : _WIRE_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7, :35:17, :103:43, :104:32, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_dst_rtype = _T_226 ? io_dis_uops_2_bits_dst_rtype_0 : _T_225 ? io_dis_uops_1_bits_dst_rtype_0 : io_dis_uops_0_bits_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_lrs3 = _T_226 ? io_dis_uops_2_bits_lrs3_0 : _T_225 ? io_dis_uops_1_bits_lrs3_0 : io_dis_uops_0_bits_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_lrs2 = _T_226 ? io_dis_uops_2_bits_lrs2_0 : _T_225 ? io_dis_uops_1_bits_lrs2_0 : io_dis_uops_0_bits_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_lrs1 = _T_226 ? io_dis_uops_2_bits_lrs1_0 : _T_225 ? io_dis_uops_1_bits_lrs1_0 : io_dis_uops_0_bits_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_ldst = _T_226 ? io_dis_uops_2_bits_ldst_0 : _T_225 ? io_dis_uops_1_bits_ldst_0 : io_dis_uops_0_bits_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_ldst_is_rs1 = _T_226 ? io_dis_uops_2_bits_ldst_is_rs1_0 : _T_225 ? io_dis_uops_1_bits_ldst_is_rs1_0 : io_dis_uops_0_bits_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_csr_cmd = _T_226 ? io_dis_uops_2_bits_csr_cmd_0 : _T_225 ? io_dis_uops_1_bits_csr_cmd_0 : io_dis_uops_0_bits_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_flush_on_commit = _T_226 ? io_dis_uops_2_bits_flush_on_commit_0 : _T_225 ? io_dis_uops_1_bits_flush_on_commit_0 : io_dis_uops_0_bits_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_is_unique = _T_226 ? io_dis_uops_2_bits_is_unique_0 : _T_225 ? io_dis_uops_1_bits_is_unique_0 : io_dis_uops_0_bits_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_uses_stq = _T_226 ? io_dis_uops_2_bits_uses_stq_0 : _T_225 ? io_dis_uops_1_bits_uses_stq_0 : io_dis_uops_0_bits_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_uses_ldq = _T_226 ? io_dis_uops_2_bits_uses_ldq_0 : _T_225 ? io_dis_uops_1_bits_uses_ldq_0 : io_dis_uops_0_bits_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_mem_signed = _T_226 ? io_dis_uops_2_bits_mem_signed_0 : _T_225 ? io_dis_uops_1_bits_mem_signed_0 : io_dis_uops_0_bits_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_mem_size = _T_226 ? io_dis_uops_2_bits_mem_size_0 : _T_225 ? io_dis_uops_1_bits_mem_size_0 : io_dis_uops_0_bits_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_mem_cmd = _T_226 ? io_dis_uops_2_bits_mem_cmd_0 : _T_225 ? io_dis_uops_1_bits_mem_cmd_0 : io_dis_uops_0_bits_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_exc_cause = _T_226 ? io_dis_uops_2_bits_exc_cause_0 : _T_225 ? io_dis_uops_1_bits_exc_cause_0 : io_dis_uops_0_bits_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_exception = _T_226 ? io_dis_uops_2_bits_exception_0 : _T_225 ? io_dis_uops_1_bits_exception_0 : io_dis_uops_0_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_stale_pdst = _T_226 ? io_dis_uops_2_bits_stale_pdst_0 : _T_225 ? io_dis_uops_1_bits_stale_pdst_0 : io_dis_uops_0_bits_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_prs3_busy = _T_226 ? ~_T_94 & io_dis_uops_2_bits_prs3_busy_0 : _T_225 ? _WIRE_1_prs3_busy : _WIRE_prs3_busy; // @[issue-unit-age-ordered.scala:22:7, :35:17, :76:{32,38}, :77:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_prs2_busy = _T_226 ? ~_T_82 & io_dis_uops_2_bits_prs2_busy_0 : _T_225 ? _WIRE_1_prs2_busy : _WIRE_prs2_busy; // @[issue-unit-age-ordered.scala:22:7, :35:17, :65:{32,38}, :66:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_prs1_busy = _T_226 ? ~io_dis_uops_2_bits_uses_stq_0 & ~_T_70 & io_dis_uops_2_bits_prs1_busy_0 : _T_225 ? _WIRE_1_prs1_busy : _WIRE_prs1_busy; // @[issue-unit-age-ordered.scala:22:7, :35:17, :57:{32,38}, :58:29, :62:116, :103:43, :105:32, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_ppred = _T_226 ? io_dis_uops_2_bits_ppred_0 : _T_225 ? io_dis_uops_1_bits_ppred_0 : io_dis_uops_0_bits_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_prs3 = _T_226 ? io_dis_uops_2_bits_prs3_0 : _T_225 ? io_dis_uops_1_bits_prs3_0 : io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_prs2 = _T_226 ? io_dis_uops_2_bits_prs2_0 : _T_225 ? io_dis_uops_1_bits_prs2_0 : io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_prs1 = _T_226 ? io_dis_uops_2_bits_prs1_0 : _T_225 ? io_dis_uops_1_bits_prs1_0 : io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_pdst = _T_226 ? io_dis_uops_2_bits_pdst_0 : _T_225 ? io_dis_uops_1_bits_pdst_0 : io_dis_uops_0_bits_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_rxq_idx = _T_226 ? io_dis_uops_2_bits_rxq_idx_0 : _T_225 ? io_dis_uops_1_bits_rxq_idx_0 : io_dis_uops_0_bits_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_stq_idx = _T_226 ? io_dis_uops_2_bits_stq_idx_0 : _T_225 ? io_dis_uops_1_bits_stq_idx_0 : io_dis_uops_0_bits_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_ldq_idx = _T_226 ? io_dis_uops_2_bits_ldq_idx_0 : _T_225 ? io_dis_uops_1_bits_ldq_idx_0 : io_dis_uops_0_bits_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_rob_idx = _T_226 ? io_dis_uops_2_bits_rob_idx_0 : _T_225 ? io_dis_uops_1_bits_rob_idx_0 : io_dis_uops_0_bits_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_vec = _T_226 ? io_dis_uops_2_bits_fp_ctrl_vec_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_vec_0 : io_dis_uops_0_bits_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_wflags = _T_226 ? io_dis_uops_2_bits_fp_ctrl_wflags_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_wflags_0 : io_dis_uops_0_bits_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_sqrt = _T_226 ? io_dis_uops_2_bits_fp_ctrl_sqrt_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_sqrt_0 : io_dis_uops_0_bits_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_div = _T_226 ? io_dis_uops_2_bits_fp_ctrl_div_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_div_0 : io_dis_uops_0_bits_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_fma = _T_226 ? io_dis_uops_2_bits_fp_ctrl_fma_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_fma_0 : io_dis_uops_0_bits_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_fastpipe = _T_226 ? io_dis_uops_2_bits_fp_ctrl_fastpipe_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_fastpipe_0 : io_dis_uops_0_bits_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_toint = _T_226 ? io_dis_uops_2_bits_fp_ctrl_toint_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_toint_0 : io_dis_uops_0_bits_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_fromint = _T_226 ? io_dis_uops_2_bits_fp_ctrl_fromint_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_fromint_0 : io_dis_uops_0_bits_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_typeTagOut = _T_226 ? io_dis_uops_2_bits_fp_ctrl_typeTagOut_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_typeTagOut_0 : io_dis_uops_0_bits_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_typeTagIn = _T_226 ? io_dis_uops_2_bits_fp_ctrl_typeTagIn_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_typeTagIn_0 : io_dis_uops_0_bits_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_swap23 = _T_226 ? io_dis_uops_2_bits_fp_ctrl_swap23_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_swap23_0 : io_dis_uops_0_bits_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_swap12 = _T_226 ? io_dis_uops_2_bits_fp_ctrl_swap12_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_swap12_0 : io_dis_uops_0_bits_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_ren3 = _T_226 ? io_dis_uops_2_bits_fp_ctrl_ren3_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_ren3_0 : io_dis_uops_0_bits_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_ren2 = _T_226 ? io_dis_uops_2_bits_fp_ctrl_ren2_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_ren2_0 : io_dis_uops_0_bits_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_ren1 = _T_226 ? io_dis_uops_2_bits_fp_ctrl_ren1_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_ren1_0 : io_dis_uops_0_bits_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_wen = _T_226 ? io_dis_uops_2_bits_fp_ctrl_wen_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_wen_0 : io_dis_uops_0_bits_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_ldst = _T_226 ? io_dis_uops_2_bits_fp_ctrl_ldst_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_ldst_0 : io_dis_uops_0_bits_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_op2_sel = _T_226 ? io_dis_uops_2_bits_op2_sel_0 : _T_225 ? io_dis_uops_1_bits_op2_sel_0 : io_dis_uops_0_bits_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_op1_sel = _T_226 ? io_dis_uops_2_bits_op1_sel_0 : _T_225 ? io_dis_uops_1_bits_op1_sel_0 : io_dis_uops_0_bits_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_imm_packed = _T_226 ? io_dis_uops_2_bits_imm_packed_0 : _T_225 ? io_dis_uops_1_bits_imm_packed_0 : io_dis_uops_0_bits_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_pimm = _T_226 ? io_dis_uops_2_bits_pimm_0 : _T_225 ? io_dis_uops_1_bits_pimm_0 : io_dis_uops_0_bits_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_imm_sel = _T_226 ? io_dis_uops_2_bits_imm_sel_0 : _T_225 ? io_dis_uops_1_bits_imm_sel_0 : io_dis_uops_0_bits_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_imm_rename = _T_226 ? io_dis_uops_2_bits_imm_rename_0 : _T_225 ? io_dis_uops_1_bits_imm_rename_0 : io_dis_uops_0_bits_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_taken = _T_226 ? io_dis_uops_2_bits_taken_0 : _T_225 ? io_dis_uops_1_bits_taken_0 : io_dis_uops_0_bits_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_pc_lob = _T_226 ? io_dis_uops_2_bits_pc_lob_0 : _T_225 ? io_dis_uops_1_bits_pc_lob_0 : io_dis_uops_0_bits_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_edge_inst = _T_226 ? io_dis_uops_2_bits_edge_inst_0 : _T_225 ? io_dis_uops_1_bits_edge_inst_0 : io_dis_uops_0_bits_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_ftq_idx = _T_226 ? io_dis_uops_2_bits_ftq_idx_0 : _T_225 ? io_dis_uops_1_bits_ftq_idx_0 : io_dis_uops_0_bits_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_is_mov = _T_226 ? io_dis_uops_2_bits_is_mov_0 : _T_225 ? io_dis_uops_1_bits_is_mov_0 : io_dis_uops_0_bits_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_is_rocc = _T_226 ? io_dis_uops_2_bits_is_rocc_0 : _T_225 ? io_dis_uops_1_bits_is_rocc_0 : io_dis_uops_0_bits_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_is_sys_pc2epc = _T_226 ? io_dis_uops_2_bits_is_sys_pc2epc_0 : _T_225 ? io_dis_uops_1_bits_is_sys_pc2epc_0 : io_dis_uops_0_bits_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_is_eret = _T_226 ? io_dis_uops_2_bits_is_eret_0 : _T_225 ? io_dis_uops_1_bits_is_eret_0 : io_dis_uops_0_bits_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_is_amo = _T_226 ? io_dis_uops_2_bits_is_amo_0 : _T_225 ? io_dis_uops_1_bits_is_amo_0 : io_dis_uops_0_bits_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_is_sfence = _T_226 ? io_dis_uops_2_bits_is_sfence_0 : _T_225 ? io_dis_uops_1_bits_is_sfence_0 : io_dis_uops_0_bits_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_is_fencei = _T_226 ? io_dis_uops_2_bits_is_fencei_0 : _T_225 ? io_dis_uops_1_bits_is_fencei_0 : io_dis_uops_0_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_is_fence = _T_226 ? io_dis_uops_2_bits_is_fence_0 : _T_225 ? io_dis_uops_1_bits_is_fence_0 : io_dis_uops_0_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_is_sfb = _T_226 ? io_dis_uops_2_bits_is_sfb_0 : _T_225 ? io_dis_uops_1_bits_is_sfb_0 : io_dis_uops_0_bits_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_br_type = _T_226 ? io_dis_uops_2_bits_br_type_0 : _T_225 ? io_dis_uops_1_bits_br_type_0 : io_dis_uops_0_bits_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_br_tag = _T_226 ? io_dis_uops_2_bits_br_tag_0 : _T_225 ? io_dis_uops_1_bits_br_tag_0 : io_dis_uops_0_bits_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_br_mask = _T_226 ? io_dis_uops_2_bits_br_mask_0 : _T_225 ? io_dis_uops_1_bits_br_mask_0 : io_dis_uops_0_bits_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_dis_col_sel = _T_226 ? io_dis_uops_2_bits_dis_col_sel_0 : _T_225 ? io_dis_uops_1_bits_dis_col_sel_0 : io_dis_uops_0_bits_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_iw_p3_bypass_hint = _T_226 ? _T_94 & prs3_wakeups_0_2 : _T_225 ? _WIRE_1_iw_p3_bypass_hint : _WIRE_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:41:35, :49:89, :76:{32,38}, :78:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_iw_p2_bypass_hint = _T_226 ? _T_82 & prs2_wakeups_0_2 : _T_225 ? _WIRE_1_iw_p2_bypass_hint : _WIRE_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:40:35, :48:89, :65:{32,38}, :68:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_iw_p1_bypass_hint = _T_226 ? _T_70 & prs1_wakeups_0_2 : _T_225 ? _WIRE_1_iw_p1_bypass_hint : _WIRE_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:39:35, :47:89, :57:{32,38}, :60:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_iw_p2_speculative_child = _T_226 ? (_T_82 ? 3'h0 : io_dis_uops_2_bits_iw_p2_speculative_child_0) : _T_225 ? _WIRE_1_iw_p2_speculative_child : _T_12 ? 3'h0 : io_dis_uops_0_bits_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :65:{32,38}, :67:43, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_iw_p1_speculative_child = _T_226 ? (_T_70 ? 3'h0 : io_dis_uops_2_bits_iw_p1_speculative_child_0) : _T_225 ? _WIRE_1_iw_p1_speculative_child : _T ? 3'h0 : io_dis_uops_0_bits_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :57:{32,38}, :59:43, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fu_code_0 = _T_226 ? io_dis_uops_2_bits_fu_code_0_0 : _T_225 ? io_dis_uops_1_bits_fu_code_0_0 : io_dis_uops_0_bits_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fu_code_1 = _T_226 ? io_dis_uops_2_bits_fu_code_1_0 : _T_225 ? io_dis_uops_1_bits_fu_code_1_0 : io_dis_uops_0_bits_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fu_code_2 = _T_226 ? io_dis_uops_2_bits_fu_code_2_0 : _T_225 ? io_dis_uops_1_bits_fu_code_2_0 : io_dis_uops_0_bits_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fu_code_3 = _T_226 ? io_dis_uops_2_bits_fu_code_3_0 : _T_225 ? io_dis_uops_1_bits_fu_code_3_0 : io_dis_uops_0_bits_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fu_code_4 = _T_226 ? io_dis_uops_2_bits_fu_code_4_0 : _T_225 ? io_dis_uops_1_bits_fu_code_4_0 : io_dis_uops_0_bits_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fu_code_5 = _T_226 ? io_dis_uops_2_bits_fu_code_5_0 : _T_225 ? io_dis_uops_1_bits_fu_code_5_0 : io_dis_uops_0_bits_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fu_code_6 = _T_226 ? io_dis_uops_2_bits_fu_code_6_0 : _T_225 ? io_dis_uops_1_bits_fu_code_6_0 : io_dis_uops_0_bits_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fu_code_7 = _T_226 ? io_dis_uops_2_bits_fu_code_7_0 : _T_225 ? io_dis_uops_1_bits_fu_code_7_0 : io_dis_uops_0_bits_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fu_code_8 = _T_226 ? io_dis_uops_2_bits_fu_code_8_0 : _T_225 ? io_dis_uops_1_bits_fu_code_8_0 : io_dis_uops_0_bits_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fu_code_9 = _T_226 ? io_dis_uops_2_bits_fu_code_9_0 : _T_225 ? io_dis_uops_1_bits_fu_code_9_0 : io_dis_uops_0_bits_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_iq_type_0 = _T_226 ? io_dis_uops_2_bits_iq_type_0_0 : _T_225 ? io_dis_uops_1_bits_iq_type_0_0 : io_dis_uops_0_bits_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_iq_type_1 = _T_226 ? io_dis_uops_2_bits_iq_type_1_0 : _T_225 ? io_dis_uops_1_bits_iq_type_1_0 : io_dis_uops_0_bits_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_iq_type_2 = _T_226 ? io_dis_uops_2_bits_iq_type_2_0 : _T_225 ? io_dis_uops_1_bits_iq_type_2_0 : io_dis_uops_0_bits_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_iq_type_3 = _T_226 ? io_dis_uops_2_bits_iq_type_3_0 : _T_225 ? io_dis_uops_1_bits_iq_type_3_0 : io_dis_uops_0_bits_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_debug_pc = _T_226 ? io_dis_uops_2_bits_debug_pc_0 : _T_225 ? io_dis_uops_1_bits_debug_pc_0 : io_dis_uops_0_bits_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_is_rvc = _T_226 ? io_dis_uops_2_bits_is_rvc_0 : _T_225 ? io_dis_uops_1_bits_is_rvc_0 : io_dis_uops_0_bits_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_debug_inst = _T_226 ? io_dis_uops_2_bits_debug_inst_0 : _T_225 ? io_dis_uops_1_bits_debug_inst_0 : io_dis_uops_0_bits_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_inst = _T_226 ? io_dis_uops_2_bits_inst_0 : _T_225 ? io_dis_uops_1_bits_inst_0 : io_dis_uops_0_bits_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign _issue_slots_23_clear_T = \|shamts_oh_23; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_23_clear = _issue_slots_23_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] reg is_available_0; // @[issue-unit-age-ordered.scala:208:25] reg is_available_1; // @[issue-unit-age-ordered.scala:208:25] reg is_available_2; // @[issue-unit-age-ordered.scala:208:25] reg is_available_3; // @[issue-unit-age-ordered.scala:208:25] reg is_available_4; // @[issue-unit-age-ordered.scala:208:25] reg is_available_5; // @[issue-unit-age-ordered.scala:208:25] reg is_available_6; // @[issue-unit-age-ordered.scala:208:25] reg is_available_7; // @[issue-unit-age-ordered.scala:208:25] reg is_available_8; // @[issue-unit-age-ordered.scala:208:25] reg is_available_9; // @[issue-unit-age-ordered.scala:208:25] reg is_available_10; // @[issue-unit-age-ordered.scala:208:25] reg is_available_11; // @[issue-unit-age-ordered.scala:208:25] wire [1:0] _GEN_1 = {1'h0, is_available_1} + {1'h0, is_available_2}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T = _GEN_1; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T = _GEN_1; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_2_ready_T = _GEN_1; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_1 = _io_dis_uops_0_ready_T; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _GEN_2 = {2'h0, is_available_0}; // @[issue-unit-age-ordered.scala:141:19, :208:25, :212:45] wire [2:0] _io_dis_uops_0_ready_T_2 = _GEN_2 + {1'h0, _io_dis_uops_0_ready_T_1}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_3 = _io_dis_uops_0_ready_T_2[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _GEN_3 = {1'h0, is_available_4} + {1'h0, is_available_5}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T_4; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T_4 = _GEN_3; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_4; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T_4 = _GEN_3; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_4; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_2_ready_T_4 = _GEN_3; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_5 = _io_dis_uops_0_ready_T_4; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _GEN_4 = {2'h0, is_available_3}; // @[issue-unit-age-ordered.scala:141:19, :208:25, :212:45] wire [2:0] _io_dis_uops_0_ready_T_6 = _GEN_4 + {1'h0, _io_dis_uops_0_ready_T_5}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_7 = _io_dis_uops_0_ready_T_6[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_8 = {1'h0, _io_dis_uops_0_ready_T_3} + {1'h0, _io_dis_uops_0_ready_T_7}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_9 = _io_dis_uops_0_ready_T_8; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _GEN_5 = {1'h0, is_available_7} + {1'h0, is_available_8}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T_10; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T_10 = _GEN_5; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_10; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T_10 = _GEN_5; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_10; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_2_ready_T_10 = _GEN_5; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_11 = _io_dis_uops_0_ready_T_10; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _GEN_6 = {2'h0, is_available_6}; // @[issue-unit-age-ordered.scala:141:19, :208:25, :212:45] wire [2:0] _io_dis_uops_0_ready_T_12 = _GEN_6 + {1'h0, _io_dis_uops_0_ready_T_11}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_13 = _io_dis_uops_0_ready_T_12[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _GEN_7 = {1'h0, is_available_10} + {1'h0, is_available_11}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T_14; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T_14 = _GEN_7; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_14; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T_14 = _GEN_7; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_14; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_2_ready_T_14 = _GEN_7; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_15 = _io_dis_uops_0_ready_T_14; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _GEN_8 = {2'h0, is_available_9}; // @[issue-unit-age-ordered.scala:141:19, :208:25, :212:45] wire [2:0] _io_dis_uops_0_ready_T_16 = _GEN_8 + {1'h0, _io_dis_uops_0_ready_T_15}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_17 = _io_dis_uops_0_ready_T_16[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_18 = {1'h0, _io_dis_uops_0_ready_T_13} + {1'h0, _io_dis_uops_0_ready_T_17}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_19 = _io_dis_uops_0_ready_T_18; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_0_ready_T_20 = {1'h0, _io_dis_uops_0_ready_T_9} + {1'h0, _io_dis_uops_0_ready_T_19}; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_0_ready_T_21 = _io_dis_uops_0_ready_T_20; // @[issue-unit-age-ordered.scala:212:45] wire _GEN_9 = io_dis_uops_0_ready_0 & io_dis_uops_0_valid_0; // @[Decoupled.scala:51:35] wire _io_dis_uops_0_ready_T_22; // @[Decoupled.scala:51:35] assign _io_dis_uops_0_ready_T_22 = _GEN_9; // @[Decoupled.scala:51:35] wire _io_dis_uops_1_ready_T_22; // @[Decoupled.scala:51:35] assign _io_dis_uops_1_ready_T_22 = _GEN_9; // @[Decoupled.scala:51:35] wire _io_dis_uops_2_ready_T_22; // @[Decoupled.scala:51:35] assign _io_dis_uops_2_ready_T_22 = _GEN_9; // @[Decoupled.scala:51:35] wire _GEN_10 = io_dis_uops_1_ready_0 & io_dis_uops_1_valid_0; // @[Decoupled.scala:51:35] wire _io_dis_uops_0_ready_T_23; // @[Decoupled.scala:51:35] assign _io_dis_uops_0_ready_T_23 = _GEN_10; // @[Decoupled.scala:51:35] wire _io_dis_uops_1_ready_T_23; // @[Decoupled.scala:51:35] assign _io_dis_uops_1_ready_T_23 = _GEN_10; // @[Decoupled.scala:51:35] wire _io_dis_uops_2_ready_T_23; // @[Decoupled.scala:51:35] assign _io_dis_uops_2_ready_T_23 = _GEN_10; // @[Decoupled.scala:51:35] wire _GEN_11 = io_dis_uops_2_ready_0 & io_dis_uops_2_valid_0; // @[Decoupled.scala:51:35] wire _io_dis_uops_0_ready_T_24; // @[Decoupled.scala:51:35] assign _io_dis_uops_0_ready_T_24 = _GEN_11; // @[Decoupled.scala:51:35] wire _io_dis_uops_1_ready_T_24; // @[Decoupled.scala:51:35] assign _io_dis_uops_1_ready_T_24 = _GEN_11; // @[Decoupled.scala:51:35] wire _io_dis_uops_2_ready_T_24; // @[Decoupled.scala:51:35] assign _io_dis_uops_2_ready_T_24 = _GEN_11; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_0_ready_T_25 = {1'h0, _io_dis_uops_0_ready_T_23} + {1'h0, _io_dis_uops_0_ready_T_24}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_0_ready_T_26 = _io_dis_uops_0_ready_T_25; // @[issue-unit-age-ordered.scala:212:100] wire [2:0] _io_dis_uops_0_ready_T_27 = {2'h0, _io_dis_uops_0_ready_T_22} + {1'h0, _io_dis_uops_0_ready_T_26}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_0_ready_T_28 = _io_dis_uops_0_ready_T_27[1:0]; // @[issue-unit-age-ordered.scala:212:100] wire [4:0] _io_dis_uops_0_ready_T_29 = {3'h0, _io_dis_uops_0_ready_T_28}; // @[issue-unit-age-ordered.scala:212:{90,100}] wire [3:0] _io_dis_uops_0_ready_T_30 = _io_dis_uops_0_ready_T_29[3:0]; // @[issue-unit-age-ordered.scala:212:90] wire _io_dis_uops_0_ready_T_31 = _io_dis_uops_0_ready_T_21 > _io_dis_uops_0_ready_T_30; // @[issue-unit-age-ordered.scala:212:{45,60,90}] reg io_dis_uops_0_ready_REG; // @[issue-unit-age-ordered.scala:212:36] assign io_dis_uops_0_ready_0 = io_dis_uops_0_ready_REG; // @[issue-unit-age-ordered.scala:22:7, :212:36] wire [1:0] _io_dis_uops_1_ready_T_1 = _io_dis_uops_1_ready_T; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_2 = _GEN_2 + {1'h0, _io_dis_uops_1_ready_T_1}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_3 = _io_dis_uops_1_ready_T_2[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_5 = _io_dis_uops_1_ready_T_4; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_6 = _GEN_4 + {1'h0, _io_dis_uops_1_ready_T_5}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_7 = _io_dis_uops_1_ready_T_6[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_8 = {1'h0, _io_dis_uops_1_ready_T_3} + {1'h0, _io_dis_uops_1_ready_T_7}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_9 = _io_dis_uops_1_ready_T_8; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_11 = _io_dis_uops_1_ready_T_10; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_12 = _GEN_6 + {1'h0, _io_dis_uops_1_ready_T_11}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_13 = _io_dis_uops_1_ready_T_12[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_15 = _io_dis_uops_1_ready_T_14; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_16 = _GEN_8 + {1'h0, _io_dis_uops_1_ready_T_15}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_17 = _io_dis_uops_1_ready_T_16[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_18 = {1'h0, _io_dis_uops_1_ready_T_13} + {1'h0, _io_dis_uops_1_ready_T_17}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_19 = _io_dis_uops_1_ready_T_18; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_1_ready_T_20 = {1'h0, _io_dis_uops_1_ready_T_9} + {1'h0, _io_dis_uops_1_ready_T_19}; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_1_ready_T_21 = _io_dis_uops_1_ready_T_20; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_25 = {1'h0, _io_dis_uops_1_ready_T_23} + {1'h0, _io_dis_uops_1_ready_T_24}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_1_ready_T_26 = _io_dis_uops_1_ready_T_25; // @[issue-unit-age-ordered.scala:212:100] wire [2:0] _io_dis_uops_1_ready_T_27 = {2'h0, _io_dis_uops_1_ready_T_22} + {1'h0, _io_dis_uops_1_ready_T_26}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_1_ready_T_28 = _io_dis_uops_1_ready_T_27[1:0]; // @[issue-unit-age-ordered.scala:212:100] wire [4:0] _io_dis_uops_1_ready_T_29 = {3'h0, _io_dis_uops_1_ready_T_28} + 5'h1; // @[issue-unit-age-ordered.scala:212:{90,100}] wire [3:0] _io_dis_uops_1_ready_T_30 = _io_dis_uops_1_ready_T_29[3:0]; // @[issue-unit-age-ordered.scala:212:90] wire _io_dis_uops_1_ready_T_31 = _io_dis_uops_1_ready_T_21 > _io_dis_uops_1_ready_T_30; // @[issue-unit-age-ordered.scala:212:{45,60,90}] reg io_dis_uops_1_ready_REG; // @[issue-unit-age-ordered.scala:212:36] assign io_dis_uops_1_ready_0 = io_dis_uops_1_ready_REG; // @[issue-unit-age-ordered.scala:22:7, :212:36] wire [1:0] _io_dis_uops_2_ready_T_1 = _io_dis_uops_2_ready_T; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_2 = _GEN_2 + {1'h0, _io_dis_uops_2_ready_T_1}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_3 = _io_dis_uops_2_ready_T_2[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_5 = _io_dis_uops_2_ready_T_4; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_6 = _GEN_4 + {1'h0, _io_dis_uops_2_ready_T_5}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_7 = _io_dis_uops_2_ready_T_6[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_8 = {1'h0, _io_dis_uops_2_ready_T_3} + {1'h0, _io_dis_uops_2_ready_T_7}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_9 = _io_dis_uops_2_ready_T_8; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_11 = _io_dis_uops_2_ready_T_10; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_12 = _GEN_6 + {1'h0, _io_dis_uops_2_ready_T_11}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_13 = _io_dis_uops_2_ready_T_12[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_15 = _io_dis_uops_2_ready_T_14; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_16 = _GEN_8 + {1'h0, _io_dis_uops_2_ready_T_15}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_17 = _io_dis_uops_2_ready_T_16[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_18 = {1'h0, _io_dis_uops_2_ready_T_13} + {1'h0, _io_dis_uops_2_ready_T_17}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_19 = _io_dis_uops_2_ready_T_18; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_2_ready_T_20 = {1'h0, _io_dis_uops_2_ready_T_9} + {1'h0, _io_dis_uops_2_ready_T_19}; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_2_ready_T_21 = _io_dis_uops_2_ready_T_20; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_25 = {1'h0, _io_dis_uops_2_ready_T_23} + {1'h0, _io_dis_uops_2_ready_T_24}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_2_ready_T_26 = _io_dis_uops_2_ready_T_25; // @[issue-unit-age-ordered.scala:212:100] wire [2:0] _io_dis_uops_2_ready_T_27 = {2'h0, _io_dis_uops_2_ready_T_22} + {1'h0, _io_dis_uops_2_ready_T_26}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_2_ready_T_28 = _io_dis_uops_2_ready_T_27[1:0]; // @[issue-unit-age-ordered.scala:212:100] wire [4:0] _io_dis_uops_2_ready_T_29 = {3'h0, _io_dis_uops_2_ready_T_28} + 5'h2; // @[issue-unit-age-ordered.scala:212:{90,100}] wire [3:0] _io_dis_uops_2_ready_T_30 = _io_dis_uops_2_ready_T_29[3:0]; // @[issue-unit-age-ordered.scala:212:90] wire _io_dis_uops_2_ready_T_31 = _io_dis_uops_2_ready_T_21 > _io_dis_uops_2_ready_T_30; // @[issue-unit-age-ordered.scala:212:{45,60,90}] reg io_dis_uops_2_ready_REG; // @[issue-unit-age-ordered.scala:212:36] assign io_dis_uops_2_ready_0 = io_dis_uops_2_ready_REG; // @[issue-unit-age-ordered.scala:22:7, :212:36]
Generate the Verilog code corresponding to the following Chisel files. File SourceB.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class SourceBRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val param = UInt(3.W) val tag = UInt(params.tagBits.W) val set = UInt(params.setBits.W) val clients = UInt(params.clientBits.W) } class SourceB(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val req = Flipped(Decoupled(new SourceBRequest(params))) val b = Decoupled(new TLBundleB(params.inner.bundle)) }) if (params.firstLevel) { // Tie off unused ports io.req.ready := true.B io.b.valid := false.B io.b.bits := DontCare } else { val remain = RegInit(0.U(params.clientBits.W)) val remain_set = WireInit(init = 0.U(params.clientBits.W)) val remain_clr = WireInit(init = 0.U(params.clientBits.W)) remain := (remain \| remain_set) & ~remain_clr val busy = remain.orR val todo = Mux(busy, remain, io.req.bits.clients) val next = ~(leftOR(todo) << 1) & todo if (params.clientBits > 1) { params.ccover(PopCount(remain) > 1.U, "SOURCEB_MULTI_PROBE", "Had to probe more than one client") } assert (!io.req.valid \|\| io.req.bits.clients =/= 0.U) io.req.ready := !busy when (io.req.fire) { remain_set := io.req.bits.clients } // No restrictions on the type of buffer used here val b = Wire(chiselTypeOf(io.b)) io.b <> params.micro.innerBuf.b(b) b.valid := busy \|\| io.req.valid when (b.fire) { remain_clr := next } params.ccover(b.valid && !b.ready, "SOURCEB_STALL", "Backpressured when issuing a probe") val tag = Mux(!busy, io.req.bits.tag, RegEnable(io.req.bits.tag, io.req.fire)) val set = Mux(!busy, io.req.bits.set, RegEnable(io.req.bits.set, io.req.fire)) val param = Mux(!busy, io.req.bits.param, RegEnable(io.req.bits.param, io.req.fire)) b.bits.opcode := TLMessages.Probe b.bits.param := param b.bits.size := params.offsetBits .U b.bits.source := params.clientSource(next) b.bits.address := params.expandAddress(tag, set, 0.U) b.bits.mask := ~0.U(params.inner.manager.beatBytes.W) b.bits.data := 0.U b.bits.corrupt := false.B } } File Parameters.scala: / * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relListscache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_\|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x \| 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ \|\| _) (matches, bits.U) } expanded \| Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) \|\| (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) \|\| ((opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm \|\| opcode === TLMessages.Get \|\| (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN \|\| param === TLPermissions.BtoN \|\| param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB \|\| param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle	module SourceB( // @[SourceB.scala:33:7] input clock, // @[SourceB.scala:33:7] input reset, // @[SourceB.scala:33:7] output io_req_ready, // @[SourceB.scala:35:14] input io_req_valid, // @[SourceB.scala:35:14] input [2:0] io_req_bits_param, // @[SourceB.scala:35:14] input [12:0] io_req_bits_tag, // @[SourceB.scala:35:14] input [9:0] io_req_bits_set, // @[SourceB.scala:35:14] input io_req_bits_clients, // @[SourceB.scala:35:14] input io_b_ready, // @[SourceB.scala:35:14] output io_b_valid, // @[SourceB.scala:35:14] output [1:0] io_b_bits_param, // @[SourceB.scala:35:14] output [31:0] io_b_bits_address // @[SourceB.scala:35:14] ); wire io_req_valid_0 = io_req_valid; // @[SourceB.scala:33:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceB.scala:33:7] wire [12:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceB.scala:33:7] wire [9:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceB.scala:33:7] wire io_req_bits_clients_0 = io_req_bits_clients; // @[SourceB.scala:33:7] wire io_b_ready_0 = io_b_ready; // @[SourceB.scala:33:7] wire _b_bits_address_base_T_2 = reset; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_8 = reset; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_14 = reset; // @[Parameters.scala:222:12] wire [2:0] io_b_bits_opcode = 3'h6; // @[SourceB.scala:33:7] wire [2:0] io_b_bits_size = 3'h6; // @[SourceB.scala:33:7] wire [2:0] b_bits_opcode = 3'h6; // @[SourceB.scala:65:17] wire [2:0] b_bits_size = 3'h6; // @[SourceB.scala:65:17] wire [7:0] io_b_bits_source = 8'hA0; // @[SourceB.scala:33:7] wire [7:0] b_bits_source = 8'hA0; // @[SourceB.scala:65:17] wire [15:0] io_b_bits_mask = 16'hFFFF; // @[SourceB.scala:33:7] wire [15:0] b_bits_mask = 16'hFFFF; // @[SourceB.scala:65:17] wire [15:0] _b_bits_mask_T = 16'hFFFF; // @[SourceB.scala:81:23] wire [127:0] io_b_bits_data = 128'h0; // @[SourceB.scala:33:7] wire [127:0] b_bits_data = 128'h0; // @[SourceB.scala:65:17] wire io_b_bits_corrupt = 1'h0; // @[SourceB.scala:33:7] wire b_bits_corrupt = 1'h0; // @[SourceB.scala:65:17] wire _b_bits_address_base_T = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_4 = 1'h0; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_6 = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_10 = 1'h0; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_12 = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_16 = 1'h0; // @[Parameters.scala:222:12] wire [1:0] b_bits_address_hi_hi_hi_lo = 2'h0; // @[Parameters.scala:230:8] wire [5:0] b_bits_address_base_y_2 = 6'h0; // @[Parameters.scala:221:15] wire [5:0] _b_bits_address_base_T_17 = 6'h0; // @[Parameters.scala:223:6] wire _b_bits_address_base_T_1 = 1'h1; // @[Parameters.scala:222:24] wire _b_bits_address_base_T_7 = 1'h1; // @[Parameters.scala:222:24] wire _b_bits_address_base_T_13 = 1'h1; // @[Parameters.scala:222:24] wire _io_req_ready_T; // @[SourceB.scala:61:21] wire b_ready = io_b_ready_0; // @[SourceB.scala:33:7, :65:17] wire b_valid; // @[SourceB.scala:65:17] wire [1:0] b_bits_param; // @[SourceB.scala:65:17] wire [31:0] b_bits_address; // @[SourceB.scala:65:17] wire io_req_ready_0; // @[SourceB.scala:33:7] wire [1:0] io_b_bits_param_0; // @[SourceB.scala:33:7] wire [31:0] io_b_bits_address_0; // @[SourceB.scala:33:7] wire io_b_valid_0; // @[SourceB.scala:33:7] reg remain; // @[SourceB.scala:46:25] wire busy = remain; // @[SourceB.scala:46:25, :51:23] wire remain_set; // @[SourceB.scala:47:30] wire remain_clr; // @[SourceB.scala:48:30] wire _remain_T = remain \| remain_set; // @[SourceB.scala:46:25, :47:30, :49:23] wire _remain_T_1 = ~remain_clr; // @[SourceB.scala:48:30, :49:39] wire _remain_T_2 = _remain_T & _remain_T_1; // @[SourceB.scala:49:{23,37,39}] wire todo = busy ? remain : io_req_bits_clients_0; // @[SourceB.scala:33:7, :46:25, :51:23, :52:19] wire _next_T = todo; // @[package.scala:254:17] wire [1:0] _next_T_1 = {_next_T, 1'h0}; // @[package.scala:254:17] wire [1:0] _next_T_2 = ~_next_T_1; // @[SourceB.scala:53:{16,31}] wire [1:0] next = {1'h0, _next_T_2[0] & todo}; // @[SourceB.scala:52:19, :53:{16,37}]
Generate the Verilog code corresponding to the following Chisel files. File SwitchAllocator.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ class SwitchAllocReq(val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams]) (implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val tail = Bool() } class SwitchArbiter(inN: Int, outN: Int, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Module { val io = IO(new Bundle { val in = Flipped(Vec(inN, Decoupled(new SwitchAllocReq(outParams, egressParams)))) val out = Vec(outN, Decoupled(new SwitchAllocReq(outParams, egressParams))) val chosen_oh = Vec(outN, Output(UInt(inN.W))) }) val lock = Seq.fill(outN) { RegInit(0.U(inN.W)) } val unassigned = Cat(io.in.map(_.valid).reverse) & ~(lock.reduce(_\|_)) val mask = RegInit(0.U(inN.W)) val choices = Wire(Vec(outN, UInt(inN.W))) var sel = PriorityEncoderOH(Cat(unassigned, unassigned & ~mask)) for (i <- 0 until outN) { choices(i) := sel \| (sel >> inN) sel = PriorityEncoderOH(unassigned & ~choices(i)) } io.in.foreach(_.ready := false.B) var chosens = 0.U(inN.W) val in_tails = Cat(io.in.map(_.bits.tail).reverse) for (i <- 0 until outN) { val in_valids = Cat((0 until inN).map { j => io.in(j).valid && !chosens(j) }.reverse) val chosen = Mux((in_valids & lock(i) & ~chosens).orR, lock(i), choices(i)) io.chosen_oh(i) := chosen io.out(i).valid := (in_valids & chosen).orR io.out(i).bits := Mux1H(chosen, io.in.map(_.bits)) for (j <- 0 until inN) { when (chosen(j) && io.out(i).ready) { io.in(j).ready := true.B } } chosens = chosens \| chosen when (io.out(i).fire) { lock(i) := chosen & ~in_tails } } when (io.out(0).fire) { mask := (0 until inN).map { i => (io.chosen_oh(0) >> i) }.reduce(_\|_) } .otherwise { mask := Mux(~mask === 0.U, 0.U, (mask << 1) \| 1.U(1.W)) } } class SwitchAllocator( val routerParams: RouterParams, val inParams: Seq[ChannelParams], val outParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterParams with HasRouterInputParams with HasRouterOutputParams { val io = IO(new Bundle { val req = MixedVec(allInParams.map(u => Vec(u.destSpeedup, Flipped(Decoupled(new SwitchAllocReq(outParams, egressParams)))))) val credit_alloc = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Output(new OutputCreditAlloc))}) val switch_sel = MixedVec(allOutParams.map { o => Vec(o.srcSpeedup, MixedVec(allInParams.map { i => Vec(i.destSpeedup, Output(Bool())) })) }) }) val nInputChannels = allInParams.map(_.nVirtualChannels).sum val arbs = allOutParams.map { oP => Module(new SwitchArbiter( allInParams.map(_.destSpeedup).reduce(_+_), oP.srcSpeedup, outParams, egressParams ))} arbs.foreach(_.io.out.foreach(_.ready := true.B)) var idx = 0 io.req.foreach(_.foreach { o => val fires = Wire(Vec(arbs.size, Bool())) arbs.zipWithIndex.foreach { case (a,i) => a.io.in(idx).valid := o.valid && o.bits.vc_sel(i).reduce(_\|\|_) a.io.in(idx).bits := o.bits fires(i) := a.io.in(idx).fire } o.ready := fires.reduce(_\|\|_) idx += 1 }) for (i <- 0 until nAllOutputs) { for (j <- 0 until allOutParams(i).srcSpeedup) { idx = 0 for (m <- 0 until nAllInputs) { for (n <- 0 until allInParams(m).destSpeedup) { io.switch_sel(i)(j)(m)(n) := arbs(i).io.in(idx).valid && arbs(i).io.chosen_oh(j)(idx) && arbs(i).io.out(j).valid idx += 1 } } } } io.credit_alloc.foreach(_.foreach(_.alloc := false.B)) io.credit_alloc.foreach(_.foreach(_.tail := false.B)) (arbs zip io.credit_alloc).zipWithIndex.map { case ((a,i),t) => for (j <- 0 until i.size) { for (k <- 0 until a.io.out.size) { when (a.io.out(k).valid && a.io.out(k).bits.vc_sel(t)(j)) { i(j).alloc := true.B i(j).tail := a.io.out(k).bits.tail } } } } }	module SwitchArbiter_313( // @[SwitchAllocator.scala:17:7] input clock, // @[SwitchAllocator.scala:17:7] input reset, // @[SwitchAllocator.scala:17:7] output io_in_0_ready, // @[SwitchAllocator.scala:18:14] input io_in_0_valid, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_3, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_4, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_5, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_6, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_7, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_8, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_9, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_8, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_9, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_8, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_9, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_1_ready, // @[SwitchAllocator.scala:18:14] input io_in_1_valid, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_3, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_4, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_5, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_6, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_7, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_8, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_9, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_8, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_9, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_8, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_9, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_2_ready, // @[SwitchAllocator.scala:18:14] input io_in_2_valid, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_3, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_4, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_5, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_6, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_7, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_8, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_9, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_8, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_9, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_8, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_9, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_tail, // @[SwitchAllocator.scala:18:14] output io_out_0_valid, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_3, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_4, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_5, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_6, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_7, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_8, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_9, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_8, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_9, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_8, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_9, // @[SwitchAllocator.scala:18:14] output [2:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14] ); reg [2:0] lock_0; // @[SwitchAllocator.scala:24:38] wire [2:0] unassigned = {io_in_2_valid, io_in_1_valid, io_in_0_valid} & ~lock_0; // @[SwitchAllocator.scala:24:38, :25:{23,52,54}] reg [2:0] mask; // @[SwitchAllocator.scala:27:21] wire [2:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}] wire [5:0] sel = _sel_T_1[0] ? 6'h1 : _sel_T_1[1] ? 6'h2 : _sel_T_1[2] ? 6'h4 : unassigned[0] ? 6'h8 : unassigned[1] ? 6'h10 : {unassigned[2], 5'h0}; // @[OneHot.scala:85:71] wire [2:0] in_valids = {io_in_2_valid, io_in_1_valid, io_in_0_valid}; // @[SwitchAllocator.scala:41:24] wire [2:0] chosen = (\|(in_valids & lock_0)) ? lock_0 : sel[2:0] \| sel[5:3]; // @[Mux.scala:50:70] wire [2:0] _io_out_0_valid_T = in_valids & chosen; // @[SwitchAllocator.scala:41:24, :42:21, :44:35] wire [1:0] _GEN = chosen[1:0] \| chosen[2:1]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] always @(posedge clock) begin // @[SwitchAllocator.scala:17:7] if (reset) begin // @[SwitchAllocator.scala:17:7] lock_0 <= 3'h0; // @[SwitchAllocator.scala:24:38] mask <= 3'h0; // @[SwitchAllocator.scala:27:21] end else begin // @[SwitchAllocator.scala:17:7] if (\|_io_out_0_valid_T) // @[SwitchAllocator.scala:44:{35,45}] lock_0 <= chosen & ~{io_in_2_bits_tail, io_in_1_bits_tail, io_in_0_bits_tail}; // @[SwitchAllocator.scala:24:38, :39:21, :42:21, :53:{25,27}] mask <= (\|_io_out_0_valid_T) ? {chosen[2], _GEN[1], _GEN[0] \| chosen[2]} : (&mask) ? 3'h0 : {mask[1:0], 1'h1}; // @[SwitchAllocator.scala:17:7, :27:21, :42:21, :44:{35,45}, :57:25, :58:{10,55,71}, :60:{10,16,23,49}] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_71( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_327 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry / case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic / val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U \| in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } / Write request logic / // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) \| usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U \| in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) / Read/write response logic / val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied \|\| out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B / Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. / def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } / ReservableListBuffer logic, and associated classes. / class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /* Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. / abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /* A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index / class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) \| validSet used := (used & ~usedClr) \| usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) \| dataIsPresentSet / Reservation logic signals / val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) / Response logic signals / val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) / Reservation logic / reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } / Response logic / // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } / Response unwind logic / // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent \|\| isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind \|\| (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind \|\| (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready \|\| !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire \|\| unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /* Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) \| usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }	module dataMems_399( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File ToAXI4.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.amba.{AMBACorrupt, AMBACorruptField, AMBAProt, AMBAProtField} import freechips.rocketchip.amba.axi4.{AXI4BundleARW, AXI4MasterParameters, AXI4MasterPortParameters, AXI4Parameters, AXI4Imp} import freechips.rocketchip.diplomacy.{IdMap, IdMapEntry, IdRange} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, UIntToOH1} import freechips.rocketchip.util.DataToAugmentedData class AXI4TLStateBundle(val sourceBits: Int) extends Bundle { val size = UInt(4.W) val source = UInt((sourceBits max 1).W) } case object AXI4TLState extends ControlKey[AXI4TLStateBundle]("tl_state") case class AXI4TLStateField(sourceBits: Int) extends BundleField[AXI4TLStateBundle](AXI4TLState, Output(new AXI4TLStateBundle(sourceBits)), x => { x.size := 0.U x.source := 0.U }) /* TLtoAXI4IdMap serves as a record for the translation performed between id spaces. * * Its member [axi4Masters] is used as the new AXI4MasterParameters in diplomacy. * Its member [mapping] is used as the template for the circuit generated in TLToAXI4Node.module. / class TLtoAXI4IdMap(tlPort: TLMasterPortParameters) extends IdMap[TLToAXI4IdMapEntry] { val tlMasters = tlPort.masters.sortBy(_.sourceId).sortWith(TLToAXI4.sortByType) private val axi4IdSize = tlMasters.map { tl => if (tl.requestFifo) 1 else tl.sourceId.size } private val axi4IdStart = axi4IdSize.scanLeft(0)(_+_).init val axi4Masters = axi4IdStart.zip(axi4IdSize).zip(tlMasters).map { case ((start, size), tl) => AXI4MasterParameters( name = tl.name, id = IdRange(start, start+size), aligned = true, maxFlight = Some(if (tl.requestFifo) tl.sourceId.size else 1), nodePath = tl.nodePath) } private val axi4IdEnd = axi4Masters.map(_.id.end).max private val axiDigits = String.valueOf(axi4IdEnd-1).length() private val tlDigits = String.valueOf(tlPort.endSourceId-1).length() protected val fmt = s"\t[%${axiDigits}d, %${axiDigits}d) <= [%${tlDigits}d, %${tlDigits}d) %s%s%s" val mapping: Seq[TLToAXI4IdMapEntry] = tlMasters.zip(axi4Masters).map { case (tl, axi) => TLToAXI4IdMapEntry(axi.id, tl.sourceId, tl.name, tl.supports.probe, tl.requestFifo) } } case class TLToAXI4IdMapEntry(axi4Id: IdRange, tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = axi4Id val maxTransactionsInFlight = Some(tlId.size) } case class TLToAXI4Node(wcorrupt: Boolean = true)(implicit valName: ValName) extends MixedAdapterNode(TLImp, AXI4Imp)( dFn = { p => AXI4MasterPortParameters( masters = (new TLtoAXI4IdMap(p)).axi4Masters, requestFields = (if (wcorrupt) Seq(AMBACorruptField()) else Seq()) ++ p.requestFields.filter(!_.isInstanceOf[AMBAProtField]), echoFields = AXI4TLStateField(log2Ceil(p.endSourceId)) +: p.echoFields, responseKeys = p.responseKeys) }, uFn = { p => TLSlavePortParameters.v1( managers = p.slaves.map { case s => TLSlaveParameters.v1( address = s.address, resources = s.resources, regionType = s.regionType, executable = s.executable, nodePath = s.nodePath, supportsGet = s.supportsRead, supportsPutFull = s.supportsWrite, supportsPutPartial = s.supportsWrite, fifoId = Some(0), mayDenyPut = true, mayDenyGet = true)}, beatBytes = p.beatBytes, minLatency = p.minLatency, responseFields = p.responseFields, requestKeys = AMBAProt +: p.requestKeys) }) // wcorrupt alone is not enough; a slave must include AMBACorrupt in the slave port's requestKeys class TLToAXI4(val combinational: Boolean = true, val adapterName: Option[String] = None, val stripBits: Int = 0, val wcorrupt: Boolean = true)(implicit p: Parameters) extends LazyModule { require(stripBits == 0, "stripBits > 0 is no longer supported on TLToAXI4") val node = TLToAXI4Node(wcorrupt) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val slaves = edgeOut.slave.slaves // All pairs of slaves must promise that they will never interleave data require (slaves(0).interleavedId.isDefined) slaves.foreach { s => require (s.interleavedId == slaves(0).interleavedId) } // Construct the source=>ID mapping table val map = new TLtoAXI4IdMap(edgeIn.client) val sourceStall = WireDefault(VecInit.fill(edgeIn.client.endSourceId)(false.B)) val sourceTable = WireDefault(VecInit.fill(edgeIn.client.endSourceId)(0.U.asTypeOf(out.aw.bits.id))) val idStall = WireDefault(VecInit.fill(edgeOut.master.endId)(false.B)) var idCount = Array.fill(edgeOut.master.endId) { None:Option[Int] } map.mapping.foreach { case TLToAXI4IdMapEntry(axi4Id, tlId, _, _, fifo) => for (i <- 0 until tlId.size) { val id = axi4Id.start + (if (fifo) 0 else i) sourceStall(tlId.start + i) := idStall(id) sourceTable(tlId.start + i) := id.U } if (fifo) { idCount(axi4Id.start) = Some(tlId.size) } } adapterName.foreach { n => println(s"$n AXI4-ID <= TL-Source mapping:\n${map.pretty}\n") ElaborationArtefacts.add(s"$n.axi4.json", s"""{"mapping":[${map.mapping.mkString(",")}]}""") } // We need to keep the following state from A => D: (size, source) // All of those fields could potentially require 0 bits (argh. Chisel.) // We will pack all of that extra information into the echo bits. require (log2Ceil(edgeIn.maxLgSize+1) <= 4) val a_address = edgeIn.address(in.a.bits) val a_source = in.a.bits.source val a_size = edgeIn.size(in.a.bits) val a_isPut = edgeIn.hasData(in.a.bits) val (a_first, a_last, _) = edgeIn.firstlast(in.a) val r_state = out.r.bits.echo(AXI4TLState) val r_source = r_state.source val r_size = r_state.size val b_state = out.b.bits.echo(AXI4TLState) val b_source = b_state.source val b_size = b_state.size // We need these Queues because AXI4 queues are irrevocable val depth = if (combinational) 1 else 2 val out_arw = Wire(Decoupled(new AXI4BundleARW(out.params))) val out_w = Wire(chiselTypeOf(out.w)) out.w :<>= Queue.irrevocable(out_w, entries=depth, flow=combinational) val queue_arw = Queue.irrevocable(out_arw, entries=depth, flow=combinational) // Fan out the ARW channel to AR and AW out.ar.bits := queue_arw.bits out.aw.bits := queue_arw.bits out.ar.valid := queue_arw.valid && !queue_arw.bits.wen out.aw.valid := queue_arw.valid && queue_arw.bits.wen queue_arw.ready := Mux(queue_arw.bits.wen, out.aw.ready, out.ar.ready) val beatBytes = edgeIn.manager.beatBytes val maxSize = log2Ceil(beatBytes).U val doneAW = RegInit(false.B) when (in.a.fire) { doneAW := !a_last } val arw = out_arw.bits arw.wen := a_isPut arw.id := sourceTable(a_source) arw.addr := a_address arw.len := UIntToOH1(a_size, AXI4Parameters.lenBits + log2Ceil(beatBytes)) >> log2Ceil(beatBytes) arw.size := Mux(a_size >= maxSize, maxSize, a_size) arw.burst := AXI4Parameters.BURST_INCR arw.lock := 0.U // not exclusive (LR/SC unsupported b/c no forward progress guarantee) arw.cache := 0.U // do not allow AXI to modify our transactions arw.prot := AXI4Parameters.PROT_PRIVILEGED arw.qos := 0.U // no QoS Connectable.waiveUnmatched(arw.user, in.a.bits.user) match { case (lhs, rhs) => lhs :<= rhs } Connectable.waiveUnmatched(arw.echo, in.a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = arw.echo(AXI4TLState) a_extra.source := a_source a_extra.size := a_size in.a.bits.user.lift(AMBAProt).foreach { x => val prot = Wire(Vec(3, Bool())) val cache = Wire(Vec(4, Bool())) prot(0) := x.privileged prot(1) := !x.secure prot(2) := x.fetch cache(0) := x.bufferable cache(1) := x.modifiable cache(2) := x.readalloc cache(3) := x.writealloc arw.prot := Cat(prot.reverse) arw.cache := Cat(cache.reverse) } val stall = sourceStall(in.a.bits.source) && a_first in.a.ready := !stall && Mux(a_isPut, (doneAW \|\| out_arw.ready) && out_w.ready, out_arw.ready) out_arw.valid := !stall && in.a.valid && Mux(a_isPut, !doneAW && out_w.ready, true.B) out_w.valid := !stall && in.a.valid && a_isPut && (doneAW \|\| out_arw.ready) out_w.bits.data := in.a.bits.data out_w.bits.strb := in.a.bits.mask out_w.bits.last := a_last out_w.bits.user.lift(AMBACorrupt).foreach { _ := in.a.bits.corrupt } // R and B => D arbitration val r_holds_d = RegInit(false.B) when (out.r.fire) { r_holds_d := !out.r.bits.last } // Give R higher priority than B, unless B has been delayed for 8 cycles val b_delay = Reg(UInt(3.W)) when (out.b.valid && !out.b.ready) { b_delay := b_delay + 1.U } .otherwise { b_delay := 0.U } val r_wins = (out.r.valid && b_delay =/= 7.U) \|\| r_holds_d out.r.ready := in.d.ready && r_wins out.b.ready := in.d.ready && !r_wins in.d.valid := Mux(r_wins, out.r.valid, out.b.valid) // If the first beat of the AXI RRESP is RESP_DECERR, treat this as a denied // request. We must pulse extend this value as AXI is allowed to change the // value of RRESP on every beat, and ChipLink may not. val r_first = RegInit(true.B) when (out.r.fire) { r_first := out.r.bits.last } val r_denied = out.r.bits.resp === AXI4Parameters.RESP_DECERR holdUnless r_first val r_corrupt = out.r.bits.resp =/= AXI4Parameters.RESP_OKAY val b_denied = out.b.bits.resp =/= AXI4Parameters.RESP_OKAY val r_d = edgeIn.AccessAck(r_source, r_size, 0.U, denied = r_denied, corrupt = r_corrupt \|\| r_denied) val b_d = edgeIn.AccessAck(b_source, b_size, denied = b_denied) Connectable.waiveUnmatched(r_d.user, out.r.bits.user) match { case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll } Connectable.waiveUnmatched(r_d.echo, out.r.bits.echo) match { case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll } Connectable.waiveUnmatched(b_d.user, out.b.bits.user) match { case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll } Connectable.waiveUnmatched(b_d.echo, out.b.bits.echo) match { case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll } in.d.bits := Mux(r_wins, r_d, b_d) in.d.bits.data := out.r.bits.data // avoid a costly Mux // We need to track if any reads or writes are inflight for a given ID. // If the opposite type arrives, we must stall until it completes. val a_sel = UIntToOH(arw.id, edgeOut.master.endId).asBools val d_sel = UIntToOH(Mux(r_wins, out.r.bits.id, out.b.bits.id), edgeOut.master.endId).asBools val d_last = Mux(r_wins, out.r.bits.last, true.B) // If FIFO was requested, ensure that R+W ordering is preserved (a_sel zip d_sel zip idStall zip idCount) foreach { case (((as, ds), s), n) => // AXI does not guarantee read vs. write ordering. In particular, if we // are in the middle of receiving a read burst and then issue a write, // the write might affect the read burst. This violates FIFO behaviour. // To solve this, we must wait until the last beat of a burst, but this // means that a TileLink master which performs early source reuse can // have one more transaction inflight than we promised AXI; stall it too. val maxCount = n.getOrElse(1) val count = RegInit(0.U(log2Ceil(maxCount + 1).W)) val write = Reg(Bool()) val idle = count === 0.U val inc = as && out_arw.fire val dec = ds && d_last && in.d.fire count := count + inc.asUInt - dec.asUInt assert (!dec \|\| count =/= 0.U) // underflow assert (!inc \|\| count =/= maxCount.U) // overflow when (inc) { write := arw.wen } // If only one transaction can be inflight, it can't mismatch val mismatch = if (maxCount > 1) { write =/= arw.wen } else { false.B } s := (!idle && mismatch) \|\| (count === maxCount.U) } // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B } } } object TLToAXI4 { def apply(combinational: Boolean = true, adapterName: Option[String] = None, stripBits: Int = 0, wcorrupt: Boolean = true)(implicit p: Parameters) = { val tl2axi4 = LazyModule(new TLToAXI4(combinational, adapterName, stripBits, wcorrupt)) tl2axi4.node } def sortByType(a: TLMasterParameters, b: TLMasterParameters): Boolean = { if ( a.supports.probe && !b.supports.probe) return false if (!a.supports.probe && b.supports.probe) return true if ( a.requestFifo && !b.requestFifo ) return false if (!a.requestFifo && b.requestFifo ) return true return false } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLToAXI4( // @[ToAXI4.scala:103:9] input clock, // @[ToAXI4.scala:103:9] input reset, // @[ToAXI4.scala:103:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_aw_ready, // @[LazyModuleImp.scala:107:25] output auto_out_aw_valid, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_aw_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_aw_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_aw_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_out_w_ready, // @[LazyModuleImp.scala:107:25] output auto_out_w_valid, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_w_bits_data, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_w_bits_strb, // @[LazyModuleImp.scala:107:25] output auto_out_w_bits_last, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [5:0] auto_out_b_bits_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_resp, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_out_b_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_out_ar_ready, // @[LazyModuleImp.scala:107:25] output auto_out_ar_valid, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_ar_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_ar_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_ar_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_out_r_ready, // @[LazyModuleImp.scala:107:25] input auto_out_r_valid, // @[LazyModuleImp.scala:107:25] input [5:0] auto_out_r_bits_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_r_bits_data, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_r_bits_resp, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_r_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_out_r_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_out_r_bits_last // @[LazyModuleImp.scala:107:25] ); reg count_57; // @[ToAXI4.scala:272:28] reg count_56; // @[ToAXI4.scala:272:28] reg count_55; // @[ToAXI4.scala:272:28] reg count_54; // @[ToAXI4.scala:272:28] reg count_53; // @[ToAXI4.scala:272:28] reg count_52; // @[ToAXI4.scala:272:28] reg count_51; // @[ToAXI4.scala:272:28] reg count_50; // @[ToAXI4.scala:272:28] reg count_49; // @[ToAXI4.scala:272:28] reg count_48; // @[ToAXI4.scala:272:28] reg count_47; // @[ToAXI4.scala:272:28] reg count_46; // @[ToAXI4.scala:272:28] reg count_45; // @[ToAXI4.scala:272:28] reg count_44; // @[ToAXI4.scala:272:28] reg count_43; // @[ToAXI4.scala:272:28] reg count_42; // @[ToAXI4.scala:272:28] reg count_41; // @[ToAXI4.scala:272:28] reg count_40; // @[ToAXI4.scala:272:28] reg count_39; // @[ToAXI4.scala:272:28] reg count_38; // @[ToAXI4.scala:272:28] reg count_37; // @[ToAXI4.scala:272:28] reg count_36; // @[ToAXI4.scala:272:28] reg count_35; // @[ToAXI4.scala:272:28] reg count_34; // @[ToAXI4.scala:272:28] reg count_33; // @[ToAXI4.scala:272:28] reg count_32; // @[ToAXI4.scala:272:28] reg count_31; // @[ToAXI4.scala:272:28] reg count_30; // @[ToAXI4.scala:272:28] reg count_29; // @[ToAXI4.scala:272:28] reg count_28; // @[ToAXI4.scala:272:28] reg count_27; // @[ToAXI4.scala:272:28] reg count_26; // @[ToAXI4.scala:272:28] reg count_25; // @[ToAXI4.scala:272:28] reg count_24; // @[ToAXI4.scala:272:28] reg count_23; // @[ToAXI4.scala:272:28] reg count_22; // @[ToAXI4.scala:272:28] reg count_21; // @[ToAXI4.scala:272:28] reg count_20; // @[ToAXI4.scala:272:28] reg count_19; // @[ToAXI4.scala:272:28] reg count_18; // @[ToAXI4.scala:272:28] reg count_17; // @[ToAXI4.scala:272:28] reg count_16; // @[ToAXI4.scala:272:28] reg count_15; // @[ToAXI4.scala:272:28] reg count_14; // @[ToAXI4.scala:272:28] reg count_13; // @[ToAXI4.scala:272:28] reg count_12; // @[ToAXI4.scala:272:28] reg count_11; // @[ToAXI4.scala:272:28] reg count_10; // @[ToAXI4.scala:272:28] reg count_9; // @[ToAXI4.scala:272:28] reg count_8; // @[ToAXI4.scala:272:28] reg count_7; // @[ToAXI4.scala:272:28] reg count_6; // @[ToAXI4.scala:272:28] reg count_5; // @[ToAXI4.scala:272:28] reg count_4; // @[ToAXI4.scala:272:28] reg count_3; // @[ToAXI4.scala:272:28] reg count_2; // @[ToAXI4.scala:272:28] reg count_1; // @[ToAXI4.scala:272:28] reg count; // @[ToAXI4.scala:272:28] wire _queue_arw_deq_q_io_enq_ready; // @[Decoupled.scala:362:21] wire _queue_arw_deq_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [5:0] _queue_arw_deq_q_io_deq_bits_id; // @[Decoupled.scala:362:21] wire [31:0] _queue_arw_deq_q_io_deq_bits_addr; // @[Decoupled.scala:362:21] wire [7:0] _queue_arw_deq_q_io_deq_bits_len; // @[Decoupled.scala:362:21] wire [2:0] _queue_arw_deq_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [1:0] _queue_arw_deq_q_io_deq_bits_burst; // @[Decoupled.scala:362:21] wire _queue_arw_deq_q_io_deq_bits_lock; // @[Decoupled.scala:362:21] wire [3:0] _queue_arw_deq_q_io_deq_bits_cache; // @[Decoupled.scala:362:21] wire [2:0] _queue_arw_deq_q_io_deq_bits_prot; // @[Decoupled.scala:362:21] wire [3:0] _queue_arw_deq_q_io_deq_bits_qos; // @[Decoupled.scala:362:21] wire [3:0] _queue_arw_deq_q_io_deq_bits_echo_tl_state_size; // @[Decoupled.scala:362:21] wire [5:0] _queue_arw_deq_q_io_deq_bits_echo_tl_state_source; // @[Decoupled.scala:362:21] wire _queue_arw_deq_q_io_deq_bits_wen; // @[Decoupled.scala:362:21] wire _nodeOut_w_deq_q_io_enq_ready; // @[Decoupled.scala:362:21] wire [63:0][5:0] _GEN = '{6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h39, 6'h38, 6'h37, 6'h36, 6'h35, 6'h34, 6'h33, 6'h32, 6'h31, 6'h30, 6'h2F, 6'h2E, 6'h2D, 6'h2C, 6'h2B, 6'h2A, 6'h29, 6'h28, 6'h27, 6'h26, 6'h25, 6'h24, 6'h23, 6'h22, 6'h21, 6'h20, 6'h1F, 6'h1E, 6'h1D, 6'h1C, 6'h1B, 6'h1A, 6'h19, 6'h18, 6'h17, 6'h16, 6'h15, 6'h14, 6'h13, 6'h12, 6'h11, 6'h10, 6'hF, 6'hE, 6'hD, 6'hC, 6'hB, 6'hA, 6'h9, 6'h8, 6'h7, 6'h6, 6'h5, 6'h4, 6'h3, 6'h2, 6'h1, 6'h0}; wire [12:0] _r_beats1_decode_T = 13'h3F << auto_in_a_bits_size; // @[package.scala:243:71] wire [2:0] r_beats1 = auto_in_a_bits_opcode[2] ? 3'h0 : ~(_r_beats1_decode_T[5:3]); // @[package.scala:243:{46,71,76}] reg [2:0] r_counter; // @[Edges.scala:229:27] wire a_first = r_counter == 3'h0; // @[ToAXI4.scala:103:9] wire a_last = r_counter == 3'h1 \| r_beats1 == 3'h0; // @[ToAXI4.scala:103:9] reg doneAW; // @[ToAXI4.scala:167:30] wire [17:0] _out_arw_bits_len_T = 18'h7FF << auto_in_a_bits_size; // @[package.scala:243:71] wire [63:0] _GEN_0 = {{count}, {count}, {count}, {count}, {count}, {count}, {count_57}, {count_56}, {count_55}, {count_54}, {count_53}, {count_52}, {count_51}, {count_50}, {count_49}, {count_48}, {count_47}, {count_46}, {count_45}, {count_44}, {count_43}, {count_42}, {count_41}, {count_40}, {count_39}, {count_38}, {count_37}, {count_36}, {count_35}, {count_34}, {count_33}, {count_32}, {count_31}, {count_30}, {count_29}, {count_28}, {count_27}, {count_26}, {count_25}, {count_24}, {count_23}, {count_22}, {count_21}, {count_20}, {count_19}, {count_18}, {count_17}, {count_16}, {count_15}, {count_14}, {count_13}, {count_12}, {count_11}, {count_10}, {count_9}, {count_8}, {count_7}, {count_6}, {count_5}, {count_4}, {count_3}, {count_2}, {count_1}, {count}}; // @[ToAXI4.scala:205:49, :272:28] wire stall = _GEN_0[auto_in_a_bits_source] & a_first; // @[ToAXI4.scala:205:49] wire _out_w_valid_T_3 = doneAW \| _queue_arw_deq_q_io_enq_ready; // @[Decoupled.scala:362:21] wire nodeIn_a_ready = ~stall & (auto_in_a_bits_opcode[2] ? _queue_arw_deq_q_io_enq_ready : _out_w_valid_T_3 & _nodeOut_w_deq_q_io_enq_ready); // @[Decoupled.scala:362:21] wire out_arw_valid = ~stall & auto_in_a_valid & (auto_in_a_bits_opcode[2] \| ~doneAW & _nodeOut_w_deq_q_io_enq_ready); // @[Decoupled.scala:362:21] reg r_holds_d; // @[ToAXI4.scala:216:30] reg [2:0] b_delay; // @[ToAXI4.scala:219:24] wire r_wins = auto_out_r_valid & b_delay != 3'h7 \| r_holds_d; // @[ToAXI4.scala:216:30, :219:24, :225:{33,44,53}] wire nodeOut_r_ready = auto_in_d_ready & r_wins; // @[ToAXI4.scala:225:53, :227:33] wire nodeOut_b_ready = auto_in_d_ready & ~r_wins; // @[ToAXI4.scala:225:53, :228:{33,36}] wire nodeIn_d_valid = r_wins ? auto_out_r_valid : auto_out_b_valid; // @[ToAXI4.scala:225:53, :229:24] reg r_first; // @[ToAXI4.scala:234:28] reg r_denied_r; // @[package.scala:88:63] wire r_denied = r_first ? (&auto_out_r_bits_resp) : r_denied_r; // @[package.scala:88:{42,63}] wire [2:0] nodeIn_d_bits_opcode = {2'h0, r_wins}; // @[ToAXI4.scala:103:9, :225:53, :255:23] wire [2:0] nodeIn_d_bits_size = r_wins ? auto_out_r_bits_echo_tl_state_size[2:0] : auto_out_b_bits_echo_tl_state_size[2:0]; // @[ToAXI4.scala:225:53, :255:23] wire [5:0] nodeIn_d_bits_source = r_wins ? auto_out_r_bits_echo_tl_state_source : auto_out_b_bits_echo_tl_state_source; // @[ToAXI4.scala:225:53, :255:23] wire nodeIn_d_bits_denied = r_wins ? r_denied : (\|auto_out_b_bits_resp); // @[package.scala:88:42] wire nodeIn_d_bits_corrupt = r_wins & ((\|auto_out_r_bits_resp) \| r_denied); // @[package.scala:88:42] wire [5:0] d_sel_shiftAmount = r_wins ? auto_out_r_bits_id : auto_out_b_bits_id; // @[ToAXI4.scala:225:53, :261:31] wire d_last = ~r_wins \| auto_out_r_bits_last; // @[ToAXI4.scala:225:53, :262:23] wire _inc_T_57 = _queue_arw_deq_q_io_enq_ready & out_arw_valid; // @[Decoupled.scala:51:35, :362:21] wire inc = _GEN[auto_in_a_bits_source] == 6'h0 & _inc_T_57; // @[OneHot.scala:65:27] wire _dec_T_115 = auto_in_d_ready & nodeIn_d_valid; // @[Decoupled.scala:51:35] wire dec = d_sel_shiftAmount == 6'h0 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_1 = _GEN[auto_in_a_bits_source] == 6'h1 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_1 = d_sel_shiftAmount == 6'h1 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_2 = _GEN[auto_in_a_bits_source] == 6'h2 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_2 = d_sel_shiftAmount == 6'h2 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_3 = _GEN[auto_in_a_bits_source] == 6'h3 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_3 = d_sel_shiftAmount == 6'h3 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_4 = _GEN[auto_in_a_bits_source] == 6'h4 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_4 = d_sel_shiftAmount == 6'h4 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_5 = _GEN[auto_in_a_bits_source] == 6'h5 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_5 = d_sel_shiftAmount == 6'h5 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_6 = _GEN[auto_in_a_bits_source] == 6'h6 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_6 = d_sel_shiftAmount == 6'h6 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_7 = _GEN[auto_in_a_bits_source] == 6'h7 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_7 = d_sel_shiftAmount == 6'h7 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_8 = _GEN[auto_in_a_bits_source] == 6'h8 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_8 = d_sel_shiftAmount == 6'h8 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_9 = _GEN[auto_in_a_bits_source] == 6'h9 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_9 = d_sel_shiftAmount == 6'h9 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_10 = _GEN[auto_in_a_bits_source] == 6'hA & _inc_T_57; // @[OneHot.scala:65:27] wire dec_10 = d_sel_shiftAmount == 6'hA & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_11 = _GEN[auto_in_a_bits_source] == 6'hB & _inc_T_57; // @[OneHot.scala:65:27] wire dec_11 = d_sel_shiftAmount == 6'hB & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_12 = _GEN[auto_in_a_bits_source] == 6'hC & _inc_T_57; // @[OneHot.scala:65:27] wire dec_12 = d_sel_shiftAmount == 6'hC & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_13 = _GEN[auto_in_a_bits_source] == 6'hD & _inc_T_57; // @[OneHot.scala:65:27] wire dec_13 = d_sel_shiftAmount == 6'hD & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_14 = _GEN[auto_in_a_bits_source] == 6'hE & _inc_T_57; // @[OneHot.scala:65:27] wire dec_14 = d_sel_shiftAmount == 6'hE & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_15 = _GEN[auto_in_a_bits_source] == 6'hF & _inc_T_57; // @[OneHot.scala:65:27] wire dec_15 = d_sel_shiftAmount == 6'hF & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_16 = _GEN[auto_in_a_bits_source] == 6'h10 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_16 = d_sel_shiftAmount == 6'h10 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_17 = _GEN[auto_in_a_bits_source] == 6'h11 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_17 = d_sel_shiftAmount == 6'h11 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_18 = _GEN[auto_in_a_bits_source] == 6'h12 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_18 = d_sel_shiftAmount == 6'h12 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_19 = _GEN[auto_in_a_bits_source] == 6'h13 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_19 = d_sel_shiftAmount == 6'h13 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_20 = _GEN[auto_in_a_bits_source] == 6'h14 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_20 = d_sel_shiftAmount == 6'h14 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_21 = _GEN[auto_in_a_bits_source] == 6'h15 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_21 = d_sel_shiftAmount == 6'h15 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_22 = _GEN[auto_in_a_bits_source] == 6'h16 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_22 = d_sel_shiftAmount == 6'h16 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_23 = _GEN[auto_in_a_bits_source] == 6'h17 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_23 = d_sel_shiftAmount == 6'h17 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_24 = _GEN[auto_in_a_bits_source] == 6'h18 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_24 = d_sel_shiftAmount == 6'h18 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_25 = _GEN[auto_in_a_bits_source] == 6'h19 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_25 = d_sel_shiftAmount == 6'h19 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_26 = _GEN[auto_in_a_bits_source] == 6'h1A & _inc_T_57; // @[OneHot.scala:65:27] wire dec_26 = d_sel_shiftAmount == 6'h1A & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_27 = _GEN[auto_in_a_bits_source] == 6'h1B & _inc_T_57; // @[OneHot.scala:65:27] wire dec_27 = d_sel_shiftAmount == 6'h1B & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_28 = _GEN[auto_in_a_bits_source] == 6'h1C & _inc_T_57; // @[OneHot.scala:65:27] wire dec_28 = d_sel_shiftAmount == 6'h1C & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_29 = _GEN[auto_in_a_bits_source] == 6'h1D & _inc_T_57; // @[OneHot.scala:65:27] wire dec_29 = d_sel_shiftAmount == 6'h1D & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_30 = _GEN[auto_in_a_bits_source] == 6'h1E & _inc_T_57; // @[OneHot.scala:65:27] wire dec_30 = d_sel_shiftAmount == 6'h1E & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_31 = _GEN[auto_in_a_bits_source] == 6'h1F & _inc_T_57; // @[OneHot.scala:65:27] wire dec_31 = d_sel_shiftAmount == 6'h1F & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_32 = _GEN[auto_in_a_bits_source] == 6'h20 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_32 = d_sel_shiftAmount == 6'h20 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_33 = _GEN[auto_in_a_bits_source] == 6'h21 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_33 = d_sel_shiftAmount == 6'h21 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_34 = _GEN[auto_in_a_bits_source] == 6'h22 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_34 = d_sel_shiftAmount == 6'h22 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_35 = _GEN[auto_in_a_bits_source] == 6'h23 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_35 = d_sel_shiftAmount == 6'h23 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_36 = _GEN[auto_in_a_bits_source] == 6'h24 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_36 = d_sel_shiftAmount == 6'h24 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_37 = _GEN[auto_in_a_bits_source] == 6'h25 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_37 = d_sel_shiftAmount == 6'h25 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_38 = _GEN[auto_in_a_bits_source] == 6'h26 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_38 = d_sel_shiftAmount == 6'h26 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_39 = _GEN[auto_in_a_bits_source] == 6'h27 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_39 = d_sel_shiftAmount == 6'h27 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_40 = _GEN[auto_in_a_bits_source] == 6'h28 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_40 = d_sel_shiftAmount == 6'h28 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_41 = _GEN[auto_in_a_bits_source] == 6'h29 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_41 = d_sel_shiftAmount == 6'h29 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_42 = _GEN[auto_in_a_bits_source] == 6'h2A & _inc_T_57; // @[OneHot.scala:65:27] wire dec_42 = d_sel_shiftAmount == 6'h2A & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_43 = _GEN[auto_in_a_bits_source] == 6'h2B & _inc_T_57; // @[OneHot.scala:65:27] wire dec_43 = d_sel_shiftAmount == 6'h2B & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_44 = _GEN[auto_in_a_bits_source] == 6'h2C & _inc_T_57; // @[OneHot.scala:65:27] wire dec_44 = d_sel_shiftAmount == 6'h2C & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_45 = _GEN[auto_in_a_bits_source] == 6'h2D & _inc_T_57; // @[OneHot.scala:65:27] wire dec_45 = d_sel_shiftAmount == 6'h2D & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_46 = _GEN[auto_in_a_bits_source] == 6'h2E & _inc_T_57; // @[OneHot.scala:65:27] wire dec_46 = d_sel_shiftAmount == 6'h2E & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_47 = _GEN[auto_in_a_bits_source] == 6'h2F & _inc_T_57; // @[OneHot.scala:65:27] wire dec_47 = d_sel_shiftAmount == 6'h2F & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_48 = _GEN[auto_in_a_bits_source] == 6'h30 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_48 = d_sel_shiftAmount == 6'h30 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_49 = _GEN[auto_in_a_bits_source] == 6'h31 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_49 = d_sel_shiftAmount == 6'h31 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_50 = _GEN[auto_in_a_bits_source] == 6'h32 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_50 = d_sel_shiftAmount == 6'h32 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_51 = _GEN[auto_in_a_bits_source] == 6'h33 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_51 = d_sel_shiftAmount == 6'h33 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_52 = _GEN[auto_in_a_bits_source] == 6'h34 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_52 = d_sel_shiftAmount == 6'h34 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_53 = _GEN[auto_in_a_bits_source] == 6'h35 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_53 = d_sel_shiftAmount == 6'h35 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_54 = _GEN[auto_in_a_bits_source] == 6'h36 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_54 = d_sel_shiftAmount == 6'h36 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_55 = _GEN[auto_in_a_bits_source] == 6'h37 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_55 = d_sel_shiftAmount == 6'h37 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_56 = _GEN[auto_in_a_bits_source] == 6'h38 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_56 = d_sel_shiftAmount == 6'h38 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_57 = _GEN[auto_in_a_bits_source] == 6'h39 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_57 = d_sel_shiftAmount == 6'h39 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File FPU.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util._ import chisel3.{DontCare, WireInit, withClock, withReset} import chisel3.experimental.SourceInfo import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property case class FPUParams( minFLen: Int = 32, fLen: Int = 64, divSqrt: Boolean = true, sfmaLatency: Int = 3, dfmaLatency: Int = 4, fpmuLatency: Int = 2, ifpuLatency: Int = 2 ) object FPConstants { val RM_SZ = 3 val FLAGS_SZ = 5 } trait HasFPUCtrlSigs { val ldst = Bool() val wen = Bool() val ren1 = Bool() val ren2 = Bool() val ren3 = Bool() val swap12 = Bool() val swap23 = Bool() val typeTagIn = UInt(2.W) val typeTagOut = UInt(2.W) val fromint = Bool() val toint = Bool() val fastpipe = Bool() val fma = Bool() val div = Bool() val sqrt = Bool() val wflags = Bool() val vec = Bool() } class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new Bundle { val inst = Input(Bits(32.W)) val sigs = Output(new FPUCtrlSigs()) }) private val X2 = BitPat.dontCare(2) val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N) val h: Array[(BitPat, List[BitPat])] = Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N), FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N), FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N), FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N), FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N), FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N), FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N), FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N), FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N)) val f: Array[(BitPat, List[BitPat])] = Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N), FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N), FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N), FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N), FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N), FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N), FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N)) val d: Array[(BitPat, List[BitPat])] = Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N), FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N), FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N), FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N), FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N), FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N), FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N), FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N), FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N)) val fcvt_hd: Array[(BitPat, List[BitPat])] = Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N), FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N)) val vfmv_f_s: Array[(BitPat, List[BitPat])] = Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y)) val insns = ((minFLen, fLen) match { case (32, 32) => f case (16, 32) => h ++ f case (32, 64) => f ++ d case (16, 64) => h ++ f ++ d ++ fcvt_hd case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration") }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]()) val decoder = DecodeLogic(io.inst, default, insns) val s = io.sigs val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec) sigs zip decoder map {case(s,d) => s := d} } class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val time = Input(UInt(xLen.W)) val inst = Input(Bits(32.W)) val fromint_data = Input(Bits(xLen.W)) val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W)) val v_sew = Input(UInt(3.W)) val store_data = Output(Bits(fLen.W)) val toint_data = Output(Bits(xLen.W)) val ll_resp_val = Input(Bool()) val ll_resp_type = Input(Bits(3.W)) val ll_resp_tag = Input(UInt(5.W)) val ll_resp_data = Input(Bits(fLen.W)) val valid = Input(Bool()) val fcsr_rdy = Output(Bool()) val nack_mem = Output(Bool()) val illegal_rm = Output(Bool()) val killx = Input(Bool()) val killm = Input(Bool()) val dec = Output(new FPUCtrlSigs()) val sboard_set = Output(Bool()) val sboard_clr = Output(Bool()) val sboard_clra = Output(UInt(5.W)) val keep_clock_enabled = Input(Bool()) } class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) { val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs val cp_resp = Decoupled(new FPResult()) } class FPResult(implicit p: Parameters) extends CoreBundle()(p) { val data = Bits((fLen+1).W) val exc = Bits(FPConstants.FLAGS_SZ.W) } class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val typ = Bits(2.W) val in1 = Bits(xLen.W) } class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val fmaCmd = Bits(2.W) val typ = Bits(2.W) val fmt = Bits(2.W) val in1 = Bits((fLen+1).W) val in2 = Bits((fLen+1).W) val in3 = Bits((fLen+1).W) } case class FType(exp: Int, sig: Int) { def ieeeWidth = exp + sig def recodedWidth = ieeeWidth + 1 def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W) def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W) def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2) def classify(x: UInt) = { val sign = x(sig + exp) val code = x(exp + sig - 1, exp + sig - 3) val codeHi = code(2, 1) val isSpecial = codeHi === 3.U val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U val isSubnormal = code === 1.U \|\| codeHi === 1.U && isHighSubnormalIn val isNormal = codeHi === 1.U && !isHighSubnormalIn \|\| codeHi === 2.U val isZero = code === 0.U val isInf = isSpecial && !code(0) val isNaN = code.andR val isSNaN = isNaN && !x(sig-2) val isQNaN = isNaN && x(sig-2) Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign, isSubnormal && !sign, isZero && !sign, isZero && sign, isSubnormal && sign, isNormal && sign, isInf && sign) } // convert between formats, ignoring rounding, range, NaN def unsafeConvert(x: UInt, to: FType) = if (this == to) x else { val sign = x(sig + exp) val fractIn = x(sig - 2, 0) val expIn = x(sig + exp - 1, sig - 1) val fractOut = fractIn << to.sig >> sig val expOut = { val expCode = expIn(exp, exp - 2) val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U Mux(expCode === 0.U \|\| expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0)) } Cat(sign, expOut, fractOut) } private def ieeeBundle = { val expWidth = exp class IEEEBundle extends Bundle { val sign = Bool() val exp = UInt(expWidth.W) val sig = UInt((ieeeWidth-expWidth-1).W) } new IEEEBundle } def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle) def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x) def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x) } object FType { val H = new FType(5, 11) val S = new FType(8, 24) val D = new FType(11, 53) val all = List(H, S, D) } trait HasFPUParameters { require(fLen == 0 \|\| FType.all.exists(_.ieeeWidth == fLen)) val minFLen: Int val fLen: Int def xLen: Int val minXLen = 32 val nIntTypes = log2Ceil(xLen/minXLen) + 1 def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen) def minType = floatTypes.head def maxType = floatTypes.last def prevType(t: FType) = floatTypes(typeTag(t) - 1) def maxExpWidth = maxType.exp def maxSigWidth = maxType.sig def typeTag(t: FType) = floatTypes.indexOf(t) def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U // typeTag def H = typeTagGroup(FType.H) def S = typeTagGroup(FType.S) def D = typeTagGroup(FType.D) def I = typeTag(maxType).U private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = { require(xt.ieeeWidth == 2 yt.ieeeWidth) val swizzledNaN = Cat( x(xt.sig + xt.exp, xt.sig + xt.exp - 3), x(xt.sig - 2, yt.recodedWidth - 1).andR, x(xt.sig + xt.exp - 5, xt.sig), y(yt.recodedWidth - 2), x(xt.sig - 2, yt.recodedWidth - 1), y(yt.recodedWidth - 1), y(yt.recodedWidth - 3, 0)) Mux(xt.isNaN(x), swizzledNaN, x) } // implement NaN unboxing for FU inputs def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = { val outType = exactType.getOrElse(maxType) def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = { val prev = if (t == minType) { Seq() } else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prev = helper(unswizzled, prevT) val isbox = isBox(x, t) prev.map(p => (isbox && p._1, p._2)) } prev :+ (true.B, t.unsafeConvert(x, outType)) } val (oks, floats) = helper(x, maxType).unzip if (exactType.isEmpty \|\| floatTypes.size == 1) { Mux(oks(tag), floats(tag), maxType.qNaN) } else { val t = exactType.get floats(typeTag(t)) \| Mux(oks(typeTag(t)), 0.U, t.qNaN) } } // make sure that the redundant bits in the NaN-boxed encoding are consistent def consistent(x: UInt): Bool = { def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prevOK = !isBox(x, t) \|\| helper(unswizzled, prevT) val curOK = !t.isNaN(x) \|\| x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR prevOK && curOK } helper(x, maxType) } // generate a NaN box from an FU result def box(x: UInt, t: FType): UInt = { if (t == maxType) { x } else { val nt = floatTypes(typeTag(t) + 1) val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t) bigger \| ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U } } // generate a NaN box from an FU result def box(x: UInt, tag: UInt): UInt = { val opts = floatTypes.map(t => box(x, t)) opts(tag) } // zap bits that hardfloat thinks are don't-cares, but we do care about def sanitizeNaN(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { x } else { val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) \| (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W) Mux(t.isNaN(x), maskedNaN, x) } } // implement NaN boxing and recoding for FL/fmv..x def recode(x: UInt, tag: UInt): UInt = { def helper(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { t.recode(x) } else { val prevT = prevType(t) box(t.recode(x), t, helper(x, prevT), prevT) } } // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U) helper(boxes(tag) \| x, maxType) } // implement NaN unboxing and un-recoding for FS/fmv.x. def ieee(x: UInt, t: FType = maxType): UInt = { if (typeTag(t) == 0) { t.ieee(x) } else { val unrecoded = t.ieee(x) val prevT = prevType(t) val prevRecoded = Cat( x(prevT.recodedWidth-2), x(t.sig-1), x(prevT.recodedWidth-3, 0)) val prevUnrecoded = ieee(prevRecoded, prevT) Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0))) } } } abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { class Output extends Bundle { val in = new FPInput val lt = Bool() val store = Bits(fLen.W) val toint = Bits(xLen.W) val exc = Bits(FPConstants.FLAGS_SZ.W) } val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new Output) }) val in = RegEnable(io.in.bits, io.in.valid) val valid = RegNext(io.in.valid) val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth)) dcmp.io.a := in.in1 dcmp.io.b := in.in2 dcmp.io.signaling := !in.rm(1) val tag = in.typeTagOut val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen)) else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) val toint = WireDefault(toint_ieee) val intType = WireDefault(in.fmt(0)) io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType) io.out.bits.exc := 0.U when (in.rm(0)) { val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag) toint := classify_out \| (toint_ieee >> minXLen << minXLen) intType := false.B } when (in.wflags) { // feq/flt/fle, fcvt toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR \| (toint_ieee >> minXLen << minXLen) io.out.bits.exc := dcmp.io.exceptionFlags intType := false.B when (!in.ren2) { // fcvt val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1) intType := cvtType val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen)) conv.io.in := in.in1 conv.io.roundingMode := in.rm conv.io.signedOut := ~in.typ(0) toint := conv.io.out io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0)) for (i <- 0 until nIntTypes-1) { val w = minXLen << i when (cvtType === i.U) { val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w)) narrow.io.in := in.in1 narrow.io.roundingMode := in.rm narrow.io.signedOut := ~in.typ(0) val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1) val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign)) val invalid = conv.io.intExceptionFlags(2) \|\| narrow.io.intExceptionFlags(1) when (invalid) { toint := Cat(conv.io.out >> w, excOut) } io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0)) } } } } io.out.valid := valid io.out.bits.lt := dcmp.io.lt \|\| (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S) io.out.bits.in := in } class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new IntToFPInput)) val out = Valid(new FPResult) }) val in = Pipe(io.in) val tag = in.bits.typeTagIn val mux = Wire(new FPResult) mux.exc := 0.U mux.data := recode(in.bits.in1, tag) val intValue = { val res = WireDefault(in.bits.in1.asSInt) for (i <- 0 until nIntTypes-1) { val smallInt = in.bits.in1((minXLen << i) - 1, 0) when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) { res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt) } } res.asUInt } when (in.bits.wflags) { // fcvt // could be improved for RVD/RVQ with a single variable-position rounding // unit, rather than N fixed-position ones val i2fResults = for (t <- floatTypes) yield { val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig)) i2f.io.signedIn := ~in.bits.typ(0) i2f.io.in := intValue i2f.io.roundingMode := in.bits.rm i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags) } val (data, exc) = i2fResults.unzip val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last mux.data := dataPadded(tag) mux.exc := exc(tag) } io.out <> Pipe(in.valid, mux, latency-1) } class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) val lt = Input(Bool()) // from FPToInt }) val in = Pipe(io.in) val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2)) val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0)) val fsgnjMux = Wire(new FPResult) fsgnjMux.exc := 0.U fsgnjMux.data := fsgnj when (in.bits.wflags) { // fmin/fmax val isnan1 = maxType.isNaN(in.bits.in1) val isnan2 = maxType.isNaN(in.bits.in2) val isInvalid = maxType.isSNaN(in.bits.in1) \|\| maxType.isSNaN(in.bits.in2) val isNaNOut = isnan1 && isnan2 val isLHS = isnan2 \|\| in.bits.rm(0) =/= io.lt && !isnan1 fsgnjMux.exc := isInvalid << 4 fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2)) } val inTag = in.bits.typeTagIn val outTag = in.bits.typeTagOut val mux = WireDefault(fsgnjMux) for (t <- floatTypes.init) { when (outTag === typeTag(t).U) { mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t)) } } when (in.bits.wflags && !in.bits.ren2) { // fcvt if (floatTypes.size > 1) { // widening conversions simply canonicalize NaN operands val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1) fsgnjMux.data := widened fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4 // narrowing conversions require rounding (for RVQ, this could be // optimized to use a single variable-position rounding unit, rather // than two fixed-position ones) for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B \|\| outTag < inTag)) { val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig)) narrower.io.in := in.bits.in1 narrower.io.roundingMode := in.bits.rm narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding val narrowed = sanitizeNaN(narrower.io.out, outType) mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed) mux.exc := narrower.io.exceptionFlags } } } io.out <> Pipe(in.valid, mux, latency-1) } class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module { override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}" require(latency<=2) val io = IO(new Bundle { val validin = Input(Bool()) val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) val validout = Output(Bool()) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC val valid_stage0 = Wire(Bool()) val roundingMode_stage0 = Wire(UInt(3.W)) val detectTininess_stage0 = Wire(UInt(1.W)) val postmul_regs = if(latency>0) 1 else 0 mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0)) val round_regs = if(latency==2) 1 else 0 roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits io.validout := Pipe(valid_stage0, false.B, round_regs).valid roundRawFNToRecFN.io.infiniteExc := false.B io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } class FPUFMAPipe(val latency: Int, val t: FType) (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}" require(latency>0) val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) }) val valid = RegNext(io.in.valid) val in = Reg(new FPInput) when (io.in.valid) { val one = 1.U << (t.sig + t.exp - 1) val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp)) val cmd_fma = io.in.bits.ren3 val cmd_addsub = io.in.bits.swap23 in := io.in.bits when (cmd_addsub) { in.in2 := one } when (!(cmd_fma \|\| cmd_addsub)) { in.in3 := zero } } val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig)) fma.io.validin := valid fma.io.op := in.fmaCmd fma.io.roundingMode := in.rm fma.io.detectTininess := hardfloat.consts.tininess_afterRounding fma.io.a := in.in1 fma.io.b := in.in2 fma.io.c := in.in3 val res = Wire(new FPResult) res.data := sanitizeNaN(fma.io.out, t) res.exc := fma.io.exceptionFlags io.out := Pipe(fma.io.validout, res, (latency-3) max 0) } class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new FPUIO) val (useClockGating, useDebugROB) = coreParams match { case r: RocketCoreParams => val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1 (r.clockGate, sz < 1) case _ => (false, false) } val clock_en_reg = Reg(Bool()) val clock_en = clock_en_reg \|\| io.cp_req.valid val gated_clock = if (!useClockGating) clock else ClockGate(clock, clock_en, "fpu_clock_gate") val fp_decoder = Module(new FPUDecoder) fp_decoder.io.inst := io.inst val id_ctrl = WireInit(fp_decoder.io.sigs) coreParams match { case r: RocketCoreParams => r.vector.map(v => { val v_decode = v.decoder(p) // Only need to get ren1 v_decode.io.inst := io.inst v_decode.io.vconfig := DontCare // core deals with this when (v_decode.io.legal && v_decode.io.read_frs1) { id_ctrl.ren1 := true.B id_ctrl.swap12 := false.B id_ctrl.toint := true.B id_ctrl.typeTagIn := I id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S) } when (v_decode.io.write_frd) { id_ctrl.wen := true.B } })} val ex_reg_valid = RegNext(io.valid, false.B) val ex_reg_inst = RegEnable(io.inst, io.valid) val ex_reg_ctrl = RegEnable(id_ctrl, io.valid) val ex_ra = List.fill(3)(Reg(UInt())) // load/vector response val load_wb = RegNext(io.ll_resp_val) val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val) val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val) val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val) class FPUImpl { // entering gated-clock domain val req_valid = ex_reg_valid \|\| io.cp_req.valid val ex_cp_valid = io.cp_req.fire val mem_cp_valid = RegNext(ex_cp_valid, false.B) val wb_cp_valid = RegNext(mem_cp_valid, false.B) val mem_reg_valid = RegInit(false.B) val killm = (io.killm \|\| io.nack_mem) && !mem_cp_valid // Kill X-stage instruction if M-stage is killed. This prevents it from // speculatively being sent to the div-sqrt unit, which can cause priority // inversion for two back-to-back divides, the first of which is killed. val killx = io.killx \|\| mem_reg_valid && killm mem_reg_valid := ex_reg_valid && !killx \|\| ex_cp_valid val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid) val wb_reg_valid = RegNext(mem_reg_valid && (!killm \|\| mem_cp_valid), false.B) val cp_ctrl = Wire(new FPUCtrlSigs) cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs) io.cp_resp.valid := false.B io.cp_resp.bits.data := 0.U io.cp_resp.bits.exc := DontCare val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl) val mem_ctrl = RegEnable(ex_ctrl, req_valid) val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid) // CoreMonitorBundle to monitor fp register file writes val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare)) frfWriteBundle.foreach { i => i.clock := clock i.reset := reset i.hartid := io.hartid i.timer := io.time(31,0) i.valid := false.B i.wrenx := false.B i.wrenf := false.B i.excpt := false.B } // regfile val regfile = Mem(32, Bits((fLen+1).W)) when (load_wb) { val wdata = recode(load_wb_data, load_wb_typeTag) regfile(load_wb_tag) := wdata assert(consistent(wdata)) if (enableCommitLog) printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata)) if (useDebugROB) DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata)) frfWriteBundle(0).wrdst := load_wb_tag frfWriteBundle(0).wrenf := true.B frfWriteBundle(0).wrdata := ieee(wdata) } val ex_rs = ex_ra.map(a => regfile(a)) when (io.valid) { when (id_ctrl.ren1) { when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) } when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) } } when (id_ctrl.ren2) { when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) } when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) } when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) } } when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) } } val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12)) def fuInput(minT: Option[FType]): FPInput = { val req = Wire(new FPInput) val tag = ex_ctrl.typeTagIn req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs) req.rm := ex_rm req.in1 := unbox(ex_rs(0), tag, minT) req.in2 := unbox(ex_rs(1), tag, minT) req.in3 := unbox(ex_rs(2), tag, minT) req.typ := ex_reg_inst(21,20) req.fmt := ex_reg_inst(26,25) req.fmaCmd := ex_reg_inst(3,2) \| (!ex_ctrl.ren3 && ex_reg_inst(27)) when (ex_cp_valid) { req := io.cp_req.bits when (io.cp_req.bits.swap12) { req.in1 := io.cp_req.bits.in2 req.in2 := io.cp_req.bits.in1 } when (io.cp_req.bits.swap23) { req.in2 := io.cp_req.bits.in3 req.in3 := io.cp_req.bits.in2 } } req } val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S)) sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S sfma.io.in.bits := fuInput(Some(sfma.t)) val fpiu = Module(new FPToInt) fpiu.io.in.valid := req_valid && (ex_ctrl.toint \|\| ex_ctrl.div \|\| ex_ctrl.sqrt \|\| (ex_ctrl.fastpipe && ex_ctrl.wflags)) fpiu.io.in.bits := fuInput(None) io.store_data := fpiu.io.out.bits.store io.toint_data := fpiu.io.out.bits.toint when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){ io.cp_resp.bits.data := fpiu.io.out.bits.toint io.cp_resp.valid := true.B } val ifpu = Module(new IntToFP(cfg.ifpuLatency)) ifpu.io.in.valid := req_valid && ex_ctrl.fromint ifpu.io.in.bits := fpiu.io.in.bits ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) val fpmu = Module(new FPToFP(cfg.fpmuLatency)) fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe fpmu.io.in.bits := fpiu.io.in.bits fpmu.io.lt := fpiu.io.out.bits.lt val divSqrt_wen = WireDefault(false.B) val divSqrt_inFlight = WireDefault(false.B) val divSqrt_waddr = Reg(UInt(5.W)) val divSqrt_cp = Reg(Bool()) val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W)) val divSqrt_wdata = Wire(UInt((fLen+1).W)) val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W)) divSqrt_typeTag := DontCare divSqrt_wdata := DontCare divSqrt_flags := DontCare // writeback arbitration case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult) val pipes = List( Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits), Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits), Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++ (fLen > 32).option({ val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D)) dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D dfma.io.in.bits := fuInput(Some(dfma.t)) Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits) }) ++ (minFLen == 16).option({ val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H)) hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H hfma.io.in.bits := fuInput(Some(hfma.t)) Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits) }) def latencyMask(c: FPUCtrlSigs, offset: Int) = { require(pipes.forall(_.lat >= offset)) pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_\|_) } def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_\|_) val maxLatency = pipes.map(_.lat).max val memLatencyMask = latencyMask(mem_ctrl, 2) class WBInfo extends Bundle { val rd = UInt(5.W) val typeTag = UInt(log2Up(floatTypes.size).W) val cp = Bool() val pipeid = UInt(log2Ceil(pipes.size).W) } val wen = RegInit(0.U((maxLatency-1).W)) val wbInfo = Reg(Vec(maxLatency-1, new WBInfo)) val mem_wen = mem_reg_valid && (mem_ctrl.fma \|\| mem_ctrl.fastpipe \|\| mem_ctrl.fromint) val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR \|\| (wen & latencyMask(ex_ctrl, 0)).orR, req_valid) ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback") for (i <- 0 until maxLatency-2) { when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) } } wen := wen >> 1 when (mem_wen) { when (!killm) { wen := wen >> 1 \| memLatencyMask } for (i <- 0 until maxLatency-1) { when (!write_port_busy && memLatencyMask(i)) { wbInfo(i).cp := mem_cp_valid wbInfo(i).typeTag := mem_ctrl.typeTagOut wbInfo(i).pipeid := pipeid(mem_ctrl) wbInfo(i).rd := mem_reg_inst(11,7) } } } val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd) val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp) val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag) val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag) val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid) when ((!wbInfo(0).cp && wen(0)) \|\| divSqrt_wen) { assert(consistent(wdata)) regfile(waddr) := wdata if (enableCommitLog) { printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata)) } frfWriteBundle(1).wrdst := waddr frfWriteBundle(1).wrenf := true.B frfWriteBundle(1).wrdata := ieee(wdata) } if (useDebugROB) { DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) \|\| divSqrt_wen, waddr + 32.U, ieee(wdata)) } when (wb_cp && (wen(0) \|\| divSqrt_wen)) { io.cp_resp.bits.data := wdata io.cp_resp.valid := true.B } assert(!io.cp_req.valid \|\| pipes.forall(_.lat == pipes.head.lat).B, s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}") // Avoid structural hazards and nacking of external requests // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight val wb_toint_valid = wb_reg_valid && wb_ctrl.toint val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint) io.fcsr_flags.valid := wb_toint_valid \|\| divSqrt_wen \|\| wen(0) io.fcsr_flags.bits := Mux(wb_toint_valid, wb_toint_exc, 0.U) \| Mux(divSqrt_wen, divSqrt_flags, 0.U) \| Mux(wen(0), wexc, 0.U) val divSqrt_write_port_busy = (mem_ctrl.div \|\| mem_ctrl.sqrt) && wen.orR io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags \|\| mem_reg_valid && mem_ctrl.wflags \|\| wb_reg_valid && wb_ctrl.toint \|\| wen.orR \|\| divSqrt_inFlight) io.nack_mem := (write_port_busy \|\| divSqrt_write_port_busy \|\| divSqrt_inFlight) && !mem_cp_valid io.dec <> id_ctrl def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_\|\|_) io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) \|\| mem_ctrl.div \|\| mem_ctrl.sqrt \|\| mem_ctrl.vec) io.sboard_clr := !wb_cp_valid && (divSqrt_wen \|\| (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U))) io.sboard_clra := waddr ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle") // we don't currently support round-max-magnitude (rm=4) io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) \|\| io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U if (cfg.divSqrt) { val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div \|\| mem_ctrl.sqrt) && !divSqrt_inFlight val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B) when (divSqrt_inValid) { divSqrt_waddr := mem_reg_inst(11,7) divSqrt_cp := mem_cp_valid } ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider") ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div \|\| mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard") ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback") for (t <- floatTypes) { val tag = mem_ctrl.typeTagOut val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) } divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U divSqrt.io.sqrtOp := mem_ctrl.sqrt divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t) divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t) divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight when (divSqrt.io.outValid_div \|\| divSqrt.io.outValid_sqrt) { divSqrt_wen := !divSqrt_killed divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t) divSqrt_flags := divSqrt.io.exceptionFlags divSqrt_typeTag := typeTag(t).U } } when (divSqrt_killed) { divSqrt_inFlight := false.B } } else { when (id_ctrl.div \|\| id_ctrl.sqrt) { io.illegal_rm := true.B } } // gate the clock clock_en_reg := !useClockGating.B \|\| io.keep_clock_enabled \|\| // chicken bit io.valid \|\| // ID stage req_valid \|\| // EX stage mem_reg_valid \|\| mem_cp_valid \|\| // MEM stage wb_reg_valid \|\| wb_cp_valid \|\| // WB stage wen.orR \|\| divSqrt_inFlight \|\| // post-WB stage io.ll_resp_val // load writeback } // leaving gated-clock domain val fpuImpl = withClock (gated_clock) { new FPUImpl } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"FPU_$label", "Core;;" + desc) } File fNFromRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ object fNFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits) = { val minNormExp = (BigInt(1)<<(expWidth - 1)) + 2 val rawIn = rawFloatFromRecFN(expWidth, sigWidth, in) val isSubnormal = rawIn.sExp < minNormExp.S val denormShiftDist = 1.U - rawIn.sExp(log2Up(sigWidth - 1) - 1, 0) val denormFract = ((rawIn.sig>>1)>>denormShiftDist)(sigWidth - 2, 0) val expOut = Mux(isSubnormal, 0.U, rawIn.sExp(expWidth - 1, 0) - ((BigInt(1)<<(expWidth - 1)) + 1).U ) \| Fill(expWidth, rawIn.isNaN \|\| rawIn.isInf) val fractOut = Mux(isSubnormal, denormFract, Mux(rawIn.isInf, 0.U, rawIn.sig(sigWidth - 2, 0)) ) Cat(rawIn.sign, expOut, fractOut) } } File rawFloatFromRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ /---------------------------------------------------------------------------- \| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be \| set. ----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }	module FPToInt_1( // @[FPU.scala:453:7] input clock, // @[FPU.scala:453:7] input reset, // @[FPU.scala:453:7] input io_in_valid, // @[FPU.scala:461:14] input io_in_bits_ldst, // @[FPU.scala:461:14] input io_in_bits_wen, // @[FPU.scala:461:14] input io_in_bits_ren1, // @[FPU.scala:461:14] input io_in_bits_ren2, // @[FPU.scala:461:14] input io_in_bits_ren3, // @[FPU.scala:461:14] input io_in_bits_swap12, // @[FPU.scala:461:14] input io_in_bits_swap23, // @[FPU.scala:461:14] input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:461:14] input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:461:14] input io_in_bits_fromint, // @[FPU.scala:461:14] input io_in_bits_toint, // @[FPU.scala:461:14] input io_in_bits_fastpipe, // @[FPU.scala:461:14] input io_in_bits_fma, // @[FPU.scala:461:14] input io_in_bits_div, // @[FPU.scala:461:14] input io_in_bits_sqrt, // @[FPU.scala:461:14] input io_in_bits_wflags, // @[FPU.scala:461:14] input io_in_bits_vec, // @[FPU.scala:461:14] input [2:0] io_in_bits_rm, // @[FPU.scala:461:14] input [1:0] io_in_bits_typ, // @[FPU.scala:461:14] input [64:0] io_in_bits_in1, // @[FPU.scala:461:14] input [64:0] io_in_bits_in2, // @[FPU.scala:461:14] output [2:0] io_out_bits_in_rm, // @[FPU.scala:461:14] output [64:0] io_out_bits_in_in1, // @[FPU.scala:461:14] output [64:0] io_out_bits_in_in2 // @[FPU.scala:461:14] ); wire [2:0] _narrow_io_intExceptionFlags; // @[FPU.scala:508:30] wire [63:0] _conv_io_out; // @[FPU.scala:498:24] wire [2:0] _conv_io_intExceptionFlags; // @[FPU.scala:498:24] wire _dcmp_io_lt; // @[FPU.scala:469:20] wire _dcmp_io_eq; // @[FPU.scala:469:20] wire [4:0] _dcmp_io_exceptionFlags; // @[FPU.scala:469:20] wire io_in_valid_0 = io_in_valid; // @[FPU.scala:453:7] wire io_in_bits_ldst_0 = io_in_bits_ldst; // @[FPU.scala:453:7] wire io_in_bits_wen_0 = io_in_bits_wen; // @[FPU.scala:453:7] wire io_in_bits_ren1_0 = io_in_bits_ren1; // @[FPU.scala:453:7] wire io_in_bits_ren2_0 = io_in_bits_ren2; // @[FPU.scala:453:7] wire io_in_bits_ren3_0 = io_in_bits_ren3; // @[FPU.scala:453:7] wire io_in_bits_swap12_0 = io_in_bits_swap12; // @[FPU.scala:453:7] wire io_in_bits_swap23_0 = io_in_bits_swap23; // @[FPU.scala:453:7] wire [1:0] io_in_bits_typeTagIn_0 = io_in_bits_typeTagIn; // @[FPU.scala:453:7] wire [1:0] io_in_bits_typeTagOut_0 = io_in_bits_typeTagOut; // @[FPU.scala:453:7] wire io_in_bits_fromint_0 = io_in_bits_fromint; // @[FPU.scala:453:7] wire io_in_bits_toint_0 = io_in_bits_toint; // @[FPU.scala:453:7] wire io_in_bits_fastpipe_0 = io_in_bits_fastpipe; // @[FPU.scala:453:7] wire io_in_bits_fma_0 = io_in_bits_fma; // @[FPU.scala:453:7] wire io_in_bits_div_0 = io_in_bits_div; // @[FPU.scala:453:7] wire io_in_bits_sqrt_0 = io_in_bits_sqrt; // @[FPU.scala:453:7] wire io_in_bits_wflags_0 = io_in_bits_wflags; // @[FPU.scala:453:7] wire io_in_bits_vec_0 = io_in_bits_vec; // @[FPU.scala:453:7] wire [2:0] io_in_bits_rm_0 = io_in_bits_rm; // @[FPU.scala:453:7] wire [1:0] io_in_bits_typ_0 = io_in_bits_typ; // @[FPU.scala:453:7] wire [64:0] io_in_bits_in1_0 = io_in_bits_in1; // @[FPU.scala:453:7] wire [64:0] io_in_bits_in2_0 = io_in_bits_in2; // @[FPU.scala:453:7] wire [1:0] io_in_bits_fmaCmd = 2'h0; // @[FPU.scala:453:7] wire [1:0] io_in_bits_fmt = 2'h0; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_fmaCmd = 2'h0; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_fmt = 2'h0; // @[FPU.scala:453:7] wire [64:0] io_in_bits_in3 = 65'h0; // @[FPU.scala:453:7, :524:53] wire [64:0] io_out_bits_in_in3 = 65'h0; // @[FPU.scala:453:7, :524:53] wire _intType_T = 1'h0; // @[FPU.scala:479:35] wire _io_out_bits_lt_T_5; // @[FPU.scala:524:32] wire [63:0] _io_out_bits_store_T_16; // @[package.scala:39:76] wire [63:0] _io_out_bits_toint_T_6; // @[package.scala:39:76] wire io_out_bits_in_ldst; // @[FPU.scala:453:7] wire io_out_bits_in_wen; // @[FPU.scala:453:7] wire io_out_bits_in_ren1; // @[FPU.scala:453:7] wire io_out_bits_in_ren2; // @[FPU.scala:453:7] wire io_out_bits_in_ren3; // @[FPU.scala:453:7] wire io_out_bits_in_swap12; // @[FPU.scala:453:7] wire io_out_bits_in_swap23; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_typeTagIn; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_typeTagOut; // @[FPU.scala:453:7] wire io_out_bits_in_fromint; // @[FPU.scala:453:7] wire io_out_bits_in_toint; // @[FPU.scala:453:7] wire io_out_bits_in_fastpipe; // @[FPU.scala:453:7] wire io_out_bits_in_fma; // @[FPU.scala:453:7] wire io_out_bits_in_div; // @[FPU.scala:453:7] wire io_out_bits_in_sqrt; // @[FPU.scala:453:7] wire io_out_bits_in_wflags; // @[FPU.scala:453:7] wire io_out_bits_in_vec; // @[FPU.scala:453:7] wire [2:0] io_out_bits_in_rm_0; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_typ; // @[FPU.scala:453:7] wire [64:0] io_out_bits_in_in1_0; // @[FPU.scala:453:7] wire [64:0] io_out_bits_in_in2_0; // @[FPU.scala:453:7] wire io_out_bits_lt; // @[FPU.scala:453:7] wire [63:0] io_out_bits_store; // @[FPU.scala:453:7] wire [63:0] io_out_bits_toint; // @[FPU.scala:453:7] wire [4:0] io_out_bits_exc; // @[FPU.scala:453:7] wire io_out_valid; // @[FPU.scala:453:7] reg in_ldst; // @[FPU.scala:466:21] assign io_out_bits_in_ldst = in_ldst; // @[FPU.scala:453:7, :466:21] reg in_wen; // @[FPU.scala:466:21] assign io_out_bits_in_wen = in_wen; // @[FPU.scala:453:7, :466:21] reg in_ren1; // @[FPU.scala:466:21] assign io_out_bits_in_ren1 = in_ren1; // @[FPU.scala:453:7, :466:21] reg in_ren2; // @[FPU.scala:466:21] assign io_out_bits_in_ren2 = in_ren2; // @[FPU.scala:453:7, :466:21] reg in_ren3; // @[FPU.scala:466:21] assign io_out_bits_in_ren3 = in_ren3; // @[FPU.scala:453:7, :466:21] reg in_swap12; // @[FPU.scala:466:21] assign io_out_bits_in_swap12 = in_swap12; // @[FPU.scala:453:7, :466:21] reg in_swap23; // @[FPU.scala:466:21] assign io_out_bits_in_swap23 = in_swap23; // @[FPU.scala:453:7, :466:21] reg [1:0] in_typeTagIn; // @[FPU.scala:466:21] assign io_out_bits_in_typeTagIn = in_typeTagIn; // @[FPU.scala:453:7, :466:21] reg [1:0] in_typeTagOut; // @[FPU.scala:466:21] assign io_out_bits_in_typeTagOut = in_typeTagOut; // @[FPU.scala:453:7, :466:21] wire [1:0] _toint_ieee_truncIdx_T = in_typeTagOut; // @[package.scala:38:21] wire [1:0] _io_out_bits_store_truncIdx_T = in_typeTagOut; // @[package.scala:38:21] wire [1:0] _classify_out_truncIdx_T = in_typeTagOut; // @[package.scala:38:21] reg in_fromint; // @[FPU.scala:466:21] assign io_out_bits_in_fromint = in_fromint; // @[FPU.scala:453:7, :466:21] reg in_toint; // @[FPU.scala:466:21] assign io_out_bits_in_toint = in_toint; // @[FPU.scala:453:7, :466:21] reg in_fastpipe; // @[FPU.scala:466:21] assign io_out_bits_in_fastpipe = in_fastpipe; // @[FPU.scala:453:7, :466:21] reg in_fma; // @[FPU.scala:466:21] assign io_out_bits_in_fma = in_fma; // @[FPU.scala:453:7, :466:21] reg in_div; // @[FPU.scala:466:21] assign io_out_bits_in_div = in_div; // @[FPU.scala:453:7, :466:21] reg in_sqrt; // @[FPU.scala:466:21] assign io_out_bits_in_sqrt = in_sqrt; // @[FPU.scala:453:7, :466:21] reg in_wflags; // @[FPU.scala:466:21] assign io_out_bits_in_wflags = in_wflags; // @[FPU.scala:453:7, :466:21] reg in_vec; // @[FPU.scala:466:21] assign io_out_bits_in_vec = in_vec; // @[FPU.scala:453:7, :466:21] reg [2:0] in_rm; // @[FPU.scala:466:21] assign io_out_bits_in_rm_0 = in_rm; // @[FPU.scala:453:7, :466:21] reg [1:0] in_typ; // @[FPU.scala:466:21] assign io_out_bits_in_typ = in_typ; // @[FPU.scala:453:7, :466:21] reg [64:0] in_in1; // @[FPU.scala:466:21] assign io_out_bits_in_in1_0 = in_in1; // @[FPU.scala:453:7, :466:21] wire [64:0] _io_out_bits_lt_T = in_in1; // @[FPU.scala:466:21, :524:46] reg [64:0] in_in2; // @[FPU.scala:466:21] assign io_out_bits_in_in2_0 = in_in2; // @[FPU.scala:453:7, :466:21] wire [64:0] _io_out_bits_lt_T_2 = in_in2; // @[FPU.scala:466:21, :524:72] reg valid; // @[FPU.scala:467:22] assign io_out_valid = valid; // @[FPU.scala:453:7, :467:22] wire _dcmp_io_signaling_T = in_rm[1]; // @[FPU.scala:466:21, :472:30] wire _dcmp_io_signaling_T_1 = ~_dcmp_io_signaling_T; // @[FPU.scala:472:{24,30}] wire [11:0] toint_ieee_unrecoded_rawIn_exp = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] toint_ieee_unrecoded_rawIn_exp_1 = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] io_out_bits_store_unrecoded_rawIn_exp = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] io_out_bits_store_unrecoded_rawIn_exp_1 = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] classify_out_expIn = in_in1[63:52]; // @[FPU.scala:276:18, :466:21] wire [2:0] _toint_ieee_unrecoded_rawIn_isZero_T = toint_ieee_unrecoded_rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_unrecoded_rawIn_isZero = _toint_ieee_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_unrecoded_rawIn_isZero_0 = toint_ieee_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_unrecoded_rawIn_isSpecial_T = toint_ieee_unrecoded_rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_unrecoded_rawIn_isSpecial = &_toint_ieee_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _toint_ieee_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _toint_ieee_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] toint_ieee_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] toint_ieee_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T = toint_ieee_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_unrecoded_rawIn_out_isInf_T = toint_ieee_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_unrecoded_rawIn_out_isNaN_T_1 = toint_ieee_unrecoded_rawIn_isSpecial & _toint_ieee_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_unrecoded_rawIn_isNaN = _toint_ieee_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_1 = ~_toint_ieee_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_unrecoded_rawIn_out_isInf_T_2 = toint_ieee_unrecoded_rawIn_isSpecial & _toint_ieee_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_unrecoded_rawIn_isInf = _toint_ieee_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_unrecoded_rawIn_out_sign_T = in_in1[64]; // @[FPU.scala:466:21] wire _toint_ieee_unrecoded_rawIn_out_sign_T_1 = in_in1[64]; // @[FPU.scala:466:21] wire _io_out_bits_store_unrecoded_rawIn_out_sign_T = in_in1[64]; // @[FPU.scala:466:21] wire _io_out_bits_store_unrecoded_rawIn_out_sign_T_1 = in_in1[64]; // @[FPU.scala:466:21] wire classify_out_sign = in_in1[64]; // @[FPU.scala:274:17, :466:21] wire classify_out_sign_2 = in_in1[64]; // @[FPU.scala:253:17, :466:21] wire _excSign_T = in_in1[64]; // @[FPU.scala:466:21, :513:31] assign toint_ieee_unrecoded_rawIn_sign = _toint_ieee_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_unrecoded_rawIn_out_sExp_T = {1'h0, toint_ieee_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_unrecoded_rawIn_sExp = _toint_ieee_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_unrecoded_rawIn_out_sig_T = ~toint_ieee_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_unrecoded_rawIn_out_sig_T_1 = {1'h0, _toint_ieee_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _toint_ieee_unrecoded_rawIn_out_sig_T_2 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] _toint_ieee_unrecoded_rawIn_out_sig_T_6 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_2 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_6 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] classify_out_fractIn = in_in1[51:0]; // @[FPU.scala:275:20, :466:21] assign _toint_ieee_unrecoded_rawIn_out_sig_T_3 = {_toint_ieee_unrecoded_rawIn_out_sig_T_1, _toint_ieee_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_unrecoded_rawIn_sig = _toint_ieee_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_unrecoded_isSubnormal = $signed(toint_ieee_unrecoded_rawIn_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_unrecoded_denormShiftDist_T = toint_ieee_unrecoded_rawIn_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _toint_ieee_unrecoded_denormShiftDist_T_1 = 7'h1 - {1'h0, _toint_ieee_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] toint_ieee_unrecoded_denormShiftDist = _toint_ieee_unrecoded_denormShiftDist_T_1[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _toint_ieee_unrecoded_denormFract_T = toint_ieee_unrecoded_rawIn_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _toint_ieee_unrecoded_denormFract_T_1 = _toint_ieee_unrecoded_denormFract_T >> toint_ieee_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] toint_ieee_unrecoded_denormFract = _toint_ieee_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _toint_ieee_unrecoded_expOut_T = toint_ieee_unrecoded_rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _toint_ieee_unrecoded_expOut_T_1 = {1'h0, _toint_ieee_unrecoded_expOut_T} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _toint_ieee_unrecoded_expOut_T_2 = _toint_ieee_unrecoded_expOut_T_1[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _toint_ieee_unrecoded_expOut_T_3 = toint_ieee_unrecoded_isSubnormal ? 11'h0 : _toint_ieee_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_unrecoded_expOut_T_4 = toint_ieee_unrecoded_rawIn_isNaN \| toint_ieee_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_unrecoded_expOut_T_5 = {11{_toint_ieee_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] toint_ieee_unrecoded_expOut = _toint_ieee_unrecoded_expOut_T_3 \| _toint_ieee_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _toint_ieee_unrecoded_fractOut_T = toint_ieee_unrecoded_rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _toint_ieee_unrecoded_fractOut_T_1 = toint_ieee_unrecoded_rawIn_isInf ? 52'h0 : _toint_ieee_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] toint_ieee_unrecoded_fractOut = toint_ieee_unrecoded_isSubnormal ? toint_ieee_unrecoded_denormFract : _toint_ieee_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] toint_ieee_unrecoded_hi = {toint_ieee_unrecoded_rawIn_sign, toint_ieee_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] toint_ieee_unrecoded = {toint_ieee_unrecoded_hi, toint_ieee_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire _toint_ieee_prevRecoded_T = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _toint_ieee_prevRecoded_T_3 = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _io_out_bits_store_prevRecoded_T = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _io_out_bits_store_prevRecoded_T_3 = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _toint_ieee_prevRecoded_T_1 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire _toint_ieee_prevRecoded_T_4 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire _io_out_bits_store_prevRecoded_T_1 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire _io_out_bits_store_prevRecoded_T_4 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire [30:0] _toint_ieee_prevRecoded_T_2 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [30:0] _toint_ieee_prevRecoded_T_5 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [30:0] _io_out_bits_store_prevRecoded_T_2 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [30:0] _io_out_bits_store_prevRecoded_T_5 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [1:0] toint_ieee_prevRecoded_hi = {_toint_ieee_prevRecoded_T, _toint_ieee_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] toint_ieee_prevRecoded = {toint_ieee_prevRecoded_hi, _toint_ieee_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [8:0] toint_ieee_prevUnrecoded_rawIn_exp = toint_ieee_prevRecoded[31:23]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_rawIn_isZero_T = toint_ieee_prevUnrecoded_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_rawIn_isZero = _toint_ieee_prevUnrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_rawIn_isZero_0 = toint_ieee_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_rawIn_isSpecial_T = toint_ieee_prevUnrecoded_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_rawIn_isSpecial = &_toint_ieee_prevUnrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _toint_ieee_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _toint_ieee_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] toint_ieee_prevUnrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_rawIn_out_isNaN_T = toint_ieee_prevUnrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_rawIn_out_isInf_T = toint_ieee_prevUnrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_rawIn_out_isNaN_T_1 = toint_ieee_prevUnrecoded_rawIn_isSpecial & _toint_ieee_prevUnrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_rawIn_isNaN = _toint_ieee_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_rawIn_out_isInf_T_1 = ~_toint_ieee_prevUnrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_rawIn_out_isInf_T_2 = toint_ieee_prevUnrecoded_rawIn_isSpecial & _toint_ieee_prevUnrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_rawIn_isInf = _toint_ieee_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_rawIn_out_sign_T = toint_ieee_prevRecoded[32]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_rawIn_sign = _toint_ieee_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_rawIn_out_sExp_T = {1'h0, toint_ieee_prevUnrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_rawIn_sExp = _toint_ieee_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_rawIn_out_sig_T = ~toint_ieee_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_rawIn_out_sig_T_1 = {1'h0, _toint_ieee_prevUnrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _toint_ieee_prevUnrecoded_rawIn_out_sig_T_2 = toint_ieee_prevRecoded[22:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_rawIn_out_sig_T_3 = {_toint_ieee_prevUnrecoded_rawIn_out_sig_T_1, _toint_ieee_prevUnrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_rawIn_sig = _toint_ieee_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_isSubnormal = $signed(toint_ieee_prevUnrecoded_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_denormShiftDist_T = toint_ieee_prevUnrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_denormShiftDist_T_1 = 6'h1 - {1'h0, _toint_ieee_prevUnrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] toint_ieee_prevUnrecoded_denormShiftDist = _toint_ieee_prevUnrecoded_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _toint_ieee_prevUnrecoded_denormFract_T = toint_ieee_prevUnrecoded_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _toint_ieee_prevUnrecoded_denormFract_T_1 = _toint_ieee_prevUnrecoded_denormFract_T >> toint_ieee_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] toint_ieee_prevUnrecoded_denormFract = _toint_ieee_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _toint_ieee_prevUnrecoded_expOut_T = toint_ieee_prevUnrecoded_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _toint_ieee_prevUnrecoded_expOut_T_1 = {1'h0, _toint_ieee_prevUnrecoded_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _toint_ieee_prevUnrecoded_expOut_T_2 = _toint_ieee_prevUnrecoded_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _toint_ieee_prevUnrecoded_expOut_T_3 = toint_ieee_prevUnrecoded_isSubnormal ? 8'h0 : _toint_ieee_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_expOut_T_4 = toint_ieee_prevUnrecoded_rawIn_isNaN \| toint_ieee_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _toint_ieee_prevUnrecoded_expOut_T_5 = {8{_toint_ieee_prevUnrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] toint_ieee_prevUnrecoded_expOut = _toint_ieee_prevUnrecoded_expOut_T_3 \| _toint_ieee_prevUnrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _toint_ieee_prevUnrecoded_fractOut_T = toint_ieee_prevUnrecoded_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _toint_ieee_prevUnrecoded_fractOut_T_1 = toint_ieee_prevUnrecoded_rawIn_isInf ? 23'h0 : _toint_ieee_prevUnrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] toint_ieee_prevUnrecoded_fractOut = toint_ieee_prevUnrecoded_isSubnormal ? toint_ieee_prevUnrecoded_denormFract : _toint_ieee_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] toint_ieee_prevUnrecoded_hi = {toint_ieee_prevUnrecoded_rawIn_sign, toint_ieee_prevUnrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] toint_ieee_prevUnrecoded = {toint_ieee_prevUnrecoded_hi, toint_ieee_prevUnrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire [31:0] _toint_ieee_T = toint_ieee_unrecoded[63:32]; // @[FPU.scala:446:21] wire [2:0] _toint_ieee_T_1 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] _toint_ieee_T_9 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] _io_out_bits_store_T_1 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] _io_out_bits_store_T_9 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] classify_out_code_1 = in_in1[63:61]; // @[FPU.scala:249:25, :254:17, :466:21] wire [2:0] _excSign_T_1 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire _toint_ieee_T_2 = &_toint_ieee_T_1; // @[FPU.scala:249:{25,56}] wire [31:0] _toint_ieee_T_3 = toint_ieee_unrecoded[31:0]; // @[FPU.scala:446:81] wire [31:0] _toint_ieee_T_4 = _toint_ieee_T_2 ? toint_ieee_prevUnrecoded : _toint_ieee_T_3; // @[FPU.scala:249:56, :446:{44,81}] wire [63:0] _toint_ieee_T_5 = {_toint_ieee_T, _toint_ieee_T_4}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _toint_ieee_T_6 = _toint_ieee_T_5[31:0]; // @[FPU.scala:446:10, :476:109] wire [63:0] _toint_ieee_T_7 = {2{_toint_ieee_T_6}}; // @[FPU.scala:476:{63,109}] wire [2:0] _toint_ieee_unrecoded_rawIn_isZero_T_1 = toint_ieee_unrecoded_rawIn_exp_1[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_unrecoded_rawIn_isZero_1 = _toint_ieee_unrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_unrecoded_rawIn_1_isZero = toint_ieee_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_unrecoded_rawIn_isSpecial_T_1 = toint_ieee_unrecoded_rawIn_exp_1[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_unrecoded_rawIn_isSpecial_1 = &_toint_ieee_unrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire [12:0] _toint_ieee_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _toint_ieee_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_unrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] toint_ieee_unrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] toint_ieee_unrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_2 = toint_ieee_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_3 = toint_ieee_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_unrecoded_rawIn_out_isNaN_T_3 = toint_ieee_unrecoded_rawIn_isSpecial_1 & _toint_ieee_unrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_unrecoded_rawIn_1_isNaN = _toint_ieee_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_4 = ~_toint_ieee_unrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_unrecoded_rawIn_out_isInf_T_5 = toint_ieee_unrecoded_rawIn_isSpecial_1 & _toint_ieee_unrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_unrecoded_rawIn_1_isInf = _toint_ieee_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign toint_ieee_unrecoded_rawIn_1_sign = _toint_ieee_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_unrecoded_rawIn_out_sExp_T_1 = {1'h0, toint_ieee_unrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_unrecoded_rawIn_1_sExp = _toint_ieee_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_unrecoded_rawIn_out_sig_T_4 = ~toint_ieee_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_unrecoded_rawIn_out_sig_T_5 = {1'h0, _toint_ieee_unrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] assign _toint_ieee_unrecoded_rawIn_out_sig_T_7 = {_toint_ieee_unrecoded_rawIn_out_sig_T_5, _toint_ieee_unrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_unrecoded_rawIn_1_sig = _toint_ieee_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_unrecoded_isSubnormal_1 = $signed(toint_ieee_unrecoded_rawIn_1_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_unrecoded_denormShiftDist_T_2 = toint_ieee_unrecoded_rawIn_1_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _toint_ieee_unrecoded_denormShiftDist_T_3 = 7'h1 - {1'h0, _toint_ieee_unrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] toint_ieee_unrecoded_denormShiftDist_1 = _toint_ieee_unrecoded_denormShiftDist_T_3[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _toint_ieee_unrecoded_denormFract_T_2 = toint_ieee_unrecoded_rawIn_1_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _toint_ieee_unrecoded_denormFract_T_3 = _toint_ieee_unrecoded_denormFract_T_2 >> toint_ieee_unrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] toint_ieee_unrecoded_denormFract_1 = _toint_ieee_unrecoded_denormFract_T_3[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _toint_ieee_unrecoded_expOut_T_6 = toint_ieee_unrecoded_rawIn_1_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _toint_ieee_unrecoded_expOut_T_7 = {1'h0, _toint_ieee_unrecoded_expOut_T_6} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _toint_ieee_unrecoded_expOut_T_8 = _toint_ieee_unrecoded_expOut_T_7[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _toint_ieee_unrecoded_expOut_T_9 = toint_ieee_unrecoded_isSubnormal_1 ? 11'h0 : _toint_ieee_unrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_unrecoded_expOut_T_10 = toint_ieee_unrecoded_rawIn_1_isNaN \| toint_ieee_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_unrecoded_expOut_T_11 = {11{_toint_ieee_unrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] toint_ieee_unrecoded_expOut_1 = _toint_ieee_unrecoded_expOut_T_9 \| _toint_ieee_unrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _toint_ieee_unrecoded_fractOut_T_2 = toint_ieee_unrecoded_rawIn_1_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _toint_ieee_unrecoded_fractOut_T_3 = toint_ieee_unrecoded_rawIn_1_isInf ? 52'h0 : _toint_ieee_unrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] toint_ieee_unrecoded_fractOut_1 = toint_ieee_unrecoded_isSubnormal_1 ? toint_ieee_unrecoded_denormFract_1 : _toint_ieee_unrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] toint_ieee_unrecoded_hi_1 = {toint_ieee_unrecoded_rawIn_1_sign, toint_ieee_unrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] toint_ieee_unrecoded_1 = {toint_ieee_unrecoded_hi_1, toint_ieee_unrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] toint_ieee_prevRecoded_hi_1 = {_toint_ieee_prevRecoded_T_3, _toint_ieee_prevRecoded_T_4}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] toint_ieee_prevRecoded_1 = {toint_ieee_prevRecoded_hi_1, _toint_ieee_prevRecoded_T_5}; // @[FPU.scala:441:28, :444:10] wire [8:0] toint_ieee_prevUnrecoded_rawIn_exp_1 = toint_ieee_prevRecoded_1[31:23]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_rawIn_isZero_T_1 = toint_ieee_prevUnrecoded_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_rawIn_isZero_1 = _toint_ieee_prevUnrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_rawIn_1_isZero = toint_ieee_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_rawIn_isSpecial_T_1 = toint_ieee_prevUnrecoded_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_rawIn_isSpecial_1 = &_toint_ieee_prevUnrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _toint_ieee_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _toint_ieee_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] toint_ieee_prevUnrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_rawIn_out_isNaN_T_2 = toint_ieee_prevUnrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_rawIn_out_isInf_T_3 = toint_ieee_prevUnrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_rawIn_out_isNaN_T_3 = toint_ieee_prevUnrecoded_rawIn_isSpecial_1 & _toint_ieee_prevUnrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_rawIn_1_isNaN = _toint_ieee_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_rawIn_out_isInf_T_4 = ~_toint_ieee_prevUnrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_rawIn_out_isInf_T_5 = toint_ieee_prevUnrecoded_rawIn_isSpecial_1 & _toint_ieee_prevUnrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_rawIn_1_isInf = _toint_ieee_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_rawIn_out_sign_T_1 = toint_ieee_prevRecoded_1[32]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_rawIn_1_sign = _toint_ieee_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_rawIn_out_sExp_T_1 = {1'h0, toint_ieee_prevUnrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_rawIn_1_sExp = _toint_ieee_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_rawIn_out_sig_T_4 = ~toint_ieee_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_rawIn_out_sig_T_5 = {1'h0, _toint_ieee_prevUnrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _toint_ieee_prevUnrecoded_rawIn_out_sig_T_6 = toint_ieee_prevRecoded_1[22:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_rawIn_out_sig_T_7 = {_toint_ieee_prevUnrecoded_rawIn_out_sig_T_5, _toint_ieee_prevUnrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_rawIn_1_sig = _toint_ieee_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_isSubnormal_1 = $signed(toint_ieee_prevUnrecoded_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_denormShiftDist_T_2 = toint_ieee_prevUnrecoded_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_denormShiftDist_T_3 = 6'h1 - {1'h0, _toint_ieee_prevUnrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] toint_ieee_prevUnrecoded_denormShiftDist_1 = _toint_ieee_prevUnrecoded_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _toint_ieee_prevUnrecoded_denormFract_T_2 = toint_ieee_prevUnrecoded_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _toint_ieee_prevUnrecoded_denormFract_T_3 = _toint_ieee_prevUnrecoded_denormFract_T_2 >> toint_ieee_prevUnrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] toint_ieee_prevUnrecoded_denormFract_1 = _toint_ieee_prevUnrecoded_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _toint_ieee_prevUnrecoded_expOut_T_6 = toint_ieee_prevUnrecoded_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _toint_ieee_prevUnrecoded_expOut_T_7 = {1'h0, _toint_ieee_prevUnrecoded_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _toint_ieee_prevUnrecoded_expOut_T_8 = _toint_ieee_prevUnrecoded_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _toint_ieee_prevUnrecoded_expOut_T_9 = toint_ieee_prevUnrecoded_isSubnormal_1 ? 8'h0 : _toint_ieee_prevUnrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_expOut_T_10 = toint_ieee_prevUnrecoded_rawIn_1_isNaN \| toint_ieee_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _toint_ieee_prevUnrecoded_expOut_T_11 = {8{_toint_ieee_prevUnrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] toint_ieee_prevUnrecoded_expOut_1 = _toint_ieee_prevUnrecoded_expOut_T_9 \| _toint_ieee_prevUnrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _toint_ieee_prevUnrecoded_fractOut_T_2 = toint_ieee_prevUnrecoded_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _toint_ieee_prevUnrecoded_fractOut_T_3 = toint_ieee_prevUnrecoded_rawIn_1_isInf ? 23'h0 : _toint_ieee_prevUnrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] toint_ieee_prevUnrecoded_fractOut_1 = toint_ieee_prevUnrecoded_isSubnormal_1 ? toint_ieee_prevUnrecoded_denormFract_1 : _toint_ieee_prevUnrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] toint_ieee_prevUnrecoded_hi_1 = {toint_ieee_prevUnrecoded_rawIn_1_sign, toint_ieee_prevUnrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] toint_ieee_prevUnrecoded_1 = {toint_ieee_prevUnrecoded_hi_1, toint_ieee_prevUnrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire [31:0] _toint_ieee_T_8 = toint_ieee_unrecoded_1[63:32]; // @[FPU.scala:446:21] wire _toint_ieee_T_10 = &_toint_ieee_T_9; // @[FPU.scala:249:{25,56}] wire [31:0] _toint_ieee_T_11 = toint_ieee_unrecoded_1[31:0]; // @[FPU.scala:446:81] wire [31:0] _toint_ieee_T_12 = _toint_ieee_T_10 ? toint_ieee_prevUnrecoded_1 : _toint_ieee_T_11; // @[FPU.scala:249:56, :446:{44,81}] wire [63:0] _toint_ieee_T_13 = {_toint_ieee_T_8, _toint_ieee_T_12}; // @[FPU.scala:446:{10,21,44}] wire [63:0] _toint_ieee_T_14 = _toint_ieee_T_13; // @[FPU.scala:446:10, :476:109] wire toint_ieee_truncIdx = _toint_ieee_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _toint_ieee_T_15 = toint_ieee_truncIdx; // @[package.scala:38:47, :39:86] wire [63:0] toint_ieee = _toint_ieee_T_15 ? _toint_ieee_T_14 : _toint_ieee_T_7; // @[package.scala:39:{76,86}] wire [63:0] toint; // @[FPU.scala:478:26] wire [63:0] _io_out_bits_toint_T_4 = toint; // @[FPU.scala:478:26, :481:59] wire intType; // @[FPU.scala:479:28] wire _io_out_bits_toint_T_5 = intType; // @[package.scala:39:86] wire [2:0] _io_out_bits_store_unrecoded_rawIn_isZero_T = io_out_bits_store_unrecoded_rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_unrecoded_rawIn_isZero = _io_out_bits_store_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_unrecoded_rawIn_isZero_0 = io_out_bits_store_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_unrecoded_rawIn_isSpecial_T = io_out_bits_store_unrecoded_rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_unrecoded_rawIn_isSpecial = &_io_out_bits_store_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire [12:0] _io_out_bits_store_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] io_out_bits_store_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] io_out_bits_store_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T = io_out_bits_store_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T = io_out_bits_store_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1 = io_out_bits_store_unrecoded_rawIn_isSpecial & _io_out_bits_store_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_unrecoded_rawIn_isNaN = _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1 = ~_io_out_bits_store_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2 = io_out_bits_store_unrecoded_rawIn_isSpecial & _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_unrecoded_rawIn_isInf = _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign io_out_bits_store_unrecoded_rawIn_sign = _io_out_bits_store_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_unrecoded_rawIn_out_sExp_T = {1'h0, io_out_bits_store_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_unrecoded_rawIn_sExp = _io_out_bits_store_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_unrecoded_rawIn_out_sig_T = ~io_out_bits_store_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_1 = {1'h0, _io_out_bits_store_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] assign _io_out_bits_store_unrecoded_rawIn_out_sig_T_3 = {_io_out_bits_store_unrecoded_rawIn_out_sig_T_1, _io_out_bits_store_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_unrecoded_rawIn_sig = _io_out_bits_store_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_unrecoded_isSubnormal = $signed(io_out_bits_store_unrecoded_rawIn_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_unrecoded_denormShiftDist_T = io_out_bits_store_unrecoded_rawIn_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _io_out_bits_store_unrecoded_denormShiftDist_T_1 = 7'h1 - {1'h0, _io_out_bits_store_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] io_out_bits_store_unrecoded_denormShiftDist = _io_out_bits_store_unrecoded_denormShiftDist_T_1[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T = io_out_bits_store_unrecoded_rawIn_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_1 = _io_out_bits_store_unrecoded_denormFract_T >> io_out_bits_store_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] io_out_bits_store_unrecoded_denormFract = _io_out_bits_store_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T = io_out_bits_store_unrecoded_rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _io_out_bits_store_unrecoded_expOut_T_1 = {1'h0, _io_out_bits_store_unrecoded_expOut_T} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_2 = _io_out_bits_store_unrecoded_expOut_T_1[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_3 = io_out_bits_store_unrecoded_isSubnormal ? 11'h0 : _io_out_bits_store_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_unrecoded_expOut_T_4 = io_out_bits_store_unrecoded_rawIn_isNaN \| io_out_bits_store_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_5 = {11{_io_out_bits_store_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] io_out_bits_store_unrecoded_expOut = _io_out_bits_store_unrecoded_expOut_T_3 \| _io_out_bits_store_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T = io_out_bits_store_unrecoded_rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_1 = io_out_bits_store_unrecoded_rawIn_isInf ? 52'h0 : _io_out_bits_store_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] io_out_bits_store_unrecoded_fractOut = io_out_bits_store_unrecoded_isSubnormal ? io_out_bits_store_unrecoded_denormFract : _io_out_bits_store_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] io_out_bits_store_unrecoded_hi = {io_out_bits_store_unrecoded_rawIn_sign, io_out_bits_store_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] io_out_bits_store_unrecoded = {io_out_bits_store_unrecoded_hi, io_out_bits_store_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] io_out_bits_store_prevRecoded_hi = {_io_out_bits_store_prevRecoded_T, _io_out_bits_store_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] io_out_bits_store_prevRecoded = {io_out_bits_store_prevRecoded_hi, _io_out_bits_store_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [8:0] io_out_bits_store_prevUnrecoded_rawIn_exp = io_out_bits_store_prevRecoded[31:23]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_rawIn_isZero_T = io_out_bits_store_prevUnrecoded_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_rawIn_isZero = _io_out_bits_store_prevUnrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_rawIn_isZero_0 = io_out_bits_store_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_rawIn_isSpecial_T = io_out_bits_store_prevUnrecoded_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_rawIn_isSpecial = &_io_out_bits_store_prevUnrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_bits_store_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_bits_store_prevUnrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_rawIn_out_isNaN_T = io_out_bits_store_prevUnrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T = io_out_bits_store_prevUnrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_rawIn_out_isNaN_T_1 = io_out_bits_store_prevUnrecoded_rawIn_isSpecial & _io_out_bits_store_prevUnrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_rawIn_isNaN = _io_out_bits_store_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_1 = ~_io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_2 = io_out_bits_store_prevUnrecoded_rawIn_isSpecial & _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_rawIn_isInf = _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_rawIn_out_sign_T = io_out_bits_store_prevRecoded[32]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_rawIn_sign = _io_out_bits_store_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_rawIn_out_sExp_T = {1'h0, io_out_bits_store_prevUnrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_rawIn_sExp = _io_out_bits_store_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T = ~io_out_bits_store_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_1 = {1'h0, _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_2 = io_out_bits_store_prevRecoded[22:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_3 = {_io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_1, _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_rawIn_sig = _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_isSubnormal = $signed(io_out_bits_store_prevUnrecoded_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_denormShiftDist_T = io_out_bits_store_prevUnrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_denormShiftDist_T_1 = 6'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_bits_store_prevUnrecoded_denormShiftDist = _io_out_bits_store_prevUnrecoded_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_bits_store_prevUnrecoded_denormFract_T = io_out_bits_store_prevUnrecoded_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_bits_store_prevUnrecoded_denormFract_T_1 = _io_out_bits_store_prevUnrecoded_denormFract_T >> io_out_bits_store_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_bits_store_prevUnrecoded_denormFract = _io_out_bits_store_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_bits_store_prevUnrecoded_expOut_T = io_out_bits_store_prevUnrecoded_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_bits_store_prevUnrecoded_expOut_T_1 = {1'h0, _io_out_bits_store_prevUnrecoded_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_bits_store_prevUnrecoded_expOut_T_2 = _io_out_bits_store_prevUnrecoded_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_bits_store_prevUnrecoded_expOut_T_3 = io_out_bits_store_prevUnrecoded_isSubnormal ? 8'h0 : _io_out_bits_store_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_expOut_T_4 = io_out_bits_store_prevUnrecoded_rawIn_isNaN \| io_out_bits_store_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_bits_store_prevUnrecoded_expOut_T_5 = {8{_io_out_bits_store_prevUnrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_bits_store_prevUnrecoded_expOut = _io_out_bits_store_prevUnrecoded_expOut_T_3 \| _io_out_bits_store_prevUnrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_bits_store_prevUnrecoded_fractOut_T = io_out_bits_store_prevUnrecoded_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_bits_store_prevUnrecoded_fractOut_T_1 = io_out_bits_store_prevUnrecoded_rawIn_isInf ? 23'h0 : _io_out_bits_store_prevUnrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_bits_store_prevUnrecoded_fractOut = io_out_bits_store_prevUnrecoded_isSubnormal ? io_out_bits_store_prevUnrecoded_denormFract : _io_out_bits_store_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_bits_store_prevUnrecoded_hi = {io_out_bits_store_prevUnrecoded_rawIn_sign, io_out_bits_store_prevUnrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] io_out_bits_store_prevUnrecoded = {io_out_bits_store_prevUnrecoded_hi, io_out_bits_store_prevUnrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire [31:0] _io_out_bits_store_T = io_out_bits_store_unrecoded[63:32]; // @[FPU.scala:446:21] wire _io_out_bits_store_T_2 = &_io_out_bits_store_T_1; // @[FPU.scala:249:{25,56}] wire [31:0] _io_out_bits_store_T_3 = io_out_bits_store_unrecoded[31:0]; // @[FPU.scala:446:81] wire [31:0] _io_out_bits_store_T_4 = _io_out_bits_store_T_2 ? io_out_bits_store_prevUnrecoded : _io_out_bits_store_T_3; // @[FPU.scala:249:56, :446:{44,81}] wire [63:0] _io_out_bits_store_T_5 = {_io_out_bits_store_T, _io_out_bits_store_T_4}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _io_out_bits_store_T_6 = _io_out_bits_store_T_5[31:0]; // @[FPU.scala:446:10, :480:82] wire [63:0] _io_out_bits_store_T_7 = {2{_io_out_bits_store_T_6}}; // @[FPU.scala:480:{49,82}] wire [2:0] _io_out_bits_store_unrecoded_rawIn_isZero_T_1 = io_out_bits_store_unrecoded_rawIn_exp_1[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_unrecoded_rawIn_isZero_1 = _io_out_bits_store_unrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_unrecoded_rawIn_1_isZero = io_out_bits_store_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_unrecoded_rawIn_isSpecial_T_1 = io_out_bits_store_unrecoded_rawIn_exp_1[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_unrecoded_rawIn_isSpecial_1 = &_io_out_bits_store_unrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire [12:0] _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_unrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] io_out_bits_store_unrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] io_out_bits_store_unrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2 = io_out_bits_store_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_3 = io_out_bits_store_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3 = io_out_bits_store_unrecoded_rawIn_isSpecial_1 & _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_unrecoded_rawIn_1_isNaN = _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4 = ~_io_out_bits_store_unrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5 = io_out_bits_store_unrecoded_rawIn_isSpecial_1 & _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_unrecoded_rawIn_1_isInf = _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign io_out_bits_store_unrecoded_rawIn_1_sign = _io_out_bits_store_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1 = {1'h0, io_out_bits_store_unrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_unrecoded_rawIn_1_sExp = _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_unrecoded_rawIn_out_sig_T_4 = ~io_out_bits_store_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_5 = {1'h0, _io_out_bits_store_unrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] assign _io_out_bits_store_unrecoded_rawIn_out_sig_T_7 = {_io_out_bits_store_unrecoded_rawIn_out_sig_T_5, _io_out_bits_store_unrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_unrecoded_rawIn_1_sig = _io_out_bits_store_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_unrecoded_isSubnormal_1 = $signed(io_out_bits_store_unrecoded_rawIn_1_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_unrecoded_denormShiftDist_T_2 = io_out_bits_store_unrecoded_rawIn_1_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _io_out_bits_store_unrecoded_denormShiftDist_T_3 = 7'h1 - {1'h0, _io_out_bits_store_unrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] io_out_bits_store_unrecoded_denormShiftDist_1 = _io_out_bits_store_unrecoded_denormShiftDist_T_3[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_2 = io_out_bits_store_unrecoded_rawIn_1_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_3 = _io_out_bits_store_unrecoded_denormFract_T_2 >> io_out_bits_store_unrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] io_out_bits_store_unrecoded_denormFract_1 = _io_out_bits_store_unrecoded_denormFract_T_3[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_6 = io_out_bits_store_unrecoded_rawIn_1_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _io_out_bits_store_unrecoded_expOut_T_7 = {1'h0, _io_out_bits_store_unrecoded_expOut_T_6} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_8 = _io_out_bits_store_unrecoded_expOut_T_7[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_9 = io_out_bits_store_unrecoded_isSubnormal_1 ? 11'h0 : _io_out_bits_store_unrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_unrecoded_expOut_T_10 = io_out_bits_store_unrecoded_rawIn_1_isNaN \| io_out_bits_store_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_11 = {11{_io_out_bits_store_unrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] io_out_bits_store_unrecoded_expOut_1 = _io_out_bits_store_unrecoded_expOut_T_9 \| _io_out_bits_store_unrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_2 = io_out_bits_store_unrecoded_rawIn_1_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_3 = io_out_bits_store_unrecoded_rawIn_1_isInf ? 52'h0 : _io_out_bits_store_unrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] io_out_bits_store_unrecoded_fractOut_1 = io_out_bits_store_unrecoded_isSubnormal_1 ? io_out_bits_store_unrecoded_denormFract_1 : _io_out_bits_store_unrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] io_out_bits_store_unrecoded_hi_1 = {io_out_bits_store_unrecoded_rawIn_1_sign, io_out_bits_store_unrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] io_out_bits_store_unrecoded_1 = {io_out_bits_store_unrecoded_hi_1, io_out_bits_store_unrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] io_out_bits_store_prevRecoded_hi_1 = {_io_out_bits_store_prevRecoded_T_3, _io_out_bits_store_prevRecoded_T_4}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] io_out_bits_store_prevRecoded_1 = {io_out_bits_store_prevRecoded_hi_1, _io_out_bits_store_prevRecoded_T_5}; // @[FPU.scala:441:28, :444:10] wire [8:0] io_out_bits_store_prevUnrecoded_rawIn_exp_1 = io_out_bits_store_prevRecoded_1[31:23]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_rawIn_isZero_T_1 = io_out_bits_store_prevUnrecoded_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_rawIn_isZero_1 = _io_out_bits_store_prevUnrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_rawIn_1_isZero = io_out_bits_store_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_rawIn_isSpecial_T_1 = io_out_bits_store_prevUnrecoded_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_rawIn_isSpecial_1 = &_io_out_bits_store_prevUnrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_bits_store_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_bits_store_prevUnrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_rawIn_out_isNaN_T_2 = io_out_bits_store_prevUnrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_3 = io_out_bits_store_prevUnrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_rawIn_out_isNaN_T_3 = io_out_bits_store_prevUnrecoded_rawIn_isSpecial_1 & _io_out_bits_store_prevUnrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_rawIn_1_isNaN = _io_out_bits_store_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_4 = ~_io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_5 = io_out_bits_store_prevUnrecoded_rawIn_isSpecial_1 & _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_rawIn_1_isInf = _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_rawIn_out_sign_T_1 = io_out_bits_store_prevRecoded_1[32]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_rawIn_1_sign = _io_out_bits_store_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_rawIn_out_sExp_T_1 = {1'h0, io_out_bits_store_prevUnrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_rawIn_1_sExp = _io_out_bits_store_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_4 = ~io_out_bits_store_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_5 = {1'h0, _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_6 = io_out_bits_store_prevRecoded_1[22:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_7 = {_io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_5, _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_rawIn_1_sig = _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_isSubnormal_1 = $signed(io_out_bits_store_prevUnrecoded_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_denormShiftDist_T_2 = io_out_bits_store_prevUnrecoded_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_denormShiftDist_T_3 = 6'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_bits_store_prevUnrecoded_denormShiftDist_1 = _io_out_bits_store_prevUnrecoded_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_bits_store_prevUnrecoded_denormFract_T_2 = io_out_bits_store_prevUnrecoded_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_bits_store_prevUnrecoded_denormFract_T_3 = _io_out_bits_store_prevUnrecoded_denormFract_T_2 >> io_out_bits_store_prevUnrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_bits_store_prevUnrecoded_denormFract_1 = _io_out_bits_store_prevUnrecoded_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_bits_store_prevUnrecoded_expOut_T_6 = io_out_bits_store_prevUnrecoded_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_bits_store_prevUnrecoded_expOut_T_7 = {1'h0, _io_out_bits_store_prevUnrecoded_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_bits_store_prevUnrecoded_expOut_T_8 = _io_out_bits_store_prevUnrecoded_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_bits_store_prevUnrecoded_expOut_T_9 = io_out_bits_store_prevUnrecoded_isSubnormal_1 ? 8'h0 : _io_out_bits_store_prevUnrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_expOut_T_10 = io_out_bits_store_prevUnrecoded_rawIn_1_isNaN \| io_out_bits_store_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_bits_store_prevUnrecoded_expOut_T_11 = {8{_io_out_bits_store_prevUnrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_bits_store_prevUnrecoded_expOut_1 = _io_out_bits_store_prevUnrecoded_expOut_T_9 \| _io_out_bits_store_prevUnrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_bits_store_prevUnrecoded_fractOut_T_2 = io_out_bits_store_prevUnrecoded_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_bits_store_prevUnrecoded_fractOut_T_3 = io_out_bits_store_prevUnrecoded_rawIn_1_isInf ? 23'h0 : _io_out_bits_store_prevUnrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_bits_store_prevUnrecoded_fractOut_1 = io_out_bits_store_prevUnrecoded_isSubnormal_1 ? io_out_bits_store_prevUnrecoded_denormFract_1 : _io_out_bits_store_prevUnrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_bits_store_prevUnrecoded_hi_1 = {io_out_bits_store_prevUnrecoded_rawIn_1_sign, io_out_bits_store_prevUnrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] io_out_bits_store_prevUnrecoded_1 = {io_out_bits_store_prevUnrecoded_hi_1, io_out_bits_store_prevUnrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire [31:0] _io_out_bits_store_T_8 = io_out_bits_store_unrecoded_1[63:32]; // @[FPU.scala:446:21] wire _io_out_bits_store_T_10 = &_io_out_bits_store_T_9; // @[FPU.scala:249:{25,56}] wire [31:0] _io_out_bits_store_T_11 = io_out_bits_store_unrecoded_1[31:0]; // @[FPU.scala:446:81] wire [31:0] _io_out_bits_store_T_12 = _io_out_bits_store_T_10 ? io_out_bits_store_prevUnrecoded_1 : _io_out_bits_store_T_11; // @[FPU.scala:249:56, :446:{44,81}] wire [63:0] _io_out_bits_store_T_13 = {_io_out_bits_store_T_8, _io_out_bits_store_T_12}; // @[FPU.scala:446:{10,21,44}] wire [63:0] _io_out_bits_store_T_14 = _io_out_bits_store_T_13; // @[FPU.scala:446:10, :480:82] wire io_out_bits_store_truncIdx = _io_out_bits_store_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_out_bits_store_T_15 = io_out_bits_store_truncIdx; // @[package.scala:38:47, :39:86] assign _io_out_bits_store_T_16 = _io_out_bits_store_T_15 ? _io_out_bits_store_T_14 : _io_out_bits_store_T_7; // @[package.scala:39:{76,86}] assign io_out_bits_store = _io_out_bits_store_T_16; // @[package.scala:39:76] wire [31:0] _io_out_bits_toint_T = toint[31:0]; // @[FPU.scala:478:26, :481:59] wire _io_out_bits_toint_T_1 = _io_out_bits_toint_T[31]; // @[package.scala:132:38] wire [31:0] _io_out_bits_toint_T_2 = {32{_io_out_bits_toint_T_1}}; // @[package.scala:132:{20,38}] wire [63:0] _io_out_bits_toint_T_3 = {_io_out_bits_toint_T_2, _io_out_bits_toint_T}; // @[package.scala:132:{15,20}] assign _io_out_bits_toint_T_6 = _io_out_bits_toint_T_5 ? _io_out_bits_toint_T_4 : _io_out_bits_toint_T_3; // @[package.scala:39:{76,86}, :132:15] assign io_out_bits_toint = _io_out_bits_toint_T_6; // @[package.scala:39:76] wire [75:0] _classify_out_fractOut_T = {classify_out_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] classify_out_fractOut = _classify_out_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] classify_out_expOut_expCode = classify_out_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _classify_out_expOut_commonCase_T = {1'h0, classify_out_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _classify_out_expOut_commonCase_T_1 = _classify_out_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _classify_out_expOut_commonCase_T_2 = {1'h0, _classify_out_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] classify_out_expOut_commonCase = _classify_out_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _classify_out_expOut_T = classify_out_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _classify_out_expOut_T_1 = classify_out_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _classify_out_expOut_T_2 = _classify_out_expOut_T \| _classify_out_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [5:0] _classify_out_expOut_T_3 = classify_out_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _classify_out_expOut_T_4 = {classify_out_expOut_expCode, _classify_out_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _classify_out_expOut_T_5 = classify_out_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] classify_out_expOut = _classify_out_expOut_T_2 ? _classify_out_expOut_T_4 : _classify_out_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] classify_out_hi = {classify_out_sign, classify_out_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] _classify_out_T = {classify_out_hi, classify_out_fractOut}; // @[FPU.scala:277:38, :283:8] wire classify_out_sign_1 = _classify_out_T[32]; // @[FPU.scala:253:17, :283:8] wire [2:0] classify_out_code = _classify_out_T[31:29]; // @[FPU.scala:254:17, :283:8] wire [1:0] classify_out_codeHi = classify_out_code[2:1]; // @[FPU.scala:254:17, :255:22] wire classify_out_isSpecial = &classify_out_codeHi; // @[FPU.scala:255:22, :256:28] wire [6:0] _classify_out_isHighSubnormalIn_T = _classify_out_T[29:23]; // @[FPU.scala:258:30, :283:8] wire classify_out_isHighSubnormalIn = _classify_out_isHighSubnormalIn_T < 7'h2; // @[FPU.scala:258:{30,55}] wire _classify_out_isSubnormal_T = classify_out_code == 3'h1; // @[FPU.scala:254:17, :259:28] wire _GEN = classify_out_codeHi == 2'h1; // @[FPU.scala:255:22, :259:46] wire _classify_out_isSubnormal_T_1; // @[FPU.scala:259:46] assign _classify_out_isSubnormal_T_1 = _GEN; // @[FPU.scala:259:46] wire _classify_out_isNormal_T; // @[FPU.scala:260:27] assign _classify_out_isNormal_T = _GEN; // @[FPU.scala:259:46, :260:27] wire _classify_out_isSubnormal_T_2 = _classify_out_isSubnormal_T_1 & classify_out_isHighSubnormalIn; // @[FPU.scala:258:55, :259:{46,54}] wire classify_out_isSubnormal = _classify_out_isSubnormal_T \| _classify_out_isSubnormal_T_2; // @[FPU.scala:259:{28,36,54}] wire _classify_out_isNormal_T_1 = ~classify_out_isHighSubnormalIn; // @[FPU.scala:258:55, :260:38] wire _classify_out_isNormal_T_2 = _classify_out_isNormal_T & _classify_out_isNormal_T_1; // @[FPU.scala:260:{27,35,38}] wire _classify_out_isNormal_T_3 = classify_out_codeHi == 2'h2; // @[FPU.scala:255:22, :260:67] wire classify_out_isNormal = _classify_out_isNormal_T_2 \| _classify_out_isNormal_T_3; // @[FPU.scala:260:{35,57,67}] wire classify_out_isZero = classify_out_code == 3'h0; // @[FPU.scala:254:17, :261:23] wire _classify_out_isInf_T = classify_out_code[0]; // @[FPU.scala:254:17, :262:35] wire _classify_out_isInf_T_1 = ~_classify_out_isInf_T; // @[FPU.scala:262:{30,35}] wire classify_out_isInf = classify_out_isSpecial & _classify_out_isInf_T_1; // @[FPU.scala:256:28, :262:{27,30}] wire classify_out_isNaN = &classify_out_code; // @[FPU.scala:254:17, :263:22] wire _classify_out_isSNaN_T = _classify_out_T[22]; // @[FPU.scala:264:29, :283:8] wire _classify_out_isQNaN_T = _classify_out_T[22]; // @[FPU.scala:264:29, :265:28, :283:8] wire _classify_out_isSNaN_T_1 = ~_classify_out_isSNaN_T; // @[FPU.scala:264:{27,29}] wire classify_out_isSNaN = classify_out_isNaN & _classify_out_isSNaN_T_1; // @[FPU.scala:263:22, :264:{24,27}] wire classify_out_isQNaN = classify_out_isNaN & _classify_out_isQNaN_T; // @[FPU.scala:263:22, :265:{24,28}] wire _classify_out_T_1 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:34] wire _classify_out_T_2 = classify_out_isInf & _classify_out_T_1; // @[FPU.scala:262:27, :267:{31,34}] wire _classify_out_T_3 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:{34,53}] wire _classify_out_T_4 = classify_out_isNormal & _classify_out_T_3; // @[FPU.scala:260:57, :267:{50,53}] wire _classify_out_T_5 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:34, :268:24] wire _classify_out_T_6 = classify_out_isSubnormal & _classify_out_T_5; // @[FPU.scala:259:36, :268:{21,24}] wire _classify_out_T_7 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:34, :268:41] wire _classify_out_T_8 = classify_out_isZero & _classify_out_T_7; // @[FPU.scala:261:23, :268:{38,41}] wire _classify_out_T_9 = classify_out_isZero & classify_out_sign_1; // @[FPU.scala:253:17, :261:23, :268:55] wire _classify_out_T_10 = classify_out_isSubnormal & classify_out_sign_1; // @[FPU.scala:253:17, :259:36, :269:21] wire _classify_out_T_11 = classify_out_isNormal & classify_out_sign_1; // @[FPU.scala:253:17, :260:57, :269:39] wire _classify_out_T_12 = classify_out_isInf & classify_out_sign_1; // @[FPU.scala:253:17, :262:27, :269:54] wire [1:0] classify_out_lo_lo = {_classify_out_T_11, _classify_out_T_12}; // @[FPU.scala:267:8, :269:{39,54}] wire [1:0] classify_out_lo_hi_hi = {_classify_out_T_8, _classify_out_T_9}; // @[FPU.scala:267:8, :268:{38,55}] wire [2:0] classify_out_lo_hi = {classify_out_lo_hi_hi, _classify_out_T_10}; // @[FPU.scala:267:8, :269:21] wire [4:0] classify_out_lo = {classify_out_lo_hi, classify_out_lo_lo}; // @[FPU.scala:267:8] wire [1:0] classify_out_hi_lo = {_classify_out_T_4, _classify_out_T_6}; // @[FPU.scala:267:{8,50}, :268:21] wire [1:0] classify_out_hi_hi_hi = {classify_out_isQNaN, classify_out_isSNaN}; // @[FPU.scala:264:24, :265:24, :267:8] wire [2:0] classify_out_hi_hi = {classify_out_hi_hi_hi, _classify_out_T_2}; // @[FPU.scala:267:{8,31}] wire [4:0] classify_out_hi_1 = {classify_out_hi_hi, classify_out_hi_lo}; // @[FPU.scala:267:8] wire [9:0] _classify_out_T_13 = {classify_out_hi_1, classify_out_lo}; // @[FPU.scala:267:8] wire [1:0] classify_out_codeHi_1 = classify_out_code_1[2:1]; // @[FPU.scala:254:17, :255:22] wire classify_out_isSpecial_1 = &classify_out_codeHi_1; // @[FPU.scala:255:22, :256:28] wire [9:0] _classify_out_isHighSubnormalIn_T_1 = in_in1[61:52]; // @[FPU.scala:258:30, :466:21] wire classify_out_isHighSubnormalIn_1 = _classify_out_isHighSubnormalIn_T_1 < 10'h2; // @[FPU.scala:258:{30,55}] wire _classify_out_isSubnormal_T_3 = classify_out_code_1 == 3'h1; // @[FPU.scala:254:17, :259:28] wire _GEN_0 = classify_out_codeHi_1 == 2'h1; // @[FPU.scala:255:22, :259:46] wire _classify_out_isSubnormal_T_4; // @[FPU.scala:259:46] assign _classify_out_isSubnormal_T_4 = _GEN_0; // @[FPU.scala:259:46] wire _classify_out_isNormal_T_4; // @[FPU.scala:260:27] assign _classify_out_isNormal_T_4 = _GEN_0; // @[FPU.scala:259:46, :260:27] wire _classify_out_isSubnormal_T_5 = _classify_out_isSubnormal_T_4 & classify_out_isHighSubnormalIn_1; // @[FPU.scala:258:55, :259:{46,54}] wire classify_out_isSubnormal_1 = _classify_out_isSubnormal_T_3 \| _classify_out_isSubnormal_T_5; // @[FPU.scala:259:{28,36,54}] wire _classify_out_isNormal_T_5 = ~classify_out_isHighSubnormalIn_1; // @[FPU.scala:258:55, :260:38] wire _classify_out_isNormal_T_6 = _classify_out_isNormal_T_4 & _classify_out_isNormal_T_5; // @[FPU.scala:260:{27,35,38}] wire _classify_out_isNormal_T_7 = classify_out_codeHi_1 == 2'h2; // @[FPU.scala:255:22, :260:67] wire classify_out_isNormal_1 = _classify_out_isNormal_T_6 \| _classify_out_isNormal_T_7; // @[FPU.scala:260:{35,57,67}] wire classify_out_isZero_1 = classify_out_code_1 == 3'h0; // @[FPU.scala:254:17, :261:23] wire _classify_out_isInf_T_2 = classify_out_code_1[0]; // @[FPU.scala:254:17, :262:35] wire _classify_out_isInf_T_3 = ~_classify_out_isInf_T_2; // @[FPU.scala:262:{30,35}] wire classify_out_isInf_1 = classify_out_isSpecial_1 & _classify_out_isInf_T_3; // @[FPU.scala:256:28, :262:{27,30}] wire classify_out_isNaN_1 = &classify_out_code_1; // @[FPU.scala:254:17, :263:22] wire _classify_out_isSNaN_T_2 = in_in1[51]; // @[FPU.scala:264:29, :466:21] wire _classify_out_isQNaN_T_1 = in_in1[51]; // @[FPU.scala:264:29, :265:28, :466:21] wire _classify_out_isSNaN_T_3 = ~_classify_out_isSNaN_T_2; // @[FPU.scala:264:{27,29}] wire classify_out_isSNaN_1 = classify_out_isNaN_1 & _classify_out_isSNaN_T_3; // @[FPU.scala:263:22, :264:{24,27}] wire classify_out_isQNaN_1 = classify_out_isNaN_1 & _classify_out_isQNaN_T_1; // @[FPU.scala:263:22, :265:{24,28}] wire _classify_out_T_14 = ~classify_out_sign_2; // @[FPU.scala:253:17, :267:34] wire _classify_out_T_15 = classify_out_isInf_1 & _classify_out_T_14; // @[FPU.scala:262:27, :267:{31,34}] wire _classify_out_T_16 = ~classify_out_sign_2; // @[FPU.scala:253:17, :267:{34,53}] wire _classify_out_T_17 = classify_out_isNormal_1 & _classify_out_T_16; // @[FPU.scala:260:57, :267:{50,53}] wire _classify_out_T_18 = ~classify_out_sign_2; // @[FPU.scala:253:17, :267:34, :268:24] wire _classify_out_T_19 = classify_out_isSubnormal_1 & _classify_out_T_18; // @[FPU.scala:259:36, :268:{21,24}] wire _classify_out_T_20 = ~classify_out_sign_2; // @[FPU.scala:253:17, :267:34, :268:41] wire _classify_out_T_21 = classify_out_isZero_1 & _classify_out_T_20; // @[FPU.scala:261:23, :268:{38,41}] wire _classify_out_T_22 = classify_out_isZero_1 & classify_out_sign_2; // @[FPU.scala:253:17, :261:23, :268:55] wire _classify_out_T_23 = classify_out_isSubnormal_1 & classify_out_sign_2; // @[FPU.scala:253:17, :259:36, :269:21] wire _classify_out_T_24 = classify_out_isNormal_1 & classify_out_sign_2; // @[FPU.scala:253:17, :260:57, :269:39] wire _classify_out_T_25 = classify_out_isInf_1 & classify_out_sign_2; // @[FPU.scala:253:17, :262:27, :269:54] wire [1:0] classify_out_lo_lo_1 = {_classify_out_T_24, _classify_out_T_25}; // @[FPU.scala:267:8, :269:{39,54}] wire [1:0] classify_out_lo_hi_hi_1 = {_classify_out_T_21, _classify_out_T_22}; // @[FPU.scala:267:8, :268:{38,55}] wire [2:0] classify_out_lo_hi_1 = {classify_out_lo_hi_hi_1, _classify_out_T_23}; // @[FPU.scala:267:8, :269:21] wire [4:0] classify_out_lo_1 = {classify_out_lo_hi_1, classify_out_lo_lo_1}; // @[FPU.scala:267:8] wire [1:0] classify_out_hi_lo_1 = {_classify_out_T_17, _classify_out_T_19}; // @[FPU.scala:267:{8,50}, :268:21] wire [1:0] classify_out_hi_hi_hi_1 = {classify_out_isQNaN_1, classify_out_isSNaN_1}; // @[FPU.scala:264:24, :265:24, :267:8] wire [2:0] classify_out_hi_hi_1 = {classify_out_hi_hi_hi_1, _classify_out_T_15}; // @[FPU.scala:267:{8,31}] wire [4:0] classify_out_hi_2 = {classify_out_hi_hi_1, classify_out_hi_lo_1}; // @[FPU.scala:267:8] wire [9:0] _classify_out_T_26 = {classify_out_hi_2, classify_out_lo_1}; // @[FPU.scala:267:8] wire classify_out_truncIdx = _classify_out_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _classify_out_T_27 = classify_out_truncIdx; // @[package.scala:38:47, :39:86] wire [9:0] classify_out = _classify_out_T_27 ? _classify_out_T_26 : _classify_out_T_13; // @[package.scala:39:{76,86}] wire [31:0] _toint_T = toint_ieee[63:32]; // @[package.scala:39:76] wire [31:0] _toint_T_7 = toint_ieee[63:32]; // @[package.scala:39:76] wire [63:0] _toint_T_1 = {_toint_T, 32'h0}; // @[FPU.scala:486:{41,52}] wire [63:0] _toint_T_2 = {54'h0, classify_out} \| _toint_T_1; // @[package.scala:39:76] wire [2:0] _toint_T_3 = ~in_rm; // @[FPU.scala:466:21, :491:15] wire [1:0] _toint_T_4 = {_dcmp_io_lt, _dcmp_io_eq}; // @[FPU.scala:469:20, :491:27] wire [2:0] _toint_T_5 = {1'h0, _toint_T_3[1:0] & _toint_T_4}; // @[FPU.scala:491:{15,22,27}] wire _toint_T_6 = \|_toint_T_5; // @[FPU.scala:491:{22,53}] wire [63:0] _toint_T_8 = {_toint_T_7, 32'h0}; // @[FPU.scala:491:{71,82}] wire [63:0] _toint_T_9 = {63'h0, _toint_T_6} \| _toint_T_8; // @[FPU.scala:491:{53,57,82}] wire cvtType = in_typ[1]; // @[package.scala:163:13] assign intType = in_wflags & ~in_ren2 & cvtType; // @[package.scala:163:13] wire _conv_io_signedOut_T = in_typ[0]; // @[FPU.scala:466:21, :501:35] wire _narrow_io_signedOut_T = in_typ[0]; // @[FPU.scala:466:21, :501:35, :511:41] wire _conv_io_signedOut_T_1 = ~_conv_io_signedOut_T; // @[FPU.scala:501:{28,35}] wire [1:0] _io_out_bits_exc_T = _conv_io_intExceptionFlags[2:1]; // @[FPU.scala:498:24, :503:55] wire _io_out_bits_exc_T_1 = \|_io_out_bits_exc_T; // @[FPU.scala:503:{55,62}] wire _io_out_bits_exc_T_2 = _conv_io_intExceptionFlags[0]; // @[FPU.scala:498:24, :503:102] wire _io_out_bits_exc_T_5 = _conv_io_intExceptionFlags[0]; // @[FPU.scala:498:24, :503:102, :517:90] wire [3:0] io_out_bits_exc_hi = {_io_out_bits_exc_T_1, 3'h0}; // @[FPU.scala:503:{29,62}] wire [4:0] _io_out_bits_exc_T_3 = {io_out_bits_exc_hi, _io_out_bits_exc_T_2}; // @[FPU.scala:503:{29,102}] wire _narrow_io_signedOut_T_1 = ~_narrow_io_signedOut_T; // @[FPU.scala:511:{34,41}] wire _excSign_T_2 = &_excSign_T_1; // @[FPU.scala:249:{25,56}] wire _excSign_T_3 = ~_excSign_T_2; // @[FPU.scala:249:56, :513:62] wire excSign = _excSign_T & _excSign_T_3; // @[FPU.scala:513:{31,59,62}] wire _excOut_T = _conv_io_signedOut_T_1 == excSign; // @[FPU.scala:501:28, :513:59, :514:46] wire _excOut_T_1 = ~excSign; // @[FPU.scala:513:59, :514:69] wire [30:0] _excOut_T_2 = {31{_excOut_T_1}}; // @[FPU.scala:514:{63,69}] wire [31:0] excOut = {_excOut_T, _excOut_T_2}; // @[FPU.scala:514:{27,46,63}] wire _invalid_T = _conv_io_intExceptionFlags[2]; // @[FPU.scala:498:24, :515:50] wire _invalid_T_1 = _narrow_io_intExceptionFlags[1]; // @[FPU.scala:508:30, :515:84] wire invalid = _invalid_T \| _invalid_T_1; // @[FPU.scala:515:{50,54,84}] wire [31:0] _toint_T_10 = _conv_io_out[63:32]; // @[FPU.scala:498:24, :516:53] wire [63:0] _toint_T_11 = {_toint_T_10, excOut}; // @[FPU.scala:514:27, :516:{40,53}] assign toint = in_wflags ? (in_ren2 ? _toint_T_9 : ~cvtType & invalid ? _toint_T_11 : _conv_io_out) : in_rm[0] ? _toint_T_2 : toint_ieee; // @[package.scala:39:76, :163:13] wire _io_out_bits_exc_T_4 = ~invalid; // @[FPU.scala:515:54, :517:53] wire _io_out_bits_exc_T_6 = _io_out_bits_exc_T_4 & _io_out_bits_exc_T_5; // @[FPU.scala:517:{53,62,90}] wire [3:0] io_out_bits_exc_hi_1 = {invalid, 3'h0}; // @[FPU.scala:515:54, :517:33] wire [4:0] _io_out_bits_exc_T_7 = {io_out_bits_exc_hi_1, _io_out_bits_exc_T_6}; // @[FPU.scala:517:{33,62}] assign io_out_bits_exc = in_wflags ? (in_ren2 ? _dcmp_io_exceptionFlags : cvtType ? _io_out_bits_exc_T_3 : _io_out_bits_exc_T_7) : 5'h0; // @[package.scala:163:13] wire _io_out_bits_lt_T_1 = $signed(_io_out_bits_lt_T) < 65'sh0; // @[FPU.scala:524:{46,53}] wire _io_out_bits_lt_T_3 = $signed(_io_out_bits_lt_T_2) > -65'sh1; // @[FPU.scala:524:{72,79}] wire _io_out_bits_lt_T_4 = _io_out_bits_lt_T_1 & _io_out_bits_lt_T_3; // @[FPU.scala:524:{53,59,79}] assign _io_out_bits_lt_T_5 = _dcmp_io_lt \| _io_out_bits_lt_T_4; // @[FPU.scala:469:20, :524:{32,59}] assign io_out_bits_lt = _io_out_bits_lt_T_5; // @[FPU.scala:453:7, :524:32] always @(posedge clock) begin // @[FPU.scala:453:7] if (io_in_valid_0) begin // @[FPU.scala:453:7] in_ldst <= io_in_bits_ldst_0; // @[FPU.scala:453:7, :466:21] in_wen <= io_in_bits_wen_0; // @[FPU.scala:453:7, :466:21] in_ren1 <= io_in_bits_ren1_0; // @[FPU.scala:453:7, :466:21] in_ren2 <= io_in_bits_ren2_0; // @[FPU.scala:453:7, :466:21] in_ren3 <= io_in_bits_ren3_0; // @[FPU.scala:453:7, :466:21] in_swap12 <= io_in_bits_swap12_0; // @[FPU.scala:453:7, :466:21] in_swap23 <= io_in_bits_swap23_0; // @[FPU.scala:453:7, :466:21] in_typeTagIn <= io_in_bits_typeTagIn_0; // @[FPU.scala:453:7, :466:21] in_typeTagOut <= io_in_bits_typeTagOut_0; // @[FPU.scala:453:7, :466:21] in_fromint <= io_in_bits_fromint_0; // @[FPU.scala:453:7, :466:21] in_toint <= io_in_bits_toint_0; // @[FPU.scala:453:7, :466:21] in_fastpipe <= io_in_bits_fastpipe_0; // @[FPU.scala:453:7, :466:21] in_fma <= io_in_bits_fma_0; // @[FPU.scala:453:7, :466:21] in_div <= io_in_bits_div_0; // @[FPU.scala:453:7, :466:21] in_sqrt <= io_in_bits_sqrt_0; // @[FPU.scala:453:7, :466:21] in_wflags <= io_in_bits_wflags_0; // @[FPU.scala:453:7, :466:21] in_vec <= io_in_bits_vec_0; // @[FPU.scala:453:7, :466:21] in_rm <= io_in_bits_rm_0; // @[FPU.scala:453:7, :466:21] in_typ <= io_in_bits_typ_0; // @[FPU.scala:453:7, :466:21] in_in1 <= io_in_bits_in1_0; // @[FPU.scala:453:7, :466:21] in_in2 <= io_in_bits_in2_0; // @[FPU.scala:453:7, :466:21] end valid <= io_in_valid_0; // @[FPU.scala:453:7, :467:22] always @(posedge) CompareRecFN_1 dcmp ( // @[FPU.scala:469:20] .io_a (in_in1), // @[FPU.scala:466:21] .io_b (in_in2), // @[FPU.scala:466:21] .io_signaling (_dcmp_io_signaling_T_1), // @[FPU.scala:472:24] .io_lt (_dcmp_io_lt), .io_eq (_dcmp_io_eq), .io_exceptionFlags (_dcmp_io_exceptionFlags) ); // @[FPU.scala:469:20] RecFNToIN_e11_s53_i64_1 conv ( // @[FPU.scala:498:24] .clock (clock), .reset (reset), .io_in (in_in1), // @[FPU.scala:466:21] .io_roundingMode (in_rm), // @[FPU.scala:466:21] .io_signedOut (_conv_io_signedOut_T_1), // @[FPU.scala:501:28] .io_out (_conv_io_out), .io_intExceptionFlags (_conv_io_intExceptionFlags) ); // @[FPU.scala:498:24] RecFNToIN_e11_s53_i32_1 narrow ( // @[FPU.scala:508:30] .clock (clock), .reset (reset), .io_in (in_in1), // @[FPU.scala:466:21] .io_roundingMode (in_rm), // @[FPU.scala:466:21] .io_signedOut (_narrow_io_signedOut_T_1), // @[FPU.scala:511:34] .io_intExceptionFlags (_narrow_io_intExceptionFlags) ); // @[FPU.scala:508:30] assign io_out_bits_in_rm = io_out_bits_in_rm_0; // @[FPU.scala:453:7] assign io_out_bits_in_in1 = io_out_bits_in_in1_0; // @[FPU.scala:453:7] assign io_out_bits_in_in2 = io_out_bits_in_in2_0; // @[FPU.scala:453:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Decode.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.BitPat import chisel3.util.experimental.decode._ object DecodeLogic { // TODO This should be a method on BitPat private def hasDontCare(bp: BitPat): Boolean = bp.mask.bitCount != bp.width // Pads BitPats that are safe to pad (no don't cares), errors otherwise private def padBP(bp: BitPat, width: Int): BitPat = { if (bp.width == width) bp else { require(!hasDontCare(bp), s"Cannot pad '$bp' to '$width' bits because it has don't cares") val diff = width - bp.width require(diff > 0, s"Cannot pad '$bp' to '$width' because it is already '${bp.width}' bits wide!") BitPat(0.U(diff.W)) ## bp } } def apply(addr: UInt, default: BitPat, mapping: Iterable[(BitPat, BitPat)]): UInt = chisel3.util.experimental.decode.decoder(QMCMinimizer, addr, TruthTable(mapping, default)) def apply(addr: UInt, default: Seq[BitPat], mappingIn: Iterable[(BitPat, Seq[BitPat])]): Seq[UInt] = { val nElts = default.size require(mappingIn.forall(_._2.size == nElts), s"All Seq[BitPat] must be of the same length, got $nElts vs. ${mappingIn.find(_._2.size != nElts).get}" ) val elementsGrouped = mappingIn.map(_._2).transpose val elementWidths = elementsGrouped.zip(default).map { case (elts, default) => (default :: elts.toList).map(_.getWidth).max } val resultWidth = elementWidths.sum val elementIndices = elementWidths.scan(resultWidth - 1) { case (l, r) => l - r } // All BitPats that correspond to a given element in the result must have the same width in the // chisel3 decoder. We will zero pad any BitPats that are too small so long as they dont have // any don't cares. If there are don't cares, it is an error and the user needs to pad the // BitPat themselves val defaultsPadded = default.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } val mappingInPadded = mappingIn.map { case (in, elts) => in -> elts.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } } val decoded = apply(addr, defaultsPadded.reduce(_ ## _), mappingInPadded.map { case (in, out) => (in, out.reduce(_ ## _)) }) elementIndices.zip(elementIndices.tail).map { case (msb, lsb) => decoded(msb, lsb + 1) }.toList } def apply(addr: UInt, default: Seq[BitPat], mappingIn: List[(UInt, Seq[BitPat])]): Seq[UInt] = apply(addr, default, mappingIn.map(m => (BitPat(m._1), m._2)).asInstanceOf[Iterable[(BitPat, Seq[BitPat])]]) def apply(addr: UInt, trues: Iterable[UInt], falses: Iterable[UInt]): Bool = apply(addr, BitPat.dontCare(1), trues.map(BitPat(_) -> BitPat("b1")) ++ falses.map(BitPat(_) -> BitPat("b0"))).asBool } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File CustomCSRs.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import org.chipsalliance.cde.config.Parameters case class CustomCSR(id: Int, mask: BigInt, init: Option[BigInt]) object CustomCSR { def constant(id: Int, value: BigInt): CustomCSR = CustomCSR(id, BigInt(0), Some(value)) } class CustomCSRIO(implicit p: Parameters) extends CoreBundle { val ren = Output(Bool()) // set by CSRFile, indicates an instruction is reading the CSR val wen = Output(Bool()) // set by CSRFile, indicates an instruction is writing the CSR val wdata = Output(UInt(xLen.W)) // wdata provided by instruction writing CSR val value = Output(UInt(xLen.W)) // current value of CSR in CSRFile val stall = Input(Bool()) // reads and writes to this CSR should stall (must be bounded) val set = Input(Bool()) // set/sdata enables external agents to set the value of this CSR val sdata = Input(UInt(xLen.W)) } class CustomCSRs(implicit p: Parameters) extends CoreBundle { // Not all cores have these CSRs, but those that do should follow the same // numbering conventions. So we list them here but default them to None. protected def bpmCSRId = 0x7c0 protected def bpmCSR: Option[CustomCSR] = None protected def chickenCSRId = 0x7c1 protected def chickenCSR: Option[CustomCSR] = None // If you override this, you'll want to concatenate super.decls def decls: Seq[CustomCSR] = bpmCSR.toSeq ++ chickenCSR val csrs = Vec(decls.size, new CustomCSRIO) def flushBTB = getOrElse(bpmCSR, _.wen, false.B) def bpmStatic = getOrElse(bpmCSR, _.value(0), false.B) def disableDCacheClockGate = getOrElse(chickenCSR, _.value(0), false.B) def disableICacheClockGate = getOrElse(chickenCSR, _.value(1), false.B) def disableCoreClockGate = getOrElse(chickenCSR, _.value(2), false.B) def disableSpeculativeICacheRefill = getOrElse(chickenCSR, _.value(3), false.B) def suppressCorruptOnGrantData = getOrElse(chickenCSR, _.value(9), false.B) protected def getByIdOrElse[T](id: Int, f: CustomCSRIO => T, alt: T): T = { val idx = decls.indexWhere(_.id == id) if (idx < 0) alt else f(csrs(idx)) } protected def getOrElse[T](csr: Option[CustomCSR], f: CustomCSRIO => T, alt: T): T = csr.map(c => getByIdOrElse(c.id, f, alt)).getOrElse(alt) } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) \|\| isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR \|\| cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) \|\| isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR \|\| cmd === M_PWR \|\| cmd === M_XSC \|\| isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) \|\| cmd === M_PFW \|\| cmd === M_XLR } File Events.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.log2Ceil import freechips.rocketchip.util._ import freechips.rocketchip.util.property class EventSet(val gate: (UInt, UInt) => Bool, val events: Seq[(String, () => Bool)]) { def size = events.size val hits = WireDefault(VecInit(Seq.fill(size)(false.B))) def check(mask: UInt) = { hits := events.map(_._2()) gate(mask, hits.asUInt) } def dump(): Unit = { for (((name, _), i) <- events.zipWithIndex) when (check(1.U << i)) { printf(s"Event $name\n") } } def withCovers: Unit = { events.zipWithIndex.foreach { case ((name, func), i) => property.cover(gate((1.U << i), (func() << i)), name) } } } class EventSets(val eventSets: Seq[EventSet]) { def maskEventSelector(eventSel: UInt): UInt = { // allow full associativity between counters and event sets (for now?) val setMask = (BigInt(1) << eventSetIdBits) - 1 val maskMask = ((BigInt(1) << eventSets.map(_.size).max) - 1) << maxEventSetIdBits eventSel & (setMask \| maskMask).U } private def decode(counter: UInt): (UInt, UInt) = { require(eventSets.size <= (1 << maxEventSetIdBits)) require(eventSetIdBits > 0) (counter(eventSetIdBits-1, 0), counter >> maxEventSetIdBits) } def evaluate(eventSel: UInt): Bool = { val (set, mask) = decode(eventSel) val sets = for (e <- eventSets) yield { require(e.hits.getWidth <= mask.getWidth, s"too many events ${e.hits.getWidth} wider than mask ${mask.getWidth}") e check mask } sets(set) } def cover() = eventSets.foreach { _.withCovers } private def eventSetIdBits = log2Ceil(eventSets.size) private def maxEventSetIdBits = 8 require(eventSetIdBits <= maxEventSetIdBits) } class SuperscalarEventSets(val eventSets: Seq[(Seq[EventSet], (UInt, UInt) => UInt)]) { def evaluate(eventSel: UInt): UInt = { val (set, mask) = decode(eventSel) val sets = for ((sets, reducer) <- eventSets) yield { sets.map { set => require(set.hits.getWidth <= mask.getWidth, s"too many events ${set.hits.getWidth} wider than mask ${mask.getWidth}") set.check(mask) }.reduce(reducer) } val zeroPadded = sets.padTo(1 << eventSetIdBits, 0.U) zeroPadded(set) } def toScalarEventSets: EventSets = new EventSets(eventSets.map(_._1.head)) def cover(): Unit = { eventSets.foreach(_._1.foreach(_.withCovers)) } private def decode(counter: UInt): (UInt, UInt) = { require(eventSets.size <= (1 << maxEventSetIdBits)) require(eventSetIdBits > 0) (counter(eventSetIdBits-1, 0), counter >> maxEventSetIdBits) } private def eventSetIdBits = log2Ceil(eventSets.size) private def maxEventSetIdBits = 8 require(eventSets.forall(s => s._1.forall(_.size == s._1.head.size))) require(eventSetIdBits <= maxEventSetIdBits) } File RocketCore.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.withClock import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ArrayBuffer case class RocketCoreParams( xLen: Int = 64, pgLevels: Int = 3, // sv39 default bootFreqHz: BigInt = 0, useVM: Boolean = true, useUser: Boolean = false, useSupervisor: Boolean = false, useHypervisor: Boolean = false, useDebug: Boolean = true, useAtomics: Boolean = true, useAtomicsOnlyForIO: Boolean = false, useCompressed: Boolean = true, useRVE: Boolean = false, useConditionalZero: Boolean = false, useZba: Boolean = false, useZbb: Boolean = false, useZbs: Boolean = false, nLocalInterrupts: Int = 0, useNMI: Boolean = false, nBreakpoints: Int = 1, useBPWatch: Boolean = false, mcontextWidth: Int = 0, scontextWidth: Int = 0, nPMPs: Int = 8, nPerfCounters: Int = 0, haveBasicCounters: Boolean = true, haveCFlush: Boolean = false, misaWritable: Boolean = true, nL2TLBEntries: Int = 0, nL2TLBWays: Int = 1, nPTECacheEntries: Int = 8, mtvecInit: Option[BigInt] = Some(BigInt(0)), mtvecWritable: Boolean = true, fastLoadWord: Boolean = true, fastLoadByte: Boolean = false, branchPredictionModeCSR: Boolean = false, clockGate: Boolean = false, mvendorid: Int = 0, // 0 means non-commercial implementation mimpid: Int = 0x20181004, // release date in BCD mulDiv: Option[MulDivParams] = Some(MulDivParams()), fpu: Option[FPUParams] = Some(FPUParams()), debugROB: Option[DebugROBParams] = None, // if size < 1, SW ROB, else HW ROB haveCease: Boolean = true, // non-standard CEASE instruction haveSimTimeout: Boolean = true, // add plusarg for simulation timeout vector: Option[RocketCoreVectorParams] = None ) extends CoreParams { val lgPauseCycles = 5 val haveFSDirty = false val pmpGranularity: Int = if (useHypervisor) 4096 else 4 val fetchWidth: Int = if (useCompressed) 2 else 1 // fetchWidth doubled, but coreInstBytes halved, for RVC: val decodeWidth: Int = fetchWidth / (if (useCompressed) 2 else 1) val retireWidth: Int = 1 val instBits: Int = if (useCompressed) 16 else 32 val lrscCycles: Int = 80 // worst case is 14 mispredicted branches + slop val traceHasWdata: Boolean = debugROB.isDefined // ooo wb, so no wdata in trace override val useVector = vector.isDefined override val vectorUseDCache = vector.map(_.useDCache).getOrElse(false) override def vLen = vector.map(_.vLen).getOrElse(0) override def eLen = vector.map(_.eLen).getOrElse(0) override def vfLen = vector.map(_.vfLen).getOrElse(0) override def vfh = vector.map(_.vfh).getOrElse(false) override def vExts = vector.map(_.vExts).getOrElse(Nil) override def vMemDataBits = vector.map(_.vMemDataBits).getOrElse(0) override val customIsaExt = Option.when(haveCease)("xrocket") // CEASE instruction override def minFLen: Int = fpu.map(_.minFLen).getOrElse(32) override def customCSRs(implicit p: Parameters) = new RocketCustomCSRs } trait HasRocketCoreParameters extends HasCoreParameters { lazy val rocketParams: RocketCoreParams = tileParams.core.asInstanceOf[RocketCoreParams] val fastLoadWord = rocketParams.fastLoadWord val fastLoadByte = rocketParams.fastLoadByte val mulDivParams = rocketParams.mulDiv.getOrElse(MulDivParams()) // TODO ask andrew about this require(!fastLoadByte \|\| fastLoadWord) require(!rocketParams.haveFSDirty, "rocket doesn't support setting fs dirty from outside, please disable haveFSDirty") } class RocketCustomCSRs(implicit p: Parameters) extends CustomCSRs with HasRocketCoreParameters { override def bpmCSR = { rocketParams.branchPredictionModeCSR.option(CustomCSR(bpmCSRId, BigInt(1), Some(BigInt(0)))) } private def haveDCache = tileParams.dcache.get.scratch.isEmpty override def chickenCSR = { val mask = BigInt( tileParams.dcache.get.clockGate.toInt << 0 \| rocketParams.clockGate.toInt << 1 \| rocketParams.clockGate.toInt << 2 \| 1 << 3 \| // disableSpeculativeICacheRefill haveDCache.toInt << 9 \| // suppressCorruptOnGrantData tileParams.icache.get.prefetch.toInt << 17 ) Some(CustomCSR(chickenCSRId, mask, Some(mask))) } def disableICachePrefetch = getOrElse(chickenCSR, _.value(17), true.B) def marchid = CustomCSR.constant(CSRs.marchid, BigInt(1)) def mvendorid = CustomCSR.constant(CSRs.mvendorid, BigInt(rocketParams.mvendorid)) // mimpid encodes a release version in the form of a BCD-encoded datestamp. def mimpid = CustomCSR.constant(CSRs.mimpid, BigInt(rocketParams.mimpid)) override def decls = super.decls :+ marchid :+ mvendorid :+ mimpid } class CoreInterrupts(val hasBeu: Boolean)(implicit p: Parameters) extends TileInterrupts()(p) { val buserror = Option.when(hasBeu)(Bool()) } trait HasRocketCoreIO extends HasRocketCoreParameters { implicit val p: Parameters def nTotalRoCCCSRs: Int val io = IO(new CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val reset_vector = Input(UInt(resetVectorLen.W)) val interrupts = Input(new CoreInterrupts(tileParams.asInstanceOf[RocketTileParams].beuAddr.isDefined)) val imem = new FrontendIO val dmem = new HellaCacheIO val ptw = Flipped(new DatapathPTWIO()) val fpu = Flipped(new FPUCoreIO()) val rocc = Flipped(new RoCCCoreIO(nTotalRoCCCSRs)) val trace = Output(new TraceBundle) val bpwatch = Output(Vec(coreParams.nBreakpoints, new BPWatch(coreParams.retireWidth))) val cease = Output(Bool()) val wfi = Output(Bool()) val traceStall = Input(Bool()) val vector = if (usingVector) Some(Flipped(new VectorCoreIO)) else None }) } class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p) with HasRocketCoreParameters with HasRocketCoreIO { def nTotalRoCCCSRs = tile.roccCSRs.flatten.size import ALU._ val clock_en_reg = RegInit(true.B) val long_latency_stall = Reg(Bool()) val id_reg_pause = Reg(Bool()) val imem_might_request_reg = Reg(Bool()) val clock_en = WireDefault(true.B) val gated_clock = if (!rocketParams.clockGate) clock else ClockGate(clock, clock_en, "rocket_clock_gate") class RocketImpl { // entering gated-clock domain // performance counters def pipelineIDToWB[T <: Data](x: T): T = RegEnable(RegEnable(RegEnable(x, !ctrl_killd), ex_pc_valid), mem_pc_valid) val perfEvents = new EventSets(Seq( new EventSet((mask, hits) => Mux(wb_xcpt, mask(0), wb_valid && pipelineIDToWB((mask & hits).orR)), Seq( ("exception", () => false.B), ("load", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XRD && !id_ctrl.fp), ("store", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XWR && !id_ctrl.fp), ("amo", () => usingAtomics.B && id_ctrl.mem && (isAMO(id_ctrl.mem_cmd) \|\| id_ctrl.mem_cmd.isOneOf(M_XLR, M_XSC))), ("system", () => id_ctrl.csr =/= CSR.N), ("arith", () => id_ctrl.wxd && !(id_ctrl.jal \|\| id_ctrl.jalr \|\| id_ctrl.mem \|\| id_ctrl.fp \|\| id_ctrl.mul \|\| id_ctrl.div \|\| id_ctrl.csr =/= CSR.N)), ("branch", () => id_ctrl.branch), ("jal", () => id_ctrl.jal), ("jalr", () => id_ctrl.jalr)) ++ (if (!usingMulDiv) Seq() else Seq( ("mul", () => if (pipelinedMul) id_ctrl.mul else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) =/= FN_DIV), ("div", () => if (pipelinedMul) id_ctrl.div else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) === FN_DIV))) ++ (if (!usingFPU) Seq() else Seq( ("fp load", () => id_ctrl.fp && io.fpu.dec.ldst && io.fpu.dec.wen), ("fp store", () => id_ctrl.fp && io.fpu.dec.ldst && !io.fpu.dec.wen), ("fp add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.swap23), ("fp mul", () => id_ctrl.fp && io.fpu.dec.fma && !io.fpu.dec.swap23 && !io.fpu.dec.ren3), ("fp mul-add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.ren3), ("fp div/sqrt", () => id_ctrl.fp && (io.fpu.dec.div \|\| io.fpu.dec.sqrt)), ("fp other", () => id_ctrl.fp && !(io.fpu.dec.ldst \|\| io.fpu.dec.fma \|\| io.fpu.dec.div \|\| io.fpu.dec.sqrt))))), new EventSet((mask, hits) => (mask & hits).orR, Seq( ("load-use interlock", () => id_ex_hazard && ex_ctrl.mem \|\| id_mem_hazard && mem_ctrl.mem \|\| id_wb_hazard && wb_ctrl.mem), ("long-latency interlock", () => id_sboard_hazard), ("csr interlock", () => id_ex_hazard && ex_ctrl.csr =/= CSR.N \|\| id_mem_hazard && mem_ctrl.csr =/= CSR.N \|\| id_wb_hazard && wb_ctrl.csr =/= CSR.N), ("I$ blocked", () => icache_blocked), ("D$ blocked", () => id_ctrl.mem && dcache_blocked), ("branch misprediction", () => take_pc_mem && mem_direction_misprediction), ("control-flow target misprediction", () => take_pc_mem && mem_misprediction && mem_cfi && !mem_direction_misprediction && !icache_blocked), ("flush", () => wb_reg_flush_pipe), ("replay", () => replay_wb)) ++ (if (!usingMulDiv) Seq() else Seq( ("mul/div interlock", () => id_ex_hazard && (ex_ctrl.mul \|\| ex_ctrl.div) \|\| id_mem_hazard && (mem_ctrl.mul \|\| mem_ctrl.div) \|\| id_wb_hazard && wb_ctrl.div))) ++ (if (!usingFPU) Seq() else Seq( ("fp interlock", () => id_ex_hazard && ex_ctrl.fp \|\| id_mem_hazard && mem_ctrl.fp \|\| id_wb_hazard && wb_ctrl.fp \|\| id_ctrl.fp && id_stall_fpu)))), new EventSet((mask, hits) => (mask & hits).orR, Seq( ("I$ miss", () => io.imem.perf.acquire), ("D$ miss", () => io.dmem.perf.acquire), ("D$ release", () => io.dmem.perf.release), ("ITLB miss", () => io.imem.perf.tlbMiss), ("DTLB miss", () => io.dmem.perf.tlbMiss), ("L2 TLB miss", () => io.ptw.perf.l2miss))))) val pipelinedMul = usingMulDiv && mulDivParams.mulUnroll == xLen val decode_table = { (if (usingMulDiv) new MDecode(pipelinedMul) +: (xLen > 32).option(new M64Decode(pipelinedMul)).toSeq else Nil) ++: (if (usingAtomics) new ADecode +: (xLen > 32).option(new A64Decode).toSeq else Nil) ++: (if (fLen >= 32) new FDecode +: (xLen > 32).option(new F64Decode).toSeq else Nil) ++: (if (fLen >= 64) new DDecode +: (xLen > 32).option(new D64Decode).toSeq else Nil) ++: (if (minFLen == 16) new HDecode +: (xLen > 32).option(new H64Decode).toSeq ++: (fLen >= 64).option(new HDDecode).toSeq else Nil) ++: (usingRoCC.option(new RoCCDecode)) ++: (if (xLen == 32) new I32Decode else new I64Decode) +: (usingVM.option(new SVMDecode)) ++: (usingSupervisor.option(new SDecode)) ++: (usingHypervisor.option(new HypervisorDecode)) ++: ((usingHypervisor && (xLen == 64)).option(new Hypervisor64Decode)) ++: (usingDebug.option(new DebugDecode)) ++: (usingNMI.option(new NMIDecode)) ++: (usingConditionalZero.option(new ConditionalZeroDecode)) ++: Seq(new FenceIDecode(tile.dcache.flushOnFenceI)) ++: coreParams.haveCFlush.option(new CFlushDecode(tile.dcache.canSupportCFlushLine)) ++: rocketParams.haveCease.option(new CeaseDecode) ++: usingVector.option(new VCFGDecode) ++: (if (coreParams.useZba) new ZbaDecode +: (xLen > 32).option(new Zba64Decode).toSeq else Nil) ++: (if (coreParams.useZbb) Seq(new ZbbDecode, if (xLen == 32) new Zbb32Decode else new Zbb64Decode) else Nil) ++: coreParams.useZbs.option(new ZbsDecode) ++: Seq(new IDecode) } flatMap(_.table) val ex_ctrl = Reg(new IntCtrlSigs) val mem_ctrl = Reg(new IntCtrlSigs) val wb_ctrl = Reg(new IntCtrlSigs) val ex_reg_xcpt_interrupt = Reg(Bool()) val ex_reg_valid = Reg(Bool()) val ex_reg_rvc = Reg(Bool()) val ex_reg_btb_resp = Reg(new BTBResp) val ex_reg_xcpt = Reg(Bool()) val ex_reg_flush_pipe = Reg(Bool()) val ex_reg_load_use = Reg(Bool()) val ex_reg_cause = Reg(UInt()) val ex_reg_replay = Reg(Bool()) val ex_reg_pc = Reg(UInt()) val ex_reg_mem_size = Reg(UInt()) val ex_reg_hls = Reg(Bool()) val ex_reg_inst = Reg(Bits()) val ex_reg_raw_inst = Reg(UInt()) val ex_reg_wphit = Reg(Vec(nBreakpoints, Bool())) val ex_reg_set_vconfig = Reg(Bool()) val mem_reg_xcpt_interrupt = Reg(Bool()) val mem_reg_valid = Reg(Bool()) val mem_reg_rvc = Reg(Bool()) val mem_reg_btb_resp = Reg(new BTBResp) val mem_reg_xcpt = Reg(Bool()) val mem_reg_replay = Reg(Bool()) val mem_reg_flush_pipe = Reg(Bool()) val mem_reg_cause = Reg(UInt()) val mem_reg_slow_bypass = Reg(Bool()) val mem_reg_load = Reg(Bool()) val mem_reg_store = Reg(Bool()) val mem_reg_set_vconfig = Reg(Bool()) val mem_reg_sfence = Reg(Bool()) val mem_reg_pc = Reg(UInt()) val mem_reg_inst = Reg(Bits()) val mem_reg_mem_size = Reg(UInt()) val mem_reg_hls_or_dv = Reg(Bool()) val mem_reg_raw_inst = Reg(UInt()) val mem_reg_wdata = Reg(Bits()) val mem_reg_rs2 = Reg(Bits()) val mem_br_taken = Reg(Bool()) val take_pc_mem = Wire(Bool()) val mem_reg_wphit = Reg(Vec(nBreakpoints, Bool())) val wb_reg_valid = Reg(Bool()) val wb_reg_xcpt = Reg(Bool()) val wb_reg_replay = Reg(Bool()) val wb_reg_flush_pipe = Reg(Bool()) val wb_reg_cause = Reg(UInt()) val wb_reg_set_vconfig = Reg(Bool()) val wb_reg_sfence = Reg(Bool()) val wb_reg_pc = Reg(UInt()) val wb_reg_mem_size = Reg(UInt()) val wb_reg_hls_or_dv = Reg(Bool()) val wb_reg_hfence_v = Reg(Bool()) val wb_reg_hfence_g = Reg(Bool()) val wb_reg_inst = Reg(Bits()) val wb_reg_raw_inst = Reg(UInt()) val wb_reg_wdata = Reg(Bits()) val wb_reg_rs2 = Reg(Bits()) val take_pc_wb = Wire(Bool()) val wb_reg_wphit = Reg(Vec(nBreakpoints, Bool())) val take_pc_mem_wb = take_pc_wb \|\| take_pc_mem val take_pc = take_pc_mem_wb // decode stage val ibuf = Module(new IBuf) val id_expanded_inst = ibuf.io.inst.map(_.bits.inst) val id_raw_inst = ibuf.io.inst.map(_.bits.raw) val id_inst = id_expanded_inst.map(_.bits) ibuf.io.imem <> io.imem.resp ibuf.io.kill := take_pc require(decodeWidth == 1 / TODO / && retireWidth == decodeWidth) require(!(coreParams.useRVE && coreParams.fpu.nonEmpty), "Can't select both RVE and floating-point") require(!(coreParams.useRVE && coreParams.useHypervisor), "Can't select both RVE and Hypervisor") val id_ctrl = Wire(new IntCtrlSigs).decode(id_inst(0), decode_table) val lgNXRegs = if (coreParams.useRVE) 4 else 5 val regAddrMask = (1 << lgNXRegs) - 1 def decodeReg(x: UInt) = (x.extract(x.getWidth-1, lgNXRegs).asBool, x(lgNXRegs-1, 0)) val (id_raddr3_illegal, id_raddr3) = decodeReg(id_expanded_inst(0).rs3) val (id_raddr2_illegal, id_raddr2) = decodeReg(id_expanded_inst(0).rs2) val (id_raddr1_illegal, id_raddr1) = decodeReg(id_expanded_inst(0).rs1) val (id_waddr_illegal, id_waddr) = decodeReg(id_expanded_inst(0).rd) val id_load_use = Wire(Bool()) val id_reg_fence = RegInit(false.B) val id_ren = IndexedSeq(id_ctrl.rxs1, id_ctrl.rxs2) val id_raddr = IndexedSeq(id_raddr1, id_raddr2) val rf = new RegFile(regAddrMask, xLen) val id_rs = id_raddr.map(rf.read _) val ctrl_killd = Wire(Bool()) val id_npc = (ibuf.io.pc.asSInt + ImmGen(IMM_UJ, id_inst(0))).asUInt val csr = Module(new CSRFile(perfEvents, coreParams.customCSRs.decls, tile.roccCSRs.flatten, tile.rocketParams.beuAddr.isDefined)) val id_csr_en = id_ctrl.csr.isOneOf(CSR.S, CSR.C, CSR.W) val id_system_insn = id_ctrl.csr === CSR.I val id_csr_ren = id_ctrl.csr.isOneOf(CSR.S, CSR.C) && id_expanded_inst(0).rs1 === 0.U val id_csr = Mux(id_system_insn && id_ctrl.mem, CSR.N, Mux(id_csr_ren, CSR.R, id_ctrl.csr)) val id_csr_flush = id_system_insn \|\| (id_csr_en && !id_csr_ren && csr.io.decode(0).write_flush) val id_set_vconfig = Seq(Instructions.VSETVLI, Instructions.VSETIVLI, Instructions.VSETVL).map(_ === id_inst(0)).orR && usingVector.B id_ctrl.vec := false.B if (usingVector) { val v_decode = rocketParams.vector.get.decoder(p) v_decode.io.inst := id_inst(0) v_decode.io.vconfig := csr.io.vector.get.vconfig when (v_decode.io.legal) { id_ctrl.legal := !csr.io.vector.get.vconfig.vtype.vill id_ctrl.fp := v_decode.io.fp id_ctrl.rocc := false.B id_ctrl.branch := false.B id_ctrl.jal := false.B id_ctrl.jalr := false.B id_ctrl.rxs2 := v_decode.io.read_rs2 id_ctrl.rxs1 := v_decode.io.read_rs1 id_ctrl.mem := false.B id_ctrl.rfs1 := v_decode.io.read_frs1 id_ctrl.rfs2 := false.B id_ctrl.rfs3 := false.B id_ctrl.wfd := v_decode.io.write_frd id_ctrl.mul := false.B id_ctrl.div := false.B id_ctrl.wxd := v_decode.io.write_rd id_ctrl.csr := CSR.N id_ctrl.fence_i := false.B id_ctrl.fence := false.B id_ctrl.amo := false.B id_ctrl.dp := false.B id_ctrl.vec := true.B } } val id_illegal_insn = !id_ctrl.legal \|\| (id_ctrl.mul \|\| id_ctrl.div) && !csr.io.status.isa('m'-'a') \|\| id_ctrl.amo && !csr.io.status.isa('a'-'a') \|\| id_ctrl.fp && (csr.io.decode(0).fp_illegal \|\| (io.fpu.illegal_rm && !id_ctrl.vec)) \|\| (id_ctrl.vec) && (csr.io.decode(0).vector_illegal \|\| csr.io.vector.map(_.vconfig.vtype.vill).getOrElse(false.B)) \|\| id_ctrl.dp && !csr.io.status.isa('d'-'a') \|\| ibuf.io.inst(0).bits.rvc && !csr.io.status.isa('c'-'a') \|\| id_raddr2_illegal && id_ctrl.rxs2 \|\| id_raddr1_illegal && id_ctrl.rxs1 \|\| id_waddr_illegal && id_ctrl.wxd \|\| id_ctrl.rocc && csr.io.decode(0).rocc_illegal \|\| id_csr_en && (csr.io.decode(0).read_illegal \|\| !id_csr_ren && csr.io.decode(0).write_illegal) \|\| !ibuf.io.inst(0).bits.rvc && (id_system_insn && csr.io.decode(0).system_illegal) val id_virtual_insn = id_ctrl.legal && ((id_csr_en && !(!id_csr_ren && csr.io.decode(0).write_illegal) && csr.io.decode(0).virtual_access_illegal) \|\| (!ibuf.io.inst(0).bits.rvc && id_system_insn && csr.io.decode(0).virtual_system_illegal)) // stall decode for fences (now, for AMO.rl; later, for AMO.aq and FENCE) val id_amo_aq = id_inst(0)(26) val id_amo_rl = id_inst(0)(25) val id_fence_pred = id_inst(0)(27,24) val id_fence_succ = id_inst(0)(23,20) val id_fence_next = id_ctrl.fence \|\| id_ctrl.amo && id_amo_aq val id_mem_busy = !io.dmem.ordered \|\| io.dmem.req.valid when (!id_mem_busy) { id_reg_fence := false.B } val id_rocc_busy = usingRoCC.B && (io.rocc.busy \|\| ex_reg_valid && ex_ctrl.rocc \|\| mem_reg_valid && mem_ctrl.rocc \|\| wb_reg_valid && wb_ctrl.rocc) val id_csr_rocc_write = tile.roccCSRs.flatten.map(_.id.U === id_inst(0)(31,20)).orR && id_csr_en && !id_csr_ren val id_vec_busy = io.vector.map(v => v.backend_busy \|\| v.trap_check_busy).getOrElse(false.B) val id_do_fence = WireDefault(id_rocc_busy && (id_ctrl.fence \|\| id_csr_rocc_write) \|\| id_vec_busy && id_ctrl.fence \|\| id_mem_busy && (id_ctrl.amo && id_amo_rl \|\| id_ctrl.fence_i \|\| id_reg_fence && (id_ctrl.mem \|\| id_ctrl.rocc))) val bpu = Module(new BreakpointUnit(nBreakpoints)) bpu.io.status := csr.io.status bpu.io.bp := csr.io.bp bpu.io.pc := ibuf.io.pc bpu.io.ea := mem_reg_wdata bpu.io.mcontext := csr.io.mcontext bpu.io.scontext := csr.io.scontext val id_xcpt0 = ibuf.io.inst(0).bits.xcpt0 val id_xcpt1 = ibuf.io.inst(0).bits.xcpt1 val (id_xcpt, id_cause) = checkExceptions(List( (csr.io.interrupt, csr.io.interrupt_cause), (bpu.io.debug_if, CSR.debugTriggerCause.U), (bpu.io.xcpt_if, Causes.breakpoint.U), (id_xcpt0.pf.inst, Causes.fetch_page_fault.U), (id_xcpt0.gf.inst, Causes.fetch_guest_page_fault.U), (id_xcpt0.ae.inst, Causes.fetch_access.U), (id_xcpt1.pf.inst, Causes.fetch_page_fault.U), (id_xcpt1.gf.inst, Causes.fetch_guest_page_fault.U), (id_xcpt1.ae.inst, Causes.fetch_access.U), (id_virtual_insn, Causes.virtual_instruction.U), (id_illegal_insn, Causes.illegal_instruction.U))) val idCoverCauses = List( (CSR.debugTriggerCause, "DEBUG_TRIGGER"), (Causes.breakpoint, "BREAKPOINT"), (Causes.fetch_access, "FETCH_ACCESS"), (Causes.illegal_instruction, "ILLEGAL_INSTRUCTION") ) ++ (if (usingVM) List( (Causes.fetch_page_fault, "FETCH_PAGE_FAULT") ) else Nil) coverExceptions(id_xcpt, id_cause, "DECODE", idCoverCauses) val dcache_bypass_data = if (fastLoadByte) io.dmem.resp.bits.data(xLen-1, 0) else if (fastLoadWord) io.dmem.resp.bits.data_word_bypass(xLen-1, 0) else wb_reg_wdata // detect bypass opportunities val ex_waddr = ex_reg_inst(11,7) & regAddrMask.U val mem_waddr = mem_reg_inst(11,7) & regAddrMask.U val wb_waddr = wb_reg_inst(11,7) & regAddrMask.U val bypass_sources = IndexedSeq( (true.B, 0.U, 0.U), // treat reading x0 as a bypass (ex_reg_valid && ex_ctrl.wxd, ex_waddr, mem_reg_wdata), (mem_reg_valid && mem_ctrl.wxd && !mem_ctrl.mem, mem_waddr, wb_reg_wdata), (mem_reg_valid && mem_ctrl.wxd, mem_waddr, dcache_bypass_data)) val id_bypass_src = id_raddr.map(raddr => bypass_sources.map(s => s._1 && s._2 === raddr)) // execute stage val bypass_mux = bypass_sources.map(_._3) val ex_reg_rs_bypass = Reg(Vec(id_raddr.size, Bool())) val ex_reg_rs_lsb = Reg(Vec(id_raddr.size, UInt(log2Ceil(bypass_sources.size).W))) val ex_reg_rs_msb = Reg(Vec(id_raddr.size, UInt())) val ex_rs = for (i <- 0 until id_raddr.size) yield Mux(ex_reg_rs_bypass(i), bypass_mux(ex_reg_rs_lsb(i)), Cat(ex_reg_rs_msb(i), ex_reg_rs_lsb(i))) val ex_imm = ImmGen(ex_ctrl.sel_imm, ex_reg_inst) val ex_rs1shl = Mux(ex_reg_inst(3), ex_rs(0)(31,0), ex_rs(0)) << ex_reg_inst(14,13) val ex_op1 = MuxLookup(ex_ctrl.sel_alu1, 0.S)(Seq( A1_RS1 -> ex_rs(0).asSInt, A1_PC -> ex_reg_pc.asSInt, A1_RS1SHL -> (if (rocketParams.useZba) ex_rs1shl.asSInt else 0.S) )) val ex_op2_oh = UIntToOH(Mux(ex_ctrl.sel_alu2(0), (ex_reg_inst >> 20).asUInt, ex_rs(1))(log2Ceil(xLen)-1,0)).asSInt val ex_op2 = MuxLookup(ex_ctrl.sel_alu2, 0.S)(Seq( A2_RS2 -> ex_rs(1).asSInt, A2_IMM -> ex_imm, A2_SIZE -> Mux(ex_reg_rvc, 2.S, 4.S), ) ++ (if (coreParams.useZbs) Seq( A2_RS2OH -> ex_op2_oh, A2_IMMOH -> ex_op2_oh, ) else Nil)) val (ex_new_vl, ex_new_vconfig) = if (usingVector) { val ex_new_vtype = VType.fromUInt(MuxCase(ex_rs(1), Seq( ex_reg_inst(31,30).andR -> ex_reg_inst(29,20), !ex_reg_inst(31) -> ex_reg_inst(30,20)))) val ex_avl = Mux(ex_ctrl.rxs1, Mux(ex_reg_inst(19,15) === 0.U, Mux(ex_reg_inst(11,7) === 0.U, csr.io.vector.get.vconfig.vl, ex_new_vtype.vlMax), ex_rs(0) ), ex_reg_inst(19,15)) val ex_new_vl = ex_new_vtype.vl(ex_avl, csr.io.vector.get.vconfig.vl, false.B, false.B, false.B) val ex_new_vconfig = Wire(new VConfig) ex_new_vconfig.vtype := ex_new_vtype ex_new_vconfig.vl := ex_new_vl (Some(ex_new_vl), Some(ex_new_vconfig)) } else { (None, None) } val alu = Module(new ALU) alu.io.dw := ex_ctrl.alu_dw alu.io.fn := ex_ctrl.alu_fn alu.io.in2 := ex_op2.asUInt alu.io.in1 := ex_op1.asUInt // multiplier and divider val div = Module(new MulDiv(if (pipelinedMul) mulDivParams.copy(mulUnroll = 0) else mulDivParams, width = xLen)) div.io.req.valid := ex_reg_valid && ex_ctrl.div div.io.req.bits.dw := ex_ctrl.alu_dw div.io.req.bits.fn := ex_ctrl.alu_fn div.io.req.bits.in1 := ex_rs(0) div.io.req.bits.in2 := ex_rs(1) div.io.req.bits.tag := ex_waddr val mul = pipelinedMul.option { val m = Module(new PipelinedMultiplier(xLen, 2)) m.io.req.valid := ex_reg_valid && ex_ctrl.mul m.io.req.bits := div.io.req.bits m } ex_reg_valid := !ctrl_killd ex_reg_replay := !take_pc && ibuf.io.inst(0).valid && ibuf.io.inst(0).bits.replay ex_reg_xcpt := !ctrl_killd && id_xcpt ex_reg_xcpt_interrupt := !take_pc && ibuf.io.inst(0).valid && csr.io.interrupt when (!ctrl_killd) { ex_ctrl := id_ctrl ex_reg_rvc := ibuf.io.inst(0).bits.rvc ex_ctrl.csr := id_csr when (id_ctrl.fence && id_fence_succ === 0.U) { id_reg_pause := true.B } when (id_fence_next) { id_reg_fence := true.B } when (id_xcpt) { // pass PC down ALU writeback pipeline for badaddr ex_ctrl.alu_fn := FN_ADD ex_ctrl.alu_dw := DW_XPR ex_ctrl.sel_alu1 := A1_RS1 // badaddr := instruction ex_ctrl.sel_alu2 := A2_ZERO when (id_xcpt1.asUInt.orR) { // badaddr := PC+2 ex_ctrl.sel_alu1 := A1_PC ex_ctrl.sel_alu2 := A2_SIZE ex_reg_rvc := true.B } when (bpu.io.xcpt_if \|\| id_xcpt0.asUInt.orR) { // badaddr := PC ex_ctrl.sel_alu1 := A1_PC ex_ctrl.sel_alu2 := A2_ZERO } } ex_reg_flush_pipe := id_ctrl.fence_i \|\| id_csr_flush ex_reg_load_use := id_load_use ex_reg_hls := usingHypervisor.B && id_system_insn && id_ctrl.mem_cmd.isOneOf(M_XRD, M_XWR, M_HLVX) ex_reg_mem_size := Mux(usingHypervisor.B && id_system_insn, id_inst(0)(27, 26), id_inst(0)(13, 12)) when (id_ctrl.mem_cmd.isOneOf(M_SFENCE, M_HFENCEV, M_HFENCEG, M_FLUSH_ALL)) { ex_reg_mem_size := Cat(id_raddr2 =/= 0.U, id_raddr1 =/= 0.U) } when (id_ctrl.mem_cmd === M_SFENCE && csr.io.status.v) { ex_ctrl.mem_cmd := M_HFENCEV } if (tile.dcache.flushOnFenceI) { when (id_ctrl.fence_i) { ex_reg_mem_size := 0.U } } for (i <- 0 until id_raddr.size) { val do_bypass = id_bypass_src(i).reduce(_\|\|_) val bypass_src = PriorityEncoder(id_bypass_src(i)) ex_reg_rs_bypass(i) := do_bypass ex_reg_rs_lsb(i) := bypass_src when (id_ren(i) && !do_bypass) { ex_reg_rs_lsb(i) := id_rs(i)(log2Ceil(bypass_sources.size)-1, 0) ex_reg_rs_msb(i) := id_rs(i) >> log2Ceil(bypass_sources.size) } } when (id_illegal_insn \|\| id_virtual_insn) { val inst = Mux(ibuf.io.inst(0).bits.rvc, id_raw_inst(0)(15, 0), id_raw_inst(0)) ex_reg_rs_bypass(0) := false.B ex_reg_rs_lsb(0) := inst(log2Ceil(bypass_sources.size)-1, 0) ex_reg_rs_msb(0) := inst >> log2Ceil(bypass_sources.size) } } when (!ctrl_killd \|\| csr.io.interrupt \|\| ibuf.io.inst(0).bits.replay) { ex_reg_cause := id_cause ex_reg_inst := id_inst(0) ex_reg_raw_inst := id_raw_inst(0) ex_reg_pc := ibuf.io.pc ex_reg_btb_resp := ibuf.io.btb_resp ex_reg_wphit := bpu.io.bpwatch.map { bpw => bpw.ivalid(0) } ex_reg_set_vconfig := id_set_vconfig && !id_xcpt } // replay inst in ex stage? val ex_pc_valid = ex_reg_valid \|\| ex_reg_replay \|\| ex_reg_xcpt_interrupt val wb_dcache_miss = wb_ctrl.mem && !io.dmem.resp.valid val replay_ex_structural = ex_ctrl.mem && !io.dmem.req.ready \|\| ex_ctrl.div && !div.io.req.ready \|\| ex_ctrl.vec && !io.vector.map(_.ex.ready).getOrElse(true.B) val replay_ex_load_use = wb_dcache_miss && ex_reg_load_use val replay_ex = ex_reg_replay \|\| (ex_reg_valid && (replay_ex_structural \|\| replay_ex_load_use)) val ctrl_killx = take_pc_mem_wb \|\| replay_ex \|\| !ex_reg_valid // detect 2-cycle load-use delay for LB/LH/SC val ex_slow_bypass = ex_ctrl.mem_cmd === M_XSC \|\| ex_reg_mem_size < 2.U val ex_sfence = usingVM.B && ex_ctrl.mem && (ex_ctrl.mem_cmd === M_SFENCE \|\| ex_ctrl.mem_cmd === M_HFENCEV \|\| ex_ctrl.mem_cmd === M_HFENCEG) val (ex_xcpt, ex_cause) = checkExceptions(List( (ex_reg_xcpt_interrupt \|\| ex_reg_xcpt, ex_reg_cause))) val exCoverCauses = idCoverCauses coverExceptions(ex_xcpt, ex_cause, "EXECUTE", exCoverCauses) // memory stage val mem_pc_valid = mem_reg_valid \|\| mem_reg_replay \|\| mem_reg_xcpt_interrupt val mem_br_target = mem_reg_pc.asSInt + Mux(mem_ctrl.branch && mem_br_taken, ImmGen(IMM_SB, mem_reg_inst), Mux(mem_ctrl.jal, ImmGen(IMM_UJ, mem_reg_inst), Mux(mem_reg_rvc, 2.S, 4.S))) val mem_npc = (Mux(mem_ctrl.jalr \|\| mem_reg_sfence, encodeVirtualAddress(mem_reg_wdata, mem_reg_wdata).asSInt, mem_br_target) & (-2).S).asUInt val mem_wrong_npc = Mux(ex_pc_valid, mem_npc =/= ex_reg_pc, Mux(ibuf.io.inst(0).valid \|\| ibuf.io.imem.valid, mem_npc =/= ibuf.io.pc, true.B)) val mem_npc_misaligned = !csr.io.status.isa('c'-'a') && mem_npc(1) && !mem_reg_sfence val mem_int_wdata = Mux(!mem_reg_xcpt && (mem_ctrl.jalr ^ mem_npc_misaligned), mem_br_target, mem_reg_wdata.asSInt).asUInt val mem_cfi = mem_ctrl.branch \|\| mem_ctrl.jalr \|\| mem_ctrl.jal val mem_cfi_taken = (mem_ctrl.branch && mem_br_taken) \|\| mem_ctrl.jalr \|\| mem_ctrl.jal val mem_direction_misprediction = mem_ctrl.branch && mem_br_taken =/= (usingBTB.B && mem_reg_btb_resp.taken) val mem_misprediction = if (usingBTB) mem_wrong_npc else mem_cfi_taken take_pc_mem := mem_reg_valid && !mem_reg_xcpt && (mem_misprediction \|\| mem_reg_sfence) mem_reg_valid := !ctrl_killx mem_reg_replay := !take_pc_mem_wb && replay_ex mem_reg_xcpt := !ctrl_killx && ex_xcpt mem_reg_xcpt_interrupt := !take_pc_mem_wb && ex_reg_xcpt_interrupt // on pipeline flushes, cause mem_npc to hold the sequential npc, which // will drive the W-stage npc mux when (mem_reg_valid && mem_reg_flush_pipe) { mem_reg_sfence := false.B }.elsewhen (ex_pc_valid) { mem_ctrl := ex_ctrl mem_reg_rvc := ex_reg_rvc mem_reg_load := ex_ctrl.mem && isRead(ex_ctrl.mem_cmd) mem_reg_store := ex_ctrl.mem && isWrite(ex_ctrl.mem_cmd) mem_reg_sfence := ex_sfence mem_reg_btb_resp := ex_reg_btb_resp mem_reg_flush_pipe := ex_reg_flush_pipe mem_reg_slow_bypass := ex_slow_bypass mem_reg_wphit := ex_reg_wphit mem_reg_set_vconfig := ex_reg_set_vconfig mem_reg_cause := ex_cause mem_reg_inst := ex_reg_inst mem_reg_raw_inst := ex_reg_raw_inst mem_reg_mem_size := ex_reg_mem_size mem_reg_hls_or_dv := io.dmem.req.bits.dv mem_reg_pc := ex_reg_pc // IDecode ensured they are 1H mem_reg_wdata := Mux(ex_reg_set_vconfig, ex_new_vl.getOrElse(alu.io.out), alu.io.out) mem_br_taken := alu.io.cmp_out when (ex_ctrl.rxs2 && (ex_ctrl.mem \|\| ex_ctrl.rocc \|\| ex_sfence)) { val size = Mux(ex_ctrl.rocc, log2Ceil(xLen/8).U, ex_reg_mem_size) mem_reg_rs2 := new StoreGen(size, 0.U, ex_rs(1), coreDataBytes).data } if (usingVector) { when (ex_reg_set_vconfig) { mem_reg_rs2 := ex_new_vconfig.get.asUInt } } when (ex_ctrl.jalr && csr.io.status.debug) { // flush I$ on D-mode JALR to effect uncached fetch without D$ flush mem_ctrl.fence_i := true.B mem_reg_flush_pipe := true.B } } val mem_breakpoint = (mem_reg_load && bpu.io.xcpt_ld) \|\| (mem_reg_store && bpu.io.xcpt_st) val mem_debug_breakpoint = (mem_reg_load && bpu.io.debug_ld) \|\| (mem_reg_store && bpu.io.debug_st) val (mem_ldst_xcpt, mem_ldst_cause) = checkExceptions(List( (mem_debug_breakpoint, CSR.debugTriggerCause.U), (mem_breakpoint, Causes.breakpoint.U))) val (mem_xcpt, mem_cause) = checkExceptions(List( (mem_reg_xcpt_interrupt \|\| mem_reg_xcpt, mem_reg_cause), (mem_reg_valid && mem_npc_misaligned, Causes.misaligned_fetch.U), (mem_reg_valid && mem_ldst_xcpt, mem_ldst_cause))) val memCoverCauses = (exCoverCauses ++ List( (CSR.debugTriggerCause, "DEBUG_TRIGGER"), (Causes.breakpoint, "BREAKPOINT"), (Causes.misaligned_fetch, "MISALIGNED_FETCH") )).distinct coverExceptions(mem_xcpt, mem_cause, "MEMORY", memCoverCauses) val dcache_kill_mem = mem_reg_valid && mem_ctrl.wxd && io.dmem.replay_next // structural hazard on writeback port val fpu_kill_mem = mem_reg_valid && mem_ctrl.fp && io.fpu.nack_mem val vec_kill_mem = mem_reg_valid && mem_ctrl.mem && io.vector.map(_.mem.block_mem).getOrElse(false.B) val vec_kill_all = mem_reg_valid && io.vector.map(_.mem.block_all).getOrElse(false.B) val replay_mem = dcache_kill_mem \|\| mem_reg_replay \|\| fpu_kill_mem \|\| vec_kill_mem \|\| vec_kill_all val killm_common = dcache_kill_mem \|\| take_pc_wb \|\| mem_reg_xcpt \|\| !mem_reg_valid div.io.kill := killm_common && RegNext(div.io.req.fire) val ctrl_killm = killm_common \|\| mem_xcpt \|\| fpu_kill_mem \|\| vec_kill_mem // writeback stage wb_reg_valid := !ctrl_killm wb_reg_replay := replay_mem && !take_pc_wb wb_reg_xcpt := mem_xcpt && !take_pc_wb && !io.vector.map(_.mem.block_all).getOrElse(false.B) wb_reg_flush_pipe := !ctrl_killm && mem_reg_flush_pipe when (mem_pc_valid) { wb_ctrl := mem_ctrl wb_reg_sfence := mem_reg_sfence wb_reg_wdata := Mux(!mem_reg_xcpt && mem_ctrl.fp && mem_ctrl.wxd, io.fpu.toint_data, mem_int_wdata) when (mem_ctrl.rocc \|\| mem_reg_sfence \|\| mem_reg_set_vconfig) { wb_reg_rs2 := mem_reg_rs2 } wb_reg_cause := mem_cause wb_reg_inst := mem_reg_inst wb_reg_raw_inst := mem_reg_raw_inst wb_reg_mem_size := mem_reg_mem_size wb_reg_hls_or_dv := mem_reg_hls_or_dv wb_reg_hfence_v := mem_ctrl.mem_cmd === M_HFENCEV wb_reg_hfence_g := mem_ctrl.mem_cmd === M_HFENCEG wb_reg_pc := mem_reg_pc wb_reg_wphit := mem_reg_wphit \| bpu.io.bpwatch.map { bpw => (bpw.rvalid(0) && mem_reg_load) \|\| (bpw.wvalid(0) && mem_reg_store) } wb_reg_set_vconfig := mem_reg_set_vconfig } val (wb_xcpt, wb_cause) = checkExceptions(List( (wb_reg_xcpt, wb_reg_cause), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.st, Causes.store_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.ld, Causes.load_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.st, Causes.store_guest_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.ld, Causes.load_guest_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.st, Causes.store_access.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.ld, Causes.load_access.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.st, Causes.misaligned_store.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.ld, Causes.misaligned_load.U) )) val wbCoverCauses = List( (Causes.misaligned_store, "MISALIGNED_STORE"), (Causes.misaligned_load, "MISALIGNED_LOAD"), (Causes.store_access, "STORE_ACCESS"), (Causes.load_access, "LOAD_ACCESS") ) ++ (if(usingVM) List( (Causes.store_page_fault, "STORE_PAGE_FAULT"), (Causes.load_page_fault, "LOAD_PAGE_FAULT") ) else Nil) ++ (if (usingHypervisor) List( (Causes.store_guest_page_fault, "STORE_GUEST_PAGE_FAULT"), (Causes.load_guest_page_fault, "LOAD_GUEST_PAGE_FAULT"), ) else Nil) coverExceptions(wb_xcpt, wb_cause, "WRITEBACK", wbCoverCauses) val wb_pc_valid = wb_reg_valid \|\| wb_reg_replay \|\| wb_reg_xcpt val wb_wxd = wb_reg_valid && wb_ctrl.wxd val wb_set_sboard = wb_ctrl.div \|\| wb_dcache_miss \|\| wb_ctrl.rocc \|\| wb_ctrl.vec val replay_wb_common = io.dmem.s2_nack \|\| wb_reg_replay val replay_wb_rocc = wb_reg_valid && wb_ctrl.rocc && !io.rocc.cmd.ready val replay_wb_csr: Bool = wb_reg_valid && csr.io.rw_stall val replay_wb_vec = wb_reg_valid && io.vector.map(_.wb.replay).getOrElse(false.B) val replay_wb = replay_wb_common \|\| replay_wb_rocc \|\| replay_wb_csr \|\| replay_wb_vec take_pc_wb := replay_wb \|\| wb_xcpt \|\| csr.io.eret \|\| wb_reg_flush_pipe // writeback arbitration val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).asBool val dmem_resp_fpu = io.dmem.resp.bits.tag(0).asBool val dmem_resp_waddr = io.dmem.resp.bits.tag(5, 1) val dmem_resp_valid = io.dmem.resp.valid && io.dmem.resp.bits.has_data val dmem_resp_replay = dmem_resp_valid && io.dmem.resp.bits.replay class LLWB extends Bundle { val data = UInt(xLen.W) val tag = UInt(5.W) } val ll_arb = Module(new Arbiter(new LLWB, 3)) // div, rocc, vec ll_arb.io.in.foreach(_.valid := false.B) ll_arb.io.in.foreach(_.bits := DontCare) val ll_wdata = WireInit(ll_arb.io.out.bits.data) val ll_waddr = WireInit(ll_arb.io.out.bits.tag) val ll_wen = WireInit(ll_arb.io.out.fire) ll_arb.io.out.ready := !wb_wxd div.io.resp.ready := ll_arb.io.in(0).ready ll_arb.io.in(0).valid := div.io.resp.valid ll_arb.io.in(0).bits.data := div.io.resp.bits.data ll_arb.io.in(0).bits.tag := div.io.resp.bits.tag if (usingRoCC) { io.rocc.resp.ready := ll_arb.io.in(1).ready ll_arb.io.in(1).valid := io.rocc.resp.valid ll_arb.io.in(1).bits.data := io.rocc.resp.bits.data ll_arb.io.in(1).bits.tag := io.rocc.resp.bits.rd } else { // tie off RoCC io.rocc.resp.ready := false.B io.rocc.mem.req.ready := false.B } io.vector.map { v => v.resp.ready := Mux(v.resp.bits.fp, !(dmem_resp_valid && dmem_resp_fpu), ll_arb.io.in(2).ready) ll_arb.io.in(2).valid := v.resp.valid && !v.resp.bits.fp ll_arb.io.in(2).bits.data := v.resp.bits.data ll_arb.io.in(2).bits.tag := v.resp.bits.rd } // Dont care mem since not all RoCC need accessing memory io.rocc.mem := DontCare when (dmem_resp_replay && dmem_resp_xpu) { ll_arb.io.out.ready := false.B ll_waddr := dmem_resp_waddr ll_wen := true.B } val wb_valid = wb_reg_valid && !replay_wb && !wb_xcpt val wb_wen = wb_valid && wb_ctrl.wxd val rf_wen = wb_wen \|\| ll_wen val rf_waddr = Mux(ll_wen, ll_waddr, wb_waddr) val rf_wdata = Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data(xLen-1, 0), Mux(ll_wen, ll_wdata, Mux(wb_ctrl.csr =/= CSR.N, csr.io.rw.rdata, Mux(wb_ctrl.mul, mul.map(_.io.resp.bits.data).getOrElse(wb_reg_wdata), wb_reg_wdata)))) when (rf_wen) { rf.write(rf_waddr, rf_wdata) } // hook up control/status regfile csr.io.ungated_clock := clock csr.io.decode(0).inst := id_inst(0) csr.io.exception := wb_xcpt csr.io.cause := wb_cause csr.io.retire := wb_valid csr.io.inst(0) := (if (usingCompressed) Cat(Mux(wb_reg_raw_inst(1, 0).andR, wb_reg_inst >> 16, 0.U), wb_reg_raw_inst(15, 0)) else wb_reg_inst) csr.io.interrupts := io.interrupts csr.io.hartid := io.hartid io.fpu.fcsr_rm := csr.io.fcsr_rm val vector_fcsr_flags = io.vector.map(_.set_fflags.bits).getOrElse(0.U(5.W)) val vector_fcsr_flags_valid = io.vector.map(_.set_fflags.valid).getOrElse(false.B) csr.io.fcsr_flags.valid := io.fpu.fcsr_flags.valid \| vector_fcsr_flags_valid csr.io.fcsr_flags.bits := (io.fpu.fcsr_flags.bits & Fill(5, io.fpu.fcsr_flags.valid)) \| (vector_fcsr_flags & Fill(5, vector_fcsr_flags_valid)) io.fpu.time := csr.io.time(31,0) io.fpu.hartid := io.hartid csr.io.rocc_interrupt := io.rocc.interrupt csr.io.pc := wb_reg_pc val tval_dmem_addr = !wb_reg_xcpt val tval_any_addr = tval_dmem_addr \|\| wb_reg_cause.isOneOf(Causes.breakpoint.U, Causes.fetch_access.U, Causes.fetch_page_fault.U, Causes.fetch_guest_page_fault.U) val tval_inst = wb_reg_cause === Causes.illegal_instruction.U val tval_valid = wb_xcpt && (tval_any_addr \|\| tval_inst) csr.io.gva := wb_xcpt && (tval_any_addr && csr.io.status.v \|\| tval_dmem_addr && wb_reg_hls_or_dv) csr.io.tval := Mux(tval_valid, encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata), 0.U) val (htval, mhtinst_read_pseudo) = { val htval_valid_imem = wb_reg_xcpt && wb_reg_cause === Causes.fetch_guest_page_fault.U val htval_imem = Mux(htval_valid_imem, io.imem.gpa.bits, 0.U) assert(!htval_valid_imem \|\| io.imem.gpa.valid) val htval_valid_dmem = wb_xcpt && tval_dmem_addr && io.dmem.s2_xcpt.gf.asUInt.orR && !io.dmem.s2_xcpt.pf.asUInt.orR val htval_dmem = Mux(htval_valid_dmem, io.dmem.s2_gpa, 0.U) val htval = (htval_dmem \| htval_imem) >> hypervisorExtraAddrBits // read pseudoinstruction if a guest-page fault is caused by an implicit memory access for VS-stage address translation val mhtinst_read_pseudo = (io.imem.gpa_is_pte && htval_valid_imem) \|\| (io.dmem.s2_gpa_is_pte && htval_valid_dmem) (htval, mhtinst_read_pseudo) } csr.io.vector.foreach { v => v.set_vconfig.valid := wb_reg_set_vconfig && wb_reg_valid v.set_vconfig.bits := wb_reg_rs2.asTypeOf(new VConfig) v.set_vs_dirty := wb_valid && wb_ctrl.vec v.set_vstart.valid := wb_valid && wb_reg_set_vconfig v.set_vstart.bits := 0.U } io.vector.foreach { v => when (v.wb.retire \|\| v.wb.xcpt \|\| wb_ctrl.vec) { csr.io.pc := v.wb.pc csr.io.retire := v.wb.retire csr.io.inst(0) := v.wb.inst when (v.wb.xcpt && !wb_reg_xcpt) { wb_xcpt := true.B wb_cause := v.wb.cause csr.io.tval := v.wb.tval } } v.wb.store_pending := io.dmem.store_pending v.wb.vxrm := csr.io.vector.get.vxrm v.wb.frm := csr.io.fcsr_rm csr.io.vector.get.set_vxsat := v.set_vxsat when (v.set_vconfig.valid) { csr.io.vector.get.set_vconfig.valid := true.B csr.io.vector.get.set_vconfig.bits := v.set_vconfig.bits } when (v.set_vstart.valid) { csr.io.vector.get.set_vstart.valid := true.B csr.io.vector.get.set_vstart.bits := v.set_vstart.bits } } csr.io.htval := htval csr.io.mhtinst_read_pseudo := mhtinst_read_pseudo io.ptw.ptbr := csr.io.ptbr io.ptw.hgatp := csr.io.hgatp io.ptw.vsatp := csr.io.vsatp (io.ptw.customCSRs.csrs zip csr.io.customCSRs).map { case (lhs, rhs) => lhs <> rhs } io.ptw.status := csr.io.status io.ptw.hstatus := csr.io.hstatus io.ptw.gstatus := csr.io.gstatus io.ptw.pmp := csr.io.pmp csr.io.rw.addr := wb_reg_inst(31,20) csr.io.rw.cmd := CSR.maskCmd(wb_reg_valid, wb_ctrl.csr) csr.io.rw.wdata := wb_reg_wdata io.rocc.csrs <> csr.io.roccCSRs io.trace.time := csr.io.time io.trace.insns := csr.io.trace if (rocketParams.debugROB.isDefined) { val sz = rocketParams.debugROB.get.size if (sz < 1) { // use unsynthesizable ROB val csr_trace_with_wdata = WireInit(csr.io.trace(0)) csr_trace_with_wdata.wdata.get := rf_wdata val should_wb = WireInit((wb_ctrl.wfd \|\| (wb_ctrl.wxd && wb_waddr =/= 0.U)) && !csr.io.trace(0).exception) val has_wb = WireInit(wb_ctrl.wxd && wb_wen && !wb_set_sboard) val wb_addr = WireInit(wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U)) io.vector.foreach { v => when (v.wb.retire) { should_wb := v.wb.rob_should_wb has_wb := false.B wb_addr := Cat(v.wb.rob_should_wb_fp, csr_trace_with_wdata.insn(11,7)) }} DebugROB.pushTrace(clock, reset, io.hartid, csr_trace_with_wdata, should_wb, has_wb, wb_addr) io.trace.insns(0) := DebugROB.popTrace(clock, reset, io.hartid) DebugROB.pushWb(clock, reset, io.hartid, ll_wen, rf_waddr, rf_wdata) } else { // synthesizable ROB (no FPRs) require(!usingVector, "Synthesizable ROB does not support vector implementations") val csr_trace_with_wdata = WireInit(csr.io.trace(0)) csr_trace_with_wdata.wdata.get := rf_wdata val debug_rob = Module(new HardDebugROB(sz, 32)) debug_rob.io.i_insn := csr_trace_with_wdata debug_rob.io.should_wb := (wb_ctrl.wfd \|\| (wb_ctrl.wxd && wb_waddr =/= 0.U)) && !csr.io.trace(0).exception debug_rob.io.has_wb := wb_ctrl.wxd && wb_wen && !wb_set_sboard debug_rob.io.tag := wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U) debug_rob.io.wb_val := ll_wen debug_rob.io.wb_tag := rf_waddr debug_rob.io.wb_data := rf_wdata io.trace.insns(0) := debug_rob.io.o_insn } } else { io.trace.insns := csr.io.trace } for (((iobpw, wphit), bp) <- io.bpwatch zip wb_reg_wphit zip csr.io.bp) { iobpw.valid(0) := wphit iobpw.action := bp.control.action // tie off bpwatch valids iobpw.rvalid.foreach(_ := false.B) iobpw.wvalid.foreach(_ := false.B) iobpw.ivalid.foreach(_ := false.B) } val hazard_targets = Seq((id_ctrl.rxs1 && id_raddr1 =/= 0.U, id_raddr1), (id_ctrl.rxs2 && id_raddr2 =/= 0.U, id_raddr2), (id_ctrl.wxd && id_waddr =/= 0.U, id_waddr)) val fp_hazard_targets = Seq((io.fpu.dec.ren1, id_raddr1), (io.fpu.dec.ren2, id_raddr2), (io.fpu.dec.ren3, id_raddr3), (io.fpu.dec.wen, id_waddr)) val sboard = new Scoreboard(32, true) sboard.clear(ll_wen, ll_waddr) def id_sboard_clear_bypass(r: UInt) = { // ll_waddr arrives late when D$ has ECC, so reshuffle the hazard check if (!tileParams.dcache.get.dataECC.isDefined) ll_wen && ll_waddr === r else div.io.resp.fire && div.io.resp.bits.tag === r \|\| dmem_resp_replay && dmem_resp_xpu && dmem_resp_waddr === r } val id_sboard_hazard = checkHazards(hazard_targets, rd => sboard.read(rd) && !id_sboard_clear_bypass(rd)) sboard.set(wb_set_sboard && wb_wen, wb_waddr) // stall for RAW/WAW hazards on CSRs, loads, AMOs, and mul/div in execute stage. val ex_cannot_bypass = ex_ctrl.csr =/= CSR.N \|\| ex_ctrl.jalr \|\| ex_ctrl.mem \|\| ex_ctrl.mul \|\| ex_ctrl.div \|\| ex_ctrl.fp \|\| ex_ctrl.rocc \|\| ex_ctrl.vec val data_hazard_ex = ex_ctrl.wxd && checkHazards(hazard_targets, _ === ex_waddr) val fp_data_hazard_ex = id_ctrl.fp && ex_ctrl.wfd && checkHazards(fp_hazard_targets, _ === ex_waddr) val id_ex_hazard = ex_reg_valid && (data_hazard_ex && ex_cannot_bypass \|\| fp_data_hazard_ex) // stall for RAW/WAW hazards on CSRs, LB/LH, and mul/div in memory stage. val mem_mem_cmd_bh = if (fastLoadWord) (!fastLoadByte).B && mem_reg_slow_bypass else true.B val mem_cannot_bypass = mem_ctrl.csr =/= CSR.N \|\| mem_ctrl.mem && mem_mem_cmd_bh \|\| mem_ctrl.mul \|\| mem_ctrl.div \|\| mem_ctrl.fp \|\| mem_ctrl.rocc \|\| mem_ctrl.vec val data_hazard_mem = mem_ctrl.wxd && checkHazards(hazard_targets, _ === mem_waddr) val fp_data_hazard_mem = id_ctrl.fp && mem_ctrl.wfd && checkHazards(fp_hazard_targets, _ === mem_waddr) val id_mem_hazard = mem_reg_valid && (data_hazard_mem && mem_cannot_bypass \|\| fp_data_hazard_mem) id_load_use := mem_reg_valid && data_hazard_mem && mem_ctrl.mem val id_vconfig_hazard = id_ctrl.vec && ( (ex_reg_valid && ex_reg_set_vconfig) \|\| (mem_reg_valid && mem_reg_set_vconfig) \|\| (wb_reg_valid && wb_reg_set_vconfig)) // stall for RAW/WAW hazards on load/AMO misses and mul/div in writeback. val data_hazard_wb = wb_ctrl.wxd && checkHazards(hazard_targets, _ === wb_waddr) val fp_data_hazard_wb = id_ctrl.fp && wb_ctrl.wfd && checkHazards(fp_hazard_targets, _ === wb_waddr) val id_wb_hazard = wb_reg_valid && (data_hazard_wb && wb_set_sboard \|\| fp_data_hazard_wb) val id_stall_fpu = if (usingFPU) { val fp_sboard = new Scoreboard(32) fp_sboard.set(((wb_dcache_miss \|\| wb_ctrl.vec) && wb_ctrl.wfd \|\| io.fpu.sboard_set) && wb_valid, wb_waddr) val v_ll = io.vector.map(v => v.resp.fire && v.resp.bits.fp).getOrElse(false.B) fp_sboard.clear((dmem_resp_replay && dmem_resp_fpu) \|\| v_ll, io.fpu.ll_resp_tag) fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra) checkHazards(fp_hazard_targets, fp_sboard.read _) } else false.B val dcache_blocked = { // speculate that a blocked D$ will unblock the cycle after a Grant val blocked = Reg(Bool()) blocked := !io.dmem.req.ready && io.dmem.clock_enabled && !io.dmem.perf.grant && (blocked \|\| io.dmem.req.valid \|\| io.dmem.s2_nack) blocked && !io.dmem.perf.grant } val rocc_blocked = Reg(Bool()) rocc_blocked := !wb_xcpt && !io.rocc.cmd.ready && (io.rocc.cmd.valid \|\| rocc_blocked) val ctrl_stalld = id_ex_hazard \|\| id_mem_hazard \|\| id_wb_hazard \|\| id_sboard_hazard \|\| id_vconfig_hazard \|\| csr.io.singleStep && (ex_reg_valid \|\| mem_reg_valid \|\| wb_reg_valid) \|\| id_csr_en && csr.io.decode(0).fp_csr && !io.fpu.fcsr_rdy \|\| id_csr_en && csr.io.decode(0).vector_csr && id_vec_busy \|\| id_ctrl.fp && id_stall_fpu \|\| id_ctrl.mem && dcache_blocked \|\| // reduce activity during D$ misses id_ctrl.rocc && rocc_blocked \|\| // reduce activity while RoCC is busy id_ctrl.div && (!(div.io.req.ready \|\| (div.io.resp.valid && !wb_wxd)) \|\| div.io.req.valid) \|\| // reduce odds of replay !clock_en \|\| id_do_fence \|\| csr.io.csr_stall \|\| id_reg_pause \|\| io.traceStall ctrl_killd := !ibuf.io.inst(0).valid \|\| ibuf.io.inst(0).bits.replay \|\| take_pc_mem_wb \|\| ctrl_stalld \|\| csr.io.interrupt io.imem.req.valid := take_pc io.imem.req.bits.speculative := !take_pc_wb io.imem.req.bits.pc := Mux(wb_xcpt \|\| csr.io.eret, csr.io.evec, // exception or [m\|s]ret Mux(replay_wb, wb_reg_pc, // replay mem_npc)) // flush or branch misprediction io.imem.flush_icache := wb_reg_valid && wb_ctrl.fence_i && !io.dmem.s2_nack io.imem.might_request := { imem_might_request_reg := ex_pc_valid \|\| mem_pc_valid \|\| io.ptw.customCSRs.disableICacheClockGate \|\| io.vector.map(_.trap_check_busy).getOrElse(false.B) imem_might_request_reg } io.imem.progress := RegNext(wb_reg_valid && !replay_wb_common) io.imem.sfence.valid := wb_reg_valid && wb_reg_sfence io.imem.sfence.bits.rs1 := wb_reg_mem_size(0) io.imem.sfence.bits.rs2 := wb_reg_mem_size(1) io.imem.sfence.bits.addr := wb_reg_wdata io.imem.sfence.bits.asid := wb_reg_rs2 io.imem.sfence.bits.hv := wb_reg_hfence_v io.imem.sfence.bits.hg := wb_reg_hfence_g io.ptw.sfence := io.imem.sfence ibuf.io.inst(0).ready := !ctrl_stalld io.imem.btb_update.valid := mem_reg_valid && !take_pc_wb && mem_wrong_npc && (!mem_cfi \|\| mem_cfi_taken) io.imem.btb_update.bits.isValid := mem_cfi io.imem.btb_update.bits.cfiType := Mux((mem_ctrl.jal \|\| mem_ctrl.jalr) && mem_waddr(0), CFIType.call, Mux(mem_ctrl.jalr && (mem_reg_inst(19,15) & regAddrMask.U) === BitPat("b00?01"), CFIType.ret, Mux(mem_ctrl.jal \|\| mem_ctrl.jalr, CFIType.jump, CFIType.branch))) io.imem.btb_update.bits.target := io.imem.req.bits.pc io.imem.btb_update.bits.br_pc := (if (usingCompressed) mem_reg_pc + Mux(mem_reg_rvc, 0.U, 2.U) else mem_reg_pc) io.imem.btb_update.bits.pc := ~(~io.imem.btb_update.bits.br_pc \| (coreInstBytesfetchWidth-1).U) io.imem.btb_update.bits.prediction := mem_reg_btb_resp io.imem.btb_update.bits.taken := DontCare io.imem.bht_update.valid := mem_reg_valid && !take_pc_wb io.imem.bht_update.bits.pc := io.imem.btb_update.bits.pc io.imem.bht_update.bits.taken := mem_br_taken io.imem.bht_update.bits.mispredict := mem_wrong_npc io.imem.bht_update.bits.branch := mem_ctrl.branch io.imem.bht_update.bits.prediction := mem_reg_btb_resp.bht // Connect RAS in Frontend io.imem.ras_update := DontCare io.fpu.valid := !ctrl_killd && id_ctrl.fp io.fpu.killx := ctrl_killx io.fpu.killm := killm_common io.fpu.inst := id_inst(0) io.fpu.fromint_data := ex_rs(0) io.fpu.ll_resp_val := dmem_resp_valid && dmem_resp_fpu io.fpu.ll_resp_data := (if (minFLen == 32) io.dmem.resp.bits.data_word_bypass else io.dmem.resp.bits.data) io.fpu.ll_resp_type := io.dmem.resp.bits.size io.fpu.ll_resp_tag := dmem_resp_waddr io.fpu.keep_clock_enabled := io.ptw.customCSRs.disableCoreClockGate io.fpu.v_sew := csr.io.vector.map(_.vconfig.vtype.vsew).getOrElse(0.U) io.vector.map { v => when (!(dmem_resp_valid && dmem_resp_fpu)) { io.fpu.ll_resp_val := v.resp.valid && v.resp.bits.fp io.fpu.ll_resp_data := v.resp.bits.data io.fpu.ll_resp_type := v.resp.bits.size io.fpu.ll_resp_tag := v.resp.bits.rd } } io.vector.foreach { v => v.ex.valid := ex_reg_valid && (ex_ctrl.vec \|\| rocketParams.vector.get.issueVConfig.B && ex_reg_set_vconfig) && !ctrl_killx v.ex.inst := ex_reg_inst v.ex.vconfig := csr.io.vector.get.vconfig v.ex.vstart := Mux(mem_reg_valid && mem_ctrl.vec \|\| wb_reg_valid && wb_ctrl.vec, 0.U, csr.io.vector.get.vstart) v.ex.rs1 := ex_rs(0) v.ex.rs2 := ex_rs(1) v.ex.pc := ex_reg_pc v.mem.frs1 := io.fpu.store_data v.killm := killm_common v.status := csr.io.status } io.dmem.req.valid := ex_reg_valid && ex_ctrl.mem val ex_dcache_tag = Cat(ex_waddr, ex_ctrl.fp) require(coreParams.dcacheReqTagBits >= ex_dcache_tag.getWidth) io.dmem.req.bits.tag := ex_dcache_tag io.dmem.req.bits.cmd := ex_ctrl.mem_cmd io.dmem.req.bits.size := ex_reg_mem_size io.dmem.req.bits.signed := !Mux(ex_reg_hls, ex_reg_inst(20), ex_reg_inst(14)) io.dmem.req.bits.phys := false.B io.dmem.req.bits.addr := encodeVirtualAddress(ex_rs(0), alu.io.adder_out) io.dmem.req.bits.idx.foreach(_ := io.dmem.req.bits.addr) io.dmem.req.bits.dprv := Mux(ex_reg_hls, csr.io.hstatus.spvp, csr.io.status.dprv) io.dmem.req.bits.dv := ex_reg_hls \|\| csr.io.status.dv io.dmem.req.bits.no_resp := !isRead(ex_ctrl.mem_cmd) \|\| (!ex_ctrl.fp && ex_waddr === 0.U) io.dmem.req.bits.no_alloc := DontCare io.dmem.req.bits.no_xcpt := DontCare io.dmem.req.bits.data := DontCare io.dmem.req.bits.mask := DontCare io.dmem.s1_data.data := (if (fLen == 0) mem_reg_rs2 else Mux(mem_ctrl.fp, Fill(coreDataBits / fLen, io.fpu.store_data), mem_reg_rs2)) io.dmem.s1_data.mask := DontCare io.dmem.s1_kill := killm_common \|\| mem_ldst_xcpt \|\| fpu_kill_mem \|\| vec_kill_mem io.dmem.s2_kill := false.B // don't let D$ go to sleep if we're probably going to use it soon io.dmem.keep_clock_enabled := ibuf.io.inst(0).valid && id_ctrl.mem && !csr.io.csr_stall io.rocc.cmd.valid := wb_reg_valid && wb_ctrl.rocc && !replay_wb_common io.rocc.exception := wb_xcpt && csr.io.status.xs.orR io.rocc.cmd.bits.status := csr.io.status io.rocc.cmd.bits.inst := wb_reg_inst.asTypeOf(new RoCCInstruction()) io.rocc.cmd.bits.rs1 := wb_reg_wdata io.rocc.cmd.bits.rs2 := wb_reg_rs2 // gate the clock val unpause = csr.io.time(rocketParams.lgPauseCycles-1, 0) === 0.U \|\| csr.io.inhibit_cycle \|\| io.dmem.perf.release \|\| take_pc when (unpause) { id_reg_pause := false.B } io.cease := csr.io.status.cease && !clock_en_reg io.wfi := csr.io.status.wfi if (rocketParams.clockGate) { long_latency_stall := csr.io.csr_stall \|\| io.dmem.perf.blocked \|\| id_reg_pause && !unpause clock_en := clock_en_reg \|\| ex_pc_valid \|\| (!long_latency_stall && io.imem.resp.valid) clock_en_reg := ex_pc_valid \|\| mem_pc_valid \|\| wb_pc_valid \|\| // instruction in flight io.ptw.customCSRs.disableCoreClockGate \|\| // chicken bit !div.io.req.ready \|\| // mul/div in flight usingFPU.B && !io.fpu.fcsr_rdy \|\| // long-latency FPU in flight io.dmem.replay_next \|\| // long-latency load replaying (!long_latency_stall && (ibuf.io.inst(0).valid \|\| io.imem.resp.valid)) // instruction pending assert(!(ex_pc_valid \|\| mem_pc_valid \|\| wb_pc_valid) \|\| clock_en) } // evaluate performance counters val icache_blocked = !(io.imem.resp.valid \|\| RegNext(io.imem.resp.valid)) csr.io.counters foreach { c => c.inc := RegNext(perfEvents.evaluate(c.eventSel)) } val coreMonitorBundle = Wire(new CoreMonitorBundle(xLen, fLen)) coreMonitorBundle.clock := clock coreMonitorBundle.reset := reset coreMonitorBundle.hartid := io.hartid coreMonitorBundle.timer := csr.io.time(31,0) coreMonitorBundle.valid := csr.io.trace(0).valid && !csr.io.trace(0).exception coreMonitorBundle.pc := csr.io.trace(0).iaddr(vaddrBitsExtended-1, 0).sextTo(xLen) coreMonitorBundle.wrenx := wb_wen && !wb_set_sboard coreMonitorBundle.wrenf := false.B coreMonitorBundle.wrdst := wb_waddr coreMonitorBundle.wrdata := rf_wdata coreMonitorBundle.rd0src := wb_reg_inst(19,15) coreMonitorBundle.rd0val := RegNext(RegNext(ex_rs(0))) coreMonitorBundle.rd1src := wb_reg_inst(24,20) coreMonitorBundle.rd1val := RegNext(RegNext(ex_rs(1))) coreMonitorBundle.inst := csr.io.trace(0).insn coreMonitorBundle.excpt := csr.io.trace(0).exception coreMonitorBundle.priv_mode := csr.io.trace(0).priv if (enableCommitLog) { val t = csr.io.trace(0) val rd = wb_waddr val wfd = wb_ctrl.wfd val wxd = wb_ctrl.wxd val has_data = wb_wen && !wb_set_sboard when (t.valid && !t.exception) { when (wfd) { printf ("%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd+32.U) } .elsewhen (wxd && rd =/= 0.U && has_data) { printf ("%d 0x%x (0x%x) x%d 0x%x\n", t.priv, t.iaddr, t.insn, rd, rf_wdata) } .elsewhen (wxd && rd =/= 0.U && !has_data) { printf ("%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd) } .otherwise { printf ("%d 0x%x (0x%x)\n", t.priv, t.iaddr, t.insn) } } when (ll_wen && rf_waddr =/= 0.U) { printf ("x%d p%d 0x%x\n", rf_waddr, rf_waddr, rf_wdata) } } else { when (csr.io.trace(0).valid) { printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", io.hartid, coreMonitorBundle.timer, coreMonitorBundle.valid, coreMonitorBundle.pc, Mux(wb_ctrl.wxd \|\| wb_ctrl.wfd, coreMonitorBundle.wrdst, 0.U), Mux(coreMonitorBundle.wrenx, coreMonitorBundle.wrdata, 0.U), coreMonitorBundle.wrenx, Mux(wb_ctrl.rxs1 \|\| wb_ctrl.rfs1, coreMonitorBundle.rd0src, 0.U), Mux(wb_ctrl.rxs1 \|\| wb_ctrl.rfs1, coreMonitorBundle.rd0val, 0.U), Mux(wb_ctrl.rxs2 \|\| wb_ctrl.rfs2, coreMonitorBundle.rd1src, 0.U), Mux(wb_ctrl.rxs2 \|\| wb_ctrl.rfs2, coreMonitorBundle.rd1val, 0.U), coreMonitorBundle.inst, coreMonitorBundle.inst) } } // CoreMonitorBundle for late latency writes val xrfWriteBundle = Wire(new CoreMonitorBundle(xLen, fLen)) xrfWriteBundle.clock := clock xrfWriteBundle.reset := reset xrfWriteBundle.hartid := io.hartid xrfWriteBundle.timer := csr.io.time(31,0) xrfWriteBundle.valid := false.B xrfWriteBundle.pc := 0.U xrfWriteBundle.wrdst := rf_waddr xrfWriteBundle.wrenx := rf_wen && !(csr.io.trace(0).valid && wb_wen && (wb_waddr === rf_waddr)) xrfWriteBundle.wrenf := false.B xrfWriteBundle.wrdata := rf_wdata xrfWriteBundle.rd0src := 0.U xrfWriteBundle.rd0val := 0.U xrfWriteBundle.rd1src := 0.U xrfWriteBundle.rd1val := 0.U xrfWriteBundle.inst := 0.U xrfWriteBundle.excpt := false.B xrfWriteBundle.priv_mode := csr.io.trace(0).priv if (rocketParams.haveSimTimeout) PlusArg.timeout( name = "max_core_cycles", docstring = "Kill the emulation after INT rdtime cycles. Off if 0." )(csr.io.time) } // leaving gated-clock domain val rocketImpl = withClock (gated_clock) { new RocketImpl } def checkExceptions(x: Seq[(Bool, UInt)]) = (WireInit(x.map(_._1).reduce(_\|\|_)), WireInit(PriorityMux(x))) def coverExceptions(exceptionValid: Bool, cause: UInt, labelPrefix: String, coverCausesLabels: Seq[(Int, String)]): Unit = { for ((coverCause, label) <- coverCausesLabels) { property.cover(exceptionValid && (cause === coverCause.U), s"${labelPrefix}_${label}") } } def checkHazards(targets: Seq[(Bool, UInt)], cond: UInt => Bool) = targets.map(h => h._1 && cond(h._2)).reduce(_\|\|_) def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) ea else { // efficient means to compress 64-bit VA into vaddrBits+1 bits // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)) val b = vaddrBitsExtended-1 val a = (a0 >> b).asSInt val msb = Mux(a === 0.S \|\| a === -1.S, ea(b), !ea(b-1)) Cat(msb, ea(b-1, 0)) } class Scoreboard(n: Int, zero: Boolean = false) { def set(en: Bool, addr: UInt): Unit = update(en, _next \| mask(en, addr)) def clear(en: Bool, addr: UInt): Unit = update(en, _next & ~mask(en, addr)) def read(addr: UInt): Bool = r(addr) def readBypassed(addr: UInt): Bool = _next(addr) private val _r = RegInit(0.U(n.W)) private val r = if (zero) (_r >> 1 << 1) else _r private var _next = r private var ens = false.B private def mask(en: Bool, addr: UInt) = Mux(en, 1.U << addr, 0.U) private def update(en: Bool, update: UInt) = { _next = update ens = ens \|\| en when (ens) { _r := _next } } } } class RegFile(n: Int, w: Int, zero: Boolean = false) { val rf = Mem(n, UInt(w.W)) private def access(addr: UInt) = rf(~addr(log2Up(n)-1,0)) private val reads = ArrayBuffer[(UInt,UInt)]() private var canRead = true def read(addr: UInt) = { require(canRead) reads += addr -> Wire(UInt()) reads.last._2 := Mux(zero.B && addr === 0.U, 0.U, access(addr)) reads.last._2 } def write(addr: UInt, data: UInt) = { canRead = false when (addr =/= 0.U) { access(addr) := data for ((raddr, rdata) <- reads) when (addr === raddr) { rdata := data } } } } object ImmGen { def apply(sel: UInt, inst: UInt) = { val sign = Mux(sel === IMM_Z, 0.S, inst(31).asSInt) val b30_20 = Mux(sel === IMM_U, inst(30,20).asSInt, sign) val b19_12 = Mux(sel =/= IMM_U && sel =/= IMM_UJ, sign, inst(19,12).asSInt) val b11 = Mux(sel === IMM_U \|\| sel === IMM_Z, 0.S, Mux(sel === IMM_UJ, inst(20).asSInt, Mux(sel === IMM_SB, inst(7).asSInt, sign))) val b10_5 = Mux(sel === IMM_U \|\| sel === IMM_Z, 0.U, inst(30,25)) val b4_1 = Mux(sel === IMM_U, 0.U, Mux(sel === IMM_S \|\| sel === IMM_SB, inst(11,8), Mux(sel === IMM_Z, inst(19,16), inst(24,21)))) val b0 = Mux(sel === IMM_S, inst(7), Mux(sel === IMM_I, inst(20), Mux(sel === IMM_Z, inst(15), 0.U))) Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0).asSInt } } File AMOALU.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) { val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W)) size := typ val dat_padded = dat.pad(maxSize8) def misaligned: Bool = (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR def mask = { var res = 1.U for (i <- 0 until log2Up(maxSize)) { val upper = Mux(addr(i), res, 0.U) \| Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U) val lower = Mux(addr(i), 0.U, res) res = Cat(upper, lower) } res } protected def genData(i: Int): UInt = if (i >= log2Up(maxSize)) dat_padded else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1)) def data = genData(0) def wordData = genData(2) } class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { private val size = new StoreGen(typ, addr, dat, maxSize).size private def genData(logMinSize: Int): UInt = { var res = dat for (i <- log2Up(maxSize)-1 to logMinSize by -1) { val pos = 8 << i val shifted = Mux(addr(i), res(2pos-1,pos), res(pos-1,0)) val doZero = (i == 0).B && zero val zeroed = Mux(doZero, 0.U, shifted) res = Cat(Mux(size === i.U \|\| doZero, Fill(8maxSize-pos, signed && zeroed(pos-1)), res(8maxSize-1,pos)), zeroed) } res } def wordData = genData(2) def data = genData(0) } class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module { val minXLen = 32 val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _) val io = IO(new Bundle { val mask = Input(UInt((operandBits / 8).W)) val cmd = Input(UInt(M_SZ.W)) val lhs = Input(UInt(operandBits.W)) val rhs = Input(UInt(operandBits.W)) val out = Output(UInt(operandBits.W)) val out_unmasked = Output(UInt(operandBits.W)) }) val max = io.cmd === M_XA_MAX \|\| io.cmd === M_XA_MAXU val min = io.cmd === M_XA_MIN \|\| io.cmd === M_XA_MINU val add = io.cmd === M_XA_ADD val logic_and = io.cmd === M_XA_OR \|\| io.cmd === M_XA_AND val logic_xor = io.cmd === M_XA_XOR \|\| io.cmd === M_XA_OR val adder_out = { // partition the carry chain to support sub-xLen addition val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_\|_) (io.lhs & mask) + (io.rhs & mask) } val less = { // break up the comparator so the lower parts will be CSE'd def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = { if (n == minXLen) x(n-1, 0) < y(n-1, 0) else x(n-1, n/2) < y(n-1, n/2) \|\| x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2) } def isLess(x: UInt, y: UInt, n: Int): Bool = { val signed = { val mask = M_XA_MIN ^ M_XA_MINU (io.cmd & mask) === (M_XA_MIN & mask) } Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1))) } PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w)))) } val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs) val logic = Mux(logic_and, io.lhs & io.rhs, 0.U) \| Mux(logic_xor, io.lhs ^ io.rhs, 0.U) val out = Mux(add, adder_out, Mux(logic_and \|\| logic_xor, logic, minmax)) val wmask = FillInterleaved(8, io.mask) io.out := wmask & out \| ~wmask & io.lhs io.out_unmasked := out } File CSR.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{BitPat, Cat, Fill, Mux1H, PopCount, PriorityMux, RegEnable, UIntToOH, Valid, log2Ceil, log2Up} import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.LinkedHashMap import Instructions._ import CustomInstructions._ class MStatus extends Bundle { // not truly part of mstatus, but convenient val debug = Bool() val cease = Bool() val wfi = Bool() val isa = UInt(32.W) val dprv = UInt(PRV.SZ.W) // effective prv for data accesses val dv = Bool() // effective v for data accesses val prv = UInt(PRV.SZ.W) val v = Bool() val sd = Bool() val zero2 = UInt(23.W) val mpv = Bool() val gva = Bool() val mbe = Bool() val sbe = Bool() val sxl = UInt(2.W) val uxl = UInt(2.W) val sd_rv32 = Bool() val zero1 = UInt(8.W) val tsr = Bool() val tw = Bool() val tvm = Bool() val mxr = Bool() val sum = Bool() val mprv = Bool() val xs = UInt(2.W) val fs = UInt(2.W) val mpp = UInt(2.W) val vs = UInt(2.W) val spp = UInt(1.W) val mpie = Bool() val ube = Bool() val spie = Bool() val upie = Bool() val mie = Bool() val hie = Bool() val sie = Bool() val uie = Bool() } class MNStatus extends Bundle { val mpp = UInt(2.W) val zero3 = UInt(3.W) val mpv = Bool() val zero2 = UInt(3.W) val mie = Bool() val zero1 = UInt(3.W) } class HStatus extends Bundle { val zero6 = UInt(30.W) val vsxl = UInt(2.W) val zero5 = UInt(9.W) val vtsr = Bool() val vtw = Bool() val vtvm = Bool() val zero3 = UInt(2.W) val vgein = UInt(6.W) val zero2 = UInt(2.W) val hu = Bool() val spvp = Bool() val spv = Bool() val gva = Bool() val vsbe = Bool() val zero1 = UInt(5.W) } class DCSR extends Bundle { val xdebugver = UInt(2.W) val zero4 = UInt(2.W) val zero3 = UInt(12.W) val ebreakm = Bool() val ebreakh = Bool() val ebreaks = Bool() val ebreaku = Bool() val zero2 = Bool() val stopcycle = Bool() val stoptime = Bool() val cause = UInt(3.W) val v = Bool() val zero1 = UInt(2.W) val step = Bool() val prv = UInt(PRV.SZ.W) } class MIP(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val lip = Vec(coreParams.nLocalInterrupts, Bool()) val zero1 = Bool() val debug = Bool() // keep in sync with CSR.debugIntCause val rocc = Bool() val sgeip = Bool() val meip = Bool() val vseip = Bool() val seip = Bool() val ueip = Bool() val mtip = Bool() val vstip = Bool() val stip = Bool() val utip = Bool() val msip = Bool() val vssip = Bool() val ssip = Bool() val usip = Bool() } class Envcfg extends Bundle { val stce = Bool() // only for menvcfg/henvcfg val pbmte = Bool() // only for menvcfg/henvcfg val zero54 = UInt(54.W) val cbze = Bool() val cbcfe = Bool() val cbie = UInt(2.W) val zero3 = UInt(3.W) val fiom = Bool() def write(wdata: UInt) { val new_envcfg = wdata.asTypeOf(new Envcfg) fiom := new_envcfg.fiom // only FIOM is writable currently } } class PTBR(implicit p: Parameters) extends CoreBundle()(p) { def additionalPgLevels = mode.extract(log2Ceil(pgLevels-minPgLevels+1)-1, 0) def pgLevelsToMode(i: Int) = (xLen, i) match { case (32, 2) => 1 case (64, x) if x >= 3 && x <= 6 => x + 5 } val (modeBits, maxASIdBits) = xLen match { case 32 => (1, 9) case 64 => (4, 16) } require(modeBits + maxASIdBits + maxPAddrBits - pgIdxBits == xLen) val mode = UInt(modeBits.W) val asid = UInt(maxASIdBits.W) val ppn = UInt((maxPAddrBits - pgIdxBits).W) } object PRV { val SZ = 2 val U = 0 val S = 1 val H = 2 val M = 3 } object CSR { // commands val SZ = 3 def X = BitPat.dontCare(SZ) def N = 0.U(SZ.W) def R = 2.U(SZ.W) def I = 4.U(SZ.W) def W = 5.U(SZ.W) def S = 6.U(SZ.W) def C = 7.U(SZ.W) // mask a CSR cmd with a valid bit def maskCmd(valid: Bool, cmd: UInt): UInt = { // all commands less than CSR.I are treated by CSRFile as NOPs cmd & ~Mux(valid, 0.U, CSR.I) } val ADDRSZ = 12 def modeLSB: Int = 8 def mode(addr: Int): Int = (addr >> modeLSB) % (1 << PRV.SZ) def mode(addr: UInt): UInt = addr(modeLSB + PRV.SZ - 1, modeLSB) def busErrorIntCause = 128 def debugIntCause = 14 // keep in sync with MIP.debug def debugTriggerCause = { val res = debugIntCause require(!(Causes.all contains res)) res } def rnmiIntCause = 13 // NMI: Higher numbers = higher priority, must not reuse debugIntCause def rnmiBEUCause = 12 val firstCtr = CSRs.cycle val firstCtrH = CSRs.cycleh val firstHPC = CSRs.hpmcounter3 val firstHPCH = CSRs.hpmcounter3h val firstHPE = CSRs.mhpmevent3 val firstMHPC = CSRs.mhpmcounter3 val firstMHPCH = CSRs.mhpmcounter3h val firstHPM = 3 val nCtr = 32 val nHPM = nCtr - firstHPM val hpmWidth = 40 val maxPMPs = 16 } class PerfCounterIO(implicit p: Parameters) extends CoreBundle with HasCoreParameters { val eventSel = Output(UInt(xLen.W)) val inc = Input(UInt(log2Ceil(1+retireWidth).W)) } class TracedInstruction(implicit p: Parameters) extends CoreBundle { val valid = Bool() val iaddr = UInt(coreMaxAddrBits.W) val insn = UInt(iLen.W) val priv = UInt(3.W) val exception = Bool() val interrupt = Bool() val cause = UInt(xLen.W) val tval = UInt((coreMaxAddrBits max iLen).W) val wdata = Option.when(traceHasWdata)(UInt((vLen max xLen).W)) } class TraceAux extends Bundle { val enable = Bool() val stall = Bool() } class CSRDecodeIO(implicit p: Parameters) extends CoreBundle { val inst = Input(UInt(iLen.W)) def csr_addr = (inst >> 20)(CSR.ADDRSZ-1, 0) val fp_illegal = Output(Bool()) val vector_illegal = Output(Bool()) val fp_csr = Output(Bool()) val vector_csr = Output(Bool()) val rocc_illegal = Output(Bool()) val read_illegal = Output(Bool()) val write_illegal = Output(Bool()) val write_flush = Output(Bool()) val system_illegal = Output(Bool()) val virtual_access_illegal = Output(Bool()) val virtual_system_illegal = Output(Bool()) } class CSRFileIO(hasBeu: Boolean)(implicit p: Parameters) extends CoreBundle with HasCoreParameters { val ungated_clock = Input(Clock()) val interrupts = Input(new CoreInterrupts(hasBeu)) val hartid = Input(UInt(hartIdLen.W)) val rw = new Bundle { val addr = Input(UInt(CSR.ADDRSZ.W)) val cmd = Input(Bits(CSR.SZ.W)) val rdata = Output(Bits(xLen.W)) val wdata = Input(Bits(xLen.W)) } val decode = Vec(decodeWidth, new CSRDecodeIO) val csr_stall = Output(Bool()) // stall retire for wfi val rw_stall = Output(Bool()) // stall rw, rw will have no effect while rw_stall val eret = Output(Bool()) val singleStep = Output(Bool()) val status = Output(new MStatus()) val hstatus = Output(new HStatus()) val gstatus = Output(new MStatus()) val ptbr = Output(new PTBR()) val hgatp = Output(new PTBR()) val vsatp = Output(new PTBR()) val evec = Output(UInt(vaddrBitsExtended.W)) val exception = Input(Bool()) val retire = Input(UInt(log2Up(1+retireWidth).W)) val cause = Input(UInt(xLen.W)) val pc = Input(UInt(vaddrBitsExtended.W)) val tval = Input(UInt(vaddrBitsExtended.W)) val htval = Input(UInt(((maxSVAddrBits + 1) min xLen).W)) val mhtinst_read_pseudo = Input(Bool()) val gva = Input(Bool()) val time = Output(UInt(xLen.W)) val fcsr_rm = Output(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Flipped(Valid(Bits(FPConstants.FLAGS_SZ.W))) val set_fs_dirty = coreParams.haveFSDirty.option(Input(Bool())) val rocc_interrupt = Input(Bool()) val interrupt = Output(Bool()) val interrupt_cause = Output(UInt(xLen.W)) val bp = Output(Vec(nBreakpoints, new BP)) val pmp = Output(Vec(nPMPs, new PMP)) val counters = Vec(nPerfCounters, new PerfCounterIO) val csrw_counter = Output(UInt(CSR.nCtr.W)) val inhibit_cycle = Output(Bool()) val inst = Input(Vec(retireWidth, UInt(iLen.W))) val trace = Output(Vec(retireWidth, new TracedInstruction)) val mcontext = Output(UInt(coreParams.mcontextWidth.W)) val scontext = Output(UInt(coreParams.scontextWidth.W)) val fiom = Output(Bool()) val vector = usingVector.option(new Bundle { val vconfig = Output(new VConfig()) val vstart = Output(UInt(maxVLMax.log2.W)) val vxrm = Output(UInt(2.W)) val set_vs_dirty = Input(Bool()) val set_vconfig = Flipped(Valid(new VConfig)) val set_vstart = Flipped(Valid(vstart)) val set_vxsat = Input(Bool()) }) } class VConfig(implicit p: Parameters) extends CoreBundle { val vl = UInt((maxVLMax.log2 + 1).W) val vtype = new VType } object VType { def fromUInt(that: UInt, ignore_vill: Boolean = false)(implicit p: Parameters): VType = { val res = 0.U.asTypeOf(new VType) val in = that.asTypeOf(res) val vill = (in.max_vsew.U < in.vsew) \|\| !in.lmul_ok \|\| in.reserved =/= 0.U \|\| in.vill when (!vill \|\| ignore_vill.B) { res := in res.vsew := in.vsew(log2Ceil(1 + in.max_vsew) - 1, 0) } res.reserved := 0.U res.vill := vill res } def computeVL(avl: UInt, vtype: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool)(implicit p: Parameters): UInt = VType.fromUInt(vtype, true).vl(avl, currentVL, useCurrentVL, useMax, useZero) } class VType(implicit p: Parameters) extends CoreBundle { val vill = Bool() val reserved = UInt((xLen - 9).W) val vma = Bool() val vta = Bool() val vsew = UInt(3.W) val vlmul_sign = Bool() val vlmul_mag = UInt(2.W) def vlmul_signed: SInt = Cat(vlmul_sign, vlmul_mag).asSInt @deprecated("use vlmul_sign, vlmul_mag, or vlmul_signed", "RVV 0.9") def vlmul: UInt = vlmul_mag def max_vsew = log2Ceil(eLen/8) def max_vlmul = (1 << vlmul_mag.getWidth) - 1 def lmul_ok: Bool = Mux(this.vlmul_sign, this.vlmul_mag =/= 0.U && ~this.vlmul_mag < max_vsew.U - this.vsew, true.B) def minVLMax: Int = ((maxVLMax / eLen) >> ((1 << vlmul_mag.getWidth) - 1)) max 1 def vlMax: UInt = (maxVLMax.U >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).andNot((minVLMax-1).U) def vl(avl: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool): UInt = { val atLeastMaxVLMax = useMax \|\| Mux(useCurrentVL, currentVL >= maxVLMax.U, avl >= maxVLMax.U) val avl_lsbs = Mux(useCurrentVL, currentVL, avl)(maxVLMax.log2 - 1, 0) val atLeastVLMax = atLeastMaxVLMax \|\| (avl_lsbs & (-maxVLMax.S >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).asUInt.andNot((minVLMax-1).U)).orR val isZero = vill \|\| useZero Mux(!isZero && atLeastVLMax, vlMax, 0.U) \| Mux(!isZero && !atLeastVLMax, avl_lsbs, 0.U) } } class CSRFile( perfEventSets: EventSets = new EventSets(Seq()), customCSRs: Seq[CustomCSR] = Nil, roccCSRs: Seq[CustomCSR] = Nil, hasBeu: Boolean = false)(implicit p: Parameters) extends CoreModule()(p) with HasCoreParameters { val io = IO(new CSRFileIO(hasBeu) { val customCSRs = Vec(CSRFile.this.customCSRs.size, new CustomCSRIO) val roccCSRs = Vec(CSRFile.this.roccCSRs.size, new CustomCSRIO) }) io.rw_stall := false.B val reset_mstatus = WireDefault(0.U.asTypeOf(new MStatus())) reset_mstatus.mpp := PRV.M.U reset_mstatus.prv := PRV.M.U reset_mstatus.xs := (if (usingRoCC) 3.U else 0.U) val reg_mstatus = RegInit(reset_mstatus) val new_prv = WireDefault(reg_mstatus.prv) reg_mstatus.prv := legalizePrivilege(new_prv) val reset_dcsr = WireDefault(0.U.asTypeOf(new DCSR())) reset_dcsr.xdebugver := 1.U reset_dcsr.prv := PRV.M.U val reg_dcsr = RegInit(reset_dcsr) val (supported_interrupts, delegable_interrupts) = { val sup = Wire(new MIP) sup.usip := false.B sup.ssip := usingSupervisor.B sup.vssip := usingHypervisor.B sup.msip := true.B sup.utip := false.B sup.stip := usingSupervisor.B sup.vstip := usingHypervisor.B sup.mtip := true.B sup.ueip := false.B sup.seip := usingSupervisor.B sup.vseip := usingHypervisor.B sup.meip := true.B sup.sgeip := false.B sup.rocc := usingRoCC.B sup.debug := false.B sup.zero1 := false.B sup.lip foreach { _ := true.B } val supported_high_interrupts = if (io.interrupts.buserror.nonEmpty && !usingNMI) (BigInt(1) << CSR.busErrorIntCause).U else 0.U val del = WireDefault(sup) del.msip := false.B del.mtip := false.B del.meip := false.B (sup.asUInt \| supported_high_interrupts, del.asUInt) } val delegable_base_exceptions = Seq( Causes.misaligned_fetch, Causes.fetch_page_fault, Causes.breakpoint, Causes.load_page_fault, Causes.store_page_fault, Causes.misaligned_load, Causes.misaligned_store, Causes.illegal_instruction, Causes.user_ecall, ) val delegable_hypervisor_exceptions = Seq( Causes.virtual_supervisor_ecall, Causes.fetch_guest_page_fault, Causes.load_guest_page_fault, Causes.virtual_instruction, Causes.store_guest_page_fault, ) val delegable_exceptions = ( delegable_base_exceptions ++ (if (usingHypervisor) delegable_hypervisor_exceptions else Seq()) ).map(1 << _).sum.U val hs_delegable_exceptions = Seq( Causes.misaligned_fetch, Causes.fetch_access, Causes.illegal_instruction, Causes.breakpoint, Causes.misaligned_load, Causes.load_access, Causes.misaligned_store, Causes.store_access, Causes.user_ecall, Causes.fetch_page_fault, Causes.load_page_fault, Causes.store_page_fault).map(1 << _).sum.U val (hs_delegable_interrupts, mideleg_always_hs) = { val always = WireDefault(0.U.asTypeOf(new MIP())) always.vssip := usingHypervisor.B always.vstip := usingHypervisor.B always.vseip := usingHypervisor.B val deleg = WireDefault(always) deleg.lip.foreach { _ := usingHypervisor.B } (deleg.asUInt, always.asUInt) } val reg_debug = RegInit(false.B) val reg_dpc = Reg(UInt(vaddrBitsExtended.W)) val reg_dscratch0 = Reg(UInt(xLen.W)) val reg_dscratch1 = (p(DebugModuleKey).map(_.nDscratch).getOrElse(1) > 1).option(Reg(UInt(xLen.W))) val reg_singleStepped = Reg(Bool()) val reg_mcontext = (coreParams.mcontextWidth > 0).option(RegInit(0.U(coreParams.mcontextWidth.W))) val reg_scontext = (coreParams.scontextWidth > 0).option(RegInit(0.U(coreParams.scontextWidth.W))) val reg_tselect = Reg(UInt(log2Up(nBreakpoints).W)) val reg_bp = Reg(Vec(1 << log2Up(nBreakpoints), new BP)) val reg_pmp = Reg(Vec(nPMPs, new PMPReg)) val reg_mie = Reg(UInt(xLen.W)) val (reg_mideleg, read_mideleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingSupervisor.B, reg & delegable_interrupts \| mideleg_always_hs, 0.U)) } val (reg_medeleg, read_medeleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingSupervisor.B, reg & delegable_exceptions, 0.U)) } val reg_mip = Reg(new MIP) val reg_mepc = Reg(UInt(vaddrBitsExtended.W)) val reg_mcause = RegInit(0.U(xLen.W)) val reg_mtval = Reg(UInt(vaddrBitsExtended.W)) val reg_mtval2 = Reg(UInt(((maxSVAddrBits + 1) min xLen).W)) val reg_mscratch = Reg(Bits(xLen.W)) val mtvecWidth = paddrBits min xLen val reg_mtvec = mtvecInit match { case Some(addr) => RegInit(addr.U(mtvecWidth.W)) case None => Reg(UInt(mtvecWidth.W)) } val reset_mnstatus = WireDefault(0.U.asTypeOf(new MNStatus())) reset_mnstatus.mpp := PRV.M.U val reg_mnscratch = Reg(Bits(xLen.W)) val reg_mnepc = Reg(UInt(vaddrBitsExtended.W)) val reg_mncause = RegInit(0.U(xLen.W)) val reg_mnstatus = RegInit(reset_mnstatus) val reg_rnmie = RegInit(true.B) val nmie = reg_rnmie val reg_menvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val reg_senvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val reg_henvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val delegable_counters = ((BigInt(1) << (nPerfCounters + CSR.firstHPM)) - 1).U val (reg_mcounteren, read_mcounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingUser.B, reg & delegable_counters, 0.U)) } val (reg_scounteren, read_scounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingSupervisor.B, reg & delegable_counters, 0.U)) } val (reg_hideleg, read_hideleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_interrupts, 0.U)) } val (reg_hedeleg, read_hedeleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_exceptions, 0.U)) } val hs_delegable_counters = delegable_counters val (reg_hcounteren, read_hcounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_counters, 0.U)) } val reg_hstatus = RegInit(0.U.asTypeOf(new HStatus)) val reg_hgatp = Reg(new PTBR) val reg_htval = Reg(reg_mtval2.cloneType) val read_hvip = reg_mip.asUInt & hs_delegable_interrupts val read_hie = reg_mie & hs_delegable_interrupts val (reg_vstvec, read_vstvec) = { val reg = Reg(UInt(vaddrBitsExtended.W)) (reg, formTVec(reg).sextTo(xLen)) } val reg_vsstatus = Reg(new MStatus) val reg_vsscratch = Reg(Bits(xLen.W)) val reg_vsepc = Reg(UInt(vaddrBitsExtended.W)) val reg_vscause = Reg(Bits(xLen.W)) val reg_vstval = Reg(UInt(vaddrBitsExtended.W)) val reg_vsatp = Reg(new PTBR) val reg_sepc = Reg(UInt(vaddrBitsExtended.W)) val reg_scause = Reg(Bits(xLen.W)) val reg_stval = Reg(UInt(vaddrBitsExtended.W)) val reg_sscratch = Reg(Bits(xLen.W)) val reg_stvec = Reg(UInt((if (usingHypervisor) vaddrBitsExtended else vaddrBits).W)) val reg_satp = Reg(new PTBR) val reg_wfi = withClock(io.ungated_clock) { RegInit(false.B) } val reg_fflags = Reg(UInt(5.W)) val reg_frm = Reg(UInt(3.W)) val reg_vconfig = usingVector.option(Reg(new VConfig)) val reg_vstart = usingVector.option(Reg(UInt(maxVLMax.log2.W))) val reg_vxsat = usingVector.option(Reg(Bool())) val reg_vxrm = usingVector.option(Reg(UInt(io.vector.get.vxrm.getWidth.W))) val reg_mtinst_read_pseudo = Reg(Bool()) val reg_htinst_read_pseudo = Reg(Bool()) // XLEN=32: 0x00002000 // XLEN=64: 0x00003000 val Seq(read_mtinst, read_htinst) = Seq(reg_mtinst_read_pseudo, reg_htinst_read_pseudo).map(r => Cat(r, (xLen == 32).option(0.U).getOrElse(r), 0.U(12.W))) val reg_mcountinhibit = RegInit(0.U((CSR.firstHPM + nPerfCounters).W)) io.inhibit_cycle := reg_mcountinhibit(0) val reg_instret = WideCounter(64, io.retire, inhibit = reg_mcountinhibit(2)) val reg_cycle = if (enableCommitLog) WideCounter(64, io.retire, inhibit = reg_mcountinhibit(0)) else withClock(io.ungated_clock) { WideCounter(64, !io.csr_stall, inhibit = reg_mcountinhibit(0)) } val reg_hpmevent = io.counters.map(c => RegInit(0.U(xLen.W))) (io.counters zip reg_hpmevent) foreach { case (c, e) => c.eventSel := e } val reg_hpmcounter = io.counters.zipWithIndex.map { case (c, i) => WideCounter(CSR.hpmWidth, c.inc, reset = false, inhibit = reg_mcountinhibit(CSR.firstHPM+i)) } val mip = WireDefault(reg_mip) mip.lip := (io.interrupts.lip: Seq[Bool]) mip.mtip := io.interrupts.mtip mip.msip := io.interrupts.msip mip.meip := io.interrupts.meip // seip is the OR of reg_mip.seip and the actual line from the PLIC io.interrupts.seip.foreach { mip.seip := reg_mip.seip \|\| _ } // Simimlar sort of thing would apply if the PLIC had a VSEIP line: //io.interrupts.vseip.foreach { mip.vseip := reg_mip.vseip \|\| _ } mip.rocc := io.rocc_interrupt val read_mip = mip.asUInt & supported_interrupts val read_hip = read_mip & hs_delegable_interrupts val high_interrupts = (if (usingNMI) 0.U else io.interrupts.buserror.map(_ << CSR.busErrorIntCause).getOrElse(0.U)) val pending_interrupts = high_interrupts \| (read_mip & reg_mie) val d_interrupts = io.interrupts.debug << CSR.debugIntCause val (nmi_interrupts, nmiFlag) = io.interrupts.nmi.map(nmi => (((nmi.rnmi && reg_rnmie) << CSR.rnmiIntCause) \| io.interrupts.buserror.map(_ << CSR.rnmiBEUCause).getOrElse(0.U), !io.interrupts.debug && nmi.rnmi && reg_rnmie)).getOrElse(0.U, false.B) val m_interrupts = Mux(nmie && (reg_mstatus.prv <= PRV.S.U \|\| reg_mstatus.mie), ~(~pending_interrupts \| read_mideleg), 0.U) val s_interrupts = Mux(nmie && (reg_mstatus.v \|\| reg_mstatus.prv < PRV.S.U \|\| (reg_mstatus.prv === PRV.S.U && reg_mstatus.sie)), pending_interrupts & read_mideleg & ~read_hideleg, 0.U) val vs_interrupts = Mux(nmie && (reg_mstatus.v && (reg_mstatus.prv < PRV.S.U \|\| reg_mstatus.prv === PRV.S.U && reg_vsstatus.sie)), pending_interrupts & read_hideleg, 0.U) val (anyInterrupt, whichInterrupt) = chooseInterrupt(Seq(vs_interrupts, s_interrupts, m_interrupts, nmi_interrupts, d_interrupts)) val interruptMSB = BigInt(1) << (xLen-1) val interruptCause = interruptMSB.U + (nmiFlag << (xLen-2)) + whichInterrupt io.interrupt := (anyInterrupt && !io.singleStep \|\| reg_singleStepped) && !(reg_debug \|\| io.status.cease) io.interrupt_cause := interruptCause io.bp := reg_bp take nBreakpoints io.mcontext := reg_mcontext.getOrElse(0.U) io.scontext := reg_scontext.getOrElse(0.U) io.fiom := (reg_mstatus.prv < PRV.M.U && reg_menvcfg.fiom) \|\| (reg_mstatus.prv < PRV.S.U && reg_senvcfg.fiom) \|\| (reg_mstatus.v && reg_henvcfg.fiom) io.pmp := reg_pmp.map(PMP(_)) val isaMaskString = (if (usingMulDiv) "M" else "") + (if (usingAtomics) "A" else "") + (if (fLen >= 32) "F" else "") + (if (fLen >= 64) "D" else "") + (if (coreParams.hasV) "V" else "") + (if (usingCompressed) "C" else "") val isaString = (if (coreParams.useRVE) "E" else "I") + isaMaskString + (if (customIsaExt.isDefined \|\| usingRoCC) "X" else "") + (if (usingSupervisor) "S" else "") + (if (usingHypervisor) "H" else "") + (if (usingUser) "U" else "") val isaMax = (BigInt(log2Ceil(xLen) - 4) << (xLen-2)) \| isaStringToMask(isaString) val reg_misa = RegInit(isaMax.U) val read_mstatus = io.status.asUInt.extract(xLen-1,0) val read_mtvec = formTVec(reg_mtvec).padTo(xLen) val read_stvec = formTVec(reg_stvec).sextTo(xLen) val read_mapping = LinkedHashMap[Int,Bits]( CSRs.tselect -> reg_tselect, CSRs.tdata1 -> reg_bp(reg_tselect).control.asUInt, CSRs.tdata2 -> reg_bp(reg_tselect).address.sextTo(xLen), CSRs.tdata3 -> reg_bp(reg_tselect).textra.asUInt, CSRs.misa -> reg_misa, CSRs.mstatus -> read_mstatus, CSRs.mtvec -> read_mtvec, CSRs.mip -> read_mip, CSRs.mie -> reg_mie, CSRs.mscratch -> reg_mscratch, CSRs.mepc -> readEPC(reg_mepc).sextTo(xLen), CSRs.mtval -> reg_mtval.sextTo(xLen), CSRs.mcause -> reg_mcause, CSRs.mhartid -> io.hartid) val debug_csrs = if (!usingDebug) LinkedHashMap() else LinkedHashMap[Int,Bits]( CSRs.dcsr -> reg_dcsr.asUInt, CSRs.dpc -> readEPC(reg_dpc).sextTo(xLen), CSRs.dscratch0 -> reg_dscratch0.asUInt) ++ reg_dscratch1.map(r => CSRs.dscratch1 -> r) val read_mnstatus = WireInit(0.U.asTypeOf(new MNStatus())) read_mnstatus.mpp := reg_mnstatus.mpp read_mnstatus.mpv := reg_mnstatus.mpv read_mnstatus.mie := reg_rnmie val nmi_csrs = if (!usingNMI) LinkedHashMap() else LinkedHashMap[Int,Bits]( CustomCSRs.mnscratch -> reg_mnscratch, CustomCSRs.mnepc -> readEPC(reg_mnepc).sextTo(xLen), CustomCSRs.mncause -> reg_mncause, CustomCSRs.mnstatus -> read_mnstatus.asUInt) val context_csrs = LinkedHashMap[Int,Bits]() ++ reg_mcontext.map(r => CSRs.mcontext -> r) ++ reg_scontext.map(r => CSRs.scontext -> r) val read_fcsr = Cat(reg_frm, reg_fflags) val fp_csrs = LinkedHashMap[Int,Bits]() ++ usingFPU.option(CSRs.fflags -> reg_fflags) ++ usingFPU.option(CSRs.frm -> reg_frm) ++ (usingFPU \|\| usingVector).option(CSRs.fcsr -> read_fcsr) val read_vcsr = Cat(reg_vxrm.getOrElse(0.U), reg_vxsat.getOrElse(0.U)) val vector_csrs = if (!usingVector) LinkedHashMap() else LinkedHashMap[Int,Bits]( CSRs.vxsat -> reg_vxsat.get, CSRs.vxrm -> reg_vxrm.get, CSRs.vcsr -> read_vcsr, CSRs.vstart -> reg_vstart.get, CSRs.vtype -> reg_vconfig.get.vtype.asUInt, CSRs.vl -> reg_vconfig.get.vl, CSRs.vlenb -> (vLen / 8).U) read_mapping ++= debug_csrs read_mapping ++= nmi_csrs read_mapping ++= context_csrs read_mapping ++= fp_csrs read_mapping ++= vector_csrs if (coreParams.haveBasicCounters) { read_mapping += CSRs.mcountinhibit -> reg_mcountinhibit read_mapping += CSRs.mcycle -> reg_cycle read_mapping += CSRs.minstret -> reg_instret for (((e, c), i) <- (reg_hpmevent.padTo(CSR.nHPM, 0.U) zip reg_hpmcounter.map(x => x: UInt).padTo(CSR.nHPM, 0.U)).zipWithIndex) { read_mapping += (i + CSR.firstHPE) -> e // mhpmeventN read_mapping += (i + CSR.firstMHPC) -> c // mhpmcounterN read_mapping += (i + CSR.firstHPC) -> c // hpmcounterN if (xLen == 32) { read_mapping += (i + CSR.firstMHPCH) -> (c >> 32) // mhpmcounterNh read_mapping += (i + CSR.firstHPCH) -> (c >> 32) // hpmcounterNh } } if (usingUser) { read_mapping += CSRs.mcounteren -> read_mcounteren } read_mapping += CSRs.cycle -> reg_cycle read_mapping += CSRs.instret -> reg_instret if (xLen == 32) { read_mapping += CSRs.mcycleh -> (reg_cycle >> 32) read_mapping += CSRs.minstreth -> (reg_instret >> 32) read_mapping += CSRs.cycleh -> (reg_cycle >> 32) read_mapping += CSRs.instreth -> (reg_instret >> 32) } } if (usingUser) { read_mapping += CSRs.menvcfg -> reg_menvcfg.asUInt if (xLen == 32) read_mapping += CSRs.menvcfgh -> (reg_menvcfg.asUInt >> 32) } val sie_mask = { val sgeip_mask = WireInit(0.U.asTypeOf(new MIP)) sgeip_mask.sgeip := true.B read_mideleg & ~(hs_delegable_interrupts \| sgeip_mask.asUInt) } if (usingSupervisor) { val read_sie = reg_mie & sie_mask val read_sip = read_mip & sie_mask val read_sstatus = WireDefault(0.U.asTypeOf(new MStatus)) read_sstatus.sd := io.status.sd read_sstatus.uxl := io.status.uxl read_sstatus.sd_rv32 := io.status.sd_rv32 read_sstatus.mxr := io.status.mxr read_sstatus.sum := io.status.sum read_sstatus.xs := io.status.xs read_sstatus.fs := io.status.fs read_sstatus.vs := io.status.vs read_sstatus.spp := io.status.spp read_sstatus.spie := io.status.spie read_sstatus.sie := io.status.sie read_mapping += CSRs.sstatus -> (read_sstatus.asUInt)(xLen-1,0) read_mapping += CSRs.sip -> read_sip.asUInt read_mapping += CSRs.sie -> read_sie.asUInt read_mapping += CSRs.sscratch -> reg_sscratch read_mapping += CSRs.scause -> reg_scause read_mapping += CSRs.stval -> reg_stval.sextTo(xLen) read_mapping += CSRs.satp -> reg_satp.asUInt read_mapping += CSRs.sepc -> readEPC(reg_sepc).sextTo(xLen) read_mapping += CSRs.stvec -> read_stvec read_mapping += CSRs.scounteren -> read_scounteren read_mapping += CSRs.mideleg -> read_mideleg read_mapping += CSRs.medeleg -> read_medeleg read_mapping += CSRs.senvcfg -> reg_senvcfg.asUInt } val pmpCfgPerCSR = xLen / new PMPConfig().getWidth def pmpCfgIndex(i: Int) = (xLen / 32) * (i / pmpCfgPerCSR) if (reg_pmp.nonEmpty) { require(reg_pmp.size <= CSR.maxPMPs) val read_pmp = reg_pmp.padTo(CSR.maxPMPs, 0.U.asTypeOf(new PMP)) for (i <- 0 until read_pmp.size by pmpCfgPerCSR) read_mapping += (CSRs.pmpcfg0 + pmpCfgIndex(i)) -> read_pmp.map(_.cfg).slice(i, i + pmpCfgPerCSR).asUInt for ((pmp, i) <- read_pmp.zipWithIndex) read_mapping += (CSRs.pmpaddr0 + i) -> pmp.readAddr } // implementation-defined CSRs def generateCustomCSR(csr: CustomCSR, csr_io: CustomCSRIO) = { require(csr.mask >= 0 && csr.mask.bitLength <= xLen) require(!read_mapping.contains(csr.id)) val reg = csr.init.map(init => RegInit(init.U(xLen.W))).getOrElse(Reg(UInt(xLen.W))) val read = io.rw.cmd =/= CSR.N && io.rw.addr === csr.id.U csr_io.ren := read when (read && csr_io.stall) { io.rw_stall := true.B } read_mapping += csr.id -> reg reg } val reg_custom = customCSRs.zip(io.customCSRs).map(t => generateCustomCSR(t._1, t._2)) val reg_rocc = roccCSRs.zip(io.roccCSRs).map(t => generateCustomCSR(t._1, t._2)) if (usingHypervisor) { read_mapping += CSRs.mtinst -> read_mtinst read_mapping += CSRs.mtval2 -> reg_mtval2 val read_hstatus = io.hstatus.asUInt.extract(xLen-1,0) read_mapping += CSRs.hstatus -> read_hstatus read_mapping += CSRs.hedeleg -> read_hedeleg read_mapping += CSRs.hideleg -> read_hideleg read_mapping += CSRs.hcounteren-> read_hcounteren read_mapping += CSRs.hgatp -> reg_hgatp.asUInt read_mapping += CSRs.hip -> read_hip read_mapping += CSRs.hie -> read_hie read_mapping += CSRs.hvip -> read_hvip read_mapping += CSRs.hgeie -> 0.U read_mapping += CSRs.hgeip -> 0.U read_mapping += CSRs.htval -> reg_htval read_mapping += CSRs.htinst -> read_htinst read_mapping += CSRs.henvcfg -> reg_henvcfg.asUInt if (xLen == 32) read_mapping += CSRs.henvcfgh -> (reg_henvcfg.asUInt >> 32) val read_vsie = (read_hie & read_hideleg) >> 1 val read_vsip = (read_hip & read_hideleg) >> 1 val read_vsepc = readEPC(reg_vsepc).sextTo(xLen) val read_vstval = reg_vstval.sextTo(xLen) val read_vsstatus = io.gstatus.asUInt.extract(xLen-1,0) read_mapping += CSRs.vsstatus -> read_vsstatus read_mapping += CSRs.vsip -> read_vsip read_mapping += CSRs.vsie -> read_vsie read_mapping += CSRs.vsscratch -> reg_vsscratch read_mapping += CSRs.vscause -> reg_vscause read_mapping += CSRs.vstval -> read_vstval read_mapping += CSRs.vsatp -> reg_vsatp.asUInt read_mapping += CSRs.vsepc -> read_vsepc read_mapping += CSRs.vstvec -> read_vstvec } // mimpid, marchid, mvendorid, and mconfigptr are 0 unless overridden by customCSRs Seq(CSRs.mimpid, CSRs.marchid, CSRs.mvendorid, CSRs.mconfigptr).foreach(id => read_mapping.getOrElseUpdate(id, 0.U)) val decoded_addr = { val addr = Cat(io.status.v, io.rw.addr) val pats = for (((k, _), i) <- read_mapping.zipWithIndex) yield (BitPat(k.U), (0 until read_mapping.size).map(j => BitPat((i == j).B))) val decoded = DecodeLogic(addr, Seq.fill(read_mapping.size)(X), pats) val unvirtualized_mapping = (for (((k, _), v) <- read_mapping zip decoded) yield k -> v.asBool).toMap for ((k, v) <- unvirtualized_mapping) yield k -> { val alt: Option[Bool] = CSR.mode(k) match { // hcontext was assigned an unfortunate address; it lives where a // hypothetical vscontext will live. Exclude them from the S/VS remapping. // (on separate lines so scala-lint doesnt do something stupid) case _ if k == CSRs.scontext => None case _ if k == CSRs.hcontext => None // When V=1, if a corresponding VS CSR exists, access it instead... case PRV.H => unvirtualized_mapping.lift(k - (1 << CSR.modeLSB)) // ...and don't access the original S-mode version. case PRV.S => unvirtualized_mapping.contains(k + (1 << CSR.modeLSB)).option(false.B) case _ => None } alt.map(Mux(reg_mstatus.v, _, v)).getOrElse(v) } } val wdata = readModifyWriteCSR(io.rw.cmd, io.rw.rdata, io.rw.wdata) val system_insn = io.rw.cmd === CSR.I val hlsv = Seq(HLV_B, HLV_BU, HLV_H, HLV_HU, HLV_W, HLV_WU, HLV_D, HSV_B, HSV_H, HSV_W, HSV_D, HLVX_HU, HLVX_WU) val decode_table = Seq( ECALL-> List(Y,N,N,N,N,N,N,N,N), EBREAK-> List(N,Y,N,N,N,N,N,N,N), MRET-> List(N,N,Y,N,N,N,N,N,N), CEASE-> List(N,N,N,Y,N,N,N,N,N), WFI-> List(N,N,N,N,Y,N,N,N,N)) ++ usingDebug.option( DRET-> List(N,N,Y,N,N,N,N,N,N)) ++ usingNMI.option( MNRET-> List(N,N,Y,N,N,N,N,N,N)) ++ coreParams.haveCFlush.option(CFLUSH_D_L1-> List(N,N,N,N,N,N,N,N,N)) ++ usingSupervisor.option( SRET-> List(N,N,Y,N,N,N,N,N,N)) ++ usingVM.option( SFENCE_VMA-> List(N,N,N,N,N,Y,N,N,N)) ++ usingHypervisor.option( HFENCE_VVMA-> List(N,N,N,N,N,N,Y,N,N)) ++ usingHypervisor.option( HFENCE_GVMA-> List(N,N,N,N,N,N,N,Y,N)) ++ (if (usingHypervisor) hlsv.map(_-> List(N,N,N,N,N,N,N,N,Y)) else Seq()) val insn_call :: insn_break :: insn_ret :: insn_cease :: insn_wfi :: _ :: _ :: _ :: _ :: Nil = { val insn = ECALL.value.U \| (io.rw.addr << 20) DecodeLogic(insn, decode_table(0)._2.map(x=>X), decode_table).map(system_insn && _.asBool) } for (io_dec <- io.decode) { val addr = io_dec.inst(31, 20) def decodeAny(m: LinkedHashMap[Int,Bits]): Bool = m.map { case(k: Int, _: Bits) => addr === k.U }.reduce(_\|\|_) def decodeFast(s: Seq[Int]): Bool = DecodeLogic(addr, s.map(_.U), (read_mapping -- s).keys.toList.map(_.U)) val _ :: is_break :: is_ret :: _ :: is_wfi :: is_sfence :: is_hfence_vvma :: is_hfence_gvma :: is_hlsv :: Nil = DecodeLogic(io_dec.inst, decode_table(0)._2.map(x=>X), decode_table).map(_.asBool) val is_counter = (addr.inRange(CSR.firstCtr.U, (CSR.firstCtr + CSR.nCtr).U) \|\| addr.inRange(CSR.firstCtrH.U, (CSR.firstCtrH + CSR.nCtr).U)) val allow_wfi = (!usingSupervisor).B \|\| reg_mstatus.prv > PRV.S.U \|\| !reg_mstatus.tw && (!reg_mstatus.v \|\| !reg_hstatus.vtw) val allow_sfence_vma = (!usingVM).B \|\| reg_mstatus.prv > PRV.S.U \|\| !Mux(reg_mstatus.v, reg_hstatus.vtvm, reg_mstatus.tvm) val allow_hfence_vvma = (!usingHypervisor).B \|\| !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U) val allow_hlsv = (!usingHypervisor).B \|\| !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U \|\| reg_hstatus.hu) val allow_sret = (!usingSupervisor).B \|\| reg_mstatus.prv > PRV.S.U \|\| !Mux(reg_mstatus.v, reg_hstatus.vtsr, reg_mstatus.tsr) val counter_addr = addr(log2Ceil(read_mcounteren.getWidth)-1, 0) val allow_counter = (reg_mstatus.prv > PRV.S.U \|\| read_mcounteren(counter_addr)) && (!usingSupervisor.B \|\| reg_mstatus.prv >= PRV.S.U \|\| read_scounteren(counter_addr)) && (!usingHypervisor.B \|\| !reg_mstatus.v \|\| read_hcounteren(counter_addr)) io_dec.fp_illegal := io.status.fs === 0.U \|\| reg_mstatus.v && reg_vsstatus.fs === 0.U \|\| !reg_misa('f'-'a') io_dec.vector_illegal := io.status.vs === 0.U \|\| reg_mstatus.v && reg_vsstatus.vs === 0.U \|\| !reg_misa('v'-'a') io_dec.fp_csr := decodeFast(fp_csrs.keys.toList) io_dec.vector_csr := decodeFast(vector_csrs.keys.toList) io_dec.rocc_illegal := io.status.xs === 0.U \|\| reg_mstatus.v && reg_vsstatus.xs === 0.U \|\| !reg_misa('x'-'a') val csr_addr_legal = reg_mstatus.prv >= CSR.mode(addr) \|\| usingHypervisor.B && !reg_mstatus.v && reg_mstatus.prv === PRV.S.U && CSR.mode(addr) === PRV.H.U val csr_exists = decodeAny(read_mapping) io_dec.read_illegal := !csr_addr_legal \|\| !csr_exists \|\| ((addr === CSRs.satp.U \|\| addr === CSRs.hgatp.U) && !allow_sfence_vma) \|\| is_counter && !allow_counter \|\| decodeFast(debug_csrs.keys.toList) && !reg_debug \|\| decodeFast(vector_csrs.keys.toList) && io_dec.vector_illegal \|\| io_dec.fp_csr && io_dec.fp_illegal io_dec.write_illegal := addr(11,10).andR io_dec.write_flush := { val addr_m = addr \| (PRV.M.U << CSR.modeLSB) !(addr_m >= CSRs.mscratch.U && addr_m <= CSRs.mtval.U) } io_dec.system_illegal := !csr_addr_legal && !is_hlsv \|\| is_wfi && !allow_wfi \|\| is_ret && !allow_sret \|\| is_ret && addr(10) && addr(7) && !reg_debug \|\| (is_sfence \|\| is_hfence_gvma) && !allow_sfence_vma \|\| is_hfence_vvma && !allow_hfence_vvma \|\| is_hlsv && !allow_hlsv io_dec.virtual_access_illegal := reg_mstatus.v && csr_exists && ( CSR.mode(addr) === PRV.H.U \|\| is_counter && read_mcounteren(counter_addr) && (!read_hcounteren(counter_addr) \|\| !reg_mstatus.prv(0) && !read_scounteren(counter_addr)) \|\| CSR.mode(addr) === PRV.S.U && !reg_mstatus.prv(0) \|\| addr === CSRs.satp.U && reg_mstatus.prv(0) && reg_hstatus.vtvm) io_dec.virtual_system_illegal := reg_mstatus.v && ( is_hfence_vvma \|\| is_hfence_gvma \|\| is_hlsv \|\| is_wfi && (!reg_mstatus.prv(0) \|\| !reg_mstatus.tw && reg_hstatus.vtw) \|\| is_ret && CSR.mode(addr) === PRV.S.U && (!reg_mstatus.prv(0) \|\| reg_hstatus.vtsr) \|\| is_sfence && (!reg_mstatus.prv(0) \|\| reg_hstatus.vtvm)) } val cause = Mux(insn_call, Causes.user_ecall.U + Mux(reg_mstatus.prv(0) && reg_mstatus.v, PRV.H.U, reg_mstatus.prv), Mux[UInt](insn_break, Causes.breakpoint.U, io.cause)) val cause_lsbs = cause(log2Ceil(1 + CSR.busErrorIntCause)-1, 0) val cause_deleg_lsbs = cause(log2Ceil(xLen)-1,0) val causeIsDebugInt = cause(xLen-1) && cause_lsbs === CSR.debugIntCause.U val causeIsDebugTrigger = !cause(xLen-1) && cause_lsbs === CSR.debugTriggerCause.U val causeIsDebugBreak = !cause(xLen-1) && insn_break && Cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh, reg_dcsr.ebreaks, reg_dcsr.ebreaku)(reg_mstatus.prv) val trapToDebug = usingDebug.B && (reg_singleStepped \|\| causeIsDebugInt \|\| causeIsDebugTrigger \|\| causeIsDebugBreak \|\| reg_debug) val debugEntry = p(DebugModuleKey).map(_.debugEntry).getOrElse(BigInt(0x800)) val debugException = p(DebugModuleKey).map(_.debugException).getOrElse(BigInt(0x808)) val debugTVec = Mux(reg_debug, Mux(insn_break, debugEntry.U, debugException.U), debugEntry.U) val delegate = usingSupervisor.B && reg_mstatus.prv <= PRV.S.U && Mux(cause(xLen-1), read_mideleg(cause_deleg_lsbs), read_medeleg(cause_deleg_lsbs)) val delegateVS = reg_mstatus.v && delegate && Mux(cause(xLen-1), read_hideleg(cause_deleg_lsbs), read_hedeleg(cause_deleg_lsbs)) def mtvecBaseAlign = 2 def mtvecInterruptAlign = { require(reg_mip.getWidth <= xLen) log2Ceil(xLen) } val notDebugTVec = { val base = Mux(delegate, Mux(delegateVS, read_vstvec, read_stvec), read_mtvec) val interruptOffset = cause(mtvecInterruptAlign-1, 0) << mtvecBaseAlign val interruptVec = Cat(base >> (mtvecInterruptAlign + mtvecBaseAlign), interruptOffset) val doVector = base(0) && cause(cause.getWidth-1) && (cause_lsbs >> mtvecInterruptAlign) === 0.U Mux(doVector, interruptVec, base >> mtvecBaseAlign << mtvecBaseAlign) } val causeIsRnmiInt = cause(xLen-1) && cause(xLen-2) && (cause_lsbs === CSR.rnmiIntCause.U \|\| cause_lsbs === CSR.rnmiBEUCause.U) val causeIsRnmiBEU = cause(xLen-1) && cause(xLen-2) && cause_lsbs === CSR.rnmiBEUCause.U val causeIsNmi = causeIsRnmiInt val nmiTVecInt = io.interrupts.nmi.map(nmi => nmi.rnmi_interrupt_vector).getOrElse(0.U) val nmiTVecXcpt = io.interrupts.nmi.map(nmi => nmi.rnmi_exception_vector).getOrElse(0.U) val trapToNmiInt = usingNMI.B && causeIsNmi val trapToNmiXcpt = usingNMI.B && !nmie val trapToNmi = trapToNmiInt \|\| trapToNmiXcpt val nmiTVec = (Mux(causeIsNmi, nmiTVecInt, nmiTVecXcpt)>>1)<<1 val tvec = Mux(trapToDebug, debugTVec, Mux(trapToNmi, nmiTVec, notDebugTVec)) io.evec := tvec io.ptbr := reg_satp io.hgatp := reg_hgatp io.vsatp := reg_vsatp io.eret := insn_call \|\| insn_break \|\| insn_ret io.singleStep := reg_dcsr.step && !reg_debug io.status := reg_mstatus io.status.sd := io.status.fs.andR \|\| io.status.xs.andR \|\| io.status.vs.andR io.status.debug := reg_debug io.status.isa := reg_misa io.status.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U io.status.sxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U io.status.dprv := Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpp, reg_mstatus.prv) io.status.dv := reg_mstatus.v \|\| Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpv, false.B) io.status.sd_rv32 := (xLen == 32).B && io.status.sd io.status.mpv := reg_mstatus.mpv io.status.gva := reg_mstatus.gva io.hstatus := reg_hstatus io.hstatus.vsxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U io.gstatus := reg_vsstatus io.gstatus.sd := io.gstatus.fs.andR \|\| io.gstatus.xs.andR \|\| io.gstatus.vs.andR io.gstatus.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U io.gstatus.sd_rv32 := (xLen == 32).B && io.gstatus.sd val exception = insn_call \|\| insn_break \|\| io.exception assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1.U, "these conditions must be mutually exclusive") when (insn_wfi && !io.singleStep && !reg_debug) { reg_wfi := true.B } when (pending_interrupts.orR \|\| io.interrupts.debug \|\| exception) { reg_wfi := false.B } io.interrupts.nmi.map(nmi => when (nmi.rnmi) { reg_wfi := false.B } ) when (io.retire(0) \|\| exception) { reg_singleStepped := true.B } when (!io.singleStep) { reg_singleStepped := false.B } assert(!io.singleStep \|\| io.retire <= 1.U) assert(!reg_singleStepped \|\| io.retire === 0.U) val epc = formEPC(io.pc) val tval = Mux(insn_break, epc, io.tval) when (exception) { when (trapToDebug) { when (!reg_debug) { reg_mstatus.v := false.B reg_debug := true.B reg_dpc := epc reg_dcsr.cause := Mux(reg_singleStepped, 4.U, Mux(causeIsDebugInt, 3.U, Mux[UInt](causeIsDebugTrigger, 2.U, 1.U))) reg_dcsr.prv := trimPrivilege(reg_mstatus.prv) reg_dcsr.v := reg_mstatus.v new_prv := PRV.M.U } }.elsewhen (trapToNmiInt) { when (reg_rnmie) { reg_mstatus.v := false.B reg_mnstatus.mpv := reg_mstatus.v reg_rnmie := false.B reg_mnepc := epc reg_mncause := (BigInt(1) << (xLen-1)).U \| Mux(causeIsRnmiBEU, 3.U, 2.U) reg_mnstatus.mpp := trimPrivilege(reg_mstatus.prv) new_prv := PRV.M.U } }.elsewhen (delegateVS && nmie) { reg_mstatus.v := true.B reg_vsstatus.spp := reg_mstatus.prv reg_vsepc := epc reg_vscause := Mux(cause(xLen-1), Cat(cause(xLen-1, 2), 1.U(2.W)), cause) reg_vstval := tval reg_vsstatus.spie := reg_vsstatus.sie reg_vsstatus.sie := false.B new_prv := PRV.S.U }.elsewhen (delegate && nmie) { reg_mstatus.v := false.B reg_hstatus.spvp := Mux(reg_mstatus.v, reg_mstatus.prv(0),reg_hstatus.spvp) reg_hstatus.gva := io.gva reg_hstatus.spv := reg_mstatus.v reg_sepc := epc reg_scause := cause reg_stval := tval reg_htval := io.htval reg_htinst_read_pseudo := io.mhtinst_read_pseudo reg_mstatus.spie := reg_mstatus.sie reg_mstatus.spp := reg_mstatus.prv reg_mstatus.sie := false.B new_prv := PRV.S.U }.otherwise { reg_mstatus.v := false.B reg_mstatus.mpv := reg_mstatus.v reg_mstatus.gva := io.gva reg_mepc := epc reg_mcause := cause reg_mtval := tval reg_mtval2 := io.htval reg_mtinst_read_pseudo := io.mhtinst_read_pseudo reg_mstatus.mpie := reg_mstatus.mie reg_mstatus.mpp := trimPrivilege(reg_mstatus.prv) reg_mstatus.mie := false.B new_prv := PRV.M.U } } for (i <- 0 until supported_interrupts.getWidth) { val en = exception && (supported_interrupts & (BigInt(1) << i).U) =/= 0.U && cause === (BigInt(1) << (xLen - 1)).U + i.U val delegable = (delegable_interrupts & (BigInt(1) << i).U) =/= 0.U property.cover(en && !delegate, s"INTERRUPT_M_$i") property.cover(en && delegable && delegate, s"INTERRUPT_S_$i") } for (i <- 0 until xLen) { val supported_exceptions: BigInt = 0x8fe \| (if (usingCompressed && !coreParams.misaWritable) 0 else 1) \| (if (usingUser) 0x100 else 0) \| (if (usingSupervisor) 0x200 else 0) \| (if (usingVM) 0xb000 else 0) if (((supported_exceptions >> i) & 1) != 0) { val en = exception && cause === i.U val delegable = (delegable_exceptions & (BigInt(1) << i).U) =/= 0.U property.cover(en && !delegate, s"EXCEPTION_M_$i") property.cover(en && delegable && delegate, s"EXCEPTION_S_$i") } } when (insn_ret) { val ret_prv = WireInit(UInt(), DontCare) when (usingSupervisor.B && !io.rw.addr(9)) { when (!reg_mstatus.v) { reg_mstatus.sie := reg_mstatus.spie reg_mstatus.spie := true.B reg_mstatus.spp := PRV.U.U ret_prv := reg_mstatus.spp reg_mstatus.v := usingHypervisor.B && reg_hstatus.spv io.evec := readEPC(reg_sepc) reg_hstatus.spv := false.B }.otherwise { reg_vsstatus.sie := reg_vsstatus.spie reg_vsstatus.spie := true.B reg_vsstatus.spp := PRV.U.U ret_prv := reg_vsstatus.spp reg_mstatus.v := usingHypervisor.B io.evec := readEPC(reg_vsepc) } }.elsewhen (usingDebug.B && io.rw.addr(10) && io.rw.addr(7)) { ret_prv := reg_dcsr.prv reg_mstatus.v := usingHypervisor.B && reg_dcsr.v && reg_dcsr.prv <= PRV.S.U reg_debug := false.B io.evec := readEPC(reg_dpc) }.elsewhen (usingNMI.B && io.rw.addr(10) && !io.rw.addr(7)) { ret_prv := reg_mnstatus.mpp reg_mstatus.v := usingHypervisor.B && reg_mnstatus.mpv && reg_mnstatus.mpp <= PRV.S.U reg_rnmie := true.B io.evec := readEPC(reg_mnepc) }.otherwise { reg_mstatus.mie := reg_mstatus.mpie reg_mstatus.mpie := true.B reg_mstatus.mpp := legalizePrivilege(PRV.U.U) reg_mstatus.mpv := false.B ret_prv := reg_mstatus.mpp reg_mstatus.v := usingHypervisor.B && reg_mstatus.mpv && reg_mstatus.mpp <= PRV.S.U io.evec := readEPC(reg_mepc) } new_prv := ret_prv when (usingUser.B && ret_prv <= PRV.S.U) { reg_mstatus.mprv := false.B } } io.time := reg_cycle io.csr_stall := reg_wfi \|\| io.status.cease io.status.cease := RegEnable(true.B, false.B, insn_cease) io.status.wfi := reg_wfi for ((io, reg) <- io.customCSRs zip reg_custom) { io.wen := false.B io.wdata := wdata io.value := reg } for ((io, reg) <- io.roccCSRs zip reg_rocc) { io.wen := false.B io.wdata := wdata io.value := reg } io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v) // cover access to register val coverable_counters = read_mapping.filterNot { case (k, _) => k >= CSR.firstHPC + nPerfCounters && k < CSR.firstHPC + CSR.nHPM } coverable_counters.foreach( {case (k, v) => { when (!k.U(11,10).andR) { // Cover points for RW CSR registers property.cover(io.rw.cmd.isOneOf(CSR.W, CSR.S, CSR.C) && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field") } .otherwise { // Cover points for RO CSR registers property.cover(io.rw.cmd===CSR.R && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field") } }}) val set_vs_dirty = WireDefault(io.vector.map(_.set_vs_dirty).getOrElse(false.B)) io.vector.foreach { vio => when (set_vs_dirty) { assert(reg_mstatus.vs > 0.U) when (reg_mstatus.v) { reg_vsstatus.vs := 3.U } reg_mstatus.vs := 3.U } } val set_fs_dirty = WireDefault(io.set_fs_dirty.getOrElse(false.B)) if (coreParams.haveFSDirty) { when (set_fs_dirty) { assert(reg_mstatus.fs > 0.U) when (reg_mstatus.v) { reg_vsstatus.fs := 3.U } reg_mstatus.fs := 3.U } } io.fcsr_rm := reg_frm when (io.fcsr_flags.valid) { reg_fflags := reg_fflags \| io.fcsr_flags.bits set_fs_dirty := true.B } io.vector.foreach { vio => when (vio.set_vxsat) { reg_vxsat.get := true.B set_vs_dirty := true.B } } val csr_wen = io.rw.cmd.isOneOf(CSR.S, CSR.C, CSR.W) && !io.rw_stall io.csrw_counter := Mux(coreParams.haveBasicCounters.B && csr_wen && (io.rw.addr.inRange(CSRs.mcycle.U, (CSRs.mcycle + CSR.nCtr).U) \|\| io.rw.addr.inRange(CSRs.mcycleh.U, (CSRs.mcycleh + CSR.nCtr).U)), UIntToOH(io.rw.addr(log2Ceil(CSR.nCtr+nPerfCounters)-1, 0)), 0.U) when (csr_wen) { val scause_mask = ((BigInt(1) << (xLen-1)) + 31).U /* only implement 5 LSBs and MSB / val satp_valid_modes = 0 +: (minPgLevels to pgLevels).map(new PTBR().pgLevelsToMode(_)) when (decoded_addr(CSRs.mstatus)) { val new_mstatus = wdata.asTypeOf(new MStatus()) reg_mstatus.mie := new_mstatus.mie reg_mstatus.mpie := new_mstatus.mpie if (usingUser) { reg_mstatus.mprv := new_mstatus.mprv reg_mstatus.mpp := legalizePrivilege(new_mstatus.mpp) if (usingSupervisor) { reg_mstatus.spp := new_mstatus.spp reg_mstatus.spie := new_mstatus.spie reg_mstatus.sie := new_mstatus.sie reg_mstatus.tw := new_mstatus.tw reg_mstatus.tsr := new_mstatus.tsr } if (usingVM) { reg_mstatus.mxr := new_mstatus.mxr reg_mstatus.sum := new_mstatus.sum reg_mstatus.tvm := new_mstatus.tvm } if (usingHypervisor) { reg_mstatus.mpv := new_mstatus.mpv reg_mstatus.gva := new_mstatus.gva } } if (usingSupervisor \|\| usingFPU) reg_mstatus.fs := formFS(new_mstatus.fs) reg_mstatus.vs := formVS(new_mstatus.vs) } when (decoded_addr(CSRs.misa)) { val mask = isaStringToMask(isaMaskString).U(xLen.W) val f = wdata('f' - 'a') // suppress write if it would cause the next fetch to be misaligned when (!usingCompressed.B \|\| !io.pc(1) \|\| wdata('c' - 'a')) { if (coreParams.misaWritable) reg_misa := ~(~wdata \| (!f << ('d' - 'a'))) & mask \| reg_misa & ~mask } } when (decoded_addr(CSRs.mip)) { // MIP should be modified based on the value in reg_mip, not the value // in read_mip, since read_mip.seip is the OR of reg_mip.seip and // io.interrupts.seip. We don't want the value on the PLIC line to // inadvertently be OR'd into read_mip.seip. val new_mip = readModifyWriteCSR(io.rw.cmd, reg_mip.asUInt, io.rw.wdata).asTypeOf(new MIP) if (usingSupervisor) { reg_mip.ssip := new_mip.ssip reg_mip.stip := new_mip.stip reg_mip.seip := new_mip.seip } if (usingHypervisor) { reg_mip.vssip := new_mip.vssip } } when (decoded_addr(CSRs.mie)) { reg_mie := wdata & supported_interrupts } when (decoded_addr(CSRs.mepc)) { reg_mepc := formEPC(wdata) } when (decoded_addr(CSRs.mscratch)) { reg_mscratch := wdata } if (mtvecWritable) when (decoded_addr(CSRs.mtvec)) { reg_mtvec := wdata } when (decoded_addr(CSRs.mcause)) { reg_mcause := wdata & ((BigInt(1) << (xLen-1)) + (BigInt(1) << whichInterrupt.getWidth) - 1).U } when (decoded_addr(CSRs.mtval)) { reg_mtval := wdata } if (usingNMI) { val new_mnstatus = wdata.asTypeOf(new MNStatus()) when (decoded_addr(CustomCSRs.mnscratch)) { reg_mnscratch := wdata } when (decoded_addr(CustomCSRs.mnepc)) { reg_mnepc := formEPC(wdata) } when (decoded_addr(CustomCSRs.mncause)) { reg_mncause := wdata & ((BigInt(1) << (xLen-1)) + BigInt(3)).U } when (decoded_addr(CustomCSRs.mnstatus)) { reg_mnstatus.mpp := legalizePrivilege(new_mnstatus.mpp) reg_mnstatus.mpv := usingHypervisor.B && new_mnstatus.mpv reg_rnmie := reg_rnmie \| new_mnstatus.mie // mnie bit settable but not clearable from software } } for (((e, c), i) <- (reg_hpmevent zip reg_hpmcounter).zipWithIndex) { writeCounter(i + CSR.firstMHPC, c, wdata) when (decoded_addr(i + CSR.firstHPE)) { e := perfEventSets.maskEventSelector(wdata) } } if (coreParams.haveBasicCounters) { when (decoded_addr(CSRs.mcountinhibit)) { reg_mcountinhibit := wdata & ~2.U(xLen.W) } // mcountinhibit bit [1] is tied zero writeCounter(CSRs.mcycle, reg_cycle, wdata) writeCounter(CSRs.minstret, reg_instret, wdata) } if (usingFPU) { when (decoded_addr(CSRs.fflags)) { set_fs_dirty := true.B; reg_fflags := wdata } when (decoded_addr(CSRs.frm)) { set_fs_dirty := true.B; reg_frm := wdata } when (decoded_addr(CSRs.fcsr)) { set_fs_dirty := true.B reg_fflags := wdata reg_frm := wdata >> reg_fflags.getWidth } } if (usingDebug) { when (decoded_addr(CSRs.dcsr)) { val new_dcsr = wdata.asTypeOf(new DCSR()) reg_dcsr.step := new_dcsr.step reg_dcsr.ebreakm := new_dcsr.ebreakm if (usingSupervisor) reg_dcsr.ebreaks := new_dcsr.ebreaks if (usingUser) reg_dcsr.ebreaku := new_dcsr.ebreaku if (usingUser) reg_dcsr.prv := legalizePrivilege(new_dcsr.prv) if (usingHypervisor) reg_dcsr.v := new_dcsr.v } when (decoded_addr(CSRs.dpc)) { reg_dpc := formEPC(wdata) } when (decoded_addr(CSRs.dscratch0)) { reg_dscratch0 := wdata } reg_dscratch1.foreach { r => when (decoded_addr(CSRs.dscratch1)) { r := wdata } } } if (usingSupervisor) { when (decoded_addr(CSRs.sstatus)) { val new_sstatus = wdata.asTypeOf(new MStatus()) reg_mstatus.sie := new_sstatus.sie reg_mstatus.spie := new_sstatus.spie reg_mstatus.spp := new_sstatus.spp reg_mstatus.fs := formFS(new_sstatus.fs) reg_mstatus.vs := formVS(new_sstatus.vs) if (usingVM) { reg_mstatus.mxr := new_sstatus.mxr reg_mstatus.sum := new_sstatus.sum } } when (decoded_addr(CSRs.sip)) { val new_sip = ((read_mip & ~read_mideleg) \| (wdata & read_mideleg)).asTypeOf(new MIP()) reg_mip.ssip := new_sip.ssip } when (decoded_addr(CSRs.satp)) { if (usingVM) { val new_satp = wdata.asTypeOf(new PTBR()) when (new_satp.mode.isOneOf(satp_valid_modes.map(_.U))) { reg_satp.mode := new_satp.mode & satp_valid_modes.reduce(_\|_).U reg_satp.ppn := new_satp.ppn(ppnBits-1,0) if (asIdBits > 0) reg_satp.asid := new_satp.asid(asIdBits-1,0) } } } when (decoded_addr(CSRs.sie)) { reg_mie := (reg_mie & ~sie_mask) \| (wdata & sie_mask) } when (decoded_addr(CSRs.sscratch)) { reg_sscratch := wdata } when (decoded_addr(CSRs.sepc)) { reg_sepc := formEPC(wdata) } when (decoded_addr(CSRs.stvec)) { reg_stvec := wdata } when (decoded_addr(CSRs.scause)) { reg_scause := wdata & scause_mask } when (decoded_addr(CSRs.stval)) { reg_stval := wdata } when (decoded_addr(CSRs.mideleg)) { reg_mideleg := wdata } when (decoded_addr(CSRs.medeleg)) { reg_medeleg := wdata } when (decoded_addr(CSRs.scounteren)) { reg_scounteren := wdata } when (decoded_addr(CSRs.senvcfg)) { reg_senvcfg.write(wdata) } } if (usingHypervisor) { when (decoded_addr(CSRs.hstatus)) { val new_hstatus = wdata.asTypeOf(new HStatus()) reg_hstatus.gva := new_hstatus.gva reg_hstatus.spv := new_hstatus.spv reg_hstatus.spvp := new_hstatus.spvp reg_hstatus.hu := new_hstatus.hu reg_hstatus.vtvm := new_hstatus.vtvm reg_hstatus.vtw := new_hstatus.vtw reg_hstatus.vtsr := new_hstatus.vtsr reg_hstatus.vsxl := new_hstatus.vsxl } when (decoded_addr(CSRs.hideleg)) { reg_hideleg := wdata } when (decoded_addr(CSRs.hedeleg)) { reg_hedeleg := wdata } when (decoded_addr(CSRs.hgatp)) { val new_hgatp = wdata.asTypeOf(new PTBR()) val valid_modes = 0 +: (minPgLevels to pgLevels).map(new_hgatp.pgLevelsToMode(_)) when (new_hgatp.mode.isOneOf(valid_modes.map(_.U))) { reg_hgatp.mode := new_hgatp.mode & valid_modes.reduce(_\|_).U } reg_hgatp.ppn := Cat(new_hgatp.ppn(ppnBits-1,2), 0.U(2.W)) if (vmIdBits > 0) reg_hgatp.asid := new_hgatp.asid(vmIdBits-1,0) } when (decoded_addr(CSRs.hip)) { val new_hip = ((read_mip & ~hs_delegable_interrupts) \| (wdata & hs_delegable_interrupts)).asTypeOf(new MIP()) reg_mip.vssip := new_hip.vssip } when (decoded_addr(CSRs.hie)) { reg_mie := (reg_mie & ~hs_delegable_interrupts) \| (wdata & hs_delegable_interrupts) } when (decoded_addr(CSRs.hvip)) { val new_sip = ((read_mip & ~hs_delegable_interrupts) \| (wdata & hs_delegable_interrupts)).asTypeOf(new MIP()) reg_mip.vssip := new_sip.vssip reg_mip.vstip := new_sip.vstip reg_mip.vseip := new_sip.vseip } when (decoded_addr(CSRs.hcounteren)) { reg_hcounteren := wdata } when (decoded_addr(CSRs.htval)) { reg_htval := wdata } when (decoded_addr(CSRs.mtval2)) { reg_mtval2 := wdata } val write_mhtinst_read_pseudo = wdata(13) && (xLen == 32).option(true.B).getOrElse(wdata(12)) when(decoded_addr(CSRs.mtinst)) { reg_mtinst_read_pseudo := write_mhtinst_read_pseudo } when(decoded_addr(CSRs.htinst)) { reg_htinst_read_pseudo := write_mhtinst_read_pseudo } when (decoded_addr(CSRs.vsstatus)) { val new_vsstatus = wdata.asTypeOf(new MStatus()) reg_vsstatus.sie := new_vsstatus.sie reg_vsstatus.spie := new_vsstatus.spie reg_vsstatus.spp := new_vsstatus.spp reg_vsstatus.mxr := new_vsstatus.mxr reg_vsstatus.sum := new_vsstatus.sum reg_vsstatus.fs := formFS(new_vsstatus.fs) reg_vsstatus.vs := formVS(new_vsstatus.vs) } when (decoded_addr(CSRs.vsip)) { val new_vsip = ((read_hip & ~read_hideleg) \| ((wdata << 1) & read_hideleg)).asTypeOf(new MIP()) reg_mip.vssip := new_vsip.vssip } when (decoded_addr(CSRs.vsatp)) { val new_vsatp = wdata.asTypeOf(new PTBR()) val mode_ok = new_vsatp.mode.isOneOf(satp_valid_modes.map(_.U)) when (mode_ok) { reg_vsatp.mode := new_vsatp.mode & satp_valid_modes.reduce(_\|_).U } when (mode_ok \|\| !reg_mstatus.v) { reg_vsatp.ppn := new_vsatp.ppn(vpnBits.min(new_vsatp.ppn.getWidth)-1,0) if (asIdBits > 0) reg_vsatp.asid := new_vsatp.asid(asIdBits-1,0) } } when (decoded_addr(CSRs.vsie)) { reg_mie := (reg_mie & ~read_hideleg) \| ((wdata << 1) & read_hideleg) } when (decoded_addr(CSRs.vsscratch)) { reg_vsscratch := wdata } when (decoded_addr(CSRs.vsepc)) { reg_vsepc := formEPC(wdata) } when (decoded_addr(CSRs.vstvec)) { reg_vstvec := wdata } when (decoded_addr(CSRs.vscause)) { reg_vscause := wdata & scause_mask } when (decoded_addr(CSRs.vstval)) { reg_vstval := wdata } when (decoded_addr(CSRs.henvcfg)) { reg_henvcfg.write(wdata) } } if (usingUser) { when (decoded_addr(CSRs.mcounteren)) { reg_mcounteren := wdata } when (decoded_addr(CSRs.menvcfg)) { reg_menvcfg.write(wdata) } } if (nBreakpoints > 0) { when (decoded_addr(CSRs.tselect)) { reg_tselect := wdata } for ((bp, i) <- reg_bp.zipWithIndex) { when (i.U === reg_tselect && (!bp.control.dmode \|\| reg_debug)) { when (decoded_addr(CSRs.tdata2)) { bp.address := wdata } when (decoded_addr(CSRs.tdata3)) { if (coreParams.mcontextWidth > 0) { bp.textra.mselect := wdata(bp.textra.mselectPos) bp.textra.mvalue := wdata >> bp.textra.mvaluePos } if (coreParams.scontextWidth > 0) { bp.textra.sselect := wdata(bp.textra.sselectPos) bp.textra.svalue := wdata >> bp.textra.svaluePos } } when (decoded_addr(CSRs.tdata1)) { bp.control := wdata.asTypeOf(bp.control) val prevChain = if (i == 0) false.B else reg_bp(i-1).control.chain val prevDMode = if (i == 0) false.B else reg_bp(i-1).control.dmode val nextChain = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.chain val nextDMode = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.dmode val newBPC = readModifyWriteCSR(io.rw.cmd, bp.control.asUInt, io.rw.wdata).asTypeOf(bp.control) val dMode = newBPC.dmode && reg_debug && (prevDMode \|\| !prevChain) bp.control.dmode := dMode when (dMode \|\| (newBPC.action > 1.U)) { bp.control.action := newBPC.action }.otherwise { bp.control.action := 0.U } bp.control.chain := newBPC.chain && !(prevChain \|\| nextChain) && (dMode \|\| !nextDMode) } } } } reg_mcontext.foreach { r => when (decoded_addr(CSRs.mcontext)) { r := wdata }} reg_scontext.foreach { r => when (decoded_addr(CSRs.scontext)) { r := wdata }} if (reg_pmp.nonEmpty) for (((pmp, next), i) <- (reg_pmp zip (reg_pmp.tail :+ reg_pmp.last)).zipWithIndex) { require(xLen % pmp.cfg.getWidth == 0) when (decoded_addr(CSRs.pmpcfg0 + pmpCfgIndex(i)) && !pmp.cfgLocked) { val newCfg = (wdata >> ((i pmp.cfg.getWidth) % xLen)).asTypeOf(new PMPConfig()) pmp.cfg := newCfg // disallow unreadable but writable PMPs pmp.cfg.w := newCfg.w && newCfg.r // can't select a=NA4 with coarse-grained PMPs if (pmpGranularity.log2 > PMP.lgAlign) pmp.cfg.a := Cat(newCfg.a(1), newCfg.a.orR) } when (decoded_addr(CSRs.pmpaddr0 + i) && !pmp.addrLocked(next)) { pmp.addr := wdata } } def writeCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = { val mask = csr.mask.U(xLen.W) when (decoded_addr(csr.id)) { reg := (wdata & mask) \| (reg & ~mask) io.wen := true.B } } for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) { writeCustomCSR(io, csr, reg) } for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) { writeCustomCSR(io, csr, reg) } if (usingVector) { when (decoded_addr(CSRs.vstart)) { set_vs_dirty := true.B; reg_vstart.get := wdata } when (decoded_addr(CSRs.vxrm)) { set_vs_dirty := true.B; reg_vxrm.get := wdata } when (decoded_addr(CSRs.vxsat)) { set_vs_dirty := true.B; reg_vxsat.get := wdata } when (decoded_addr(CSRs.vcsr)) { set_vs_dirty := true.B reg_vxsat.get := wdata reg_vxrm.get := wdata >> 1 } } } def setCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = { val mask = csr.mask.U(xLen.W) when (io.set) { reg := (io.sdata & mask) \| (reg & ~mask) } } for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) { setCustomCSR(io, csr, reg) } for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) { setCustomCSR(io, csr, reg) } io.vector.map { vio => when (vio.set_vconfig.valid) { // user of CSRFile is responsible for set_vs_dirty in this case assert(vio.set_vconfig.bits.vl <= vio.set_vconfig.bits.vtype.vlMax) reg_vconfig.get := vio.set_vconfig.bits } when (vio.set_vstart.valid) { set_vs_dirty := true.B reg_vstart.get := vio.set_vstart.bits } vio.vstart := reg_vstart.get vio.vconfig := reg_vconfig.get vio.vxrm := reg_vxrm.get when (reset.asBool) { reg_vconfig.get.vl := 0.U reg_vconfig.get.vtype := 0.U.asTypeOf(new VType) reg_vconfig.get.vtype.vill := true.B } } when(reset.asBool) { reg_satp.mode := 0.U reg_vsatp.mode := 0.U reg_hgatp.mode := 0.U } if (!usingVM) { reg_satp.mode := 0.U reg_satp.ppn := 0.U reg_satp.asid := 0.U } if (!usingHypervisor) { reg_vsatp.mode := 0.U reg_vsatp.ppn := 0.U reg_vsatp.asid := 0.U reg_hgatp.mode := 0.U reg_hgatp.ppn := 0.U reg_hgatp.asid := 0.U } if (!(asIdBits > 0)) { reg_satp.asid := 0.U reg_vsatp.asid := 0.U } if (!(vmIdBits > 0)) { reg_hgatp.asid := 0.U } reg_vsstatus.xs := (if (usingRoCC) 3.U else 0.U) if (nBreakpoints <= 1) reg_tselect := 0.U for (bpc <- reg_bp map {_.control}) { bpc.ttype := bpc.tType.U bpc.maskmax := bpc.maskMax.U bpc.reserved := 0.U bpc.zero := 0.U bpc.h := false.B if (!usingSupervisor) bpc.s := false.B if (!usingUser) bpc.u := false.B if (!usingSupervisor && !usingUser) bpc.m := true.B when (reset.asBool) { bpc.action := 0.U bpc.dmode := false.B bpc.chain := false.B bpc.r := false.B bpc.w := false.B bpc.x := false.B } } for (bpx <- reg_bp map {_.textra}) { if (coreParams.mcontextWidth == 0) bpx.mselect := false.B if (coreParams.scontextWidth == 0) bpx.sselect := false.B } for (bp <- reg_bp drop nBreakpoints) bp := 0.U.asTypeOf(new BP()) for (pmp <- reg_pmp) { pmp.cfg.res := 0.U when (reset.asBool) { pmp.reset() } } for (((t, insn), i) <- (io.trace zip io.inst).zipWithIndex) { t.exception := io.retire >= i.U && exception t.valid := io.retire > i.U \|\| t.exception t.insn := insn t.iaddr := io.pc t.priv := Cat(reg_debug, reg_mstatus.prv) t.cause := cause t.interrupt := cause(xLen-1) t.tval := io.tval t.wdata.foreach(_ := DontCare) } def chooseInterrupt(masksIn: Seq[UInt]): (Bool, UInt) = { val nonstandard = supported_interrupts.getWidth-1 to 12 by -1 // MEI, MSI, MTI, SEI, SSI, STI, VSEI, VSSI, VSTI, UEI, USI, UTI val standard = Seq(11, 3, 7, 9, 1, 5, 10, 2, 6, 8, 0, 4) val priority = nonstandard ++ standard val masks = masksIn.reverse val any = masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => m(i))).reduce(_\|\|_) val which = PriorityMux(masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => (m(i), i.U)))) (any, which) } def readModifyWriteCSR(cmd: UInt, rdata: UInt, wdata: UInt) = { (Mux(cmd(1), rdata, 0.U) \| wdata) & ~Mux(cmd(1,0).andR, wdata, 0.U) } def legalizePrivilege(priv: UInt): UInt = if (usingSupervisor) Mux(priv === PRV.H.U, PRV.U.U, priv) else if (usingUser) Fill(2, priv(0)) else PRV.M.U def trimPrivilege(priv: UInt): UInt = if (usingSupervisor) priv else legalizePrivilege(priv) def writeCounter(lo: Int, ctr: WideCounter, wdata: UInt) = { if (xLen == 32) { val hi = lo + CSRs.mcycleh - CSRs.mcycle when (decoded_addr(lo)) { ctr := Cat(ctr(ctr.getWidth-1, 32), wdata) } when (decoded_addr(hi)) { ctr := Cat(wdata(ctr.getWidth-33, 0), ctr(31, 0)) } } else { when (decoded_addr(lo)) { ctr := wdata(ctr.getWidth-1, 0) } } } def formEPC(x: UInt) = ~(~x \| (if (usingCompressed) 1.U else 3.U)) def readEPC(x: UInt) = ~(~x \| Mux(reg_misa('c' - 'a'), 1.U, 3.U)) def formTVec(x: UInt) = x andNot Mux(x(0), ((((BigInt(1) << mtvecInterruptAlign) - 1) << mtvecBaseAlign) \| 2).U, 2.U) def isaStringToMask(s: String) = s.map(x => 1 << (x - 'A')).foldLeft(0)(_\|_) def formFS(fs: UInt) = if (coreParams.haveFSDirty) fs else Fill(2, fs.orR) def formVS(vs: UInt) = if (usingVector) vs else 0.U }	module Rocket_7( // @[RocketCore.scala:153:7] input clock, // @[RocketCore.scala:153:7] input reset, // @[RocketCore.scala:153:7] input [2:0] io_hartid, // @[RocketCore.scala:134:14] input io_interrupts_debug, // @[RocketCore.scala:134:14] input io_interrupts_mtip, // @[RocketCore.scala:134:14] input io_interrupts_msip, // @[RocketCore.scala:134:14] input io_interrupts_meip, // @[RocketCore.scala:134:14] input io_interrupts_seip, // @[RocketCore.scala:134:14] output io_imem_might_request, // @[RocketCore.scala:134:14] output io_imem_req_valid, // @[RocketCore.scala:134:14] output [39:0] io_imem_req_bits_pc, // @[RocketCore.scala:134:14] output io_imem_req_bits_speculative, // @[RocketCore.scala:134:14] output io_imem_sfence_valid, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_rs1, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_rs2, // @[RocketCore.scala:134:14] output [38:0] io_imem_sfence_bits_addr, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_asid, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_hv, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_hg, // @[RocketCore.scala:134:14] output io_imem_resp_ready, // @[RocketCore.scala:134:14] input io_imem_resp_valid, // @[RocketCore.scala:134:14] input [1:0] io_imem_resp_bits_btb_cfiType, // @[RocketCore.scala:134:14] input io_imem_resp_bits_btb_taken, // @[RocketCore.scala:134:14] input [1:0] io_imem_resp_bits_btb_mask, // @[RocketCore.scala:134:14] input io_imem_resp_bits_btb_bridx, // @[RocketCore.scala:134:14] input [38:0] io_imem_resp_bits_btb_target, // @[RocketCore.scala:134:14] input [4:0] io_imem_resp_bits_btb_entry, // @[RocketCore.scala:134:14] input [7:0] io_imem_resp_bits_btb_bht_history, // @[RocketCore.scala:134:14] input io_imem_resp_bits_btb_bht_value, // @[RocketCore.scala:134:14] input [39:0] io_imem_resp_bits_pc, // @[RocketCore.scala:134:14] input [31:0] io_imem_resp_bits_data, // @[RocketCore.scala:134:14] input [1:0] io_imem_resp_bits_mask, // @[RocketCore.scala:134:14] input io_imem_resp_bits_xcpt_pf_inst, // @[RocketCore.scala:134:14] input io_imem_resp_bits_xcpt_gf_inst, // @[RocketCore.scala:134:14] input io_imem_resp_bits_xcpt_ae_inst, // @[RocketCore.scala:134:14] input io_imem_resp_bits_replay, // @[RocketCore.scala:134:14] input io_imem_gpa_valid, // @[RocketCore.scala:134:14] input [39:0] io_imem_gpa_bits, // @[RocketCore.scala:134:14] input io_imem_gpa_is_pte, // @[RocketCore.scala:134:14] output io_imem_btb_update_valid, // @[RocketCore.scala:134:14] output [1:0] io_imem_btb_update_bits_prediction_cfiType, // @[RocketCore.scala:134:14] output io_imem_btb_update_bits_prediction_taken, // @[RocketCore.scala:134:14] output [1:0] io_imem_btb_update_bits_prediction_mask, // @[RocketCore.scala:134:14] output io_imem_btb_update_bits_prediction_bridx, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_prediction_target, // @[RocketCore.scala:134:14] output [4:0] io_imem_btb_update_bits_prediction_entry, // @[RocketCore.scala:134:14] output [7:0] io_imem_btb_update_bits_prediction_bht_history, // @[RocketCore.scala:134:14] output io_imem_btb_update_bits_prediction_bht_value, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_pc, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_target, // @[RocketCore.scala:134:14] output io_imem_btb_update_bits_isValid, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_br_pc, // @[RocketCore.scala:134:14] output [1:0] io_imem_btb_update_bits_cfiType, // @[RocketCore.scala:134:14] output io_imem_bht_update_valid, // @[RocketCore.scala:134:14] output [7:0] io_imem_bht_update_bits_prediction_history, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_prediction_value, // @[RocketCore.scala:134:14] output [38:0] io_imem_bht_update_bits_pc, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_branch, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_taken, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_mispredict, // @[RocketCore.scala:134:14] output io_imem_flush_icache, // @[RocketCore.scala:134:14] input [39:0] io_imem_npc, // @[RocketCore.scala:134:14] input io_imem_perf_acquire, // @[RocketCore.scala:134:14] input io_imem_perf_tlbMiss, // @[RocketCore.scala:134:14] output io_imem_progress, // @[RocketCore.scala:134:14] input io_dmem_req_ready, // @[RocketCore.scala:134:14] output io_dmem_req_valid, // @[RocketCore.scala:134:14] output [39:0] io_dmem_req_bits_addr, // @[RocketCore.scala:134:14] output [6:0] io_dmem_req_bits_tag, // @[RocketCore.scala:134:14] output [4:0] io_dmem_req_bits_cmd, // @[RocketCore.scala:134:14] output [1:0] io_dmem_req_bits_size, // @[RocketCore.scala:134:14] output io_dmem_req_bits_signed, // @[RocketCore.scala:134:14] output [1:0] io_dmem_req_bits_dprv, // @[RocketCore.scala:134:14] output io_dmem_req_bits_dv, // @[RocketCore.scala:134:14] output io_dmem_req_bits_no_resp, // @[RocketCore.scala:134:14] output io_dmem_s1_kill, // @[RocketCore.scala:134:14] output [63:0] io_dmem_s1_data_data, // @[RocketCore.scala:134:14] input io_dmem_s2_nack, // @[RocketCore.scala:134:14] input io_dmem_s2_nack_cause_raw, // @[RocketCore.scala:134:14] input io_dmem_s2_uncached, // @[RocketCore.scala:134:14] input [31:0] io_dmem_s2_paddr, // @[RocketCore.scala:134:14] input io_dmem_resp_valid, // @[RocketCore.scala:134:14] input [39:0] io_dmem_resp_bits_addr, // @[RocketCore.scala:134:14] input [6:0] io_dmem_resp_bits_tag, // @[RocketCore.scala:134:14] input [4:0] io_dmem_resp_bits_cmd, // @[RocketCore.scala:134:14] input [1:0] io_dmem_resp_bits_size, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_signed, // @[RocketCore.scala:134:14] input [1:0] io_dmem_resp_bits_dprv, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_dv, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_data, // @[RocketCore.scala:134:14] input [7:0] io_dmem_resp_bits_mask, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_replay, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_has_data, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_data_word_bypass, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_data_raw, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_store_data, // @[RocketCore.scala:134:14] input io_dmem_replay_next, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ma_ld, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ma_st, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_pf_ld, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_pf_st, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ae_ld, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ae_st, // @[RocketCore.scala:134:14] input [39:0] io_dmem_s2_gpa, // @[RocketCore.scala:134:14] input io_dmem_ordered, // @[RocketCore.scala:134:14] input io_dmem_store_pending, // @[RocketCore.scala:134:14] input io_dmem_perf_acquire, // @[RocketCore.scala:134:14] input io_dmem_perf_release, // @[RocketCore.scala:134:14] input io_dmem_perf_grant, // @[RocketCore.scala:134:14] input io_dmem_perf_tlbMiss, // @[RocketCore.scala:134:14] input io_dmem_perf_blocked, // @[RocketCore.scala:134:14] input io_dmem_perf_canAcceptStoreThenLoad, // @[RocketCore.scala:134:14] input io_dmem_perf_canAcceptStoreThenRMW, // @[RocketCore.scala:134:14] input io_dmem_perf_canAcceptLoadThenLoad, // @[RocketCore.scala:134:14] input io_dmem_perf_storeBufferEmptyAfterLoad, // @[RocketCore.scala:134:14] input io_dmem_perf_storeBufferEmptyAfterStore, // @[RocketCore.scala:134:14] output io_dmem_keep_clock_enabled, // @[RocketCore.scala:134:14] output [3:0] io_ptw_ptbr_mode, // @[RocketCore.scala:134:14] output [43:0] io_ptw_ptbr_ppn, // @[RocketCore.scala:134:14] output io_ptw_sfence_valid, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_rs1, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_rs2, // @[RocketCore.scala:134:14] output [38:0] io_ptw_sfence_bits_addr, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_asid, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_hv, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_hg, // @[RocketCore.scala:134:14] output io_ptw_status_debug, // @[RocketCore.scala:134:14] output io_ptw_status_cease, // @[RocketCore.scala:134:14] output io_ptw_status_wfi, // @[RocketCore.scala:134:14] output [31:0] io_ptw_status_isa, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_dprv, // @[RocketCore.scala:134:14] output io_ptw_status_dv, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_prv, // @[RocketCore.scala:134:14] output io_ptw_status_v, // @[RocketCore.scala:134:14] output io_ptw_status_sd, // @[RocketCore.scala:134:14] output io_ptw_status_mpv, // @[RocketCore.scala:134:14] output io_ptw_status_gva, // @[RocketCore.scala:134:14] output io_ptw_status_tsr, // @[RocketCore.scala:134:14] output io_ptw_status_tw, // @[RocketCore.scala:134:14] output io_ptw_status_tvm, // @[RocketCore.scala:134:14] output io_ptw_status_mxr, // @[RocketCore.scala:134:14] output io_ptw_status_sum, // @[RocketCore.scala:134:14] output io_ptw_status_mprv, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_fs, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_mpp, // @[RocketCore.scala:134:14] output io_ptw_status_spp, // @[RocketCore.scala:134:14] output io_ptw_status_mpie, // @[RocketCore.scala:134:14] output io_ptw_status_spie, // @[RocketCore.scala:134:14] output io_ptw_status_mie, // @[RocketCore.scala:134:14] output io_ptw_status_sie, // @[RocketCore.scala:134:14] output io_ptw_hstatus_spvp, // @[RocketCore.scala:134:14] output io_ptw_hstatus_spv, // @[RocketCore.scala:134:14] output io_ptw_hstatus_gva, // @[RocketCore.scala:134:14] output io_ptw_gstatus_debug, // @[RocketCore.scala:134:14] output io_ptw_gstatus_cease, // @[RocketCore.scala:134:14] output io_ptw_gstatus_wfi, // @[RocketCore.scala:134:14] output [31:0] io_ptw_gstatus_isa, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_dprv, // @[RocketCore.scala:134:14] output io_ptw_gstatus_dv, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_prv, // @[RocketCore.scala:134:14] output io_ptw_gstatus_v, // @[RocketCore.scala:134:14] output io_ptw_gstatus_sd, // @[RocketCore.scala:134:14] output [22:0] io_ptw_gstatus_zero2, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mpv, // @[RocketCore.scala:134:14] output io_ptw_gstatus_gva, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mbe, // @[RocketCore.scala:134:14] output io_ptw_gstatus_sbe, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_sxl, // @[RocketCore.scala:134:14] output [7:0] io_ptw_gstatus_zero1, // @[RocketCore.scala:134:14] output io_ptw_gstatus_tsr, // @[RocketCore.scala:134:14] output io_ptw_gstatus_tw, // @[RocketCore.scala:134:14] output io_ptw_gstatus_tvm, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mxr, // @[RocketCore.scala:134:14] output io_ptw_gstatus_sum, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mprv, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_fs, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_mpp, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_vs, // @[RocketCore.scala:134:14] output io_ptw_gstatus_spp, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mpie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_ube, // @[RocketCore.scala:134:14] output io_ptw_gstatus_spie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_upie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_hie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_sie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_uie, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_0_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_0_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_0_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_1_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_1_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_1_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_2_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_2_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_2_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_3_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_3_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_3_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_4_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_4_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_4_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_5_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_5_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_5_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_6_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_6_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_6_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_7_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_7_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_7_mask, // @[RocketCore.scala:134:14] input io_ptw_perf_pte_miss, // @[RocketCore.scala:134:14] input io_ptw_perf_pte_hit, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_0_ren, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_0_wen, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_0_value, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_1_ren, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_1_wen, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_1_value, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_2_ren, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_2_wen, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_2_value, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_3_ren, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_3_wen, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_3_value, // @[RocketCore.scala:134:14] input io_ptw_clock_enabled, // @[RocketCore.scala:134:14] output [2:0] io_fpu_hartid, // @[RocketCore.scala:134:14] output [63:0] io_fpu_time, // @[RocketCore.scala:134:14] output [31:0] io_fpu_inst, // @[RocketCore.scala:134:14] output [63:0] io_fpu_fromint_data, // @[RocketCore.scala:134:14] output [2:0] io_fpu_fcsr_rm, // @[RocketCore.scala:134:14] input io_fpu_fcsr_flags_valid, // @[RocketCore.scala:134:14] input [4:0] io_fpu_fcsr_flags_bits, // @[RocketCore.scala:134:14] input [63:0] io_fpu_store_data, // @[RocketCore.scala:134:14] input [63:0] io_fpu_toint_data, // @[RocketCore.scala:134:14] output io_fpu_ll_resp_val, // @[RocketCore.scala:134:14] output [2:0] io_fpu_ll_resp_type, // @[RocketCore.scala:134:14] output [4:0] io_fpu_ll_resp_tag, // @[RocketCore.scala:134:14] output [63:0] io_fpu_ll_resp_data, // @[RocketCore.scala:134:14] output io_fpu_valid, // @[RocketCore.scala:134:14] input io_fpu_fcsr_rdy, // @[RocketCore.scala:134:14] input io_fpu_nack_mem, // @[RocketCore.scala:134:14] input io_fpu_illegal_rm, // @[RocketCore.scala:134:14] output io_fpu_killx, // @[RocketCore.scala:134:14] output io_fpu_killm, // @[RocketCore.scala:134:14] input io_fpu_dec_ldst, // @[RocketCore.scala:134:14] input io_fpu_dec_wen, // @[RocketCore.scala:134:14] input io_fpu_dec_ren1, // @[RocketCore.scala:134:14] input io_fpu_dec_ren2, // @[RocketCore.scala:134:14] input io_fpu_dec_ren3, // @[RocketCore.scala:134:14] input io_fpu_dec_swap12, // @[RocketCore.scala:134:14] input io_fpu_dec_swap23, // @[RocketCore.scala:134:14] input [1:0] io_fpu_dec_typeTagIn, // @[RocketCore.scala:134:14] input [1:0] io_fpu_dec_typeTagOut, // @[RocketCore.scala:134:14] input io_fpu_dec_fromint, // @[RocketCore.scala:134:14] input io_fpu_dec_toint, // @[RocketCore.scala:134:14] input io_fpu_dec_fastpipe, // @[RocketCore.scala:134:14] input io_fpu_dec_fma, // @[RocketCore.scala:134:14] input io_fpu_dec_div, // @[RocketCore.scala:134:14] input io_fpu_dec_sqrt, // @[RocketCore.scala:134:14] input io_fpu_dec_wflags, // @[RocketCore.scala:134:14] input io_fpu_dec_vec, // @[RocketCore.scala:134:14] input io_fpu_sboard_set, // @[RocketCore.scala:134:14] input io_fpu_sboard_clr, // @[RocketCore.scala:134:14] input [4:0] io_fpu_sboard_clra, // @[RocketCore.scala:134:14] output io_fpu_keep_clock_enabled, // @[RocketCore.scala:134:14] output io_trace_insns_0_valid, // @[RocketCore.scala:134:14] output [39:0] io_trace_insns_0_iaddr, // @[RocketCore.scala:134:14] output [31:0] io_trace_insns_0_insn, // @[RocketCore.scala:134:14] output [2:0] io_trace_insns_0_priv, // @[RocketCore.scala:134:14] output io_trace_insns_0_exception, // @[RocketCore.scala:134:14] output io_trace_insns_0_interrupt, // @[RocketCore.scala:134:14] output [63:0] io_trace_insns_0_cause, // @[RocketCore.scala:134:14] output [39:0] io_trace_insns_0_tval, // @[RocketCore.scala:134:14] output [63:0] io_trace_time, // @[RocketCore.scala:134:14] output io_bpwatch_0_valid_0, // @[RocketCore.scala:134:14] output [2:0] io_bpwatch_0_action, // @[RocketCore.scala:134:14] output io_wfi // @[RocketCore.scala:134:14] ); wire ll_arb_io_out_ready; // @[RocketCore.scala:782:23, :809:44, :810:25] wire id_ctrl_fence; // @[RocketCore.scala:321:21] wire id_ctrl_rocc; // @[RocketCore.scala:321:21] wire io_imem_sfence_bits_hg_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_bits_hv_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_bits_asid_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_sfence_bits_addr_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_bits_rs2_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_bits_rs1_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_valid_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_btb_update_bits_pc_0; // @[RocketCore.scala:153:7] wire _ll_arb_io_in_0_ready; // @[RocketCore.scala:776:22] wire _ll_arb_io_out_valid; // @[RocketCore.scala:776:22] wire [4:0] _ll_arb_io_out_bits_tag; // @[RocketCore.scala:776:22] wire _div_io_req_ready; // @[RocketCore.scala:511:19] wire _div_io_resp_valid; // @[RocketCore.scala:511:19] wire [63:0] _div_io_resp_bits_data; // @[RocketCore.scala:511:19] wire [4:0] _div_io_resp_bits_tag; // @[RocketCore.scala:511:19] wire [63:0] _alu_io_adder_out; // @[RocketCore.scala:504:19] wire _alu_io_cmp_out; // @[RocketCore.scala:504:19] wire _bpu_io_xcpt_if; // @[RocketCore.scala:414:19] wire _bpu_io_xcpt_ld; // @[RocketCore.scala:414:19] wire _bpu_io_xcpt_st; // @[RocketCore.scala:414:19] wire _bpu_io_debug_if; // @[RocketCore.scala:414:19] wire _bpu_io_debug_ld; // @[RocketCore.scala:414:19] wire _bpu_io_debug_st; // @[RocketCore.scala:414:19] wire _bpu_io_bpwatch_0_rvalid_0; // @[RocketCore.scala:414:19] wire _bpu_io_bpwatch_0_wvalid_0; // @[RocketCore.scala:414:19] wire _bpu_io_bpwatch_0_ivalid_0; // @[RocketCore.scala:414:19] wire [63:0] _csr_io_rw_rdata; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_fp_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_fp_csr; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_read_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_write_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_write_flush; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_system_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_virtual_access_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_virtual_system_illegal; // @[RocketCore.scala:341:19] wire _csr_io_csr_stall; // @[RocketCore.scala:341:19] wire _csr_io_eret; // @[RocketCore.scala:341:19] wire _csr_io_singleStep; // @[RocketCore.scala:341:19] wire _csr_io_status_debug; // @[RocketCore.scala:341:19] wire _csr_io_status_cease; // @[RocketCore.scala:341:19] wire _csr_io_status_wfi; // @[RocketCore.scala:341:19] wire [31:0] _csr_io_status_isa; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_dprv; // @[RocketCore.scala:341:19] wire _csr_io_status_dv; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_prv; // @[RocketCore.scala:341:19] wire _csr_io_status_v; // @[RocketCore.scala:341:19] wire _csr_io_status_sd; // @[RocketCore.scala:341:19] wire _csr_io_status_mpv; // @[RocketCore.scala:341:19] wire _csr_io_status_gva; // @[RocketCore.scala:341:19] wire _csr_io_status_tsr; // @[RocketCore.scala:341:19] wire _csr_io_status_tw; // @[RocketCore.scala:341:19] wire _csr_io_status_tvm; // @[RocketCore.scala:341:19] wire _csr_io_status_mxr; // @[RocketCore.scala:341:19] wire _csr_io_status_sum; // @[RocketCore.scala:341:19] wire _csr_io_status_mprv; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_fs; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_mpp; // @[RocketCore.scala:341:19] wire _csr_io_status_spp; // @[RocketCore.scala:341:19] wire _csr_io_status_mpie; // @[RocketCore.scala:341:19] wire _csr_io_status_spie; // @[RocketCore.scala:341:19] wire _csr_io_status_mie; // @[RocketCore.scala:341:19] wire _csr_io_status_sie; // @[RocketCore.scala:341:19] wire [39:0] _csr_io_evec; // @[RocketCore.scala:341:19] wire [63:0] _csr_io_time; // @[RocketCore.scala:341:19] wire _csr_io_interrupt; // @[RocketCore.scala:341:19] wire [63:0] _csr_io_interrupt_cause; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_dmode; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_action; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_bp_0_control_tmatch; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_m; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_s; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_u; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_x; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_w; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_r; // @[RocketCore.scala:341:19] wire [38:0] _csr_io_bp_0_address; // @[RocketCore.scala:341:19] wire [47:0] _csr_io_bp_0_textra_pad2; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_textra_pad1; // @[RocketCore.scala:341:19] wire _csr_io_inhibit_cycle; // @[RocketCore.scala:341:19] wire _csr_io_trace_0_valid; // @[RocketCore.scala:341:19] wire [39:0] _csr_io_trace_0_iaddr; // @[RocketCore.scala:341:19] wire [31:0] _csr_io_trace_0_insn; // @[RocketCore.scala:341:19] wire [2:0] _csr_io_trace_0_priv; // @[RocketCore.scala:341:19] wire _csr_io_trace_0_exception; // @[RocketCore.scala:341:19] wire [39:0] _ibuf_io_pc; // @[RocketCore.scala:311:20] wire [1:0] _ibuf_io_btb_resp_cfiType; // @[RocketCore.scala:311:20] wire _ibuf_io_btb_resp_taken; // @[RocketCore.scala:311:20] wire [1:0] _ibuf_io_btb_resp_mask; // @[RocketCore.scala:311:20] wire _ibuf_io_btb_resp_bridx; // @[RocketCore.scala:311:20] wire [38:0] _ibuf_io_btb_resp_target; // @[RocketCore.scala:311:20] wire [4:0] _ibuf_io_btb_resp_entry; // @[RocketCore.scala:311:20] wire [7:0] _ibuf_io_btb_resp_bht_history; // @[RocketCore.scala:311:20] wire _ibuf_io_btb_resp_bht_value; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt0_pf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt0_gf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt0_ae_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt1_pf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt1_gf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt1_ae_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_replay; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala:311:20] wire [31:0] _ibuf_io_inst_0_bits_inst_bits; // @[RocketCore.scala:311:20] wire [4:0] _ibuf_io_inst_0_bits_inst_rs1; // @[RocketCore.scala:311:20] wire [31:0] _ibuf_io_inst_0_bits_raw; // @[RocketCore.scala:311:20] wire [2:0] io_hartid_0 = io_hartid; // @[RocketCore.scala:153:7] wire io_interrupts_debug_0 = io_interrupts_debug; // @[RocketCore.scala:153:7] wire io_interrupts_mtip_0 = io_interrupts_mtip; // @[RocketCore.scala:153:7] wire io_interrupts_msip_0 = io_interrupts_msip; // @[RocketCore.scala:153:7] wire io_interrupts_meip_0 = io_interrupts_meip; // @[RocketCore.scala:153:7] wire io_interrupts_seip_0 = io_interrupts_seip; // @[RocketCore.scala:153:7] wire io_imem_resp_valid_0 = io_imem_resp_valid; // @[RocketCore.scala:153:7] wire [1:0] io_imem_resp_bits_btb_cfiType_0 = io_imem_resp_bits_btb_cfiType; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_btb_taken_0 = io_imem_resp_bits_btb_taken; // @[RocketCore.scala:153:7] wire [1:0] io_imem_resp_bits_btb_mask_0 = io_imem_resp_bits_btb_mask; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_btb_bridx_0 = io_imem_resp_bits_btb_bridx; // @[RocketCore.scala:153:7] wire [38:0] io_imem_resp_bits_btb_target_0 = io_imem_resp_bits_btb_target; // @[RocketCore.scala:153:7] wire [4:0] io_imem_resp_bits_btb_entry_0 = io_imem_resp_bits_btb_entry; // @[RocketCore.scala:153:7] wire [7:0] io_imem_resp_bits_btb_bht_history_0 = io_imem_resp_bits_btb_bht_history; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_btb_bht_value_0 = io_imem_resp_bits_btb_bht_value; // @[RocketCore.scala:153:7] wire [39:0] io_imem_resp_bits_pc_0 = io_imem_resp_bits_pc; // @[RocketCore.scala:153:7] wire [31:0] io_imem_resp_bits_data_0 = io_imem_resp_bits_data; // @[RocketCore.scala:153:7] wire [1:0] io_imem_resp_bits_mask_0 = io_imem_resp_bits_mask; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_xcpt_pf_inst_0 = io_imem_resp_bits_xcpt_pf_inst; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_xcpt_gf_inst_0 = io_imem_resp_bits_xcpt_gf_inst; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_xcpt_ae_inst_0 = io_imem_resp_bits_xcpt_ae_inst; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_replay_0 = io_imem_resp_bits_replay; // @[RocketCore.scala:153:7] wire io_imem_gpa_valid_0 = io_imem_gpa_valid; // @[RocketCore.scala:153:7] wire [39:0] io_imem_gpa_bits_0 = io_imem_gpa_bits; // @[RocketCore.scala:153:7] wire io_imem_gpa_is_pte_0 = io_imem_gpa_is_pte; // @[RocketCore.scala:153:7] wire [39:0] io_imem_npc_0 = io_imem_npc; // @[RocketCore.scala:153:7] wire io_imem_perf_acquire_0 = io_imem_perf_acquire; // @[RocketCore.scala:153:7] wire io_imem_perf_tlbMiss_0 = io_imem_perf_tlbMiss; // @[RocketCore.scala:153:7] wire io_dmem_req_ready_0 = io_dmem_req_ready; // @[RocketCore.scala:153:7] wire io_dmem_s2_nack_0 = io_dmem_s2_nack; // @[RocketCore.scala:153:7] wire io_dmem_s2_nack_cause_raw_0 = io_dmem_s2_nack_cause_raw; // @[RocketCore.scala:153:7] wire io_dmem_s2_uncached_0 = io_dmem_s2_uncached; // @[RocketCore.scala:153:7] wire [31:0] io_dmem_s2_paddr_0 = io_dmem_s2_paddr; // @[RocketCore.scala:153:7] wire io_dmem_resp_valid_0 = io_dmem_resp_valid; // @[RocketCore.scala:153:7] wire [39:0] io_dmem_resp_bits_addr_0 = io_dmem_resp_bits_addr; // @[RocketCore.scala:153:7] wire [6:0] io_dmem_resp_bits_tag_0 = io_dmem_resp_bits_tag; // @[RocketCore.scala:153:7] wire [4:0] io_dmem_resp_bits_cmd_0 = io_dmem_resp_bits_cmd; // @[RocketCore.scala:153:7] wire [1:0] io_dmem_resp_bits_size_0 = io_dmem_resp_bits_size; // @[RocketCore.scala:153:7] wire io_dmem_resp_bits_signed_0 = io_dmem_resp_bits_signed; // @[RocketCore.scala:153:7] wire [1:0] io_dmem_resp_bits_dprv_0 = io_dmem_resp_bits_dprv; // @[RocketCore.scala:153:7] wire io_dmem_resp_bits_dv_0 = io_dmem_resp_bits_dv; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_resp_bits_data_0 = io_dmem_resp_bits_data; // @[RocketCore.scala:153:7] wire [7:0] io_dmem_resp_bits_mask_0 = io_dmem_resp_bits_mask; // @[RocketCore.scala:153:7] wire io_dmem_resp_bits_replay_0 = io_dmem_resp_bits_replay; // @[RocketCore.scala:153:7] wire io_dmem_resp_bits_has_data_0 = io_dmem_resp_bits_has_data; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_resp_bits_data_word_bypass_0 = io_dmem_resp_bits_data_word_bypass; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_resp_bits_data_raw_0 = io_dmem_resp_bits_data_raw; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_resp_bits_store_data_0 = io_dmem_resp_bits_store_data; // @[RocketCore.scala:153:7] wire io_dmem_replay_next_0 = io_dmem_replay_next; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_ma_ld_0 = io_dmem_s2_xcpt_ma_ld; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_ma_st_0 = io_dmem_s2_xcpt_ma_st; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_pf_ld_0 = io_dmem_s2_xcpt_pf_ld; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_pf_st_0 = io_dmem_s2_xcpt_pf_st; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_ae_ld_0 = io_dmem_s2_xcpt_ae_ld; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_ae_st_0 = io_dmem_s2_xcpt_ae_st; // @[RocketCore.scala:153:7] wire [39:0] io_dmem_s2_gpa_0 = io_dmem_s2_gpa; // @[RocketCore.scala:153:7] wire io_dmem_ordered_0 = io_dmem_ordered; // @[RocketCore.scala:153:7] wire io_dmem_store_pending_0 = io_dmem_store_pending; // @[RocketCore.scala:153:7] wire io_dmem_perf_acquire_0 = io_dmem_perf_acquire; // @[RocketCore.scala:153:7] wire io_dmem_perf_release_0 = io_dmem_perf_release; // @[RocketCore.scala:153:7] wire io_dmem_perf_grant_0 = io_dmem_perf_grant; // @[RocketCore.scala:153:7] wire io_dmem_perf_tlbMiss_0 = io_dmem_perf_tlbMiss; // @[RocketCore.scala:153:7] wire io_dmem_perf_blocked_0 = io_dmem_perf_blocked; // @[RocketCore.scala:153:7] wire io_dmem_perf_canAcceptStoreThenLoad_0 = io_dmem_perf_canAcceptStoreThenLoad; // @[RocketCore.scala:153:7] wire io_dmem_perf_canAcceptStoreThenRMW_0 = io_dmem_perf_canAcceptStoreThenRMW; // @[RocketCore.scala:153:7] wire io_dmem_perf_canAcceptLoadThenLoad_0 = io_dmem_perf_canAcceptLoadThenLoad; // @[RocketCore.scala:153:7] wire io_dmem_perf_storeBufferEmptyAfterLoad_0 = io_dmem_perf_storeBufferEmptyAfterLoad; // @[RocketCore.scala:153:7] wire io_dmem_perf_storeBufferEmptyAfterStore_0 = io_dmem_perf_storeBufferEmptyAfterStore; // @[RocketCore.scala:153:7] wire io_ptw_perf_pte_miss_0 = io_ptw_perf_pte_miss; // @[RocketCore.scala:153:7] wire io_ptw_perf_pte_hit_0 = io_ptw_perf_pte_hit; // @[RocketCore.scala:153:7] wire io_ptw_clock_enabled_0 = io_ptw_clock_enabled; // @[RocketCore.scala:153:7] wire io_fpu_fcsr_flags_valid_0 = io_fpu_fcsr_flags_valid; // @[RocketCore.scala:153:7] wire [4:0] io_fpu_fcsr_flags_bits_0 = io_fpu_fcsr_flags_bits; // @[RocketCore.scala:153:7] wire [63:0] io_fpu_store_data_0 = io_fpu_store_data; // @[RocketCore.scala:153:7] wire [63:0] io_fpu_toint_data_0 = io_fpu_toint_data; // @[RocketCore.scala:153:7] wire io_fpu_fcsr_rdy_0 = io_fpu_fcsr_rdy; // @[RocketCore.scala:153:7] wire io_fpu_nack_mem_0 = io_fpu_nack_mem; // @[RocketCore.scala:153:7] wire io_fpu_illegal_rm_0 = io_fpu_illegal_rm; // @[RocketCore.scala:153:7] wire io_fpu_dec_ldst_0 = io_fpu_dec_ldst; // @[RocketCore.scala:153:7] wire io_fpu_dec_wen_0 = io_fpu_dec_wen; // @[RocketCore.scala:153:7] wire io_fpu_dec_ren1_0 = io_fpu_dec_ren1; // @[RocketCore.scala:153:7] wire io_fpu_dec_ren2_0 = io_fpu_dec_ren2; // @[RocketCore.scala:153:7] wire io_fpu_dec_ren3_0 = io_fpu_dec_ren3; // @[RocketCore.scala:153:7] wire io_fpu_dec_swap12_0 = io_fpu_dec_swap12; // @[RocketCore.scala:153:7] wire io_fpu_dec_swap23_0 = io_fpu_dec_swap23; // @[RocketCore.scala:153:7] wire [1:0] io_fpu_dec_typeTagIn_0 = io_fpu_dec_typeTagIn; // @[RocketCore.scala:153:7] wire [1:0] io_fpu_dec_typeTagOut_0 = io_fpu_dec_typeTagOut; // @[RocketCore.scala:153:7] wire io_fpu_dec_fromint_0 = io_fpu_dec_fromint; // @[RocketCore.scala:153:7] wire io_fpu_dec_toint_0 = io_fpu_dec_toint; // @[RocketCore.scala:153:7] wire io_fpu_dec_fastpipe_0 = io_fpu_dec_fastpipe; // @[RocketCore.scala:153:7] wire io_fpu_dec_fma_0 = io_fpu_dec_fma; // @[RocketCore.scala:153:7] wire io_fpu_dec_div_0 = io_fpu_dec_div; // @[RocketCore.scala:153:7] wire io_fpu_dec_sqrt_0 = io_fpu_dec_sqrt; // @[RocketCore.scala:153:7] wire io_fpu_dec_wflags_0 = io_fpu_dec_wflags; // @[RocketCore.scala:153:7] wire io_fpu_dec_vec_0 = io_fpu_dec_vec; // @[RocketCore.scala:153:7] wire io_fpu_sboard_set_0 = io_fpu_sboard_set; // @[RocketCore.scala:153:7] wire io_fpu_sboard_clr_0 = io_fpu_sboard_clr; // @[RocketCore.scala:153:7] wire [4:0] io_fpu_sboard_clra_0 = io_fpu_sboard_clra; // @[RocketCore.scala:153:7] wire coreMonitorBundle_clock = clock; // @[RocketCore.scala:1186:31] wire coreMonitorBundle_reset = reset; // @[RocketCore.scala:1186:31] wire xrfWriteBundle_clock = clock; // @[RocketCore.scala:1249:28] wire xrfWriteBundle_reset = reset; // @[RocketCore.scala:1249:28] wire io_imem_clock_enabled = 1'h1; // @[RocketCore.scala:153:7] wire io_dmem_clock_enabled = 1'h1; // @[RocketCore.scala:153:7] wire clock_en = 1'h1; // @[RocketCore.scala:153:7, :163:29] wire _id_npc_b19_12_T = 1'h1; // @[RocketCore.scala:153:7, :1343:26] wire _id_npc_b11_T_3 = 1'h1; // @[RocketCore.scala:153:7, :1345:23] wire _id_illegal_insn_T_10 = 1'h1; // @[RocketCore.scala:153:7, :384:73] wire _id_illegal_insn_T_15 = 1'h1; // @[RocketCore.scala:153:7, :385:55] wire _mem_br_target_b19_12_T = 1'h1; // @[RocketCore.scala:153:7, :1343:26] wire _mem_br_target_b19_12_T_1 = 1'h1; // @[RocketCore.scala:153:7, :1343:43] wire _mem_br_target_b19_12_T_2 = 1'h1; // @[RocketCore.scala:153:7, :1343:36] wire _mem_br_target_b11_T_6 = 1'h1; // @[RocketCore.scala:153:7, :1346:23] wire _mem_br_target_b4_1_T_2 = 1'h1; // @[RocketCore.scala:153:7, :1349:41] wire _mem_br_target_b4_1_T_3 = 1'h1; // @[RocketCore.scala:153:7, :1349:34] wire _mem_br_target_b19_12_T_5 = 1'h1; // @[RocketCore.scala:153:7, :1343:26] wire _mem_br_target_b11_T_14 = 1'h1; // @[RocketCore.scala:153:7, :1345:23] wire _wb_reg_xcpt_T_2 = 1'h1; // @[RocketCore.scala:153:7, :707:45] wire _replay_wb_rocc_T_1 = 1'h1; // @[RocketCore.scala:153:7, :758:56] wire _rocc_blocked_T_1 = 1'h1; // @[RocketCore.scala:153:7, :1029:31] wire io_imem_btb_update_bits_taken = 1'h0; // @[RocketCore.scala:153:7] wire io_imem_ras_update_valid = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_phys = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_no_alloc = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_no_xcpt = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_s2_kill = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_gf_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_gf_st = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_s2_gpa_is_pte = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_mbe = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_sbe = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_ube = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_upie = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_hie = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_uie = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_vtw = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_hu = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_perf_l2miss = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_perf_l2hit = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_ready = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mbe = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sbe = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sd_rv32 = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_ube = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_upie = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_hie = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_uie = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_resp_ready = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_resp_valid = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_ready = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_valid = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_signed = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_dv = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_phys = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_no_resp = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_no_alloc = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_no_xcpt = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s1_kill = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_nack = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_nack_cause_raw = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_kill = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_uncached = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_valid = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_bits_signed = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_bits_dv = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_bits_replay = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_bits_has_data = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_replay_next = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_ma_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_ma_st = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_pf_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_pf_st = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_gf_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_gf_st = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_ae_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_ae_st = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_gpa_is_pte = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_ordered = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_store_pending = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_acquire = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_release = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_grant = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_tlbMiss = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_blocked = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_keep_clock_enabled = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_clock_enabled = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_busy = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_interrupt = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_exception = 1'h0; // @[RocketCore.scala:153:7] wire io_bpwatch_0_rvalid_0 = 1'h0; // @[RocketCore.scala:153:7] wire io_bpwatch_0_wvalid_0 = 1'h0; // @[RocketCore.scala:153:7] wire io_bpwatch_0_ivalid_0 = 1'h0; // @[RocketCore.scala:153:7] wire io_cease = 1'h0; // @[RocketCore.scala:153:7] wire io_traceStall = 1'h0; // @[RocketCore.scala:153:7] wire _hits_WIRE_0 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_3 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_4 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_5 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_6 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_7 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_8 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_9 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_10 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_11 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_12 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_13 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_14 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_15 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_16 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_17 = 1'h0; // @[Events.scala:13:33] wire hits_0 = 1'h0; // @[Events.scala:13:25] wire hits_1 = 1'h0; // @[Events.scala:13:25] wire hits_2 = 1'h0; // @[Events.scala:13:25] wire hits_3 = 1'h0; // @[Events.scala:13:25] wire hits_4 = 1'h0; // @[Events.scala:13:25] wire hits_5 = 1'h0; // @[Events.scala:13:25] wire hits_6 = 1'h0; // @[Events.scala:13:25] wire hits_7 = 1'h0; // @[Events.scala:13:25] wire hits_8 = 1'h0; // @[Events.scala:13:25] wire hits_9 = 1'h0; // @[Events.scala:13:25] wire hits_10 = 1'h0; // @[Events.scala:13:25] wire hits_11 = 1'h0; // @[Events.scala:13:25] wire hits_12 = 1'h0; // @[Events.scala:13:25] wire hits_13 = 1'h0; // @[Events.scala:13:25] wire hits_14 = 1'h0; // @[Events.scala:13:25] wire hits_15 = 1'h0; // @[Events.scala:13:25] wire hits_16 = 1'h0; // @[Events.scala:13:25] wire hits_17 = 1'h0; // @[Events.scala:13:25] wire _hits_WIRE_1_0 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_1 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_2 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_3 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_4 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_5 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_6 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_7 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_8 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_9 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_10 = 1'h0; // @[Events.scala:13:33] wire hits_1_0 = 1'h0; // @[Events.scala:13:25] wire hits_1_1 = 1'h0; // @[Events.scala:13:25] wire hits_1_2 = 1'h0; // @[Events.scala:13:25] wire hits_1_3 = 1'h0; // @[Events.scala:13:25] wire hits_1_4 = 1'h0; // @[Events.scala:13:25] wire hits_1_5 = 1'h0; // @[Events.scala:13:25] wire hits_1_6 = 1'h0; // @[Events.scala:13:25] wire hits_1_7 = 1'h0; // @[Events.scala:13:25] wire hits_1_8 = 1'h0; // @[Events.scala:13:25] wire hits_1_9 = 1'h0; // @[Events.scala:13:25] wire hits_1_10 = 1'h0; // @[Events.scala:13:25] wire _hits_WIRE_2_0 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_1 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_2 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_3 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_4 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_5 = 1'h0; // @[Events.scala:13:33] wire hits_2_0 = 1'h0; // @[Events.scala:13:25] wire hits_2_1 = 1'h0; // @[Events.scala:13:25] wire hits_2_2 = 1'h0; // @[Events.scala:13:25] wire hits_2_3 = 1'h0; // @[Events.scala:13:25] wire hits_2_4 = 1'h0; // @[Events.scala:13:25] wire hits_2_5 = 1'h0; // @[Events.scala:13:25] wire id_ctrl_vec = 1'h0; // @[RocketCore.scala:321:21] wire _id_rs_T_1 = 1'h0; // @[RocketCore.scala:1326:33] wire _id_rs_T_6 = 1'h0; // @[RocketCore.scala:1326:33] wire _id_npc_sign_T = 1'h0; // @[RocketCore.scala:1341:24] wire _id_npc_b30_20_T = 1'h0; // @[RocketCore.scala:1342:26] wire _id_npc_b19_12_T_1 = 1'h0; // @[RocketCore.scala:1343:43] wire _id_npc_b19_12_T_2 = 1'h0; // @[RocketCore.scala:1343:36] wire _id_npc_b11_T = 1'h0; // @[RocketCore.scala:1344:23] wire _id_npc_b11_T_1 = 1'h0; // @[RocketCore.scala:1344:40] wire _id_npc_b11_T_2 = 1'h0; // @[RocketCore.scala:1344:33] wire _id_npc_b11_T_6 = 1'h0; // @[RocketCore.scala:1346:23] wire _id_npc_b10_5_T = 1'h0; // @[RocketCore.scala:1347:25] wire _id_npc_b10_5_T_1 = 1'h0; // @[RocketCore.scala:1347:42] wire _id_npc_b10_5_T_2 = 1'h0; // @[RocketCore.scala:1347:35] wire _id_npc_b4_1_T = 1'h0; // @[RocketCore.scala:1348:24] wire _id_npc_b4_1_T_1 = 1'h0; // @[RocketCore.scala:1349:24] wire _id_npc_b4_1_T_2 = 1'h0; // @[RocketCore.scala:1349:41] wire _id_npc_b4_1_T_3 = 1'h0; // @[RocketCore.scala:1349:34] wire _id_npc_b4_1_T_5 = 1'h0; // @[RocketCore.scala:1350:24] wire _id_npc_b0_T = 1'h0; // @[RocketCore.scala:1351:22] wire _id_npc_b0_T_2 = 1'h0; // @[RocketCore.scala:1352:22] wire _id_npc_b0_T_4 = 1'h0; // @[RocketCore.scala:1353:22] wire _id_npc_b0_T_6 = 1'h0; // @[RocketCore.scala:1353:17] wire _id_npc_b0_T_7 = 1'h0; // @[RocketCore.scala:1352:17] wire id_npc_b0 = 1'h0; // @[RocketCore.scala:1351:17] wire id_set_vconfig = 1'h0; // @[RocketCore.scala:347:120] wire _id_illegal_insn_T_16 = 1'h0; // @[RocketCore.scala:385:19] wire _id_illegal_insn_T_26 = 1'h0; // @[RocketCore.scala:388:23] wire _id_illegal_insn_T_28 = 1'h0; // @[RocketCore.scala:389:23] wire _id_illegal_insn_T_30 = 1'h0; // @[RocketCore.scala:390:22] wire id_rocc_busy = 1'h0; // @[RocketCore.scala:405:34] wire _id_csr_rocc_write_T = 1'h0; // @[RocketCore.scala:408:87] wire id_csr_rocc_write = 1'h0; // @[RocketCore.scala:408:100] wire _id_do_fence_T_1 = 1'h0; // @[RocketCore.scala:410:46] wire _id_do_fence_T_2 = 1'h0; // @[RocketCore.scala:411:17] wire _id_do_fence_T_3 = 1'h0; // @[RocketCore.scala:410:86] wire _ex_reg_hls_T = 1'h0; // @[RocketCore.scala:553:37] wire _ex_reg_hls_T_6 = 1'h0; // @[RocketCore.scala:553:55] wire _ex_reg_mem_size_T = 1'h0; // @[RocketCore.scala:554:46] wire _ex_reg_set_vconfig_T_1 = 1'h0; // @[RocketCore.scala:591:42] wire _replay_ex_structural_T_5 = 1'h0; // @[RocketCore.scala:599:45] wire _replay_ex_structural_T_6 = 1'h0; // @[RocketCore.scala:599:42] wire _mem_br_target_sign_T = 1'h0; // @[RocketCore.scala:1341:24] wire _mem_br_target_b30_20_T = 1'h0; // @[RocketCore.scala:1342:26] wire _mem_br_target_b11_T = 1'h0; // @[RocketCore.scala:1344:23] wire _mem_br_target_b11_T_1 = 1'h0; // @[RocketCore.scala:1344:40] wire _mem_br_target_b11_T_2 = 1'h0; // @[RocketCore.scala:1344:33] wire _mem_br_target_b11_T_3 = 1'h0; // @[RocketCore.scala:1345:23] wire _mem_br_target_b10_5_T = 1'h0; // @[RocketCore.scala:1347:25] wire _mem_br_target_b10_5_T_1 = 1'h0; // @[RocketCore.scala:1347:42] wire _mem_br_target_b10_5_T_2 = 1'h0; // @[RocketCore.scala:1347:35] wire _mem_br_target_b4_1_T = 1'h0; // @[RocketCore.scala:1348:24] wire _mem_br_target_b4_1_T_1 = 1'h0; // @[RocketCore.scala:1349:24] wire _mem_br_target_b4_1_T_5 = 1'h0; // @[RocketCore.scala:1350:24] wire _mem_br_target_b0_T = 1'h0; // @[RocketCore.scala:1351:22] wire _mem_br_target_b0_T_2 = 1'h0; // @[RocketCore.scala:1352:22] wire _mem_br_target_b0_T_4 = 1'h0; // @[RocketCore.scala:1353:22] wire _mem_br_target_b0_T_6 = 1'h0; // @[RocketCore.scala:1353:17] wire _mem_br_target_b0_T_7 = 1'h0; // @[RocketCore.scala:1352:17] wire mem_br_target_b0 = 1'h0; // @[RocketCore.scala:1351:17] wire _mem_br_target_sign_T_3 = 1'h0; // @[RocketCore.scala:1341:24] wire _mem_br_target_b30_20_T_3 = 1'h0; // @[RocketCore.scala:1342:26] wire _mem_br_target_b19_12_T_6 = 1'h0; // @[RocketCore.scala:1343:43] wire _mem_br_target_b19_12_T_7 = 1'h0; // @[RocketCore.scala:1343:36] wire _mem_br_target_b11_T_11 = 1'h0; // @[RocketCore.scala:1344:23] wire _mem_br_target_b11_T_12 = 1'h0; // @[RocketCore.scala:1344:40] wire _mem_br_target_b11_T_13 = 1'h0; // @[RocketCore.scala:1344:33] wire _mem_br_target_b11_T_17 = 1'h0; // @[RocketCore.scala:1346:23] wire _mem_br_target_b10_5_T_4 = 1'h0; // @[RocketCore.scala:1347:25] wire _mem_br_target_b10_5_T_5 = 1'h0; // @[RocketCore.scala:1347:42] wire _mem_br_target_b10_5_T_6 = 1'h0; // @[RocketCore.scala:1347:35] wire _mem_br_target_b4_1_T_10 = 1'h0; // @[RocketCore.scala:1348:24] wire _mem_br_target_b4_1_T_11 = 1'h0; // @[RocketCore.scala:1349:24] wire _mem_br_target_b4_1_T_12 = 1'h0; // @[RocketCore.scala:1349:41] wire _mem_br_target_b4_1_T_13 = 1'h0; // @[RocketCore.scala:1349:34] wire _mem_br_target_b4_1_T_15 = 1'h0; // @[RocketCore.scala:1350:24] wire _mem_br_target_b0_T_8 = 1'h0; // @[RocketCore.scala:1351:22] wire _mem_br_target_b0_T_10 = 1'h0; // @[RocketCore.scala:1352:22] wire _mem_br_target_b0_T_12 = 1'h0; // @[RocketCore.scala:1353:22] wire _mem_br_target_b0_T_14 = 1'h0; // @[RocketCore.scala:1353:17] wire _mem_br_target_b0_T_15 = 1'h0; // @[RocketCore.scala:1352:17] wire mem_br_target_b0_1 = 1'h0; // @[RocketCore.scala:1351:17] wire vec_kill_mem = 1'h0; // @[RocketCore.scala:697:52] wire vec_kill_all = 1'h0; // @[RocketCore.scala:698:36] wire replay_wb_csr = 1'h0; // @[RocketCore.scala:759:42] wire replay_wb_vec = 1'h0; // @[RocketCore.scala:760:36] wire _htval_valid_dmem_T_2 = 1'h0; // @[RocketCore.scala:857:83] wire _htval_valid_dmem_T_3 = 1'h0; // @[RocketCore.scala:857:54] wire htval_valid_dmem = 1'h0; // @[RocketCore.scala:857:87] wire _mhtinst_read_pseudo_T_1 = 1'h0; // @[RocketCore.scala:862:98] wire _id_vconfig_hazard_T = 1'h0; // @[RocketCore.scala:1003:19] wire id_vconfig_hazard = 1'h0; // @[RocketCore.scala:1002:39] wire _ctrl_stalld_T_12 = 1'h0; // @[RocketCore.scala:1036:15] wire _ctrl_stalld_T_13 = 1'h0; // @[RocketCore.scala:1036:46] wire _ctrl_stalld_T_28 = 1'h0; // @[RocketCore.scala:1041:5] wire _io_rocc_exception_T = 1'h0; // @[RocketCore.scala:1157:52] wire _io_rocc_exception_T_1 = 1'h0; // @[RocketCore.scala:1157:32] wire _io_cease_T = 1'h0; // @[RocketCore.scala:1166:38] wire _io_cease_T_1 = 1'h0; // @[RocketCore.scala:1166:35] wire coreMonitorBundle_wrenf = 1'h0; // @[RocketCore.scala:1186:31] wire xrfWriteBundle_excpt = 1'h0; // @[RocketCore.scala:1249:28] wire xrfWriteBundle_valid = 1'h0; // @[RocketCore.scala:1249:28] wire xrfWriteBundle_wrenf = 1'h0; // @[RocketCore.scala:1249:28] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[RocketCore.scala:153:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[RocketCore.scala:153:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[RocketCore.scala:153:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[RocketCore.scala:153:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[RocketCore.scala:153:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[RocketCore.scala:153:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[RocketCore.scala:153:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[RocketCore.scala:153:7] wire [22:0] io_rocc_cmd_bits_status_zero2 = 23'h0; // @[RocketCore.scala:153:7] wire [7:0] io_dmem_req_bits_mask = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_dmem_s1_data_mask = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_rocc_cmd_bits_status_zero1 = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_rocc_mem_req_bits_mask = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_rocc_mem_s1_data_mask = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_rocc_mem_resp_bits_mask = 8'h0; // @[RocketCore.scala:153:7] wire [1:0] io_imem_ras_update_bits_cfiType = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_xs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_xs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_vs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_mem_req_bits_size = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_mem_req_bits_dprv = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_mem_resp_bits_size = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_mem_resp_bits_dprv = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] _htval_valid_dmem_T_1 = 2'h0; // @[RocketCore.scala:857:76] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[RocketCore.scala:153:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[RocketCore.scala:153:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[RocketCore.scala:153:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_resp_bits_rd = 5'h0; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_mem_req_bits_cmd = 5'h0; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_mem_resp_bits_cmd = 5'h0; // @[RocketCore.scala:153:7] wire [4:0] _csr_io_fcsr_flags_bits_T_2 = 5'h0; // @[RocketCore.scala:839:116] wire [4:0] _csr_io_fcsr_flags_bits_T_3 = 5'h0; // @[RocketCore.scala:839:110] wire [4:0] xrfWriteBundle_rd0src = 5'h0; // @[RocketCore.scala:1249:28] wire [4:0] xrfWriteBundle_rd1src = 5'h0; // @[RocketCore.scala:1249:28] wire [39:0] io_rocc_mem_req_bits_addr = 40'h0; // @[RocketCore.scala:153:7] wire [39:0] io_rocc_mem_resp_bits_addr = 40'h0; // @[RocketCore.scala:153:7] wire [39:0] io_rocc_mem_s2_gpa = 40'h0; // @[RocketCore.scala:153:7] wire [39:0] htval_dmem = 40'h0; // @[RocketCore.scala:858:25] wire [31:0] io_reset_vector = 32'h0; // @[RocketCore.scala:153:7] wire [31:0] io_rocc_mem_s2_paddr = 32'h0; // @[RocketCore.scala:153:7] wire [31:0] xrfWriteBundle_inst = 32'h0; // @[RocketCore.scala:1249:28] wire [38:0] io_imem_ras_update_bits_returnAddr = 39'h0; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_req_bits_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_resp_bits_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_req_bits_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_s1_data_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_resp_bits_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_resp_bits_data_word_bypass = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_resp_bits_data_raw = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_resp_bits_store_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] xrfWriteBundle_pc = 64'h0; // @[RocketCore.scala:1249:28] wire [63:0] xrfWriteBundle_rd0val = 64'h0; // @[RocketCore.scala:1249:28] wire [63:0] xrfWriteBundle_rd1val = 64'h0; // @[RocketCore.scala:1249:28] wire [1:0] io_ptw_status_sxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_sxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_uxl = 2'h2; // @[RocketCore.scala:153:7] wire [2:0] io_fpu_v_sew = 3'h0; // @[RocketCore.scala:153:7] wire [6:0] io_rocc_mem_req_bits_tag = 7'h0; // @[RocketCore.scala:153:7] wire [6:0] io_rocc_mem_resp_bits_tag = 7'h0; // @[RocketCore.scala:153:7] wire [2:0] io_fpu_hartid_0 = io_hartid_0; // @[RocketCore.scala:153:7] wire take_pc_mem_wb; // @[RocketCore.scala:307:35] wire [39:0] _io_imem_req_bits_pc_T_2; // @[RocketCore.scala:1051:8] wire _io_imem_req_bits_speculative_T; // @[RocketCore.scala:1049:35] wire _io_imem_sfence_valid_T; // @[RocketCore.scala:1060:40] wire io_ptw_sfence_valid_0 = io_imem_sfence_valid_0; // @[RocketCore.scala:153:7] wire _io_imem_sfence_bits_rs1_T; // @[RocketCore.scala:1061:45] wire io_ptw_sfence_bits_rs1_0 = io_imem_sfence_bits_rs1_0; // @[RocketCore.scala:153:7] wire _io_imem_sfence_bits_rs2_T; // @[RocketCore.scala:1062:45] wire io_ptw_sfence_bits_rs2_0 = io_imem_sfence_bits_rs2_0; // @[RocketCore.scala:153:7] wire [38:0] io_ptw_sfence_bits_addr_0 = io_imem_sfence_bits_addr_0; // @[RocketCore.scala:153:7] wire io_ptw_sfence_bits_asid_0 = io_imem_sfence_bits_asid_0; // @[RocketCore.scala:153:7] wire io_ptw_sfence_bits_hv_0 = io_imem_sfence_bits_hv_0; // @[RocketCore.scala:153:7] wire io_ptw_sfence_bits_hg_0 = io_imem_sfence_bits_hg_0; // @[RocketCore.scala:153:7] wire _io_imem_btb_update_valid_T_5; // @[RocketCore.scala:1071:77] wire [38:0] _io_imem_btb_update_bits_pc_T_2; // @[RocketCore.scala:1080:33] wire [38:0] io_imem_bht_update_bits_pc_0 = io_imem_btb_update_bits_pc_0; // @[RocketCore.scala:153:7] wire mem_cfi; // @[RocketCore.scala:625:50] wire [1:0] _io_imem_btb_update_bits_cfiType_T_11; // @[RocketCore.scala:1074:8] wire _io_imem_bht_update_valid_T_1; // @[RocketCore.scala:1084:45] wire mem_wrong_npc; // @[RocketCore.scala:621:8] wire _io_imem_flush_icache_T_2; // @[RocketCore.scala:1054:59] wire _io_dmem_req_valid_T; // @[RocketCore.scala:1130:41] wire [39:0] _io_dmem_req_bits_addr_T_1; // @[RocketCore.scala:1295:8] wire _io_dmem_req_bits_signed_T_3; // @[RocketCore.scala:1136:30] wire [1:0] _io_dmem_req_bits_dprv_T; // @[RocketCore.scala:1140:31] wire _io_dmem_req_bits_dv_T; // @[RocketCore.scala:1141:37] wire _io_dmem_req_bits_no_resp_T_29; // @[RocketCore.scala:1142:56] wire _io_dmem_s1_kill_T_2; // @[RocketCore.scala:1151:68] wire [63:0] _io_dmem_s1_data_data_T; // @[RocketCore.scala:1148:63] wire [63:0] io_fpu_ll_resp_data_0 = io_dmem_resp_bits_data_0; // @[RocketCore.scala:153:7] wire [63:0] _rf_wdata_T_1 = io_dmem_resp_bits_data_0; // @[RocketCore.scala:153:7, :819:78] wire [63:0] dcache_bypass_data = io_dmem_resp_bits_data_word_bypass_0; // @[RocketCore.scala:153:7, :449:62] wire _io_dmem_keep_clock_enabled_T_2; // @[RocketCore.scala:1154:70] wire [63:0] ex_rs_0; // @[RocketCore.scala:469:14] wire _csr_io_fcsr_flags_valid_T = io_fpu_fcsr_flags_valid_0; // @[RocketCore.scala:153:7, :838:54] wire _io_fpu_ll_resp_val_T; // @[RocketCore.scala:1099:41] wire [4:0] dmem_resp_waddr; // @[RocketCore.scala:767:46] wire _io_fpu_valid_T_1; // @[RocketCore.scala:1094:31] wire _id_illegal_insn_T_11 = io_fpu_illegal_rm_0; // @[RocketCore.scala:153:7, :384:70] wire ctrl_killx; // @[RocketCore.scala:602:48] wire killm_common; // @[RocketCore.scala:700:68] wire _io_fpu_keep_clock_enabled_T; // @[CustomCSRs.scala:45:59] wire _io_rocc_cmd_valid_T_2; // @[RocketCore.scala:1156:53] wire [6:0] _io_rocc_cmd_bits_inst_WIRE_funct; // @[RocketCore.scala:1159:48] wire [4:0] _io_rocc_cmd_bits_inst_WIRE_rs2; // @[RocketCore.scala:1159:48] wire [4:0] _io_rocc_cmd_bits_inst_WIRE_rs1; // @[RocketCore.scala:1159:48] wire _io_rocc_cmd_bits_inst_WIRE_xd; // @[RocketCore.scala:1159:48] wire _io_rocc_cmd_bits_inst_WIRE_xs1; // @[RocketCore.scala:1159:48] wire _io_rocc_cmd_bits_inst_WIRE_xs2; // @[RocketCore.scala:1159:48] wire [4:0] _io_rocc_cmd_bits_inst_WIRE_rd; // @[RocketCore.scala:1159:48] wire [6:0] _io_rocc_cmd_bits_inst_WIRE_opcode; // @[RocketCore.scala:1159:48] wire [39:0] io_imem_req_bits_pc_0; // @[RocketCore.scala:153:7] wire io_imem_req_bits_speculative_0; // @[RocketCore.scala:153:7] wire io_imem_req_valid_0; // @[RocketCore.scala:153:7] wire io_imem_resp_ready_0; // @[RocketCore.scala:153:7] wire [7:0] io_imem_btb_update_bits_prediction_bht_history_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_bits_prediction_bht_value_0; // @[RocketCore.scala:153:7] wire [1:0] io_imem_btb_update_bits_prediction_cfiType_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_bits_prediction_taken_0; // @[RocketCore.scala:153:7] wire [1:0] io_imem_btb_update_bits_prediction_mask_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_bits_prediction_bridx_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_btb_update_bits_prediction_target_0; // @[RocketCore.scala:153:7] wire [4:0] io_imem_btb_update_bits_prediction_entry_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_btb_update_bits_target_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_bits_isValid_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_btb_update_bits_br_pc_0; // @[RocketCore.scala:153:7] wire [1:0] io_imem_btb_update_bits_cfiType_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_valid_0; // @[RocketCore.scala:153:7] wire [7:0] io_imem_bht_update_bits_prediction_history_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_bits_prediction_value_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_bits_branch_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_bits_taken_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_bits_mispredict_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_valid_0; // @[RocketCore.scala:153:7] wire io_imem_might_request_0; // @[RocketCore.scala:153:7] wire io_imem_flush_icache_0; // @[RocketCore.scala:153:7] wire io_imem_progress_0; // @[RocketCore.scala:153:7] wire [39:0] io_dmem_req_bits_addr_0; // @[RocketCore.scala:153:7] wire [6:0] io_dmem_req_bits_tag_0; // @[RocketCore.scala:153:7] wire [4:0] io_dmem_req_bits_cmd_0; // @[RocketCore.scala:153:7] wire [1:0] io_dmem_req_bits_size_0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_signed_0; // @[RocketCore.scala:153:7] wire [1:0] io_dmem_req_bits_dprv_0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_dv_0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_no_resp_0; // @[RocketCore.scala:153:7] wire io_dmem_req_valid_0; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_s1_data_data_0; // @[RocketCore.scala:153:7] wire io_dmem_s1_kill_0; // @[RocketCore.scala:153:7] wire io_dmem_keep_clock_enabled_0; // @[RocketCore.scala:153:7] wire [3:0] io_ptw_ptbr_mode_0; // @[RocketCore.scala:153:7] wire [43:0] io_ptw_ptbr_ppn_0; // @[RocketCore.scala:153:7] wire io_ptw_status_debug_0; // @[RocketCore.scala:153:7] wire io_ptw_status_cease_0; // @[RocketCore.scala:153:7] wire io_ptw_status_wfi_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_status_isa_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_dprv_0; // @[RocketCore.scala:153:7] wire io_ptw_status_dv_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_prv_0; // @[RocketCore.scala:153:7] wire io_ptw_status_v_0; // @[RocketCore.scala:153:7] wire io_ptw_status_sd_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mpv_0; // @[RocketCore.scala:153:7] wire io_ptw_status_gva_0; // @[RocketCore.scala:153:7] wire io_ptw_status_tsr_0; // @[RocketCore.scala:153:7] wire io_ptw_status_tw_0; // @[RocketCore.scala:153:7] wire io_ptw_status_tvm_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mxr_0; // @[RocketCore.scala:153:7] wire io_ptw_status_sum_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mprv_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_fs_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_mpp_0; // @[RocketCore.scala:153:7] wire io_ptw_status_spp_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mpie_0; // @[RocketCore.scala:153:7] wire io_ptw_status_spie_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mie_0; // @[RocketCore.scala:153:7] wire io_ptw_status_sie_0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_spvp_0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_spv_0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_gva_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_debug_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_cease_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_wfi_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_gstatus_isa_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_dprv_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_dv_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_prv_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_v_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sd_0; // @[RocketCore.scala:153:7] wire [22:0] io_ptw_gstatus_zero2_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mpv_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_gva_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mbe_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sbe_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_sxl_0; // @[RocketCore.scala:153:7] wire [7:0] io_ptw_gstatus_zero1_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_tsr_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_tw_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_tvm_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mxr_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sum_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mprv_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_fs_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_mpp_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_vs_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_spp_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mpie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_ube_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_spie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_upie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_hie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_uie_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_0_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_0_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_0_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_0_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_0_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_0_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_0_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_1_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_1_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_1_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_1_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_1_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_1_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_1_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_2_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_2_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_2_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_2_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_2_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_2_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_2_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_3_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_3_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_3_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_3_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_3_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_3_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_3_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_4_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_4_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_4_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_4_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_4_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_4_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_4_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_5_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_5_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_5_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_5_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_5_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_5_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_5_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_6_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_6_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_6_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_6_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_6_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_6_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_6_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_7_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_7_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_7_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_7_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_7_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_7_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_7_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_0_ren_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_0_wen_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_1_ren_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_1_wen_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_2_ren_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_2_wen_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_3_ren_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_3_wen_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0; // @[RocketCore.scala:153:7] wire [63:0] io_fpu_time_0; // @[RocketCore.scala:153:7] wire [31:0] io_fpu_inst_0; // @[RocketCore.scala:153:7] wire [63:0] io_fpu_fromint_data_0; // @[RocketCore.scala:153:7] wire [2:0] io_fpu_fcsr_rm_0; // @[RocketCore.scala:153:7] wire io_fpu_ll_resp_val_0; // @[RocketCore.scala:153:7] wire [2:0] io_fpu_ll_resp_type_0; // @[RocketCore.scala:153:7] wire [4:0] io_fpu_ll_resp_tag_0; // @[RocketCore.scala:153:7] wire io_fpu_valid_0; // @[RocketCore.scala:153:7] wire io_fpu_killx_0; // @[RocketCore.scala:153:7] wire io_fpu_killm_0; // @[RocketCore.scala:153:7] wire io_fpu_keep_clock_enabled_0; // @[RocketCore.scala:153:7] wire [6:0] io_rocc_cmd_bits_inst_funct; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_cmd_bits_inst_rs2; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_cmd_bits_inst_rs1; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_inst_xd; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_inst_xs1; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_inst_xs2; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_cmd_bits_inst_rd; // @[RocketCore.scala:153:7] wire [6:0] io_rocc_cmd_bits_inst_opcode; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_debug; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_cease; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_wfi; // @[RocketCore.scala:153:7] wire [31:0] io_rocc_cmd_bits_status_isa; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_dprv; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_dv; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_prv; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_v; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sd; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mpv; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_gva; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_tsr; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_tw; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_tvm; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mxr; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sum; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mprv; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_fs; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_mpp; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_spp; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mpie; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_spie; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mie; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sie; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_cmd_bits_rs1; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_cmd_bits_rs2; // @[RocketCore.scala:153:7] wire io_rocc_cmd_valid; // @[RocketCore.scala:153:7] wire io_trace_insns_0_valid_0; // @[RocketCore.scala:153:7] wire [39:0] io_trace_insns_0_iaddr_0; // @[RocketCore.scala:153:7] wire [31:0] io_trace_insns_0_insn_0; // @[RocketCore.scala:153:7] wire [2:0] io_trace_insns_0_priv_0; // @[RocketCore.scala:153:7] wire io_trace_insns_0_exception_0; // @[RocketCore.scala:153:7] wire io_trace_insns_0_interrupt_0; // @[RocketCore.scala:153:7] wire [63:0] io_trace_insns_0_cause_0; // @[RocketCore.scala:153:7] wire [39:0] io_trace_insns_0_tval_0; // @[RocketCore.scala:153:7] wire [63:0] io_trace_time_0; // @[RocketCore.scala:153:7] wire io_bpwatch_0_valid_0_0; // @[RocketCore.scala:153:7] wire [2:0] io_bpwatch_0_action_0; // @[RocketCore.scala:153:7] wire io_wfi_0; // @[RocketCore.scala:153:7] reg id_reg_pause; // @[RocketCore.scala:161:25] reg imem_might_request_reg; // @[RocketCore.scala:162:35] assign io_imem_might_request_0 = imem_might_request_reg; // @[RocketCore.scala:153:7, :162:35] reg ex_ctrl_legal; // @[RocketCore.scala:243:20] reg ex_ctrl_fp; // @[RocketCore.scala:243:20] reg ex_ctrl_rocc; // @[RocketCore.scala:243:20] reg ex_ctrl_branch; // @[RocketCore.scala:243:20] reg ex_ctrl_jal; // @[RocketCore.scala:243:20] reg ex_ctrl_jalr; // @[RocketCore.scala:243:20] reg ex_ctrl_rxs2; // @[RocketCore.scala:243:20] reg ex_ctrl_rxs1; // @[RocketCore.scala:243:20] reg [2:0] ex_ctrl_sel_alu2; // @[RocketCore.scala:243:20] reg [1:0] ex_ctrl_sel_alu1; // @[RocketCore.scala:243:20] reg [2:0] ex_ctrl_sel_imm; // @[RocketCore.scala:243:20] reg ex_ctrl_alu_dw; // @[RocketCore.scala:243:20] reg [4:0] ex_ctrl_alu_fn; // @[RocketCore.scala:243:20] reg ex_ctrl_mem; // @[RocketCore.scala:243:20] wire _ex_sfence_T = ex_ctrl_mem; // @[RocketCore.scala:243:20, :605:29] reg [4:0] ex_ctrl_mem_cmd; // @[RocketCore.scala:243:20] assign io_dmem_req_bits_cmd_0 = ex_ctrl_mem_cmd; // @[RocketCore.scala:153:7, :243:20] reg ex_ctrl_rfs1; // @[RocketCore.scala:243:20] reg ex_ctrl_rfs2; // @[RocketCore.scala:243:20] reg ex_ctrl_rfs3; // @[RocketCore.scala:243:20] reg ex_ctrl_wfd; // @[RocketCore.scala:243:20] reg ex_ctrl_mul; // @[RocketCore.scala:243:20] reg ex_ctrl_div; // @[RocketCore.scala:243:20] reg ex_ctrl_wxd; // @[RocketCore.scala:243:20] reg [2:0] ex_ctrl_csr; // @[RocketCore.scala:243:20] reg ex_ctrl_fence_i; // @[RocketCore.scala:243:20] reg ex_ctrl_fence; // @[RocketCore.scala:243:20] reg ex_ctrl_amo; // @[RocketCore.scala:243:20] reg ex_ctrl_dp; // @[RocketCore.scala:243:20] reg mem_ctrl_legal; // @[RocketCore.scala:244:21] reg mem_ctrl_fp; // @[RocketCore.scala:244:21] reg mem_ctrl_rocc; // @[RocketCore.scala:244:21] reg mem_ctrl_branch; // @[RocketCore.scala:244:21] assign io_imem_bht_update_bits_branch_0 = mem_ctrl_branch; // @[RocketCore.scala:153:7, :244:21] reg mem_ctrl_jal; // @[RocketCore.scala:244:21] reg mem_ctrl_jalr; // @[RocketCore.scala:244:21] reg mem_ctrl_rxs2; // @[RocketCore.scala:244:21] reg mem_ctrl_rxs1; // @[RocketCore.scala:244:21] reg [2:0] mem_ctrl_sel_alu2; // @[RocketCore.scala:244:21] reg [1:0] mem_ctrl_sel_alu1; // @[RocketCore.scala:244:21] reg [2:0] mem_ctrl_sel_imm; // @[RocketCore.scala:244:21] reg mem_ctrl_alu_dw; // @[RocketCore.scala:244:21] reg [4:0] mem_ctrl_alu_fn; // @[RocketCore.scala:244:21] reg mem_ctrl_mem; // @[RocketCore.scala:244:21] reg [4:0] mem_ctrl_mem_cmd; // @[RocketCore.scala:244:21] reg mem_ctrl_rfs1; // @[RocketCore.scala:244:21] reg mem_ctrl_rfs2; // @[RocketCore.scala:244:21] reg mem_ctrl_rfs3; // @[RocketCore.scala:244:21] reg mem_ctrl_wfd; // @[RocketCore.scala:244:21] reg mem_ctrl_mul; // @[RocketCore.scala:244:21] reg mem_ctrl_div; // @[RocketCore.scala:244:21] reg mem_ctrl_wxd; // @[RocketCore.scala:244:21] reg [2:0] mem_ctrl_csr; // @[RocketCore.scala:244:21] reg mem_ctrl_fence_i; // @[RocketCore.scala:244:21] reg mem_ctrl_fence; // @[RocketCore.scala:244:21] reg mem_ctrl_amo; // @[RocketCore.scala:244:21] reg mem_ctrl_dp; // @[RocketCore.scala:244:21] reg mem_ctrl_vec; // @[RocketCore.scala:244:21] reg wb_ctrl_legal; // @[RocketCore.scala:245:20] reg wb_ctrl_fp; // @[RocketCore.scala:245:20] reg wb_ctrl_rocc; // @[RocketCore.scala:245:20] reg wb_ctrl_branch; // @[RocketCore.scala:245:20] reg wb_ctrl_jal; // @[RocketCore.scala:245:20] reg wb_ctrl_jalr; // @[RocketCore.scala:245:20] reg wb_ctrl_rxs2; // @[RocketCore.scala:245:20] reg wb_ctrl_rxs1; // @[RocketCore.scala:245:20] reg [2:0] wb_ctrl_sel_alu2; // @[RocketCore.scala:245:20] reg [1:0] wb_ctrl_sel_alu1; // @[RocketCore.scala:245:20] reg [2:0] wb_ctrl_sel_imm; // @[RocketCore.scala:245:20] reg wb_ctrl_alu_dw; // @[RocketCore.scala:245:20] reg [4:0] wb_ctrl_alu_fn; // @[RocketCore.scala:245:20] reg wb_ctrl_mem; // @[RocketCore.scala:245:20] reg [4:0] wb_ctrl_mem_cmd; // @[RocketCore.scala:245:20] reg wb_ctrl_rfs1; // @[RocketCore.scala:245:20] reg wb_ctrl_rfs2; // @[RocketCore.scala:245:20] reg wb_ctrl_rfs3; // @[RocketCore.scala:245:20] reg wb_ctrl_wfd; // @[RocketCore.scala:245:20] reg wb_ctrl_mul; // @[RocketCore.scala:245:20] reg wb_ctrl_div; // @[RocketCore.scala:245:20] reg wb_ctrl_wxd; // @[RocketCore.scala:245:20] reg [2:0] wb_ctrl_csr; // @[RocketCore.scala:245:20] reg wb_ctrl_fence_i; // @[RocketCore.scala:245:20] reg wb_ctrl_fence; // @[RocketCore.scala:245:20] reg wb_ctrl_amo; // @[RocketCore.scala:245:20] reg wb_ctrl_dp; // @[RocketCore.scala:245:20] reg wb_ctrl_vec; // @[RocketCore.scala:245:20] reg ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35] reg ex_reg_valid; // @[RocketCore.scala:248:35] reg ex_reg_rvc; // @[RocketCore.scala:249:35] reg [1:0] ex_reg_btb_resp_cfiType; // @[RocketCore.scala:250:35] reg ex_reg_btb_resp_taken; // @[RocketCore.scala:250:35] reg [1:0] ex_reg_btb_resp_mask; // @[RocketCore.scala:250:35] reg ex_reg_btb_resp_bridx; // @[RocketCore.scala:250:35] reg [38:0] ex_reg_btb_resp_target; // @[RocketCore.scala:250:35] reg [4:0] ex_reg_btb_resp_entry; // @[RocketCore.scala:250:35] reg [7:0] ex_reg_btb_resp_bht_history; // @[RocketCore.scala:250:35] reg ex_reg_btb_resp_bht_value; // @[RocketCore.scala:250:35] reg ex_reg_xcpt; // @[RocketCore.scala:251:35] reg ex_reg_flush_pipe; // @[RocketCore.scala:252:35] reg ex_reg_load_use; // @[RocketCore.scala:253:35] reg [63:0] ex_reg_cause; // @[RocketCore.scala:254:35] wire [63:0] ex_cause = ex_reg_cause; // @[RocketCore.scala:254:35, :1278:50] reg ex_reg_replay; // @[RocketCore.scala:255:26] reg [39:0] ex_reg_pc; // @[RocketCore.scala:256:22] wire [39:0] _ex_op1_T_1 = ex_reg_pc; // @[RocketCore.scala:256:22, :474:24] reg [1:0] ex_reg_mem_size; // @[RocketCore.scala:257:28] assign io_dmem_req_bits_size_0 = ex_reg_mem_size; // @[RocketCore.scala:153:7, :257:28] reg [31:0] ex_reg_inst; // @[RocketCore.scala:259:24] reg [31:0] ex_reg_raw_inst; // @[RocketCore.scala:260:28] reg ex_reg_wphit_0; // @[RocketCore.scala:261:36] reg mem_reg_xcpt_interrupt; // @[RocketCore.scala:264:36] reg mem_reg_valid; // @[RocketCore.scala:265:36] reg mem_reg_rvc; // @[RocketCore.scala:266:36] reg [1:0] mem_reg_btb_resp_cfiType; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_cfiType_0 = mem_reg_btb_resp_cfiType; // @[RocketCore.scala:153:7, :267:36] reg mem_reg_btb_resp_taken; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_taken_0 = mem_reg_btb_resp_taken; // @[RocketCore.scala:153:7, :267:36] wire _mem_direction_misprediction_T = mem_reg_btb_resp_taken; // @[RocketCore.scala:267:36, :627:85] reg [1:0] mem_reg_btb_resp_mask; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_mask_0 = mem_reg_btb_resp_mask; // @[RocketCore.scala:153:7, :267:36] reg mem_reg_btb_resp_bridx; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_bridx_0 = mem_reg_btb_resp_bridx; // @[RocketCore.scala:153:7, :267:36] reg [38:0] mem_reg_btb_resp_target; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_target_0 = mem_reg_btb_resp_target; // @[RocketCore.scala:153:7, :267:36] reg [4:0] mem_reg_btb_resp_entry; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_entry_0 = mem_reg_btb_resp_entry; // @[RocketCore.scala:153:7, :267:36] reg [7:0] mem_reg_btb_resp_bht_history; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_bht_history_0 = mem_reg_btb_resp_bht_history; // @[RocketCore.scala:153:7, :267:36] assign io_imem_bht_update_bits_prediction_history_0 = mem_reg_btb_resp_bht_history; // @[RocketCore.scala:153:7, :267:36] reg mem_reg_btb_resp_bht_value; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_bht_value_0 = mem_reg_btb_resp_bht_value; // @[RocketCore.scala:153:7, :267:36] assign io_imem_bht_update_bits_prediction_value_0 = mem_reg_btb_resp_bht_value; // @[RocketCore.scala:153:7, :267:36] reg mem_reg_xcpt; // @[RocketCore.scala:268:36] reg mem_reg_replay; // @[RocketCore.scala:269:36] reg mem_reg_flush_pipe; // @[RocketCore.scala:270:36] reg [63:0] mem_reg_cause; // @[RocketCore.scala:271:36] reg mem_reg_slow_bypass; // @[RocketCore.scala:272:36] wire mem_mem_cmd_bh = mem_reg_slow_bypass; // @[RocketCore.scala:272:36, :995:41] reg mem_reg_load; // @[RocketCore.scala:273:36] reg mem_reg_store; // @[RocketCore.scala:274:36] reg mem_reg_set_vconfig; // @[RocketCore.scala:275:36] reg mem_reg_sfence; // @[RocketCore.scala:276:27] reg [39:0] mem_reg_pc; // @[RocketCore.scala:277:23] wire [39:0] _mem_br_target_T = mem_reg_pc; // @[RocketCore.scala:277:23, :615:34] reg [31:0] mem_reg_inst; // @[RocketCore.scala:278:25] reg [1:0] mem_reg_mem_size; // @[RocketCore.scala:279:29] reg mem_reg_hls_or_dv; // @[RocketCore.scala:280:30] reg [31:0] mem_reg_raw_inst; // @[RocketCore.scala:281:29] reg [63:0] mem_reg_wdata; // @[RocketCore.scala:282:26] wire [63:0] _mem_int_wdata_T_3 = mem_reg_wdata; // @[RocketCore.scala:282:26, :624:111] reg [63:0] mem_reg_rs2; // @[RocketCore.scala:283:24] reg mem_br_taken; // @[RocketCore.scala:284:25] assign io_imem_bht_update_bits_taken_0 = mem_br_taken; // @[RocketCore.scala:153:7, :284:25] wire _take_pc_mem_T_3; // @[RocketCore.scala:629:49] wire take_pc_mem; // @[RocketCore.scala:285:25] reg mem_reg_wphit_0; // @[RocketCore.scala:286:35] reg wb_reg_valid; // @[RocketCore.scala:288:35] reg wb_reg_xcpt; // @[RocketCore.scala:289:35] reg wb_reg_replay; // @[RocketCore.scala:290:35] reg wb_reg_flush_pipe; // @[RocketCore.scala:291:35] reg [63:0] wb_reg_cause; // @[RocketCore.scala:292:35] reg wb_reg_set_vconfig; // @[RocketCore.scala:293:35] reg wb_reg_sfence; // @[RocketCore.scala:294:26] reg [39:0] wb_reg_pc; // @[RocketCore.scala:295:22] reg [1:0] wb_reg_mem_size; // @[RocketCore.scala:296:28] reg wb_reg_hls_or_dv; // @[RocketCore.scala:297:29] reg wb_reg_hfence_v; // @[RocketCore.scala:298:28] assign io_imem_sfence_bits_hv_0 = wb_reg_hfence_v; // @[RocketCore.scala:153:7, :298:28] reg wb_reg_hfence_g; // @[RocketCore.scala:299:28] assign io_imem_sfence_bits_hg_0 = wb_reg_hfence_g; // @[RocketCore.scala:153:7, :299:28] reg [31:0] wb_reg_inst; // @[RocketCore.scala:300:24] wire [31:0] _io_rocc_cmd_bits_inst_WIRE_1 = wb_reg_inst; // @[RocketCore.scala:300:24, :1159:48] reg [31:0] wb_reg_raw_inst; // @[RocketCore.scala:301:28] reg [63:0] wb_reg_wdata; // @[RocketCore.scala:302:25] assign io_rocc_cmd_bits_rs1 = wb_reg_wdata; // @[RocketCore.scala:153:7, :302:25] wire [63:0] _rf_wdata_T_3 = wb_reg_wdata; // @[RocketCore.scala:302:25, :822:21] reg [63:0] wb_reg_rs2; // @[RocketCore.scala:303:23] assign io_rocc_cmd_bits_rs2 = wb_reg_rs2; // @[RocketCore.scala:153:7, :303:23] wire _take_pc_wb_T_2; // @[RocketCore.scala:762:53] wire take_pc_wb; // @[RocketCore.scala:304:24] reg wb_reg_wphit_0; // @[RocketCore.scala:305:35] assign io_bpwatch_0_valid_0_0 = wb_reg_wphit_0; // @[RocketCore.scala:153:7, :305:35] assign take_pc_mem_wb = take_pc_wb \| take_pc_mem; // @[RocketCore.scala:285:25, :304:24, :307:35] assign io_imem_req_valid_0 = take_pc_mem_wb; // @[RocketCore.scala:153:7, :307:35] wire id_ctrl_decoder_0; // @[Decode.scala:50:77] wire id_ctrl_decoder_1; // @[Decode.scala:50:77] wire id_ctrl_decoder_2; // @[Decode.scala:50:77] wire id_ctrl_decoder_3; // @[Decode.scala:50:77] wire _id_illegal_insn_T_32 = id_ctrl_rocc; // @[RocketCore.scala:321:21, :391:18] wire id_ctrl_decoder_4; // @[Decode.scala:50:77] wire id_ctrl_decoder_5; // @[Decode.scala:50:77] wire id_ctrl_decoder_6; // @[Decode.scala:50:77] wire id_ctrl_decoder_7; // @[Decode.scala:50:77] wire [2:0] id_ctrl_decoder_8; // @[Decode.scala:50:77] wire [1:0] id_ctrl_decoder_9; // @[Decode.scala:50:77] wire [2:0] id_ctrl_decoder_10; // @[Decode.scala:50:77] wire id_ctrl_decoder_11; // @[Decode.scala:50:77] wire [4:0] id_ctrl_decoder_12; // @[Decode.scala:50:77] wire id_ctrl_decoder_13; // @[Decode.scala:50:77] wire [4:0] id_ctrl_decoder_14; // @[Decode.scala:50:77] wire id_ctrl_decoder_15; // @[Decode.scala:50:77] wire id_ctrl_decoder_16; // @[Decode.scala:50:77] wire id_ctrl_decoder_17; // @[Decode.scala:50:77] wire id_ctrl_decoder_18; // @[Decode.scala:50:77] wire id_ctrl_decoder_19; // @[Decode.scala:50:77] wire id_ctrl_decoder_20; // @[Decode.scala:50:77] wire id_ctrl_decoder_21; // @[Decode.scala:50:77] wire [2:0] id_ctrl_decoder_22; // @[Decode.scala:50:77] wire id_ctrl_decoder_23; // @[Decode.scala:50:77] wire id_ctrl_decoder_24; // @[Decode.scala:50:77] wire id_ctrl_decoder_25; // @[Decode.scala:50:77] wire _id_do_fence_T = id_ctrl_fence; // @[RocketCore.scala:321:21, :410:64] wire id_ctrl_decoder_26; // @[Decode.scala:50:77] wire id_ctrl_legal; // @[RocketCore.scala:321:21] wire id_ctrl_fp; // @[RocketCore.scala:321:21] wire id_ctrl_branch; // @[RocketCore.scala:321:21] wire id_ctrl_jal; // @[RocketCore.scala:321:21] wire id_ctrl_jalr; // @[RocketCore.scala:321:21] wire id_ctrl_rxs2; // @[RocketCore.scala:321:21] wire id_ctrl_rxs1; // @[RocketCore.scala:321:21] wire [2:0] id_ctrl_sel_alu2; // @[RocketCore.scala:321:21] wire [1:0] id_ctrl_sel_alu1; // @[RocketCore.scala:321:21] wire [2:0] id_ctrl_sel_imm; // @[RocketCore.scala:321:21] wire id_ctrl_alu_dw; // @[RocketCore.scala:321:21] wire [4:0] id_ctrl_alu_fn; // @[RocketCore.scala:321:21] wire id_ctrl_mem; // @[RocketCore.scala:321:21] wire [4:0] id_ctrl_mem_cmd; // @[RocketCore.scala:321:21] wire id_ctrl_rfs1; // @[RocketCore.scala:321:21] wire id_ctrl_rfs2; // @[RocketCore.scala:321:21] wire id_ctrl_rfs3; // @[RocketCore.scala:321:21] wire id_ctrl_wfd; // @[RocketCore.scala:321:21] wire id_ctrl_mul; // @[RocketCore.scala:321:21] wire id_ctrl_div; // @[RocketCore.scala:321:21] wire id_ctrl_wxd; // @[RocketCore.scala:321:21] wire [2:0] id_ctrl_csr; // @[RocketCore.scala:321:21] wire id_ctrl_fence_i; // @[RocketCore.scala:321:21] wire id_ctrl_amo; // @[RocketCore.scala:321:21] wire id_ctrl_dp; // @[RocketCore.scala:321:21] wire [31:0] id_ctrl_decoder_decoded_plaInput; // @[pla.scala:77:22] wire [31:0] id_ctrl_decoder_decoded_invInputs = ~id_ctrl_decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [41:0] id_ctrl_decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [41:0] id_ctrl_decoder_decoded; // @[pla.scala:81:23] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_175 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_176 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_177 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_178 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_179 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_180 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_181 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_182 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_183 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_184 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_185 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_186 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_187 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_188 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_189 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_190 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_191 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_192 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_193 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_175 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_176 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_177 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_178 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_179 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_180 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_181 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_182 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_183 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_184 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_185 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_186 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_187 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_188 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_189 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_190 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_191 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_192 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_193 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_175 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_176 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_177 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_178 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_179 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_180 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_181 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_182 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_183 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_184 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_185 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_186 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_187 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_188 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_189 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_190 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_191 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_192 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_193 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_175 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_176 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_177 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_178 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_179 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_180 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_181 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_182 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_183 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_184 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_185 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_186 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_187 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_188 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_189 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_190 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_191 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_192 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_193 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_174 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_175 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_176 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_177 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_178 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_179 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_180 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_181 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_182 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_183 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_184 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_185 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_186 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_187 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_188 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_189 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_190 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_191 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_192 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_164 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_175 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_176 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_179 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_181 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_182 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T = {id_ctrl_decoder_decoded_andMatrixOutputs_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_99_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_102_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_163 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_165 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_156 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_157 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_177 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_178 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_160 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_180 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_162 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_163 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_9_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_146 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_136 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_137 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_158 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_159 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_140 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_161 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_142 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_143 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_29_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_139_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_117_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_4 = id_ctrl_decoder_decoded_andMatrixOutputs_117_2; // @[pla.scala:98:70, :114:36] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_175 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_176 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_177 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_178 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_179 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_180 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_181 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_182 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_183 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_184 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_185 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_186 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_187 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_188 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_189 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_190 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_191 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_192 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_193 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_96_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:90:45, :98:53] wire [5:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_35_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_182_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_128_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_67_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_131 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_113 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_76 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_132 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_71 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_114 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_43 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_75 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_77 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_123 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_128 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_129 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_72 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_73 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_44 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_45 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_46 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_122 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_119 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_120 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_121 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_122 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_123 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_31 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_78_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_190_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [12:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_7_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_98_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_32_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_71_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_172 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_173 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_174 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_175 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_176 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_177 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_178 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_179 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_180 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_181 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_182 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_183 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_184 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_185 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_186 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_187 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_188 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_189 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17}; // @[pla.scala:91:29, :98:53] wire [4:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_181_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_16 = id_ctrl_decoder_decoded_andMatrixOutputs_181_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:91:29, :98:53] wire [5:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_145_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19}; // @[pla.scala:91:29, :98:53] wire [5:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_143_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_20_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_22_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_97_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_39_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_131_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53] wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_191_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_63 = id_ctrl_decoder_decoded_andMatrixOutputs_191_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_164_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_64 = id_ctrl_decoder_decoded_andMatrixOutputs_164_2; // @[pla.scala:98:70, :114:36] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_147 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_148 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_130 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_131 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_135 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_136 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_134 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_138 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_136 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_137 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_168 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_169 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_170 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_171 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_172 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_173 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_174 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_126 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_127 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_132 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_133 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_130 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_135 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_132 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_133 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_149 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_150 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_151 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_152 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_153 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_154 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_155 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_124 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_125 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_128 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_129 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_128 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_131 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_130 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_131 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_133 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_134 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_135 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_111 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_112 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_126 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_127 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_115 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_129 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_117 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_118 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53] wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_55_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:98:53] wire [14:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53] wire [30:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_90_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_30_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_26_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_175_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_77_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53] wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_21_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_5 = id_ctrl_decoder_decoded_andMatrixOutputs_21_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_121_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_61_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_105_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_24_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_165_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_160_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_95_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_56_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_16_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_185_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_6 = id_ctrl_decoder_decoded_andMatrixOutputs_185_2; // @[pla.scala:98:70, :114:36] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_140_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_53_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_193_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_92_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_17_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_129_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_177_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_123_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_14_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_27 = id_ctrl_decoder_decoded_andMatrixOutputs_14_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_132_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_49_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_155_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_7 = id_ctrl_decoder_decoded_andMatrixOutputs_155_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_184_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_148_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_115_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_13}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_14}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_162_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_44_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_14}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_15}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_126_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_15}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_16}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_150_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_161_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_16}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_17}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_133_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_17}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_179_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_19}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_5_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_19}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_20}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_88_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_20}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_21}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_94_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_66_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_125_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_91_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_112_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_21}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_22}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_170_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_146_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_168_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_2_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53] wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_lo_77}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_15_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_77; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_130 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_74 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_116 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_22}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_23}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_78}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_176_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_78; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_23}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_24}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_79}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_172_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_79; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_76}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_80}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_76_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_80; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_77}; // @[pla.scala:98:53] wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_81}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_87_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_81; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_24}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_25}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_78}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_82}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_144_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_82; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_25}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_26}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_79}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_83}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_36_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_83; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_26}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_27}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_80}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_84}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_41_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_84; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_27}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_28}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_81}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_85}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_8_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_85; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_28}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_29}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_82}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_86}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_104_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_86; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_29}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_30}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_83}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_87}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_73_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_87; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_30}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_31}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_84}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_88}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_189_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_88; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_31}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_32}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_85}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_89}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_28_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_89; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_33}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_86}; // @[pla.scala:98:53] wire [12:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_90}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_0_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_90; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_166 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_167 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_133 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_134 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_138 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_139 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_137 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_141 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_139 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_140 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_32}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_34}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_87}; // @[pla.scala:98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_91}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_60_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_91; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_33}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_35}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_88}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_92}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_48_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_92; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_34}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_89}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_93}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_167_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_93; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_35}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_37}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_90}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_94}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_163_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_94; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_124 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_125 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_38}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_91}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_95}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_137_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_95; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_37}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_39}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_92}; // @[pla.scala:98:53] wire [18:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_96}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_74_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_96; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_38}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_40}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_93}; // @[pla.scala:98:53] wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_97}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_59_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_97; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_39}; // @[pla.scala:98:53] wire [14:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_41}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_94}; // @[pla.scala:98:53] wire [30:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_98}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_152_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_98; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5 = id_ctrl_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5 = id_ctrl_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66 = id_ctrl_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_40}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_42}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_95}; // @[pla.scala:98:53] wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_99}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_47_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_99; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_41}; // @[pla.scala:98:53] wire [14:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_43}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_96}; // @[pla.scala:98:53] wire [30:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_100}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_103_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_100; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_42}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_44}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_97}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_101}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_83_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_101; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_28 = id_ctrl_decoder_decoded_andMatrixOutputs_83_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_43}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_45}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_98}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_102}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_31_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_102; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_44}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_46}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_99}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_103}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_13_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_103; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_45}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_47}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_100}; // @[pla.scala:98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_104}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_111_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_104; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_46}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_48}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_101}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_105}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_65_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_105; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_47}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_49}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_102}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_106}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_124_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_106; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_48}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_50}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_103}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_107}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_50_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_107; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_49}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_51}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_104}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_108}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_6_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_108; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_50}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_52}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_105}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_109}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_134_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_109; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_51}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_53}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_106}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_110}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_153_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_110; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_52}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_54}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_107}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_111}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_109_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_111; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_53}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_55}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_108}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_112}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_187_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_112; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_54}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_56}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_109}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_113}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_45_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_113; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_110}; // @[pla.scala:98:53] wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_114}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_79_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_114; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_55}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_57}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_111}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_115}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_159_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_115; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_56}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_58}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_112}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_116}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_34_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_116; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_57}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_59}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_113}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_117}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_86_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_117; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_58}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_60}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_114}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_118}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_10_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_118; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_59}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_61}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_115}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_119}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_93_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_119; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_60}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_62}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_116}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_120}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_180_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_120; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_61}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_63}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_117}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_121}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_43_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_121; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_62}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_64}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_118}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_122}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_135_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_122; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_63}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_65}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_119}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_123}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_3_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_123; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_64}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_66}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_120}; // @[pla.scala:98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_124}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_188_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_124; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_118 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_108 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_109 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_110 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_65}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_67}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_121}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_125}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_4_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_125; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_66}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_68}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_122}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_126}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_25_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_126; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_123}; // @[pla.scala:98:53] wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_127}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_58_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_127; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_67}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_69}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_124}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_128}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_147_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_128; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_68}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_70}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_125}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_129}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_27_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_129; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_69}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_119}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_71}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_126}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_130}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_52_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_130; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_70}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_120}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_72}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_127}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_131}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_138_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_131; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_71}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_121}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_73}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_128}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_132}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_178_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_132; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_72}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_122}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_74}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_129}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_133}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_173_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_133; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_73}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_123}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_75}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_130}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_134}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_120_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_134; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_74}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_124}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_76}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_131}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_135}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_19_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_135; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_75}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_125}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_77}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_132}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_136}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_64_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_136; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_76}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_126}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_78}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_133}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_137}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_142_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_137; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_77}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_127}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_79}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_134}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_138}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_11_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_138; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_78}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_128}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_80}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_135}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_139}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_46_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_139; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_79}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_129}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_81}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_136}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_140}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_141_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_140; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_80}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_130}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_82}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_137}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_141}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_114_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_141; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_81}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_131}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_83}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_138}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_142}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_70_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_142; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_82}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_132}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_84}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_139}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_143}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_72_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_143; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_83}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_133}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_85}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_140}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_lo_144}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_174_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_144; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_84}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_134}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_86}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_141}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_lo_145}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_81_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_145; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87 = id_ctrl_decoder_decoded_plaInput[26]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88 = id_ctrl_decoder_decoded_plaInput[26]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_85}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_135}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_87}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_142}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_lo_146}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_130_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_146; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_86}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_136}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_88}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_143}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_lo_147}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_157_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_147; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_87}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_137}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_89}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_144}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_lo_148}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_68_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_148; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_88}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_138}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_90}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_145}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_lo_149}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_42_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_149; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_89}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_139}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_91}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_146}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_lo_150}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_54_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_150; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_90}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_140}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_92}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_147}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_lo_151}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_63_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_151; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_91}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_141}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_93}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_148}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_lo_152}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_69_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_152; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_92}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_142}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_94}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_149}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_lo_153}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_183_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_153; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_93}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_143}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_95}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_150}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_lo_154}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_51_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_154; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_94}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_144}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_96}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_151}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_lo_155}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_136_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_155; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_95}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_145}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_97}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_152}; // @[pla.scala:98:53] wire [18:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_lo_156}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_127_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_156; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_96}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_146}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_98}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_153}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_lo_157}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_151_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_157; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_97}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_147}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_99}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_154}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_lo_158}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_1_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_158; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_98}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_148}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_100}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_155}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_lo_159}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_100_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_159; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_99}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_149}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_101}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_156}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_lo_160}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_106_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_160; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_100}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_150}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_102}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_157}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_lo_161}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_186_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_161; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_101}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_151}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_103}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_158}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_lo_162}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_18_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_162; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_102}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_152}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_104}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_159}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_lo_163}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_108_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_163; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_103}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_153}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_105}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_160}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_lo_164}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_89_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_164; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_104}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_154}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_106}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_161}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_lo_165}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_62_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_165; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_105}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_155}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_107}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_162}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_lo_166}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_149_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_166; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_106}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_156}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_108}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_163}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_lo_167}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_171_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_167; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_107}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_157}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_109}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_164}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_lo_168}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_37_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_168; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108 = id_ctrl_decoder_decoded_plaInput[23]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95 = id_ctrl_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11 = id_ctrl_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7 = id_ctrl_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_108}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_158}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_110}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_165}; // @[pla.scala:98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_lo_169}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_122_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_169; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_109}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_159}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_111}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_166}; // @[pla.scala:98:53] wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_lo_170}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_82_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_170; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_110}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_160}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_112}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_167}; // @[pla.scala:98:53] wire [31:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_lo_171}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_119_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_171; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_161}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_168}; // @[pla.scala:98:53] wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_lo_172}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_169_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_172; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_111}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_162}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_113}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_169}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_lo_173}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_57_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_173; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_112}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_163}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_163}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_114}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_170}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_lo_174}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_80_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_174; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_113}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_164}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_164}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_174}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_175}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_175}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_115}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_171}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_lo_175}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_166_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_175; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_114}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_165}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_165}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_175}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_176}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_176}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_116}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_172}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_lo_176}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_154_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_176; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_115}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_166}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_166}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_176}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_177}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_177}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_117}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_173}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_lo_177}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_192_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_177; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_116}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_167}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_167}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_177}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_178}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_178}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_118}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_174}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_lo_178}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_38_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_178; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_117}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_168}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_168}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_178}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_179}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_179}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_119}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_175}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_lo_179}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_158_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_179; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_118}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_169}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_169}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_179}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_180}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_180}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_120}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_176}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_lo_180}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_110_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_180; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_119}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_119}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_170}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_170}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_180}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_181}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_181}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_121}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_177}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_lo_181}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_23_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_181; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_120}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_120}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_171}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_171}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_181}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_182}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_182}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_122}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_178}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_lo_182}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_101_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_182; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_121}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_133}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_121}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_172}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_172}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_182}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_183}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_183}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_123}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_179}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_lo_183}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_118_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_183; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_128}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_134}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_122}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_173}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_173}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_183}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_184}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_184}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_124}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_180}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_lo_184}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_116_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_184; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_129}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_135}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_123}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_174}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_174}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_184}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_185}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_185}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_125}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_181}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_lo_185}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_156_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_185; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_111}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_130}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_126}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_124}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_175}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_136}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_182}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_175}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_186}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_186}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_186}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_126}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_182}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_lo_186}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_113_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_186; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_112}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_131}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_127}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_125}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_176}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_137}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_183}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_176}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_187}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_187}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_187}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_127}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_183}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_lo_187}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_107_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_187; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_113}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_132}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_128}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_126}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_177}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_138}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_184}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_177}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_188}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_188}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_188}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_128}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_184}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_lo_188}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_84_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_188; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_114}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_133}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_129}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_127}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_178}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_139}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_185}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_178}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_189}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_189}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_189}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_129}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_185}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_lo_189}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_33_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_189; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_130}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_128}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_128}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_179}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_137}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_179}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_160}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_190, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_190}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_189}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_190, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_190}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_190}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_130}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_186}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_lo_190}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_85_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_190; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_131}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_129}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_129}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_180}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_138}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_180}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_161}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_191, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_191}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_190}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_191, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_191}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_191}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_131}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_187}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_lo_191}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_40_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_191; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_76}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_132}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_130}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_130}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_181}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_139}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_181}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_162}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_192, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_192}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_191}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_192, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_192}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_192}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_132}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_188}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_lo_192}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_12_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_192; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_77}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_133}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_131}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_131}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_182}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_140}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_182}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_163}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_193, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_193}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_192}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_193, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_193}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_193}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_133}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_193, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_189}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_193, id_ctrl_decoder_decoded_andMatrixOutputs_lo_193}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_75_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_193; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_118_2, id_ctrl_decoder_decoded_andMatrixOutputs_85_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_114_2, id_ctrl_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_127_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_86_2, id_ctrl_decoder_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_93_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_148_2, id_ctrl_decoder_decoded_andMatrixOutputs_76_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_87_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19] wire [11:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T = {id_ctrl_decoder_decoded_orMatrixOutputs_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_1 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] _GEN = {id_ctrl_decoder_decoded_andMatrixOutputs_14_2, id_ctrl_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_1 = _GEN; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6 = _GEN; // @[pla.scala:114:19] wire [2:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_3 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_47_2, id_ctrl_decoder_decoded_andMatrixOutputs_83_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_82_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_155_2, id_ctrl_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_55_2, id_ctrl_decoder_decoded_andMatrixOutputs_185_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:114:19] wire [6:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_9 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_8; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_0 = {id_ctrl_decoder_decoded_andMatrixOutputs_84_2, id_ctrl_decoder_decoded_andMatrixOutputs_33_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo = _GEN_0; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2 = _GEN_0; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = _GEN_0; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_154_2, id_ctrl_decoder_decoded_andMatrixOutputs_23_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_57_2, id_ctrl_decoder_decoded_andMatrixOutputs_80_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_166_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_100_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_69_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_52_2, id_ctrl_decoder_decoded_andMatrixOutputs_173_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = _GEN_1; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2 = _GEN_1; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4 = _GEN_1; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_180_2, id_ctrl_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = _GEN_2; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8 = _GEN_2; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1 = _GEN_2; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_24; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_24 = _GEN_2; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2 = _GEN_2; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3 = _GEN_2; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_137_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:114:19] wire [22:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo = _GEN_3; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2 = _GEN_3; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4 = _GEN_3; // @[pla.scala:114:19] wire [1:0] _GEN_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_41_2, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = _GEN_4; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10 = _GEN_4; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3 = _GEN_4; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_14_2, id_ctrl_decoder_decoded_andMatrixOutputs_155_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = _GEN_5; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3 = _GEN_5; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_105_2, id_ctrl_decoder_decoded_andMatrixOutputs_185_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_191_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_121_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_7_2, id_ctrl_decoder_decoded_andMatrixOutputs_98_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = _GEN_6; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7 = _GEN_6; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = _GEN_6; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_96_2, id_ctrl_decoder_decoded_andMatrixOutputs_35_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = _GEN_7; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4 = _GEN_7; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_99_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = _GEN_8; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:114:19] wire [22:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_2}; // @[pla.scala:114:19] wire [45:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_11 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_176_2, id_ctrl_decoder_decoded_andMatrixOutputs_172_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_13 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_12; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_12_2, id_ctrl_decoder_decoded_andMatrixOutputs_75_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1 = _GEN_9; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2 = _GEN_9; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4 = _GEN_9; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_116_2, id_ctrl_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_51_2, id_ctrl_decoder_decoded_andMatrixOutputs_136_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = _GEN_10; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = _GEN_10; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = _GEN_10; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_72_2, id_ctrl_decoder_decoded_andMatrixOutputs_81_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_157_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_45_2, id_ctrl_decoder_decoded_andMatrixOutputs_114_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_153_2, id_ctrl_decoder_decoded_andMatrixOutputs_109_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1 = _GEN_11; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_12; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_12 = _GEN_11; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3 = _GEN_11; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_187_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_77_2, id_ctrl_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_181_2, id_ctrl_decoder_decoded_andMatrixOutputs_20_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1 = _GEN_12; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = _GEN_12; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2 = _GEN_12; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11 = _GEN_12; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:114:19] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_3}; // @[pla.scala:114:19] wire [18:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_3}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_15 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_14; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_109_2, id_ctrl_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_136_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_6_2, id_ctrl_decoder_decoded_andMatrixOutputs_134_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = _GEN_13; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2 = _GEN_13; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = _GEN_13; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_123_2, id_ctrl_decoder_decoded_andMatrixOutputs_124_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_22_2, id_ctrl_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_4}; // @[pla.scala:114:19] wire [12:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_4}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_18 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_17; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_23_2, id_ctrl_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_70_2, id_ctrl_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2 = _GEN_14; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = _GEN_14; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_130_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_109_2, id_ctrl_decoder_decoded_andMatrixOutputs_141_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_124_2, id_ctrl_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:114:19] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_5}; // @[pla.scala:114:19] wire [18:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_5}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_20 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_19; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_65_2, id_ctrl_decoder_decoded_andMatrixOutputs_79_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_128_2, id_ctrl_decoder_decoded_andMatrixOutputs_165_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_177_2}; // @[pla.scala:98:70, :114:19] wire [4:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_6}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_22 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_21; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_137_2, id_ctrl_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_58_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_24 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_23; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_83_2, id_ctrl_decoder_decoded_andMatrixOutputs_169_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_10; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_10 = _GEN_15; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7 = _GEN_15; // @[pla.scala:114:19] wire [3:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_25 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_7}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_26 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_25; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_74_2, id_ctrl_decoder_decoded_andMatrixOutputs_111_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_102_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_6}; // @[pla.scala:114:19] wire [8:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_29 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_8}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_30 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_29; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_142_2, id_ctrl_decoder_decoded_andMatrixOutputs_46_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_149_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_167_2, id_ctrl_decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_104_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_6}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_15_2, id_ctrl_decoder_decoded_andMatrixOutputs_144_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_94_2, id_ctrl_decoder_decoded_andMatrixOutputs_125_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_56_2, id_ctrl_decoder_decoded_andMatrixOutputs_179_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_121_2, id_ctrl_decoder_decoded_andMatrixOutputs_105_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6 = _GEN_16; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3 = _GEN_16; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = _GEN_16; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:114:19] wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_7}; // @[pla.scala:114:19] wire [14:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_31 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_9}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_32 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_31; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_64_2, id_ctrl_decoder_decoded_andMatrixOutputs_142_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_138_2, id_ctrl_decoder_decoded_andMatrixOutputs_173_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6 = _GEN_17; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5 = _GEN_17; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_25_2, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_43_2, id_ctrl_decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_73_2, id_ctrl_decoder_decoded_andMatrixOutputs_163_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_168_2, id_ctrl_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_112_2, id_ctrl_decoder_decoded_andMatrixOutputs_170_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_39_2, id_ctrl_decoder_decoded_andMatrixOutputs_115_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_162_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_8}; // @[pla.scala:114:19] wire [17:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_33 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_10}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_34 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_33; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_5_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_150_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_133_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_132_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_44_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_9}; // @[pla.scala:114:19] wire [10:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_35 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_11}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_36 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_35; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_54_2, id_ctrl_decoder_decoded_andMatrixOutputs_183_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_147_2, id_ctrl_decoder_decoded_andMatrixOutputs_178_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_9}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_48_2, id_ctrl_decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_129_2, id_ctrl_decoder_decoded_andMatrixOutputs_49_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_10}; // @[pla.scala:114:19] wire [9:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_37 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_12}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_38 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_37; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_171_2, id_ctrl_decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_108_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_5 = _GEN_18; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = _GEN_18; // @[pla.scala:114:19] wire [1:0] _GEN_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_106_2, id_ctrl_decoder_decoded_andMatrixOutputs_186_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_9; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_9 = _GEN_19; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3 = _GEN_19; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_10}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_11_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_188_2, id_ctrl_decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_11}; // @[pla.scala:114:19] wire [13:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_39 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_13}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_40 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_39; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_62_2, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_151_2, id_ctrl_decoder_decoded_andMatrixOutputs_18_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_42_2, id_ctrl_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1 = _GEN_20; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2 = _GEN_20; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3 = _GEN_20; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_135_2, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_34_2, id_ctrl_decoder_decoded_andMatrixOutputs_180_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_83_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_189_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_11}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_161_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_155_2, id_ctrl_decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1 = _GEN_21; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1 = _GEN_21; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2 = _GEN_21; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_121_2, id_ctrl_decoder_decoded_andMatrixOutputs_95_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_164_2, id_ctrl_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_7_2, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_78_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_12}; // @[pla.scala:114:19] wire [35:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_41 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_14}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_42 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_41; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_66_2, id_ctrl_decoder_decoded_andMatrixOutputs_146_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_97_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_43 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_15}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_44 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_43; // @[pla.scala:114:{19,36}] wire [1:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_46 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_45; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_100_2, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_42_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] _GEN_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_188_2, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2 = _GEN_22; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3 = _GEN_22; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = _GEN_22; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5 = _GEN_23; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3 = _GEN_23; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_180_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_12}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_91_2, id_ctrl_decoder_decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_24_2, id_ctrl_decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_191_2, id_ctrl_decoder_decoded_andMatrixOutputs_26_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_61_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_13}; // @[pla.scala:114:19] wire [21:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_47 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_16}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_48 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_47; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_122_2, id_ctrl_decoder_decoded_andMatrixOutputs_116_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1 = _GEN_24; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2 = _GEN_24; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_1_2, id_ctrl_decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1 = _GEN_25; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3 = _GEN_25; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4 = _GEN_25; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2 = _GEN_25; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_31_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1 = _GEN_26; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2 = _GEN_26; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:114:19] wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_13}; // @[pla.scala:114:19] wire [1:0] _GEN_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_8_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2 = _GEN_27; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4 = _GEN_27; // @[pla.scala:114:19] wire [1:0] _GEN_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_126_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1 = _GEN_28; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2 = _GEN_28; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = _GEN_28; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_184_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_105_2, id_ctrl_decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2 = _GEN_29; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4 = _GEN_29; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] _GEN_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_121_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2 = _GEN_30; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4 = _GEN_30; // @[pla.scala:114:19] wire [1:0] _GEN_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_98_2, id_ctrl_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1 = _GEN_31; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3 = _GEN_31; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2 = _GEN_31; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_96_2, id_ctrl_decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1 = _GEN_32; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2 = _GEN_32; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:114:19] wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_14}; // @[pla.scala:114:19] wire [43:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_49 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_lo_17}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_50 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_49; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_182_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_189_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_51 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_lo_18}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_52 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_51; // @[pla.scala:114:{19,36}] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_120_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_180_2, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_2_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:114:19] wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_14}; // @[pla.scala:114:19] wire [1:0] _GEN_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_140_2, id_ctrl_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3 = _GEN_33; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4 = _GEN_33; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = _GEN_33; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_91_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_61_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_24_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_191_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_29_2, id_ctrl_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:114:19] wire [12:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_15}; // @[pla.scala:114:19] wire [24:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_53 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_lo_19}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_54 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_53; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_89_2, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_142_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:114:19] wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] _GEN_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_159_2, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5 = _GEN_34; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7 = _GEN_34; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = _GEN_34; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_146_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:114:19] wire [16:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_15}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_126_2, id_ctrl_decoder_decoded_andMatrixOutputs_66_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_97_2, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_190_2, id_ctrl_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_16}; // @[pla.scala:114:19] wire [34:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_55 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_23, id_ctrl_decoder_decoded_orMatrixOutputs_lo_20}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_56 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_55; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_68_2, id_ctrl_decoder_decoded_andMatrixOutputs_63_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_57 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_24, id_ctrl_decoder_decoded_orMatrixOutputs_lo_21}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_58 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_57; // @[pla.scala:114:{19,36}] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:114:19] wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_16}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_184_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:114:19] wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_25 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_17}; // @[pla.scala:114:19] wire [43:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_59 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_25, id_ctrl_decoder_decoded_orMatrixOutputs_lo_22}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_60 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_59; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_69_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_17}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_161_2, id_ctrl_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_71_2, id_ctrl_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_32_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_128_2, id_ctrl_decoder_decoded_andMatrixOutputs_67_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_26 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_18}; // @[pla.scala:114:19] wire [21:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_61 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_26, id_ctrl_decoder_decoded_orMatrixOutputs_lo_23}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_62 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_61; // @[pla.scala:114:{19,36}] wire [1:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_97_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_66 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_65; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_158_2, id_ctrl_decoder_decoded_andMatrixOutputs_110_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_11; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_11 = _GEN_35; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = _GEN_35; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_136_2, id_ctrl_decoder_decoded_andMatrixOutputs_192_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_38_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_130_2, id_ctrl_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_141_2, id_ctrl_decoder_decoded_andMatrixOutputs_70_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_13}; // @[pla.scala:114:19] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_24 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_18}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_50_2, id_ctrl_decoder_decoded_andMatrixOutputs_6_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_134_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_175_2, id_ctrl_decoder_decoded_andMatrixOutputs_193_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_124_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_14}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_27 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_19}; // @[pla.scala:114:19] wire [20:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_67 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_27, id_ctrl_decoder_decoded_orMatrixOutputs_lo_24}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_68 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_67; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_113_2, id_ctrl_decoder_decoded_andMatrixOutputs_107_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_122_2, id_ctrl_decoder_decoded_andMatrixOutputs_119_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5}; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_130_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:114:19] wire [16:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_12}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_173_2, id_ctrl_decoder_decoded_andMatrixOutputs_141_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5}; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_111_2, id_ctrl_decoder_decoded_andMatrixOutputs_124_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:114:19] wire [16:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_14}; // @[pla.scala:114:19] wire [33:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_25 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_19}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_152_2, id_ctrl_decoder_decoded_andMatrixOutputs_103_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_74_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5}; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_95_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:114:19] wire [16:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_13}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_90_2, id_ctrl_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_131_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_20_2, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_71_2, id_ctrl_decoder_decoded_andMatrixOutputs_145_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_143_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_117_2, id_ctrl_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_15}; // @[pla.scala:114:19] wire [34:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_28 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_20}; // @[pla.scala:114:19] wire [68:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_69 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_28, id_ctrl_decoder_decoded_orMatrixOutputs_lo_25}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_70 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_69; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_3, _id_ctrl_decoder_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_9, _id_ctrl_decoder_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_5 = {1'h0, _id_ctrl_decoder_decoded_orMatrixOutputs_T_13}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_5, _id_ctrl_decoder_decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:102:36] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_13}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_16, _id_ctrl_decoder_decoded_orMatrixOutputs_T_15}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_22, _id_ctrl_decoder_decoded_orMatrixOutputs_T_20}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_18}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_27, _id_ctrl_decoder_decoded_orMatrixOutputs_T_26}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_24}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_32, _id_ctrl_decoder_decoded_orMatrixOutputs_T_30}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_28}; // @[pla.scala:102:36, :114:36] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:102:36] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_15}; // @[pla.scala:102:36] wire [20:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_26 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_20}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_36, _id_ctrl_decoder_decoded_orMatrixOutputs_T_34}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_42, _id_ctrl_decoder_decoded_orMatrixOutputs_T_40}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_38}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_46, _id_ctrl_decoder_decoded_orMatrixOutputs_T_44}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_52, _id_ctrl_decoder_decoded_orMatrixOutputs_T_50}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_48}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:102:36] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_14}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_56, _id_ctrl_decoder_decoded_orMatrixOutputs_T_54}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_62, _id_ctrl_decoder_decoded_orMatrixOutputs_T_60}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_58}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_66, _id_ctrl_decoder_decoded_orMatrixOutputs_T_64}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_63}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_70, _id_ctrl_decoder_decoded_orMatrixOutputs_T_68}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_6, 1'h0}; // @[pla.scala:102:36] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:102:36] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_16}; // @[pla.scala:102:36] wire [20:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_29 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_23, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_21}; // @[pla.scala:102:36] wire [41:0] id_ctrl_decoder_decoded_orMatrixOutputs = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_29, id_ctrl_decoder_decoded_orMatrixOutputs_lo_26}; // @[pla.scala:102:36] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T = id_ctrl_decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_1 = id_ctrl_decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_2 = id_ctrl_decoder_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_3 = id_ctrl_decoder_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_4 = id_ctrl_decoder_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_5 = id_ctrl_decoder_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_6 = id_ctrl_decoder_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_7 = id_ctrl_decoder_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_8 = id_ctrl_decoder_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_9 = id_ctrl_decoder_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_10 = id_ctrl_decoder_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_11 = id_ctrl_decoder_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_12 = id_ctrl_decoder_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_13 = id_ctrl_decoder_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_14 = id_ctrl_decoder_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_15 = id_ctrl_decoder_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_16 = id_ctrl_decoder_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_17 = id_ctrl_decoder_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_18 = id_ctrl_decoder_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_19 = id_ctrl_decoder_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_20 = id_ctrl_decoder_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_21 = id_ctrl_decoder_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_22 = id_ctrl_decoder_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_23 = id_ctrl_decoder_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_24 = id_ctrl_decoder_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_25 = id_ctrl_decoder_decoded_orMatrixOutputs[25]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_26 = id_ctrl_decoder_decoded_orMatrixOutputs[26]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_27 = id_ctrl_decoder_decoded_orMatrixOutputs[27]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_28 = id_ctrl_decoder_decoded_orMatrixOutputs[28]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_29 = id_ctrl_decoder_decoded_orMatrixOutputs[29]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_30 = id_ctrl_decoder_decoded_orMatrixOutputs[30]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_31 = id_ctrl_decoder_decoded_orMatrixOutputs[31]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_32 = id_ctrl_decoder_decoded_orMatrixOutputs[32]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_33 = id_ctrl_decoder_decoded_orMatrixOutputs[33]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_34 = id_ctrl_decoder_decoded_orMatrixOutputs[34]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_35 = id_ctrl_decoder_decoded_orMatrixOutputs[35]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_36 = id_ctrl_decoder_decoded_orMatrixOutputs[36]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_37 = id_ctrl_decoder_decoded_orMatrixOutputs[37]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_38 = id_ctrl_decoder_decoded_orMatrixOutputs[38]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_39 = id_ctrl_decoder_decoded_orMatrixOutputs[39]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_40 = id_ctrl_decoder_decoded_orMatrixOutputs[40]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_41 = id_ctrl_decoder_decoded_orMatrixOutputs[41]; // @[pla.scala:102:36, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_1, _id_ctrl_decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_4, _id_ctrl_decoder_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_6, _id_ctrl_decoder_decoded_invMatrixOutputs_T_5}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_9, _id_ctrl_decoder_decoded_invMatrixOutputs_T_8}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [9:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_11, _id_ctrl_decoder_decoded_invMatrixOutputs_T_10}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_14, _id_ctrl_decoder_decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_12}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_17, _id_ctrl_decoder_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_20, _id_ctrl_decoder_decoded_invMatrixOutputs_T_19}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_18}; // @[pla.scala:120:37, :124:31] wire [5:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [10:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [20:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_22, _id_ctrl_decoder_decoded_invMatrixOutputs_T_21}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_25, _id_ctrl_decoder_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_23}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_27, _id_ctrl_decoder_decoded_invMatrixOutputs_T_26}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_30, _id_ctrl_decoder_decoded_invMatrixOutputs_T_29}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_28}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [9:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_32, _id_ctrl_decoder_decoded_invMatrixOutputs_T_31}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_35, _id_ctrl_decoder_decoded_invMatrixOutputs_T_34}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_33}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_38, _id_ctrl_decoder_decoded_invMatrixOutputs_T_37}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_36}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_41, _id_ctrl_decoder_decoded_invMatrixOutputs_T_40}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_39}; // @[pla.scala:120:37, :124:31] wire [5:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [10:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [20:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign id_ctrl_decoder_decoded_invMatrixOutputs = {id_ctrl_decoder_decoded_invMatrixOutputs_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign id_ctrl_decoder_decoded = id_ctrl_decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign id_ctrl_decoder_0 = id_ctrl_decoder_decoded[41]; // @[pla.scala:81:23] assign id_ctrl_legal = id_ctrl_decoder_0; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_1 = id_ctrl_decoder_decoded[40]; // @[pla.scala:81:23] assign id_ctrl_fp = id_ctrl_decoder_1; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_2 = id_ctrl_decoder_decoded[39]; // @[pla.scala:81:23] assign id_ctrl_rocc = id_ctrl_decoder_2; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_3 = id_ctrl_decoder_decoded[38]; // @[pla.scala:81:23] assign id_ctrl_branch = id_ctrl_decoder_3; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_4 = id_ctrl_decoder_decoded[37]; // @[pla.scala:81:23] assign id_ctrl_jal = id_ctrl_decoder_4; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_5 = id_ctrl_decoder_decoded[36]; // @[pla.scala:81:23] assign id_ctrl_jalr = id_ctrl_decoder_5; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_6 = id_ctrl_decoder_decoded[35]; // @[pla.scala:81:23] assign id_ctrl_rxs2 = id_ctrl_decoder_6; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_7 = id_ctrl_decoder_decoded[34]; // @[pla.scala:81:23] assign id_ctrl_rxs1 = id_ctrl_decoder_7; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_8 = id_ctrl_decoder_decoded[33:31]; // @[pla.scala:81:23] assign id_ctrl_sel_alu2 = id_ctrl_decoder_8; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_9 = id_ctrl_decoder_decoded[30:29]; // @[pla.scala:81:23] assign id_ctrl_sel_alu1 = id_ctrl_decoder_9; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_10 = id_ctrl_decoder_decoded[28:26]; // @[pla.scala:81:23] assign id_ctrl_sel_imm = id_ctrl_decoder_10; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_11 = id_ctrl_decoder_decoded[25]; // @[pla.scala:81:23] assign id_ctrl_alu_dw = id_ctrl_decoder_11; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_12 = id_ctrl_decoder_decoded[24:20]; // @[pla.scala:81:23] assign id_ctrl_alu_fn = id_ctrl_decoder_12; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_13 = id_ctrl_decoder_decoded[19]; // @[pla.scala:81:23] assign id_ctrl_mem = id_ctrl_decoder_13; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_14 = id_ctrl_decoder_decoded[18:14]; // @[pla.scala:81:23] assign id_ctrl_mem_cmd = id_ctrl_decoder_14; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_15 = id_ctrl_decoder_decoded[13]; // @[pla.scala:81:23] assign id_ctrl_rfs1 = id_ctrl_decoder_15; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_16 = id_ctrl_decoder_decoded[12]; // @[pla.scala:81:23] assign id_ctrl_rfs2 = id_ctrl_decoder_16; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_17 = id_ctrl_decoder_decoded[11]; // @[pla.scala:81:23] assign id_ctrl_rfs3 = id_ctrl_decoder_17; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_18 = id_ctrl_decoder_decoded[10]; // @[pla.scala:81:23] assign id_ctrl_wfd = id_ctrl_decoder_18; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_19 = id_ctrl_decoder_decoded[9]; // @[pla.scala:81:23] assign id_ctrl_mul = id_ctrl_decoder_19; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_20 = id_ctrl_decoder_decoded[8]; // @[pla.scala:81:23] assign id_ctrl_div = id_ctrl_decoder_20; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_21 = id_ctrl_decoder_decoded[7]; // @[pla.scala:81:23] assign id_ctrl_wxd = id_ctrl_decoder_21; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_22 = id_ctrl_decoder_decoded[6:4]; // @[pla.scala:81:23] assign id_ctrl_csr = id_ctrl_decoder_22; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_23 = id_ctrl_decoder_decoded[3]; // @[pla.scala:81:23] assign id_ctrl_fence_i = id_ctrl_decoder_23; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_24 = id_ctrl_decoder_decoded[2]; // @[pla.scala:81:23] assign id_ctrl_fence = id_ctrl_decoder_24; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_25 = id_ctrl_decoder_decoded[1]; // @[pla.scala:81:23] assign id_ctrl_amo = id_ctrl_decoder_25; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_26 = id_ctrl_decoder_decoded[0]; // @[pla.scala:81:23] assign id_ctrl_dp = id_ctrl_decoder_26; // @[RocketCore.scala:321:21] wire [4:0] id_raddr3; // @[RocketCore.scala:326:72] wire [4:0] id_raddr2; // @[RocketCore.scala:326:72] wire [4:0] _id_rs_T_7 = id_raddr2; // @[RocketCore.scala:326:72, :1320:44] wire [4:0] id_raddr1; // @[RocketCore.scala:326:72] wire [4:0] _id_rs_T_2 = id_raddr1; // @[RocketCore.scala:326:72, :1320:44] wire [4:0] id_waddr; // @[RocketCore.scala:326:72] wire _id_load_use_T_1; // @[RocketCore.scala:1001:51] wire id_load_use; // @[RocketCore.scala:332:25] reg id_reg_fence; // @[RocketCore.scala:333:29] wire [63:0] id_rs_0; // @[RocketCore.scala:1325:26] wire _id_rs_T = ~(\|id_raddr1); // @[RocketCore.scala:326:72, :1326:41] wire [4:0] _id_rs_T_3 = ~_id_rs_T_2; // @[RocketCore.scala:1320:{39,44}] wire [63:0] id_rs_1; // @[RocketCore.scala:1325:26] wire _id_rs_T_5 = ~(\|id_raddr2); // @[RocketCore.scala:326:72, :1326:41] wire [4:0] _id_rs_T_8 = ~_id_rs_T_7; // @[RocketCore.scala:1320:{39,44}] wire _ctrl_killd_T_4; // @[RocketCore.scala:1046:104] wire ctrl_killd; // @[RocketCore.scala:338:24] wire _id_npc_sign_T_1 = _ibuf_io_inst_0_bits_inst_bits[31]; // @[RocketCore.scala:311:20, :1341:44] wire _id_npc_sign_T_2 = _id_npc_sign_T_1; // @[RocketCore.scala:1341:{44,49}] wire id_npc_sign = _id_npc_sign_T_2; // @[RocketCore.scala:1341:{19,49}] wire _id_npc_b11_T_9 = id_npc_sign; // @[RocketCore.scala:1341:19, :1346:18] wire id_npc_hi_hi_hi = id_npc_sign; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _id_npc_b30_20_T_1 = _ibuf_io_inst_0_bits_inst_bits[30:20]; // @[RocketCore.scala:311:20, :1342:41] wire [10:0] _id_npc_b30_20_T_2 = _id_npc_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}] wire [10:0] id_npc_b30_20 = {11{id_npc_sign}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] id_npc_hi_hi_lo = id_npc_b30_20; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _id_npc_b19_12_T_3 = _ibuf_io_inst_0_bits_inst_bits[19:12]; // @[RocketCore.scala:311:20, :1343:65] wire [7:0] _id_npc_b19_12_T_4 = _id_npc_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}] wire [7:0] id_npc_b19_12 = _id_npc_b19_12_T_4; // @[RocketCore.scala:1343:{21,73}] wire [7:0] id_npc_hi_lo_hi = id_npc_b19_12; // @[RocketCore.scala:1343:21, :1355:8] wire _id_npc_b11_T_4 = _ibuf_io_inst_0_bits_inst_bits[20]; // @[RocketCore.scala:311:20, :1345:39] wire _id_npc_b0_T_3 = _ibuf_io_inst_0_bits_inst_bits[20]; // @[RocketCore.scala:311:20, :1345:39, :1352:37] wire _id_npc_b11_T_5 = _id_npc_b11_T_4; // @[RocketCore.scala:1345:{39,44}] wire _id_npc_b11_T_10 = _id_npc_b11_T_5; // @[RocketCore.scala:1345:{18,44}] wire _id_npc_b11_T_7 = _ibuf_io_inst_0_bits_inst_bits[7]; // @[RocketCore.scala:311:20, :1346:39] wire _id_npc_b0_T_1 = _ibuf_io_inst_0_bits_inst_bits[7]; // @[RocketCore.scala:311:20, :1346:39, :1351:37] wire _id_npc_b11_T_8 = _id_npc_b11_T_7; // @[RocketCore.scala:1346:{39,43}] wire id_npc_b11 = _id_npc_b11_T_10; // @[RocketCore.scala:1344:18, :1345:18] wire id_npc_hi_lo_lo = id_npc_b11; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] _id_npc_b10_5_T_3 = _ibuf_io_inst_0_bits_inst_bits[30:25]; // @[RocketCore.scala:311:20, :1347:62] wire [5:0] id_npc_b10_5 = _id_npc_b10_5_T_3; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _id_npc_b4_1_T_4 = _ibuf_io_inst_0_bits_inst_bits[11:8]; // @[RocketCore.scala:311:20, :1349:57] wire [3:0] _id_npc_b4_1_T_6 = _ibuf_io_inst_0_bits_inst_bits[19:16]; // @[RocketCore.scala:311:20, :1350:39] wire [3:0] _id_npc_b4_1_T_7 = _ibuf_io_inst_0_bits_inst_bits[24:21]; // @[RocketCore.scala:311:20, :1350:52] wire [3:0] _id_npc_b4_1_T_8 = _id_npc_b4_1_T_7; // @[RocketCore.scala:1350:{19,52}] wire [3:0] _id_npc_b4_1_T_9 = _id_npc_b4_1_T_8; // @[RocketCore.scala:1349:19, :1350:19] wire [3:0] id_npc_b4_1 = _id_npc_b4_1_T_9; // @[RocketCore.scala:1348:19, :1349:19] wire _id_npc_b0_T_5 = _ibuf_io_inst_0_bits_inst_bits[15]; // @[RocketCore.scala:311:20, :1353:37] wire [9:0] id_npc_lo_hi = {id_npc_b10_5, id_npc_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] id_npc_lo = {id_npc_lo_hi, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] id_npc_hi_lo = {id_npc_hi_lo_hi, id_npc_hi_lo_lo}; // @[RocketCore.scala:1355:8] wire [11:0] id_npc_hi_hi = {id_npc_hi_hi_hi, id_npc_hi_hi_lo}; // @[RocketCore.scala:1355:8] wire [20:0] id_npc_hi = {id_npc_hi_hi, id_npc_hi_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _id_npc_T_1 = {id_npc_hi, id_npc_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _id_npc_T_2 = _id_npc_T_1; // @[RocketCore.scala:1355:{8,53}] wire [39:0] _id_npc_T; // @[RocketCore.scala:339:28] wire [40:0] _id_npc_T_3 = {_id_npc_T[39], _id_npc_T} + {{9{_id_npc_T_2[31]}}, _id_npc_T_2}; // @[RocketCore.scala:339:{28,35}, :1355:53] wire [39:0] _id_npc_T_4 = _id_npc_T_3[39:0]; // @[RocketCore.scala:339:35] wire [39:0] _id_npc_T_5 = _id_npc_T_4; // @[RocketCore.scala:339:35] wire [39:0] id_npc = _id_npc_T_5; // @[RocketCore.scala:339:{35,65}] wire _GEN_36 = id_ctrl_csr == 3'h6; // @[package.scala:16:47] wire _id_csr_en_T; // @[package.scala:16:47] assign _id_csr_en_T = _GEN_36; // @[package.scala:16:47] wire _id_csr_ren_T; // @[package.scala:16:47] assign _id_csr_ren_T = _GEN_36; // @[package.scala:16:47] wire _id_csr_en_T_1 = &id_ctrl_csr; // @[package.scala:16:47] wire _id_csr_en_T_2 = id_ctrl_csr == 3'h5; // @[package.scala:16:47] wire _id_csr_en_T_3 = _id_csr_en_T \| _id_csr_en_T_1; // @[package.scala:16:47, :81:59] wire id_csr_en = _id_csr_en_T_3 \| _id_csr_en_T_2; // @[package.scala:16:47, :81:59] wire id_system_insn = id_ctrl_csr == 3'h4; // @[RocketCore.scala:321:21, :343:36] wire _id_csr_ren_T_1 = &id_ctrl_csr; // @[package.scala:16:47] wire _id_csr_ren_T_2 = _id_csr_ren_T \| _id_csr_ren_T_1; // @[package.scala:16:47, :81:59] wire _id_csr_ren_T_3 = _ibuf_io_inst_0_bits_inst_rs1 == 5'h0; // @[RocketCore.scala:311:20, :344:81] wire id_csr_ren = _id_csr_ren_T_2 & _id_csr_ren_T_3; // @[package.scala:81:59] wire _id_csr_T = id_system_insn & id_ctrl_mem; // @[RocketCore.scala:321:21, :343:36, :345:35] wire [2:0] _id_csr_T_1 = id_csr_ren ? 3'h2 : id_ctrl_csr; // @[RocketCore.scala:321:21, :344:54, :345:61] wire [2:0] id_csr = _id_csr_T ? 3'h0 : _id_csr_T_1; // @[RocketCore.scala:345:{19,35,61}] wire _id_csr_flush_T = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54] wire _id_csr_flush_T_1 = id_csr_en & _id_csr_flush_T; // @[package.scala:81:59] wire _id_csr_flush_T_2 = _id_csr_flush_T_1 & _csr_io_decode_0_write_flush; // @[RocketCore.scala:341:19, :346:{51,66}] wire id_csr_flush = id_system_insn \| _id_csr_flush_T_2; // @[RocketCore.scala:343:36, :346:{37,66}] wire [31:0] _id_set_vconfig_T = _ibuf_io_inst_0_bits_inst_bits & 32'h8000707F; // @[RocketCore.scala:311:20, :347:100] wire _id_set_vconfig_T_1 = _id_set_vconfig_T == 32'h7057; // @[RocketCore.scala:347:100] wire [31:0] _id_set_vconfig_T_2 = _ibuf_io_inst_0_bits_inst_bits & 32'hC000707F; // @[RocketCore.scala:311:20, :347:100] wire _id_set_vconfig_T_3 = _id_set_vconfig_T_2 == 32'hC0007057; // @[RocketCore.scala:347:100] wire [31:0] _id_set_vconfig_T_4 = _ibuf_io_inst_0_bits_inst_bits & 32'hFE00707F; // @[RocketCore.scala:311:20, :347:100] wire _id_set_vconfig_T_5 = _id_set_vconfig_T_4 == 32'h80007057; // @[RocketCore.scala:347:100] wire _id_set_vconfig_T_6 = _id_set_vconfig_T_1 \| _id_set_vconfig_T_3; // @[package.scala:81:59] wire _id_set_vconfig_T_7 = _id_set_vconfig_T_6 \| _id_set_vconfig_T_5; // @[package.scala:81:59] wire _id_illegal_insn_T = ~id_ctrl_legal; // @[RocketCore.scala:321:21, :381:25] wire _id_illegal_insn_T_1 = id_ctrl_mul \| id_ctrl_div; // @[RocketCore.scala:321:21, :382:18] wire _id_illegal_insn_T_2 = _csr_io_status_isa[12]; // @[RocketCore.scala:341:19, :382:55] wire _id_illegal_insn_T_3 = ~_id_illegal_insn_T_2; // @[RocketCore.scala:382:{37,55}] wire _id_illegal_insn_T_4 = _id_illegal_insn_T_1 & _id_illegal_insn_T_3; // @[RocketCore.scala:382:{18,34,37}] wire _id_illegal_insn_T_5 = _id_illegal_insn_T \| _id_illegal_insn_T_4; // @[RocketCore.scala:381:{25,40}, :382:34] wire _id_illegal_insn_T_6 = _csr_io_status_isa[0]; // @[RocketCore.scala:341:19, :383:38] wire _id_illegal_insn_T_7 = ~_id_illegal_insn_T_6; // @[RocketCore.scala:383:{20,38}] wire _id_illegal_insn_T_8 = id_ctrl_amo & _id_illegal_insn_T_7; // @[RocketCore.scala:321:21, :383:{17,20}] wire _id_illegal_insn_T_9 = _id_illegal_insn_T_5 \| _id_illegal_insn_T_8; // @[RocketCore.scala:381:40, :382:65, :383:17] wire _id_illegal_insn_T_12 = _csr_io_decode_0_fp_illegal \| _id_illegal_insn_T_11; // @[RocketCore.scala:341:19, :384:{48,70}] wire _id_illegal_insn_T_13 = id_ctrl_fp & _id_illegal_insn_T_12; // @[RocketCore.scala:321:21, :384:{16,48}] wire _id_illegal_insn_T_14 = _id_illegal_insn_T_9 \| _id_illegal_insn_T_13; // @[RocketCore.scala:382:65, :383:48, :384:16] wire _id_illegal_insn_T_17 = _id_illegal_insn_T_14; // @[RocketCore.scala:383:48, :384:88] wire _id_illegal_insn_T_18 = _csr_io_status_isa[3]; // @[RocketCore.scala:341:19, :386:37] wire _id_illegal_insn_T_19 = ~_id_illegal_insn_T_18; // @[RocketCore.scala:386:{19,37}] wire _id_illegal_insn_T_20 = id_ctrl_dp & _id_illegal_insn_T_19; // @[RocketCore.scala:321:21, :386:{16,19}] wire _id_illegal_insn_T_21 = _id_illegal_insn_T_17 \| _id_illegal_insn_T_20; // @[RocketCore.scala:384:88, :385:118, :386:16] wire _id_illegal_insn_T_22 = _csr_io_status_isa[2]; // @[RocketCore.scala:341:19, :387:51] wire _mem_npc_misaligned_T = _csr_io_status_isa[2]; // @[RocketCore.scala:341:19, :387:51, :623:46] wire _id_illegal_insn_T_23 = ~_id_illegal_insn_T_22; // @[RocketCore.scala:387:{33,51}] wire _id_illegal_insn_T_24 = _ibuf_io_inst_0_bits_rvc & _id_illegal_insn_T_23; // @[RocketCore.scala:311:20, :387:{30,33}] wire _id_illegal_insn_T_25 = _id_illegal_insn_T_21 \| _id_illegal_insn_T_24; // @[RocketCore.scala:385:118, :386:47, :387:30] wire _id_illegal_insn_T_27 = _id_illegal_insn_T_25; // @[RocketCore.scala:386:47, :387:61] wire _id_illegal_insn_T_29 = _id_illegal_insn_T_27; // @[RocketCore.scala:387:61, :388:39] wire _id_illegal_insn_T_31 = _id_illegal_insn_T_29; // @[RocketCore.scala:388:39, :389:39] wire _id_illegal_insn_T_33 = _id_illegal_insn_T_31 \| _id_illegal_insn_T_32; // @[RocketCore.scala:389:39, :390:37, :391:18] wire _id_illegal_insn_T_34 = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54, :392:52] wire _id_illegal_insn_T_35 = _id_illegal_insn_T_34 & _csr_io_decode_0_write_illegal; // @[RocketCore.scala:341:19, :392:{52,64}] wire _id_illegal_insn_T_36 = _csr_io_decode_0_read_illegal \| _id_illegal_insn_T_35; // @[RocketCore.scala:341:19, :392:{49,64}] wire _id_illegal_insn_T_37 = id_csr_en & _id_illegal_insn_T_36; // @[package.scala:81:59] wire _id_illegal_insn_T_38 = _id_illegal_insn_T_33 \| _id_illegal_insn_T_37; // @[RocketCore.scala:390:37, :391:51, :392:15] wire _id_illegal_insn_T_39 = ~_ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala:311:20, :393:5] wire _id_illegal_insn_T_40 = id_system_insn & _csr_io_decode_0_system_illegal; // @[RocketCore.scala:341:19, :343:36, :393:50] wire _id_illegal_insn_T_41 = _id_illegal_insn_T_39 & _id_illegal_insn_T_40; // @[RocketCore.scala:393:{5,31,50}] wire id_illegal_insn = _id_illegal_insn_T_38 \| _id_illegal_insn_T_41; // @[RocketCore.scala:391:51, :392:99, :393:31] wire _id_virtual_insn_T = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54, :395:22] wire _id_virtual_insn_T_1 = _id_virtual_insn_T & _csr_io_decode_0_write_illegal; // @[RocketCore.scala:341:19, :395:{22,34}] wire _id_virtual_insn_T_2 = ~_id_virtual_insn_T_1; // @[RocketCore.scala:395:{20,34}] wire _id_virtual_insn_T_3 = id_csr_en & _id_virtual_insn_T_2; // @[package.scala:81:59] wire _id_virtual_insn_T_4 = _id_virtual_insn_T_3 & _csr_io_decode_0_virtual_access_illegal; // @[RocketCore.scala:341:19, :395:{17,69}] wire _id_virtual_insn_T_5 = ~_ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala:311:20, :393:5, :396:7] wire _id_virtual_insn_T_6 = _id_virtual_insn_T_5 & id_system_insn; // @[RocketCore.scala:343:36, :396:{7,33}] wire _id_virtual_insn_T_7 = _id_virtual_insn_T_6 & _csr_io_decode_0_virtual_system_illegal; // @[RocketCore.scala:341:19, :396:{33,51}] wire _id_virtual_insn_T_8 = _id_virtual_insn_T_4 \| _id_virtual_insn_T_7; // @[RocketCore.scala:395:{69,113}, :396:51] wire id_virtual_insn = id_ctrl_legal & _id_virtual_insn_T_8; // @[RocketCore.scala:321:21, :394:39, :395:113] wire id_amo_aq = _ibuf_io_inst_0_bits_inst_bits[26]; // @[RocketCore.scala:311:20, :398:29] wire id_amo_rl = _ibuf_io_inst_0_bits_inst_bits[25]; // @[RocketCore.scala:311:20, :399:29] wire [3:0] id_fence_pred = _ibuf_io_inst_0_bits_inst_bits[27:24]; // @[RocketCore.scala:311:20, :400:33] wire [3:0] id_fence_succ = _ibuf_io_inst_0_bits_inst_bits[23:20]; // @[RocketCore.scala:311:20, :401:33] wire _id_fence_next_T = id_ctrl_amo & id_amo_aq; // @[RocketCore.scala:321:21, :398:29, :402:52] wire id_fence_next = id_ctrl_fence \| _id_fence_next_T; // @[RocketCore.scala:321:21, :402:{37,52}] wire _id_mem_busy_T = ~io_dmem_ordered_0; // @[RocketCore.scala:153:7, :403:21] wire id_mem_busy = _id_mem_busy_T \| io_dmem_req_valid_0; // @[RocketCore.scala:153:7, :403:{21,38}] wire _id_rocc_busy_T = ex_reg_valid & ex_ctrl_rocc; // @[RocketCore.scala:243:20, :248:35, :406:35] wire _id_rocc_busy_T_1 = _id_rocc_busy_T; // @[RocketCore.scala:406:{19,35}] wire _id_rocc_busy_T_2 = mem_reg_valid & mem_ctrl_rocc; // @[RocketCore.scala:244:21, :265:36, :407:20] wire _id_rocc_busy_T_3 = _id_rocc_busy_T_1 \| _id_rocc_busy_T_2; // @[RocketCore.scala:406:{19,51}, :407:20] wire _GEN_37 = wb_reg_valid & wb_ctrl_rocc; // @[RocketCore.scala:245:20, :288:35, :407:53] wire _id_rocc_busy_T_4; // @[RocketCore.scala:407:53] assign _id_rocc_busy_T_4 = _GEN_37; // @[RocketCore.scala:407:53] wire _replay_wb_rocc_T; // @[RocketCore.scala:758:37] assign _replay_wb_rocc_T = _GEN_37; // @[RocketCore.scala:407:53, :758:37] wire _io_rocc_cmd_valid_T; // @[RocketCore.scala:1156:37] assign _io_rocc_cmd_valid_T = _GEN_37; // @[RocketCore.scala:407:53, :1156:37] wire _id_rocc_busy_T_5 = _id_rocc_busy_T_3 \| _id_rocc_busy_T_4; // @[RocketCore.scala:406:51, :407:{37,53}] wire _id_csr_rocc_write_T_1 = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54, :408:103] wire _id_do_fence_T_4 = id_ctrl_amo & id_amo_rl; // @[RocketCore.scala:321:21, :399:29, :412:33] wire _id_do_fence_T_5 = _id_do_fence_T_4 \| id_ctrl_fence_i; // @[RocketCore.scala:321:21, :412:{33,46}] wire _id_do_fence_T_6 = id_ctrl_mem \| id_ctrl_rocc; // @[RocketCore.scala:321:21, :412:97] wire _id_do_fence_T_7 = id_reg_fence & _id_do_fence_T_6; // @[RocketCore.scala:333:29, :412:{81,97}] wire _id_do_fence_T_8 = _id_do_fence_T_5 \| _id_do_fence_T_7; // @[RocketCore.scala:412:{46,65,81}] wire _id_do_fence_T_9 = id_mem_busy & _id_do_fence_T_8; // @[RocketCore.scala:403:38, :412:{17,65}] wire _id_do_fence_T_10 = _id_do_fence_T_9; // @[RocketCore.scala:411:34, :412:17] wire id_do_fence = _id_do_fence_T_10; // @[RocketCore.scala:410:32, :411:34] wire [38:0] _mem_npc_T_1 = mem_reg_wdata[38:0]; // @[RocketCore.scala:282:26, :418:13, :1295:16] wire id_xcpt = _csr_io_interrupt \| _bpu_io_debug_if \| _bpu_io_xcpt_if \| _ibuf_io_inst_0_bits_xcpt0_pf_inst \| _ibuf_io_inst_0_bits_xcpt0_gf_inst \| _ibuf_io_inst_0_bits_xcpt0_ae_inst \| _ibuf_io_inst_0_bits_xcpt1_pf_inst \| _ibuf_io_inst_0_bits_xcpt1_gf_inst \| _ibuf_io_inst_0_bits_xcpt1_ae_inst \| id_virtual_insn \| id_illegal_insn; // @[RocketCore.scala:311:20, :341:19, :392:99, :394:39, :414:19, :1278:{14,35}] wire [63:0] id_cause = _csr_io_interrupt ? _csr_io_interrupt_cause : {59'h0, _bpu_io_debug_if ? 5'hE : _bpu_io_xcpt_if ? 5'h3 : _ibuf_io_inst_0_bits_xcpt0_pf_inst ? 5'hC : _ibuf_io_inst_0_bits_xcpt0_gf_inst ? 5'h14 : _ibuf_io_inst_0_bits_xcpt0_ae_inst ? 5'h1 : _ibuf_io_inst_0_bits_xcpt1_pf_inst ? 5'hC : _ibuf_io_inst_0_bits_xcpt1_gf_inst ? 5'h14 : _ibuf_io_inst_0_bits_xcpt1_ae_inst ? 5'h1 : id_virtual_insn ? 5'h16 : 5'h2}; // @[Mux.scala:50:70] wire [4:0] _ex_waddr_T = ex_reg_inst[11:7]; // @[RocketCore.scala:259:24, :453:29] wire [4:0] ex_waddr = _ex_waddr_T; // @[RocketCore.scala:453:{29,36}] wire [4:0] _mem_waddr_T = mem_reg_inst[11:7]; // @[RocketCore.scala:278:25, :454:31] wire [4:0] mem_waddr = _mem_waddr_T; // @[RocketCore.scala:454:{31,38}] wire [4:0] _wb_waddr_T = wb_reg_inst[11:7]; // @[RocketCore.scala:300:24, :455:29] wire [4:0] wb_waddr = _wb_waddr_T; // @[RocketCore.scala:455:{29,36}] wire [4:0] coreMonitorBundle_wrdst = wb_waddr; // @[RocketCore.scala:455:36, :1186:31] wire bypass_sources_1_1 = ex_reg_valid & ex_ctrl_wxd; // @[RocketCore.scala:243:20, :248:35, :458:19] wire _GEN_38 = mem_reg_valid & mem_ctrl_wxd; // @[RocketCore.scala:244:21, :265:36, :459:20] wire _bypass_sources_T; // @[RocketCore.scala:459:20] assign _bypass_sources_T = _GEN_38; // @[RocketCore.scala:459:20] wire bypass_sources_3_1; // @[RocketCore.scala:460:20] assign bypass_sources_3_1 = _GEN_38; // @[RocketCore.scala:459:20, :460:20] wire _dcache_kill_mem_T; // @[RocketCore.scala:695:39] assign _dcache_kill_mem_T = _GEN_38; // @[RocketCore.scala:459:20, :695:39] wire _bypass_sources_T_1 = ~mem_ctrl_mem; // @[RocketCore.scala:244:21, :459:39] wire bypass_sources_2_1 = _bypass_sources_T & _bypass_sources_T_1; // @[RocketCore.scala:459:{20,36,39}] wire _id_bypass_src_T = ~(\|id_raddr1); // @[RocketCore.scala:326:72, :461:82, :1326:41] wire id_bypass_src_0_0 = _id_bypass_src_T; // @[RocketCore.scala:461:{74,82}] wire _GEN_39 = ex_waddr == id_raddr1; // @[RocketCore.scala:326:72, :453:36, :461:82] wire _id_bypass_src_T_1; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_1 = _GEN_39; // @[RocketCore.scala:461:82] wire _data_hazard_ex_T; // @[RocketCore.scala:989:70] assign _data_hazard_ex_T = _GEN_39; // @[RocketCore.scala:461:82, :989:70] wire _fp_data_hazard_ex_T_1; // @[RocketCore.scala:990:90] assign _fp_data_hazard_ex_T_1 = _GEN_39; // @[RocketCore.scala:461:82, :990:90] wire id_bypass_src_0_1 = bypass_sources_1_1 & _id_bypass_src_T_1; // @[RocketCore.scala:458:19, :461:{74,82}] wire _GEN_40 = mem_waddr == id_raddr1; // @[RocketCore.scala:326:72, :454:38, :461:82] wire _id_bypass_src_T_2; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_2 = _GEN_40; // @[RocketCore.scala:461:82] wire _id_bypass_src_T_3; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_3 = _GEN_40; // @[RocketCore.scala:461:82] wire _data_hazard_mem_T; // @[RocketCore.scala:998:72] assign _data_hazard_mem_T = _GEN_40; // @[RocketCore.scala:461:82, :998:72] wire _fp_data_hazard_mem_T_1; // @[RocketCore.scala:999:92] assign _fp_data_hazard_mem_T_1 = _GEN_40; // @[RocketCore.scala:461:82, :999:92] wire id_bypass_src_0_2 = bypass_sources_2_1 & _id_bypass_src_T_2; // @[RocketCore.scala:459:36, :461:{74,82}] wire id_bypass_src_0_3 = bypass_sources_3_1 & _id_bypass_src_T_3; // @[RocketCore.scala:460:20, :461:{74,82}] wire _id_bypass_src_T_4 = ~(\|id_raddr2); // @[RocketCore.scala:326:72, :461:82, :1326:41] wire id_bypass_src_1_0 = _id_bypass_src_T_4; // @[RocketCore.scala:461:{74,82}] wire _GEN_41 = ex_waddr == id_raddr2; // @[RocketCore.scala:326:72, :453:36, :461:82] wire _id_bypass_src_T_5; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_5 = _GEN_41; // @[RocketCore.scala:461:82] wire _data_hazard_ex_T_2; // @[RocketCore.scala:989:70] assign _data_hazard_ex_T_2 = _GEN_41; // @[RocketCore.scala:461:82, :989:70] wire _fp_data_hazard_ex_T_3; // @[RocketCore.scala:990:90] assign _fp_data_hazard_ex_T_3 = _GEN_41; // @[RocketCore.scala:461:82, :990:90] wire id_bypass_src_1_1 = bypass_sources_1_1 & _id_bypass_src_T_5; // @[RocketCore.scala:458:19, :461:{74,82}] wire _GEN_42 = mem_waddr == id_raddr2; // @[RocketCore.scala:326:72, :454:38, :461:82] wire _id_bypass_src_T_6; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_6 = _GEN_42; // @[RocketCore.scala:461:82] wire _id_bypass_src_T_7; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_7 = _GEN_42; // @[RocketCore.scala:461:82] wire _data_hazard_mem_T_2; // @[RocketCore.scala:998:72] assign _data_hazard_mem_T_2 = _GEN_42; // @[RocketCore.scala:461:82, :998:72] wire _fp_data_hazard_mem_T_3; // @[RocketCore.scala:999:92] assign _fp_data_hazard_mem_T_3 = _GEN_42; // @[RocketCore.scala:461:82, :999:92] wire id_bypass_src_1_2 = bypass_sources_2_1 & _id_bypass_src_T_6; // @[RocketCore.scala:459:36, :461:{74,82}] wire id_bypass_src_1_3 = bypass_sources_3_1 & _id_bypass_src_T_7; // @[RocketCore.scala:460:20, :461:{74,82}] reg ex_reg_rs_bypass_0; // @[RocketCore.scala:465:29] reg ex_reg_rs_bypass_1; // @[RocketCore.scala:465:29] reg [1:0] ex_reg_rs_lsb_0; // @[RocketCore.scala:466:26] reg [1:0] ex_reg_rs_lsb_1; // @[RocketCore.scala:466:26] reg [61:0] ex_reg_rs_msb_0; // @[RocketCore.scala:467:26] reg [61:0] ex_reg_rs_msb_1; // @[RocketCore.scala:467:26] wire _ex_rs_T = ex_reg_rs_lsb_0 == 2'h1; // @[package.scala:39:86] wire [63:0] _ex_rs_T_1 = _ex_rs_T ? mem_reg_wdata : 64'h0; // @[package.scala:39:{76,86}] wire _ex_rs_T_2 = ex_reg_rs_lsb_0 == 2'h2; // @[package.scala:39:86] wire [63:0] _ex_rs_T_3 = _ex_rs_T_2 ? wb_reg_wdata : _ex_rs_T_1; // @[package.scala:39:{76,86}] wire _ex_rs_T_4 = &ex_reg_rs_lsb_0; // @[package.scala:39:86] wire [63:0] _ex_rs_T_5 = _ex_rs_T_4 ? dcache_bypass_data : _ex_rs_T_3; // @[package.scala:39:{76,86}] wire [63:0] _ex_rs_T_6 = {ex_reg_rs_msb_0, ex_reg_rs_lsb_0}; // @[RocketCore.scala:466:26, :467:26, :469:69] assign ex_rs_0 = ex_reg_rs_bypass_0 ? _ex_rs_T_5 : _ex_rs_T_6; // @[package.scala:39:76] assign io_fpu_fromint_data_0 = ex_rs_0; // @[RocketCore.scala:153:7, :469:14] wire [63:0] _ex_op1_T = ex_rs_0; // @[RocketCore.scala:469:14, :473:24] wire _ex_rs_T_7 = ex_reg_rs_lsb_1 == 2'h1; // @[package.scala:39:86] wire [63:0] _ex_rs_T_8 = _ex_rs_T_7 ? mem_reg_wdata : 64'h0; // @[package.scala:39:{76,86}] wire _ex_rs_T_9 = ex_reg_rs_lsb_1 == 2'h2; // @[package.scala:39:86] wire [63:0] _ex_rs_T_10 = _ex_rs_T_9 ? wb_reg_wdata : _ex_rs_T_8; // @[package.scala:39:{76,86}] wire _ex_rs_T_11 = &ex_reg_rs_lsb_1; // @[package.scala:39:86] wire [63:0] _ex_rs_T_12 = _ex_rs_T_11 ? dcache_bypass_data : _ex_rs_T_10; // @[package.scala:39:{76,86}] wire [63:0] _ex_rs_T_13 = {ex_reg_rs_msb_1, ex_reg_rs_lsb_1}; // @[RocketCore.scala:466:26, :467:26, :469:69] wire [63:0] ex_rs_1 = ex_reg_rs_bypass_1 ? _ex_rs_T_12 : _ex_rs_T_13; // @[package.scala:39:76] wire [63:0] _ex_op2_T = ex_rs_1; // @[RocketCore.scala:469:14, :479:24] wire [63:0] mem_reg_rs2_dat_padded = ex_rs_1; // @[RocketCore.scala:469:14] wire _GEN_43 = ex_ctrl_sel_imm == 3'h5; // @[RocketCore.scala:243:20, :1341:24] wire _ex_imm_sign_T; // @[RocketCore.scala:1341:24] assign _ex_imm_sign_T = _GEN_43; // @[RocketCore.scala:1341:24] wire _ex_imm_b11_T_1; // @[RocketCore.scala:1344:40] assign _ex_imm_b11_T_1 = _GEN_43; // @[RocketCore.scala:1341:24, :1344:40] wire _ex_imm_b10_5_T_1; // @[RocketCore.scala:1347:42] assign _ex_imm_b10_5_T_1 = _GEN_43; // @[RocketCore.scala:1341:24, :1347:42] wire _ex_imm_b4_1_T_5; // @[RocketCore.scala:1350:24] assign _ex_imm_b4_1_T_5 = _GEN_43; // @[RocketCore.scala:1341:24, :1350:24] wire _ex_imm_b0_T_4; // @[RocketCore.scala:1353:22] assign _ex_imm_b0_T_4 = _GEN_43; // @[RocketCore.scala:1341:24, :1353:22] wire _ex_imm_sign_T_1 = ex_reg_inst[31]; // @[RocketCore.scala:259:24, :1341:44] wire _ex_imm_sign_T_2 = _ex_imm_sign_T_1; // @[RocketCore.scala:1341:{44,49}] wire ex_imm_sign = ~_ex_imm_sign_T & _ex_imm_sign_T_2; // @[RocketCore.scala:1341:{19,24,49}] wire ex_imm_hi_hi_hi = ex_imm_sign; // @[RocketCore.scala:1341:19, :1355:8] wire _GEN_44 = ex_ctrl_sel_imm == 3'h2; // @[RocketCore.scala:243:20, :1342:26] wire _ex_imm_b30_20_T; // @[RocketCore.scala:1342:26] assign _ex_imm_b30_20_T = _GEN_44; // @[RocketCore.scala:1342:26] wire _ex_imm_b11_T; // @[RocketCore.scala:1344:23] assign _ex_imm_b11_T = _GEN_44; // @[RocketCore.scala:1342:26, :1344:23] wire _ex_imm_b10_5_T; // @[RocketCore.scala:1347:25] assign _ex_imm_b10_5_T = _GEN_44; // @[RocketCore.scala:1342:26, :1347:25] wire _ex_imm_b4_1_T; // @[RocketCore.scala:1348:24] assign _ex_imm_b4_1_T = _GEN_44; // @[RocketCore.scala:1342:26, :1348:24] wire [10:0] _ex_imm_b30_20_T_1 = ex_reg_inst[30:20]; // @[RocketCore.scala:259:24, :1342:41] wire [10:0] _ex_imm_b30_20_T_2 = _ex_imm_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}] wire [10:0] ex_imm_b30_20 = _ex_imm_b30_20_T ? _ex_imm_b30_20_T_2 : {11{ex_imm_sign}}; // @[RocketCore.scala:1341:19, :1342:{21,26,49}] wire [10:0] ex_imm_hi_hi_lo = ex_imm_b30_20; // @[RocketCore.scala:1342:21, :1355:8] wire _ex_imm_b19_12_T = ex_ctrl_sel_imm != 3'h2; // @[RocketCore.scala:243:20, :1343:26] wire _ex_imm_b19_12_T_1 = ex_ctrl_sel_imm != 3'h3; // @[RocketCore.scala:243:20, :1343:43] wire _ex_imm_b19_12_T_2 = _ex_imm_b19_12_T & _ex_imm_b19_12_T_1; // @[RocketCore.scala:1343:{26,36,43}] wire [7:0] _ex_imm_b19_12_T_3 = ex_reg_inst[19:12]; // @[RocketCore.scala:259:24, :1343:65] wire [7:0] _ex_imm_b19_12_T_4 = _ex_imm_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}] wire [7:0] ex_imm_b19_12 = _ex_imm_b19_12_T_2 ? {8{ex_imm_sign}} : _ex_imm_b19_12_T_4; // @[RocketCore.scala:1341:19, :1343:{21,36,73}] wire [7:0] ex_imm_hi_lo_hi = ex_imm_b19_12; // @[RocketCore.scala:1343:21, :1355:8] wire _ex_imm_b11_T_2 = _ex_imm_b11_T \| _ex_imm_b11_T_1; // @[RocketCore.scala:1344:{23,33,40}] wire _ex_imm_b11_T_3 = ex_ctrl_sel_imm == 3'h3; // @[RocketCore.scala:243:20, :1345:23] wire _ex_imm_b11_T_4 = ex_reg_inst[20]; // @[RocketCore.scala:259:24, :1345:39] wire _ex_imm_b0_T_3 = ex_reg_inst[20]; // @[RocketCore.scala:259:24, :1345:39, :1352:37] wire _io_dmem_req_bits_signed_T = ex_reg_inst[20]; // @[RocketCore.scala:259:24, :1136:58, :1345:39] wire _ex_imm_b11_T_5 = _ex_imm_b11_T_4; // @[RocketCore.scala:1345:{39,44}] wire _GEN_45 = ex_ctrl_sel_imm == 3'h1; // @[RocketCore.scala:243:20, :1346:23] wire _ex_imm_b11_T_6; // @[RocketCore.scala:1346:23] assign _ex_imm_b11_T_6 = _GEN_45; // @[RocketCore.scala:1346:23] wire _ex_imm_b4_1_T_2; // @[RocketCore.scala:1349:41] assign _ex_imm_b4_1_T_2 = _GEN_45; // @[RocketCore.scala:1346:23, :1349:41] wire _ex_imm_b11_T_7 = ex_reg_inst[7]; // @[RocketCore.scala:259:24, :1346:39] wire _ex_imm_b0_T_1 = ex_reg_inst[7]; // @[RocketCore.scala:259:24, :1346:39, :1351:37] wire _ex_imm_b11_T_8 = _ex_imm_b11_T_7; // @[RocketCore.scala:1346:{39,43}] wire _ex_imm_b11_T_9 = _ex_imm_b11_T_6 ? _ex_imm_b11_T_8 : ex_imm_sign; // @[RocketCore.scala:1341:19, :1346:{18,23,43}] wire _ex_imm_b11_T_10 = _ex_imm_b11_T_3 ? _ex_imm_b11_T_5 : _ex_imm_b11_T_9; // @[RocketCore.scala:1345:{18,23,44}, :1346:18] wire ex_imm_b11 = ~_ex_imm_b11_T_2 & _ex_imm_b11_T_10; // @[RocketCore.scala:1344:{18,33}, :1345:18] wire ex_imm_hi_lo_lo = ex_imm_b11; // @[RocketCore.scala:1344:18, :1355:8] wire _ex_imm_b10_5_T_2 = _ex_imm_b10_5_T \| _ex_imm_b10_5_T_1; // @[RocketCore.scala:1347:{25,35,42}] wire [5:0] _ex_imm_b10_5_T_3 = ex_reg_inst[30:25]; // @[RocketCore.scala:259:24, :1347:62] wire [5:0] ex_imm_b10_5 = _ex_imm_b10_5_T_2 ? 6'h0 : _ex_imm_b10_5_T_3; // @[RocketCore.scala:1347:{20,35,62}] wire _GEN_46 = ex_ctrl_sel_imm == 3'h0; // @[RocketCore.scala:243:20, :1349:24] wire _ex_imm_b4_1_T_1; // @[RocketCore.scala:1349:24] assign _ex_imm_b4_1_T_1 = _GEN_46; // @[RocketCore.scala:1349:24] wire _ex_imm_b0_T; // @[RocketCore.scala:1351:22] assign _ex_imm_b0_T = _GEN_46; // @[RocketCore.scala:1349:24, :1351:22] wire _ex_imm_b4_1_T_3 = _ex_imm_b4_1_T_1 \| _ex_imm_b4_1_T_2; // @[RocketCore.scala:1349:{24,34,41}] wire [3:0] _ex_imm_b4_1_T_4 = ex_reg_inst[11:8]; // @[RocketCore.scala:259:24, :1349:57] wire [3:0] _ex_imm_b4_1_T_6 = ex_reg_inst[19:16]; // @[RocketCore.scala:259:24, :1350:39] wire [3:0] _ex_imm_b4_1_T_7 = ex_reg_inst[24:21]; // @[RocketCore.scala:259:24, :1350:52] wire [3:0] _ex_imm_b4_1_T_8 = _ex_imm_b4_1_T_5 ? _ex_imm_b4_1_T_6 : _ex_imm_b4_1_T_7; // @[RocketCore.scala:1350:{19,24,39,52}] wire [3:0] _ex_imm_b4_1_T_9 = _ex_imm_b4_1_T_3 ? _ex_imm_b4_1_T_4 : _ex_imm_b4_1_T_8; // @[RocketCore.scala:1349:{19,34,57}, :1350:19] wire [3:0] ex_imm_b4_1 = _ex_imm_b4_1_T ? 4'h0 : _ex_imm_b4_1_T_9; // @[RocketCore.scala:1348:{19,24}, :1349:19] wire _ex_imm_b0_T_2 = ex_ctrl_sel_imm == 3'h4; // @[RocketCore.scala:243:20, :1352:22] wire _ex_imm_b0_T_5 = ex_reg_inst[15]; // @[RocketCore.scala:259:24, :1353:37] wire _ex_imm_b0_T_6 = _ex_imm_b0_T_4 & _ex_imm_b0_T_5; // @[RocketCore.scala:1353:{17,22,37}] wire _ex_imm_b0_T_7 = _ex_imm_b0_T_2 ? _ex_imm_b0_T_3 : _ex_imm_b0_T_6; // @[RocketCore.scala:1352:{17,22,37}, :1353:17] wire ex_imm_b0 = _ex_imm_b0_T ? _ex_imm_b0_T_1 : _ex_imm_b0_T_7; // @[RocketCore.scala:1351:{17,22,37}, :1352:17] wire [9:0] ex_imm_lo_hi = {ex_imm_b10_5, ex_imm_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] ex_imm_lo = {ex_imm_lo_hi, ex_imm_b0}; // @[RocketCore.scala:1351:17, :1355:8] wire [8:0] ex_imm_hi_lo = {ex_imm_hi_lo_hi, ex_imm_hi_lo_lo}; // @[RocketCore.scala:1355:8] wire [11:0] ex_imm_hi_hi = {ex_imm_hi_hi_hi, ex_imm_hi_hi_lo}; // @[RocketCore.scala:1355:8] wire [20:0] ex_imm_hi = {ex_imm_hi_hi, ex_imm_hi_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _ex_imm_T = {ex_imm_hi, ex_imm_lo}; // @[RocketCore.scala:1355:8] wire [31:0] ex_imm = _ex_imm_T; // @[RocketCore.scala:1355:{8,53}] wire _ex_rs1shl_T = ex_reg_inst[3]; // @[RocketCore.scala:259:24, :471:34] wire [31:0] _ex_rs1shl_T_1 = ex_rs_0[31:0]; // @[RocketCore.scala:469:14, :471:47] wire [63:0] _ex_rs1shl_T_2 = _ex_rs1shl_T ? {32'h0, _ex_rs1shl_T_1} : ex_rs_0; // @[RocketCore.scala:469:14, :471:{22,34,47}] wire [1:0] _ex_rs1shl_T_3 = ex_reg_inst[14:13]; // @[RocketCore.scala:259:24, :471:79] wire [66:0] ex_rs1shl = {3'h0, _ex_rs1shl_T_2} << _ex_rs1shl_T_3; // @[RocketCore.scala:471:{22,65,79}] wire [66:0] _ex_op1_T_2 = ex_rs1shl; // @[RocketCore.scala:471:65, :475:54] wire _ex_op1_T_3 = ex_ctrl_sel_alu1 == 2'h1; // @[RocketCore.scala:243:20, :472:48] wire [63:0] _ex_op1_T_4 = _ex_op1_T_3 ? _ex_op1_T : 64'h0; // @[RocketCore.scala:472:48, :473:24] wire _ex_op1_T_5 = ex_ctrl_sel_alu1 == 2'h2; // @[RocketCore.scala:243:20, :472:48] wire [63:0] _ex_op1_T_6 = _ex_op1_T_5 ? {{24{_ex_op1_T_1[39]}}, _ex_op1_T_1} : _ex_op1_T_4; // @[RocketCore.scala:472:48, :474:24] wire _ex_op1_T_7 = &ex_ctrl_sel_alu1; // @[RocketCore.scala:243:20, :472:48] wire [66:0] ex_op1 = _ex_op1_T_7 ? _ex_op1_T_2 : {{3{_ex_op1_T_6[63]}}, _ex_op1_T_6}; // @[RocketCore.scala:472:48, :475:54] wire [66:0] _alu_io_in1_T = ex_op1; // @[RocketCore.scala:472:48, :508:24] wire _ex_op2_oh_T = ex_ctrl_sel_alu2[0]; // @[RocketCore.scala:243:20, :477:48] wire [11:0] _ex_op2_oh_T_1 = ex_reg_inst[31:20]; // @[RocketCore.scala:259:24, :477:66] wire [63:0] _ex_op2_oh_T_2 = _ex_op2_oh_T ? {52'h0, _ex_op2_oh_T_1} : ex_rs_1; // @[RocketCore.scala:469:14, :477:{31,48,66}] wire [5:0] _ex_op2_oh_T_3 = _ex_op2_oh_T_2[5:0]; // @[RocketCore.scala:477:{31,90}] wire [63:0] _ex_op2_oh_T_4 = 64'h1 << _ex_op2_oh_T_3; // @[OneHot.scala:58:35] wire [63:0] ex_op2_oh = _ex_op2_oh_T_4; // @[OneHot.scala:58:35] wire [3:0] _ex_op2_T_1 = ex_reg_rvc ? 4'h2 : 4'h4; // @[RocketCore.scala:249:35, :481:19] wire _ex_op2_T_2 = ex_ctrl_sel_alu2 == 3'h2; // @[RocketCore.scala:243:20, :478:48] wire [63:0] _ex_op2_T_3 = _ex_op2_T_2 ? _ex_op2_T : 64'h0; // @[RocketCore.scala:478:48, :479:24] wire _ex_op2_T_4 = ex_ctrl_sel_alu2 == 3'h3; // @[RocketCore.scala:243:20, :478:48] wire [63:0] _ex_op2_T_5 = _ex_op2_T_4 ? {{32{ex_imm[31]}}, ex_imm} : _ex_op2_T_3; // @[RocketCore.scala:478:48, :1355:53] wire _ex_op2_T_6 = ex_ctrl_sel_alu2 == 3'h1; // @[RocketCore.scala:243:20, :478:48] wire [63:0] _ex_op2_T_7 = _ex_op2_T_6 ? {{60{_ex_op2_T_1[3]}}, _ex_op2_T_1} : _ex_op2_T_5; // @[RocketCore.scala:478:48, :481:19] wire _ex_op2_T_8 = ex_ctrl_sel_alu2 == 3'h4; // @[RocketCore.scala:243:20, :478:48] wire [63:0] _ex_op2_T_9 = _ex_op2_T_8 ? ex_op2_oh : _ex_op2_T_7; // @[RocketCore.scala:477:112, :478:48] wire _ex_op2_T_10 = ex_ctrl_sel_alu2 == 3'h5; // @[RocketCore.scala:243:20, :478:48] wire [63:0] ex_op2 = _ex_op2_T_10 ? ex_op2_oh : _ex_op2_T_9; // @[RocketCore.scala:477:112, :478:48] wire [63:0] _alu_io_in2_T = ex_op2; // @[RocketCore.scala:478:48, :507:24] wire _div_io_req_valid_T = ex_reg_valid & ex_ctrl_div; // @[RocketCore.scala:243:20, :248:35, :512:36] wire _ex_reg_valid_T = ~ctrl_killd; // @[RocketCore.scala:338:24, :525:19] wire _ex_reg_replay_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20] wire _ex_reg_replay_T_1 = _ex_reg_replay_T & _ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20, :526:{20,29}] wire _ex_reg_replay_T_2 = _ex_reg_replay_T_1 & _ibuf_io_inst_0_bits_replay; // @[RocketCore.scala:311:20, :526:{29,54}] wire _ex_reg_xcpt_T = ~ctrl_killd; // @[RocketCore.scala:338:24, :525:19, :527:18] wire _ex_reg_xcpt_T_1 = _ex_reg_xcpt_T & id_xcpt; // @[RocketCore.scala:527:{18,30}, :1278:14] wire _ex_reg_xcpt_interrupt_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20, :528:28] wire _ex_reg_xcpt_interrupt_T_1 = _ex_reg_xcpt_interrupt_T & _ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20, :528:{28,37}] wire _ex_reg_xcpt_interrupt_T_2 = _ex_reg_xcpt_interrupt_T_1 & _csr_io_interrupt; // @[RocketCore.scala:341:19, :528:{37,62}] wire [1:0] hi = {_ibuf_io_inst_0_bits_xcpt1_pf_inst, _ibuf_io_inst_0_bits_xcpt1_gf_inst}; // @[RocketCore.scala:311:20, :541:22] wire [1:0] hi_1 = {_ibuf_io_inst_0_bits_xcpt0_pf_inst, _ibuf_io_inst_0_bits_xcpt0_gf_inst}; // @[RocketCore.scala:311:20, :546:40] wire _ex_reg_flush_pipe_T = id_ctrl_fence_i \| id_csr_flush; // @[RocketCore.scala:321:21, :346:37, :551:42] wire _ex_reg_hls_T_1 = id_ctrl_mem_cmd == 5'h0; // @[package.scala:16:47] wire _ex_reg_hls_T_2 = id_ctrl_mem_cmd == 5'h1; // @[package.scala:16:47] wire _ex_reg_hls_T_3 = id_ctrl_mem_cmd == 5'h10; // @[package.scala:16:47] wire _ex_reg_hls_T_4 = _ex_reg_hls_T_1 \| _ex_reg_hls_T_2; // @[package.scala:16:47, :81:59] wire _ex_reg_hls_T_5 = _ex_reg_hls_T_4 \| _ex_reg_hls_T_3; // @[package.scala:16:47, :81:59] wire [1:0] _ex_reg_mem_size_T_1 = _ibuf_io_inst_0_bits_inst_bits[27:26]; // @[RocketCore.scala:311:20, :554:75] wire [1:0] _ex_reg_mem_size_T_2 = _ibuf_io_inst_0_bits_inst_bits[13:12]; // @[RocketCore.scala:311:20, :554:95] wire [1:0] _ex_reg_mem_size_T_3 = _ex_reg_mem_size_T_2; // @[RocketCore.scala:554:{27,95}] wire _ex_reg_mem_size_T_4 = \|id_raddr2; // @[RocketCore.scala:326:72, :556:40, :1326:41] wire _ex_reg_mem_size_T_5 = \|id_raddr1; // @[RocketCore.scala:326:72, :556:59, :1326:41] wire [1:0] _ex_reg_mem_size_T_6 = {_ex_reg_mem_size_T_4, _ex_reg_mem_size_T_5}; // @[RocketCore.scala:556:{29,40,59}] wire _do_bypass_T = id_bypass_src_0_0 \| id_bypass_src_0_1; // @[RocketCore.scala:461:74, :568:48] wire _do_bypass_T_1 = _do_bypass_T \| id_bypass_src_0_2; // @[RocketCore.scala:461:74, :568:48] wire do_bypass = _do_bypass_T_1 \| id_bypass_src_0_3; // @[RocketCore.scala:461:74, :568:48] wire [1:0] _bypass_src_T = {1'h1, ~id_bypass_src_0_2}; // @[Mux.scala:50:70] wire [1:0] _bypass_src_T_1 = id_bypass_src_0_1 ? 2'h1 : _bypass_src_T; // @[Mux.scala:50:70] wire [1:0] bypass_src = id_bypass_src_0_0 ? 2'h0 : _bypass_src_T_1; // @[Mux.scala:50:70] wire [1:0] _ex_reg_rs_lsb_0_T = id_rs_0[1:0]; // @[RocketCore.scala:573:37, :1325:26] wire [61:0] _ex_reg_rs_msb_0_T = id_rs_0[63:2]; // @[RocketCore.scala:574:38, :1325:26] wire _do_bypass_T_2 = id_bypass_src_1_0 \| id_bypass_src_1_1; // @[RocketCore.scala:461:74, :568:48] wire _do_bypass_T_3 = _do_bypass_T_2 \| id_bypass_src_1_2; // @[RocketCore.scala:461:74, :568:48] wire do_bypass_1 = _do_bypass_T_3 \| id_bypass_src_1_3; // @[RocketCore.scala:461:74, :568:48] wire [1:0] _bypass_src_T_2 = {1'h1, ~id_bypass_src_1_2}; // @[Mux.scala:50:70] wire [1:0] _bypass_src_T_3 = id_bypass_src_1_1 ? 2'h1 : _bypass_src_T_2; // @[Mux.scala:50:70] wire [1:0] bypass_src_1 = id_bypass_src_1_0 ? 2'h0 : _bypass_src_T_3; // @[Mux.scala:50:70] wire [1:0] _ex_reg_rs_lsb_1_T = id_rs_1[1:0]; // @[RocketCore.scala:573:37, :1325:26] wire [61:0] _ex_reg_rs_msb_1_T = id_rs_1[63:2]; // @[RocketCore.scala:574:38, :1325:26] wire [15:0] _inst_T = _ibuf_io_inst_0_bits_raw[15:0]; // @[RocketCore.scala:311:20, :578:62] wire [31:0] inst = _ibuf_io_inst_0_bits_rvc ? {16'h0, _inst_T} : _ibuf_io_inst_0_bits_raw; // @[RocketCore.scala:311:20, :578:{21,62}] wire [1:0] _ex_reg_rs_lsb_0_T_1 = inst[1:0]; // @[RocketCore.scala:578:21, :580:31] wire [29:0] _ex_reg_rs_msb_0_T_1 = inst[31:2]; // @[RocketCore.scala:578:21, :581:32] wire _ex_reg_set_vconfig_T = ~id_xcpt; // @[RocketCore.scala:591:45, :1278:14] wire _ex_pc_valid_T = ex_reg_valid \| ex_reg_replay; // @[RocketCore.scala:248:35, :255:26, :595:34] wire ex_pc_valid = _ex_pc_valid_T \| ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35, :595:{34,51}] wire _wb_dcache_miss_T = ~io_dmem_resp_valid_0; // @[RocketCore.scala:153:7, :596:39] wire wb_dcache_miss = wb_ctrl_mem & _wb_dcache_miss_T; // @[RocketCore.scala:245:20, :596:{36,39}] wire _replay_ex_structural_T = ~io_dmem_req_ready_0; // @[RocketCore.scala:153:7, :597:45] wire _replay_ex_structural_T_1 = ex_ctrl_mem & _replay_ex_structural_T; // @[RocketCore.scala:243:20, :597:{42,45}] wire _replay_ex_structural_T_2 = ~_div_io_req_ready; // @[RocketCore.scala:511:19, :598:45] wire _replay_ex_structural_T_3 = ex_ctrl_div & _replay_ex_structural_T_2; // @[RocketCore.scala:243:20, :598:{42,45}] wire _replay_ex_structural_T_4 = _replay_ex_structural_T_1 \| _replay_ex_structural_T_3; // @[RocketCore.scala:597:{42,64}, :598:42] wire replay_ex_structural = _replay_ex_structural_T_4; // @[RocketCore.scala:597:64, :598:63] wire replay_ex_load_use = wb_dcache_miss & ex_reg_load_use; // @[RocketCore.scala:253:35, :596:36, :600:43] wire _replay_ex_T = replay_ex_structural \| replay_ex_load_use; // @[RocketCore.scala:598:63, :600:43, :601:75] wire _replay_ex_T_1 = ex_reg_valid & _replay_ex_T; // @[RocketCore.scala:248:35, :601:{50,75}] wire replay_ex = ex_reg_replay \| _replay_ex_T_1; // @[RocketCore.scala:255:26, :601:{33,50}] wire _ctrl_killx_T = take_pc_mem_wb \| replay_ex; // @[RocketCore.scala:307:35, :601:33, :602:35] wire _ctrl_killx_T_1 = ~ex_reg_valid; // @[RocketCore.scala:248:35, :602:51] assign ctrl_killx = _ctrl_killx_T \| _ctrl_killx_T_1; // @[RocketCore.scala:602:{35,48,51}] assign io_fpu_killx_0 = ctrl_killx; // @[RocketCore.scala:153:7, :602:48] wire _GEN_47 = ex_ctrl_mem_cmd == 5'h7; // @[RocketCore.scala:243:20, :604:40] wire _ex_slow_bypass_T; // @[RocketCore.scala:604:40] assign _ex_slow_bypass_T = _GEN_47; // @[RocketCore.scala:604:40] wire _mem_reg_load_T_3; // @[package.scala:16:47] assign _mem_reg_load_T_3 = _GEN_47; // @[package.scala:16:47] wire _mem_reg_store_T_3; // @[Consts.scala:90:66] assign _mem_reg_store_T_3 = _GEN_47; // @[RocketCore.scala:604:40] wire _io_dmem_req_bits_no_resp_T_3; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_3 = _GEN_47; // @[package.scala:16:47] wire _ex_slow_bypass_T_1 = ~(ex_reg_mem_size[1]); // @[RocketCore.scala:257:28, :604:69] wire ex_slow_bypass = _ex_slow_bypass_T \| _ex_slow_bypass_T_1; // @[RocketCore.scala:604:{40,50,69}] wire _ex_sfence_T_1 = ex_ctrl_mem_cmd == 5'h14; // @[RocketCore.scala:243:20, :605:64] wire _ex_sfence_T_2 = ex_ctrl_mem_cmd == 5'h15; // @[RocketCore.scala:243:20, :605:96] wire _ex_sfence_T_3 = _ex_sfence_T_1 \| _ex_sfence_T_2; // @[RocketCore.scala:605:{64,77,96}] wire _ex_sfence_T_4 = ex_ctrl_mem_cmd == 5'h16; // @[RocketCore.scala:243:20, :605:129] wire _ex_sfence_T_5 = _ex_sfence_T_3 \| _ex_sfence_T_4; // @[RocketCore.scala:605:{77,110,129}] wire ex_sfence = _ex_sfence_T & _ex_sfence_T_5; // @[RocketCore.scala:605:{29,44,110}] wire ex_xcpt = ex_reg_xcpt_interrupt \| ex_reg_xcpt; // @[RocketCore.scala:247:35, :251:35, :608:28, :1278:14] wire _mem_pc_valid_T = mem_reg_valid \| mem_reg_replay; // @[RocketCore.scala:265:36, :269:36, :614:36] wire mem_pc_valid = _mem_pc_valid_T \| mem_reg_xcpt_interrupt; // @[RocketCore.scala:264:36, :614:{36,54}] wire _GEN_48 = mem_ctrl_branch & mem_br_taken; // @[RocketCore.scala:244:21, :284:25, :616:25] wire _mem_br_target_T_1; // @[RocketCore.scala:616:25] assign _mem_br_target_T_1 = _GEN_48; // @[RocketCore.scala:616:25] wire _mem_cfi_taken_T; // @[RocketCore.scala:626:40] assign _mem_cfi_taken_T = _GEN_48; // @[RocketCore.scala:616:25, :626:40] wire _mem_br_target_sign_T_1 = mem_reg_inst[31]; // @[RocketCore.scala:278:25, :1341:44] wire _mem_br_target_sign_T_4 = mem_reg_inst[31]; // @[RocketCore.scala:278:25, :1341:44] wire _mem_br_target_sign_T_2 = _mem_br_target_sign_T_1; // @[RocketCore.scala:1341:{44,49}] wire mem_br_target_sign = _mem_br_target_sign_T_2; // @[RocketCore.scala:1341:{19,49}] wire mem_br_target_hi_hi_hi = mem_br_target_sign; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _mem_br_target_b30_20_T_1 = mem_reg_inst[30:20]; // @[RocketCore.scala:278:25, :1342:41] wire [10:0] _mem_br_target_b30_20_T_4 = mem_reg_inst[30:20]; // @[RocketCore.scala:278:25, :1342:41] wire [10:0] _mem_br_target_b30_20_T_2 = _mem_br_target_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}] wire [10:0] mem_br_target_b30_20 = {11{mem_br_target_sign}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] mem_br_target_hi_hi_lo = mem_br_target_b30_20; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _mem_br_target_b19_12_T_3 = mem_reg_inst[19:12]; // @[RocketCore.scala:278:25, :1343:65] wire [7:0] _mem_br_target_b19_12_T_8 = mem_reg_inst[19:12]; // @[RocketCore.scala:278:25, :1343:65] wire [7:0] _mem_br_target_b19_12_T_4 = _mem_br_target_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}] wire [7:0] mem_br_target_b19_12 = {8{mem_br_target_sign}}; // @[RocketCore.scala:1341:19, :1343:21] wire [7:0] mem_br_target_hi_lo_hi = mem_br_target_b19_12; // @[RocketCore.scala:1343:21, :1355:8] wire _mem_br_target_b11_T_4 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39] wire _mem_br_target_b0_T_3 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39, :1352:37] wire _mem_br_target_b11_T_15 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39] wire _mem_br_target_b0_T_11 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39, :1352:37] wire _mem_br_target_b11_T_5 = _mem_br_target_b11_T_4; // @[RocketCore.scala:1345:{39,44}] wire _mem_br_target_b11_T_7 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39] wire _mem_br_target_b0_T_1 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39, :1351:37] wire _mem_br_target_b11_T_18 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39] wire _mem_br_target_b0_T_9 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39, :1351:37] wire _mem_br_target_b11_T_8 = _mem_br_target_b11_T_7; // @[RocketCore.scala:1346:{39,43}] wire _mem_br_target_b11_T_9 = _mem_br_target_b11_T_8; // @[RocketCore.scala:1346:{18,43}] wire _mem_br_target_b11_T_10 = _mem_br_target_b11_T_9; // @[RocketCore.scala:1345:18, :1346:18] wire mem_br_target_b11 = _mem_br_target_b11_T_10; // @[RocketCore.scala:1344:18, :1345:18] wire mem_br_target_hi_lo_lo = mem_br_target_b11; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] _mem_br_target_b10_5_T_3 = mem_reg_inst[30:25]; // @[RocketCore.scala:278:25, :1347:62] wire [5:0] _mem_br_target_b10_5_T_7 = mem_reg_inst[30:25]; // @[RocketCore.scala:278:25, :1347:62] wire [5:0] mem_br_target_b10_5 = _mem_br_target_b10_5_T_3; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _mem_br_target_b4_1_T_4 = mem_reg_inst[11:8]; // @[RocketCore.scala:278:25, :1349:57] wire [3:0] _mem_br_target_b4_1_T_14 = mem_reg_inst[11:8]; // @[RocketCore.scala:278:25, :1349:57] wire [3:0] _mem_br_target_b4_1_T_9 = _mem_br_target_b4_1_T_4; // @[RocketCore.scala:1349:{19,57}] wire [3:0] _mem_br_target_b4_1_T_6 = mem_reg_inst[19:16]; // @[RocketCore.scala:278:25, :1350:39] wire [3:0] _mem_br_target_b4_1_T_16 = mem_reg_inst[19:16]; // @[RocketCore.scala:278:25, :1350:39] wire [3:0] _mem_br_target_b4_1_T_7 = mem_reg_inst[24:21]; // @[RocketCore.scala:278:25, :1350:52] wire [3:0] _mem_br_target_b4_1_T_17 = mem_reg_inst[24:21]; // @[RocketCore.scala:278:25, :1350:52] wire [3:0] _mem_br_target_b4_1_T_8 = _mem_br_target_b4_1_T_7; // @[RocketCore.scala:1350:{19,52}] wire [3:0] mem_br_target_b4_1 = _mem_br_target_b4_1_T_9; // @[RocketCore.scala:1348:19, :1349:19] wire _mem_br_target_b0_T_5 = mem_reg_inst[15]; // @[RocketCore.scala:278:25, :1353:37] wire _mem_br_target_b0_T_13 = mem_reg_inst[15]; // @[RocketCore.scala:278:25, :1353:37] wire [9:0] mem_br_target_lo_hi = {mem_br_target_b10_5, mem_br_target_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] mem_br_target_lo = {mem_br_target_lo_hi, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] mem_br_target_hi_lo = {mem_br_target_hi_lo_hi, mem_br_target_hi_lo_lo}; // @[RocketCore.scala:1355:8] wire [11:0] mem_br_target_hi_hi = {mem_br_target_hi_hi_hi, mem_br_target_hi_hi_lo}; // @[RocketCore.scala:1355:8] wire [20:0] mem_br_target_hi = {mem_br_target_hi_hi, mem_br_target_hi_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_br_target_T_2 = {mem_br_target_hi, mem_br_target_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_br_target_T_3 = _mem_br_target_T_2; // @[RocketCore.scala:1355:{8,53}] wire _mem_br_target_sign_T_5 = _mem_br_target_sign_T_4; // @[RocketCore.scala:1341:{44,49}] wire mem_br_target_sign_1 = _mem_br_target_sign_T_5; // @[RocketCore.scala:1341:{19,49}] wire _mem_br_target_b11_T_20 = mem_br_target_sign_1; // @[RocketCore.scala:1341:19, :1346:18] wire mem_br_target_hi_hi_hi_1 = mem_br_target_sign_1; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _mem_br_target_b30_20_T_5 = _mem_br_target_b30_20_T_4; // @[RocketCore.scala:1342:{41,49}] wire [10:0] mem_br_target_b30_20_1 = {11{mem_br_target_sign_1}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] mem_br_target_hi_hi_lo_1 = mem_br_target_b30_20_1; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _mem_br_target_b19_12_T_9 = _mem_br_target_b19_12_T_8; // @[RocketCore.scala:1343:{65,73}] wire [7:0] mem_br_target_b19_12_1 = _mem_br_target_b19_12_T_9; // @[RocketCore.scala:1343:{21,73}] wire [7:0] mem_br_target_hi_lo_hi_1 = mem_br_target_b19_12_1; // @[RocketCore.scala:1343:21, :1355:8] wire _mem_br_target_b11_T_16 = _mem_br_target_b11_T_15; // @[RocketCore.scala:1345:{39,44}] wire _mem_br_target_b11_T_21 = _mem_br_target_b11_T_16; // @[RocketCore.scala:1345:{18,44}] wire _mem_br_target_b11_T_19 = _mem_br_target_b11_T_18; // @[RocketCore.scala:1346:{39,43}] wire mem_br_target_b11_1 = _mem_br_target_b11_T_21; // @[RocketCore.scala:1344:18, :1345:18] wire mem_br_target_hi_lo_lo_1 = mem_br_target_b11_1; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] mem_br_target_b10_5_1 = _mem_br_target_b10_5_T_7; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _mem_br_target_b4_1_T_18 = _mem_br_target_b4_1_T_17; // @[RocketCore.scala:1350:{19,52}] wire [3:0] _mem_br_target_b4_1_T_19 = _mem_br_target_b4_1_T_18; // @[RocketCore.scala:1349:19, :1350:19] wire [3:0] mem_br_target_b4_1_1 = _mem_br_target_b4_1_T_19; // @[RocketCore.scala:1348:19, :1349:19] wire [9:0] mem_br_target_lo_hi_1 = {mem_br_target_b10_5_1, mem_br_target_b4_1_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] mem_br_target_lo_1 = {mem_br_target_lo_hi_1, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] mem_br_target_hi_lo_1 = {mem_br_target_hi_lo_hi_1, mem_br_target_hi_lo_lo_1}; // @[RocketCore.scala:1355:8] wire [11:0] mem_br_target_hi_hi_1 = {mem_br_target_hi_hi_hi_1, mem_br_target_hi_hi_lo_1}; // @[RocketCore.scala:1355:8] wire [20:0] mem_br_target_hi_1 = {mem_br_target_hi_hi_1, mem_br_target_hi_lo_1}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_br_target_T_4 = {mem_br_target_hi_1, mem_br_target_lo_1}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_br_target_T_5 = _mem_br_target_T_4; // @[RocketCore.scala:1355:{8,53}] wire [3:0] _mem_br_target_T_6 = mem_reg_rvc ? 4'h2 : 4'h4; // @[RocketCore.scala:266:36, :618:8] wire [31:0] _mem_br_target_T_7 = mem_ctrl_jal ? _mem_br_target_T_5 : {{28{_mem_br_target_T_6[3]}}, _mem_br_target_T_6}; // @[RocketCore.scala:244:21, :617:8, :618:8, :1355:53] wire [31:0] _mem_br_target_T_8 = _mem_br_target_T_1 ? _mem_br_target_T_3 : _mem_br_target_T_7; // @[RocketCore.scala:616:{8,25}, :617:8, :1355:53] wire [40:0] _mem_br_target_T_9 = {_mem_br_target_T[39], _mem_br_target_T} + {{9{_mem_br_target_T_8[31]}}, _mem_br_target_T_8}; // @[RocketCore.scala:615:{34,41}, :616:8] wire [39:0] _mem_br_target_T_10 = _mem_br_target_T_9[39:0]; // @[RocketCore.scala:615:41] wire [39:0] mem_br_target = _mem_br_target_T_10; // @[RocketCore.scala:615:41] wire _mem_npc_T = mem_ctrl_jalr \| mem_reg_sfence; // @[RocketCore.scala:244:21, :276:27, :619:36] wire [24:0] _mem_npc_a_T = mem_reg_wdata[63:39]; // @[RocketCore.scala:282:26, :1293:17] wire [24:0] mem_npc_a = _mem_npc_a_T; // @[RocketCore.scala:1293:{17,23}] wire _mem_npc_msb_T = mem_npc_a == 25'h0; // @[RocketCore.scala:1293:23, :1294:21] wire _mem_npc_msb_T_1 = &mem_npc_a; // @[RocketCore.scala:1293:23, :1294:34] wire _mem_npc_msb_T_2 = _mem_npc_msb_T \| _mem_npc_msb_T_1; // @[RocketCore.scala:1294:{21,29,34}] wire _mem_npc_msb_T_3 = mem_reg_wdata[39]; // @[RocketCore.scala:282:26, :1294:46] wire _mem_npc_msb_T_4 = mem_reg_wdata[38]; // @[RocketCore.scala:282:26, :1294:54] wire _mem_npc_msb_T_5 = ~_mem_npc_msb_T_4; // @[RocketCore.scala:1294:{51,54}] wire mem_npc_msb = _mem_npc_msb_T_2 ? _mem_npc_msb_T_3 : _mem_npc_msb_T_5; // @[RocketCore.scala:1294:{18,29,46,51}] wire [39:0] _mem_npc_T_2 = {mem_npc_msb, _mem_npc_T_1}; // @[RocketCore.scala:1294:18, :1295:{8,16}] wire [39:0] _mem_npc_T_3 = _mem_npc_T_2; // @[RocketCore.scala:619:106, :1295:8] wire [39:0] _mem_npc_T_4 = _mem_npc_T ? _mem_npc_T_3 : mem_br_target; // @[RocketCore.scala:615:41, :619:{21,36,106}] wire [39:0] _mem_npc_T_5 = _mem_npc_T_4 & 40'hFFFFFFFFFE; // @[RocketCore.scala:619:{21,129}] wire [39:0] _mem_npc_T_6 = _mem_npc_T_5; // @[RocketCore.scala:619:129] wire [39:0] mem_npc = _mem_npc_T_6; // @[RocketCore.scala:619:{129,139}] wire _mem_wrong_npc_T = mem_npc != ex_reg_pc; // @[RocketCore.scala:256:22, :619:139, :621:30] wire _mem_wrong_npc_T_1 = _ibuf_io_inst_0_valid \| io_imem_resp_valid_0; // @[RocketCore.scala:153:7, :311:20, :622:31] wire _mem_wrong_npc_T_2 = mem_npc != _ibuf_io_pc; // @[RocketCore.scala:311:20, :619:139, :622:62] wire _mem_wrong_npc_T_3 = ~_mem_wrong_npc_T_1 \| _mem_wrong_npc_T_2; // @[RocketCore.scala:622:{8,31,62}] assign mem_wrong_npc = ex_pc_valid ? _mem_wrong_npc_T : _mem_wrong_npc_T_3; // @[RocketCore.scala:595:51, :621:{8,30}, :622:8] assign io_imem_bht_update_bits_mispredict_0 = mem_wrong_npc; // @[RocketCore.scala:153:7, :621:8] wire _mem_npc_misaligned_T_1 = ~_mem_npc_misaligned_T; // @[RocketCore.scala:623:{28,46}] wire _mem_npc_misaligned_T_2 = mem_npc[1]; // @[RocketCore.scala:619:139, :623:66] wire _mem_npc_misaligned_T_3 = _mem_npc_misaligned_T_1 & _mem_npc_misaligned_T_2; // @[RocketCore.scala:623:{28,56,66}] wire _mem_npc_misaligned_T_4 = ~mem_reg_sfence; // @[RocketCore.scala:276:27, :623:73] wire mem_npc_misaligned = _mem_npc_misaligned_T_3 & _mem_npc_misaligned_T_4; // @[RocketCore.scala:623:{56,70,73}] wire _mem_int_wdata_T = ~mem_reg_xcpt; // @[RocketCore.scala:268:36, :624:27] wire _mem_int_wdata_T_1 = mem_ctrl_jalr ^ mem_npc_misaligned; // @[RocketCore.scala:244:21, :623:70, :624:59] wire _mem_int_wdata_T_2 = _mem_int_wdata_T & _mem_int_wdata_T_1; // @[RocketCore.scala:624:{27,41,59}] wire [63:0] _mem_int_wdata_T_4 = _mem_int_wdata_T_2 ? {{24{mem_br_target[39]}}, mem_br_target} : _mem_int_wdata_T_3; // @[RocketCore.scala:615:41, :624:{26,41,111}] wire [63:0] mem_int_wdata = _mem_int_wdata_T_4; // @[RocketCore.scala:624:{26,119}] wire _mem_cfi_T = mem_ctrl_branch \| mem_ctrl_jalr; // @[RocketCore.scala:244:21, :625:33] assign mem_cfi = _mem_cfi_T \| mem_ctrl_jal; // @[RocketCore.scala:244:21, :625:{33,50}] assign io_imem_btb_update_bits_isValid_0 = mem_cfi; // @[RocketCore.scala:153:7, :625:50] wire _mem_cfi_taken_T_1 = _mem_cfi_taken_T \| mem_ctrl_jalr; // @[RocketCore.scala:244:21, :626:{40,57}] wire mem_cfi_taken = _mem_cfi_taken_T_1 \| mem_ctrl_jal; // @[RocketCore.scala:244:21, :626:{57,74}] wire _mem_direction_misprediction_T_1 = mem_br_taken != _mem_direction_misprediction_T; // @[RocketCore.scala:284:25, :627:{69,85}] wire mem_direction_misprediction = mem_ctrl_branch & _mem_direction_misprediction_T_1; // @[RocketCore.scala:244:21, :627:{53,69}] wire _take_pc_mem_T = ~mem_reg_xcpt; // @[RocketCore.scala:268:36, :624:27, :629:35] wire _take_pc_mem_T_1 = mem_reg_valid & _take_pc_mem_T; // @[RocketCore.scala:265:36, :629:{32,35}] wire _take_pc_mem_T_2 = mem_wrong_npc \| mem_reg_sfence; // @[RocketCore.scala:276:27, :621:8, :629:71] assign _take_pc_mem_T_3 = _take_pc_mem_T_1 & _take_pc_mem_T_2; // @[RocketCore.scala:629:{32,49,71}] assign take_pc_mem = _take_pc_mem_T_3; // @[RocketCore.scala:285:25, :629:49] wire _mem_reg_valid_T = ~ctrl_killx; // @[RocketCore.scala:602:48, :631:20] wire _mem_reg_replay_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20, :632:21] wire _mem_reg_replay_T_1 = _mem_reg_replay_T & replay_ex; // @[RocketCore.scala:601:33, :632:{21,37}] wire _mem_reg_xcpt_T = ~ctrl_killx; // @[RocketCore.scala:602:48, :631:20, :633:19] wire _mem_reg_xcpt_T_1 = _mem_reg_xcpt_T & ex_xcpt; // @[RocketCore.scala:633:{19,31}, :1278:14] wire _mem_reg_xcpt_interrupt_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20, :634:29] wire _mem_reg_xcpt_interrupt_T_1 = _mem_reg_xcpt_interrupt_T & ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35, :634:{29,45}] wire _GEN_49 = ex_ctrl_mem_cmd == 5'h0; // @[package.scala:16:47] wire _mem_reg_load_T; // @[package.scala:16:47] assign _mem_reg_load_T = _GEN_49; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T = _GEN_49; // @[package.scala:16:47] wire _GEN_50 = ex_ctrl_mem_cmd == 5'h10; // @[package.scala:16:47] wire _mem_reg_load_T_1; // @[package.scala:16:47] assign _mem_reg_load_T_1 = _GEN_50; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_1; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_1 = _GEN_50; // @[package.scala:16:47] wire _GEN_51 = ex_ctrl_mem_cmd == 5'h6; // @[package.scala:16:47] wire _mem_reg_load_T_2; // @[package.scala:16:47] assign _mem_reg_load_T_2 = _GEN_51; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_2; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_2 = _GEN_51; // @[package.scala:16:47] wire _mem_reg_load_T_4 = _mem_reg_load_T \| _mem_reg_load_T_1; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_5 = _mem_reg_load_T_4 \| _mem_reg_load_T_2; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_6 = _mem_reg_load_T_5 \| _mem_reg_load_T_3; // @[package.scala:16:47, :81:59] wire _GEN_52 = ex_ctrl_mem_cmd == 5'h4; // @[package.scala:16:47] wire _mem_reg_load_T_7; // @[package.scala:16:47] assign _mem_reg_load_T_7 = _GEN_52; // @[package.scala:16:47] wire _mem_reg_store_T_5; // @[package.scala:16:47] assign _mem_reg_store_T_5 = _GEN_52; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_7; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_7 = _GEN_52; // @[package.scala:16:47] wire _GEN_53 = ex_ctrl_mem_cmd == 5'h9; // @[package.scala:16:47] wire _mem_reg_load_T_8; // @[package.scala:16:47] assign _mem_reg_load_T_8 = _GEN_53; // @[package.scala:16:47] wire _mem_reg_store_T_6; // @[package.scala:16:47] assign _mem_reg_store_T_6 = _GEN_53; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_8; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_8 = _GEN_53; // @[package.scala:16:47] wire _GEN_54 = ex_ctrl_mem_cmd == 5'hA; // @[package.scala:16:47] wire _mem_reg_load_T_9; // @[package.scala:16:47] assign _mem_reg_load_T_9 = _GEN_54; // @[package.scala:16:47] wire _mem_reg_store_T_7; // @[package.scala:16:47] assign _mem_reg_store_T_7 = _GEN_54; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_9; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_9 = _GEN_54; // @[package.scala:16:47] wire _GEN_55 = ex_ctrl_mem_cmd == 5'hB; // @[package.scala:16:47] wire _mem_reg_load_T_10; // @[package.scala:16:47] assign _mem_reg_load_T_10 = _GEN_55; // @[package.scala:16:47] wire _mem_reg_store_T_8; // @[package.scala:16:47] assign _mem_reg_store_T_8 = _GEN_55; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_10; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_10 = _GEN_55; // @[package.scala:16:47] wire _mem_reg_load_T_11 = _mem_reg_load_T_7 \| _mem_reg_load_T_8; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_12 = _mem_reg_load_T_11 \| _mem_reg_load_T_9; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_13 = _mem_reg_load_T_12 \| _mem_reg_load_T_10; // @[package.scala:16:47, :81:59] wire _GEN_56 = ex_ctrl_mem_cmd == 5'h8; // @[package.scala:16:47] wire _mem_reg_load_T_14; // @[package.scala:16:47] assign _mem_reg_load_T_14 = _GEN_56; // @[package.scala:16:47] wire _mem_reg_store_T_12; // @[package.scala:16:47] assign _mem_reg_store_T_12 = _GEN_56; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_14; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_14 = _GEN_56; // @[package.scala:16:47] wire _GEN_57 = ex_ctrl_mem_cmd == 5'hC; // @[package.scala:16:47] wire _mem_reg_load_T_15; // @[package.scala:16:47] assign _mem_reg_load_T_15 = _GEN_57; // @[package.scala:16:47] wire _mem_reg_store_T_13; // @[package.scala:16:47] assign _mem_reg_store_T_13 = _GEN_57; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_15; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_15 = _GEN_57; // @[package.scala:16:47] wire _GEN_58 = ex_ctrl_mem_cmd == 5'hD; // @[package.scala:16:47] wire _mem_reg_load_T_16; // @[package.scala:16:47] assign _mem_reg_load_T_16 = _GEN_58; // @[package.scala:16:47] wire _mem_reg_store_T_14; // @[package.scala:16:47] assign _mem_reg_store_T_14 = _GEN_58; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_16; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_16 = _GEN_58; // @[package.scala:16:47] wire _GEN_59 = ex_ctrl_mem_cmd == 5'hE; // @[package.scala:16:47] wire _mem_reg_load_T_17; // @[package.scala:16:47] assign _mem_reg_load_T_17 = _GEN_59; // @[package.scala:16:47] wire _mem_reg_store_T_15; // @[package.scala:16:47] assign _mem_reg_store_T_15 = _GEN_59; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_17; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_17 = _GEN_59; // @[package.scala:16:47] wire _GEN_60 = ex_ctrl_mem_cmd == 5'hF; // @[package.scala:16:47] wire _mem_reg_load_T_18; // @[package.scala:16:47] assign _mem_reg_load_T_18 = _GEN_60; // @[package.scala:16:47] wire _mem_reg_store_T_16; // @[package.scala:16:47] assign _mem_reg_store_T_16 = _GEN_60; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_18; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_18 = _GEN_60; // @[package.scala:16:47] wire _mem_reg_load_T_19 = _mem_reg_load_T_14 \| _mem_reg_load_T_15; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_20 = _mem_reg_load_T_19 \| _mem_reg_load_T_16; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_21 = _mem_reg_load_T_20 \| _mem_reg_load_T_17; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_22 = _mem_reg_load_T_21 \| _mem_reg_load_T_18; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_23 = _mem_reg_load_T_13 \| _mem_reg_load_T_22; // @[package.scala:81:59] wire _mem_reg_load_T_24 = _mem_reg_load_T_6 \| _mem_reg_load_T_23; // @[package.scala:81:59] wire _mem_reg_load_T_25 = ex_ctrl_mem & _mem_reg_load_T_24; // @[RocketCore.scala:243:20, :643:33] wire _mem_reg_store_T = ex_ctrl_mem_cmd == 5'h1; // @[RocketCore.scala:243:20] wire _mem_reg_store_T_1 = ex_ctrl_mem_cmd == 5'h11; // @[RocketCore.scala:243:20] wire _mem_reg_store_T_2 = _mem_reg_store_T \| _mem_reg_store_T_1; // @[Consts.scala:90:{32,42,49}] wire _mem_reg_store_T_4 = _mem_reg_store_T_2 \| _mem_reg_store_T_3; // @[Consts.scala:90:{42,59,66}] wire _mem_reg_store_T_9 = _mem_reg_store_T_5 \| _mem_reg_store_T_6; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_10 = _mem_reg_store_T_9 \| _mem_reg_store_T_7; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_11 = _mem_reg_store_T_10 \| _mem_reg_store_T_8; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_17 = _mem_reg_store_T_12 \| _mem_reg_store_T_13; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_18 = _mem_reg_store_T_17 \| _mem_reg_store_T_14; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_19 = _mem_reg_store_T_18 \| _mem_reg_store_T_15; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_20 = _mem_reg_store_T_19 \| _mem_reg_store_T_16; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_21 = _mem_reg_store_T_11 \| _mem_reg_store_T_20; // @[package.scala:81:59] wire _mem_reg_store_T_22 = _mem_reg_store_T_4 \| _mem_reg_store_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _mem_reg_store_T_23 = ex_ctrl_mem & _mem_reg_store_T_22; // @[RocketCore.scala:243:20, :644:34] wire [1:0] size = ex_ctrl_rocc ? 2'h3 : ex_reg_mem_size; // @[RocketCore.scala:243:20, :257:28, :664:21] wire [1:0] mem_reg_rs2_size = size; // @[RocketCore.scala:664:21] wire _mem_reg_rs2_T = mem_reg_rs2_size == 2'h0; // @[AMOALU.scala:11:18, :29:19] wire [7:0] _mem_reg_rs2_T_1 = mem_reg_rs2_dat_padded[7:0]; // @[AMOALU.scala:13:27, :29:69] wire [15:0] _mem_reg_rs2_T_2 = {2{_mem_reg_rs2_T_1}}; // @[AMOALU.scala:29:{32,69}] wire [31:0] _mem_reg_rs2_T_3 = {2{_mem_reg_rs2_T_2}}; // @[AMOALU.scala:29:32] wire [63:0] _mem_reg_rs2_T_4 = {2{_mem_reg_rs2_T_3}}; // @[AMOALU.scala:29:32] wire _mem_reg_rs2_T_5 = mem_reg_rs2_size == 2'h1; // @[AMOALU.scala:11:18, :29:19] wire [15:0] _mem_reg_rs2_T_6 = mem_reg_rs2_dat_padded[15:0]; // @[AMOALU.scala:13:27, :29:69] wire [31:0] _mem_reg_rs2_T_7 = {2{_mem_reg_rs2_T_6}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _mem_reg_rs2_T_8 = {2{_mem_reg_rs2_T_7}}; // @[AMOALU.scala:29:32] wire _mem_reg_rs2_T_9 = mem_reg_rs2_size == 2'h2; // @[AMOALU.scala:11:18, :29:19] wire [31:0] _mem_reg_rs2_T_10 = mem_reg_rs2_dat_padded[31:0]; // @[AMOALU.scala:13:27, :29:69] wire [63:0] _mem_reg_rs2_T_11 = {2{_mem_reg_rs2_T_10}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _mem_reg_rs2_T_12 = _mem_reg_rs2_T_9 ? _mem_reg_rs2_T_11 : mem_reg_rs2_dat_padded; // @[AMOALU.scala:13:27, :29:{13,19,32}] wire [63:0] _mem_reg_rs2_T_13 = _mem_reg_rs2_T_5 ? _mem_reg_rs2_T_8 : _mem_reg_rs2_T_12; // @[AMOALU.scala:29:{13,19,32}] wire [63:0] _mem_reg_rs2_T_14 = _mem_reg_rs2_T ? _mem_reg_rs2_T_4 : _mem_reg_rs2_T_13; // @[AMOALU.scala:29:{13,19,32}] wire _mem_breakpoint_T = mem_reg_load & _bpu_io_xcpt_ld; // @[RocketCore.scala:273:36, :414:19, :677:38] wire _mem_breakpoint_T_1 = mem_reg_store & _bpu_io_xcpt_st; // @[RocketCore.scala:274:36, :414:19, :677:75] wire mem_breakpoint = _mem_breakpoint_T \| _mem_breakpoint_T_1; // @[RocketCore.scala:677:{38,57,75}] wire _mem_debug_breakpoint_T = mem_reg_load & _bpu_io_debug_ld; // @[RocketCore.scala:273:36, :414:19, :678:44] wire _mem_debug_breakpoint_T_1 = mem_reg_store & _bpu_io_debug_st; // @[RocketCore.scala:274:36, :414:19, :678:82] wire mem_debug_breakpoint = _mem_debug_breakpoint_T \| _mem_debug_breakpoint_T_1; // @[RocketCore.scala:678:{44,64,82}] wire mem_ldst_xcpt = mem_debug_breakpoint \| mem_breakpoint; // @[RocketCore.scala:677:57, :678:64, :1278:{14,35}] wire [3:0] mem_ldst_cause = mem_debug_breakpoint ? 4'hE : 4'h3; // @[Mux.scala:50:70] wire _T_74 = mem_reg_xcpt_interrupt \| mem_reg_xcpt; // @[RocketCore.scala:264:36, :268:36, :684:29] wire _T_75 = mem_reg_valid & mem_npc_misaligned; // @[RocketCore.scala:265:36, :623:70, :685:20] wire mem_xcpt = _T_74 \| _T_75 \| mem_reg_valid & mem_ldst_xcpt; // @[RocketCore.scala:265:36, :684:29, :685:20, :686:20, :1278:{14,35}] wire [63:0] mem_cause = _T_74 ? mem_reg_cause : {60'h0, _T_75 ? 4'h0 : mem_ldst_cause}; // @[Mux.scala:50:70] wire dcache_kill_mem = _dcache_kill_mem_T & io_dmem_replay_next_0; // @[RocketCore.scala:153:7, :695:{39,55}] wire _fpu_kill_mem_T = mem_reg_valid & mem_ctrl_fp; // @[RocketCore.scala:244:21, :265:36, :696:36] wire fpu_kill_mem = _fpu_kill_mem_T & io_fpu_nack_mem_0; // @[RocketCore.scala:153:7, :696:{36,51}] wire _vec_kill_mem_T = mem_reg_valid & mem_ctrl_mem; // @[RocketCore.scala:244:21, :265:36, :697:36] wire _replay_mem_T = dcache_kill_mem \| mem_reg_replay; // @[RocketCore.scala:269:36, :695:55, :699:37] wire _replay_mem_T_1 = _replay_mem_T \| fpu_kill_mem; // @[RocketCore.scala:696:51, :699:{37,55}] wire _replay_mem_T_2 = _replay_mem_T_1; // @[RocketCore.scala:699:{55,71}] wire replay_mem = _replay_mem_T_2; // @[RocketCore.scala:699:{71,87}] wire _killm_common_T = dcache_kill_mem \| take_pc_wb; // @[RocketCore.scala:304:24, :695:55, :700:38] wire _killm_common_T_1 = _killm_common_T \| mem_reg_xcpt; // @[RocketCore.scala:268:36, :700:{38,52}] wire _killm_common_T_2 = ~mem_reg_valid; // @[RocketCore.scala:265:36, :700:71] assign killm_common = _killm_common_T_1 \| _killm_common_T_2; // @[RocketCore.scala:700:{52,68,71}] assign io_fpu_killm_0 = killm_common; // @[RocketCore.scala:153:7, :700:68] wire _div_io_kill_T = _div_io_req_ready & _div_io_req_valid_T; // @[Decoupled.scala:51:35] reg div_io_kill_REG; // @[RocketCore.scala:701:41] wire _div_io_kill_T_1 = killm_common & div_io_kill_REG; // @[RocketCore.scala:700:68, :701:{31,41}] wire _ctrl_killm_T = killm_common \| mem_xcpt; // @[RocketCore.scala:700:68, :702:33, :1278:14] wire _ctrl_killm_T_1 = _ctrl_killm_T \| fpu_kill_mem; // @[RocketCore.scala:696:51, :702:{33,45}] wire ctrl_killm = _ctrl_killm_T_1; // @[RocketCore.scala:702:{45,61}] wire _wb_reg_valid_T = ~ctrl_killm; // @[RocketCore.scala:702:61, :705:19] wire _wb_reg_replay_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34] wire _wb_reg_replay_T_1 = replay_mem & _wb_reg_replay_T; // @[RocketCore.scala:699:87, :706:{31,34}] wire _wb_reg_xcpt_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :707:30] wire _wb_reg_xcpt_T_1 = mem_xcpt & _wb_reg_xcpt_T; // @[RocketCore.scala:707:{27,30}, :1278:14] wire _wb_reg_xcpt_T_3 = _wb_reg_xcpt_T_1; // @[RocketCore.scala:707:{27,42}] wire _wb_reg_flush_pipe_T = ~ctrl_killm; // @[RocketCore.scala:702:61, :705:19, :708:24] wire _wb_reg_flush_pipe_T_1 = _wb_reg_flush_pipe_T & mem_reg_flush_pipe; // @[RocketCore.scala:270:36, :708:{24,36}] wire _wb_reg_wdata_T = ~mem_reg_xcpt; // @[RocketCore.scala:268:36, :624:27, :712:25] wire _wb_reg_wdata_T_1 = _wb_reg_wdata_T & mem_ctrl_fp; // @[RocketCore.scala:244:21, :712:{25,39}] wire _wb_reg_wdata_T_2 = _wb_reg_wdata_T_1 & mem_ctrl_wxd; // @[RocketCore.scala:244:21, :712:{39,54}] wire [63:0] _wb_reg_wdata_T_3 = _wb_reg_wdata_T_2 ? io_fpu_toint_data_0 : mem_int_wdata; // @[RocketCore.scala:153:7, :624:119, :712:{24,54}] wire _wb_reg_hfence_v_T = mem_ctrl_mem_cmd == 5'h15; // @[RocketCore.scala:244:21, :721:41] wire _wb_reg_hfence_g_T = mem_ctrl_mem_cmd == 5'h16; // @[RocketCore.scala:244:21, :722:41] wire _T_113 = wb_reg_valid & wb_ctrl_mem; // @[RocketCore.scala:245:20, :288:35, :730:19] wire _T_100 = _T_113 & io_dmem_s2_xcpt_pf_st_0; // @[RocketCore.scala:153:7, :730:{19,34}] wire _T_102 = _T_113 & io_dmem_s2_xcpt_pf_ld_0; // @[RocketCore.scala:153:7, :730:19, :731:34] wire _T_108 = _T_113 & io_dmem_s2_xcpt_ae_st_0; // @[RocketCore.scala:153:7, :730:19, :734:34] wire _T_110 = _T_113 & io_dmem_s2_xcpt_ae_ld_0; // @[RocketCore.scala:153:7, :730:19, :735:34] wire _T_112 = _T_113 & io_dmem_s2_xcpt_ma_st_0; // @[RocketCore.scala:153:7, :730:19, :736:34] wire wb_xcpt = wb_reg_xcpt \| _T_100 \| _T_102 \| _T_108 \| _T_110 \| _T_112 \| _T_113 & io_dmem_s2_xcpt_ma_ld_0; // @[RocketCore.scala:153:7, :289:35, :730:{19,34}, :731:34, :734:34, :735:34, :736:34, :737:34, :1278:{14,35}] wire [63:0] wb_cause = wb_reg_xcpt ? wb_reg_cause : {59'h0, _T_100 ? 5'hF : _T_102 ? 5'hD : {2'h0, _T_108 ? 3'h7 : _T_110 ? 3'h5 : {1'h1, _T_112, 1'h0}}}; // @[Mux.scala:50:70] wire _wb_pc_valid_T = wb_reg_valid \| wb_reg_replay; // @[RocketCore.scala:288:35, :290:35, :754:34] wire wb_pc_valid = _wb_pc_valid_T \| wb_reg_xcpt; // @[RocketCore.scala:289:35, :754:{34,51}] wire wb_wxd = wb_reg_valid & wb_ctrl_wxd; // @[RocketCore.scala:245:20, :288:35, :755:29] wire _wb_set_sboard_T = wb_ctrl_div \| wb_dcache_miss; // @[RocketCore.scala:245:20, :596:36, :756:35] wire _wb_set_sboard_T_1 = _wb_set_sboard_T \| wb_ctrl_rocc; // @[RocketCore.scala:245:20, :756:{35,53}] wire wb_set_sboard = _wb_set_sboard_T_1 \| wb_ctrl_vec; // @[RocketCore.scala:245:20, :756:{53,69}] wire replay_wb_common = io_dmem_s2_nack_0 \| wb_reg_replay; // @[RocketCore.scala:153:7, :290:35, :757:42] wire replay_wb_rocc = _replay_wb_rocc_T; // @[RocketCore.scala:758:{37,53}] wire _replay_wb_T = replay_wb_common \| replay_wb_rocc; // @[RocketCore.scala:757:42, :758:53, :761:36] wire _replay_wb_T_1 = _replay_wb_T; // @[RocketCore.scala:761:{36,54}] wire replay_wb = _replay_wb_T_1; // @[RocketCore.scala:761:{54,71}] wire _take_pc_wb_T = replay_wb \| wb_xcpt; // @[RocketCore.scala:761:71, :762:27, :1278:14] wire _take_pc_wb_T_1 = _take_pc_wb_T \| _csr_io_eret; // @[RocketCore.scala:341:19, :762:{27,38}] assign _take_pc_wb_T_2 = _take_pc_wb_T_1 \| wb_reg_flush_pipe; // @[RocketCore.scala:291:35, :762:{38,53}] assign take_pc_wb = _take_pc_wb_T_2; // @[RocketCore.scala:304:24, :762:53] wire _dmem_resp_xpu_T = io_dmem_resp_bits_tag_0[0]; // @[RocketCore.scala:153:7, :765:45] wire dmem_resp_fpu = io_dmem_resp_bits_tag_0[0]; // @[RocketCore.scala:153:7, :765:45, :766:45] wire dmem_resp_xpu = ~_dmem_resp_xpu_T; // @[RocketCore.scala:765:{23,45}] assign dmem_resp_waddr = io_dmem_resp_bits_tag_0[5:1]; // @[RocketCore.scala:153:7, :767:46] assign io_fpu_ll_resp_tag_0 = dmem_resp_waddr; // @[RocketCore.scala:153:7, :767:46] wire dmem_resp_valid = io_dmem_resp_valid_0 & io_dmem_resp_bits_has_data_0; // @[RocketCore.scala:153:7, :768:44] wire dmem_resp_replay = dmem_resp_valid & io_dmem_resp_bits_replay_0; // @[RocketCore.scala:153:7, :768:44, :769:42] wire [63:0] ll_wdata; // @[RocketCore.scala:779:26] wire [4:0] ll_waddr; // @[RocketCore.scala:780:26] wire _ll_wen_T = ll_arb_io_out_ready & _ll_arb_io_out_valid; // @[Decoupled.scala:51:35] wire ll_wen; // @[RocketCore.scala:781:24] wire _ll_arb_io_out_ready_T = ~wb_wxd; // @[RocketCore.scala:755:29, :782:26] wire _T_143 = dmem_resp_replay & dmem_resp_xpu; // @[RocketCore.scala:765:23, :769:42, :809:26] assign ll_arb_io_out_ready = ~_T_143 & _ll_arb_io_out_ready_T; // @[RocketCore.scala:782:{23,26}, :809:{26,44}, :810:25] assign ll_waddr = _T_143 ? dmem_resp_waddr : _ll_arb_io_out_bits_tag; // @[RocketCore.scala:767:46, :776:22, :780:26, :809:{26,44}, :811:14] assign ll_wen = _T_143 \| _ll_wen_T; // @[Decoupled.scala:51:35] wire _wb_valid_T = ~replay_wb; // @[RocketCore.scala:761:71, :815:34] wire _wb_valid_T_1 = wb_reg_valid & _wb_valid_T; // @[RocketCore.scala:288:35, :815:{31,34}] wire _wb_valid_T_2 = ~wb_xcpt; // @[RocketCore.scala:815:48, :1278:14] wire wb_valid = _wb_valid_T_1 & _wb_valid_T_2; // @[RocketCore.scala:815:{31,45,48}] wire wb_wen = wb_valid & wb_ctrl_wxd; // @[RocketCore.scala:245:20, :815:45, :816:25] wire rf_wen = wb_wen \| ll_wen; // @[RocketCore.scala:781:24, :816:25, :817:23] wire [4:0] rf_waddr = ll_wen ? ll_waddr : wb_waddr; // @[RocketCore.scala:455:36, :780:26, :781:24, :818:21] wire [4:0] xrfWriteBundle_wrdst = rf_waddr; // @[RocketCore.scala:818:21, :1249:28] wire _rf_wdata_T = dmem_resp_valid & dmem_resp_xpu; // @[RocketCore.scala:765:23, :768:44, :819:38] wire _rf_wdata_T_2 = \|wb_ctrl_csr; // @[RocketCore.scala:245:20, :821:34] wire [63:0] _rf_wdata_T_4 = _rf_wdata_T_2 ? _csr_io_rw_rdata : _rf_wdata_T_3; // @[RocketCore.scala:341:19, :821:{21,34}, :822:21] wire [63:0] _rf_wdata_T_5 = ll_wen ? ll_wdata : _rf_wdata_T_4; // @[RocketCore.scala:779:26, :781:24, :820:21, :821:21] wire [63:0] rf_wdata = _rf_wdata_T ? _rf_wdata_T_1 : _rf_wdata_T_5; // @[RocketCore.scala:819:{21,38,78}, :820:21] wire [63:0] coreMonitorBundle_wrdata = rf_wdata; // @[RocketCore.scala:819:21, :1186:31] wire [63:0] xrfWriteBundle_wrdata = rf_wdata; // @[RocketCore.scala:819:21, :1249:28] wire [63:0] _id_rs_T_4; // @[RocketCore.scala:1326:25] assign id_rs_0 = rf_wen & (\|rf_waddr) & rf_waddr == id_raddr1 ? rf_wdata : _id_rs_T_4; // @[RocketCore.scala:326:72, :817:23, :818:21, :819:21, :824:17, :1325:26, :1326:{19,25}, :1331:{16,25}, :1334:{20,31,39}] wire [63:0] _id_rs_T_9; // @[RocketCore.scala:1326:25] assign id_rs_1 = rf_wen & (\|rf_waddr) & rf_waddr == id_raddr2 ? rf_wdata : _id_rs_T_9; // @[RocketCore.scala:326:72, :817:23, :818:21, :819:21, :824:17, :1325:26, :1326:{19,25}, :1331:{16,25}, :1334:{20,31,39}] wire [1:0] _csr_io_inst_0_T = wb_reg_raw_inst[1:0]; // @[RocketCore.scala:301:28, :832:66] wire _csr_io_inst_0_T_1 = &_csr_io_inst_0_T; // @[RocketCore.scala:832:{66,73}] wire [15:0] _csr_io_inst_0_T_2 = wb_reg_inst[31:16]; // @[RocketCore.scala:300:24, :832:91] wire [15:0] _csr_io_inst_0_T_3 = _csr_io_inst_0_T_1 ? _csr_io_inst_0_T_2 : 16'h0; // @[RocketCore.scala:832:{50,73,91}] wire [15:0] _csr_io_inst_0_T_4 = wb_reg_raw_inst[15:0]; // @[RocketCore.scala:301:28, :832:119] wire [31:0] _csr_io_inst_0_T_5 = {_csr_io_inst_0_T_3, _csr_io_inst_0_T_4}; // @[RocketCore.scala:832:{46,50,119}] wire [4:0] _csr_io_fcsr_flags_bits_T = {5{io_fpu_fcsr_flags_valid_0}}; // @[RocketCore.scala:153:7, :839:59] wire [4:0] _csr_io_fcsr_flags_bits_T_1 = io_fpu_fcsr_flags_bits_0 & _csr_io_fcsr_flags_bits_T; // @[RocketCore.scala:153:7, :839:{53,59}] wire [4:0] _csr_io_fcsr_flags_bits_T_4 = _csr_io_fcsr_flags_bits_T_1; // @[RocketCore.scala:839:{53,89}] wire [31:0] _io_fpu_time_T = _csr_io_time[31:0]; // @[RocketCore.scala:341:19, :840:29] wire [31:0] _coreMonitorBundle_timer_T = _csr_io_time[31:0]; // @[RocketCore.scala:341:19, :840:29, :1191:41] wire [31:0] _xrfWriteBundle_timer_T = _csr_io_time[31:0]; // @[RocketCore.scala:341:19, :840:29, :1254:38] assign io_fpu_time_0 = {32'h0, _io_fpu_time_T}; // @[RocketCore.scala:153:7, :840:{15,29}] wire tval_dmem_addr = ~wb_reg_xcpt; // @[RocketCore.scala:289:35, :845:24] wire _tval_any_addr_T = wb_reg_cause == 64'h3; // @[package.scala:16:47] wire _tval_any_addr_T_1 = wb_reg_cause == 64'h1; // @[package.scala:16:47] wire _tval_any_addr_T_2 = wb_reg_cause == 64'hC; // @[package.scala:16:47] wire _GEN_61 = wb_reg_cause == 64'h14; // @[package.scala:16:47] wire _tval_any_addr_T_3; // @[package.scala:16:47] assign _tval_any_addr_T_3 = _GEN_61; // @[package.scala:16:47] wire _htval_valid_imem_T; // @[RocketCore.scala:853:56] assign _htval_valid_imem_T = _GEN_61; // @[package.scala:16:47] wire _tval_any_addr_T_4 = _tval_any_addr_T \| _tval_any_addr_T_1; // @[package.scala:16:47, :81:59] wire _tval_any_addr_T_5 = _tval_any_addr_T_4 \| _tval_any_addr_T_2; // @[package.scala:16:47, :81:59] wire _tval_any_addr_T_6 = _tval_any_addr_T_5 \| _tval_any_addr_T_3; // @[package.scala:16:47, :81:59] wire tval_any_addr = tval_dmem_addr \| _tval_any_addr_T_6; // @[package.scala:81:59] wire tval_inst = wb_reg_cause == 64'h2; // @[RocketCore.scala:292:35, :848:32] wire _tval_valid_T = tval_any_addr \| tval_inst; // @[RocketCore.scala:846:38, :848:32, :849:46] wire tval_valid = wb_xcpt & _tval_valid_T; // @[RocketCore.scala:849:{28,46}, :1278:14] wire _csr_io_gva_T = tval_any_addr & _csr_io_status_v; // @[RocketCore.scala:341:19, :846:38, :850:43] wire _csr_io_gva_T_1 = tval_dmem_addr & wb_reg_hls_or_dv; // @[RocketCore.scala:297:29, :845:24, :850:80] wire _csr_io_gva_T_2 = _csr_io_gva_T \| _csr_io_gva_T_1; // @[RocketCore.scala:850:{43,62,80}] wire _csr_io_gva_T_3 = wb_xcpt & _csr_io_gva_T_2; // @[RocketCore.scala:850:{25,62}, :1278:14] wire [24:0] _csr_io_tval_a_T = wb_reg_wdata[63:39]; // @[RocketCore.scala:302:25, :1293:17] wire [24:0] csr_io_tval_a = _csr_io_tval_a_T; // @[RocketCore.scala:1293:{17,23}] wire _csr_io_tval_msb_T = csr_io_tval_a == 25'h0; // @[RocketCore.scala:1293:23, :1294:21] wire _csr_io_tval_msb_T_1 = &csr_io_tval_a; // @[RocketCore.scala:1293:23, :1294:34] wire _csr_io_tval_msb_T_2 = _csr_io_tval_msb_T \| _csr_io_tval_msb_T_1; // @[RocketCore.scala:1294:{21,29,34}] wire _csr_io_tval_msb_T_3 = wb_reg_wdata[39]; // @[RocketCore.scala:302:25, :1294:46] wire _csr_io_tval_msb_T_4 = wb_reg_wdata[38]; // @[RocketCore.scala:302:25, :1294:54] wire _csr_io_tval_msb_T_5 = ~_csr_io_tval_msb_T_4; // @[RocketCore.scala:1294:{51,54}] wire csr_io_tval_msb = _csr_io_tval_msb_T_2 ? _csr_io_tval_msb_T_3 : _csr_io_tval_msb_T_5; // @[RocketCore.scala:1294:{18,29,46,51}] assign io_imem_sfence_bits_addr_0 = wb_reg_wdata[38:0]; // @[RocketCore.scala:153:7, :302:25, :1295:16] wire [38:0] _csr_io_tval_T = wb_reg_wdata[38:0]; // @[RocketCore.scala:302:25, :1295:16] wire [39:0] _csr_io_tval_T_1 = {csr_io_tval_msb, _csr_io_tval_T}; // @[RocketCore.scala:1294:18, :1295:{8,16}] wire [39:0] _csr_io_tval_T_2 = tval_valid ? _csr_io_tval_T_1 : 40'h0; // @[RocketCore.scala:849:28, :851:21, :1295:8] wire htval_valid_imem = wb_reg_xcpt & _htval_valid_imem_T; // @[RocketCore.scala:289:35, :853:{40,56}] wire [39:0] htval_imem = htval_valid_imem ? io_imem_gpa_bits_0 : 40'h0; // @[RocketCore.scala:153:7, :853:40, :854:25] wire [39:0] _htval_T = htval_imem; // @[RocketCore.scala:854:25, :860:29] wire _htval_valid_dmem_T = wb_xcpt & tval_dmem_addr; // @[RocketCore.scala:845:24, :857:36, :1278:14] wire [1:0] _htval_valid_dmem_T_4 = {io_dmem_s2_xcpt_pf_ld_0, io_dmem_s2_xcpt_pf_st_0}; // @[RocketCore.scala:153:7, :857:110] wire _htval_valid_dmem_T_5 = \|_htval_valid_dmem_T_4; // @[RocketCore.scala:857:{110,117}] wire _htval_valid_dmem_T_6 = ~_htval_valid_dmem_T_5; // @[RocketCore.scala:857:{90,117}] wire [39:0] htval = _htval_T; // @[RocketCore.scala:860:{29,43}] wire _mhtinst_read_pseudo_T = io_imem_gpa_is_pte_0 & htval_valid_imem; // @[RocketCore.scala:153:7, :853:40, :862:51] wire mhtinst_read_pseudo = _mhtinst_read_pseudo_T; // @[RocketCore.scala:862:{51,72}] wire [11:0] _csr_io_rw_addr_T = wb_reg_inst[31:20]; // @[RocketCore.scala:300:24, :909:32] wire [2:0] _csr_io_rw_cmd_T = {~wb_reg_valid, 2'h0}; // @[RocketCore.scala:288:35] wire [2:0] _csr_io_rw_cmd_T_1 = ~_csr_io_rw_cmd_T; // @[CSR.scala:183:{11,15}] wire [2:0] _csr_io_rw_cmd_T_2 = wb_ctrl_csr & _csr_io_rw_cmd_T_1; // @[RocketCore.scala:245:20] assign io_bpwatch_0_action_0 = {2'h0, _csr_io_bp_0_control_action}; // @[RocketCore.scala:153:7, :341:19, :962:18] wire _hazard_targets_T = \|id_raddr1; // @[RocketCore.scala:326:72, :969:55, :1326:41] wire hazard_targets_0_1 = id_ctrl_rxs1 & _hazard_targets_T; // @[RocketCore.scala:321:21, :969:{42,55}] wire _hazard_targets_T_1 = \|id_raddr2; // @[RocketCore.scala:326:72, :970:55, :1326:41] wire hazard_targets_1_1 = id_ctrl_rxs2 & _hazard_targets_T_1; // @[RocketCore.scala:321:21, :970:{42,55}] wire _hazard_targets_T_2 = \|id_waddr; // @[RocketCore.scala:326:72, :971:55] wire hazard_targets_2_1 = id_ctrl_wxd & _hazard_targets_T_2; // @[RocketCore.scala:321:21, :971:{42,55}] reg [31:0] _r; // @[RocketCore.scala:1305:29] wire [30:0] _r_T = _r[31:1]; // @[RocketCore.scala:1305:29, :1306:35] wire [31:0] r = {_r_T, 1'h0}; // @[RocketCore.scala:1306:{35,40}] wire [31:0] _GEN_62 = {27'h0, id_raddr1}; // @[RocketCore.scala:326:72, :1302:35, :1309:58] wire [31:0] _id_sboard_hazard_T = r >> _GEN_62; // @[RocketCore.scala:1302:35, :1306:40] wire _id_sboard_hazard_T_1 = _id_sboard_hazard_T[0]; // @[RocketCore.scala:1302:35] wire _id_sboard_hazard_T_2 = ll_waddr == id_raddr1; // @[RocketCore.scala:326:72, :780:26, :981:70] wire _id_sboard_hazard_T_3 = ll_wen & _id_sboard_hazard_T_2; // @[RocketCore.scala:781:24, :981:{58,70}] wire _id_sboard_hazard_T_4 = ~_id_sboard_hazard_T_3; // @[RocketCore.scala:981:58, :984:80] wire _id_sboard_hazard_T_5 = _id_sboard_hazard_T_1 & _id_sboard_hazard_T_4; // @[RocketCore.scala:984:{77,80}, :1302:35] wire _id_sboard_hazard_T_6 = hazard_targets_0_1 & _id_sboard_hazard_T_5; // @[RocketCore.scala:969:42, :984:77, :1287:27] wire [31:0] _GEN_63 = {27'h0, id_raddr2}; // @[RocketCore.scala:326:72, :1302:35, :1309:58] wire [31:0] _id_sboard_hazard_T_7 = r >> _GEN_63; // @[RocketCore.scala:1302:35, :1306:40] wire _id_sboard_hazard_T_8 = _id_sboard_hazard_T_7[0]; // @[RocketCore.scala:1302:35] wire _id_sboard_hazard_T_9 = ll_waddr == id_raddr2; // @[RocketCore.scala:326:72, :780:26, :981:70] wire _id_sboard_hazard_T_10 = ll_wen & _id_sboard_hazard_T_9; // @[RocketCore.scala:781:24, :981:{58,70}] wire _id_sboard_hazard_T_11 = ~_id_sboard_hazard_T_10; // @[RocketCore.scala:981:58, :984:80] wire _id_sboard_hazard_T_12 = _id_sboard_hazard_T_8 & _id_sboard_hazard_T_11; // @[RocketCore.scala:984:{77,80}, :1302:35] wire _id_sboard_hazard_T_13 = hazard_targets_1_1 & _id_sboard_hazard_T_12; // @[RocketCore.scala:970:42, :984:77, :1287:27] wire [31:0] _GEN_64 = {27'h0, id_waddr}; // @[RocketCore.scala:326:72, :1302:35, :1309:58] wire [31:0] _id_sboard_hazard_T_14 = r >> _GEN_64; // @[RocketCore.scala:1302:35, :1306:40] wire _id_sboard_hazard_T_15 = _id_sboard_hazard_T_14[0]; // @[RocketCore.scala:1302:35] wire _id_sboard_hazard_T_16 = ll_waddr == id_waddr; // @[RocketCore.scala:326:72, :780:26, :981:70] wire _id_sboard_hazard_T_17 = ll_wen & _id_sboard_hazard_T_16; // @[RocketCore.scala:781:24, :981:{58,70}] wire _id_sboard_hazard_T_18 = ~_id_sboard_hazard_T_17; // @[RocketCore.scala:981:58, :984:80] wire _id_sboard_hazard_T_19 = _id_sboard_hazard_T_15 & _id_sboard_hazard_T_18; // @[RocketCore.scala:984:{77,80}, :1302:35] wire _id_sboard_hazard_T_20 = hazard_targets_2_1 & _id_sboard_hazard_T_19; // @[RocketCore.scala:971:42, :984:77, :1287:27] wire _id_sboard_hazard_T_21 = _id_sboard_hazard_T_6 \| _id_sboard_hazard_T_13; // @[RocketCore.scala:1287:{27,50}] wire id_sboard_hazard = _id_sboard_hazard_T_21 \| _id_sboard_hazard_T_20; // @[RocketCore.scala:1287:{27,50}] wire [31:0] _id_stall_fpu_T_4 = 32'h1 << wb_waddr; // @[RocketCore.scala:455:36, :1309:58] wire _ex_cannot_bypass_T = \|ex_ctrl_csr; // @[RocketCore.scala:243:20, :988:38] wire _ex_cannot_bypass_T_1 = _ex_cannot_bypass_T \| ex_ctrl_jalr; // @[RocketCore.scala:243:20, :988:{38,48}] wire _ex_cannot_bypass_T_2 = _ex_cannot_bypass_T_1 \| ex_ctrl_mem; // @[RocketCore.scala:243:20, :988:{48,64}] wire _ex_cannot_bypass_T_3 = _ex_cannot_bypass_T_2 \| ex_ctrl_mul; // @[RocketCore.scala:243:20, :988:{64,79}] wire _ex_cannot_bypass_T_4 = _ex_cannot_bypass_T_3 \| ex_ctrl_div; // @[RocketCore.scala:243:20, :988:{79,94}] wire _ex_cannot_bypass_T_5 = _ex_cannot_bypass_T_4 \| ex_ctrl_fp; // @[RocketCore.scala:243:20, :988:{94,109}] wire _ex_cannot_bypass_T_6 = _ex_cannot_bypass_T_5 \| ex_ctrl_rocc; // @[RocketCore.scala:243:20, :988:{109,123}] wire ex_cannot_bypass = _ex_cannot_bypass_T_6; // @[RocketCore.scala:988:{123,139}] wire _data_hazard_ex_T_1 = hazard_targets_0_1 & _data_hazard_ex_T; // @[RocketCore.scala:969:42, :989:70, :1287:27] wire _data_hazard_ex_T_3 = hazard_targets_1_1 & _data_hazard_ex_T_2; // @[RocketCore.scala:970:42, :989:70, :1287:27] wire _GEN_65 = id_waddr == ex_waddr; // @[RocketCore.scala:326:72, :453:36, :989:70] wire _data_hazard_ex_T_4; // @[RocketCore.scala:989:70] assign _data_hazard_ex_T_4 = _GEN_65; // @[RocketCore.scala:989:70] wire _fp_data_hazard_ex_T_7; // @[RocketCore.scala:990:90] assign _fp_data_hazard_ex_T_7 = _GEN_65; // @[RocketCore.scala:989:70, :990:90] wire _data_hazard_ex_T_5 = hazard_targets_2_1 & _data_hazard_ex_T_4; // @[RocketCore.scala:971:42, :989:70, :1287:27] wire _data_hazard_ex_T_6 = _data_hazard_ex_T_1 \| _data_hazard_ex_T_3; // @[RocketCore.scala:1287:{27,50}] wire _data_hazard_ex_T_7 = _data_hazard_ex_T_6 \| _data_hazard_ex_T_5; // @[RocketCore.scala:1287:{27,50}] wire data_hazard_ex = ex_ctrl_wxd & _data_hazard_ex_T_7; // @[RocketCore.scala:243:20, :989:36, :1287:50] wire _fp_data_hazard_ex_T = id_ctrl_fp & ex_ctrl_wfd; // @[RocketCore.scala:243:20, :321:21, :990:38] wire _fp_data_hazard_ex_T_2 = io_fpu_dec_ren1_0 & _fp_data_hazard_ex_T_1; // @[RocketCore.scala:153:7, :990:90, :1287:27] wire _fp_data_hazard_ex_T_4 = io_fpu_dec_ren2_0 & _fp_data_hazard_ex_T_3; // @[RocketCore.scala:153:7, :990:90, :1287:27] wire _fp_data_hazard_ex_T_5 = id_raddr3 == ex_waddr; // @[RocketCore.scala:326:72, :453:36, :990:90] wire _fp_data_hazard_ex_T_6 = io_fpu_dec_ren3_0 & _fp_data_hazard_ex_T_5; // @[RocketCore.scala:153:7, :990:90, :1287:27] wire _fp_data_hazard_ex_T_8 = io_fpu_dec_wen_0 & _fp_data_hazard_ex_T_7; // @[RocketCore.scala:153:7, :990:90, :1287:27] wire _fp_data_hazard_ex_T_9 = _fp_data_hazard_ex_T_2 \| _fp_data_hazard_ex_T_4; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_ex_T_10 = _fp_data_hazard_ex_T_9 \| _fp_data_hazard_ex_T_6; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_ex_T_11 = _fp_data_hazard_ex_T_10 \| _fp_data_hazard_ex_T_8; // @[RocketCore.scala:1287:{27,50}] wire fp_data_hazard_ex = _fp_data_hazard_ex_T & _fp_data_hazard_ex_T_11; // @[RocketCore.scala:990:{38,53}, :1287:50] wire _id_ex_hazard_T = data_hazard_ex & ex_cannot_bypass; // @[RocketCore.scala:988:139, :989:36, :991:54] wire _id_ex_hazard_T_1 = _id_ex_hazard_T \| fp_data_hazard_ex; // @[RocketCore.scala:990:53, :991:{54,74}] wire id_ex_hazard = ex_reg_valid & _id_ex_hazard_T_1; // @[RocketCore.scala:248:35, :991:{35,74}] wire _mem_cannot_bypass_T = \|mem_ctrl_csr; // @[RocketCore.scala:244:21, :997:40] wire _mem_cannot_bypass_T_1 = mem_ctrl_mem & mem_mem_cmd_bh; // @[RocketCore.scala:244:21, :995:41, :997:66] wire _mem_cannot_bypass_T_2 = _mem_cannot_bypass_T \| _mem_cannot_bypass_T_1; // @[RocketCore.scala:997:{40,50,66}] wire _mem_cannot_bypass_T_3 = _mem_cannot_bypass_T_2 \| mem_ctrl_mul; // @[RocketCore.scala:244:21, :997:{50,84}] wire _mem_cannot_bypass_T_4 = _mem_cannot_bypass_T_3 \| mem_ctrl_div; // @[RocketCore.scala:244:21, :997:{84,100}] wire _mem_cannot_bypass_T_5 = _mem_cannot_bypass_T_4 \| mem_ctrl_fp; // @[RocketCore.scala:244:21, :997:{100,116}] wire _mem_cannot_bypass_T_6 = _mem_cannot_bypass_T_5 \| mem_ctrl_rocc; // @[RocketCore.scala:244:21, :997:{116,131}] wire mem_cannot_bypass = _mem_cannot_bypass_T_6 \| mem_ctrl_vec; // @[RocketCore.scala:244:21, :997:{131,148}] wire _data_hazard_mem_T_1 = hazard_targets_0_1 & _data_hazard_mem_T; // @[RocketCore.scala:969:42, :998:72, :1287:27] wire _data_hazard_mem_T_3 = hazard_targets_1_1 & _data_hazard_mem_T_2; // @[RocketCore.scala:970:42, :998:72, :1287:27] wire _GEN_66 = id_waddr == mem_waddr; // @[RocketCore.scala:326:72, :454:38, :998:72] wire _data_hazard_mem_T_4; // @[RocketCore.scala:998:72] assign _data_hazard_mem_T_4 = _GEN_66; // @[RocketCore.scala:998:72] wire _fp_data_hazard_mem_T_7; // @[RocketCore.scala:999:92] assign _fp_data_hazard_mem_T_7 = _GEN_66; // @[RocketCore.scala:998:72, :999:92] wire _data_hazard_mem_T_5 = hazard_targets_2_1 & _data_hazard_mem_T_4; // @[RocketCore.scala:971:42, :998:72, :1287:27] wire _data_hazard_mem_T_6 = _data_hazard_mem_T_1 \| _data_hazard_mem_T_3; // @[RocketCore.scala:1287:{27,50}] wire _data_hazard_mem_T_7 = _data_hazard_mem_T_6 \| _data_hazard_mem_T_5; // @[RocketCore.scala:1287:{27,50}] wire data_hazard_mem = mem_ctrl_wxd & _data_hazard_mem_T_7; // @[RocketCore.scala:244:21, :998:38, :1287:50] wire _fp_data_hazard_mem_T = id_ctrl_fp & mem_ctrl_wfd; // @[RocketCore.scala:244:21, :321:21, :999:39] wire _fp_data_hazard_mem_T_2 = io_fpu_dec_ren1_0 & _fp_data_hazard_mem_T_1; // @[RocketCore.scala:153:7, :999:92, :1287:27] wire _fp_data_hazard_mem_T_4 = io_fpu_dec_ren2_0 & _fp_data_hazard_mem_T_3; // @[RocketCore.scala:153:7, :999:92, :1287:27] wire _fp_data_hazard_mem_T_5 = id_raddr3 == mem_waddr; // @[RocketCore.scala:326:72, :454:38, :999:92] wire _fp_data_hazard_mem_T_6 = io_fpu_dec_ren3_0 & _fp_data_hazard_mem_T_5; // @[RocketCore.scala:153:7, :999:92, :1287:27] wire _fp_data_hazard_mem_T_8 = io_fpu_dec_wen_0 & _fp_data_hazard_mem_T_7; // @[RocketCore.scala:153:7, :999:92, :1287:27] wire _fp_data_hazard_mem_T_9 = _fp_data_hazard_mem_T_2 \| _fp_data_hazard_mem_T_4; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_mem_T_10 = _fp_data_hazard_mem_T_9 \| _fp_data_hazard_mem_T_6; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_mem_T_11 = _fp_data_hazard_mem_T_10 \| _fp_data_hazard_mem_T_8; // @[RocketCore.scala:1287:{27,50}] wire fp_data_hazard_mem = _fp_data_hazard_mem_T & _fp_data_hazard_mem_T_11; // @[RocketCore.scala:999:{39,55}, :1287:50] wire _id_mem_hazard_T = data_hazard_mem & mem_cannot_bypass; // @[RocketCore.scala:997:148, :998:38, :1000:57] wire _id_mem_hazard_T_1 = _id_mem_hazard_T \| fp_data_hazard_mem; // @[RocketCore.scala:999:55, :1000:{57,78}] wire id_mem_hazard = mem_reg_valid & _id_mem_hazard_T_1; // @[RocketCore.scala:265:36, :1000:{37,78}] wire _id_load_use_T = mem_reg_valid & data_hazard_mem; // @[RocketCore.scala:265:36, :998:38, :1001:32] assign _id_load_use_T_1 = _id_load_use_T & mem_ctrl_mem; // @[RocketCore.scala:244:21, :1001:{32,51}] assign id_load_use = _id_load_use_T_1; // @[RocketCore.scala:332:25, :1001:51] wire _id_vconfig_hazard_T_1 = mem_reg_valid & mem_reg_set_vconfig; // @[RocketCore.scala:265:36, :275:36, :1004:20] wire _id_vconfig_hazard_T_2 = _id_vconfig_hazard_T_1; // @[RocketCore.scala:1003:42, :1004:20] wire _id_vconfig_hazard_T_3 = wb_reg_valid & wb_reg_set_vconfig; // @[RocketCore.scala:288:35, :293:35, :1005:19] wire _id_vconfig_hazard_T_4 = _id_vconfig_hazard_T_2 \| _id_vconfig_hazard_T_3; // @[RocketCore.scala:1003:42, :1004:44, :1005:19] wire _GEN_67 = id_raddr1 == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1008:70] wire _data_hazard_wb_T; // @[RocketCore.scala:1008:70] assign _data_hazard_wb_T = _GEN_67; // @[RocketCore.scala:1008:70] wire _fp_data_hazard_wb_T_1; // @[RocketCore.scala:1009:90] assign _fp_data_hazard_wb_T_1 = _GEN_67; // @[RocketCore.scala:1008:70, :1009:90] wire _data_hazard_wb_T_1 = hazard_targets_0_1 & _data_hazard_wb_T; // @[RocketCore.scala:969:42, :1008:70, :1287:27] wire _GEN_68 = id_raddr2 == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1008:70] wire _data_hazard_wb_T_2; // @[RocketCore.scala:1008:70] assign _data_hazard_wb_T_2 = _GEN_68; // @[RocketCore.scala:1008:70] wire _fp_data_hazard_wb_T_3; // @[RocketCore.scala:1009:90] assign _fp_data_hazard_wb_T_3 = _GEN_68; // @[RocketCore.scala:1008:70, :1009:90] wire _data_hazard_wb_T_3 = hazard_targets_1_1 & _data_hazard_wb_T_2; // @[RocketCore.scala:970:42, :1008:70, :1287:27] wire _GEN_69 = id_waddr == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1008:70] wire _data_hazard_wb_T_4; // @[RocketCore.scala:1008:70] assign _data_hazard_wb_T_4 = _GEN_69; // @[RocketCore.scala:1008:70] wire _fp_data_hazard_wb_T_7; // @[RocketCore.scala:1009:90] assign _fp_data_hazard_wb_T_7 = _GEN_69; // @[RocketCore.scala:1008:70, :1009:90] wire _data_hazard_wb_T_5 = hazard_targets_2_1 & _data_hazard_wb_T_4; // @[RocketCore.scala:971:42, :1008:70, :1287:27] wire _data_hazard_wb_T_6 = _data_hazard_wb_T_1 \| _data_hazard_wb_T_3; // @[RocketCore.scala:1287:{27,50}] wire _data_hazard_wb_T_7 = _data_hazard_wb_T_6 \| _data_hazard_wb_T_5; // @[RocketCore.scala:1287:{27,50}] wire data_hazard_wb = wb_ctrl_wxd & _data_hazard_wb_T_7; // @[RocketCore.scala:245:20, :1008:36, :1287:50] wire _fp_data_hazard_wb_T = id_ctrl_fp & wb_ctrl_wfd; // @[RocketCore.scala:245:20, :321:21, :1009:38] wire _fp_data_hazard_wb_T_2 = io_fpu_dec_ren1_0 & _fp_data_hazard_wb_T_1; // @[RocketCore.scala:153:7, :1009:90, :1287:27] wire _fp_data_hazard_wb_T_4 = io_fpu_dec_ren2_0 & _fp_data_hazard_wb_T_3; // @[RocketCore.scala:153:7, :1009:90, :1287:27] wire _fp_data_hazard_wb_T_5 = id_raddr3 == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1009:90] wire _fp_data_hazard_wb_T_6 = io_fpu_dec_ren3_0 & _fp_data_hazard_wb_T_5; // @[RocketCore.scala:153:7, :1009:90, :1287:27] wire _fp_data_hazard_wb_T_8 = io_fpu_dec_wen_0 & _fp_data_hazard_wb_T_7; // @[RocketCore.scala:153:7, :1009:90, :1287:27] wire _fp_data_hazard_wb_T_9 = _fp_data_hazard_wb_T_2 \| _fp_data_hazard_wb_T_4; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_wb_T_10 = _fp_data_hazard_wb_T_9 \| _fp_data_hazard_wb_T_6; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_wb_T_11 = _fp_data_hazard_wb_T_10 \| _fp_data_hazard_wb_T_8; // @[RocketCore.scala:1287:{27,50}] wire fp_data_hazard_wb = _fp_data_hazard_wb_T & _fp_data_hazard_wb_T_11; // @[RocketCore.scala:1009:{38,53}, :1287:50] wire _id_wb_hazard_T = data_hazard_wb & wb_set_sboard; // @[RocketCore.scala:756:69, :1008:36, :1010:54] wire _id_wb_hazard_T_1 = _id_wb_hazard_T \| fp_data_hazard_wb; // @[RocketCore.scala:1009:53, :1010:{54,71}] wire id_wb_hazard = wb_reg_valid & _id_wb_hazard_T_1; // @[RocketCore.scala:288:35, :1010:{35,71}] reg [31:0] _id_stall_fpu_r; // @[RocketCore.scala:1305:29] wire _id_stall_fpu_T = wb_dcache_miss \| wb_ctrl_vec; // @[RocketCore.scala:245:20, :596:36, :1014:36] wire _id_stall_fpu_T_1 = _id_stall_fpu_T & wb_ctrl_wfd; // @[RocketCore.scala:245:20, :1014:{36,52}] wire _id_stall_fpu_T_2 = _id_stall_fpu_T_1 \| io_fpu_sboard_set_0; // @[RocketCore.scala:153:7, :1014:{52,67}] wire _id_stall_fpu_T_3 = _id_stall_fpu_T_2 & wb_valid; // @[RocketCore.scala:815:45, :1014:{67,89}] wire _id_stall_fpu_T_7 = _id_stall_fpu_T_3; // @[RocketCore.scala:1014:89, :1312:17] wire [31:0] _id_stall_fpu_T_5 = _id_stall_fpu_T_3 ? _id_stall_fpu_T_4 : 32'h0; // @[RocketCore.scala:1014:89, :1309:{49,58}] wire [31:0] _id_stall_fpu_T_6 = _id_stall_fpu_r \| _id_stall_fpu_T_5; // @[RocketCore.scala:1300:60, :1305:29, :1309:49] wire _id_stall_fpu_T_8 = dmem_resp_replay & dmem_resp_fpu; // @[RocketCore.scala:766:45, :769:42, :1016:39] wire _id_stall_fpu_T_9 = _id_stall_fpu_T_8; // @[RocketCore.scala:1016:{39,57}] wire [31:0] _id_stall_fpu_T_10 = 32'h1 << io_fpu_ll_resp_tag_0; // @[RocketCore.scala:153:7, :1309:58] wire [31:0] _id_stall_fpu_T_11 = _id_stall_fpu_T_9 ? _id_stall_fpu_T_10 : 32'h0; // @[RocketCore.scala:1016:57, :1309:{49,58}] wire [31:0] _id_stall_fpu_T_12 = ~_id_stall_fpu_T_11; // @[RocketCore.scala:1301:64, :1309:49] wire [31:0] _id_stall_fpu_T_13 = _id_stall_fpu_T_6 & _id_stall_fpu_T_12; // @[RocketCore.scala:1300:60, :1301:{62,64}] wire _id_stall_fpu_T_14 = _id_stall_fpu_T_7 \| _id_stall_fpu_T_9; // @[RocketCore.scala:1016:57, :1312:17] wire [31:0] _id_stall_fpu_T_15 = 32'h1 << io_fpu_sboard_clra_0; // @[RocketCore.scala:153:7, :1309:58] wire [31:0] _id_stall_fpu_T_16 = io_fpu_sboard_clr_0 ? _id_stall_fpu_T_15 : 32'h0; // @[RocketCore.scala:153:7, :1309:{49,58}] wire [31:0] _id_stall_fpu_T_17 = ~_id_stall_fpu_T_16; // @[RocketCore.scala:1301:64, :1309:49] wire [31:0] _id_stall_fpu_T_18 = _id_stall_fpu_T_13 & _id_stall_fpu_T_17; // @[RocketCore.scala:1301:{62,64}] wire _id_stall_fpu_T_19 = _id_stall_fpu_T_14 \| io_fpu_sboard_clr_0; // @[RocketCore.scala:153:7, :1312:17] wire [31:0] _id_stall_fpu_T_20 = _id_stall_fpu_r >> _GEN_62; // @[RocketCore.scala:1302:35, :1305:29] wire _id_stall_fpu_T_21 = _id_stall_fpu_T_20[0]; // @[RocketCore.scala:1302:35] wire _id_stall_fpu_T_22 = io_fpu_dec_ren1_0 & _id_stall_fpu_T_21; // @[RocketCore.scala:153:7, :1287:27, :1302:35] wire [31:0] _id_stall_fpu_T_23 = _id_stall_fpu_r >> _GEN_63; // @[RocketCore.scala:1302:35, :1305:29] wire _id_stall_fpu_T_24 = _id_stall_fpu_T_23[0]; // @[RocketCore.scala:1302:35] wire _id_stall_fpu_T_25 = io_fpu_dec_ren2_0 & _id_stall_fpu_T_24; // @[RocketCore.scala:153:7, :1287:27, :1302:35] wire [31:0] _id_stall_fpu_T_26 = _id_stall_fpu_r >> id_raddr3; // @[RocketCore.scala:326:72, :1302:35, :1305:29] wire _id_stall_fpu_T_27 = _id_stall_fpu_T_26[0]; // @[RocketCore.scala:1302:35] wire _id_stall_fpu_T_28 = io_fpu_dec_ren3_0 & _id_stall_fpu_T_27; // @[RocketCore.scala:153:7, :1287:27, :1302:35] wire [31:0] _id_stall_fpu_T_29 = _id_stall_fpu_r >> _GEN_64; // @[RocketCore.scala:1302:35, :1305:29] wire _id_stall_fpu_T_30 = _id_stall_fpu_T_29[0]; // @[RocketCore.scala:1302:35] wire _id_stall_fpu_T_31 = io_fpu_dec_wen_0 & _id_stall_fpu_T_30; // @[RocketCore.scala:153:7, :1287:27, :1302:35] wire _id_stall_fpu_T_32 = _id_stall_fpu_T_22 \| _id_stall_fpu_T_25; // @[RocketCore.scala:1287:{27,50}] wire _id_stall_fpu_T_33 = _id_stall_fpu_T_32 \| _id_stall_fpu_T_28; // @[RocketCore.scala:1287:{27,50}] wire id_stall_fpu = _id_stall_fpu_T_33 \| _id_stall_fpu_T_31; // @[RocketCore.scala:1287:{27,50}] reg dcache_blocked_blocked; // @[RocketCore.scala:1024:22] wire _dcache_blocked_blocked_T = ~io_dmem_req_ready_0; // @[RocketCore.scala:153:7, :597:45, :1025:16] wire _dcache_blocked_blocked_T_1 = _dcache_blocked_blocked_T; // @[RocketCore.scala:1025:{16,35}] wire _dcache_blocked_blocked_T_2 = ~io_dmem_perf_grant_0; // @[RocketCore.scala:153:7, :1025:63] wire _dcache_blocked_blocked_T_3 = _dcache_blocked_blocked_T_1 & _dcache_blocked_blocked_T_2; // @[RocketCore.scala:1025:{35,60,63}] wire _dcache_blocked_blocked_T_4 = dcache_blocked_blocked \| io_dmem_req_valid_0; // @[RocketCore.scala:153:7, :1024:22, :1025:95] wire _dcache_blocked_blocked_T_5 = _dcache_blocked_blocked_T_4 \| io_dmem_s2_nack_0; // @[RocketCore.scala:153:7, :1025:{95,116}] wire _dcache_blocked_blocked_T_6 = _dcache_blocked_blocked_T_3 & _dcache_blocked_blocked_T_5; // @[RocketCore.scala:1025:{60,83,116}] wire _dcache_blocked_T = ~io_dmem_perf_grant_0; // @[RocketCore.scala:153:7, :1025:63, :1026:16] wire dcache_blocked = dcache_blocked_blocked & _dcache_blocked_T; // @[RocketCore.scala:1024:22, :1026:{13,16}] reg rocc_blocked; // @[RocketCore.scala:1028:25] wire _rocc_blocked_T = ~wb_xcpt; // @[RocketCore.scala:815:48, :1029:19, :1278:14] wire _rocc_blocked_T_2 = _rocc_blocked_T; // @[RocketCore.scala:1029:{19,28}] wire _rocc_blocked_T_3 = io_rocc_cmd_valid \| rocc_blocked; // @[RocketCore.scala:153:7, :1028:25, :1029:72] wire _rocc_blocked_T_4 = _rocc_blocked_T_2 & _rocc_blocked_T_3; // @[RocketCore.scala:1029:{28,50,72}] wire _ctrl_stalld_T = id_ex_hazard \| id_mem_hazard; // @[RocketCore.scala:991:35, :1000:37, :1032:18] wire _ctrl_stalld_T_1 = _ctrl_stalld_T \| id_wb_hazard; // @[RocketCore.scala:1010:35, :1032:{18,35}] wire _ctrl_stalld_T_2 = _ctrl_stalld_T_1 \| id_sboard_hazard; // @[RocketCore.scala:1032:{35,51}, :1287:50] wire _ctrl_stalld_T_3 = _ctrl_stalld_T_2; // @[RocketCore.scala:1032:{51,71}] wire _ctrl_stalld_T_4 = ex_reg_valid \| mem_reg_valid; // @[RocketCore.scala:248:35, :265:36, :1034:40] wire _ctrl_stalld_T_5 = _ctrl_stalld_T_4 \| wb_reg_valid; // @[RocketCore.scala:288:35, :1034:{40,57}] wire _ctrl_stalld_T_6 = _csr_io_singleStep & _ctrl_stalld_T_5; // @[RocketCore.scala:341:19, :1034:{23,57}] wire _ctrl_stalld_T_7 = _ctrl_stalld_T_3 \| _ctrl_stalld_T_6; // @[RocketCore.scala:1032:71, :1033:23, :1034:23] wire _ctrl_stalld_T_8 = id_csr_en & _csr_io_decode_0_fp_csr; // @[package.scala:81:59] wire _ctrl_stalld_T_9 = ~io_fpu_fcsr_rdy_0; // @[RocketCore.scala:153:7, :1035:45] wire _ctrl_stalld_T_10 = _ctrl_stalld_T_8 & _ctrl_stalld_T_9; // @[RocketCore.scala:1035:{15,42,45}] wire _ctrl_stalld_T_11 = _ctrl_stalld_T_7 \| _ctrl_stalld_T_10; // @[RocketCore.scala:1033:23, :1034:74, :1035:42] wire _ctrl_stalld_T_14 = _ctrl_stalld_T_11; // @[RocketCore.scala:1034:74, :1035:62] wire _ctrl_stalld_T_15 = id_ctrl_fp & id_stall_fpu; // @[RocketCore.scala:321:21, :1037:16, :1287:50] wire _ctrl_stalld_T_16 = _ctrl_stalld_T_14 \| _ctrl_stalld_T_15; // @[RocketCore.scala:1035:62, :1036:61, :1037:16] wire _ctrl_stalld_T_17 = id_ctrl_mem & dcache_blocked; // @[RocketCore.scala:321:21, :1026:13, :1038:17] wire _ctrl_stalld_T_18 = _ctrl_stalld_T_16 \| _ctrl_stalld_T_17; // @[RocketCore.scala:1036:61, :1037:32, :1038:17] wire _ctrl_stalld_T_19 = id_ctrl_rocc & rocc_blocked; // @[RocketCore.scala:321:21, :1028:25, :1039:18] wire _ctrl_stalld_T_20 = _ctrl_stalld_T_18 \| _ctrl_stalld_T_19; // @[RocketCore.scala:1037:32, :1038:35, :1039:18] wire _ctrl_stalld_T_21 = ~wb_wxd; // @[RocketCore.scala:755:29, :782:26, :1040:65] wire _ctrl_stalld_T_22 = _div_io_resp_valid & _ctrl_stalld_T_21; // @[RocketCore.scala:511:19, :1040:{62,65}] wire _ctrl_stalld_T_23 = _div_io_req_ready \| _ctrl_stalld_T_22; // @[RocketCore.scala:511:19, :1040:{40,62}] wire _ctrl_stalld_T_24 = ~_ctrl_stalld_T_23; // @[RocketCore.scala:1040:{21,40}] wire _ctrl_stalld_T_25 = _ctrl_stalld_T_24 \| _div_io_req_valid_T; // @[RocketCore.scala:512:36, :1040:{21,75}] wire _ctrl_stalld_T_26 = id_ctrl_div & _ctrl_stalld_T_25; // @[RocketCore.scala:321:21, :1040:{17,75}] wire _ctrl_stalld_T_27 = _ctrl_stalld_T_20 \| _ctrl_stalld_T_26; // @[RocketCore.scala:1038:35, :1039:34, :1040:17] wire _ctrl_stalld_T_29 = _ctrl_stalld_T_27; // @[RocketCore.scala:1039:34, :1040:96] wire _ctrl_stalld_T_30 = _ctrl_stalld_T_29 \| id_do_fence; // @[RocketCore.scala:410:32, :1040:96, :1041:15] wire _ctrl_stalld_T_31 = _ctrl_stalld_T_30 \| _csr_io_csr_stall; // @[RocketCore.scala:341:19, :1041:15, :1042:17] wire _ctrl_stalld_T_32 = _ctrl_stalld_T_31 \| id_reg_pause; // @[RocketCore.scala:161:25, :1042:17, :1043:22] wire ctrl_stalld = _ctrl_stalld_T_32; // @[RocketCore.scala:1043:22, :1044:18] wire _ctrl_killd_T = ~_ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20, :1046:17] wire _ctrl_killd_T_1 = _ctrl_killd_T \| _ibuf_io_inst_0_bits_replay; // @[RocketCore.scala:311:20, :1046:{17,40}] wire _ctrl_killd_T_2 = _ctrl_killd_T_1 \| take_pc_mem_wb; // @[RocketCore.scala:307:35, :1046:{40,71}] wire _ctrl_killd_T_3 = _ctrl_killd_T_2 \| ctrl_stalld; // @[RocketCore.scala:1044:18, :1046:{71,89}] assign _ctrl_killd_T_4 = _ctrl_killd_T_3 \| _csr_io_interrupt; // @[RocketCore.scala:341:19, :1046:{89,104}] assign ctrl_killd = _ctrl_killd_T_4; // @[RocketCore.scala:338:24, :1046:104] assign _io_imem_req_bits_speculative_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :1049:35] assign io_imem_req_bits_speculative_0 = _io_imem_req_bits_speculative_T; // @[RocketCore.scala:153:7, :1049:35] wire _io_imem_req_bits_pc_T = wb_xcpt \| _csr_io_eret; // @[RocketCore.scala:341:19, :1051:17, :1278:14] wire [39:0] _io_imem_req_bits_pc_T_1 = replay_wb ? wb_reg_pc : mem_npc; // @[RocketCore.scala:295:22, :619:139, :761:71, :1052:8] assign _io_imem_req_bits_pc_T_2 = _io_imem_req_bits_pc_T ? _csr_io_evec : _io_imem_req_bits_pc_T_1; // @[RocketCore.scala:341:19, :1051:{8,17}, :1052:8] assign io_imem_req_bits_pc_0 = _io_imem_req_bits_pc_T_2; // @[RocketCore.scala:153:7, :1051:8] wire _io_imem_flush_icache_T = wb_reg_valid & wb_ctrl_fence_i; // @[RocketCore.scala:245:20, :288:35, :1054:40] wire _io_imem_flush_icache_T_1 = ~io_dmem_s2_nack_0; // @[RocketCore.scala:153:7, :1054:62] assign _io_imem_flush_icache_T_2 = _io_imem_flush_icache_T & _io_imem_flush_icache_T_1; // @[RocketCore.scala:1054:{40,59,62}] assign io_imem_flush_icache_0 = _io_imem_flush_icache_T_2; // @[RocketCore.scala:153:7, :1054:59] wire _io_imem_might_request_imem_might_request_reg_T = ex_pc_valid \| mem_pc_valid; // @[RocketCore.scala:595:51, :614:54, :1056:43] wire _io_imem_might_request_imem_might_request_reg_T_1 = io_ptw_customCSRs_csrs_0_value_0[1]; // @[CustomCSRs.scala:44:61] wire _io_imem_might_request_imem_might_request_reg_T_2 = _io_imem_might_request_imem_might_request_reg_T \| _io_imem_might_request_imem_might_request_reg_T_1; // @[CustomCSRs.scala:44:61] wire _io_imem_might_request_imem_might_request_reg_T_3 = _io_imem_might_request_imem_might_request_reg_T_2; // @[RocketCore.scala:1056:{59,103}] wire _io_imem_progress_T = ~replay_wb_common; // @[RocketCore.scala:757:42, :1059:47] wire _io_imem_progress_T_1 = wb_reg_valid & _io_imem_progress_T; // @[RocketCore.scala:288:35, :1059:{44,47}] reg io_imem_progress_REG; // @[RocketCore.scala:1059:30] assign io_imem_progress_0 = io_imem_progress_REG; // @[RocketCore.scala:153:7, :1059:30] assign _io_imem_sfence_valid_T = wb_reg_valid & wb_reg_sfence; // @[RocketCore.scala:288:35, :294:26, :1060:40] assign io_imem_sfence_valid_0 = _io_imem_sfence_valid_T; // @[RocketCore.scala:153:7, :1060:40] assign _io_imem_sfence_bits_rs1_T = wb_reg_mem_size[0]; // @[RocketCore.scala:296:28, :1061:45] assign io_imem_sfence_bits_rs1_0 = _io_imem_sfence_bits_rs1_T; // @[RocketCore.scala:153:7, :1061:45] assign _io_imem_sfence_bits_rs2_T = wb_reg_mem_size[1]; // @[RocketCore.scala:296:28, :1062:45] assign io_imem_sfence_bits_rs2_0 = _io_imem_sfence_bits_rs2_T; // @[RocketCore.scala:153:7, :1062:45] assign io_imem_sfence_bits_asid_0 = wb_reg_rs2[0]; // @[RocketCore.scala:153:7, :303:23, :1064:28] wire _ibuf_io_inst_0_ready_T = ~ctrl_stalld; // @[RocketCore.scala:1044:18, :1069:28] wire _io_imem_btb_update_valid_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :1071:48] wire _io_imem_btb_update_valid_T_1 = mem_reg_valid & _io_imem_btb_update_valid_T; // @[RocketCore.scala:265:36, :1071:{45,48}] wire _io_imem_btb_update_valid_T_2 = _io_imem_btb_update_valid_T_1 & mem_wrong_npc; // @[RocketCore.scala:621:8, :1071:{45,60}] wire _io_imem_btb_update_valid_T_3 = ~mem_cfi; // @[RocketCore.scala:625:50, :1071:81] wire _io_imem_btb_update_valid_T_4 = _io_imem_btb_update_valid_T_3 \| mem_cfi_taken; // @[RocketCore.scala:626:74, :1071:{81,90}] assign _io_imem_btb_update_valid_T_5 = _io_imem_btb_update_valid_T_2 & _io_imem_btb_update_valid_T_4; // @[RocketCore.scala:1071:{60,77,90}] assign io_imem_btb_update_valid_0 = _io_imem_btb_update_valid_T_5; // @[RocketCore.scala:153:7, :1071:77] wire _GEN_70 = mem_ctrl_jal \| mem_ctrl_jalr; // @[RocketCore.scala:244:21, :1074:23] wire _io_imem_btb_update_bits_cfiType_T; // @[RocketCore.scala:1074:23] assign _io_imem_btb_update_bits_cfiType_T = _GEN_70; // @[RocketCore.scala:1074:23] wire _io_imem_btb_update_bits_cfiType_T_8; // @[RocketCore.scala:1076:22] assign _io_imem_btb_update_bits_cfiType_T_8 = _GEN_70; // @[RocketCore.scala:1074:23, :1076:22] wire _io_imem_btb_update_bits_cfiType_T_1 = mem_waddr[0]; // @[RocketCore.scala:454:38, :1074:53] wire _io_imem_btb_update_bits_cfiType_T_2 = _io_imem_btb_update_bits_cfiType_T & _io_imem_btb_update_bits_cfiType_T_1; // @[RocketCore.scala:1074:{23,41,53}] wire [4:0] _io_imem_btb_update_bits_cfiType_T_3 = mem_reg_inst[19:15]; // @[RocketCore.scala:278:25, :1075:39] wire [4:0] _io_imem_btb_update_bits_cfiType_T_4 = _io_imem_btb_update_bits_cfiType_T_3; // @[RocketCore.scala:1075:{39,47}] wire [4:0] _io_imem_btb_update_bits_cfiType_T_5 = _io_imem_btb_update_bits_cfiType_T_4 & 5'h1B; // @[RocketCore.scala:1075:{47,64}] wire _io_imem_btb_update_bits_cfiType_T_6 = _io_imem_btb_update_bits_cfiType_T_5 == 5'h1; // @[RocketCore.scala:1075:64] wire _io_imem_btb_update_bits_cfiType_T_7 = mem_ctrl_jalr & _io_imem_btb_update_bits_cfiType_T_6; // @[RocketCore.scala:244:21, :1075:{23,64}] wire _io_imem_btb_update_bits_cfiType_T_9 = _io_imem_btb_update_bits_cfiType_T_8; // @[RocketCore.scala:1076:{8,22}] wire [1:0] _io_imem_btb_update_bits_cfiType_T_10 = _io_imem_btb_update_bits_cfiType_T_7 ? 2'h3 : {1'h0, _io_imem_btb_update_bits_cfiType_T_9}; // @[RocketCore.scala:1075:{8,23}, :1076:8] assign _io_imem_btb_update_bits_cfiType_T_11 = _io_imem_btb_update_bits_cfiType_T_2 ? 2'h2 : _io_imem_btb_update_bits_cfiType_T_10; // @[RocketCore.scala:1074:{8,41}, :1075:8] assign io_imem_btb_update_bits_cfiType_0 = _io_imem_btb_update_bits_cfiType_T_11; // @[RocketCore.scala:153:7, :1074:8] assign io_imem_btb_update_bits_target_0 = io_imem_req_bits_pc_0[38:0]; // @[RocketCore.scala:153:7, :1078:34] wire [1:0] _io_imem_btb_update_bits_br_pc_T = {~mem_reg_rvc, 1'h0}; // @[RocketCore.scala:266:36, :1079:74] wire [40:0] _io_imem_btb_update_bits_br_pc_T_1 = {1'h0, mem_reg_pc} + {39'h0, _io_imem_btb_update_bits_br_pc_T}; // @[RocketCore.scala:277:23, :1079:{69,74}] wire [39:0] _io_imem_btb_update_bits_br_pc_T_2 = _io_imem_btb_update_bits_br_pc_T_1[39:0]; // @[RocketCore.scala:1079:69] assign io_imem_btb_update_bits_br_pc_0 = _io_imem_btb_update_bits_br_pc_T_2[38:0]; // @[RocketCore.scala:153:7, :1079:{33,69}] wire [38:0] _io_imem_btb_update_bits_pc_T = ~io_imem_btb_update_bits_br_pc_0; // @[RocketCore.scala:153:7, :1080:35] wire [38:0] _io_imem_btb_update_bits_pc_T_1 = {_io_imem_btb_update_bits_pc_T[38:2], 2'h3}; // @[RocketCore.scala:1080:{35,66}] assign _io_imem_btb_update_bits_pc_T_2 = ~_io_imem_btb_update_bits_pc_T_1; // @[RocketCore.scala:1080:{33,66}] assign io_imem_btb_update_bits_pc_0 = _io_imem_btb_update_bits_pc_T_2; // @[RocketCore.scala:153:7, :1080:33] wire _io_imem_bht_update_valid_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :1084:48] assign _io_imem_bht_update_valid_T_1 = mem_reg_valid & _io_imem_bht_update_valid_T; // @[RocketCore.scala:265:36, :1084:{45,48}] assign io_imem_bht_update_valid_0 = _io_imem_bht_update_valid_T_1; // @[RocketCore.scala:153:7, :1084:45] wire _io_fpu_valid_T = ~ctrl_killd; // @[RocketCore.scala:338:24, :525:19, :1094:19] assign _io_fpu_valid_T_1 = _io_fpu_valid_T & id_ctrl_fp; // @[RocketCore.scala:321:21, :1094:{19,31}] assign io_fpu_valid_0 = _io_fpu_valid_T_1; // @[RocketCore.scala:153:7, :1094:31] assign _io_fpu_ll_resp_val_T = dmem_resp_valid & dmem_resp_fpu; // @[RocketCore.scala:766:45, :768:44, :1099:41] assign io_fpu_ll_resp_val_0 = _io_fpu_ll_resp_val_T; // @[RocketCore.scala:153:7, :1099:41] assign io_fpu_ll_resp_type_0 = {1'h0, io_dmem_resp_bits_size_0}; // @[RocketCore.scala:153:7, :1101:23] assign _io_fpu_keep_clock_enabled_T = io_ptw_customCSRs_csrs_0_value_0[2]; // @[CustomCSRs.scala:45:59] assign io_fpu_keep_clock_enabled_0 = _io_fpu_keep_clock_enabled_T; // @[CustomCSRs.scala:45:59] assign _io_dmem_req_valid_T = ex_reg_valid & ex_ctrl_mem; // @[RocketCore.scala:243:20, :248:35, :1130:41] assign io_dmem_req_valid_0 = _io_dmem_req_valid_T; // @[RocketCore.scala:153:7, :1130:41] wire [5:0] ex_dcache_tag = {ex_waddr, ex_ctrl_fp}; // @[RocketCore.scala:243:20, :453:36, :1131:26] assign io_dmem_req_bits_tag_0 = {1'h0, ex_dcache_tag}; // @[RocketCore.scala:153:7, :1131:26, :1133:25] wire _io_dmem_req_bits_signed_T_1 = ex_reg_inst[14]; // @[RocketCore.scala:259:24, :1136:75] wire _io_dmem_req_bits_signed_T_2 = _io_dmem_req_bits_signed_T_1; // @[RocketCore.scala:1136:{34,75}] assign _io_dmem_req_bits_signed_T_3 = ~_io_dmem_req_bits_signed_T_2; // @[RocketCore.scala:1136:{30,34}] assign io_dmem_req_bits_signed_0 = _io_dmem_req_bits_signed_T_3; // @[RocketCore.scala:153:7, :1136:30] wire [24:0] _io_dmem_req_bits_addr_a_T = ex_rs_0[63:39]; // @[RocketCore.scala:469:14, :1293:17] wire [24:0] io_dmem_req_bits_addr_a = _io_dmem_req_bits_addr_a_T; // @[RocketCore.scala:1293:{17,23}] wire _io_dmem_req_bits_addr_msb_T = io_dmem_req_bits_addr_a == 25'h0; // @[RocketCore.scala:1293:23, :1294:21] wire _io_dmem_req_bits_addr_msb_T_1 = &io_dmem_req_bits_addr_a; // @[RocketCore.scala:1293:23, :1294:34] wire _io_dmem_req_bits_addr_msb_T_2 = _io_dmem_req_bits_addr_msb_T \| _io_dmem_req_bits_addr_msb_T_1; // @[RocketCore.scala:1294:{21,29,34}] wire _io_dmem_req_bits_addr_msb_T_3 = _alu_io_adder_out[39]; // @[RocketCore.scala:504:19, :1294:46] wire _io_dmem_req_bits_addr_msb_T_4 = _alu_io_adder_out[38]; // @[RocketCore.scala:504:19, :1294:54] wire _io_dmem_req_bits_addr_msb_T_5 = ~_io_dmem_req_bits_addr_msb_T_4; // @[RocketCore.scala:1294:{51,54}] wire io_dmem_req_bits_addr_msb = _io_dmem_req_bits_addr_msb_T_2 ? _io_dmem_req_bits_addr_msb_T_3 : _io_dmem_req_bits_addr_msb_T_5; // @[RocketCore.scala:1294:{18,29,46,51}] wire [38:0] _io_dmem_req_bits_addr_T = _alu_io_adder_out[38:0]; // @[RocketCore.scala:504:19, :1295:16] assign _io_dmem_req_bits_addr_T_1 = {io_dmem_req_bits_addr_msb, _io_dmem_req_bits_addr_T}; // @[RocketCore.scala:1294:18, :1295:{8,16}] assign io_dmem_req_bits_addr_0 = _io_dmem_req_bits_addr_T_1; // @[RocketCore.scala:153:7, :1295:8] assign io_dmem_req_bits_dprv_0 = _io_dmem_req_bits_dprv_T; // @[RocketCore.scala:153:7, :1140:31] assign io_dmem_req_bits_dv_0 = _io_dmem_req_bits_dv_T; // @[RocketCore.scala:153:7, :1141:37] wire _io_dmem_req_bits_no_resp_T_4 = _io_dmem_req_bits_no_resp_T \| _io_dmem_req_bits_no_resp_T_1; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_5 = _io_dmem_req_bits_no_resp_T_4 \| _io_dmem_req_bits_no_resp_T_2; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_6 = _io_dmem_req_bits_no_resp_T_5 \| _io_dmem_req_bits_no_resp_T_3; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_11 = _io_dmem_req_bits_no_resp_T_7 \| _io_dmem_req_bits_no_resp_T_8; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_12 = _io_dmem_req_bits_no_resp_T_11 \| _io_dmem_req_bits_no_resp_T_9; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_13 = _io_dmem_req_bits_no_resp_T_12 \| _io_dmem_req_bits_no_resp_T_10; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_19 = _io_dmem_req_bits_no_resp_T_14 \| _io_dmem_req_bits_no_resp_T_15; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_20 = _io_dmem_req_bits_no_resp_T_19 \| _io_dmem_req_bits_no_resp_T_16; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_21 = _io_dmem_req_bits_no_resp_T_20 \| _io_dmem_req_bits_no_resp_T_17; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_22 = _io_dmem_req_bits_no_resp_T_21 \| _io_dmem_req_bits_no_resp_T_18; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_23 = _io_dmem_req_bits_no_resp_T_13 \| _io_dmem_req_bits_no_resp_T_22; // @[package.scala:81:59] wire _io_dmem_req_bits_no_resp_T_24 = _io_dmem_req_bits_no_resp_T_6 \| _io_dmem_req_bits_no_resp_T_23; // @[package.scala:81:59] wire _io_dmem_req_bits_no_resp_T_25 = ~_io_dmem_req_bits_no_resp_T_24; // @[RocketCore.scala:1142:31] wire _io_dmem_req_bits_no_resp_T_26 = ~ex_ctrl_fp; // @[RocketCore.scala:243:20, :1142:60] wire _io_dmem_req_bits_no_resp_T_27 = ex_waddr == 5'h0; // @[RocketCore.scala:453:36, :1142:84] wire _io_dmem_req_bits_no_resp_T_28 = _io_dmem_req_bits_no_resp_T_26 & _io_dmem_req_bits_no_resp_T_27; // @[RocketCore.scala:1142:{60,72,84}] assign _io_dmem_req_bits_no_resp_T_29 = _io_dmem_req_bits_no_resp_T_25 \| _io_dmem_req_bits_no_resp_T_28; // @[RocketCore.scala:1142:{31,56,72}] assign io_dmem_req_bits_no_resp_0 = _io_dmem_req_bits_no_resp_T_29; // @[RocketCore.scala:153:7, :1142:56] assign _io_dmem_s1_data_data_T = mem_ctrl_fp ? io_fpu_store_data_0 : mem_reg_rs2; // @[RocketCore.scala:153:7, :244:21, :283:24, :1148:63] assign io_dmem_s1_data_data_0 = _io_dmem_s1_data_data_T; // @[RocketCore.scala:153:7, :1148:63] wire _io_dmem_s1_kill_T = killm_common \| mem_ldst_xcpt; // @[RocketCore.scala:700:68, :1151:35, :1278:14] wire _io_dmem_s1_kill_T_1 = _io_dmem_s1_kill_T \| fpu_kill_mem; // @[RocketCore.scala:696:51, :1151:{35,52}] assign _io_dmem_s1_kill_T_2 = _io_dmem_s1_kill_T_1; // @[RocketCore.scala:1151:{52,68}] assign io_dmem_s1_kill_0 = _io_dmem_s1_kill_T_2; // @[RocketCore.scala:153:7, :1151:68] wire _io_dmem_keep_clock_enabled_T = _ibuf_io_inst_0_valid & id_ctrl_mem; // @[RocketCore.scala:311:20, :321:21, :1154:55] wire _io_dmem_keep_clock_enabled_T_1 = ~_csr_io_csr_stall; // @[RocketCore.scala:341:19, :1154:73] assign _io_dmem_keep_clock_enabled_T_2 = _io_dmem_keep_clock_enabled_T & _io_dmem_keep_clock_enabled_T_1; // @[RocketCore.scala:1154:{55,70,73}] assign io_dmem_keep_clock_enabled_0 = _io_dmem_keep_clock_enabled_T_2; // @[RocketCore.scala:153:7, :1154:70] wire _io_rocc_cmd_valid_T_1 = ~replay_wb_common; // @[RocketCore.scala:757:42, :1059:47, :1156:56] assign _io_rocc_cmd_valid_T_2 = _io_rocc_cmd_valid_T & _io_rocc_cmd_valid_T_1; // @[RocketCore.scala:1156:{37,53,56}] assign io_rocc_cmd_valid = _io_rocc_cmd_valid_T_2; // @[RocketCore.scala:153:7, :1156:53] wire [6:0] _io_rocc_cmd_bits_inst_T_7; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_funct = _io_rocc_cmd_bits_inst_WIRE_funct; // @[RocketCore.scala:153:7, :1159:48] wire [4:0] _io_rocc_cmd_bits_inst_T_6; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_rs2 = _io_rocc_cmd_bits_inst_WIRE_rs2; // @[RocketCore.scala:153:7, :1159:48] wire [4:0] _io_rocc_cmd_bits_inst_T_5; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_rs1 = _io_rocc_cmd_bits_inst_WIRE_rs1; // @[RocketCore.scala:153:7, :1159:48] wire _io_rocc_cmd_bits_inst_T_4; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_xd = _io_rocc_cmd_bits_inst_WIRE_xd; // @[RocketCore.scala:153:7, :1159:48] wire _io_rocc_cmd_bits_inst_T_3; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_xs1 = _io_rocc_cmd_bits_inst_WIRE_xs1; // @[RocketCore.scala:153:7, :1159:48] wire _io_rocc_cmd_bits_inst_T_2; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_xs2 = _io_rocc_cmd_bits_inst_WIRE_xs2; // @[RocketCore.scala:153:7, :1159:48] wire [4:0] _io_rocc_cmd_bits_inst_T_1; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_rd = _io_rocc_cmd_bits_inst_WIRE_rd; // @[RocketCore.scala:153:7, :1159:48] wire [6:0] _io_rocc_cmd_bits_inst_T; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_opcode = _io_rocc_cmd_bits_inst_WIRE_opcode; // @[RocketCore.scala:153:7, :1159:48] assign _io_rocc_cmd_bits_inst_T = _io_rocc_cmd_bits_inst_WIRE_1[6:0]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_opcode = _io_rocc_cmd_bits_inst_T; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_1 = _io_rocc_cmd_bits_inst_WIRE_1[11:7]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_rd = _io_rocc_cmd_bits_inst_T_1; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_2 = _io_rocc_cmd_bits_inst_WIRE_1[12]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_xs2 = _io_rocc_cmd_bits_inst_T_2; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_3 = _io_rocc_cmd_bits_inst_WIRE_1[13]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_xs1 = _io_rocc_cmd_bits_inst_T_3; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_4 = _io_rocc_cmd_bits_inst_WIRE_1[14]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_xd = _io_rocc_cmd_bits_inst_T_4; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_5 = _io_rocc_cmd_bits_inst_WIRE_1[19:15]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_rs1 = _io_rocc_cmd_bits_inst_T_5; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_6 = _io_rocc_cmd_bits_inst_WIRE_1[24:20]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_rs2 = _io_rocc_cmd_bits_inst_T_6; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_7 = _io_rocc_cmd_bits_inst_WIRE_1[31:25]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_funct = _io_rocc_cmd_bits_inst_T_7; // @[RocketCore.scala:1159:48] wire [4:0] _unpause_T = _csr_io_time[4:0]; // @[RocketCore.scala:341:19, :1164:28] wire _unpause_T_1 = _unpause_T == 5'h0; // @[RocketCore.scala:1164:{28,62}] wire _unpause_T_2 = _unpause_T_1 \| _csr_io_inhibit_cycle; // @[RocketCore.scala:341:19, :1164:{62,70}] wire _unpause_T_3 = _unpause_T_2 \| io_dmem_perf_release_0; // @[RocketCore.scala:153:7, :1164:{70,94}] wire unpause = _unpause_T_3 \| take_pc_mem_wb; // @[RocketCore.scala:307:35, :1164:{94,118}] reg icache_blocked_REG; // @[RocketCore.scala:1183:55] wire _icache_blocked_T = io_imem_resp_valid_0 \| icache_blocked_REG; // @[RocketCore.scala:153:7, :1183:{45,55}] wire icache_blocked = ~_icache_blocked_T; // @[RocketCore.scala:1183:{24,45}] wire _coreMonitorBundle_valid_T_1; // @[RocketCore.scala:1192:52] wire [63:0] _coreMonitorBundle_pc_T_3; // @[package.scala:132:15] wire _coreMonitorBundle_wrenx_T_1; // @[RocketCore.scala:1194:37] wire [4:0] _coreMonitorBundle_rd0src_T; // @[RocketCore.scala:1198:42] wire [4:0] _coreMonitorBundle_rd1src_T; // @[RocketCore.scala:1200:42] wire coreMonitorBundle_excpt; // @[RocketCore.scala:1186:31] wire [2:0] coreMonitorBundle_priv_mode; // @[RocketCore.scala:1186:31] wire [63:0] coreMonitorBundle_hartid; // @[RocketCore.scala:1186:31] wire [31:0] coreMonitorBundle_timer; // @[RocketCore.scala:1186:31] wire coreMonitorBundle_valid; // @[RocketCore.scala:1186:31] wire [63:0] coreMonitorBundle_pc; // @[RocketCore.scala:1186:31] wire coreMonitorBundle_wrenx; // @[RocketCore.scala:1186:31] wire [4:0] coreMonitorBundle_rd0src; // @[RocketCore.scala:1186:31] wire [63:0] coreMonitorBundle_rd0val; // @[RocketCore.scala:1186:31] wire [4:0] coreMonitorBundle_rd1src; // @[RocketCore.scala:1186:31] wire [63:0] coreMonitorBundle_rd1val; // @[RocketCore.scala:1186:31] wire [31:0] coreMonitorBundle_inst; // @[RocketCore.scala:1186:31] wire [63:0] _GEN_71 = {61'h0, io_hartid_0}; // @[RocketCore.scala:153:7, :1190:28] assign coreMonitorBundle_hartid = _GEN_71; // @[RocketCore.scala:1186:31, :1190:28] wire [63:0] xrfWriteBundle_hartid; // @[RocketCore.scala:1249:28] assign xrfWriteBundle_hartid = _GEN_71; // @[RocketCore.scala:1190:28, :1249:28] assign coreMonitorBundle_timer = _coreMonitorBundle_timer_T; // @[RocketCore.scala:1186:31, :1191:41] wire _coreMonitorBundle_valid_T = ~_csr_io_trace_0_exception; // @[RocketCore.scala:341:19, :1192:55] assign _coreMonitorBundle_valid_T_1 = _csr_io_trace_0_valid & _coreMonitorBundle_valid_T; // @[RocketCore.scala:341:19, :1192:{52,55}] assign coreMonitorBundle_valid = _coreMonitorBundle_valid_T_1; // @[RocketCore.scala:1186:31, :1192:52] wire [39:0] _coreMonitorBundle_pc_T; // @[RocketCore.scala:1193:48] wire _coreMonitorBundle_pc_T_1 = _coreMonitorBundle_pc_T[39]; // @[package.scala:132:38] wire [23:0] _coreMonitorBundle_pc_T_2 = {24{_coreMonitorBundle_pc_T_1}}; // @[package.scala:132:{20,38}] assign _coreMonitorBundle_pc_T_3 = {_coreMonitorBundle_pc_T_2, _coreMonitorBundle_pc_T}; // @[package.scala:132:{15,20}] assign coreMonitorBundle_pc = _coreMonitorBundle_pc_T_3; // @[package.scala:132:15] wire _coreMonitorBundle_wrenx_T = ~wb_set_sboard; // @[RocketCore.scala:756:69, :1194:40] assign _coreMonitorBundle_wrenx_T_1 = wb_wen & _coreMonitorBundle_wrenx_T; // @[RocketCore.scala:816:25, :1194:{37,40}] assign coreMonitorBundle_wrenx = _coreMonitorBundle_wrenx_T_1; // @[RocketCore.scala:1186:31, :1194:37] assign _coreMonitorBundle_rd0src_T = wb_reg_inst[19:15]; // @[RocketCore.scala:300:24, :1198:42] assign coreMonitorBundle_rd0src = _coreMonitorBundle_rd0src_T; // @[RocketCore.scala:1186:31, :1198:42] reg [63:0] coreMonitorBundle_rd0val_REG; // @[RocketCore.scala:1199:46] reg [63:0] coreMonitorBundle_rd0val_REG_1; // @[RocketCore.scala:1199:38] assign coreMonitorBundle_rd0val = coreMonitorBundle_rd0val_REG_1; // @[RocketCore.scala:1186:31, :1199:38] assign _coreMonitorBundle_rd1src_T = wb_reg_inst[24:20]; // @[RocketCore.scala:300:24, :1200:42] assign coreMonitorBundle_rd1src = _coreMonitorBundle_rd1src_T; // @[RocketCore.scala:1186:31, :1200:42] reg [63:0] coreMonitorBundle_rd1val_REG; // @[RocketCore.scala:1201:46] reg [63:0] coreMonitorBundle_rd1val_REG_1; // @[RocketCore.scala:1201:38] assign coreMonitorBundle_rd1val = coreMonitorBundle_rd1val_REG_1; // @[RocketCore.scala:1186:31, :1201:38]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_50( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [5:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire [12:0] _GEN_0 = {10'h0, io_in_c_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [2:0] b_first_counter; // @[Edges.scala:229:27] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [5:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35] reg [2:0] c_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [5:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [62:0] inflight; // @[Monitor.scala:614:27] reg [251:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [251:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [63:0] _GEN_1 = {58'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [63:0] _GEN_4 = {58'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [62:0] inflight_1; // @[Monitor.scala:726:35] reg [251:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] c_first_counter_1; // @[Edges.scala:229:27] wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}] wire [63:0] _GEN_6 = {58'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35] wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] reg [6:0] inflight_2; // @[Monitor.scala:828:27] reg [2:0] d_first_counter_3; // @[Edges.scala:229:27] wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35] wire [7:0] _d_set_T = 8'h1 << io_in_d_bits_sink; // @[OneHot.scala:58:35] wire [6:0] d_set = _GEN_8 ? _d_set_T[6:0] : 7'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to the following Chisel files. File RecFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import consts._ class RecFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val in = Input(Bits((inExpWidth + inSigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in); if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- io.out := io.in<<(outSigWidth - inSigWidth) io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W) } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( inExpWidth, inSigWidth, outExpWidth, outSigWidth, flRoundOpt_sigMSBitAlwaysZero )) roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn) roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := rawIn roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } } File rawFloatFromRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ /---------------------------------------------------------------------------- \| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be \| set. ----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }	module RecFNToRecFN_87( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_147( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File MemoryBus.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.{BuiltInDevices, HasBuiltInDeviceParams, BuiltInErrorDeviceParams, BuiltInZeroDeviceParams} import freechips.rocketchip.tilelink.{ ReplicatedRegion, HasTLBusParams, HasRegionReplicatorParams, TLBusWrapper, TLBusWrapperInstantiationLike, RegionReplicator, TLXbar, TLInwardNode, TLOutwardNode, ProbePicker, TLEdge, TLFIFOFixer } import freechips.rocketchip.util.Location /** Parameterization of the memory-side bus created for each memory channel / case class MemoryBusParams( beatBytes: Int, blockBytes: Int, dtsFrequency: Option[BigInt] = None, zeroDevice: Option[BuiltInZeroDeviceParams] = None, errorDevice: Option[BuiltInErrorDeviceParams] = None, replication: Option[ReplicatedRegion] = None) extends HasTLBusParams with HasBuiltInDeviceParams with HasRegionReplicatorParams with TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): MemoryBus = { val mbus = LazyModule(new MemoryBus(this, loc.name)) mbus.suggestName(loc.name) context.tlBusWrapperLocationMap += (loc -> mbus) mbus } } /* Wrapper for creating TL nodes from a bus connected to the back of each mem channel / class MemoryBus(params: MemoryBusParams, name: String = "memory_bus")(implicit p: Parameters) extends TLBusWrapper(params, name)(p) { private val replicator = params.replication.map(r => LazyModule(new RegionReplicator(r))) val prefixNode = replicator.map { r => r.prefix := addressPrefixNexusNode addressPrefixNexusNode } private val xbar = LazyModule(new TLXbar(nameSuffix = Some(name))).suggestName(busName + "_xbar") val inwardNode: TLInwardNode = replicator.map(xbar.node :=* TLFIFOFixer(TLFIFOFixer.all) := _.node) .getOrElse(xbar.node := TLFIFOFixer(TLFIFOFixer.all)) val outwardNode: TLOutwardNode = ProbePicker() := xbar.node def busView: TLEdge = xbar.node.edges.in.head val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode) } File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File ClockGroup.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.prci import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.resources.FixedClockResource case class ClockGroupingNode(groupName: String)(implicit valName: ValName) extends MixedNexusNode(ClockGroupImp, ClockImp)( dFn = { _ => ClockSourceParameters() }, uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq) }) { override def circuitIdentity = outputs.size == 1 } class ClockGroup(groupName: String)(implicit p: Parameters) extends LazyModule { val node = ClockGroupingNode(groupName) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in(0) val (out, _) = node.out.unzip require (node.in.size == 1) require (in.member.size == out.size) (in.member.data zip out) foreach { case (i, o) => o := i } } } object ClockGroup { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroup(valName.name)).node } case class ClockGroupAggregateNode(groupName: String)(implicit valName: ValName) extends NexusNode(ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq.flatMap(_.members))}) { override def circuitIdentity = outputs.size == 1 } class ClockGroupAggregator(groupName: String)(implicit p: Parameters) extends LazyModule { val node = ClockGroupAggregateNode(groupName) override lazy val desiredName = s"ClockGroupAggregator_$groupName" lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in.unzip val (out, _) = node.out.unzip val outputs = out.flatMap(_.member.data) require (node.in.size == 1, s"Aggregator for groupName: ${groupName} had ${node.in.size} inward edges instead of 1") require (in.head.member.size == outputs.size) in.head.member.data.zip(outputs).foreach { case (i, o) => o := i } } } object ClockGroupAggregator { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupAggregator(valName.name)).node } class SimpleClockGroupSource(numSources: Int = 1)(implicit p: Parameters) extends LazyModule { val node = ClockGroupSourceNode(List.fill(numSources) { ClockGroupSourceParameters() }) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val (out, _) = node.out.unzip out.map { out: ClockGroupBundle => out.member.data.foreach { o => o.clock := clock; o.reset := reset } } } } object SimpleClockGroupSource { def apply(num: Int = 1)(implicit p: Parameters, valName: ValName) = LazyModule(new SimpleClockGroupSource(num)).node } case class FixedClockBroadcastNode(fixedClockOpt: Option[ClockParameters])(implicit valName: ValName) extends NexusNode(ClockImp)( dFn = { seq => fixedClockOpt.map(_ => ClockSourceParameters(give = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSourceParameters()) }, uFn = { seq => fixedClockOpt.map(_ => ClockSinkParameters(take = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSinkParameters()) }, inputRequiresOutput = false) { def fixedClockResources(name: String, prefix: String = "soc/"): Seq[Option[FixedClockResource]] = Seq(fixedClockOpt.map(t => new FixedClockResource(name, t.freqMHz, prefix))) } class FixedClockBroadcast(fixedClockOpt: Option[ClockParameters])(implicit p: Parameters) extends LazyModule { val node = new FixedClockBroadcastNode(fixedClockOpt) { override def circuitIdentity = outputs.size == 1 } lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in(0) val (out, _) = node.out.unzip override def desiredName = s"FixedClockBroadcast_${out.size}" require (node.in.size == 1, "FixedClockBroadcast can only broadcast a single clock") out.foreach { _ := in } } } object FixedClockBroadcast { def apply(fixedClockOpt: Option[ClockParameters] = None)(implicit p: Parameters, valName: ValName) = LazyModule(new FixedClockBroadcast(fixedClockOpt)).node } case class PRCIClockGroupNode()(implicit valName: ValName) extends NexusNode(ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, uFn = { _ => ClockGroupSinkParameters("prci", Nil) }, outputRequiresInput = false) File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File ProbePicker.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, IdRange} / A ProbePicker is used to unify multiple cache banks into one logical cache / class ProbePicker(implicit p: Parameters) extends LazyModule { val node = TLAdapterNode( clientFn = { p => // The ProbePicker assembles multiple clients based on the assumption they are contiguous in the clients list // This should be true for custers of xbar := BankBinder connections def combine(next: TLMasterParameters, pair: (TLMasterParameters, Seq[TLMasterParameters])) = { val (head, output) = pair if (head.visibility.exists(x => next.visibility.exists(_.overlaps(x)))) { (next, head +: output) // pair is not banked, push head without merging } else { def redact(x: TLMasterParameters) = x.v1copy(sourceId = IdRange(0,1), nodePath = Nil, visibility = Seq(AddressSet(0, ~0))) require (redact(next) == redact(head), s"${redact(next)} != ${redact(head)}") val merge = head.v1copy( sourceId = IdRange( head.sourceId.start min next.sourceId.start, head.sourceId.end max next.sourceId.end), visibility = AddressSet.unify(head.visibility ++ next.visibility)) (merge, output) } } val myNil: Seq[TLMasterParameters] = Nil val (head, output) = p.clients.init.foldRight((p.clients.last, myNil))(combine) p.v1copy(clients = head +: output) }, managerFn = { p => p }) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out <> in // Based on address, adjust source to route to the correct bank if (edgeIn.client.clients.size != edgeOut.client.clients.size) { in.b.bits.source := Mux1H( edgeOut.client.clients.map(_.sourceId contains out.b.bits.source), edgeOut.client.clients.map { c => val banks = edgeIn.client.clients.filter(c.sourceId contains _.sourceId) if (banks.size == 1) { out.b.bits.source // allow sharing the value between single-bank cases } else { Mux1H( banks.map(_.visibility.map(_ contains out.b.bits.address).reduce(_ \|\| _)), banks.map(_.sourceId.start.U)) } } ) } } } } object ProbePicker { def apply()(implicit p: Parameters): TLNode = { val picker = LazyModule(new ProbePicker) picker.node } } File LazyScope.scala: package org.chipsalliance.diplomacy.lazymodule import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.ValName /** Allows dynamic creation of [[Module]] hierarchy and "shoving" logic into a [[LazyModule]]. / trait LazyScope { this: LazyModule => override def toString: String = s"LazyScope named $name" /* Evaluate `body` in the current [[LazyModule.scope]] / def apply[T](body: => T): T = { // Preserve the previous value of the [[LazyModule.scope]], because when calling [[apply]] function, // [[LazyModule.scope]] will be altered. val saved = LazyModule.scope // [[LazyModule.scope]] stack push. LazyModule.scope = Some(this) // Evaluate [[body]] in the current `scope`, saving the result to [[out]]. val out = body // Check that the `scope` after evaluating `body` is the same as when we started. require(LazyModule.scope.isDefined, s"LazyScope $name tried to exit, but scope was empty!") require( LazyModule.scope.get eq this, s"LazyScope $name exited before LazyModule ${LazyModule.scope.get.name} was closed" ) // [[LazyModule.scope]] stack pop. LazyModule.scope = saved out } } /* Used to automatically create a level of module hierarchy (a [[SimpleLazyModule]]) within which [[LazyModule]]s can * be instantiated and connected. * * It will instantiate a [[SimpleLazyModule]] to manage evaluation of `body` and evaluate `body` code snippets in this * scope. / object LazyScope { /* Create a [[LazyScope]] with an implicit instance name. * * @param body * code executed within the generated [[SimpleLazyModule]]. * @param valName * instance name of generated [[SimpleLazyModule]]. * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. / def apply[T]( body: => T )( implicit valName: ValName, p: Parameters ): T = { apply(valName.value, "SimpleLazyModule", None)(body)(p) } /* Create a [[LazyScope]] with an explicitly defined instance name. * * @param name * instance name of generated [[SimpleLazyModule]]. * @param body * code executed within the generated `SimpleLazyModule` * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. / def apply[T]( name: String )(body: => T )( implicit p: Parameters ): T = { apply(name, "SimpleLazyModule", None)(body)(p) } /* Create a [[LazyScope]] with an explicit instance and class name, and control inlining. * * @param name * instance name of generated [[SimpleLazyModule]]. * @param desiredModuleName * class name of generated [[SimpleLazyModule]]. * @param overrideInlining * tell FIRRTL that this [[SimpleLazyModule]]'s module should be inlined. * @param body * code executed within the generated `SimpleLazyModule` * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. / def apply[T]( name: String, desiredModuleName: String, overrideInlining: Option[Boolean] = None )(body: => T )( implicit p: Parameters ): T = { val scope = LazyModule(new SimpleLazyModule with LazyScope { override lazy val desiredName = desiredModuleName override def shouldBeInlined = overrideInlining.getOrElse(super.shouldBeInlined) }).suggestName(name) scope { body } } /* Create a [[LazyScope]] to temporarily group children for some reason, but tell Firrtl to inline it. * * For example, we might want to control a set of children's clocks but then not keep the parent wrapper. * * @param body * code executed within the generated `SimpleLazyModule` * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. */ def inline[T]( body: => T )( implicit p: Parameters ): T = { apply("noname", "ShouldBeInlined", Some(false))(body)(p) } }	module MemoryBus( // @[ClockDomain.scala:14:9] input auto_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_valid, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_data, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_strb, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_last, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_data, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_resp, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_last, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_1_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_0_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_0_reset, // @[LazyModuleImp.scala:107:25] input auto_mbus_clock_groups_in_member_mbus_0_clock, // @[LazyModuleImp.scala:107:25] input auto_mbus_clock_groups_in_member_mbus_0_reset, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_3_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_3_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_3_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_3_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_bus_xing_in_3_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_bus_xing_in_3_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_3_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_in_3_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_3_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_3_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bus_xing_in_3_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_3_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_bus_xing_in_3_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_3_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_3_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_in_3_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_2_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_2_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_2_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_2_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_bus_xing_in_2_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_bus_xing_in_2_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_2_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_in_2_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_2_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_2_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bus_xing_in_2_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_2_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_bus_xing_in_2_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_2_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_2_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_in_2_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_bus_xing_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_bus_xing_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bus_xing_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_bus_xing_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_bus_xing_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_bus_xing_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bus_xing_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_bus_xing_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _buffer_1_auto_in_a_ready; // @[Buffer.scala:75:28] wire _buffer_1_auto_in_d_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_1_auto_in_d_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_1_auto_in_d_bits_param; // @[Buffer.scala:75:28] wire [2:0] _buffer_1_auto_in_d_bits_size; // @[Buffer.scala:75:28] wire [6:0] _buffer_1_auto_in_d_bits_source; // @[Buffer.scala:75:28] wire _buffer_1_auto_in_d_bits_sink; // @[Buffer.scala:75:28] wire _buffer_1_auto_in_d_bits_denied; // @[Buffer.scala:75:28] wire [63:0] _buffer_1_auto_in_d_bits_data; // @[Buffer.scala:75:28] wire _buffer_1_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28] wire _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_source; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_param; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_source; // @[LazyScope.scala:98:27] wire [31:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_address; // @[LazyScope.scala:98:27] wire [7:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_mask; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_tl_out_d_ready; // @[LazyScope.scala:98:27] wire _picker_auto_in_1_a_ready; // @[ProbePicker.scala:69:28] wire _picker_auto_in_1_d_valid; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_in_1_d_bits_opcode; // @[ProbePicker.scala:69:28] wire [1:0] _picker_auto_in_1_d_bits_param; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_in_1_d_bits_size; // @[ProbePicker.scala:69:28] wire [6:0] _picker_auto_in_1_d_bits_source; // @[ProbePicker.scala:69:28] wire _picker_auto_in_1_d_bits_sink; // @[ProbePicker.scala:69:28] wire _picker_auto_in_1_d_bits_denied; // @[ProbePicker.scala:69:28] wire [63:0] _picker_auto_in_1_d_bits_data; // @[ProbePicker.scala:69:28] wire _picker_auto_in_1_d_bits_corrupt; // @[ProbePicker.scala:69:28] wire _picker_auto_in_0_a_ready; // @[ProbePicker.scala:69:28] wire _picker_auto_in_0_d_valid; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_in_0_d_bits_opcode; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_in_0_d_bits_size; // @[ProbePicker.scala:69:28] wire [6:0] _picker_auto_in_0_d_bits_source; // @[ProbePicker.scala:69:28] wire _picker_auto_in_0_d_bits_denied; // @[ProbePicker.scala:69:28] wire [63:0] _picker_auto_in_0_d_bits_data; // @[ProbePicker.scala:69:28] wire _picker_auto_in_0_d_bits_corrupt; // @[ProbePicker.scala:69:28] wire _picker_auto_out_1_a_valid; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_1_a_bits_opcode; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_1_a_bits_param; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_1_a_bits_size; // @[ProbePicker.scala:69:28] wire [6:0] _picker_auto_out_1_a_bits_source; // @[ProbePicker.scala:69:28] wire [27:0] _picker_auto_out_1_a_bits_address; // @[ProbePicker.scala:69:28] wire [7:0] _picker_auto_out_1_a_bits_mask; // @[ProbePicker.scala:69:28] wire [63:0] _picker_auto_out_1_a_bits_data; // @[ProbePicker.scala:69:28] wire _picker_auto_out_1_a_bits_corrupt; // @[ProbePicker.scala:69:28] wire _picker_auto_out_1_d_ready; // @[ProbePicker.scala:69:28] wire _picker_auto_out_0_a_valid; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_0_a_bits_opcode; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_0_a_bits_param; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_0_a_bits_size; // @[ProbePicker.scala:69:28] wire [6:0] _picker_auto_out_0_a_bits_source; // @[ProbePicker.scala:69:28] wire [31:0] _picker_auto_out_0_a_bits_address; // @[ProbePicker.scala:69:28] wire [7:0] _picker_auto_out_0_a_bits_mask; // @[ProbePicker.scala:69:28] wire [63:0] _picker_auto_out_0_a_bits_data; // @[ProbePicker.scala:69:28] wire _picker_auto_out_0_a_bits_corrupt; // @[ProbePicker.scala:69:28] wire _picker_auto_out_0_d_ready; // @[ProbePicker.scala:69:28] wire _mbus_xbar_auto_anon_out_1_a_valid; // @[MemoryBus.scala:47:32] wire [2:0] _mbus_xbar_auto_anon_out_1_a_bits_opcode; // @[MemoryBus.scala:47:32] wire [2:0] _mbus_xbar_auto_anon_out_1_a_bits_param; // @[MemoryBus.scala:47:32] wire [2:0] _mbus_xbar_auto_anon_out_1_a_bits_size; // @[MemoryBus.scala:47:32] wire [6:0] _mbus_xbar_auto_anon_out_1_a_bits_source; // @[MemoryBus.scala:47:32] wire [27:0] _mbus_xbar_auto_anon_out_1_a_bits_address; // @[MemoryBus.scala:47:32] wire [7:0] _mbus_xbar_auto_anon_out_1_a_bits_mask; // @[MemoryBus.scala:47:32] wire [63:0] _mbus_xbar_auto_anon_out_1_a_bits_data; // @[MemoryBus.scala:47:32] wire _mbus_xbar_auto_anon_out_1_a_bits_corrupt; // @[MemoryBus.scala:47:32] wire _mbus_xbar_auto_anon_out_1_d_ready; // @[MemoryBus.scala:47:32] wire _mbus_xbar_auto_anon_out_0_a_valid; // @[MemoryBus.scala:47:32] wire [2:0] _mbus_xbar_auto_anon_out_0_a_bits_opcode; // @[MemoryBus.scala:47:32] wire [2:0] _mbus_xbar_auto_anon_out_0_a_bits_param; // @[MemoryBus.scala:47:32] wire [2:0] _mbus_xbar_auto_anon_out_0_a_bits_size; // @[MemoryBus.scala:47:32] wire [6:0] _mbus_xbar_auto_anon_out_0_a_bits_source; // @[MemoryBus.scala:47:32] wire [31:0] _mbus_xbar_auto_anon_out_0_a_bits_address; // @[MemoryBus.scala:47:32] wire [7:0] _mbus_xbar_auto_anon_out_0_a_bits_mask; // @[MemoryBus.scala:47:32] wire [63:0] _mbus_xbar_auto_anon_out_0_a_bits_data; // @[MemoryBus.scala:47:32] wire _mbus_xbar_auto_anon_out_0_a_bits_corrupt; // @[MemoryBus.scala:47:32] wire _mbus_xbar_auto_anon_out_0_d_ready; // @[MemoryBus.scala:47:32] wire _fixedClockNode_auto_anon_out_0_clock; // @[ClockGroup.scala:115:114] wire _fixedClockNode_auto_anon_out_0_reset; // @[ClockGroup.scala:115:114] FixedClockBroadcast_3 fixedClockNode ( // @[ClockGroup.scala:115:114] .auto_anon_in_clock (auto_mbus_clock_groups_in_member_mbus_0_clock), .auto_anon_in_reset (auto_mbus_clock_groups_in_member_mbus_0_reset), .auto_anon_out_2_clock (auto_fixedClockNode_anon_out_1_clock), .auto_anon_out_1_clock (auto_fixedClockNode_anon_out_0_clock), .auto_anon_out_1_reset (auto_fixedClockNode_anon_out_0_reset), .auto_anon_out_0_clock (_fixedClockNode_auto_anon_out_0_clock), .auto_anon_out_0_reset (_fixedClockNode_auto_anon_out_0_reset) ); // @[ClockGroup.scala:115:114] TLXbar_mbus_i4_o2_a32d64s7k1z3u mbus_xbar ( // @[MemoryBus.scala:47:32] .clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114] .reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114] .auto_anon_in_3_a_ready (auto_bus_xing_in_3_a_ready), .auto_anon_in_3_a_valid (auto_bus_xing_in_3_a_valid), .auto_anon_in_3_a_bits_opcode (auto_bus_xing_in_3_a_bits_opcode), .auto_anon_in_3_a_bits_param (auto_bus_xing_in_3_a_bits_param), .auto_anon_in_3_a_bits_size (auto_bus_xing_in_3_a_bits_size), .auto_anon_in_3_a_bits_source (auto_bus_xing_in_3_a_bits_source), .auto_anon_in_3_a_bits_address (auto_bus_xing_in_3_a_bits_address), .auto_anon_in_3_a_bits_mask (auto_bus_xing_in_3_a_bits_mask), .auto_anon_in_3_a_bits_data (auto_bus_xing_in_3_a_bits_data), .auto_anon_in_3_a_bits_corrupt (auto_bus_xing_in_3_a_bits_corrupt), .auto_anon_in_3_d_ready (auto_bus_xing_in_3_d_ready), .auto_anon_in_3_d_valid (auto_bus_xing_in_3_d_valid), .auto_anon_in_3_d_bits_opcode (auto_bus_xing_in_3_d_bits_opcode), .auto_anon_in_3_d_bits_param (auto_bus_xing_in_3_d_bits_param), .auto_anon_in_3_d_bits_size (auto_bus_xing_in_3_d_bits_size), .auto_anon_in_3_d_bits_source (auto_bus_xing_in_3_d_bits_source), .auto_anon_in_3_d_bits_sink (auto_bus_xing_in_3_d_bits_sink), .auto_anon_in_3_d_bits_denied (auto_bus_xing_in_3_d_bits_denied), .auto_anon_in_3_d_bits_data (auto_bus_xing_in_3_d_bits_data), .auto_anon_in_3_d_bits_corrupt (auto_bus_xing_in_3_d_bits_corrupt), .auto_anon_in_2_a_ready (auto_bus_xing_in_2_a_ready), .auto_anon_in_2_a_valid (auto_bus_xing_in_2_a_valid), .auto_anon_in_2_a_bits_opcode (auto_bus_xing_in_2_a_bits_opcode), .auto_anon_in_2_a_bits_param (auto_bus_xing_in_2_a_bits_param), .auto_anon_in_2_a_bits_size (auto_bus_xing_in_2_a_bits_size), .auto_anon_in_2_a_bits_source (auto_bus_xing_in_2_a_bits_source), .auto_anon_in_2_a_bits_address (auto_bus_xing_in_2_a_bits_address), .auto_anon_in_2_a_bits_mask (auto_bus_xing_in_2_a_bits_mask), .auto_anon_in_2_a_bits_data (auto_bus_xing_in_2_a_bits_data), .auto_anon_in_2_a_bits_corrupt (auto_bus_xing_in_2_a_bits_corrupt), .auto_anon_in_2_d_ready (auto_bus_xing_in_2_d_ready), .auto_anon_in_2_d_valid (auto_bus_xing_in_2_d_valid), .auto_anon_in_2_d_bits_opcode (auto_bus_xing_in_2_d_bits_opcode), .auto_anon_in_2_d_bits_param (auto_bus_xing_in_2_d_bits_param), .auto_anon_in_2_d_bits_size (auto_bus_xing_in_2_d_bits_size), .auto_anon_in_2_d_bits_source (auto_bus_xing_in_2_d_bits_source), .auto_anon_in_2_d_bits_sink (auto_bus_xing_in_2_d_bits_sink), .auto_anon_in_2_d_bits_denied (auto_bus_xing_in_2_d_bits_denied), .auto_anon_in_2_d_bits_data (auto_bus_xing_in_2_d_bits_data), .auto_anon_in_2_d_bits_corrupt (auto_bus_xing_in_2_d_bits_corrupt), .auto_anon_in_1_a_ready (auto_bus_xing_in_1_a_ready), .auto_anon_in_1_a_valid (auto_bus_xing_in_1_a_valid), .auto_anon_in_1_a_bits_opcode (auto_bus_xing_in_1_a_bits_opcode), .auto_anon_in_1_a_bits_param (auto_bus_xing_in_1_a_bits_param), .auto_anon_in_1_a_bits_size (auto_bus_xing_in_1_a_bits_size), .auto_anon_in_1_a_bits_source (auto_bus_xing_in_1_a_bits_source), .auto_anon_in_1_a_bits_address (auto_bus_xing_in_1_a_bits_address), .auto_anon_in_1_a_bits_mask (auto_bus_xing_in_1_a_bits_mask), .auto_anon_in_1_a_bits_data (auto_bus_xing_in_1_a_bits_data), .auto_anon_in_1_a_bits_corrupt (auto_bus_xing_in_1_a_bits_corrupt), .auto_anon_in_1_d_ready (auto_bus_xing_in_1_d_ready), .auto_anon_in_1_d_valid (auto_bus_xing_in_1_d_valid), .auto_anon_in_1_d_bits_opcode (auto_bus_xing_in_1_d_bits_opcode), .auto_anon_in_1_d_bits_param (auto_bus_xing_in_1_d_bits_param), .auto_anon_in_1_d_bits_size (auto_bus_xing_in_1_d_bits_size), .auto_anon_in_1_d_bits_source (auto_bus_xing_in_1_d_bits_source), .auto_anon_in_1_d_bits_sink (auto_bus_xing_in_1_d_bits_sink), .auto_anon_in_1_d_bits_denied (auto_bus_xing_in_1_d_bits_denied), .auto_anon_in_1_d_bits_data (auto_bus_xing_in_1_d_bits_data), .auto_anon_in_1_d_bits_corrupt (auto_bus_xing_in_1_d_bits_corrupt), .auto_anon_in_0_a_ready (auto_bus_xing_in_0_a_ready), .auto_anon_in_0_a_valid (auto_bus_xing_in_0_a_valid), .auto_anon_in_0_a_bits_opcode (auto_bus_xing_in_0_a_bits_opcode), .auto_anon_in_0_a_bits_param (auto_bus_xing_in_0_a_bits_param), .auto_anon_in_0_a_bits_size (auto_bus_xing_in_0_a_bits_size), .auto_anon_in_0_a_bits_source (auto_bus_xing_in_0_a_bits_source), .auto_anon_in_0_a_bits_address (auto_bus_xing_in_0_a_bits_address), .auto_anon_in_0_a_bits_mask (auto_bus_xing_in_0_a_bits_mask), .auto_anon_in_0_a_bits_data (auto_bus_xing_in_0_a_bits_data), .auto_anon_in_0_a_bits_corrupt (auto_bus_xing_in_0_a_bits_corrupt), .auto_anon_in_0_d_ready (auto_bus_xing_in_0_d_ready), .auto_anon_in_0_d_valid (auto_bus_xing_in_0_d_valid), .auto_anon_in_0_d_bits_opcode (auto_bus_xing_in_0_d_bits_opcode), .auto_anon_in_0_d_bits_param (auto_bus_xing_in_0_d_bits_param), .auto_anon_in_0_d_bits_size (auto_bus_xing_in_0_d_bits_size), .auto_anon_in_0_d_bits_source (auto_bus_xing_in_0_d_bits_source), .auto_anon_in_0_d_bits_sink (auto_bus_xing_in_0_d_bits_sink), .auto_anon_in_0_d_bits_denied (auto_bus_xing_in_0_d_bits_denied), .auto_anon_in_0_d_bits_data (auto_bus_xing_in_0_d_bits_data), .auto_anon_in_0_d_bits_corrupt (auto_bus_xing_in_0_d_bits_corrupt), .auto_anon_out_1_a_ready (_picker_auto_in_1_a_ready), // @[ProbePicker.scala:69:28] .auto_anon_out_1_a_valid (_mbus_xbar_auto_anon_out_1_a_valid), .auto_anon_out_1_a_bits_opcode (_mbus_xbar_auto_anon_out_1_a_bits_opcode), .auto_anon_out_1_a_bits_param (_mbus_xbar_auto_anon_out_1_a_bits_param), .auto_anon_out_1_a_bits_size (_mbus_xbar_auto_anon_out_1_a_bits_size), .auto_anon_out_1_a_bits_source (_mbus_xbar_auto_anon_out_1_a_bits_source), .auto_anon_out_1_a_bits_address (_mbus_xbar_auto_anon_out_1_a_bits_address), .auto_anon_out_1_a_bits_mask (_mbus_xbar_auto_anon_out_1_a_bits_mask), .auto_anon_out_1_a_bits_data (_mbus_xbar_auto_anon_out_1_a_bits_data), .auto_anon_out_1_a_bits_corrupt (_mbus_xbar_auto_anon_out_1_a_bits_corrupt), .auto_anon_out_1_d_ready (_mbus_xbar_auto_anon_out_1_d_ready), .auto_anon_out_1_d_valid (_picker_auto_in_1_d_valid), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_opcode (_picker_auto_in_1_d_bits_opcode), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_param (_picker_auto_in_1_d_bits_param), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_size (_picker_auto_in_1_d_bits_size), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_source (_picker_auto_in_1_d_bits_source), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_sink (_picker_auto_in_1_d_bits_sink), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_denied (_picker_auto_in_1_d_bits_denied), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_data (_picker_auto_in_1_d_bits_data), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_corrupt (_picker_auto_in_1_d_bits_corrupt), // @[ProbePicker.scala:69:28] .auto_anon_out_0_a_ready (_picker_auto_in_0_a_ready), // @[ProbePicker.scala:69:28] .auto_anon_out_0_a_valid (_mbus_xbar_auto_anon_out_0_a_valid), .auto_anon_out_0_a_bits_opcode (_mbus_xbar_auto_anon_out_0_a_bits_opcode), .auto_anon_out_0_a_bits_param (_mbus_xbar_auto_anon_out_0_a_bits_param), .auto_anon_out_0_a_bits_size (_mbus_xbar_auto_anon_out_0_a_bits_size), .auto_anon_out_0_a_bits_source (_mbus_xbar_auto_anon_out_0_a_bits_source), .auto_anon_out_0_a_bits_address (_mbus_xbar_auto_anon_out_0_a_bits_address), .auto_anon_out_0_a_bits_mask (_mbus_xbar_auto_anon_out_0_a_bits_mask), .auto_anon_out_0_a_bits_data (_mbus_xbar_auto_anon_out_0_a_bits_data), .auto_anon_out_0_a_bits_corrupt (_mbus_xbar_auto_anon_out_0_a_bits_corrupt), .auto_anon_out_0_d_ready (_mbus_xbar_auto_anon_out_0_d_ready), .auto_anon_out_0_d_valid (_picker_auto_in_0_d_valid), // @[ProbePicker.scala:69:28] .auto_anon_out_0_d_bits_opcode (_picker_auto_in_0_d_bits_opcode), // @[ProbePicker.scala:69:28] .auto_anon_out_0_d_bits_size (_picker_auto_in_0_d_bits_size), // @[ProbePicker.scala:69:28] .auto_anon_out_0_d_bits_source (_picker_auto_in_0_d_bits_source), // @[ProbePicker.scala:69:28] .auto_anon_out_0_d_bits_denied (_picker_auto_in_0_d_bits_denied), // @[ProbePicker.scala:69:28] .auto_anon_out_0_d_bits_data (_picker_auto_in_0_d_bits_data), // @[ProbePicker.scala:69:28] .auto_anon_out_0_d_bits_corrupt (_picker_auto_in_0_d_bits_corrupt) // @[ProbePicker.scala:69:28] ); // @[MemoryBus.scala:47:32] ProbePicker picker ( // @[ProbePicker.scala:69:28] .clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114] .reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114] .auto_in_1_a_ready (_picker_auto_in_1_a_ready), .auto_in_1_a_valid (_mbus_xbar_auto_anon_out_1_a_valid), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_opcode (_mbus_xbar_auto_anon_out_1_a_bits_opcode), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_param (_mbus_xbar_auto_anon_out_1_a_bits_param), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_size (_mbus_xbar_auto_anon_out_1_a_bits_size), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_source (_mbus_xbar_auto_anon_out_1_a_bits_source), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_address (_mbus_xbar_auto_anon_out_1_a_bits_address), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_mask (_mbus_xbar_auto_anon_out_1_a_bits_mask), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_data (_mbus_xbar_auto_anon_out_1_a_bits_data), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_corrupt (_mbus_xbar_auto_anon_out_1_a_bits_corrupt), // @[MemoryBus.scala:47:32] .auto_in_1_d_ready (_mbus_xbar_auto_anon_out_1_d_ready), // @[MemoryBus.scala:47:32] .auto_in_1_d_valid (_picker_auto_in_1_d_valid), .auto_in_1_d_bits_opcode (_picker_auto_in_1_d_bits_opcode), .auto_in_1_d_bits_param (_picker_auto_in_1_d_bits_param), .auto_in_1_d_bits_size (_picker_auto_in_1_d_bits_size), .auto_in_1_d_bits_source (_picker_auto_in_1_d_bits_source), .auto_in_1_d_bits_sink (_picker_auto_in_1_d_bits_sink), .auto_in_1_d_bits_denied (_picker_auto_in_1_d_bits_denied), .auto_in_1_d_bits_data (_picker_auto_in_1_d_bits_data), .auto_in_1_d_bits_corrupt (_picker_auto_in_1_d_bits_corrupt), .auto_in_0_a_ready (_picker_auto_in_0_a_ready), .auto_in_0_a_valid (_mbus_xbar_auto_anon_out_0_a_valid), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_opcode (_mbus_xbar_auto_anon_out_0_a_bits_opcode), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_param (_mbus_xbar_auto_anon_out_0_a_bits_param), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_size (_mbus_xbar_auto_anon_out_0_a_bits_size), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_source (_mbus_xbar_auto_anon_out_0_a_bits_source), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_address (_mbus_xbar_auto_anon_out_0_a_bits_address), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_mask (_mbus_xbar_auto_anon_out_0_a_bits_mask), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_data (_mbus_xbar_auto_anon_out_0_a_bits_data), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_corrupt (_mbus_xbar_auto_anon_out_0_a_bits_corrupt), // @[MemoryBus.scala:47:32] .auto_in_0_d_ready (_mbus_xbar_auto_anon_out_0_d_ready), // @[MemoryBus.scala:47:32] .auto_in_0_d_valid (_picker_auto_in_0_d_valid), .auto_in_0_d_bits_opcode (_picker_auto_in_0_d_bits_opcode), .auto_in_0_d_bits_size (_picker_auto_in_0_d_bits_size), .auto_in_0_d_bits_source (_picker_auto_in_0_d_bits_source), .auto_in_0_d_bits_denied (_picker_auto_in_0_d_bits_denied), .auto_in_0_d_bits_data (_picker_auto_in_0_d_bits_data), .auto_in_0_d_bits_corrupt (_picker_auto_in_0_d_bits_corrupt), .auto_out_1_a_ready (_buffer_1_auto_in_a_ready), // @[Buffer.scala:75:28] .auto_out_1_a_valid (_picker_auto_out_1_a_valid), .auto_out_1_a_bits_opcode (_picker_auto_out_1_a_bits_opcode), .auto_out_1_a_bits_param (_picker_auto_out_1_a_bits_param), .auto_out_1_a_bits_size (_picker_auto_out_1_a_bits_size), .auto_out_1_a_bits_source (_picker_auto_out_1_a_bits_source), .auto_out_1_a_bits_address (_picker_auto_out_1_a_bits_address), .auto_out_1_a_bits_mask (_picker_auto_out_1_a_bits_mask), .auto_out_1_a_bits_data (_picker_auto_out_1_a_bits_data), .auto_out_1_a_bits_corrupt (_picker_auto_out_1_a_bits_corrupt), .auto_out_1_d_ready (_picker_auto_out_1_d_ready), .auto_out_1_d_valid (_buffer_1_auto_in_d_valid), // @[Buffer.scala:75:28] .auto_out_1_d_bits_opcode (_buffer_1_auto_in_d_bits_opcode), // @[Buffer.scala:75:28] .auto_out_1_d_bits_param (_buffer_1_auto_in_d_bits_param), // @[Buffer.scala:75:28] .auto_out_1_d_bits_size (_buffer_1_auto_in_d_bits_size), // @[Buffer.scala:75:28] .auto_out_1_d_bits_source (_buffer_1_auto_in_d_bits_source), // @[Buffer.scala:75:28] .auto_out_1_d_bits_sink (_buffer_1_auto_in_d_bits_sink), // @[Buffer.scala:75:28] .auto_out_1_d_bits_denied (_buffer_1_auto_in_d_bits_denied), // @[Buffer.scala:75:28] .auto_out_1_d_bits_data (_buffer_1_auto_in_d_bits_data), // @[Buffer.scala:75:28] .auto_out_1_d_bits_corrupt (_buffer_1_auto_in_d_bits_corrupt), // @[Buffer.scala:75:28] .auto_out_0_a_ready (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_out_0_a_valid (_picker_auto_out_0_a_valid), .auto_out_0_a_bits_opcode (_picker_auto_out_0_a_bits_opcode), .auto_out_0_a_bits_param (_picker_auto_out_0_a_bits_param), .auto_out_0_a_bits_size (_picker_auto_out_0_a_bits_size), .auto_out_0_a_bits_source (_picker_auto_out_0_a_bits_source), .auto_out_0_a_bits_address (_picker_auto_out_0_a_bits_address), .auto_out_0_a_bits_mask (_picker_auto_out_0_a_bits_mask), .auto_out_0_a_bits_data (_picker_auto_out_0_a_bits_data), .auto_out_0_a_bits_corrupt (_picker_auto_out_0_a_bits_corrupt), .auto_out_0_d_ready (_picker_auto_out_0_d_ready), .auto_out_0_d_valid (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_out_0_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_out_0_d_bits_size (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_out_0_d_bits_source (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_out_0_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_denied), // @[LazyScope.scala:98:27] .auto_out_0_d_bits_data (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_out_0_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_corrupt) // @[LazyScope.scala:98:27] ); // @[ProbePicker.scala:69:28] TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4 coupler_to_memory_controller_port_named_axi4 ( // @[LazyScope.scala:98:27] .clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114] .reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114] .auto_widget_anon_in_a_ready (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_a_ready), .auto_widget_anon_in_a_valid (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_valid), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_opcode (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_opcode), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_param (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_param), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_size (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_size), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_source (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_source), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_address (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_address), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_mask (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_mask), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_data (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_data), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_corrupt), // @[LazyScope.scala:98:27] .auto_widget_anon_in_d_ready (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_d_ready), // @[LazyScope.scala:98:27] .auto_widget_anon_in_d_valid (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_valid), .auto_widget_anon_in_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_opcode), .auto_widget_anon_in_d_bits_size (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_size), .auto_widget_anon_in_d_bits_source (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_source), .auto_widget_anon_in_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_denied), .auto_widget_anon_in_d_bits_data (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_data), .auto_widget_anon_in_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_corrupt), .auto_axi4yank_out_aw_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready), .auto_axi4yank_out_aw_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid), .auto_axi4yank_out_aw_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id), .auto_axi4yank_out_aw_bits_addr (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr), .auto_axi4yank_out_aw_bits_len (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len), .auto_axi4yank_out_aw_bits_size (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size), .auto_axi4yank_out_aw_bits_burst (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst), .auto_axi4yank_out_aw_bits_lock (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock), .auto_axi4yank_out_aw_bits_cache (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache), .auto_axi4yank_out_aw_bits_prot (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot), .auto_axi4yank_out_aw_bits_qos (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos), .auto_axi4yank_out_w_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_ready), .auto_axi4yank_out_w_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_valid), .auto_axi4yank_out_w_bits_data (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_data), .auto_axi4yank_out_w_bits_strb (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_strb), .auto_axi4yank_out_w_bits_last (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_last), .auto_axi4yank_out_b_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready), .auto_axi4yank_out_b_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_valid), .auto_axi4yank_out_b_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id), .auto_axi4yank_out_b_bits_resp (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp), .auto_axi4yank_out_ar_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready), .auto_axi4yank_out_ar_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid), .auto_axi4yank_out_ar_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id), .auto_axi4yank_out_ar_bits_addr (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr), .auto_axi4yank_out_ar_bits_len (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len), .auto_axi4yank_out_ar_bits_size (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size), .auto_axi4yank_out_ar_bits_burst (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst), .auto_axi4yank_out_ar_bits_lock (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock), .auto_axi4yank_out_ar_bits_cache (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache), .auto_axi4yank_out_ar_bits_prot (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot), .auto_axi4yank_out_ar_bits_qos (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos), .auto_axi4yank_out_r_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_ready), .auto_axi4yank_out_r_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_valid), .auto_axi4yank_out_r_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_id), .auto_axi4yank_out_r_bits_data (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_data), .auto_axi4yank_out_r_bits_resp (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_resp), .auto_axi4yank_out_r_bits_last (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_last), .auto_tl_in_a_ready (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_a_ready), .auto_tl_in_a_valid (_picker_auto_out_0_a_valid), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_opcode (_picker_auto_out_0_a_bits_opcode), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_param (_picker_auto_out_0_a_bits_param), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_size (_picker_auto_out_0_a_bits_size), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_source (_picker_auto_out_0_a_bits_source), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_address (_picker_auto_out_0_a_bits_address), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_mask (_picker_auto_out_0_a_bits_mask), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_data (_picker_auto_out_0_a_bits_data), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_corrupt (_picker_auto_out_0_a_bits_corrupt), // @[ProbePicker.scala:69:28] .auto_tl_in_d_ready (_picker_auto_out_0_d_ready), // @[ProbePicker.scala:69:28] .auto_tl_in_d_valid (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_denied), .auto_tl_in_d_bits_data (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_data), .auto_tl_in_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_corrupt), .auto_tl_out_a_ready (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_a_ready), // @[LazyScope.scala:98:27] .auto_tl_out_a_valid (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_valid), .auto_tl_out_a_bits_opcode (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_opcode), .auto_tl_out_a_bits_param (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_param), .auto_tl_out_a_bits_size (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_size), .auto_tl_out_a_bits_source (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_source), .auto_tl_out_a_bits_address (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_address), .auto_tl_out_a_bits_mask (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_mask), .auto_tl_out_a_bits_data (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_data), .auto_tl_out_a_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_corrupt), .auto_tl_out_d_ready (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_d_ready), .auto_tl_out_d_valid (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_valid), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_size (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_source (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_denied), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_data (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_corrupt) // @[LazyScope.scala:98:27] ); // @[LazyScope.scala:98:27] TLBuffer_a28d64s7k1z3u buffer_1 ( // @[Buffer.scala:75:28] .clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114] .reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114] .auto_in_a_ready (_buffer_1_auto_in_a_ready), .auto_in_a_valid (_picker_auto_out_1_a_valid), // @[ProbePicker.scala:69:28] .auto_in_a_bits_opcode (_picker_auto_out_1_a_bits_opcode), // @[ProbePicker.scala:69:28] .auto_in_a_bits_param (_picker_auto_out_1_a_bits_param), // @[ProbePicker.scala:69:28] .auto_in_a_bits_size (_picker_auto_out_1_a_bits_size), // @[ProbePicker.scala:69:28] .auto_in_a_bits_source (_picker_auto_out_1_a_bits_source), // @[ProbePicker.scala:69:28] .auto_in_a_bits_address (_picker_auto_out_1_a_bits_address), // @[ProbePicker.scala:69:28] .auto_in_a_bits_mask (_picker_auto_out_1_a_bits_mask), // @[ProbePicker.scala:69:28] .auto_in_a_bits_data (_picker_auto_out_1_a_bits_data), // @[ProbePicker.scala:69:28] .auto_in_a_bits_corrupt (_picker_auto_out_1_a_bits_corrupt), // @[ProbePicker.scala:69:28] .auto_in_d_ready (_picker_auto_out_1_d_ready), // @[ProbePicker.scala:69:28] .auto_in_d_valid (_buffer_1_auto_in_d_valid), .auto_in_d_bits_opcode (_buffer_1_auto_in_d_bits_opcode), .auto_in_d_bits_param (_buffer_1_auto_in_d_bits_param), .auto_in_d_bits_size (_buffer_1_auto_in_d_bits_size), .auto_in_d_bits_source (_buffer_1_auto_in_d_bits_source), .auto_in_d_bits_sink (_buffer_1_auto_in_d_bits_sink), .auto_in_d_bits_denied (_buffer_1_auto_in_d_bits_denied), .auto_in_d_bits_data (_buffer_1_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_buffer_1_auto_in_d_bits_corrupt), .auto_out_a_ready (auto_buffer_out_a_ready), .auto_out_a_valid (auto_buffer_out_a_valid), .auto_out_a_bits_opcode (auto_buffer_out_a_bits_opcode), .auto_out_a_bits_param (auto_buffer_out_a_bits_param), .auto_out_a_bits_size (auto_buffer_out_a_bits_size), .auto_out_a_bits_source (auto_buffer_out_a_bits_source), .auto_out_a_bits_address (auto_buffer_out_a_bits_address), .auto_out_a_bits_mask (auto_buffer_out_a_bits_mask), .auto_out_a_bits_data (auto_buffer_out_a_bits_data), .auto_out_a_bits_corrupt (auto_buffer_out_a_bits_corrupt), .auto_out_d_ready (auto_buffer_out_d_ready), .auto_out_d_valid (auto_buffer_out_d_valid), .auto_out_d_bits_opcode (auto_buffer_out_d_bits_opcode), .auto_out_d_bits_param (auto_buffer_out_d_bits_param), .auto_out_d_bits_size (auto_buffer_out_d_bits_size), .auto_out_d_bits_source (auto_buffer_out_d_bits_source), .auto_out_d_bits_sink (auto_buffer_out_d_bits_sink), .auto_out_d_bits_denied (auto_buffer_out_d_bits_denied), .auto_out_d_bits_data (auto_buffer_out_d_bits_data), .auto_out_d_bits_corrupt (auto_buffer_out_d_bits_corrupt) ); // @[Buffer.scala:75:28] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_52( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_64 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 \|\| cParam.destSpeedup > 1 \|\| fullSize <= 1) \|\| !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_\|\|_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) \| (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_\|\|_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow \|\| routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }	module InputUnit_17( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [1:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_5_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_5_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_2, // @[InputUnit.scala:170:14] input io_out_credit_available_5_0, // @[InputUnit.scala:170:14] input io_out_credit_available_4_0, // @[InputUnit.scala:170:14] input io_out_credit_available_3_0, // @[InputUnit.scala:170:14] input io_out_credit_available_3_1, // @[InputUnit.scala:170:14] input io_out_credit_available_3_2, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_1, // @[InputUnit.scala:170:14] input io_out_credit_available_1_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_0, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_5_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [144:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [1:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [1:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [144:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [2:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [2:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire _GEN; // @[MixedVec.scala:116:9] wire _GEN_0; // @[MixedVec.scala:116:9] wire vcalloc_reqs_2_vc_sel_3_2; // @[MixedVec.scala:116:9] wire vcalloc_vals_2; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _GEN_1; // @[MixedVec.scala:116:9] wire _GEN_2; // @[MixedVec.scala:116:9] wire vcalloc_reqs_1_vc_sel_3_1; // @[MixedVec.scala:116:9] wire vcalloc_vals_1; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _GEN_3; // @[MixedVec.scala:116:9] wire _GEN_4; // @[MixedVec.scala:116:9] wire vcalloc_reqs_0_vc_sel_3_0; // @[MixedVec.scala:116:9] wire vcalloc_vals_0; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [2:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [1:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_0_g; // @[InputUnit.scala:192:19] reg states_0_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_3_0; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_1; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_2; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN_5 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:158:7, :192:19, :229:22] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:158:7, :192:19, :229:22] wire _GEN_6 = _route_arbiter_io_in_1_ready & route_arbiter_io_in_1_valid; // @[Decoupled.scala:51:35] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:158:7, :192:19, :229:22] wire _GEN_7 = _route_arbiter_io_in_2_ready & route_arbiter_io_in_2_valid; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to the following Chisel files. File MSHR.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import freechips.rocketchip.tilelink._ import TLPermissions._ import TLMessages._ import MetaData._ import chisel3.PrintableHelper import chisel3.experimental.dataview._ class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val a = Valid(new SourceARequest(params)) val b = Valid(new SourceBRequest(params)) val c = Valid(new SourceCRequest(params)) val d = Valid(new SourceDRequest(params)) val e = Valid(new SourceERequest(params)) val x = Valid(new SourceXRequest(params)) val dir = Valid(new DirectoryWrite(params)) val reload = Bool() // get next request via allocate (if any) } class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val way = UInt(params.wayBits.W) val blockB = Bool() val nestB = Bool() val blockC = Bool() val nestC = Bool() } class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val b_toN = Bool() // nested Probes may unhit us val b_toB = Bool() // nested Probes may demote us val b_clr_dirty = Bool() // nested Probes clear dirty val c_set_dirty = Bool() // nested Releases MAY set dirty } sealed trait CacheState { val code = CacheState.index.U CacheState.index = CacheState.index + 1 } object CacheState { var index = 0 } case object S_INVALID extends CacheState case object S_BRANCH extends CacheState case object S_BRANCH_C extends CacheState case object S_TIP extends CacheState case object S_TIP_C extends CacheState case object S_TIP_CD extends CacheState case object S_TIP_D extends CacheState case object S_TRUNK_C extends CacheState case object S_TRUNK_CD extends CacheState class MSHR(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup val status = Valid(new MSHRStatus(params)) val schedule = Decoupled(new ScheduleRequest(params)) val sinkc = Flipped(Valid(new SinkCResponse(params))) val sinkd = Flipped(Valid(new SinkDResponse(params))) val sinke = Flipped(Valid(new SinkEResponse(params))) val nestedwb = Flipped(new NestedWriteback(params)) }) val request_valid = RegInit(false.B) val request = Reg(new FullRequest(params)) val meta_valid = RegInit(false.B) val meta = Reg(new DirectoryResult(params)) // Define which states are valid when (meta_valid) { when (meta.state === INVALID) { assert (!meta.clients.orR) assert (!meta.dirty) } when (meta.state === BRANCH) { assert (!meta.dirty) } when (meta.state === TRUNK) { assert (meta.clients.orR) assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one } when (meta.state === TIP) { // noop } } // Completed transitions (s_ = scheduled), (w_ = waiting) val s_rprobe = RegInit(true.B) // B val w_rprobeackfirst = RegInit(true.B) val w_rprobeacklast = RegInit(true.B) val s_release = RegInit(true.B) // CW w_rprobeackfirst val w_releaseack = RegInit(true.B) val s_pprobe = RegInit(true.B) // B val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1] val s_flush = RegInit(true.B) // X w_releaseack val w_grantfirst = RegInit(true.B) val w_grantlast = RegInit(true.B) val w_grant = RegInit(true.B) // first \| last depending on wormhole val w_pprobeackfirst = RegInit(true.B) val w_pprobeacklast = RegInit(true.B) val w_pprobeack = RegInit(true.B) // first \| last depending on wormhole val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_) val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD val s_execute = RegInit(true.B) // D w_pprobeack, w_grant val w_grantack = RegInit(true.B) val s_writeback = RegInit(true.B) // W w_* // [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall) // However, inB and outC are higher priority than outB, so s_release and s_pprobe // may be safely issued while blockB. Thus we must NOT try to schedule the // potentially stuck s_acquire with either of them (scheduler is all or none). // Meta-data that we discover underway val sink = Reg(UInt(params.outer.bundle.sinkBits.W)) val gotT = Reg(Bool()) val bad_grant = Reg(Bool()) val probes_done = Reg(UInt(params.clientBits.W)) val probes_toN = Reg(UInt(params.clientBits.W)) val probes_noT = Reg(Bool()) // When a nested transaction completes, update our meta data when (meta_valid && meta.state =/= INVALID && io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) { when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B } when (io.nestedwb.c_set_dirty) { meta.dirty := true.B } when (io.nestedwb.b_toB) { meta.state := BRANCH } when (io.nestedwb.b_toN) { meta.hit := false.B } } // Scheduler status io.status.valid := request_valid io.status.bits.set := request.set io.status.bits.tag := request.tag io.status.bits.way := meta.way io.status.bits.blockB := !meta_valid \|\| ((!w_releaseack \|\| !w_rprobeacklast \|\| !w_pprobeacklast) && !w_grantfirst) io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst // The above rules ensure we will block and not nest an outer probe while still doing our // own inner probes. Thus every probe wakes exactly one MSHR. io.status.bits.blockC := !meta_valid io.status.bits.nestC := meta_valid && (!w_rprobeackfirst \|\| !w_pprobeackfirst \|\| !w_grantfirst) // The w_grantfirst in nestC is necessary to deal with: // acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock // ... this is possible because the release+probe can be for same set, but different tag // We can only demand: block, nest, or queue assert (!io.status.bits.nestB \|\| !io.status.bits.blockB) assert (!io.status.bits.nestC \|\| !io.status.bits.blockC) // Scheduler requests val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe io.schedule.bits.b.valid := !s_rprobe \|\| !s_pprobe io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) \|\| (!s_probeack && w_pprobeackfirst) io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant io.schedule.bits.e.valid := !s_grantack && w_grantfirst io.schedule.bits.x.valid := !s_flush && w_releaseack io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) \|\| (!s_writeback && no_wait) io.schedule.bits.reload := no_wait io.schedule.valid := io.schedule.bits.a.valid \|\| io.schedule.bits.b.valid \|\| io.schedule.bits.c.valid \|\| io.schedule.bits.d.valid \|\| io.schedule.bits.e.valid \|\| io.schedule.bits.x.valid \|\| io.schedule.bits.dir.valid // Schedule completions when (io.schedule.ready) { s_rprobe := true.B when (w_rprobeackfirst) { s_release := true.B } s_pprobe := true.B when (s_release && s_pprobe) { s_acquire := true.B } when (w_releaseack) { s_flush := true.B } when (w_pprobeackfirst) { s_probeack := true.B } when (w_grantfirst) { s_grantack := true.B } when (w_pprobeack && w_grant) { s_execute := true.B } when (no_wait) { s_writeback := true.B } // Await the next operation when (no_wait) { request_valid := false.B meta_valid := false.B } } // Resulting meta-data val final_meta_writeback = WireInit(meta) val req_clientBit = params.clientBit(request.source) val req_needT = needT(request.opcode, request.param) val req_acquire = request.opcode === AcquireBlock \|\| request.opcode === AcquirePerm val meta_no_clients = !meta.clients.orR val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT) when (request.prio(2) && (!params.firstLevel).B) { // always a hit final_meta_writeback.dirty := meta.dirty \|\| request.opcode(0) final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state) final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U) final_meta_writeback.hit := true.B // chained requests are hits } .elsewhen (request.control && params.control.B) { // request.prio(0) when (meta.hit) { final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := meta.clients & ~probes_toN } final_meta_writeback.hit := false.B } .otherwise { final_meta_writeback.dirty := (meta.hit && meta.dirty) \|\| !request.opcode(2) final_meta_writeback.state := Mux(req_needT, Mux(req_acquire, TRUNK, TIP), Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH), MuxLookup(meta.state, 0.U(2.W))(Seq( INVALID -> BRANCH, BRANCH -> BRANCH, TRUNK -> TIP, TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP))))) final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) \| Mux(req_acquire, req_clientBit, 0.U) final_meta_writeback.tag := request.tag final_meta_writeback.hit := true.B } when (bad_grant) { when (meta.hit) { // upgrade failed (B -> T) assert (!meta_valid \|\| meta.state === BRANCH) final_meta_writeback.hit := true.B final_meta_writeback.dirty := false.B final_meta_writeback.state := BRANCH final_meta_writeback.clients := meta.clients & ~probes_toN } .otherwise { // failed N -> (T or B) final_meta_writeback.hit := false.B final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := 0.U } } val invalid = Wire(new DirectoryEntry(params)) invalid.dirty := false.B invalid.state := INVALID invalid.clients := 0.U invalid.tag := 0.U // Just because a client says BtoT, by the time we process the request he may be N. // Therefore, we must consult our own meta-data state to confirm he owns the line still. val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR // The client asking us to act is proof they don't have permissions. val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U) io.schedule.bits.a.bits.tag := request.tag io.schedule.bits.a.bits.set := request.set io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB) io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U \|\| !(request.opcode === PutFullData \|\| request.opcode === AcquirePerm) io.schedule.bits.a.bits.source := 0.U io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB))) io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag) io.schedule.bits.b.bits.set := request.set io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release) io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN) io.schedule.bits.c.bits.source := 0.U io.schedule.bits.c.bits.tag := meta.tag io.schedule.bits.c.bits.set := request.set io.schedule.bits.c.bits.way := meta.way io.schedule.bits.c.bits.dirty := meta.dirty io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param, MuxLookup(request.param, request.param)(Seq( NtoB -> Mux(req_promoteT, NtoT, NtoB), BtoT -> Mux(honour_BtoT, BtoT, NtoT), NtoT -> NtoT))) io.schedule.bits.d.bits.sink := 0.U io.schedule.bits.d.bits.way := meta.way io.schedule.bits.d.bits.bad := bad_grant io.schedule.bits.e.bits.sink := sink io.schedule.bits.x.bits.fail := false.B io.schedule.bits.dir.bits.set := request.set io.schedule.bits.dir.bits.way := meta.way io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback)) // Coverage of state transitions def cacheState(entry: DirectoryEntry, hit: Bool) = { val out = WireDefault(0.U) val c = entry.clients.orR val d = entry.dirty switch (entry.state) { is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) } is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) } is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) } is (INVALID) { out := S_INVALID.code } } when (!hit) { out := S_INVALID.code } out } val p = !params.lastLevel // can be probed val c = !params.firstLevel // can be acquired val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read) val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist val f = params.control // flush control register exists val cfg = (p, c, m, r, f) val b = r \|\| p // can reach branch state (via probe downgrade or read-only device) // The cache must be used for something or we would not be here require(c \|\| m) val evict = cacheState(meta, !meta.hit) val before = cacheState(meta, meta.hit) val after = cacheState(final_meta_writeback, true.B) def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}") } else { assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}") } if (cover && f) { params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}") } else { assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}") } } def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}") } else { assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}") } } when ((!s_release && w_rprobeackfirst) && io.schedule.ready) { eviction(S_BRANCH, b) // MMIO read to read-only device eviction(S_BRANCH_C, b && c) // you need children to become C eviction(S_TIP, true) // MMIO read \|\| clean release can lead to this state eviction(S_TIP_C, c) // needs two clients \|\| client + mmio \|\| downgrading client eviction(S_TIP_CD, c) // needs two clients \|\| client + mmio \|\| downgrading client eviction(S_TIP_D, true) // MMIO write \|\| dirty release lead here eviction(S_TRUNK_C, c) // acquire for write eviction(S_TRUNK_CD, c) // dirty release then reacquire } when ((!s_writeback && no_wait) && io.schedule.ready) { transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches transition(S_INVALID, S_TIP, m) // MMIO read transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_INVALID, S_TIP_D, m) // MMIO write transition(S_INVALID, S_TRUNK_C, c) // acquire transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions) transition(S_BRANCH, S_BRANCH_C, b && c) // acquire transition(S_BRANCH, S_TIP, b && m) // prefetch write transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_TIP_D, b && m) // MMIO write transition(S_BRANCH, S_TRUNK_C, b && c) // acquire transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH_C, S_INVALID, b && c && p) transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional) transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_TIP, S_INVALID, p) transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately transition(S_TIP, S_TRUNK_C, c) // acquire transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately transition(S_TIP_C, S_INVALID, c && p) transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_TIP, c) // probed while MMIO read \|\| clean release (optional) transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_TIP_C, S_TRUNK_C, c) // acquire transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty transition(S_TIP_D, S_INVALID, p) transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared transition(S_TIP_D, S_TIP, p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired transition(S_TIP_D, S_TRUNK_CD, c) // acquire transition(S_TIP_CD, S_INVALID, c && p) transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_CD, S_TIP_D, c) // MMIO write \|\| clean release (optional) transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire transition(S_TIP_CD, S_TRUNK_CD, c) // acquire transition(S_TRUNK_C, S_INVALID, c && p) transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_TIP, c) // MMIO read \|\| clean release (optional) transition(S_TRUNK_C, S_TIP_C, c) // bounce shared transition(S_TRUNK_C, S_TIP_D, c) // dirty release transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce transition(S_TRUNK_CD, S_INVALID, c && p) transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TRUNK_CD, S_TIP_D, c) // dirty release transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire } // Handle response messages val probe_bit = params.clientBit(io.sinkc.bits.source) val last_probe = (probes_done \| probe_bit) === (meta.clients & ~excluded_client) val probe_toN = isToN(io.sinkc.bits.param) if (!params.firstLevel) when (io.sinkc.valid) { params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B") params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B") // Caution: the probe matches us only in set. // We would never allow an outer probe to nest until both w_[rp]probeack complete, so // it is safe to just unguardedly update the probe FSM. probes_done := probes_done \| probe_bit probes_toN := probes_toN \| Mux(probe_toN, probe_bit, 0.U) probes_noT := probes_noT \|\| io.sinkc.bits.param =/= TtoT w_rprobeackfirst := w_rprobeackfirst \|\| last_probe w_rprobeacklast := w_rprobeacklast \|\| (last_probe && io.sinkc.bits.last) w_pprobeackfirst := w_pprobeackfirst \|\| last_probe w_pprobeacklast := w_pprobeacklast \|\| (last_probe && io.sinkc.bits.last) // Allow wormhole routing from sinkC if the first request beat has offset 0 val set_pprobeack = last_probe && (io.sinkc.bits.last \|\| request.offset === 0.U) w_pprobeack := w_pprobeack \|\| set_pprobeack params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data") params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data") // However, meta-data updates need to be done more cautiously when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!! } when (io.sinkd.valid) { when (io.sinkd.bits.opcode === Grant \|\| io.sinkd.bits.opcode === GrantData) { sink := io.sinkd.bits.sink w_grantfirst := true.B w_grantlast := io.sinkd.bits.last // Record if we need to prevent taking ownership bad_grant := io.sinkd.bits.denied // Allow wormhole routing for requests whose first beat has offset 0 w_grant := request.offset === 0.U \|\| io.sinkd.bits.last params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data") params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data") gotT := io.sinkd.bits.param === toT } .elsewhen (io.sinkd.bits.opcode === ReleaseAck) { w_releaseack := true.B } } when (io.sinke.valid) { w_grantack := true.B } // Bootstrap new requests val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits) val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits) val new_request = Mux(io.allocate.valid, allocate_as_full, request) val new_needT = needT(new_request.opcode, new_request.param) val new_clientBit = params.clientBit(new_request.source) val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U) val prior = cacheState(final_meta_writeback, true.B) def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}") } else { assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}") } } when (io.allocate.valid && io.allocate.bits.repeat) { bypass(S_INVALID, f \|\| p) // Can lose permissions (probe/flush) bypass(S_BRANCH, b) // MMIO read to read-only device bypass(S_BRANCH_C, b && c) // you need children to become C bypass(S_TIP, true) // MMIO read \|\| clean release can lead to this state bypass(S_TIP_C, c) // needs two clients \|\| client + mmio \|\| downgrading client bypass(S_TIP_CD, c) // needs two clients \|\| client + mmio \|\| downgrading client bypass(S_TIP_D, true) // MMIO write \|\| dirty release lead here bypass(S_TRUNK_C, c) // acquire for write bypass(S_TRUNK_CD, c) // dirty release then reacquire } when (io.allocate.valid) { assert (!request_valid \|\| (no_wait && io.schedule.fire)) request_valid := true.B request := io.allocate.bits } // Create execution plan when (io.directory.valid \|\| (io.allocate.valid && io.allocate.bits.repeat)) { meta_valid := true.B meta := new_meta probes_done := 0.U probes_toN := 0.U probes_noT := false.B gotT := false.B bad_grant := false.B // These should already be either true or turning true // We clear them here explicitly to simplify the mux tree s_rprobe := true.B w_rprobeackfirst := true.B w_rprobeacklast := true.B s_release := true.B w_releaseack := true.B s_pprobe := true.B s_acquire := true.B s_flush := true.B w_grantfirst := true.B w_grantlast := true.B w_grant := true.B w_pprobeackfirst := true.B w_pprobeacklast := true.B w_pprobeack := true.B s_probeack := true.B s_grantack := true.B s_execute := true.B w_grantack := true.B s_writeback := true.B // For C channel requests (ie: Release[Data]) when (new_request.prio(2) && (!params.firstLevel).B) { s_execute := false.B // Do we need to go dirty? when (new_request.opcode(0) && !new_meta.dirty) { s_writeback := false.B } // Does our state change? when (isToB(new_request.param) && new_meta.state === TRUNK) { s_writeback := false.B } // Do our clients change? when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) { s_writeback := false.B } assert (new_meta.hit) } // For X channel requests (ie: flush) .elsewhen (new_request.control && params.control.B) { // new_request.prio(0) s_flush := false.B // Do we need to actually do something? when (new_meta.hit) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } } // For A channel requests .otherwise { // new_request.prio(0) && !new_request.control s_execute := false.B // Do we need an eviction? when (!new_meta.hit && new_meta.state =/= INVALID) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } // Do we need an acquire? when (!new_meta.hit \|\| (new_meta.state === BRANCH && new_needT)) { s_acquire := false.B w_grantfirst := false.B w_grantlast := false.B w_grant := false.B s_grantack := false.B s_writeback := false.B } // Do we need a probe? when ((!params.firstLevel).B && (new_meta.hit && (new_needT \|\| new_meta.state === TRUNK) && (new_meta.clients & ~new_skipProbe) =/= 0.U)) { s_pprobe := false.B w_pprobeackfirst := false.B w_pprobeacklast := false.B w_pprobeack := false.B s_writeback := false.B } // Do we need a grantack? when (new_request.opcode === AcquireBlock \|\| new_request.opcode === AcquirePerm) { w_grantack := false.B s_writeback := false.B } // Becomes dirty? when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) { s_writeback := false.B } } } } File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relListscache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_\|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x \| 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ \|\| _) (matches, bits.U) } expanded \| Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) \|\| (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) \|\| ((opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm \|\| opcode === TLMessages.Get \|\| (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN \|\| param === TLPermissions.BtoN \|\| param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB \|\| param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle	module MSHR_3( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input [5:0] io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire [5:0] final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire [5:0] io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [5:0] invalid_clients = 6'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire [5:0] _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire [5:0] _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg [5:0] meta_clients; // @[MSHR.scala:100:17] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg [5:0] probes_done; // @[MSHR.scala:150:24] reg [5:0] probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire [5:0] _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire _req_clientBit_T = request_source == 6'h24; // @[Parameters.scala:46:9] wire _req_clientBit_T_1 = request_source == 6'h2E; // @[Parameters.scala:46:9] wire _req_clientBit_T_2 = request_source == 6'h2C; // @[Parameters.scala:46:9] wire _req_clientBit_T_3 = request_source == 6'h2A; // @[Parameters.scala:46:9] wire _req_clientBit_T_4 = request_source == 6'h28; // @[Parameters.scala:46:9] wire _req_clientBit_T_5 = request_source == 6'h20; // @[Parameters.scala:46:9] wire [1:0] req_clientBit_lo_hi = {_req_clientBit_T_2, _req_clientBit_T_1}; // @[Parameters.scala:46:9] wire [2:0] req_clientBit_lo = {req_clientBit_lo_hi, _req_clientBit_T}; // @[Parameters.scala:46:9] wire [1:0] req_clientBit_hi_hi = {_req_clientBit_T_5, _req_clientBit_T_4}; // @[Parameters.scala:46:9] wire [2:0] req_clientBit_hi = {req_clientBit_hi_hi, _req_clientBit_T_3}; // @[Parameters.scala:46:9] wire [5:0] req_clientBit = {req_clientBit_hi, req_clientBit_lo}; // @[Parameters.scala:201:10] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire _meta_no_clients_T = \|meta_clients; // @[MSHR.scala:100:17, :220:39] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire [5:0] _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 ? req_clientBit : 6'h0; // @[Parameters.scala:201:10, :282:66] wire [5:0] _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire [5:0] _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire [5:0] _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire [5:0] _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire [5:0] _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire [5:0] _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire [5:0] _final_meta_writeback_clients_T_12 = meta_hit ? _final_meta_writeback_clients_T_11 : 6'h0; // @[MSHR.scala:100:17, :245:{40,64}] wire [5:0] _final_meta_writeback_clients_T_13 = req_acquire ? req_clientBit : 6'h0; // @[Parameters.scala:201:10] wire [5:0] _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire [5:0] _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire [5:0] _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? (meta_hit ? _final_meta_writeback_clients_T_16 : 6'h0) : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire [5:0] _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:201:10] wire _honour_BtoT_T_1 = \|_honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire [5:0] excluded_client = _excluded_client_T_9 ? req_clientBit : 6'h0; // @[Parameters.scala:201:10] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire [5:0] _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = _io_schedule_bits_dir_bits_data_T ? 6'h0 : _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire evict_c = \|meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire before_c = \|meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire after_c = \|final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _probe_bit_T = io_sinkc_bits_source_0 == 6'h24; // @[Parameters.scala:46:9] wire _probe_bit_T_1 = io_sinkc_bits_source_0 == 6'h2E; // @[Parameters.scala:46:9] wire _probe_bit_T_2 = io_sinkc_bits_source_0 == 6'h2C; // @[Parameters.scala:46:9] wire _probe_bit_T_3 = io_sinkc_bits_source_0 == 6'h2A; // @[Parameters.scala:46:9] wire _probe_bit_T_4 = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9] wire _probe_bit_T_5 = io_sinkc_bits_source_0 == 6'h20; // @[Parameters.scala:46:9] wire [1:0] probe_bit_lo_hi = {_probe_bit_T_2, _probe_bit_T_1}; // @[Parameters.scala:46:9] wire [2:0] probe_bit_lo = {probe_bit_lo_hi, _probe_bit_T}; // @[Parameters.scala:46:9] wire [1:0] probe_bit_hi_hi = {_probe_bit_T_5, _probe_bit_T_4}; // @[Parameters.scala:46:9] wire [2:0] probe_bit_hi = {probe_bit_hi_hi, _probe_bit_T_3}; // @[Parameters.scala:46:9] wire [5:0] probe_bit = {probe_bit_hi, probe_bit_lo}; // @[Parameters.scala:201:10] wire [5:0] _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:201:10] wire [5:0] _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire [5:0] _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire [5:0] _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire [5:0] _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire [5:0] _probes_toN_T = probe_toN ? probe_bit : 6'h0; // @[Parameters.scala:201:10, :282:66] wire [5:0] _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [5:0] new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _new_clientBit_T = new_request_source == 6'h24; // @[Parameters.scala:46:9] wire _new_clientBit_T_1 = new_request_source == 6'h2E; // @[Parameters.scala:46:9] wire _new_clientBit_T_2 = new_request_source == 6'h2C; // @[Parameters.scala:46:9] wire _new_clientBit_T_3 = new_request_source == 6'h2A; // @[Parameters.scala:46:9] wire _new_clientBit_T_4 = new_request_source == 6'h28; // @[Parameters.scala:46:9] wire _new_clientBit_T_5 = new_request_source == 6'h20; // @[Parameters.scala:46:9] wire [1:0] new_clientBit_lo_hi = {_new_clientBit_T_2, _new_clientBit_T_1}; // @[Parameters.scala:46:9] wire [2:0] new_clientBit_lo = {new_clientBit_lo_hi, _new_clientBit_T}; // @[Parameters.scala:46:9] wire [1:0] new_clientBit_hi_hi = {_new_clientBit_T_5, _new_clientBit_T_4}; // @[Parameters.scala:46:9] wire [2:0] new_clientBit_hi = {new_clientBit_hi_hi, _new_clientBit_T_3}; // @[Parameters.scala:46:9] wire [5:0] new_clientBit = {new_clientBit_hi, new_clientBit_lo}; // @[Parameters.scala:201:10] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire [5:0] new_skipProbe = _new_skipProbe_T_7 ? new_clientBit : 6'h0; // @[Parameters.scala:201:10, :279:106] wire [3:0] prior; // @[MSHR.scala:314:26] wire prior_c = \|final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]

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Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File PMP.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Cat, log2Ceil} import org.chipsalliance.cde.config._ import freechips.rocketchip.tile._ import freechips.rocketchip.util._ class PMPConfig extends Bundle { val l = Bool() val res = UInt(2.W) val a = UInt(2.W) val x = Bool() val w = Bool() val r = Bool() } object PMP { def lgAlign = 2 def apply(reg: PMPReg): PMP = { val pmp = Wire(new PMP()(reg.p)) pmp.cfg := reg.cfg pmp.addr := reg.addr pmp.mask := pmp.computeMask pmp } } class PMPReg(implicit p: Parameters) extends CoreBundle()(p) { val cfg = new PMPConfig val addr = UInt((paddrBits - PMP.lgAlign).W) def reset(): Unit = { cfg.a := 0.U cfg.l := 0.U } def readAddr = if (pmpGranularity.log2 == PMP.lgAlign) addr else { val mask = ((BigInt(1) << (pmpGranularity.log2 - PMP.lgAlign)) - 1).U Mux(napot, addr \| (mask >> 1), ~(~addr \| mask)) } def napot = cfg.a(1) def torNotNAPOT = cfg.a(0) def tor = !napot && torNotNAPOT def cfgLocked = cfg.l def addrLocked(next: PMPReg) = cfgLocked \|\| next.cfgLocked && next.tor } class PMP(implicit p: Parameters) extends PMPReg { val mask = UInt(paddrBits.W) import PMP._ def computeMask = { val base = Cat(addr, cfg.a(0)) \| ((pmpGranularity - 1).U >> lgAlign) Cat(base & ~(base + 1.U), ((1 << lgAlign) - 1).U) } private def comparand = ~(~(addr << lgAlign) \| (pmpGranularity - 1).U) private def pow2Match(x: UInt, lgSize: UInt, lgMaxSize: Int) = { def eval(a: UInt, b: UInt, m: UInt) = ((a ^ b) & ~m) === 0.U if (lgMaxSize <= pmpGranularity.log2) { eval(x, comparand, mask) } else { // break up the circuit; the MSB part will be CSE'd val lsbMask = mask \| UIntToOH1(lgSize, lgMaxSize) val msbMatch = eval(x >> lgMaxSize, comparand >> lgMaxSize, mask >> lgMaxSize) val lsbMatch = eval(x(lgMaxSize-1, 0), comparand(lgMaxSize-1, 0), lsbMask(lgMaxSize-1, 0)) msbMatch && lsbMatch } } private def boundMatch(x: UInt, lsbMask: UInt, lgMaxSize: Int) = { if (lgMaxSize <= pmpGranularity.log2) { x < comparand } else { // break up the circuit; the MSB part will be CSE'd val msbsLess = (x >> lgMaxSize) < (comparand >> lgMaxSize) val msbsEqual = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U val lsbsLess = (x(lgMaxSize-1, 0) \| lsbMask) < comparand(lgMaxSize-1, 0) msbsLess \|\| (msbsEqual && lsbsLess) } } private def lowerBoundMatch(x: UInt, lgSize: UInt, lgMaxSize: Int) = !boundMatch(x, UIntToOH1(lgSize, lgMaxSize), lgMaxSize) private def upperBoundMatch(x: UInt, lgMaxSize: Int) = boundMatch(x, 0.U, lgMaxSize) private def rangeMatch(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP) = prev.lowerBoundMatch(x, lgSize, lgMaxSize) && upperBoundMatch(x, lgMaxSize) private def pow2Homogeneous(x: UInt, pgLevel: UInt) = { val maskHomogeneous = pgLevelMap { idxBits => if (idxBits > paddrBits) false.B else mask(idxBits - 1) } (pgLevel) maskHomogeneous \|\| (pgLevelMap { idxBits => ((x ^ comparand) >> idxBits) =/= 0.U } (pgLevel)) } private def pgLevelMap[T](f: Int => T) = (0 until pgLevels).map { i => f(pgIdxBits + (pgLevels - 1 - i) pgLevelBits) } private def rangeHomogeneous(x: UInt, pgLevel: UInt, prev: PMP) = { val beginsAfterLower = !(x < prev.comparand) val beginsAfterUpper = !(x < comparand) val pgMask = pgLevelMap { idxBits => (((BigInt(1) << paddrBits) - (BigInt(1) << idxBits)) max 0).U } (pgLevel) val endsBeforeLower = (x & pgMask) < (prev.comparand & pgMask) val endsBeforeUpper = (x & pgMask) < (comparand & pgMask) endsBeforeLower \|\| beginsAfterUpper \|\| (beginsAfterLower && endsBeforeUpper) } // returns whether this PMP completely contains, or contains none of, a page def homogeneous(x: UInt, pgLevel: UInt, prev: PMP): Bool = Mux(napot, pow2Homogeneous(x, pgLevel), !torNotNAPOT \|\| rangeHomogeneous(x, pgLevel, prev)) // returns whether this matching PMP fully contains the access def aligned(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = if (lgMaxSize <= pmpGranularity.log2) true.B else { val lsbMask = UIntToOH1(lgSize, lgMaxSize) val straddlesLowerBound = ((x >> lgMaxSize) ^ (prev.comparand >> lgMaxSize)) === 0.U && (prev.comparand(lgMaxSize-1, 0) & ~x(lgMaxSize-1, 0)) =/= 0.U val straddlesUpperBound = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U && (comparand(lgMaxSize-1, 0) & (x(lgMaxSize-1, 0) \| lsbMask)) =/= 0.U val rangeAligned = !(straddlesLowerBound \|\| straddlesUpperBound) val pow2Aligned = (lsbMask & ~mask(lgMaxSize-1, 0)) === 0.U Mux(napot, pow2Aligned, rangeAligned) } // returns whether this PMP matches at least one byte of the access def hit(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = Mux(napot, pow2Match(x, lgSize, lgMaxSize), torNotNAPOT && rangeMatch(x, lgSize, lgMaxSize, prev)) } class PMPHomogeneityChecker(pmps: Seq[PMP])(implicit p: Parameters) { def apply(addr: UInt, pgLevel: UInt): Bool = { pmps.foldLeft((true.B, 0.U.asTypeOf(new PMP))) { case ((h, prev), pmp) => (h && pmp.homogeneous(addr, pgLevel, prev), pmp) }._1 } } class PMPChecker(lgMaxSize: Int)(implicit val p: Parameters) extends Module with HasCoreParameters { override def desiredName = s"PMPChecker_s${lgMaxSize}" val io = IO(new Bundle { val prv = Input(UInt(PRV.SZ.W)) val pmp = Input(Vec(nPMPs, new PMP)) val addr = Input(UInt(paddrBits.W)) val size = Input(UInt(log2Ceil(lgMaxSize + 1).W)) val r = Output(Bool()) val w = Output(Bool()) val x = Output(Bool()) }) val default = if (io.pmp.isEmpty) true.B else io.prv > PRV.S.U val pmp0 = WireInit(0.U.asTypeOf(new PMP)) pmp0.cfg.r := default pmp0.cfg.w := default pmp0.cfg.x := default val res = (io.pmp zip (pmp0 +: io.pmp)).reverse.foldLeft(pmp0) { case (prev, (pmp, prevPMP)) => val hit = pmp.hit(io.addr, io.size, lgMaxSize, prevPMP) val ignore = default && !pmp.cfg.l val aligned = pmp.aligned(io.addr, io.size, lgMaxSize, prevPMP) for ((name, idx) <- Seq("no", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) property.cover(pmp.cfg.a === idx.U, s"The cfg access is set to ${name} access ", "Cover PMP access mode setting") property.cover(pmp.cfg.l === 0x1.U, s"The cfg lock is set to high ", "Cover PMP lock mode setting") // Not including Write and no Read permission as the combination is reserved for ((name, idx) <- Seq("no", "RO", "", "RW", "X", "RX", "", "RWX").zipWithIndex; if name.nonEmpty) property.cover((Cat(pmp.cfg.x, pmp.cfg.w, pmp.cfg.r) === idx.U), s"The permission is set to ${name} access ", "Cover PMP access permission setting") for ((name, idx) <- Seq("", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) { property.cover(!ignore && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode ", "Cover PMP access") property.cover(pmp.cfg.l && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode with lock bit high", "Cover PMP access with lock bit") } val cur = WireInit(pmp) cur.cfg.r := aligned && (pmp.cfg.r \|\| ignore) cur.cfg.w := aligned && (pmp.cfg.w \|\| ignore) cur.cfg.x := aligned && (pmp.cfg.x \|\| ignore) Mux(hit, cur, prev) } io.r := res.cfg.r io.w := res.cfg.w io.x := res.cfg.x }	module PMPChecker_s2_7( // @[PMP.scala:143:7] input clock, // @[PMP.scala:143:7] input reset, // @[PMP.scala:143:7] input [1:0] io_prv, // @[PMP.scala:146:14] input io_pmp_0_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_0_cfg_a, // @[PMP.scala:146:14] input io_pmp_0_cfg_x, // @[PMP.scala:146:14] input io_pmp_0_cfg_w, // @[PMP.scala:146:14] input io_pmp_0_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_0_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_0_mask, // @[PMP.scala:146:14] input io_pmp_1_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_1_cfg_a, // @[PMP.scala:146:14] input io_pmp_1_cfg_x, // @[PMP.scala:146:14] input io_pmp_1_cfg_w, // @[PMP.scala:146:14] input io_pmp_1_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_1_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_1_mask, // @[PMP.scala:146:14] input io_pmp_2_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_2_cfg_a, // @[PMP.scala:146:14] input io_pmp_2_cfg_x, // @[PMP.scala:146:14] input io_pmp_2_cfg_w, // @[PMP.scala:146:14] input io_pmp_2_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_2_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_2_mask, // @[PMP.scala:146:14] input io_pmp_3_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_3_cfg_a, // @[PMP.scala:146:14] input io_pmp_3_cfg_x, // @[PMP.scala:146:14] input io_pmp_3_cfg_w, // @[PMP.scala:146:14] input io_pmp_3_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_3_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_3_mask, // @[PMP.scala:146:14] input io_pmp_4_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_4_cfg_a, // @[PMP.scala:146:14] input io_pmp_4_cfg_x, // @[PMP.scala:146:14] input io_pmp_4_cfg_w, // @[PMP.scala:146:14] input io_pmp_4_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_4_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_4_mask, // @[PMP.scala:146:14] input io_pmp_5_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_5_cfg_a, // @[PMP.scala:146:14] input io_pmp_5_cfg_x, // @[PMP.scala:146:14] input io_pmp_5_cfg_w, // @[PMP.scala:146:14] input io_pmp_5_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_5_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_5_mask, // @[PMP.scala:146:14] input io_pmp_6_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_6_cfg_a, // @[PMP.scala:146:14] input io_pmp_6_cfg_x, // @[PMP.scala:146:14] input io_pmp_6_cfg_w, // @[PMP.scala:146:14] input io_pmp_6_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_6_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_6_mask, // @[PMP.scala:146:14] input io_pmp_7_cfg_l, // @[PMP.scala:146:14] input [1:0] io_pmp_7_cfg_a, // @[PMP.scala:146:14] input io_pmp_7_cfg_x, // @[PMP.scala:146:14] input io_pmp_7_cfg_w, // @[PMP.scala:146:14] input io_pmp_7_cfg_r, // @[PMP.scala:146:14] input [29:0] io_pmp_7_addr, // @[PMP.scala:146:14] input [31:0] io_pmp_7_mask, // @[PMP.scala:146:14] input [31:0] io_addr, // @[PMP.scala:146:14] output io_r, // @[PMP.scala:146:14] output io_w, // @[PMP.scala:146:14] output io_x // @[PMP.scala:146:14] ); wire [1:0] io_prv_0 = io_prv; // @[PMP.scala:143:7] wire io_pmp_0_cfg_l_0 = io_pmp_0_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_0_cfg_a_0 = io_pmp_0_cfg_a; // @[PMP.scala:143:7] wire io_pmp_0_cfg_x_0 = io_pmp_0_cfg_x; // @[PMP.scala:143:7] wire io_pmp_0_cfg_w_0 = io_pmp_0_cfg_w; // @[PMP.scala:143:7] wire io_pmp_0_cfg_r_0 = io_pmp_0_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_0_addr_0 = io_pmp_0_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_0_mask_0 = io_pmp_0_mask; // @[PMP.scala:143:7] wire io_pmp_1_cfg_l_0 = io_pmp_1_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_1_cfg_a_0 = io_pmp_1_cfg_a; // @[PMP.scala:143:7] wire io_pmp_1_cfg_x_0 = io_pmp_1_cfg_x; // @[PMP.scala:143:7] wire io_pmp_1_cfg_w_0 = io_pmp_1_cfg_w; // @[PMP.scala:143:7] wire io_pmp_1_cfg_r_0 = io_pmp_1_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_1_addr_0 = io_pmp_1_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_1_mask_0 = io_pmp_1_mask; // @[PMP.scala:143:7] wire io_pmp_2_cfg_l_0 = io_pmp_2_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_2_cfg_a_0 = io_pmp_2_cfg_a; // @[PMP.scala:143:7] wire io_pmp_2_cfg_x_0 = io_pmp_2_cfg_x; // @[PMP.scala:143:7] wire io_pmp_2_cfg_w_0 = io_pmp_2_cfg_w; // @[PMP.scala:143:7] wire io_pmp_2_cfg_r_0 = io_pmp_2_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_2_addr_0 = io_pmp_2_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_2_mask_0 = io_pmp_2_mask; // @[PMP.scala:143:7] wire io_pmp_3_cfg_l_0 = io_pmp_3_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_3_cfg_a_0 = io_pmp_3_cfg_a; // @[PMP.scala:143:7] wire io_pmp_3_cfg_x_0 = io_pmp_3_cfg_x; // @[PMP.scala:143:7] wire io_pmp_3_cfg_w_0 = io_pmp_3_cfg_w; // @[PMP.scala:143:7] wire io_pmp_3_cfg_r_0 = io_pmp_3_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_3_addr_0 = io_pmp_3_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_3_mask_0 = io_pmp_3_mask; // @[PMP.scala:143:7] wire io_pmp_4_cfg_l_0 = io_pmp_4_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_4_cfg_a_0 = io_pmp_4_cfg_a; // @[PMP.scala:143:7] wire io_pmp_4_cfg_x_0 = io_pmp_4_cfg_x; // @[PMP.scala:143:7] wire io_pmp_4_cfg_w_0 = io_pmp_4_cfg_w; // @[PMP.scala:143:7] wire io_pmp_4_cfg_r_0 = io_pmp_4_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_4_addr_0 = io_pmp_4_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_4_mask_0 = io_pmp_4_mask; // @[PMP.scala:143:7] wire io_pmp_5_cfg_l_0 = io_pmp_5_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_5_cfg_a_0 = io_pmp_5_cfg_a; // @[PMP.scala:143:7] wire io_pmp_5_cfg_x_0 = io_pmp_5_cfg_x; // @[PMP.scala:143:7] wire io_pmp_5_cfg_w_0 = io_pmp_5_cfg_w; // @[PMP.scala:143:7] wire io_pmp_5_cfg_r_0 = io_pmp_5_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_5_addr_0 = io_pmp_5_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_5_mask_0 = io_pmp_5_mask; // @[PMP.scala:143:7] wire io_pmp_6_cfg_l_0 = io_pmp_6_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_6_cfg_a_0 = io_pmp_6_cfg_a; // @[PMP.scala:143:7] wire io_pmp_6_cfg_x_0 = io_pmp_6_cfg_x; // @[PMP.scala:143:7] wire io_pmp_6_cfg_w_0 = io_pmp_6_cfg_w; // @[PMP.scala:143:7] wire io_pmp_6_cfg_r_0 = io_pmp_6_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_6_addr_0 = io_pmp_6_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_6_mask_0 = io_pmp_6_mask; // @[PMP.scala:143:7] wire io_pmp_7_cfg_l_0 = io_pmp_7_cfg_l; // @[PMP.scala:143:7] wire [1:0] io_pmp_7_cfg_a_0 = io_pmp_7_cfg_a; // @[PMP.scala:143:7] wire io_pmp_7_cfg_x_0 = io_pmp_7_cfg_x; // @[PMP.scala:143:7] wire io_pmp_7_cfg_w_0 = io_pmp_7_cfg_w; // @[PMP.scala:143:7] wire io_pmp_7_cfg_r_0 = io_pmp_7_cfg_r; // @[PMP.scala:143:7] wire [29:0] io_pmp_7_addr_0 = io_pmp_7_addr; // @[PMP.scala:143:7] wire [31:0] io_pmp_7_mask_0 = io_pmp_7_mask; // @[PMP.scala:143:7] wire [31:0] io_addr_0 = io_addr; // @[PMP.scala:143:7] wire [29:0] _pmp0_WIRE_addr = 30'h0; // @[PMP.scala:157:35] wire [29:0] pmp0_addr = 30'h0; // @[PMP.scala:157:22] wire [4:0] _res_hit_T_10 = 5'hC; // @[package.scala:243:71] wire [4:0] _res_hit_T_36 = 5'hC; // @[package.scala:243:71] wire [4:0] _res_hit_T_62 = 5'hC; // @[package.scala:243:71] wire [4:0] _res_hit_T_88 = 5'hC; // @[package.scala:243:71] wire [4:0] _res_hit_T_114 = 5'hC; // @[package.scala:243:71] wire [4:0] _res_hit_T_140 = 5'hC; // @[package.scala:243:71] wire [4:0] _res_hit_T_166 = 5'hC; // @[package.scala:243:71] wire [4:0] _res_hit_T_192 = 5'hC; // @[package.scala:243:71] wire [1:0] _res_hit_T_12 = 2'h3; // @[package.scala:243:46] wire [1:0] _res_hit_T_38 = 2'h3; // @[package.scala:243:46] wire [1:0] _res_hit_T_64 = 2'h3; // @[package.scala:243:46] wire [1:0] _res_hit_T_90 = 2'h3; // @[package.scala:243:46] wire [1:0] _res_hit_T_116 = 2'h3; // @[package.scala:243:46] wire [1:0] _res_hit_T_142 = 2'h3; // @[package.scala:243:46] wire [1:0] _res_hit_T_168 = 2'h3; // @[package.scala:243:46] wire [1:0] _res_hit_T_194 = 2'h3; // @[package.scala:243:46] wire [31:0] _res_hit_T_196 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_197 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _pmp0_WIRE_mask = 32'h0; // @[PMP.scala:157:35] wire [31:0] pmp0_mask = 32'h0; // @[PMP.scala:157:22] wire [31:0] _res_hit_T_195 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_198 = 32'h0; // @[PMP.scala:60:27] wire _pmp0_WIRE_cfg_l = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_x = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_w = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_r = 1'h0; // @[PMP.scala:157:35] wire pmp0_cfg_l = 1'h0; // @[PMP.scala:157:22] wire _res_hit_T_199 = 1'h0; // @[PMP.scala:77:9] wire _res_hit_T_200 = 1'h1; // @[PMP.scala:88:5] wire [1:0] io_size = 2'h2; // @[PMP.scala:143:7] wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] _pmp0_WIRE_cfg_res = 2'h0; // @[PMP.scala:157:35] wire [1:0] _pmp0_WIRE_cfg_a = 2'h0; // @[PMP.scala:157:35] wire [1:0] pmp0_cfg_res = 2'h0; // @[PMP.scala:157:22] wire [1:0] pmp0_cfg_a = 2'h0; // @[PMP.scala:157:22] wire [1:0] _res_hit_T_11 = 2'h0; // @[package.scala:243:76] wire [1:0] res_cur_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_44_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] _res_hit_T_37 = 2'h0; // @[package.scala:243:76] wire [1:0] res_cur_1_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_89_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] _res_hit_T_63 = 2'h0; // @[package.scala:243:76] wire [1:0] res_cur_2_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_134_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] _res_hit_T_89 = 2'h0; // @[package.scala:243:76] wire [1:0] res_cur_3_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_179_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] _res_hit_T_115 = 2'h0; // @[package.scala:243:76] wire [1:0] res_cur_4_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_224_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] _res_hit_T_141 = 2'h0; // @[package.scala:243:76] wire [1:0] res_cur_5_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_269_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] _res_hit_T_167 = 2'h0; // @[package.scala:243:76] wire [1:0] res_cur_6_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_314_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] _res_hit_T_193 = 2'h0; // @[package.scala:243:76] wire [1:0] res_cur_7_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] res_cfg_res = 2'h0; // @[PMP.scala:185:8] wire _res_T_319 = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_7_cfg_l = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_7_cfg_a = io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_7_addr = io_pmp_0_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_7_mask = io_pmp_0_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_274 = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_6_cfg_l = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_6_cfg_a = io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_6_addr = io_pmp_1_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_6_mask = io_pmp_1_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_229 = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_5_cfg_l = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_5_cfg_a = io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_5_addr = io_pmp_2_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_5_mask = io_pmp_2_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_184 = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_4_cfg_l = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_4_cfg_a = io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_4_addr = io_pmp_3_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_4_mask = io_pmp_3_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_139 = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_3_cfg_l = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_3_cfg_a = io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_3_addr = io_pmp_4_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_3_mask = io_pmp_4_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_94 = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_2_cfg_l = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_2_cfg_a = io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_2_addr = io_pmp_5_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_2_mask = io_pmp_5_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_49 = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_1_cfg_l = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_1_cfg_a = io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_1_addr = io_pmp_6_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_1_mask = io_pmp_6_mask_0; // @[PMP.scala:143:7, :181:23] wire _res_T_4 = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :170:30] wire res_cur_cfg_l = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :181:23] wire [1:0] res_cur_cfg_a = io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :181:23] wire [29:0] res_cur_addr = io_pmp_7_addr_0; // @[PMP.scala:143:7, :181:23] wire [31:0] res_cur_mask = io_pmp_7_mask_0; // @[PMP.scala:143:7, :181:23] wire res_cfg_r; // @[PMP.scala:185:8] wire res_cfg_w; // @[PMP.scala:185:8] wire res_cfg_x; // @[PMP.scala:185:8] wire io_r_0; // @[PMP.scala:143:7] wire io_w_0; // @[PMP.scala:143:7] wire io_x_0; // @[PMP.scala:143:7] wire default_0 = io_prv_0[1]; // @[PMP.scala:143:7, :156:56] wire pmp0_cfg_x = default_0; // @[PMP.scala:156:56, :157:22] wire pmp0_cfg_w = default_0; // @[PMP.scala:156:56, :157:22] wire pmp0_cfg_r = default_0; // @[PMP.scala:156:56, :157:22] wire _res_hit_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [31:0] _GEN = {io_pmp_7_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_T_1; // @[PMP.scala:60:36] assign _res_hit_T_1 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_19; // @[PMP.scala:60:36] assign _res_hit_T_19 = _GEN; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_2 = ~_res_hit_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_3 = {_res_hit_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_4 = ~_res_hit_T_3; // @[PMP.scala:60:{27,48}] wire [31:0] _res_hit_T_5 = io_addr_0 ^ _res_hit_T_4; // @[PMP.scala:60:27, :63:47, :143:7] wire [31:0] _res_hit_T_6 = ~io_pmp_7_mask_0; // @[PMP.scala:63:54, :143:7] wire [31:0] _res_hit_T_7 = _res_hit_T_5 & _res_hit_T_6; // @[PMP.scala:63:{47,52,54}] wire _res_hit_T_8 = _res_hit_T_7 == 32'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_9 = io_pmp_7_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_0 = {io_pmp_6_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_T_13; // @[PMP.scala:60:36] assign _res_hit_T_13 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_27; // @[PMP.scala:60:36] assign _res_hit_T_27 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_45; // @[PMP.scala:60:36] assign _res_hit_T_45 = _GEN_0; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_14 = ~_res_hit_T_13; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_15 = {_res_hit_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_16 = ~_res_hit_T_15; // @[PMP.scala:60:{27,48}] wire _res_hit_T_17 = io_addr_0 < _res_hit_T_16; // @[PMP.scala:60:27, :77:9, :143:7] wire _res_hit_T_18 = ~_res_hit_T_17; // @[PMP.scala:77:9, :88:5] wire [31:0] _res_hit_T_20 = ~_res_hit_T_19; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_21 = {_res_hit_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_22 = ~_res_hit_T_21; // @[PMP.scala:60:{27,48}] wire _res_hit_T_23 = io_addr_0 < _res_hit_T_22; // @[PMP.scala:60:27, :77:9, :143:7] wire _res_hit_T_24 = _res_hit_T_18 & _res_hit_T_23; // @[PMP.scala:77:9, :88:5, :94:48] wire _res_hit_T_25 = _res_hit_T_9 & _res_hit_T_24; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit = _res_hit_T ? _res_hit_T_8 : _res_hit_T_25; // @[PMP.scala:45:20, :63:58, :132:{8,61}] wire _res_ignore_T = ~io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore = default_0 & _res_ignore_T; // @[PMP.scala:156:56, :164:{26,29}] wire _res_T = io_pmp_7_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_1 = io_pmp_7_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_1; // @[PMP.scala:168:32] assign _res_T_1 = _GEN_1; // @[PMP.scala:168:32] wire _res_T_20; // @[PMP.scala:177:61] assign _res_T_20 = _GEN_1; // @[PMP.scala:168:32, :177:61] wire _res_T_24; // @[PMP.scala:178:63] assign _res_T_24 = _GEN_1; // @[PMP.scala:168:32, :178:63] wire _GEN_2 = io_pmp_7_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_2; // @[PMP.scala:168:32] assign _res_T_2 = _GEN_2; // @[PMP.scala:168:32] wire _res_T_29; // @[PMP.scala:177:61] assign _res_T_29 = _GEN_2; // @[PMP.scala:168:32, :177:61] wire _res_T_33; // @[PMP.scala:178:63] assign _res_T_33 = _GEN_2; // @[PMP.scala:168:32, :178:63] wire _res_T_3 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_3 = {io_pmp_7_cfg_x_0, io_pmp_7_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi; // @[PMP.scala:174:26] assign res_hi = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_1; // @[PMP.scala:174:26] assign res_hi_1 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_2; // @[PMP.scala:174:26] assign res_hi_2 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_3; // @[PMP.scala:174:26] assign res_hi_3 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_4; // @[PMP.scala:174:26] assign res_hi_4 = _GEN_3; // @[PMP.scala:174:26] wire [1:0] res_hi_5; // @[PMP.scala:174:26] assign res_hi_5 = _GEN_3; // @[PMP.scala:174:26] wire [2:0] _res_T_5 = {res_hi, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_6 = _res_T_5 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_7 = {res_hi_1, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_8 = _res_T_7 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_9 = {res_hi_2, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_10 = _res_T_9 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_11 = {res_hi_3, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_12 = _res_T_11 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_13 = {res_hi_4, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_14 = _res_T_13 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_15 = {res_hi_5, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_16 = &_res_T_15; // @[PMP.scala:174:{26,60}] wire _res_T_17 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_18 = _res_T_17 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_19 = _res_T_18; // @[PMP.scala:177:{30,37}] wire _res_T_21 = _res_T_19 & _res_T_20; // @[PMP.scala:177:{37,48,61}] wire _GEN_4 = io_pmp_7_cfg_l_0 & res_hit; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_22; // @[PMP.scala:178:32] assign _res_T_22 = _GEN_4; // @[PMP.scala:178:32] wire _res_T_31; // @[PMP.scala:178:32] assign _res_T_31 = _GEN_4; // @[PMP.scala:178:32] wire _res_T_40; // @[PMP.scala:178:32] assign _res_T_40 = _GEN_4; // @[PMP.scala:178:32] wire _res_T_23 = _res_T_22; // @[PMP.scala:178:{32,39}] wire _res_T_25 = _res_T_23 & _res_T_24; // @[PMP.scala:178:{39,50,63}] wire _res_T_26 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_27 = _res_T_26 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_28 = _res_T_27; // @[PMP.scala:177:{30,37}] wire _res_T_30 = _res_T_28 & _res_T_29; // @[PMP.scala:177:{37,48,61}] wire _res_T_32 = _res_T_31; // @[PMP.scala:178:{32,39}] wire _res_T_34 = _res_T_32 & _res_T_33; // @[PMP.scala:178:{39,50,63}] wire _res_T_35 = ~res_ignore; // @[PMP.scala:164:26, :177:22] wire _res_T_36 = _res_T_35 & res_hit; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_37 = _res_T_36; // @[PMP.scala:177:{30,37}] wire _res_T_38 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_39 = _res_T_37 & _res_T_38; // @[PMP.scala:177:{37,48,61}] wire _res_T_41 = _res_T_40; // @[PMP.scala:178:{32,39}] wire _res_T_42 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_43 = _res_T_41 & _res_T_42; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_1; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_1; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_1; // @[PMP.scala:182:26] wire res_cur_cfg_x; // @[PMP.scala:181:23] wire res_cur_cfg_w; // @[PMP.scala:181:23] wire res_cur_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T = io_pmp_7_cfg_r_0 \| res_ignore; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_1 = _res_cur_cfg_r_T; // @[PMP.scala:182:{26,40}] assign res_cur_cfg_r = _res_cur_cfg_r_T_1; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T = io_pmp_7_cfg_w_0 \| res_ignore; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_1 = _res_cur_cfg_w_T; // @[PMP.scala:183:{26,40}] assign res_cur_cfg_w = _res_cur_cfg_w_T_1; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T = io_pmp_7_cfg_x_0 \| res_ignore; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_1 = _res_cur_cfg_x_T; // @[PMP.scala:184:{26,40}] assign res_cur_cfg_x = _res_cur_cfg_x_T_1; // @[PMP.scala:181:23, :184:26] wire _res_T_44_cfg_l = res_hit & res_cur_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_44_cfg_a = res_hit ? res_cur_cfg_a : 2'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_44_cfg_x = res_hit ? res_cur_cfg_x : pmp0_cfg_x; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire _res_T_44_cfg_w = res_hit ? res_cur_cfg_w : pmp0_cfg_w; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire _res_T_44_cfg_r = res_hit ? res_cur_cfg_r : pmp0_cfg_r; // @[PMP.scala:132:8, :157:22, :181:23, :185:8] wire [29:0] _res_T_44_addr = res_hit ? res_cur_addr : 30'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_44_mask = res_hit ? res_cur_mask : 32'h0; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_26 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [31:0] _res_hit_T_28 = ~_res_hit_T_27; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_29 = {_res_hit_T_28[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_30 = ~_res_hit_T_29; // @[PMP.scala:60:{27,48}] wire [31:0] _res_hit_T_31 = io_addr_0 ^ _res_hit_T_30; // @[PMP.scala:60:27, :63:47, :143:7] wire [31:0] _res_hit_T_32 = ~io_pmp_6_mask_0; // @[PMP.scala:63:54, :143:7] wire [31:0] _res_hit_T_33 = _res_hit_T_31 & _res_hit_T_32; // @[PMP.scala:63:{47,52,54}] wire _res_hit_T_34 = _res_hit_T_33 == 32'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_35 = io_pmp_6_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_5 = {io_pmp_5_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_T_39; // @[PMP.scala:60:36] assign _res_hit_T_39 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_53; // @[PMP.scala:60:36] assign _res_hit_T_53 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_71; // @[PMP.scala:60:36] assign _res_hit_T_71 = _GEN_5; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_40 = ~_res_hit_T_39; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_41 = {_res_hit_T_40[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_42 = ~_res_hit_T_41; // @[PMP.scala:60:{27,48}] wire _res_hit_T_43 = io_addr_0 < _res_hit_T_42; // @[PMP.scala:60:27, :77:9, :143:7] wire _res_hit_T_44 = ~_res_hit_T_43; // @[PMP.scala:77:9, :88:5] wire [31:0] _res_hit_T_46 = ~_res_hit_T_45; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_47 = {_res_hit_T_46[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_48 = ~_res_hit_T_47; // @[PMP.scala:60:{27,48}] wire _res_hit_T_49 = io_addr_0 < _res_hit_T_48; // @[PMP.scala:60:27, :77:9, :143:7] wire _res_hit_T_50 = _res_hit_T_44 & _res_hit_T_49; // @[PMP.scala:77:9, :88:5, :94:48] wire _res_hit_T_51 = _res_hit_T_35 & _res_hit_T_50; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_1 = _res_hit_T_26 ? _res_hit_T_34 : _res_hit_T_51; // @[PMP.scala:45:20, :63:58, :132:{8,61}] wire _res_ignore_T_1 = ~io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_1 = default_0 & _res_ignore_T_1; // @[PMP.scala:156:56, :164:{26,29}] wire _res_T_45 = io_pmp_6_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_6 = io_pmp_6_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_46; // @[PMP.scala:168:32] assign _res_T_46 = _GEN_6; // @[PMP.scala:168:32] wire _res_T_65; // @[PMP.scala:177:61] assign _res_T_65 = _GEN_6; // @[PMP.scala:168:32, :177:61] wire _res_T_69; // @[PMP.scala:178:63] assign _res_T_69 = _GEN_6; // @[PMP.scala:168:32, :178:63] wire _GEN_7 = io_pmp_6_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_47; // @[PMP.scala:168:32] assign _res_T_47 = _GEN_7; // @[PMP.scala:168:32] wire _res_T_74; // @[PMP.scala:177:61] assign _res_T_74 = _GEN_7; // @[PMP.scala:168:32, :177:61] wire _res_T_78; // @[PMP.scala:178:63] assign _res_T_78 = _GEN_7; // @[PMP.scala:168:32, :178:63] wire _res_T_48 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_8 = {io_pmp_6_cfg_x_0, io_pmp_6_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_6; // @[PMP.scala:174:26] assign res_hi_6 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_7; // @[PMP.scala:174:26] assign res_hi_7 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_8; // @[PMP.scala:174:26] assign res_hi_8 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_9; // @[PMP.scala:174:26] assign res_hi_9 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_10; // @[PMP.scala:174:26] assign res_hi_10 = _GEN_8; // @[PMP.scala:174:26] wire [1:0] res_hi_11; // @[PMP.scala:174:26] assign res_hi_11 = _GEN_8; // @[PMP.scala:174:26] wire [2:0] _res_T_50 = {res_hi_6, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_51 = _res_T_50 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_52 = {res_hi_7, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_53 = _res_T_52 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_54 = {res_hi_8, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_55 = _res_T_54 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_56 = {res_hi_9, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_57 = _res_T_56 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_58 = {res_hi_10, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_59 = _res_T_58 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_60 = {res_hi_11, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_61 = &_res_T_60; // @[PMP.scala:174:{26,60}] wire _res_T_62 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_63 = _res_T_62 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_64 = _res_T_63; // @[PMP.scala:177:{30,37}] wire _res_T_66 = _res_T_64 & _res_T_65; // @[PMP.scala:177:{37,48,61}] wire _GEN_9 = io_pmp_6_cfg_l_0 & res_hit_1; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_67; // @[PMP.scala:178:32] assign _res_T_67 = _GEN_9; // @[PMP.scala:178:32] wire _res_T_76; // @[PMP.scala:178:32] assign _res_T_76 = _GEN_9; // @[PMP.scala:178:32] wire _res_T_85; // @[PMP.scala:178:32] assign _res_T_85 = _GEN_9; // @[PMP.scala:178:32] wire _res_T_68 = _res_T_67; // @[PMP.scala:178:{32,39}] wire _res_T_70 = _res_T_68 & _res_T_69; // @[PMP.scala:178:{39,50,63}] wire _res_T_71 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_72 = _res_T_71 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_73 = _res_T_72; // @[PMP.scala:177:{30,37}] wire _res_T_75 = _res_T_73 & _res_T_74; // @[PMP.scala:177:{37,48,61}] wire _res_T_77 = _res_T_76; // @[PMP.scala:178:{32,39}] wire _res_T_79 = _res_T_77 & _res_T_78; // @[PMP.scala:178:{39,50,63}] wire _res_T_80 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22] wire _res_T_81 = _res_T_80 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_82 = _res_T_81; // @[PMP.scala:177:{30,37}] wire _res_T_83 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_84 = _res_T_82 & _res_T_83; // @[PMP.scala:177:{37,48,61}] wire _res_T_86 = _res_T_85; // @[PMP.scala:178:{32,39}] wire _res_T_87 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_88 = _res_T_86 & _res_T_87; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_3; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_3; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_3; // @[PMP.scala:182:26] wire res_cur_1_cfg_x; // @[PMP.scala:181:23] wire res_cur_1_cfg_w; // @[PMP.scala:181:23] wire res_cur_1_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_2 = io_pmp_6_cfg_r_0 \| res_ignore_1; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_3 = _res_cur_cfg_r_T_2; // @[PMP.scala:182:{26,40}] assign res_cur_1_cfg_r = _res_cur_cfg_r_T_3; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_2 = io_pmp_6_cfg_w_0 \| res_ignore_1; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_3 = _res_cur_cfg_w_T_2; // @[PMP.scala:183:{26,40}] assign res_cur_1_cfg_w = _res_cur_cfg_w_T_3; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_2 = io_pmp_6_cfg_x_0 \| res_ignore_1; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_3 = _res_cur_cfg_x_T_2; // @[PMP.scala:184:{26,40}] assign res_cur_1_cfg_x = _res_cur_cfg_x_T_3; // @[PMP.scala:181:23, :184:26] wire _res_T_89_cfg_l = res_hit_1 ? res_cur_1_cfg_l : _res_T_44_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_89_cfg_a = res_hit_1 ? res_cur_1_cfg_a : _res_T_44_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_x = res_hit_1 ? res_cur_1_cfg_x : _res_T_44_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_w = res_hit_1 ? res_cur_1_cfg_w : _res_T_44_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_89_cfg_r = res_hit_1 ? res_cur_1_cfg_r : _res_T_44_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_89_addr = res_hit_1 ? res_cur_1_addr : _res_T_44_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_89_mask = res_hit_1 ? res_cur_1_mask : _res_T_44_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_52 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [31:0] _res_hit_T_54 = ~_res_hit_T_53; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_55 = {_res_hit_T_54[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_56 = ~_res_hit_T_55; // @[PMP.scala:60:{27,48}] wire [31:0] _res_hit_T_57 = io_addr_0 ^ _res_hit_T_56; // @[PMP.scala:60:27, :63:47, :143:7] wire [31:0] _res_hit_T_58 = ~io_pmp_5_mask_0; // @[PMP.scala:63:54, :143:7] wire [31:0] _res_hit_T_59 = _res_hit_T_57 & _res_hit_T_58; // @[PMP.scala:63:{47,52,54}] wire _res_hit_T_60 = _res_hit_T_59 == 32'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_61 = io_pmp_5_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_10 = {io_pmp_4_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_T_65; // @[PMP.scala:60:36] assign _res_hit_T_65 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_79; // @[PMP.scala:60:36] assign _res_hit_T_79 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_97; // @[PMP.scala:60:36] assign _res_hit_T_97 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_66 = ~_res_hit_T_65; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_67 = {_res_hit_T_66[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_68 = ~_res_hit_T_67; // @[PMP.scala:60:{27,48}] wire _res_hit_T_69 = io_addr_0 < _res_hit_T_68; // @[PMP.scala:60:27, :77:9, :143:7] wire _res_hit_T_70 = ~_res_hit_T_69; // @[PMP.scala:77:9, :88:5] wire [31:0] _res_hit_T_72 = ~_res_hit_T_71; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_73 = {_res_hit_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_74 = ~_res_hit_T_73; // @[PMP.scala:60:{27,48}] wire _res_hit_T_75 = io_addr_0 < _res_hit_T_74; // @[PMP.scala:60:27, :77:9, :143:7] wire _res_hit_T_76 = _res_hit_T_70 & _res_hit_T_75; // @[PMP.scala:77:9, :88:5, :94:48] wire _res_hit_T_77 = _res_hit_T_61 & _res_hit_T_76; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_2 = _res_hit_T_52 ? _res_hit_T_60 : _res_hit_T_77; // @[PMP.scala:45:20, :63:58, :132:{8,61}] wire _res_ignore_T_2 = ~io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_2 = default_0 & _res_ignore_T_2; // @[PMP.scala:156:56, :164:{26,29}] wire _res_T_90 = io_pmp_5_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_11 = io_pmp_5_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_91; // @[PMP.scala:168:32] assign _res_T_91 = _GEN_11; // @[PMP.scala:168:32] wire _res_T_110; // @[PMP.scala:177:61] assign _res_T_110 = _GEN_11; // @[PMP.scala:168:32, :177:61] wire _res_T_114; // @[PMP.scala:178:63] assign _res_T_114 = _GEN_11; // @[PMP.scala:168:32, :178:63] wire _GEN_12 = io_pmp_5_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_92; // @[PMP.scala:168:32] assign _res_T_92 = _GEN_12; // @[PMP.scala:168:32] wire _res_T_119; // @[PMP.scala:177:61] assign _res_T_119 = _GEN_12; // @[PMP.scala:168:32, :177:61] wire _res_T_123; // @[PMP.scala:178:63] assign _res_T_123 = _GEN_12; // @[PMP.scala:168:32, :178:63] wire _res_T_93 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_13 = {io_pmp_5_cfg_x_0, io_pmp_5_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_12; // @[PMP.scala:174:26] assign res_hi_12 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_13; // @[PMP.scala:174:26] assign res_hi_13 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_14; // @[PMP.scala:174:26] assign res_hi_14 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_15; // @[PMP.scala:174:26] assign res_hi_15 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_16; // @[PMP.scala:174:26] assign res_hi_16 = _GEN_13; // @[PMP.scala:174:26] wire [1:0] res_hi_17; // @[PMP.scala:174:26] assign res_hi_17 = _GEN_13; // @[PMP.scala:174:26] wire [2:0] _res_T_95 = {res_hi_12, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_96 = _res_T_95 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_97 = {res_hi_13, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_98 = _res_T_97 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_99 = {res_hi_14, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_100 = _res_T_99 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_101 = {res_hi_15, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_102 = _res_T_101 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_103 = {res_hi_16, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_104 = _res_T_103 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_105 = {res_hi_17, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_106 = &_res_T_105; // @[PMP.scala:174:{26,60}] wire _res_T_107 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_108 = _res_T_107 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_109 = _res_T_108; // @[PMP.scala:177:{30,37}] wire _res_T_111 = _res_T_109 & _res_T_110; // @[PMP.scala:177:{37,48,61}] wire _GEN_14 = io_pmp_5_cfg_l_0 & res_hit_2; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_112; // @[PMP.scala:178:32] assign _res_T_112 = _GEN_14; // @[PMP.scala:178:32] wire _res_T_121; // @[PMP.scala:178:32] assign _res_T_121 = _GEN_14; // @[PMP.scala:178:32] wire _res_T_130; // @[PMP.scala:178:32] assign _res_T_130 = _GEN_14; // @[PMP.scala:178:32] wire _res_T_113 = _res_T_112; // @[PMP.scala:178:{32,39}] wire _res_T_115 = _res_T_113 & _res_T_114; // @[PMP.scala:178:{39,50,63}] wire _res_T_116 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_117 = _res_T_116 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_118 = _res_T_117; // @[PMP.scala:177:{30,37}] wire _res_T_120 = _res_T_118 & _res_T_119; // @[PMP.scala:177:{37,48,61}] wire _res_T_122 = _res_T_121; // @[PMP.scala:178:{32,39}] wire _res_T_124 = _res_T_122 & _res_T_123; // @[PMP.scala:178:{39,50,63}] wire _res_T_125 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22] wire _res_T_126 = _res_T_125 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_127 = _res_T_126; // @[PMP.scala:177:{30,37}] wire _res_T_128 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_129 = _res_T_127 & _res_T_128; // @[PMP.scala:177:{37,48,61}] wire _res_T_131 = _res_T_130; // @[PMP.scala:178:{32,39}] wire _res_T_132 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_133 = _res_T_131 & _res_T_132; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_5; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_5; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_5; // @[PMP.scala:182:26] wire res_cur_2_cfg_x; // @[PMP.scala:181:23] wire res_cur_2_cfg_w; // @[PMP.scala:181:23] wire res_cur_2_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_4 = io_pmp_5_cfg_r_0 \| res_ignore_2; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_5 = _res_cur_cfg_r_T_4; // @[PMP.scala:182:{26,40}] assign res_cur_2_cfg_r = _res_cur_cfg_r_T_5; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_4 = io_pmp_5_cfg_w_0 \| res_ignore_2; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_5 = _res_cur_cfg_w_T_4; // @[PMP.scala:183:{26,40}] assign res_cur_2_cfg_w = _res_cur_cfg_w_T_5; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_4 = io_pmp_5_cfg_x_0 \| res_ignore_2; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_5 = _res_cur_cfg_x_T_4; // @[PMP.scala:184:{26,40}] assign res_cur_2_cfg_x = _res_cur_cfg_x_T_5; // @[PMP.scala:181:23, :184:26] wire _res_T_134_cfg_l = res_hit_2 ? res_cur_2_cfg_l : _res_T_89_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_134_cfg_a = res_hit_2 ? res_cur_2_cfg_a : _res_T_89_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_x = res_hit_2 ? res_cur_2_cfg_x : _res_T_89_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_w = res_hit_2 ? res_cur_2_cfg_w : _res_T_89_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_134_cfg_r = res_hit_2 ? res_cur_2_cfg_r : _res_T_89_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_134_addr = res_hit_2 ? res_cur_2_addr : _res_T_89_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_134_mask = res_hit_2 ? res_cur_2_mask : _res_T_89_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_78 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [31:0] _res_hit_T_80 = ~_res_hit_T_79; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_81 = {_res_hit_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_82 = ~_res_hit_T_81; // @[PMP.scala:60:{27,48}] wire [31:0] _res_hit_T_83 = io_addr_0 ^ _res_hit_T_82; // @[PMP.scala:60:27, :63:47, :143:7] wire [31:0] _res_hit_T_84 = ~io_pmp_4_mask_0; // @[PMP.scala:63:54, :143:7] wire [31:0] _res_hit_T_85 = _res_hit_T_83 & _res_hit_T_84; // @[PMP.scala:63:{47,52,54}] wire _res_hit_T_86 = _res_hit_T_85 == 32'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_87 = io_pmp_4_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_15 = {io_pmp_3_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_T_91; // @[PMP.scala:60:36] assign _res_hit_T_91 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_105; // @[PMP.scala:60:36] assign _res_hit_T_105 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_123; // @[PMP.scala:60:36] assign _res_hit_T_123 = _GEN_15; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_92 = ~_res_hit_T_91; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_93 = {_res_hit_T_92[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_94 = ~_res_hit_T_93; // @[PMP.scala:60:{27,48}] wire _res_hit_T_95 = io_addr_0 < _res_hit_T_94; // @[PMP.scala:60:27, :77:9, :143:7] wire _res_hit_T_96 = ~_res_hit_T_95; // @[PMP.scala:77:9, :88:5] wire [31:0] _res_hit_T_98 = ~_res_hit_T_97; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_99 = {_res_hit_T_98[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_100 = ~_res_hit_T_99; // @[PMP.scala:60:{27,48}] wire _res_hit_T_101 = io_addr_0 < _res_hit_T_100; // @[PMP.scala:60:27, :77:9, :143:7] wire _res_hit_T_102 = _res_hit_T_96 & _res_hit_T_101; // @[PMP.scala:77:9, :88:5, :94:48] wire _res_hit_T_103 = _res_hit_T_87 & _res_hit_T_102; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_3 = _res_hit_T_78 ? _res_hit_T_86 : _res_hit_T_103; // @[PMP.scala:45:20, :63:58, :132:{8,61}] wire _res_ignore_T_3 = ~io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_3 = default_0 & _res_ignore_T_3; // @[PMP.scala:156:56, :164:{26,29}] wire _res_T_135 = io_pmp_4_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_16 = io_pmp_4_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_136; // @[PMP.scala:168:32] assign _res_T_136 = _GEN_16; // @[PMP.scala:168:32] wire _res_T_155; // @[PMP.scala:177:61] assign _res_T_155 = _GEN_16; // @[PMP.scala:168:32, :177:61] wire _res_T_159; // @[PMP.scala:178:63] assign _res_T_159 = _GEN_16; // @[PMP.scala:168:32, :178:63] wire _GEN_17 = io_pmp_4_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_137; // @[PMP.scala:168:32] assign _res_T_137 = _GEN_17; // @[PMP.scala:168:32] wire _res_T_164; // @[PMP.scala:177:61] assign _res_T_164 = _GEN_17; // @[PMP.scala:168:32, :177:61] wire _res_T_168; // @[PMP.scala:178:63] assign _res_T_168 = _GEN_17; // @[PMP.scala:168:32, :178:63] wire _res_T_138 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_18 = {io_pmp_4_cfg_x_0, io_pmp_4_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_18; // @[PMP.scala:174:26] assign res_hi_18 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_19; // @[PMP.scala:174:26] assign res_hi_19 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_20; // @[PMP.scala:174:26] assign res_hi_20 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_21; // @[PMP.scala:174:26] assign res_hi_21 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_22; // @[PMP.scala:174:26] assign res_hi_22 = _GEN_18; // @[PMP.scala:174:26] wire [1:0] res_hi_23; // @[PMP.scala:174:26] assign res_hi_23 = _GEN_18; // @[PMP.scala:174:26] wire [2:0] _res_T_140 = {res_hi_18, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_141 = _res_T_140 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_142 = {res_hi_19, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_143 = _res_T_142 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_144 = {res_hi_20, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_145 = _res_T_144 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_146 = {res_hi_21, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_147 = _res_T_146 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_148 = {res_hi_22, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_149 = _res_T_148 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_150 = {res_hi_23, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_151 = &_res_T_150; // @[PMP.scala:174:{26,60}] wire _res_T_152 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_153 = _res_T_152 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_154 = _res_T_153; // @[PMP.scala:177:{30,37}] wire _res_T_156 = _res_T_154 & _res_T_155; // @[PMP.scala:177:{37,48,61}] wire _GEN_19 = io_pmp_4_cfg_l_0 & res_hit_3; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_157; // @[PMP.scala:178:32] assign _res_T_157 = _GEN_19; // @[PMP.scala:178:32] wire _res_T_166; // @[PMP.scala:178:32] assign _res_T_166 = _GEN_19; // @[PMP.scala:178:32] wire _res_T_175; // @[PMP.scala:178:32] assign _res_T_175 = _GEN_19; // @[PMP.scala:178:32] wire _res_T_158 = _res_T_157; // @[PMP.scala:178:{32,39}] wire _res_T_160 = _res_T_158 & _res_T_159; // @[PMP.scala:178:{39,50,63}] wire _res_T_161 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_162 = _res_T_161 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_163 = _res_T_162; // @[PMP.scala:177:{30,37}] wire _res_T_165 = _res_T_163 & _res_T_164; // @[PMP.scala:177:{37,48,61}] wire _res_T_167 = _res_T_166; // @[PMP.scala:178:{32,39}] wire _res_T_169 = _res_T_167 & _res_T_168; // @[PMP.scala:178:{39,50,63}] wire _res_T_170 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22] wire _res_T_171 = _res_T_170 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_172 = _res_T_171; // @[PMP.scala:177:{30,37}] wire _res_T_173 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_174 = _res_T_172 & _res_T_173; // @[PMP.scala:177:{37,48,61}] wire _res_T_176 = _res_T_175; // @[PMP.scala:178:{32,39}] wire _res_T_177 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_178 = _res_T_176 & _res_T_177; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_7; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_7; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_7; // @[PMP.scala:182:26] wire res_cur_3_cfg_x; // @[PMP.scala:181:23] wire res_cur_3_cfg_w; // @[PMP.scala:181:23] wire res_cur_3_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_6 = io_pmp_4_cfg_r_0 \| res_ignore_3; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_7 = _res_cur_cfg_r_T_6; // @[PMP.scala:182:{26,40}] assign res_cur_3_cfg_r = _res_cur_cfg_r_T_7; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_6 = io_pmp_4_cfg_w_0 \| res_ignore_3; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_7 = _res_cur_cfg_w_T_6; // @[PMP.scala:183:{26,40}] assign res_cur_3_cfg_w = _res_cur_cfg_w_T_7; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_6 = io_pmp_4_cfg_x_0 \| res_ignore_3; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_7 = _res_cur_cfg_x_T_6; // @[PMP.scala:184:{26,40}] assign res_cur_3_cfg_x = _res_cur_cfg_x_T_7; // @[PMP.scala:181:23, :184:26] wire _res_T_179_cfg_l = res_hit_3 ? res_cur_3_cfg_l : _res_T_134_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_179_cfg_a = res_hit_3 ? res_cur_3_cfg_a : _res_T_134_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_x = res_hit_3 ? res_cur_3_cfg_x : _res_T_134_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_w = res_hit_3 ? res_cur_3_cfg_w : _res_T_134_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_179_cfg_r = res_hit_3 ? res_cur_3_cfg_r : _res_T_134_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_179_addr = res_hit_3 ? res_cur_3_addr : _res_T_134_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_179_mask = res_hit_3 ? res_cur_3_mask : _res_T_134_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_104 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [31:0] _res_hit_T_106 = ~_res_hit_T_105; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_107 = {_res_hit_T_106[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_108 = ~_res_hit_T_107; // @[PMP.scala:60:{27,48}] wire [31:0] _res_hit_T_109 = io_addr_0 ^ _res_hit_T_108; // @[PMP.scala:60:27, :63:47, :143:7] wire [31:0] _res_hit_T_110 = ~io_pmp_3_mask_0; // @[PMP.scala:63:54, :143:7] wire [31:0] _res_hit_T_111 = _res_hit_T_109 & _res_hit_T_110; // @[PMP.scala:63:{47,52,54}] wire _res_hit_T_112 = _res_hit_T_111 == 32'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_113 = io_pmp_3_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_20 = {io_pmp_2_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_T_117; // @[PMP.scala:60:36] assign _res_hit_T_117 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_131; // @[PMP.scala:60:36] assign _res_hit_T_131 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_149; // @[PMP.scala:60:36] assign _res_hit_T_149 = _GEN_20; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_118 = ~_res_hit_T_117; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_119 = {_res_hit_T_118[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_120 = ~_res_hit_T_119; // @[PMP.scala:60:{27,48}] wire _res_hit_T_121 = io_addr_0 < _res_hit_T_120; // @[PMP.scala:60:27, :77:9, :143:7] wire _res_hit_T_122 = ~_res_hit_T_121; // @[PMP.scala:77:9, :88:5] wire [31:0] _res_hit_T_124 = ~_res_hit_T_123; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_125 = {_res_hit_T_124[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_126 = ~_res_hit_T_125; // @[PMP.scala:60:{27,48}] wire _res_hit_T_127 = io_addr_0 < _res_hit_T_126; // @[PMP.scala:60:27, :77:9, :143:7] wire _res_hit_T_128 = _res_hit_T_122 & _res_hit_T_127; // @[PMP.scala:77:9, :88:5, :94:48] wire _res_hit_T_129 = _res_hit_T_113 & _res_hit_T_128; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_4 = _res_hit_T_104 ? _res_hit_T_112 : _res_hit_T_129; // @[PMP.scala:45:20, :63:58, :132:{8,61}] wire _res_ignore_T_4 = ~io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_4 = default_0 & _res_ignore_T_4; // @[PMP.scala:156:56, :164:{26,29}] wire _res_T_180 = io_pmp_3_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_21 = io_pmp_3_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_181; // @[PMP.scala:168:32] assign _res_T_181 = _GEN_21; // @[PMP.scala:168:32] wire _res_T_200; // @[PMP.scala:177:61] assign _res_T_200 = _GEN_21; // @[PMP.scala:168:32, :177:61] wire _res_T_204; // @[PMP.scala:178:63] assign _res_T_204 = _GEN_21; // @[PMP.scala:168:32, :178:63] wire _GEN_22 = io_pmp_3_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_182; // @[PMP.scala:168:32] assign _res_T_182 = _GEN_22; // @[PMP.scala:168:32] wire _res_T_209; // @[PMP.scala:177:61] assign _res_T_209 = _GEN_22; // @[PMP.scala:168:32, :177:61] wire _res_T_213; // @[PMP.scala:178:63] assign _res_T_213 = _GEN_22; // @[PMP.scala:168:32, :178:63] wire _res_T_183 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_23 = {io_pmp_3_cfg_x_0, io_pmp_3_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_24; // @[PMP.scala:174:26] assign res_hi_24 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_25; // @[PMP.scala:174:26] assign res_hi_25 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_26; // @[PMP.scala:174:26] assign res_hi_26 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_27; // @[PMP.scala:174:26] assign res_hi_27 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_28; // @[PMP.scala:174:26] assign res_hi_28 = _GEN_23; // @[PMP.scala:174:26] wire [1:0] res_hi_29; // @[PMP.scala:174:26] assign res_hi_29 = _GEN_23; // @[PMP.scala:174:26] wire [2:0] _res_T_185 = {res_hi_24, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_186 = _res_T_185 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_187 = {res_hi_25, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_188 = _res_T_187 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_189 = {res_hi_26, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_190 = _res_T_189 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_191 = {res_hi_27, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_192 = _res_T_191 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_193 = {res_hi_28, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_194 = _res_T_193 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_195 = {res_hi_29, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_196 = &_res_T_195; // @[PMP.scala:174:{26,60}] wire _res_T_197 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_198 = _res_T_197 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_199 = _res_T_198; // @[PMP.scala:177:{30,37}] wire _res_T_201 = _res_T_199 & _res_T_200; // @[PMP.scala:177:{37,48,61}] wire _GEN_24 = io_pmp_3_cfg_l_0 & res_hit_4; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_202; // @[PMP.scala:178:32] assign _res_T_202 = _GEN_24; // @[PMP.scala:178:32] wire _res_T_211; // @[PMP.scala:178:32] assign _res_T_211 = _GEN_24; // @[PMP.scala:178:32] wire _res_T_220; // @[PMP.scala:178:32] assign _res_T_220 = _GEN_24; // @[PMP.scala:178:32] wire _res_T_203 = _res_T_202; // @[PMP.scala:178:{32,39}] wire _res_T_205 = _res_T_203 & _res_T_204; // @[PMP.scala:178:{39,50,63}] wire _res_T_206 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_207 = _res_T_206 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_208 = _res_T_207; // @[PMP.scala:177:{30,37}] wire _res_T_210 = _res_T_208 & _res_T_209; // @[PMP.scala:177:{37,48,61}] wire _res_T_212 = _res_T_211; // @[PMP.scala:178:{32,39}] wire _res_T_214 = _res_T_212 & _res_T_213; // @[PMP.scala:178:{39,50,63}] wire _res_T_215 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22] wire _res_T_216 = _res_T_215 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_217 = _res_T_216; // @[PMP.scala:177:{30,37}] wire _res_T_218 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_219 = _res_T_217 & _res_T_218; // @[PMP.scala:177:{37,48,61}] wire _res_T_221 = _res_T_220; // @[PMP.scala:178:{32,39}] wire _res_T_222 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_223 = _res_T_221 & _res_T_222; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_9; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_9; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_9; // @[PMP.scala:182:26] wire res_cur_4_cfg_x; // @[PMP.scala:181:23] wire res_cur_4_cfg_w; // @[PMP.scala:181:23] wire res_cur_4_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_8 = io_pmp_3_cfg_r_0 \| res_ignore_4; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_9 = _res_cur_cfg_r_T_8; // @[PMP.scala:182:{26,40}] assign res_cur_4_cfg_r = _res_cur_cfg_r_T_9; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_8 = io_pmp_3_cfg_w_0 \| res_ignore_4; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_9 = _res_cur_cfg_w_T_8; // @[PMP.scala:183:{26,40}] assign res_cur_4_cfg_w = _res_cur_cfg_w_T_9; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_8 = io_pmp_3_cfg_x_0 \| res_ignore_4; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_9 = _res_cur_cfg_x_T_8; // @[PMP.scala:184:{26,40}] assign res_cur_4_cfg_x = _res_cur_cfg_x_T_9; // @[PMP.scala:181:23, :184:26] wire _res_T_224_cfg_l = res_hit_4 ? res_cur_4_cfg_l : _res_T_179_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_224_cfg_a = res_hit_4 ? res_cur_4_cfg_a : _res_T_179_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_x = res_hit_4 ? res_cur_4_cfg_x : _res_T_179_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_w = res_hit_4 ? res_cur_4_cfg_w : _res_T_179_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_224_cfg_r = res_hit_4 ? res_cur_4_cfg_r : _res_T_179_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_224_addr = res_hit_4 ? res_cur_4_addr : _res_T_179_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_224_mask = res_hit_4 ? res_cur_4_mask : _res_T_179_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_130 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [31:0] _res_hit_T_132 = ~_res_hit_T_131; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_133 = {_res_hit_T_132[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_134 = ~_res_hit_T_133; // @[PMP.scala:60:{27,48}] wire [31:0] _res_hit_T_135 = io_addr_0 ^ _res_hit_T_134; // @[PMP.scala:60:27, :63:47, :143:7] wire [31:0] _res_hit_T_136 = ~io_pmp_2_mask_0; // @[PMP.scala:63:54, :143:7] wire [31:0] _res_hit_T_137 = _res_hit_T_135 & _res_hit_T_136; // @[PMP.scala:63:{47,52,54}] wire _res_hit_T_138 = _res_hit_T_137 == 32'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_139 = io_pmp_2_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_25 = {io_pmp_1_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_T_143; // @[PMP.scala:60:36] assign _res_hit_T_143 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_157; // @[PMP.scala:60:36] assign _res_hit_T_157 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_175; // @[PMP.scala:60:36] assign _res_hit_T_175 = _GEN_25; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_144 = ~_res_hit_T_143; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_145 = {_res_hit_T_144[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_146 = ~_res_hit_T_145; // @[PMP.scala:60:{27,48}] wire _res_hit_T_147 = io_addr_0 < _res_hit_T_146; // @[PMP.scala:60:27, :77:9, :143:7] wire _res_hit_T_148 = ~_res_hit_T_147; // @[PMP.scala:77:9, :88:5] wire [31:0] _res_hit_T_150 = ~_res_hit_T_149; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_151 = {_res_hit_T_150[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_152 = ~_res_hit_T_151; // @[PMP.scala:60:{27,48}] wire _res_hit_T_153 = io_addr_0 < _res_hit_T_152; // @[PMP.scala:60:27, :77:9, :143:7] wire _res_hit_T_154 = _res_hit_T_148 & _res_hit_T_153; // @[PMP.scala:77:9, :88:5, :94:48] wire _res_hit_T_155 = _res_hit_T_139 & _res_hit_T_154; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_5 = _res_hit_T_130 ? _res_hit_T_138 : _res_hit_T_155; // @[PMP.scala:45:20, :63:58, :132:{8,61}] wire _res_ignore_T_5 = ~io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_5 = default_0 & _res_ignore_T_5; // @[PMP.scala:156:56, :164:{26,29}] wire _res_T_225 = io_pmp_2_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_26 = io_pmp_2_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_226; // @[PMP.scala:168:32] assign _res_T_226 = _GEN_26; // @[PMP.scala:168:32] wire _res_T_245; // @[PMP.scala:177:61] assign _res_T_245 = _GEN_26; // @[PMP.scala:168:32, :177:61] wire _res_T_249; // @[PMP.scala:178:63] assign _res_T_249 = _GEN_26; // @[PMP.scala:168:32, :178:63] wire _GEN_27 = io_pmp_2_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_227; // @[PMP.scala:168:32] assign _res_T_227 = _GEN_27; // @[PMP.scala:168:32] wire _res_T_254; // @[PMP.scala:177:61] assign _res_T_254 = _GEN_27; // @[PMP.scala:168:32, :177:61] wire _res_T_258; // @[PMP.scala:178:63] assign _res_T_258 = _GEN_27; // @[PMP.scala:168:32, :178:63] wire _res_T_228 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_28 = {io_pmp_2_cfg_x_0, io_pmp_2_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_30; // @[PMP.scala:174:26] assign res_hi_30 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_31; // @[PMP.scala:174:26] assign res_hi_31 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_32; // @[PMP.scala:174:26] assign res_hi_32 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_33; // @[PMP.scala:174:26] assign res_hi_33 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_34; // @[PMP.scala:174:26] assign res_hi_34 = _GEN_28; // @[PMP.scala:174:26] wire [1:0] res_hi_35; // @[PMP.scala:174:26] assign res_hi_35 = _GEN_28; // @[PMP.scala:174:26] wire [2:0] _res_T_230 = {res_hi_30, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_231 = _res_T_230 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_232 = {res_hi_31, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_233 = _res_T_232 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_234 = {res_hi_32, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_235 = _res_T_234 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_236 = {res_hi_33, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_237 = _res_T_236 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_238 = {res_hi_34, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_239 = _res_T_238 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_240 = {res_hi_35, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_241 = &_res_T_240; // @[PMP.scala:174:{26,60}] wire _res_T_242 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_243 = _res_T_242 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_244 = _res_T_243; // @[PMP.scala:177:{30,37}] wire _res_T_246 = _res_T_244 & _res_T_245; // @[PMP.scala:177:{37,48,61}] wire _GEN_29 = io_pmp_2_cfg_l_0 & res_hit_5; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_247; // @[PMP.scala:178:32] assign _res_T_247 = _GEN_29; // @[PMP.scala:178:32] wire _res_T_256; // @[PMP.scala:178:32] assign _res_T_256 = _GEN_29; // @[PMP.scala:178:32] wire _res_T_265; // @[PMP.scala:178:32] assign _res_T_265 = _GEN_29; // @[PMP.scala:178:32] wire _res_T_248 = _res_T_247; // @[PMP.scala:178:{32,39}] wire _res_T_250 = _res_T_248 & _res_T_249; // @[PMP.scala:178:{39,50,63}] wire _res_T_251 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_252 = _res_T_251 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_253 = _res_T_252; // @[PMP.scala:177:{30,37}] wire _res_T_255 = _res_T_253 & _res_T_254; // @[PMP.scala:177:{37,48,61}] wire _res_T_257 = _res_T_256; // @[PMP.scala:178:{32,39}] wire _res_T_259 = _res_T_257 & _res_T_258; // @[PMP.scala:178:{39,50,63}] wire _res_T_260 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22] wire _res_T_261 = _res_T_260 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_262 = _res_T_261; // @[PMP.scala:177:{30,37}] wire _res_T_263 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_264 = _res_T_262 & _res_T_263; // @[PMP.scala:177:{37,48,61}] wire _res_T_266 = _res_T_265; // @[PMP.scala:178:{32,39}] wire _res_T_267 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_268 = _res_T_266 & _res_T_267; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_11; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_11; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_11; // @[PMP.scala:182:26] wire res_cur_5_cfg_x; // @[PMP.scala:181:23] wire res_cur_5_cfg_w; // @[PMP.scala:181:23] wire res_cur_5_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_10 = io_pmp_2_cfg_r_0 \| res_ignore_5; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_11 = _res_cur_cfg_r_T_10; // @[PMP.scala:182:{26,40}] assign res_cur_5_cfg_r = _res_cur_cfg_r_T_11; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_10 = io_pmp_2_cfg_w_0 \| res_ignore_5; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_11 = _res_cur_cfg_w_T_10; // @[PMP.scala:183:{26,40}] assign res_cur_5_cfg_w = _res_cur_cfg_w_T_11; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_10 = io_pmp_2_cfg_x_0 \| res_ignore_5; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_11 = _res_cur_cfg_x_T_10; // @[PMP.scala:184:{26,40}] assign res_cur_5_cfg_x = _res_cur_cfg_x_T_11; // @[PMP.scala:181:23, :184:26] wire _res_T_269_cfg_l = res_hit_5 ? res_cur_5_cfg_l : _res_T_224_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_269_cfg_a = res_hit_5 ? res_cur_5_cfg_a : _res_T_224_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_x = res_hit_5 ? res_cur_5_cfg_x : _res_T_224_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_w = res_hit_5 ? res_cur_5_cfg_w : _res_T_224_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_269_cfg_r = res_hit_5 ? res_cur_5_cfg_r : _res_T_224_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_269_addr = res_hit_5 ? res_cur_5_addr : _res_T_224_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_269_mask = res_hit_5 ? res_cur_5_mask : _res_T_224_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_156 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [31:0] _res_hit_T_158 = ~_res_hit_T_157; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_159 = {_res_hit_T_158[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_160 = ~_res_hit_T_159; // @[PMP.scala:60:{27,48}] wire [31:0] _res_hit_T_161 = io_addr_0 ^ _res_hit_T_160; // @[PMP.scala:60:27, :63:47, :143:7] wire [31:0] _res_hit_T_162 = ~io_pmp_1_mask_0; // @[PMP.scala:63:54, :143:7] wire [31:0] _res_hit_T_163 = _res_hit_T_161 & _res_hit_T_162; // @[PMP.scala:63:{47,52,54}] wire _res_hit_T_164 = _res_hit_T_163 == 32'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_165 = io_pmp_1_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _GEN_30 = {io_pmp_0_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7] wire [31:0] _res_hit_T_169; // @[PMP.scala:60:36] assign _res_hit_T_169 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_183; // @[PMP.scala:60:36] assign _res_hit_T_183 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_201; // @[PMP.scala:60:36] assign _res_hit_T_201 = _GEN_30; // @[PMP.scala:60:36] wire [31:0] _res_hit_T_170 = ~_res_hit_T_169; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_171 = {_res_hit_T_170[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_172 = ~_res_hit_T_171; // @[PMP.scala:60:{27,48}] wire _res_hit_T_173 = io_addr_0 < _res_hit_T_172; // @[PMP.scala:60:27, :77:9, :143:7] wire _res_hit_T_174 = ~_res_hit_T_173; // @[PMP.scala:77:9, :88:5] wire [31:0] _res_hit_T_176 = ~_res_hit_T_175; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_177 = {_res_hit_T_176[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_178 = ~_res_hit_T_177; // @[PMP.scala:60:{27,48}] wire _res_hit_T_179 = io_addr_0 < _res_hit_T_178; // @[PMP.scala:60:27, :77:9, :143:7] wire _res_hit_T_180 = _res_hit_T_174 & _res_hit_T_179; // @[PMP.scala:77:9, :88:5, :94:48] wire _res_hit_T_181 = _res_hit_T_165 & _res_hit_T_180; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_6 = _res_hit_T_156 ? _res_hit_T_164 : _res_hit_T_181; // @[PMP.scala:45:20, :63:58, :132:{8,61}] wire _res_ignore_T_6 = ~io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_6 = default_0 & _res_ignore_T_6; // @[PMP.scala:156:56, :164:{26,29}] wire _res_T_270 = io_pmp_1_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_31 = io_pmp_1_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_271; // @[PMP.scala:168:32] assign _res_T_271 = _GEN_31; // @[PMP.scala:168:32] wire _res_T_290; // @[PMP.scala:177:61] assign _res_T_290 = _GEN_31; // @[PMP.scala:168:32, :177:61] wire _res_T_294; // @[PMP.scala:178:63] assign _res_T_294 = _GEN_31; // @[PMP.scala:168:32, :178:63] wire _GEN_32 = io_pmp_1_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_272; // @[PMP.scala:168:32] assign _res_T_272 = _GEN_32; // @[PMP.scala:168:32] wire _res_T_299; // @[PMP.scala:177:61] assign _res_T_299 = _GEN_32; // @[PMP.scala:168:32, :177:61] wire _res_T_303; // @[PMP.scala:178:63] assign _res_T_303 = _GEN_32; // @[PMP.scala:168:32, :178:63] wire _res_T_273 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_33 = {io_pmp_1_cfg_x_0, io_pmp_1_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_36; // @[PMP.scala:174:26] assign res_hi_36 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_37; // @[PMP.scala:174:26] assign res_hi_37 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_38; // @[PMP.scala:174:26] assign res_hi_38 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_39; // @[PMP.scala:174:26] assign res_hi_39 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_40; // @[PMP.scala:174:26] assign res_hi_40 = _GEN_33; // @[PMP.scala:174:26] wire [1:0] res_hi_41; // @[PMP.scala:174:26] assign res_hi_41 = _GEN_33; // @[PMP.scala:174:26] wire [2:0] _res_T_275 = {res_hi_36, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_276 = _res_T_275 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_277 = {res_hi_37, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_278 = _res_T_277 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_279 = {res_hi_38, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_280 = _res_T_279 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_281 = {res_hi_39, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_282 = _res_T_281 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_283 = {res_hi_40, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_284 = _res_T_283 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_285 = {res_hi_41, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_286 = &_res_T_285; // @[PMP.scala:174:{26,60}] wire _res_T_287 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_288 = _res_T_287 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_289 = _res_T_288; // @[PMP.scala:177:{30,37}] wire _res_T_291 = _res_T_289 & _res_T_290; // @[PMP.scala:177:{37,48,61}] wire _GEN_34 = io_pmp_1_cfg_l_0 & res_hit_6; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_292; // @[PMP.scala:178:32] assign _res_T_292 = _GEN_34; // @[PMP.scala:178:32] wire _res_T_301; // @[PMP.scala:178:32] assign _res_T_301 = _GEN_34; // @[PMP.scala:178:32] wire _res_T_310; // @[PMP.scala:178:32] assign _res_T_310 = _GEN_34; // @[PMP.scala:178:32] wire _res_T_293 = _res_T_292; // @[PMP.scala:178:{32,39}] wire _res_T_295 = _res_T_293 & _res_T_294; // @[PMP.scala:178:{39,50,63}] wire _res_T_296 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_297 = _res_T_296 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_298 = _res_T_297; // @[PMP.scala:177:{30,37}] wire _res_T_300 = _res_T_298 & _res_T_299; // @[PMP.scala:177:{37,48,61}] wire _res_T_302 = _res_T_301; // @[PMP.scala:178:{32,39}] wire _res_T_304 = _res_T_302 & _res_T_303; // @[PMP.scala:178:{39,50,63}] wire _res_T_305 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22] wire _res_T_306 = _res_T_305 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_307 = _res_T_306; // @[PMP.scala:177:{30,37}] wire _res_T_308 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_309 = _res_T_307 & _res_T_308; // @[PMP.scala:177:{37,48,61}] wire _res_T_311 = _res_T_310; // @[PMP.scala:178:{32,39}] wire _res_T_312 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_313 = _res_T_311 & _res_T_312; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_13; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_13; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_13; // @[PMP.scala:182:26] wire res_cur_6_cfg_x; // @[PMP.scala:181:23] wire res_cur_6_cfg_w; // @[PMP.scala:181:23] wire res_cur_6_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_12 = io_pmp_1_cfg_r_0 \| res_ignore_6; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_13 = _res_cur_cfg_r_T_12; // @[PMP.scala:182:{26,40}] assign res_cur_6_cfg_r = _res_cur_cfg_r_T_13; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_12 = io_pmp_1_cfg_w_0 \| res_ignore_6; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_13 = _res_cur_cfg_w_T_12; // @[PMP.scala:183:{26,40}] assign res_cur_6_cfg_w = _res_cur_cfg_w_T_13; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_12 = io_pmp_1_cfg_x_0 \| res_ignore_6; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_13 = _res_cur_cfg_x_T_12; // @[PMP.scala:184:{26,40}] assign res_cur_6_cfg_x = _res_cur_cfg_x_T_13; // @[PMP.scala:181:23, :184:26] wire _res_T_314_cfg_l = res_hit_6 ? res_cur_6_cfg_l : _res_T_269_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] _res_T_314_cfg_a = res_hit_6 ? res_cur_6_cfg_a : _res_T_269_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_x = res_hit_6 ? res_cur_6_cfg_x : _res_T_269_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_w = res_hit_6 ? res_cur_6_cfg_w : _res_T_269_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_T_314_cfg_r = res_hit_6 ? res_cur_6_cfg_r : _res_T_269_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] _res_T_314_addr = res_hit_6 ? res_cur_6_addr : _res_T_269_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] _res_T_314_mask = res_hit_6 ? res_cur_6_mask : _res_T_269_mask; // @[PMP.scala:132:8, :181:23, :185:8] wire _res_hit_T_182 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7] wire [31:0] _res_hit_T_184 = ~_res_hit_T_183; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_185 = {_res_hit_T_184[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_186 = ~_res_hit_T_185; // @[PMP.scala:60:{27,48}] wire [31:0] _res_hit_T_187 = io_addr_0 ^ _res_hit_T_186; // @[PMP.scala:60:27, :63:47, :143:7] wire [31:0] _res_hit_T_188 = ~io_pmp_0_mask_0; // @[PMP.scala:63:54, :143:7] wire [31:0] _res_hit_T_189 = _res_hit_T_187 & _res_hit_T_188; // @[PMP.scala:63:{47,52,54}] wire _res_hit_T_190 = _res_hit_T_189 == 32'h0; // @[PMP.scala:63:{52,58}] wire _res_hit_T_191 = io_pmp_0_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7] wire [31:0] _res_hit_T_202 = ~_res_hit_T_201; // @[PMP.scala:60:{29,36}] wire [31:0] _res_hit_T_203 = {_res_hit_T_202[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_T_204 = ~_res_hit_T_203; // @[PMP.scala:60:{27,48}] wire _res_hit_T_205 = io_addr_0 < _res_hit_T_204; // @[PMP.scala:60:27, :77:9, :143:7] wire _res_hit_T_206 = _res_hit_T_205; // @[PMP.scala:77:9, :94:48] wire _res_hit_T_207 = _res_hit_T_191 & _res_hit_T_206; // @[PMP.scala:46:26, :94:48, :132:61] wire res_hit_7 = _res_hit_T_182 ? _res_hit_T_190 : _res_hit_T_207; // @[PMP.scala:45:20, :63:58, :132:{8,61}] wire _res_ignore_T_7 = ~io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :164:29] wire res_ignore_7 = default_0 & _res_ignore_T_7; // @[PMP.scala:156:56, :164:{26,29}] wire _res_T_315 = io_pmp_0_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32] wire _GEN_35 = io_pmp_0_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32] wire _res_T_316; // @[PMP.scala:168:32] assign _res_T_316 = _GEN_35; // @[PMP.scala:168:32] wire _res_T_335; // @[PMP.scala:177:61] assign _res_T_335 = _GEN_35; // @[PMP.scala:168:32, :177:61] wire _res_T_339; // @[PMP.scala:178:63] assign _res_T_339 = _GEN_35; // @[PMP.scala:168:32, :178:63] wire _GEN_36 = io_pmp_0_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32] wire _res_T_317; // @[PMP.scala:168:32] assign _res_T_317 = _GEN_36; // @[PMP.scala:168:32] wire _res_T_344; // @[PMP.scala:177:61] assign _res_T_344 = _GEN_36; // @[PMP.scala:168:32, :177:61] wire _res_T_348; // @[PMP.scala:178:63] assign _res_T_348 = _GEN_36; // @[PMP.scala:168:32, :178:63] wire _res_T_318 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32] wire [1:0] _GEN_37 = {io_pmp_0_cfg_x_0, io_pmp_0_cfg_w_0}; // @[PMP.scala:143:7, :174:26] wire [1:0] res_hi_42; // @[PMP.scala:174:26] assign res_hi_42 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_43; // @[PMP.scala:174:26] assign res_hi_43 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_44; // @[PMP.scala:174:26] assign res_hi_44 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_45; // @[PMP.scala:174:26] assign res_hi_45 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_46; // @[PMP.scala:174:26] assign res_hi_46 = _GEN_37; // @[PMP.scala:174:26] wire [1:0] res_hi_47; // @[PMP.scala:174:26] assign res_hi_47 = _GEN_37; // @[PMP.scala:174:26] wire [2:0] _res_T_320 = {res_hi_42, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_321 = _res_T_320 == 3'h0; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_322 = {res_hi_43, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_323 = _res_T_322 == 3'h1; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_324 = {res_hi_44, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_325 = _res_T_324 == 3'h3; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_326 = {res_hi_45, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_327 = _res_T_326 == 3'h4; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_328 = {res_hi_46, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_329 = _res_T_328 == 3'h5; // @[PMP.scala:174:{26,60}] wire [2:0] _res_T_330 = {res_hi_47, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26] wire _res_T_331 = &_res_T_330; // @[PMP.scala:174:{26,60}] wire _res_T_332 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_333 = _res_T_332 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_334 = _res_T_333; // @[PMP.scala:177:{30,37}] wire _res_T_336 = _res_T_334 & _res_T_335; // @[PMP.scala:177:{37,48,61}] wire _GEN_38 = io_pmp_0_cfg_l_0 & res_hit_7; // @[PMP.scala:132:8, :143:7, :178:32] wire _res_T_337; // @[PMP.scala:178:32] assign _res_T_337 = _GEN_38; // @[PMP.scala:178:32] wire _res_T_346; // @[PMP.scala:178:32] assign _res_T_346 = _GEN_38; // @[PMP.scala:178:32] wire _res_T_355; // @[PMP.scala:178:32] assign _res_T_355 = _GEN_38; // @[PMP.scala:178:32] wire _res_T_338 = _res_T_337; // @[PMP.scala:178:{32,39}] wire _res_T_340 = _res_T_338 & _res_T_339; // @[PMP.scala:178:{39,50,63}] wire _res_T_341 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_342 = _res_T_341 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_343 = _res_T_342; // @[PMP.scala:177:{30,37}] wire _res_T_345 = _res_T_343 & _res_T_344; // @[PMP.scala:177:{37,48,61}] wire _res_T_347 = _res_T_346; // @[PMP.scala:178:{32,39}] wire _res_T_349 = _res_T_347 & _res_T_348; // @[PMP.scala:178:{39,50,63}] wire _res_T_350 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22] wire _res_T_351 = _res_T_350 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}] wire _res_T_352 = _res_T_351; // @[PMP.scala:177:{30,37}] wire _res_T_353 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61] wire _res_T_354 = _res_T_352 & _res_T_353; // @[PMP.scala:177:{37,48,61}] wire _res_T_356 = _res_T_355; // @[PMP.scala:178:{32,39}] wire _res_T_357 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63] wire _res_T_358 = _res_T_356 & _res_T_357; // @[PMP.scala:178:{39,50,63}] wire _res_cur_cfg_x_T_15; // @[PMP.scala:184:26] wire _res_cur_cfg_w_T_15; // @[PMP.scala:183:26] wire _res_cur_cfg_r_T_15; // @[PMP.scala:182:26] wire res_cur_7_cfg_x; // @[PMP.scala:181:23] wire res_cur_7_cfg_w; // @[PMP.scala:181:23] wire res_cur_7_cfg_r; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_14 = io_pmp_0_cfg_r_0 \| res_ignore_7; // @[PMP.scala:143:7, :164:26, :182:40] assign _res_cur_cfg_r_T_15 = _res_cur_cfg_r_T_14; // @[PMP.scala:182:{26,40}] assign res_cur_7_cfg_r = _res_cur_cfg_r_T_15; // @[PMP.scala:181:23, :182:26] wire _res_cur_cfg_w_T_14 = io_pmp_0_cfg_w_0 \| res_ignore_7; // @[PMP.scala:143:7, :164:26, :183:40] assign _res_cur_cfg_w_T_15 = _res_cur_cfg_w_T_14; // @[PMP.scala:183:{26,40}] assign res_cur_7_cfg_w = _res_cur_cfg_w_T_15; // @[PMP.scala:181:23, :183:26] wire _res_cur_cfg_x_T_14 = io_pmp_0_cfg_x_0 \| res_ignore_7; // @[PMP.scala:143:7, :164:26, :184:40] assign _res_cur_cfg_x_T_15 = _res_cur_cfg_x_T_14; // @[PMP.scala:184:{26,40}] assign res_cur_7_cfg_x = _res_cur_cfg_x_T_15; // @[PMP.scala:181:23, :184:26] wire res_cfg_l = res_hit_7 ? res_cur_7_cfg_l : _res_T_314_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8] wire [1:0] res_cfg_a = res_hit_7 ? res_cur_7_cfg_a : _res_T_314_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_x = res_hit_7 ? res_cur_7_cfg_x : _res_T_314_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_w = res_hit_7 ? res_cur_7_cfg_w : _res_T_314_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8] assign res_cfg_r = res_hit_7 ? res_cur_7_cfg_r : _res_T_314_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8] wire [29:0] res_addr = res_hit_7 ? res_cur_7_addr : _res_T_314_addr; // @[PMP.scala:132:8, :181:23, :185:8] wire [31:0] res_mask = res_hit_7 ? res_cur_7_mask : _res_T_314_mask; // @[PMP.scala:132:8, :181:23, :185:8] assign io_x_0 = res_cfg_x; // @[PMP.scala:143:7, :185:8] assign io_w_0 = res_cfg_w; // @[PMP.scala:143:7, :185:8] assign io_r_0 = res_cfg_r; // @[PMP.scala:143:7, :185:8] assign io_r = io_r_0; // @[PMP.scala:143:7] assign io_w = io_w_0; // @[PMP.scala:143:7] assign io_x = io_x_0; // @[PMP.scala:143:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_293( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_19( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [13:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire io_in_d_bits_denied = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_47 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_wo_ready_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_wo_ready_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_4_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_5_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_30 = _source_ok_T_29 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_31 = _source_ok_T_30 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_32 = _source_ok_T_31 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_33 = _source_ok_T_32 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_34 = _source_ok_T_33 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_35 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [13:0] _is_aligned_T = {2'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 14'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_37 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_43 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_38 = _source_ok_T_37 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_44 = _source_ok_T_43 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_48 = _source_ok_T_46; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = _source_ok_T_49 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_54; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_56 = _source_ok_T_55 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_60; // @[Parameters.scala:1138:31] wire _source_ok_T_61 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire _source_ok_T_62 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire _source_ok_T_63 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire _source_ok_T_64 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire _source_ok_T_65 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_68 = _source_ok_T_67 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_69 = _source_ok_T_68 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_70 = _source_ok_T_69 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_71 = _source_ok_T_70 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_71 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1110 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1110; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1110; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [13:0] address; // @[Monitor.scala:391:22] wire _T_1183 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1183; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1183; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1183; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [519:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1036 = _T_1110 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1036 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1036 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1036 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1036 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1036 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1082 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1082 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1051 = _T_1183 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1051 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1051 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1051 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [519:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1154 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1154 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1136 = _T_1183 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1136 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1136 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1136 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module MacUnit_134( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }	module OptimizationBarrier_TLBEntryData_82( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry / case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic / val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U \| in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } / Write request logic / // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) \| usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U \| in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) / Read/write response logic / val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied \|\| out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B / Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. / def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } / ReservableListBuffer logic, and associated classes. / class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /* Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. / abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /* A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index / class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) \| validSet used := (used & ~usedClr) \| usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) \| dataIsPresentSet / Reservation logic signals / val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) / Response logic signals / val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) / Reservation logic / reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } / Response logic / // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } / Response unwind logic / // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent \|\| isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind \|\| (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind \|\| (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready \|\| !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire \|\| unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /* Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) \| usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }	module dataMems_53( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File Fragmenter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} import scala.math.min import freechips.rocketchip.util.DataToAugmentedData object EarlyAck { sealed trait T case object AllPuts extends T case object PutFulls extends T case object None extends T } // minSize: minimum size of transfers supported by all outward managers // maxSize: maximum size of transfers supported after the Fragmenter is applied // alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager) // earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat // holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst // nameSuffix: appends a suffix to the module name // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize") require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize") require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize") val fragmentBits = log2Ceil(maxSize / minSize) val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0 val toggleBits = 1 val addedBits = fragmentBits + toggleBits + fullBits def expandTransfer(x: TransferSizes, op: String) = if (!x) x else { // validate that we can apply the fragmenter correctly require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})") TransferSizes(x.min, maxSize) } private def noChangeRequired = minSize == maxSize private def shrinkTransfer(x: TransferSizes) = if (!alwaysMin) x else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none private def mapManager(m: TLSlaveParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"), supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"), supportsHint = expandTransfer(m.supportsHint, "Hint")) val node = new TLAdapterNode( // We require that all the responses are mutually FIFO // Thus we need to compact all of the masters into one big master clientFn = { c => (if (noChangeRequired) c else c.v2copy( masters = Seq(TLMasterParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => if (noChangeRequired) { out <> in } else { // All managers must share a common FIFO domain (responses might end up interleaved) val manager = edgeOut.manager val managers = manager.managers val beatBytes = manager.beatBytes val fifoId = managers(0).fifoId require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _)) require (!manager.anySupportAcquireB \|\| !edgeOut.client.anySupportProbe, s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region") require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses") // We can't support devices which are cached on both sides of us require (!edgeOut.manager.anySupportAcquireB \|\| !edgeIn.client.anySupportProbe) // We can't support denied because we reassemble fragments require (!edgeOut.manager.mayDenyGet \|\| holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true") require (!edgeOut.manager.mayDenyPut \|\| earlyAck == EarlyAck.None) /* The Fragmenter is a bit tricky, because there are 5 sizes in play: * max size -- the maximum transfer size possible * orig size -- the original pre-fragmenter size * frag size -- the modified post-fragmenter size * min size -- the threshold below which frag=orig * beat size -- the amount transfered on any given beat * * The relationships are as follows: * max >= orig >= frag * max > min >= beat * It IS possible that orig <= min (then frag=orig; ie: no fragmentation) * * The fragment# (sent via TL.source) is measured in multiples of min size. * Meanwhile, to track the progress, counters measure in multiples of beat size. * * Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16. * * in.A out.A (frag#) out.D (frag#) in.D gen# ack# * get64 get16 6 ackD16 6 ackD64 12 15 * ackD16 6 ackD64 14 * ackD16 6 ackD64 13 * ackD16 6 ackD64 12 * get16 4 ackD16 4 ackD64 8 11 * ackD16 4 ackD64 10 * ackD16 4 ackD64 9 * ackD16 4 ackD64 8 * get16 2 ackD16 2 ackD64 4 7 * ackD16 2 ackD64 6 * ackD16 2 ackD64 5 * ackD16 2 ackD64 4 * get16 0 ackD16 0 ackD64 0 3 * ackD16 0 ackD64 2 * ackD16 0 ackD64 1 * ackD16 0 ackD64 0 * * get8 get8 0 ackD8 0 ackD8 0 1 * ackD8 0 ackD8 0 * * get4 get4 0 ackD4 0 ackD4 0 0 * get1 get1 0 ackD1 0 ackD1 0 0 * * put64 put16 6 15 * put64 put16 6 14 * put64 put16 6 13 * put64 put16 6 ack16 6 12 12 * put64 put16 4 11 * put64 put16 4 10 * put64 put16 4 9 * put64 put16 4 ack16 4 8 8 * put64 put16 2 7 * put64 put16 2 6 * put64 put16 2 5 * put64 put16 2 ack16 2 4 4 * put64 put16 0 3 * put64 put16 0 2 * put64 put16 0 1 * put64 put16 0 ack16 0 ack64 0 0 * * put8 put8 0 1 * put8 put8 0 ack8 0 ack8 0 0 * * put4 put4 0 ack4 0 ack4 0 0 * put1 put1 0 ack1 0 ack1 0 0 / val counterBits = log2Up(maxSize/beatBytes) val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize) // Consider the following waveform for two 4-beat bursts: // ---A----A------------ // -------D-----DDD-DDDD // Under TL rules, the second A can use the same source as the first A, // because the source is released for reuse on the first response beat. // // However, if we fragment the requests, it looks like this: // ---3210-3210--------- // -------3-----210-3210 // ... now we've broken the rules because 210 are twice inflight. // // This phenomenon means we can have essentially 2maxSize/minSize-1 // fragmented transactions in flight per original transaction source. // // To keep the source unique, we encode the beat counter in the low // bits of the source. To solve the overlap, we use a toggle bit. // Whatever toggle bit the D is reassembling, A will use the opposite. // First, handle the return path val acknum = RegInit(0.U(counterBits.W)) val dOrig = Reg(UInt()) val dToggle = RegInit(false.B) val dFragnum = out.d.bits.source(fragmentBits-1, 0) val dFirst = acknum === 0.U val dLast = dFragnum === 0.U // only for AccessAck (!Data) val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1) val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize)) val dHasData = edgeOut.hasData(out.d.bits) // calculate new acknum val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes) val acknum_size = dsizeOH1 >> log2Ceil(beatBytes) assert (!out.d.valid \|\| (acknum_fragment & acknum_size) === 0.U) val dFirst_acknum = acknum_fragment \| Mux(dHasData, acknum_size, 0.U) val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes)) // calculate the original size val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) \| dsizeOH1) when (out.d.fire) { acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement) when (dFirst) { dOrig := dFirst_size dToggle := out.d.bits.source(fragmentBits) } } // Swallow up non-data ack fragments val doEarlyAck = earlyAck match { case EarlyAck.AllPuts => true.B case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1) case EarlyAck.None => false.B } val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast) out.d.ready := in.d.ready \|\| drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged in.d.bits.source := out.d.bits.source >> addedBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig) if (edgeOut.manager.mayDenyPut) { val r_denied = Reg(Bool()) val d_denied = (!dFirst && r_denied) \|\| out.d.bits.denied when (out.d.fire) { r_denied := d_denied } in.d.bits.denied := d_denied } if (edgeOut.manager.mayDenyGet) { // Take denied only from the first beat and hold that value val d_denied = out.d.bits.denied holdUnless dFirst when (dHasData) { in.d.bits.denied := d_denied in.d.bits.corrupt := d_denied \|\| out.d.bits.corrupt } } // What maximum transfer sizes do downstream devices support? val maxArithmetics = managers.map(_.supportsArithmetic.max) val maxLogicals = managers.map(_.supportsLogical.max) val maxGets = managers.map(_.supportsGet.max) val maxPutFulls = managers.map(_.supportsPutFull.max) val maxPutPartials = managers.map(_.supportsPutPartial.max) val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0) // We assume that the request is valid => size 0 is impossible val lgMinSize = log2Ceil(minSize).U val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) // Make the request repeatable val repeater = Module(new Repeater(in.a.bits)) repeater.io.enq <> in.a val in_a = repeater.io.deq // If this is infront of a single manager, these become constants val find = manager.findFast(edgeIn.address(in_a.bits)) val maxLgArithmetic = Mux1H(find, maxLgArithmetics) val maxLgLogical = Mux1H(find, maxLgLogicals) val maxLgGet = Mux1H(find, maxLgGets) val maxLgPutFull = Mux1H(find, maxLgPutFulls) val maxLgPutPartial = Mux1H(find, maxLgPutPartials) val maxLgHint = Mux1H(find, maxLgHints) val limit = if (alwaysMin) lgMinSize else MuxLookup(in_a.bits.opcode, lgMinSize)(Array( TLMessages.PutFullData -> maxLgPutFull, TLMessages.PutPartialData -> maxLgPutPartial, TLMessages.ArithmeticData -> maxLgArithmetic, TLMessages.LogicalData -> maxLgLogical, TLMessages.Get -> maxLgGet, TLMessages.Hint -> maxLgHint)) val aOrig = in_a.bits.size val aFrag = Mux(aOrig > limit, limit, aOrig) val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize)) val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize)) val aHasData = edgeIn.hasData(in_a.bits) val aMask = Mux(aHasData, 0.U, aFragOH1) val gennum = RegInit(0.U(counterBits.W)) val aFirst = gennum === 0.U val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U) val new_gennum = ~(~old_gennum1 \| (aMask >> log2Ceil(beatBytes))) // ~(~x\|y) is width safe val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) \| (aFragOH1 >> log2Ceil(minSize))) val aLast = aFragnum === 0.U val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst)) val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None when (out.a.fire) { gennum := new_gennum } repeater.io.repeat := !aHasData && aFragnum =/= 0.U out.a <> in_a out.a.bits.address := in_a.bits.address \| ~(old_gennum1 << log2Ceil(beatBytes) \| ~aOrigOH1 \| aFragOH1 \| (minSize-1).U) out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum)) out.a.bits.size := aFrag // Optimize away some of the Repeater's registers assert (!repeater.io.full \|\| !aHasData) out.a.bits.data := in.a.bits.data val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full \|\| in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFragmenter { def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { if (minSize <= maxSize) { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix)) fragmenter.node } else { TLEphemeralNode()(ValName("no_fragmenter")) } } def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix) def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) (ram.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.1) := TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLFragmenter(ramBeatBytes, maxSize/2) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module TLInterconnectCoupler_cbus_to_l2_ctrl( // @[LazyModuleImp.scala:138:7] input clock, // @[LazyModuleImp.scala:138:7] input reset, // @[LazyModuleImp.scala:138:7] input auto_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_tl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_tl_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_tl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_tl_in_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire tlOut_d_valid; // @[MixedNode.scala:542:17] wire tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] tlOut_d_bits_data; // @[MixedNode.scala:542:17] wire tlOut_d_bits_denied; // @[MixedNode.scala:542:17] wire tlOut_d_bits_sink; // @[MixedNode.scala:542:17] wire [7:0] tlOut_d_bits_source; // @[MixedNode.scala:542:17] wire [2:0] tlOut_d_bits_size; // @[MixedNode.scala:542:17] wire [1:0] tlOut_d_bits_param; // @[MixedNode.scala:542:17] wire [2:0] tlOut_d_bits_opcode; // @[MixedNode.scala:542:17] wire tlOut_a_ready; // @[MixedNode.scala:542:17] wire _fragmenter_auto_anon_out_a_valid; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_auto_anon_out_a_bits_opcode; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_auto_anon_out_a_bits_param; // @[Fragmenter.scala:345:34] wire [1:0] _fragmenter_auto_anon_out_a_bits_size; // @[Fragmenter.scala:345:34] wire [11:0] _fragmenter_auto_anon_out_a_bits_source; // @[Fragmenter.scala:345:34] wire [25:0] _fragmenter_auto_anon_out_a_bits_address; // @[Fragmenter.scala:345:34] wire [7:0] _fragmenter_auto_anon_out_a_bits_mask; // @[Fragmenter.scala:345:34] wire [63:0] _fragmenter_auto_anon_out_a_bits_data; // @[Fragmenter.scala:345:34] wire _fragmenter_auto_anon_out_a_bits_corrupt; // @[Fragmenter.scala:345:34] wire _fragmenter_auto_anon_out_d_ready; // @[Fragmenter.scala:345:34] wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28] wire [11:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28] wire auto_buffer_out_a_ready_0 = auto_buffer_out_a_ready; // @[LazyModuleImp.scala:138:7] wire auto_buffer_out_d_valid_0 = auto_buffer_out_d_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_buffer_out_d_bits_opcode_0 = auto_buffer_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] auto_buffer_out_d_bits_size_0 = auto_buffer_out_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [11:0] auto_buffer_out_d_bits_source_0 = auto_buffer_out_d_bits_source; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_buffer_out_d_bits_data_0 = auto_buffer_out_d_bits_data; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_a_valid_0 = auto_tl_in_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_a_bits_opcode_0 = auto_tl_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_a_bits_param_0 = auto_tl_in_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_a_bits_size_0 = auto_tl_in_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_tl_in_a_bits_source_0 = auto_tl_in_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [25:0] auto_tl_in_a_bits_address_0 = auto_tl_in_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_tl_in_a_bits_mask_0 = auto_tl_in_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_tl_in_a_bits_data_0 = auto_tl_in_a_bits_data; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_a_bits_corrupt_0 = auto_tl_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_d_ready_0 = auto_tl_in_d_ready; // @[LazyModuleImp.scala:138:7] wire auto_buffer_out_d_bits_sink = 1'h0; // @[Buffer.scala:75:28] wire auto_buffer_out_d_bits_denied = 1'h0; // @[Buffer.scala:75:28] wire auto_buffer_out_d_bits_corrupt = 1'h0; // @[Buffer.scala:75:28] wire [1:0] auto_buffer_out_d_bits_param = 2'h0; // @[Buffer.scala:75:28] wire tlIn_a_ready; // @[MixedNode.scala:551:17] wire tlIn_a_valid = auto_tl_in_a_valid_0; // @[MixedNode.scala:551:17] wire [2:0] tlIn_a_bits_opcode = auto_tl_in_a_bits_opcode_0; // @[MixedNode.scala:551:17] wire [2:0] tlIn_a_bits_param = auto_tl_in_a_bits_param_0; // @[MixedNode.scala:551:17] wire [2:0] tlIn_a_bits_size = auto_tl_in_a_bits_size_0; // @[MixedNode.scala:551:17] wire [7:0] tlIn_a_bits_source = auto_tl_in_a_bits_source_0; // @[MixedNode.scala:551:17] wire [25:0] tlIn_a_bits_address = auto_tl_in_a_bits_address_0; // @[MixedNode.scala:551:17] wire [7:0] tlIn_a_bits_mask = auto_tl_in_a_bits_mask_0; // @[MixedNode.scala:551:17] wire [63:0] tlIn_a_bits_data = auto_tl_in_a_bits_data_0; // @[MixedNode.scala:551:17] wire tlIn_a_bits_corrupt = auto_tl_in_a_bits_corrupt_0; // @[MixedNode.scala:551:17] wire tlIn_d_ready = auto_tl_in_d_ready_0; // @[MixedNode.scala:551:17] wire tlIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] tlIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] tlIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] tlIn_d_bits_size; // @[MixedNode.scala:551:17] wire [7:0] tlIn_d_bits_source; // @[MixedNode.scala:551:17] wire tlIn_d_bits_sink; // @[MixedNode.scala:551:17] wire tlIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] tlIn_d_bits_data; // @[MixedNode.scala:551:17] wire tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [2:0] auto_buffer_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_buffer_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7] wire [1:0] auto_buffer_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7] wire [11:0] auto_buffer_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7] wire [25:0] auto_buffer_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_buffer_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_buffer_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7] wire auto_buffer_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] wire auto_buffer_out_a_valid_0; // @[LazyModuleImp.scala:138:7] wire auto_buffer_out_d_ready_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7] wire [1:0] auto_tl_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7] wire [2:0] auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7] wire [7:0] auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7] wire [63:0] auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] wire auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7] assign tlIn_a_ready = tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_valid = tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_opcode = tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_param = tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_size = tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_source = tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_sink = tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_denied = tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign tlIn_d_bits_data = tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] wire [2:0] tlOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] tlOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] tlOut_a_bits_size; // @[MixedNode.scala:542:17] wire [7:0] tlOut_a_bits_source; // @[MixedNode.scala:542:17] wire [25:0] tlOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] tlOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] tlOut_a_bits_data; // @[MixedNode.scala:542:17] wire tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign tlIn_d_bits_corrupt = tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] wire tlOut_a_valid; // @[MixedNode.scala:542:17] wire tlOut_d_ready; // @[MixedNode.scala:542:17] assign auto_tl_in_a_ready_0 = tlIn_a_ready; // @[MixedNode.scala:551:17] assign tlOut_a_valid = tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_opcode = tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_param = tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_size = tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_source = tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_address = tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_mask = tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_data = tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign tlOut_a_bits_corrupt = tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign tlOut_d_ready = tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_tl_in_d_valid_0 = tlIn_d_valid; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_opcode_0 = tlIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_param_0 = tlIn_d_bits_param; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_size_0 = tlIn_d_bits_size; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_source_0 = tlIn_d_bits_source; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_sink_0 = tlIn_d_bits_sink; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_denied_0 = tlIn_d_bits_denied; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_data_0 = tlIn_d_bits_data; // @[MixedNode.scala:551:17] assign auto_tl_in_d_bits_corrupt_0 = tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17] TLBuffer_a26d64s12k1z2u buffer ( // @[Buffer.scala:75:28] .clock (clock), .reset (reset), .auto_in_a_ready (_buffer_auto_in_a_ready), .auto_in_a_valid (_fragmenter_auto_anon_out_a_valid), // @[Fragmenter.scala:345:34] .auto_in_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode), // @[Fragmenter.scala:345:34] .auto_in_a_bits_param (_fragmenter_auto_anon_out_a_bits_param), // @[Fragmenter.scala:345:34] .auto_in_a_bits_size (_fragmenter_auto_anon_out_a_bits_size), // @[Fragmenter.scala:345:34] .auto_in_a_bits_source (_fragmenter_auto_anon_out_a_bits_source), // @[Fragmenter.scala:345:34] .auto_in_a_bits_address (_fragmenter_auto_anon_out_a_bits_address), // @[Fragmenter.scala:345:34] .auto_in_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask), // @[Fragmenter.scala:345:34] .auto_in_a_bits_data (_fragmenter_auto_anon_out_a_bits_data), // @[Fragmenter.scala:345:34] .auto_in_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt), // @[Fragmenter.scala:345:34] .auto_in_d_ready (_fragmenter_auto_anon_out_d_ready), // @[Fragmenter.scala:345:34] .auto_in_d_valid (_buffer_auto_in_d_valid), .auto_in_d_bits_opcode (_buffer_auto_in_d_bits_opcode), .auto_in_d_bits_param (_buffer_auto_in_d_bits_param), .auto_in_d_bits_size (_buffer_auto_in_d_bits_size), .auto_in_d_bits_source (_buffer_auto_in_d_bits_source), .auto_in_d_bits_sink (_buffer_auto_in_d_bits_sink), .auto_in_d_bits_denied (_buffer_auto_in_d_bits_denied), .auto_in_d_bits_data (_buffer_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt), .auto_out_a_ready (auto_buffer_out_a_ready_0), // @[LazyModuleImp.scala:138:7] .auto_out_a_valid (auto_buffer_out_a_valid_0), .auto_out_a_bits_opcode (auto_buffer_out_a_bits_opcode_0), .auto_out_a_bits_param (auto_buffer_out_a_bits_param_0), .auto_out_a_bits_size (auto_buffer_out_a_bits_size_0), .auto_out_a_bits_source (auto_buffer_out_a_bits_source_0), .auto_out_a_bits_address (auto_buffer_out_a_bits_address_0), .auto_out_a_bits_mask (auto_buffer_out_a_bits_mask_0), .auto_out_a_bits_data (auto_buffer_out_a_bits_data_0), .auto_out_a_bits_corrupt (auto_buffer_out_a_bits_corrupt_0), .auto_out_d_ready (auto_buffer_out_d_ready_0), .auto_out_d_valid (auto_buffer_out_d_valid_0), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_opcode (auto_buffer_out_d_bits_opcode_0), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_size (auto_buffer_out_d_bits_size_0), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_source (auto_buffer_out_d_bits_source_0), // @[LazyModuleImp.scala:138:7] .auto_out_d_bits_data (auto_buffer_out_d_bits_data_0) // @[LazyModuleImp.scala:138:7] ); // @[Buffer.scala:75:28] TLFragmenter_LLCCtrl fragmenter ( // @[Fragmenter.scala:345:34] .clock (clock), .reset (reset), .auto_anon_in_a_ready (tlOut_a_ready), .auto_anon_in_a_valid (tlOut_a_valid), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_opcode (tlOut_a_bits_opcode), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_param (tlOut_a_bits_param), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_size (tlOut_a_bits_size), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_source (tlOut_a_bits_source), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_address (tlOut_a_bits_address), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_mask (tlOut_a_bits_mask), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_data (tlOut_a_bits_data), // @[MixedNode.scala:542:17] .auto_anon_in_a_bits_corrupt (tlOut_a_bits_corrupt), // @[MixedNode.scala:542:17] .auto_anon_in_d_ready (tlOut_d_ready), // @[MixedNode.scala:542:17] .auto_anon_in_d_valid (tlOut_d_valid), .auto_anon_in_d_bits_opcode (tlOut_d_bits_opcode), .auto_anon_in_d_bits_param (tlOut_d_bits_param), .auto_anon_in_d_bits_size (tlOut_d_bits_size), .auto_anon_in_d_bits_source (tlOut_d_bits_source), .auto_anon_in_d_bits_sink (tlOut_d_bits_sink), .auto_anon_in_d_bits_denied (tlOut_d_bits_denied), .auto_anon_in_d_bits_data (tlOut_d_bits_data), .auto_anon_in_d_bits_corrupt (tlOut_d_bits_corrupt), .auto_anon_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28] .auto_anon_out_a_valid (_fragmenter_auto_anon_out_a_valid), .auto_anon_out_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (_fragmenter_auto_anon_out_a_bits_param), .auto_anon_out_a_bits_size (_fragmenter_auto_anon_out_a_bits_size), .auto_anon_out_a_bits_source (_fragmenter_auto_anon_out_a_bits_source), .auto_anon_out_a_bits_address (_fragmenter_auto_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (_fragmenter_auto_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (_fragmenter_auto_anon_out_d_ready), .auto_anon_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_opcode (_buffer_auto_in_d_bits_opcode), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_param (_buffer_auto_in_d_bits_param), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_size (_buffer_auto_in_d_bits_size), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_source (_buffer_auto_in_d_bits_source), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_sink (_buffer_auto_in_d_bits_sink), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_denied (_buffer_auto_in_d_bits_denied), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28] .auto_anon_out_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt) // @[Buffer.scala:75:28] ); // @[Fragmenter.scala:345:34] assign auto_buffer_out_a_valid = auto_buffer_out_a_valid_0; // @[LazyModuleImp.scala:138:7] assign auto_buffer_out_a_bits_opcode = auto_buffer_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7] assign auto_buffer_out_a_bits_param = auto_buffer_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7] assign auto_buffer_out_a_bits_size = auto_buffer_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7] assign auto_buffer_out_a_bits_source = auto_buffer_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7] assign auto_buffer_out_a_bits_address = auto_buffer_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7] assign auto_buffer_out_a_bits_mask = auto_buffer_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7] assign auto_buffer_out_a_bits_data = auto_buffer_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7] assign auto_buffer_out_a_bits_corrupt = auto_buffer_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] assign auto_buffer_out_d_ready = auto_buffer_out_d_ready_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_a_ready = auto_tl_in_a_ready_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_valid = auto_tl_in_d_valid_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_opcode = auto_tl_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_param = auto_tl_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_size = auto_tl_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_source = auto_tl_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_sink = auto_tl_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_denied = auto_tl_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_data = auto_tl_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7] assign auto_tl_in_d_bits_corrupt = auto_tl_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Metadata.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.constants.MemoryOpConstants import freechips.rocketchip.util._ object ClientStates { val width = 2 def Nothing = 0.U(width.W) def Branch = 1.U(width.W) def Trunk = 2.U(width.W) def Dirty = 3.U(width.W) def hasReadPermission(state: UInt): Bool = state > Nothing def hasWritePermission(state: UInt): Bool = state > Branch } object MemoryOpCategories extends MemoryOpConstants { def wr = Cat(true.B, true.B) // Op actually writes def wi = Cat(false.B, true.B) // Future op will write def rd = Cat(false.B, false.B) // Op only reads def categorize(cmd: UInt): UInt = { val cat = Cat(isWrite(cmd), isWriteIntent(cmd)) //assert(cat.isOneOf(wr,wi,rd), "Could not categorize command.") cat } } /* Stores the client-side coherence information, * such as permissions on the data and whether the data is dirty. * Its API can be used to make TileLink messages in response to * memory operations, cache control oeprations, or Probe messages. / class ClientMetadata extends Bundle { /* Actual state information stored in this bundle / val state = UInt(ClientStates.width.W) /* Metadata equality / def ===(rhs: UInt): Bool = state === rhs def ===(rhs: ClientMetadata): Bool = state === rhs.state def =/=(rhs: ClientMetadata): Bool = !this.===(rhs) /* Is the block's data present in this cache / def isValid(dummy: Int = 0): Bool = state > ClientStates.Nothing /* Determine whether this cmd misses, and the new state (on hit) or param to be sent (on miss) / private def growStarter(cmd: UInt): (Bool, UInt) = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) MuxTLookup(Cat(c, state), (false.B, 0.U), Seq( //(effect, am now) -> (was a hit, next) Cat(rd, Dirty) -> (true.B, Dirty), Cat(rd, Trunk) -> (true.B, Trunk), Cat(rd, Branch) -> (true.B, Branch), Cat(wi, Dirty) -> (true.B, Dirty), Cat(wi, Trunk) -> (true.B, Trunk), Cat(wr, Dirty) -> (true.B, Dirty), Cat(wr, Trunk) -> (true.B, Dirty), //(effect, am now) -> (was a miss, param) Cat(rd, Nothing) -> (false.B, NtoB), Cat(wi, Branch) -> (false.B, BtoT), Cat(wi, Nothing) -> (false.B, NtoT), Cat(wr, Branch) -> (false.B, BtoT), Cat(wr, Nothing) -> (false.B, NtoT))) } /* Determine what state to go to after miss based on Grant param * For now, doesn't depend on state (which may have been Probed). / private def growFinisher(cmd: UInt, param: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) //assert(c === rd \|\| param === toT, "Client was expecting trunk permissions.") MuxLookup(Cat(c, param), Nothing)(Seq( //(effect param) -> (next) Cat(rd, toB) -> Branch, Cat(rd, toT) -> Trunk, Cat(wi, toT) -> Trunk, Cat(wr, toT) -> Dirty)) } /* Does this cache have permissions on this block sufficient to perform op, * and what to do next (Acquire message param or updated metadata). / def onAccess(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = growStarter(cmd) (r._1, r._2, ClientMetadata(r._2)) } /* Does a secondary miss on the block require another Acquire message / def onSecondaryAccess(first_cmd: UInt, second_cmd: UInt): (Bool, Bool, UInt, ClientMetadata, UInt) = { import MemoryOpCategories._ val r1 = growStarter(first_cmd) val r2 = growStarter(second_cmd) val needs_second_acq = isWriteIntent(second_cmd) && !isWriteIntent(first_cmd) val hit_again = r1._1 && r2._1 val dirties = categorize(second_cmd) === wr val biggest_grow_param = Mux(dirties, r2._2, r1._2) val dirtiest_state = ClientMetadata(biggest_grow_param) val dirtiest_cmd = Mux(dirties, second_cmd, first_cmd) (needs_second_acq, hit_again, biggest_grow_param, dirtiest_state, dirtiest_cmd) } /* Metadata change on a returned Grant / def onGrant(cmd: UInt, param: UInt): ClientMetadata = ClientMetadata(growFinisher(cmd, param)) /* Determine what state to go to based on Probe param / private def shrinkHelper(param: UInt): (Bool, UInt, UInt) = { import ClientStates._ import TLPermissions._ MuxTLookup(Cat(param, state), (false.B, 0.U, 0.U), Seq( //(wanted, am now) -> (hasDirtyData resp, next) Cat(toT, Dirty) -> (true.B, TtoT, Trunk), Cat(toT, Trunk) -> (false.B, TtoT, Trunk), Cat(toT, Branch) -> (false.B, BtoB, Branch), Cat(toT, Nothing) -> (false.B, NtoN, Nothing), Cat(toB, Dirty) -> (true.B, TtoB, Branch), Cat(toB, Trunk) -> (false.B, TtoB, Branch), // Policy: Don't notify on clean downgrade Cat(toB, Branch) -> (false.B, BtoB, Branch), Cat(toB, Nothing) -> (false.B, NtoN, Nothing), Cat(toN, Dirty) -> (true.B, TtoN, Nothing), Cat(toN, Trunk) -> (false.B, TtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Branch) -> (false.B, BtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Nothing) -> (false.B, NtoN, Nothing))) } /* Translate cache control cmds into Probe param / private def cmdToPermCap(cmd: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ MuxLookup(cmd, toN)(Seq( M_FLUSH -> toN, M_PRODUCE -> toB, M_CLEAN -> toT)) } def onCacheControl(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(cmdToPermCap(cmd)) (r._1, r._2, ClientMetadata(r._3)) } def onProbe(param: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(param) (r._1, r._2, ClientMetadata(r._3)) } } /* Factories for ClientMetadata, including on reset / object ClientMetadata { def apply(perm: UInt) = { val meta = Wire(new ClientMetadata) meta.state := perm meta } def onReset = ClientMetadata(ClientStates.Nothing) def maximum = ClientMetadata(ClientStates.Dirty) } File Replacement.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import freechips.rocketchip.util.property.cover abstract class ReplacementPolicy { def nBits: Int def perSet: Boolean def way: UInt def miss: Unit def hit: Unit def access(touch_way: UInt): Unit def access(touch_ways: Seq[Valid[UInt]]): Unit def state_read: UInt def get_next_state(state: UInt, touch_way: UInt): UInt def get_next_state(state: UInt, touch_ways: Seq[Valid[UInt]]): UInt = { touch_ways.foldLeft(state)((prev, touch_way) => Mux(touch_way.valid, get_next_state(prev, touch_way.bits), prev)) } def get_replace_way(state: UInt): UInt } object ReplacementPolicy { def fromString(s: String, n_ways: Int): ReplacementPolicy = s.toLowerCase match { case "random" => new RandomReplacement(n_ways) case "lru" => new TrueLRU(n_ways) case "plru" => new PseudoLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } } class RandomReplacement(n_ways: Int) extends ReplacementPolicy { private val replace = Wire(Bool()) replace := false.B def nBits = 16 def perSet = false private val lfsr = LFSR(nBits, replace) def state_read = WireDefault(lfsr) def way = Random(n_ways, lfsr) def miss = replace := true.B def hit = {} def access(touch_way: UInt) = {} def access(touch_ways: Seq[Valid[UInt]]) = {} def get_next_state(state: UInt, touch_way: UInt) = 0.U //DontCare def get_replace_way(state: UInt) = way } abstract class SeqReplacementPolicy { def access(set: UInt): Unit def update(valid: Bool, hit: Bool, set: UInt, way: UInt): Unit def way: UInt } abstract class SetAssocReplacementPolicy { def access(set: UInt, touch_way: UInt): Unit def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]): Unit def way(set: UInt): UInt } class SeqRandom(n_ways: Int) extends SeqReplacementPolicy { val logic = new RandomReplacement(n_ways) def access(set: UInt) = { } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { when (valid && !hit) { logic.miss } } def way = logic.way } class TrueLRU(n_ways: Int) extends ReplacementPolicy { // True LRU replacement policy, using a triangular matrix to track which sets are more recently used than others. // The matrix is packed into a single UInt (or Bits). Example 4-way (6-bits): // [5] - 3 more recent than 2 // [4] - 3 more recent than 1 // [3] - 2 more recent than 1 // [2] - 3 more recent than 0 // [1] - 2 more recent than 0 // [0] - 1 more recent than 0 def nBits = (n_ways (n_ways-1)) / 2 def perSet = true private val state_reg = RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) private def extractMRUVec(state: UInt): Seq[UInt] = { // Extract per-way information about which higher-indexed ways are more recently used val moreRecentVec = Wire(Vec(n_ways-1, UInt(n_ways.W))) var lsb = 0 for (i <- 0 until n_ways-1) { moreRecentVec(i) := Cat(state(lsb+n_ways-i-2,lsb), 0.U((i+1).W)) lsb = lsb + (n_ways - i - 1) } moreRecentVec } def get_next_state(state: UInt, touch_way: UInt): UInt = { val nextState = Wire(Vec(n_ways-1, UInt(n_ways.W))) val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix val wayDec = UIntToOH(touch_way, n_ways) // Compute next value of triangular matrix // set the touched way as more recent than every other way nextState.zipWithIndex.map { case (e, i) => e := Mux(i.U === touch_way, 0.U(n_ways.W), moreRecentVec(i) \| wayDec) } nextState.zipWithIndex.tail.foldLeft((nextState.head.apply(n_ways-1,1),0)) { case ((pe,pi),(ce,ci)) => (Cat(ce.apply(n_ways-1,ci+1), pe), ci) }._1 } def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"LRU_UpdateCount$i", s"LRU Update $i simultaneous") } } def get_replace_way(state: UInt): UInt = { val moreRecentVec = extractMRUVec(state) // reconstruct lower triangular matrix // For each way, determine if all other ways are more recent val mruWayDec = (0 until n_ways).map { i => val upperMoreRecent = (if (i == n_ways-1) true.B else moreRecentVec(i).apply(n_ways-1,i+1).andR) val lowerMoreRecent = (if (i == 0) true.B else moreRecentVec.map(e => !e(i)).reduce(_ && _)) upperMoreRecent && lowerMoreRecent } OHToUInt(mruWayDec) } def way = get_replace_way(state_reg) def miss = access(way) def hit = {} @deprecated("replace 'replace' with 'way' from abstract class ReplacementPolicy","Rocket Chip 2020.05") def replace: UInt = way } class PseudoLRU(n_ways: Int) extends ReplacementPolicy { // Pseudo-LRU tree algorithm: https://en.wikipedia.org/wiki/Pseudo-LRU#Tree-PLRU // // // - bits storage example for 4-way PLRU binary tree: // bit[2]: ways 3+2 older than ways 1+0 // / \ // bit[1]: way 3 older than way 2 bit[0]: way 1 older than way 0 // // // - bits storage example for 3-way PLRU binary tree: // bit[1]: way 2 older than ways 1+0 // \ // bit[0]: way 1 older than way 0 // // // - bits storage example for 8-way PLRU binary tree: // bit[6]: ways 7-4 older than ways 3-0 // / \ // bit[5]: ways 7+6 > 5+4 bit[2]: ways 3+2 > 1+0 // / \ / \ // bit[4]: way 7>6 bit[3]: way 5>4 bit[1]: way 3>2 bit[0]: way 1>0 def nBits = n_ways - 1 def perSet = true private val state_reg = if (nBits == 0) Reg(UInt(0.W)) else RegInit(0.U(nBits.W)) def state_read = WireDefault(state_reg) def access(touch_way: UInt): Unit = { state_reg := get_next_state(state_reg, touch_way) } def access(touch_ways: Seq[Valid[UInt]]): Unit = { when (touch_ways.map(_.valid).orR) { state_reg := get_next_state(state_reg, touch_ways) } for (i <- 1 until touch_ways.size) { cover(PopCount(touch_ways.map(_.valid)) === i.U, s"PLRU_UpdateCount$i", s"PLRU Update $i simultaneous") } } /** @param state state_reg bits for this sub-tree * @param touch_way touched way encoded value bits for this sub-tree * @param tree_nways number of ways in this sub-tree / def get_next_state(state: UInt, touch_way: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") require(touch_way.getWidth == (log2Ceil(tree_nways) max 1), s"wrong encoded way width ${touch_way.getWidth} for $tree_nways ways") if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val set_left_older = !touch_way(log2Ceil(tree_nways)-1) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(set_left_older, Mux(set_left_older, left_subtree_state, // if setting left sub-tree as older, do NOT recurse into left sub-tree get_next_state(left_subtree_state, touch_way.extract(log2Ceil(left_nways)-1,0), left_nways)), // recurse left if newer Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(set_left_older, Mux(set_left_older, get_next_state(right_subtree_state, touch_way(log2Ceil(right_nways)-1,0), right_nways), // recurse right if newer right_subtree_state)) // if setting right sub-tree as older, do NOT recurse into right sub-tree } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so set the single state bit opposite of the lsb of the touched way encoded value !touch_way(0) } else { // tree_nways <= 1 // we are at an empty node in an empty tree for 1 way, so return single zero bit for Chisel (no zero-width wires) 0.U(1.W) } } def get_next_state(state: UInt, touch_way: UInt): UInt = { val touch_way_sized = if (touch_way.getWidth < log2Ceil(n_ways)) touch_way.padTo (log2Ceil(n_ways)) else touch_way.extract(log2Ceil(n_ways)-1,0) get_next_state(state, touch_way_sized, n_ways) } /* @param state state_reg bits for this sub-tree * @param tree_nways number of ways in this sub-tree / def get_replace_way(state: UInt, tree_nways: Int): UInt = { require(state.getWidth == (tree_nways-1), s"wrong state bits width ${state.getWidth} for $tree_nways ways") // this algorithm recursively descends the binary tree, filling in the way-to-replace encoded value from msb to lsb if (tree_nways > 2) { // we are at a branching node in the tree, so recurse val right_nways: Int = 1 << (log2Ceil(tree_nways) - 1) // number of ways in the right sub-tree val left_nways: Int = tree_nways - right_nways // number of ways in the left sub-tree val left_subtree_older = state(tree_nways-2) val left_subtree_state = state.extract(tree_nways-3, right_nways-1) val right_subtree_state = state(right_nways-2, 0) if (left_nways > 1) { // we are at a branching node in the tree with both left and right sub-trees, so recurse both sub-trees Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, recurse left, else recurse right get_replace_way(left_subtree_state, left_nways), // recurse left get_replace_way(right_subtree_state, right_nways))) // recurse right } else { // we are at a branching node in the tree with only a right sub-tree, so recurse only right sub-tree Cat(left_subtree_older, // return the top state bit (current tree node) as msb of the way-to-replace encoded value Mux(left_subtree_older, // if left sub-tree is older, return and do not recurse right 0.U(1.W), get_replace_way(right_subtree_state, right_nways))) // recurse right } } else if (tree_nways == 2) { // we are at a leaf node at the end of the tree, so just return the single state bit as lsb of the way-to-replace encoded value state(0) } else { // tree_nways <= 1 // we are at an empty node in an unbalanced tree for non-power-of-2 ways, so return single zero bit as lsb of the way-to-replace encoded value 0.U(1.W) } } def get_replace_way(state: UInt): UInt = get_replace_way(state, n_ways) def way = get_replace_way(state_reg) def miss = access(way) def hit = {} } class SeqPLRU(n_sets: Int, n_ways: Int) extends SeqReplacementPolicy { val logic = new PseudoLRU(n_ways) val state = SyncReadMem(n_sets, UInt(logic.nBits.W)) val current_state = Wire(UInt(logic.nBits.W)) val next_state = Wire(UInt(logic.nBits.W)) val plru_way = logic.get_replace_way(current_state) def access(set: UInt) = { current_state := state.read(set) } def update(valid: Bool, hit: Bool, set: UInt, way: UInt) = { val update_way = Mux(hit, way, plru_way) next_state := logic.get_next_state(current_state, update_way) when (valid) { state.write(set, next_state) } } def way = plru_way } class SetAssocLRU(n_sets: Int, n_ways: Int, policy: String) extends SetAssocReplacementPolicy { val logic = policy.toLowerCase match { case "plru" => new PseudoLRU(n_ways) case "lru" => new TrueLRU(n_ways) case t => throw new IllegalArgumentException(s"unknown Replacement Policy type $t") } val state_vec = if (logic.nBits == 0) Reg(Vec(n_sets, UInt(logic.nBits.W))) // Work around elaboration error on following line else RegInit(VecInit(Seq.fill(n_sets)(0.U(logic.nBits.W)))) def access(set: UInt, touch_way: UInt) = { state_vec(set) := logic.get_next_state(state_vec(set), touch_way) } def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]) = { require(sets.size == touch_ways.size, "internal consistency check: should be same number of simultaneous updates for sets and touch_ways") for (set <- 0 until n_sets) { val set_touch_ways = (sets zip touch_ways).map { case (touch_set, touch_way) => Pipe(touch_way.valid && (touch_set === set.U), touch_way.bits, 0)} when (set_touch_ways.map(_.valid).orR) { state_vec(set) := logic.get_next_state(state_vec(set), set_touch_ways) } } } def way(set: UInt) = logic.get_replace_way(state_vec(set)) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class PLRUTest(n_ways: Int, timeout: Int = 500) extends UnitTest(timeout) { val plru = new PseudoLRU(n_ways) // step io.finished := RegNext(true.B, false.B) val get_replace_ways = (0 until (1 << (n_ways-1))).map(state => plru.get_replace_way(state = state.U((n_ways-1).W))) val get_next_states = (0 until (1 << (n_ways-1))).map(state => (0 until n_ways).map(way => plru.get_next_state (state = state.U((n_ways-1).W), touch_way = way.U(log2Ceil(n_ways).W)))) n_ways match { case 2 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_next_states(0)(0) === 1.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=1 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 0.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=0 actual=%d", get_next_states(0)(1)) assert(get_next_states(1)(0) === 1.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=1 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 0.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=0 actual=%d", get_next_states(1)(1)) } case 3 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=2 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=2 actual=%d", get_replace_ways(3)) assert(get_next_states(0)(0) === 3.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=3 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 2.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=2 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 0.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=0 actual=%d", get_next_states(0)(2)) assert(get_next_states(1)(0) === 3.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=3 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 2.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=2 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 1.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=1 actual=%d", get_next_states(1)(2)) assert(get_next_states(2)(0) === 3.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=3 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 2.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=2 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 0.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=0 actual=%d", get_next_states(2)(2)) assert(get_next_states(3)(0) === 3.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=3 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 2.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=2 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 1.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=1 actual=%d", get_next_states(3)(2)) } case 4 => { assert(get_replace_ways(0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=0: expected=0 actual=%d", get_replace_ways(0)) assert(get_replace_ways(1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=1: expected=1 actual=%d", get_replace_ways(1)) assert(get_replace_ways(2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=2: expected=0 actual=%d", get_replace_ways(2)) assert(get_replace_ways(3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=3: expected=1 actual=%d", get_replace_ways(3)) assert(get_replace_ways(4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=4: expected=2 actual=%d", get_replace_ways(4)) assert(get_replace_ways(5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=5: expected=2 actual=%d", get_replace_ways(5)) assert(get_replace_ways(6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=6: expected=3 actual=%d", get_replace_ways(6)) assert(get_replace_ways(7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=7: expected=3 actual=%d", get_replace_ways(7)) assert(get_next_states(0)(0) === 5.U(plru.nBits.W), s"get_next_state state=0 way=0: expected=5 actual=%d", get_next_states(0)(0)) assert(get_next_states(0)(1) === 4.U(plru.nBits.W), s"get_next_state state=0 way=1: expected=4 actual=%d", get_next_states(0)(1)) assert(get_next_states(0)(2) === 2.U(plru.nBits.W), s"get_next_state state=0 way=2: expected=2 actual=%d", get_next_states(0)(2)) assert(get_next_states(0)(3) === 0.U(plru.nBits.W), s"get_next_state state=0 way=3: expected=0 actual=%d", get_next_states(0)(3)) assert(get_next_states(1)(0) === 5.U(plru.nBits.W), s"get_next_state state=1 way=0: expected=5 actual=%d", get_next_states(1)(0)) assert(get_next_states(1)(1) === 4.U(plru.nBits.W), s"get_next_state state=1 way=1: expected=4 actual=%d", get_next_states(1)(1)) assert(get_next_states(1)(2) === 3.U(plru.nBits.W), s"get_next_state state=1 way=2: expected=3 actual=%d", get_next_states(1)(2)) assert(get_next_states(1)(3) === 1.U(plru.nBits.W), s"get_next_state state=1 way=3: expected=1 actual=%d", get_next_states(1)(3)) assert(get_next_states(2)(0) === 7.U(plru.nBits.W), s"get_next_state state=2 way=0: expected=7 actual=%d", get_next_states(2)(0)) assert(get_next_states(2)(1) === 6.U(plru.nBits.W), s"get_next_state state=2 way=1: expected=6 actual=%d", get_next_states(2)(1)) assert(get_next_states(2)(2) === 2.U(plru.nBits.W), s"get_next_state state=2 way=2: expected=2 actual=%d", get_next_states(2)(2)) assert(get_next_states(2)(3) === 0.U(plru.nBits.W), s"get_next_state state=2 way=3: expected=0 actual=%d", get_next_states(2)(3)) assert(get_next_states(3)(0) === 7.U(plru.nBits.W), s"get_next_state state=3 way=0: expected=7 actual=%d", get_next_states(3)(0)) assert(get_next_states(3)(1) === 6.U(plru.nBits.W), s"get_next_state state=3 way=1: expected=6 actual=%d", get_next_states(3)(1)) assert(get_next_states(3)(2) === 3.U(plru.nBits.W), s"get_next_state state=3 way=2: expected=3 actual=%d", get_next_states(3)(2)) assert(get_next_states(3)(3) === 1.U(plru.nBits.W), s"get_next_state state=3 way=3: expected=1 actual=%d", get_next_states(3)(3)) assert(get_next_states(4)(0) === 5.U(plru.nBits.W), s"get_next_state state=4 way=0: expected=5 actual=%d", get_next_states(4)(0)) assert(get_next_states(4)(1) === 4.U(plru.nBits.W), s"get_next_state state=4 way=1: expected=4 actual=%d", get_next_states(4)(1)) assert(get_next_states(4)(2) === 2.U(plru.nBits.W), s"get_next_state state=4 way=2: expected=2 actual=%d", get_next_states(4)(2)) assert(get_next_states(4)(3) === 0.U(plru.nBits.W), s"get_next_state state=4 way=3: expected=0 actual=%d", get_next_states(4)(3)) assert(get_next_states(5)(0) === 5.U(plru.nBits.W), s"get_next_state state=5 way=0: expected=5 actual=%d", get_next_states(5)(0)) assert(get_next_states(5)(1) === 4.U(plru.nBits.W), s"get_next_state state=5 way=1: expected=4 actual=%d", get_next_states(5)(1)) assert(get_next_states(5)(2) === 3.U(plru.nBits.W), s"get_next_state state=5 way=2: expected=3 actual=%d", get_next_states(5)(2)) assert(get_next_states(5)(3) === 1.U(plru.nBits.W), s"get_next_state state=5 way=3: expected=1 actual=%d", get_next_states(5)(3)) assert(get_next_states(6)(0) === 7.U(plru.nBits.W), s"get_next_state state=6 way=0: expected=7 actual=%d", get_next_states(6)(0)) assert(get_next_states(6)(1) === 6.U(plru.nBits.W), s"get_next_state state=6 way=1: expected=6 actual=%d", get_next_states(6)(1)) assert(get_next_states(6)(2) === 2.U(plru.nBits.W), s"get_next_state state=6 way=2: expected=2 actual=%d", get_next_states(6)(2)) assert(get_next_states(6)(3) === 0.U(plru.nBits.W), s"get_next_state state=6 way=3: expected=0 actual=%d", get_next_states(6)(3)) assert(get_next_states(7)(0) === 7.U(plru.nBits.W), s"get_next_state state=7 way=0: expected=7 actual=%d", get_next_states(7)(0)) assert(get_next_states(7)(1) === 6.U(plru.nBits.W), s"get_next_state state=7 way=5: expected=6 actual=%d", get_next_states(7)(1)) assert(get_next_states(7)(2) === 3.U(plru.nBits.W), s"get_next_state state=7 way=2: expected=3 actual=%d", get_next_states(7)(2)) assert(get_next_states(7)(3) === 1.U(plru.nBits.W), s"get_next_state state=7 way=3: expected=1 actual=%d", get_next_states(7)(3)) } case 5 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=4 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=4 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=4 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=4 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=4 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=4 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=4 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=4 actual=%d", get_replace_ways(15)) assert(get_next_states( 0)(0) === 13.U(plru.nBits.W), s"get_next_state state=00 way=0: expected=13 actual=%d", get_next_states( 0)(0)) assert(get_next_states( 0)(1) === 12.U(plru.nBits.W), s"get_next_state state=00 way=1: expected=12 actual=%d", get_next_states( 0)(1)) assert(get_next_states( 0)(2) === 10.U(plru.nBits.W), s"get_next_state state=00 way=2: expected=10 actual=%d", get_next_states( 0)(2)) assert(get_next_states( 0)(3) === 8.U(plru.nBits.W), s"get_next_state state=00 way=3: expected=08 actual=%d", get_next_states( 0)(3)) assert(get_next_states( 0)(4) === 0.U(plru.nBits.W), s"get_next_state state=00 way=4: expected=00 actual=%d", get_next_states( 0)(4)) assert(get_next_states( 1)(0) === 13.U(plru.nBits.W), s"get_next_state state=01 way=0: expected=13 actual=%d", get_next_states( 1)(0)) assert(get_next_states( 1)(1) === 12.U(plru.nBits.W), s"get_next_state state=01 way=1: expected=12 actual=%d", get_next_states( 1)(1)) assert(get_next_states( 1)(2) === 11.U(plru.nBits.W), s"get_next_state state=01 way=2: expected=11 actual=%d", get_next_states( 1)(2)) assert(get_next_states( 1)(3) === 9.U(plru.nBits.W), s"get_next_state state=01 way=3: expected=09 actual=%d", get_next_states( 1)(3)) assert(get_next_states( 1)(4) === 1.U(plru.nBits.W), s"get_next_state state=01 way=4: expected=01 actual=%d", get_next_states( 1)(4)) assert(get_next_states( 2)(0) === 15.U(plru.nBits.W), s"get_next_state state=02 way=0: expected=15 actual=%d", get_next_states( 2)(0)) assert(get_next_states( 2)(1) === 14.U(plru.nBits.W), s"get_next_state state=02 way=1: expected=14 actual=%d", get_next_states( 2)(1)) assert(get_next_states( 2)(2) === 10.U(plru.nBits.W), s"get_next_state state=02 way=2: expected=10 actual=%d", get_next_states( 2)(2)) assert(get_next_states( 2)(3) === 8.U(plru.nBits.W), s"get_next_state state=02 way=3: expected=08 actual=%d", get_next_states( 2)(3)) assert(get_next_states( 2)(4) === 2.U(plru.nBits.W), s"get_next_state state=02 way=4: expected=02 actual=%d", get_next_states( 2)(4)) assert(get_next_states( 3)(0) === 15.U(plru.nBits.W), s"get_next_state state=03 way=0: expected=15 actual=%d", get_next_states( 3)(0)) assert(get_next_states( 3)(1) === 14.U(plru.nBits.W), s"get_next_state state=03 way=1: expected=14 actual=%d", get_next_states( 3)(1)) assert(get_next_states( 3)(2) === 11.U(plru.nBits.W), s"get_next_state state=03 way=2: expected=11 actual=%d", get_next_states( 3)(2)) assert(get_next_states( 3)(3) === 9.U(plru.nBits.W), s"get_next_state state=03 way=3: expected=09 actual=%d", get_next_states( 3)(3)) assert(get_next_states( 3)(4) === 3.U(plru.nBits.W), s"get_next_state state=03 way=4: expected=03 actual=%d", get_next_states( 3)(4)) assert(get_next_states( 4)(0) === 13.U(plru.nBits.W), s"get_next_state state=04 way=0: expected=13 actual=%d", get_next_states( 4)(0)) assert(get_next_states( 4)(1) === 12.U(plru.nBits.W), s"get_next_state state=04 way=1: expected=12 actual=%d", get_next_states( 4)(1)) assert(get_next_states( 4)(2) === 10.U(plru.nBits.W), s"get_next_state state=04 way=2: expected=10 actual=%d", get_next_states( 4)(2)) assert(get_next_states( 4)(3) === 8.U(plru.nBits.W), s"get_next_state state=04 way=3: expected=08 actual=%d", get_next_states( 4)(3)) assert(get_next_states( 4)(4) === 4.U(plru.nBits.W), s"get_next_state state=04 way=4: expected=04 actual=%d", get_next_states( 4)(4)) assert(get_next_states( 5)(0) === 13.U(plru.nBits.W), s"get_next_state state=05 way=0: expected=13 actual=%d", get_next_states( 5)(0)) assert(get_next_states( 5)(1) === 12.U(plru.nBits.W), s"get_next_state state=05 way=1: expected=12 actual=%d", get_next_states( 5)(1)) assert(get_next_states( 5)(2) === 11.U(plru.nBits.W), s"get_next_state state=05 way=2: expected=11 actual=%d", get_next_states( 5)(2)) assert(get_next_states( 5)(3) === 9.U(plru.nBits.W), s"get_next_state state=05 way=3: expected=09 actual=%d", get_next_states( 5)(3)) assert(get_next_states( 5)(4) === 5.U(plru.nBits.W), s"get_next_state state=05 way=4: expected=05 actual=%d", get_next_states( 5)(4)) assert(get_next_states( 6)(0) === 15.U(plru.nBits.W), s"get_next_state state=06 way=0: expected=15 actual=%d", get_next_states( 6)(0)) assert(get_next_states( 6)(1) === 14.U(plru.nBits.W), s"get_next_state state=06 way=1: expected=14 actual=%d", get_next_states( 6)(1)) assert(get_next_states( 6)(2) === 10.U(plru.nBits.W), s"get_next_state state=06 way=2: expected=10 actual=%d", get_next_states( 6)(2)) assert(get_next_states( 6)(3) === 8.U(plru.nBits.W), s"get_next_state state=06 way=3: expected=08 actual=%d", get_next_states( 6)(3)) assert(get_next_states( 6)(4) === 6.U(plru.nBits.W), s"get_next_state state=06 way=4: expected=06 actual=%d", get_next_states( 6)(4)) assert(get_next_states( 7)(0) === 15.U(plru.nBits.W), s"get_next_state state=07 way=0: expected=15 actual=%d", get_next_states( 7)(0)) assert(get_next_states( 7)(1) === 14.U(plru.nBits.W), s"get_next_state state=07 way=5: expected=14 actual=%d", get_next_states( 7)(1)) assert(get_next_states( 7)(2) === 11.U(plru.nBits.W), s"get_next_state state=07 way=2: expected=11 actual=%d", get_next_states( 7)(2)) assert(get_next_states( 7)(3) === 9.U(plru.nBits.W), s"get_next_state state=07 way=3: expected=09 actual=%d", get_next_states( 7)(3)) assert(get_next_states( 7)(4) === 7.U(plru.nBits.W), s"get_next_state state=07 way=4: expected=07 actual=%d", get_next_states( 7)(4)) assert(get_next_states( 8)(0) === 13.U(plru.nBits.W), s"get_next_state state=08 way=0: expected=13 actual=%d", get_next_states( 8)(0)) assert(get_next_states( 8)(1) === 12.U(plru.nBits.W), s"get_next_state state=08 way=1: expected=12 actual=%d", get_next_states( 8)(1)) assert(get_next_states( 8)(2) === 10.U(plru.nBits.W), s"get_next_state state=08 way=2: expected=10 actual=%d", get_next_states( 8)(2)) assert(get_next_states( 8)(3) === 8.U(plru.nBits.W), s"get_next_state state=08 way=3: expected=08 actual=%d", get_next_states( 8)(3)) assert(get_next_states( 8)(4) === 0.U(plru.nBits.W), s"get_next_state state=08 way=4: expected=00 actual=%d", get_next_states( 8)(4)) assert(get_next_states( 9)(0) === 13.U(plru.nBits.W), s"get_next_state state=09 way=0: expected=13 actual=%d", get_next_states( 9)(0)) assert(get_next_states( 9)(1) === 12.U(plru.nBits.W), s"get_next_state state=09 way=1: expected=12 actual=%d", get_next_states( 9)(1)) assert(get_next_states( 9)(2) === 11.U(plru.nBits.W), s"get_next_state state=09 way=2: expected=11 actual=%d", get_next_states( 9)(2)) assert(get_next_states( 9)(3) === 9.U(plru.nBits.W), s"get_next_state state=09 way=3: expected=09 actual=%d", get_next_states( 9)(3)) assert(get_next_states( 9)(4) === 1.U(plru.nBits.W), s"get_next_state state=09 way=4: expected=01 actual=%d", get_next_states( 9)(4)) assert(get_next_states(10)(0) === 15.U(plru.nBits.W), s"get_next_state state=10 way=0: expected=15 actual=%d", get_next_states(10)(0)) assert(get_next_states(10)(1) === 14.U(plru.nBits.W), s"get_next_state state=10 way=1: expected=14 actual=%d", get_next_states(10)(1)) assert(get_next_states(10)(2) === 10.U(plru.nBits.W), s"get_next_state state=10 way=2: expected=10 actual=%d", get_next_states(10)(2)) assert(get_next_states(10)(3) === 8.U(plru.nBits.W), s"get_next_state state=10 way=3: expected=08 actual=%d", get_next_states(10)(3)) assert(get_next_states(10)(4) === 2.U(plru.nBits.W), s"get_next_state state=10 way=4: expected=02 actual=%d", get_next_states(10)(4)) assert(get_next_states(11)(0) === 15.U(plru.nBits.W), s"get_next_state state=11 way=0: expected=15 actual=%d", get_next_states(11)(0)) assert(get_next_states(11)(1) === 14.U(plru.nBits.W), s"get_next_state state=11 way=1: expected=14 actual=%d", get_next_states(11)(1)) assert(get_next_states(11)(2) === 11.U(plru.nBits.W), s"get_next_state state=11 way=2: expected=11 actual=%d", get_next_states(11)(2)) assert(get_next_states(11)(3) === 9.U(plru.nBits.W), s"get_next_state state=11 way=3: expected=09 actual=%d", get_next_states(11)(3)) assert(get_next_states(11)(4) === 3.U(plru.nBits.W), s"get_next_state state=11 way=4: expected=03 actual=%d", get_next_states(11)(4)) assert(get_next_states(12)(0) === 13.U(plru.nBits.W), s"get_next_state state=12 way=0: expected=13 actual=%d", get_next_states(12)(0)) assert(get_next_states(12)(1) === 12.U(plru.nBits.W), s"get_next_state state=12 way=1: expected=12 actual=%d", get_next_states(12)(1)) assert(get_next_states(12)(2) === 10.U(plru.nBits.W), s"get_next_state state=12 way=2: expected=10 actual=%d", get_next_states(12)(2)) assert(get_next_states(12)(3) === 8.U(plru.nBits.W), s"get_next_state state=12 way=3: expected=08 actual=%d", get_next_states(12)(3)) assert(get_next_states(12)(4) === 4.U(plru.nBits.W), s"get_next_state state=12 way=4: expected=04 actual=%d", get_next_states(12)(4)) assert(get_next_states(13)(0) === 13.U(plru.nBits.W), s"get_next_state state=13 way=0: expected=13 actual=%d", get_next_states(13)(0)) assert(get_next_states(13)(1) === 12.U(plru.nBits.W), s"get_next_state state=13 way=1: expected=12 actual=%d", get_next_states(13)(1)) assert(get_next_states(13)(2) === 11.U(plru.nBits.W), s"get_next_state state=13 way=2: expected=11 actual=%d", get_next_states(13)(2)) assert(get_next_states(13)(3) === 9.U(plru.nBits.W), s"get_next_state state=13 way=3: expected=09 actual=%d", get_next_states(13)(3)) assert(get_next_states(13)(4) === 5.U(plru.nBits.W), s"get_next_state state=13 way=4: expected=05 actual=%d", get_next_states(13)(4)) assert(get_next_states(14)(0) === 15.U(plru.nBits.W), s"get_next_state state=14 way=0: expected=15 actual=%d", get_next_states(14)(0)) assert(get_next_states(14)(1) === 14.U(plru.nBits.W), s"get_next_state state=14 way=1: expected=14 actual=%d", get_next_states(14)(1)) assert(get_next_states(14)(2) === 10.U(plru.nBits.W), s"get_next_state state=14 way=2: expected=10 actual=%d", get_next_states(14)(2)) assert(get_next_states(14)(3) === 8.U(plru.nBits.W), s"get_next_state state=14 way=3: expected=08 actual=%d", get_next_states(14)(3)) assert(get_next_states(14)(4) === 6.U(plru.nBits.W), s"get_next_state state=14 way=4: expected=06 actual=%d", get_next_states(14)(4)) assert(get_next_states(15)(0) === 15.U(plru.nBits.W), s"get_next_state state=15 way=0: expected=15 actual=%d", get_next_states(15)(0)) assert(get_next_states(15)(1) === 14.U(plru.nBits.W), s"get_next_state state=15 way=5: expected=14 actual=%d", get_next_states(15)(1)) assert(get_next_states(15)(2) === 11.U(plru.nBits.W), s"get_next_state state=15 way=2: expected=11 actual=%d", get_next_states(15)(2)) assert(get_next_states(15)(3) === 9.U(plru.nBits.W), s"get_next_state state=15 way=3: expected=09 actual=%d", get_next_states(15)(3)) assert(get_next_states(15)(4) === 7.U(plru.nBits.W), s"get_next_state state=15 way=4: expected=07 actual=%d", get_next_states(15)(4)) } case 6 => { assert(get_replace_ways( 0) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=00: expected=0 actual=%d", get_replace_ways( 0)) assert(get_replace_ways( 1) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=01: expected=1 actual=%d", get_replace_ways( 1)) assert(get_replace_ways( 2) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=02: expected=0 actual=%d", get_replace_ways( 2)) assert(get_replace_ways( 3) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=03: expected=1 actual=%d", get_replace_ways( 3)) assert(get_replace_ways( 4) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=04: expected=2 actual=%d", get_replace_ways( 4)) assert(get_replace_ways( 5) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=05: expected=2 actual=%d", get_replace_ways( 5)) assert(get_replace_ways( 6) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=06: expected=3 actual=%d", get_replace_ways( 6)) assert(get_replace_ways( 7) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=07: expected=3 actual=%d", get_replace_ways( 7)) assert(get_replace_ways( 8) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=08: expected=0 actual=%d", get_replace_ways( 8)) assert(get_replace_ways( 9) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=09: expected=1 actual=%d", get_replace_ways( 9)) assert(get_replace_ways(10) === 0.U(log2Ceil(n_ways).W), s"get_replace_way state=10: expected=0 actual=%d", get_replace_ways(10)) assert(get_replace_ways(11) === 1.U(log2Ceil(n_ways).W), s"get_replace_way state=11: expected=1 actual=%d", get_replace_ways(11)) assert(get_replace_ways(12) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=12: expected=2 actual=%d", get_replace_ways(12)) assert(get_replace_ways(13) === 2.U(log2Ceil(n_ways).W), s"get_replace_way state=13: expected=2 actual=%d", get_replace_ways(13)) assert(get_replace_ways(14) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=14: expected=3 actual=%d", get_replace_ways(14)) assert(get_replace_ways(15) === 3.U(log2Ceil(n_ways).W), s"get_replace_way state=15: expected=3 actual=%d", get_replace_ways(15)) assert(get_replace_ways(16) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=16: expected=4 actual=%d", get_replace_ways(16)) assert(get_replace_ways(17) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=17: expected=4 actual=%d", get_replace_ways(17)) assert(get_replace_ways(18) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=18: expected=4 actual=%d", get_replace_ways(18)) assert(get_replace_ways(19) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=19: expected=4 actual=%d", get_replace_ways(19)) assert(get_replace_ways(20) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=20: expected=4 actual=%d", get_replace_ways(20)) assert(get_replace_ways(21) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=21: expected=4 actual=%d", get_replace_ways(21)) assert(get_replace_ways(22) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=22: expected=4 actual=%d", get_replace_ways(22)) assert(get_replace_ways(23) === 4.U(log2Ceil(n_ways).W), s"get_replace_way state=23: expected=4 actual=%d", get_replace_ways(23)) assert(get_replace_ways(24) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=24: expected=5 actual=%d", get_replace_ways(24)) assert(get_replace_ways(25) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=25: expected=5 actual=%d", get_replace_ways(25)) assert(get_replace_ways(26) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=26: expected=5 actual=%d", get_replace_ways(26)) assert(get_replace_ways(27) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=27: expected=5 actual=%d", get_replace_ways(27)) assert(get_replace_ways(28) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=28: expected=5 actual=%d", get_replace_ways(28)) assert(get_replace_ways(29) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=29: expected=5 actual=%d", get_replace_ways(29)) assert(get_replace_ways(30) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=30: expected=5 actual=%d", get_replace_ways(30)) assert(get_replace_ways(31) === 5.U(log2Ceil(n_ways).W), s"get_replace_way state=31: expected=5 actual=%d", get_replace_ways(31)) } case _ => throw new IllegalArgumentException(s"no test pattern found for n_ways=$n_ways") } } File HellaCache.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3.{dontTouch, _} import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.AMBAProtField import freechips.rocketchip.diplomacy.{IdRange, TransferSizes, RegionType} import freechips.rocketchip.tile.{L1CacheParams, HasL1CacheParameters, HasCoreParameters, CoreBundle, HasNonDiplomaticTileParameters, BaseTile, HasTileParameters} import freechips.rocketchip.tilelink.{TLMasterParameters, TLClientNode, TLMasterPortParameters, TLEdgeOut, TLWidthWidget, TLFIFOFixer, ClientMetadata} import freechips.rocketchip.util.{Code, RandomReplacement, ParameterizedBundle} import freechips.rocketchip.util.{BooleanToAugmentedBoolean, IntToAugmentedInt} import scala.collection.mutable.ListBuffer case class DCacheParams( nSets: Int = 64, nWays: Int = 4, rowBits: Int = 64, subWordBits: Option[Int] = None, replacementPolicy: String = "random", nTLBSets: Int = 1, nTLBWays: Int = 32, nTLBBasePageSectors: Int = 4, nTLBSuperpages: Int = 4, tagECC: Option[String] = None, dataECC: Option[String] = None, dataECCBytes: Int = 1, nMSHRs: Int = 1, nSDQ: Int = 17, nRPQ: Int = 16, nMMIOs: Int = 1, blockBytes: Int = 64, separateUncachedResp: Boolean = false, acquireBeforeRelease: Boolean = false, pipelineWayMux: Boolean = false, clockGate: Boolean = false, scratch: Option[BigInt] = None) extends L1CacheParams { def tagCode: Code = Code.fromString(tagECC) def dataCode: Code = Code.fromString(dataECC) def dataScratchpadBytes: Int = scratch.map(_ => nSetsblockBytes).getOrElse(0) def replacement = new RandomReplacement(nWays) def silentDrop: Boolean = !acquireBeforeRelease require((!scratch.isDefined \|\| nWays == 1), "Scratchpad only allowed in direct-mapped cache.") require((!scratch.isDefined \|\| nMSHRs == 0), "Scratchpad only allowed in blocking cache.") if (scratch.isEmpty) require(isPow2(nSets), s"nSets($nSets) must be pow2") } trait HasL1HellaCacheParameters extends HasL1CacheParameters with HasCoreParameters { val cacheParams = tileParams.dcache.get val cfg = cacheParams def wordBits = coreDataBits def wordBytes = coreDataBytes def subWordBits = cacheParams.subWordBits.getOrElse(wordBits) def subWordBytes = subWordBits / 8 def wordOffBits = log2Up(wordBytes) def beatBytes = cacheBlockBytes / cacheDataBeats def beatWords = beatBytes / wordBytes def beatOffBits = log2Up(beatBytes) def idxMSB = untagBits-1 def idxLSB = blockOffBits def offsetmsb = idxLSB-1 def offsetlsb = wordOffBits def rowWords = rowBits/wordBits def doNarrowRead = coreDataBits * nWays % rowBits == 0 def eccBytes = cacheParams.dataECCBytes val eccBits = cacheParams.dataECCBytes * 8 val encBits = cacheParams.dataCode.width(eccBits) val encWordBits = encBits * (wordBits / eccBits) def encDataBits = cacheParams.dataCode.width(coreDataBits) // NBDCache only def encRowBits = encDataBitsrowWords def lrscCycles = coreParams.lrscCycles // ISA requires 16-insn LRSC sequences to succeed def lrscBackoff = 3 // disallow LRSC reacquisition briefly def blockProbeAfterGrantCycles = 8 // give the processor some time to issue a request after a grant def nIOMSHRs = cacheParams.nMMIOs def maxUncachedInFlight = cacheParams.nMMIOs def dataScratchpadSize = cacheParams.dataScratchpadBytes require(rowBits >= coreDataBits, s"rowBits($rowBits) < coreDataBits($coreDataBits)") if (!usingDataScratchpad) require(rowBits == cacheDataBits, s"rowBits($rowBits) != cacheDataBits($cacheDataBits)") // would need offset addr for puts if data width < xlen require(xLen <= cacheDataBits, s"xLen($xLen) > cacheDataBits($cacheDataBits)") } abstract class L1HellaCacheModule(implicit val p: Parameters) extends Module with HasL1HellaCacheParameters abstract class L1HellaCacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p) with HasL1HellaCacheParameters /* Bundle definitions for HellaCache interfaces / trait HasCoreMemOp extends HasL1HellaCacheParameters { val addr = UInt(coreMaxAddrBits.W) val idx = (usingVM && untagBits > pgIdxBits).option(UInt(coreMaxAddrBits.W)) val tag = UInt((coreParams.dcacheReqTagBits + log2Ceil(dcacheArbPorts)).W) val cmd = UInt(M_SZ.W) val size = UInt(log2Ceil(coreDataBytes.log2 + 1).W) val signed = Bool() val dprv = UInt(PRV.SZ.W) val dv = Bool() } trait HasCoreData extends HasCoreParameters { val data = UInt(coreDataBits.W) val mask = UInt(coreDataBytes.W) } class HellaCacheReqInternal(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp { val phys = Bool() val no_resp = Bool() // The dcache may omit generating a response for this request val no_alloc = Bool() val no_xcpt = Bool() } class HellaCacheReq(implicit p: Parameters) extends HellaCacheReqInternal()(p) with HasCoreData class HellaCacheResp(implicit p: Parameters) extends CoreBundle()(p) with HasCoreMemOp with HasCoreData { val replay = Bool() val has_data = Bool() val data_word_bypass = UInt(coreDataBits.W) val data_raw = UInt(coreDataBits.W) val store_data = UInt(coreDataBits.W) } class AlignmentExceptions extends Bundle { val ld = Bool() val st = Bool() } class HellaCacheExceptions extends Bundle { val ma = new AlignmentExceptions val pf = new AlignmentExceptions val gf = new AlignmentExceptions val ae = new AlignmentExceptions } class HellaCacheWriteData(implicit p: Parameters) extends CoreBundle()(p) with HasCoreData class HellaCachePerfEvents extends Bundle { val acquire = Bool() val release = Bool() val grant = Bool() val tlbMiss = Bool() val blocked = Bool() val canAcceptStoreThenLoad = Bool() val canAcceptStoreThenRMW = Bool() val canAcceptLoadThenLoad = Bool() val storeBufferEmptyAfterLoad = Bool() val storeBufferEmptyAfterStore = Bool() } // interface between D$ and processor/DTLB class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) { val req = Decoupled(new HellaCacheReq) val s1_kill = Output(Bool()) // kill previous cycle's req val s1_data = Output(new HellaCacheWriteData()) // data for previous cycle's req val s2_nack = Input(Bool()) // req from two cycles ago is rejected val s2_nack_cause_raw = Input(Bool()) // reason for nack is store-load RAW hazard (performance hint) val s2_kill = Output(Bool()) // kill req from two cycles ago val s2_uncached = Input(Bool()) // advisory signal that the access is MMIO val s2_paddr = Input(UInt(paddrBits.W)) // translated address val resp = Flipped(Valid(new HellaCacheResp)) val replay_next = Input(Bool()) val s2_xcpt = Input(new HellaCacheExceptions) val s2_gpa = Input(UInt(vaddrBitsExtended.W)) val s2_gpa_is_pte = Input(Bool()) val uncached_resp = tileParams.dcache.get.separateUncachedResp.option(Flipped(Decoupled(new HellaCacheResp))) val ordered = Input(Bool()) val store_pending = Input(Bool()) // there is a store in a store buffer somewhere val perf = Input(new HellaCachePerfEvents()) val keep_clock_enabled = Output(Bool()) // should D$ avoid clock-gating itself? val clock_enabled = Input(Bool()) // is D$ currently being clocked? } /* Base classes for Diplomatic TL2 HellaCaches / abstract class HellaCache(tileId: Int)(implicit p: Parameters) extends LazyModule with HasNonDiplomaticTileParameters { protected val cfg = tileParams.dcache.get protected def cacheClientParameters = cfg.scratch.map(x => Seq()).getOrElse(Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache", sourceId = IdRange(0, 1 max cfg.nMSHRs), supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes)))) protected def mmioClientParameters = Seq(TLMasterParameters.v1( name = s"Core ${tileId} DCache MMIO", sourceId = IdRange(firstMMIO, firstMMIO + cfg.nMMIOs), requestFifo = true)) def firstMMIO = (cacheClientParameters.map(_.sourceId.end) :+ 0).max val node = TLClientNode(Seq(TLMasterPortParameters.v1( clients = cacheClientParameters ++ mmioClientParameters, minLatency = 1, requestFields = tileParams.core.useVM.option(Seq()).getOrElse(Seq(AMBAProtField()))))) val hartIdSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val mmioAddressPrefixSinkNodeOpt = cfg.scratch.map(_ => BundleBridgeSink[UInt]()) val module: HellaCacheModule def flushOnFenceI = cfg.scratch.isEmpty && !node.edges.out(0).manager.managers.forall(m => !m.supportsAcquireB \|\| !m.executable \|\| m.regionType >= RegionType.TRACKED \|\| m.regionType <= RegionType.IDEMPOTENT) def canSupportCFlushLine = !usingVM \|\| cfg.blockBytes cfg.nSets <= (1 << pgIdxBits) require(!tileParams.core.haveCFlush \|\| cfg.scratch.isEmpty, "CFLUSH_D_L1 instruction requires a D$") } class HellaCacheBundle(implicit p: Parameters) extends CoreBundle()(p) { val cpu = Flipped(new HellaCacheIO) val ptw = new TLBPTWIO() val errors = new DCacheErrors val tlb_port = new DCacheTLBPort } class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer) with HasL1HellaCacheParameters { implicit val edge: TLEdgeOut = outer.node.edges.out(0) val (tl_out, _) = outer.node.out(0) val io = IO(new HellaCacheBundle) val io_hartid = outer.hartIdSinkNodeOpt.map(_.bundle) val io_mmio_address_prefix = outer.mmioAddressPrefixSinkNodeOpt.map(_.bundle) dontTouch(io.cpu.resp) // Users like to monitor these fields even if the core ignores some signals dontTouch(io.cpu.s1_data) require(rowBits == edge.bundle.dataBits) private val fifoManagers = edge.manager.managers.filter(TLFIFOFixer.allVolatile) fifoManagers.foreach { m => require (m.fifoId == fifoManagers.head.fifoId, s"IOMSHRs must be FIFO for all regions with effects, but HellaCache sees\n"+ s"${m.nodePath.map(_.name)}\nversus\n${fifoManagers.head.nodePath.map(_.name)}") } } /** Support overriding which HellaCache is instantiated / case object BuildHellaCache extends Field[BaseTile => Parameters => HellaCache](HellaCacheFactory.apply) object HellaCacheFactory { def apply(tile: BaseTile)(p: Parameters): HellaCache = { if (tile.tileParams.dcache.get.nMSHRs == 0) new DCache(tile.tileId, tile.crossing)(p) else new NonBlockingDCache(tile.tileId)(p) } } /* Mix-ins for constructing tiles that have a HellaCache / trait HasHellaCache { this: BaseTile => val module: HasHellaCacheModule implicit val p: Parameters var nDCachePorts = 0 lazy val dcache: HellaCache = LazyModule(p(BuildHellaCache)(this)(p)) tlMasterXbar.node := TLWidthWidget(tileParams.dcache.get.rowBits/8) := dcache.node dcache.hartIdSinkNodeOpt.map { _ := hartIdNexusNode } dcache.mmioAddressPrefixSinkNodeOpt.map { _ := mmioAddressPrefixNexusNode } InModuleBody { dcache.module.io.tlb_port := DontCare } } trait HasHellaCacheModule { val outer: HasHellaCache with HasTileParameters implicit val p: Parameters val dcachePorts = ListBuffer[HellaCacheIO]() val dcacheArb = Module(new HellaCacheArbiter(outer.nDCachePorts)(outer.p)) outer.dcache.module.io.cpu <> dcacheArb.io.mem } /* Metadata array used for all HellaCaches / class L1Metadata(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val coh = new ClientMetadata val tag = UInt(tagBits.W) } object L1Metadata { def apply(tag: Bits, coh: ClientMetadata)(implicit p: Parameters) = { val meta = Wire(new L1Metadata) meta.tag := tag meta.coh := coh meta } } class L1MetaReadReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val idx = UInt(idxBits.W) val way_en = UInt(nWays.W) val tag = UInt(tagBits.W) } class L1MetaWriteReq(implicit p: Parameters) extends L1MetaReadReq()(p) { val data = new L1Metadata } class L1MetadataArray[T <: L1Metadata](onReset: () => T)(implicit p: Parameters) extends L1HellaCacheModule()(p) { val rstVal = onReset() val io = IO(new Bundle { val read = Flipped(Decoupled(new L1MetaReadReq)) val write = Flipped(Decoupled(new L1MetaWriteReq)) val resp = Output(Vec(nWays, rstVal.cloneType)) }) val rst_cnt = RegInit(0.U(log2Up(nSets+1).W)) val rst = rst_cnt < nSets.U val waddr = Mux(rst, rst_cnt, io.write.bits.idx) val wdata = Mux(rst, rstVal, io.write.bits.data).asUInt val wmask = Mux(rst \|\| (nWays == 1).B, (-1).S, io.write.bits.way_en.asSInt).asBools val rmask = Mux(rst \|\| (nWays == 1).B, (-1).S, io.read.bits.way_en.asSInt).asBools when (rst) { rst_cnt := rst_cnt+1.U } val metabits = rstVal.getWidth val tag_array = SyncReadMem(nSets, Vec(nWays, UInt(metabits.W))) val wen = rst \|\| io.write.valid when (wen) { tag_array.write(waddr, VecInit.fill(nWays)(wdata), wmask) } io.resp := tag_array.read(io.read.bits.idx, io.read.fire).map(_.asTypeOf(chiselTypeOf(rstVal))) io.read.ready := !wen // so really this could be a 6T RAM io.write.ready := !rst } File ECC.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR abstract class Decoding { def uncorrected: UInt def corrected: UInt def correctable: Bool def uncorrectable: Bool // If true, correctable should be ignored def error = correctable \|\| uncorrectable } abstract class Code { def canDetect: Boolean def canCorrect: Boolean def width(w0: Int): Int /* Takes the unencoded width and returns a list of indices indicating which * bits of the encoded value will be used for ecc / def eccIndices(width: Int): Seq[Int] /* Encode x to a codeword suitable for decode. * If poison is true, the decoded value will report uncorrectable * error despite uncorrected == corrected == x. / def encode(x: UInt, poison: Bool = false.B): UInt def decode(x: UInt): Decoding /* Copy the bits in x to the right bit positions in an encoded word, * so that x === decode(swizzle(x)).uncorrected; but don't generate * the other code bits, so decode(swizzle(x)).error might be true. * For codes for which this operation is not trivial, throw an * UnsupportedOperationException. / def swizzle(x: UInt): UInt } class IdentityCode extends Code { def canDetect = false def canCorrect = false def width(w0: Int) = w0 def eccIndices(width: Int) = Seq.empty[Int] def encode(x: UInt, poison: Bool = false.B) = { require (poison.isLit && poison.litValue == 0, "IdentityCode can not be poisoned") x } def swizzle(x: UInt) = x def decode(y: UInt) = new Decoding { def uncorrected = y def corrected = y def correctable = false.B def uncorrectable = false.B } } class ParityCode extends Code { def canDetect = true def canCorrect = false def width(w0: Int) = w0+1 def eccIndices(w0: Int) = Seq(w0) def encode(x: UInt, poison: Bool = false.B) = Cat(x.xorR ^ poison, x) def swizzle(x: UInt) = Cat(false.B, x) def decode(y: UInt) = new Decoding { val uncorrected = y(y.getWidth-2,0) val corrected = uncorrected val correctable = false.B val uncorrectable = y.xorR } } class SECCode extends Code { def canDetect = true def canCorrect = true // SEC codes may or may not be poisonous depending on the length // If the code is perfect, every non-codeword is correctable def poisonous(n: Int) = !isPow2(n+1) def width(k: Int) = { val m = log2Floor(k) + 1 k + m + (if((1 << m) < m+k+1) 1 else 0) } def eccIndices(w0: Int) = { (0 until width(w0)).collect { case i if i >= w0 => i } } def swizzle(x: UInt) = { val k = x.getWidth val n = width(k) Cat(0.U((n-k).W), x) } // An (n=16, k=11) Hamming code is naturally encoded as: // PPxPxxxPxxxxxxxP where P are parity bits and x are data // Indexes typically start at 1, because then the P are on powers of two // In systematic coding, you put all the data in the front: // xxxxxxxxxxxPPPPP // Indexes typically start at 0, because Computer Science // For sanity when reading SRAMs, you want systematic form. private def impl(n: Int, k: Int) = { require (n >= 3 && k >= 1 && !isPow2(n)) val hamm2sys = IndexedSeq.tabulate(n+1) { i => if (i == 0) { n / undefined / } else if (isPow2(i)) { k + log2Ceil(i) } else { i - 1 - log2Ceil(i) } } val sys2hamm = hamm2sys.zipWithIndex.sortBy(_._1).map(_._2).toIndexedSeq def syndrome(j: Int) = { val bit = 1 << j ("b" + Seq.tabulate(n) { i => if ((sys2hamm(i) & bit) != 0) "1" else "0" }.reverse.mkString).U } (hamm2sys, sys2hamm, syndrome _) } def encode(x: UInt, poison: Bool = false.B) = { val k = x.getWidth val n = width(k) val (_, _, syndrome) = impl(n, k) require ((poison.isLit && poison.litValue == 0) \|\| poisonous(n), s"SEC code of length ${n} cannot be poisoned") / By setting the entire syndrome on poison, the corrected bit falls off the end of the code / val syndromeUInt = VecInit.tabulate(n-k) { j => (syndrome(j)(k-1, 0) & x).xorR ^ poison }.asUInt Cat(syndromeUInt, x) } def decode(y: UInt) = new Decoding { val n = y.getWidth val k = n - log2Ceil(n) val (_, sys2hamm, syndrome) = impl(n, k) val syndromeUInt = VecInit.tabulate(n-k) { j => (syndrome(j) & y).xorR }.asUInt val hammBadBitOH = UIntToOH(syndromeUInt, n+1) val sysBadBitOH = VecInit.tabulate(k) { i => hammBadBitOH(sys2hamm(i)) }.asUInt val uncorrected = y(k-1, 0) val corrected = uncorrected ^ sysBadBitOH val correctable = syndromeUInt.orR val uncorrectable = if (poisonous(n)) { syndromeUInt > n.U } else { false.B } } } class SECDEDCode extends Code { def canDetect = true def canCorrect = true private val sec = new SECCode private val par = new ParityCode def width(k: Int) = sec.width(k)+1 def eccIndices(w0: Int) = { (0 until width(w0)).collect { case i if i >= w0 => i } } def encode(x: UInt, poison: Bool = false.B) = { // toggling two bits ensures the error is uncorrectable // to ensure corrected == uncorrected, we pick one redundant // bit from SEC (the highest); correcting it does not affect // corrected == uncorrected. the second toggled bit is the // parity bit, which also does not appear in the decoding val toggle_lo = Cat(poison.asUInt, poison.asUInt) val toggle_hi = toggle_lo << (sec.width(x.getWidth)-1) par.encode(sec.encode(x)) ^ toggle_hi } def swizzle(x: UInt) = par.swizzle(sec.swizzle(x)) def decode(x: UInt) = new Decoding { val secdec = sec.decode(x(x.getWidth-2,0)) val pardec = par.decode(x) val uncorrected = secdec.uncorrected val corrected = secdec.corrected val correctable = pardec.uncorrectable val uncorrectable = !pardec.uncorrectable && secdec.correctable } } object ErrGen { // generate a 1-bit error with approximate probability 2^-f def apply(width: Int, f: Int): UInt = { require(width > 0 && f >= 0 && log2Up(width) + f <= 16) UIntToOH(LFSR(16)(log2Up(width)+f-1,0))(width-1,0) } def apply(x: UInt, f: Int): UInt = x ^ apply(x.getWidth, f) } trait CanHaveErrors extends Bundle { val correctable: Option[ValidIO[UInt]] val uncorrectable: Option[ValidIO[UInt]] } case class ECCParams( bytes: Int = 1, code: Code = new IdentityCode, notifyErrors: Boolean = false, ) object Code { def fromString(s: Option[String]): Code = fromString(s.getOrElse("none")) def fromString(s: String): Code = s.toLowerCase match { case "none" => new IdentityCode case "identity" => new IdentityCode case "parity" => new ParityCode case "sec" => new SECCode case "secded" => new SECDEDCode case _ => throw new IllegalArgumentException("Unknown ECC type") } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class ECCTest(k: Int, timeout: Int = 500000) extends UnitTest(timeout) { val code = new SECDEDCode val n = code.width(k) // Brute force the decode space val test = RegInit(0.U((n+1).W)) val last = test(n) test := test + !last io.finished := RegNext(last, false.B) // Confirm the decoding matches the encoding val decoded = code.decode(test(n-1, 0)) val recoded = code.encode(decoded.corrected) val distance = PopCount(recoded ^ test) // Count the cases val correct = RegInit(0.U(n.W)) val correctable = RegInit(0.U(n.W)) val uncorrectable = RegInit(0.U(n.W)) when (!last) { when (decoded.uncorrectable) { assert (distance >= 2.U) // uncorrectable uncorrectable := uncorrectable + 1.U } .elsewhen (decoded.correctable) { assert (distance(0)) // correctable => odd bit errors correctable := correctable + 1.U } .otherwise { assert (distance === 0.U) // correct assert (decoded.uncorrected === decoded.corrected) correct := correct + 1.U } } // Expected number of each case val nCodes = BigInt(1) << n val nCorrect = BigInt(1) << k val nCorrectable = nCodes / 2 val nUncorrectable = nCodes - nCorrectable - nCorrect when (last) { assert (correct === nCorrect.U) assert (correctable === nCorrectable.U) assert (uncorrectable === nUncorrectable.U) } } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) \|\| isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR \|\| cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) \|\| isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR \|\| cmd === M_PWR \|\| cmd === M_XSC \|\| isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) \|\| cmd === M_PFW \|\| cmd === M_XLR } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File TLB.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.diplomacy.RegionType import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile.{CoreModule, CoreBundle} import freechips.rocketchip.tilelink._ import freechips.rocketchip.util.{OptimizationBarrier, SetAssocLRU, PseudoLRU, PopCountAtLeast, property} import freechips.rocketchip.util.BooleanToAugmentedBoolean import freechips.rocketchip.util.IntToAugmentedInt import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.UIntIsOneOf import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.SeqBoolBitwiseOps case object ASIdBits extends Field[Int](0) case object VMIdBits extends Field[Int](0) /* =SFENCE= * rs1 rs2 * {{{ * 0 0 -> flush All * 0 1 -> flush by ASID * 1 1 -> flush by ADDR * 1 0 -> flush by ADDR and ASID * }}} * {{{ * If rs1=x0 and rs2=x0, the fence orders all reads and writes made to any level of the page tables, for all address spaces. * If rs1=x0 and rs2!=x0, the fence orders all reads and writes made to any level of the page tables, but only for the address space identified by integer register rs2. Accesses to global mappings (see Section 4.3.1) are not ordered. * If rs1!=x0 and rs2=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for all address spaces. * If rs1!=x0 and rs2!=x0, the fence orders only reads and writes made to the leaf page table entry corresponding to the virtual address in rs1, for the address space identified by integer register rs2. Accesses to global mappings are not ordered. * }}} / class SFenceReq(implicit p: Parameters) extends CoreBundle()(p) { val rs1 = Bool() val rs2 = Bool() val addr = UInt(vaddrBits.W) val asid = UInt((asIdBits max 1).W) // TODO zero-width val hv = Bool() val hg = Bool() } class TLBReq(lgMaxSize: Int)(implicit p: Parameters) extends CoreBundle()(p) { /* request address from CPU. / val vaddr = UInt(vaddrBitsExtended.W) /* don't lookup TLB, bypass vaddr as paddr / val passthrough = Bool() /* granularity / val size = UInt(log2Ceil(lgMaxSize + 1).W) /* memory command. / val cmd = Bits(M_SZ.W) val prv = UInt(PRV.SZ.W) /* virtualization mode / val v = Bool() } class TLBExceptions extends Bundle { val ld = Bool() val st = Bool() val inst = Bool() } class TLBResp(lgMaxSize: Int = 3)(implicit p: Parameters) extends CoreBundle()(p) { // lookup responses val miss = Bool() /* physical address / val paddr = UInt(paddrBits.W) val gpa = UInt(vaddrBitsExtended.W) val gpa_is_pte = Bool() /* page fault exception / val pf = new TLBExceptions /* guest page fault exception / val gf = new TLBExceptions /* access exception / val ae = new TLBExceptions /* misaligned access exception / val ma = new TLBExceptions /* if this address is cacheable / val cacheable = Bool() /* if caches must allocate this address / val must_alloc = Bool() /* if this address is prefetchable for caches/ val prefetchable = Bool() /* size/cmd of request that generated this response/ val size = UInt(log2Ceil(lgMaxSize + 1).W) val cmd = UInt(M_SZ.W) } class TLBEntryData(implicit p: Parameters) extends CoreBundle()(p) { val ppn = UInt(ppnBits.W) /* pte.u user / val u = Bool() /* pte.g global / val g = Bool() /* access exception. * D$ -> PTW -> TLB AE * Alignment failed. / val ae_ptw = Bool() val ae_final = Bool() val ae_stage2 = Bool() /* page fault / val pf = Bool() /* guest page fault / val gf = Bool() /* supervisor write / val sw = Bool() /* supervisor execute / val sx = Bool() /* supervisor read / val sr = Bool() /* hypervisor write / val hw = Bool() /* hypervisor excute / val hx = Bool() /* hypervisor read / val hr = Bool() /* prot_w / val pw = Bool() /* prot_x / val px = Bool() /* prot_r / val pr = Bool() /* PutPartial / val ppp = Bool() /* AMO logical / val pal = Bool() /* AMO arithmetic / val paa = Bool() /* get/put effects / val eff = Bool() /* cacheable / val c = Bool() /* fragmented_superpage support / val fragmented_superpage = Bool() } /* basic cell for TLB data / class TLBEntry(val nSectors: Int, val superpage: Boolean, val superpageOnly: Boolean)(implicit p: Parameters) extends CoreBundle()(p) { require(nSectors == 1 \|\| !superpage) require(!superpageOnly \|\| superpage) val level = UInt(log2Ceil(pgLevels).W) /* use vpn as tag / val tag_vpn = UInt(vpnBits.W) /* tag in vitualization mode / val tag_v = Bool() /* entry data / val data = Vec(nSectors, UInt(new TLBEntryData().getWidth.W)) /* valid bit / val valid = Vec(nSectors, Bool()) /* returns all entry data in this entry / def entry_data = data.map(_.asTypeOf(new TLBEntryData)) /* returns the index of sector / private def sectorIdx(vpn: UInt) = vpn.extract(nSectors.log2-1, 0) /* returns the entry data matched with this vpn/ def getData(vpn: UInt) = OptimizationBarrier(data(sectorIdx(vpn)).asTypeOf(new TLBEntryData)) /* returns whether a sector hits / def sectorHit(vpn: UInt, virtual: Bool) = valid.orR && sectorTagMatch(vpn, virtual) /* returns whether tag matches vpn / def sectorTagMatch(vpn: UInt, virtual: Bool) = (((tag_vpn ^ vpn) >> nSectors.log2) === 0.U) && (tag_v === virtual) /* returns hit signal / def hit(vpn: UInt, virtual: Bool): Bool = { if (superpage && usingVM) { var tagMatch = valid.head && (tag_v === virtual) for (j <- 0 until pgLevels) { val base = (pgLevels - 1 - j) pgLevelBits val n = pgLevelBits + (if (j == 0) hypervisorExtraAddrBits else 0) val ignore = level < j.U \|\| (superpageOnly && j == pgLevels - 1).B tagMatch = tagMatch && (ignore \|\| (tag_vpn ^ vpn)(base + n - 1, base) === 0.U) } tagMatch } else { val idx = sectorIdx(vpn) valid(idx) && sectorTagMatch(vpn, virtual) } } /** returns the ppn of the input TLBEntryData / def ppn(vpn: UInt, data: TLBEntryData) = { val supervisorVPNBits = pgLevels pgLevelBits if (superpage && usingVM) { var res = data.ppn >> pgLevelBits(pgLevels - 1) for (j <- 1 until pgLevels) { val ignore = level < j.U \|\| (superpageOnly && j == pgLevels - 1).B res = Cat(res, (Mux(ignore, vpn, 0.U) \| data.ppn)(supervisorVPNBits - jpgLevelBits - 1, supervisorVPNBits - (j + 1)pgLevelBits)) } res } else { data.ppn } } /* does the refill * * find the target entry with vpn tag * and replace the target entry with the input entry data / def insert(vpn: UInt, virtual: Bool, level: UInt, entry: TLBEntryData): Unit = { this.tag_vpn := vpn this.tag_v := virtual this.level := level.extract(log2Ceil(pgLevels - superpageOnly.toInt)-1, 0) val idx = sectorIdx(vpn) valid(idx) := true.B data(idx) := entry.asUInt } def invalidate(): Unit = { valid.foreach(_ := false.B) } def invalidate(virtual: Bool): Unit = { for ((v, e) <- valid zip entry_data) when (tag_v === virtual) { v := false.B } } def invalidateVPN(vpn: UInt, virtual: Bool): Unit = { if (superpage) { when (hit(vpn, virtual)) { invalidate() } } else { when (sectorTagMatch(vpn, virtual)) { for (((v, e), i) <- (valid zip entry_data).zipWithIndex) when (tag_v === virtual && i.U === sectorIdx(vpn)) { v := false.B } } } // For fragmented superpage mappings, we assume the worst (largest) // case, and zap entries whose most-significant VPNs match when (((tag_vpn ^ vpn) >> (pgLevelBits (pgLevels - 1))) === 0.U) { for ((v, e) <- valid zip entry_data) when (tag_v === virtual && e.fragmented_superpage) { v := false.B } } } def invalidateNonGlobal(virtual: Bool): Unit = { for ((v, e) <- valid zip entry_data) when (tag_v === virtual && !e.g) { v := false.B } } } /** TLB config * * @param nSets the number of sets of PTE, follow [[ICacheParams.nSets]] * @param nWays the total number of wayss of PTE, follow [[ICacheParams.nWays]] * @param nSectors the number of ways in a single PTE TLBEntry * @param nSuperpageEntries the number of SuperpageEntries / case class TLBConfig( nSets: Int, nWays: Int, nSectors: Int = 4, nSuperpageEntries: Int = 4) /* =Overview= * [[TLB]] is a TLB template which contains PMA logic and PMP checker. * * TLB caches PTE and accelerates the address translation process. * When tlb miss happens, ask PTW(L2TLB) for Page Table Walk. * Perform PMP and PMA check during the translation and throw exception if there were any. * * ==Cache Structure== * - Sectored Entry (PTE) * - set-associative or direct-mapped * - nsets = [[TLBConfig.nSets]] * - nways = [[TLBConfig.nWays]] / [[TLBConfig.nSectors]] * - PTEEntry( sectors = [[TLBConfig.nSectors]] ) * - LRU(if set-associative) * * - Superpage Entry(superpage PTE) * - fully associative * - nsets = [[TLBConfig.nSuperpageEntries]] * - PTEEntry(sectors = 1) * - PseudoLRU * * - Special Entry(PTE across PMP) * - nsets = 1 * - PTEEntry(sectors = 1) * * ==Address structure== * {{{ * \|vaddr \| * \|ppn/vpn \| pgIndex \| * \| \| \| * \| \|nSets \|nSector \| \|}}} * * ==State Machine== * {{{ * s_ready: ready to accept request from CPU. * s_request: when L1TLB(this) miss, send request to PTW(L2TLB), . * s_wait: wait for PTW to refill L1TLB. * s_wait_invalidate: L1TLB is waiting for respond from PTW, but L1TLB will invalidate respond from PTW.}}} * * ==PMP== * pmp check * - special_entry: always check * - other entry: check on refill * * ==Note== * PMA consume diplomacy parameter generate physical memory address checking logic * * Boom use Rocket ITLB, and its own DTLB. * * Accelerators:{{{ * sha3: DTLB * gemmini: DTLB * hwacha: DTLB2+ITLB}}} @param instruction true for ITLB, false for DTLB * @param lgMaxSize @todo seems granularity * @param cfg [[TLBConfig]] * @param edge collect SoC metadata. / class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { override def desiredName = if (instruction) "ITLB" else "DTLB" val io = IO(new Bundle { /* request from Core / val req = Flipped(Decoupled(new TLBReq(lgMaxSize))) /* response to Core / val resp = Output(new TLBResp(lgMaxSize)) /* SFence Input / val sfence = Flipped(Valid(new SFenceReq)) /* IO to PTW / val ptw = new TLBPTWIO /* suppress a TLB refill, one cycle after a miss / val kill = Input(Bool()) }) io.ptw.customCSRs := DontCare val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) val vpn = io.req.bits.vaddr(vaddrBits-1, pgIdxBits) /* index for sectored_Entry / val memIdx = vpn.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2) /* TLB Entry / val sectored_entries = Reg(Vec(cfg.nSets, Vec(cfg.nWays / cfg.nSectors, new TLBEntry(cfg.nSectors, false, false)))) /* Superpage Entry / val superpage_entries = Reg(Vec(cfg.nSuperpageEntries, new TLBEntry(1, true, true))) /* Special Entry * * If PMP granularity is less than page size, thus need additional "special" entry manage PMP. / val special_entry = (!pageGranularityPMPs).option(Reg(new TLBEntry(1, true, false))) def ordinary_entries = sectored_entries(memIdx) ++ superpage_entries def all_entries = ordinary_entries ++ special_entry def all_real_entries = sectored_entries.flatten ++ superpage_entries ++ special_entry val s_ready :: s_request :: s_wait :: s_wait_invalidate :: Nil = Enum(4) val state = RegInit(s_ready) // use vpn as refill_tag val r_refill_tag = Reg(UInt(vpnBits.W)) val r_superpage_repl_addr = Reg(UInt(log2Ceil(superpage_entries.size).W)) val r_sectored_repl_addr = Reg(UInt(log2Ceil(sectored_entries.head.size).W)) val r_sectored_hit = Reg(Valid(UInt(log2Ceil(sectored_entries.head.size).W))) val r_superpage_hit = Reg(Valid(UInt(log2Ceil(superpage_entries.size).W))) val r_vstage1_en = Reg(Bool()) val r_stage2_en = Reg(Bool()) val r_need_gpa = Reg(Bool()) val r_gpa_valid = Reg(Bool()) val r_gpa = Reg(UInt(vaddrBits.W)) val r_gpa_vpn = Reg(UInt(vpnBits.W)) val r_gpa_is_pte = Reg(Bool()) /* privilege mode / val priv = io.req.bits.prv val priv_v = usingHypervisor.B && io.req.bits.v val priv_s = priv(0) // user mode and supervisor mode val priv_uses_vm = priv <= PRV.S.U val satp = Mux(priv_v, io.ptw.vsatp, io.ptw.ptbr) val stage1_en = usingVM.B && satp.mode(satp.mode.getWidth-1) /* VS-stage translation enable / val vstage1_en = usingHypervisor.B && priv_v && io.ptw.vsatp.mode(io.ptw.vsatp.mode.getWidth-1) /* G-stage translation enable / val stage2_en = usingHypervisor.B && priv_v && io.ptw.hgatp.mode(io.ptw.hgatp.mode.getWidth-1) /* Enable Virtual Memory when: * 1. statically configured * 1. satp highest bits enabled * i. RV32: * - 0 -> Bare * - 1 -> SV32 * i. RV64: * - 0000 -> Bare * - 1000 -> SV39 * - 1001 -> SV48 * - 1010 -> SV57 * - 1011 -> SV64 * 1. In virtualization mode, vsatp highest bits enabled * 1. priv mode in U and S. * 1. in H & M mode, disable VM. * 1. no passthrough(micro-arch defined.) * * @see RV-priv spec 4.1.11 Supervisor Address Translation and Protection (satp) Register * @see RV-priv spec 8.2.18 Virtual Supervisor Address Translation and Protection Register (vsatp) / val vm_enabled = (stage1_en \|\| stage2_en) && priv_uses_vm && !io.req.bits.passthrough // flush guest entries on vsatp.MODE Bare <-> SvXX transitions val v_entries_use_stage1 = RegInit(false.B) val vsatp_mode_mismatch = priv_v && (vstage1_en =/= v_entries_use_stage1) && !io.req.bits.passthrough // share a single physical memory attribute checker (unshare if critical path) val refill_ppn = io.ptw.resp.bits.pte.ppn(ppnBits-1, 0) /* refill signal / val do_refill = usingVM.B && io.ptw.resp.valid /* sfence invalidate refill / val invalidate_refill = state.isOneOf(s_request / don't care /, s_wait_invalidate) \|\| io.sfence.valid // PMP val mpu_ppn = Mux(do_refill, refill_ppn, Mux(vm_enabled && special_entry.nonEmpty.B, special_entry.map(e => e.ppn(vpn, e.getData(vpn))).getOrElse(0.U), io.req.bits.vaddr >> pgIdxBits)) val mpu_physaddr = Cat(mpu_ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) val mpu_priv = Mux[UInt](usingVM.B && (do_refill \|\| io.req.bits.passthrough / PTW /), PRV.S.U, Cat(io.ptw.status.debug, priv)) val pmp = Module(new PMPChecker(lgMaxSize)) pmp.io.addr := mpu_physaddr pmp.io.size := io.req.bits.size pmp.io.pmp := (io.ptw.pmp: Seq[PMP]) pmp.io.prv := mpu_priv val pma = Module(new PMAChecker(edge.manager)(p)) pma.io.paddr := mpu_physaddr // todo: using DataScratchpad doesn't support cacheable. val cacheable = pma.io.resp.cacheable && (instruction \|\| !usingDataScratchpad).B val homogeneous = TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), BigInt(1) << pgIdxBits, 1 << lgMaxSize)(mpu_physaddr).homogeneous // In M mode, if access DM address(debug module program buffer) val deny_access_to_debug = mpu_priv <= PRV.M.U && p(DebugModuleKey).map(dmp => dmp.address.contains(mpu_physaddr)).getOrElse(false.B) val prot_r = pma.io.resp.r && !deny_access_to_debug && pmp.io.r val prot_w = pma.io.resp.w && !deny_access_to_debug && pmp.io.w val prot_pp = pma.io.resp.pp val prot_al = pma.io.resp.al val prot_aa = pma.io.resp.aa val prot_x = pma.io.resp.x && !deny_access_to_debug && pmp.io.x val prot_eff = pma.io.resp.eff // hit check val sector_hits = sectored_entries(memIdx).map(_.sectorHit(vpn, priv_v)) val superpage_hits = superpage_entries.map(_.hit(vpn, priv_v)) val hitsVec = all_entries.map(vm_enabled && _.hit(vpn, priv_v)) val real_hits = hitsVec.asUInt val hits = Cat(!vm_enabled, real_hits) // use ptw response to refill // permission bit arrays when (do_refill) { val pte = io.ptw.resp.bits.pte val refill_v = r_vstage1_en \|\| r_stage2_en val newEntry = Wire(new TLBEntryData) newEntry.ppn := pte.ppn newEntry.c := cacheable newEntry.u := pte.u newEntry.g := pte.g && pte.v newEntry.ae_ptw := io.ptw.resp.bits.ae_ptw newEntry.ae_final := io.ptw.resp.bits.ae_final newEntry.ae_stage2 := io.ptw.resp.bits.ae_final && io.ptw.resp.bits.gpa_is_pte && r_stage2_en newEntry.pf := io.ptw.resp.bits.pf newEntry.gf := io.ptw.resp.bits.gf newEntry.hr := io.ptw.resp.bits.hr newEntry.hw := io.ptw.resp.bits.hw newEntry.hx := io.ptw.resp.bits.hx newEntry.sr := pte.sr() newEntry.sw := pte.sw() newEntry.sx := pte.sx() newEntry.pr := prot_r newEntry.pw := prot_w newEntry.px := prot_x newEntry.ppp := prot_pp newEntry.pal := prot_al newEntry.paa := prot_aa newEntry.eff := prot_eff newEntry.fragmented_superpage := io.ptw.resp.bits.fragmented_superpage // refill special_entry when (special_entry.nonEmpty.B && !io.ptw.resp.bits.homogeneous) { special_entry.foreach(_.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry)) }.elsewhen (io.ptw.resp.bits.level < (pgLevels-1).U) { val waddr = Mux(r_superpage_hit.valid && usingHypervisor.B, r_superpage_hit.bits, r_superpage_repl_addr) for ((e, i) <- superpage_entries.zipWithIndex) when (r_superpage_repl_addr === i.U) { e.insert(r_refill_tag, refill_v, io.ptw.resp.bits.level, newEntry) when (invalidate_refill) { e.invalidate() } } // refill sectored_hit }.otherwise { val r_memIdx = r_refill_tag.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2) val waddr = Mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr) for ((e, i) <- sectored_entries(r_memIdx).zipWithIndex) when (waddr === i.U) { when (!r_sectored_hit.valid) { e.invalidate() } e.insert(r_refill_tag, refill_v, 0.U, newEntry) when (invalidate_refill) { e.invalidate() } } } r_gpa_valid := io.ptw.resp.bits.gpa.valid r_gpa := io.ptw.resp.bits.gpa.bits r_gpa_is_pte := io.ptw.resp.bits.gpa_is_pte } // get all entries data. val entries = all_entries.map(_.getData(vpn)) val normal_entries = entries.take(ordinary_entries.size) // parallel query PPN from [[all_entries]], if VM not enabled return VPN instead val ppn = Mux1H(hitsVec :+ !vm_enabled, (all_entries zip entries).map{ case (entry, data) => entry.ppn(vpn, data) } :+ vpn(ppnBits-1, 0)) val nPhysicalEntries = 1 + special_entry.size // generally PTW misaligned load exception. val ptw_ae_array = Cat(false.B, entries.map(_.ae_ptw).asUInt) val final_ae_array = Cat(false.B, entries.map(_.ae_final).asUInt) val ptw_pf_array = Cat(false.B, entries.map(_.pf).asUInt) val ptw_gf_array = Cat(false.B, entries.map(_.gf).asUInt) val sum = Mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum) // if in hypervisor/machine mode, cannot read/write user entries. // if in superviosr/user mode, "If the SUM bit in the sstatus register is set, supervisor mode software may also access pages with U=1.(from spec)" val priv_rw_ok = Mux(!priv_s \|\| sum, entries.map(_.u).asUInt, 0.U) \| Mux(priv_s, ~entries.map(_.u).asUInt, 0.U) // if in hypervisor/machine mode, other than user pages, all pages are executable. // if in superviosr/user mode, only user page can execute. val priv_x_ok = Mux(priv_s, ~entries.map(_.u).asUInt, entries.map(_.u).asUInt) val stage1_bypass = Fill(entries.size, usingHypervisor.B) & (Fill(entries.size, !stage1_en) \| entries.map(_.ae_stage2).asUInt) val mxr = io.ptw.status.mxr \| Mux(priv_v, io.ptw.gstatus.mxr, false.B) // "The vsstatus field MXR, which makes execute-only pages readable, only overrides VS-stage page protection.(from spec)" val r_array = Cat(true.B, (priv_rw_ok & (entries.map(_.sr).asUInt \| Mux(mxr, entries.map(_.sx).asUInt, 0.U))) \| stage1_bypass) val w_array = Cat(true.B, (priv_rw_ok & entries.map(_.sw).asUInt) \| stage1_bypass) val x_array = Cat(true.B, (priv_x_ok & entries.map(_.sx).asUInt) \| stage1_bypass) val stage2_bypass = Fill(entries.size, !stage2_en) val hr_array = Cat(true.B, entries.map(_.hr).asUInt \| Mux(io.ptw.status.mxr, entries.map(_.hx).asUInt, 0.U) \| stage2_bypass) val hw_array = Cat(true.B, entries.map(_.hw).asUInt \| stage2_bypass) val hx_array = Cat(true.B, entries.map(_.hx).asUInt \| stage2_bypass) // These array is for each TLB entries. // user mode can read: PMA OK, TLB OK, AE OK val pr_array = Cat(Fill(nPhysicalEntries, prot_r), normal_entries.map(_.pr).asUInt) & ~(ptw_ae_array \| final_ae_array) // user mode can write: PMA OK, TLB OK, AE OK val pw_array = Cat(Fill(nPhysicalEntries, prot_w), normal_entries.map(_.pw).asUInt) & ~(ptw_ae_array \| final_ae_array) // user mode can write: PMA OK, TLB OK, AE OK val px_array = Cat(Fill(nPhysicalEntries, prot_x), normal_entries.map(_.px).asUInt) & ~(ptw_ae_array \| final_ae_array) // put effect val eff_array = Cat(Fill(nPhysicalEntries, prot_eff), normal_entries.map(_.eff).asUInt) // cacheable val c_array = Cat(Fill(nPhysicalEntries, cacheable), normal_entries.map(_.c).asUInt) // put partial val ppp_array = Cat(Fill(nPhysicalEntries, prot_pp), normal_entries.map(_.ppp).asUInt) // atomic arithmetic val paa_array = Cat(Fill(nPhysicalEntries, prot_aa), normal_entries.map(_.paa).asUInt) // atomic logic val pal_array = Cat(Fill(nPhysicalEntries, prot_al), normal_entries.map(_.pal).asUInt) val ppp_array_if_cached = ppp_array \| c_array val paa_array_if_cached = paa_array \| (if(usingAtomicsInCache) c_array else 0.U) val pal_array_if_cached = pal_array \| (if(usingAtomicsInCache) c_array else 0.U) val prefetchable_array = Cat((cacheable && homogeneous) << (nPhysicalEntries-1), normal_entries.map(_.c).asUInt) // vaddr misaligned: vaddr[1:0]=b00 val misaligned = (io.req.bits.vaddr & (UIntToOH(io.req.bits.size) - 1.U)).orR def badVA(guestPA: Boolean): Bool = { val additionalPgLevels = (if (guestPA) io.ptw.hgatp else satp).additionalPgLevels val extraBits = if (guestPA) hypervisorExtraAddrBits else 0 val signed = !guestPA val nPgLevelChoices = pgLevels - minPgLevels + 1 val minVAddrBits = pgIdxBits + minPgLevels pgLevelBits + extraBits (for (i <- 0 until nPgLevelChoices) yield { val mask = ((BigInt(1) << vaddrBitsExtended) - (BigInt(1) << (minVAddrBits + i * pgLevelBits - signed.toInt))).U val maskedVAddr = io.req.bits.vaddr & mask additionalPgLevels === i.U && !(maskedVAddr === 0.U \|\| signed.B && maskedVAddr === mask) }).orR } val bad_gpa = if (!usingHypervisor) false.B else vm_enabled && !stage1_en && badVA(true) val bad_va = if (!usingVM \|\| (minPgLevels == pgLevels && vaddrBits == vaddrBitsExtended)) false.B else vm_enabled && stage1_en && badVA(false) val cmd_lrsc = usingAtomics.B && io.req.bits.cmd.isOneOf(M_XLR, M_XSC) val cmd_amo_logical = usingAtomics.B && isAMOLogical(io.req.bits.cmd) val cmd_amo_arithmetic = usingAtomics.B && isAMOArithmetic(io.req.bits.cmd) val cmd_put_partial = io.req.bits.cmd === M_PWR val cmd_read = isRead(io.req.bits.cmd) val cmd_readx = usingHypervisor.B && io.req.bits.cmd === M_HLVX val cmd_write = isWrite(io.req.bits.cmd) val cmd_write_perms = cmd_write \|\| io.req.bits.cmd.isOneOf(M_FLUSH_ALL, M_WOK) // not a write, but needs write permissions val lrscAllowed = Mux((usingDataScratchpad \|\| usingAtomicsOnlyForIO).B, 0.U, c_array) val ae_array = Mux(misaligned, eff_array, 0.U) \| Mux(cmd_lrsc, ~lrscAllowed, 0.U) // access exception needs SoC information from PMA val ae_ld_array = Mux(cmd_read, ae_array \| ~pr_array, 0.U) val ae_st_array = Mux(cmd_write_perms, ae_array \| ~pw_array, 0.U) \| Mux(cmd_put_partial, ~ppp_array_if_cached, 0.U) \| Mux(cmd_amo_logical, ~pal_array_if_cached, 0.U) \| Mux(cmd_amo_arithmetic, ~paa_array_if_cached, 0.U) val must_alloc_array = Mux(cmd_put_partial, ~ppp_array, 0.U) \| Mux(cmd_amo_logical, ~pal_array, 0.U) \| Mux(cmd_amo_arithmetic, ~paa_array, 0.U) \| Mux(cmd_lrsc, ~0.U(pal_array.getWidth.W), 0.U) val pf_ld_array = Mux(cmd_read, ((~Mux(cmd_readx, x_array, r_array) & ~ptw_ae_array) \| ptw_pf_array) & ~ptw_gf_array, 0.U) val pf_st_array = Mux(cmd_write_perms, ((~w_array & ~ptw_ae_array) \| ptw_pf_array) & ~ptw_gf_array, 0.U) val pf_inst_array = ((~x_array & ~ptw_ae_array) \| ptw_pf_array) & ~ptw_gf_array val gf_ld_array = Mux(priv_v && cmd_read, (~Mux(cmd_readx, hx_array, hr_array) \| ptw_gf_array) & ~ptw_ae_array, 0.U) val gf_st_array = Mux(priv_v && cmd_write_perms, (~hw_array \| ptw_gf_array) & ~ptw_ae_array, 0.U) val gf_inst_array = Mux(priv_v, (~hx_array \| ptw_gf_array) & ~ptw_ae_array, 0.U) val gpa_hits = { val need_gpa_mask = if (instruction) gf_inst_array else gf_ld_array \| gf_st_array val hit_mask = Fill(ordinary_entries.size, r_gpa_valid && r_gpa_vpn === vpn) \| Fill(all_entries.size, !vstage1_en) hit_mask \| ~need_gpa_mask(all_entries.size-1, 0) } val tlb_hit_if_not_gpa_miss = real_hits.orR val tlb_hit = (real_hits & gpa_hits).orR // leads to s_request val tlb_miss = vm_enabled && !vsatp_mode_mismatch && !bad_va && !tlb_hit val sectored_plru = new SetAssocLRU(cfg.nSets, sectored_entries.head.size, "plru") val superpage_plru = new PseudoLRU(superpage_entries.size) when (io.req.valid && vm_enabled) { // replace when (sector_hits.orR) { sectored_plru.access(memIdx, OHToUInt(sector_hits)) } when (superpage_hits.orR) { superpage_plru.access(OHToUInt(superpage_hits)) } } // Superpages create the possibility that two entries in the TLB may match. // This corresponds to a software bug, but we can't return complete garbage; // we must return either the old translation or the new translation. This // isn't compatible with the Mux1H approach. So, flush the TLB and report // a miss on duplicate entries. val multipleHits = PopCountAtLeast(real_hits, 2) // only pull up req.ready when this is s_ready state. io.req.ready := state === s_ready // page fault io.resp.pf.ld := (bad_va && cmd_read) \|\| (pf_ld_array & hits).orR io.resp.pf.st := (bad_va && cmd_write_perms) \|\| (pf_st_array & hits).orR io.resp.pf.inst := bad_va \|\| (pf_inst_array & hits).orR // guest page fault io.resp.gf.ld := (bad_gpa && cmd_read) \|\| (gf_ld_array & hits).orR io.resp.gf.st := (bad_gpa && cmd_write_perms) \|\| (gf_st_array & hits).orR io.resp.gf.inst := bad_gpa \|\| (gf_inst_array & hits).orR // access exception io.resp.ae.ld := (ae_ld_array & hits).orR io.resp.ae.st := (ae_st_array & hits).orR io.resp.ae.inst := (~px_array & hits).orR // misaligned io.resp.ma.ld := misaligned && cmd_read io.resp.ma.st := misaligned && cmd_write io.resp.ma.inst := false.B // this is up to the pipeline to figure out io.resp.cacheable := (c_array & hits).orR io.resp.must_alloc := (must_alloc_array & hits).orR io.resp.prefetchable := (prefetchable_array & hits).orR && edge.manager.managers.forall(m => !m.supportsAcquireB \|\| m.supportsHint).B io.resp.miss := do_refill \|\| vsatp_mode_mismatch \|\| tlb_miss \|\| multipleHits io.resp.paddr := Cat(ppn, io.req.bits.vaddr(pgIdxBits-1, 0)) io.resp.size := io.req.bits.size io.resp.cmd := io.req.bits.cmd io.resp.gpa_is_pte := vstage1_en && r_gpa_is_pte io.resp.gpa := { val page = Mux(!vstage1_en, Cat(bad_gpa, vpn), r_gpa >> pgIdxBits) val offset = Mux(io.resp.gpa_is_pte, r_gpa(pgIdxBits-1, 0), io.req.bits.vaddr(pgIdxBits-1, 0)) Cat(page, offset) } io.ptw.req.valid := state === s_request io.ptw.req.bits.valid := !io.kill io.ptw.req.bits.bits.addr := r_refill_tag io.ptw.req.bits.bits.vstage1 := r_vstage1_en io.ptw.req.bits.bits.stage2 := r_stage2_en io.ptw.req.bits.bits.need_gpa := r_need_gpa if (usingVM) { when(io.ptw.req.fire && io.ptw.req.bits.valid) { r_gpa_valid := false.B r_gpa_vpn := r_refill_tag } val sfence = io.sfence.valid // this is [[s_ready]] // handle miss/hit at the first cycle. // if miss, request PTW(L2TLB). when (io.req.fire && tlb_miss) { state := s_request r_refill_tag := vpn r_need_gpa := tlb_hit_if_not_gpa_miss r_vstage1_en := vstage1_en r_stage2_en := stage2_en r_superpage_repl_addr := replacementEntry(superpage_entries, superpage_plru.way) r_sectored_repl_addr := replacementEntry(sectored_entries(memIdx), sectored_plru.way(memIdx)) r_sectored_hit.valid := sector_hits.orR r_sectored_hit.bits := OHToUInt(sector_hits) r_superpage_hit.valid := superpage_hits.orR r_superpage_hit.bits := OHToUInt(superpage_hits) } // Handle SFENCE.VMA when send request to PTW. // SFENCE.VMA io.ptw.req.ready kill // ? ? 1 // 0 0 0 // 0 1 0 -> s_wait // 1 0 0 -> s_wait_invalidate // 1 0 0 -> s_ready when (state === s_request) { // SFENCE.VMA will kill TLB entries based on rs1 and rs2. It will take 1 cycle. when (sfence) { state := s_ready } // here should be io.ptw.req.fire, but assert(io.ptw.req.ready === true.B) // fire -> s_wait when (io.ptw.req.ready) { state := Mux(sfence, s_wait_invalidate, s_wait) } // If CPU kills request(frontend.s2_redirect) when (io.kill) { state := s_ready } } // sfence in refill will results in invalidate when (state === s_wait && sfence) { state := s_wait_invalidate } // after CPU acquire response, go back to s_ready. when (io.ptw.resp.valid) { state := s_ready } // SFENCE processing logic. when (sfence) { assert(!io.sfence.bits.rs1 \|\| (io.sfence.bits.addr >> pgIdxBits) === vpn) for (e <- all_real_entries) { val hv = usingHypervisor.B && io.sfence.bits.hv val hg = usingHypervisor.B && io.sfence.bits.hg when (!hg && io.sfence.bits.rs1) { e.invalidateVPN(vpn, hv) } .elsewhen (!hg && io.sfence.bits.rs2) { e.invalidateNonGlobal(hv) } .otherwise { e.invalidate(hv \|\| hg) } } } when(io.req.fire && vsatp_mode_mismatch) { all_real_entries.foreach(_.invalidate(true.B)) v_entries_use_stage1 := vstage1_en } when (multipleHits \|\| reset.asBool) { all_real_entries.foreach(_.invalidate()) } ccover(io.ptw.req.fire, "MISS", "TLB miss") ccover(io.ptw.req.valid && !io.ptw.req.ready, "PTW_STALL", "TLB miss, but PTW busy") ccover(state === s_wait_invalidate, "SFENCE_DURING_REFILL", "flush TLB during TLB refill") ccover(sfence && !io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_ALL", "flush TLB") ccover(sfence && !io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_ASID", "flush TLB ASID") ccover(sfence && io.sfence.bits.rs1 && !io.sfence.bits.rs2, "SFENCE_LINE", "flush TLB line") ccover(sfence && io.sfence.bits.rs1 && io.sfence.bits.rs2, "SFENCE_LINE_ASID", "flush TLB line/ASID") ccover(multipleHits, "MULTIPLE_HITS", "Two matching translations in TLB") } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"${if (instruction) "I" else "D"}TLB_$label", "MemorySystem;;" + desc) /** Decides which entry to be replaced * * If there is a invalid entry, replace it with priorityencoder; * if not, replace the alt entry * * @return mask for TLBEntry replacement / def replacementEntry(set: Seq[TLBEntry], alt: UInt) = { val valids = set.map(_.valid.orR).asUInt Mux(valids.andR, alt, PriorityEncoder(~valids)) } } File TLBPermissions.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes, RegionType, AddressDecoder} import freechips.rocketchip.tilelink.TLManagerParameters case class TLBPermissions( homogeneous: Bool, // if false, the below are undefined r: Bool, // readable w: Bool, // writeable x: Bool, // executable c: Bool, // cacheable a: Bool, // arithmetic ops l: Bool) // logical ops object TLBPageLookup { private case class TLBFixedPermissions( e: Boolean, // get-/put-effects r: Boolean, // readable w: Boolean, // writeable x: Boolean, // executable c: Boolean, // cacheable a: Boolean, // arithmetic ops l: Boolean) { // logical ops val useful = r \|\| w \|\| x \|\| c \|\| a \|\| l } private def groupRegions(managers: Seq[TLManagerParameters]): Map[TLBFixedPermissions, Seq[AddressSet]] = { val permissions = managers.map { m => (m.address, TLBFixedPermissions( e = Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains m.regionType, r = m.supportsGet \|\| m.supportsAcquireB, // if cached, never uses Get w = m.supportsPutFull \|\| m.supportsAcquireT, // if cached, never uses Put x = m.executable, c = m.supportsAcquireB, a = m.supportsArithmetic, l = m.supportsLogical)) } permissions .filter(_._2.useful) // get rid of no-permission devices .groupBy(_._2) // group by permission type .mapValues(seq => AddressSet.unify(seq.flatMap(_._1))) // coalesce same-permission regions .toMap } // Unmapped memory is considered to be inhomogeneous def apply(managers: Seq[TLManagerParameters], xLen: Int, cacheBlockBytes: Int, pageSize: BigInt, maxRequestBytes: Int): UInt => TLBPermissions = { require (isPow2(xLen) && xLen >= 8) require (isPow2(cacheBlockBytes) && cacheBlockBytes >= xLen/8) require (isPow2(pageSize) && pageSize >= cacheBlockBytes) val xferSizes = TransferSizes(cacheBlockBytes, cacheBlockBytes) val allSizes = TransferSizes(1, maxRequestBytes) val amoSizes = TransferSizes(4, xLen/8) val permissions = managers.foreach { m => require (!m.supportsGet \|\| m.supportsGet .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsGet} Get, but must support ${allSizes}") require (!m.supportsPutFull \|\| m.supportsPutFull .contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutFull} PutFull, but must support ${allSizes}") require (!m.supportsPutPartial \|\| m.supportsPutPartial.contains(allSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsPutPartial} PutPartial, but must support ${allSizes}") require (!m.supportsAcquireB \|\| m.supportsAcquireB .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireB} AcquireB, but must support ${xferSizes}") require (!m.supportsAcquireT \|\| m.supportsAcquireT .contains(xferSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsAcquireT} AcquireT, but must support ${xferSizes}") require (!m.supportsLogical \|\| m.supportsLogical .contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsLogical} Logical, but must support ${amoSizes}") require (!m.supportsArithmetic \|\| m.supportsArithmetic.contains(amoSizes), s"Memory region '${m.name}' at ${m.address} only supports ${m.supportsArithmetic} Arithmetic, but must support ${amoSizes}") require (!(m.supportsAcquireB && m.supportsPutFull && !m.supportsAcquireT), s"Memory region '${m.name}' supports AcquireB (cached read) and PutFull (un-cached write) but not AcquireT (cached write)") } val grouped = groupRegions(managers) .mapValues(_.filter(_.alignment >= pageSize)) // discard any region that's not big enough def lowCostProperty(prop: TLBFixedPermissions => Boolean): UInt => Bool = { val (yesm, nom) = grouped.partition { case (k, eq) => prop(k) } val (yes, no) = (yesm.values.flatten.toList, nom.values.flatten.toList) // Find the minimal bits needed to distinguish between yes and no val decisionMask = AddressDecoder(Seq(yes, no)) def simplify(x: Seq[AddressSet]) = AddressSet.unify(x.map(_.widen(~decisionMask)).distinct) val (yesf, nof) = (simplify(yes), simplify(no)) if (yesf.size < no.size) { (x: UInt) => yesf.map(_.contains(x)).foldLeft(false.B)(_ \|\| _) } else { (x: UInt) => !nof.map(_.contains(x)).foldLeft(false.B)(_ \|\| _) } } // Derive simplified property circuits (don't care when !homo) val rfn = lowCostProperty(_.r) val wfn = lowCostProperty(_.w) val xfn = lowCostProperty(_.x) val cfn = lowCostProperty(_.c) val afn = lowCostProperty(_.a) val lfn = lowCostProperty(_.l) val homo = AddressSet.unify(grouped.values.flatten.toList) (x: UInt) => TLBPermissions( homogeneous = homo.map(_.contains(x)).foldLeft(false.B)(_ \|\| _), r = rfn(x), w = wfn(x), x = xfn(x), c = cfn(x), a = afn(x), l = lfn(x)) } // Are all pageSize intervals of mapped regions homogeneous? def homogeneous(managers: Seq[TLManagerParameters], pageSize: BigInt): Boolean = { groupRegions(managers).values.forall(_.forall(_.alignment >= pageSize)) } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File PTW.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{Arbiter, Cat, Decoupled, Enum, Mux1H, OHToUInt, PopCount, PriorityEncoder, PriorityEncoderOH, RegEnable, UIntToOH, Valid, is, isPow2, log2Ceil, switch} import chisel3.withClock import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.subsystem.CacheBlockBytes import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ListBuffer /* PTE request from TLB to PTW * * TLB send a PTE request to PTW when L1TLB miss / class PTWReq(implicit p: Parameters) extends CoreBundle()(p) { val addr = UInt(vpnBits.W) val need_gpa = Bool() val vstage1 = Bool() val stage2 = Bool() } /* PTE info from L2TLB to TLB * * containing: target PTE, exceptions, two-satge tanslation info / class PTWResp(implicit p: Parameters) extends CoreBundle()(p) { /* ptw access exception / val ae_ptw = Bool() /* final access exception / val ae_final = Bool() /* page fault / val pf = Bool() /* guest page fault / val gf = Bool() /* hypervisor read / val hr = Bool() /* hypervisor write / val hw = Bool() /* hypervisor execute / val hx = Bool() /* PTE to refill L1TLB * * source: L2TLB / val pte = new PTE /* pte pglevel / val level = UInt(log2Ceil(pgLevels).W) /* fragmented_superpage support / val fragmented_superpage = Bool() /* homogeneous for both pma and pmp / val homogeneous = Bool() val gpa = Valid(UInt(vaddrBits.W)) val gpa_is_pte = Bool() } /* IO between TLB and PTW * * PTW receives : * - PTE request * - CSRs info * - pmp results from PMP(in TLB) / class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val req = Decoupled(Valid(new PTWReq)) val resp = Flipped(Valid(new PTWResp)) val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val customCSRs = Flipped(coreParams.customCSRs) } /* PTW performance statistics / class PTWPerfEvents extends Bundle { val l2miss = Bool() val l2hit = Bool() val pte_miss = Bool() val pte_hit = Bool() } /* Datapath IO between PTW and Core * * PTW receives CSRs info, pmp checks, sfence instruction info * * PTW sends its performance statistics to core / class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val ptbr = Input(new PTBR()) val hgatp = Input(new PTBR()) val vsatp = Input(new PTBR()) val sfence = Flipped(Valid(new SFenceReq)) val status = Input(new MStatus()) val hstatus = Input(new HStatus()) val gstatus = Input(new MStatus()) val pmp = Input(Vec(nPMPs, new PMP)) val perf = Output(new PTWPerfEvents()) val customCSRs = Flipped(coreParams.customCSRs) /* enable clock generated by ptw / val clock_enabled = Output(Bool()) } /* PTE template for transmission * * contains useful methods to check PTE attributes * @see RV-priv spec 4.3.1 for pgae table entry format / class PTE(implicit p: Parameters) extends CoreBundle()(p) { val reserved_for_future = UInt(10.W) val ppn = UInt(44.W) val reserved_for_software = Bits(2.W) /* dirty bit / val d = Bool() /* access bit / val a = Bool() /* global mapping / val g = Bool() /* user mode accessible / val u = Bool() /* whether the page is executable / val x = Bool() /* whether the page is writable / val w = Bool() /* whether the page is readable / val r = Bool() /* valid bit / val v = Bool() /* return true if find a pointer to next level page table / def table(dummy: Int = 0) = v && !r && !w && !x && !d && !a && !u && reserved_for_future === 0.U /* return true if find a leaf PTE / def leaf(dummy: Int = 0) = v && (r \|\| (x && !w)) && a /* user read / def ur(dummy: Int = 0) = sr() && u /* user write/ def uw(dummy: Int = 0) = sw() && u /* user execute / def ux(dummy: Int = 0) = sx() && u /* supervisor read / def sr(dummy: Int = 0) = leaf() && r /* supervisor write / def sw(dummy: Int = 0) = leaf() && w && d /* supervisor execute / def sx(dummy: Int = 0) = leaf() && x /* full permission: writable and executable in user mode / def isFullPerm(dummy: Int = 0) = uw() && ux() } /* L2TLB PTE template * * contains tag bits * @param nSets number of sets in L2TLB * @see RV-priv spec 4.3.1 for page table entry format / class L2TLBEntry(nSets: Int)(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val idxBits = log2Ceil(nSets) val tagBits = maxSVAddrBits - pgIdxBits - idxBits + (if (usingHypervisor) 1 else 0) val tag = UInt(tagBits.W) val ppn = UInt(ppnBits.W) /* dirty bit / val d = Bool() /* access bit / val a = Bool() /* user mode accessible / val u = Bool() /* whether the page is executable / val x = Bool() /* whether the page is writable / val w = Bool() /* whether the page is readable / val r = Bool() } /* PTW contains L2TLB, and performs page table walk for high level TLB, and cache queries from L1 TLBs(I$, D$, RoCC) * * It performs hierarchy page table query to mem for the desired leaf PTE and cache them in l2tlb. * Besides leaf PTEs, it also caches non-leaf PTEs in pte_cache to accerlerate the process. * * ==Structure== * - l2tlb : for leaf PTEs * - set-associative (configurable with [[CoreParams.nL2TLBEntries]]and [[CoreParams.nL2TLBWays]])) * - PLRU * - pte_cache: for non-leaf PTEs * - set-associative * - LRU * - s2_pte_cache: for non-leaf PTEs in 2-stage translation * - set-associative * - PLRU * * l2tlb Pipeline: 3 stage * {{{ * stage 0 : read * stage 1 : decode * stage 2 : hit check * }}} * ==State Machine== * s_ready: ready to reveive request from TLB * s_req: request mem; pte_cache hit judge * s_wait1: deal with l2tlb error * s_wait2: final hit judge * s_wait3: receive mem response * s_fragment_superpage: for superpage PTE * * @note l2tlb hit happens in s_req or s_wait1 * @see RV-priv spec 4.3-4.6 for Virtual-Memory System * @see RV-priv spec 8.5 for Two-Stage Address Translation * @todo details in two-stage translation / class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { /* to n TLB / val requestor = Flipped(Vec(n, new TLBPTWIO)) /* to HellaCache / val mem = new HellaCacheIO /* to Core * * contains CSRs info and performance statistics / val dpath = new DatapathPTWIO }) val s_ready :: s_req :: s_wait1 :: s_dummy1 :: s_wait2 :: s_wait3 :: s_dummy2 :: s_fragment_superpage :: Nil = Enum(8) val state = RegInit(s_ready) val l2_refill_wire = Wire(Bool()) /* Arbiter to arbite request from n TLB / val arb = Module(new Arbiter(Valid(new PTWReq), n)) // use TLB req as arbitor's input arb.io.in <> io.requestor.map(_.req) // receive req only when s_ready and not in refill arb.io.out.ready := (state === s_ready) && !l2_refill_wire val resp_valid = RegNext(VecInit(Seq.fill(io.requestor.size)(false.B))) val clock_en = state =/= s_ready \|\| l2_refill_wire \|\| arb.io.out.valid \|\| io.dpath.sfence.valid \|\| io.dpath.customCSRs.disableDCacheClockGate io.dpath.clock_enabled := usingVM.B && clock_en val gated_clock = if (!usingVM \|\| !tileParams.dcache.get.clockGate) clock else ClockGate(clock, clock_en, "ptw_clock_gate") withClock (gated_clock) { // entering gated-clock domain val invalidated = Reg(Bool()) /* current PTE level * {{{ * 0 <= count <= pgLevel-1 * count = pgLevel - 1 : leaf PTE * count < pgLevel - 1 : non-leaf PTE * }}} / val count = Reg(UInt(log2Ceil(pgLevels).W)) val resp_ae_ptw = Reg(Bool()) val resp_ae_final = Reg(Bool()) val resp_pf = Reg(Bool()) val resp_gf = Reg(Bool()) val resp_hr = Reg(Bool()) val resp_hw = Reg(Bool()) val resp_hx = Reg(Bool()) val resp_fragmented_superpage = Reg(Bool()) /* tlb request / val r_req = Reg(new PTWReq) /* current selected way in arbitor / val r_req_dest = Reg(Bits()) // to respond to L1TLB : l2_hit // to construct mem.req.addr val r_pte = Reg(new PTE) val r_hgatp = Reg(new PTBR) // 2-stage pageLevel val aux_count = Reg(UInt(log2Ceil(pgLevels).W)) /* pte for 2-stage translation / val aux_pte = Reg(new PTE) val gpa_pgoff = Reg(UInt(pgIdxBits.W)) // only valid in resp_gf case val stage2 = Reg(Bool()) val stage2_final = Reg(Bool()) val satp = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr) val r_hgatp_initial_count = pgLevels.U - minPgLevels.U - r_hgatp.additionalPgLevels /* 2-stage translation both enable / val do_both_stages = r_req.vstage1 && r_req.stage2 val max_count = count max aux_count val vpn = Mux(r_req.vstage1 && stage2, aux_pte.ppn, r_req.addr) val mem_resp_valid = RegNext(io.mem.resp.valid) val mem_resp_data = RegNext(io.mem.resp.bits.data) io.mem.uncached_resp.map { resp => assert(!(resp.valid && io.mem.resp.valid)) resp.ready := true.B when (resp.valid) { mem_resp_valid := true.B mem_resp_data := resp.bits.data } } // construct pte from mem.resp val (pte, invalid_paddr, invalid_gpa) = { val tmp = mem_resp_data.asTypeOf(new PTE()) val res = WireDefault(tmp) res.ppn := Mux(do_both_stages && !stage2, tmp.ppn(vpnBits.min(tmp.ppn.getWidth)-1, 0), tmp.ppn(ppnBits-1, 0)) when (tmp.r \|\| tmp.w \|\| tmp.x) { // for superpage mappings, make sure PPN LSBs are zero for (i <- 0 until pgLevels-1) when (count <= i.U && tmp.ppn((pgLevels-1-i)pgLevelBits-1, (pgLevels-2-i)pgLevelBits) =/= 0.U) { res.v := false.B } } (res, Mux(do_both_stages && !stage2, (tmp.ppn >> vpnBits) =/= 0.U, (tmp.ppn >> ppnBits) =/= 0.U), do_both_stages && !stage2 && checkInvalidHypervisorGPA(r_hgatp, tmp.ppn)) } // find non-leaf PTE, need traverse val traverse = pte.table() && !invalid_paddr && !invalid_gpa && count < (pgLevels-1).U /* address send to mem for enquerry / val pte_addr = if (!usingVM) 0.U else { val vpn_idxs = (0 until pgLevels).map { i => val width = pgLevelBits + (if (i <= pgLevels - minPgLevels) hypervisorExtraAddrBits else 0) (vpn >> (pgLevels - i - 1) pgLevelBits)(width - 1, 0) } val mask = Mux(stage2 && count === r_hgatp_initial_count, ((1 << (hypervisorExtraAddrBits + pgLevelBits)) - 1).U, ((1 << pgLevelBits) - 1).U) val vpn_idx = vpn_idxs(count) & mask val raw_pte_addr = ((r_pte.ppn << pgLevelBits) \| vpn_idx) << log2Ceil(xLen / 8) val size = if (usingHypervisor) vaddrBits else paddrBits //use r_pte.ppn as page table base address //use vpn slice as offset raw_pte_addr.apply(size.min(raw_pte_addr.getWidth) - 1, 0) } /** stage2_pte_cache input addr / val stage2_pte_cache_addr = if (!usingHypervisor) 0.U else { val vpn_idxs = (0 until pgLevels - 1).map { i => (r_req.addr >> (pgLevels - i - 1) pgLevelBits)(pgLevelBits - 1, 0) } val vpn_idx = vpn_idxs(aux_count) val raw_s2_pte_cache_addr = Cat(aux_pte.ppn, vpn_idx) << log2Ceil(xLen / 8) raw_s2_pte_cache_addr(vaddrBits.min(raw_s2_pte_cache_addr.getWidth) - 1, 0) } def makeFragmentedSuperpagePPN(ppn: UInt): Seq[UInt] = { (pgLevels-1 until 0 by -1).map(i => Cat(ppn >> (pgLevelBitsi), r_req.addr(((pgLevelBitsi) min vpnBits)-1, 0).padTo(pgLevelBitsi))) } /* PTECache caches non-leaf PTE * @param s2 true: 2-stage address translation / def makePTECache(s2: Boolean): (Bool, UInt) = if (coreParams.nPTECacheEntries == 0) { (false.B, 0.U) } else { val plru = new PseudoLRU(coreParams.nPTECacheEntries) val valid = RegInit(0.U(coreParams.nPTECacheEntries.W)) val tags = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor) 1 + vaddrBits else paddrBits).W))) // not include full pte, only ppn val data = Reg(Vec(coreParams.nPTECacheEntries, UInt((if (usingHypervisor && s2) vpnBits else ppnBits).W))) val can_hit = if (s2) count === r_hgatp_initial_count && aux_count < (pgLevels-1).U && r_req.vstage1 && stage2 && !stage2_final else count < (pgLevels-1).U && Mux(r_req.vstage1, stage2, !r_req.stage2) val can_refill = if (s2) do_both_stages && !stage2 && !stage2_final else can_hit val tag = if (s2) Cat(true.B, stage2_pte_cache_addr.padTo(vaddrBits)) else Cat(r_req.vstage1, pte_addr.padTo(if (usingHypervisor) vaddrBits else paddrBits)) val hits = tags.map(_ === tag).asUInt & valid val hit = hits.orR && can_hit // refill with mem response when (mem_resp_valid && traverse && can_refill && !hits.orR && !invalidated) { val r = Mux(valid.andR, plru.way, PriorityEncoder(~valid)) valid := valid \| UIntToOH(r) tags(r) := tag data(r) := pte.ppn plru.access(r) } // replace when (hit && state === s_req) { plru.access(OHToUInt(hits)) } when (io.dpath.sfence.valid && (!io.dpath.sfence.bits.rs1 \|\| usingHypervisor.B && io.dpath.sfence.bits.hg)) { valid := 0.U } val lcount = if (s2) aux_count else count for (i <- 0 until pgLevels-1) { ccover(hit && state === s_req && lcount === i.U, s"PTE_CACHE_HIT_L$i", s"PTE cache hit, level $i") } (hit, Mux1H(hits, data)) } // generate pte_cache val (pte_cache_hit, pte_cache_data) = makePTECache(false) // generate pte_cache with 2-stage translation val (stage2_pte_cache_hit, stage2_pte_cache_data) = makePTECache(true) // pte_cache hit or 2-stage pte_cache hit val pte_hit = RegNext(false.B) io.dpath.perf.pte_miss := false.B io.dpath.perf.pte_hit := pte_hit && (state === s_req) && !io.dpath.perf.l2hit assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss \|\| io.dpath.perf.pte_hit)), "PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event") // l2_refill happens when find the leaf pte val l2_refill = RegNext(false.B) l2_refill_wire := l2_refill io.dpath.perf.l2miss := false.B io.dpath.perf.l2hit := false.B // l2tlb val (l2_hit, l2_error, l2_pte, l2_tlb_ram) = if (coreParams.nL2TLBEntries == 0) (false.B, false.B, WireDefault(0.U.asTypeOf(new PTE)), None) else { val code = new ParityCode require(isPow2(coreParams.nL2TLBEntries)) require(isPow2(coreParams.nL2TLBWays)) require(coreParams.nL2TLBEntries >= coreParams.nL2TLBWays) val nL2TLBSets = coreParams.nL2TLBEntries / coreParams.nL2TLBWays require(isPow2(nL2TLBSets)) val idxBits = log2Ceil(nL2TLBSets) val l2_plru = new SetAssocLRU(nL2TLBSets, coreParams.nL2TLBWays, "plru") val ram = DescribedSRAM( name = "l2_tlb_ram", desc = "L2 TLB", size = nL2TLBSets, data = Vec(coreParams.nL2TLBWays, UInt(code.width(new L2TLBEntry(nL2TLBSets).getWidth).W)) ) val g = Reg(Vec(coreParams.nL2TLBWays, UInt(nL2TLBSets.W))) val valid = RegInit(VecInit(Seq.fill(coreParams.nL2TLBWays)(0.U(nL2TLBSets.W)))) // use r_req to construct tag val (r_tag, r_idx) = Split(Cat(r_req.vstage1, r_req.addr(maxSVAddrBits-pgIdxBits-1, 0)), idxBits) /* the valid vec for the selected set(including n ways) / val r_valid_vec = valid.map(_(r_idx)).asUInt val r_valid_vec_q = Reg(UInt(coreParams.nL2TLBWays.W)) val r_l2_plru_way = Reg(UInt(log2Ceil(coreParams.nL2TLBWays max 1).W)) r_valid_vec_q := r_valid_vec // replacement way r_l2_plru_way := (if (coreParams.nL2TLBWays > 1) l2_plru.way(r_idx) else 0.U) // refill with r_pte(leaf pte) when (l2_refill && !invalidated) { val entry = Wire(new L2TLBEntry(nL2TLBSets)) entry.ppn := r_pte.ppn entry.d := r_pte.d entry.a := r_pte.a entry.u := r_pte.u entry.x := r_pte.x entry.w := r_pte.w entry.r := r_pte.r entry.tag := r_tag // if all the way are valid, use plru to select one way to be replaced, // otherwise use PriorityEncoderOH to select one val wmask = if (coreParams.nL2TLBWays > 1) Mux(r_valid_vec_q.andR, UIntToOH(r_l2_plru_way, coreParams.nL2TLBWays), PriorityEncoderOH(~r_valid_vec_q)) else 1.U(1.W) ram.write(r_idx, VecInit(Seq.fill(coreParams.nL2TLBWays)(code.encode(entry.asUInt))), wmask.asBools) val mask = UIntToOH(r_idx) for (way <- 0 until coreParams.nL2TLBWays) { when (wmask(way)) { valid(way) := valid(way) \| mask g(way) := Mux(r_pte.g, g(way) \| mask, g(way) & ~mask) } } } // sfence happens when (io.dpath.sfence.valid) { val hg = usingHypervisor.B && io.dpath.sfence.bits.hg for (way <- 0 until coreParams.nL2TLBWays) { valid(way) := Mux(!hg && io.dpath.sfence.bits.rs1, valid(way) & ~UIntToOH(io.dpath.sfence.bits.addr(idxBits+pgIdxBits-1, pgIdxBits)), Mux(!hg && io.dpath.sfence.bits.rs2, valid(way) & g(way), 0.U)) } } val s0_valid = !l2_refill && arb.io.out.fire val s0_suitable = arb.io.out.bits.bits.vstage1 === arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.need_gpa val s1_valid = RegNext(s0_valid && s0_suitable && arb.io.out.bits.valid) val s2_valid = RegNext(s1_valid) // read from tlb idx val s1_rdata = ram.read(arb.io.out.bits.bits.addr(idxBits-1, 0), s0_valid) val s2_rdata = s1_rdata.map(s1_rdway => code.decode(RegEnable(s1_rdway, s1_valid))) val s2_valid_vec = RegEnable(r_valid_vec, s1_valid) val s2_g_vec = RegEnable(VecInit(g.map(_(r_idx))), s1_valid) val s2_error = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && s2_rdata(way).error).orR when (s2_valid && s2_error) { valid.foreach { _ := 0.U }} // decode val s2_entry_vec = s2_rdata.map(_.uncorrected.asTypeOf(new L2TLBEntry(nL2TLBSets))) val s2_hit_vec = (0 until coreParams.nL2TLBWays).map(way => s2_valid_vec(way) && (r_tag === s2_entry_vec(way).tag)) val s2_hit = s2_valid && s2_hit_vec.orR io.dpath.perf.l2miss := s2_valid && !(s2_hit_vec.orR) io.dpath.perf.l2hit := s2_hit when (s2_hit) { l2_plru.access(r_idx, OHToUInt(s2_hit_vec)) assert((PopCount(s2_hit_vec) === 1.U) \|\| s2_error, "L2 TLB multi-hit") } val s2_pte = Wire(new PTE) val s2_hit_entry = Mux1H(s2_hit_vec, s2_entry_vec) s2_pte.ppn := s2_hit_entry.ppn s2_pte.d := s2_hit_entry.d s2_pte.a := s2_hit_entry.a s2_pte.g := Mux1H(s2_hit_vec, s2_g_vec) s2_pte.u := s2_hit_entry.u s2_pte.x := s2_hit_entry.x s2_pte.w := s2_hit_entry.w s2_pte.r := s2_hit_entry.r s2_pte.v := true.B s2_pte.reserved_for_future := 0.U s2_pte.reserved_for_software := 0.U for (way <- 0 until coreParams.nL2TLBWays) { ccover(s2_hit && s2_hit_vec(way), s"L2_TLB_HIT_WAY$way", s"L2 TLB hit way$way") } (s2_hit, s2_error, s2_pte, Some(ram)) } // if SFENCE occurs during walk, don't refill PTE cache or L2 TLB until next walk invalidated := io.dpath.sfence.valid \|\| (invalidated && state =/= s_ready) // mem request io.mem.keep_clock_enabled := false.B io.mem.req.valid := state === s_req \|\| state === s_dummy1 io.mem.req.bits.phys := true.B io.mem.req.bits.cmd := M_XRD io.mem.req.bits.size := log2Ceil(xLen/8).U io.mem.req.bits.signed := false.B io.mem.req.bits.addr := pte_addr io.mem.req.bits.idx.foreach(_ := pte_addr) io.mem.req.bits.dprv := PRV.S.U // PTW accesses are S-mode by definition io.mem.req.bits.dv := do_both_stages && !stage2 io.mem.req.bits.tag := DontCare io.mem.req.bits.no_resp := false.B io.mem.req.bits.no_alloc := DontCare io.mem.req.bits.no_xcpt := DontCare io.mem.req.bits.data := DontCare io.mem.req.bits.mask := DontCare io.mem.s1_kill := l2_hit \|\| (state =/= s_wait1) \|\| resp_gf io.mem.s1_data := DontCare io.mem.s2_kill := false.B val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) require(!usingHypervisor \|\| pageGranularityPMPs, s"hypervisor requires pmpGranularity >= ${1<<pgIdxBits}") val pmaPgLevelHomogeneous = (0 until pgLevels) map { i => val pgSize = BigInt(1) << (pgIdxBits + ((pgLevels - 1 - i) pgLevelBits)) if (pageGranularityPMPs && i == pgLevels - 1) { require(TLBPageLookup.homogeneous(edge.manager.managers, pgSize), s"All memory regions must be $pgSize-byte aligned") true.B } else { TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), pgSize, xLen/8)(r_pte.ppn << pgIdxBits).homogeneous } } val pmaHomogeneous = pmaPgLevelHomogeneous(count) val pmpHomogeneous = new PMPHomogeneityChecker(io.dpath.pmp).apply(r_pte.ppn << pgIdxBits, count) val homogeneous = pmaHomogeneous && pmpHomogeneous // response to tlb for (i <- 0 until io.requestor.size) { io.requestor(i).resp.valid := resp_valid(i) io.requestor(i).resp.bits.ae_ptw := resp_ae_ptw io.requestor(i).resp.bits.ae_final := resp_ae_final io.requestor(i).resp.bits.pf := resp_pf io.requestor(i).resp.bits.gf := resp_gf io.requestor(i).resp.bits.hr := resp_hr io.requestor(i).resp.bits.hw := resp_hw io.requestor(i).resp.bits.hx := resp_hx io.requestor(i).resp.bits.pte := r_pte io.requestor(i).resp.bits.level := max_count io.requestor(i).resp.bits.homogeneous := homogeneous \|\| pageGranularityPMPs.B io.requestor(i).resp.bits.fragmented_superpage := resp_fragmented_superpage && pageGranularityPMPs.B io.requestor(i).resp.bits.gpa.valid := r_req.need_gpa io.requestor(i).resp.bits.gpa.bits := Cat(Mux(!stage2_final \|\| !r_req.vstage1 \|\| aux_count === (pgLevels - 1).U, aux_pte.ppn, makeFragmentedSuperpagePPN(aux_pte.ppn)(aux_count)), gpa_pgoff) io.requestor(i).resp.bits.gpa_is_pte := !stage2_final io.requestor(i).ptbr := io.dpath.ptbr io.requestor(i).hgatp := io.dpath.hgatp io.requestor(i).vsatp := io.dpath.vsatp io.requestor(i).customCSRs <> io.dpath.customCSRs io.requestor(i).status := io.dpath.status io.requestor(i).hstatus := io.dpath.hstatus io.requestor(i).gstatus := io.dpath.gstatus io.requestor(i).pmp := io.dpath.pmp } // control state machine val next_state = WireDefault(state) state := OptimizationBarrier(next_state) val do_switch = WireDefault(false.B) switch (state) { is (s_ready) { when (arb.io.out.fire) { val satp_initial_count = pgLevels.U - minPgLevels.U - satp.additionalPgLevels val vsatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.vsatp.additionalPgLevels val hgatp_initial_count = pgLevels.U - minPgLevels.U - io.dpath.hgatp.additionalPgLevels val aux_ppn = Mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr) r_req := arb.io.out.bits.bits r_req_dest := arb.io.chosen next_state := Mux(arb.io.out.bits.valid, s_req, s_ready) stage2 := arb.io.out.bits.bits.stage2 stage2_final := arb.io.out.bits.bits.stage2 && !arb.io.out.bits.bits.vstage1 count := Mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count) aux_count := Mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, 0.U) aux_pte.ppn := aux_ppn aux_pte.reserved_for_future := 0.U resp_ae_ptw := false.B resp_ae_final := false.B resp_pf := false.B resp_gf := checkInvalidHypervisorGPA(io.dpath.hgatp, aux_ppn) && arb.io.out.bits.bits.stage2 resp_hr := true.B resp_hw := true.B resp_hx := true.B resp_fragmented_superpage := false.B r_hgatp := io.dpath.hgatp assert(!arb.io.out.bits.bits.need_gpa \|\| arb.io.out.bits.bits.stage2) } } is (s_req) { when(stage2 && count === r_hgatp_initial_count) { gpa_pgoff := Mux(aux_count === (pgLevels-1).U, r_req.addr << (xLen/8).log2, stage2_pte_cache_addr) } // pte_cache hit when (stage2_pte_cache_hit) { aux_count := aux_count + 1.U aux_pte.ppn := stage2_pte_cache_data aux_pte.reserved_for_future := 0.U pte_hit := true.B }.elsewhen (pte_cache_hit) { count := count + 1.U pte_hit := true.B }.otherwise { next_state := Mux(io.mem.req.ready, s_wait1, s_req) } when(resp_gf) { next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_wait1) { // This Mux is for the l2_error case; the l2_hit && !l2_error case is overriden below next_state := Mux(l2_hit, s_req, s_wait2) } is (s_wait2) { next_state := s_wait3 io.dpath.perf.pte_miss := count < (pgLevels-1).U when (io.mem.s2_xcpt.ae.ld) { resp_ae_ptw := true.B next_state := s_ready resp_valid(r_req_dest) := true.B } } is (s_fragment_superpage) { next_state := s_ready resp_valid(r_req_dest) := true.B when (!homogeneous) { count := (pgLevels-1).U resp_fragmented_superpage := true.B } when (do_both_stages) { resp_fragmented_superpage := true.B } } } val merged_pte = { val superpage_masks = (0 until pgLevels).map(i => ((BigInt(1) << pte.ppn.getWidth) - (BigInt(1) << (pgLevels-1-i)pgLevelBits)).U) val superpage_mask = superpage_masks(Mux(stage2_final, max_count, (pgLevels-1).U)) val stage1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)pgLevelBits), aux_pte.ppn((pgLevels-i-1)pgLevelBits-1,0))) :+ pte.ppn val stage1_ppn = stage1_ppns(count) makePTE(stage1_ppn & superpage_mask, aux_pte) } r_pte := OptimizationBarrier( // l2tlb hit->find a leaf PTE(l2_pte), respond to L1TLB Mux(l2_hit && !l2_error && !resp_gf, l2_pte, // S2 PTE cache hit -> proceed to the next level of walking, update the r_pte with hgatp Mux(state === s_req && stage2_pte_cache_hit, makeHypervisorRootPTE(r_hgatp, stage2_pte_cache_data, l2_pte), // pte cache hit->find a non-leaf PTE(pte_cache),continue to request mem Mux(state === s_req && pte_cache_hit, makePTE(pte_cache_data, l2_pte), // 2-stage translation Mux(do_switch, makeHypervisorRootPTE(r_hgatp, pte.ppn, r_pte), // when mem respond, store mem.resp.pte Mux(mem_resp_valid, Mux(!traverse && r_req.vstage1 && stage2, merged_pte, pte), // fragment_superpage Mux(state === s_fragment_superpage && !homogeneous && count =/= (pgLevels - 1).U, makePTE(makeFragmentedSuperpagePPN(r_pte.ppn)(count), r_pte), // when tlb request come->request mem, use root address in satp(or vsatp,hgatp) Mux(arb.io.out.fire, Mux(arb.io.out.bits.bits.stage2, makeHypervisorRootPTE(io.dpath.hgatp, io.dpath.vsatp.ppn, r_pte), makePTE(satp.ppn, r_pte)), r_pte)))))))) when (l2_hit && !l2_error && !resp_gf) { assert(state === s_req \|\| state === s_wait1) next_state := s_ready resp_valid(r_req_dest) := true.B count := (pgLevels-1).U } when (mem_resp_valid) { assert(state === s_wait3) next_state := s_req when (traverse) { when (do_both_stages && !stage2) { do_switch := true.B } count := count + 1.U }.otherwise { val gf = (stage2 && !stage2_final && !pte.ur()) \|\| (pte.leaf() && pte.reserved_for_future === 0.U && invalid_gpa) val ae = pte.v && invalid_paddr val pf = pte.v && pte.reserved_for_future =/= 0.U val success = pte.v && !ae && !pf && !gf when (do_both_stages && !stage2_final && success) { when (stage2) { stage2 := false.B count := aux_count }.otherwise { stage2_final := true.B do_switch := true.B } }.otherwise { // find a leaf pte, start l2 refill l2_refill := success && count === (pgLevels-1).U && !r_req.need_gpa && (!r_req.vstage1 && !r_req.stage2 \|\| do_both_stages && aux_count === (pgLevels-1).U && pte.isFullPerm()) count := max_count when (pageGranularityPMPs.B && !(count === (pgLevels-1).U && (!do_both_stages \|\| aux_count === (pgLevels-1).U))) { next_state := s_fragment_superpage }.otherwise { next_state := s_ready resp_valid(r_req_dest) := true.B } resp_ae_ptw := ae && count < (pgLevels-1).U && pte.table() resp_ae_final := ae && pte.leaf() resp_pf := pf && !stage2 resp_gf := gf \|\| (pf && stage2) resp_hr := !stage2 \|\| (!pf && !gf && pte.ur()) resp_hw := !stage2 \|\| (!pf && !gf && pte.uw()) resp_hx := !stage2 \|\| (!pf && !gf && pte.ux()) } } } when (io.mem.s2_nack) { assert(state === s_wait2) next_state := s_req } when (do_switch) { aux_count := Mux(traverse, count + 1.U, count) count := r_hgatp_initial_count aux_pte := Mux(traverse, pte, { val s1_ppns = (0 until pgLevels-1).map(i => Cat(pte.ppn(pte.ppn.getWidth-1, (pgLevels-i-1)pgLevelBits), r_req.addr(((pgLevels-i-1)pgLevelBits min vpnBits)-1,0).padTo((pgLevels-i-1)pgLevelBits))) :+ pte.ppn makePTE(s1_ppns(count), pte) }) stage2 := true.B } for (i <- 0 until pgLevels) { val leaf = mem_resp_valid && !traverse && count === i.U ccover(leaf && pte.v && !invalid_paddr && !invalid_gpa && pte.reserved_for_future === 0.U, s"L$i", s"successful page-table access, level $i") ccover(leaf && pte.v && invalid_paddr, s"L${i}_BAD_PPN_MSB", s"PPN too large, level $i") ccover(leaf && pte.v && invalid_gpa, s"L${i}_BAD_GPA_MSB", s"GPA too large, level $i") ccover(leaf && pte.v && pte.reserved_for_future =/= 0.U, s"L${i}_BAD_RSV_MSB", s"reserved MSBs set, level $i") ccover(leaf && !mem_resp_data(0), s"L${i}_INVALID_PTE", s"page not present, level $i") if (i != pgLevels-1) ccover(leaf && !pte.v && mem_resp_data(0), s"L${i}_BAD_PPN_LSB", s"PPN LSBs not zero, level $i") } ccover(mem_resp_valid && count === (pgLevels-1).U && pte.table(), s"TOO_DEEP", s"page table too deep") ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access") ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table") } // leaving gated-clock domain private def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = if (usingVM) property.cover(cond, s"PTW_$label", "MemorySystem;;" + desc) /** Relace PTE.ppn with ppn / private def makePTE(ppn: UInt, default: PTE) = { val pte = WireDefault(default) pte.ppn := ppn pte } /* use hgatp and vpn to construct a new ppn / private def makeHypervisorRootPTE(hgatp: PTBR, vpn: UInt, default: PTE) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> (pgLevels-i)pgLevelBits)) val lsbs = WireDefault(UInt(maxHypervisorExtraAddrBits.W), idxs(count)) val pte = WireDefault(default) pte.ppn := Cat(hgatp.ppn >> maxHypervisorExtraAddrBits, lsbs) pte } /** use hgatp and vpn to check for gpa out of range / private def checkInvalidHypervisorGPA(hgatp: PTBR, vpn: UInt) = { val count = pgLevels.U - minPgLevels.U - hgatp.additionalPgLevels val idxs = (0 to pgLevels-minPgLevels).map(i => (vpn >> ((pgLevels-i)pgLevelBits)+maxHypervisorExtraAddrBits)) idxs.extract(count) =/= 0.U } } /** Mix-ins for constructing tiles that might have a PTW / trait CanHavePTW extends HasTileParameters with HasHellaCache { this: BaseTile => val module: CanHavePTWModule var nPTWPorts = 1 nDCachePorts += usingPTW.toInt } trait CanHavePTWModule extends HasHellaCacheModule { val outer: CanHavePTW val ptwPorts = ListBuffer(outer.dcache.module.io.ptw) val ptw = Module(new PTW(outer.nPTWPorts)(outer.dcache.node.edges.out(0), outer.p)) ptw.io.mem <> DontCare if (outer.usingPTW) { dcachePorts += ptw.io.mem } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File DCache.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.amba.AMBAProt import freechips.rocketchip.diplomacy.{BufferParams} import freechips.rocketchip.prci.{ClockCrossingType, RationalCrossing, SynchronousCrossing, AsynchronousCrossing, CreditedCrossing} import freechips.rocketchip.tile.{CoreBundle, LookupByHartId} import freechips.rocketchip.tilelink.{TLFIFOFixer,ClientMetadata, TLBundleA, TLAtomics, TLBundleB, TLPermissions} import freechips.rocketchip.tilelink.TLMessages.{AccessAck, HintAck, AccessAckData, Grant, GrantData, ReleaseAck} import freechips.rocketchip.util.{CanHaveErrors, ClockGate, IdentityCode, ReplacementPolicy, DescribedSRAM, property} import freechips.rocketchip.util.BooleanToAugmentedBoolean import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.UIntIsOneOf import freechips.rocketchip.util.IntToAugmentedInt import freechips.rocketchip.util.SeqToAugmentedSeq import freechips.rocketchip.util.SeqBoolBitwiseOps // TODO: delete this trait once deduplication is smart enough to avoid globally inlining matching circuits trait InlineInstance { self: chisel3.experimental.BaseModule => chisel3.experimental.annotate( new chisel3.experimental.ChiselAnnotation { def toFirrtl: firrtl.annotations.Annotation = firrtl.passes.InlineAnnotation(self.toNamed) } ) } class DCacheErrors(implicit p: Parameters) extends L1HellaCacheBundle()(p) with CanHaveErrors { val correctable = (cacheParams.tagCode.canCorrect \|\| cacheParams.dataCode.canCorrect).option(Valid(UInt(paddrBits.W))) val uncorrectable = (cacheParams.tagCode.canDetect \|\| cacheParams.dataCode.canDetect).option(Valid(UInt(paddrBits.W))) val bus = Valid(UInt(paddrBits.W)) } class DCacheDataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val addr = UInt(untagBits.W) val write = Bool() val wdata = UInt((encBits rowBytes / eccBytes).W) val wordMask = UInt((rowBytes / subWordBytes).W) val eccMask = UInt((wordBytes / eccBytes).W) val way_en = UInt(nWays.W) } class DCacheDataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) { val io = IO(new Bundle { val req = Flipped(Valid(new DCacheDataReq)) val resp = Output(Vec(nWays, UInt((req.bits.wdata.getWidth).W))) }) require(rowBits % subWordBits == 0, "rowBits must be a multiple of subWordBits") val eccMask = if (eccBits == subWordBits) Seq(true.B) else io.req.bits.eccMask.asBools val wMask = if (nWays == 1) eccMask else (0 until nWays).flatMap(i => eccMask.map(_ && io.req.bits.way_en(i))) val wWords = io.req.bits.wdata.grouped(encBits * (subWordBits / eccBits)) val addr = io.req.bits.addr >> rowOffBits val data_arrays = Seq.tabulate(rowBits / subWordBits) { i => DescribedSRAM( name = s"${tileParams.baseName}_dcache_data_arrays_${i}", desc = "DCache Data Array", size = nSets * cacheBlockBytes / rowBytes, data = Vec(nWays * (subWordBits / eccBits), UInt(encBits.W)) ) } val rdata = for ((array , i) <- data_arrays.zipWithIndex) yield { val valid = io.req.valid && ((data_arrays.size == 1).B \|\| io.req.bits.wordMask(i)) when (valid && io.req.bits.write) { val wMaskSlice = (0 until wMask.size).filter(j => i % (wordBits/subWordBits) == (j % (wordBytes/eccBytes)) / (subWordBytes/eccBytes)).map(wMask(_)) val wData = wWords(i).grouped(encBits) array.write(addr, VecInit((0 until nWays).flatMap(i => wData)), wMaskSlice) } val data = array.read(addr, valid && !io.req.bits.write) data.grouped(subWordBits / eccBits).map(_.asUInt).toSeq } (io.resp zip rdata.transpose).foreach { case (resp, data) => resp := data.asUInt } } class DCacheMetadataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) { val write = Bool() val addr = UInt(vaddrBitsExtended.W) val idx = UInt(idxBits.W) val way_en = UInt(nWays.W) val data = UInt(cacheParams.tagCode.width(new L1Metadata().getWidth).W) } class DCache(staticIdForMetadataUseOnly: Int, val crossing: ClockCrossingType)(implicit p: Parameters) extends HellaCache(staticIdForMetadataUseOnly)(p) { override lazy val module = new DCacheModule(this) } class DCacheTLBPort(implicit p: Parameters) extends CoreBundle()(p) { val req = Flipped(Decoupled(new TLBReq(coreDataBytes.log2))) val s1_resp = Output(new TLBResp(coreDataBytes.log2)) val s2_kill = Input(Bool()) } class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { val tECC = cacheParams.tagCode val dECC = cacheParams.dataCode require(subWordBits % eccBits == 0, "subWordBits must be a multiple of eccBits") require(eccBytes == 1 \|\| !dECC.isInstanceOf[IdentityCode]) require(cacheParams.silentDrop \|\| cacheParams.acquireBeforeRelease, "!silentDrop requires acquireBeforeRelease") val usingRMW = eccBytes > 1 \|\| usingAtomicsInCache val mmioOffset = outer.firstMMIO edge.manager.requireFifo(TLFIFOFixer.allVolatile) // TileLink pipelining MMIO requests val clock_en_reg = Reg(Bool()) io.cpu.clock_enabled := clock_en_reg val gated_clock = if (!cacheParams.clockGate) clock else ClockGate(clock, clock_en_reg, "dcache_clock_gate") class DCacheModuleImpl { // entering gated-clock domain val tlb = Module(new TLB(false, log2Ceil(coreDataBytes), TLBConfig(nTLBSets, nTLBWays, cacheParams.nTLBBasePageSectors, cacheParams.nTLBSuperpages))) val pma_checker = Module(new TLB(false, log2Ceil(coreDataBytes), TLBConfig(nTLBSets, nTLBWays, cacheParams.nTLBBasePageSectors, cacheParams.nTLBSuperpages)) with InlineInstance) // tags val replacer = ReplacementPolicy.fromString(cacheParams.replacementPolicy, nWays) /** Metadata Arbiter: * 0: Tag update on reset * 1: Tag update on ECC error * 2: Tag update on hit * 3: Tag update on refill * 4: Tag update on release * 5: Tag update on flush * 6: Tag update on probe * 7: Tag update on CPU request / val metaArb = Module(new Arbiter(new DCacheMetadataReq, 8) with InlineInstance) val tag_array = DescribedSRAM( name = s"${tileParams.baseName}_dcache_tag_array", desc = "DCache Tag Array", size = nSets, data = Vec(nWays, chiselTypeOf(metaArb.io.out.bits.data)) ) // data val data = Module(new DCacheDataArray) /* Data Arbiter * 0: data from pending store buffer * 1: data from TL-D refill * 2: release to TL-A * 3: hit path to CPU / val dataArb = Module(new Arbiter(new DCacheDataReq, 4) with InlineInstance) dataArb.io.in.tail.foreach(_.bits.wdata := dataArb.io.in.head.bits.wdata) // tie off write ports by default data.io.req.bits <> dataArb.io.out.bits data.io.req.valid := dataArb.io.out.valid dataArb.io.out.ready := true.B metaArb.io.out.ready := clock_en_reg val tl_out_a = Wire(chiselTypeOf(tl_out.a)) tl_out.a <> { val a_queue_depth = outer.crossing match { case RationalCrossing(_) => // TODO make this depend on the actual ratio? if (cacheParams.separateUncachedResp) (maxUncachedInFlight + 1) / 2 else 2 min maxUncachedInFlight-1 case SynchronousCrossing(BufferParams.none) => 1 // Need some buffering to guarantee livelock freedom case SynchronousCrossing(_) => 0 // Adequate buffering within the crossing case _: AsynchronousCrossing => 0 // Adequate buffering within the crossing case _: CreditedCrossing => 0 // Adequate buffering within the crossing } Queue(tl_out_a, a_queue_depth, flow = true) } val (tl_out_c, release_queue_empty) = if (cacheParams.acquireBeforeRelease) { val q = Module(new Queue(chiselTypeOf(tl_out.c.bits), cacheDataBeats, flow = true)) tl_out.c <> q.io.deq (q.io.enq, q.io.count === 0.U) } else { (tl_out.c, true.B) } val s1_valid = RegNext(io.cpu.req.fire, false.B) val s1_probe = RegNext(tl_out.b.fire, false.B) val probe_bits = RegEnable(tl_out.b.bits, tl_out.b.fire) // TODO has data now :( val s1_nack = WireDefault(false.B) val s1_valid_masked = s1_valid && !io.cpu.s1_kill val s1_valid_not_nacked = s1_valid && !s1_nack val s1_tlb_req_valid = RegNext(io.tlb_port.req.fire, false.B) val s2_tlb_req_valid = RegNext(s1_tlb_req_valid, false.B) val s0_clk_en = metaArb.io.out.valid && !metaArb.io.out.bits.write val s0_req = WireInit(io.cpu.req.bits) s0_req.addr := Cat(metaArb.io.out.bits.addr >> blockOffBits, io.cpu.req.bits.addr(blockOffBits-1,0)) s0_req.idx.foreach(_ := Cat(metaArb.io.out.bits.idx, s0_req.addr(blockOffBits-1, 0))) when (!metaArb.io.in(7).ready) { s0_req.phys := true.B } val s1_req = RegEnable(s0_req, s0_clk_en) val s1_vaddr = Cat(s1_req.idx.getOrElse(s1_req.addr) >> tagLSB, s1_req.addr(tagLSB-1, 0)) val s0_tlb_req = WireInit(io.tlb_port.req.bits) when (!io.tlb_port.req.fire) { s0_tlb_req.passthrough := s0_req.phys s0_tlb_req.vaddr := s0_req.addr s0_tlb_req.size := s0_req.size s0_tlb_req.cmd := s0_req.cmd s0_tlb_req.prv := s0_req.dprv s0_tlb_req.v := s0_req.dv } val s1_tlb_req = RegEnable(s0_tlb_req, s0_clk_en \|\| io.tlb_port.req.valid) val s1_read = isRead(s1_req.cmd) val s1_write = isWrite(s1_req.cmd) val s1_readwrite = s1_read \|\| s1_write val s1_sfence = s1_req.cmd === M_SFENCE \|\| s1_req.cmd === M_HFENCEV \|\| s1_req.cmd === M_HFENCEG val s1_flush_line = s1_req.cmd === M_FLUSH_ALL && s1_req.size(0) val s1_flush_valid = Reg(Bool()) val s1_waw_hazard = Wire(Bool()) val s_ready :: s_voluntary_writeback :: s_probe_rep_dirty :: s_probe_rep_clean :: s_probe_retry :: s_probe_rep_miss :: s_voluntary_write_meta :: s_probe_write_meta :: s_dummy :: s_voluntary_release :: Nil = Enum(10) val supports_flush = outer.flushOnFenceI \|\| coreParams.haveCFlush val flushed = RegInit(true.B) val flushing = RegInit(false.B) val flushing_req = Reg(chiselTypeOf(s1_req)) val cached_grant_wait = RegInit(false.B) val resetting = RegInit(false.B) val flushCounter = RegInit((nSets (nWays-1)).U(log2Ceil(nSets * nWays).W)) val release_ack_wait = RegInit(false.B) val release_ack_addr = Reg(UInt(paddrBits.W)) val release_state = RegInit(s_ready) val refill_way = Reg(UInt()) val any_pstore_valid = Wire(Bool()) val inWriteback = release_state.isOneOf(s_voluntary_writeback, s_probe_rep_dirty) val releaseWay = Wire(UInt()) io.cpu.req.ready := (release_state === s_ready) && !cached_grant_wait && !s1_nack // I/O MSHRs val uncachedInFlight = RegInit(VecInit(Seq.fill(maxUncachedInFlight)(false.B))) val uncachedReqs = Reg(Vec(maxUncachedInFlight, new HellaCacheReq)) val uncachedResp = WireInit(new HellaCacheReq, DontCare) // hit initiation path val s0_read = isRead(io.cpu.req.bits.cmd) dataArb.io.in(3).valid := io.cpu.req.valid && likelyNeedsRead(io.cpu.req.bits) dataArb.io.in(3).bits := dataArb.io.in(1).bits dataArb.io.in(3).bits.write := false.B dataArb.io.in(3).bits.addr := Cat(io.cpu.req.bits.idx.getOrElse(io.cpu.req.bits.addr) >> tagLSB, io.cpu.req.bits.addr(tagLSB-1, 0)) dataArb.io.in(3).bits.wordMask := { val mask = (subWordBytes.log2 until rowOffBits).foldLeft(1.U) { case (in, i) => val upper_mask = Mux((i >= wordBytes.log2).B \|\| io.cpu.req.bits.size <= i.U, 0.U, ((BigInt(1) << (1 << (i - subWordBytes.log2)))-1).U) val upper = Mux(io.cpu.req.bits.addr(i), in, 0.U) \| upper_mask val lower = Mux(io.cpu.req.bits.addr(i), 0.U, in) upper ## lower } Fill(subWordBytes / eccBytes, mask) } dataArb.io.in(3).bits.eccMask := ~0.U((wordBytes / eccBytes).W) dataArb.io.in(3).bits.way_en := ~0.U(nWays.W) when (!dataArb.io.in(3).ready && s0_read) { io.cpu.req.ready := false.B } val s1_did_read = RegEnable(dataArb.io.in(3).ready && (io.cpu.req.valid && needsRead(io.cpu.req.bits)), s0_clk_en) val s1_read_mask = RegEnable(dataArb.io.in(3).bits.wordMask, s0_clk_en) metaArb.io.in(7).valid := io.cpu.req.valid metaArb.io.in(7).bits.write := false.B metaArb.io.in(7).bits.idx := dataArb.io.in(3).bits.addr(idxMSB, idxLSB) metaArb.io.in(7).bits.addr := io.cpu.req.bits.addr metaArb.io.in(7).bits.way_en := metaArb.io.in(4).bits.way_en metaArb.io.in(7).bits.data := metaArb.io.in(4).bits.data when (!metaArb.io.in(7).ready) { io.cpu.req.ready := false.B } // address translation val s1_cmd_uses_tlb = s1_readwrite \|\| s1_flush_line \|\| s1_req.cmd === M_WOK io.ptw <> tlb.io.ptw tlb.io.kill := io.cpu.s2_kill \|\| s2_tlb_req_valid && io.tlb_port.s2_kill tlb.io.req.valid := s1_tlb_req_valid \|\| s1_valid && !io.cpu.s1_kill && s1_cmd_uses_tlb tlb.io.req.bits := s1_tlb_req when (!tlb.io.req.ready && !tlb.io.ptw.resp.valid && !io.cpu.req.bits.phys) { io.cpu.req.ready := false.B } when (!s1_tlb_req_valid && s1_valid && s1_cmd_uses_tlb && tlb.io.resp.miss) { s1_nack := true.B } tlb.io.sfence.valid := s1_valid && !io.cpu.s1_kill && s1_sfence tlb.io.sfence.bits.rs1 := s1_req.size(0) tlb.io.sfence.bits.rs2 := s1_req.size(1) tlb.io.sfence.bits.asid := io.cpu.s1_data.data tlb.io.sfence.bits.addr := s1_req.addr tlb.io.sfence.bits.hv := s1_req.cmd === M_HFENCEV tlb.io.sfence.bits.hg := s1_req.cmd === M_HFENCEG io.tlb_port.req.ready := clock_en_reg io.tlb_port.s1_resp := tlb.io.resp when (s1_tlb_req_valid && s1_valid && !(s1_req.phys && s1_req.no_xcpt)) { s1_nack := true.B } pma_checker.io <> DontCare pma_checker.io.req.bits.passthrough := true.B pma_checker.io.req.bits.vaddr := s1_req.addr pma_checker.io.req.bits.size := s1_req.size pma_checker.io.req.bits.cmd := s1_req.cmd pma_checker.io.req.bits.prv := s1_req.dprv pma_checker.io.req.bits.v := s1_req.dv val s1_paddr = Cat(Mux(s1_tlb_req_valid, s1_req.addr(paddrBits-1, pgIdxBits), tlb.io.resp.paddr >> pgIdxBits), s1_req.addr(pgIdxBits-1, 0)) val s1_victim_way = Wire(UInt()) val (s1_hit_way, s1_hit_state, s1_meta) = if (usingDataScratchpad) { val baseAddr = p(LookupByHartId)(_.dcache.flatMap(_.scratch.map(_.U)), io_hartid.get) \| io_mmio_address_prefix.get val inScratchpad = s1_paddr >= baseAddr && s1_paddr < baseAddr + (nSets * cacheBlockBytes).U val hitState = Mux(inScratchpad, ClientMetadata.maximum, ClientMetadata.onReset) val dummyMeta = L1Metadata(0.U, ClientMetadata.onReset) (inScratchpad, hitState, Seq(tECC.encode(dummyMeta.asUInt))) } else { val metaReq = metaArb.io.out val metaIdx = metaReq.bits.idx when (metaReq.valid && metaReq.bits.write) { val wmask = if (nWays == 1) Seq(true.B) else metaReq.bits.way_en.asBools tag_array.write(metaIdx, VecInit(Seq.fill(nWays)(metaReq.bits.data)), wmask) } val s1_meta = tag_array.read(metaIdx, metaReq.valid && !metaReq.bits.write) val s1_meta_uncorrected = s1_meta.map(tECC.decode(_).uncorrected.asTypeOf(new L1Metadata)) val s1_tag = s1_paddr >> tagLSB val s1_meta_hit_way = s1_meta_uncorrected.map(r => r.coh.isValid() && r.tag === s1_tag).asUInt val s1_meta_hit_state = ( s1_meta_uncorrected.map(r => Mux(r.tag === s1_tag && !s1_flush_valid, r.coh.asUInt, 0.U)) .reduce (_\|_)).asTypeOf(chiselTypeOf(ClientMetadata.onReset)) (s1_meta_hit_way, s1_meta_hit_state, s1_meta) } val s1_data_way = WireDefault(if (nWays == 1) 1.U else Mux(inWriteback, releaseWay, s1_hit_way)) val tl_d_data_encoded = Wire(chiselTypeOf(encodeData(tl_out.d.bits.data, false.B))) val s1_all_data_ways = VecInit(data.io.resp ++ (!cacheParams.separateUncachedResp).option(tl_d_data_encoded)) val s1_mask_xwr = new StoreGen(s1_req.size, s1_req.addr, 0.U, wordBytes).mask val s1_mask = Mux(s1_req.cmd === M_PWR, io.cpu.s1_data.mask, s1_mask_xwr) // for partial writes, s1_data.mask must be a subset of s1_mask_xwr assert(!(s1_valid_masked && s1_req.cmd === M_PWR) \|\| (s1_mask_xwr \| ~io.cpu.s1_data.mask).andR) val s2_valid = RegNext(s1_valid_masked && !s1_sfence, init=false.B) val s2_valid_no_xcpt = s2_valid && !io.cpu.s2_xcpt.asUInt.orR val s2_probe = RegNext(s1_probe, init=false.B) val releaseInFlight = s1_probe \|\| s2_probe \|\| release_state =/= s_ready val s2_not_nacked_in_s1 = RegNext(!s1_nack) val s2_valid_not_nacked_in_s1 = s2_valid && s2_not_nacked_in_s1 val s2_valid_masked = s2_valid_no_xcpt && s2_not_nacked_in_s1 val s2_valid_not_killed = s2_valid_masked && !io.cpu.s2_kill val s2_req = Reg(chiselTypeOf(io.cpu.req.bits)) val s2_cmd_flush_all = s2_req.cmd === M_FLUSH_ALL && !s2_req.size(0) val s2_cmd_flush_line = s2_req.cmd === M_FLUSH_ALL && s2_req.size(0) val s2_tlb_xcpt = Reg(chiselTypeOf(tlb.io.resp)) val s2_pma = Reg(chiselTypeOf(tlb.io.resp)) val s2_uncached_resp_addr = Reg(chiselTypeOf(s2_req.addr)) // should be DCE'd in synthesis when (s1_valid_not_nacked \|\| s1_flush_valid) { s2_req := s1_req s2_req.addr := s1_paddr s2_tlb_xcpt := tlb.io.resp s2_pma := Mux(s1_tlb_req_valid, pma_checker.io.resp, tlb.io.resp) } val s2_vaddr = Cat(RegEnable(s1_vaddr, s1_valid_not_nacked \|\| s1_flush_valid) >> tagLSB, s2_req.addr(tagLSB-1, 0)) val s2_read = isRead(s2_req.cmd) val s2_write = isWrite(s2_req.cmd) val s2_readwrite = s2_read \|\| s2_write val s2_flush_valid_pre_tag_ecc = RegNext(s1_flush_valid) val s1_meta_decoded = s1_meta.map(tECC.decode(_)) val s1_meta_clk_en = s1_valid_not_nacked \|\| s1_flush_valid \|\| s1_probe val s2_meta_correctable_errors = s1_meta_decoded.map(m => RegEnable(m.correctable, s1_meta_clk_en)).asUInt val s2_meta_uncorrectable_errors = s1_meta_decoded.map(m => RegEnable(m.uncorrectable, s1_meta_clk_en)).asUInt val s2_meta_error_uncorrectable = s2_meta_uncorrectable_errors.orR val s2_meta_corrected = s1_meta_decoded.map(m => RegEnable(m.corrected, s1_meta_clk_en).asTypeOf(new L1Metadata)) val s2_meta_error = (s2_meta_uncorrectable_errors \| s2_meta_correctable_errors).orR val s2_flush_valid = s2_flush_valid_pre_tag_ecc && !s2_meta_error val s2_data = { val wordsPerRow = rowBits / subWordBits val en = s1_valid \|\| inWriteback \|\| io.cpu.replay_next val word_en = Mux(inWriteback, Fill(wordsPerRow, 1.U), Mux(s1_did_read, s1_read_mask, 0.U)) val s1_way_words = s1_all_data_ways.map(_.grouped(dECC.width(eccBits) * (subWordBits / eccBits))) if (cacheParams.pipelineWayMux) { val s1_word_en = Mux(io.cpu.replay_next, 0.U, word_en) (for (i <- 0 until wordsPerRow) yield { val s2_way_en = RegEnable(Mux(s1_word_en(i), s1_data_way, 0.U), en) val s2_way_words = (0 until nWays).map(j => RegEnable(s1_way_words(j)(i), en && word_en(i))) (0 until nWays).map(j => Mux(s2_way_en(j), s2_way_words(j), 0.U)).reduce(_\|_) }).asUInt } else { val s1_word_en = Mux(!io.cpu.replay_next, word_en, UIntToOH(uncachedResp.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)), wordsPerRow)) (for (i <- 0 until wordsPerRow) yield { RegEnable(Mux1H(Mux(s1_word_en(i), s1_data_way, 0.U), s1_way_words.map(_(i))), en) }).asUInt } } val s2_probe_way = RegEnable(s1_hit_way, s1_probe) val s2_probe_state = RegEnable(s1_hit_state, s1_probe) val s2_hit_way = RegEnable(s1_hit_way, s1_valid_not_nacked) val s2_hit_state = RegEnable(s1_hit_state, s1_valid_not_nacked \|\| s1_flush_valid) val s2_waw_hazard = RegEnable(s1_waw_hazard, s1_valid_not_nacked) val s2_store_merge = Wire(Bool()) val s2_hit_valid = s2_hit_state.isValid() val (s2_hit, s2_grow_param, s2_new_hit_state) = s2_hit_state.onAccess(s2_req.cmd) val s2_data_decoded = decodeData(s2_data) val s2_word_idx = s2_req.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)) val s2_data_error = s2_data_decoded.map(_.error).orR val s2_data_error_uncorrectable = s2_data_decoded.map(_.uncorrectable).orR val s2_data_corrected = (s2_data_decoded.map(_.corrected): Seq[UInt]).asUInt val s2_data_uncorrected = (s2_data_decoded.map(_.uncorrected): Seq[UInt]).asUInt val s2_valid_hit_maybe_flush_pre_data_ecc_and_waw = s2_valid_masked && !s2_meta_error && s2_hit val s2_no_alloc_hazard = if (!usingVM \|\| pgIdxBits >= untagBits) false.B else { // make sure that any in-flight non-allocating accesses are ordered before // any allocating accesses. this can only happen if aliasing is possible. val any_no_alloc_in_flight = Reg(Bool()) when (!uncachedInFlight.asUInt.orR) { any_no_alloc_in_flight := false.B } when (s2_valid && s2_req.no_alloc) { any_no_alloc_in_flight := true.B } val s1_need_check = any_no_alloc_in_flight \|\| s2_valid && s2_req.no_alloc val concerns = (uncachedInFlight zip uncachedReqs) :+ (s2_valid && s2_req.no_alloc, s2_req) val s1_uncached_hits = concerns.map { c => val concern_wmask = new StoreGen(c._2.size, c._2.addr, 0.U, wordBytes).mask val addr_match = (c._2.addr ^ s1_paddr)(pgIdxBits+pgLevelBits-1, wordBytes.log2) === 0.U val mask_match = (concern_wmask & s1_mask_xwr).orR \|\| c._2.cmd === M_PWR \|\| s1_req.cmd === M_PWR val cmd_match = isWrite(c._2.cmd) \|\| isWrite(s1_req.cmd) c._1 && s1_need_check && cmd_match && addr_match && mask_match } val s2_uncached_hits = RegEnable(s1_uncached_hits.asUInt, s1_valid_not_nacked) s2_uncached_hits.orR } val s2_valid_hit_pre_data_ecc_and_waw = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw && s2_readwrite && !s2_no_alloc_hazard val s2_valid_flush_line = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw && s2_cmd_flush_line val s2_valid_hit_pre_data_ecc = s2_valid_hit_pre_data_ecc_and_waw && (!s2_waw_hazard \|\| s2_store_merge) val s2_valid_data_error = s2_valid_hit_pre_data_ecc_and_waw && s2_data_error val s2_valid_hit = s2_valid_hit_pre_data_ecc && !s2_data_error val s2_valid_miss = s2_valid_masked && s2_readwrite && !s2_meta_error && !s2_hit val s2_uncached = !s2_pma.cacheable \|\| s2_req.no_alloc && !s2_pma.must_alloc && !s2_hit_valid val s2_valid_cached_miss = s2_valid_miss && !s2_uncached && !uncachedInFlight.asUInt.orR dontTouch(s2_valid_cached_miss) val s2_want_victimize = (!usingDataScratchpad).B && (s2_valid_cached_miss \|\| s2_valid_flush_line \|\| s2_valid_data_error \|\| s2_flush_valid) val s2_cannot_victimize = !s2_flush_valid && io.cpu.s2_kill val s2_victimize = s2_want_victimize && !s2_cannot_victimize val s2_valid_uncached_pending = s2_valid_miss && s2_uncached && !uncachedInFlight.asUInt.andR val s2_victim_way = UIntToOH(RegEnable(s1_victim_way, s1_valid_not_nacked \|\| s1_flush_valid)) val s2_victim_or_hit_way = Mux(s2_hit_valid, s2_hit_way, s2_victim_way) val s2_victim_tag = Mux(s2_valid_data_error \|\| s2_valid_flush_line, s2_req.addr(paddrBits-1, tagLSB), Mux1H(s2_victim_way, s2_meta_corrected).tag) val s2_victim_state = Mux(s2_hit_valid, s2_hit_state, Mux1H(s2_victim_way, s2_meta_corrected).coh) val (s2_prb_ack_data, s2_report_param, probeNewCoh)= s2_probe_state.onProbe(probe_bits.param) val (s2_victim_dirty, s2_shrink_param, voluntaryNewCoh) = s2_victim_state.onCacheControl(M_FLUSH) dontTouch(s2_victim_dirty) val s2_update_meta = s2_hit_state =/= s2_new_hit_state val s2_dont_nack_uncached = s2_valid_uncached_pending && tl_out_a.ready val s2_dont_nack_misc = s2_valid_masked && !s2_meta_error && (supports_flush.B && s2_cmd_flush_all && flushed && !flushing \|\| supports_flush.B && s2_cmd_flush_line && !s2_hit \|\| s2_req.cmd === M_WOK) io.cpu.s2_nack := s2_valid_no_xcpt && !s2_dont_nack_uncached && !s2_dont_nack_misc && !s2_valid_hit when (io.cpu.s2_nack \|\| (s2_valid_hit_pre_data_ecc_and_waw && s2_update_meta)) { s1_nack := true.B } // tag updates on ECC errors val s2_first_meta_corrected = PriorityMux(s2_meta_correctable_errors, s2_meta_corrected) metaArb.io.in(1).valid := s2_meta_error && (s2_valid_masked \|\| s2_flush_valid_pre_tag_ecc \|\| s2_probe) metaArb.io.in(1).bits.write := true.B metaArb.io.in(1).bits.way_en := s2_meta_uncorrectable_errors \| Mux(s2_meta_error_uncorrectable, 0.U, PriorityEncoderOH(s2_meta_correctable_errors)) metaArb.io.in(1).bits.idx := Mux(s2_probe, probeIdx(probe_bits), s2_vaddr(idxMSB, idxLSB)) metaArb.io.in(1).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, metaArb.io.in(1).bits.idx << blockOffBits) metaArb.io.in(1).bits.data := tECC.encode { val new_meta = WireDefault(s2_first_meta_corrected) when (s2_meta_error_uncorrectable) { new_meta.coh := ClientMetadata.onReset } new_meta.asUInt } // tag updates on hit metaArb.io.in(2).valid := s2_valid_hit_pre_data_ecc_and_waw && s2_update_meta metaArb.io.in(2).bits.write := !io.cpu.s2_kill metaArb.io.in(2).bits.way_en := s2_victim_or_hit_way metaArb.io.in(2).bits.idx := s2_vaddr(idxMSB, idxLSB) metaArb.io.in(2).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, s2_vaddr(idxMSB, 0)) metaArb.io.in(2).bits.data := tECC.encode(L1Metadata(s2_req.addr >> tagLSB, s2_new_hit_state).asUInt) // load reservations and TL error reporting val s2_lr = (usingAtomics && !usingDataScratchpad).B && s2_req.cmd === M_XLR val s2_sc = (usingAtomics && !usingDataScratchpad).B && s2_req.cmd === M_XSC val lrscCount = RegInit(0.U) val lrscValid = lrscCount > lrscBackoff.U val lrscBackingOff = lrscCount > 0.U && !lrscValid val lrscAddr = Reg(UInt()) val lrscAddrMatch = lrscAddr === (s2_req.addr >> blockOffBits) val s2_sc_fail = s2_sc && !(lrscValid && lrscAddrMatch) when ((s2_valid_hit && s2_lr && !cached_grant_wait \|\| s2_valid_cached_miss) && !io.cpu.s2_kill) { lrscCount := Mux(s2_hit, (lrscCycles - 1).U, 0.U) lrscAddr := s2_req.addr >> blockOffBits } when (lrscCount > 0.U) { lrscCount := lrscCount - 1.U } when (s2_valid_not_killed && lrscValid) { lrscCount := lrscBackoff.U } when (s1_probe) { lrscCount := 0.U } // don't perform data correction if it might clobber a recent store val s2_correct = s2_data_error && !any_pstore_valid && !RegNext(any_pstore_valid \|\| s2_valid) && usingDataScratchpad.B // pending store buffer val s2_valid_correct = s2_valid_hit_pre_data_ecc_and_waw && s2_correct && !io.cpu.s2_kill def s2_store_valid_pre_kill = s2_valid_hit && s2_write && !s2_sc_fail def s2_store_valid = s2_store_valid_pre_kill && !io.cpu.s2_kill val pstore1_cmd = RegEnable(s1_req.cmd, s1_valid_not_nacked && s1_write) val pstore1_addr = RegEnable(s1_vaddr, s1_valid_not_nacked && s1_write) val pstore1_data = RegEnable(io.cpu.s1_data.data, s1_valid_not_nacked && s1_write) val pstore1_way = RegEnable(s1_hit_way, s1_valid_not_nacked && s1_write) val pstore1_mask = RegEnable(s1_mask, s1_valid_not_nacked && s1_write) val pstore1_storegen_data = WireDefault(pstore1_data) val pstore1_rmw = usingRMW.B && RegEnable(needsRead(s1_req), s1_valid_not_nacked && s1_write) val pstore1_merge_likely = s2_valid_not_nacked_in_s1 && s2_write && s2_store_merge val pstore1_merge = s2_store_valid && s2_store_merge val pstore2_valid = RegInit(false.B) val pstore_drain_opportunistic = !(io.cpu.req.valid && likelyNeedsRead(io.cpu.req.bits)) && !(s1_valid && s1_waw_hazard) val pstore_drain_on_miss = releaseInFlight \|\| RegNext(io.cpu.s2_nack) val pstore1_held = RegInit(false.B) val pstore1_valid_likely = s2_valid && s2_write \|\| pstore1_held def pstore1_valid_not_rmw(s2_kill: Bool) = s2_valid_hit_pre_data_ecc && s2_write && !s2_kill \|\| pstore1_held val pstore1_valid = s2_store_valid \|\| pstore1_held any_pstore_valid := pstore1_held \|\| pstore2_valid val pstore_drain_structural = pstore1_valid_likely && pstore2_valid && ((s1_valid && s1_write) \|\| pstore1_rmw) assert(pstore1_rmw \|\| pstore1_valid_not_rmw(io.cpu.s2_kill) === pstore1_valid) ccover(pstore_drain_structural, "STORE_STRUCTURAL_HAZARD", "D$ read-modify-write structural hazard") ccover(pstore1_valid && pstore_drain_on_miss, "STORE_DRAIN_ON_MISS", "D$ store buffer drain on miss") ccover(s1_valid_not_nacked && s1_waw_hazard, "WAW_HAZARD", "D$ write-after-write hazard") def should_pstore_drain(truly: Bool) = { val s2_kill = truly && io.cpu.s2_kill !pstore1_merge_likely && (usingRMW.B && pstore_drain_structural \|\| (((pstore1_valid_not_rmw(s2_kill) && !pstore1_rmw) \|\| pstore2_valid) && (pstore_drain_opportunistic \|\| pstore_drain_on_miss))) } val pstore_drain = should_pstore_drain(true.B) pstore1_held := (s2_store_valid && !s2_store_merge \|\| pstore1_held) && pstore2_valid && !pstore_drain val advance_pstore1 = (pstore1_valid \|\| s2_valid_correct) && (pstore2_valid === pstore_drain) pstore2_valid := pstore2_valid && !pstore_drain \|\| advance_pstore1 val pstore2_addr = RegEnable(Mux(s2_correct, s2_vaddr, pstore1_addr), advance_pstore1) val pstore2_way = RegEnable(Mux(s2_correct, s2_hit_way, pstore1_way), advance_pstore1) val pstore2_storegen_data = { for (i <- 0 until wordBytes) yield RegEnable(pstore1_storegen_data(8(i+1)-1, 8i), advance_pstore1 \|\| pstore1_merge && pstore1_mask(i)) }.asUInt val pstore2_storegen_mask = { val mask = Reg(UInt(wordBytes.W)) when (advance_pstore1 \|\| pstore1_merge) { val mergedMask = pstore1_mask \| Mux(pstore1_merge, mask, 0.U) mask := ~Mux(s2_correct, 0.U, ~mergedMask) } mask } s2_store_merge := (if (eccBytes == 1) false.B else { ccover(pstore1_merge, "STORE_MERGED", "D$ store merged") // only merge stores to ECC granules that are already stored-to, to avoid // WAW hazards val wordMatch = (eccMask(pstore2_storegen_mask) \| ~eccMask(pstore1_mask)).andR val idxMatch = s2_vaddr(untagBits-1, log2Ceil(wordBytes)) === pstore2_addr(untagBits-1, log2Ceil(wordBytes)) val tagMatch = (s2_hit_way & pstore2_way).orR pstore2_valid && wordMatch && idxMatch && tagMatch }) dataArb.io.in(0).valid := should_pstore_drain(false.B) dataArb.io.in(0).bits.write := pstore_drain dataArb.io.in(0).bits.addr := Mux(pstore2_valid, pstore2_addr, pstore1_addr) dataArb.io.in(0).bits.way_en := Mux(pstore2_valid, pstore2_way, pstore1_way) dataArb.io.in(0).bits.wdata := encodeData(Fill(rowWords, Mux(pstore2_valid, pstore2_storegen_data, pstore1_data)), false.B) dataArb.io.in(0).bits.wordMask := { val eccMask = dataArb.io.in(0).bits.eccMask.asBools.grouped(subWordBytes/eccBytes).map(_.orR).toSeq.asUInt val wordMask = UIntToOH(Mux(pstore2_valid, pstore2_addr, pstore1_addr).extract(rowOffBits-1, wordBytes.log2)) FillInterleaved(wordBytes/subWordBytes, wordMask) & Fill(rowBytes/wordBytes, eccMask) } dataArb.io.in(0).bits.eccMask := eccMask(Mux(pstore2_valid, pstore2_storegen_mask, pstore1_mask)) // store->load RAW hazard detection def s1Depends(addr: UInt, mask: UInt) = addr(idxMSB, wordOffBits) === s1_vaddr(idxMSB, wordOffBits) && Mux(s1_write, (eccByteMask(mask) & eccByteMask(s1_mask_xwr)).orR, (mask & s1_mask_xwr).orR) val s1_hazard = (pstore1_valid_likely && s1Depends(pstore1_addr, pstore1_mask)) \|\| (pstore2_valid && s1Depends(pstore2_addr, pstore2_storegen_mask)) val s1_raw_hazard = s1_read && s1_hazard s1_waw_hazard := (if (eccBytes == 1) false.B else { ccover(s1_valid_not_nacked && s1_waw_hazard, "WAW_HAZARD", "D$ write-after-write hazard") s1_write && (s1_hazard \|\| needsRead(s1_req) && !s1_did_read) }) when (s1_valid && s1_raw_hazard) { s1_nack := true.B } // performance hints to processor io.cpu.s2_nack_cause_raw := RegNext(s1_raw_hazard) \|\| !(!s2_waw_hazard \|\| s2_store_merge) // Prepare a TileLink request message that initiates a transaction val a_source = PriorityEncoder(~uncachedInFlight.asUInt << mmioOffset) // skip the MSHR val acquire_address = (s2_req.addr >> idxLSB) << idxLSB val access_address = s2_req.addr val a_size = s2_req.size val a_data = Fill(beatWords, pstore1_data) val a_mask = pstore1_mask << (access_address.extract(beatBytes.log2-1, wordBytes.log2) << 3) val get = edge.Get(a_source, access_address, a_size)._2 val put = edge.Put(a_source, access_address, a_size, a_data)._2 val putpartial = edge.Put(a_source, access_address, a_size, a_data, a_mask)._2 val atomics = if (edge.manager.anySupportLogical) { MuxLookup(s2_req.cmd, WireDefault(0.U.asTypeOf(new TLBundleA(edge.bundle))))(Array( M_XA_SWAP -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.SWAP)._2, M_XA_XOR -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.XOR) ._2, M_XA_OR -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.OR) ._2, M_XA_AND -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.AND) ._2, M_XA_ADD -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.ADD)._2, M_XA_MIN -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MIN)._2, M_XA_MAX -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MAX)._2, M_XA_MINU -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MINU)._2, M_XA_MAXU -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MAXU)._2)) } else { // If no managers support atomics, assert fail if processor asks for them assert (!(tl_out_a.valid && s2_read && s2_write && s2_uncached)) WireDefault(new TLBundleA(edge.bundle), DontCare) } tl_out_a.valid := !io.cpu.s2_kill && (s2_valid_uncached_pending \|\| (s2_valid_cached_miss && !(release_ack_wait && (s2_req.addr ^ release_ack_addr)(((pgIdxBits + pgLevelBits) min paddrBits) - 1, idxLSB) === 0.U) && (cacheParams.acquireBeforeRelease.B && !release_ack_wait && release_queue_empty \|\| !s2_victim_dirty))) tl_out_a.bits := Mux(!s2_uncached, acquire(s2_vaddr, s2_req.addr, s2_grow_param), Mux(!s2_write, get, Mux(s2_req.cmd === M_PWR, putpartial, Mux(!s2_read, put, atomics)))) // Drive APROT Bits tl_out_a.bits.user.lift(AMBAProt).foreach { x => val user_bit_cacheable = s2_pma.cacheable x.privileged := s2_req.dprv === PRV.M.U \|\| user_bit_cacheable // if the address is cacheable, enable outer caches x.bufferable := user_bit_cacheable x.modifiable := user_bit_cacheable x.readalloc := user_bit_cacheable x.writealloc := user_bit_cacheable // Following are always tied off x.fetch := false.B x.secure := true.B } // Set pending bits for outstanding TileLink transaction val a_sel = UIntToOH(a_source, maxUncachedInFlight+mmioOffset) >> mmioOffset when (tl_out_a.fire) { when (s2_uncached) { (a_sel.asBools zip (uncachedInFlight zip uncachedReqs)) foreach { case (s, (f, r)) => when (s) { f := true.B r := s2_req r.cmd := Mux(s2_write, Mux(s2_req.cmd === M_PWR, M_PWR, M_XWR), M_XRD) } } }.otherwise { cached_grant_wait := true.B refill_way := s2_victim_or_hit_way } } // grant val (d_first, d_last, d_done, d_address_inc) = edge.addr_inc(tl_out.d) val (d_opc, grantIsUncached, grantIsUncachedData) = { val uncachedGrantOpcodesSansData = Seq(AccessAck, HintAck) val uncachedGrantOpcodesWithData = Seq(AccessAckData) val uncachedGrantOpcodes = uncachedGrantOpcodesWithData ++ uncachedGrantOpcodesSansData val whole_opc = tl_out.d.bits.opcode if (usingDataScratchpad) { assert(!tl_out.d.valid \|\| whole_opc.isOneOf(uncachedGrantOpcodes)) // the only valid TL-D messages are uncached, so we can do some pruning val opc = whole_opc(uncachedGrantOpcodes.map(_.getWidth).max - 1, 0) val data = DecodeLogic(opc, uncachedGrantOpcodesWithData, uncachedGrantOpcodesSansData) (opc, true.B, data) } else { (whole_opc, whole_opc.isOneOf(uncachedGrantOpcodes), whole_opc.isOneOf(uncachedGrantOpcodesWithData)) } } tl_d_data_encoded := encodeData(tl_out.d.bits.data, tl_out.d.bits.corrupt && !io.ptw.customCSRs.suppressCorruptOnGrantData && !grantIsUncached) val grantIsCached = d_opc.isOneOf(Grant, GrantData) val grantIsVoluntary = d_opc === ReleaseAck // Clears a different pending bit val grantIsRefill = d_opc === GrantData // Writes the data array val grantInProgress = RegInit(false.B) val blockProbeAfterGrantCount = RegInit(0.U) when (blockProbeAfterGrantCount > 0.U) { blockProbeAfterGrantCount := blockProbeAfterGrantCount - 1.U } val canAcceptCachedGrant = !release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta, s_voluntary_release) tl_out.d.ready := Mux(grantIsCached, (!d_first \|\| tl_out.e.ready) && canAcceptCachedGrant, true.B) val uncachedRespIdxOH = UIntToOH(tl_out.d.bits.source, maxUncachedInFlight+mmioOffset) >> mmioOffset uncachedResp := Mux1H(uncachedRespIdxOH, uncachedReqs) when (tl_out.d.fire) { when (grantIsCached) { grantInProgress := true.B assert(cached_grant_wait, "A GrantData was unexpected by the dcache.") when(d_last) { cached_grant_wait := false.B grantInProgress := false.B blockProbeAfterGrantCount := (blockProbeAfterGrantCycles - 1).U replacer.miss } } .elsewhen (grantIsUncached) { (uncachedRespIdxOH.asBools zip uncachedInFlight) foreach { case (s, f) => when (s && d_last) { assert(f, "An AccessAck was unexpected by the dcache.") // TODO must handle Ack coming back on same cycle! f := false.B } } when (grantIsUncachedData) { if (!cacheParams.separateUncachedResp) { if (!cacheParams.pipelineWayMux) s1_data_way := 1.U << nWays s2_req.cmd := M_XRD s2_req.size := uncachedResp.size s2_req.signed := uncachedResp.signed s2_req.tag := uncachedResp.tag s2_req.addr := { require(rowOffBits >= beatOffBits) val dontCareBits = s1_paddr >> rowOffBits << rowOffBits dontCareBits \| uncachedResp.addr(beatOffBits-1, 0) } s2_uncached_resp_addr := uncachedResp.addr } } } .elsewhen (grantIsVoluntary) { assert(release_ack_wait, "A ReleaseAck was unexpected by the dcache.") // TODO should handle Ack coming back on same cycle! release_ack_wait := false.B } } // Finish TileLink transaction by issuing a GrantAck tl_out.e.valid := tl_out.d.valid && d_first && grantIsCached && canAcceptCachedGrant tl_out.e.bits := edge.GrantAck(tl_out.d.bits) assert(tl_out.e.fire === (tl_out.d.fire && d_first && grantIsCached)) // data refill // note this ready-valid signaling ignores E-channel backpressure, which // benignly means the data RAM might occasionally be redundantly written dataArb.io.in(1).valid := tl_out.d.valid && grantIsRefill && canAcceptCachedGrant when (grantIsRefill && !dataArb.io.in(1).ready) { tl_out.e.valid := false.B tl_out.d.ready := false.B } if (!usingDataScratchpad) { dataArb.io.in(1).bits.write := true.B dataArb.io.in(1).bits.addr := (s2_vaddr >> idxLSB) << idxLSB \| d_address_inc dataArb.io.in(1).bits.way_en := refill_way dataArb.io.in(1).bits.wdata := tl_d_data_encoded dataArb.io.in(1).bits.wordMask := ~0.U((rowBytes / subWordBytes).W) dataArb.io.in(1).bits.eccMask := ~0.U((wordBytes / eccBytes).W) } else { dataArb.io.in(1).bits := dataArb.io.in(0).bits } // tag updates on refill // ignore backpressure from metaArb, which can only be caused by tag ECC // errors on hit-under-miss. failing to write the new tag will leave the // line invalid, so we'll simply request the line again later. metaArb.io.in(3).valid := grantIsCached && d_done && !tl_out.d.bits.denied metaArb.io.in(3).bits.write := true.B metaArb.io.in(3).bits.way_en := refill_way metaArb.io.in(3).bits.idx := s2_vaddr(idxMSB, idxLSB) metaArb.io.in(3).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, s2_vaddr(idxMSB, 0)) metaArb.io.in(3).bits.data := tECC.encode(L1Metadata(s2_req.addr >> tagLSB, s2_hit_state.onGrant(s2_req.cmd, tl_out.d.bits.param)).asUInt) if (!cacheParams.separateUncachedResp) { // don't accept uncached grants if there's a structural hazard on s2_data... val blockUncachedGrant = Reg(Bool()) blockUncachedGrant := dataArb.io.out.valid when (grantIsUncachedData && (blockUncachedGrant \|\| s1_valid)) { tl_out.d.ready := false.B // ...but insert bubble to guarantee grant's eventual forward progress when (tl_out.d.valid) { io.cpu.req.ready := false.B dataArb.io.in(1).valid := true.B dataArb.io.in(1).bits.write := false.B blockUncachedGrant := !dataArb.io.in(1).ready } } } ccover(tl_out.d.valid && !tl_out.d.ready, "BLOCK_D", "D$ D-channel blocked") // Handle an incoming TileLink Probe message val block_probe_for_core_progress = blockProbeAfterGrantCount > 0.U \|\| lrscValid val block_probe_for_pending_release_ack = release_ack_wait && (tl_out.b.bits.address ^ release_ack_addr)(((pgIdxBits + pgLevelBits) min paddrBits) - 1, idxLSB) === 0.U val block_probe_for_ordering = releaseInFlight \|\| block_probe_for_pending_release_ack \|\| grantInProgress metaArb.io.in(6).valid := tl_out.b.valid && (!block_probe_for_core_progress \|\| lrscBackingOff) tl_out.b.ready := metaArb.io.in(6).ready && !(block_probe_for_core_progress \|\| block_probe_for_ordering \|\| s1_valid \|\| s2_valid) metaArb.io.in(6).bits.write := false.B metaArb.io.in(6).bits.idx := probeIdx(tl_out.b.bits) metaArb.io.in(6).bits.addr := Cat(io.cpu.req.bits.addr >> paddrBits, tl_out.b.bits.address) metaArb.io.in(6).bits.way_en := metaArb.io.in(4).bits.way_en metaArb.io.in(6).bits.data := metaArb.io.in(4).bits.data // replacement policy s1_victim_way := (if (replacer.perSet && nWays > 1) { val repl_array = Mem(nSets, UInt(replacer.nBits.W)) val s1_repl_idx = s1_req.addr(idxBits+blockOffBits-1, blockOffBits) val s2_repl_idx = s2_vaddr(idxBits+blockOffBits-1, blockOffBits) val s2_repl_state = Reg(UInt(replacer.nBits.W)) val s2_new_repl_state = replacer.get_next_state(s2_repl_state, OHToUInt(s2_hit_way)) val s2_repl_wen = s2_valid_masked && s2_hit_way.orR && s2_repl_state =/= s2_new_repl_state val s1_repl_state = Mux(s2_repl_wen && s2_repl_idx === s1_repl_idx, s2_new_repl_state, repl_array(s1_repl_idx)) when (s1_valid_not_nacked) { s2_repl_state := s1_repl_state } val waddr = Mux(resetting, flushCounter(idxBits-1, 0), s2_repl_idx) val wdata = Mux(resetting, 0.U, s2_new_repl_state) val wen = resetting \|\| s2_repl_wen when (wen) { repl_array(waddr) := wdata } replacer.get_replace_way(s1_repl_state) } else { replacer.way }) // release val (c_first, c_last, releaseDone, c_count) = edge.count(tl_out_c) val releaseRejected = Wire(Bool()) val s1_release_data_valid = RegNext(dataArb.io.in(2).fire) val s2_release_data_valid = RegNext(s1_release_data_valid && !releaseRejected) releaseRejected := s2_release_data_valid && !tl_out_c.fire val releaseDataBeat = Cat(0.U, c_count) + Mux(releaseRejected, 0.U, s1_release_data_valid + Cat(0.U, s2_release_data_valid)) val nackResponseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = TLPermissions.NtoN) val cleanReleaseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = s2_report_param) val dirtyReleaseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = s2_report_param, data = 0.U) tl_out_c.valid := (s2_release_data_valid \|\| (!cacheParams.silentDrop.B && release_state === s_voluntary_release)) && !(c_first && release_ack_wait) tl_out_c.bits := nackResponseMessage val newCoh = WireDefault(probeNewCoh) releaseWay := s2_probe_way if (!usingDataScratchpad) { when (s2_victimize) { assert(s2_valid_flush_line \|\| s2_flush_valid \|\| io.cpu.s2_nack) val discard_line = s2_valid_flush_line && s2_req.size(1) \|\| s2_flush_valid && flushing_req.size(1) release_state := Mux(s2_victim_dirty && !discard_line, s_voluntary_writeback, Mux(!cacheParams.silentDrop.B && !release_ack_wait && release_queue_empty && s2_victim_state.isValid() && (s2_valid_flush_line \|\| s2_flush_valid \|\| s2_readwrite && !s2_hit_valid), s_voluntary_release, s_voluntary_write_meta)) probe_bits := addressToProbe(s2_vaddr, Cat(s2_victim_tag, s2_req.addr(tagLSB-1, idxLSB)) << idxLSB) } when (s2_probe) { val probeNack = WireDefault(true.B) when (s2_meta_error) { release_state := s_probe_retry }.elsewhen (s2_prb_ack_data) { release_state := s_probe_rep_dirty }.elsewhen (s2_probe_state.isValid()) { tl_out_c.valid := true.B tl_out_c.bits := cleanReleaseMessage release_state := Mux(releaseDone, s_probe_write_meta, s_probe_rep_clean) }.otherwise { tl_out_c.valid := true.B probeNack := !releaseDone release_state := Mux(releaseDone, s_ready, s_probe_rep_miss) } when (probeNack) { s1_nack := true.B } } when (release_state === s_probe_retry) { metaArb.io.in(6).valid := true.B metaArb.io.in(6).bits.idx := probeIdx(probe_bits) metaArb.io.in(6).bits.addr := Cat(io.cpu.req.bits.addr >> paddrBits, probe_bits.address) when (metaArb.io.in(6).ready) { release_state := s_ready s1_probe := true.B } } when (release_state === s_probe_rep_miss) { tl_out_c.valid := true.B when (releaseDone) { release_state := s_ready } } when (release_state === s_probe_rep_clean) { tl_out_c.valid := true.B tl_out_c.bits := cleanReleaseMessage when (releaseDone) { release_state := s_probe_write_meta } } when (release_state === s_probe_rep_dirty) { tl_out_c.bits := dirtyReleaseMessage when (releaseDone) { release_state := s_probe_write_meta } } when (release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta, s_voluntary_release)) { when (release_state === s_voluntary_release) { tl_out_c.bits := edge.Release(fromSource = 0.U, toAddress = 0.U, lgSize = lgCacheBlockBytes.U, shrinkPermissions = s2_shrink_param)._2 }.otherwise { tl_out_c.bits := edge.Release(fromSource = 0.U, toAddress = 0.U, lgSize = lgCacheBlockBytes.U, shrinkPermissions = s2_shrink_param, data = 0.U)._2 } newCoh := voluntaryNewCoh releaseWay := s2_victim_or_hit_way when (releaseDone) { release_state := s_voluntary_write_meta } when (tl_out_c.fire && c_first) { release_ack_wait := true.B release_ack_addr := probe_bits.address } } tl_out_c.bits.source := probe_bits.source tl_out_c.bits.address := probe_bits.address tl_out_c.bits.data := s2_data_corrected tl_out_c.bits.corrupt := inWriteback && s2_data_error_uncorrectable } tl_out_c.bits.user.lift(AMBAProt).foreach { x => x.fetch := false.B x.secure := true.B x.privileged := true.B x.bufferable := true.B x.modifiable := true.B x.readalloc := true.B x.writealloc := true.B } dataArb.io.in(2).valid := inWriteback && releaseDataBeat < refillCycles.U dataArb.io.in(2).bits := dataArb.io.in(1).bits dataArb.io.in(2).bits.write := false.B dataArb.io.in(2).bits.addr := (probeIdx(probe_bits) << blockOffBits) \| (releaseDataBeat(log2Up(refillCycles)-1,0) << rowOffBits) dataArb.io.in(2).bits.wordMask := ~0.U((rowBytes / subWordBytes).W) dataArb.io.in(2).bits.eccMask := ~0.U((wordBytes / eccBytes).W) dataArb.io.in(2).bits.way_en := ~0.U(nWays.W) metaArb.io.in(4).valid := release_state.isOneOf(s_voluntary_write_meta, s_probe_write_meta) metaArb.io.in(4).bits.write := true.B metaArb.io.in(4).bits.way_en := releaseWay metaArb.io.in(4).bits.idx := probeIdx(probe_bits) metaArb.io.in(4).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, probe_bits.address(idxMSB, 0)) metaArb.io.in(4).bits.data := tECC.encode(L1Metadata(tl_out_c.bits.address >> tagLSB, newCoh).asUInt) when (metaArb.io.in(4).fire) { release_state := s_ready } // cached response (io.cpu.resp.bits: Data).waiveAll :<>= (s2_req: Data).waiveAll io.cpu.resp.bits.has_data := s2_read io.cpu.resp.bits.replay := false.B io.cpu.s2_uncached := s2_uncached && !s2_hit io.cpu.s2_paddr := s2_req.addr io.cpu.s2_gpa := s2_tlb_xcpt.gpa io.cpu.s2_gpa_is_pte := s2_tlb_xcpt.gpa_is_pte // report whether there are any outstanding accesses. disregard any // slave-port accesses, since they don't affect local memory ordering. val s1_isSlavePortAccess = s1_req.no_xcpt val s2_isSlavePortAccess = s2_req.no_xcpt io.cpu.ordered := !(s1_valid && !s1_isSlavePortAccess \|\| s2_valid && !s2_isSlavePortAccess \|\| cached_grant_wait \|\| uncachedInFlight.asUInt.orR) io.cpu.store_pending := (cached_grant_wait && isWrite(s2_req.cmd)) \|\| uncachedInFlight.asUInt.orR val s1_xcpt_valid = tlb.io.req.valid && !s1_isSlavePortAccess && !s1_nack io.cpu.s2_xcpt := Mux(RegNext(s1_xcpt_valid), s2_tlb_xcpt, 0.U.asTypeOf(s2_tlb_xcpt)) if (usingDataScratchpad) { assert(!(s2_valid_masked && s2_req.cmd.isOneOf(M_XLR, M_XSC))) } else { ccover(tl_out.b.valid && !tl_out.b.ready, "BLOCK_B", "D$ B-channel blocked") } // uncached response val s1_uncached_data_word = { val word_idx = uncachedResp.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)) val words = tl_out.d.bits.data.grouped(wordBits) words(word_idx) } val s2_uncached_data_word = RegEnable(s1_uncached_data_word, io.cpu.replay_next) val doUncachedResp = RegNext(io.cpu.replay_next) io.cpu.resp.valid := (s2_valid_hit_pre_data_ecc \|\| doUncachedResp) && !s2_data_error io.cpu.replay_next := tl_out.d.fire && grantIsUncachedData && !cacheParams.separateUncachedResp.B when (doUncachedResp) { assert(!s2_valid_hit) io.cpu.resp.bits.replay := true.B io.cpu.resp.bits.addr := s2_uncached_resp_addr } io.cpu.uncached_resp.map { resp => resp.valid := tl_out.d.valid && grantIsUncachedData resp.bits.tag := uncachedResp.tag resp.bits.size := uncachedResp.size resp.bits.signed := uncachedResp.signed resp.bits.data := new LoadGen(uncachedResp.size, uncachedResp.signed, uncachedResp.addr, s1_uncached_data_word, false.B, wordBytes).data resp.bits.data_raw := s1_uncached_data_word when (grantIsUncachedData && !resp.ready) { tl_out.d.ready := false.B } } // load data subword mux/sign extension val s2_data_word = (0 until rowBits by wordBits).map(i => s2_data_uncorrected(wordBits+i-1,i)).reduce(_\|_) val s2_data_word_corrected = (0 until rowBits by wordBits).map(i => s2_data_corrected(wordBits+i-1,i)).reduce(_\|_) val s2_data_word_possibly_uncached = Mux(cacheParams.pipelineWayMux.B && doUncachedResp, s2_uncached_data_word, 0.U) \| s2_data_word val loadgen = new LoadGen(s2_req.size, s2_req.signed, s2_req.addr, s2_data_word_possibly_uncached, s2_sc, wordBytes) io.cpu.resp.bits.data := loadgen.data \| s2_sc_fail io.cpu.resp.bits.data_word_bypass := loadgen.wordData io.cpu.resp.bits.data_raw := s2_data_word io.cpu.resp.bits.store_data := pstore1_data // AMOs if (usingRMW) { val amoalus = (0 until coreDataBits / xLen).map { i => val amoalu = Module(new AMOALU(xLen)) amoalu.io.mask := pstore1_mask >> (i * xBytes) amoalu.io.cmd := (if (usingAtomicsInCache) pstore1_cmd else M_XWR) amoalu.io.lhs := s2_data_word >> (i * xLen) amoalu.io.rhs := pstore1_data >> (i * xLen) amoalu } pstore1_storegen_data := (if (!usingDataScratchpad) amoalus.map(_.io.out).asUInt else { val mask = FillInterleaved(8, Mux(s2_correct, 0.U, pstore1_mask)) amoalus.map(_.io.out_unmasked).asUInt & mask \| s2_data_word_corrected & ~mask }) } else if (!usingAtomics) { assert(!(s1_valid_masked && s1_read && s1_write), "unsupported D$ operation") } if (coreParams.useVector) { edge.manager.managers.foreach { m => // Statically ensure that no-allocate accesses are permitted. // We could consider turning some of these into dynamic PMA checks. require(!m.supportsAcquireB \|\| m.supportsGet, "With a vector unit, cacheable memory must support Get") require(!m.supportsAcquireT \|\| m.supportsPutPartial, "With a vector unit, cacheable memory must support PutPartial") } } // flushes if (!usingDataScratchpad) when (RegNext(reset.asBool)) { resetting := true.B } val flushCounterNext = flushCounter +& 1.U val flushDone = (flushCounterNext >> log2Ceil(nSets)) === nWays.U val flushCounterWrap = flushCounterNext(log2Ceil(nSets)-1, 0) ccover(s2_valid_masked && s2_cmd_flush_all && s2_meta_error, "TAG_ECC_ERROR_DURING_FENCE_I", "D$ ECC error in tag array during cache flush") ccover(s2_valid_masked && s2_cmd_flush_all && s2_data_error, "DATA_ECC_ERROR_DURING_FENCE_I", "D$ ECC error in data array during cache flush") s1_flush_valid := metaArb.io.in(5).fire && !s1_flush_valid && !s2_flush_valid_pre_tag_ecc && release_state === s_ready && !release_ack_wait metaArb.io.in(5).valid := flushing && !flushed metaArb.io.in(5).bits.write := false.B metaArb.io.in(5).bits.idx := flushCounter(idxBits-1, 0) metaArb.io.in(5).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, metaArb.io.in(5).bits.idx << blockOffBits) metaArb.io.in(5).bits.way_en := metaArb.io.in(4).bits.way_en metaArb.io.in(5).bits.data := metaArb.io.in(4).bits.data // Only flush D$ on FENCE.I if some cached executable regions are untracked. if (supports_flush) { when (s2_valid_masked && s2_cmd_flush_all) { when (!flushed && !io.cpu.s2_kill && !release_ack_wait && !uncachedInFlight.asUInt.orR) { flushing := true.B flushing_req := s2_req } } when (tl_out_a.fire && !s2_uncached) { flushed := false.B } when (flushing) { s1_victim_way := flushCounter >> log2Up(nSets) when (s2_flush_valid) { flushCounter := flushCounterNext when (flushDone) { flushed := true.B if (!isPow2(nWays)) flushCounter := flushCounterWrap } } when (flushed && release_state === s_ready && !release_ack_wait) { flushing := false.B } } } metaArb.io.in(0).valid := resetting metaArb.io.in(0).bits := metaArb.io.in(5).bits metaArb.io.in(0).bits.write := true.B metaArb.io.in(0).bits.way_en := ~0.U(nWays.W) metaArb.io.in(0).bits.data := tECC.encode(L1Metadata(0.U, ClientMetadata.onReset).asUInt) when (resetting) { flushCounter := flushCounterNext when (flushDone) { resetting := false.B if (!isPow2(nWays)) flushCounter := flushCounterWrap } } // gate the clock clock_en_reg := !cacheParams.clockGate.B \|\| io.ptw.customCSRs.disableDCacheClockGate \|\| io.cpu.keep_clock_enabled \|\| metaArb.io.out.valid \|\| // subsumes resetting \|\| flushing s1_probe \|\| s2_probe \|\| s1_valid \|\| s2_valid \|\| io.tlb_port.req.valid \|\| s1_tlb_req_valid \|\| s2_tlb_req_valid \|\| pstore1_held \|\| pstore2_valid \|\| release_state =/= s_ready \|\| release_ack_wait \|\| !release_queue_empty \|\| !tlb.io.req.ready \|\| cached_grant_wait \|\| uncachedInFlight.asUInt.orR \|\| lrscCount > 0.U \|\| blockProbeAfterGrantCount > 0.U // performance events io.cpu.perf.acquire := edge.done(tl_out_a) io.cpu.perf.release := edge.done(tl_out_c) io.cpu.perf.grant := tl_out.d.valid && d_last io.cpu.perf.tlbMiss := io.ptw.req.fire io.cpu.perf.storeBufferEmptyAfterLoad := !( (s1_valid && s1_write) \|\| ((s2_valid && s2_write && !s2_waw_hazard) \|\| pstore1_held) \|\| pstore2_valid) io.cpu.perf.storeBufferEmptyAfterStore := !( (s1_valid && s1_write) \|\| (s2_valid && s2_write && pstore1_rmw) \|\| ((s2_valid && s2_write && !s2_waw_hazard \|\| pstore1_held) && pstore2_valid)) io.cpu.perf.canAcceptStoreThenLoad := !( ((s2_valid && s2_write && pstore1_rmw) && (s1_valid && s1_write && !s1_waw_hazard)) \|\| (pstore2_valid && pstore1_valid_likely && (s1_valid && s1_write))) io.cpu.perf.canAcceptStoreThenRMW := io.cpu.perf.canAcceptStoreThenLoad && !pstore2_valid io.cpu.perf.canAcceptLoadThenLoad := !((s1_valid && s1_write && needsRead(s1_req)) && ((s2_valid && s2_write && !s2_waw_hazard \|\| pstore1_held) \|\| pstore2_valid)) io.cpu.perf.blocked := { // stop reporting blocked just before unblocking to avoid overly conservative stalling val beatsBeforeEnd = outer.crossing match { case SynchronousCrossing(_) => 2 case RationalCrossing(_) => 1 // assumes 1 < ratio <= 2; need more bookkeeping for optimal handling of >2 case _: AsynchronousCrossing => 1 // likewise case _: CreditedCrossing => 1 // likewise } val near_end_of_refill = if (cacheBlockBytes / beatBytes <= beatsBeforeEnd) tl_out.d.valid else { val refill_count = RegInit(0.U((cacheBlockBytes / beatBytes).log2.W)) when (tl_out.d.fire && grantIsRefill) { refill_count := refill_count + 1.U } refill_count >= (cacheBlockBytes / beatBytes - beatsBeforeEnd).U } cached_grant_wait && !near_end_of_refill } // report errors val (data_error, data_error_uncorrectable, data_error_addr) = if (usingDataScratchpad) (s2_valid_data_error, s2_data_error_uncorrectable, s2_req.addr) else { (RegNext(tl_out_c.fire && inWriteback && s2_data_error), RegNext(s2_data_error_uncorrectable), probe_bits.address) // This is stable for a cycle after tl_out_c.fire, so don't need a register } { val error_addr = Mux(metaArb.io.in(1).valid, Cat(s2_first_meta_corrected.tag, metaArb.io.in(1).bits.addr(tagLSB-1, idxLSB)), data_error_addr >> idxLSB) << idxLSB io.errors.uncorrectable.foreach { u => u.valid := metaArb.io.in(1).valid && s2_meta_error_uncorrectable \|\| data_error && data_error_uncorrectable u.bits := error_addr } io.errors.correctable.foreach { c => c.valid := metaArb.io.in(1).valid \|\| data_error c.bits := error_addr io.errors.uncorrectable.foreach { u => when (u.valid) { c.valid := false.B } } } io.errors.bus.valid := tl_out.d.fire && (tl_out.d.bits.denied \|\| tl_out.d.bits.corrupt) io.errors.bus.bits := Mux(grantIsCached, s2_req.addr >> idxLSB << idxLSB, 0.U) ccoverNotScratchpad(io.errors.bus.valid && grantIsCached, "D_ERROR_CACHED", "D$ D-channel error, cached") ccover(io.errors.bus.valid && !grantIsCached, "D_ERROR_UNCACHED", "D$ D-channel error, uncached") } if (usingDataScratchpad) { val data_error_cover = Seq( property.CoverBoolean(!data_error, Seq("no_data_error")), property.CoverBoolean(data_error && !data_error_uncorrectable, Seq("data_correctable_error")), property.CoverBoolean(data_error && data_error_uncorrectable, Seq("data_uncorrectable_error"))) val request_source = Seq( property.CoverBoolean(s2_isSlavePortAccess, Seq("from_TL")), property.CoverBoolean(!s2_isSlavePortAccess, Seq("from_CPU"))) property.cover(new property.CrossProperty( Seq(data_error_cover, request_source), Seq(), "MemorySystem;;Scratchpad Memory Bit Flip Cross Covers")) } else { val data_error_type = Seq( property.CoverBoolean(!s2_valid_data_error, Seq("no_data_error")), property.CoverBoolean(s2_valid_data_error && !s2_data_error_uncorrectable, Seq("data_correctable_error")), property.CoverBoolean(s2_valid_data_error && s2_data_error_uncorrectable, Seq("data_uncorrectable_error"))) val data_error_dirty = Seq( property.CoverBoolean(!s2_victim_dirty, Seq("data_clean")), property.CoverBoolean(s2_victim_dirty, Seq("data_dirty"))) val request_source = if (supports_flush) { Seq( property.CoverBoolean(!flushing, Seq("access")), property.CoverBoolean(flushing, Seq("during_flush"))) } else { Seq(property.CoverBoolean(true.B, Seq("never_flush"))) } val tag_error_cover = Seq( property.CoverBoolean( !s2_meta_error, Seq("no_tag_error")), property.CoverBoolean( s2_meta_error && !s2_meta_error_uncorrectable, Seq("tag_correctable_error")), property.CoverBoolean( s2_meta_error && s2_meta_error_uncorrectable, Seq("tag_uncorrectable_error"))) property.cover(new property.CrossProperty( Seq(data_error_type, data_error_dirty, request_source, tag_error_cover), Seq(), "MemorySystem;;Cache Memory Bit Flip Cross Covers")) } } // leaving gated-clock domain val dcacheImpl = withClock (gated_clock) { new DCacheModuleImpl } def encodeData(x: UInt, poison: Bool) = x.grouped(eccBits).map(dECC.encode(_, if (dECC.canDetect) poison else false.B)).asUInt def dummyEncodeData(x: UInt) = x.grouped(eccBits).map(dECC.swizzle(_)).asUInt def decodeData(x: UInt) = x.grouped(dECC.width(eccBits)).map(dECC.decode(_)) def eccMask(byteMask: UInt) = byteMask.grouped(eccBytes).map(_.orR).asUInt def eccByteMask(byteMask: UInt) = FillInterleaved(eccBytes, eccMask(byteMask)) def likelyNeedsRead(req: HellaCacheReq) = { val res = !req.cmd.isOneOf(M_XWR, M_PFW) \|\| req.size < log2Ceil(eccBytes).U assert(!needsRead(req) \|\| res) res } def needsRead(req: HellaCacheReq) = isRead(req.cmd) \|\| (isWrite(req.cmd) && (req.cmd === M_PWR \|\| req.size < log2Ceil(eccBytes).U)) def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"DCACHE_$label", "MemorySystem;;" + desc) def ccoverNotScratchpad(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = if (!usingDataScratchpad) ccover(cond, label, desc) require(!usingVM \|\| tagLSB <= pgIdxBits, s"D$$ set size must not exceed ${1<<(pgIdxBits-10)} KiB; got ${(nSets * cacheBlockBytes)>>10} KiB") def tagLSB: Int = untagBits def probeIdx(b: TLBundleB): UInt = b.address(idxMSB, idxLSB) def addressToProbe(vaddr: UInt, paddr: UInt): TLBundleB = { val res = Wire(new TLBundleB(edge.bundle)) res :#= DontCare res.address := paddr res.source := (mmioOffset - 1).U res } def acquire(vaddr: UInt, paddr: UInt, param: UInt): TLBundleA = { if (!edge.manager.anySupportAcquireB) WireDefault(0.U.asTypeOf(new TLBundleA(edge.bundle))) else edge.AcquireBlock(0.U, paddr >> lgCacheBlockBytes << lgCacheBlockBytes, lgCacheBlockBytes.U, param)._2 } } File DescribedSRAM.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3.{Data, SyncReadMem, Vec} import chisel3.util.log2Ceil object DescribedSRAM { def apply[T <: Data]( name: String, desc: String, size: BigInt, // depth data: T ): SyncReadMem[T] = { val mem = SyncReadMem(size, data) mem.suggestName(name) val granWidth = data match { case v: Vec[_] => v.head.getWidth case d => d.getWidth } val uid = 0 Annotated.srams( component = mem, name = name, address_width = log2Ceil(size), data_width = data.getWidth, depth = size, description = desc, write_mask_granularity = granWidth ) mem } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File AMOALU.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) { val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W)) size := typ val dat_padded = dat.pad(maxSize8) def misaligned: Bool = (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR def mask = { var res = 1.U for (i <- 0 until log2Up(maxSize)) { val upper = Mux(addr(i), res, 0.U) \| Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U) val lower = Mux(addr(i), 0.U, res) res = Cat(upper, lower) } res } protected def genData(i: Int): UInt = if (i >= log2Up(maxSize)) dat_padded else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1)) def data = genData(0) def wordData = genData(2) } class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { private val size = new StoreGen(typ, addr, dat, maxSize).size private def genData(logMinSize: Int): UInt = { var res = dat for (i <- log2Up(maxSize)-1 to logMinSize by -1) { val pos = 8 << i val shifted = Mux(addr(i), res(2pos-1,pos), res(pos-1,0)) val doZero = (i == 0).B && zero val zeroed = Mux(doZero, 0.U, shifted) res = Cat(Mux(size === i.U \|\| doZero, Fill(8maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed) } res } def wordData = genData(2) def data = genData(0) } class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module { val minXLen = 32 val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _) val io = IO(new Bundle { val mask = Input(UInt((operandBits / 8).W)) val cmd = Input(UInt(M_SZ.W)) val lhs = Input(UInt(operandBits.W)) val rhs = Input(UInt(operandBits.W)) val out = Output(UInt(operandBits.W)) val out_unmasked = Output(UInt(operandBits.W)) }) val max = io.cmd === M_XA_MAX \|\| io.cmd === M_XA_MAXU val min = io.cmd === M_XA_MIN \|\| io.cmd === M_XA_MINU val add = io.cmd === M_XA_ADD val logic_and = io.cmd === M_XA_OR \|\| io.cmd === M_XA_AND val logic_xor = io.cmd === M_XA_XOR \|\| io.cmd === M_XA_OR val adder_out = { // partition the carry chain to support sub-xLen addition val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_\|_) (io.lhs & mask) + (io.rhs & mask) } val less = { // break up the comparator so the lower parts will be CSE'd def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = { if (n == minXLen) x(n-1, 0) < y(n-1, 0) else x(n-1, n/2) < y(n-1, n/2) \|\| x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2) } def isLess(x: UInt, y: UInt, n: Int): Bool = { val signed = { val mask = M_XA_MIN ^ M_XA_MINU (io.cmd & mask) === (M_XA_MIN & mask) } Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1))) } PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w)))) } val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs) val logic = Mux(logic_and, io.lhs & io.rhs, 0.U) \| Mux(logic_xor, io.lhs ^ io.rhs, 0.U) val out = Mux(add, adder_out, Mux(logic_and \|\| logic_xor, logic, minmax)) val wmask = FillInterleaved(8, io.mask) io.out := wmask & out \| ~wmask & io.lhs io.out_unmasked := out }	module DCache_1( // @[DCache.scala:101:7] input clock, // @[DCache.scala:101:7] input reset, // @[DCache.scala:101:7] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] output io_cpu_req_ready, // @[HellaCache.scala:243:14] input io_cpu_req_valid, // @[HellaCache.scala:243:14] input [39:0] io_cpu_req_bits_addr, // @[HellaCache.scala:243:14] input [6:0] io_cpu_req_bits_tag, // @[HellaCache.scala:243:14] input [4:0] io_cpu_req_bits_cmd, // @[HellaCache.scala:243:14] input [1:0] io_cpu_req_bits_size, // @[HellaCache.scala:243:14] input io_cpu_req_bits_signed, // @[HellaCache.scala:243:14] input [1:0] io_cpu_req_bits_dprv, // @[HellaCache.scala:243:14] input io_cpu_req_bits_dv, // @[HellaCache.scala:243:14] input io_cpu_req_bits_phys, // @[HellaCache.scala:243:14] input io_cpu_req_bits_no_resp, // @[HellaCache.scala:243:14] input io_cpu_s1_kill, // @[HellaCache.scala:243:14] input [63:0] io_cpu_s1_data_data, // @[HellaCache.scala:243:14] input [7:0] io_cpu_s1_data_mask, // @[HellaCache.scala:243:14] output io_cpu_s2_nack, // @[HellaCache.scala:243:14] output io_cpu_s2_nack_cause_raw, // @[HellaCache.scala:243:14] output io_cpu_s2_uncached, // @[HellaCache.scala:243:14] output [31:0] io_cpu_s2_paddr, // @[HellaCache.scala:243:14] output io_cpu_resp_valid, // @[HellaCache.scala:243:14] output [39:0] io_cpu_resp_bits_addr, // @[HellaCache.scala:243:14] output [6:0] io_cpu_resp_bits_tag, // @[HellaCache.scala:243:14] output [4:0] io_cpu_resp_bits_cmd, // @[HellaCache.scala:243:14] output [1:0] io_cpu_resp_bits_size, // @[HellaCache.scala:243:14] output io_cpu_resp_bits_signed, // @[HellaCache.scala:243:14] output [1:0] io_cpu_resp_bits_dprv, // @[HellaCache.scala:243:14] output io_cpu_resp_bits_dv, // @[HellaCache.scala:243:14] output [63:0] io_cpu_resp_bits_data, // @[HellaCache.scala:243:14] output [7:0] io_cpu_resp_bits_mask, // @[HellaCache.scala:243:14] output io_cpu_resp_bits_replay, // @[HellaCache.scala:243:14] output io_cpu_resp_bits_has_data, // @[HellaCache.scala:243:14] output [63:0] io_cpu_resp_bits_data_word_bypass, // @[HellaCache.scala:243:14] output [63:0] io_cpu_resp_bits_data_raw, // @[HellaCache.scala:243:14] output [63:0] io_cpu_resp_bits_store_data, // @[HellaCache.scala:243:14] output io_cpu_replay_next, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_ma_ld, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_ma_st, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_pf_ld, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_pf_st, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_ae_ld, // @[HellaCache.scala:243:14] output io_cpu_s2_xcpt_ae_st, // @[HellaCache.scala:243:14] output [39:0] io_cpu_s2_gpa, // @[HellaCache.scala:243:14] output io_cpu_ordered, // @[HellaCache.scala:243:14] output io_cpu_store_pending, // @[HellaCache.scala:243:14] output io_cpu_perf_acquire, // @[HellaCache.scala:243:14] output io_cpu_perf_release, // @[HellaCache.scala:243:14] output io_cpu_perf_grant, // @[HellaCache.scala:243:14] output io_cpu_perf_tlbMiss, // @[HellaCache.scala:243:14] output io_cpu_perf_blocked, // @[HellaCache.scala:243:14] output io_cpu_perf_canAcceptStoreThenLoad, // @[HellaCache.scala:243:14] output io_cpu_perf_canAcceptStoreThenRMW, // @[HellaCache.scala:243:14] output io_cpu_perf_canAcceptLoadThenLoad, // @[HellaCache.scala:243:14] output io_cpu_perf_storeBufferEmptyAfterLoad, // @[HellaCache.scala:243:14] output io_cpu_perf_storeBufferEmptyAfterStore, // @[HellaCache.scala:243:14] input io_cpu_keep_clock_enabled, // @[HellaCache.scala:243:14] input io_ptw_req_ready, // @[HellaCache.scala:243:14] output io_ptw_req_valid, // @[HellaCache.scala:243:14] output [26:0] io_ptw_req_bits_bits_addr, // @[HellaCache.scala:243:14] output io_ptw_req_bits_bits_need_gpa, // @[HellaCache.scala:243:14] input io_ptw_resp_valid, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_ae_ptw, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_ae_final, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pf, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_gf, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_hr, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_hw, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_hx, // @[HellaCache.scala:243:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[HellaCache.scala:243:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[HellaCache.scala:243:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_d, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_a, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_g, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_u, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_x, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_w, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_r, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_pte_v, // @[HellaCache.scala:243:14] input [1:0] io_ptw_resp_bits_level, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_homogeneous, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_gpa_valid, // @[HellaCache.scala:243:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[HellaCache.scala:243:14] input io_ptw_resp_bits_gpa_is_pte, // @[HellaCache.scala:243:14] input [3:0] io_ptw_ptbr_mode, // @[HellaCache.scala:243:14] input [43:0] io_ptw_ptbr_ppn, // @[HellaCache.scala:243:14] input io_ptw_status_debug, // @[HellaCache.scala:243:14] input io_ptw_status_cease, // @[HellaCache.scala:243:14] input io_ptw_status_wfi, // @[HellaCache.scala:243:14] input [31:0] io_ptw_status_isa, // @[HellaCache.scala:243:14] input [1:0] io_ptw_status_dprv, // @[HellaCache.scala:243:14] input io_ptw_status_dv, // @[HellaCache.scala:243:14] input [1:0] io_ptw_status_prv, // @[HellaCache.scala:243:14] input io_ptw_status_v, // @[HellaCache.scala:243:14] input io_ptw_status_sd, // @[HellaCache.scala:243:14] input io_ptw_status_mpv, // @[HellaCache.scala:243:14] input io_ptw_status_gva, // @[HellaCache.scala:243:14] input io_ptw_status_tsr, // @[HellaCache.scala:243:14] input io_ptw_status_tw, // @[HellaCache.scala:243:14] input io_ptw_status_tvm, // @[HellaCache.scala:243:14] input io_ptw_status_mxr, // @[HellaCache.scala:243:14] input io_ptw_status_sum, // @[HellaCache.scala:243:14] input io_ptw_status_mprv, // @[HellaCache.scala:243:14] input [1:0] io_ptw_status_fs, // @[HellaCache.scala:243:14] input [1:0] io_ptw_status_mpp, // @[HellaCache.scala:243:14] input io_ptw_status_spp, // @[HellaCache.scala:243:14] input io_ptw_status_mpie, // @[HellaCache.scala:243:14] input io_ptw_status_spie, // @[HellaCache.scala:243:14] input io_ptw_status_mie, // @[HellaCache.scala:243:14] input io_ptw_status_sie, // @[HellaCache.scala:243:14] input io_ptw_hstatus_spvp, // @[HellaCache.scala:243:14] input io_ptw_hstatus_spv, // @[HellaCache.scala:243:14] input io_ptw_hstatus_gva, // @[HellaCache.scala:243:14] input io_ptw_gstatus_debug, // @[HellaCache.scala:243:14] input io_ptw_gstatus_cease, // @[HellaCache.scala:243:14] input io_ptw_gstatus_wfi, // @[HellaCache.scala:243:14] input [31:0] io_ptw_gstatus_isa, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_dprv, // @[HellaCache.scala:243:14] input io_ptw_gstatus_dv, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_prv, // @[HellaCache.scala:243:14] input io_ptw_gstatus_v, // @[HellaCache.scala:243:14] input io_ptw_gstatus_sd, // @[HellaCache.scala:243:14] input [22:0] io_ptw_gstatus_zero2, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mpv, // @[HellaCache.scala:243:14] input io_ptw_gstatus_gva, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mbe, // @[HellaCache.scala:243:14] input io_ptw_gstatus_sbe, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_sxl, // @[HellaCache.scala:243:14] input [7:0] io_ptw_gstatus_zero1, // @[HellaCache.scala:243:14] input io_ptw_gstatus_tsr, // @[HellaCache.scala:243:14] input io_ptw_gstatus_tw, // @[HellaCache.scala:243:14] input io_ptw_gstatus_tvm, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mxr, // @[HellaCache.scala:243:14] input io_ptw_gstatus_sum, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mprv, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_fs, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_mpp, // @[HellaCache.scala:243:14] input [1:0] io_ptw_gstatus_vs, // @[HellaCache.scala:243:14] input io_ptw_gstatus_spp, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mpie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_ube, // @[HellaCache.scala:243:14] input io_ptw_gstatus_spie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_upie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_mie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_hie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_sie, // @[HellaCache.scala:243:14] input io_ptw_gstatus_uie, // @[HellaCache.scala:243:14] input io_ptw_pmp_0_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_0_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_0_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_0_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_0_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_0_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_1_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_1_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_1_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_1_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_1_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_1_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_2_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_2_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_2_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_2_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_2_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_2_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_3_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_3_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_3_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_3_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_3_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_3_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_4_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_4_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_4_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_4_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_4_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_4_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_5_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_5_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_5_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_5_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_5_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_5_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_6_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_6_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_6_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_6_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_6_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_6_mask, // @[HellaCache.scala:243:14] input io_ptw_pmp_7_cfg_l, // @[HellaCache.scala:243:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[HellaCache.scala:243:14] input io_ptw_pmp_7_cfg_x, // @[HellaCache.scala:243:14] input io_ptw_pmp_7_cfg_w, // @[HellaCache.scala:243:14] input io_ptw_pmp_7_cfg_r, // @[HellaCache.scala:243:14] input [29:0] io_ptw_pmp_7_addr, // @[HellaCache.scala:243:14] input [31:0] io_ptw_pmp_7_mask, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_0_ren, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_0_wen, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_1_ren, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_1_wen, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_2_ren, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_2_wen, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_3_ren, // @[HellaCache.scala:243:14] input io_ptw_customCSRs_csrs_3_wen, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[HellaCache.scala:243:14] input [63:0] io_ptw_customCSRs_csrs_3_value // @[HellaCache.scala:243:14] ); wire [19:0] s2_meta_corrected_7_tag; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_7_coh_state; // @[DCache.scala:361:99] wire [63:0] s1_all_data_ways_7; // @[DCache.scala:325:33] wire [63:0] s1_all_data_ways_6; // @[DCache.scala:325:33] wire [63:0] s1_all_data_ways_5; // @[DCache.scala:325:33] wire [63:0] s1_all_data_ways_4; // @[DCache.scala:325:33] wire [63:0] s1_all_data_ways_3; // @[DCache.scala:325:33] wire [63:0] s1_all_data_ways_2; // @[DCache.scala:325:33] wire [63:0] s1_all_data_ways_1; // @[DCache.scala:325:33] wire [63:0] s1_all_data_ways_0; // @[DCache.scala:325:33] wire rockettile_dcache_tag_array_MPORT_en; // @[DCache.scala:310:27] wire s0_req_phys; // @[DCache.scala:192:24] wire [39:0] s0_req_addr; // @[DCache.scala:192:24] wire tl_out_a_valid; // @[DCache.scala:159:22] wire [63:0] tl_out_a_bits_data; // @[DCache.scala:159:22] wire [7:0] tl_out_a_bits_mask; // @[DCache.scala:159:22] wire [31:0] tl_out_a_bits_address; // @[DCache.scala:159:22] wire tl_out_a_bits_source; // @[DCache.scala:159:22] wire [3:0] tl_out_a_bits_size; // @[DCache.scala:159:22] wire [2:0] tl_out_a_bits_param; // @[DCache.scala:159:22] wire [2:0] tl_out_a_bits_opcode; // @[DCache.scala:159:22] wire [5:0] metaArb_io_out_bits_idx; // @[DCache.scala:135:28] wire metaArb_io_in_0_valid; // @[DCache.scala:135:28] wire [4:0] pma_checker_io_req_bits_cmd; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_req_bits_size; // @[DCache.scala:120:32] wire [175:0] _rockettile_dcache_tag_array_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire _lfsr_prng_io_out_0; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_1; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_2; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_3; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_4; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_5; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_6; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_7; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_8; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_9; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_10; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_11; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_12; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_13; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_14; // @[PRNG.scala:91:22] wire _lfsr_prng_io_out_15; // @[PRNG.scala:91:22] wire [19:0] _pma_checker_entries_barrier_12_io_y_ppn; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_12_io_y_hr; // @[package.scala:267:25] wire [19:0] _pma_checker_entries_barrier_11_io_y_ppn; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_11_io_y_c; // @[package.scala:267:25] wire [19:0] _pma_checker_entries_barrier_10_io_y_ppn; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_10_io_y_c; // @[package.scala:267:25] wire [19:0] _pma_checker_entries_barrier_9_io_y_ppn; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_9_io_y_c; // @[package.scala:267:25] wire [19:0] _pma_checker_entries_barrier_8_io_y_ppn; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_8_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_7_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_6_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_5_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_4_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_3_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_2_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_1_io_y_c; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_u; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_ae_ptw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_ae_final; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_ae_stage2; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_pf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_gf; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_sw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_sx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_sr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_hw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_hx; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_hr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_pw; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_px; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_pr; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_ppp; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_pal; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_paa; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_eff; // @[package.scala:267:25] wire _pma_checker_entries_barrier_io_y_c; // @[package.scala:267:25] wire _pma_checker_pma_io_resp_r; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_w; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_pp; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_al; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_aa; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_x; // @[TLB.scala:422:19] wire _pma_checker_pma_io_resp_eff; // @[TLB.scala:422:19] wire [19:0] _pma_checker_mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25] wire _tlb_io_req_ready; // @[DCache.scala:119:19] wire _tlb_io_resp_miss; // @[DCache.scala:119:19] wire [31:0] _tlb_io_resp_paddr; // @[DCache.scala:119:19] wire [39:0] _tlb_io_resp_gpa; // @[DCache.scala:119:19] wire _tlb_io_resp_pf_ld; // @[DCache.scala:119:19] wire _tlb_io_resp_pf_st; // @[DCache.scala:119:19] wire _tlb_io_resp_pf_inst; // @[DCache.scala:119:19] wire _tlb_io_resp_ae_ld; // @[DCache.scala:119:19] wire _tlb_io_resp_ae_st; // @[DCache.scala:119:19] wire _tlb_io_resp_ae_inst; // @[DCache.scala:119:19] wire _tlb_io_resp_ma_ld; // @[DCache.scala:119:19] wire _tlb_io_resp_ma_st; // @[DCache.scala:119:19] wire _tlb_io_resp_cacheable; // @[DCache.scala:119:19] wire _tlb_io_resp_must_alloc; // @[DCache.scala:119:19] wire _tlb_io_resp_prefetchable; // @[DCache.scala:119:19] wire [1:0] _tlb_io_resp_size; // @[DCache.scala:119:19] wire [4:0] _tlb_io_resp_cmd; // @[DCache.scala:119:19] wire auto_out_a_ready_0 = auto_out_a_ready; // @[DCache.scala:101:7] wire auto_out_b_valid_0 = auto_out_b_valid; // @[DCache.scala:101:7] wire [2:0] auto_out_b_bits_opcode_0 = auto_out_b_bits_opcode; // @[DCache.scala:101:7] wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[DCache.scala:101:7] wire [3:0] auto_out_b_bits_size_0 = auto_out_b_bits_size; // @[DCache.scala:101:7] wire auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[DCache.scala:101:7] wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[DCache.scala:101:7] wire [7:0] auto_out_b_bits_mask_0 = auto_out_b_bits_mask; // @[DCache.scala:101:7] wire [63:0] auto_out_b_bits_data_0 = auto_out_b_bits_data; // @[DCache.scala:101:7] wire auto_out_b_bits_corrupt_0 = auto_out_b_bits_corrupt; // @[DCache.scala:101:7] wire auto_out_c_ready_0 = auto_out_c_ready; // @[DCache.scala:101:7] wire auto_out_d_valid_0 = auto_out_d_valid; // @[DCache.scala:101:7] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[DCache.scala:101:7] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[DCache.scala:101:7] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[DCache.scala:101:7] wire auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[DCache.scala:101:7] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[DCache.scala:101:7] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[DCache.scala:101:7] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[DCache.scala:101:7] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[DCache.scala:101:7] wire auto_out_e_ready_0 = auto_out_e_ready; // @[DCache.scala:101:7] wire io_cpu_req_valid_0 = io_cpu_req_valid; // @[DCache.scala:101:7] wire [39:0] io_cpu_req_bits_addr_0 = io_cpu_req_bits_addr; // @[DCache.scala:101:7] wire [6:0] io_cpu_req_bits_tag_0 = io_cpu_req_bits_tag; // @[DCache.scala:101:7] wire [4:0] io_cpu_req_bits_cmd_0 = io_cpu_req_bits_cmd; // @[DCache.scala:101:7] wire [1:0] io_cpu_req_bits_size_0 = io_cpu_req_bits_size; // @[DCache.scala:101:7] wire io_cpu_req_bits_signed_0 = io_cpu_req_bits_signed; // @[DCache.scala:101:7] wire [1:0] io_cpu_req_bits_dprv_0 = io_cpu_req_bits_dprv; // @[DCache.scala:101:7] wire io_cpu_req_bits_dv_0 = io_cpu_req_bits_dv; // @[DCache.scala:101:7] wire io_cpu_req_bits_phys_0 = io_cpu_req_bits_phys; // @[DCache.scala:101:7] wire io_cpu_req_bits_no_resp_0 = io_cpu_req_bits_no_resp; // @[DCache.scala:101:7] wire io_cpu_s1_kill_0 = io_cpu_s1_kill; // @[DCache.scala:101:7] wire [63:0] io_cpu_s1_data_data_0 = io_cpu_s1_data_data; // @[DCache.scala:101:7] wire [7:0] io_cpu_s1_data_mask_0 = io_cpu_s1_data_mask; // @[DCache.scala:101:7] wire io_cpu_keep_clock_enabled_0 = io_cpu_keep_clock_enabled; // @[DCache.scala:101:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[DCache.scala:101:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[DCache.scala:101:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[DCache.scala:101:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[DCache.scala:101:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[DCache.scala:101:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[DCache.scala:101:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[DCache.scala:101:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[DCache.scala:101:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[DCache.scala:101:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[DCache.scala:101:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[DCache.scala:101:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[DCache.scala:101:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[DCache.scala:101:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[DCache.scala:101:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[DCache.scala:101:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[DCache.scala:101:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[DCache.scala:101:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[DCache.scala:101:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[DCache.scala:101:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[DCache.scala:101:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[DCache.scala:101:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[DCache.scala:101:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[DCache.scala:101:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[DCache.scala:101:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[DCache.scala:101:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[DCache.scala:101:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[DCache.scala:101:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[DCache.scala:101:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[DCache.scala:101:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[DCache.scala:101:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[DCache.scala:101:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[DCache.scala:101:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[DCache.scala:101:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[DCache.scala:101:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[DCache.scala:101:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[DCache.scala:101:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[DCache.scala:101:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[DCache.scala:101:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[DCache.scala:101:7] wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[DCache.scala:101:7] wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[DCache.scala:101:7] wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[DCache.scala:101:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[DCache.scala:101:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[DCache.scala:101:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[DCache.scala:101:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[DCache.scala:101:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[DCache.scala:101:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[DCache.scala:101:7] wire io_ptw_gstatus_sd_0 = io_ptw_gstatus_sd; // @[DCache.scala:101:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[DCache.scala:101:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[DCache.scala:101:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[DCache.scala:101:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[DCache.scala:101:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[DCache.scala:101:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[DCache.scala:101:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[DCache.scala:101:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[DCache.scala:101:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[DCache.scala:101:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[DCache.scala:101:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[DCache.scala:101:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[DCache.scala:101:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[DCache.scala:101:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[DCache.scala:101:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[DCache.scala:101:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[DCache.scala:101:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[DCache.scala:101:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[DCache.scala:101:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[DCache.scala:101:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[DCache.scala:101:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[DCache.scala:101:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[DCache.scala:101:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[DCache.scala:101:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[DCache.scala:101:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[DCache.scala:101:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[DCache.scala:101:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[DCache.scala:101:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[DCache.scala:101:7] wire _dataArb_io_in_3_valid_T_55 = reset; // @[DCache.scala:1186:11] wire _pstore_drain_opportunistic_T_55 = reset; // @[DCache.scala:1186:11] wire auto_out_a_bits_corrupt = 1'h0; // @[DCache.scala:101:7] wire auto_out_c_bits_corrupt = 1'h0; // @[DCache.scala:101:7] wire io_cpu_req_bits_no_alloc = 1'h0; // @[DCache.scala:101:7] wire io_cpu_req_bits_no_xcpt = 1'h0; // @[DCache.scala:101:7] wire io_cpu_s2_kill = 1'h0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_gf_ld = 1'h0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_gf_st = 1'h0; // @[DCache.scala:101:7] wire io_cpu_s2_gpa_is_pte = 1'h0; // @[DCache.scala:101:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[DCache.scala:101:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[DCache.scala:101:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_mbe = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_sbe = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_ube = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_upie = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_hie = 1'h0; // @[DCache.scala:101:7] wire io_ptw_status_uie = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_vtw = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_hu = 1'h0; // @[DCache.scala:101:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[DCache.scala:101:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[DCache.scala:101:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_req_valid = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_req_bits_passthrough = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_req_bits_v = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_gpa_is_pte = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_gf_ld = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_gf_st = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_gf_inst = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ma_inst = 1'h0; // @[DCache.scala:101:7] wire io_tlb_port_s2_kill = 1'h0; // @[DCache.scala:101:7] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire pma_checker_io_req_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_miss = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_gpa_is_pte = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_gf_ld = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_gf_st = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_gf_inst = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_resp_ma_inst = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_rs1 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_rs2 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_asid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_hv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_sfence_bits_hg = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_ready = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_bits_bits_need_gpa = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_bits_bits_vstage1 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_bits_bits_stage2 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_ae_ptw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_ae_final = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pf = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_gf = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_hr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_hw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_hx = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_d = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_a = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_g = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_u = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_pte_v = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_homogeneous = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_gpa_valid = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_resp_bits_gpa_is_pte = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_debug = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_cease = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_wfi = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_dv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_v = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sd = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mpv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_gva = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sd_rv32 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_tsr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_tw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_tvm = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mxr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sum = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mprv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_spp = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mpie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_ube = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_spie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_upie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_mie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_hie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_sie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_status_uie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_vtsr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_vtw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_vtvm = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_hu = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_spvp = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_spv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_gva = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_hstatus_vsbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_debug = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_cease = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_wfi = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_dv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_v = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sd = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mpv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_gva = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sbe = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sd_rv32 = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_tsr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_tw = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_tvm = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mxr = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sum = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mprv = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_spp = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mpie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_ube = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_spie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_upie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_mie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_hie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_sie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_gstatus_uie = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_0_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_0_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_0_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_0_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_1_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_1_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_1_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_1_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_2_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_2_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_2_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_2_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_3_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_3_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_3_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_3_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_4_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_4_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_4_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_4_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_5_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_5_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_5_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_5_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_6_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_6_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_6_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_6_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_7_cfg_l = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_7_cfg_x = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_7_cfg_w = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_pmp_7_cfg_r = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_0_set = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_1_set = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_2_ren = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_2_wen = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_2_set = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_3_ren = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_3_wen = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_ptw_customCSRs_csrs_3_set = 1'h0; // @[DCache.scala:120:32] wire pma_checker_io_kill = 1'h0; // @[DCache.scala:120:32] wire pma_checker_priv_v = 1'h0; // @[TLB.scala:369:34] wire pma_checker__stage1_en_T = 1'h0; // @[TLB.scala:374:41] wire pma_checker_stage1_en = 1'h0; // @[TLB.scala:374:29] wire pma_checker__vstage1_en_T = 1'h0; // @[TLB.scala:376:38] wire pma_checker__vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68] wire pma_checker_vstage1_en = 1'h0; // @[TLB.scala:376:48] wire pma_checker__stage2_en_T = 1'h0; // @[TLB.scala:378:38] wire pma_checker__stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68] wire pma_checker_stage2_en = 1'h0; // @[TLB.scala:378:48] wire pma_checker__vm_enabled_T = 1'h0; // @[TLB.scala:399:31] wire pma_checker__vm_enabled_T_1 = 1'h0; // @[TLB.scala:399:45] wire pma_checker__vm_enabled_T_2 = 1'h0; // @[TLB.scala:399:64] wire pma_checker_vm_enabled = 1'h0; // @[TLB.scala:399:61] wire pma_checker__vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52] wire pma_checker__vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37] wire pma_checker__vsatp_mode_mismatch_T_2 = 1'h0; // @[TLB.scala:403:81] wire pma_checker_vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78] wire pma_checker_do_refill = 1'h0; // @[TLB.scala:408:29] wire pma_checker__invalidate_refill_T = 1'h0; // @[package.scala:16:47] wire pma_checker__invalidate_refill_T_1 = 1'h0; // @[package.scala:16:47] wire pma_checker__invalidate_refill_T_2 = 1'h0; // @[package.scala:81:59] wire pma_checker_invalidate_refill = 1'h0; // @[TLB.scala:410:88] wire pma_checker__mpu_ppn_T = 1'h0; // @[TLB.scala:413:32] wire pma_checker_prot_r = 1'h0; // @[TLB.scala:429:55] wire pma_checker_prot_w = 1'h0; // @[TLB.scala:430:55] wire pma_checker_prot_x = 1'h0; // @[TLB.scala:434:55] wire pma_checker__sector_hits_T = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_1 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_2 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_0 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_8 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_9 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_10 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_1 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_16 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_17 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_18 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_2 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_24 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_25 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_26 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_3 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_32 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_33 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_34 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_4 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_40 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_41 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_42 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_5 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_48 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_49 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_50 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_6 = 1'h0; // @[TLB.scala:172:55] wire pma_checker__sector_hits_T_56 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_57 = 1'h0; // @[package.scala:81:59] wire pma_checker__sector_hits_T_58 = 1'h0; // @[package.scala:81:59] wire pma_checker_sector_hits_7 = 1'h0; // @[TLB.scala:172:55] wire pma_checker_superpage_hits_tagMatch = 1'h0; // @[TLB.scala:178:33] wire pma_checker__superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_4 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__superpage_hits_T_9 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_0 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_tagMatch_1 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__superpage_hits_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_18 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__superpage_hits_T_23 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_1 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_tagMatch_2 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__superpage_hits_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_32 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__superpage_hits_T_37 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_2 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_tagMatch_3 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__superpage_hits_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_46 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__superpage_hits_T_51 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_superpage_hits_3 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_5 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_0 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_11 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_1 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_17 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_2 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_23 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_3 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_29 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_4 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_35 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_5 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_41 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_6 = 1'h0; // @[TLB.scala:440:44] wire pma_checker__hitsVec_T_47 = 1'h0; // @[TLB.scala:188:18] wire pma_checker_hitsVec_7 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_hitsVec_tagMatch = 1'h0; // @[TLB.scala:178:33] wire pma_checker__hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore = 1'h0; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_52 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_57 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_62 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_hitsVec_8 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_hitsVec_tagMatch_1 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_67 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_72 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_77 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_hitsVec_9 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_hitsVec_tagMatch_2 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__hitsVec_ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_82 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_87 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_92 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_hitsVec_10 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_hitsVec_tagMatch_3 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__hitsVec_ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_97 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_102 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_107 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_hitsVec_11 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_hitsVec_tagMatch_4 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__hitsVec_ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_12 = 1'h0; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_112 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_117 = 1'h0; // @[TLB.scala:183:29] wire pma_checker__hitsVec_T_122 = 1'h0; // @[TLB.scala:183:29] wire pma_checker_hitsVec_12 = 1'h0; // @[TLB.scala:440:44] wire pma_checker_refill_v = 1'h0; // @[TLB.scala:448:33] wire pma_checker_newEntry_u = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_g = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_ae_ptw = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_ae_final = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_pf = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_gf = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_sw = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_sx = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_sr = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_hw = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_hx = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_hr = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_pw = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_px = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_pr = 1'h0; // @[TLB.scala:449:24] wire pma_checker_newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24] wire pma_checker__newEntry_g_T = 1'h0; // @[TLB.scala:453:25] wire pma_checker__newEntry_ae_stage2_T = 1'h0; // @[TLB.scala:456:53] wire pma_checker__newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84] wire pma_checker__newEntry_sr_T_1 = 1'h0; // @[PTW.scala:141:44] wire pma_checker__newEntry_sr_T_2 = 1'h0; // @[PTW.scala:141:38] wire pma_checker__newEntry_sr_T_3 = 1'h0; // @[PTW.scala:141:32] wire pma_checker__newEntry_sr_T_4 = 1'h0; // @[PTW.scala:141:52] wire pma_checker__newEntry_sr_T_5 = 1'h0; // @[PTW.scala:149:35] wire pma_checker__newEntry_sw_T_1 = 1'h0; // @[PTW.scala:141:44] wire pma_checker__newEntry_sw_T_2 = 1'h0; // @[PTW.scala:141:38] wire pma_checker__newEntry_sw_T_3 = 1'h0; // @[PTW.scala:141:32] wire pma_checker__newEntry_sw_T_4 = 1'h0; // @[PTW.scala:141:52] wire pma_checker__newEntry_sw_T_5 = 1'h0; // @[PTW.scala:151:35] wire pma_checker__newEntry_sw_T_6 = 1'h0; // @[PTW.scala:151:40] wire pma_checker__newEntry_sx_T_1 = 1'h0; // @[PTW.scala:141:44] wire pma_checker__newEntry_sx_T_2 = 1'h0; // @[PTW.scala:141:38] wire pma_checker__newEntry_sx_T_3 = 1'h0; // @[PTW.scala:141:32] wire pma_checker__newEntry_sx_T_4 = 1'h0; // @[PTW.scala:141:52] wire pma_checker__newEntry_sx_T_5 = 1'h0; // @[PTW.scala:153:35] wire pma_checker__waddr_T = 1'h0; // @[TLB.scala:477:45] wire pma_checker__superpage_entries_0_level_T = 1'h0; // @[package.scala:163:13] wire pma_checker__superpage_entries_1_level_T = 1'h0; // @[package.scala:163:13] wire pma_checker__superpage_entries_2_level_T = 1'h0; // @[package.scala:163:13] wire pma_checker__superpage_entries_3_level_T = 1'h0; // @[package.scala:163:13] wire pma_checker_sum = 1'h0; // @[TLB.scala:510:16] wire pma_checker__mxr_T = 1'h0; // @[TLB.scala:518:36] wire pma_checker_mxr = 1'h0; // @[TLB.scala:518:31] wire pma_checker__bad_va_T = 1'h0; // @[TLB.scala:568:21] wire pma_checker_bad_va = 1'h0; // @[TLB.scala:568:34] wire pma_checker_cmd_readx = 1'h0; // @[TLB.scala:575:37] wire pma_checker__gf_ld_array_T = 1'h0; // @[TLB.scala:600:32] wire pma_checker__gf_st_array_T = 1'h0; // @[TLB.scala:601:32] wire pma_checker__gpa_hits_hit_mask_T_1 = 1'h0; // @[TLB.scala:606:60] wire pma_checker_tlb_hit_if_not_gpa_miss = 1'h0; // @[TLB.scala:610:43] wire pma_checker_tlb_hit = 1'h0; // @[TLB.scala:611:40] wire pma_checker__tlb_miss_T_1 = 1'h0; // @[TLB.scala:613:29] wire pma_checker__tlb_miss_T_3 = 1'h0; // @[TLB.scala:613:53] wire pma_checker_tlb_miss = 1'h0; // @[TLB.scala:613:64] wire pma_checker__state_vec_0_set_left_older_T = 1'h0; // @[Replacement.scala:196:43] wire pma_checker__state_vec_0_set_left_older_T_1 = 1'h0; // @[Replacement.scala:196:43] wire pma_checker_state_vec_0_left_subtree_state_1 = 1'h0; // @[package.scala:163:13] wire pma_checker_state_vec_0_right_subtree_state_1 = 1'h0; // @[Replacement.scala:198:38] wire pma_checker__state_vec_0_T_1 = 1'h0; // @[package.scala:163:13] wire pma_checker__state_vec_0_T_2 = 1'h0; // @[Replacement.scala:218:17] wire pma_checker__state_vec_0_T_4 = 1'h0; // @[Replacement.scala:203:16] wire pma_checker__state_vec_0_T_5 = 1'h0; // @[Replacement.scala:207:62] wire pma_checker__state_vec_0_T_6 = 1'h0; // @[Replacement.scala:218:17] wire pma_checker__state_vec_0_set_left_older_T_2 = 1'h0; // @[Replacement.scala:196:43] wire pma_checker_state_vec_0_left_subtree_state_2 = 1'h0; // @[package.scala:163:13] wire pma_checker_state_vec_0_right_subtree_state_2 = 1'h0; // @[Replacement.scala:198:38] wire pma_checker__state_vec_0_T_12 = 1'h0; // @[package.scala:163:13] wire pma_checker__state_vec_0_T_13 = 1'h0; // @[Replacement.scala:218:17] wire pma_checker__state_vec_0_T_15 = 1'h0; // @[Replacement.scala:203:16] wire pma_checker__state_vec_0_T_16 = 1'h0; // @[Replacement.scala:207:62] wire pma_checker__state_vec_0_T_17 = 1'h0; // @[Replacement.scala:218:17] wire pma_checker__state_reg_set_left_older_T = 1'h0; // @[Replacement.scala:196:43] wire pma_checker_state_reg_left_subtree_state = 1'h0; // @[package.scala:163:13] wire pma_checker_state_reg_right_subtree_state = 1'h0; // @[Replacement.scala:198:38] wire pma_checker__state_reg_T = 1'h0; // @[package.scala:163:13] wire pma_checker__state_reg_T_1 = 1'h0; // @[Replacement.scala:218:17] wire pma_checker__state_reg_T_3 = 1'h0; // @[Replacement.scala:203:16] wire pma_checker__state_reg_T_4 = 1'h0; // @[Replacement.scala:207:62] wire pma_checker__state_reg_T_5 = 1'h0; // @[Replacement.scala:218:17] wire pma_checker__multipleHits_T_2 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_4 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_1 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_5 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_rightOne_1 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_7 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_leftOne_2 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_8 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_9 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_leftTwo = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_11 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_3 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_13 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_4 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_14 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne_2 = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_rightOne_3 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_16 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_1 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_rightOne_4 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_17 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_18 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_2 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_leftOne_5 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_19 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_20 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_leftTwo_1 = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_23 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_6 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_25 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_7 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_26 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne_5 = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_rightOne_6 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_28 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_3 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_leftOne_8 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_29 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_30 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_leftTwo_2 = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_33 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_9 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_34 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne_7 = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_leftOne_10 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_36 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_leftTwo_3 = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_38 = 1'h0; // @[Misc.scala:181:37] wire pma_checker_multipleHits_leftOne_11 = 1'h0; // @[Misc.scala:178:18] wire pma_checker__multipleHits_T_39 = 1'h0; // @[Misc.scala:182:39] wire pma_checker_multipleHits_rightOne_8 = 1'h0; // @[Misc.scala:178:18] wire pma_checker_multipleHits_rightOne_9 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_41 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_4 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_rightOne_10 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_42 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_43 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_5 = 1'h0; // @[Misc.scala:183:49] wire pma_checker_multipleHits_rightOne_11 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_44 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_45 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits_rightTwo_6 = 1'h0; // @[Misc.scala:183:49] wire pma_checker__multipleHits_T_46 = 1'h0; // @[Misc.scala:183:16] wire pma_checker__multipleHits_T_47 = 1'h0; // @[Misc.scala:183:37] wire pma_checker__multipleHits_T_48 = 1'h0; // @[Misc.scala:183:61] wire pma_checker_multipleHits = 1'h0; // @[Misc.scala:183:49] wire pma_checker__io_resp_pf_ld_T = 1'h0; // @[TLB.scala:633:28] wire pma_checker__io_resp_pf_st_T = 1'h0; // @[TLB.scala:634:28] wire pma_checker__io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29] wire pma_checker__io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66] wire pma_checker__io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42] wire pma_checker__io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29] wire pma_checker__io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73] wire pma_checker__io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49] wire pma_checker__io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56] wire pma_checker__io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30] wire pma_checker__io_resp_miss_T = 1'h0; // @[TLB.scala:651:29] wire pma_checker__io_resp_miss_T_1 = 1'h0; // @[TLB.scala:651:52] wire pma_checker__io_resp_miss_T_2 = 1'h0; // @[TLB.scala:651:64] wire pma_checker__io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36] wire pma_checker__io_ptw_req_valid_T = 1'h0; // @[TLB.scala:662:29] wire pma_checker_r_superpage_repl_addr_left_subtree_older = 1'h0; // @[Replacement.scala:243:38] wire pma_checker_r_superpage_repl_addr_left_subtree_state = 1'h0; // @[package.scala:163:13] wire pma_checker_r_superpage_repl_addr_right_subtree_state = 1'h0; // @[Replacement.scala:245:38] wire pma_checker__r_superpage_repl_addr_T = 1'h0; // @[Replacement.scala:262:12] wire pma_checker__r_superpage_repl_addr_T_1 = 1'h0; // @[Replacement.scala:262:12] wire pma_checker__r_superpage_repl_addr_T_2 = 1'h0; // @[Replacement.scala:250:16] wire pma_checker__r_superpage_repl_addr_T_4 = 1'h0; // @[TLB.scala:757:16] wire pma_checker_r_sectored_repl_addr_left_subtree_older = 1'h0; // @[Replacement.scala:243:38] wire pma_checker_r_sectored_repl_addr_left_subtree_older_1 = 1'h0; // @[Replacement.scala:243:38] wire pma_checker_r_sectored_repl_addr_left_subtree_state_1 = 1'h0; // @[package.scala:163:13] wire pma_checker_r_sectored_repl_addr_right_subtree_state_1 = 1'h0; // @[Replacement.scala:245:38] wire pma_checker__r_sectored_repl_addr_T = 1'h0; // @[Replacement.scala:262:12] wire pma_checker__r_sectored_repl_addr_T_1 = 1'h0; // @[Replacement.scala:262:12] wire pma_checker__r_sectored_repl_addr_T_2 = 1'h0; // @[Replacement.scala:250:16] wire pma_checker_r_sectored_repl_addr_left_subtree_older_2 = 1'h0; // @[Replacement.scala:243:38] wire pma_checker_r_sectored_repl_addr_left_subtree_state_2 = 1'h0; // @[package.scala:163:13] wire pma_checker_r_sectored_repl_addr_right_subtree_state_2 = 1'h0; // @[Replacement.scala:245:38] wire pma_checker__r_sectored_repl_addr_T_4 = 1'h0; // @[Replacement.scala:262:12] wire pma_checker__r_sectored_repl_addr_T_5 = 1'h0; // @[Replacement.scala:262:12] wire pma_checker__r_sectored_repl_addr_T_6 = 1'h0; // @[Replacement.scala:250:16] wire pma_checker__r_sectored_repl_addr_valids_T = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_1 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_2 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_3 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_4 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_5 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_6 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_7 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_8 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_9 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_10 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_11 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_12 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_13 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_14 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_15 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_16 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_17 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_18 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_19 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_20 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_21 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_22 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_valids_T_23 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_repl_addr_T_10 = 1'h0; // @[TLB.scala:757:16] wire pma_checker__r_sectored_hit_valid_T = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_valid_T_1 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_valid_T_2 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_valid_T_3 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_valid_T_4 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_valid_T_5 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_valid_T_6 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_sectored_hit_bits_T_1 = 1'h0; // @[OneHot.scala:32:14] wire pma_checker__r_sectored_hit_bits_T_3 = 1'h0; // @[OneHot.scala:32:14] wire pma_checker__r_sectored_hit_bits_T_5 = 1'h0; // @[CircuitMath.scala:28:8] wire pma_checker__r_superpage_hit_valid_T = 1'h0; // @[package.scala:81:59] wire pma_checker__r_superpage_hit_valid_T_1 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_superpage_hit_valid_T_2 = 1'h0; // @[package.scala:81:59] wire pma_checker__r_superpage_hit_bits_T_1 = 1'h0; // @[OneHot.scala:32:14] wire pma_checker__r_superpage_hit_bits_T_3 = 1'h0; // @[CircuitMath.scala:28:8] wire pma_checker_hv = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_1 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_1 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_2 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_2 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_3 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_3 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_4 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_4 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_5 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_5 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_6 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_6 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_7 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_7 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_hv_8 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_8 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_tagMatch = 1'h0; // @[TLB.scala:178:33] wire pma_checker__ignore_T = 1'h0; // @[TLB.scala:182:28] wire pma_checker_ignore = 1'h0; // @[TLB.scala:182:34] wire pma_checker_hv_9 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_9 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_tagMatch_1 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__ignore_T_3 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_ignore_3 = 1'h0; // @[TLB.scala:182:34] wire pma_checker_hv_10 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_10 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_tagMatch_2 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__ignore_T_6 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_ignore_6 = 1'h0; // @[TLB.scala:182:34] wire pma_checker_hv_11 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_11 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_tagMatch_3 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__ignore_T_9 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_ignore_9 = 1'h0; // @[TLB.scala:182:34] wire pma_checker_hv_12 = 1'h0; // @[TLB.scala:721:36] wire pma_checker_hg_12 = 1'h0; // @[TLB.scala:722:36] wire pma_checker_tagMatch_4 = 1'h0; // @[TLB.scala:178:33] wire pma_checker__ignore_T_12 = 1'h0; // @[TLB.scala:182:28] wire pma_checker_ignore_12 = 1'h0; // @[TLB.scala:182:34] wire metaArb_io_in_1_valid = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_5_valid = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_5_bits_write = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_6_bits_write = 1'h0; // @[DCache.scala:135:28] wire metaArb_io_in_7_bits_write = 1'h0; // @[DCache.scala:135:28] wire dataArb_io_in_2_bits_write = 1'h0; // @[DCache.scala:152:28] wire dataArb_io_in_3_bits_write = 1'h0; // @[DCache.scala:152:28] wire tl_out_a_bits_corrupt = 1'h0; // @[DCache.scala:159:22] wire nodeOut_a_deq_bits_corrupt = 1'h0; // @[Decoupled.scala:356:21] wire _s1_tlb_req_valid_T = 1'h0; // @[Decoupled.scala:51:35] wire s0_req_no_alloc = 1'h0; // @[DCache.scala:192:24] wire s0_req_no_xcpt = 1'h0; // @[DCache.scala:192:24] wire s1_waw_hazard = 1'h0; // @[DCache.scala:216:27] wire _uncachedInFlight_WIRE_0 = 1'h0; // @[DCache.scala:236:41] wire _dataArb_io_in_3_valid_res_T_4 = 1'h0; // @[DCache.scala:1185:58] wire _dataArb_io_in_3_valid_T_49 = 1'h0; // @[DCache.scala:1191:57] wire _s1_did_read_T_49 = 1'h0; // @[DCache.scala:1191:57] wire _tlb_io_kill_T = 1'h0; // @[DCache.scala:272:53] wire _tlb_io_kill_T_1 = 1'h0; // @[DCache.scala:272:33] wire _s2_pma_T_gpa_is_pte = 1'h0; // @[DCache.scala:349:18] wire _s2_pma_T_gf_ld = 1'h0; // @[DCache.scala:349:18] wire _s2_pma_T_gf_st = 1'h0; // @[DCache.scala:349:18] wire _s2_pma_T_gf_inst = 1'h0; // @[DCache.scala:349:18] wire _s2_pma_T_ma_inst = 1'h0; // @[DCache.scala:349:18] wire s2_meta_error_uncorrectable = 1'h0; // @[DCache.scala:360:66] wire s2_meta_error = 1'h0; // @[DCache.scala:362:83] wire s2_store_merge = 1'h0; // @[DCache.scala:388:28] wire _r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _s2_data_error_T = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_1 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_2 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_3 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_4 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_5 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_6 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_7 = 1'h0; // @[ECC.scala:15:27] wire _s2_data_error_T_8 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_9 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_10 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_11 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_12 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_T_13 = 1'h0; // @[package.scala:81:59] wire s2_data_error = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_1 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_2 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_3 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_4 = 1'h0; // @[package.scala:81:59] wire _s2_data_error_uncorrectable_T_5 = 1'h0; // @[package.scala:81:59] wire s2_data_error_uncorrectable = 1'h0; // @[package.scala:81:59] wire s2_valid_data_error = 1'h0; // @[DCache.scala:421:63] wire s2_cannot_victimize = 1'h0; // @[DCache.scala:428:45] wire _r_T_73 = 1'h0; // @[Misc.scala:38:9] wire _r_T_77 = 1'h0; // @[Misc.scala:38:9] wire _r_T_81 = 1'h0; // @[Misc.scala:38:9] wire _r_T_119 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_121 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_137 = 1'h0; // @[Misc.scala:38:9] wire _r_T_141 = 1'h0; // @[Misc.scala:38:9] wire _r_T_145 = 1'h0; // @[Misc.scala:38:9] wire _s2_dont_nack_misc_T_2 = 1'h0; // @[DCache.scala:442:23] wire _s2_dont_nack_misc_T_3 = 1'h0; // @[DCache.scala:442:43] wire _s2_dont_nack_misc_T_5 = 1'h0; // @[DCache.scala:442:54] wire _s2_dont_nack_misc_T_6 = 1'h0; // @[DCache.scala:443:23] wire _s2_dont_nack_misc_T_8 = 1'h0; // @[DCache.scala:443:44] wire _s2_dont_nack_misc_T_9 = 1'h0; // @[DCache.scala:442:67] wire _s2_first_meta_corrected_T = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_1 = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_2 = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_3 = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_4 = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_5 = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_6 = 1'h0; // @[Mux.scala:52:83] wire _s2_first_meta_corrected_T_7 = 1'h0; // @[Mux.scala:52:83] wire _metaArb_io_in_1_valid_T_2 = 1'h0; // @[DCache.scala:450:43] wire _metaArb_io_in_1_bits_way_en_T = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_1 = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_2 = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_3 = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_4 = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_5 = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_6 = 1'h0; // @[OneHot.scala:85:71] wire _metaArb_io_in_1_bits_way_en_T_7 = 1'h0; // @[OneHot.scala:85:71] wire _s2_correct_T_1 = 1'h0; // @[DCache.scala:487:34] wire _s2_correct_T_4 = 1'h0; // @[DCache.scala:487:55] wire s2_correct = 1'h0; // @[DCache.scala:487:97] wire _s2_valid_correct_T = 1'h0; // @[DCache.scala:489:60] wire s2_valid_correct = 1'h0; // @[DCache.scala:489:74] wire _pstore1_rmw_T_49 = 1'h0; // @[DCache.scala:1191:57] wire pstore1_merge_likely = 1'h0; // @[DCache.scala:499:68] wire pstore1_merge = 1'h0; // @[DCache.scala:500:38] wire _pstore_drain_opportunistic_res_T_4 = 1'h0; // @[DCache.scala:1185:58] wire _pstore_drain_opportunistic_T_49 = 1'h0; // @[DCache.scala:1191:57] wire _pstore_drain_opportunistic_T_60 = 1'h0; // @[DCache.scala:502:106] wire pstore_drain_s2_kill = 1'h0; // @[DCache.scala:515:25] wire _pstore2_storegen_data_T_2 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_6 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_10 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_14 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_18 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_22 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_26 = 1'h0; // @[DCache.scala:528:95] wire _pstore2_storegen_data_T_30 = 1'h0; // @[DCache.scala:528:95] wire dataArb_io_in_0_valid_s2_kill = 1'h0; // @[DCache.scala:515:25] wire _dataArb_io_in_0_bits_wordMask_T_1 = 1'h0; // @[DCache.scala:555:20] wire _io_cpu_s2_nack_cause_raw_T_2 = 1'h0; // @[DCache.scala:574:57] wire get_corrupt = 1'h0; // @[Edges.scala:460:17] wire _put_legal_T_62 = 1'h0; // @[Parameters.scala:684:29] wire _put_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire put_corrupt = 1'h0; // @[Edges.scala:480:17] wire _putpartial_legal_T_62 = 1'h0; // @[Parameters.scala:684:29] wire _putpartial_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire putpartial_corrupt = 1'h0; // @[Edges.scala:500:17] wire _atomics_WIRE_source = 1'h0; // @[DCache.scala:587:51] wire _atomics_WIRE_corrupt = 1'h0; // @[DCache.scala:587:51] wire _atomics_WIRE_1_source = 1'h0; // @[DCache.scala:587:38] wire _atomics_WIRE_1_corrupt = 1'h0; // @[DCache.scala:587:38] wire _atomics_legal_T_46 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_52 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_corrupt = 1'h0; // @[Edges.scala:534:17] wire _atomics_legal_T_100 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_106 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_1_corrupt = 1'h0; // @[Edges.scala:534:17] wire _atomics_legal_T_154 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_160 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_2_corrupt = 1'h0; // @[Edges.scala:534:17] wire _atomics_legal_T_208 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_214 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_3_corrupt = 1'h0; // @[Edges.scala:534:17] wire _atomics_legal_T_262 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_268 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_4_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_legal_T_316 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_322 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_5_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_legal_T_370 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_376 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_6_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_legal_T_424 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_430 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_7_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_legal_T_478 = 1'h0; // @[Parameters.scala:684:29] wire _atomics_legal_T_484 = 1'h0; // @[Parameters.scala:684:54] wire atomics_a_8_corrupt = 1'h0; // @[Edges.scala:517:17] wire _atomics_T_1_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_3_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_5_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_7_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_9_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_11_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_13_corrupt = 1'h0; // @[DCache.scala:587:81] wire _atomics_T_15_corrupt = 1'h0; // @[DCache.scala:587:81] wire atomics_corrupt = 1'h0; // @[DCache.scala:587:81] wire _tl_out_a_valid_T_8 = 1'h0; // @[DCache.scala:607:44] wire _tl_out_a_valid_T_9 = 1'h0; // @[DCache.scala:607:65] wire _tl_out_a_bits_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _tl_out_a_bits_legal_T_18 = 1'h0; // @[Parameters.scala:684:54] wire _tl_out_a_bits_legal_T_33 = 1'h0; // @[Parameters.scala:686:26] wire tl_out_a_bits_a_source = 1'h0; // @[Edges.scala:346:17] wire tl_out_a_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17] wire tl_out_a_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _tl_out_a_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _tl_out_a_bits_T_6_corrupt = 1'h0; // @[DCache.scala:611:8] wire _tl_out_a_bits_T_7_corrupt = 1'h0; // @[DCache.scala:610:8] wire _tl_out_a_bits_T_8_corrupt = 1'h0; // @[DCache.scala:609:8] wire _tl_out_a_bits_T_9_corrupt = 1'h0; // @[DCache.scala:608:23] wire nackResponseMessage_corrupt = 1'h0; // @[Edges.scala:416:17] wire cleanReleaseMessage_corrupt = 1'h0; // @[Edges.scala:416:17] wire dirtyReleaseMessage_corrupt = 1'h0; // @[Edges.scala:433:17] wire _nodeOut_c_valid_T = 1'h0; // @[DCache.scala:810:48] wire _nodeOut_c_valid_T_2 = 1'h0; // @[DCache.scala:810:74] wire _discard_line_T_2 = 1'h0; // @[DCache.scala:818:102] wire _release_state_T_2 = 1'h0; // @[DCache.scala:820:28] wire _release_state_T_4 = 1'h0; // @[DCache.scala:820:54] wire _release_state_T_5 = 1'h0; // @[DCache.scala:820:75] wire _release_state_T_7 = 1'h0; // @[DCache.scala:820:98] wire _release_state_T_12 = 1'h0; // @[DCache.scala:820:127] wire probe_bits_res_source = 1'h0; // @[DCache.scala:1202:19] wire probe_bits_res_corrupt = 1'h0; // @[DCache.scala:1202:19] wire _nodeOut_c_bits_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _nodeOut_c_bits_legal_T_1 = 1'h0; // @[Parameters.scala:137:31] wire _nodeOut_c_bits_legal_T_10 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_15 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_18 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_c_bits_legal_T_25 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_30 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_31 = 1'h0; // @[Parameters.scala:685:42] wire _nodeOut_c_bits_legal_T_32 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_c_bits_legal_T_33 = 1'h0; // @[Parameters.scala:686:26] wire nodeOut_c_bits_legal = 1'h0; // @[Parameters.scala:686:26] wire nodeOut_c_bits_c_source = 1'h0; // @[Edges.scala:380:17] wire nodeOut_c_bits_c_corrupt = 1'h0; // @[Edges.scala:380:17] wire _nodeOut_c_bits_legal_T_34 = 1'h0; // @[Parameters.scala:684:29] wire _nodeOut_c_bits_legal_T_35 = 1'h0; // @[Parameters.scala:137:31] wire _nodeOut_c_bits_legal_T_44 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_49 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_52 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_c_bits_legal_T_59 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_64 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_65 = 1'h0; // @[Parameters.scala:685:42] wire _nodeOut_c_bits_legal_T_66 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_c_bits_legal_T_67 = 1'h0; // @[Parameters.scala:686:26] wire nodeOut_c_bits_legal_1 = 1'h0; // @[Parameters.scala:686:26] wire nodeOut_c_bits_c_1_source = 1'h0; // @[Edges.scala:396:17] wire nodeOut_c_bits_c_1_corrupt = 1'h0; // @[Edges.scala:396:17] wire _nodeOut_c_bits_corrupt_T = 1'h0; // @[DCache.scala:887:42] wire _io_cpu_s2_xcpt_WIRE_miss = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_gpa_is_pte = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_pf_ld = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_pf_st = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_pf_inst = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_gf_ld = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_gf_st = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_gf_inst = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ae_ld = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ae_st = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ae_inst = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ma_ld = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ma_st = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_ma_inst = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_cacheable = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_must_alloc = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_WIRE_prefetchable = 1'h0; // @[DCache.scala:933:74] wire _io_cpu_s2_xcpt_T_gpa_is_pte = 1'h0; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_gf_ld = 1'h0; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_gf_st = 1'h0; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_gf_inst = 1'h0; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_ma_inst = 1'h0; // @[DCache.scala:933:24] wire _s2_data_word_possibly_uncached_T = 1'h0; // @[DCache.scala:972:73] wire io_cpu_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_cpu_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_cpu_resp_bits_data_word_bypass_doZero = 1'h0; // @[AMOALU.scala:43:31] wire _s1_flush_valid_T = 1'h0; // @[Decoupled.scala:51:35] wire _s1_flush_valid_T_2 = 1'h0; // @[DCache.scala:1014:43] wire _s1_flush_valid_T_4 = 1'h0; // @[DCache.scala:1014:62] wire _s1_flush_valid_T_6 = 1'h0; // @[DCache.scala:1014:93] wire _s1_flush_valid_T_8 = 1'h0; // @[DCache.scala:1014:122] wire _metaArb_io_in_5_valid_T = 1'h0; // @[DCache.scala:1015:41] wire _metaArb_io_in_5_valid_T_1 = 1'h0; // @[DCache.scala:1015:38] wire _clock_en_reg_T_17 = 1'h0; // @[DCache.scala:1070:25] wire _io_cpu_perf_canAcceptLoadThenLoad_T_50 = 1'h0; // @[DCache.scala:1191:57] wire io_cpu_clock_enabled = 1'h1; // @[DCache.scala:101:7] wire io_ptw_req_bits_valid = 1'h1; // @[DCache.scala:101:7] wire io_tlb_port_req_ready = 1'h1; // @[DCache.scala:101:7] wire pma_checker_io_req_ready = 1'h1; // @[DCache.scala:120:32] wire pma_checker_io_req_bits_passthrough = 1'h1; // @[DCache.scala:120:32] wire pma_checker_io_ptw_req_bits_valid = 1'h1; // @[DCache.scala:120:32] wire pma_checker__mpu_ppn_ignore_T = 1'h1; // @[TLB.scala:197:28] wire pma_checker_mpu_ppn_ignore = 1'h1; // @[TLB.scala:197:34] wire pma_checker__mpu_ppn_ignore_T_1 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_mpu_ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__mpu_priv_T = 1'h1; // @[TLB.scala:415:52] wire pma_checker__mpu_priv_T_1 = 1'h1; // @[TLB.scala:415:38] wire pma_checker__homogeneous_T_59 = 1'h1; // @[TLBPermissions.scala:87:22] wire pma_checker__deny_access_to_debug_T = 1'h1; // @[TLB.scala:428:39] wire pma_checker__sector_hits_T_6 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_14 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_22 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_30 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_38 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_46 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_54 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__sector_hits_T_62 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__superpage_hits_tagMatch_T = 1'h1; // @[TLB.scala:178:43] wire pma_checker__superpage_hits_ignore_T_1 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__superpage_hits_ignore_T_2 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__superpage_hits_tagMatch_T_1 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__superpage_hits_ignore_T_4 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__superpage_hits_ignore_T_5 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_27 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__superpage_hits_tagMatch_T_2 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__superpage_hits_ignore_T_7 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__superpage_hits_ignore_T_8 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_41 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__superpage_hits_tagMatch_T_3 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__superpage_hits_ignore_T_10 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__superpage_hits_ignore_T_11 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_superpage_hits_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__superpage_hits_T_55 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hitsVec_T_3 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_9 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_15 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_21 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_27 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_33 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_39 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_T_45 = 1'h1; // @[TLB.scala:174:105] wire pma_checker__hitsVec_tagMatch_T = 1'h1; // @[TLB.scala:178:43] wire pma_checker__hitsVec_ignore_T_1 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__hitsVec_ignore_T_2 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_61 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hitsVec_tagMatch_T_1 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__hitsVec_ignore_T_4 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__hitsVec_ignore_T_5 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_76 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hitsVec_tagMatch_T_2 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__hitsVec_ignore_T_7 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__hitsVec_ignore_T_8 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_91 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hitsVec_tagMatch_T_3 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__hitsVec_ignore_T_10 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__hitsVec_ignore_T_11 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_106 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hitsVec_tagMatch_T_4 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__hitsVec_ignore_T_13 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_13 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_116 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hitsVec_ignore_T_14 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_hitsVec_ignore_14 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__hitsVec_T_121 = 1'h1; // @[TLB.scala:183:40] wire pma_checker__hits_T = 1'h1; // @[TLB.scala:442:18] wire pma_checker__newEntry_sr_T = 1'h1; // @[PTW.scala:141:47] wire pma_checker__newEntry_sw_T = 1'h1; // @[PTW.scala:141:47] wire pma_checker__newEntry_sx_T = 1'h1; // @[PTW.scala:141:47] wire pma_checker__ppn_T = 1'h1; // @[TLB.scala:502:30] wire pma_checker__ppn_ignore_T = 1'h1; // @[TLB.scala:197:28] wire pma_checker__ppn_ignore_T_1 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__ppn_ignore_T_2 = 1'h1; // @[TLB.scala:197:28] wire pma_checker__ppn_ignore_T_3 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_ppn_ignore_3 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__ppn_ignore_T_4 = 1'h1; // @[TLB.scala:197:28] wire pma_checker__ppn_ignore_T_5 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_ppn_ignore_5 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__ppn_ignore_T_6 = 1'h1; // @[TLB.scala:197:28] wire pma_checker__ppn_ignore_T_7 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_ppn_ignore_7 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__ppn_ignore_T_8 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_ppn_ignore_8 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__ppn_ignore_T_9 = 1'h1; // @[TLB.scala:197:28] wire pma_checker_ppn_ignore_9 = 1'h1; // @[TLB.scala:197:34] wire pma_checker__stage1_bypass_T_1 = 1'h1; // @[TLB.scala:517:83] wire pma_checker__stage2_bypass_T = 1'h1; // @[TLB.scala:523:42] wire pma_checker__bad_va_T_1 = 1'h1; // @[TLB.scala:560:26] wire pma_checker__gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107] wire pma_checker__tlb_miss_T = 1'h1; // @[TLB.scala:613:32] wire pma_checker__tlb_miss_T_2 = 1'h1; // @[TLB.scala:613:56] wire pma_checker__tlb_miss_T_4 = 1'h1; // @[TLB.scala:613:67] wire pma_checker_state_vec_0_set_left_older = 1'h1; // @[Replacement.scala:196:33] wire pma_checker_state_vec_0_set_left_older_1 = 1'h1; // @[Replacement.scala:196:33] wire pma_checker__state_vec_0_T_3 = 1'h1; // @[Replacement.scala:218:7] wire pma_checker__state_vec_0_T_7 = 1'h1; // @[Replacement.scala:218:7] wire pma_checker__state_vec_0_T_8 = 1'h1; // @[Replacement.scala:206:16] wire pma_checker_state_vec_0_set_left_older_2 = 1'h1; // @[Replacement.scala:196:33] wire pma_checker__state_vec_0_T_14 = 1'h1; // @[Replacement.scala:218:7] wire pma_checker__state_vec_0_T_18 = 1'h1; // @[Replacement.scala:218:7] wire pma_checker__state_vec_0_T_19 = 1'h1; // @[Replacement.scala:206:16] wire pma_checker_state_reg_set_left_older = 1'h1; // @[Replacement.scala:196:33] wire pma_checker__state_reg_T_2 = 1'h1; // @[Replacement.scala:218:7] wire pma_checker__state_reg_T_6 = 1'h1; // @[Replacement.scala:218:7] wire pma_checker__state_reg_T_7 = 1'h1; // @[Replacement.scala:206:16] wire pma_checker__io_req_ready_T = 1'h1; // @[TLB.scala:631:25] wire pma_checker__io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20] wire pma_checker__io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28] wire pma_checker__r_superpage_repl_addr_T_6 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_superpage_repl_addr_T_7 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_superpage_repl_addr_T_8 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_superpage_repl_addr_T_9 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_12 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_13 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_14 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_15 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_16 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_17 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_18 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__r_sectored_repl_addr_T_19 = 1'h1; // @[OneHot.scala:48:45] wire pma_checker__tagMatch_T = 1'h1; // @[TLB.scala:178:43] wire pma_checker__ignore_T_1 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__ignore_T_2 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_ignore_2 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__tagMatch_T_1 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__ignore_T_4 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__ignore_T_5 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_ignore_5 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__tagMatch_T_2 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__ignore_T_7 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__ignore_T_8 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_ignore_8 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__tagMatch_T_3 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__ignore_T_10 = 1'h1; // @[TLB.scala:182:28] wire pma_checker__ignore_T_11 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_ignore_11 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__tagMatch_T_4 = 1'h1; // @[TLB.scala:178:43] wire pma_checker__ignore_T_13 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_ignore_13 = 1'h1; // @[TLB.scala:182:34] wire pma_checker__ignore_T_14 = 1'h1; // @[TLB.scala:182:28] wire pma_checker_ignore_14 = 1'h1; // @[TLB.scala:182:34] wire metaArb_io_in_0_ready = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_0_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_1_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_2_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_3_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_in_4_bits_write = 1'h1; // @[DCache.scala:135:28] wire metaArb_io_out_ready = 1'h1; // @[DCache.scala:135:28] wire metaArb__io_in_0_ready_T = 1'h1; // @[Arbiter.scala:153:19] wire dataArb_io_in_0_ready = 1'h1; // @[DCache.scala:152:28] wire dataArb_io_in_1_bits_wordMask = 1'h1; // @[DCache.scala:152:28] wire dataArb_io_in_2_bits_wordMask = 1'h1; // @[DCache.scala:152:28] wire dataArb_io_in_3_bits_wordMask = 1'h1; // @[DCache.scala:152:28] wire dataArb_io_out_ready = 1'h1; // @[DCache.scala:152:28] wire dataArb__io_in_0_ready_T = 1'h1; // @[Arbiter.scala:153:19] wire _s2_valid_not_killed_T = 1'h1; // @[DCache.scala:338:48] wire _s2_flush_valid_T = 1'h1; // @[DCache.scala:363:54] wire _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T = 1'h1; // @[DCache.scala:397:74] wire _s2_valid_hit_pre_data_ecc_and_waw_T_1 = 1'h1; // @[DCache.scala:418:108] wire _s2_valid_hit_pre_data_ecc_T = 1'h1; // @[DCache.scala:420:73] wire _s2_valid_hit_pre_data_ecc_T_1 = 1'h1; // @[DCache.scala:420:88] wire _s2_valid_hit_T = 1'h1; // @[DCache.scala:422:51] wire _s2_valid_miss_T_1 = 1'h1; // @[DCache.scala:423:58] wire _s2_victimize_T = 1'h1; // @[DCache.scala:429:43] wire _r_T_117 = 1'h1; // @[Metadata.scala:140:24] wire _s2_dont_nack_misc_T = 1'h1; // @[DCache.scala:441:46] wire _s2_dont_nack_misc_T_4 = 1'h1; // @[DCache.scala:442:57] wire _metaArb_io_in_2_bits_write_T = 1'h1; // @[DCache.scala:463:34] wire _s2_valid_correct_T_1 = 1'h1; // @[DCache.scala:489:77] wire _pstore1_merge_T_3 = 1'h1; // @[DCache.scala:491:51] wire _pstore_drain_opportunistic_T_61 = 1'h1; // @[DCache.scala:502:95] wire _pstore1_valid_T_3 = 1'h1; // @[DCache.scala:491:51] wire _pstore_drain_T = 1'h1; // @[DCache.scala:516:5] wire _pstore_drain_T_3 = 1'h1; // @[DCache.scala:506:87] wire _pstore1_held_T_3 = 1'h1; // @[DCache.scala:491:51] wire _pstore1_held_T_5 = 1'h1; // @[DCache.scala:521:38] wire _dataArb_io_in_0_valid_T = 1'h1; // @[DCache.scala:516:5] wire _dataArb_io_in_0_valid_T_3 = 1'h1; // @[DCache.scala:506:87] wire _dataArb_io_in_0_bits_wordMask_T = 1'h1; // @[DCache.scala:555:20] wire _io_cpu_s2_nack_cause_raw_T = 1'h1; // @[DCache.scala:574:59] wire _io_cpu_s2_nack_cause_raw_T_1 = 1'h1; // @[DCache.scala:574:74] wire _get_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _get_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _get_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _get_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _get_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _put_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _put_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _put_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _put_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _putpartial_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _putpartial_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _putpartial_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _putpartial_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _putpartial_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _putpartial_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _putpartial_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _putpartial_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_54 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_55 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_56 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_57 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_108 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_109 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_110 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_111 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_162 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_163 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_164 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_165 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_216 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_217 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_218 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_219 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_270 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_271 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_272 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_273 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_324 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_325 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_326 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_327 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_378 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_379 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_380 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_381 = 1'h1; // @[Parameters.scala:684:29] wire _atomics_legal_T_432 = 1'h1; // @[Parameters.scala:92:28] wire _atomics_legal_T_433 = 1'h1; // @[Parameters.scala:92:38] wire _atomics_legal_T_434 = 1'h1; // @[Parameters.scala:92:33] wire _atomics_legal_T_435 = 1'h1; // @[Parameters.scala:684:29] wire _tl_out_a_valid_T = 1'h1; // @[DCache.scala:603:21] wire _tl_out_a_bits_legal_T_19 = 1'h1; // @[Parameters.scala:91:44] wire _tl_out_a_bits_legal_T_20 = 1'h1; // @[Parameters.scala:684:29] wire tl_out_a_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire tl_out_a_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire tl_out_a_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire tl_out_a_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire tl_out_a_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire _dataArb_io_in_1_bits_wordMask_T = 1'h1; // @[DCache.scala:731:39] wire _nodeOut_c_bits_legal_T_5 = 1'h1; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_16 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_c_bits_legal_T_17 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_c_bits_legal_T_19 = 1'h1; // @[Parameters.scala:91:44] wire _nodeOut_c_bits_legal_T_20 = 1'h1; // @[Parameters.scala:684:29] wire _nodeOut_c_bits_legal_T_39 = 1'h1; // @[Parameters.scala:137:59] wire _nodeOut_c_bits_legal_T_50 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_c_bits_legal_T_51 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_c_bits_legal_T_53 = 1'h1; // @[Parameters.scala:91:44] wire _nodeOut_c_bits_legal_T_54 = 1'h1; // @[Parameters.scala:684:29] wire _dataArb_io_in_2_bits_wordMask_T = 1'h1; // @[DCache.scala:904:37] wire _io_cpu_ordered_T = 1'h1; // @[DCache.scala:929:35] wire _s1_xcpt_valid_T = 1'h1; // @[DCache.scala:932:43] wire _io_cpu_resp_valid_T_1 = 1'h1; // @[DCache.scala:949:73] wire _io_cpu_replay_next_T_2 = 1'h1; // @[DCache.scala:950:65] wire _clock_en_reg_T = 1'h1; // @[DCache.scala:1060:19] wire _clock_en_reg_T_2 = 1'h1; // @[DCache.scala:1060:44] wire _clock_en_reg_T_3 = 1'h1; // @[DCache.scala:1061:46] wire _clock_en_reg_T_4 = 1'h1; // @[DCache.scala:1062:31] wire _clock_en_reg_T_5 = 1'h1; // @[DCache.scala:1063:26] wire _clock_en_reg_T_6 = 1'h1; // @[DCache.scala:1064:14] wire _clock_en_reg_T_7 = 1'h1; // @[DCache.scala:1064:26] wire _clock_en_reg_T_8 = 1'h1; // @[DCache.scala:1065:14] wire _clock_en_reg_T_9 = 1'h1; // @[DCache.scala:1065:26] wire _clock_en_reg_T_10 = 1'h1; // @[DCache.scala:1066:27] wire _clock_en_reg_T_11 = 1'h1; // @[DCache.scala:1067:22] wire _clock_en_reg_T_12 = 1'h1; // @[DCache.scala:1067:42] wire _clock_en_reg_T_13 = 1'h1; // @[DCache.scala:1068:18] wire _clock_en_reg_T_15 = 1'h1; // @[DCache.scala:1068:35] wire _clock_en_reg_T_16 = 1'h1; // @[DCache.scala:1069:31] wire _clock_en_reg_T_18 = 1'h1; // @[DCache.scala:1070:22] wire _clock_en_reg_T_20 = 1'h1; // @[DCache.scala:1070:46] wire _clock_en_reg_T_21 = 1'h1; // @[DCache.scala:1071:23] wire _clock_en_reg_T_23 = 1'h1; // @[DCache.scala:1072:23] wire _clock_en_reg_T_25 = 1'h1; // @[DCache.scala:1072:54] wire _clock_en_reg_T_27 = 1'h1; // @[DCache.scala:1073:21] wire _io_cpu_perf_storeBufferEmptyAfterLoad_T_2 = 1'h1; // @[DCache.scala:1082:31] wire _io_cpu_perf_storeBufferEmptyAfterStore_T_5 = 1'h1; // @[DCache.scala:1087:31] wire _io_cpu_perf_canAcceptStoreThenLoad_T_3 = 1'h1; // @[DCache.scala:1089:72] wire _io_cpu_perf_canAcceptLoadThenLoad_T_56 = 1'h1; // @[DCache.scala:1092:115] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[DCache.scala:101:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[DCache.scala:101:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[DCache.scala:101:7] wire [15:0] pma_checker_io_ptw_ptbr_asid = 16'h0; // @[DCache.scala:120:32] wire [15:0] pma_checker_io_ptw_hgatp_asid = 16'h0; // @[DCache.scala:120:32] wire [15:0] pma_checker_io_ptw_vsatp_asid = 16'h0; // @[DCache.scala:120:32] wire [15:0] pma_checker_satp_asid = 16'h0; // @[TLB.scala:373:17] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[DCache.scala:101:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[DCache.scala:101:7] wire [3:0] pma_checker_io_ptw_ptbr_mode = 4'h0; // @[DCache.scala:120:32] wire [3:0] pma_checker_io_ptw_hgatp_mode = 4'h0; // @[DCache.scala:120:32] wire [3:0] pma_checker_io_ptw_vsatp_mode = 4'h0; // @[DCache.scala:120:32] wire [3:0] pma_checker_satp_mode = 4'h0; // @[TLB.scala:373:17] wire [3:0] pma_checker_real_hits_hi_hi = 4'h0; // @[package.scala:45:27] wire [3:0] pma_checker_lo = 4'h0; // @[OneHot.scala:21:45] wire [3:0] pma_checker_hi = 4'h0; // @[OneHot.scala:21:45] wire [3:0] pma_checker_hi_1 = 4'h0; // @[OneHot.scala:30:18] wire [3:0] pma_checker_lo_1 = 4'h0; // @[OneHot.scala:31:18] wire [3:0] pma_checker__multipleHits_T_31 = 4'h0; // @[Misc.scala:182:39] wire [3:0] pma_checker_r_superpage_repl_addr_valids = 4'h0; // @[package.scala:45:27] wire [3:0] pma_checker_r_sectored_repl_addr_valids_lo = 4'h0; // @[package.scala:45:27] wire [3:0] pma_checker_r_sectored_repl_addr_valids_hi = 4'h0; // @[package.scala:45:27] wire [3:0] pma_checker_r_sectored_hit_bits_lo = 4'h0; // @[OneHot.scala:21:45] wire [3:0] pma_checker_r_sectored_hit_bits_hi = 4'h0; // @[OneHot.scala:21:45] wire [3:0] pma_checker_r_sectored_hit_bits_hi_1 = 4'h0; // @[OneHot.scala:30:18] wire [3:0] pma_checker_r_sectored_hit_bits_lo_1 = 4'h0; // @[OneHot.scala:31:18] wire [3:0] pma_checker__r_sectored_hit_bits_T_2 = 4'h0; // @[OneHot.scala:32:28] wire [3:0] pma_checker__r_superpage_hit_bits_T = 4'h0; // @[OneHot.scala:21:45] wire [3:0] s2_meta_correctable_errors_lo = 4'h0; // @[package.scala:45:27] wire [3:0] s2_meta_correctable_errors_hi = 4'h0; // @[package.scala:45:27] wire [3:0] s2_meta_uncorrectable_errors_lo = 4'h0; // @[package.scala:45:27] wire [3:0] s2_meta_uncorrectable_errors_hi = 4'h0; // @[package.scala:45:27] wire [3:0] _r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r_T_63 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _r_T_127 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _a_mask_T = 4'h0; // @[DCache.scala:582:90] wire [3:0] _atomics_WIRE_size = 4'h0; // @[DCache.scala:587:51] wire [3:0] _atomics_WIRE_1_size = 4'h0; // @[DCache.scala:587:38] wire [3:0] _metaArb_io_in_3_bits_data_T_5 = 4'h0; // @[Metadata.scala:87:10] wire [3:0] probe_bits_res_size = 4'h0; // @[DCache.scala:1202:19] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[DCache.scala:101:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[DCache.scala:101:7] wire [43:0] pma_checker_io_ptw_resp_bits_pte_ppn = 44'h0; // @[DCache.scala:120:32] wire [43:0] pma_checker_io_ptw_ptbr_ppn = 44'h0; // @[DCache.scala:120:32] wire [43:0] pma_checker_io_ptw_hgatp_ppn = 44'h0; // @[DCache.scala:120:32] wire [43:0] pma_checker_io_ptw_vsatp_ppn = 44'h0; // @[DCache.scala:120:32] wire [43:0] pma_checker_satp_ppn = 44'h0; // @[TLB.scala:373:17] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[DCache.scala:101:7] wire [22:0] pma_checker_io_ptw_status_zero2 = 23'h0; // @[DCache.scala:120:32] wire [22:0] pma_checker_io_ptw_gstatus_zero2 = 23'h0; // @[DCache.scala:120:32] wire [7:0] io_cpu_req_bits_mask = 8'h0; // @[DCache.scala:101:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[DCache.scala:101:7] wire [7:0] pma_checker_io_ptw_status_zero1 = 8'h0; // @[DCache.scala:120:32] wire [7:0] pma_checker_io_ptw_gstatus_zero1 = 8'h0; // @[DCache.scala:120:32] wire [7:0] pma_checker_r_sectored_repl_addr_valids = 8'h0; // @[package.scala:45:27] wire [7:0] pma_checker__r_sectored_hit_bits_T = 8'h0; // @[OneHot.scala:21:45] wire [7:0] metaArb_io_in_1_bits_way_en = 8'h0; // @[DCache.scala:135:28] wire [7:0] s0_req_mask = 8'h0; // @[DCache.scala:192:24] wire [7:0] s2_meta_correctable_errors = 8'h0; // @[package.scala:45:27] wire [7:0] s2_meta_uncorrectable_errors = 8'h0; // @[package.scala:45:27] wire [7:0] _s2_meta_error_T = 8'h0; // @[DCache.scala:362:53] wire [7:0] _metaArb_io_in_1_bits_way_en_T_8 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_9 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_10 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_11 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_12 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_13 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_14 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_15 = 8'h0; // @[Mux.scala:50:70] wire [7:0] _metaArb_io_in_1_bits_way_en_T_16 = 8'h0; // @[DCache.scala:452:69] wire [7:0] _metaArb_io_in_1_bits_way_en_T_17 = 8'h0; // @[DCache.scala:452:64] wire [7:0] _pstore2_storegen_mask_mergedMask_T = 8'h0; // @[DCache.scala:533:42] wire [7:0] _atomics_WIRE_mask = 8'h0; // @[DCache.scala:587:51] wire [7:0] _atomics_WIRE_1_mask = 8'h0; // @[DCache.scala:587:38] wire [7:0] probe_bits_res_mask = 8'h0; // @[DCache.scala:1202:19] wire [1:0] io_ptw_status_xs = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_tlb_port_req_bits_size = 2'h0; // @[DCache.scala:101:7] wire [1:0] io_tlb_port_req_bits_prv = 2'h0; // @[DCache.scala:101:7] wire [1:0] pma_checker_io_ptw_resp_bits_pte_reserved_for_software = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_resp_bits_level = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_dprv = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_prv = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_sxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_uxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_xs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_fs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_mpp = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_status_vs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_hstatus_vsxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_hstatus_zero3 = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_hstatus_zero2 = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_dprv = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_prv = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_sxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_uxl = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_xs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_fs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_mpp = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_gstatus_vs = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_0_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_0_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_1_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_1_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_2_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_2_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_3_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_3_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_4_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_4_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_5_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_5_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_6_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_6_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_7_cfg_res = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_ptw_pmp_7_cfg_a = 2'h0; // @[DCache.scala:120:32] wire [1:0] pma_checker_real_hits_lo_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_real_hits_lo_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_real_hits_hi_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_real_hits_hi_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_real_hits_hi_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker__special_entry_level_T = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_special_entry_data_0_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_special_entry_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_special_entry_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_special_entry_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_special_entry_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_waddr = 2'h0; // @[TLB.scala:477:22] wire [1:0] pma_checker_superpage_entries_0_data_0_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_0_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_1 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_1_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_2 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_2_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_3 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_3_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_4 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_4_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_5 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_5_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_6 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_6_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_idx_7 = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker_sectored_entries_0_7_data_lo_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24] wire [1:0] pma_checker__pr_array_T = 2'h0; // @[TLB.scala:529:26] wire [1:0] pma_checker__pw_array_T = 2'h0; // @[TLB.scala:531:26] wire [1:0] pma_checker__px_array_T = 2'h0; // @[TLB.scala:533:26] wire [1:0] pma_checker_lo_lo = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_lo_hi = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_hi_lo = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_hi_hi = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_hi_2 = 2'h0; // @[OneHot.scala:30:18] wire [1:0] pma_checker_lo_2 = 2'h0; // @[OneHot.scala:31:18] wire [1:0] pma_checker__state_vec_0_T = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker__state_vec_0_T_11 = 2'h0; // @[Replacement.scala:207:62] wire [1:0] pma_checker_lo_3 = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_hi_3 = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_hi_4 = 2'h0; // @[OneHot.scala:30:18] wire [1:0] pma_checker_lo_4 = 2'h0; // @[OneHot.scala:31:18] wire [1:0] pma_checker_state_reg_touch_way_sized = 2'h0; // @[package.scala:163:13] wire [1:0] pma_checker__multipleHits_T_3 = 2'h0; // @[Misc.scala:182:39] wire [1:0] pma_checker__multipleHits_T_12 = 2'h0; // @[Misc.scala:182:39] wire [1:0] pma_checker__multipleHits_T_24 = 2'h0; // @[Misc.scala:182:39] wire [1:0] pma_checker__multipleHits_T_32 = 2'h0; // @[Misc.scala:181:37] wire [1:0] pma_checker__multipleHits_T_37 = 2'h0; // @[Misc.scala:182:39] wire [1:0] pma_checker__r_superpage_repl_addr_T_3 = 2'h0; // @[Replacement.scala:249:12] wire [1:0] pma_checker_r_superpage_repl_addr_valids_lo = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_r_superpage_repl_addr_valids_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker__r_superpage_repl_addr_T_12 = 2'h0; // @[Mux.scala:50:70] wire [1:0] pma_checker__r_superpage_repl_addr_T_13 = 2'h0; // @[TLB.scala:757:8] wire [1:0] pma_checker__r_sectored_repl_addr_T_3 = 2'h0; // @[Replacement.scala:249:12] wire [1:0] pma_checker__r_sectored_repl_addr_T_7 = 2'h0; // @[Replacement.scala:249:12] wire [1:0] pma_checker__r_sectored_repl_addr_T_8 = 2'h0; // @[Replacement.scala:250:16] wire [1:0] pma_checker_r_sectored_repl_addr_valids_lo_lo = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_r_sectored_repl_addr_valids_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_r_sectored_repl_addr_valids_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_r_sectored_repl_addr_valids_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] pma_checker_r_sectored_hit_bits_lo_lo = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_r_sectored_hit_bits_lo_hi = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_r_sectored_hit_bits_hi_lo = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_r_sectored_hit_bits_hi_hi = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_r_sectored_hit_bits_hi_2 = 2'h0; // @[OneHot.scala:30:18] wire [1:0] pma_checker_r_sectored_hit_bits_lo_2 = 2'h0; // @[OneHot.scala:31:18] wire [1:0] pma_checker__r_sectored_hit_bits_T_4 = 2'h0; // @[OneHot.scala:32:28] wire [1:0] pma_checker__r_sectored_hit_bits_T_6 = 2'h0; // @[OneHot.scala:32:10] wire [1:0] pma_checker_r_superpage_hit_bits_lo = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_r_superpage_hit_bits_hi = 2'h0; // @[OneHot.scala:21:45] wire [1:0] pma_checker_r_superpage_hit_bits_hi_1 = 2'h0; // @[OneHot.scala:30:18] wire [1:0] pma_checker_r_superpage_hit_bits_lo_1 = 2'h0; // @[OneHot.scala:31:18] wire [1:0] pma_checker__r_superpage_hit_bits_T_2 = 2'h0; // @[OneHot.scala:32:28] wire [1:0] pma_checker__r_superpage_hit_bits_T_4 = 2'h0; // @[OneHot.scala:32:10] wire [1:0] s1_meta_hit_state_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _s2_valid_no_xcpt_T_1 = 2'h0; // @[DCache.scala:332:54] wire [1:0] s2_meta_correctable_errors_lo_lo = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_correctable_errors_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_correctable_errors_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_correctable_errors_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_uncorrectable_errors_lo_lo = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_uncorrectable_errors_lo_hi = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_uncorrectable_errors_hi_lo = 2'h0; // @[package.scala:45:27] wire [1:0] s2_meta_uncorrectable_errors_hi_hi = 2'h0; // @[package.scala:45:27] wire [1:0] _r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_75 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_79 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_83 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_87 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_91 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_139 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_143 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_147 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_151 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_155 = 2'h0; // @[Misc.scala:38:63] wire [1:0] metaArb_io_in_1_bits_data_new_meta_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _metaArb_io_in_3_bits_data_T_2 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _metaArb_io_in_3_bits_data_T_4 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] probe_bits_res_param = 2'h0; // @[DCache.scala:1202:19] wire [1:0] _nodeOut_c_bits_legal_T_2 = 2'h0; // @[Parameters.scala:137:41] wire [1:0] _nodeOut_c_bits_legal_T_36 = 2'h0; // @[Parameters.scala:137:41] wire [1:0] _io_cpu_s2_xcpt_WIRE_size = 2'h0; // @[DCache.scala:933:74] wire [1:0] metaArb_io_in_0_bits_data_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] metaArb_io_in_0_bits_data_meta_1_coh_state = 2'h0; // @[HellaCache.scala:305:20] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[DCache.scala:101:7] wire [29:0] pma_checker_io_ptw_hstatus_zero6 = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_0_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_1_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_2_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_3_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_4_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_5_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_6_addr = 30'h0; // @[DCache.scala:120:32] wire [29:0] pma_checker_io_ptw_pmp_7_addr = 30'h0; // @[DCache.scala:120:32] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[DCache.scala:101:7] wire [8:0] pma_checker_io_ptw_hstatus_zero5 = 9'h0; // @[DCache.scala:120:32] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[DCache.scala:101:7] wire [5:0] pma_checker_io_ptw_hstatus_vgein = 6'h0; // @[DCache.scala:120:32] wire [5:0] pma_checker_real_hits_lo = 6'h0; // @[package.scala:45:27] wire [5:0] pma_checker_special_entry_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_0_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_1_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_2_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_3_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_0_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_1_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_2_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_3_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_4_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_5_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_6_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_7_data_hi_lo = 6'h0; // @[TLB.scala:217:24] wire [5:0] pma_checker__multipleHits_T = 6'h0; // @[Misc.scala:181:37] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[DCache.scala:101:7] wire [4:0] io_tlb_port_req_bits_cmd = 5'h0; // @[DCache.scala:101:7] wire [4:0] pma_checker_io_ptw_hstatus_zero1 = 5'h0; // @[DCache.scala:120:32] wire [4:0] _io_cpu_s2_xcpt_WIRE_cmd = 5'h0; // @[DCache.scala:933:74] wire [7:0] pma_checker__r_sectored_repl_addr_T_11 = 8'hFF; // @[TLB.scala:757:43] wire [7:0] metaArb_io_in_0_bits_way_en = 8'hFF; // @[DCache.scala:135:28] wire [7:0] dataArb_io_in_1_bits_eccMask = 8'hFF; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_2_bits_eccMask = 8'hFF; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_2_bits_way_en = 8'hFF; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_3_bits_eccMask = 8'hFF; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_3_bits_way_en = 8'hFF; // @[DCache.scala:152:28] wire [7:0] _dataArb_io_in_3_bits_wordMask_T = 8'hFF; // @[DCache.scala:254:9] wire [7:0] _dataArb_io_in_3_bits_eccMask_T = 8'hFF; // @[DCache.scala:256:36] wire [7:0] _dataArb_io_in_3_bits_way_en_T = 8'hFF; // @[DCache.scala:257:35] wire [7:0] tl_out_a_bits_a_mask = 8'hFF; // @[Edges.scala:346:17] wire [7:0] _tl_out_a_bits_a_mask_T = 8'hFF; // @[Misc.scala:222:10] wire [7:0] _dataArb_io_in_1_bits_eccMask_T = 8'hFF; // @[DCache.scala:732:38] wire [7:0] _dataArb_io_in_2_bits_eccMask_T = 8'hFF; // @[DCache.scala:905:36] wire [7:0] _dataArb_io_in_2_bits_way_en_T = 8'hFF; // @[DCache.scala:906:35] wire [7:0] _metaArb_io_in_0_bits_way_en_T = 8'hFF; // @[DCache.scala:1049:35] wire [2:0] pma_checker__r_sectored_repl_addr_T_20 = 3'h6; // @[Mux.scala:50:70] wire [2:0] tl_out_a_bits_a_opcode = 3'h6; // @[Edges.scala:346:17] wire [2:0] _tl_out_a_bits_a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34] wire [2:0] nodeOut_c_bits_c_opcode = 3'h6; // @[Edges.scala:380:17] wire [2:0] pma_checker_real_hits_lo_lo = 3'h0; // @[package.scala:45:27] wire [2:0] pma_checker_real_hits_lo_hi = 3'h0; // @[package.scala:45:27] wire [2:0] pma_checker_real_hits_hi_lo = 3'h0; // @[package.scala:45:27] wire [2:0] pma_checker_special_entry_data_0_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_special_entry_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_special_entry_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_special_entry_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_waddr_1 = 3'h0; // @[TLB.scala:485:22] wire [2:0] pma_checker_sectored_entries_0_0_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_lo_hi_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24] wire [2:0] pma_checker_state_vec_0_touch_way_sized = 3'h0; // @[package.scala:163:13] wire [2:0] pma_checker_state_vec_0_left_subtree_state = 3'h0; // @[package.scala:163:13] wire [2:0] pma_checker_state_vec_0_right_subtree_state = 3'h0; // @[Replacement.scala:198:38] wire [2:0] pma_checker__state_vec_0_T_10 = 3'h0; // @[Replacement.scala:203:16] wire [2:0] pma_checker__multipleHits_T_1 = 3'h0; // @[Misc.scala:181:37] wire [2:0] pma_checker__multipleHits_T_10 = 3'h0; // @[Misc.scala:182:39] wire [2:0] pma_checker__multipleHits_T_22 = 3'h0; // @[Misc.scala:181:37] wire [2:0] pma_checker_r_sectored_repl_addr_left_subtree_state = 3'h0; // @[package.scala:163:13] wire [2:0] pma_checker_r_sectored_repl_addr_right_subtree_state = 3'h0; // @[Replacement.scala:245:38] wire [2:0] pma_checker__r_sectored_repl_addr_T_9 = 3'h0; // @[Replacement.scala:249:12] wire [2:0] pma_checker__r_sectored_repl_addr_T_26 = 3'h0; // @[Mux.scala:50:70] wire [2:0] pma_checker__r_sectored_repl_addr_T_27 = 3'h0; // @[TLB.scala:757:8] wire [2:0] pma_checker__r_sectored_hit_bits_T_7 = 3'h0; // @[OneHot.scala:32:10] wire [2:0] get_param = 3'h0; // @[Edges.scala:460:17] wire [2:0] put_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] put_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] putpartial_param = 3'h0; // @[Edges.scala:500:17] wire [2:0] _atomics_WIRE_opcode = 3'h0; // @[DCache.scala:587:51] wire [2:0] _atomics_WIRE_param = 3'h0; // @[DCache.scala:587:51] wire [2:0] _atomics_WIRE_1_opcode = 3'h0; // @[DCache.scala:587:38] wire [2:0] _atomics_WIRE_1_param = 3'h0; // @[DCache.scala:587:38] wire [2:0] atomics_a_1_param = 3'h0; // @[Edges.scala:534:17] wire [2:0] atomics_a_5_param = 3'h0; // @[Edges.scala:517:17] wire [2:0] probe_bits_res_opcode = 3'h0; // @[DCache.scala:1202:19] wire [2:0] pma_checker__state_vec_0_T_9 = 3'h5; // @[Replacement.scala:202:12] wire [2:0] pma_checker__state_vec_0_T_20 = 3'h5; // @[Replacement.scala:202:12] wire [2:0] pma_checker__state_vec_0_T_21 = 3'h5; // @[Replacement.scala:206:16] wire [2:0] pma_checker__state_reg_T_8 = 3'h5; // @[Replacement.scala:202:12] wire [2:0] pma_checker__r_sectored_repl_addr_T_21 = 3'h5; // @[Mux.scala:50:70] wire [2:0] tl_out_a_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [2:0] nackResponseMessage_param = 3'h5; // @[Edges.scala:416:17] wire [2:0] dirtyReleaseMessage_opcode = 3'h5; // @[Edges.scala:433:17] wire [2:0] pma_checker__r_sectored_repl_addr_T_22 = 3'h4; // @[Mux.scala:50:70] wire [2:0] get_opcode = 3'h4; // @[Edges.scala:460:17] wire [2:0] atomics_a_4_param = 3'h4; // @[Edges.scala:517:17] wire [2:0] _tl_out_a_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] nackResponseMessage_opcode = 3'h4; // @[Edges.scala:416:17] wire [2:0] cleanReleaseMessage_opcode = 3'h4; // @[Edges.scala:416:17] wire [1:0] pma_checker__r_superpage_repl_addr_T_11 = 2'h1; // @[Mux.scala:50:70] wire [1:0] _r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] dataArb_io_in_0_bits_wordMask_wordMask = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _dataArb_io_in_0_bits_wordMask_T_2 = 2'h1; // @[DCache.scala:555:20] wire [1:0] _metaArb_io_in_3_bits_data_T_6 = 2'h1; // @[Metadata.scala:25:15] wire [3:0] pma_checker__r_superpage_repl_addr_T_5 = 4'hF; // @[TLB.scala:757:43] wire [3:0] _r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] tl_out_a_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] tl_out_a_bits_a_mask_hi = 4'hF; // @[Misc.scala:222:10] wire [1:0] io_ptw_status_sxl = 2'h2; // @[DCache.scala:101:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[DCache.scala:101:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[DCache.scala:101:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[DCache.scala:101:7] wire [1:0] pma_checker_state_vec_0_hi = 2'h2; // @[Replacement.scala:202:12] wire [1:0] pma_checker_state_vec_0_hi_1 = 2'h2; // @[Replacement.scala:202:12] wire [1:0] pma_checker_state_reg_hi = 2'h2; // @[Replacement.scala:202:12] wire [1:0] pma_checker__r_superpage_repl_addr_T_10 = 2'h2; // @[Mux.scala:50:70] wire [1:0] pma_checker__state_T = 2'h2; // @[TLB.scala:704:45] wire [1:0] _r_T_118 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_120 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_122 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] tl_out_a_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [2:0] pma_checker__r_sectored_repl_addr_T_23 = 3'h3; // @[Mux.scala:50:70] wire [2:0] atomics_a_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_param = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_1_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_2_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_3_opcode = 3'h3; // @[Edges.scala:534:17] wire [2:0] atomics_a_8_param = 3'h3; // @[Edges.scala:517:17] wire [2:0] pma_checker__r_sectored_repl_addr_T_24 = 3'h2; // @[Mux.scala:50:70] wire [2:0] atomics_a_3_param = 3'h2; // @[Edges.scala:534:17] wire [2:0] atomics_a_4_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_5_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_6_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_7_param = 3'h2; // @[Edges.scala:517:17] wire [2:0] atomics_a_8_opcode = 3'h2; // @[Edges.scala:517:17] wire [2:0] pma_checker_mpu_priv = 3'h1; // @[TLB.scala:415:27] wire [2:0] pma_checker__r_sectored_repl_addr_T_25 = 3'h1; // @[Mux.scala:50:70] wire [2:0] putpartial_opcode = 3'h1; // @[Edges.scala:500:17] wire [2:0] atomics_a_2_param = 3'h1; // @[Edges.scala:534:17] wire [2:0] atomics_a_6_param = 3'h1; // @[Edges.scala:517:17] wire [3:0] pma_checker_state_vec_0_hi_2 = 4'h8; // @[Replacement.scala:202:12] wire [3:0] _r_T_71 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _r_T_135 = 4'h8; // @[Metadata.scala:133:10] wire [11:0] pma_checker__gpa_hits_hit_mask_T_2 = 12'h0; // @[TLB.scala:606:24] wire [11:0] pma_checker__io_resp_gpa_offset_T = 12'h0; // @[TLB.scala:658:47] wire [26:0] pma_checker_io_ptw_req_bits_bits_addr = 27'h0; // @[DCache.scala:120:32] wire [26:0] pma_checker__io_resp_gpa_page_T_2 = 27'h0; // @[TLB.scala:657:58] wire [6:0] pma_checker__state_vec_0_T_22 = 7'h45; // @[Replacement.scala:202:12] wire [63:0] io_cpu_req_bits_data = 64'h0; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[DCache.scala:101:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[DCache.scala:101:7] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_0_value = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_1_value = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_2_wdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_2_value = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_3_wdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_3_value = 64'h0; // @[DCache.scala:120:32] wire [63:0] pma_checker_io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[DCache.scala:120:32] wire [63:0] s0_req_data = 64'h0; // @[DCache.scala:192:24] wire [63:0] get_data = 64'h0; // @[Edges.scala:460:17] wire [63:0] _atomics_WIRE_data = 64'h0; // @[DCache.scala:587:51] wire [63:0] _atomics_WIRE_1_data = 64'h0; // @[DCache.scala:587:38] wire [63:0] tl_out_a_bits_a_data = 64'h0; // @[Edges.scala:346:17] wire [63:0] nackResponseMessage_data = 64'h0; // @[Edges.scala:416:17] wire [63:0] cleanReleaseMessage_data = 64'h0; // @[Edges.scala:416:17] wire [63:0] dirtyReleaseMessage_data = 64'h0; // @[Edges.scala:433:17] wire [63:0] probe_bits_res_data = 64'h0; // @[DCache.scala:1202:19] wire [63:0] nodeOut_c_bits_c_data = 64'h0; // @[Edges.scala:380:17] wire [63:0] nodeOut_c_bits_c_1_data = 64'h0; // @[Edges.scala:396:17] wire [63:0] _s2_data_word_possibly_uncached_T_1 = 64'h0; // @[DCache.scala:972:43] wire [38:0] pma_checker_io_sfence_bits_addr = 39'h0; // @[DCache.scala:120:32] wire [38:0] pma_checker_io_ptw_resp_bits_gpa_bits = 39'h0; // @[DCache.scala:120:32] wire [39:0] io_tlb_port_req_bits_vaddr = 40'h0; // @[DCache.scala:101:7] wire [39:0] _io_cpu_s2_xcpt_WIRE_gpa = 40'h0; // @[DCache.scala:933:74] wire [21:0] pma_checker_special_entry_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_superpage_entries_0_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_superpage_entries_1_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_superpage_entries_2_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_superpage_entries_3_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_0_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_1_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_2_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_3_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_4_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_5_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_6_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] pma_checker_sectored_entries_0_7_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24] wire [21:0] metaArb_io_in_0_bits_data = 22'h0; // @[DCache.scala:135:28] wire [21:0] _metaArb_io_in_0_bits_data_T = 22'h0; // @[DCache.scala:1050:85] wire [19:0] pma_checker_refill_ppn = 20'h0; // @[TLB.scala:406:44] wire [19:0] pma_checker_newEntry_ppn = 20'h0; // @[TLB.scala:449:24] wire [19:0] pma_checker__ppn_T_42 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_43 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_44 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_45 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_46 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_47 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_48 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_49 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_50 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_51 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_52 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_53 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_54 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_56 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_57 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_58 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_59 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_60 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_61 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_62 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_63 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_64 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_65 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_66 = 20'h0; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_67 = 20'h0; // @[Mux.scala:30:73] wire [19:0] metaArb_io_in_0_bits_data_meta_1_tag = 20'h0; // @[HellaCache.scala:305:20] wire [31:0] pma_checker_io_ptw_status_isa = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_gstatus_isa = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_0_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_1_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_2_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_3_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_4_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_5_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_6_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_ptw_pmp_7_mask = 32'h0; // @[DCache.scala:120:32] wire [31:0] _atomics_WIRE_address = 32'h0; // @[DCache.scala:587:51] wire [31:0] _atomics_WIRE_1_address = 32'h0; // @[DCache.scala:587:38] wire [31:0] nodeOut_c_bits_c_address = 32'h0; // @[Edges.scala:380:17] wire [31:0] nodeOut_c_bits_c_1_address = 32'h0; // @[Edges.scala:396:17] wire [31:0] _io_cpu_s2_xcpt_WIRE_paddr = 32'h0; // @[DCache.scala:933:74] wire [3:0] _r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r_T_65 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _r_T_129 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] tl_out_a_bits_a_size = 4'h6; // @[Edges.scala:346:17] wire [3:0] _release_state_T_13 = 4'h6; // @[DCache.scala:820:27] wire [3:0] nodeOut_c_bits_c_size = 4'h6; // @[Edges.scala:380:17] wire [3:0] nodeOut_c_bits_c_1_size = 4'h6; // @[Edges.scala:396:17] wire [2:0] nodeOut_c_bits_c_1_opcode = 3'h7; // @[Edges.scala:396:17] wire [32:0] _nodeOut_c_bits_legal_T_27 = 33'h80000000; // @[Parameters.scala:137:41] wire [32:0] _nodeOut_c_bits_legal_T_28 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_29 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_61 = 33'h80000000; // @[Parameters.scala:137:41] wire [32:0] _nodeOut_c_bits_legal_T_62 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_63 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_23 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_24 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_57 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_58 = 33'h8000000; // @[Parameters.scala:137:46] wire [28:0] _nodeOut_c_bits_legal_T_22 = 29'h8000000; // @[Parameters.scala:137:41] wire [28:0] _nodeOut_c_bits_legal_T_56 = 29'h8000000; // @[Parameters.scala:137:41] wire [32:0] _nodeOut_c_bits_legal_T_13 = 33'hC000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_14 = 33'hC000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_47 = 33'hC000000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_48 = 33'hC000000; // @[Parameters.scala:137:46] wire [28:0] _nodeOut_c_bits_legal_T_12 = 29'hC000000; // @[Parameters.scala:137:41] wire [28:0] _nodeOut_c_bits_legal_T_46 = 29'hC000000; // @[Parameters.scala:137:41] wire [32:0] _nodeOut_c_bits_legal_T_8 = 33'h10000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_9 = 33'h10000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_42 = 33'h10000; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_43 = 33'h10000; // @[Parameters.scala:137:46] wire [17:0] _nodeOut_c_bits_legal_T_7 = 18'h10000; // @[Parameters.scala:137:41] wire [17:0] _nodeOut_c_bits_legal_T_41 = 18'h10000; // @[Parameters.scala:137:41] wire [32:0] _nodeOut_c_bits_legal_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_4 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_37 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _nodeOut_c_bits_legal_T_38 = 33'h0; // @[Parameters.scala:137:46] wire [3:0] _r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _metaArb_io_in_3_bits_data_T_9 = 4'hC; // @[Metadata.scala:89:10] wire [1:0] _r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] tl_out_a_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] tl_out_a_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] tl_out_a_bits_a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] tl_out_a_bits_a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _metaArb_io_in_3_bits_data_T_8 = 2'h3; // @[Metadata.scala:24:15] wire [3:0] _r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r_T_67 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _r_T_131 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _tl_out_a_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _metaArb_io_in_3_bits_data_T_7 = 4'h4; // @[Metadata.scala:88:10] wire [3:0] _r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_62 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _r_T_126 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _metaArb_io_in_3_bits_data_T_3 = 4'h1; // @[Metadata.scala:86:10] wire [8:0] _s1_data_way_T_1 = 9'h100; // @[DCache.scala:694:32] wire [3:0] _r_T_70 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_134 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_69 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_133 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_68 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _r_T_132 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r_T_66 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_130 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r_T_64 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_128 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_61 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_125 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_60 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_124 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [13:0] pma_checker__gf_ld_array_T_2 = 14'h0; // @[TLB.scala:600:46] wire [13:0] pma_checker_gf_ld_array = 14'h0; // @[TLB.scala:600:24] wire [13:0] pma_checker__gf_st_array_T_1 = 14'h0; // @[TLB.scala:601:53] wire [13:0] pma_checker_gf_st_array = 14'h0; // @[TLB.scala:601:24] wire [13:0] pma_checker__gf_inst_array_T = 14'h0; // @[TLB.scala:602:36] wire [13:0] pma_checker_gf_inst_array = 14'h0; // @[TLB.scala:602:26] wire [13:0] pma_checker_gpa_hits_need_gpa_mask = 14'h0; // @[TLB.scala:605:73] wire [13:0] pma_checker__io_resp_gf_ld_T_1 = 14'h0; // @[TLB.scala:637:58] wire [13:0] pma_checker__io_resp_gf_st_T_1 = 14'h0; // @[TLB.scala:638:65] wire [13:0] pma_checker__io_resp_gf_inst_T = 14'h0; // @[TLB.scala:639:48] wire [6:0] pma_checker_real_hits_hi = 7'h0; // @[package.scala:45:27] wire [6:0] pma_checker__state_vec_WIRE_0 = 7'h0; // @[Replacement.scala:305:25] wire [6:0] pma_checker__multipleHits_T_21 = 7'h0; // @[Misc.scala:182:39] wire [12:0] pma_checker_real_hits = 13'h0; // @[package.scala:45:27] wire [12:0] pma_checker__stage1_bypass_T = 13'h0; // @[TLB.scala:517:27] wire [12:0] pma_checker_stage1_bypass = 13'h0; // @[TLB.scala:517:61] wire [12:0] pma_checker__r_array_T_2 = 13'h0; // @[TLB.scala:520:74] wire [12:0] pma_checker__hr_array_T_2 = 13'h0; // @[TLB.scala:524:60] wire [12:0] pma_checker__gpa_hits_T = 13'h0; // @[TLB.scala:607:30] wire [12:0] pma_checker__tlb_hit_T = 13'h0; // @[TLB.scala:611:28] wire [12:0] pma_checker__stage1_bypass_T_2 = 13'h1FFF; // @[TLB.scala:517:68] wire [12:0] pma_checker__stage1_bypass_T_4 = 13'h1FFF; // @[TLB.scala:517:95] wire [12:0] pma_checker_stage2_bypass = 13'h1FFF; // @[TLB.scala:523:27] wire [12:0] pma_checker__hr_array_T_4 = 13'h1FFF; // @[TLB.scala:524:111] wire [12:0] pma_checker__hw_array_T_1 = 13'h1FFF; // @[TLB.scala:525:55] wire [12:0] pma_checker__hx_array_T_1 = 13'h1FFF; // @[TLB.scala:526:55] wire [12:0] pma_checker__gpa_hits_hit_mask_T_4 = 13'h1FFF; // @[TLB.scala:606:88] wire [12:0] pma_checker_gpa_hits_hit_mask = 13'h1FFF; // @[TLB.scala:606:82] wire [12:0] pma_checker__gpa_hits_T_1 = 13'h1FFF; // @[TLB.scala:607:16] wire [12:0] pma_checker_gpa_hits = 13'h1FFF; // @[TLB.scala:607:14] wire [13:0] pma_checker_hr_array = 14'h3FFF; // @[TLB.scala:524:21] wire [13:0] pma_checker_hw_array = 14'h3FFF; // @[TLB.scala:525:21] wire [13:0] pma_checker_hx_array = 14'h3FFF; // @[TLB.scala:526:21] wire [13:0] pma_checker__must_alloc_array_T_8 = 14'h3FFF; // @[TLB.scala:596:19] wire [13:0] pma_checker__gf_ld_array_T_1 = 14'h3FFF; // @[TLB.scala:600:50] wire [30:0] pma_checker_special_entry_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_superpage_entries_0_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_superpage_entries_1_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_superpage_entries_2_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_superpage_entries_3_data_0_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_0_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_1_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_2_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_3_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_4_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_5_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_6_data_hi = 31'h0; // @[TLB.scala:217:24] wire [30:0] pma_checker_sectored_entries_0_7_data_hi = 31'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_special_entry_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_superpage_entries_0_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_superpage_entries_1_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_superpage_entries_2_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_superpage_entries_3_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_0_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_1_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_2_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_3_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_4_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_5_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_6_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [24:0] pma_checker_sectored_entries_0_7_data_hi_hi = 25'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_special_entry_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_superpage_entries_0_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_superpage_entries_1_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_superpage_entries_2_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_superpage_entries_3_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_0_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_1_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_2_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_3_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_4_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_5_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_6_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [20:0] pma_checker_sectored_entries_0_7_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24] wire [13:0] pma_checker_hits = 14'h2000; // @[TLB.scala:442:17] wire [9:0] pma_checker_io_ptw_resp_bits_pte_reserved_for_future = 10'h0; // @[DCache.scala:120:32] wire [31:0] _nodeOut_c_bits_legal_T_26 = 32'h80000000; // @[Parameters.scala:137:31] wire [31:0] _nodeOut_c_bits_legal_T_60 = 32'h80000000; // @[Parameters.scala:137:31] wire [27:0] _nodeOut_c_bits_legal_T_11 = 28'hC000000; // @[Parameters.scala:137:31] wire [27:0] _nodeOut_c_bits_legal_T_45 = 28'hC000000; // @[Parameters.scala:137:31] wire [27:0] _nodeOut_c_bits_legal_T_21 = 28'h8000000; // @[Parameters.scala:137:31] wire [27:0] _nodeOut_c_bits_legal_T_55 = 28'h8000000; // @[Parameters.scala:137:31] wire [16:0] _nodeOut_c_bits_legal_T_6 = 17'h10000; // @[Parameters.scala:137:31] wire [16:0] _nodeOut_c_bits_legal_T_40 = 17'h10000; // @[Parameters.scala:137:31] wire [41:0] pma_checker__mpu_ppn_WIRE_1 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_1 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_3 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_5 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_7 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_9 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_11 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_13 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_15 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_17 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_19 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_21 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_23 = 42'h0; // @[TLB.scala:170:77] wire [41:0] pma_checker__entries_WIRE_25 = 42'h0; // @[TLB.scala:170:77] wire nodeOut_a_ready = auto_out_a_ready_0; // @[DCache.scala:101:7] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[DCache.scala:101:7] wire [2:0] nodeOut_b_bits_opcode = auto_out_b_bits_opcode_0; // @[DCache.scala:101:7] wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[DCache.scala:101:7] wire [3:0] nodeOut_b_bits_size = auto_out_b_bits_size_0; // @[DCache.scala:101:7] wire nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[DCache.scala:101:7] wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[DCache.scala:101:7] wire [7:0] nodeOut_b_bits_mask = auto_out_b_bits_mask_0; // @[DCache.scala:101:7] wire [63:0] nodeOut_b_bits_data = auto_out_b_bits_data_0; // @[DCache.scala:101:7] wire nodeOut_b_bits_corrupt = auto_out_b_bits_corrupt_0; // @[DCache.scala:101:7] wire nodeOut_c_ready = auto_out_c_ready_0; // @[DCache.scala:101:7] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[DCache.scala:101:7] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[DCache.scala:101:7] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[DCache.scala:101:7] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[DCache.scala:101:7] wire nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[DCache.scala:101:7] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[DCache.scala:101:7] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[DCache.scala:101:7] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[DCache.scala:101:7] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[DCache.scala:101:7] wire nodeOut_e_ready = auto_out_e_ready_0; // @[DCache.scala:101:7] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire metaArb_io_in_7_valid = io_cpu_req_valid_0; // @[DCache.scala:101:7, :135:28] wire [39:0] metaArb_io_in_7_bits_addr = io_cpu_req_bits_addr_0; // @[DCache.scala:101:7, :135:28] wire [6:0] s0_req_tag = io_cpu_req_bits_tag_0; // @[DCache.scala:101:7, :192:24] wire [4:0] s0_req_cmd = io_cpu_req_bits_cmd_0; // @[DCache.scala:101:7, :192:24] wire [1:0] s0_req_size = io_cpu_req_bits_size_0; // @[DCache.scala:101:7, :192:24] wire s0_req_signed = io_cpu_req_bits_signed_0; // @[DCache.scala:101:7, :192:24] wire [1:0] s0_req_dprv = io_cpu_req_bits_dprv_0; // @[DCache.scala:101:7, :192:24] wire s0_req_dv = io_cpu_req_bits_dv_0; // @[DCache.scala:101:7, :192:24] wire s0_req_no_resp = io_cpu_req_bits_no_resp_0; // @[DCache.scala:101:7, :192:24] wire _io_cpu_s2_nack_T_5; // @[DCache.scala:445:86] wire _io_cpu_s2_nack_cause_raw_T_3; // @[DCache.scala:574:54] wire _io_cpu_s2_uncached_T_1; // @[DCache.scala:920:37] wire _io_cpu_resp_valid_T_2; // @[DCache.scala:949:70] wire [63:0] _io_cpu_resp_bits_data_T_24; // @[DCache.scala:974:41] wire s2_read; // @[Consts.scala:89:68] wire [63:0] _io_cpu_resp_bits_data_word_bypass_T_7; // @[AMOALU.scala:45:16] wire [63:0] s2_data_word; // @[DCache.scala:970:80] wire _io_cpu_replay_next_T_3; // @[DCache.scala:950:62] wire _io_cpu_s2_xcpt_T_ma_ld; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_ma_st; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_pf_ld; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_pf_st; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_ae_ld; // @[DCache.scala:933:24] wire _io_cpu_s2_xcpt_T_ae_st; // @[DCache.scala:933:24] wire _io_cpu_ordered_T_8; // @[DCache.scala:929:21] wire _io_cpu_store_pending_T_25; // @[DCache.scala:930:70] wire io_cpu_perf_acquire_done; // @[Edges.scala:233:22] wire io_cpu_perf_release_done; // @[Edges.scala:233:22] wire _io_cpu_perf_grant_T; // @[DCache.scala:1078:39] wire _io_cpu_perf_tlbMiss_T; // @[Decoupled.scala:51:35] wire _io_cpu_perf_blocked_T_1; // @[DCache.scala:1106:23] wire _io_cpu_perf_canAcceptStoreThenLoad_T_10; // @[DCache.scala:1088:41] wire _io_cpu_perf_canAcceptStoreThenRMW_T_1; // @[DCache.scala:1091:75] wire _io_cpu_perf_canAcceptLoadThenLoad_T_61; // @[DCache.scala:1092:40] wire _io_cpu_perf_storeBufferEmptyAfterLoad_T_7; // @[DCache.scala:1080:44] wire _io_cpu_perf_storeBufferEmptyAfterStore_T_10; // @[DCache.scala:1084:45] wire _io_errors_bus_valid_T_2; // @[DCache.scala:1129:42] wire [2:0] auto_out_a_bits_opcode_0; // @[DCache.scala:101:7] wire [2:0] auto_out_a_bits_param_0; // @[DCache.scala:101:7] wire [3:0] auto_out_a_bits_size_0; // @[DCache.scala:101:7] wire auto_out_a_bits_source_0; // @[DCache.scala:101:7] wire [31:0] auto_out_a_bits_address_0; // @[DCache.scala:101:7] wire [7:0] auto_out_a_bits_mask_0; // @[DCache.scala:101:7] wire [63:0] auto_out_a_bits_data_0; // @[DCache.scala:101:7] wire auto_out_a_valid_0; // @[DCache.scala:101:7] wire auto_out_b_ready_0; // @[DCache.scala:101:7] wire [2:0] auto_out_c_bits_opcode_0; // @[DCache.scala:101:7] wire [2:0] auto_out_c_bits_param_0; // @[DCache.scala:101:7] wire [3:0] auto_out_c_bits_size_0; // @[DCache.scala:101:7] wire auto_out_c_bits_source_0; // @[DCache.scala:101:7] wire [31:0] auto_out_c_bits_address_0; // @[DCache.scala:101:7] wire [63:0] auto_out_c_bits_data_0; // @[DCache.scala:101:7] wire auto_out_c_valid_0; // @[DCache.scala:101:7] wire auto_out_d_ready_0; // @[DCache.scala:101:7] wire [2:0] auto_out_e_bits_sink_0; // @[DCache.scala:101:7] wire auto_out_e_valid_0; // @[DCache.scala:101:7] wire io_cpu_req_ready_0; // @[DCache.scala:101:7] wire [39:0] io_cpu_resp_bits_addr_0; // @[DCache.scala:101:7] wire [6:0] io_cpu_resp_bits_tag_0; // @[DCache.scala:101:7] wire [4:0] io_cpu_resp_bits_cmd_0; // @[DCache.scala:101:7] wire [1:0] io_cpu_resp_bits_size_0; // @[DCache.scala:101:7] wire io_cpu_resp_bits_signed_0; // @[DCache.scala:101:7] wire [1:0] io_cpu_resp_bits_dprv_0; // @[DCache.scala:101:7] wire io_cpu_resp_bits_dv_0; // @[DCache.scala:101:7] wire [63:0] io_cpu_resp_bits_data_0; // @[DCache.scala:101:7] wire [7:0] io_cpu_resp_bits_mask_0; // @[DCache.scala:101:7] wire io_cpu_resp_bits_replay_0; // @[DCache.scala:101:7] wire io_cpu_resp_bits_has_data_0; // @[DCache.scala:101:7] wire [63:0] io_cpu_resp_bits_data_word_bypass_0; // @[DCache.scala:101:7] wire [63:0] io_cpu_resp_bits_data_raw_0; // @[DCache.scala:101:7] wire [63:0] io_cpu_resp_bits_store_data_0; // @[DCache.scala:101:7] wire io_cpu_resp_valid_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_ma_ld_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_ma_st_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_pf_ld_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_pf_st_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_ae_ld_0; // @[DCache.scala:101:7] wire io_cpu_s2_xcpt_ae_st_0; // @[DCache.scala:101:7] wire io_cpu_perf_acquire_0; // @[DCache.scala:101:7] wire io_cpu_perf_release_0; // @[DCache.scala:101:7] wire io_cpu_perf_grant_0; // @[DCache.scala:101:7] wire io_cpu_perf_tlbMiss_0; // @[DCache.scala:101:7] wire io_cpu_perf_blocked_0; // @[DCache.scala:101:7] wire io_cpu_perf_canAcceptStoreThenLoad_0; // @[DCache.scala:101:7] wire io_cpu_perf_canAcceptStoreThenRMW_0; // @[DCache.scala:101:7] wire io_cpu_perf_canAcceptLoadThenLoad_0; // @[DCache.scala:101:7] wire io_cpu_perf_storeBufferEmptyAfterLoad_0; // @[DCache.scala:101:7] wire io_cpu_perf_storeBufferEmptyAfterStore_0; // @[DCache.scala:101:7] wire io_cpu_s2_nack_0; // @[DCache.scala:101:7] wire io_cpu_s2_nack_cause_raw_0; // @[DCache.scala:101:7] wire io_cpu_s2_uncached_0; // @[DCache.scala:101:7] wire [31:0] io_cpu_s2_paddr_0; // @[DCache.scala:101:7] wire io_cpu_replay_next_0; // @[DCache.scala:101:7] wire [39:0] io_cpu_s2_gpa_0; // @[DCache.scala:101:7] wire io_cpu_ordered_0; // @[DCache.scala:101:7] wire io_cpu_store_pending_0; // @[DCache.scala:101:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[DCache.scala:101:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[DCache.scala:101:7] wire io_ptw_req_valid_0; // @[DCache.scala:101:7] wire io_errors_bus_valid; // @[DCache.scala:101:7] wire [31:0] io_errors_bus_bits; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_pf_ld; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_pf_st; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_pf_inst; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ae_ld; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ae_st; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ae_inst; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ma_ld; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_ma_st; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_miss; // @[DCache.scala:101:7] wire [31:0] io_tlb_port_s1_resp_paddr; // @[DCache.scala:101:7] wire [39:0] io_tlb_port_s1_resp_gpa; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_cacheable; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_must_alloc; // @[DCache.scala:101:7] wire io_tlb_port_s1_resp_prefetchable; // @[DCache.scala:101:7] wire [1:0] io_tlb_port_s1_resp_size; // @[DCache.scala:101:7] wire [4:0] io_tlb_port_s1_resp_cmd; // @[DCache.scala:101:7] wire nodeOut_a_deq_ready = nodeOut_a_ready; // @[Decoupled.scala:356:21] wire nodeOut_a_deq_valid; // @[Decoupled.scala:356:21] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[DCache.scala:101:7] wire [2:0] nodeOut_a_deq_bits_opcode; // @[Decoupled.scala:356:21] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[DCache.scala:101:7] wire [2:0] nodeOut_a_deq_bits_param; // @[Decoupled.scala:356:21] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[DCache.scala:101:7] wire [3:0] nodeOut_a_deq_bits_size; // @[Decoupled.scala:356:21] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[DCache.scala:101:7] wire nodeOut_a_deq_bits_source; // @[Decoupled.scala:356:21] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[DCache.scala:101:7] wire [31:0] nodeOut_a_deq_bits_address; // @[Decoupled.scala:356:21] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[DCache.scala:101:7] wire [7:0] nodeOut_a_deq_bits_mask; // @[Decoupled.scala:356:21] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[DCache.scala:101:7] wire [63:0] nodeOut_a_deq_bits_data; // @[Decoupled.scala:356:21] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[DCache.scala:101:7] wire _nodeOut_b_ready_T_4; // @[DCache.scala:770:44] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[DCache.scala:101:7] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[DCache.scala:101:7] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[DCache.scala:101:7] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[DCache.scala:101:7] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[DCache.scala:101:7] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[DCache.scala:101:7] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[DCache.scala:101:7] wire [63:0] s2_data_corrected; // @[package.scala:45:27] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[DCache.scala:101:7] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[DCache.scala:101:7] wire uncachedRespIdxOH_shiftAmount = nodeOut_d_bits_source; // @[OneHot.scala:64:49] wire [2:0] nodeOut_e_bits_e_sink = nodeOut_d_bits_sink; // @[Edges.scala:451:17] wire [63:0] s1_uncached_data_word = nodeOut_d_bits_data; // @[package.scala:211:50] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[DCache.scala:101:7] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[DCache.scala:101:7] wire [1:0] pma_checker_io_resp_size = pma_checker_io_req_bits_size; // @[DCache.scala:120:32] wire [4:0] pma_checker_io_resp_cmd = pma_checker_io_req_bits_cmd; // @[DCache.scala:120:32] wire [31:0] pma_checker__io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [39:0] pma_checker__io_resp_gpa_T; // @[TLB.scala:659:8] wire pma_checker__io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire pma_checker__io_resp_pf_st_T_3; // @[TLB.scala:634:48] wire pma_checker__io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire pma_checker__io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire pma_checker__io_resp_ae_st_T_1; // @[TLB.scala:642:41] wire pma_checker__io_resp_ae_inst_T_2; // @[TLB.scala:643:41] wire pma_checker__io_resp_ma_ld_T; // @[TLB.scala:645:31] wire pma_checker__io_resp_ma_st_T; // @[TLB.scala:646:31] wire pma_checker__io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire pma_checker__io_resp_must_alloc_T_1; // @[TLB.scala:649:51] wire pma_checker__io_resp_prefetchable_T_2; // @[TLB.scala:650:59] wire [39:0] pma_checker_io_req_bits_vaddr; // @[DCache.scala:120:32] wire [1:0] pma_checker_io_req_bits_prv; // @[DCache.scala:120:32] wire pma_checker_io_req_bits_v; // @[DCache.scala:120:32] wire pma_checker_io_resp_pf_ld; // @[DCache.scala:120:32] wire pma_checker_io_resp_pf_st; // @[DCache.scala:120:32] wire pma_checker_io_resp_pf_inst; // @[DCache.scala:120:32] wire pma_checker_io_resp_ae_ld; // @[DCache.scala:120:32] wire pma_checker_io_resp_ae_st; // @[DCache.scala:120:32] wire pma_checker_io_resp_ae_inst; // @[DCache.scala:120:32] wire pma_checker_io_resp_ma_ld; // @[DCache.scala:120:32] wire pma_checker_io_resp_ma_st; // @[DCache.scala:120:32] wire [31:0] pma_checker_io_resp_paddr; // @[DCache.scala:120:32] wire [39:0] pma_checker_io_resp_gpa; // @[DCache.scala:120:32] wire pma_checker_io_resp_cacheable; // @[DCache.scala:120:32] wire pma_checker_io_resp_must_alloc; // @[DCache.scala:120:32] wire pma_checker_io_resp_prefetchable; // @[DCache.scala:120:32] wire [26:0] pma_checker_vpn = pma_checker_io_req_bits_vaddr[38:12]; // @[TLB.scala:335:30] wire [26:0] pma_checker__mpu_ppn_T_24 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__mpu_ppn_T_28 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__sector_hits_T_3 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_11 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_19 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_27 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_35 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_43 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_51 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__sector_hits_T_59 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__superpage_hits_T = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_5 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_10 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_14 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_19 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_24 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_28 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_33 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_38 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_42 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_47 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__superpage_hits_T_52 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_6 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_12 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_18 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_24 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_30 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_36 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_42 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30] wire [26:0] pma_checker__hitsVec_T_48 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_53 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_58 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_63 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_68 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_73 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_78 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_83 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_88 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_93 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_98 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_103 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_108 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_113 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__hitsVec_T_118 = pma_checker_vpn; // @[TLB.scala:183:52, :335:30] wire [26:0] pma_checker__ppn_T_5 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__ppn_T_13 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__ppn_T_21 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__ppn_T_29 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__ppn_T_33 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire [26:0] pma_checker__ppn_T_37 = pma_checker_vpn; // @[TLB.scala:198:28, :335:30] wire pma_checker_priv_s = pma_checker_io_req_bits_prv[0]; // @[TLB.scala:370:20] wire pma_checker_priv_uses_vm = ~(pma_checker_io_req_bits_prv[1]); // @[TLB.scala:372:27] wire [19:0] pma_checker__mpu_ppn_T_23; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_22; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_21; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_20; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_19; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_18; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_17; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_16; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_15; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_14; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_13; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_12; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_11; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_10; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_9; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_8; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_7; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_6; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_5; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_4; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_3; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_2; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_T_1; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_1 = pma_checker__mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_fragmented_superpage = pma_checker__mpu_ppn_T_1; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_2 = pma_checker__mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_c = pma_checker__mpu_ppn_T_2; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_3 = pma_checker__mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_eff = pma_checker__mpu_ppn_T_3; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_4 = pma_checker__mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_paa = pma_checker__mpu_ppn_T_4; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_5 = pma_checker__mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_pal = pma_checker__mpu_ppn_T_5; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_6 = pma_checker__mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_ppp = pma_checker__mpu_ppn_T_6; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_7 = pma_checker__mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_pr = pma_checker__mpu_ppn_T_7; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_8 = pma_checker__mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_px = pma_checker__mpu_ppn_T_8; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_9 = pma_checker__mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_pw = pma_checker__mpu_ppn_T_9; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_10 = pma_checker__mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_hr = pma_checker__mpu_ppn_T_10; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_11 = pma_checker__mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_hx = pma_checker__mpu_ppn_T_11; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_12 = pma_checker__mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_hw = pma_checker__mpu_ppn_T_12; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_13 = pma_checker__mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_sr = pma_checker__mpu_ppn_T_13; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_14 = pma_checker__mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_sx = pma_checker__mpu_ppn_T_14; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_15 = pma_checker__mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_sw = pma_checker__mpu_ppn_T_15; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_16 = pma_checker__mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_gf = pma_checker__mpu_ppn_T_16; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_17 = pma_checker__mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_pf = pma_checker__mpu_ppn_T_17; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_18 = pma_checker__mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_ae_stage2 = pma_checker__mpu_ppn_T_18; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_19 = pma_checker__mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_ae_final = pma_checker__mpu_ppn_T_19; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_20 = pma_checker__mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_ae_ptw = pma_checker__mpu_ppn_T_20; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_21 = pma_checker__mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_g = pma_checker__mpu_ppn_T_21; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_22 = pma_checker__mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77] wire pma_checker__mpu_ppn_WIRE_u = pma_checker__mpu_ppn_T_22; // @[TLB.scala:170:77] assign pma_checker__mpu_ppn_T_23 = pma_checker__mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__mpu_ppn_WIRE_ppn = pma_checker__mpu_ppn_T_23; // @[TLB.scala:170:77] wire [1:0] pma_checker_mpu_ppn_res = _pma_checker_mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25] wire [26:0] pma_checker__mpu_ppn_T_25 = {pma_checker__mpu_ppn_T_24[26:20], pma_checker__mpu_ppn_T_24[19:0] \| _pma_checker_mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__mpu_ppn_T_26 = pma_checker__mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] pma_checker__mpu_ppn_T_27 = {pma_checker_mpu_ppn_res, pma_checker__mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}] wire [26:0] pma_checker__mpu_ppn_T_29 = {pma_checker__mpu_ppn_T_28[26:20], pma_checker__mpu_ppn_T_28[19:0] \| _pma_checker_mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__mpu_ppn_T_30 = pma_checker__mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] pma_checker__mpu_ppn_T_31 = {pma_checker__mpu_ppn_T_27, pma_checker__mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}] wire [27:0] pma_checker__mpu_ppn_T_32 = pma_checker_io_req_bits_vaddr[39:12]; // @[TLB.scala:413:146] wire [27:0] pma_checker__mpu_ppn_T_33 = pma_checker__mpu_ppn_T_32; // @[TLB.scala:413:{20,146}] wire [27:0] pma_checker_mpu_ppn = pma_checker__mpu_ppn_T_33; // @[TLB.scala:412:20, :413:20] wire [11:0] pma_checker__mpu_physaddr_T = pma_checker_io_req_bits_vaddr[11:0]; // @[TLB.scala:414:52] wire [11:0] pma_checker__io_resp_paddr_T = pma_checker_io_req_bits_vaddr[11:0]; // @[TLB.scala:414:52, :652:46] wire [11:0] pma_checker__io_resp_gpa_offset_T_1 = pma_checker_io_req_bits_vaddr[11:0]; // @[TLB.scala:414:52, :658:82] wire [39:0] pma_checker_mpu_physaddr = {pma_checker_mpu_ppn, pma_checker__mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}] wire [39:0] pma_checker__homogeneous_T = pma_checker_mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] pma_checker__homogeneous_T_67 = pma_checker_mpu_physaddr; // @[TLB.scala:414:25] wire [39:0] pma_checker__deny_access_to_debug_T_1 = pma_checker_mpu_physaddr; // @[TLB.scala:414:25] wire [2:0] pma_checker__mpu_priv_T_2 = {1'h0, pma_checker_io_req_bits_prv}; // @[TLB.scala:415:103] wire pma_checker_cacheable; // @[TLB.scala:425:41] wire pma_checker_newEntry_c = pma_checker_cacheable; // @[TLB.scala:425:41, :449:24] wire [40:0] pma_checker__homogeneous_T_1 = {1'h0, pma_checker__homogeneous_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_2 = pma_checker__homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_3 = pma_checker__homogeneous_T_2; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_4 = pma_checker__homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_50 = pma_checker__homogeneous_T_4; // @[TLBPermissions.scala:101:65] wire [39:0] _GEN = {pma_checker_mpu_physaddr[39:14], pma_checker_mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25] wire [39:0] pma_checker__homogeneous_T_5; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_5 = _GEN; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_72; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_72 = _GEN; // @[Parameters.scala:137:31] wire [40:0] pma_checker__homogeneous_T_6 = {1'h0, pma_checker__homogeneous_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_7 = pma_checker__homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_8 = pma_checker__homogeneous_T_7; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_9 = pma_checker__homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_0 = {pma_checker_mpu_physaddr[39:17], pma_checker_mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25] wire [39:0] pma_checker__homogeneous_T_10; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_10 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_60; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_60 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_77; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_77 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_109; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_109 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_116; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_116 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] pma_checker__homogeneous_T_11 = {1'h0, pma_checker__homogeneous_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_12 = pma_checker__homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_13 = pma_checker__homogeneous_T_12; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_14 = pma_checker__homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] pma_checker__homogeneous_T_15 = {pma_checker_mpu_physaddr[39:21], pma_checker_mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25] wire [40:0] pma_checker__homogeneous_T_16 = {1'h0, pma_checker__homogeneous_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_17 = pma_checker__homogeneous_T_16 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_18 = pma_checker__homogeneous_T_17; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_19 = pma_checker__homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] pma_checker__homogeneous_T_20 = {pma_checker_mpu_physaddr[39:26], pma_checker_mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25] wire [40:0] pma_checker__homogeneous_T_21 = {1'h0, pma_checker__homogeneous_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_22 = pma_checker__homogeneous_T_21 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_23 = pma_checker__homogeneous_T_22; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_24 = pma_checker__homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] pma_checker__homogeneous_T_25 = {pma_checker_mpu_physaddr[39:26], pma_checker_mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25] wire [40:0] pma_checker__homogeneous_T_26 = {1'h0, pma_checker__homogeneous_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_27 = pma_checker__homogeneous_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_28 = pma_checker__homogeneous_T_27; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_29 = pma_checker__homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_1 = {pma_checker_mpu_physaddr[39:28], pma_checker_mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25] wire [39:0] pma_checker__homogeneous_T_30; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_30 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_82; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_82 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_97; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_97 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] pma_checker__homogeneous_T_31 = {1'h0, pma_checker__homogeneous_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_32 = pma_checker__homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_33 = pma_checker__homogeneous_T_32; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_34 = pma_checker__homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] pma_checker__homogeneous_T_35 = {pma_checker_mpu_physaddr[39:28], pma_checker_mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25] wire [40:0] pma_checker__homogeneous_T_36 = {1'h0, pma_checker__homogeneous_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_37 = pma_checker__homogeneous_T_36 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_38 = pma_checker__homogeneous_T_37; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_39 = pma_checker__homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] pma_checker__homogeneous_T_40 = {pma_checker_mpu_physaddr[39:29], pma_checker_mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25] wire [40:0] pma_checker__homogeneous_T_41 = {1'h0, pma_checker__homogeneous_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_42 = pma_checker__homogeneous_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_43 = pma_checker__homogeneous_T_42; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_44 = pma_checker__homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_2 = {pma_checker_mpu_physaddr[39:32], pma_checker_mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15] wire [39:0] pma_checker__homogeneous_T_45; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_45 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_87; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_87 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] pma_checker__homogeneous_T_102; // @[Parameters.scala:137:31] assign pma_checker__homogeneous_T_102 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] pma_checker__homogeneous_T_46 = {1'h0, pma_checker__homogeneous_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_47 = pma_checker__homogeneous_T_46 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_48 = pma_checker__homogeneous_T_47; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_49 = pma_checker__homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_51 = pma_checker__homogeneous_T_50 \| pma_checker__homogeneous_T_9; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_52 = pma_checker__homogeneous_T_51 \| pma_checker__homogeneous_T_14; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_53 = pma_checker__homogeneous_T_52 \| pma_checker__homogeneous_T_19; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_54 = pma_checker__homogeneous_T_53 \| pma_checker__homogeneous_T_24; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_55 = pma_checker__homogeneous_T_54 \| pma_checker__homogeneous_T_29; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_56 = pma_checker__homogeneous_T_55 \| pma_checker__homogeneous_T_34; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_57 = pma_checker__homogeneous_T_56 \| pma_checker__homogeneous_T_39; // @[TLBPermissions.scala:101:65] wire pma_checker__homogeneous_T_58 = pma_checker__homogeneous_T_57 \| pma_checker__homogeneous_T_44; // @[TLBPermissions.scala:101:65] wire pma_checker_homogeneous = pma_checker__homogeneous_T_58 \| pma_checker__homogeneous_T_49; // @[TLBPermissions.scala:101:65] wire [40:0] pma_checker__homogeneous_T_61 = {1'h0, pma_checker__homogeneous_T_60}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_62 = pma_checker__homogeneous_T_61 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_63 = pma_checker__homogeneous_T_62; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_64 = pma_checker__homogeneous_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_65 = pma_checker__homogeneous_T_64; // @[TLBPermissions.scala:87:66] wire pma_checker__homogeneous_T_66 = ~pma_checker__homogeneous_T_65; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] pma_checker__homogeneous_T_68 = {1'h0, pma_checker__homogeneous_T_67}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_69 = pma_checker__homogeneous_T_68 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_70 = pma_checker__homogeneous_T_69; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_71 = pma_checker__homogeneous_T_70 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_92 = pma_checker__homogeneous_T_71; // @[TLBPermissions.scala:85:66] wire [40:0] pma_checker__homogeneous_T_73 = {1'h0, pma_checker__homogeneous_T_72}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_74 = pma_checker__homogeneous_T_73 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_75 = pma_checker__homogeneous_T_74; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_76 = pma_checker__homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] pma_checker__homogeneous_T_78 = {1'h0, pma_checker__homogeneous_T_77}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_79 = pma_checker__homogeneous_T_78 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_80 = pma_checker__homogeneous_T_79; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_81 = pma_checker__homogeneous_T_80 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] pma_checker__homogeneous_T_83 = {1'h0, pma_checker__homogeneous_T_82}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_84 = pma_checker__homogeneous_T_83 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_85 = pma_checker__homogeneous_T_84; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_86 = pma_checker__homogeneous_T_85 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] pma_checker__homogeneous_T_88 = {1'h0, pma_checker__homogeneous_T_87}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_89 = pma_checker__homogeneous_T_88 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_90 = pma_checker__homogeneous_T_89; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_91 = pma_checker__homogeneous_T_90 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_93 = pma_checker__homogeneous_T_92 \| pma_checker__homogeneous_T_76; // @[TLBPermissions.scala:85:66] wire pma_checker__homogeneous_T_94 = pma_checker__homogeneous_T_93 \| pma_checker__homogeneous_T_81; // @[TLBPermissions.scala:85:66] wire pma_checker__homogeneous_T_95 = pma_checker__homogeneous_T_94 \| pma_checker__homogeneous_T_86; // @[TLBPermissions.scala:85:66] wire pma_checker__homogeneous_T_96 = pma_checker__homogeneous_T_95 \| pma_checker__homogeneous_T_91; // @[TLBPermissions.scala:85:66] wire [40:0] pma_checker__homogeneous_T_98 = {1'h0, pma_checker__homogeneous_T_97}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_99 = pma_checker__homogeneous_T_98 & 41'h8E000000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_100 = pma_checker__homogeneous_T_99; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_101 = pma_checker__homogeneous_T_100 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_107 = pma_checker__homogeneous_T_101; // @[TLBPermissions.scala:85:66] wire [40:0] pma_checker__homogeneous_T_103 = {1'h0, pma_checker__homogeneous_T_102}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_104 = pma_checker__homogeneous_T_103 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_105 = pma_checker__homogeneous_T_104; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_106 = pma_checker__homogeneous_T_105 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_108 = pma_checker__homogeneous_T_107 \| pma_checker__homogeneous_T_106; // @[TLBPermissions.scala:85:66] wire [40:0] pma_checker__homogeneous_T_110 = {1'h0, pma_checker__homogeneous_T_109}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_111 = pma_checker__homogeneous_T_110 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_112 = pma_checker__homogeneous_T_111; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_113 = pma_checker__homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_114 = pma_checker__homogeneous_T_113; // @[TLBPermissions.scala:87:66] wire pma_checker__homogeneous_T_115 = ~pma_checker__homogeneous_T_114; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] pma_checker__homogeneous_T_117 = {1'h0, pma_checker__homogeneous_T_116}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__homogeneous_T_118 = pma_checker__homogeneous_T_117 & 41'h8A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__homogeneous_T_119 = pma_checker__homogeneous_T_118; // @[Parameters.scala:137:46] wire pma_checker__homogeneous_T_120 = pma_checker__homogeneous_T_119 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker__homogeneous_T_121 = pma_checker__homogeneous_T_120; // @[TLBPermissions.scala:87:66] wire pma_checker__homogeneous_T_122 = ~pma_checker__homogeneous_T_121; // @[TLBPermissions.scala:87:{22,66}] wire [40:0] pma_checker__deny_access_to_debug_T_2 = {1'h0, pma_checker__deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] pma_checker__deny_access_to_debug_T_3 = pma_checker__deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] pma_checker__deny_access_to_debug_T_4 = pma_checker__deny_access_to_debug_T_3; // @[Parameters.scala:137:46] wire pma_checker__deny_access_to_debug_T_5 = pma_checker__deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire pma_checker_deny_access_to_debug = pma_checker__deny_access_to_debug_T_5; // @[TLB.scala:428:50] wire pma_checker__prot_r_T = ~pma_checker_deny_access_to_debug; // @[TLB.scala:428:50, :429:33] wire pma_checker__prot_r_T_1 = _pma_checker_pma_io_resp_r & pma_checker__prot_r_T; // @[TLB.scala:422:19, :429:{30,33}] wire pma_checker__prot_w_T = ~pma_checker_deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33] wire pma_checker__prot_w_T_1 = _pma_checker_pma_io_resp_w & pma_checker__prot_w_T; // @[TLB.scala:422:19, :430:{30,33}] wire pma_checker__prot_x_T = ~pma_checker_deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33] wire pma_checker__prot_x_T_1 = _pma_checker_pma_io_resp_x & pma_checker__prot_x_T; // @[TLB.scala:422:19, :434:{30,33}] wire [24:0] pma_checker__sector_hits_T_4 = pma_checker__sector_hits_T_3[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_5 = pma_checker__sector_hits_T_4 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_7 = pma_checker__sector_hits_T_5 & pma_checker__sector_hits_T_6; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_12 = pma_checker__sector_hits_T_11[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_13 = pma_checker__sector_hits_T_12 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_15 = pma_checker__sector_hits_T_13 & pma_checker__sector_hits_T_14; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_20 = pma_checker__sector_hits_T_19[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_21 = pma_checker__sector_hits_T_20 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_23 = pma_checker__sector_hits_T_21 & pma_checker__sector_hits_T_22; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_28 = pma_checker__sector_hits_T_27[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_29 = pma_checker__sector_hits_T_28 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_31 = pma_checker__sector_hits_T_29 & pma_checker__sector_hits_T_30; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_36 = pma_checker__sector_hits_T_35[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_37 = pma_checker__sector_hits_T_36 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_39 = pma_checker__sector_hits_T_37 & pma_checker__sector_hits_T_38; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_44 = pma_checker__sector_hits_T_43[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_45 = pma_checker__sector_hits_T_44 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_47 = pma_checker__sector_hits_T_45 & pma_checker__sector_hits_T_46; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_52 = pma_checker__sector_hits_T_51[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_53 = pma_checker__sector_hits_T_52 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_55 = pma_checker__sector_hits_T_53 & pma_checker__sector_hits_T_54; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__sector_hits_T_60 = pma_checker__sector_hits_T_59[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__sector_hits_T_61 = pma_checker__sector_hits_T_60 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__sector_hits_T_63 = pma_checker__sector_hits_T_61 & pma_checker__sector_hits_T_62; // @[TLB.scala:174:{86,95,105}] wire [8:0] pma_checker__superpage_hits_T_1 = pma_checker__superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_2 = pma_checker__superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_3 = pma_checker__superpage_hits_T_2; // @[TLB.scala:183:{40,79}] wire pma_checker_superpage_hits_ignore_1 = pma_checker__superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__superpage_hits_T_6 = pma_checker__superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_7 = pma_checker__superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_8 = pma_checker_superpage_hits_ignore_1 \| pma_checker__superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__superpage_hits_T_11 = pma_checker__superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_12 = pma_checker__superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__superpage_hits_T_15 = pma_checker__superpage_hits_T_14[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_16 = pma_checker__superpage_hits_T_15 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_17 = pma_checker__superpage_hits_T_16; // @[TLB.scala:183:{40,79}] wire pma_checker_superpage_hits_ignore_4 = pma_checker__superpage_hits_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__superpage_hits_T_20 = pma_checker__superpage_hits_T_19[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_21 = pma_checker__superpage_hits_T_20 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_22 = pma_checker_superpage_hits_ignore_4 \| pma_checker__superpage_hits_T_21; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__superpage_hits_T_25 = pma_checker__superpage_hits_T_24[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_26 = pma_checker__superpage_hits_T_25 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__superpage_hits_T_29 = pma_checker__superpage_hits_T_28[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_30 = pma_checker__superpage_hits_T_29 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_31 = pma_checker__superpage_hits_T_30; // @[TLB.scala:183:{40,79}] wire pma_checker_superpage_hits_ignore_7 = pma_checker__superpage_hits_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__superpage_hits_T_34 = pma_checker__superpage_hits_T_33[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_35 = pma_checker__superpage_hits_T_34 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_36 = pma_checker_superpage_hits_ignore_7 \| pma_checker__superpage_hits_T_35; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__superpage_hits_T_39 = pma_checker__superpage_hits_T_38[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_40 = pma_checker__superpage_hits_T_39 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__superpage_hits_T_43 = pma_checker__superpage_hits_T_42[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_44 = pma_checker__superpage_hits_T_43 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_45 = pma_checker__superpage_hits_T_44; // @[TLB.scala:183:{40,79}] wire pma_checker_superpage_hits_ignore_10 = pma_checker__superpage_hits_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__superpage_hits_T_48 = pma_checker__superpage_hits_T_47[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_49 = pma_checker__superpage_hits_T_48 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__superpage_hits_T_50 = pma_checker_superpage_hits_ignore_10 \| pma_checker__superpage_hits_T_49; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__superpage_hits_T_53 = pma_checker__superpage_hits_T_52[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__superpage_hits_T_54 = pma_checker__superpage_hits_T_53 == 9'h0; // @[TLB.scala:183:{58,79}] wire [1:0] pma_checker_hitsVec_idx = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_1 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_2 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_3 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_4 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_5 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_6 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker_hitsVec_idx_7 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_24 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_48 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_72 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_96 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_120 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_144 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [1:0] pma_checker__entries_T_168 = pma_checker_vpn[1:0]; // @[package.scala:163:13] wire [24:0] pma_checker__hitsVec_T_1 = pma_checker__hitsVec_T[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_2 = pma_checker__hitsVec_T_1 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_4 = pma_checker__hitsVec_T_2 & pma_checker__hitsVec_T_3; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_7 = pma_checker__hitsVec_T_6[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_8 = pma_checker__hitsVec_T_7 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_10 = pma_checker__hitsVec_T_8 & pma_checker__hitsVec_T_9; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_13 = pma_checker__hitsVec_T_12[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_14 = pma_checker__hitsVec_T_13 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_16 = pma_checker__hitsVec_T_14 & pma_checker__hitsVec_T_15; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_19 = pma_checker__hitsVec_T_18[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_20 = pma_checker__hitsVec_T_19 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_22 = pma_checker__hitsVec_T_20 & pma_checker__hitsVec_T_21; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_25 = pma_checker__hitsVec_T_24[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_26 = pma_checker__hitsVec_T_25 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_28 = pma_checker__hitsVec_T_26 & pma_checker__hitsVec_T_27; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_31 = pma_checker__hitsVec_T_30[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_32 = pma_checker__hitsVec_T_31 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_34 = pma_checker__hitsVec_T_32 & pma_checker__hitsVec_T_33; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_37 = pma_checker__hitsVec_T_36[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_38 = pma_checker__hitsVec_T_37 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_40 = pma_checker__hitsVec_T_38 & pma_checker__hitsVec_T_39; // @[TLB.scala:174:{86,95,105}] wire [24:0] pma_checker__hitsVec_T_43 = pma_checker__hitsVec_T_42[26:2]; // @[TLB.scala:174:{61,68}] wire pma_checker__hitsVec_T_44 = pma_checker__hitsVec_T_43 == 25'h0; // @[TLB.scala:174:{68,86}] wire pma_checker__hitsVec_T_46 = pma_checker__hitsVec_T_44 & pma_checker__hitsVec_T_45; // @[TLB.scala:174:{86,95,105}] wire [8:0] pma_checker__hitsVec_T_49 = pma_checker__hitsVec_T_48[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_50 = pma_checker__hitsVec_T_49 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_51 = pma_checker__hitsVec_T_50; // @[TLB.scala:183:{40,79}] wire pma_checker_hitsVec_ignore_1 = pma_checker__hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__hitsVec_T_54 = pma_checker__hitsVec_T_53[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_55 = pma_checker__hitsVec_T_54 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_56 = pma_checker_hitsVec_ignore_1 \| pma_checker__hitsVec_T_55; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__hitsVec_T_59 = pma_checker__hitsVec_T_58[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_60 = pma_checker__hitsVec_T_59 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__hitsVec_T_64 = pma_checker__hitsVec_T_63[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_65 = pma_checker__hitsVec_T_64 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_66 = pma_checker__hitsVec_T_65; // @[TLB.scala:183:{40,79}] wire pma_checker_hitsVec_ignore_4 = pma_checker__hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__hitsVec_T_69 = pma_checker__hitsVec_T_68[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_70 = pma_checker__hitsVec_T_69 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_71 = pma_checker_hitsVec_ignore_4 \| pma_checker__hitsVec_T_70; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__hitsVec_T_74 = pma_checker__hitsVec_T_73[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_75 = pma_checker__hitsVec_T_74 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__hitsVec_T_79 = pma_checker__hitsVec_T_78[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_80 = pma_checker__hitsVec_T_79 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_81 = pma_checker__hitsVec_T_80; // @[TLB.scala:183:{40,79}] wire pma_checker_hitsVec_ignore_7 = pma_checker__hitsVec_ignore_T_7; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__hitsVec_T_84 = pma_checker__hitsVec_T_83[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_85 = pma_checker__hitsVec_T_84 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_86 = pma_checker_hitsVec_ignore_7 \| pma_checker__hitsVec_T_85; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__hitsVec_T_89 = pma_checker__hitsVec_T_88[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_90 = pma_checker__hitsVec_T_89 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__hitsVec_T_94 = pma_checker__hitsVec_T_93[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_95 = pma_checker__hitsVec_T_94 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_96 = pma_checker__hitsVec_T_95; // @[TLB.scala:183:{40,79}] wire pma_checker_hitsVec_ignore_10 = pma_checker__hitsVec_ignore_T_10; // @[TLB.scala:182:{28,34}] wire [8:0] pma_checker__hitsVec_T_99 = pma_checker__hitsVec_T_98[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_100 = pma_checker__hitsVec_T_99 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_101 = pma_checker_hitsVec_ignore_10 \| pma_checker__hitsVec_T_100; // @[TLB.scala:182:34, :183:{40,79}] wire [8:0] pma_checker__hitsVec_T_104 = pma_checker__hitsVec_T_103[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_105 = pma_checker__hitsVec_T_104 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__hitsVec_T_109 = pma_checker__hitsVec_T_108[26:18]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_110 = pma_checker__hitsVec_T_109 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker__hitsVec_T_111 = pma_checker__hitsVec_T_110; // @[TLB.scala:183:{40,79}] wire [8:0] pma_checker__hitsVec_T_114 = pma_checker__hitsVec_T_113[17:9]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_115 = pma_checker__hitsVec_T_114 == 9'h0; // @[TLB.scala:183:{58,79}] wire [8:0] pma_checker__hitsVec_T_119 = pma_checker__hitsVec_T_118[8:0]; // @[TLB.scala:183:{52,58}] wire pma_checker__hitsVec_T_120 = pma_checker__hitsVec_T_119 == 9'h0; // @[TLB.scala:183:{58,79}] wire pma_checker_newEntry_ppp; // @[TLB.scala:449:24] wire pma_checker_newEntry_pal; // @[TLB.scala:449:24] wire pma_checker_newEntry_paa; // @[TLB.scala:449:24] wire pma_checker_newEntry_eff; // @[TLB.scala:449:24] wire [1:0] _GEN_3 = {pma_checker_newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24] wire [1:0] pma_checker_special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_special_entry_data_0_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_0_data_0_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_1_data_0_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_2_data_0_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_3_data_0_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_0_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_1_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_2_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_3_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_4_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_5_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_6_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_lo_lo_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_7_data_lo_lo_lo = _GEN_3; // @[TLB.scala:217:24] wire [1:0] _GEN_4 = {pma_checker_newEntry_pal, pma_checker_newEntry_paa}; // @[TLB.scala:217:24, :449:24] wire [1:0] pma_checker_special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_special_entry_data_0_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_1_data_0_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_2_data_0_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_superpage_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_3_data_0_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_0_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_0_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_1_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_1_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_2_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_2_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_3_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_3_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_4_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_4_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_5_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_5_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_6_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_6_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [1:0] pma_checker_sectored_entries_0_7_data_lo_lo_hi_hi; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_7_data_lo_lo_hi_hi = _GEN_4; // @[TLB.scala:217:24] wire [2:0] pma_checker_special_entry_data_0_lo_lo_hi = {pma_checker_special_entry_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_special_entry_data_0_lo_lo = {pma_checker_special_entry_data_0_lo_lo_hi, pma_checker_special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [2:0] _GEN_5 = {2'h0, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24] wire [2:0] pma_checker_special_entry_data_0_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_special_entry_data_0_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_0_data_0_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_1_data_0_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_2_data_0_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_superpage_entries_3_data_0_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_0_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_1_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_2_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_3_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_4_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_5_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_6_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_lo_hi_lo; // @[TLB.scala:217:24] assign pma_checker_sectored_entries_0_7_data_lo_hi_lo = _GEN_5; // @[TLB.scala:217:24] wire [5:0] pma_checker_special_entry_data_0_lo_hi = {3'h0, pma_checker_special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_special_entry_data_0_lo = {pma_checker_special_entry_data_0_lo_hi, pma_checker_special_entry_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__special_entry_data_0_T = {31'h0, pma_checker_special_entry_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_0_data_0_lo_lo_hi = {pma_checker_superpage_entries_0_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_superpage_entries_0_data_0_lo_lo = {pma_checker_superpage_entries_0_data_0_lo_lo_hi, pma_checker_superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_0_data_0_lo_hi = {3'h0, pma_checker_superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_superpage_entries_0_data_0_lo = {pma_checker_superpage_entries_0_data_0_lo_hi, pma_checker_superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__superpage_entries_0_data_0_T = {31'h0, pma_checker_superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_1_data_0_lo_lo_hi = {pma_checker_superpage_entries_1_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_superpage_entries_1_data_0_lo_lo = {pma_checker_superpage_entries_1_data_0_lo_lo_hi, pma_checker_superpage_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_1_data_0_lo_hi = {3'h0, pma_checker_superpage_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_superpage_entries_1_data_0_lo = {pma_checker_superpage_entries_1_data_0_lo_hi, pma_checker_superpage_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__superpage_entries_1_data_0_T = {31'h0, pma_checker_superpage_entries_1_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_2_data_0_lo_lo_hi = {pma_checker_superpage_entries_2_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_superpage_entries_2_data_0_lo_lo = {pma_checker_superpage_entries_2_data_0_lo_lo_hi, pma_checker_superpage_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_2_data_0_lo_hi = {3'h0, pma_checker_superpage_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_superpage_entries_2_data_0_lo = {pma_checker_superpage_entries_2_data_0_lo_hi, pma_checker_superpage_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__superpage_entries_2_data_0_T = {31'h0, pma_checker_superpage_entries_2_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_superpage_entries_3_data_0_lo_lo_hi = {pma_checker_superpage_entries_3_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_superpage_entries_3_data_0_lo_lo = {pma_checker_superpage_entries_3_data_0_lo_lo_hi, pma_checker_superpage_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_superpage_entries_3_data_0_lo_hi = {3'h0, pma_checker_superpage_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_superpage_entries_3_data_0_lo = {pma_checker_superpage_entries_3_data_0_lo_hi, pma_checker_superpage_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__superpage_entries_3_data_0_T = {31'h0, pma_checker_superpage_entries_3_data_0_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_0_data_lo_lo_hi = {pma_checker_sectored_entries_0_0_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_0_data_lo_lo = {pma_checker_sectored_entries_0_0_data_lo_lo_hi, pma_checker_sectored_entries_0_0_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_0_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_0_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_0_data_lo = {pma_checker_sectored_entries_0_0_data_lo_hi, pma_checker_sectored_entries_0_0_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_0_data_T = {31'h0, pma_checker_sectored_entries_0_0_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_1_data_lo_lo_hi = {pma_checker_sectored_entries_0_1_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_1_data_lo_lo = {pma_checker_sectored_entries_0_1_data_lo_lo_hi, pma_checker_sectored_entries_0_1_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_1_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_1_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_1_data_lo = {pma_checker_sectored_entries_0_1_data_lo_hi, pma_checker_sectored_entries_0_1_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_1_data_T = {31'h0, pma_checker_sectored_entries_0_1_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_2_data_lo_lo_hi = {pma_checker_sectored_entries_0_2_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_2_data_lo_lo = {pma_checker_sectored_entries_0_2_data_lo_lo_hi, pma_checker_sectored_entries_0_2_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_2_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_2_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_2_data_lo = {pma_checker_sectored_entries_0_2_data_lo_hi, pma_checker_sectored_entries_0_2_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_2_data_T = {31'h0, pma_checker_sectored_entries_0_2_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_3_data_lo_lo_hi = {pma_checker_sectored_entries_0_3_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_3_data_lo_lo = {pma_checker_sectored_entries_0_3_data_lo_lo_hi, pma_checker_sectored_entries_0_3_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_3_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_3_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_3_data_lo = {pma_checker_sectored_entries_0_3_data_lo_hi, pma_checker_sectored_entries_0_3_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_3_data_T = {31'h0, pma_checker_sectored_entries_0_3_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_4_data_lo_lo_hi = {pma_checker_sectored_entries_0_4_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_4_data_lo_lo = {pma_checker_sectored_entries_0_4_data_lo_lo_hi, pma_checker_sectored_entries_0_4_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_4_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_4_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_4_data_lo = {pma_checker_sectored_entries_0_4_data_lo_hi, pma_checker_sectored_entries_0_4_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_4_data_T = {31'h0, pma_checker_sectored_entries_0_4_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_5_data_lo_lo_hi = {pma_checker_sectored_entries_0_5_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_5_data_lo_lo = {pma_checker_sectored_entries_0_5_data_lo_lo_hi, pma_checker_sectored_entries_0_5_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_5_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_5_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_5_data_lo = {pma_checker_sectored_entries_0_5_data_lo_hi, pma_checker_sectored_entries_0_5_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_5_data_T = {31'h0, pma_checker_sectored_entries_0_5_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_6_data_lo_lo_hi = {pma_checker_sectored_entries_0_6_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_6_data_lo_lo = {pma_checker_sectored_entries_0_6_data_lo_lo_hi, pma_checker_sectored_entries_0_6_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_6_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_6_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_6_data_lo = {pma_checker_sectored_entries_0_6_data_lo_hi, pma_checker_sectored_entries_0_6_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_6_data_T = {31'h0, pma_checker_sectored_entries_0_6_data_lo}; // @[TLB.scala:217:24] wire [2:0] pma_checker_sectored_entries_0_7_data_lo_lo_hi = {pma_checker_sectored_entries_0_7_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24] wire [4:0] pma_checker_sectored_entries_0_7_data_lo_lo = {pma_checker_sectored_entries_0_7_data_lo_lo_hi, pma_checker_sectored_entries_0_7_data_lo_lo_lo}; // @[TLB.scala:217:24] wire [5:0] pma_checker_sectored_entries_0_7_data_lo_hi = {3'h0, pma_checker_sectored_entries_0_7_data_lo_hi_lo}; // @[TLB.scala:217:24] wire [10:0] pma_checker_sectored_entries_0_7_data_lo = {pma_checker_sectored_entries_0_7_data_lo_hi, pma_checker_sectored_entries_0_7_data_lo_lo}; // @[TLB.scala:217:24] wire [41:0] pma_checker__sectored_entries_0_7_data_T = {31'h0, pma_checker_sectored_entries_0_7_data_lo}; // @[TLB.scala:217:24] wire [19:0] pma_checker__entries_T_23; // @[TLB.scala:170:77] wire pma_checker__entries_T_22; // @[TLB.scala:170:77] wire pma_checker__entries_T_21; // @[TLB.scala:170:77] wire pma_checker__entries_T_20; // @[TLB.scala:170:77] wire pma_checker__entries_T_19; // @[TLB.scala:170:77] wire pma_checker__entries_T_18; // @[TLB.scala:170:77] wire pma_checker__entries_T_17; // @[TLB.scala:170:77] wire pma_checker__entries_T_16; // @[TLB.scala:170:77] wire pma_checker__entries_T_15; // @[TLB.scala:170:77] wire pma_checker__entries_T_14; // @[TLB.scala:170:77] wire pma_checker__entries_T_13; // @[TLB.scala:170:77] wire pma_checker__entries_T_12; // @[TLB.scala:170:77] wire pma_checker__entries_T_11; // @[TLB.scala:170:77] wire pma_checker__entries_T_10; // @[TLB.scala:170:77] wire pma_checker__entries_T_9; // @[TLB.scala:170:77] wire pma_checker__entries_T_8; // @[TLB.scala:170:77] wire pma_checker__entries_T_7; // @[TLB.scala:170:77] wire pma_checker__entries_T_6; // @[TLB.scala:170:77] wire pma_checker__entries_T_5; // @[TLB.scala:170:77] wire pma_checker__entries_T_4; // @[TLB.scala:170:77] wire pma_checker__entries_T_3; // @[TLB.scala:170:77] wire pma_checker__entries_T_2; // @[TLB.scala:170:77] wire pma_checker__entries_T_1; // @[TLB.scala:170:77] assign pma_checker__entries_T_1 = pma_checker__entries_WIRE_1[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_fragmented_superpage = pma_checker__entries_T_1; // @[TLB.scala:170:77] assign pma_checker__entries_T_2 = pma_checker__entries_WIRE_1[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_c = pma_checker__entries_T_2; // @[TLB.scala:170:77] assign pma_checker__entries_T_3 = pma_checker__entries_WIRE_1[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_eff = pma_checker__entries_T_3; // @[TLB.scala:170:77] assign pma_checker__entries_T_4 = pma_checker__entries_WIRE_1[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_paa = pma_checker__entries_T_4; // @[TLB.scala:170:77] assign pma_checker__entries_T_5 = pma_checker__entries_WIRE_1[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_pal = pma_checker__entries_T_5; // @[TLB.scala:170:77] assign pma_checker__entries_T_6 = pma_checker__entries_WIRE_1[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_ppp = pma_checker__entries_T_6; // @[TLB.scala:170:77] assign pma_checker__entries_T_7 = pma_checker__entries_WIRE_1[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_pr = pma_checker__entries_T_7; // @[TLB.scala:170:77] assign pma_checker__entries_T_8 = pma_checker__entries_WIRE_1[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_px = pma_checker__entries_T_8; // @[TLB.scala:170:77] assign pma_checker__entries_T_9 = pma_checker__entries_WIRE_1[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_pw = pma_checker__entries_T_9; // @[TLB.scala:170:77] assign pma_checker__entries_T_10 = pma_checker__entries_WIRE_1[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_hr = pma_checker__entries_T_10; // @[TLB.scala:170:77] assign pma_checker__entries_T_11 = pma_checker__entries_WIRE_1[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_hx = pma_checker__entries_T_11; // @[TLB.scala:170:77] assign pma_checker__entries_T_12 = pma_checker__entries_WIRE_1[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_hw = pma_checker__entries_T_12; // @[TLB.scala:170:77] assign pma_checker__entries_T_13 = pma_checker__entries_WIRE_1[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_sr = pma_checker__entries_T_13; // @[TLB.scala:170:77] assign pma_checker__entries_T_14 = pma_checker__entries_WIRE_1[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_sx = pma_checker__entries_T_14; // @[TLB.scala:170:77] assign pma_checker__entries_T_15 = pma_checker__entries_WIRE_1[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_sw = pma_checker__entries_T_15; // @[TLB.scala:170:77] assign pma_checker__entries_T_16 = pma_checker__entries_WIRE_1[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_gf = pma_checker__entries_T_16; // @[TLB.scala:170:77] assign pma_checker__entries_T_17 = pma_checker__entries_WIRE_1[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_pf = pma_checker__entries_T_17; // @[TLB.scala:170:77] assign pma_checker__entries_T_18 = pma_checker__entries_WIRE_1[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_ae_stage2 = pma_checker__entries_T_18; // @[TLB.scala:170:77] assign pma_checker__entries_T_19 = pma_checker__entries_WIRE_1[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_ae_final = pma_checker__entries_T_19; // @[TLB.scala:170:77] assign pma_checker__entries_T_20 = pma_checker__entries_WIRE_1[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_ae_ptw = pma_checker__entries_T_20; // @[TLB.scala:170:77] assign pma_checker__entries_T_21 = pma_checker__entries_WIRE_1[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_g = pma_checker__entries_T_21; // @[TLB.scala:170:77] assign pma_checker__entries_T_22 = pma_checker__entries_WIRE_1[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_u = pma_checker__entries_T_22; // @[TLB.scala:170:77] assign pma_checker__entries_T_23 = pma_checker__entries_WIRE_1[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_ppn = pma_checker__entries_T_23; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_47; // @[TLB.scala:170:77] wire pma_checker__entries_T_46; // @[TLB.scala:170:77] wire pma_checker__entries_T_45; // @[TLB.scala:170:77] wire pma_checker__entries_T_44; // @[TLB.scala:170:77] wire pma_checker__entries_T_43; // @[TLB.scala:170:77] wire pma_checker__entries_T_42; // @[TLB.scala:170:77] wire pma_checker__entries_T_41; // @[TLB.scala:170:77] wire pma_checker__entries_T_40; // @[TLB.scala:170:77] wire pma_checker__entries_T_39; // @[TLB.scala:170:77] wire pma_checker__entries_T_38; // @[TLB.scala:170:77] wire pma_checker__entries_T_37; // @[TLB.scala:170:77] wire pma_checker__entries_T_36; // @[TLB.scala:170:77] wire pma_checker__entries_T_35; // @[TLB.scala:170:77] wire pma_checker__entries_T_34; // @[TLB.scala:170:77] wire pma_checker__entries_T_33; // @[TLB.scala:170:77] wire pma_checker__entries_T_32; // @[TLB.scala:170:77] wire pma_checker__entries_T_31; // @[TLB.scala:170:77] wire pma_checker__entries_T_30; // @[TLB.scala:170:77] wire pma_checker__entries_T_29; // @[TLB.scala:170:77] wire pma_checker__entries_T_28; // @[TLB.scala:170:77] wire pma_checker__entries_T_27; // @[TLB.scala:170:77] wire pma_checker__entries_T_26; // @[TLB.scala:170:77] wire pma_checker__entries_T_25; // @[TLB.scala:170:77] assign pma_checker__entries_T_25 = pma_checker__entries_WIRE_3[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_fragmented_superpage = pma_checker__entries_T_25; // @[TLB.scala:170:77] assign pma_checker__entries_T_26 = pma_checker__entries_WIRE_3[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_c = pma_checker__entries_T_26; // @[TLB.scala:170:77] assign pma_checker__entries_T_27 = pma_checker__entries_WIRE_3[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_eff = pma_checker__entries_T_27; // @[TLB.scala:170:77] assign pma_checker__entries_T_28 = pma_checker__entries_WIRE_3[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_paa = pma_checker__entries_T_28; // @[TLB.scala:170:77] assign pma_checker__entries_T_29 = pma_checker__entries_WIRE_3[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_pal = pma_checker__entries_T_29; // @[TLB.scala:170:77] assign pma_checker__entries_T_30 = pma_checker__entries_WIRE_3[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_ppp = pma_checker__entries_T_30; // @[TLB.scala:170:77] assign pma_checker__entries_T_31 = pma_checker__entries_WIRE_3[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_pr = pma_checker__entries_T_31; // @[TLB.scala:170:77] assign pma_checker__entries_T_32 = pma_checker__entries_WIRE_3[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_px = pma_checker__entries_T_32; // @[TLB.scala:170:77] assign pma_checker__entries_T_33 = pma_checker__entries_WIRE_3[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_pw = pma_checker__entries_T_33; // @[TLB.scala:170:77] assign pma_checker__entries_T_34 = pma_checker__entries_WIRE_3[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_hr = pma_checker__entries_T_34; // @[TLB.scala:170:77] assign pma_checker__entries_T_35 = pma_checker__entries_WIRE_3[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_hx = pma_checker__entries_T_35; // @[TLB.scala:170:77] assign pma_checker__entries_T_36 = pma_checker__entries_WIRE_3[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_hw = pma_checker__entries_T_36; // @[TLB.scala:170:77] assign pma_checker__entries_T_37 = pma_checker__entries_WIRE_3[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_sr = pma_checker__entries_T_37; // @[TLB.scala:170:77] assign pma_checker__entries_T_38 = pma_checker__entries_WIRE_3[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_sx = pma_checker__entries_T_38; // @[TLB.scala:170:77] assign pma_checker__entries_T_39 = pma_checker__entries_WIRE_3[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_sw = pma_checker__entries_T_39; // @[TLB.scala:170:77] assign pma_checker__entries_T_40 = pma_checker__entries_WIRE_3[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_gf = pma_checker__entries_T_40; // @[TLB.scala:170:77] assign pma_checker__entries_T_41 = pma_checker__entries_WIRE_3[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_pf = pma_checker__entries_T_41; // @[TLB.scala:170:77] assign pma_checker__entries_T_42 = pma_checker__entries_WIRE_3[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_ae_stage2 = pma_checker__entries_T_42; // @[TLB.scala:170:77] assign pma_checker__entries_T_43 = pma_checker__entries_WIRE_3[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_ae_final = pma_checker__entries_T_43; // @[TLB.scala:170:77] assign pma_checker__entries_T_44 = pma_checker__entries_WIRE_3[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_ae_ptw = pma_checker__entries_T_44; // @[TLB.scala:170:77] assign pma_checker__entries_T_45 = pma_checker__entries_WIRE_3[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_g = pma_checker__entries_T_45; // @[TLB.scala:170:77] assign pma_checker__entries_T_46 = pma_checker__entries_WIRE_3[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_2_u = pma_checker__entries_T_46; // @[TLB.scala:170:77] assign pma_checker__entries_T_47 = pma_checker__entries_WIRE_3[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_2_ppn = pma_checker__entries_T_47; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_71; // @[TLB.scala:170:77] wire pma_checker__entries_T_70; // @[TLB.scala:170:77] wire pma_checker__entries_T_69; // @[TLB.scala:170:77] wire pma_checker__entries_T_68; // @[TLB.scala:170:77] wire pma_checker__entries_T_67; // @[TLB.scala:170:77] wire pma_checker__entries_T_66; // @[TLB.scala:170:77] wire pma_checker__entries_T_65; // @[TLB.scala:170:77] wire pma_checker__entries_T_64; // @[TLB.scala:170:77] wire pma_checker__entries_T_63; // @[TLB.scala:170:77] wire pma_checker__entries_T_62; // @[TLB.scala:170:77] wire pma_checker__entries_T_61; // @[TLB.scala:170:77] wire pma_checker__entries_T_60; // @[TLB.scala:170:77] wire pma_checker__entries_T_59; // @[TLB.scala:170:77] wire pma_checker__entries_T_58; // @[TLB.scala:170:77] wire pma_checker__entries_T_57; // @[TLB.scala:170:77] wire pma_checker__entries_T_56; // @[TLB.scala:170:77] wire pma_checker__entries_T_55; // @[TLB.scala:170:77] wire pma_checker__entries_T_54; // @[TLB.scala:170:77] wire pma_checker__entries_T_53; // @[TLB.scala:170:77] wire pma_checker__entries_T_52; // @[TLB.scala:170:77] wire pma_checker__entries_T_51; // @[TLB.scala:170:77] wire pma_checker__entries_T_50; // @[TLB.scala:170:77] wire pma_checker__entries_T_49; // @[TLB.scala:170:77] assign pma_checker__entries_T_49 = pma_checker__entries_WIRE_5[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_fragmented_superpage = pma_checker__entries_T_49; // @[TLB.scala:170:77] assign pma_checker__entries_T_50 = pma_checker__entries_WIRE_5[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_c = pma_checker__entries_T_50; // @[TLB.scala:170:77] assign pma_checker__entries_T_51 = pma_checker__entries_WIRE_5[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_eff = pma_checker__entries_T_51; // @[TLB.scala:170:77] assign pma_checker__entries_T_52 = pma_checker__entries_WIRE_5[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_paa = pma_checker__entries_T_52; // @[TLB.scala:170:77] assign pma_checker__entries_T_53 = pma_checker__entries_WIRE_5[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_pal = pma_checker__entries_T_53; // @[TLB.scala:170:77] assign pma_checker__entries_T_54 = pma_checker__entries_WIRE_5[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_ppp = pma_checker__entries_T_54; // @[TLB.scala:170:77] assign pma_checker__entries_T_55 = pma_checker__entries_WIRE_5[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_pr = pma_checker__entries_T_55; // @[TLB.scala:170:77] assign pma_checker__entries_T_56 = pma_checker__entries_WIRE_5[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_px = pma_checker__entries_T_56; // @[TLB.scala:170:77] assign pma_checker__entries_T_57 = pma_checker__entries_WIRE_5[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_pw = pma_checker__entries_T_57; // @[TLB.scala:170:77] assign pma_checker__entries_T_58 = pma_checker__entries_WIRE_5[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_hr = pma_checker__entries_T_58; // @[TLB.scala:170:77] assign pma_checker__entries_T_59 = pma_checker__entries_WIRE_5[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_hx = pma_checker__entries_T_59; // @[TLB.scala:170:77] assign pma_checker__entries_T_60 = pma_checker__entries_WIRE_5[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_hw = pma_checker__entries_T_60; // @[TLB.scala:170:77] assign pma_checker__entries_T_61 = pma_checker__entries_WIRE_5[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_sr = pma_checker__entries_T_61; // @[TLB.scala:170:77] assign pma_checker__entries_T_62 = pma_checker__entries_WIRE_5[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_sx = pma_checker__entries_T_62; // @[TLB.scala:170:77] assign pma_checker__entries_T_63 = pma_checker__entries_WIRE_5[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_sw = pma_checker__entries_T_63; // @[TLB.scala:170:77] assign pma_checker__entries_T_64 = pma_checker__entries_WIRE_5[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_gf = pma_checker__entries_T_64; // @[TLB.scala:170:77] assign pma_checker__entries_T_65 = pma_checker__entries_WIRE_5[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_pf = pma_checker__entries_T_65; // @[TLB.scala:170:77] assign pma_checker__entries_T_66 = pma_checker__entries_WIRE_5[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_ae_stage2 = pma_checker__entries_T_66; // @[TLB.scala:170:77] assign pma_checker__entries_T_67 = pma_checker__entries_WIRE_5[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_ae_final = pma_checker__entries_T_67; // @[TLB.scala:170:77] assign pma_checker__entries_T_68 = pma_checker__entries_WIRE_5[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_ae_ptw = pma_checker__entries_T_68; // @[TLB.scala:170:77] assign pma_checker__entries_T_69 = pma_checker__entries_WIRE_5[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_g = pma_checker__entries_T_69; // @[TLB.scala:170:77] assign pma_checker__entries_T_70 = pma_checker__entries_WIRE_5[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_4_u = pma_checker__entries_T_70; // @[TLB.scala:170:77] assign pma_checker__entries_T_71 = pma_checker__entries_WIRE_5[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_4_ppn = pma_checker__entries_T_71; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_95; // @[TLB.scala:170:77] wire pma_checker__entries_T_94; // @[TLB.scala:170:77] wire pma_checker__entries_T_93; // @[TLB.scala:170:77] wire pma_checker__entries_T_92; // @[TLB.scala:170:77] wire pma_checker__entries_T_91; // @[TLB.scala:170:77] wire pma_checker__entries_T_90; // @[TLB.scala:170:77] wire pma_checker__entries_T_89; // @[TLB.scala:170:77] wire pma_checker__entries_T_88; // @[TLB.scala:170:77] wire pma_checker__entries_T_87; // @[TLB.scala:170:77] wire pma_checker__entries_T_86; // @[TLB.scala:170:77] wire pma_checker__entries_T_85; // @[TLB.scala:170:77] wire pma_checker__entries_T_84; // @[TLB.scala:170:77] wire pma_checker__entries_T_83; // @[TLB.scala:170:77] wire pma_checker__entries_T_82; // @[TLB.scala:170:77] wire pma_checker__entries_T_81; // @[TLB.scala:170:77] wire pma_checker__entries_T_80; // @[TLB.scala:170:77] wire pma_checker__entries_T_79; // @[TLB.scala:170:77] wire pma_checker__entries_T_78; // @[TLB.scala:170:77] wire pma_checker__entries_T_77; // @[TLB.scala:170:77] wire pma_checker__entries_T_76; // @[TLB.scala:170:77] wire pma_checker__entries_T_75; // @[TLB.scala:170:77] wire pma_checker__entries_T_74; // @[TLB.scala:170:77] wire pma_checker__entries_T_73; // @[TLB.scala:170:77] assign pma_checker__entries_T_73 = pma_checker__entries_WIRE_7[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_fragmented_superpage = pma_checker__entries_T_73; // @[TLB.scala:170:77] assign pma_checker__entries_T_74 = pma_checker__entries_WIRE_7[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_c = pma_checker__entries_T_74; // @[TLB.scala:170:77] assign pma_checker__entries_T_75 = pma_checker__entries_WIRE_7[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_eff = pma_checker__entries_T_75; // @[TLB.scala:170:77] assign pma_checker__entries_T_76 = pma_checker__entries_WIRE_7[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_paa = pma_checker__entries_T_76; // @[TLB.scala:170:77] assign pma_checker__entries_T_77 = pma_checker__entries_WIRE_7[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_pal = pma_checker__entries_T_77; // @[TLB.scala:170:77] assign pma_checker__entries_T_78 = pma_checker__entries_WIRE_7[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_ppp = pma_checker__entries_T_78; // @[TLB.scala:170:77] assign pma_checker__entries_T_79 = pma_checker__entries_WIRE_7[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_pr = pma_checker__entries_T_79; // @[TLB.scala:170:77] assign pma_checker__entries_T_80 = pma_checker__entries_WIRE_7[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_px = pma_checker__entries_T_80; // @[TLB.scala:170:77] assign pma_checker__entries_T_81 = pma_checker__entries_WIRE_7[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_pw = pma_checker__entries_T_81; // @[TLB.scala:170:77] assign pma_checker__entries_T_82 = pma_checker__entries_WIRE_7[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_hr = pma_checker__entries_T_82; // @[TLB.scala:170:77] assign pma_checker__entries_T_83 = pma_checker__entries_WIRE_7[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_hx = pma_checker__entries_T_83; // @[TLB.scala:170:77] assign pma_checker__entries_T_84 = pma_checker__entries_WIRE_7[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_hw = pma_checker__entries_T_84; // @[TLB.scala:170:77] assign pma_checker__entries_T_85 = pma_checker__entries_WIRE_7[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_sr = pma_checker__entries_T_85; // @[TLB.scala:170:77] assign pma_checker__entries_T_86 = pma_checker__entries_WIRE_7[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_sx = pma_checker__entries_T_86; // @[TLB.scala:170:77] assign pma_checker__entries_T_87 = pma_checker__entries_WIRE_7[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_sw = pma_checker__entries_T_87; // @[TLB.scala:170:77] assign pma_checker__entries_T_88 = pma_checker__entries_WIRE_7[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_gf = pma_checker__entries_T_88; // @[TLB.scala:170:77] assign pma_checker__entries_T_89 = pma_checker__entries_WIRE_7[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_pf = pma_checker__entries_T_89; // @[TLB.scala:170:77] assign pma_checker__entries_T_90 = pma_checker__entries_WIRE_7[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_ae_stage2 = pma_checker__entries_T_90; // @[TLB.scala:170:77] assign pma_checker__entries_T_91 = pma_checker__entries_WIRE_7[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_ae_final = pma_checker__entries_T_91; // @[TLB.scala:170:77] assign pma_checker__entries_T_92 = pma_checker__entries_WIRE_7[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_ae_ptw = pma_checker__entries_T_92; // @[TLB.scala:170:77] assign pma_checker__entries_T_93 = pma_checker__entries_WIRE_7[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_g = pma_checker__entries_T_93; // @[TLB.scala:170:77] assign pma_checker__entries_T_94 = pma_checker__entries_WIRE_7[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_6_u = pma_checker__entries_T_94; // @[TLB.scala:170:77] assign pma_checker__entries_T_95 = pma_checker__entries_WIRE_7[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_6_ppn = pma_checker__entries_T_95; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_119; // @[TLB.scala:170:77] wire pma_checker__entries_T_118; // @[TLB.scala:170:77] wire pma_checker__entries_T_117; // @[TLB.scala:170:77] wire pma_checker__entries_T_116; // @[TLB.scala:170:77] wire pma_checker__entries_T_115; // @[TLB.scala:170:77] wire pma_checker__entries_T_114; // @[TLB.scala:170:77] wire pma_checker__entries_T_113; // @[TLB.scala:170:77] wire pma_checker__entries_T_112; // @[TLB.scala:170:77] wire pma_checker__entries_T_111; // @[TLB.scala:170:77] wire pma_checker__entries_T_110; // @[TLB.scala:170:77] wire pma_checker__entries_T_109; // @[TLB.scala:170:77] wire pma_checker__entries_T_108; // @[TLB.scala:170:77] wire pma_checker__entries_T_107; // @[TLB.scala:170:77] wire pma_checker__entries_T_106; // @[TLB.scala:170:77] wire pma_checker__entries_T_105; // @[TLB.scala:170:77] wire pma_checker__entries_T_104; // @[TLB.scala:170:77] wire pma_checker__entries_T_103; // @[TLB.scala:170:77] wire pma_checker__entries_T_102; // @[TLB.scala:170:77] wire pma_checker__entries_T_101; // @[TLB.scala:170:77] wire pma_checker__entries_T_100; // @[TLB.scala:170:77] wire pma_checker__entries_T_99; // @[TLB.scala:170:77] wire pma_checker__entries_T_98; // @[TLB.scala:170:77] wire pma_checker__entries_T_97; // @[TLB.scala:170:77] assign pma_checker__entries_T_97 = pma_checker__entries_WIRE_9[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_fragmented_superpage = pma_checker__entries_T_97; // @[TLB.scala:170:77] assign pma_checker__entries_T_98 = pma_checker__entries_WIRE_9[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_c = pma_checker__entries_T_98; // @[TLB.scala:170:77] assign pma_checker__entries_T_99 = pma_checker__entries_WIRE_9[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_eff = pma_checker__entries_T_99; // @[TLB.scala:170:77] assign pma_checker__entries_T_100 = pma_checker__entries_WIRE_9[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_paa = pma_checker__entries_T_100; // @[TLB.scala:170:77] assign pma_checker__entries_T_101 = pma_checker__entries_WIRE_9[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_pal = pma_checker__entries_T_101; // @[TLB.scala:170:77] assign pma_checker__entries_T_102 = pma_checker__entries_WIRE_9[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_ppp = pma_checker__entries_T_102; // @[TLB.scala:170:77] assign pma_checker__entries_T_103 = pma_checker__entries_WIRE_9[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_pr = pma_checker__entries_T_103; // @[TLB.scala:170:77] assign pma_checker__entries_T_104 = pma_checker__entries_WIRE_9[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_px = pma_checker__entries_T_104; // @[TLB.scala:170:77] assign pma_checker__entries_T_105 = pma_checker__entries_WIRE_9[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_pw = pma_checker__entries_T_105; // @[TLB.scala:170:77] assign pma_checker__entries_T_106 = pma_checker__entries_WIRE_9[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_hr = pma_checker__entries_T_106; // @[TLB.scala:170:77] assign pma_checker__entries_T_107 = pma_checker__entries_WIRE_9[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_hx = pma_checker__entries_T_107; // @[TLB.scala:170:77] assign pma_checker__entries_T_108 = pma_checker__entries_WIRE_9[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_hw = pma_checker__entries_T_108; // @[TLB.scala:170:77] assign pma_checker__entries_T_109 = pma_checker__entries_WIRE_9[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_sr = pma_checker__entries_T_109; // @[TLB.scala:170:77] assign pma_checker__entries_T_110 = pma_checker__entries_WIRE_9[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_sx = pma_checker__entries_T_110; // @[TLB.scala:170:77] assign pma_checker__entries_T_111 = pma_checker__entries_WIRE_9[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_sw = pma_checker__entries_T_111; // @[TLB.scala:170:77] assign pma_checker__entries_T_112 = pma_checker__entries_WIRE_9[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_gf = pma_checker__entries_T_112; // @[TLB.scala:170:77] assign pma_checker__entries_T_113 = pma_checker__entries_WIRE_9[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_pf = pma_checker__entries_T_113; // @[TLB.scala:170:77] assign pma_checker__entries_T_114 = pma_checker__entries_WIRE_9[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_ae_stage2 = pma_checker__entries_T_114; // @[TLB.scala:170:77] assign pma_checker__entries_T_115 = pma_checker__entries_WIRE_9[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_ae_final = pma_checker__entries_T_115; // @[TLB.scala:170:77] assign pma_checker__entries_T_116 = pma_checker__entries_WIRE_9[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_ae_ptw = pma_checker__entries_T_116; // @[TLB.scala:170:77] assign pma_checker__entries_T_117 = pma_checker__entries_WIRE_9[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_g = pma_checker__entries_T_117; // @[TLB.scala:170:77] assign pma_checker__entries_T_118 = pma_checker__entries_WIRE_9[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_8_u = pma_checker__entries_T_118; // @[TLB.scala:170:77] assign pma_checker__entries_T_119 = pma_checker__entries_WIRE_9[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_8_ppn = pma_checker__entries_T_119; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_143; // @[TLB.scala:170:77] wire pma_checker__entries_T_142; // @[TLB.scala:170:77] wire pma_checker__entries_T_141; // @[TLB.scala:170:77] wire pma_checker__entries_T_140; // @[TLB.scala:170:77] wire pma_checker__entries_T_139; // @[TLB.scala:170:77] wire pma_checker__entries_T_138; // @[TLB.scala:170:77] wire pma_checker__entries_T_137; // @[TLB.scala:170:77] wire pma_checker__entries_T_136; // @[TLB.scala:170:77] wire pma_checker__entries_T_135; // @[TLB.scala:170:77] wire pma_checker__entries_T_134; // @[TLB.scala:170:77] wire pma_checker__entries_T_133; // @[TLB.scala:170:77] wire pma_checker__entries_T_132; // @[TLB.scala:170:77] wire pma_checker__entries_T_131; // @[TLB.scala:170:77] wire pma_checker__entries_T_130; // @[TLB.scala:170:77] wire pma_checker__entries_T_129; // @[TLB.scala:170:77] wire pma_checker__entries_T_128; // @[TLB.scala:170:77] wire pma_checker__entries_T_127; // @[TLB.scala:170:77] wire pma_checker__entries_T_126; // @[TLB.scala:170:77] wire pma_checker__entries_T_125; // @[TLB.scala:170:77] wire pma_checker__entries_T_124; // @[TLB.scala:170:77] wire pma_checker__entries_T_123; // @[TLB.scala:170:77] wire pma_checker__entries_T_122; // @[TLB.scala:170:77] wire pma_checker__entries_T_121; // @[TLB.scala:170:77] assign pma_checker__entries_T_121 = pma_checker__entries_WIRE_11[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_fragmented_superpage = pma_checker__entries_T_121; // @[TLB.scala:170:77] assign pma_checker__entries_T_122 = pma_checker__entries_WIRE_11[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_c = pma_checker__entries_T_122; // @[TLB.scala:170:77] assign pma_checker__entries_T_123 = pma_checker__entries_WIRE_11[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_eff = pma_checker__entries_T_123; // @[TLB.scala:170:77] assign pma_checker__entries_T_124 = pma_checker__entries_WIRE_11[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_paa = pma_checker__entries_T_124; // @[TLB.scala:170:77] assign pma_checker__entries_T_125 = pma_checker__entries_WIRE_11[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_pal = pma_checker__entries_T_125; // @[TLB.scala:170:77] assign pma_checker__entries_T_126 = pma_checker__entries_WIRE_11[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_ppp = pma_checker__entries_T_126; // @[TLB.scala:170:77] assign pma_checker__entries_T_127 = pma_checker__entries_WIRE_11[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_pr = pma_checker__entries_T_127; // @[TLB.scala:170:77] assign pma_checker__entries_T_128 = pma_checker__entries_WIRE_11[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_px = pma_checker__entries_T_128; // @[TLB.scala:170:77] assign pma_checker__entries_T_129 = pma_checker__entries_WIRE_11[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_pw = pma_checker__entries_T_129; // @[TLB.scala:170:77] assign pma_checker__entries_T_130 = pma_checker__entries_WIRE_11[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_hr = pma_checker__entries_T_130; // @[TLB.scala:170:77] assign pma_checker__entries_T_131 = pma_checker__entries_WIRE_11[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_hx = pma_checker__entries_T_131; // @[TLB.scala:170:77] assign pma_checker__entries_T_132 = pma_checker__entries_WIRE_11[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_hw = pma_checker__entries_T_132; // @[TLB.scala:170:77] assign pma_checker__entries_T_133 = pma_checker__entries_WIRE_11[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_sr = pma_checker__entries_T_133; // @[TLB.scala:170:77] assign pma_checker__entries_T_134 = pma_checker__entries_WIRE_11[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_sx = pma_checker__entries_T_134; // @[TLB.scala:170:77] assign pma_checker__entries_T_135 = pma_checker__entries_WIRE_11[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_sw = pma_checker__entries_T_135; // @[TLB.scala:170:77] assign pma_checker__entries_T_136 = pma_checker__entries_WIRE_11[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_gf = pma_checker__entries_T_136; // @[TLB.scala:170:77] assign pma_checker__entries_T_137 = pma_checker__entries_WIRE_11[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_pf = pma_checker__entries_T_137; // @[TLB.scala:170:77] assign pma_checker__entries_T_138 = pma_checker__entries_WIRE_11[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_ae_stage2 = pma_checker__entries_T_138; // @[TLB.scala:170:77] assign pma_checker__entries_T_139 = pma_checker__entries_WIRE_11[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_ae_final = pma_checker__entries_T_139; // @[TLB.scala:170:77] assign pma_checker__entries_T_140 = pma_checker__entries_WIRE_11[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_ae_ptw = pma_checker__entries_T_140; // @[TLB.scala:170:77] assign pma_checker__entries_T_141 = pma_checker__entries_WIRE_11[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_g = pma_checker__entries_T_141; // @[TLB.scala:170:77] assign pma_checker__entries_T_142 = pma_checker__entries_WIRE_11[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_10_u = pma_checker__entries_T_142; // @[TLB.scala:170:77] assign pma_checker__entries_T_143 = pma_checker__entries_WIRE_11[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_10_ppn = pma_checker__entries_T_143; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_167; // @[TLB.scala:170:77] wire pma_checker__entries_T_166; // @[TLB.scala:170:77] wire pma_checker__entries_T_165; // @[TLB.scala:170:77] wire pma_checker__entries_T_164; // @[TLB.scala:170:77] wire pma_checker__entries_T_163; // @[TLB.scala:170:77] wire pma_checker__entries_T_162; // @[TLB.scala:170:77] wire pma_checker__entries_T_161; // @[TLB.scala:170:77] wire pma_checker__entries_T_160; // @[TLB.scala:170:77] wire pma_checker__entries_T_159; // @[TLB.scala:170:77] wire pma_checker__entries_T_158; // @[TLB.scala:170:77] wire pma_checker__entries_T_157; // @[TLB.scala:170:77] wire pma_checker__entries_T_156; // @[TLB.scala:170:77] wire pma_checker__entries_T_155; // @[TLB.scala:170:77] wire pma_checker__entries_T_154; // @[TLB.scala:170:77] wire pma_checker__entries_T_153; // @[TLB.scala:170:77] wire pma_checker__entries_T_152; // @[TLB.scala:170:77] wire pma_checker__entries_T_151; // @[TLB.scala:170:77] wire pma_checker__entries_T_150; // @[TLB.scala:170:77] wire pma_checker__entries_T_149; // @[TLB.scala:170:77] wire pma_checker__entries_T_148; // @[TLB.scala:170:77] wire pma_checker__entries_T_147; // @[TLB.scala:170:77] wire pma_checker__entries_T_146; // @[TLB.scala:170:77] wire pma_checker__entries_T_145; // @[TLB.scala:170:77] assign pma_checker__entries_T_145 = pma_checker__entries_WIRE_13[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_fragmented_superpage = pma_checker__entries_T_145; // @[TLB.scala:170:77] assign pma_checker__entries_T_146 = pma_checker__entries_WIRE_13[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_c = pma_checker__entries_T_146; // @[TLB.scala:170:77] assign pma_checker__entries_T_147 = pma_checker__entries_WIRE_13[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_eff = pma_checker__entries_T_147; // @[TLB.scala:170:77] assign pma_checker__entries_T_148 = pma_checker__entries_WIRE_13[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_paa = pma_checker__entries_T_148; // @[TLB.scala:170:77] assign pma_checker__entries_T_149 = pma_checker__entries_WIRE_13[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_pal = pma_checker__entries_T_149; // @[TLB.scala:170:77] assign pma_checker__entries_T_150 = pma_checker__entries_WIRE_13[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_ppp = pma_checker__entries_T_150; // @[TLB.scala:170:77] assign pma_checker__entries_T_151 = pma_checker__entries_WIRE_13[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_pr = pma_checker__entries_T_151; // @[TLB.scala:170:77] assign pma_checker__entries_T_152 = pma_checker__entries_WIRE_13[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_px = pma_checker__entries_T_152; // @[TLB.scala:170:77] assign pma_checker__entries_T_153 = pma_checker__entries_WIRE_13[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_pw = pma_checker__entries_T_153; // @[TLB.scala:170:77] assign pma_checker__entries_T_154 = pma_checker__entries_WIRE_13[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_hr = pma_checker__entries_T_154; // @[TLB.scala:170:77] assign pma_checker__entries_T_155 = pma_checker__entries_WIRE_13[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_hx = pma_checker__entries_T_155; // @[TLB.scala:170:77] assign pma_checker__entries_T_156 = pma_checker__entries_WIRE_13[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_hw = pma_checker__entries_T_156; // @[TLB.scala:170:77] assign pma_checker__entries_T_157 = pma_checker__entries_WIRE_13[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_sr = pma_checker__entries_T_157; // @[TLB.scala:170:77] assign pma_checker__entries_T_158 = pma_checker__entries_WIRE_13[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_sx = pma_checker__entries_T_158; // @[TLB.scala:170:77] assign pma_checker__entries_T_159 = pma_checker__entries_WIRE_13[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_sw = pma_checker__entries_T_159; // @[TLB.scala:170:77] assign pma_checker__entries_T_160 = pma_checker__entries_WIRE_13[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_gf = pma_checker__entries_T_160; // @[TLB.scala:170:77] assign pma_checker__entries_T_161 = pma_checker__entries_WIRE_13[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_pf = pma_checker__entries_T_161; // @[TLB.scala:170:77] assign pma_checker__entries_T_162 = pma_checker__entries_WIRE_13[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_ae_stage2 = pma_checker__entries_T_162; // @[TLB.scala:170:77] assign pma_checker__entries_T_163 = pma_checker__entries_WIRE_13[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_ae_final = pma_checker__entries_T_163; // @[TLB.scala:170:77] assign pma_checker__entries_T_164 = pma_checker__entries_WIRE_13[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_ae_ptw = pma_checker__entries_T_164; // @[TLB.scala:170:77] assign pma_checker__entries_T_165 = pma_checker__entries_WIRE_13[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_g = pma_checker__entries_T_165; // @[TLB.scala:170:77] assign pma_checker__entries_T_166 = pma_checker__entries_WIRE_13[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_12_u = pma_checker__entries_T_166; // @[TLB.scala:170:77] assign pma_checker__entries_T_167 = pma_checker__entries_WIRE_13[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_12_ppn = pma_checker__entries_T_167; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_191; // @[TLB.scala:170:77] wire pma_checker__entries_T_190; // @[TLB.scala:170:77] wire pma_checker__entries_T_189; // @[TLB.scala:170:77] wire pma_checker__entries_T_188; // @[TLB.scala:170:77] wire pma_checker__entries_T_187; // @[TLB.scala:170:77] wire pma_checker__entries_T_186; // @[TLB.scala:170:77] wire pma_checker__entries_T_185; // @[TLB.scala:170:77] wire pma_checker__entries_T_184; // @[TLB.scala:170:77] wire pma_checker__entries_T_183; // @[TLB.scala:170:77] wire pma_checker__entries_T_182; // @[TLB.scala:170:77] wire pma_checker__entries_T_181; // @[TLB.scala:170:77] wire pma_checker__entries_T_180; // @[TLB.scala:170:77] wire pma_checker__entries_T_179; // @[TLB.scala:170:77] wire pma_checker__entries_T_178; // @[TLB.scala:170:77] wire pma_checker__entries_T_177; // @[TLB.scala:170:77] wire pma_checker__entries_T_176; // @[TLB.scala:170:77] wire pma_checker__entries_T_175; // @[TLB.scala:170:77] wire pma_checker__entries_T_174; // @[TLB.scala:170:77] wire pma_checker__entries_T_173; // @[TLB.scala:170:77] wire pma_checker__entries_T_172; // @[TLB.scala:170:77] wire pma_checker__entries_T_171; // @[TLB.scala:170:77] wire pma_checker__entries_T_170; // @[TLB.scala:170:77] wire pma_checker__entries_T_169; // @[TLB.scala:170:77] assign pma_checker__entries_T_169 = pma_checker__entries_WIRE_15[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_fragmented_superpage = pma_checker__entries_T_169; // @[TLB.scala:170:77] assign pma_checker__entries_T_170 = pma_checker__entries_WIRE_15[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_c = pma_checker__entries_T_170; // @[TLB.scala:170:77] assign pma_checker__entries_T_171 = pma_checker__entries_WIRE_15[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_eff = pma_checker__entries_T_171; // @[TLB.scala:170:77] assign pma_checker__entries_T_172 = pma_checker__entries_WIRE_15[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_paa = pma_checker__entries_T_172; // @[TLB.scala:170:77] assign pma_checker__entries_T_173 = pma_checker__entries_WIRE_15[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_pal = pma_checker__entries_T_173; // @[TLB.scala:170:77] assign pma_checker__entries_T_174 = pma_checker__entries_WIRE_15[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_ppp = pma_checker__entries_T_174; // @[TLB.scala:170:77] assign pma_checker__entries_T_175 = pma_checker__entries_WIRE_15[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_pr = pma_checker__entries_T_175; // @[TLB.scala:170:77] assign pma_checker__entries_T_176 = pma_checker__entries_WIRE_15[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_px = pma_checker__entries_T_176; // @[TLB.scala:170:77] assign pma_checker__entries_T_177 = pma_checker__entries_WIRE_15[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_pw = pma_checker__entries_T_177; // @[TLB.scala:170:77] assign pma_checker__entries_T_178 = pma_checker__entries_WIRE_15[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_hr = pma_checker__entries_T_178; // @[TLB.scala:170:77] assign pma_checker__entries_T_179 = pma_checker__entries_WIRE_15[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_hx = pma_checker__entries_T_179; // @[TLB.scala:170:77] assign pma_checker__entries_T_180 = pma_checker__entries_WIRE_15[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_hw = pma_checker__entries_T_180; // @[TLB.scala:170:77] assign pma_checker__entries_T_181 = pma_checker__entries_WIRE_15[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_sr = pma_checker__entries_T_181; // @[TLB.scala:170:77] assign pma_checker__entries_T_182 = pma_checker__entries_WIRE_15[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_sx = pma_checker__entries_T_182; // @[TLB.scala:170:77] assign pma_checker__entries_T_183 = pma_checker__entries_WIRE_15[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_sw = pma_checker__entries_T_183; // @[TLB.scala:170:77] assign pma_checker__entries_T_184 = pma_checker__entries_WIRE_15[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_gf = pma_checker__entries_T_184; // @[TLB.scala:170:77] assign pma_checker__entries_T_185 = pma_checker__entries_WIRE_15[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_pf = pma_checker__entries_T_185; // @[TLB.scala:170:77] assign pma_checker__entries_T_186 = pma_checker__entries_WIRE_15[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_ae_stage2 = pma_checker__entries_T_186; // @[TLB.scala:170:77] assign pma_checker__entries_T_187 = pma_checker__entries_WIRE_15[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_ae_final = pma_checker__entries_T_187; // @[TLB.scala:170:77] assign pma_checker__entries_T_188 = pma_checker__entries_WIRE_15[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_ae_ptw = pma_checker__entries_T_188; // @[TLB.scala:170:77] assign pma_checker__entries_T_189 = pma_checker__entries_WIRE_15[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_g = pma_checker__entries_T_189; // @[TLB.scala:170:77] assign pma_checker__entries_T_190 = pma_checker__entries_WIRE_15[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_14_u = pma_checker__entries_T_190; // @[TLB.scala:170:77] assign pma_checker__entries_T_191 = pma_checker__entries_WIRE_15[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_14_ppn = pma_checker__entries_T_191; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_214; // @[TLB.scala:170:77] wire pma_checker__entries_T_213; // @[TLB.scala:170:77] wire pma_checker__entries_T_212; // @[TLB.scala:170:77] wire pma_checker__entries_T_211; // @[TLB.scala:170:77] wire pma_checker__entries_T_210; // @[TLB.scala:170:77] wire pma_checker__entries_T_209; // @[TLB.scala:170:77] wire pma_checker__entries_T_208; // @[TLB.scala:170:77] wire pma_checker__entries_T_207; // @[TLB.scala:170:77] wire pma_checker__entries_T_206; // @[TLB.scala:170:77] wire pma_checker__entries_T_205; // @[TLB.scala:170:77] wire pma_checker__entries_T_204; // @[TLB.scala:170:77] wire pma_checker__entries_T_203; // @[TLB.scala:170:77] wire pma_checker__entries_T_202; // @[TLB.scala:170:77] wire pma_checker__entries_T_201; // @[TLB.scala:170:77] wire pma_checker__entries_T_200; // @[TLB.scala:170:77] wire pma_checker__entries_T_199; // @[TLB.scala:170:77] wire pma_checker__entries_T_198; // @[TLB.scala:170:77] wire pma_checker__entries_T_197; // @[TLB.scala:170:77] wire pma_checker__entries_T_196; // @[TLB.scala:170:77] wire pma_checker__entries_T_195; // @[TLB.scala:170:77] wire pma_checker__entries_T_194; // @[TLB.scala:170:77] wire pma_checker__entries_T_193; // @[TLB.scala:170:77] wire pma_checker__entries_T_192; // @[TLB.scala:170:77] assign pma_checker__entries_T_192 = pma_checker__entries_WIRE_17[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_fragmented_superpage = pma_checker__entries_T_192; // @[TLB.scala:170:77] assign pma_checker__entries_T_193 = pma_checker__entries_WIRE_17[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_c = pma_checker__entries_T_193; // @[TLB.scala:170:77] assign pma_checker__entries_T_194 = pma_checker__entries_WIRE_17[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_eff = pma_checker__entries_T_194; // @[TLB.scala:170:77] assign pma_checker__entries_T_195 = pma_checker__entries_WIRE_17[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_paa = pma_checker__entries_T_195; // @[TLB.scala:170:77] assign pma_checker__entries_T_196 = pma_checker__entries_WIRE_17[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_pal = pma_checker__entries_T_196; // @[TLB.scala:170:77] assign pma_checker__entries_T_197 = pma_checker__entries_WIRE_17[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_ppp = pma_checker__entries_T_197; // @[TLB.scala:170:77] assign pma_checker__entries_T_198 = pma_checker__entries_WIRE_17[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_pr = pma_checker__entries_T_198; // @[TLB.scala:170:77] assign pma_checker__entries_T_199 = pma_checker__entries_WIRE_17[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_px = pma_checker__entries_T_199; // @[TLB.scala:170:77] assign pma_checker__entries_T_200 = pma_checker__entries_WIRE_17[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_pw = pma_checker__entries_T_200; // @[TLB.scala:170:77] assign pma_checker__entries_T_201 = pma_checker__entries_WIRE_17[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_hr = pma_checker__entries_T_201; // @[TLB.scala:170:77] assign pma_checker__entries_T_202 = pma_checker__entries_WIRE_17[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_hx = pma_checker__entries_T_202; // @[TLB.scala:170:77] assign pma_checker__entries_T_203 = pma_checker__entries_WIRE_17[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_hw = pma_checker__entries_T_203; // @[TLB.scala:170:77] assign pma_checker__entries_T_204 = pma_checker__entries_WIRE_17[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_sr = pma_checker__entries_T_204; // @[TLB.scala:170:77] assign pma_checker__entries_T_205 = pma_checker__entries_WIRE_17[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_sx = pma_checker__entries_T_205; // @[TLB.scala:170:77] assign pma_checker__entries_T_206 = pma_checker__entries_WIRE_17[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_sw = pma_checker__entries_T_206; // @[TLB.scala:170:77] assign pma_checker__entries_T_207 = pma_checker__entries_WIRE_17[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_gf = pma_checker__entries_T_207; // @[TLB.scala:170:77] assign pma_checker__entries_T_208 = pma_checker__entries_WIRE_17[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_pf = pma_checker__entries_T_208; // @[TLB.scala:170:77] assign pma_checker__entries_T_209 = pma_checker__entries_WIRE_17[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_ae_stage2 = pma_checker__entries_T_209; // @[TLB.scala:170:77] assign pma_checker__entries_T_210 = pma_checker__entries_WIRE_17[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_ae_final = pma_checker__entries_T_210; // @[TLB.scala:170:77] assign pma_checker__entries_T_211 = pma_checker__entries_WIRE_17[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_ae_ptw = pma_checker__entries_T_211; // @[TLB.scala:170:77] assign pma_checker__entries_T_212 = pma_checker__entries_WIRE_17[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_g = pma_checker__entries_T_212; // @[TLB.scala:170:77] assign pma_checker__entries_T_213 = pma_checker__entries_WIRE_17[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_16_u = pma_checker__entries_T_213; // @[TLB.scala:170:77] assign pma_checker__entries_T_214 = pma_checker__entries_WIRE_17[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_16_ppn = pma_checker__entries_T_214; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_237; // @[TLB.scala:170:77] wire pma_checker__entries_T_236; // @[TLB.scala:170:77] wire pma_checker__entries_T_235; // @[TLB.scala:170:77] wire pma_checker__entries_T_234; // @[TLB.scala:170:77] wire pma_checker__entries_T_233; // @[TLB.scala:170:77] wire pma_checker__entries_T_232; // @[TLB.scala:170:77] wire pma_checker__entries_T_231; // @[TLB.scala:170:77] wire pma_checker__entries_T_230; // @[TLB.scala:170:77] wire pma_checker__entries_T_229; // @[TLB.scala:170:77] wire pma_checker__entries_T_228; // @[TLB.scala:170:77] wire pma_checker__entries_T_227; // @[TLB.scala:170:77] wire pma_checker__entries_T_226; // @[TLB.scala:170:77] wire pma_checker__entries_T_225; // @[TLB.scala:170:77] wire pma_checker__entries_T_224; // @[TLB.scala:170:77] wire pma_checker__entries_T_223; // @[TLB.scala:170:77] wire pma_checker__entries_T_222; // @[TLB.scala:170:77] wire pma_checker__entries_T_221; // @[TLB.scala:170:77] wire pma_checker__entries_T_220; // @[TLB.scala:170:77] wire pma_checker__entries_T_219; // @[TLB.scala:170:77] wire pma_checker__entries_T_218; // @[TLB.scala:170:77] wire pma_checker__entries_T_217; // @[TLB.scala:170:77] wire pma_checker__entries_T_216; // @[TLB.scala:170:77] wire pma_checker__entries_T_215; // @[TLB.scala:170:77] assign pma_checker__entries_T_215 = pma_checker__entries_WIRE_19[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_fragmented_superpage = pma_checker__entries_T_215; // @[TLB.scala:170:77] assign pma_checker__entries_T_216 = pma_checker__entries_WIRE_19[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_c = pma_checker__entries_T_216; // @[TLB.scala:170:77] assign pma_checker__entries_T_217 = pma_checker__entries_WIRE_19[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_eff = pma_checker__entries_T_217; // @[TLB.scala:170:77] assign pma_checker__entries_T_218 = pma_checker__entries_WIRE_19[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_paa = pma_checker__entries_T_218; // @[TLB.scala:170:77] assign pma_checker__entries_T_219 = pma_checker__entries_WIRE_19[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_pal = pma_checker__entries_T_219; // @[TLB.scala:170:77] assign pma_checker__entries_T_220 = pma_checker__entries_WIRE_19[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_ppp = pma_checker__entries_T_220; // @[TLB.scala:170:77] assign pma_checker__entries_T_221 = pma_checker__entries_WIRE_19[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_pr = pma_checker__entries_T_221; // @[TLB.scala:170:77] assign pma_checker__entries_T_222 = pma_checker__entries_WIRE_19[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_px = pma_checker__entries_T_222; // @[TLB.scala:170:77] assign pma_checker__entries_T_223 = pma_checker__entries_WIRE_19[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_pw = pma_checker__entries_T_223; // @[TLB.scala:170:77] assign pma_checker__entries_T_224 = pma_checker__entries_WIRE_19[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_hr = pma_checker__entries_T_224; // @[TLB.scala:170:77] assign pma_checker__entries_T_225 = pma_checker__entries_WIRE_19[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_hx = pma_checker__entries_T_225; // @[TLB.scala:170:77] assign pma_checker__entries_T_226 = pma_checker__entries_WIRE_19[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_hw = pma_checker__entries_T_226; // @[TLB.scala:170:77] assign pma_checker__entries_T_227 = pma_checker__entries_WIRE_19[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_sr = pma_checker__entries_T_227; // @[TLB.scala:170:77] assign pma_checker__entries_T_228 = pma_checker__entries_WIRE_19[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_sx = pma_checker__entries_T_228; // @[TLB.scala:170:77] assign pma_checker__entries_T_229 = pma_checker__entries_WIRE_19[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_sw = pma_checker__entries_T_229; // @[TLB.scala:170:77] assign pma_checker__entries_T_230 = pma_checker__entries_WIRE_19[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_gf = pma_checker__entries_T_230; // @[TLB.scala:170:77] assign pma_checker__entries_T_231 = pma_checker__entries_WIRE_19[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_pf = pma_checker__entries_T_231; // @[TLB.scala:170:77] assign pma_checker__entries_T_232 = pma_checker__entries_WIRE_19[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_ae_stage2 = pma_checker__entries_T_232; // @[TLB.scala:170:77] assign pma_checker__entries_T_233 = pma_checker__entries_WIRE_19[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_ae_final = pma_checker__entries_T_233; // @[TLB.scala:170:77] assign pma_checker__entries_T_234 = pma_checker__entries_WIRE_19[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_ae_ptw = pma_checker__entries_T_234; // @[TLB.scala:170:77] assign pma_checker__entries_T_235 = pma_checker__entries_WIRE_19[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_g = pma_checker__entries_T_235; // @[TLB.scala:170:77] assign pma_checker__entries_T_236 = pma_checker__entries_WIRE_19[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_18_u = pma_checker__entries_T_236; // @[TLB.scala:170:77] assign pma_checker__entries_T_237 = pma_checker__entries_WIRE_19[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_18_ppn = pma_checker__entries_T_237; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_260; // @[TLB.scala:170:77] wire pma_checker__entries_T_259; // @[TLB.scala:170:77] wire pma_checker__entries_T_258; // @[TLB.scala:170:77] wire pma_checker__entries_T_257; // @[TLB.scala:170:77] wire pma_checker__entries_T_256; // @[TLB.scala:170:77] wire pma_checker__entries_T_255; // @[TLB.scala:170:77] wire pma_checker__entries_T_254; // @[TLB.scala:170:77] wire pma_checker__entries_T_253; // @[TLB.scala:170:77] wire pma_checker__entries_T_252; // @[TLB.scala:170:77] wire pma_checker__entries_T_251; // @[TLB.scala:170:77] wire pma_checker__entries_T_250; // @[TLB.scala:170:77] wire pma_checker__entries_T_249; // @[TLB.scala:170:77] wire pma_checker__entries_T_248; // @[TLB.scala:170:77] wire pma_checker__entries_T_247; // @[TLB.scala:170:77] wire pma_checker__entries_T_246; // @[TLB.scala:170:77] wire pma_checker__entries_T_245; // @[TLB.scala:170:77] wire pma_checker__entries_T_244; // @[TLB.scala:170:77] wire pma_checker__entries_T_243; // @[TLB.scala:170:77] wire pma_checker__entries_T_242; // @[TLB.scala:170:77] wire pma_checker__entries_T_241; // @[TLB.scala:170:77] wire pma_checker__entries_T_240; // @[TLB.scala:170:77] wire pma_checker__entries_T_239; // @[TLB.scala:170:77] wire pma_checker__entries_T_238; // @[TLB.scala:170:77] assign pma_checker__entries_T_238 = pma_checker__entries_WIRE_21[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_fragmented_superpage = pma_checker__entries_T_238; // @[TLB.scala:170:77] assign pma_checker__entries_T_239 = pma_checker__entries_WIRE_21[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_c = pma_checker__entries_T_239; // @[TLB.scala:170:77] assign pma_checker__entries_T_240 = pma_checker__entries_WIRE_21[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_eff = pma_checker__entries_T_240; // @[TLB.scala:170:77] assign pma_checker__entries_T_241 = pma_checker__entries_WIRE_21[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_paa = pma_checker__entries_T_241; // @[TLB.scala:170:77] assign pma_checker__entries_T_242 = pma_checker__entries_WIRE_21[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_pal = pma_checker__entries_T_242; // @[TLB.scala:170:77] assign pma_checker__entries_T_243 = pma_checker__entries_WIRE_21[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_ppp = pma_checker__entries_T_243; // @[TLB.scala:170:77] assign pma_checker__entries_T_244 = pma_checker__entries_WIRE_21[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_pr = pma_checker__entries_T_244; // @[TLB.scala:170:77] assign pma_checker__entries_T_245 = pma_checker__entries_WIRE_21[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_px = pma_checker__entries_T_245; // @[TLB.scala:170:77] assign pma_checker__entries_T_246 = pma_checker__entries_WIRE_21[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_pw = pma_checker__entries_T_246; // @[TLB.scala:170:77] assign pma_checker__entries_T_247 = pma_checker__entries_WIRE_21[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_hr = pma_checker__entries_T_247; // @[TLB.scala:170:77] assign pma_checker__entries_T_248 = pma_checker__entries_WIRE_21[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_hx = pma_checker__entries_T_248; // @[TLB.scala:170:77] assign pma_checker__entries_T_249 = pma_checker__entries_WIRE_21[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_hw = pma_checker__entries_T_249; // @[TLB.scala:170:77] assign pma_checker__entries_T_250 = pma_checker__entries_WIRE_21[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_sr = pma_checker__entries_T_250; // @[TLB.scala:170:77] assign pma_checker__entries_T_251 = pma_checker__entries_WIRE_21[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_sx = pma_checker__entries_T_251; // @[TLB.scala:170:77] assign pma_checker__entries_T_252 = pma_checker__entries_WIRE_21[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_sw = pma_checker__entries_T_252; // @[TLB.scala:170:77] assign pma_checker__entries_T_253 = pma_checker__entries_WIRE_21[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_gf = pma_checker__entries_T_253; // @[TLB.scala:170:77] assign pma_checker__entries_T_254 = pma_checker__entries_WIRE_21[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_pf = pma_checker__entries_T_254; // @[TLB.scala:170:77] assign pma_checker__entries_T_255 = pma_checker__entries_WIRE_21[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_ae_stage2 = pma_checker__entries_T_255; // @[TLB.scala:170:77] assign pma_checker__entries_T_256 = pma_checker__entries_WIRE_21[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_ae_final = pma_checker__entries_T_256; // @[TLB.scala:170:77] assign pma_checker__entries_T_257 = pma_checker__entries_WIRE_21[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_ae_ptw = pma_checker__entries_T_257; // @[TLB.scala:170:77] assign pma_checker__entries_T_258 = pma_checker__entries_WIRE_21[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_g = pma_checker__entries_T_258; // @[TLB.scala:170:77] assign pma_checker__entries_T_259 = pma_checker__entries_WIRE_21[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_20_u = pma_checker__entries_T_259; // @[TLB.scala:170:77] assign pma_checker__entries_T_260 = pma_checker__entries_WIRE_21[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_20_ppn = pma_checker__entries_T_260; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_283; // @[TLB.scala:170:77] wire pma_checker__entries_T_282; // @[TLB.scala:170:77] wire pma_checker__entries_T_281; // @[TLB.scala:170:77] wire pma_checker__entries_T_280; // @[TLB.scala:170:77] wire pma_checker__entries_T_279; // @[TLB.scala:170:77] wire pma_checker__entries_T_278; // @[TLB.scala:170:77] wire pma_checker__entries_T_277; // @[TLB.scala:170:77] wire pma_checker__entries_T_276; // @[TLB.scala:170:77] wire pma_checker__entries_T_275; // @[TLB.scala:170:77] wire pma_checker__entries_T_274; // @[TLB.scala:170:77] wire pma_checker__entries_T_273; // @[TLB.scala:170:77] wire pma_checker__entries_T_272; // @[TLB.scala:170:77] wire pma_checker__entries_T_271; // @[TLB.scala:170:77] wire pma_checker__entries_T_270; // @[TLB.scala:170:77] wire pma_checker__entries_T_269; // @[TLB.scala:170:77] wire pma_checker__entries_T_268; // @[TLB.scala:170:77] wire pma_checker__entries_T_267; // @[TLB.scala:170:77] wire pma_checker__entries_T_266; // @[TLB.scala:170:77] wire pma_checker__entries_T_265; // @[TLB.scala:170:77] wire pma_checker__entries_T_264; // @[TLB.scala:170:77] wire pma_checker__entries_T_263; // @[TLB.scala:170:77] wire pma_checker__entries_T_262; // @[TLB.scala:170:77] wire pma_checker__entries_T_261; // @[TLB.scala:170:77] assign pma_checker__entries_T_261 = pma_checker__entries_WIRE_23[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_fragmented_superpage = pma_checker__entries_T_261; // @[TLB.scala:170:77] assign pma_checker__entries_T_262 = pma_checker__entries_WIRE_23[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_c = pma_checker__entries_T_262; // @[TLB.scala:170:77] assign pma_checker__entries_T_263 = pma_checker__entries_WIRE_23[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_eff = pma_checker__entries_T_263; // @[TLB.scala:170:77] assign pma_checker__entries_T_264 = pma_checker__entries_WIRE_23[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_paa = pma_checker__entries_T_264; // @[TLB.scala:170:77] assign pma_checker__entries_T_265 = pma_checker__entries_WIRE_23[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_pal = pma_checker__entries_T_265; // @[TLB.scala:170:77] assign pma_checker__entries_T_266 = pma_checker__entries_WIRE_23[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_ppp = pma_checker__entries_T_266; // @[TLB.scala:170:77] assign pma_checker__entries_T_267 = pma_checker__entries_WIRE_23[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_pr = pma_checker__entries_T_267; // @[TLB.scala:170:77] assign pma_checker__entries_T_268 = pma_checker__entries_WIRE_23[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_px = pma_checker__entries_T_268; // @[TLB.scala:170:77] assign pma_checker__entries_T_269 = pma_checker__entries_WIRE_23[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_pw = pma_checker__entries_T_269; // @[TLB.scala:170:77] assign pma_checker__entries_T_270 = pma_checker__entries_WIRE_23[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_hr = pma_checker__entries_T_270; // @[TLB.scala:170:77] assign pma_checker__entries_T_271 = pma_checker__entries_WIRE_23[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_hx = pma_checker__entries_T_271; // @[TLB.scala:170:77] assign pma_checker__entries_T_272 = pma_checker__entries_WIRE_23[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_hw = pma_checker__entries_T_272; // @[TLB.scala:170:77] assign pma_checker__entries_T_273 = pma_checker__entries_WIRE_23[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_sr = pma_checker__entries_T_273; // @[TLB.scala:170:77] assign pma_checker__entries_T_274 = pma_checker__entries_WIRE_23[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_sx = pma_checker__entries_T_274; // @[TLB.scala:170:77] assign pma_checker__entries_T_275 = pma_checker__entries_WIRE_23[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_sw = pma_checker__entries_T_275; // @[TLB.scala:170:77] assign pma_checker__entries_T_276 = pma_checker__entries_WIRE_23[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_gf = pma_checker__entries_T_276; // @[TLB.scala:170:77] assign pma_checker__entries_T_277 = pma_checker__entries_WIRE_23[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_pf = pma_checker__entries_T_277; // @[TLB.scala:170:77] assign pma_checker__entries_T_278 = pma_checker__entries_WIRE_23[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_ae_stage2 = pma_checker__entries_T_278; // @[TLB.scala:170:77] assign pma_checker__entries_T_279 = pma_checker__entries_WIRE_23[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_ae_final = pma_checker__entries_T_279; // @[TLB.scala:170:77] assign pma_checker__entries_T_280 = pma_checker__entries_WIRE_23[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_ae_ptw = pma_checker__entries_T_280; // @[TLB.scala:170:77] assign pma_checker__entries_T_281 = pma_checker__entries_WIRE_23[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_g = pma_checker__entries_T_281; // @[TLB.scala:170:77] assign pma_checker__entries_T_282 = pma_checker__entries_WIRE_23[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_22_u = pma_checker__entries_T_282; // @[TLB.scala:170:77] assign pma_checker__entries_T_283 = pma_checker__entries_WIRE_23[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_22_ppn = pma_checker__entries_T_283; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_T_306; // @[TLB.scala:170:77] wire pma_checker__entries_T_305; // @[TLB.scala:170:77] wire pma_checker__entries_T_304; // @[TLB.scala:170:77] wire pma_checker__entries_T_303; // @[TLB.scala:170:77] wire pma_checker__entries_T_302; // @[TLB.scala:170:77] wire pma_checker__entries_T_301; // @[TLB.scala:170:77] wire pma_checker__entries_T_300; // @[TLB.scala:170:77] wire pma_checker__entries_T_299; // @[TLB.scala:170:77] wire pma_checker__entries_T_298; // @[TLB.scala:170:77] wire pma_checker__entries_T_297; // @[TLB.scala:170:77] wire pma_checker__entries_T_296; // @[TLB.scala:170:77] wire pma_checker__entries_T_295; // @[TLB.scala:170:77] wire pma_checker__entries_T_294; // @[TLB.scala:170:77] wire pma_checker__entries_T_293; // @[TLB.scala:170:77] wire pma_checker__entries_T_292; // @[TLB.scala:170:77] wire pma_checker__entries_T_291; // @[TLB.scala:170:77] wire pma_checker__entries_T_290; // @[TLB.scala:170:77] wire pma_checker__entries_T_289; // @[TLB.scala:170:77] wire pma_checker__entries_T_288; // @[TLB.scala:170:77] wire pma_checker__entries_T_287; // @[TLB.scala:170:77] wire pma_checker__entries_T_286; // @[TLB.scala:170:77] wire pma_checker__entries_T_285; // @[TLB.scala:170:77] wire pma_checker__entries_T_284; // @[TLB.scala:170:77] assign pma_checker__entries_T_284 = pma_checker__entries_WIRE_25[0]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_fragmented_superpage = pma_checker__entries_T_284; // @[TLB.scala:170:77] assign pma_checker__entries_T_285 = pma_checker__entries_WIRE_25[1]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_c = pma_checker__entries_T_285; // @[TLB.scala:170:77] assign pma_checker__entries_T_286 = pma_checker__entries_WIRE_25[2]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_eff = pma_checker__entries_T_286; // @[TLB.scala:170:77] assign pma_checker__entries_T_287 = pma_checker__entries_WIRE_25[3]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_paa = pma_checker__entries_T_287; // @[TLB.scala:170:77] assign pma_checker__entries_T_288 = pma_checker__entries_WIRE_25[4]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_pal = pma_checker__entries_T_288; // @[TLB.scala:170:77] assign pma_checker__entries_T_289 = pma_checker__entries_WIRE_25[5]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_ppp = pma_checker__entries_T_289; // @[TLB.scala:170:77] assign pma_checker__entries_T_290 = pma_checker__entries_WIRE_25[6]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_pr = pma_checker__entries_T_290; // @[TLB.scala:170:77] assign pma_checker__entries_T_291 = pma_checker__entries_WIRE_25[7]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_px = pma_checker__entries_T_291; // @[TLB.scala:170:77] assign pma_checker__entries_T_292 = pma_checker__entries_WIRE_25[8]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_pw = pma_checker__entries_T_292; // @[TLB.scala:170:77] assign pma_checker__entries_T_293 = pma_checker__entries_WIRE_25[9]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_hr = pma_checker__entries_T_293; // @[TLB.scala:170:77] assign pma_checker__entries_T_294 = pma_checker__entries_WIRE_25[10]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_hx = pma_checker__entries_T_294; // @[TLB.scala:170:77] assign pma_checker__entries_T_295 = pma_checker__entries_WIRE_25[11]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_hw = pma_checker__entries_T_295; // @[TLB.scala:170:77] assign pma_checker__entries_T_296 = pma_checker__entries_WIRE_25[12]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_sr = pma_checker__entries_T_296; // @[TLB.scala:170:77] assign pma_checker__entries_T_297 = pma_checker__entries_WIRE_25[13]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_sx = pma_checker__entries_T_297; // @[TLB.scala:170:77] assign pma_checker__entries_T_298 = pma_checker__entries_WIRE_25[14]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_sw = pma_checker__entries_T_298; // @[TLB.scala:170:77] assign pma_checker__entries_T_299 = pma_checker__entries_WIRE_25[15]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_gf = pma_checker__entries_T_299; // @[TLB.scala:170:77] assign pma_checker__entries_T_300 = pma_checker__entries_WIRE_25[16]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_pf = pma_checker__entries_T_300; // @[TLB.scala:170:77] assign pma_checker__entries_T_301 = pma_checker__entries_WIRE_25[17]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_ae_stage2 = pma_checker__entries_T_301; // @[TLB.scala:170:77] assign pma_checker__entries_T_302 = pma_checker__entries_WIRE_25[18]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_ae_final = pma_checker__entries_T_302; // @[TLB.scala:170:77] assign pma_checker__entries_T_303 = pma_checker__entries_WIRE_25[19]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_ae_ptw = pma_checker__entries_T_303; // @[TLB.scala:170:77] assign pma_checker__entries_T_304 = pma_checker__entries_WIRE_25[20]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_g = pma_checker__entries_T_304; // @[TLB.scala:170:77] assign pma_checker__entries_T_305 = pma_checker__entries_WIRE_25[21]; // @[TLB.scala:170:77] wire pma_checker__entries_WIRE_24_u = pma_checker__entries_T_305; // @[TLB.scala:170:77] assign pma_checker__entries_T_306 = pma_checker__entries_WIRE_25[41:22]; // @[TLB.scala:170:77] wire [19:0] pma_checker__entries_WIRE_24_ppn = pma_checker__entries_T_306; // @[TLB.scala:170:77] wire [1:0] pma_checker_ppn_res = _pma_checker_entries_barrier_8_io_y_ppn[19:18]; // @[package.scala:267:25] wire pma_checker_ppn_ignore = pma_checker__ppn_ignore_T; // @[TLB.scala:197:{28,34}] wire [26:0] pma_checker__ppn_T_1 = pma_checker_ppn_ignore ? pma_checker_vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] pma_checker__ppn_T_2 = {pma_checker__ppn_T_1[26:20], pma_checker__ppn_T_1[19:0] \| _pma_checker_entries_barrier_8_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_3 = pma_checker__ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] pma_checker__ppn_T_4 = {pma_checker_ppn_res, pma_checker__ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}] wire [26:0] pma_checker__ppn_T_6 = {pma_checker__ppn_T_5[26:20], pma_checker__ppn_T_5[19:0] \| _pma_checker_entries_barrier_8_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_7 = pma_checker__ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] pma_checker__ppn_T_8 = {pma_checker__ppn_T_4, pma_checker__ppn_T_7}; // @[TLB.scala:198:{18,58}] wire [1:0] pma_checker_ppn_res_1 = _pma_checker_entries_barrier_9_io_y_ppn[19:18]; // @[package.scala:267:25] wire pma_checker_ppn_ignore_2 = pma_checker__ppn_ignore_T_2; // @[TLB.scala:197:{28,34}] wire [26:0] pma_checker__ppn_T_9 = pma_checker_ppn_ignore_2 ? pma_checker_vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] pma_checker__ppn_T_10 = {pma_checker__ppn_T_9[26:20], pma_checker__ppn_T_9[19:0] \| _pma_checker_entries_barrier_9_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_11 = pma_checker__ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] pma_checker__ppn_T_12 = {pma_checker_ppn_res_1, pma_checker__ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}] wire [26:0] pma_checker__ppn_T_14 = {pma_checker__ppn_T_13[26:20], pma_checker__ppn_T_13[19:0] \| _pma_checker_entries_barrier_9_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_15 = pma_checker__ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] pma_checker__ppn_T_16 = {pma_checker__ppn_T_12, pma_checker__ppn_T_15}; // @[TLB.scala:198:{18,58}] wire [1:0] pma_checker_ppn_res_2 = _pma_checker_entries_barrier_10_io_y_ppn[19:18]; // @[package.scala:267:25] wire pma_checker_ppn_ignore_4 = pma_checker__ppn_ignore_T_4; // @[TLB.scala:197:{28,34}] wire [26:0] pma_checker__ppn_T_17 = pma_checker_ppn_ignore_4 ? pma_checker_vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] pma_checker__ppn_T_18 = {pma_checker__ppn_T_17[26:20], pma_checker__ppn_T_17[19:0] \| _pma_checker_entries_barrier_10_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_19 = pma_checker__ppn_T_18[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] pma_checker__ppn_T_20 = {pma_checker_ppn_res_2, pma_checker__ppn_T_19}; // @[TLB.scala:195:26, :198:{18,58}] wire [26:0] pma_checker__ppn_T_22 = {pma_checker__ppn_T_21[26:20], pma_checker__ppn_T_21[19:0] \| _pma_checker_entries_barrier_10_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_23 = pma_checker__ppn_T_22[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] pma_checker__ppn_T_24 = {pma_checker__ppn_T_20, pma_checker__ppn_T_23}; // @[TLB.scala:198:{18,58}] wire [1:0] pma_checker_ppn_res_3 = _pma_checker_entries_barrier_11_io_y_ppn[19:18]; // @[package.scala:267:25] wire pma_checker_ppn_ignore_6 = pma_checker__ppn_ignore_T_6; // @[TLB.scala:197:{28,34}] wire [26:0] pma_checker__ppn_T_25 = pma_checker_ppn_ignore_6 ? pma_checker_vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30] wire [26:0] pma_checker__ppn_T_26 = {pma_checker__ppn_T_25[26:20], pma_checker__ppn_T_25[19:0] \| _pma_checker_entries_barrier_11_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_27 = pma_checker__ppn_T_26[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] pma_checker__ppn_T_28 = {pma_checker_ppn_res_3, pma_checker__ppn_T_27}; // @[TLB.scala:195:26, :198:{18,58}] wire [26:0] pma_checker__ppn_T_30 = {pma_checker__ppn_T_29[26:20], pma_checker__ppn_T_29[19:0] \| _pma_checker_entries_barrier_11_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_31 = pma_checker__ppn_T_30[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] pma_checker__ppn_T_32 = {pma_checker__ppn_T_28, pma_checker__ppn_T_31}; // @[TLB.scala:198:{18,58}] wire [1:0] pma_checker_ppn_res_4 = _pma_checker_entries_barrier_12_io_y_ppn[19:18]; // @[package.scala:267:25] wire [26:0] pma_checker__ppn_T_34 = {pma_checker__ppn_T_33[26:20], pma_checker__ppn_T_33[19:0] \| _pma_checker_entries_barrier_12_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_35 = pma_checker__ppn_T_34[17:9]; // @[TLB.scala:198:{47,58}] wire [10:0] pma_checker__ppn_T_36 = {pma_checker_ppn_res_4, pma_checker__ppn_T_35}; // @[TLB.scala:195:26, :198:{18,58}] wire [26:0] pma_checker__ppn_T_38 = {pma_checker__ppn_T_37[26:20], pma_checker__ppn_T_37[19:0] \| _pma_checker_entries_barrier_12_io_y_ppn}; // @[package.scala:267:25] wire [8:0] pma_checker__ppn_T_39 = pma_checker__ppn_T_38[8:0]; // @[TLB.scala:198:{47,58}] wire [19:0] pma_checker__ppn_T_40 = {pma_checker__ppn_T_36, pma_checker__ppn_T_39}; // @[TLB.scala:198:{18,58}] wire [19:0] pma_checker__ppn_T_41 = pma_checker_vpn[19:0]; // @[TLB.scala:335:30, :502:125] wire [19:0] pma_checker__ppn_T_55 = pma_checker__ppn_T_41; // @[Mux.scala:30:73] wire [19:0] pma_checker__ppn_T_68 = pma_checker__ppn_T_55; // @[Mux.scala:30:73] wire [19:0] pma_checker_ppn = pma_checker__ppn_T_68; // @[Mux.scala:30:73] wire [1:0] pma_checker_ptw_ae_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ae_ptw, _pma_checker_entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_ae_array_lo_lo = {pma_checker_ptw_ae_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_ae_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ae_ptw, _pma_checker_entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_ae_array_lo_hi = {pma_checker_ptw_ae_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ptw_ae_array_lo = {pma_checker_ptw_ae_array_lo_hi, pma_checker_ptw_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_ae_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ae_ptw, _pma_checker_entries_barrier_7_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_ae_array_hi_lo = {pma_checker_ptw_ae_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_ae_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_ae_ptw, _pma_checker_entries_barrier_9_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_ae_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_ae_ptw, _pma_checker_entries_barrier_11_io_y_ae_ptw}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_ptw_ae_array_hi_hi = {pma_checker_ptw_ae_array_hi_hi_hi, pma_checker_ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_ptw_ae_array_hi = {pma_checker_ptw_ae_array_hi_hi, pma_checker_ptw_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__ptw_ae_array_T = {pma_checker_ptw_ae_array_hi, pma_checker_ptw_ae_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_ptw_ae_array = {1'h0, pma_checker__ptw_ae_array_T}; // @[package.scala:45:27] wire [1:0] pma_checker_final_ae_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ae_final, _pma_checker_entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_final_ae_array_lo_lo = {pma_checker_final_ae_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_final_ae_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ae_final, _pma_checker_entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_final_ae_array_lo_hi = {pma_checker_final_ae_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_final_ae_array_lo = {pma_checker_final_ae_array_lo_hi, pma_checker_final_ae_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_final_ae_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ae_final, _pma_checker_entries_barrier_7_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_final_ae_array_hi_lo = {pma_checker_final_ae_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_final_ae_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_ae_final, _pma_checker_entries_barrier_9_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_final_ae_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_ae_final, _pma_checker_entries_barrier_11_io_y_ae_final}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_final_ae_array_hi_hi = {pma_checker_final_ae_array_hi_hi_hi, pma_checker_final_ae_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_final_ae_array_hi = {pma_checker_final_ae_array_hi_hi, pma_checker_final_ae_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__final_ae_array_T = {pma_checker_final_ae_array_hi, pma_checker_final_ae_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_final_ae_array = {1'h0, pma_checker__final_ae_array_T}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_pf_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pf, _pma_checker_entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_pf_array_lo_lo = {pma_checker_ptw_pf_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_pf_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pf, _pma_checker_entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_pf_array_lo_hi = {pma_checker_ptw_pf_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ptw_pf_array_lo = {pma_checker_ptw_pf_array_lo_hi, pma_checker_ptw_pf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_pf_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pf, _pma_checker_entries_barrier_7_io_y_pf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_pf_array_hi_lo = {pma_checker_ptw_pf_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_pf_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_pf, _pma_checker_entries_barrier_9_io_y_pf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_pf_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_pf, _pma_checker_entries_barrier_11_io_y_pf}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_ptw_pf_array_hi_hi = {pma_checker_ptw_pf_array_hi_hi_hi, pma_checker_ptw_pf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_ptw_pf_array_hi = {pma_checker_ptw_pf_array_hi_hi, pma_checker_ptw_pf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__ptw_pf_array_T = {pma_checker_ptw_pf_array_hi, pma_checker_ptw_pf_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_ptw_pf_array = {1'h0, pma_checker__ptw_pf_array_T}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_gf_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_gf, _pma_checker_entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_gf_array_lo_lo = {pma_checker_ptw_gf_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_gf_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_gf, _pma_checker_entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_gf_array_lo_hi = {pma_checker_ptw_gf_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ptw_gf_array_lo = {pma_checker_ptw_gf_array_lo_hi, pma_checker_ptw_gf_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_ptw_gf_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_gf, _pma_checker_entries_barrier_7_io_y_gf}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ptw_gf_array_hi_lo = {pma_checker_ptw_gf_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_gf_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_gf, _pma_checker_entries_barrier_9_io_y_gf}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ptw_gf_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_gf, _pma_checker_entries_barrier_11_io_y_gf}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_ptw_gf_array_hi_hi = {pma_checker_ptw_gf_array_hi_hi_hi, pma_checker_ptw_gf_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_ptw_gf_array_hi = {pma_checker_ptw_gf_array_hi_hi, pma_checker_ptw_gf_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__ptw_gf_array_T = {pma_checker_ptw_gf_array_hi, pma_checker_ptw_gf_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_ptw_gf_array = {1'h0, pma_checker__ptw_gf_array_T}; // @[package.scala:45:27] wire [13:0] pma_checker__gf_ld_array_T_3 = pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :600:82] wire [13:0] pma_checker__gf_st_array_T_2 = pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :601:63] wire [13:0] pma_checker__gf_inst_array_T_1 = pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :602:46] wire pma_checker__priv_rw_ok_T = ~pma_checker_priv_s; // @[TLB.scala:370:20, :513:24] wire pma_checker__priv_rw_ok_T_1 = pma_checker__priv_rw_ok_T; // @[TLB.scala:513:{24,32}] wire [1:0] _GEN_6 = {_pma_checker_entries_barrier_2_io_y_u, _pma_checker_entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_lo_lo_hi = _GEN_6; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_lo_lo_hi_1 = _GEN_6; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_priv_x_ok_lo_lo_hi = _GEN_6; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_lo_lo_hi_1 = _GEN_6; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_lo_lo = {pma_checker_priv_rw_ok_lo_lo_hi, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_7 = {_pma_checker_entries_barrier_5_io_y_u, _pma_checker_entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_lo_hi_hi = _GEN_7; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_lo_hi_hi_1 = _GEN_7; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_priv_x_ok_lo_hi_hi = _GEN_7; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_lo_hi_hi_1 = _GEN_7; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_lo_hi = {pma_checker_priv_rw_ok_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_priv_rw_ok_lo = {pma_checker_priv_rw_ok_lo_hi, pma_checker_priv_rw_ok_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_8 = {_pma_checker_entries_barrier_8_io_y_u, _pma_checker_entries_barrier_7_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_lo_hi = _GEN_8; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_lo_hi_1 = _GEN_8; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_lo_hi = _GEN_8; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_lo_hi_1 = _GEN_8; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_hi_lo = {pma_checker_priv_rw_ok_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_9 = {_pma_checker_entries_barrier_10_io_y_u, _pma_checker_entries_barrier_9_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_hi_hi_lo; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_hi_lo = _GEN_9; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_hi_lo_1 = _GEN_9; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_hi_lo; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_hi_lo = _GEN_9; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_hi_lo_1 = _GEN_9; // @[package.scala:45:27] wire [1:0] _GEN_10 = {_pma_checker_entries_barrier_12_io_y_u, _pma_checker_entries_barrier_11_io_y_u}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_priv_rw_ok_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_hi_hi = _GEN_10; // @[package.scala:45:27] wire [1:0] pma_checker_priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27] assign pma_checker_priv_rw_ok_hi_hi_hi_1 = _GEN_10; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_hi_hi = _GEN_10; // @[package.scala:45:27] wire [1:0] pma_checker_priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27] assign pma_checker_priv_x_ok_hi_hi_hi_1 = _GEN_10; // @[package.scala:45:27] wire [3:0] pma_checker_priv_rw_ok_hi_hi = {pma_checker_priv_rw_ok_hi_hi_hi, pma_checker_priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_priv_rw_ok_hi = {pma_checker_priv_rw_ok_hi_hi, pma_checker_priv_rw_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_2 = {pma_checker_priv_rw_ok_hi, pma_checker_priv_rw_ok_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_3 = pma_checker__priv_rw_ok_T_1 ? pma_checker__priv_rw_ok_T_2 : 13'h0; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_lo_lo_1 = {pma_checker_priv_rw_ok_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_priv_rw_ok_lo_hi_1 = {pma_checker_priv_rw_ok_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_priv_rw_ok_lo_1 = {pma_checker_priv_rw_ok_lo_hi_1, pma_checker_priv_rw_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] pma_checker_priv_rw_ok_hi_lo_1 = {pma_checker_priv_rw_ok_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_priv_rw_ok_hi_hi_1 = {pma_checker_priv_rw_ok_hi_hi_hi_1, pma_checker_priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] pma_checker_priv_rw_ok_hi_1 = {pma_checker_priv_rw_ok_hi_hi_1, pma_checker_priv_rw_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_4 = {pma_checker_priv_rw_ok_hi_1, pma_checker_priv_rw_ok_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_5 = ~pma_checker__priv_rw_ok_T_4; // @[package.scala:45:27] wire [12:0] pma_checker__priv_rw_ok_T_6 = pma_checker_priv_s ? pma_checker__priv_rw_ok_T_5 : 13'h0; // @[TLB.scala:370:20, :513:{75,84}] wire [12:0] pma_checker_priv_rw_ok = pma_checker__priv_rw_ok_T_3 \| pma_checker__priv_rw_ok_T_6; // @[TLB.scala:513:{23,70,75}] wire [2:0] pma_checker_priv_x_ok_lo_lo = {pma_checker_priv_x_ok_lo_lo_hi, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_priv_x_ok_lo_hi = {pma_checker_priv_x_ok_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_priv_x_ok_lo = {pma_checker_priv_x_ok_lo_hi, pma_checker_priv_x_ok_lo_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_priv_x_ok_hi_lo = {pma_checker_priv_x_ok_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_priv_x_ok_hi_hi = {pma_checker_priv_x_ok_hi_hi_hi, pma_checker_priv_x_ok_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_priv_x_ok_hi = {pma_checker_priv_x_ok_hi_hi, pma_checker_priv_x_ok_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_x_ok_T = {pma_checker_priv_x_ok_hi, pma_checker_priv_x_ok_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_x_ok_T_1 = ~pma_checker__priv_x_ok_T; // @[package.scala:45:27] wire [2:0] pma_checker_priv_x_ok_lo_lo_1 = {pma_checker_priv_x_ok_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_priv_x_ok_lo_hi_1 = {pma_checker_priv_x_ok_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_priv_x_ok_lo_1 = {pma_checker_priv_x_ok_lo_hi_1, pma_checker_priv_x_ok_lo_lo_1}; // @[package.scala:45:27] wire [2:0] pma_checker_priv_x_ok_hi_lo_1 = {pma_checker_priv_x_ok_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_priv_x_ok_hi_hi_1 = {pma_checker_priv_x_ok_hi_hi_hi_1, pma_checker_priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] pma_checker_priv_x_ok_hi_1 = {pma_checker_priv_x_ok_hi_hi_1, pma_checker_priv_x_ok_hi_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__priv_x_ok_T_2 = {pma_checker_priv_x_ok_hi_1, pma_checker_priv_x_ok_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker_priv_x_ok = pma_checker_priv_s ? pma_checker__priv_x_ok_T_1 : pma_checker__priv_x_ok_T_2; // @[package.scala:45:27] wire [1:0] pma_checker_stage1_bypass_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ae_stage2, _pma_checker_entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_stage1_bypass_lo_lo = {pma_checker_stage1_bypass_lo_lo_hi, _pma_checker_entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_stage1_bypass_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ae_stage2, _pma_checker_entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_stage1_bypass_lo_hi = {pma_checker_stage1_bypass_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_stage1_bypass_lo = {pma_checker_stage1_bypass_lo_hi, pma_checker_stage1_bypass_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_stage1_bypass_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ae_stage2, _pma_checker_entries_barrier_7_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_stage1_bypass_hi_lo = {pma_checker_stage1_bypass_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_stage1_bypass_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_ae_stage2, _pma_checker_entries_barrier_9_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_stage1_bypass_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_ae_stage2, _pma_checker_entries_barrier_11_io_y_ae_stage2}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_stage1_bypass_hi_hi = {pma_checker_stage1_bypass_hi_hi_hi, pma_checker_stage1_bypass_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_stage1_bypass_hi = {pma_checker_stage1_bypass_hi_hi, pma_checker_stage1_bypass_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__stage1_bypass_T_3 = {pma_checker_stage1_bypass_hi, pma_checker_stage1_bypass_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_r_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_sr, _pma_checker_entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_r_array_lo_lo = {pma_checker_r_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_sr, _pma_checker_entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_r_array_lo_hi = {pma_checker_r_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_r_array_lo = {pma_checker_r_array_lo_hi, pma_checker_r_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_r_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_sr, _pma_checker_entries_barrier_7_io_y_sr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_r_array_hi_lo = {pma_checker_r_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_sr, _pma_checker_entries_barrier_9_io_y_sr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_sr, _pma_checker_entries_barrier_11_io_y_sr}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_r_array_hi_hi = {pma_checker_r_array_hi_hi_hi, pma_checker_r_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_r_array_hi = {pma_checker_r_array_hi_hi, pma_checker_r_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__r_array_T = {pma_checker_r_array_hi, pma_checker_r_array_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__r_array_T_3 = pma_checker__r_array_T; // @[package.scala:45:27] wire [1:0] _GEN_11 = {_pma_checker_entries_barrier_2_io_y_sx, _pma_checker_entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_lo_lo_hi_1; // @[package.scala:45:27] assign pma_checker_r_array_lo_lo_hi_1 = _GEN_11; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_x_array_lo_lo_hi = _GEN_11; // @[package.scala:45:27] wire [2:0] pma_checker_r_array_lo_lo_1 = {pma_checker_r_array_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_12 = {_pma_checker_entries_barrier_5_io_y_sx, _pma_checker_entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_lo_hi_hi_1; // @[package.scala:45:27] assign pma_checker_r_array_lo_hi_hi_1 = _GEN_12; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_x_array_lo_hi_hi = _GEN_12; // @[package.scala:45:27] wire [2:0] pma_checker_r_array_lo_hi_1 = {pma_checker_r_array_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_r_array_lo_1 = {pma_checker_r_array_lo_hi_1, pma_checker_r_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_13 = {_pma_checker_entries_barrier_8_io_y_sx, _pma_checker_entries_barrier_7_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_lo_hi_1; // @[package.scala:45:27] assign pma_checker_r_array_hi_lo_hi_1 = _GEN_13; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_x_array_hi_lo_hi = _GEN_13; // @[package.scala:45:27] wire [2:0] pma_checker_r_array_hi_lo_1 = {pma_checker_r_array_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_14 = {_pma_checker_entries_barrier_10_io_y_sx, _pma_checker_entries_barrier_9_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_hi_lo_1; // @[package.scala:45:27] assign pma_checker_r_array_hi_hi_lo_1 = _GEN_14; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_hi_hi_lo; // @[package.scala:45:27] assign pma_checker_x_array_hi_hi_lo = _GEN_14; // @[package.scala:45:27] wire [1:0] _GEN_15 = {_pma_checker_entries_barrier_12_io_y_sx, _pma_checker_entries_barrier_11_io_y_sx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_r_array_hi_hi_hi_1; // @[package.scala:45:27] assign pma_checker_r_array_hi_hi_hi_1 = _GEN_15; // @[package.scala:45:27] wire [1:0] pma_checker_x_array_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_x_array_hi_hi_hi = _GEN_15; // @[package.scala:45:27] wire [3:0] pma_checker_r_array_hi_hi_1 = {pma_checker_r_array_hi_hi_hi_1, pma_checker_r_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] pma_checker_r_array_hi_1 = {pma_checker_r_array_hi_hi_1, pma_checker_r_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__r_array_T_1 = {pma_checker_r_array_hi_1, pma_checker_r_array_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__r_array_T_4 = pma_checker_priv_rw_ok & pma_checker__r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}] wire [12:0] pma_checker__r_array_T_5 = pma_checker__r_array_T_4; // @[TLB.scala:520:{41,113}] wire [13:0] pma_checker_r_array = {1'h1, pma_checker__r_array_T_5}; // @[TLB.scala:520:{20,113}] wire [13:0] pma_checker__pf_ld_array_T = pma_checker_r_array; // @[TLB.scala:520:20, :597:41] wire [1:0] pma_checker_w_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_sw, _pma_checker_entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_w_array_lo_lo = {pma_checker_w_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_w_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_sw, _pma_checker_entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_w_array_lo_hi = {pma_checker_w_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_w_array_lo = {pma_checker_w_array_lo_hi, pma_checker_w_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_w_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_sw, _pma_checker_entries_barrier_7_io_y_sw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_w_array_hi_lo = {pma_checker_w_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_w_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_sw, _pma_checker_entries_barrier_9_io_y_sw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_w_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_sw, _pma_checker_entries_barrier_11_io_y_sw}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_w_array_hi_hi = {pma_checker_w_array_hi_hi_hi, pma_checker_w_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_w_array_hi = {pma_checker_w_array_hi_hi, pma_checker_w_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__w_array_T = {pma_checker_w_array_hi, pma_checker_w_array_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__w_array_T_1 = pma_checker_priv_rw_ok & pma_checker__w_array_T; // @[package.scala:45:27] wire [12:0] pma_checker__w_array_T_2 = pma_checker__w_array_T_1; // @[TLB.scala:521:{41,69}] wire [13:0] pma_checker_w_array = {1'h1, pma_checker__w_array_T_2}; // @[TLB.scala:521:{20,69}] wire [2:0] pma_checker_x_array_lo_lo = {pma_checker_x_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_x_array_lo_hi = {pma_checker_x_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_x_array_lo = {pma_checker_x_array_lo_hi, pma_checker_x_array_lo_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_x_array_hi_lo = {pma_checker_x_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_x_array_hi_hi = {pma_checker_x_array_hi_hi_hi, pma_checker_x_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_x_array_hi = {pma_checker_x_array_hi_hi, pma_checker_x_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__x_array_T = {pma_checker_x_array_hi, pma_checker_x_array_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__x_array_T_1 = pma_checker_priv_x_ok & pma_checker__x_array_T; // @[package.scala:45:27] wire [12:0] pma_checker__x_array_T_2 = pma_checker__x_array_T_1; // @[TLB.scala:522:{40,68}] wire [13:0] pma_checker_x_array = {1'h1, pma_checker__x_array_T_2}; // @[TLB.scala:522:{20,68}] wire [1:0] pma_checker_hr_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_hr, _pma_checker_entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hr_array_lo_lo = {pma_checker_hr_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_hr, _pma_checker_entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hr_array_lo_hi = {pma_checker_hr_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_hr_array_lo = {pma_checker_hr_array_lo_hi, pma_checker_hr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_hr_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_hr, _pma_checker_entries_barrier_7_io_y_hr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hr_array_hi_lo = {pma_checker_hr_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_hr, _pma_checker_entries_barrier_9_io_y_hr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_hr, _pma_checker_entries_barrier_11_io_y_hr}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_hr_array_hi_hi = {pma_checker_hr_array_hi_hi_hi, pma_checker_hr_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_hr_array_hi = {pma_checker_hr_array_hi_hi, pma_checker_hr_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__hr_array_T = {pma_checker_hr_array_hi, pma_checker_hr_array_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__hr_array_T_3 = pma_checker__hr_array_T; // @[package.scala:45:27] wire [1:0] _GEN_16 = {_pma_checker_entries_barrier_2_io_y_hx, _pma_checker_entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_lo_lo_hi_1; // @[package.scala:45:27] assign pma_checker_hr_array_lo_lo_hi_1 = _GEN_16; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_hx_array_lo_lo_hi = _GEN_16; // @[package.scala:45:27] wire [2:0] pma_checker_hr_array_lo_lo_1 = {pma_checker_hr_array_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_17 = {_pma_checker_entries_barrier_5_io_y_hx, _pma_checker_entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_lo_hi_hi_1; // @[package.scala:45:27] assign pma_checker_hr_array_lo_hi_hi_1 = _GEN_17; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_hx_array_lo_hi_hi = _GEN_17; // @[package.scala:45:27] wire [2:0] pma_checker_hr_array_lo_hi_1 = {pma_checker_hr_array_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_hr_array_lo_1 = {pma_checker_hr_array_lo_hi_1, pma_checker_hr_array_lo_lo_1}; // @[package.scala:45:27] wire [1:0] _GEN_18 = {_pma_checker_entries_barrier_8_io_y_hx, _pma_checker_entries_barrier_7_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_lo_hi_1; // @[package.scala:45:27] assign pma_checker_hr_array_hi_lo_hi_1 = _GEN_18; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_hx_array_hi_lo_hi = _GEN_18; // @[package.scala:45:27] wire [2:0] pma_checker_hr_array_hi_lo_1 = {pma_checker_hr_array_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_19 = {_pma_checker_entries_barrier_10_io_y_hx, _pma_checker_entries_barrier_9_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_hi_lo_1; // @[package.scala:45:27] assign pma_checker_hr_array_hi_hi_lo_1 = _GEN_19; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_hi_hi_lo; // @[package.scala:45:27] assign pma_checker_hx_array_hi_hi_lo = _GEN_19; // @[package.scala:45:27] wire [1:0] _GEN_20 = {_pma_checker_entries_barrier_12_io_y_hx, _pma_checker_entries_barrier_11_io_y_hx}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hr_array_hi_hi_hi_1; // @[package.scala:45:27] assign pma_checker_hr_array_hi_hi_hi_1 = _GEN_20; // @[package.scala:45:27] wire [1:0] pma_checker_hx_array_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_hx_array_hi_hi_hi = _GEN_20; // @[package.scala:45:27] wire [3:0] pma_checker_hr_array_hi_hi_1 = {pma_checker_hr_array_hi_hi_hi_1, pma_checker_hr_array_hi_hi_lo_1}; // @[package.scala:45:27] wire [6:0] pma_checker_hr_array_hi_1 = {pma_checker_hr_array_hi_hi_1, pma_checker_hr_array_hi_lo_1}; // @[package.scala:45:27] wire [12:0] pma_checker__hr_array_T_1 = {pma_checker_hr_array_hi_1, pma_checker_hr_array_lo_1}; // @[package.scala:45:27] wire [1:0] pma_checker_hw_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_hw, _pma_checker_entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hw_array_lo_lo = {pma_checker_hw_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hw_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_hw, _pma_checker_entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hw_array_lo_hi = {pma_checker_hw_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_hw_array_lo = {pma_checker_hw_array_lo_hi, pma_checker_hw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_hw_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_hw, _pma_checker_entries_barrier_7_io_y_hw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hw_array_hi_lo = {pma_checker_hw_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hw_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_hw, _pma_checker_entries_barrier_9_io_y_hw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_hw_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_hw, _pma_checker_entries_barrier_11_io_y_hw}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_hw_array_hi_hi = {pma_checker_hw_array_hi_hi_hi, pma_checker_hw_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_hw_array_hi = {pma_checker_hw_array_hi_hi, pma_checker_hw_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__hw_array_T = {pma_checker_hw_array_hi, pma_checker_hw_array_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_hx_array_lo_lo = {pma_checker_hx_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_hx_array_lo_hi = {pma_checker_hx_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_hx_array_lo = {pma_checker_hx_array_lo_hi, pma_checker_hx_array_lo_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_hx_array_hi_lo = {pma_checker_hx_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25] wire [3:0] pma_checker_hx_array_hi_hi = {pma_checker_hx_array_hi_hi_hi, pma_checker_hx_array_hi_hi_lo}; // @[package.scala:45:27] wire [6:0] pma_checker_hx_array_hi = {pma_checker_hx_array_hi_hi, pma_checker_hx_array_hi_lo}; // @[package.scala:45:27] wire [12:0] pma_checker__hx_array_T = {pma_checker_hx_array_hi, pma_checker_hx_array_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_pr_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pr, _pma_checker_entries_barrier_1_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pr_array_lo_lo = {pma_checker_pr_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pr_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pr, _pma_checker_entries_barrier_4_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pr_array_lo_hi = {pma_checker_pr_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pr_array_lo = {pma_checker_pr_array_lo_hi, pma_checker_pr_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_pr_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pr, _pma_checker_entries_barrier_7_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pr_array_hi_lo = {pma_checker_pr_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pr}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pr_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_pr, _pma_checker_entries_barrier_10_io_y_pr}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pr_array_hi_hi = {pma_checker_pr_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_pr}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pr_array_hi = {pma_checker_pr_array_hi_hi, pma_checker_pr_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__pr_array_T_1 = {pma_checker_pr_array_hi, pma_checker_pr_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker__pr_array_T_2 = {2'h0, pma_checker__pr_array_T_1}; // @[package.scala:45:27] wire [13:0] _GEN_21 = pma_checker_ptw_ae_array \| pma_checker_final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104] wire [13:0] pma_checker__pr_array_T_3; // @[TLB.scala:529:104] assign pma_checker__pr_array_T_3 = _GEN_21; // @[TLB.scala:529:104] wire [13:0] pma_checker__pw_array_T_3; // @[TLB.scala:531:104] assign pma_checker__pw_array_T_3 = _GEN_21; // @[TLB.scala:529:104, :531:104] wire [13:0] pma_checker__px_array_T_3; // @[TLB.scala:533:104] assign pma_checker__px_array_T_3 = _GEN_21; // @[TLB.scala:529:104, :533:104] wire [13:0] pma_checker__pr_array_T_4 = ~pma_checker__pr_array_T_3; // @[TLB.scala:529:{89,104}] wire [13:0] pma_checker_pr_array = pma_checker__pr_array_T_2 & pma_checker__pr_array_T_4; // @[TLB.scala:529:{21,87,89}] wire [1:0] pma_checker_pw_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pw, _pma_checker_entries_barrier_1_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pw_array_lo_lo = {pma_checker_pw_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pw_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pw, _pma_checker_entries_barrier_4_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pw_array_lo_hi = {pma_checker_pw_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pw_array_lo = {pma_checker_pw_array_lo_hi, pma_checker_pw_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_pw_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pw, _pma_checker_entries_barrier_7_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pw_array_hi_lo = {pma_checker_pw_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pw}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pw_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_pw, _pma_checker_entries_barrier_10_io_y_pw}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pw_array_hi_hi = {pma_checker_pw_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_pw}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pw_array_hi = {pma_checker_pw_array_hi_hi, pma_checker_pw_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__pw_array_T_1 = {pma_checker_pw_array_hi, pma_checker_pw_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker__pw_array_T_2 = {2'h0, pma_checker__pw_array_T_1}; // @[package.scala:45:27] wire [13:0] pma_checker__pw_array_T_4 = ~pma_checker__pw_array_T_3; // @[TLB.scala:531:{89,104}] wire [13:0] pma_checker_pw_array = pma_checker__pw_array_T_2 & pma_checker__pw_array_T_4; // @[TLB.scala:531:{21,87,89}] wire [1:0] pma_checker_px_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_px, _pma_checker_entries_barrier_1_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_px_array_lo_lo = {pma_checker_px_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_px_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_px, _pma_checker_entries_barrier_4_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_px_array_lo_hi = {pma_checker_px_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_px_array_lo = {pma_checker_px_array_lo_hi, pma_checker_px_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_px_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_px, _pma_checker_entries_barrier_7_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_px_array_hi_lo = {pma_checker_px_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_px}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_px_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_px, _pma_checker_entries_barrier_10_io_y_px}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_px_array_hi_hi = {pma_checker_px_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_px}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_px_array_hi = {pma_checker_px_array_hi_hi, pma_checker_px_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__px_array_T_1 = {pma_checker_px_array_hi, pma_checker_px_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker__px_array_T_2 = {2'h0, pma_checker__px_array_T_1}; // @[package.scala:45:27] wire [13:0] pma_checker__px_array_T_4 = ~pma_checker__px_array_T_3; // @[TLB.scala:533:{89,104}] wire [13:0] pma_checker_px_array = pma_checker__px_array_T_2 & pma_checker__px_array_T_4; // @[TLB.scala:533:{21,87,89}] wire [1:0] pma_checker__eff_array_T = {2{_pma_checker_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27] wire [1:0] pma_checker_eff_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_eff, _pma_checker_entries_barrier_1_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_eff_array_lo_lo = {pma_checker_eff_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_eff_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_eff, _pma_checker_entries_barrier_4_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_eff_array_lo_hi = {pma_checker_eff_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_eff_array_lo = {pma_checker_eff_array_lo_hi, pma_checker_eff_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_eff_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_eff, _pma_checker_entries_barrier_7_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_eff_array_hi_lo = {pma_checker_eff_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_eff}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_eff_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_eff, _pma_checker_entries_barrier_10_io_y_eff}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_eff_array_hi_hi = {pma_checker_eff_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_eff}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_eff_array_hi = {pma_checker_eff_array_hi_hi, pma_checker_eff_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__eff_array_T_1 = {pma_checker_eff_array_hi, pma_checker_eff_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_eff_array = {pma_checker__eff_array_T, pma_checker__eff_array_T_1}; // @[package.scala:45:27] wire [1:0] pma_checker__c_array_T = {2{pma_checker_cacheable}}; // @[TLB.scala:425:41, :537:25] wire [1:0] _GEN_22 = {_pma_checker_entries_barrier_2_io_y_c, _pma_checker_entries_barrier_1_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_c_array_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_c_array_lo_lo_hi = _GEN_22; // @[package.scala:45:27] wire [1:0] pma_checker_prefetchable_array_lo_lo_hi; // @[package.scala:45:27] assign pma_checker_prefetchable_array_lo_lo_hi = _GEN_22; // @[package.scala:45:27] wire [2:0] pma_checker_c_array_lo_lo = {pma_checker_c_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_23 = {_pma_checker_entries_barrier_5_io_y_c, _pma_checker_entries_barrier_4_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_c_array_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_c_array_lo_hi_hi = _GEN_23; // @[package.scala:45:27] wire [1:0] pma_checker_prefetchable_array_lo_hi_hi; // @[package.scala:45:27] assign pma_checker_prefetchable_array_lo_hi_hi = _GEN_23; // @[package.scala:45:27] wire [2:0] pma_checker_c_array_lo_hi = {pma_checker_c_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_c_array_lo = {pma_checker_c_array_lo_hi, pma_checker_c_array_lo_lo}; // @[package.scala:45:27] wire [1:0] _GEN_24 = {_pma_checker_entries_barrier_8_io_y_c, _pma_checker_entries_barrier_7_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_c_array_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_c_array_hi_lo_hi = _GEN_24; // @[package.scala:45:27] wire [1:0] pma_checker_prefetchable_array_hi_lo_hi; // @[package.scala:45:27] assign pma_checker_prefetchable_array_hi_lo_hi = _GEN_24; // @[package.scala:45:27] wire [2:0] pma_checker_c_array_hi_lo = {pma_checker_c_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] _GEN_25 = {_pma_checker_entries_barrier_11_io_y_c, _pma_checker_entries_barrier_10_io_y_c}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_c_array_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_c_array_hi_hi_hi = _GEN_25; // @[package.scala:45:27] wire [1:0] pma_checker_prefetchable_array_hi_hi_hi; // @[package.scala:45:27] assign pma_checker_prefetchable_array_hi_hi_hi = _GEN_25; // @[package.scala:45:27] wire [2:0] pma_checker_c_array_hi_hi = {pma_checker_c_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_c_array_hi = {pma_checker_c_array_hi_hi, pma_checker_c_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__c_array_T_1 = {pma_checker_c_array_hi, pma_checker_c_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_c_array = {pma_checker__c_array_T, pma_checker__c_array_T_1}; // @[package.scala:45:27] wire [13:0] pma_checker_lrscAllowed = pma_checker_c_array; // @[TLB.scala:537:20, :580:24] wire [1:0] pma_checker__ppp_array_T = {2{_pma_checker_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27] wire [1:0] pma_checker_ppp_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ppp, _pma_checker_entries_barrier_1_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ppp_array_lo_lo = {pma_checker_ppp_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ppp_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ppp, _pma_checker_entries_barrier_4_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ppp_array_lo_hi = {pma_checker_ppp_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ppp_array_lo = {pma_checker_ppp_array_lo_hi, pma_checker_ppp_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_ppp_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ppp, _pma_checker_entries_barrier_7_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ppp_array_hi_lo = {pma_checker_ppp_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_ppp_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_ppp, _pma_checker_entries_barrier_10_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_ppp_array_hi_hi = {pma_checker_ppp_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_ppp}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_ppp_array_hi = {pma_checker_ppp_array_hi_hi, pma_checker_ppp_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__ppp_array_T_1 = {pma_checker_ppp_array_hi, pma_checker_ppp_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_ppp_array = {pma_checker__ppp_array_T, pma_checker__ppp_array_T_1}; // @[package.scala:45:27] wire [1:0] pma_checker__paa_array_T = {2{_pma_checker_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27] wire [1:0] pma_checker_paa_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_paa, _pma_checker_entries_barrier_1_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_paa_array_lo_lo = {pma_checker_paa_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_paa_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_paa, _pma_checker_entries_barrier_4_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_paa_array_lo_hi = {pma_checker_paa_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_paa_array_lo = {pma_checker_paa_array_lo_hi, pma_checker_paa_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_paa_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_paa, _pma_checker_entries_barrier_7_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_paa_array_hi_lo = {pma_checker_paa_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_paa}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_paa_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_paa, _pma_checker_entries_barrier_10_io_y_paa}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_paa_array_hi_hi = {pma_checker_paa_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_paa}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_paa_array_hi = {pma_checker_paa_array_hi_hi, pma_checker_paa_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__paa_array_T_1 = {pma_checker_paa_array_hi, pma_checker_paa_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_paa_array = {pma_checker__paa_array_T, pma_checker__paa_array_T_1}; // @[package.scala:45:27] wire [1:0] pma_checker__pal_array_T = {2{_pma_checker_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27] wire [1:0] pma_checker_pal_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pal, _pma_checker_entries_barrier_1_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pal_array_lo_lo = {pma_checker_pal_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pal_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pal, _pma_checker_entries_barrier_4_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pal_array_lo_hi = {pma_checker_pal_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pal_array_lo = {pma_checker_pal_array_lo_hi, pma_checker_pal_array_lo_lo}; // @[package.scala:45:27] wire [1:0] pma_checker_pal_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pal, _pma_checker_entries_barrier_7_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pal_array_hi_lo = {pma_checker_pal_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pal}; // @[package.scala:45:27, :267:25] wire [1:0] pma_checker_pal_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_pal, _pma_checker_entries_barrier_10_io_y_pal}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_pal_array_hi_hi = {pma_checker_pal_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_pal}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_pal_array_hi = {pma_checker_pal_array_hi_hi, pma_checker_pal_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__pal_array_T_1 = {pma_checker_pal_array_hi, pma_checker_pal_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_pal_array = {pma_checker__pal_array_T, pma_checker__pal_array_T_1}; // @[package.scala:45:27] wire [13:0] pma_checker_ppp_array_if_cached = pma_checker_ppp_array \| pma_checker_c_array; // @[TLB.scala:537:20, :539:22, :544:39] wire [13:0] pma_checker_paa_array_if_cached = pma_checker_paa_array \| pma_checker_c_array; // @[TLB.scala:537:20, :541:22, :545:39] wire [13:0] pma_checker_pal_array_if_cached = pma_checker_pal_array \| pma_checker_c_array; // @[TLB.scala:537:20, :543:22, :546:39] wire pma_checker__prefetchable_array_T = pma_checker_cacheable & pma_checker_homogeneous; // @[TLBPermissions.scala:101:65] wire [1:0] pma_checker__prefetchable_array_T_1 = {pma_checker__prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}] wire [2:0] pma_checker_prefetchable_array_lo_lo = {pma_checker_prefetchable_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_prefetchable_array_lo_hi = {pma_checker_prefetchable_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_prefetchable_array_lo = {pma_checker_prefetchable_array_lo_hi, pma_checker_prefetchable_array_lo_lo}; // @[package.scala:45:27] wire [2:0] pma_checker_prefetchable_array_hi_lo = {pma_checker_prefetchable_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25] wire [2:0] pma_checker_prefetchable_array_hi_hi = {pma_checker_prefetchable_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25] wire [5:0] pma_checker_prefetchable_array_hi = {pma_checker_prefetchable_array_hi_hi, pma_checker_prefetchable_array_hi_lo}; // @[package.scala:45:27] wire [11:0] pma_checker__prefetchable_array_T_2 = {pma_checker_prefetchable_array_hi, pma_checker_prefetchable_array_lo}; // @[package.scala:45:27] wire [13:0] pma_checker_prefetchable_array = {pma_checker__prefetchable_array_T_1, pma_checker__prefetchable_array_T_2}; // @[package.scala:45:27] wire [3:0] pma_checker__misaligned_T = 4'h1 << pma_checker_io_req_bits_size; // @[OneHot.scala:58:35] wire [4:0] pma_checker__misaligned_T_1 = {1'h0, pma_checker__misaligned_T} - 5'h1; // @[OneHot.scala:58:35] wire [3:0] pma_checker__misaligned_T_2 = pma_checker__misaligned_T_1[3:0]; // @[TLB.scala:550:69] wire [39:0] pma_checker__misaligned_T_3 = {36'h0, pma_checker_io_req_bits_vaddr[3:0] & pma_checker__misaligned_T_2}; // @[TLB.scala:550:{39,69}] wire pma_checker_misaligned = \|pma_checker__misaligned_T_3; // @[TLB.scala:550:{39,77}] wire [39:0] pma_checker_bad_va_maskedVAddr = pma_checker_io_req_bits_vaddr & 40'hC000000000; // @[TLB.scala:559:43] wire pma_checker__bad_va_T_2 = pma_checker_bad_va_maskedVAddr == 40'h0; // @[TLB.scala:559:43, :560:51] wire pma_checker__bad_va_T_3 = pma_checker_bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86] wire pma_checker__bad_va_T_4 = pma_checker__bad_va_T_3; // @[TLB.scala:560:{71,86}] wire pma_checker__bad_va_T_5 = pma_checker__bad_va_T_2 \| pma_checker__bad_va_T_4; // @[TLB.scala:560:{51,59,71}] wire pma_checker__bad_va_T_6 = ~pma_checker__bad_va_T_5; // @[TLB.scala:560:{37,59}] wire pma_checker__bad_va_T_7 = pma_checker__bad_va_T_6; // @[TLB.scala:560:{34,37}] wire _GEN_26 = pma_checker_io_req_bits_cmd == 5'h6; // @[package.scala:16:47] wire pma_checker__cmd_lrsc_T; // @[package.scala:16:47] assign pma_checker__cmd_lrsc_T = _GEN_26; // @[package.scala:16:47] wire pma_checker__cmd_read_T_2; // @[package.scala:16:47] assign pma_checker__cmd_read_T_2 = _GEN_26; // @[package.scala:16:47] wire _GEN_27 = pma_checker_io_req_bits_cmd == 5'h7; // @[package.scala:16:47] wire pma_checker__cmd_lrsc_T_1; // @[package.scala:16:47] assign pma_checker__cmd_lrsc_T_1 = _GEN_27; // @[package.scala:16:47] wire pma_checker__cmd_read_T_3; // @[package.scala:16:47] assign pma_checker__cmd_read_T_3 = _GEN_27; // @[package.scala:16:47] wire pma_checker__cmd_write_T_3; // @[Consts.scala:90:66] assign pma_checker__cmd_write_T_3 = _GEN_27; // @[package.scala:16:47] wire pma_checker__cmd_lrsc_T_2 = pma_checker__cmd_lrsc_T \| pma_checker__cmd_lrsc_T_1; // @[package.scala:16:47, :81:59] wire pma_checker_cmd_lrsc = pma_checker__cmd_lrsc_T_2; // @[package.scala:81:59] wire _GEN_28 = pma_checker_io_req_bits_cmd == 5'h4; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T; // @[package.scala:16:47] assign pma_checker__cmd_amo_logical_T = _GEN_28; // @[package.scala:16:47] wire pma_checker__cmd_read_T_7; // @[package.scala:16:47] assign pma_checker__cmd_read_T_7 = _GEN_28; // @[package.scala:16:47] wire pma_checker__cmd_write_T_5; // @[package.scala:16:47] assign pma_checker__cmd_write_T_5 = _GEN_28; // @[package.scala:16:47] wire _GEN_29 = pma_checker_io_req_bits_cmd == 5'h9; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T_1; // @[package.scala:16:47] assign pma_checker__cmd_amo_logical_T_1 = _GEN_29; // @[package.scala:16:47] wire pma_checker__cmd_read_T_8; // @[package.scala:16:47] assign pma_checker__cmd_read_T_8 = _GEN_29; // @[package.scala:16:47] wire pma_checker__cmd_write_T_6; // @[package.scala:16:47] assign pma_checker__cmd_write_T_6 = _GEN_29; // @[package.scala:16:47] wire _GEN_30 = pma_checker_io_req_bits_cmd == 5'hA; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T_2; // @[package.scala:16:47] assign pma_checker__cmd_amo_logical_T_2 = _GEN_30; // @[package.scala:16:47] wire pma_checker__cmd_read_T_9; // @[package.scala:16:47] assign pma_checker__cmd_read_T_9 = _GEN_30; // @[package.scala:16:47] wire pma_checker__cmd_write_T_7; // @[package.scala:16:47] assign pma_checker__cmd_write_T_7 = _GEN_30; // @[package.scala:16:47] wire _GEN_31 = pma_checker_io_req_bits_cmd == 5'hB; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T_3; // @[package.scala:16:47] assign pma_checker__cmd_amo_logical_T_3 = _GEN_31; // @[package.scala:16:47] wire pma_checker__cmd_read_T_10; // @[package.scala:16:47] assign pma_checker__cmd_read_T_10 = _GEN_31; // @[package.scala:16:47] wire pma_checker__cmd_write_T_8; // @[package.scala:16:47] assign pma_checker__cmd_write_T_8 = _GEN_31; // @[package.scala:16:47] wire pma_checker__cmd_amo_logical_T_4 = pma_checker__cmd_amo_logical_T \| pma_checker__cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_logical_T_5 = pma_checker__cmd_amo_logical_T_4 \| pma_checker__cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_logical_T_6 = pma_checker__cmd_amo_logical_T_5 \| pma_checker__cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59] wire pma_checker_cmd_amo_logical = pma_checker__cmd_amo_logical_T_6; // @[package.scala:81:59] wire _GEN_32 = pma_checker_io_req_bits_cmd == 5'h8; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T = _GEN_32; // @[package.scala:16:47] wire pma_checker__cmd_read_T_14; // @[package.scala:16:47] assign pma_checker__cmd_read_T_14 = _GEN_32; // @[package.scala:16:47] wire pma_checker__cmd_write_T_12; // @[package.scala:16:47] assign pma_checker__cmd_write_T_12 = _GEN_32; // @[package.scala:16:47] wire _GEN_33 = pma_checker_io_req_bits_cmd == 5'hC; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_1; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T_1 = _GEN_33; // @[package.scala:16:47] wire pma_checker__cmd_read_T_15; // @[package.scala:16:47] assign pma_checker__cmd_read_T_15 = _GEN_33; // @[package.scala:16:47] wire pma_checker__cmd_write_T_13; // @[package.scala:16:47] assign pma_checker__cmd_write_T_13 = _GEN_33; // @[package.scala:16:47] wire _GEN_34 = pma_checker_io_req_bits_cmd == 5'hD; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_2; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T_2 = _GEN_34; // @[package.scala:16:47] wire pma_checker__cmd_read_T_16; // @[package.scala:16:47] assign pma_checker__cmd_read_T_16 = _GEN_34; // @[package.scala:16:47] wire pma_checker__cmd_write_T_14; // @[package.scala:16:47] assign pma_checker__cmd_write_T_14 = _GEN_34; // @[package.scala:16:47] wire _GEN_35 = pma_checker_io_req_bits_cmd == 5'hE; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_3; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T_3 = _GEN_35; // @[package.scala:16:47] wire pma_checker__cmd_read_T_17; // @[package.scala:16:47] assign pma_checker__cmd_read_T_17 = _GEN_35; // @[package.scala:16:47] wire pma_checker__cmd_write_T_15; // @[package.scala:16:47] assign pma_checker__cmd_write_T_15 = _GEN_35; // @[package.scala:16:47] wire _GEN_36 = pma_checker_io_req_bits_cmd == 5'hF; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_4; // @[package.scala:16:47] assign pma_checker__cmd_amo_arithmetic_T_4 = _GEN_36; // @[package.scala:16:47] wire pma_checker__cmd_read_T_18; // @[package.scala:16:47] assign pma_checker__cmd_read_T_18 = _GEN_36; // @[package.scala:16:47] wire pma_checker__cmd_write_T_16; // @[package.scala:16:47] assign pma_checker__cmd_write_T_16 = _GEN_36; // @[package.scala:16:47] wire pma_checker__cmd_amo_arithmetic_T_5 = pma_checker__cmd_amo_arithmetic_T \| pma_checker__cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_arithmetic_T_6 = pma_checker__cmd_amo_arithmetic_T_5 \| pma_checker__cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_arithmetic_T_7 = pma_checker__cmd_amo_arithmetic_T_6 \| pma_checker__cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_amo_arithmetic_T_8 = pma_checker__cmd_amo_arithmetic_T_7 \| pma_checker__cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59] wire pma_checker_cmd_amo_arithmetic = pma_checker__cmd_amo_arithmetic_T_8; // @[package.scala:81:59] wire _GEN_37 = pma_checker_io_req_bits_cmd == 5'h11; // @[TLB.scala:573:41] wire pma_checker_cmd_put_partial; // @[TLB.scala:573:41] assign pma_checker_cmd_put_partial = _GEN_37; // @[TLB.scala:573:41] wire pma_checker__cmd_write_T_1; // @[Consts.scala:90:49] assign pma_checker__cmd_write_T_1 = _GEN_37; // @[TLB.scala:573:41] wire pma_checker__cmd_read_T = pma_checker_io_req_bits_cmd == 5'h0; // @[package.scala:16:47] wire _GEN_38 = pma_checker_io_req_bits_cmd == 5'h10; // @[package.scala:16:47] wire pma_checker__cmd_read_T_1; // @[package.scala:16:47] assign pma_checker__cmd_read_T_1 = _GEN_38; // @[package.scala:16:47] wire pma_checker__cmd_readx_T; // @[TLB.scala:575:56] assign pma_checker__cmd_readx_T = _GEN_38; // @[package.scala:16:47] wire pma_checker__cmd_read_T_4 = pma_checker__cmd_read_T \| pma_checker__cmd_read_T_1; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_5 = pma_checker__cmd_read_T_4 \| pma_checker__cmd_read_T_2; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_6 = pma_checker__cmd_read_T_5 \| pma_checker__cmd_read_T_3; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_11 = pma_checker__cmd_read_T_7 \| pma_checker__cmd_read_T_8; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_12 = pma_checker__cmd_read_T_11 \| pma_checker__cmd_read_T_9; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_13 = pma_checker__cmd_read_T_12 \| pma_checker__cmd_read_T_10; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_19 = pma_checker__cmd_read_T_14 \| pma_checker__cmd_read_T_15; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_20 = pma_checker__cmd_read_T_19 \| pma_checker__cmd_read_T_16; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_21 = pma_checker__cmd_read_T_20 \| pma_checker__cmd_read_T_17; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_22 = pma_checker__cmd_read_T_21 \| pma_checker__cmd_read_T_18; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_read_T_23 = pma_checker__cmd_read_T_13 \| pma_checker__cmd_read_T_22; // @[package.scala:81:59] wire pma_checker_cmd_read = pma_checker__cmd_read_T_6 \| pma_checker__cmd_read_T_23; // @[package.scala:81:59] wire pma_checker__cmd_write_T = pma_checker_io_req_bits_cmd == 5'h1; // @[DCache.scala:120:32] wire pma_checker__cmd_write_T_2 = pma_checker__cmd_write_T \| pma_checker__cmd_write_T_1; // @[Consts.scala:90:{32,42,49}] wire pma_checker__cmd_write_T_4 = pma_checker__cmd_write_T_2 \| pma_checker__cmd_write_T_3; // @[Consts.scala:90:{42,59,66}] wire pma_checker__cmd_write_T_9 = pma_checker__cmd_write_T_5 \| pma_checker__cmd_write_T_6; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_10 = pma_checker__cmd_write_T_9 \| pma_checker__cmd_write_T_7; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_11 = pma_checker__cmd_write_T_10 \| pma_checker__cmd_write_T_8; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_17 = pma_checker__cmd_write_T_12 \| pma_checker__cmd_write_T_13; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_18 = pma_checker__cmd_write_T_17 \| pma_checker__cmd_write_T_14; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_19 = pma_checker__cmd_write_T_18 \| pma_checker__cmd_write_T_15; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_20 = pma_checker__cmd_write_T_19 \| pma_checker__cmd_write_T_16; // @[package.scala:16:47, :81:59] wire pma_checker__cmd_write_T_21 = pma_checker__cmd_write_T_11 \| pma_checker__cmd_write_T_20; // @[package.scala:81:59] wire pma_checker_cmd_write = pma_checker__cmd_write_T_4 \| pma_checker__cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire pma_checker__cmd_write_perms_T = pma_checker_io_req_bits_cmd == 5'h5; // @[package.scala:16:47] wire pma_checker__cmd_write_perms_T_1 = pma_checker_io_req_bits_cmd == 5'h17; // @[package.scala:16:47] wire pma_checker__cmd_write_perms_T_2 = pma_checker__cmd_write_perms_T \| pma_checker__cmd_write_perms_T_1; // @[package.scala:16:47, :81:59] wire pma_checker_cmd_write_perms = pma_checker_cmd_write \| pma_checker__cmd_write_perms_T_2; // @[package.scala:81:59] wire [13:0] pma_checker__ae_array_T = pma_checker_misaligned ? pma_checker_eff_array : 14'h0; // @[TLB.scala:535:22, :550:77, :582:8] wire [13:0] pma_checker__ae_array_T_1 = ~pma_checker_lrscAllowed; // @[TLB.scala:580:24, :583:19] wire [13:0] pma_checker__ae_array_T_2 = pma_checker_cmd_lrsc ? pma_checker__ae_array_T_1 : 14'h0; // @[TLB.scala:570:33, :583:{8,19}] wire [13:0] pma_checker_ae_array = pma_checker__ae_array_T \| pma_checker__ae_array_T_2; // @[TLB.scala:582:{8,37}, :583:8] wire [13:0] pma_checker__ae_ld_array_T = ~pma_checker_pr_array; // @[TLB.scala:529:87, :586:46] wire [13:0] pma_checker__ae_ld_array_T_1 = pma_checker_ae_array \| pma_checker__ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}] wire [13:0] pma_checker_ae_ld_array = pma_checker_cmd_read ? pma_checker__ae_ld_array_T_1 : 14'h0; // @[TLB.scala:586:{24,44}] wire [13:0] pma_checker__ae_st_array_T = ~pma_checker_pw_array; // @[TLB.scala:531:87, :588:37] wire [13:0] pma_checker__ae_st_array_T_1 = pma_checker_ae_array \| pma_checker__ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}] wire [13:0] pma_checker__ae_st_array_T_2 = pma_checker_cmd_write_perms ? pma_checker__ae_st_array_T_1 : 14'h0; // @[TLB.scala:577:35, :588:{8,35}] wire [13:0] pma_checker__ae_st_array_T_3 = ~pma_checker_ppp_array_if_cached; // @[TLB.scala:544:39, :589:26] wire [13:0] pma_checker__ae_st_array_T_4 = pma_checker_cmd_put_partial ? pma_checker__ae_st_array_T_3 : 14'h0; // @[TLB.scala:573:41, :589:{8,26}] wire [13:0] pma_checker__ae_st_array_T_5 = pma_checker__ae_st_array_T_2 \| pma_checker__ae_st_array_T_4; // @[TLB.scala:588:{8,53}, :589:8] wire [13:0] pma_checker__ae_st_array_T_6 = ~pma_checker_pal_array_if_cached; // @[TLB.scala:546:39, :590:26] wire [13:0] pma_checker__ae_st_array_T_7 = pma_checker_cmd_amo_logical ? pma_checker__ae_st_array_T_6 : 14'h0; // @[TLB.scala:571:40, :590:{8,26}] wire [13:0] pma_checker__ae_st_array_T_8 = pma_checker__ae_st_array_T_5 \| pma_checker__ae_st_array_T_7; // @[TLB.scala:588:53, :589:53, :590:8] wire [13:0] pma_checker__ae_st_array_T_9 = ~pma_checker_paa_array_if_cached; // @[TLB.scala:545:39, :591:29] wire [13:0] pma_checker__ae_st_array_T_10 = pma_checker_cmd_amo_arithmetic ? pma_checker__ae_st_array_T_9 : 14'h0; // @[TLB.scala:572:43, :591:{8,29}] wire [13:0] pma_checker_ae_st_array = pma_checker__ae_st_array_T_8 \| pma_checker__ae_st_array_T_10; // @[TLB.scala:589:53, :590:53, :591:8] wire [13:0] pma_checker__must_alloc_array_T = ~pma_checker_ppp_array; // @[TLB.scala:539:22, :593:26] wire [13:0] pma_checker__must_alloc_array_T_1 = pma_checker_cmd_put_partial ? pma_checker__must_alloc_array_T : 14'h0; // @[TLB.scala:573:41, :593:{8,26}] wire [13:0] pma_checker__must_alloc_array_T_2 = ~pma_checker_pal_array; // @[TLB.scala:543:22, :594:26] wire [13:0] pma_checker__must_alloc_array_T_3 = pma_checker_cmd_amo_logical ? pma_checker__must_alloc_array_T_2 : 14'h0; // @[TLB.scala:571:40, :594:{8,26}] wire [13:0] pma_checker__must_alloc_array_T_4 = pma_checker__must_alloc_array_T_1 \| pma_checker__must_alloc_array_T_3; // @[TLB.scala:593:{8,43}, :594:8] wire [13:0] pma_checker__must_alloc_array_T_5 = ~pma_checker_paa_array; // @[TLB.scala:541:22, :595:29] wire [13:0] pma_checker__must_alloc_array_T_6 = pma_checker_cmd_amo_arithmetic ? pma_checker__must_alloc_array_T_5 : 14'h0; // @[TLB.scala:572:43, :595:{8,29}] wire [13:0] pma_checker__must_alloc_array_T_7 = pma_checker__must_alloc_array_T_4 \| pma_checker__must_alloc_array_T_6; // @[TLB.scala:593:43, :594:43, :595:8] wire [13:0] pma_checker__must_alloc_array_T_9 = {14{pma_checker_cmd_lrsc}}; // @[TLB.scala:570:33, :596:8] wire [13:0] pma_checker_must_alloc_array = pma_checker__must_alloc_array_T_7 \| pma_checker__must_alloc_array_T_9; // @[TLB.scala:594:43, :595:46, :596:8] wire [13:0] pma_checker__pf_ld_array_T_1 = ~pma_checker__pf_ld_array_T; // @[TLB.scala:597:{37,41}] wire [13:0] pma_checker__pf_ld_array_T_2 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73] wire [13:0] pma_checker__pf_ld_array_T_3 = pma_checker__pf_ld_array_T_1 & pma_checker__pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}] wire [13:0] pma_checker__pf_ld_array_T_4 = pma_checker__pf_ld_array_T_3 \| pma_checker_ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}] wire [13:0] pma_checker__pf_ld_array_T_5 = ~pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :597:106] wire [13:0] pma_checker__pf_ld_array_T_6 = pma_checker__pf_ld_array_T_4 & pma_checker__pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}] wire [13:0] pma_checker_pf_ld_array = pma_checker_cmd_read ? pma_checker__pf_ld_array_T_6 : 14'h0; // @[TLB.scala:597:{24,104}] wire [13:0] pma_checker__pf_st_array_T = ~pma_checker_w_array; // @[TLB.scala:521:20, :598:44] wire [13:0] pma_checker__pf_st_array_T_1 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55] wire [13:0] pma_checker__pf_st_array_T_2 = pma_checker__pf_st_array_T & pma_checker__pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}] wire [13:0] pma_checker__pf_st_array_T_3 = pma_checker__pf_st_array_T_2 \| pma_checker_ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}] wire [13:0] pma_checker__pf_st_array_T_4 = ~pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88] wire [13:0] pma_checker__pf_st_array_T_5 = pma_checker__pf_st_array_T_3 & pma_checker__pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}] wire [13:0] pma_checker_pf_st_array = pma_checker_cmd_write_perms ? pma_checker__pf_st_array_T_5 : 14'h0; // @[TLB.scala:577:35, :598:{24,86}] wire [13:0] pma_checker__pf_inst_array_T = ~pma_checker_x_array; // @[TLB.scala:522:20, :599:25] wire [13:0] pma_checker__pf_inst_array_T_1 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36] wire [13:0] pma_checker__pf_inst_array_T_2 = pma_checker__pf_inst_array_T & pma_checker__pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}] wire [13:0] pma_checker__pf_inst_array_T_3 = pma_checker__pf_inst_array_T_2 \| pma_checker_ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}] wire [13:0] pma_checker__pf_inst_array_T_4 = ~pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69] wire [13:0] pma_checker_pf_inst_array = pma_checker__pf_inst_array_T_3 & pma_checker__pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}] wire [13:0] pma_checker__gf_ld_array_T_4 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100] wire [13:0] pma_checker__gf_ld_array_T_5 = pma_checker__gf_ld_array_T_3 & pma_checker__gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}] wire [13:0] pma_checker__gf_st_array_T_3 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81] wire [13:0] pma_checker__gf_st_array_T_4 = pma_checker__gf_st_array_T_2 & pma_checker__gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}] wire [13:0] pma_checker__gf_inst_array_T_2 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64] wire [13:0] pma_checker__gf_inst_array_T_3 = pma_checker__gf_inst_array_T_1 & pma_checker__gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}] wire pma_checker__gpa_hits_hit_mask_T = pma_checker_vpn == 27'h0; // @[TLB.scala:335:30, :606:73] wire [13:0] pma_checker__io_resp_pf_ld_T_1 = pma_checker_pf_ld_array & 14'h2000; // @[TLB.scala:597:24, :633:57] wire pma_checker__io_resp_pf_ld_T_2 = \|pma_checker__io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}] assign pma_checker__io_resp_pf_ld_T_3 = pma_checker__io_resp_pf_ld_T_2; // @[TLB.scala:633:{41,65}] assign pma_checker_io_resp_pf_ld = pma_checker__io_resp_pf_ld_T_3; // @[TLB.scala:633:41] wire [13:0] pma_checker__io_resp_pf_st_T_1 = pma_checker_pf_st_array & 14'h2000; // @[TLB.scala:598:24, :634:64] wire pma_checker__io_resp_pf_st_T_2 = \|pma_checker__io_resp_pf_st_T_1; // @[TLB.scala:634:{64,72}] assign pma_checker__io_resp_pf_st_T_3 = pma_checker__io_resp_pf_st_T_2; // @[TLB.scala:634:{48,72}] assign pma_checker_io_resp_pf_st = pma_checker__io_resp_pf_st_T_3; // @[TLB.scala:634:48] wire [13:0] pma_checker__io_resp_pf_inst_T = pma_checker_pf_inst_array & 14'h2000; // @[TLB.scala:599:67, :635:47] wire pma_checker__io_resp_pf_inst_T_1 = \|pma_checker__io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}] assign pma_checker__io_resp_pf_inst_T_2 = pma_checker__io_resp_pf_inst_T_1; // @[TLB.scala:635:{29,55}] assign pma_checker_io_resp_pf_inst = pma_checker__io_resp_pf_inst_T_2; // @[TLB.scala:635:29] wire [13:0] pma_checker__io_resp_ae_ld_T = pma_checker_ae_ld_array & 14'h2000; // @[TLB.scala:586:24, :641:33] assign pma_checker__io_resp_ae_ld_T_1 = \|pma_checker__io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}] assign pma_checker_io_resp_ae_ld = pma_checker__io_resp_ae_ld_T_1; // @[TLB.scala:641:41] wire [13:0] pma_checker__io_resp_ae_st_T = pma_checker_ae_st_array & 14'h2000; // @[TLB.scala:590:53, :642:33] assign pma_checker__io_resp_ae_st_T_1 = \|pma_checker__io_resp_ae_st_T; // @[TLB.scala:642:{33,41}] assign pma_checker_io_resp_ae_st = pma_checker__io_resp_ae_st_T_1; // @[TLB.scala:642:41] wire [13:0] pma_checker__io_resp_ae_inst_T = ~pma_checker_px_array; // @[TLB.scala:533:87, :643:23] wire [13:0] pma_checker__io_resp_ae_inst_T_1 = pma_checker__io_resp_ae_inst_T & 14'h2000; // @[TLB.scala:643:{23,33}] assign pma_checker__io_resp_ae_inst_T_2 = \|pma_checker__io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}] assign pma_checker_io_resp_ae_inst = pma_checker__io_resp_ae_inst_T_2; // @[TLB.scala:643:41] assign pma_checker__io_resp_ma_ld_T = pma_checker_misaligned & pma_checker_cmd_read; // @[TLB.scala:550:77, :645:31] assign pma_checker_io_resp_ma_ld = pma_checker__io_resp_ma_ld_T; // @[TLB.scala:645:31] assign pma_checker__io_resp_ma_st_T = pma_checker_misaligned & pma_checker_cmd_write; // @[TLB.scala:550:77, :646:31] assign pma_checker_io_resp_ma_st = pma_checker__io_resp_ma_st_T; // @[TLB.scala:646:31] wire [13:0] pma_checker__io_resp_cacheable_T = pma_checker_c_array & 14'h2000; // @[TLB.scala:537:20, :648:33] assign pma_checker__io_resp_cacheable_T_1 = \|pma_checker__io_resp_cacheable_T; // @[TLB.scala:648:{33,41}] assign pma_checker_io_resp_cacheable = pma_checker__io_resp_cacheable_T_1; // @[TLB.scala:648:41] wire [13:0] pma_checker__io_resp_must_alloc_T = pma_checker_must_alloc_array & 14'h2000; // @[TLB.scala:595:46, :649:43] assign pma_checker__io_resp_must_alloc_T_1 = \|pma_checker__io_resp_must_alloc_T; // @[TLB.scala:649:{43,51}] assign pma_checker_io_resp_must_alloc = pma_checker__io_resp_must_alloc_T_1; // @[TLB.scala:649:51] wire [13:0] pma_checker__io_resp_prefetchable_T = pma_checker_prefetchable_array & 14'h2000; // @[TLB.scala:547:31, :650:47] wire pma_checker__io_resp_prefetchable_T_1 = \|pma_checker__io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}] assign pma_checker__io_resp_prefetchable_T_2 = pma_checker__io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}] assign pma_checker_io_resp_prefetchable = pma_checker__io_resp_prefetchable_T_2; // @[TLB.scala:650:59] assign pma_checker__io_resp_paddr_T_1 = {pma_checker_ppn, pma_checker__io_resp_paddr_T}; // @[Mux.scala:30:73] assign pma_checker_io_resp_paddr = pma_checker__io_resp_paddr_T_1; // @[TLB.scala:652:23] wire [27:0] pma_checker__io_resp_gpa_page_T_1 = {1'h0, pma_checker_vpn}; // @[TLB.scala:335:30, :657:36] wire [27:0] pma_checker_io_resp_gpa_page = pma_checker__io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}] wire [11:0] pma_checker_io_resp_gpa_offset = pma_checker__io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}] assign pma_checker__io_resp_gpa_T = {pma_checker_io_resp_gpa_page, pma_checker_io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8] assign pma_checker_io_resp_gpa = pma_checker__io_resp_gpa_T; // @[TLB.scala:659:8] wire pma_checker_ignore_1 = pma_checker__ignore_T_1; // @[TLB.scala:182:{28,34}] wire pma_checker_ignore_4 = pma_checker__ignore_T_4; // @[TLB.scala:182:{28,34}] wire pma_checker_ignore_7 = pma_checker__ignore_T_7; // @[TLB.scala:182:{28,34}] wire pma_checker_ignore_10 = pma_checker__ignore_T_10; // @[TLB.scala:182:{28,34}] wire replace; // @[Replacement.scala:37:29] wire [1:0] lfsr_lo_lo_lo = {_lfsr_prng_io_out_1, _lfsr_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_lo_lo_hi = {_lfsr_prng_io_out_3, _lfsr_prng_io_out_2}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_lo_lo = {lfsr_lo_lo_hi, lfsr_lo_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] lfsr_lo_hi_lo = {_lfsr_prng_io_out_5, _lfsr_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_lo_hi_hi = {_lfsr_prng_io_out_7, _lfsr_prng_io_out_6}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_lo_hi = {lfsr_lo_hi_hi, lfsr_lo_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] lfsr_lo = {lfsr_lo_hi, lfsr_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] lfsr_hi_lo_lo = {_lfsr_prng_io_out_9, _lfsr_prng_io_out_8}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_hi_lo_hi = {_lfsr_prng_io_out_11, _lfsr_prng_io_out_10}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_hi_lo = {lfsr_hi_lo_hi, lfsr_hi_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] lfsr_hi_hi_lo = {_lfsr_prng_io_out_13, _lfsr_prng_io_out_12}; // @[PRNG.scala:91:22, :95:17] wire [1:0] lfsr_hi_hi_hi = {_lfsr_prng_io_out_15, _lfsr_prng_io_out_14}; // @[PRNG.scala:91:22, :95:17] wire [3:0] lfsr_hi_hi = {lfsr_hi_hi_hi, lfsr_hi_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] lfsr_hi = {lfsr_hi_hi, lfsr_hi_lo}; // @[PRNG.scala:95:17] wire [15:0] lfsr = {lfsr_hi, lfsr_lo}; // @[PRNG.scala:95:17] wire metaArb__grant_T = metaArb_io_in_0_valid; // @[Arbiter.scala:45:68] wire [39:0] _metaArb_io_in_5_bits_addr_T_2; // @[DCache.scala:1018:36] wire [5:0] _metaArb_io_in_5_bits_idx_T; // @[DCache.scala:1017:44] wire metaArb__io_in_1_ready_T; // @[Arbiter.scala:153:19] wire [39:0] _metaArb_io_in_1_bits_addr_T_2; // @[DCache.scala:454:36] wire [5:0] _metaArb_io_in_1_bits_idx_T_2; // @[DCache.scala:453:35] wire [21:0] _metaArb_io_in_1_bits_data_T; // @[DCache.scala:458:14] wire metaArb__io_in_2_ready_T; // @[Arbiter.scala:153:19] wire _metaArb_io_in_2_valid_T; // @[DCache.scala:462:63] wire [39:0] _metaArb_io_in_2_bits_addr_T_2; // @[DCache.scala:466:36] wire [5:0] _metaArb_io_in_2_bits_idx_T; // @[DCache.scala:465:40] wire [7:0] s2_victim_or_hit_way; // @[DCache.scala:432:33] wire [21:0] _metaArb_io_in_2_bits_data_T_1; // @[DCache.scala:467:97] wire metaArb__io_in_3_ready_T; // @[Arbiter.scala:153:19] wire _metaArb_io_in_3_valid_T_2; // @[DCache.scala:741:53] wire [39:0] _metaArb_io_in_3_bits_addr_T_2; // @[DCache.scala:745:36] wire [5:0] _metaArb_io_in_3_bits_idx_T; // @[DCache.scala:744:40] wire [21:0] _metaArb_io_in_3_bits_data_T_18; // @[DCache.scala:746:134] wire metaArb__io_in_4_ready_T; // @[Arbiter.scala:153:19] wire _metaArb_io_in_4_valid_T_2; // @[package.scala:81:59] wire [39:0] _metaArb_io_in_4_bits_addr_T_2; // @[DCache.scala:912:36] wire [5:0] _metaArb_io_in_4_bits_idx_T; // @[DCache.scala:1200:47] wire [7:0] releaseWay; // @[DCache.scala:232:24] wire [21:0] _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:913:97] wire metaArb__io_in_5_ready_T; // @[Arbiter.scala:153:19] wire metaArb__io_in_6_ready_T; // @[Arbiter.scala:153:19] wire metaArb__io_in_7_ready_T; // @[Arbiter.scala:153:19] wire [5:0] _metaArb_io_in_7_bits_idx_T; // @[DCache.scala:263:58] wire metaArb__io_out_valid_T_1; // @[Arbiter.scala:154:31] wire [5:0] _s1_meta_WIRE = metaArb_io_out_bits_idx; // @[DCache.scala:135:28, :314:35] wire [39:0] metaArb_io_in_0_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_0_bits_idx; // @[DCache.scala:135:28] wire [39:0] metaArb_io_in_1_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_1_bits_idx; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_1_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_1_ready; // @[DCache.scala:135:28] wire [39:0] metaArb_io_in_2_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_2_bits_idx; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_2_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_2_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_2_ready; // @[DCache.scala:135:28] wire metaArb_io_in_2_valid; // @[DCache.scala:135:28] wire [39:0] metaArb_io_in_3_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_3_bits_idx; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_3_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_3_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_3_ready; // @[DCache.scala:135:28] wire metaArb_io_in_3_valid; // @[DCache.scala:135:28] wire [39:0] metaArb_io_in_4_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_4_bits_idx; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_4_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_4_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_4_ready; // @[DCache.scala:135:28] wire metaArb_io_in_4_valid; // @[DCache.scala:135:28] wire [39:0] metaArb_io_in_5_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_5_bits_idx; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_5_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_5_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_5_ready; // @[DCache.scala:135:28] wire [39:0] metaArb_io_in_6_bits_addr; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_6_bits_idx; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_6_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_6_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_6_ready; // @[DCache.scala:135:28] wire metaArb_io_in_6_valid; // @[DCache.scala:135:28] wire [5:0] metaArb_io_in_7_bits_idx; // @[DCache.scala:135:28] wire [7:0] metaArb_io_in_7_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_in_7_bits_data; // @[DCache.scala:135:28] wire metaArb_io_in_7_ready; // @[DCache.scala:135:28] wire metaArb_io_out_bits_write; // @[DCache.scala:135:28] wire [39:0] metaArb_io_out_bits_addr; // @[DCache.scala:135:28] wire [7:0] metaArb_io_out_bits_way_en; // @[DCache.scala:135:28] wire [21:0] metaArb_io_out_bits_data; // @[DCache.scala:135:28] wire metaArb_io_out_valid; // @[DCache.scala:135:28] wire [2:0] metaArb_io_chosen; // @[DCache.scala:135:28] assign metaArb_io_chosen = metaArb_io_in_0_valid ? 3'h0 : metaArb_io_in_2_valid ? 3'h2 : metaArb_io_in_3_valid ? 3'h3 : metaArb_io_in_4_valid ? 3'h4 : {2'h3, ~metaArb_io_in_6_valid}; // @[Arbiter.scala:142:13, :145:26, :146:17] assign metaArb_io_out_bits_write = metaArb_io_in_0_valid \| metaArb_io_in_2_valid \| metaArb_io_in_3_valid \| metaArb_io_in_4_valid; // @[Arbiter.scala:145:26, :147:19] assign metaArb_io_out_bits_addr = metaArb_io_in_0_valid ? metaArb_io_in_0_bits_addr : metaArb_io_in_2_valid ? metaArb_io_in_2_bits_addr : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_addr : metaArb_io_in_4_valid ? metaArb_io_in_4_bits_addr : metaArb_io_in_6_valid ? metaArb_io_in_6_bits_addr : metaArb_io_in_7_bits_addr; // @[Arbiter.scala:143:15, :145:26, :147:19] assign metaArb_io_out_bits_idx = metaArb_io_in_0_valid ? metaArb_io_in_0_bits_idx : metaArb_io_in_2_valid ? metaArb_io_in_2_bits_idx : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_idx : metaArb_io_in_4_valid ? metaArb_io_in_4_bits_idx : metaArb_io_in_6_valid ? metaArb_io_in_6_bits_idx : metaArb_io_in_7_bits_idx; // @[Arbiter.scala:143:15, :145:26, :147:19] assign metaArb_io_out_bits_way_en = metaArb_io_in_0_valid ? 8'hFF : metaArb_io_in_2_valid ? metaArb_io_in_2_bits_way_en : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_way_en : metaArb_io_in_4_valid ? metaArb_io_in_4_bits_way_en : metaArb_io_in_6_valid ? metaArb_io_in_6_bits_way_en : metaArb_io_in_7_bits_way_en; // @[Arbiter.scala:143:15, :145:26, :147:19] assign metaArb_io_out_bits_data = metaArb_io_in_0_valid ? 22'h0 : metaArb_io_in_2_valid ? metaArb_io_in_2_bits_data : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_data : metaArb_io_in_4_valid ? metaArb_io_in_4_bits_data : metaArb_io_in_6_valid ? metaArb_io_in_6_bits_data : metaArb_io_in_7_bits_data; // @[Arbiter.scala:143:15, :145:26, :147:19] wire metaArb__grant_T_1 = metaArb__grant_T \| metaArb_io_in_2_valid; // @[Arbiter.scala:45:68] wire metaArb__grant_T_2 = metaArb__grant_T_1 \| metaArb_io_in_3_valid; // @[Arbiter.scala:45:68] wire metaArb__grant_T_3 = metaArb__grant_T_2 \| metaArb_io_in_4_valid; // @[Arbiter.scala:45:68] wire metaArb__grant_T_4 = metaArb__grant_T_3; // @[Arbiter.scala:45:68] wire metaArb__grant_T_5 = metaArb__grant_T_4 \| metaArb_io_in_6_valid; // @[Arbiter.scala:45:68] wire metaArb_grant_1 = ~metaArb_io_in_0_valid; // @[Arbiter.scala:45:78] assign metaArb__io_in_1_ready_T = metaArb_grant_1; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_2 = ~metaArb__grant_T; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_2_ready_T = metaArb_grant_2; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_3 = ~metaArb__grant_T_1; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_3_ready_T = metaArb_grant_3; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_4 = ~metaArb__grant_T_2; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_4_ready_T = metaArb_grant_4; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_5 = ~metaArb__grant_T_3; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_5_ready_T = metaArb_grant_5; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_6 = ~metaArb__grant_T_4; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_6_ready_T = metaArb_grant_6; // @[Arbiter.scala:45:78, :153:19] wire metaArb_grant_7 = ~metaArb__grant_T_5; // @[Arbiter.scala:45:{68,78}] assign metaArb__io_in_7_ready_T = metaArb_grant_7; // @[Arbiter.scala:45:78, :153:19] assign metaArb_io_in_1_ready = metaArb__io_in_1_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_2_ready = metaArb__io_in_2_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_3_ready = metaArb__io_in_3_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_4_ready = metaArb__io_in_4_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_5_ready = metaArb__io_in_5_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_6_ready = metaArb__io_in_6_ready_T; // @[Arbiter.scala:153:19] assign metaArb_io_in_7_ready = metaArb__io_in_7_ready_T; // @[Arbiter.scala:153:19] wire metaArb__io_out_valid_T = ~metaArb_grant_7; // @[Arbiter.scala:45:78, :154:19] assign metaArb__io_out_valid_T_1 = metaArb__io_out_valid_T \| metaArb_io_in_7_valid; // @[Arbiter.scala:154:{19,31}] assign metaArb_io_out_valid = metaArb__io_out_valid_T_1; // @[Arbiter.scala:154:31] wire _s1_meta_T_1; // @[DCache.scala:314:59] wire wmask_0; // @[DCache.scala:311:74] wire wmask_1; // @[DCache.scala:311:74] wire wmask_2; // @[DCache.scala:311:74] wire wmask_3; // @[DCache.scala:311:74] wire wmask_4; // @[DCache.scala:311:74] wire wmask_5; // @[DCache.scala:311:74] wire wmask_6; // @[DCache.scala:311:74] wire wmask_7; // @[DCache.scala:311:74] wire [21:0] _s1_meta_uncorrected_WIRE = _rockettile_dcache_tag_array_RW0_rdata[21:0]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_1 = _rockettile_dcache_tag_array_RW0_rdata[43:22]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_2 = _rockettile_dcache_tag_array_RW0_rdata[65:44]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_3 = _rockettile_dcache_tag_array_RW0_rdata[87:66]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_4 = _rockettile_dcache_tag_array_RW0_rdata[109:88]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_5 = _rockettile_dcache_tag_array_RW0_rdata[131:110]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_6 = _rockettile_dcache_tag_array_RW0_rdata[153:132]; // @[DescribedSRAM.scala:17:26] wire [21:0] _s1_meta_uncorrected_WIRE_7 = _rockettile_dcache_tag_array_RW0_rdata[175:154]; // @[DescribedSRAM.scala:17:26] wire _dataArb_io_in_0_valid_T_12; // @[DCache.scala:516:27] wire pstore_drain; // @[DCache.scala:516:27] wire [63:0] _dataArb_io_in_0_bits_wdata_T_9; // @[package.scala:45:27] wire [7:0] _dataArb_io_in_0_bits_eccMask_T_17; // @[package.scala:45:27] wire [7:0] _dataArb_io_in_0_bits_way_en_T; // @[DCache.scala:550:38] wire dataArb__io_in_1_ready_T; // @[Arbiter.scala:153:19] wire [63:0] tl_d_data_encoded; // @[DCache.scala:324:31] wire dataArb__io_in_2_ready_T; // @[Arbiter.scala:153:19] wire _dataArb_io_in_2_valid_T_1; // @[DCache.scala:900:41] wire [11:0] _dataArb_io_in_2_bits_addr_T_4; // @[DCache.scala:903:72] wire dataArb__io_in_3_ready_T; // @[Arbiter.scala:153:19] wire _dataArb_io_in_3_valid_T_58; // @[DCache.scala:242:46] wire dataArb__io_out_valid_T_1; // @[Arbiter.scala:154:31] wire [11:0] dataArb_io_in_0_bits_addr; // @[DCache.scala:152:28] wire dataArb_io_in_0_bits_write; // @[DCache.scala:152:28] wire [63:0] dataArb_io_in_0_bits_wdata; // @[DCache.scala:152:28] wire dataArb_io_in_0_bits_wordMask; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_0_bits_eccMask; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_0_bits_way_en; // @[DCache.scala:152:28] wire dataArb_io_in_0_valid; // @[DCache.scala:152:28] wire [11:0] dataArb_io_in_1_bits_addr; // @[DCache.scala:152:28] wire dataArb_io_in_1_bits_write; // @[DCache.scala:152:28] wire [63:0] dataArb_io_in_1_bits_wdata; // @[DCache.scala:152:28] wire [7:0] dataArb_io_in_1_bits_way_en; // @[DCache.scala:152:28] wire dataArb_io_in_1_ready; // @[DCache.scala:152:28] wire dataArb_io_in_1_valid; // @[DCache.scala:152:28] wire [11:0] dataArb_io_in_2_bits_addr; // @[DCache.scala:152:28] wire [63:0] dataArb_io_in_2_bits_wdata; // @[DCache.scala:152:28] wire dataArb_io_in_2_ready; // @[DCache.scala:152:28] wire dataArb_io_in_2_valid; // @[DCache.scala:152:28] wire [11:0] dataArb_io_in_3_bits_addr; // @[DCache.scala:152:28] wire [63:0] dataArb_io_in_3_bits_wdata; // @[DCache.scala:152:28] wire dataArb_io_in_3_ready; // @[DCache.scala:152:28] wire dataArb_io_in_3_valid; // @[DCache.scala:152:28] wire [11:0] dataArb_io_out_bits_addr; // @[DCache.scala:152:28] wire dataArb_io_out_bits_write; // @[DCache.scala:152:28] wire [63:0] dataArb_io_out_bits_wdata; // @[DCache.scala:152:28] wire dataArb_io_out_bits_wordMask; // @[DCache.scala:152:28] wire [7:0] dataArb_io_out_bits_eccMask; // @[DCache.scala:152:28] wire [7:0] dataArb_io_out_bits_way_en; // @[DCache.scala:152:28] wire dataArb_io_out_valid; // @[DCache.scala:152:28] wire [1:0] dataArb_io_chosen; // @[DCache.scala:152:28] assign dataArb_io_chosen = dataArb_io_in_0_valid ? 2'h0 : dataArb_io_in_1_valid ? 2'h1 : {1'h1, ~dataArb_io_in_2_valid}; // @[Arbiter.scala:142:13, :145:26, :146:17] assign dataArb_io_out_bits_addr = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_addr : dataArb_io_in_1_valid ? dataArb_io_in_1_bits_addr : dataArb_io_in_2_valid ? dataArb_io_in_2_bits_addr : dataArb_io_in_3_bits_addr; // @[Arbiter.scala:143:15, :145:26, :147:19] assign dataArb_io_out_bits_write = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_write : dataArb_io_in_1_valid & dataArb_io_in_1_bits_write; // @[Arbiter.scala:145:26, :147:19] assign dataArb_io_out_bits_wdata = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_wdata : dataArb_io_in_1_valid ? dataArb_io_in_1_bits_wdata : dataArb_io_in_2_valid ? dataArb_io_in_2_bits_wdata : dataArb_io_in_3_bits_wdata; // @[Arbiter.scala:143:15, :145:26, :147:19] assign dataArb_io_out_bits_wordMask = ~dataArb_io_in_0_valid \| dataArb_io_in_0_bits_wordMask; // @[Arbiter.scala:145:26, :147:19] assign dataArb_io_out_bits_eccMask = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_eccMask : 8'hFF; // @[Arbiter.scala:145:26, :147:19] assign dataArb_io_out_bits_way_en = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_way_en : dataArb_io_in_1_valid ? dataArb_io_in_1_bits_way_en : 8'hFF; // @[Arbiter.scala:145:26, :147:19] wire dataArb__grant_T = dataArb_io_in_0_valid \| dataArb_io_in_1_valid; // @[Arbiter.scala:45:68] wire dataArb__grant_T_1 = dataArb__grant_T \| dataArb_io_in_2_valid; // @[Arbiter.scala:45:68] wire dataArb_grant_1 = ~dataArb_io_in_0_valid; // @[Arbiter.scala:45:78] assign dataArb__io_in_1_ready_T = dataArb_grant_1; // @[Arbiter.scala:45:78, :153:19] wire dataArb_grant_2 = ~dataArb__grant_T; // @[Arbiter.scala:45:{68,78}] assign dataArb__io_in_2_ready_T = dataArb_grant_2; // @[Arbiter.scala:45:78, :153:19] wire dataArb_grant_3 = ~dataArb__grant_T_1; // @[Arbiter.scala:45:{68,78}] assign dataArb__io_in_3_ready_T = dataArb_grant_3; // @[Arbiter.scala:45:78, :153:19] assign dataArb_io_in_1_ready = dataArb__io_in_1_ready_T; // @[Arbiter.scala:153:19] assign dataArb_io_in_2_ready = dataArb__io_in_2_ready_T; // @[Arbiter.scala:153:19] assign dataArb_io_in_3_ready = dataArb__io_in_3_ready_T; // @[Arbiter.scala:153:19] wire dataArb__io_out_valid_T = ~dataArb_grant_3; // @[Arbiter.scala:45:78, :154:19] assign dataArb__io_out_valid_T_1 = dataArb__io_out_valid_T \| dataArb_io_in_3_valid; // @[Arbiter.scala:154:{19,31}] assign dataArb_io_out_valid = dataArb__io_out_valid_T_1; // @[Arbiter.scala:154:31] wire _tl_out_a_valid_T_14; // @[DCache.scala:603:37] assign nodeOut_a_deq_valid = tl_out_a_valid; // @[Decoupled.scala:356:21] wire [2:0] _tl_out_a_bits_T_9_opcode; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_opcode = tl_out_a_bits_opcode; // @[Decoupled.scala:356:21] wire [2:0] _tl_out_a_bits_T_9_param; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_param = tl_out_a_bits_param; // @[Decoupled.scala:356:21] wire [3:0] _tl_out_a_bits_T_9_size; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_size = tl_out_a_bits_size; // @[Decoupled.scala:356:21] wire _tl_out_a_bits_T_9_source; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_source = tl_out_a_bits_source; // @[Decoupled.scala:356:21] wire [31:0] _tl_out_a_bits_T_9_address; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_address = tl_out_a_bits_address; // @[Decoupled.scala:356:21] wire [7:0] _tl_out_a_bits_T_9_mask; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_mask = tl_out_a_bits_mask; // @[Decoupled.scala:356:21] wire [63:0] _tl_out_a_bits_T_9_data; // @[DCache.scala:608:23] assign nodeOut_a_deq_bits_data = tl_out_a_bits_data; // @[Decoupled.scala:356:21] wire tl_out_a_ready; // @[DCache.scala:159:22] assign tl_out_a_ready = nodeOut_a_deq_ready; // @[Decoupled.scala:356:21] assign nodeOut_a_valid = nodeOut_a_deq_valid; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_opcode = nodeOut_a_deq_bits_opcode; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_param = nodeOut_a_deq_bits_param; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_size = nodeOut_a_deq_bits_size; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_source = nodeOut_a_deq_bits_source; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_address = nodeOut_a_deq_bits_address; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_mask = nodeOut_a_deq_bits_mask; // @[Decoupled.scala:356:21] assign nodeOut_a_bits_data = nodeOut_a_deq_bits_data; // @[Decoupled.scala:356:21] wire _s1_valid_T = io_cpu_req_ready_0 & io_cpu_req_valid_0; // @[Decoupled.scala:51:35] reg s1_valid; // @[DCache.scala:182:25] wire _io_cpu_ordered_T_1 = s1_valid; // @[DCache.scala:182:25, :929:32] wire _GEN_39 = nodeOut_b_ready & nodeOut_b_valid; // @[Decoupled.scala:51:35] wire _s1_probe_T; // @[Decoupled.scala:51:35] assign _s1_probe_T = _GEN_39; // @[Decoupled.scala:51:35] wire _probe_bits_T; // @[Decoupled.scala:51:35] assign _probe_bits_T = _GEN_39; // @[Decoupled.scala:51:35] reg s1_probe; // @[DCache.scala:183:25] reg [2:0] probe_bits_opcode; // @[DCache.scala:184:29] reg [1:0] probe_bits_param; // @[DCache.scala:184:29] reg [3:0] probe_bits_size; // @[DCache.scala:184:29] wire [3:0] nackResponseMessage_size = probe_bits_size; // @[Edges.scala:416:17] wire [3:0] cleanReleaseMessage_size = probe_bits_size; // @[Edges.scala:416:17] wire [3:0] dirtyReleaseMessage_size = probe_bits_size; // @[Edges.scala:433:17] reg probe_bits_source; // @[DCache.scala:184:29] assign nodeOut_c_bits_source = probe_bits_source; // @[DCache.scala:184:29] wire nackResponseMessage_source = probe_bits_source; // @[Edges.scala:416:17] wire cleanReleaseMessage_source = probe_bits_source; // @[Edges.scala:416:17] wire dirtyReleaseMessage_source = probe_bits_source; // @[Edges.scala:433:17] reg [31:0] probe_bits_address; // @[DCache.scala:184:29] assign nodeOut_c_bits_address = probe_bits_address; // @[DCache.scala:184:29] wire [31:0] nackResponseMessage_address = probe_bits_address; // @[Edges.scala:416:17] wire [31:0] cleanReleaseMessage_address = probe_bits_address; // @[Edges.scala:416:17] wire [31:0] dirtyReleaseMessage_address = probe_bits_address; // @[Edges.scala:433:17] reg [7:0] probe_bits_mask; // @[DCache.scala:184:29] reg [63:0] probe_bits_data; // @[DCache.scala:184:29] reg probe_bits_corrupt; // @[DCache.scala:184:29] wire s1_nack; // @[DCache.scala:185:28] wire _s1_valid_masked_T = ~io_cpu_s1_kill_0; // @[DCache.scala:101:7, :186:37] wire s1_valid_masked = s1_valid & _s1_valid_masked_T; // @[DCache.scala:182:25, :186:{34,37}] wire _s1_valid_not_nacked_T = ~s1_nack; // @[DCache.scala:185:28, :187:41] wire s1_valid_not_nacked = s1_valid & _s1_valid_not_nacked_T; // @[DCache.scala:182:25, :187:{38,41}] wire _s0_clk_en_T = ~metaArb_io_out_bits_write; // @[DCache.scala:135:28, :190:43] wire s0_clk_en = metaArb_io_out_valid & _s0_clk_en_T; // @[DCache.scala:135:28, :190:{40,43}] wire _s1_tlb_req_T = s0_clk_en; // @[DCache.scala:190:40, :208:52] wire [39:0] _s0_req_addr_T_2; // @[DCache.scala:193:21] wire [39:0] s0_tlb_req_vaddr = s0_req_addr; // @[DCache.scala:192:24, :199:28] wire [4:0] s0_tlb_req_cmd = s0_req_cmd; // @[DCache.scala:192:24, :199:28] wire [1:0] s0_tlb_req_size = s0_req_size; // @[DCache.scala:192:24, :199:28] wire [1:0] s0_tlb_req_prv = s0_req_dprv; // @[DCache.scala:192:24, :199:28] wire s0_tlb_req_v = s0_req_dv; // @[DCache.scala:192:24, :199:28] wire s0_tlb_req_passthrough = s0_req_phys; // @[DCache.scala:192:24, :199:28] wire [33:0] _s0_req_addr_T = metaArb_io_out_bits_addr[39:6]; // @[DCache.scala:135:28, :193:47] wire [5:0] _s0_req_addr_T_1 = io_cpu_req_bits_addr_0[5:0]; // @[DCache.scala:101:7, :193:84] assign _s0_req_addr_T_2 = {_s0_req_addr_T, _s0_req_addr_T_1}; // @[DCache.scala:193:{21,47,84}] assign s0_req_addr = _s0_req_addr_T_2; // @[DCache.scala:192:24, :193:21] assign s0_req_phys = ~metaArb_io_in_7_ready \| io_cpu_req_bits_phys_0; // @[DCache.scala:101:7, :135:28, :192:24, :195:{9,34,48}] reg [39:0] s1_req_addr; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_vaddr = s1_req_addr; // @[DCache.scala:120:32, :196:25] reg [6:0] s1_req_tag; // @[DCache.scala:196:25] reg [4:0] s1_req_cmd; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_cmd = s1_req_cmd; // @[DCache.scala:120:32, :196:25] reg [1:0] s1_req_size; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_size = s1_req_size; // @[DCache.scala:120:32, :196:25] wire [1:0] s1_mask_xwr_size = s1_req_size; // @[DCache.scala:196:25] reg s1_req_signed; // @[DCache.scala:196:25] reg [1:0] s1_req_dprv; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_prv = s1_req_dprv; // @[DCache.scala:120:32, :196:25] reg s1_req_dv; // @[DCache.scala:196:25] assign pma_checker_io_req_bits_v = s1_req_dv; // @[DCache.scala:120:32, :196:25] reg s1_req_phys; // @[DCache.scala:196:25] reg s1_req_no_resp; // @[DCache.scala:196:25] wire [27:0] _s1_vaddr_T = s1_req_addr[39:12]; // @[DCache.scala:196:25, :197:56] wire [11:0] _s1_vaddr_T_1 = s1_req_addr[11:0]; // @[DCache.scala:196:25, :197:78] wire [11:0] _s1_paddr_T_3 = s1_req_addr[11:0]; // @[DCache.scala:196:25, :197:78, :298:125] wire [39:0] s1_vaddr = {_s1_vaddr_T, _s1_vaddr_T_1}; // @[DCache.scala:197:{21,56,78}] reg [39:0] s1_tlb_req_vaddr; // @[DCache.scala:208:29] reg s1_tlb_req_passthrough; // @[DCache.scala:208:29] reg [1:0] s1_tlb_req_size; // @[DCache.scala:208:29] reg [4:0] s1_tlb_req_cmd; // @[DCache.scala:208:29] reg [1:0] s1_tlb_req_prv; // @[DCache.scala:208:29] reg s1_tlb_req_v; // @[DCache.scala:208:29] wire _GEN_40 = s1_req_cmd == 5'h0; // @[package.scala:16:47] wire _s1_read_T; // @[package.scala:16:47] assign _s1_read_T = _GEN_40; // @[package.scala:16:47] wire _pstore1_rmw_T; // @[package.scala:16:47] assign _pstore1_rmw_T = _GEN_40; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_1; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_1 = _GEN_40; // @[package.scala:16:47] wire _GEN_41 = s1_req_cmd == 5'h10; // @[package.scala:16:47] wire _s1_read_T_1; // @[package.scala:16:47] assign _s1_read_T_1 = _GEN_41; // @[package.scala:16:47] wire _pstore1_rmw_T_1; // @[package.scala:16:47] assign _pstore1_rmw_T_1 = _GEN_41; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_2; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_2 = _GEN_41; // @[package.scala:16:47] wire _GEN_42 = s1_req_cmd == 5'h6; // @[package.scala:16:47] wire _s1_read_T_2; // @[package.scala:16:47] assign _s1_read_T_2 = _GEN_42; // @[package.scala:16:47] wire _pstore1_rmw_T_2; // @[package.scala:16:47] assign _pstore1_rmw_T_2 = _GEN_42; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_3; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_3 = _GEN_42; // @[package.scala:16:47] wire _GEN_43 = s1_req_cmd == 5'h7; // @[package.scala:16:47] wire _s1_read_T_3; // @[package.scala:16:47] assign _s1_read_T_3 = _GEN_43; // @[package.scala:16:47] wire _s1_write_T_3; // @[Consts.scala:90:66] assign _s1_write_T_3 = _GEN_43; // @[package.scala:16:47] wire _pstore1_rmw_T_3; // @[package.scala:16:47] assign _pstore1_rmw_T_3 = _GEN_43; // @[package.scala:16:47] wire _pstore1_rmw_T_28; // @[Consts.scala:90:66] assign _pstore1_rmw_T_28 = _GEN_43; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_4; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_4 = _GEN_43; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_29; // @[Consts.scala:90:66] assign _io_cpu_perf_canAcceptLoadThenLoad_T_29 = _GEN_43; // @[package.scala:16:47] wire _s1_read_T_4 = _s1_read_T \| _s1_read_T_1; // @[package.scala:16:47, :81:59] wire _s1_read_T_5 = _s1_read_T_4 \| _s1_read_T_2; // @[package.scala:16:47, :81:59] wire _s1_read_T_6 = _s1_read_T_5 \| _s1_read_T_3; // @[package.scala:16:47, :81:59] wire _GEN_44 = s1_req_cmd == 5'h4; // @[package.scala:16:47] wire _s1_read_T_7; // @[package.scala:16:47] assign _s1_read_T_7 = _GEN_44; // @[package.scala:16:47] wire _s1_write_T_5; // @[package.scala:16:47] assign _s1_write_T_5 = _GEN_44; // @[package.scala:16:47] wire _pstore1_rmw_T_7; // @[package.scala:16:47] assign _pstore1_rmw_T_7 = _GEN_44; // @[package.scala:16:47] wire _pstore1_rmw_T_30; // @[package.scala:16:47] assign _pstore1_rmw_T_30 = _GEN_44; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_8; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_8 = _GEN_44; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_31; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_31 = _GEN_44; // @[package.scala:16:47] wire _GEN_45 = s1_req_cmd == 5'h9; // @[package.scala:16:47] wire _s1_read_T_8; // @[package.scala:16:47] assign _s1_read_T_8 = _GEN_45; // @[package.scala:16:47] wire _s1_write_T_6; // @[package.scala:16:47] assign _s1_write_T_6 = _GEN_45; // @[package.scala:16:47] wire _pstore1_rmw_T_8; // @[package.scala:16:47] assign _pstore1_rmw_T_8 = _GEN_45; // @[package.scala:16:47] wire _pstore1_rmw_T_31; // @[package.scala:16:47] assign _pstore1_rmw_T_31 = _GEN_45; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_9; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_9 = _GEN_45; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_32; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_32 = _GEN_45; // @[package.scala:16:47] wire _GEN_46 = s1_req_cmd == 5'hA; // @[package.scala:16:47] wire _s1_read_T_9; // @[package.scala:16:47] assign _s1_read_T_9 = _GEN_46; // @[package.scala:16:47] wire _s1_write_T_7; // @[package.scala:16:47] assign _s1_write_T_7 = _GEN_46; // @[package.scala:16:47] wire _pstore1_rmw_T_9; // @[package.scala:16:47] assign _pstore1_rmw_T_9 = _GEN_46; // @[package.scala:16:47] wire _pstore1_rmw_T_32; // @[package.scala:16:47] assign _pstore1_rmw_T_32 = _GEN_46; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_10; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_10 = _GEN_46; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_33; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_33 = _GEN_46; // @[package.scala:16:47] wire _GEN_47 = s1_req_cmd == 5'hB; // @[package.scala:16:47] wire _s1_read_T_10; // @[package.scala:16:47] assign _s1_read_T_10 = _GEN_47; // @[package.scala:16:47] wire _s1_write_T_8; // @[package.scala:16:47] assign _s1_write_T_8 = _GEN_47; // @[package.scala:16:47] wire _pstore1_rmw_T_10; // @[package.scala:16:47] assign _pstore1_rmw_T_10 = _GEN_47; // @[package.scala:16:47] wire _pstore1_rmw_T_33; // @[package.scala:16:47] assign _pstore1_rmw_T_33 = _GEN_47; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_11; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_11 = _GEN_47; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_34; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_34 = _GEN_47; // @[package.scala:16:47] wire _s1_read_T_11 = _s1_read_T_7 \| _s1_read_T_8; // @[package.scala:16:47, :81:59] wire _s1_read_T_12 = _s1_read_T_11 \| _s1_read_T_9; // @[package.scala:16:47, :81:59] wire _s1_read_T_13 = _s1_read_T_12 \| _s1_read_T_10; // @[package.scala:16:47, :81:59] wire _GEN_48 = s1_req_cmd == 5'h8; // @[package.scala:16:47] wire _s1_read_T_14; // @[package.scala:16:47] assign _s1_read_T_14 = _GEN_48; // @[package.scala:16:47] wire _s1_write_T_12; // @[package.scala:16:47] assign _s1_write_T_12 = _GEN_48; // @[package.scala:16:47] wire _pstore1_rmw_T_14; // @[package.scala:16:47] assign _pstore1_rmw_T_14 = _GEN_48; // @[package.scala:16:47] wire _pstore1_rmw_T_37; // @[package.scala:16:47] assign _pstore1_rmw_T_37 = _GEN_48; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_15; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_15 = _GEN_48; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_38; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_38 = _GEN_48; // @[package.scala:16:47] wire _GEN_49 = s1_req_cmd == 5'hC; // @[package.scala:16:47] wire _s1_read_T_15; // @[package.scala:16:47] assign _s1_read_T_15 = _GEN_49; // @[package.scala:16:47] wire _s1_write_T_13; // @[package.scala:16:47] assign _s1_write_T_13 = _GEN_49; // @[package.scala:16:47] wire _pstore1_rmw_T_15; // @[package.scala:16:47] assign _pstore1_rmw_T_15 = _GEN_49; // @[package.scala:16:47] wire _pstore1_rmw_T_38; // @[package.scala:16:47] assign _pstore1_rmw_T_38 = _GEN_49; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_16; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_16 = _GEN_49; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_39; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_39 = _GEN_49; // @[package.scala:16:47] wire _GEN_50 = s1_req_cmd == 5'hD; // @[package.scala:16:47] wire _s1_read_T_16; // @[package.scala:16:47] assign _s1_read_T_16 = _GEN_50; // @[package.scala:16:47] wire _s1_write_T_14; // @[package.scala:16:47] assign _s1_write_T_14 = _GEN_50; // @[package.scala:16:47] wire _pstore1_rmw_T_16; // @[package.scala:16:47] assign _pstore1_rmw_T_16 = _GEN_50; // @[package.scala:16:47] wire _pstore1_rmw_T_39; // @[package.scala:16:47] assign _pstore1_rmw_T_39 = _GEN_50; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_17; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_17 = _GEN_50; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_40; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_40 = _GEN_50; // @[package.scala:16:47] wire _GEN_51 = s1_req_cmd == 5'hE; // @[package.scala:16:47] wire _s1_read_T_17; // @[package.scala:16:47] assign _s1_read_T_17 = _GEN_51; // @[package.scala:16:47] wire _s1_write_T_15; // @[package.scala:16:47] assign _s1_write_T_15 = _GEN_51; // @[package.scala:16:47] wire _pstore1_rmw_T_17; // @[package.scala:16:47] assign _pstore1_rmw_T_17 = _GEN_51; // @[package.scala:16:47] wire _pstore1_rmw_T_40; // @[package.scala:16:47] assign _pstore1_rmw_T_40 = _GEN_51; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_18; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_18 = _GEN_51; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_41; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_41 = _GEN_51; // @[package.scala:16:47] wire _GEN_52 = s1_req_cmd == 5'hF; // @[package.scala:16:47] wire _s1_read_T_18; // @[package.scala:16:47] assign _s1_read_T_18 = _GEN_52; // @[package.scala:16:47] wire _s1_write_T_16; // @[package.scala:16:47] assign _s1_write_T_16 = _GEN_52; // @[package.scala:16:47] wire _pstore1_rmw_T_18; // @[package.scala:16:47] assign _pstore1_rmw_T_18 = _GEN_52; // @[package.scala:16:47] wire _pstore1_rmw_T_41; // @[package.scala:16:47] assign _pstore1_rmw_T_41 = _GEN_52; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_19; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_19 = _GEN_52; // @[package.scala:16:47] wire _io_cpu_perf_canAcceptLoadThenLoad_T_42; // @[package.scala:16:47] assign _io_cpu_perf_canAcceptLoadThenLoad_T_42 = _GEN_52; // @[package.scala:16:47] wire _s1_read_T_19 = _s1_read_T_14 \| _s1_read_T_15; // @[package.scala:16:47, :81:59] wire _s1_read_T_20 = _s1_read_T_19 \| _s1_read_T_16; // @[package.scala:16:47, :81:59] wire _s1_read_T_21 = _s1_read_T_20 \| _s1_read_T_17; // @[package.scala:16:47, :81:59] wire _s1_read_T_22 = _s1_read_T_21 \| _s1_read_T_18; // @[package.scala:16:47, :81:59] wire _s1_read_T_23 = _s1_read_T_13 \| _s1_read_T_22; // @[package.scala:81:59] wire s1_read = _s1_read_T_6 \| _s1_read_T_23; // @[package.scala:81:59] wire _GEN_53 = s1_req_cmd == 5'h1; // @[DCache.scala:196:25] wire _s1_write_T; // @[Consts.scala:90:32] assign _s1_write_T = _GEN_53; // @[Consts.scala:90:32] wire _pstore1_rmw_T_25; // @[Consts.scala:90:32] assign _pstore1_rmw_T_25 = _GEN_53; // @[Consts.scala:90:32] wire _io_cpu_perf_canAcceptLoadThenLoad_T_26; // @[Consts.scala:90:32] assign _io_cpu_perf_canAcceptLoadThenLoad_T_26 = _GEN_53; // @[Consts.scala:90:32] wire _T_20 = s1_req_cmd == 5'h11; // @[DCache.scala:196:25] wire _s1_write_T_1; // @[Consts.scala:90:49] assign _s1_write_T_1 = _T_20; // @[Consts.scala:90:49] wire _s1_mask_T; // @[DCache.scala:327:32] assign _s1_mask_T = _T_20; // @[DCache.scala:327:32] wire _pstore1_rmw_T_26; // @[Consts.scala:90:49] assign _pstore1_rmw_T_26 = _T_20; // @[Consts.scala:90:49] wire _pstore1_rmw_T_48; // @[DCache.scala:1191:35] assign _pstore1_rmw_T_48 = _T_20; // @[DCache.scala:1191:35] wire _io_cpu_perf_canAcceptLoadThenLoad_T_27; // @[Consts.scala:90:49] assign _io_cpu_perf_canAcceptLoadThenLoad_T_27 = _T_20; // @[Consts.scala:90:49] wire _io_cpu_perf_canAcceptLoadThenLoad_T_49; // @[DCache.scala:1191:35] assign _io_cpu_perf_canAcceptLoadThenLoad_T_49 = _T_20; // @[DCache.scala:1191:35] wire _s1_write_T_2 = _s1_write_T \| _s1_write_T_1; // @[Consts.scala:90:{32,42,49}] wire _s1_write_T_4 = _s1_write_T_2 \| _s1_write_T_3; // @[Consts.scala:90:{42,59,66}] wire _s1_write_T_9 = _s1_write_T_5 \| _s1_write_T_6; // @[package.scala:16:47, :81:59] wire _s1_write_T_10 = _s1_write_T_9 \| _s1_write_T_7; // @[package.scala:16:47, :81:59] wire _s1_write_T_11 = _s1_write_T_10 \| _s1_write_T_8; // @[package.scala:16:47, :81:59] wire _s1_write_T_17 = _s1_write_T_12 \| _s1_write_T_13; // @[package.scala:16:47, :81:59] wire _s1_write_T_18 = _s1_write_T_17 \| _s1_write_T_14; // @[package.scala:16:47, :81:59] wire _s1_write_T_19 = _s1_write_T_18 \| _s1_write_T_15; // @[package.scala:16:47, :81:59] wire _s1_write_T_20 = _s1_write_T_19 \| _s1_write_T_16; // @[package.scala:16:47, :81:59] wire _s1_write_T_21 = _s1_write_T_11 \| _s1_write_T_20; // @[package.scala:81:59] wire s1_write = _s1_write_T_4 \| _s1_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire s1_readwrite = s1_read \| s1_write; // @[DCache.scala:212:30] wire _s1_sfence_T = s1_req_cmd == 5'h14; // @[DCache.scala:196:25, :213:30] wire _GEN_54 = s1_req_cmd == 5'h15; // @[DCache.scala:196:25, :213:57] wire _s1_sfence_T_1; // @[DCache.scala:213:57] assign _s1_sfence_T_1 = _GEN_54; // @[DCache.scala:213:57] wire _tlb_io_sfence_bits_hv_T; // @[DCache.scala:283:39] assign _tlb_io_sfence_bits_hv_T = _GEN_54; // @[DCache.scala:213:57, :283:39] wire _s1_sfence_T_2 = _s1_sfence_T \| _s1_sfence_T_1; // @[DCache.scala:213:{30,43,57}] wire _GEN_55 = s1_req_cmd == 5'h16; // @[DCache.scala:196:25, :213:85] wire _s1_sfence_T_3; // @[DCache.scala:213:85] assign _s1_sfence_T_3 = _GEN_55; // @[DCache.scala:213:85] wire _tlb_io_sfence_bits_hg_T; // @[DCache.scala:284:39] assign _tlb_io_sfence_bits_hg_T = _GEN_55; // @[DCache.scala:213:85, :284:39] wire s1_sfence = _s1_sfence_T_2 \| _s1_sfence_T_3; // @[DCache.scala:213:{43,71,85}] wire _s1_flush_line_T = s1_req_cmd == 5'h5; // @[DCache.scala:196:25, :214:34] wire _s1_flush_line_T_1 = s1_req_size[0]; // @[DCache.scala:196:25, :214:64] wire _tlb_io_sfence_bits_rs1_T = s1_req_size[0]; // @[DCache.scala:196:25, :214:64, :279:40] wire s1_flush_line = _s1_flush_line_T & _s1_flush_line_T_1; // @[DCache.scala:214:{34,50,64}] reg s1_flush_valid; // @[DCache.scala:215:27] reg cached_grant_wait; // @[DCache.scala:223:34] reg resetting; // @[DCache.scala:224:26] assign metaArb_io_in_0_valid = resetting; // @[DCache.scala:135:28, :224:26] reg [8:0] flushCounter; // @[DCache.scala:225:29] reg release_ack_wait; // @[DCache.scala:226:33] reg [31:0] release_ack_addr; // @[DCache.scala:227:29] reg [3:0] release_state; // @[DCache.scala:228:30] reg [7:0] refill_way; // @[DCache.scala:229:23] assign metaArb_io_in_3_bits_way_en = refill_way; // @[DCache.scala:135:28, :229:23] assign dataArb_io_in_1_bits_way_en = refill_way; // @[DCache.scala:152:28, :229:23] wire _any_pstore_valid_T; // @[DCache.scala:508:36] wire any_pstore_valid; // @[DCache.scala:230:30] wire _T_106 = release_state == 4'h1; // @[package.scala:16:47] wire _inWriteback_T; // @[package.scala:16:47] assign _inWriteback_T = _T_106; // @[package.scala:16:47] wire _canAcceptCachedGrant_T; // @[package.scala:16:47] assign _canAcceptCachedGrant_T = _T_106; // @[package.scala:16:47] wire _inWriteback_T_1 = release_state == 4'h2; // @[package.scala:16:47] wire inWriteback = _inWriteback_T \| _inWriteback_T_1; // @[package.scala:16:47, :81:59] assign metaArb_io_in_4_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24] assign metaArb_io_in_5_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24] assign metaArb_io_in_6_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24] assign metaArb_io_in_7_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24] wire _io_cpu_req_ready_T = ~(\|release_state); // @[DCache.scala:228:30, :233:38] wire _io_cpu_req_ready_T_1 = ~cached_grant_wait; // @[DCache.scala:223:34, :233:54] wire _io_cpu_req_ready_T_2 = _io_cpu_req_ready_T & _io_cpu_req_ready_T_1; // @[DCache.scala:233:{38,51,54}] wire _io_cpu_req_ready_T_3 = ~s1_nack; // @[DCache.scala:185:28, :187:41, :233:76] wire _io_cpu_req_ready_T_4 = _io_cpu_req_ready_T_2 & _io_cpu_req_ready_T_3; // @[DCache.scala:233:{51,73,76}] reg uncachedInFlight_0; // @[DCache.scala:236:33] wire _s2_valid_cached_miss_T_2 = uncachedInFlight_0; // @[DCache.scala:236:33, :425:88] wire _s2_valid_uncached_pending_T_1 = uncachedInFlight_0; // @[DCache.scala:236:33, :430:92] wire _io_cpu_ordered_T_6 = uncachedInFlight_0; // @[DCache.scala:236:33, :929:142] wire _io_cpu_store_pending_T_24 = uncachedInFlight_0; // @[DCache.scala:236:33, :930:97] wire _clock_en_reg_T_22 = uncachedInFlight_0; // @[DCache.scala:236:33, :1072:50] reg [39:0] uncachedReqs_0_addr; // @[DCache.scala:237:25] wire [39:0] uncachedResp_addr = uncachedReqs_0_addr; // @[DCache.scala:237:25, :238:30] reg [6:0] uncachedReqs_0_tag; // @[DCache.scala:237:25] wire [6:0] uncachedResp_tag = uncachedReqs_0_tag; // @[DCache.scala:237:25, :238:30] reg [4:0] uncachedReqs_0_cmd; // @[DCache.scala:237:25] wire [4:0] uncachedResp_cmd = uncachedReqs_0_cmd; // @[DCache.scala:237:25, :238:30] reg [1:0] uncachedReqs_0_size; // @[DCache.scala:237:25] wire [1:0] uncachedResp_size = uncachedReqs_0_size; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_signed; // @[DCache.scala:237:25] wire uncachedResp_signed = uncachedReqs_0_signed; // @[DCache.scala:237:25, :238:30] reg [1:0] uncachedReqs_0_dprv; // @[DCache.scala:237:25] wire [1:0] uncachedResp_dprv = uncachedReqs_0_dprv; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_dv; // @[DCache.scala:237:25] wire uncachedResp_dv = uncachedReqs_0_dv; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_phys; // @[DCache.scala:237:25] wire uncachedResp_phys = uncachedReqs_0_phys; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_no_resp; // @[DCache.scala:237:25] wire uncachedResp_no_resp = uncachedReqs_0_no_resp; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_no_alloc; // @[DCache.scala:237:25] wire uncachedResp_no_alloc = uncachedReqs_0_no_alloc; // @[DCache.scala:237:25, :238:30] reg uncachedReqs_0_no_xcpt; // @[DCache.scala:237:25] wire uncachedResp_no_xcpt = uncachedReqs_0_no_xcpt; // @[DCache.scala:237:25, :238:30] reg [63:0] uncachedReqs_0_data; // @[DCache.scala:237:25] wire [63:0] uncachedResp_data = uncachedReqs_0_data; // @[DCache.scala:237:25, :238:30] reg [7:0] uncachedReqs_0_mask; // @[DCache.scala:237:25] wire [7:0] uncachedResp_mask = uncachedReqs_0_mask; // @[DCache.scala:237:25, :238:30] wire _GEN_56 = io_cpu_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47] wire _s0_read_T; // @[package.scala:16:47] assign _s0_read_T = _GEN_56; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T = _GEN_56; // @[package.scala:16:47] wire _s1_did_read_T; // @[package.scala:16:47] assign _s1_did_read_T = _GEN_56; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T = _GEN_56; // @[package.scala:16:47] wire _GEN_57 = io_cpu_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47] wire _s0_read_T_1; // @[package.scala:16:47] assign _s0_read_T_1 = _GEN_57; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_1; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_1 = _GEN_57; // @[package.scala:16:47] wire _s1_did_read_T_1; // @[package.scala:16:47] assign _s1_did_read_T_1 = _GEN_57; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_1; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_1 = _GEN_57; // @[package.scala:16:47] wire _GEN_58 = io_cpu_req_bits_cmd_0 == 5'h6; // @[package.scala:16:47] wire _s0_read_T_2; // @[package.scala:16:47] assign _s0_read_T_2 = _GEN_58; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_2; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_2 = _GEN_58; // @[package.scala:16:47] wire _s1_did_read_T_2; // @[package.scala:16:47] assign _s1_did_read_T_2 = _GEN_58; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_2; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_2 = _GEN_58; // @[package.scala:16:47] wire _GEN_59 = io_cpu_req_bits_cmd_0 == 5'h7; // @[package.scala:16:47] wire _s0_read_T_3; // @[package.scala:16:47] assign _s0_read_T_3 = _GEN_59; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_3; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_3 = _GEN_59; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_28; // @[Consts.scala:90:66] assign _dataArb_io_in_3_valid_T_28 = _GEN_59; // @[package.scala:16:47] wire _s1_did_read_T_3; // @[package.scala:16:47] assign _s1_did_read_T_3 = _GEN_59; // @[package.scala:16:47] wire _s1_did_read_T_28; // @[Consts.scala:90:66] assign _s1_did_read_T_28 = _GEN_59; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_3; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_3 = _GEN_59; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_28; // @[Consts.scala:90:66] assign _pstore_drain_opportunistic_T_28 = _GEN_59; // @[package.scala:16:47] wire _s0_read_T_4 = _s0_read_T \| _s0_read_T_1; // @[package.scala:16:47, :81:59] wire _s0_read_T_5 = _s0_read_T_4 \| _s0_read_T_2; // @[package.scala:16:47, :81:59] wire _s0_read_T_6 = _s0_read_T_5 \| _s0_read_T_3; // @[package.scala:16:47, :81:59] wire _GEN_60 = io_cpu_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47] wire _s0_read_T_7; // @[package.scala:16:47] assign _s0_read_T_7 = _GEN_60; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_7; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_7 = _GEN_60; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_30; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_30 = _GEN_60; // @[package.scala:16:47] wire _s1_did_read_T_7; // @[package.scala:16:47] assign _s1_did_read_T_7 = _GEN_60; // @[package.scala:16:47] wire _s1_did_read_T_30; // @[package.scala:16:47] assign _s1_did_read_T_30 = _GEN_60; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_7; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_7 = _GEN_60; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_30; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_30 = _GEN_60; // @[package.scala:16:47] wire _GEN_61 = io_cpu_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47] wire _s0_read_T_8; // @[package.scala:16:47] assign _s0_read_T_8 = _GEN_61; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_8; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_8 = _GEN_61; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_31; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_31 = _GEN_61; // @[package.scala:16:47] wire _s1_did_read_T_8; // @[package.scala:16:47] assign _s1_did_read_T_8 = _GEN_61; // @[package.scala:16:47] wire _s1_did_read_T_31; // @[package.scala:16:47] assign _s1_did_read_T_31 = _GEN_61; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_8; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_8 = _GEN_61; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_31; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_31 = _GEN_61; // @[package.scala:16:47] wire _GEN_62 = io_cpu_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47] wire _s0_read_T_9; // @[package.scala:16:47] assign _s0_read_T_9 = _GEN_62; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_9; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_9 = _GEN_62; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_32; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_32 = _GEN_62; // @[package.scala:16:47] wire _s1_did_read_T_9; // @[package.scala:16:47] assign _s1_did_read_T_9 = _GEN_62; // @[package.scala:16:47] wire _s1_did_read_T_32; // @[package.scala:16:47] assign _s1_did_read_T_32 = _GEN_62; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_9; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_9 = _GEN_62; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_32; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_32 = _GEN_62; // @[package.scala:16:47] wire _GEN_63 = io_cpu_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47] wire _s0_read_T_10; // @[package.scala:16:47] assign _s0_read_T_10 = _GEN_63; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_10; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_10 = _GEN_63; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_33; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_33 = _GEN_63; // @[package.scala:16:47] wire _s1_did_read_T_10; // @[package.scala:16:47] assign _s1_did_read_T_10 = _GEN_63; // @[package.scala:16:47] wire _s1_did_read_T_33; // @[package.scala:16:47] assign _s1_did_read_T_33 = _GEN_63; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_10; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_10 = _GEN_63; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_33; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_33 = _GEN_63; // @[package.scala:16:47] wire _s0_read_T_11 = _s0_read_T_7 \| _s0_read_T_8; // @[package.scala:16:47, :81:59] wire _s0_read_T_12 = _s0_read_T_11 \| _s0_read_T_9; // @[package.scala:16:47, :81:59] wire _s0_read_T_13 = _s0_read_T_12 \| _s0_read_T_10; // @[package.scala:16:47, :81:59] wire _GEN_64 = io_cpu_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47] wire _s0_read_T_14; // @[package.scala:16:47] assign _s0_read_T_14 = _GEN_64; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_14; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_14 = _GEN_64; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_37; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_37 = _GEN_64; // @[package.scala:16:47] wire _s1_did_read_T_14; // @[package.scala:16:47] assign _s1_did_read_T_14 = _GEN_64; // @[package.scala:16:47] wire _s1_did_read_T_37; // @[package.scala:16:47] assign _s1_did_read_T_37 = _GEN_64; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_14; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_14 = _GEN_64; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_37; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_37 = _GEN_64; // @[package.scala:16:47] wire _GEN_65 = io_cpu_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47] wire _s0_read_T_15; // @[package.scala:16:47] assign _s0_read_T_15 = _GEN_65; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_15; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_15 = _GEN_65; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_38; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_38 = _GEN_65; // @[package.scala:16:47] wire _s1_did_read_T_15; // @[package.scala:16:47] assign _s1_did_read_T_15 = _GEN_65; // @[package.scala:16:47] wire _s1_did_read_T_38; // @[package.scala:16:47] assign _s1_did_read_T_38 = _GEN_65; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_15; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_15 = _GEN_65; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_38; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_38 = _GEN_65; // @[package.scala:16:47] wire _GEN_66 = io_cpu_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47] wire _s0_read_T_16; // @[package.scala:16:47] assign _s0_read_T_16 = _GEN_66; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_16; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_16 = _GEN_66; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_39; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_39 = _GEN_66; // @[package.scala:16:47] wire _s1_did_read_T_16; // @[package.scala:16:47] assign _s1_did_read_T_16 = _GEN_66; // @[package.scala:16:47] wire _s1_did_read_T_39; // @[package.scala:16:47] assign _s1_did_read_T_39 = _GEN_66; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_16; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_16 = _GEN_66; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_39; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_39 = _GEN_66; // @[package.scala:16:47] wire _GEN_67 = io_cpu_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47] wire _s0_read_T_17; // @[package.scala:16:47] assign _s0_read_T_17 = _GEN_67; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_17; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_17 = _GEN_67; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_40; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_40 = _GEN_67; // @[package.scala:16:47] wire _s1_did_read_T_17; // @[package.scala:16:47] assign _s1_did_read_T_17 = _GEN_67; // @[package.scala:16:47] wire _s1_did_read_T_40; // @[package.scala:16:47] assign _s1_did_read_T_40 = _GEN_67; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_17; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_17 = _GEN_67; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_40; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_40 = _GEN_67; // @[package.scala:16:47] wire _GEN_68 = io_cpu_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47] wire _s0_read_T_18; // @[package.scala:16:47] assign _s0_read_T_18 = _GEN_68; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_18; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_18 = _GEN_68; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_41; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_T_41 = _GEN_68; // @[package.scala:16:47] wire _s1_did_read_T_18; // @[package.scala:16:47] assign _s1_did_read_T_18 = _GEN_68; // @[package.scala:16:47] wire _s1_did_read_T_41; // @[package.scala:16:47] assign _s1_did_read_T_41 = _GEN_68; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_18; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_18 = _GEN_68; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_41; // @[package.scala:16:47] assign _pstore_drain_opportunistic_T_41 = _GEN_68; // @[package.scala:16:47] wire _s0_read_T_19 = _s0_read_T_14 \| _s0_read_T_15; // @[package.scala:16:47, :81:59] wire _s0_read_T_20 = _s0_read_T_19 \| _s0_read_T_16; // @[package.scala:16:47, :81:59] wire _s0_read_T_21 = _s0_read_T_20 \| _s0_read_T_17; // @[package.scala:16:47, :81:59] wire _s0_read_T_22 = _s0_read_T_21 \| _s0_read_T_18; // @[package.scala:16:47, :81:59] wire _s0_read_T_23 = _s0_read_T_13 \| _s0_read_T_22; // @[package.scala:81:59] wire s0_read = _s0_read_T_6 \| _s0_read_T_23; // @[package.scala:81:59] wire _GEN_69 = io_cpu_req_bits_cmd_0 == 5'h1; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_res_T; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_res_T = _GEN_69; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_T_25; // @[Consts.scala:90:32] assign _dataArb_io_in_3_valid_T_25 = _GEN_69; // @[package.scala:16:47] wire _s1_did_read_T_25; // @[Consts.scala:90:32] assign _s1_did_read_T_25 = _GEN_69; // @[package.scala:16:47] wire _pstore_drain_opportunistic_res_T; // @[package.scala:16:47] assign _pstore_drain_opportunistic_res_T = _GEN_69; // @[package.scala:16:47] wire _pstore_drain_opportunistic_T_25; // @[Consts.scala:90:32] assign _pstore_drain_opportunistic_T_25 = _GEN_69; // @[package.scala:16:47] wire _GEN_70 = io_cpu_req_bits_cmd_0 == 5'h3; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_res_T_1; // @[package.scala:16:47] assign _dataArb_io_in_3_valid_res_T_1 = _GEN_70; // @[package.scala:16:47] wire _pstore_drain_opportunistic_res_T_1; // @[package.scala:16:47] assign _pstore_drain_opportunistic_res_T_1 = _GEN_70; // @[package.scala:16:47] wire _dataArb_io_in_3_valid_res_T_2 = _dataArb_io_in_3_valid_res_T \| _dataArb_io_in_3_valid_res_T_1; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_res_T_3 = ~_dataArb_io_in_3_valid_res_T_2; // @[package.scala:81:59] wire dataArb_io_in_3_valid_res = _dataArb_io_in_3_valid_res_T_3; // @[DCache.scala:1185:{15,46}] wire _dataArb_io_in_3_valid_T_4 = _dataArb_io_in_3_valid_T \| _dataArb_io_in_3_valid_T_1; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_5 = _dataArb_io_in_3_valid_T_4 \| _dataArb_io_in_3_valid_T_2; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_6 = _dataArb_io_in_3_valid_T_5 \| _dataArb_io_in_3_valid_T_3; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_11 = _dataArb_io_in_3_valid_T_7 \| _dataArb_io_in_3_valid_T_8; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_12 = _dataArb_io_in_3_valid_T_11 \| _dataArb_io_in_3_valid_T_9; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_13 = _dataArb_io_in_3_valid_T_12 \| _dataArb_io_in_3_valid_T_10; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_19 = _dataArb_io_in_3_valid_T_14 \| _dataArb_io_in_3_valid_T_15; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_20 = _dataArb_io_in_3_valid_T_19 \| _dataArb_io_in_3_valid_T_16; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_21 = _dataArb_io_in_3_valid_T_20 \| _dataArb_io_in_3_valid_T_17; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_22 = _dataArb_io_in_3_valid_T_21 \| _dataArb_io_in_3_valid_T_18; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_23 = _dataArb_io_in_3_valid_T_13 \| _dataArb_io_in_3_valid_T_22; // @[package.scala:81:59] wire _dataArb_io_in_3_valid_T_24 = _dataArb_io_in_3_valid_T_6 \| _dataArb_io_in_3_valid_T_23; // @[package.scala:81:59] wire _GEN_71 = io_cpu_req_bits_cmd_0 == 5'h11; // @[DCache.scala:101:7] wire _dataArb_io_in_3_valid_T_26; // @[Consts.scala:90:49] assign _dataArb_io_in_3_valid_T_26 = _GEN_71; // @[Consts.scala:90:49] wire _dataArb_io_in_3_valid_T_48; // @[DCache.scala:1191:35] assign _dataArb_io_in_3_valid_T_48 = _GEN_71; // @[DCache.scala:1191:35] wire _s1_did_read_T_26; // @[Consts.scala:90:49] assign _s1_did_read_T_26 = _GEN_71; // @[Consts.scala:90:49] wire _s1_did_read_T_48; // @[DCache.scala:1191:35] assign _s1_did_read_T_48 = _GEN_71; // @[DCache.scala:1191:35] wire _pstore_drain_opportunistic_T_26; // @[Consts.scala:90:49] assign _pstore_drain_opportunistic_T_26 = _GEN_71; // @[Consts.scala:90:49] wire _pstore_drain_opportunistic_T_48; // @[DCache.scala:1191:35] assign _pstore_drain_opportunistic_T_48 = _GEN_71; // @[DCache.scala:1191:35] wire _dataArb_io_in_3_valid_T_27 = _dataArb_io_in_3_valid_T_25 \| _dataArb_io_in_3_valid_T_26; // @[Consts.scala:90:{32,42,49}] wire _dataArb_io_in_3_valid_T_29 = _dataArb_io_in_3_valid_T_27 \| _dataArb_io_in_3_valid_T_28; // @[Consts.scala:90:{42,59,66}] wire _dataArb_io_in_3_valid_T_34 = _dataArb_io_in_3_valid_T_30 \| _dataArb_io_in_3_valid_T_31; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_35 = _dataArb_io_in_3_valid_T_34 \| _dataArb_io_in_3_valid_T_32; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_36 = _dataArb_io_in_3_valid_T_35 \| _dataArb_io_in_3_valid_T_33; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_42 = _dataArb_io_in_3_valid_T_37 \| _dataArb_io_in_3_valid_T_38; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_43 = _dataArb_io_in_3_valid_T_42 \| _dataArb_io_in_3_valid_T_39; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_44 = _dataArb_io_in_3_valid_T_43 \| _dataArb_io_in_3_valid_T_40; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_45 = _dataArb_io_in_3_valid_T_44 \| _dataArb_io_in_3_valid_T_41; // @[package.scala:16:47, :81:59] wire _dataArb_io_in_3_valid_T_46 = _dataArb_io_in_3_valid_T_36 \| _dataArb_io_in_3_valid_T_45; // @[package.scala:81:59] wire _dataArb_io_in_3_valid_T_47 = _dataArb_io_in_3_valid_T_29 \| _dataArb_io_in_3_valid_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _dataArb_io_in_3_valid_T_50 = _dataArb_io_in_3_valid_T_48; // @[DCache.scala:1191:{35,45}] wire _dataArb_io_in_3_valid_T_51 = _dataArb_io_in_3_valid_T_47 & _dataArb_io_in_3_valid_T_50; // @[DCache.scala:1191:{23,45}] wire _dataArb_io_in_3_valid_T_52 = _dataArb_io_in_3_valid_T_24 \| _dataArb_io_in_3_valid_T_51; // @[DCache.scala:1190:21, :1191:23] wire _dataArb_io_in_3_valid_T_53 = ~_dataArb_io_in_3_valid_T_52; // @[DCache.scala:1186:12, :1190:21] wire _dataArb_io_in_3_valid_T_54 = _dataArb_io_in_3_valid_T_53 \| dataArb_io_in_3_valid_res; // @[DCache.scala:1185:46, :1186:{12,28}] wire _dataArb_io_in_3_valid_T_56 = ~_dataArb_io_in_3_valid_T_55; // @[DCache.scala:1186:11] wire _dataArb_io_in_3_valid_T_57 = ~_dataArb_io_in_3_valid_T_54; // @[DCache.scala:1186:{11,28}] assign _dataArb_io_in_3_valid_T_58 = io_cpu_req_valid_0 & dataArb_io_in_3_valid_res; // @[DCache.scala:101:7, :242:46, :1185:46] assign dataArb_io_in_3_valid = _dataArb_io_in_3_valid_T_58; // @[DCache.scala:152:28, :242:46] wire [27:0] _dataArb_io_in_3_bits_addr_T = io_cpu_req_bits_addr_0[39:12]; // @[DCache.scala:101:7, :245:89] wire [27:0] _metaArb_io_in_1_bits_addr_T = io_cpu_req_bits_addr_0[39:12]; // @[DCache.scala:101:7, :245:89, :454:58] wire [27:0] _metaArb_io_in_2_bits_addr_T = io_cpu_req_bits_addr_0[39:12]; // @[DCache.scala:101:7, :245:89, :466:58] wire [27:0] _metaArb_io_in_3_bits_addr_T = io_cpu_req_bits_addr_0[39:12]; // @[DCache.scala:101:7, :245:89, :745:58] wire [27:0] _metaArb_io_in_4_bits_addr_T = io_cpu_req_bits_addr_0[39:12]; // @[DCache.scala:101:7, :245:89, :912:58] wire [27:0] _metaArb_io_in_5_bits_addr_T = io_cpu_req_bits_addr_0[39:12]; // @[DCache.scala:101:7, :245:89, :1018:58] wire [11:0] _dataArb_io_in_3_bits_addr_T_1 = io_cpu_req_bits_addr_0[11:0]; // @[DCache.scala:101:7, :245:120] wire [39:0] _dataArb_io_in_3_bits_addr_T_2 = {_dataArb_io_in_3_bits_addr_T, _dataArb_io_in_3_bits_addr_T_1}; // @[DCache.scala:245:{36,89,120}] assign dataArb_io_in_3_bits_addr = _dataArb_io_in_3_bits_addr_T_2[11:0]; // @[DCache.scala:152:28, :245:{30,36}] wire _T_4 = ~dataArb_io_in_3_ready & s0_read; // @[DCache.scala:152:28, :258:{9,33}] wire _s1_did_read_T_4 = _s1_did_read_T \| _s1_did_read_T_1; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_5 = _s1_did_read_T_4 \| _s1_did_read_T_2; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_6 = _s1_did_read_T_5 \| _s1_did_read_T_3; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_11 = _s1_did_read_T_7 \| _s1_did_read_T_8; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_12 = _s1_did_read_T_11 \| _s1_did_read_T_9; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_13 = _s1_did_read_T_12 \| _s1_did_read_T_10; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_19 = _s1_did_read_T_14 \| _s1_did_read_T_15; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_20 = _s1_did_read_T_19 \| _s1_did_read_T_16; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_21 = _s1_did_read_T_20 \| _s1_did_read_T_17; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_22 = _s1_did_read_T_21 \| _s1_did_read_T_18; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_23 = _s1_did_read_T_13 \| _s1_did_read_T_22; // @[package.scala:81:59] wire _s1_did_read_T_24 = _s1_did_read_T_6 \| _s1_did_read_T_23; // @[package.scala:81:59] wire _s1_did_read_T_27 = _s1_did_read_T_25 \| _s1_did_read_T_26; // @[Consts.scala:90:{32,42,49}] wire _s1_did_read_T_29 = _s1_did_read_T_27 \| _s1_did_read_T_28; // @[Consts.scala:90:{42,59,66}] wire _s1_did_read_T_34 = _s1_did_read_T_30 \| _s1_did_read_T_31; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_35 = _s1_did_read_T_34 \| _s1_did_read_T_32; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_36 = _s1_did_read_T_35 \| _s1_did_read_T_33; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_42 = _s1_did_read_T_37 \| _s1_did_read_T_38; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_43 = _s1_did_read_T_42 \| _s1_did_read_T_39; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_44 = _s1_did_read_T_43 \| _s1_did_read_T_40; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_45 = _s1_did_read_T_44 \| _s1_did_read_T_41; // @[package.scala:16:47, :81:59] wire _s1_did_read_T_46 = _s1_did_read_T_36 \| _s1_did_read_T_45; // @[package.scala:81:59] wire _s1_did_read_T_47 = _s1_did_read_T_29 \| _s1_did_read_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _s1_did_read_T_50 = _s1_did_read_T_48; // @[DCache.scala:1191:{35,45}] wire _s1_did_read_T_51 = _s1_did_read_T_47 & _s1_did_read_T_50; // @[DCache.scala:1191:{23,45}] wire _s1_did_read_T_52 = _s1_did_read_T_24 \| _s1_did_read_T_51; // @[DCache.scala:1190:21, :1191:23] wire _s1_did_read_T_53 = io_cpu_req_valid_0 & _s1_did_read_T_52; // @[DCache.scala:101:7, :259:75, :1190:21] wire _s1_did_read_T_54 = dataArb_io_in_3_ready & _s1_did_read_T_53; // @[DCache.scala:152:28, :259:{54,75}] reg s1_did_read; // @[DCache.scala:259:30] wire _s2_data_word_en_T = s1_did_read; // @[DCache.scala:259:30, :367:63] assign _metaArb_io_in_7_bits_idx_T = _dataArb_io_in_3_bits_addr_T_2[11:6]; // @[DCache.scala:245:36, :263:58] assign metaArb_io_in_7_bits_idx = _metaArb_io_in_7_bits_idx_T; // @[DCache.scala:135:28, :263:58] wire _s1_cmd_uses_tlb_T = s1_readwrite \| s1_flush_line; // @[DCache.scala:212:30, :214:50, :270:38] wire _s1_cmd_uses_tlb_T_1 = s1_req_cmd == 5'h17; // @[DCache.scala:196:25, :270:69] wire s1_cmd_uses_tlb = _s1_cmd_uses_tlb_T \| _s1_cmd_uses_tlb_T_1; // @[DCache.scala:270:{38,55,69}] wire _tlb_io_req_valid_T = ~io_cpu_s1_kill_0; // @[DCache.scala:101:7, :186:37, :273:55] wire _tlb_io_req_valid_T_1 = s1_valid & _tlb_io_req_valid_T; // @[DCache.scala:182:25, :273:{52,55}] wire _tlb_io_req_valid_T_2 = _tlb_io_req_valid_T_1 & s1_cmd_uses_tlb; // @[DCache.scala:270:55, :273:{52,71}] wire _tlb_io_req_valid_T_3 = _tlb_io_req_valid_T_2; // @[DCache.scala:273:{40,71}] wire _s1_xcpt_valid_T_1 = _tlb_io_req_valid_T_3; // @[DCache.scala:273:40, :932:40] wire _T_10 = ~_tlb_io_req_ready & ~io_ptw_resp_valid_0 & ~io_cpu_req_bits_phys_0; // @[DCache.scala:101:7, :119:19, :275:{9,27,30,53,56}] wire _T_14 = s1_valid & s1_cmd_uses_tlb & _tlb_io_resp_miss; // @[DCache.scala:119:19, :182:25, :270:55, :276:{39,58}] wire _tlb_io_sfence_valid_T = ~io_cpu_s1_kill_0; // @[DCache.scala:101:7, :186:37, :278:38] wire _tlb_io_sfence_valid_T_1 = s1_valid & _tlb_io_sfence_valid_T; // @[DCache.scala:182:25, :278:{35,38}] wire _tlb_io_sfence_valid_T_2 = _tlb_io_sfence_valid_T_1 & s1_sfence; // @[DCache.scala:213:71, :278:{35,54}] wire _tlb_io_sfence_bits_rs2_T = s1_req_size[1]; // @[DCache.scala:196:25, :280:40] wire [19:0] _s1_paddr_T = s1_req_addr[31:12]; // @[DCache.scala:196:25, :298:55] wire [19:0] _s1_paddr_T_1 = _tlb_io_resp_paddr[31:12]; // @[DCache.scala:119:19, :298:99] wire [19:0] _s1_paddr_T_2 = _s1_paddr_T_1; // @[DCache.scala:298:{25,99}] wire [31:0] s1_paddr = {_s1_paddr_T_2, _s1_paddr_T_3}; // @[DCache.scala:298:{21,25,125}] wire [2:0] _s1_victim_way_T; // @[package.scala:163:13] wire [2:0] s1_victim_way; // @[DCache.scala:299:27] assign rockettile_dcache_tag_array_MPORT_en = metaArb_io_out_valid & metaArb_io_out_bits_write; // @[DCache.scala:135:28, :310:27] assign wmask_0 = metaArb_io_out_bits_way_en[0]; // @[DCache.scala:135:28, :311:74] assign wmask_1 = metaArb_io_out_bits_way_en[1]; // @[DCache.scala:135:28, :311:74] assign wmask_2 = metaArb_io_out_bits_way_en[2]; // @[DCache.scala:135:28, :311:74] assign wmask_3 = metaArb_io_out_bits_way_en[3]; // @[DCache.scala:135:28, :311:74] assign wmask_4 = metaArb_io_out_bits_way_en[4]; // @[DCache.scala:135:28, :311:74] assign wmask_5 = metaArb_io_out_bits_way_en[5]; // @[DCache.scala:135:28, :311:74] assign wmask_6 = metaArb_io_out_bits_way_en[6]; // @[DCache.scala:135:28, :311:74] assign wmask_7 = metaArb_io_out_bits_way_en[7]; // @[DCache.scala:135:28, :311:74] wire _s1_meta_T = ~metaArb_io_out_bits_write; // @[DCache.scala:135:28, :190:43, :314:62] assign _s1_meta_T_1 = metaArb_io_out_valid & _s1_meta_T; // @[DCache.scala:135:28, :314:{59,62}] wire [1:0] _s1_meta_uncorrected_T_1; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_0_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_0_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T = _s1_meta_uncorrected_WIRE[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_0_tag = _s1_meta_uncorrected_T; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_1 = _s1_meta_uncorrected_WIRE[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_0_coh_state = _s1_meta_uncorrected_T_1; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_3; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_2; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_1_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_1_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_2 = _s1_meta_uncorrected_WIRE_1[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_1_tag = _s1_meta_uncorrected_T_2; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_3 = _s1_meta_uncorrected_WIRE_1[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_1_coh_state = _s1_meta_uncorrected_T_3; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_5; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_4; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_2_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_2_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_4 = _s1_meta_uncorrected_WIRE_2[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_2_tag = _s1_meta_uncorrected_T_4; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_5 = _s1_meta_uncorrected_WIRE_2[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_2_coh_state = _s1_meta_uncorrected_T_5; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_7; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_6; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_3_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_3_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_6 = _s1_meta_uncorrected_WIRE_3[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_3_tag = _s1_meta_uncorrected_T_6; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_7 = _s1_meta_uncorrected_WIRE_3[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_3_coh_state = _s1_meta_uncorrected_T_7; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_9; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_8; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_4_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_4_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_8 = _s1_meta_uncorrected_WIRE_4[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_4_tag = _s1_meta_uncorrected_T_8; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_9 = _s1_meta_uncorrected_WIRE_4[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_4_coh_state = _s1_meta_uncorrected_T_9; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_11; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_10; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_5_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_5_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_10 = _s1_meta_uncorrected_WIRE_5[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_5_tag = _s1_meta_uncorrected_T_10; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_11 = _s1_meta_uncorrected_WIRE_5[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_5_coh_state = _s1_meta_uncorrected_T_11; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_13; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_12; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_6_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_6_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_12 = _s1_meta_uncorrected_WIRE_6[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_6_tag = _s1_meta_uncorrected_T_12; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_13 = _s1_meta_uncorrected_WIRE_6[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_6_coh_state = _s1_meta_uncorrected_T_13; // @[DCache.scala:315:80] wire [1:0] _s1_meta_uncorrected_T_15; // @[DCache.scala:315:80] wire [19:0] _s1_meta_uncorrected_T_14; // @[DCache.scala:315:80] wire [1:0] s1_meta_uncorrected_7_coh_state; // @[DCache.scala:315:80] wire [19:0] s1_meta_uncorrected_7_tag; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_14 = _s1_meta_uncorrected_WIRE_7[19:0]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_7_tag = _s1_meta_uncorrected_T_14; // @[DCache.scala:315:80] assign _s1_meta_uncorrected_T_15 = _s1_meta_uncorrected_WIRE_7[21:20]; // @[DCache.scala:315:80] assign s1_meta_uncorrected_7_coh_state = _s1_meta_uncorrected_T_15; // @[DCache.scala:315:80] wire [19:0] s1_tag = s1_paddr[31:12]; // @[DCache.scala:298:21, :316:29] wire _s1_meta_hit_way_T = \|s1_meta_uncorrected_0_coh_state; // @[Metadata.scala:50:45] wire _GEN_72 = s1_meta_uncorrected_0_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_1; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_1 = _GEN_72; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T = _GEN_72; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_2 = _s1_meta_hit_way_T & _s1_meta_hit_way_T_1; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_3 = \|s1_meta_uncorrected_1_coh_state; // @[Metadata.scala:50:45] wire _GEN_73 = s1_meta_uncorrected_1_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_4; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_4 = _GEN_73; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_4; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_4 = _GEN_73; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_5 = _s1_meta_hit_way_T_3 & _s1_meta_hit_way_T_4; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_6 = \|s1_meta_uncorrected_2_coh_state; // @[Metadata.scala:50:45] wire _GEN_74 = s1_meta_uncorrected_2_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_7; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_7 = _GEN_74; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_8; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_8 = _GEN_74; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_8 = _s1_meta_hit_way_T_6 & _s1_meta_hit_way_T_7; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_9 = \|s1_meta_uncorrected_3_coh_state; // @[Metadata.scala:50:45] wire _GEN_75 = s1_meta_uncorrected_3_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_10; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_10 = _GEN_75; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_12; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_12 = _GEN_75; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_11 = _s1_meta_hit_way_T_9 & _s1_meta_hit_way_T_10; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_12 = \|s1_meta_uncorrected_4_coh_state; // @[Metadata.scala:50:45] wire _GEN_76 = s1_meta_uncorrected_4_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_13; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_13 = _GEN_76; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_16; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_16 = _GEN_76; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_14 = _s1_meta_hit_way_T_12 & _s1_meta_hit_way_T_13; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_15 = \|s1_meta_uncorrected_5_coh_state; // @[Metadata.scala:50:45] wire _GEN_77 = s1_meta_uncorrected_5_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_16; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_16 = _GEN_77; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_20; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_20 = _GEN_77; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_17 = _s1_meta_hit_way_T_15 & _s1_meta_hit_way_T_16; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_18 = \|s1_meta_uncorrected_6_coh_state; // @[Metadata.scala:50:45] wire _GEN_78 = s1_meta_uncorrected_6_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_19; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_19 = _GEN_78; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_24; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_24 = _GEN_78; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_20 = _s1_meta_hit_way_T_18 & _s1_meta_hit_way_T_19; // @[Metadata.scala:50:45] wire _s1_meta_hit_way_T_21 = \|s1_meta_uncorrected_7_coh_state; // @[Metadata.scala:50:45] wire _GEN_79 = s1_meta_uncorrected_7_tag == s1_tag; // @[DCache.scala:315:80, :316:29, :317:83] wire _s1_meta_hit_way_T_22; // @[DCache.scala:317:83] assign _s1_meta_hit_way_T_22 = _GEN_79; // @[DCache.scala:317:83] wire _s1_meta_hit_state_T_28; // @[DCache.scala:319:48] assign _s1_meta_hit_state_T_28 = _GEN_79; // @[DCache.scala:317:83, :319:48] wire _s1_meta_hit_way_T_23 = _s1_meta_hit_way_T_21 & _s1_meta_hit_way_T_22; // @[Metadata.scala:50:45] wire [1:0] s1_meta_hit_way_lo_lo = {_s1_meta_hit_way_T_5, _s1_meta_hit_way_T_2}; // @[package.scala:45:27] wire [1:0] s1_meta_hit_way_lo_hi = {_s1_meta_hit_way_T_11, _s1_meta_hit_way_T_8}; // @[package.scala:45:27] wire [3:0] s1_meta_hit_way_lo = {s1_meta_hit_way_lo_hi, s1_meta_hit_way_lo_lo}; // @[package.scala:45:27] wire [1:0] s1_meta_hit_way_hi_lo = {_s1_meta_hit_way_T_17, _s1_meta_hit_way_T_14}; // @[package.scala:45:27] wire [1:0] s1_meta_hit_way_hi_hi = {_s1_meta_hit_way_T_23, _s1_meta_hit_way_T_20}; // @[package.scala:45:27] wire [3:0] s1_meta_hit_way_hi = {s1_meta_hit_way_hi_hi, s1_meta_hit_way_hi_lo}; // @[package.scala:45:27] wire [7:0] s1_hit_way = {s1_meta_hit_way_hi, s1_meta_hit_way_lo}; // @[package.scala:45:27] wire _s1_meta_hit_state_T_1 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_2 = _s1_meta_hit_state_T & _s1_meta_hit_state_T_1; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_3 = _s1_meta_hit_state_T_2 ? s1_meta_uncorrected_0_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_5 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_6 = _s1_meta_hit_state_T_4 & _s1_meta_hit_state_T_5; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_7 = _s1_meta_hit_state_T_6 ? s1_meta_uncorrected_1_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_9 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_10 = _s1_meta_hit_state_T_8 & _s1_meta_hit_state_T_9; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_11 = _s1_meta_hit_state_T_10 ? s1_meta_uncorrected_2_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_13 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_14 = _s1_meta_hit_state_T_12 & _s1_meta_hit_state_T_13; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_15 = _s1_meta_hit_state_T_14 ? s1_meta_uncorrected_3_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_17 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_18 = _s1_meta_hit_state_T_16 & _s1_meta_hit_state_T_17; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_19 = _s1_meta_hit_state_T_18 ? s1_meta_uncorrected_4_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_21 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_22 = _s1_meta_hit_state_T_20 & _s1_meta_hit_state_T_21; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_23 = _s1_meta_hit_state_T_22 ? s1_meta_uncorrected_5_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_25 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_26 = _s1_meta_hit_state_T_24 & _s1_meta_hit_state_T_25; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_27 = _s1_meta_hit_state_T_26 ? s1_meta_uncorrected_6_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire _s1_meta_hit_state_T_29 = ~s1_flush_valid; // @[DCache.scala:215:27, :319:62] wire _s1_meta_hit_state_T_30 = _s1_meta_hit_state_T_28 & _s1_meta_hit_state_T_29; // @[DCache.scala:319:{48,59,62}] wire [1:0] _s1_meta_hit_state_T_31 = _s1_meta_hit_state_T_30 ? s1_meta_uncorrected_7_coh_state : 2'h0; // @[DCache.scala:315:80, :319:{41,59}] wire [1:0] _s1_meta_hit_state_T_32 = _s1_meta_hit_state_T_3 \| _s1_meta_hit_state_T_7; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_T_33 = _s1_meta_hit_state_T_32 \| _s1_meta_hit_state_T_11; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_T_34 = _s1_meta_hit_state_T_33 \| _s1_meta_hit_state_T_15; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_T_35 = _s1_meta_hit_state_T_34 \| _s1_meta_hit_state_T_19; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_T_36 = _s1_meta_hit_state_T_35 \| _s1_meta_hit_state_T_23; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_T_37 = _s1_meta_hit_state_T_36 \| _s1_meta_hit_state_T_27; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_T_38 = _s1_meta_hit_state_T_37 \| _s1_meta_hit_state_T_31; // @[DCache.scala:319:41, :320:19] wire [1:0] _s1_meta_hit_state_WIRE = _s1_meta_hit_state_T_38; // @[DCache.scala:320:{19,32}] wire [1:0] _s1_meta_hit_state_T_39; // @[DCache.scala:320:32] wire [1:0] s1_hit_state_state; // @[DCache.scala:320:32] assign _s1_meta_hit_state_T_39 = _s1_meta_hit_state_WIRE; // @[DCache.scala:320:32] assign s1_hit_state_state = _s1_meta_hit_state_T_39; // @[DCache.scala:320:32] wire [7:0] _s1_data_way_T = inWriteback ? releaseWay : s1_hit_way; // @[package.scala:45:27, :81:59] wire [8:0] s1_data_way; // @[DCache.scala:323:32] wire [7:0] _tl_d_data_encoded_T = nodeOut_d_bits_data[7:0]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_14 = nodeOut_d_bits_data[7:0]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_1 = nodeOut_d_bits_data[15:8]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_15 = nodeOut_d_bits_data[15:8]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_2 = nodeOut_d_bits_data[23:16]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_16 = nodeOut_d_bits_data[23:16]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_3 = nodeOut_d_bits_data[31:24]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_17 = nodeOut_d_bits_data[31:24]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_4 = nodeOut_d_bits_data[39:32]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_18 = nodeOut_d_bits_data[39:32]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_5 = nodeOut_d_bits_data[47:40]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_19 = nodeOut_d_bits_data[47:40]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_6 = nodeOut_d_bits_data[55:48]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_20 = nodeOut_d_bits_data[55:48]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_7 = nodeOut_d_bits_data[63:56]; // @[package.scala:211:50] wire [7:0] _tl_d_data_encoded_T_21 = nodeOut_d_bits_data[63:56]; // @[package.scala:211:50] wire [15:0] tl_d_data_encoded_lo_lo = {_tl_d_data_encoded_T_1, _tl_d_data_encoded_T}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_lo_hi = {_tl_d_data_encoded_T_3, _tl_d_data_encoded_T_2}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_lo = {tl_d_data_encoded_lo_hi, tl_d_data_encoded_lo_lo}; // @[package.scala:45:27] wire [15:0] tl_d_data_encoded_hi_lo = {_tl_d_data_encoded_T_5, _tl_d_data_encoded_T_4}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_hi_hi = {_tl_d_data_encoded_T_7, _tl_d_data_encoded_T_6}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_hi = {tl_d_data_encoded_hi_hi, tl_d_data_encoded_hi_lo}; // @[package.scala:45:27] wire [63:0] _tl_d_data_encoded_T_8 = {tl_d_data_encoded_hi, tl_d_data_encoded_lo}; // @[package.scala:45:27] wire [63:0] _tl_d_data_encoded_T_22; // @[package.scala:45:27] assign dataArb_io_in_1_bits_wdata = tl_d_data_encoded; // @[DCache.scala:152:28, :324:31] assign dataArb_io_in_2_bits_wdata = tl_d_data_encoded; // @[DCache.scala:152:28, :324:31] assign dataArb_io_in_3_bits_wdata = tl_d_data_encoded; // @[DCache.scala:152:28, :324:31] wire [63:0] s1_all_data_ways_8 = tl_d_data_encoded; // @[DCache.scala:324:31, :325:33] wire [63:0] s2_data_s1_way_words_0_0 = s1_all_data_ways_0; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_1_0 = s1_all_data_ways_1; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_2_0 = s1_all_data_ways_2; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_3_0 = s1_all_data_ways_3; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_4_0 = s1_all_data_ways_4; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_5_0 = s1_all_data_ways_5; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_6_0 = s1_all_data_ways_6; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_7_0 = s1_all_data_ways_7; // @[package.scala:211:50] wire [63:0] s2_data_s1_way_words_8_0 = s1_all_data_ways_8; // @[package.scala:211:50] wire _s1_mask_xwr_upper_T = s1_req_addr[0]; // @[DCache.scala:196:25] wire _s1_mask_xwr_lower_T = s1_req_addr[0]; // @[DCache.scala:196:25] wire _s1_mask_xwr_upper_T_1 = _s1_mask_xwr_upper_T; // @[AMOALU.scala:20:{22,27}] wire _s1_mask_xwr_upper_T_2 = \|s1_mask_xwr_size; // @[AMOALU.scala:11:18, :20:53] wire _s1_mask_xwr_upper_T_3 = _s1_mask_xwr_upper_T_2; // @[AMOALU.scala:20:{47,53}] wire s1_mask_xwr_upper = _s1_mask_xwr_upper_T_1 \| _s1_mask_xwr_upper_T_3; // @[AMOALU.scala:20:{22,42,47}] wire s1_mask_xwr_lower = ~_s1_mask_xwr_lower_T; // @[AMOALU.scala:21:{22,27}] wire [1:0] _s1_mask_xwr_T = {s1_mask_xwr_upper, s1_mask_xwr_lower}; // @[AMOALU.scala:20:42, :21:22, :22:16] wire _s1_mask_xwr_upper_T_4 = s1_req_addr[1]; // @[DCache.scala:196:25] wire _s1_mask_xwr_lower_T_1 = s1_req_addr[1]; // @[DCache.scala:196:25] wire [1:0] _s1_mask_xwr_upper_T_5 = _s1_mask_xwr_upper_T_4 ? _s1_mask_xwr_T : 2'h0; // @[AMOALU.scala:20:{22,27}, :22:16] wire _s1_mask_xwr_upper_T_6 = s1_mask_xwr_size[1]; // @[AMOALU.scala:11:18, :20:53] wire [1:0] _s1_mask_xwr_upper_T_7 = {2{_s1_mask_xwr_upper_T_6}}; // @[AMOALU.scala:20:{47,53}] wire [1:0] s1_mask_xwr_upper_1 = _s1_mask_xwr_upper_T_5 \| _s1_mask_xwr_upper_T_7; // @[AMOALU.scala:20:{22,42,47}] wire [1:0] s1_mask_xwr_lower_1 = _s1_mask_xwr_lower_T_1 ? 2'h0 : _s1_mask_xwr_T; // @[AMOALU.scala:21:{22,27}, :22:16] wire [3:0] _s1_mask_xwr_T_1 = {s1_mask_xwr_upper_1, s1_mask_xwr_lower_1}; // @[AMOALU.scala:20:42, :21:22, :22:16] wire _s1_mask_xwr_upper_T_8 = s1_req_addr[2]; // @[DCache.scala:196:25] wire _s1_mask_xwr_lower_T_2 = s1_req_addr[2]; // @[DCache.scala:196:25] wire [3:0] _s1_mask_xwr_upper_T_9 = _s1_mask_xwr_upper_T_8 ? _s1_mask_xwr_T_1 : 4'h0; // @[AMOALU.scala:20:{22,27}, :22:16] wire _s1_mask_xwr_upper_T_10 = &s1_mask_xwr_size; // @[AMOALU.scala:11:18, :20:53] wire [3:0] _s1_mask_xwr_upper_T_11 = {4{_s1_mask_xwr_upper_T_10}}; // @[AMOALU.scala:20:{47,53}] wire [3:0] s1_mask_xwr_upper_2 = _s1_mask_xwr_upper_T_9 \| _s1_mask_xwr_upper_T_11; // @[AMOALU.scala:20:{22,42,47}] wire [3:0] s1_mask_xwr_lower_2 = _s1_mask_xwr_lower_T_2 ? 4'h0 : _s1_mask_xwr_T_1; // @[AMOALU.scala:21:{22,27}, :22:16] wire [7:0] s1_mask_xwr = {s1_mask_xwr_upper_2, s1_mask_xwr_lower_2}; // @[AMOALU.scala:20:42, :21:22, :22:16] wire [7:0] s1_mask = _s1_mask_T ? io_cpu_s1_data_mask_0 : s1_mask_xwr; // @[DCache.scala:101:7, :327:{20,32}] wire _s2_valid_T = ~s1_sfence; // @[DCache.scala:213:71, :331:45] wire _s2_valid_T_1 = s1_valid_masked & _s2_valid_T; // @[DCache.scala:186:34, :331:{42,45}] reg s2_valid; // @[DCache.scala:331:25] wire [1:0] _s2_valid_no_xcpt_T = {io_cpu_s2_xcpt_ae_ld_0, io_cpu_s2_xcpt_ae_st_0}; // @[DCache.scala:101:7, :332:54] wire [1:0] _s2_valid_no_xcpt_T_2 = {io_cpu_s2_xcpt_pf_ld_0, io_cpu_s2_xcpt_pf_st_0}; // @[DCache.scala:101:7, :332:54] wire [1:0] _s2_valid_no_xcpt_T_3 = {io_cpu_s2_xcpt_ma_ld_0, io_cpu_s2_xcpt_ma_st_0}; // @[DCache.scala:101:7, :332:54] wire [3:0] s2_valid_no_xcpt_lo = {2'h0, _s2_valid_no_xcpt_T}; // @[DCache.scala:332:54] wire [3:0] s2_valid_no_xcpt_hi = {_s2_valid_no_xcpt_T_3, _s2_valid_no_xcpt_T_2}; // @[DCache.scala:332:54] wire [7:0] _s2_valid_no_xcpt_T_4 = {s2_valid_no_xcpt_hi, s2_valid_no_xcpt_lo}; // @[DCache.scala:332:54] wire _s2_valid_no_xcpt_T_5 = \|_s2_valid_no_xcpt_T_4; // @[DCache.scala:332:{54,61}] wire _s2_valid_no_xcpt_T_6 = ~_s2_valid_no_xcpt_T_5; // @[DCache.scala:332:{38,61}] wire s2_valid_no_xcpt = s2_valid & _s2_valid_no_xcpt_T_6; // @[DCache.scala:331:25, :332:{35,38}] reg s2_probe; // @[DCache.scala:333:25] wire _releaseInFlight_T = s1_probe \| s2_probe; // @[DCache.scala:183:25, :333:25, :334:34] wire _releaseInFlight_T_1 = \|release_state; // @[DCache.scala:228:30, :233:38, :334:63] wire releaseInFlight = _releaseInFlight_T \| _releaseInFlight_T_1; // @[DCache.scala:334:{34,46,63}] wire _s2_not_nacked_in_s1_T = ~s1_nack; // @[DCache.scala:185:28, :187:41, :335:37] reg s2_not_nacked_in_s1; // @[DCache.scala:335:36] wire s2_valid_not_nacked_in_s1 = s2_valid & s2_not_nacked_in_s1; // @[DCache.scala:331:25, :335:36, :336:44] wire s2_valid_masked = s2_valid_no_xcpt & s2_not_nacked_in_s1; // @[DCache.scala:332:35, :335:36, :337:42] wire s2_valid_not_killed = s2_valid_masked; // @[DCache.scala:337:42, :338:45] wire _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T_1 = s2_valid_masked; // @[DCache.scala:337:42, :397:71] wire _s2_dont_nack_misc_T_1 = s2_valid_masked; // @[DCache.scala:337:42, :441:43] reg [39:0] s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_14 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _put_legal_T_14 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _putpartial_legal_T_14 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_4 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_58 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_112 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_166 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_220 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_274 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_328 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_382 = s2_req_addr; // @[DCache.scala:339:19] wire [39:0] _atomics_legal_T_436 = s2_req_addr; // @[DCache.scala:339:19] reg [6:0] s2_req_tag; // @[DCache.scala:339:19] assign io_cpu_resp_bits_tag_0 = s2_req_tag; // @[DCache.scala:101:7, :339:19] reg [4:0] s2_req_cmd; // @[DCache.scala:339:19] assign io_cpu_resp_bits_cmd_0 = s2_req_cmd; // @[DCache.scala:101:7, :339:19] reg [1:0] s2_req_size; // @[DCache.scala:339:19] assign io_cpu_resp_bits_size_0 = s2_req_size; // @[DCache.scala:101:7, :339:19] wire [1:0] size = s2_req_size; // @[DCache.scala:339:19] reg s2_req_signed; // @[DCache.scala:339:19] assign io_cpu_resp_bits_signed_0 = s2_req_signed; // @[DCache.scala:101:7, :339:19] reg [1:0] s2_req_dprv; // @[DCache.scala:339:19] assign io_cpu_resp_bits_dprv_0 = s2_req_dprv; // @[DCache.scala:101:7, :339:19] reg s2_req_dv; // @[DCache.scala:339:19] assign io_cpu_resp_bits_dv_0 = s2_req_dv; // @[DCache.scala:101:7, :339:19] reg s2_req_phys; // @[DCache.scala:339:19] reg s2_req_no_resp; // @[DCache.scala:339:19] reg s2_req_no_alloc; // @[DCache.scala:339:19] reg s2_req_no_xcpt; // @[DCache.scala:339:19] reg [63:0] s2_req_data; // @[DCache.scala:339:19] reg [7:0] s2_req_mask; // @[DCache.scala:339:19] assign io_cpu_resp_bits_mask_0 = s2_req_mask; // @[DCache.scala:101:7, :339:19] wire _GEN_80 = s2_req_cmd == 5'h5; // @[DCache.scala:339:19, :340:37] wire _s2_cmd_flush_all_T; // @[DCache.scala:340:37] assign _s2_cmd_flush_all_T = _GEN_80; // @[DCache.scala:340:37] wire _s2_cmd_flush_line_T; // @[DCache.scala:341:38] assign _s2_cmd_flush_line_T = _GEN_80; // @[DCache.scala:340:37, :341:38] wire _s2_cmd_flush_all_T_1 = s2_req_size[0]; // @[DCache.scala:339:19, :340:68] wire _s2_cmd_flush_line_T_1 = s2_req_size[0]; // @[DCache.scala:339:19, :340:68, :341:68] wire _s2_cmd_flush_all_T_2 = ~_s2_cmd_flush_all_T_1; // @[DCache.scala:340:{56,68}] wire s2_cmd_flush_all = _s2_cmd_flush_all_T & _s2_cmd_flush_all_T_2; // @[DCache.scala:340:{37,53,56}] wire s2_cmd_flush_line = _s2_cmd_flush_line_T & _s2_cmd_flush_line_T_1; // @[DCache.scala:341:{38,54,68}] reg s2_tlb_xcpt_miss; // @[DCache.scala:342:24] reg [31:0] s2_tlb_xcpt_paddr; // @[DCache.scala:342:24] reg [39:0] s2_tlb_xcpt_gpa; // @[DCache.scala:342:24] assign io_cpu_s2_gpa_0 = s2_tlb_xcpt_gpa; // @[DCache.scala:101:7, :342:24] reg s2_tlb_xcpt_pf_ld; // @[DCache.scala:342:24] reg s2_tlb_xcpt_pf_st; // @[DCache.scala:342:24] reg s2_tlb_xcpt_pf_inst; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ae_ld; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ae_st; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ae_inst; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ma_ld; // @[DCache.scala:342:24] reg s2_tlb_xcpt_ma_st; // @[DCache.scala:342:24] reg s2_tlb_xcpt_cacheable; // @[DCache.scala:342:24] reg s2_tlb_xcpt_must_alloc; // @[DCache.scala:342:24] reg s2_tlb_xcpt_prefetchable; // @[DCache.scala:342:24] reg [1:0] s2_tlb_xcpt_size; // @[DCache.scala:342:24] reg [4:0] s2_tlb_xcpt_cmd; // @[DCache.scala:342:24] reg s2_pma_miss; // @[DCache.scala:343:19] reg [31:0] s2_pma_paddr; // @[DCache.scala:343:19] reg [39:0] s2_pma_gpa; // @[DCache.scala:343:19] reg s2_pma_pf_ld; // @[DCache.scala:343:19] reg s2_pma_pf_st; // @[DCache.scala:343:19] reg s2_pma_pf_inst; // @[DCache.scala:343:19] reg s2_pma_ae_ld; // @[DCache.scala:343:19] reg s2_pma_ae_st; // @[DCache.scala:343:19] reg s2_pma_ae_inst; // @[DCache.scala:343:19] reg s2_pma_ma_ld; // @[DCache.scala:343:19] reg s2_pma_ma_st; // @[DCache.scala:343:19] reg s2_pma_cacheable; // @[DCache.scala:343:19] reg s2_pma_must_alloc; // @[DCache.scala:343:19] reg s2_pma_prefetchable; // @[DCache.scala:343:19] reg [1:0] s2_pma_size; // @[DCache.scala:343:19] reg [4:0] s2_pma_cmd; // @[DCache.scala:343:19] reg [39:0] s2_uncached_resp_addr; // @[DCache.scala:344:34] wire _T_30 = s1_valid_not_nacked \| s1_flush_valid; // @[DCache.scala:187:38, :215:27, :345:29] wire _s2_vaddr_T; // @[DCache.scala:351:62] assign _s2_vaddr_T = _T_30; // @[DCache.scala:345:29, :351:62] wire _s1_meta_clk_en_T; // @[DCache.scala:357:44] assign _s1_meta_clk_en_T = _T_30; // @[DCache.scala:345:29, :357:44] wire _s2_hit_state_T; // @[DCache.scala:386:66] assign _s2_hit_state_T = _T_30; // @[DCache.scala:345:29, :386:66] wire _s2_victim_way_T; // @[DCache.scala:431:77] assign _s2_victim_way_T = _T_30; // @[DCache.scala:345:29, :431:77] reg [39:0] s2_vaddr_r; // @[DCache.scala:351:31] wire [27:0] _s2_vaddr_T_1 = s2_vaddr_r[39:12]; // @[DCache.scala:351:{31,81}] wire [11:0] _s2_vaddr_T_2 = s2_req_addr[11:0]; // @[DCache.scala:339:19, :351:103] wire [39:0] s2_vaddr = {_s2_vaddr_T_1, _s2_vaddr_T_2}; // @[DCache.scala:351:{21,81,103}] wire _s2_read_T = s2_req_cmd == 5'h0; // @[package.scala:16:47] wire _s2_read_T_1 = s2_req_cmd == 5'h10; // @[package.scala:16:47] wire _GEN_81 = s2_req_cmd == 5'h6; // @[package.scala:16:47] wire _s2_read_T_2; // @[package.scala:16:47] assign _s2_read_T_2 = _GEN_81; // @[package.scala:16:47] wire _r_c_cat_T_48; // @[Consts.scala:91:71] assign _r_c_cat_T_48 = _GEN_81; // @[package.scala:16:47] wire _s2_lr_T; // @[DCache.scala:470:70] assign _s2_lr_T = _GEN_81; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_48; // @[Consts.scala:91:71] assign _metaArb_io_in_3_bits_data_c_cat_T_48 = _GEN_81; // @[package.scala:16:47] wire _GEN_82 = s2_req_cmd == 5'h7; // @[package.scala:16:47] wire _s2_read_T_3; // @[package.scala:16:47] assign _s2_read_T_3 = _GEN_82; // @[package.scala:16:47] wire _s2_write_T_3; // @[Consts.scala:90:66] assign _s2_write_T_3 = _GEN_82; // @[package.scala:16:47] wire _r_c_cat_T_3; // @[Consts.scala:90:66] assign _r_c_cat_T_3 = _GEN_82; // @[package.scala:16:47] wire _r_c_cat_T_26; // @[Consts.scala:90:66] assign _r_c_cat_T_26 = _GEN_82; // @[package.scala:16:47] wire _s2_sc_T; // @[DCache.scala:471:70] assign _s2_sc_T = _GEN_82; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_3; // @[Consts.scala:90:66] assign _metaArb_io_in_3_bits_data_c_cat_T_3 = _GEN_82; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_26; // @[Consts.scala:90:66] assign _metaArb_io_in_3_bits_data_c_cat_T_26 = _GEN_82; // @[package.scala:16:47] wire _io_cpu_store_pending_T_3; // @[Consts.scala:90:66] assign _io_cpu_store_pending_T_3 = _GEN_82; // @[package.scala:16:47] wire _s2_read_T_4 = _s2_read_T \| _s2_read_T_1; // @[package.scala:16:47, :81:59] wire _s2_read_T_5 = _s2_read_T_4 \| _s2_read_T_2; // @[package.scala:16:47, :81:59] wire _s2_read_T_6 = _s2_read_T_5 \| _s2_read_T_3; // @[package.scala:16:47, :81:59] wire _GEN_83 = s2_req_cmd == 5'h4; // @[package.scala:16:47] wire _s2_read_T_7; // @[package.scala:16:47] assign _s2_read_T_7 = _GEN_83; // @[package.scala:16:47] wire _s2_write_T_5; // @[package.scala:16:47] assign _s2_write_T_5 = _GEN_83; // @[package.scala:16:47] wire _r_c_cat_T_5; // @[package.scala:16:47] assign _r_c_cat_T_5 = _GEN_83; // @[package.scala:16:47] wire _r_c_cat_T_28; // @[package.scala:16:47] assign _r_c_cat_T_28 = _GEN_83; // @[package.scala:16:47] wire _atomics_T; // @[DCache.scala:587:81] assign _atomics_T = _GEN_83; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_5; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_5 = _GEN_83; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_28; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_28 = _GEN_83; // @[package.scala:16:47] wire _io_cpu_store_pending_T_5; // @[package.scala:16:47] assign _io_cpu_store_pending_T_5 = _GEN_83; // @[package.scala:16:47] wire _GEN_84 = s2_req_cmd == 5'h9; // @[package.scala:16:47] wire _s2_read_T_8; // @[package.scala:16:47] assign _s2_read_T_8 = _GEN_84; // @[package.scala:16:47] wire _s2_write_T_6; // @[package.scala:16:47] assign _s2_write_T_6 = _GEN_84; // @[package.scala:16:47] wire _r_c_cat_T_6; // @[package.scala:16:47] assign _r_c_cat_T_6 = _GEN_84; // @[package.scala:16:47] wire _r_c_cat_T_29; // @[package.scala:16:47] assign _r_c_cat_T_29 = _GEN_84; // @[package.scala:16:47] wire _atomics_T_2; // @[DCache.scala:587:81] assign _atomics_T_2 = _GEN_84; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_6; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_6 = _GEN_84; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_29; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_29 = _GEN_84; // @[package.scala:16:47] wire _io_cpu_store_pending_T_6; // @[package.scala:16:47] assign _io_cpu_store_pending_T_6 = _GEN_84; // @[package.scala:16:47] wire _GEN_85 = s2_req_cmd == 5'hA; // @[package.scala:16:47] wire _s2_read_T_9; // @[package.scala:16:47] assign _s2_read_T_9 = _GEN_85; // @[package.scala:16:47] wire _s2_write_T_7; // @[package.scala:16:47] assign _s2_write_T_7 = _GEN_85; // @[package.scala:16:47] wire _r_c_cat_T_7; // @[package.scala:16:47] assign _r_c_cat_T_7 = _GEN_85; // @[package.scala:16:47] wire _r_c_cat_T_30; // @[package.scala:16:47] assign _r_c_cat_T_30 = _GEN_85; // @[package.scala:16:47] wire _atomics_T_4; // @[DCache.scala:587:81] assign _atomics_T_4 = _GEN_85; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_7; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_7 = _GEN_85; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_30; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_30 = _GEN_85; // @[package.scala:16:47] wire _io_cpu_store_pending_T_7; // @[package.scala:16:47] assign _io_cpu_store_pending_T_7 = _GEN_85; // @[package.scala:16:47] wire _GEN_86 = s2_req_cmd == 5'hB; // @[package.scala:16:47] wire _s2_read_T_10; // @[package.scala:16:47] assign _s2_read_T_10 = _GEN_86; // @[package.scala:16:47] wire _s2_write_T_8; // @[package.scala:16:47] assign _s2_write_T_8 = _GEN_86; // @[package.scala:16:47] wire _r_c_cat_T_8; // @[package.scala:16:47] assign _r_c_cat_T_8 = _GEN_86; // @[package.scala:16:47] wire _r_c_cat_T_31; // @[package.scala:16:47] assign _r_c_cat_T_31 = _GEN_86; // @[package.scala:16:47] wire _atomics_T_6; // @[DCache.scala:587:81] assign _atomics_T_6 = _GEN_86; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_8; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_8 = _GEN_86; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_31; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_31 = _GEN_86; // @[package.scala:16:47] wire _io_cpu_store_pending_T_8; // @[package.scala:16:47] assign _io_cpu_store_pending_T_8 = _GEN_86; // @[package.scala:16:47] wire _s2_read_T_11 = _s2_read_T_7 \| _s2_read_T_8; // @[package.scala:16:47, :81:59] wire _s2_read_T_12 = _s2_read_T_11 \| _s2_read_T_9; // @[package.scala:16:47, :81:59] wire _s2_read_T_13 = _s2_read_T_12 \| _s2_read_T_10; // @[package.scala:16:47, :81:59] wire _GEN_87 = s2_req_cmd == 5'h8; // @[package.scala:16:47] wire _s2_read_T_14; // @[package.scala:16:47] assign _s2_read_T_14 = _GEN_87; // @[package.scala:16:47] wire _s2_write_T_12; // @[package.scala:16:47] assign _s2_write_T_12 = _GEN_87; // @[package.scala:16:47] wire _r_c_cat_T_12; // @[package.scala:16:47] assign _r_c_cat_T_12 = _GEN_87; // @[package.scala:16:47] wire _r_c_cat_T_35; // @[package.scala:16:47] assign _r_c_cat_T_35 = _GEN_87; // @[package.scala:16:47] wire _atomics_T_8; // @[DCache.scala:587:81] assign _atomics_T_8 = _GEN_87; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_12; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_12 = _GEN_87; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_35; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_35 = _GEN_87; // @[package.scala:16:47] wire _io_cpu_store_pending_T_12; // @[package.scala:16:47] assign _io_cpu_store_pending_T_12 = _GEN_87; // @[package.scala:16:47] wire _GEN_88 = s2_req_cmd == 5'hC; // @[package.scala:16:47] wire _s2_read_T_15; // @[package.scala:16:47] assign _s2_read_T_15 = _GEN_88; // @[package.scala:16:47] wire _s2_write_T_13; // @[package.scala:16:47] assign _s2_write_T_13 = _GEN_88; // @[package.scala:16:47] wire _r_c_cat_T_13; // @[package.scala:16:47] assign _r_c_cat_T_13 = _GEN_88; // @[package.scala:16:47] wire _r_c_cat_T_36; // @[package.scala:16:47] assign _r_c_cat_T_36 = _GEN_88; // @[package.scala:16:47] wire _atomics_T_10; // @[DCache.scala:587:81] assign _atomics_T_10 = _GEN_88; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_13; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_13 = _GEN_88; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_36; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_36 = _GEN_88; // @[package.scala:16:47] wire _io_cpu_store_pending_T_13; // @[package.scala:16:47] assign _io_cpu_store_pending_T_13 = _GEN_88; // @[package.scala:16:47] wire _GEN_89 = s2_req_cmd == 5'hD; // @[package.scala:16:47] wire _s2_read_T_16; // @[package.scala:16:47] assign _s2_read_T_16 = _GEN_89; // @[package.scala:16:47] wire _s2_write_T_14; // @[package.scala:16:47] assign _s2_write_T_14 = _GEN_89; // @[package.scala:16:47] wire _r_c_cat_T_14; // @[package.scala:16:47] assign _r_c_cat_T_14 = _GEN_89; // @[package.scala:16:47] wire _r_c_cat_T_37; // @[package.scala:16:47] assign _r_c_cat_T_37 = _GEN_89; // @[package.scala:16:47] wire _atomics_T_12; // @[DCache.scala:587:81] assign _atomics_T_12 = _GEN_89; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_14; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_14 = _GEN_89; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_37; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_37 = _GEN_89; // @[package.scala:16:47] wire _io_cpu_store_pending_T_14; // @[package.scala:16:47] assign _io_cpu_store_pending_T_14 = _GEN_89; // @[package.scala:16:47] wire _GEN_90 = s2_req_cmd == 5'hE; // @[package.scala:16:47] wire _s2_read_T_17; // @[package.scala:16:47] assign _s2_read_T_17 = _GEN_90; // @[package.scala:16:47] wire _s2_write_T_15; // @[package.scala:16:47] assign _s2_write_T_15 = _GEN_90; // @[package.scala:16:47] wire _r_c_cat_T_15; // @[package.scala:16:47] assign _r_c_cat_T_15 = _GEN_90; // @[package.scala:16:47] wire _r_c_cat_T_38; // @[package.scala:16:47] assign _r_c_cat_T_38 = _GEN_90; // @[package.scala:16:47] wire _atomics_T_14; // @[DCache.scala:587:81] assign _atomics_T_14 = _GEN_90; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_15; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_15 = _GEN_90; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_38; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_38 = _GEN_90; // @[package.scala:16:47] wire _io_cpu_store_pending_T_15; // @[package.scala:16:47] assign _io_cpu_store_pending_T_15 = _GEN_90; // @[package.scala:16:47] wire _GEN_91 = s2_req_cmd == 5'hF; // @[package.scala:16:47] wire _s2_read_T_18; // @[package.scala:16:47] assign _s2_read_T_18 = _GEN_91; // @[package.scala:16:47] wire _s2_write_T_16; // @[package.scala:16:47] assign _s2_write_T_16 = _GEN_91; // @[package.scala:16:47] wire _r_c_cat_T_16; // @[package.scala:16:47] assign _r_c_cat_T_16 = _GEN_91; // @[package.scala:16:47] wire _r_c_cat_T_39; // @[package.scala:16:47] assign _r_c_cat_T_39 = _GEN_91; // @[package.scala:16:47] wire _atomics_T_16; // @[DCache.scala:587:81] assign _atomics_T_16 = _GEN_91; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_16; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_16 = _GEN_91; // @[package.scala:16:47] wire _metaArb_io_in_3_bits_data_c_cat_T_39; // @[package.scala:16:47] assign _metaArb_io_in_3_bits_data_c_cat_T_39 = _GEN_91; // @[package.scala:16:47] wire _io_cpu_store_pending_T_16; // @[package.scala:16:47] assign _io_cpu_store_pending_T_16 = _GEN_91; // @[package.scala:16:47] wire _s2_read_T_19 = _s2_read_T_14 \| _s2_read_T_15; // @[package.scala:16:47, :81:59] wire _s2_read_T_20 = _s2_read_T_19 \| _s2_read_T_16; // @[package.scala:16:47, :81:59] wire _s2_read_T_21 = _s2_read_T_20 \| _s2_read_T_17; // @[package.scala:16:47, :81:59] wire _s2_read_T_22 = _s2_read_T_21 \| _s2_read_T_18; // @[package.scala:16:47, :81:59] wire _s2_read_T_23 = _s2_read_T_13 \| _s2_read_T_22; // @[package.scala:81:59] assign s2_read = _s2_read_T_6 \| _s2_read_T_23; // @[package.scala:81:59] assign io_cpu_resp_bits_has_data_0 = s2_read; // @[DCache.scala:101:7] wire _GEN_92 = s2_req_cmd == 5'h1; // @[DCache.scala:339:19] wire _s2_write_T; // @[Consts.scala:90:32] assign _s2_write_T = _GEN_92; // @[Consts.scala:90:32] wire _r_c_cat_T; // @[Consts.scala:90:32] assign _r_c_cat_T = _GEN_92; // @[Consts.scala:90:32] wire _r_c_cat_T_23; // @[Consts.scala:90:32] assign _r_c_cat_T_23 = _GEN_92; // @[Consts.scala:90:32] wire _metaArb_io_in_3_bits_data_c_cat_T; // @[Consts.scala:90:32] assign _metaArb_io_in_3_bits_data_c_cat_T = _GEN_92; // @[Consts.scala:90:32] wire _metaArb_io_in_3_bits_data_c_cat_T_23; // @[Consts.scala:90:32] assign _metaArb_io_in_3_bits_data_c_cat_T_23 = _GEN_92; // @[Consts.scala:90:32] wire _io_cpu_store_pending_T; // @[Consts.scala:90:32] assign _io_cpu_store_pending_T = _GEN_92; // @[Consts.scala:90:32] wire _GEN_93 = s2_req_cmd == 5'h11; // @[DCache.scala:339:19] wire _s2_write_T_1; // @[Consts.scala:90:49] assign _s2_write_T_1 = _GEN_93; // @[Consts.scala:90:49] wire _r_c_cat_T_1; // @[Consts.scala:90:49] assign _r_c_cat_T_1 = _GEN_93; // @[Consts.scala:90:49] wire _r_c_cat_T_24; // @[Consts.scala:90:49] assign _r_c_cat_T_24 = _GEN_93; // @[Consts.scala:90:49] wire _tl_out_a_bits_T_4; // @[DCache.scala:610:20] assign _tl_out_a_bits_T_4 = _GEN_93; // @[DCache.scala:610:20] wire _uncachedReqs_0_cmd_T; // @[DCache.scala:637:49] assign _uncachedReqs_0_cmd_T = _GEN_93; // @[DCache.scala:637:49] wire _metaArb_io_in_3_bits_data_c_cat_T_1; // @[Consts.scala:90:49] assign _metaArb_io_in_3_bits_data_c_cat_T_1 = _GEN_93; // @[Consts.scala:90:49] wire _metaArb_io_in_3_bits_data_c_cat_T_24; // @[Consts.scala:90:49] assign _metaArb_io_in_3_bits_data_c_cat_T_24 = _GEN_93; // @[Consts.scala:90:49] wire _io_cpu_store_pending_T_1; // @[Consts.scala:90:49] assign _io_cpu_store_pending_T_1 = _GEN_93; // @[Consts.scala:90:49] wire _s2_write_T_2 = _s2_write_T \| _s2_write_T_1; // @[Consts.scala:90:{32,42,49}] wire _s2_write_T_4 = _s2_write_T_2 \| _s2_write_T_3; // @[Consts.scala:90:{42,59,66}] wire _s2_write_T_9 = _s2_write_T_5 \| _s2_write_T_6; // @[package.scala:16:47, :81:59] wire _s2_write_T_10 = _s2_write_T_9 \| _s2_write_T_7; // @[package.scala:16:47, :81:59] wire _s2_write_T_11 = _s2_write_T_10 \| _s2_write_T_8; // @[package.scala:16:47, :81:59] wire _s2_write_T_17 = _s2_write_T_12 \| _s2_write_T_13; // @[package.scala:16:47, :81:59] wire _s2_write_T_18 = _s2_write_T_17 \| _s2_write_T_14; // @[package.scala:16:47, :81:59] wire _s2_write_T_19 = _s2_write_T_18 \| _s2_write_T_15; // @[package.scala:16:47, :81:59] wire _s2_write_T_20 = _s2_write_T_19 \| _s2_write_T_16; // @[package.scala:16:47, :81:59] wire _s2_write_T_21 = _s2_write_T_11 \| _s2_write_T_20; // @[package.scala:81:59] wire s2_write = _s2_write_T_4 \| _s2_write_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire s2_readwrite = s2_read \| s2_write; // @[DCache.scala:354:30] reg s2_flush_valid_pre_tag_ecc; // @[DCache.scala:355:43] wire s2_flush_valid = s2_flush_valid_pre_tag_ecc; // @[DCache.scala:355:43, :363:51] wire s1_meta_clk_en = _s1_meta_clk_en_T \| s1_probe; // @[DCache.scala:183:25, :357:{44,62}] reg [21:0] s2_meta_corrected_r; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE = s2_meta_corrected_r; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_1; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_0_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_0_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T = _s2_meta_corrected_WIRE[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_0_tag = _s2_meta_corrected_T; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_1 = _s2_meta_corrected_WIRE[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_0_coh_state = _s2_meta_corrected_T_1; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_1; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_1 = s2_meta_corrected_r_1; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_3; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_2; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_1_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_1_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_2 = _s2_meta_corrected_WIRE_1[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_1_tag = _s2_meta_corrected_T_2; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_3 = _s2_meta_corrected_WIRE_1[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_1_coh_state = _s2_meta_corrected_T_3; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_2; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_2 = s2_meta_corrected_r_2; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_5; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_4; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_2_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_2_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_4 = _s2_meta_corrected_WIRE_2[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_2_tag = _s2_meta_corrected_T_4; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_5 = _s2_meta_corrected_WIRE_2[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_2_coh_state = _s2_meta_corrected_T_5; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_3; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_3 = s2_meta_corrected_r_3; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_7; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_6; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_3_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_3_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_6 = _s2_meta_corrected_WIRE_3[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_3_tag = _s2_meta_corrected_T_6; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_7 = _s2_meta_corrected_WIRE_3[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_3_coh_state = _s2_meta_corrected_T_7; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_4; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_4 = s2_meta_corrected_r_4; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_9; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_8; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_4_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_4_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_8 = _s2_meta_corrected_WIRE_4[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_4_tag = _s2_meta_corrected_T_8; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_9 = _s2_meta_corrected_WIRE_4[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_4_coh_state = _s2_meta_corrected_T_9; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_5; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_5 = s2_meta_corrected_r_5; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_11; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_10; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_5_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_5_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_10 = _s2_meta_corrected_WIRE_5[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_5_tag = _s2_meta_corrected_T_10; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_11 = _s2_meta_corrected_WIRE_5[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_5_coh_state = _s2_meta_corrected_T_11; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_6; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_6 = s2_meta_corrected_r_6; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_13; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_12; // @[DCache.scala:361:99] wire [1:0] s2_meta_corrected_6_coh_state; // @[DCache.scala:361:99] wire [19:0] s2_meta_corrected_6_tag; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_12 = _s2_meta_corrected_WIRE_6[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_6_tag = _s2_meta_corrected_T_12; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_13 = _s2_meta_corrected_WIRE_6[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_6_coh_state = _s2_meta_corrected_T_13; // @[DCache.scala:361:99] reg [21:0] s2_meta_corrected_r_7; // @[DCache.scala:361:61] wire [21:0] _s2_meta_corrected_WIRE_7 = s2_meta_corrected_r_7; // @[DCache.scala:361:{61,99}] wire [1:0] _s2_meta_corrected_T_15; // @[DCache.scala:361:99] wire [19:0] _s2_meta_corrected_T_14; // @[DCache.scala:361:99] wire [1:0] _s2_first_meta_corrected_T_8_coh_state = s2_meta_corrected_7_coh_state; // @[Mux.scala:50:70] wire [19:0] _s2_first_meta_corrected_T_8_tag = s2_meta_corrected_7_tag; // @[Mux.scala:50:70] assign _s2_meta_corrected_T_14 = _s2_meta_corrected_WIRE_7[19:0]; // @[DCache.scala:361:99] assign s2_meta_corrected_7_tag = _s2_meta_corrected_T_14; // @[DCache.scala:361:99] assign _s2_meta_corrected_T_15 = _s2_meta_corrected_WIRE_7[21:20]; // @[DCache.scala:361:99] assign s2_meta_corrected_7_coh_state = _s2_meta_corrected_T_15; // @[DCache.scala:361:99] wire _s2_data_en_T = s1_valid \| inWriteback; // @[package.scala:81:59] wire s2_data_en = _s2_data_en_T \| io_cpu_replay_next_0; // @[DCache.scala:101:7, :366:{23,38}] wire s2_data_word_en = inWriteback \| _s2_data_word_en_T; // @[package.scala:81:59] wire _s2_data_s1_word_en_T = ~io_cpu_replay_next_0; // @[DCache.scala:101:7, :377:28] wire s2_data_s1_word_en = ~_s2_data_s1_word_en_T \| s2_data_word_en; // @[DCache.scala:367:22, :377:{27,28}] wire _s2_data_T = s2_data_s1_word_en; // @[DCache.scala:377:27, :379:39] wire [8:0] _s2_data_T_1 = _s2_data_T ? s1_data_way : 9'h0; // @[DCache.scala:323:32, :379:{28,39}] wire _s2_data_T_2 = _s2_data_T_1[0]; // @[Mux.scala:32:36] wire _s2_data_T_3 = _s2_data_T_1[1]; // @[Mux.scala:32:36] wire _s2_data_T_4 = _s2_data_T_1[2]; // @[Mux.scala:32:36] wire _s2_data_T_5 = _s2_data_T_1[3]; // @[Mux.scala:32:36] wire _s2_data_T_6 = _s2_data_T_1[4]; // @[Mux.scala:32:36] wire _s2_data_T_7 = _s2_data_T_1[5]; // @[Mux.scala:32:36] wire _s2_data_T_8 = _s2_data_T_1[6]; // @[Mux.scala:32:36] wire _s2_data_T_9 = _s2_data_T_1[7]; // @[Mux.scala:32:36] wire _s2_data_T_10 = _s2_data_T_1[8]; // @[Mux.scala:32:36] wire [63:0] _s2_data_T_11 = _s2_data_T_2 ? s2_data_s1_way_words_0_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_12 = _s2_data_T_3 ? s2_data_s1_way_words_1_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_13 = _s2_data_T_4 ? s2_data_s1_way_words_2_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_14 = _s2_data_T_5 ? s2_data_s1_way_words_3_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_15 = _s2_data_T_6 ? s2_data_s1_way_words_4_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_16 = _s2_data_T_7 ? s2_data_s1_way_words_5_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_17 = _s2_data_T_8 ? s2_data_s1_way_words_6_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_18 = _s2_data_T_9 ? s2_data_s1_way_words_7_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_19 = _s2_data_T_10 ? s2_data_s1_way_words_8_0 : 64'h0; // @[Mux.scala:30:73, :32:36] wire [63:0] _s2_data_T_20 = _s2_data_T_11 \| _s2_data_T_12; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_21 = _s2_data_T_20 \| _s2_data_T_13; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_22 = _s2_data_T_21 \| _s2_data_T_14; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_23 = _s2_data_T_22 \| _s2_data_T_15; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_24 = _s2_data_T_23 \| _s2_data_T_16; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_25 = _s2_data_T_24 \| _s2_data_T_17; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_26 = _s2_data_T_25 \| _s2_data_T_18; // @[Mux.scala:30:73] wire [63:0] _s2_data_T_27 = _s2_data_T_26 \| _s2_data_T_19; // @[Mux.scala:30:73] wire [63:0] _s2_data_WIRE = _s2_data_T_27; // @[Mux.scala:30:73] reg [63:0] s2_data; // @[DCache.scala:379:18] reg [7:0] s2_probe_way; // @[DCache.scala:383:31] reg [1:0] s2_probe_state_state; // @[DCache.scala:384:33] reg [7:0] s2_hit_way; // @[DCache.scala:385:29] reg [1:0] s2_hit_state_state; // @[DCache.scala:386:31] wire s2_hit_valid = \|s2_hit_state_state; // @[Metadata.scala:50:45] wire _r_c_cat_T_2 = _r_c_cat_T \| _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_4 = _r_c_cat_T_2 \| _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_9 = _r_c_cat_T_5 \| _r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_10 = _r_c_cat_T_9 \| _r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_11 = _r_c_cat_T_10 \| _r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_17 = _r_c_cat_T_12 \| _r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_18 = _r_c_cat_T_17 \| _r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_19 = _r_c_cat_T_18 \| _r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_20 = _r_c_cat_T_19 \| _r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_21 = _r_c_cat_T_11 \| _r_c_cat_T_20; // @[package.scala:81:59] wire _r_c_cat_T_22 = _r_c_cat_T_4 \| _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_25 = _r_c_cat_T_23 \| _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_27 = _r_c_cat_T_25 \| _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_32 = _r_c_cat_T_28 \| _r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_33 = _r_c_cat_T_32 \| _r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_34 = _r_c_cat_T_33 \| _r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_40 = _r_c_cat_T_35 \| _r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_41 = _r_c_cat_T_40 \| _r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_42 = _r_c_cat_T_41 \| _r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_43 = _r_c_cat_T_42 \| _r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_44 = _r_c_cat_T_34 \| _r_c_cat_T_43; // @[package.scala:81:59] wire _r_c_cat_T_45 = _r_c_cat_T_27 \| _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_94 = s2_req_cmd == 5'h3; // @[DCache.scala:339:19] wire _r_c_cat_T_46; // @[Consts.scala:91:54] assign _r_c_cat_T_46 = _GEN_94; // @[Consts.scala:91:54] wire _metaArb_io_in_3_bits_data_c_cat_T_46; // @[Consts.scala:91:54] assign _metaArb_io_in_3_bits_data_c_cat_T_46 = _GEN_94; // @[Consts.scala:91:54] wire _r_c_cat_T_47 = _r_c_cat_T_45 \| _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_49 = _r_c_cat_T_47 \| _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r_T = {r_c, s2_hit_state_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_25 = _r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_27 = {1'h0, _r_T_25}; // @[Misc.scala:35:36, :49:20] wire _r_T_28 = _r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_30 = _r_T_28 ? 2'h2 : _r_T_27; // @[Misc.scala:35:36, :49:20] wire _r_T_31 = _r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_33 = _r_T_31 ? 2'h1 : _r_T_30; // @[Misc.scala:35:36, :49:20] wire _r_T_34 = _r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_36 = _r_T_34 ? 2'h2 : _r_T_33; // @[Misc.scala:35:36, :49:20] wire _r_T_37 = _r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_39 = _r_T_37 ? 2'h0 : _r_T_36; // @[Misc.scala:35:36, :49:20] wire _r_T_40 = _r_T == 4'hE; // @[Misc.scala:49:20] wire _r_T_41 = _r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_42 = _r_T_40 ? 2'h3 : _r_T_39; // @[Misc.scala:35:36, :49:20] wire _r_T_43 = &_r_T; // @[Misc.scala:49:20] wire _r_T_44 = _r_T_43 \| _r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_45 = _r_T_43 ? 2'h3 : _r_T_42; // @[Misc.scala:35:36, :49:20] wire _r_T_46 = _r_T == 4'h6; // @[Misc.scala:49:20] wire _r_T_47 = _r_T_46 \| _r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_48 = _r_T_46 ? 2'h2 : _r_T_45; // @[Misc.scala:35:36, :49:20] wire _r_T_49 = _r_T == 4'h7; // @[Misc.scala:49:20] wire _r_T_50 = _r_T_49 \| _r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_51 = _r_T_49 ? 2'h3 : _r_T_48; // @[Misc.scala:35:36, :49:20] wire _r_T_52 = _r_T == 4'h1; // @[Misc.scala:49:20] wire _r_T_53 = _r_T_52 \| _r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_54 = _r_T_52 ? 2'h1 : _r_T_51; // @[Misc.scala:35:36, :49:20] wire _r_T_55 = _r_T == 4'h2; // @[Misc.scala:49:20] wire _r_T_56 = _r_T_55 \| _r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_57 = _r_T_55 ? 2'h2 : _r_T_54; // @[Misc.scala:35:36, :49:20] wire _r_T_58 = _r_T == 4'h3; // @[Misc.scala:49:20] wire s2_hit = _r_T_58 \| _r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] s2_grow_param = _r_T_58 ? 2'h3 : _r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] s2_new_hit_state_state = s2_grow_param; // @[Misc.scala:35:36] wire [1:0] metaArb_io_in_2_bits_data_meta_coh_state = s2_new_hit_state_state; // @[Metadata.scala:160:20] wire [15:0] s2_data_corrected_lo_lo = s2_data[15:0]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_lo_lo = s2_data[15:0]; // @[package.scala:45:27] wire [15:0] s2_data_corrected_lo_hi = s2_data[31:16]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_lo_hi = s2_data[31:16]; // @[package.scala:45:27] wire [31:0] s2_data_corrected_lo = {s2_data_corrected_lo_hi, s2_data_corrected_lo_lo}; // @[package.scala:45:27] wire [15:0] s2_data_corrected_hi_lo = s2_data[47:32]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_hi_lo = s2_data[47:32]; // @[package.scala:45:27] wire [15:0] s2_data_corrected_hi_hi = s2_data[63:48]; // @[package.scala:45:27] wire [15:0] s2_data_uncorrected_hi_hi = s2_data[63:48]; // @[package.scala:45:27] wire [31:0] s2_data_corrected_hi = {s2_data_corrected_hi_hi, s2_data_corrected_hi_lo}; // @[package.scala:45:27] assign s2_data_corrected = {s2_data_corrected_hi, s2_data_corrected_lo}; // @[package.scala:45:27] assign nodeOut_c_bits_data = s2_data_corrected; // @[package.scala:45:27] wire [63:0] s2_data_word_corrected = s2_data_corrected; // @[package.scala:45:27] wire [31:0] s2_data_uncorrected_lo = {s2_data_uncorrected_lo_hi, s2_data_uncorrected_lo_lo}; // @[package.scala:45:27] wire [31:0] s2_data_uncorrected_hi = {s2_data_uncorrected_hi_hi, s2_data_uncorrected_hi_lo}; // @[package.scala:45:27] wire [63:0] s2_data_uncorrected = {s2_data_uncorrected_hi, s2_data_uncorrected_lo}; // @[package.scala:45:27] assign s2_data_word = s2_data_uncorrected; // @[package.scala:45:27] wire s2_valid_hit_maybe_flush_pre_data_ecc_and_waw = _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T_1 & s2_hit; // @[Misc.scala:35:9] wire _s2_valid_hit_pre_data_ecc_and_waw_T = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw & s2_readwrite; // @[DCache.scala:354:30, :397:89, :418:89] wire s2_valid_hit_pre_data_ecc_and_waw = _s2_valid_hit_pre_data_ecc_and_waw_T; // @[DCache.scala:418:{89,105}] wire s2_valid_hit_pre_data_ecc = s2_valid_hit_pre_data_ecc_and_waw; // @[DCache.scala:418:105, :420:69] wire s2_valid_flush_line = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw & s2_cmd_flush_line; // @[DCache.scala:341:54, :397:89, :419:75] wire _s2_victim_tag_T = s2_valid_flush_line; // @[DCache.scala:419:75, :433:47] wire s2_valid_hit = s2_valid_hit_pre_data_ecc; // @[DCache.scala:420:69, :422:48] wire _s2_valid_miss_T = s2_valid_masked & s2_readwrite; // @[DCache.scala:337:42, :354:30, :423:39] wire _s2_valid_miss_T_2 = _s2_valid_miss_T; // @[DCache.scala:423:{39,55}] wire _s2_valid_miss_T_3 = ~s2_hit; // @[Misc.scala:35:9] wire s2_valid_miss = _s2_valid_miss_T_2 & _s2_valid_miss_T_3; // @[DCache.scala:423:{55,73,76}] wire _s2_uncached_T = ~s2_pma_cacheable; // @[DCache.scala:343:19, :424:21] wire _s2_uncached_T_1 = ~s2_pma_must_alloc; // @[DCache.scala:343:19, :424:61] wire _s2_uncached_T_2 = s2_req_no_alloc & _s2_uncached_T_1; // @[DCache.scala:339:19, :424:{58,61}] wire _s2_uncached_T_3 = ~s2_hit_valid; // @[Metadata.scala:50:45] wire _s2_uncached_T_4 = _s2_uncached_T_2 & _s2_uncached_T_3; // @[DCache.scala:424:{58,80,83}] wire s2_uncached = _s2_uncached_T \| _s2_uncached_T_4; // @[DCache.scala:424:{21,39,80}] wire _s2_valid_cached_miss_T = ~s2_uncached; // @[DCache.scala:424:39, :425:47] wire _s2_valid_cached_miss_T_1 = s2_valid_miss & _s2_valid_cached_miss_T; // @[DCache.scala:423:73, :425:{44,47}] wire _s2_valid_cached_miss_T_3 = ~_s2_valid_cached_miss_T_2; // @[DCache.scala:425:{63,88}] wire s2_valid_cached_miss = _s2_valid_cached_miss_T_1 & _s2_valid_cached_miss_T_3; // @[DCache.scala:425:{44,60,63}] wire _s2_want_victimize_T = s2_valid_cached_miss \| s2_valid_flush_line; // @[DCache.scala:419:75, :425:60, :427:77] wire _s2_want_victimize_T_1 = _s2_want_victimize_T; // @[DCache.scala:427:{77,100}] wire _s2_want_victimize_T_2 = _s2_want_victimize_T_1 \| s2_flush_valid; // @[DCache.scala:363:51, :427:{100,123}] wire s2_want_victimize = _s2_want_victimize_T_2; // @[DCache.scala:427:{52,123}] wire s2_victimize = s2_want_victimize; // @[DCache.scala:427:52, :429:40] wire _s2_cannot_victimize_T = ~s2_flush_valid; // @[DCache.scala:363:51, :428:29] wire _s2_valid_uncached_pending_T = s2_valid_miss & s2_uncached; // @[DCache.scala:423:73, :424:39, :430:49] wire _s2_valid_uncached_pending_T_2 = ~_s2_valid_uncached_pending_T_1; // @[DCache.scala:430:{67,92}] wire s2_valid_uncached_pending = _s2_valid_uncached_pending_T & _s2_valid_uncached_pending_T_2; // @[DCache.scala:430:{49,64,67}] reg [2:0] s2_victim_way_r; // @[DCache.scala:431:41] wire [7:0] s2_victim_way = 8'h1 << s2_victim_way_r; // @[OneHot.scala:58:35] assign s2_victim_or_hit_way = s2_hit_valid ? s2_hit_way : s2_victim_way; // @[OneHot.scala:58:35] assign metaArb_io_in_2_bits_way_en = s2_victim_or_hit_way; // @[DCache.scala:135:28, :432:33] wire [19:0] _s2_victim_tag_T_1 = s2_req_addr[31:12]; // @[DCache.scala:339:19, :433:82] wire _s2_victim_tag_T_2 = s2_victim_way[0]; // @[OneHot.scala:58:35] wire _s2_victim_state_T = s2_victim_way[0]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_3 = s2_victim_way[1]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_1 = s2_victim_way[1]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_4 = s2_victim_way[2]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_2 = s2_victim_way[2]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_5 = s2_victim_way[3]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_3 = s2_victim_way[3]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_6 = s2_victim_way[4]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_4 = s2_victim_way[4]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_7 = s2_victim_way[5]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_5 = s2_victim_way[5]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_8 = s2_victim_way[6]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_6 = s2_victim_way[6]; // @[OneHot.scala:58:35] wire _s2_victim_tag_T_9 = s2_victim_way[7]; // @[OneHot.scala:58:35] wire _s2_victim_state_T_7 = s2_victim_way[7]; // @[OneHot.scala:58:35] wire [1:0] _s2_victim_tag_WIRE_2_state; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_WIRE_1; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_10 = _s2_victim_tag_T_2 ? s2_meta_corrected_0_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_11 = _s2_victim_tag_T_3 ? s2_meta_corrected_1_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_12 = _s2_victim_tag_T_4 ? s2_meta_corrected_2_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_13 = _s2_victim_tag_T_5 ? s2_meta_corrected_3_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_14 = _s2_victim_tag_T_6 ? s2_meta_corrected_4_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_15 = _s2_victim_tag_T_7 ? s2_meta_corrected_5_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_16 = _s2_victim_tag_T_8 ? s2_meta_corrected_6_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_17 = _s2_victim_tag_T_9 ? s2_meta_corrected_7_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_tag_T_18 = _s2_victim_tag_T_10 \| _s2_victim_tag_T_11; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_19 = _s2_victim_tag_T_18 \| _s2_victim_tag_T_12; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_20 = _s2_victim_tag_T_19 \| _s2_victim_tag_T_13; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_21 = _s2_victim_tag_T_20 \| _s2_victim_tag_T_14; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_22 = _s2_victim_tag_T_21 \| _s2_victim_tag_T_15; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_23 = _s2_victim_tag_T_22 \| _s2_victim_tag_T_16; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_T_24 = _s2_victim_tag_T_23 \| _s2_victim_tag_T_17; // @[Mux.scala:30:73] assign _s2_victim_tag_WIRE_1 = _s2_victim_tag_T_24; // @[Mux.scala:30:73] wire [19:0] _s2_victim_tag_WIRE_tag = _s2_victim_tag_WIRE_1; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_WIRE_3; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_WIRE_coh_state = _s2_victim_tag_WIRE_2_state; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_25 = _s2_victim_tag_T_2 ? s2_meta_corrected_0_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_26 = _s2_victim_tag_T_3 ? s2_meta_corrected_1_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_27 = _s2_victim_tag_T_4 ? s2_meta_corrected_2_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_28 = _s2_victim_tag_T_5 ? s2_meta_corrected_3_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_29 = _s2_victim_tag_T_6 ? s2_meta_corrected_4_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_30 = _s2_victim_tag_T_7 ? s2_meta_corrected_5_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_31 = _s2_victim_tag_T_8 ? s2_meta_corrected_6_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_32 = _s2_victim_tag_T_9 ? s2_meta_corrected_7_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_tag_T_33 = _s2_victim_tag_T_25 \| _s2_victim_tag_T_26; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_34 = _s2_victim_tag_T_33 \| _s2_victim_tag_T_27; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_35 = _s2_victim_tag_T_34 \| _s2_victim_tag_T_28; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_36 = _s2_victim_tag_T_35 \| _s2_victim_tag_T_29; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_37 = _s2_victim_tag_T_36 \| _s2_victim_tag_T_30; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_38 = _s2_victim_tag_T_37 \| _s2_victim_tag_T_31; // @[Mux.scala:30:73] wire [1:0] _s2_victim_tag_T_39 = _s2_victim_tag_T_38 \| _s2_victim_tag_T_32; // @[Mux.scala:30:73] assign _s2_victim_tag_WIRE_3 = _s2_victim_tag_T_39; // @[Mux.scala:30:73] assign _s2_victim_tag_WIRE_2_state = _s2_victim_tag_WIRE_3; // @[Mux.scala:30:73] wire [19:0] s2_victim_tag = _s2_victim_tag_T ? _s2_victim_tag_T_1 : _s2_victim_tag_WIRE_tag; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_WIRE_2_state; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_WIRE_1; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_8 = _s2_victim_state_T ? s2_meta_corrected_0_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_9 = _s2_victim_state_T_1 ? s2_meta_corrected_1_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_10 = _s2_victim_state_T_2 ? s2_meta_corrected_2_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_11 = _s2_victim_state_T_3 ? s2_meta_corrected_3_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_12 = _s2_victim_state_T_4 ? s2_meta_corrected_4_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_13 = _s2_victim_state_T_5 ? s2_meta_corrected_5_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_14 = _s2_victim_state_T_6 ? s2_meta_corrected_6_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_15 = _s2_victim_state_T_7 ? s2_meta_corrected_7_tag : 20'h0; // @[Mux.scala:30:73, :32:36] wire [19:0] _s2_victim_state_T_16 = _s2_victim_state_T_8 \| _s2_victim_state_T_9; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_17 = _s2_victim_state_T_16 \| _s2_victim_state_T_10; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_18 = _s2_victim_state_T_17 \| _s2_victim_state_T_11; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_19 = _s2_victim_state_T_18 \| _s2_victim_state_T_12; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_20 = _s2_victim_state_T_19 \| _s2_victim_state_T_13; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_21 = _s2_victim_state_T_20 \| _s2_victim_state_T_14; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_T_22 = _s2_victim_state_T_21 \| _s2_victim_state_T_15; // @[Mux.scala:30:73] assign _s2_victim_state_WIRE_1 = _s2_victim_state_T_22; // @[Mux.scala:30:73] wire [19:0] _s2_victim_state_WIRE_tag = _s2_victim_state_WIRE_1; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_WIRE_3; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_WIRE_coh_state = _s2_victim_state_WIRE_2_state; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_23 = _s2_victim_state_T ? s2_meta_corrected_0_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_24 = _s2_victim_state_T_1 ? s2_meta_corrected_1_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_25 = _s2_victim_state_T_2 ? s2_meta_corrected_2_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_26 = _s2_victim_state_T_3 ? s2_meta_corrected_3_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_27 = _s2_victim_state_T_4 ? s2_meta_corrected_4_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_28 = _s2_victim_state_T_5 ? s2_meta_corrected_5_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_29 = _s2_victim_state_T_6 ? s2_meta_corrected_6_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_30 = _s2_victim_state_T_7 ? s2_meta_corrected_7_coh_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _s2_victim_state_T_31 = _s2_victim_state_T_23 \| _s2_victim_state_T_24; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_32 = _s2_victim_state_T_31 \| _s2_victim_state_T_25; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_33 = _s2_victim_state_T_32 \| _s2_victim_state_T_26; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_34 = _s2_victim_state_T_33 \| _s2_victim_state_T_27; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_35 = _s2_victim_state_T_34 \| _s2_victim_state_T_28; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_36 = _s2_victim_state_T_35 \| _s2_victim_state_T_29; // @[Mux.scala:30:73] wire [1:0] _s2_victim_state_T_37 = _s2_victim_state_T_36 \| _s2_victim_state_T_30; // @[Mux.scala:30:73] assign _s2_victim_state_WIRE_3 = _s2_victim_state_T_37; // @[Mux.scala:30:73] assign _s2_victim_state_WIRE_2_state = _s2_victim_state_WIRE_3; // @[Mux.scala:30:73] wire [1:0] s2_victim_state_state = s2_hit_valid ? s2_hit_state_state : _s2_victim_state_WIRE_coh_state; // @[Mux.scala:30:73] wire [3:0] _r_T_59 = {probe_bits_param, s2_probe_state_state}; // @[Metadata.scala:120:19] wire _r_T_72 = _r_T_59 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_74 = _r_T_72 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_76 = _r_T_59 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_78 = _r_T_76 ? 3'h2 : _r_T_74; // @[Misc.scala:38:36, :56:20] wire _r_T_80 = _r_T_59 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_82 = _r_T_80 ? 3'h1 : _r_T_78; // @[Misc.scala:38:36, :56:20] wire _r_T_84 = _r_T_59 == 4'hB; // @[Misc.scala:56:20] wire _r_T_85 = _r_T_84; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_86 = _r_T_84 ? 3'h1 : _r_T_82; // @[Misc.scala:38:36, :56:20] wire _r_T_88 = _r_T_59 == 4'h4; // @[Misc.scala:56:20] wire _r_T_89 = ~_r_T_88 & _r_T_85; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_90 = _r_T_88 ? 3'h5 : _r_T_86; // @[Misc.scala:38:36, :56:20] wire _r_T_92 = _r_T_59 == 4'h5; // @[Misc.scala:56:20] wire _r_T_93 = ~_r_T_92 & _r_T_89; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_94 = _r_T_92 ? 3'h4 : _r_T_90; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_95 = {1'h0, _r_T_92}; // @[Misc.scala:38:63, :56:20] wire _r_T_96 = _r_T_59 == 4'h6; // @[Misc.scala:56:20] wire _r_T_97 = ~_r_T_96 & _r_T_93; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_98 = _r_T_96 ? 3'h0 : _r_T_94; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_99 = _r_T_96 ? 2'h1 : _r_T_95; // @[Misc.scala:38:63, :56:20] wire _r_T_100 = _r_T_59 == 4'h7; // @[Misc.scala:56:20] wire _r_T_101 = _r_T_100 \| _r_T_97; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_102 = _r_T_100 ? 3'h0 : _r_T_98; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_103 = _r_T_100 ? 2'h1 : _r_T_99; // @[Misc.scala:38:63, :56:20] wire _r_T_104 = _r_T_59 == 4'h0; // @[Misc.scala:56:20] wire _r_T_105 = ~_r_T_104 & _r_T_101; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_106 = _r_T_104 ? 3'h5 : _r_T_102; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_107 = _r_T_104 ? 2'h0 : _r_T_103; // @[Misc.scala:38:63, :56:20] wire _r_T_108 = _r_T_59 == 4'h1; // @[Misc.scala:56:20] wire _r_T_109 = ~_r_T_108 & _r_T_105; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_110 = _r_T_108 ? 3'h4 : _r_T_106; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_111 = _r_T_108 ? 2'h1 : _r_T_107; // @[Misc.scala:38:63, :56:20] wire _r_T_112 = _r_T_59 == 4'h2; // @[Misc.scala:56:20] wire _r_T_113 = ~_r_T_112 & _r_T_109; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_114 = _r_T_112 ? 3'h3 : _r_T_110; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_115 = _r_T_112 ? 2'h2 : _r_T_111; // @[Misc.scala:38:63, :56:20] wire _r_T_116 = _r_T_59 == 4'h3; // @[Misc.scala:56:20] wire s2_prb_ack_data = _r_T_116 \| _r_T_113; // @[Misc.scala:38:9, :56:20] wire [2:0] s2_report_param = _r_T_116 ? 3'h3 : _r_T_114; // @[Misc.scala:38:36, :56:20] wire [2:0] cleanReleaseMessage_param = s2_report_param; // @[Misc.scala:38:36] wire [2:0] dirtyReleaseMessage_param = s2_report_param; // @[Misc.scala:38:36] wire [1:0] r_3 = _r_T_116 ? 2'h2 : _r_T_115; // @[Misc.scala:38:63, :56:20] wire [1:0] probeNewCoh_state = r_3; // @[Misc.scala:38:63] wire [3:0] _r_T_123 = {2'h2, s2_victim_state_state}; // @[Metadata.scala:120:19] wire _r_T_136 = _r_T_123 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_138 = _r_T_136 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_140 = _r_T_123 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_142 = _r_T_140 ? 3'h2 : _r_T_138; // @[Misc.scala:38:36, :56:20] wire _r_T_144 = _r_T_123 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_146 = _r_T_144 ? 3'h1 : _r_T_142; // @[Misc.scala:38:36, :56:20] wire _r_T_148 = _r_T_123 == 4'hB; // @[Misc.scala:56:20] wire _r_T_149 = _r_T_148; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_150 = _r_T_148 ? 3'h1 : _r_T_146; // @[Misc.scala:38:36, :56:20] wire _r_T_152 = _r_T_123 == 4'h4; // @[Misc.scala:56:20] wire _r_T_153 = ~_r_T_152 & _r_T_149; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_154 = _r_T_152 ? 3'h5 : _r_T_150; // @[Misc.scala:38:36, :56:20] wire _r_T_156 = _r_T_123 == 4'h5; // @[Misc.scala:56:20] wire _r_T_157 = ~_r_T_156 & _r_T_153; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_158 = _r_T_156 ? 3'h4 : _r_T_154; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_159 = {1'h0, _r_T_156}; // @[Misc.scala:38:63, :56:20] wire _r_T_160 = _r_T_123 == 4'h6; // @[Misc.scala:56:20] wire _r_T_161 = ~_r_T_160 & _r_T_157; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_162 = _r_T_160 ? 3'h0 : _r_T_158; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_163 = _r_T_160 ? 2'h1 : _r_T_159; // @[Misc.scala:38:63, :56:20] wire _r_T_164 = _r_T_123 == 4'h7; // @[Misc.scala:56:20] wire _r_T_165 = _r_T_164 \| _r_T_161; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_166 = _r_T_164 ? 3'h0 : _r_T_162; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_167 = _r_T_164 ? 2'h1 : _r_T_163; // @[Misc.scala:38:63, :56:20] wire _r_T_168 = _r_T_123 == 4'h0; // @[Misc.scala:56:20] wire _r_T_169 = ~_r_T_168 & _r_T_165; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_170 = _r_T_168 ? 3'h5 : _r_T_166; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_171 = _r_T_168 ? 2'h0 : _r_T_167; // @[Misc.scala:38:63, :56:20] wire _r_T_172 = _r_T_123 == 4'h1; // @[Misc.scala:56:20] wire _r_T_173 = ~_r_T_172 & _r_T_169; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_174 = _r_T_172 ? 3'h4 : _r_T_170; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_175 = _r_T_172 ? 2'h1 : _r_T_171; // @[Misc.scala:38:63, :56:20] wire _r_T_176 = _r_T_123 == 4'h2; // @[Misc.scala:56:20] wire _r_T_177 = ~_r_T_176 & _r_T_173; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_178 = _r_T_176 ? 3'h3 : _r_T_174; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_179 = _r_T_176 ? 2'h2 : _r_T_175; // @[Misc.scala:38:63, :56:20] wire _r_T_180 = _r_T_123 == 4'h3; // @[Misc.scala:56:20] wire s2_victim_dirty = _r_T_180 \| _r_T_177; // @[Misc.scala:38:9, :56:20] wire [2:0] s2_shrink_param = _r_T_180 ? 3'h3 : _r_T_178; // @[Misc.scala:38:36, :56:20] wire [2:0] nodeOut_c_bits_c_param = s2_shrink_param; // @[Misc.scala:38:36] wire [2:0] nodeOut_c_bits_c_1_param = s2_shrink_param; // @[Misc.scala:38:36] wire [1:0] r_3_1 = _r_T_180 ? 2'h2 : _r_T_179; // @[Misc.scala:38:63, :56:20] wire [1:0] voluntaryNewCoh_state = r_3_1; // @[Misc.scala:38:63] wire _s2_update_meta_T = s2_hit_state_state == s2_new_hit_state_state; // @[Metadata.scala:46:46, :160:20] wire s2_update_meta = ~_s2_update_meta_T; // @[Metadata.scala:46:46, :47:40] wire s2_dont_nack_uncached = s2_valid_uncached_pending & tl_out_a_ready; // @[DCache.scala:159:22, :430:64, :440:57] wire _s2_dont_nack_misc_T_7 = ~s2_hit; // @[Misc.scala:35:9] wire _s2_dont_nack_misc_T_10 = s2_req_cmd == 5'h17; // @[DCache.scala:339:19, :444:17] wire _s2_dont_nack_misc_T_11 = _s2_dont_nack_misc_T_10; // @[DCache.scala:443:55, :444:17] wire s2_dont_nack_misc = _s2_dont_nack_misc_T_1 & _s2_dont_nack_misc_T_11; // @[DCache.scala:441:{43,61}, :443:55] wire _io_cpu_s2_nack_T = ~s2_dont_nack_uncached; // @[DCache.scala:440:57, :445:41] wire _io_cpu_s2_nack_T_1 = s2_valid_no_xcpt & _io_cpu_s2_nack_T; // @[DCache.scala:332:35, :445:{38,41}] wire _io_cpu_s2_nack_T_2 = ~s2_dont_nack_misc; // @[DCache.scala:441:61, :445:67] wire _io_cpu_s2_nack_T_3 = _io_cpu_s2_nack_T_1 & _io_cpu_s2_nack_T_2; // @[DCache.scala:445:{38,64,67}] wire _io_cpu_s2_nack_T_4 = ~s2_valid_hit; // @[DCache.scala:422:48, :445:89] assign _io_cpu_s2_nack_T_5 = _io_cpu_s2_nack_T_3 & _io_cpu_s2_nack_T_4; // @[DCache.scala:445:{64,86,89}] assign io_cpu_s2_nack_0 = _io_cpu_s2_nack_T_5; // @[DCache.scala:101:7, :445:86] assign _metaArb_io_in_2_valid_T = s2_valid_hit_pre_data_ecc_and_waw & s2_update_meta; // @[Metadata.scala:47:40] wire _T_40 = io_cpu_s2_nack_0 \| _metaArb_io_in_2_valid_T; // @[DCache.scala:101:7, :446:24, :462:63] wire [1:0] _s2_first_meta_corrected_T_9_coh_state = _s2_first_meta_corrected_T_8_coh_state; // @[Mux.scala:50:70] wire [19:0] _s2_first_meta_corrected_T_9_tag = _s2_first_meta_corrected_T_8_tag; // @[Mux.scala:50:70] wire [1:0] _s2_first_meta_corrected_T_10_coh_state = _s2_first_meta_corrected_T_9_coh_state; // @[Mux.scala:50:70] wire [19:0] _s2_first_meta_corrected_T_10_tag = _s2_first_meta_corrected_T_9_tag; // @[Mux.scala:50:70] wire [1:0] _s2_first_meta_corrected_T_11_coh_state = _s2_first_meta_corrected_T_10_coh_state; // @[Mux.scala:50:70] wire [19:0] _s2_first_meta_corrected_T_11_tag = _s2_first_meta_corrected_T_10_tag; // @[Mux.scala:50:70] wire [1:0] _s2_first_meta_corrected_T_12_coh_state = _s2_first_meta_corrected_T_11_coh_state; // @[Mux.scala:50:70] wire [19:0] _s2_first_meta_corrected_T_12_tag = _s2_first_meta_corrected_T_11_tag; // @[Mux.scala:50:70] wire [1:0] _s2_first_meta_corrected_T_13_coh_state = _s2_first_meta_corrected_T_12_coh_state; // @[Mux.scala:50:70] wire [19:0] _s2_first_meta_corrected_T_13_tag = _s2_first_meta_corrected_T_12_tag; // @[Mux.scala:50:70] wire [1:0] s2_first_meta_corrected_coh_state = _s2_first_meta_corrected_T_13_coh_state; // @[Mux.scala:50:70] wire [19:0] s2_first_meta_corrected_tag = _s2_first_meta_corrected_T_13_tag; // @[Mux.scala:50:70] wire [1:0] metaArb_io_in_1_bits_data_new_meta_coh_state = s2_first_meta_corrected_coh_state; // @[Mux.scala:50:70] wire [19:0] metaArb_io_in_1_bits_data_new_meta_tag = s2_first_meta_corrected_tag; // @[Mux.scala:50:70] wire _metaArb_io_in_1_valid_T = s2_valid_masked \| s2_flush_valid_pre_tag_ecc; // @[DCache.scala:337:42, :355:43, :450:63] wire _metaArb_io_in_1_valid_T_1 = _metaArb_io_in_1_valid_T \| s2_probe; // @[DCache.scala:333:25, :450:{63,93}] wire [5:0] _metaArb_io_in_1_bits_idx_T = probe_bits_address[11:6]; // @[DCache.scala:184:29, :1200:47] wire [5:0] _metaArb_io_in_6_bits_idx_T_1 = probe_bits_address[11:6]; // @[DCache.scala:184:29, :1200:47] wire [5:0] _dataArb_io_in_2_bits_addr_T = probe_bits_address[11:6]; // @[DCache.scala:184:29, :1200:47] assign _metaArb_io_in_4_bits_idx_T = probe_bits_address[11:6]; // @[DCache.scala:184:29, :1200:47] wire [5:0] _metaArb_io_in_1_bits_idx_T_1 = s2_vaddr[11:6]; // @[DCache.scala:351:21, :453:76] assign _metaArb_io_in_2_bits_idx_T = s2_vaddr[11:6]; // @[DCache.scala:351:21, :453:76, :465:40] assign _metaArb_io_in_3_bits_idx_T = s2_vaddr[11:6]; // @[DCache.scala:351:21, :453:76, :744:40] assign _metaArb_io_in_1_bits_idx_T_2 = s2_probe ? _metaArb_io_in_1_bits_idx_T : _metaArb_io_in_1_bits_idx_T_1; // @[DCache.scala:333:25, :453:{35,76}, :1200:47] assign metaArb_io_in_1_bits_idx = _metaArb_io_in_1_bits_idx_T_2; // @[DCache.scala:135:28, :453:35] wire [11:0] _metaArb_io_in_1_bits_addr_T_1 = {_metaArb_io_in_1_bits_idx_T_2, 6'h0}; // @[DCache.scala:453:35, :454:98] assign _metaArb_io_in_1_bits_addr_T_2 = {_metaArb_io_in_1_bits_addr_T, _metaArb_io_in_1_bits_addr_T_1}; // @[DCache.scala:454:{36,58,98}] assign metaArb_io_in_1_bits_addr = _metaArb_io_in_1_bits_addr_T_2; // @[DCache.scala:135:28, :454:36] assign _metaArb_io_in_1_bits_data_T = {metaArb_io_in_1_bits_data_new_meta_coh_state, metaArb_io_in_1_bits_data_new_meta_tag}; // @[DCache.scala:456:31, :458:14] assign metaArb_io_in_1_bits_data = _metaArb_io_in_1_bits_data_T; // @[DCache.scala:135:28, :458:14] assign metaArb_io_in_2_valid = _metaArb_io_in_2_valid_T; // @[DCache.scala:135:28, :462:63] assign metaArb_io_in_2_bits_idx = _metaArb_io_in_2_bits_idx_T; // @[DCache.scala:135:28, :465:40] wire [11:0] _metaArb_io_in_2_bits_addr_T_1 = s2_vaddr[11:0]; // @[DCache.scala:351:21, :466:80] wire [11:0] _metaArb_io_in_3_bits_addr_T_1 = s2_vaddr[11:0]; // @[DCache.scala:351:21, :466:80, :745:80] assign _metaArb_io_in_2_bits_addr_T_2 = {_metaArb_io_in_2_bits_addr_T, _metaArb_io_in_2_bits_addr_T_1}; // @[DCache.scala:466:{36,58,80}] assign metaArb_io_in_2_bits_addr = _metaArb_io_in_2_bits_addr_T_2; // @[DCache.scala:135:28, :466:36] wire [27:0] _metaArb_io_in_2_bits_data_T = s2_req_addr[39:12]; // @[DCache.scala:339:19, :467:68] wire [27:0] _metaArb_io_in_3_bits_data_T = s2_req_addr[39:12]; // @[DCache.scala:339:19, :467:68, :746:68] wire [19:0] metaArb_io_in_2_bits_data_meta_tag; // @[HellaCache.scala:305:20] assign metaArb_io_in_2_bits_data_meta_tag = _metaArb_io_in_2_bits_data_T[19:0]; // @[HellaCache.scala:305:20, :306:14] assign _metaArb_io_in_2_bits_data_T_1 = {metaArb_io_in_2_bits_data_meta_coh_state, metaArb_io_in_2_bits_data_meta_tag}; // @[HellaCache.scala:305:20] assign metaArb_io_in_2_bits_data = _metaArb_io_in_2_bits_data_T_1; // @[DCache.scala:135:28, :467:97] wire s2_lr = _s2_lr_T; // @[DCache.scala:470:{56,70}] wire s2_sc = _s2_sc_T; // @[DCache.scala:471:{56,70}] wire io_cpu_resp_bits_data_doZero_2 = s2_sc; // @[DCache.scala:471:56] reg [6:0] lrscCount; // @[DCache.scala:472:26] wire lrscValid = \|(lrscCount[6:2]); // @[DCache.scala:472:26, :473:29] wire _lrscBackingOff_T = \|lrscCount; // @[DCache.scala:472:26, :474:34] wire _lrscBackingOff_T_1 = ~lrscValid; // @[DCache.scala:473:29, :474:43] wire lrscBackingOff = _lrscBackingOff_T & _lrscBackingOff_T_1; // @[DCache.scala:474:{34,40,43}] reg [33:0] lrscAddr; // @[DCache.scala:475:21] wire [33:0] _lrscAddrMatch_T = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49] wire [33:0] _lrscAddr_T = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49, :480:29] wire [33:0] _acquire_address_T = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49, :578:38] wire [33:0] _tl_out_a_bits_T_1 = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49, :1210:39] wire [33:0] _io_errors_bus_bits_T = s2_req_addr[39:6]; // @[DCache.scala:339:19, :476:49, :1130:58] wire lrscAddrMatch = lrscAddr == _lrscAddrMatch_T; // @[DCache.scala:475:21, :476:{32,49}] wire _s2_sc_fail_T = lrscValid & lrscAddrMatch; // @[DCache.scala:473:29, :476:32, :477:41] wire _s2_sc_fail_T_1 = ~_s2_sc_fail_T; // @[DCache.scala:477:{29,41}] wire s2_sc_fail = s2_sc & _s2_sc_fail_T_1; // @[DCache.scala:471:56, :477:{26,29}] wire [6:0] _lrscCount_T = s2_hit ? 7'h4F : 7'h0; // @[Misc.scala:35:9] wire [7:0] _lrscCount_T_1 = {1'h0, lrscCount} - 8'h1; // @[DCache.scala:472:26, :482:51] wire [6:0] _lrscCount_T_2 = _lrscCount_T_1[6:0]; // @[DCache.scala:482:51] wire _s2_correct_T = ~any_pstore_valid; // @[DCache.scala:230:30, :487:37] wire _s2_correct_T_2 = any_pstore_valid \| s2_valid; // @[DCache.scala:230:30, :331:25, :487:84] reg s2_correct_REG; // @[DCache.scala:487:66] wire _s2_correct_T_3 = ~s2_correct_REG; // @[DCache.scala:487:{58,66}] wire _GEN_95 = s1_valid_not_nacked & s1_write; // @[DCache.scala:187:38, :492:63] wire _pstore1_cmd_T; // @[DCache.scala:492:63] assign _pstore1_cmd_T = _GEN_95; // @[DCache.scala:492:63] wire _pstore1_addr_T; // @[DCache.scala:493:62] assign _pstore1_addr_T = _GEN_95; // @[DCache.scala:492:63, :493:62] wire _pstore1_data_T; // @[DCache.scala:494:73] assign _pstore1_data_T = _GEN_95; // @[DCache.scala:492:63, :494:73] wire _pstore1_way_T; // @[DCache.scala:495:63] assign _pstore1_way_T = _GEN_95; // @[DCache.scala:492:63, :495:63] wire _pstore1_mask_T; // @[DCache.scala:496:61] assign _pstore1_mask_T = _GEN_95; // @[DCache.scala:492:63, :496:61] wire _pstore1_rmw_T_53; // @[DCache.scala:498:84] assign _pstore1_rmw_T_53 = _GEN_95; // @[DCache.scala:492:63, :498:84] reg [4:0] pstore1_cmd; // @[DCache.scala:492:30] reg [39:0] pstore1_addr; // @[DCache.scala:493:31] wire [39:0] _pstore2_addr_T = pstore1_addr; // @[DCache.scala:493:31, :524:35] reg [63:0] pstore1_data; // @[DCache.scala:494:31] assign io_cpu_resp_bits_store_data_0 = pstore1_data; // @[DCache.scala:101:7, :494:31] wire [63:0] put_data = pstore1_data; // @[Edges.scala:480:17] wire [63:0] putpartial_data = pstore1_data; // @[Edges.scala:500:17] wire [63:0] atomics_a_data = pstore1_data; // @[Edges.scala:534:17] wire [63:0] atomics_a_1_data = pstore1_data; // @[Edges.scala:534:17] wire [63:0] atomics_a_2_data = pstore1_data; // @[Edges.scala:534:17] wire [63:0] atomics_a_3_data = pstore1_data; // @[Edges.scala:534:17] wire [63:0] atomics_a_4_data = pstore1_data; // @[Edges.scala:517:17] wire [63:0] atomics_a_5_data = pstore1_data; // @[Edges.scala:517:17] wire [63:0] atomics_a_6_data = pstore1_data; // @[Edges.scala:517:17] wire [63:0] atomics_a_7_data = pstore1_data; // @[Edges.scala:517:17] wire [63:0] atomics_a_8_data = pstore1_data; // @[Edges.scala:517:17] wire [63:0] _amoalu_io_rhs_T = pstore1_data; // @[DCache.scala:494:31, :986:37] reg [7:0] pstore1_way; // @[DCache.scala:495:30] wire [7:0] _pstore2_way_T = pstore1_way; // @[DCache.scala:495:30, :525:34] reg [7:0] pstore1_mask; // @[DCache.scala:496:31] wire [7:0] pstore2_storegen_mask_mergedMask = pstore1_mask; // @[DCache.scala:496:31, :533:37] wire [7:0] _amoalu_io_mask_T = pstore1_mask; // @[DCache.scala:496:31, :983:38] wire [63:0] pstore1_storegen_data; // @[DCache.scala:497:42] wire _pstore1_rmw_T_4 = _pstore1_rmw_T \| _pstore1_rmw_T_1; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_5 = _pstore1_rmw_T_4 \| _pstore1_rmw_T_2; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_6 = _pstore1_rmw_T_5 \| _pstore1_rmw_T_3; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_11 = _pstore1_rmw_T_7 \| _pstore1_rmw_T_8; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_12 = _pstore1_rmw_T_11 \| _pstore1_rmw_T_9; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_13 = _pstore1_rmw_T_12 \| _pstore1_rmw_T_10; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_19 = _pstore1_rmw_T_14 \| _pstore1_rmw_T_15; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_20 = _pstore1_rmw_T_19 \| _pstore1_rmw_T_16; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_21 = _pstore1_rmw_T_20 \| _pstore1_rmw_T_17; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_22 = _pstore1_rmw_T_21 \| _pstore1_rmw_T_18; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_23 = _pstore1_rmw_T_13 \| _pstore1_rmw_T_22; // @[package.scala:81:59] wire _pstore1_rmw_T_24 = _pstore1_rmw_T_6 \| _pstore1_rmw_T_23; // @[package.scala:81:59] wire _pstore1_rmw_T_27 = _pstore1_rmw_T_25 \| _pstore1_rmw_T_26; // @[Consts.scala:90:{32,42,49}] wire _pstore1_rmw_T_29 = _pstore1_rmw_T_27 \| _pstore1_rmw_T_28; // @[Consts.scala:90:{42,59,66}] wire _pstore1_rmw_T_34 = _pstore1_rmw_T_30 \| _pstore1_rmw_T_31; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_35 = _pstore1_rmw_T_34 \| _pstore1_rmw_T_32; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_36 = _pstore1_rmw_T_35 \| _pstore1_rmw_T_33; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_42 = _pstore1_rmw_T_37 \| _pstore1_rmw_T_38; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_43 = _pstore1_rmw_T_42 \| _pstore1_rmw_T_39; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_44 = _pstore1_rmw_T_43 \| _pstore1_rmw_T_40; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_45 = _pstore1_rmw_T_44 \| _pstore1_rmw_T_41; // @[package.scala:16:47, :81:59] wire _pstore1_rmw_T_46 = _pstore1_rmw_T_36 \| _pstore1_rmw_T_45; // @[package.scala:81:59] wire _pstore1_rmw_T_47 = _pstore1_rmw_T_29 \| _pstore1_rmw_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _pstore1_rmw_T_50 = _pstore1_rmw_T_48; // @[DCache.scala:1191:{35,45}] wire _pstore1_rmw_T_51 = _pstore1_rmw_T_47 & _pstore1_rmw_T_50; // @[DCache.scala:1191:{23,45}] wire _pstore1_rmw_T_52 = _pstore1_rmw_T_24 \| _pstore1_rmw_T_51; // @[DCache.scala:1190:21, :1191:23] reg pstore1_rmw_r; // @[DCache.scala:498:44] wire pstore1_rmw = pstore1_rmw_r; // @[DCache.scala:498:{32,44}] wire _pstore1_merge_likely_T = s2_valid_not_nacked_in_s1 & s2_write; // @[DCache.scala:336:44, :499:56] wire _GEN_96 = s2_valid_hit & s2_write; // @[DCache.scala:422:48, :490:46] wire _pstore1_merge_T; // @[DCache.scala:490:46] assign _pstore1_merge_T = _GEN_96; // @[DCache.scala:490:46] wire _pstore1_valid_T; // @[DCache.scala:490:46] assign _pstore1_valid_T = _GEN_96; // @[DCache.scala:490:46] wire _pstore1_held_T; // @[DCache.scala:490:46] assign _pstore1_held_T = _GEN_96; // @[DCache.scala:490:46] wire _pstore1_merge_T_1 = ~s2_sc_fail; // @[DCache.scala:477:26, :490:61] wire _pstore1_merge_T_2 = _pstore1_merge_T & _pstore1_merge_T_1; // @[DCache.scala:490:{46,58,61}] wire _pstore1_merge_T_4 = _pstore1_merge_T_2; // @[DCache.scala:490:58, :491:48] reg pstore2_valid; // @[DCache.scala:501:30] wire _pstore_drain_opportunistic_res_T_2 = _pstore_drain_opportunistic_res_T \| _pstore_drain_opportunistic_res_T_1; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_res_T_3 = ~_pstore_drain_opportunistic_res_T_2; // @[package.scala:81:59] wire pstore_drain_opportunistic_res = _pstore_drain_opportunistic_res_T_3; // @[DCache.scala:1185:{15,46}] wire _pstore_drain_opportunistic_T_4 = _pstore_drain_opportunistic_T \| _pstore_drain_opportunistic_T_1; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_5 = _pstore_drain_opportunistic_T_4 \| _pstore_drain_opportunistic_T_2; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_6 = _pstore_drain_opportunistic_T_5 \| _pstore_drain_opportunistic_T_3; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_11 = _pstore_drain_opportunistic_T_7 \| _pstore_drain_opportunistic_T_8; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_12 = _pstore_drain_opportunistic_T_11 \| _pstore_drain_opportunistic_T_9; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_13 = _pstore_drain_opportunistic_T_12 \| _pstore_drain_opportunistic_T_10; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_19 = _pstore_drain_opportunistic_T_14 \| _pstore_drain_opportunistic_T_15; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_20 = _pstore_drain_opportunistic_T_19 \| _pstore_drain_opportunistic_T_16; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_21 = _pstore_drain_opportunistic_T_20 \| _pstore_drain_opportunistic_T_17; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_22 = _pstore_drain_opportunistic_T_21 \| _pstore_drain_opportunistic_T_18; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_23 = _pstore_drain_opportunistic_T_13 \| _pstore_drain_opportunistic_T_22; // @[package.scala:81:59] wire _pstore_drain_opportunistic_T_24 = _pstore_drain_opportunistic_T_6 \| _pstore_drain_opportunistic_T_23; // @[package.scala:81:59] wire _pstore_drain_opportunistic_T_27 = _pstore_drain_opportunistic_T_25 \| _pstore_drain_opportunistic_T_26; // @[Consts.scala:90:{32,42,49}] wire _pstore_drain_opportunistic_T_29 = _pstore_drain_opportunistic_T_27 \| _pstore_drain_opportunistic_T_28; // @[Consts.scala:90:{42,59,66}] wire _pstore_drain_opportunistic_T_34 = _pstore_drain_opportunistic_T_30 \| _pstore_drain_opportunistic_T_31; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_35 = _pstore_drain_opportunistic_T_34 \| _pstore_drain_opportunistic_T_32; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_36 = _pstore_drain_opportunistic_T_35 \| _pstore_drain_opportunistic_T_33; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_42 = _pstore_drain_opportunistic_T_37 \| _pstore_drain_opportunistic_T_38; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_43 = _pstore_drain_opportunistic_T_42 \| _pstore_drain_opportunistic_T_39; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_44 = _pstore_drain_opportunistic_T_43 \| _pstore_drain_opportunistic_T_40; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_45 = _pstore_drain_opportunistic_T_44 \| _pstore_drain_opportunistic_T_41; // @[package.scala:16:47, :81:59] wire _pstore_drain_opportunistic_T_46 = _pstore_drain_opportunistic_T_36 \| _pstore_drain_opportunistic_T_45; // @[package.scala:81:59] wire _pstore_drain_opportunistic_T_47 = _pstore_drain_opportunistic_T_29 \| _pstore_drain_opportunistic_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _pstore_drain_opportunistic_T_50 = _pstore_drain_opportunistic_T_48; // @[DCache.scala:1191:{35,45}] wire _pstore_drain_opportunistic_T_51 = _pstore_drain_opportunistic_T_47 & _pstore_drain_opportunistic_T_50; // @[DCache.scala:1191:{23,45}] wire _pstore_drain_opportunistic_T_52 = _pstore_drain_opportunistic_T_24 \| _pstore_drain_opportunistic_T_51; // @[DCache.scala:1190:21, :1191:23] wire _pstore_drain_opportunistic_T_53 = ~_pstore_drain_opportunistic_T_52; // @[DCache.scala:1186:12, :1190:21] wire _pstore_drain_opportunistic_T_54 = _pstore_drain_opportunistic_T_53 \| pstore_drain_opportunistic_res; // @[DCache.scala:1185:46, :1186:{12,28}] wire _pstore_drain_opportunistic_T_56 = ~_pstore_drain_opportunistic_T_55; // @[DCache.scala:1186:11] wire _pstore_drain_opportunistic_T_57 = ~_pstore_drain_opportunistic_T_54; // @[DCache.scala:1186:{11,28}] wire _pstore_drain_opportunistic_T_58 = io_cpu_req_valid_0 & pstore_drain_opportunistic_res; // @[DCache.scala:101:7, :502:55, :1185:46] wire _pstore_drain_opportunistic_T_59 = ~_pstore_drain_opportunistic_T_58; // @[DCache.scala:502:{36,55}] wire pstore_drain_opportunistic = _pstore_drain_opportunistic_T_59; // @[DCache.scala:502:{36,92}] reg pstore_drain_on_miss_REG; // @[DCache.scala:503:56] wire pstore_drain_on_miss = releaseInFlight \| pstore_drain_on_miss_REG; // @[DCache.scala:334:46, :503:{46,56}] reg pstore1_held; // @[DCache.scala:504:29] wire _GEN_97 = s2_valid & s2_write; // @[DCache.scala:331:25, :505:39] wire _pstore1_valid_likely_T; // @[DCache.scala:505:39] assign _pstore1_valid_likely_T = _GEN_97; // @[DCache.scala:505:39] wire _io_cpu_perf_storeBufferEmptyAfterLoad_T_1; // @[DCache.scala:1082:16] assign _io_cpu_perf_storeBufferEmptyAfterLoad_T_1 = _GEN_97; // @[DCache.scala:505:39, :1082:16] wire _io_cpu_perf_storeBufferEmptyAfterStore_T_1; // @[DCache.scala:1086:15] assign _io_cpu_perf_storeBufferEmptyAfterStore_T_1 = _GEN_97; // @[DCache.scala:505:39, :1086:15] wire _io_cpu_perf_storeBufferEmptyAfterStore_T_4; // @[DCache.scala:1087:16] assign _io_cpu_perf_storeBufferEmptyAfterStore_T_4 = _GEN_97; // @[DCache.scala:505:39, :1087:16] wire _io_cpu_perf_canAcceptStoreThenLoad_T; // @[DCache.scala:1089:16] assign _io_cpu_perf_canAcceptStoreThenLoad_T = _GEN_97; // @[DCache.scala:505:39, :1089:16] wire _io_cpu_perf_canAcceptLoadThenLoad_T_55; // @[DCache.scala:1092:100] assign _io_cpu_perf_canAcceptLoadThenLoad_T_55 = _GEN_97; // @[DCache.scala:505:39, :1092:100] wire pstore1_valid_likely = _pstore1_valid_likely_T \| pstore1_held; // @[DCache.scala:504:29, :505:{39,51}] wire _pstore1_valid_T_1 = ~s2_sc_fail; // @[DCache.scala:477:26, :490:61] wire _pstore1_valid_T_2 = _pstore1_valid_T & _pstore1_valid_T_1; // @[DCache.scala:490:{46,58,61}] wire _pstore1_valid_T_4 = _pstore1_valid_T_2; // @[DCache.scala:490:58, :491:48] wire pstore1_valid = _pstore1_valid_T_4 \| pstore1_held; // @[DCache.scala:491:48, :504:29, :507:38] wire _advance_pstore1_T = pstore1_valid; // @[DCache.scala:507:38, :522:40] assign _any_pstore_valid_T = pstore1_held \| pstore2_valid; // @[DCache.scala:501:30, :504:29, :508:36] assign any_pstore_valid = _any_pstore_valid_T; // @[DCache.scala:230:30, :508:36] wire _GEN_98 = pstore1_valid_likely & pstore2_valid; // @[DCache.scala:501:30, :505:51, :509:54] wire _pstore_drain_structural_T; // @[DCache.scala:509:54] assign _pstore_drain_structural_T = _GEN_98; // @[DCache.scala:509:54] wire _io_cpu_perf_canAcceptStoreThenLoad_T_6; // @[DCache.scala:1090:20] assign _io_cpu_perf_canAcceptStoreThenLoad_T_6 = _GEN_98; // @[DCache.scala:509:54, :1090:20] wire _GEN_99 = s1_valid & s1_write; // @[DCache.scala:182:25, :509:85] wire _pstore_drain_structural_T_1; // @[DCache.scala:509:85] assign _pstore_drain_structural_T_1 = _GEN_99; // @[DCache.scala:509:85] wire _io_cpu_perf_storeBufferEmptyAfterLoad_T; // @[DCache.scala:1081:15] assign _io_cpu_perf_storeBufferEmptyAfterLoad_T = _GEN_99; // @[DCache.scala:509:85, :1081:15] wire _io_cpu_perf_storeBufferEmptyAfterStore_T; // @[DCache.scala:1085:15] assign _io_cpu_perf_storeBufferEmptyAfterStore_T = _GEN_99; // @[DCache.scala:509:85, :1085:15] wire _io_cpu_perf_canAcceptStoreThenLoad_T_2; // @[DCache.scala:1089:57] assign _io_cpu_perf_canAcceptStoreThenLoad_T_2 = _GEN_99; // @[DCache.scala:509:85, :1089:57] wire _io_cpu_perf_canAcceptStoreThenLoad_T_7; // @[DCache.scala:1090:57] assign _io_cpu_perf_canAcceptStoreThenLoad_T_7 = _GEN_99; // @[DCache.scala:509:85, :1090:57] wire _io_cpu_perf_canAcceptLoadThenLoad_T; // @[DCache.scala:1092:52] assign _io_cpu_perf_canAcceptLoadThenLoad_T = _GEN_99; // @[DCache.scala:509:85, :1092:52] wire _pstore_drain_structural_T_2 = _pstore_drain_structural_T_1 \| pstore1_rmw; // @[DCache.scala:498:32, :509:{85,98}] wire pstore_drain_structural = _pstore_drain_structural_T & _pstore_drain_structural_T_2; // @[DCache.scala:509:{54,71,98}] wire _pstore_drain_T_1 = pstore_drain_structural; // @[DCache.scala:509:71, :517:17] wire _dataArb_io_in_0_valid_T_1 = pstore_drain_structural; // @[DCache.scala:509:71, :517:17] wire _T_49 = s2_valid_hit_pre_data_ecc & s2_write; // @[DCache.scala:420:69, :506:72] wire _pstore_drain_T_2; // @[DCache.scala:506:72] assign _pstore_drain_T_2 = _T_49; // @[DCache.scala:506:72] wire _dataArb_io_in_0_valid_T_2; // @[DCache.scala:506:72] assign _dataArb_io_in_0_valid_T_2 = _T_49; // @[DCache.scala:506:72] wire _pstore_drain_T_4 = _pstore_drain_T_2; // @[DCache.scala:506:{72,84}] wire _pstore_drain_T_5 = _pstore_drain_T_4 \| pstore1_held; // @[DCache.scala:504:29, :506:{84,96}] wire _pstore_drain_T_6 = ~pstore1_rmw; // @[DCache.scala:498:32, :518:44] wire _pstore_drain_T_7 = _pstore_drain_T_5 & _pstore_drain_T_6; // @[DCache.scala:506:96, :518:{41,44}] wire _pstore_drain_T_8 = _pstore_drain_T_7 \| pstore2_valid; // @[DCache.scala:501:30, :518:{41,58}] wire _GEN_100 = pstore_drain_opportunistic \| pstore_drain_on_miss; // @[DCache.scala:502:92, :503:46, :518:107] wire _pstore_drain_T_9; // @[DCache.scala:518:107] assign _pstore_drain_T_9 = _GEN_100; // @[DCache.scala:518:107] wire _dataArb_io_in_0_valid_T_9; // @[DCache.scala:518:107] assign _dataArb_io_in_0_valid_T_9 = _GEN_100; // @[DCache.scala:518:107] wire _pstore_drain_T_10 = _pstore_drain_T_8 & _pstore_drain_T_9; // @[DCache.scala:518:{58,76,107}] wire _pstore_drain_T_11 = _pstore_drain_T_1 \| _pstore_drain_T_10; // @[DCache.scala:517:{17,44}, :518:76] assign pstore_drain = _pstore_drain_T_11; // @[DCache.scala:516:27, :517:44] assign dataArb_io_in_0_bits_write = pstore_drain; // @[DCache.scala:152:28, :516:27] wire _pstore1_held_T_1 = ~s2_sc_fail; // @[DCache.scala:477:26, :490:61] wire _pstore1_held_T_2 = _pstore1_held_T & _pstore1_held_T_1; // @[DCache.scala:490:{46,58,61}] wire _pstore1_held_T_4 = _pstore1_held_T_2; // @[DCache.scala:490:58, :491:48] wire _pstore1_held_T_6 = _pstore1_held_T_4; // @[DCache.scala:491:48, :521:35] wire _pstore1_held_T_7 = _pstore1_held_T_6 \| pstore1_held; // @[DCache.scala:504:29, :521:{35,54}] wire _pstore1_held_T_8 = _pstore1_held_T_7 & pstore2_valid; // @[DCache.scala:501:30, :521:{54,71}] wire _pstore1_held_T_9 = ~pstore_drain; // @[DCache.scala:516:27, :521:91] wire _pstore1_held_T_10 = _pstore1_held_T_8 & _pstore1_held_T_9; // @[DCache.scala:521:{71,88,91}] wire _advance_pstore1_T_1 = pstore2_valid == pstore_drain; // @[DCache.scala:501:30, :516:27, :522:79] wire advance_pstore1 = _advance_pstore1_T & _advance_pstore1_T_1; // @[DCache.scala:522:{40,61,79}] wire _pstore2_storegen_data_T_3 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_7 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_11 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_15 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_19 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_23 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_27 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_data_T_31 = advance_pstore1; // @[DCache.scala:522:61, :528:78] wire _pstore2_storegen_mask_T = advance_pstore1; // @[DCache.scala:522:61, :532:27] wire _pstore2_valid_T = ~pstore_drain; // @[DCache.scala:516:27, :521:91, :523:37] wire _pstore2_valid_T_1 = pstore2_valid & _pstore2_valid_T; // @[DCache.scala:501:30, :523:{34,37}] wire _pstore2_valid_T_2 = _pstore2_valid_T_1 \| advance_pstore1; // @[DCache.scala:522:61, :523:{34,51}] reg [39:0] pstore2_addr; // @[DCache.scala:524:31] reg [7:0] pstore2_way; // @[DCache.scala:525:30] wire [7:0] _pstore2_storegen_data_T = pstore1_storegen_data[7:0]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_1 = pstore1_mask[0]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_3 = pstore1_mask[0]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_4 = pstore1_storegen_data[15:8]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_5 = pstore1_mask[1]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_4 = pstore1_mask[1]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_1; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_8 = pstore1_storegen_data[23:16]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_9 = pstore1_mask[2]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_5 = pstore1_mask[2]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_2; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_12 = pstore1_storegen_data[31:24]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_13 = pstore1_mask[3]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_6 = pstore1_mask[3]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_3; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_16 = pstore1_storegen_data[39:32]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_17 = pstore1_mask[4]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_7 = pstore1_mask[4]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_4; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_20 = pstore1_storegen_data[47:40]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_21 = pstore1_mask[5]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_8 = pstore1_mask[5]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_5; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_24 = pstore1_storegen_data[55:48]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_25 = pstore1_mask[6]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_9 = pstore1_mask[6]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_6; // @[DCache.scala:528:22] wire [7:0] _pstore2_storegen_data_T_28 = pstore1_storegen_data[63:56]; // @[DCache.scala:497:42, :528:44] wire _pstore2_storegen_data_T_29 = pstore1_mask[7]; // @[DCache.scala:496:31, :528:110] wire _s1_hazard_T_10 = pstore1_mask[7]; // @[package.scala:211:50] reg [7:0] pstore2_storegen_data_r_7; // @[DCache.scala:528:22] wire [15:0] pstore2_storegen_data_lo_lo = {pstore2_storegen_data_r_1, pstore2_storegen_data_r}; // @[package.scala:45:27] wire [15:0] pstore2_storegen_data_lo_hi = {pstore2_storegen_data_r_3, pstore2_storegen_data_r_2}; // @[package.scala:45:27] wire [31:0] pstore2_storegen_data_lo = {pstore2_storegen_data_lo_hi, pstore2_storegen_data_lo_lo}; // @[package.scala:45:27] wire [15:0] pstore2_storegen_data_hi_lo = {pstore2_storegen_data_r_5, pstore2_storegen_data_r_4}; // @[package.scala:45:27] wire [15:0] pstore2_storegen_data_hi_hi = {pstore2_storegen_data_r_7, pstore2_storegen_data_r_6}; // @[package.scala:45:27] wire [31:0] pstore2_storegen_data_hi = {pstore2_storegen_data_hi_hi, pstore2_storegen_data_hi_lo}; // @[package.scala:45:27] wire [63:0] pstore2_storegen_data = {pstore2_storegen_data_hi, pstore2_storegen_data_lo}; // @[package.scala:45:27] reg [7:0] pstore2_storegen_mask; // @[DCache.scala:531:19] wire [7:0] _pstore2_storegen_mask_mask_T = ~pstore2_storegen_mask_mergedMask; // @[DCache.scala:533:37, :534:37] wire [7:0] _pstore2_storegen_mask_mask_T_1 = _pstore2_storegen_mask_mask_T; // @[DCache.scala:534:{19,37}] wire [7:0] _pstore2_storegen_mask_mask_T_2 = ~_pstore2_storegen_mask_mask_T_1; // @[DCache.scala:534:{15,19}] wire _dataArb_io_in_0_valid_T_4 = _dataArb_io_in_0_valid_T_2; // @[DCache.scala:506:{72,84}] wire _dataArb_io_in_0_valid_T_5 = _dataArb_io_in_0_valid_T_4 \| pstore1_held; // @[DCache.scala:504:29, :506:{84,96}] wire _dataArb_io_in_0_valid_T_6 = ~pstore1_rmw; // @[DCache.scala:498:32, :518:44] wire _dataArb_io_in_0_valid_T_7 = _dataArb_io_in_0_valid_T_5 & _dataArb_io_in_0_valid_T_6; // @[DCache.scala:506:96, :518:{41,44}] wire _dataArb_io_in_0_valid_T_8 = _dataArb_io_in_0_valid_T_7 \| pstore2_valid; // @[DCache.scala:501:30, :518:{41,58}] wire _dataArb_io_in_0_valid_T_10 = _dataArb_io_in_0_valid_T_8 & _dataArb_io_in_0_valid_T_9; // @[DCache.scala:518:{58,76,107}] wire _dataArb_io_in_0_valid_T_11 = _dataArb_io_in_0_valid_T_1 \| _dataArb_io_in_0_valid_T_10; // @[DCache.scala:517:{17,44}, :518:76] assign _dataArb_io_in_0_valid_T_12 = _dataArb_io_in_0_valid_T_11; // @[DCache.scala:516:27, :517:44] assign dataArb_io_in_0_valid = _dataArb_io_in_0_valid_T_12; // @[DCache.scala:152:28, :516:27] wire [39:0] _GEN_101 = pstore2_valid ? pstore2_addr : pstore1_addr; // @[DCache.scala:493:31, :501:30, :524:31, :549:36] wire [39:0] _dataArb_io_in_0_bits_addr_T; // @[DCache.scala:549:36] assign _dataArb_io_in_0_bits_addr_T = _GEN_101; // @[DCache.scala:549:36] wire [39:0] _dataArb_io_in_0_bits_wordMask_wordMask_T; // @[DCache.scala:554:32] assign _dataArb_io_in_0_bits_wordMask_wordMask_T = _GEN_101; // @[DCache.scala:549:36, :554:32] assign dataArb_io_in_0_bits_addr = _dataArb_io_in_0_bits_addr_T[11:0]; // @[DCache.scala:152:28, :549:{30,36}] assign _dataArb_io_in_0_bits_way_en_T = pstore2_valid ? pstore2_way : pstore1_way; // @[DCache.scala:495:30, :501:30, :525:30, :550:38] assign dataArb_io_in_0_bits_way_en = _dataArb_io_in_0_bits_way_en_T; // @[DCache.scala:152:28, :550:38] wire [63:0] _dataArb_io_in_0_bits_wdata_T = pstore2_valid ? pstore2_storegen_data : pstore1_data; // @[package.scala:45:27] wire [7:0] _dataArb_io_in_0_bits_wdata_T_1 = _dataArb_io_in_0_bits_wdata_T[7:0]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_2 = _dataArb_io_in_0_bits_wdata_T[15:8]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_3 = _dataArb_io_in_0_bits_wdata_T[23:16]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_4 = _dataArb_io_in_0_bits_wdata_T[31:24]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_5 = _dataArb_io_in_0_bits_wdata_T[39:32]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_6 = _dataArb_io_in_0_bits_wdata_T[47:40]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_7 = _dataArb_io_in_0_bits_wdata_T[55:48]; // @[package.scala:211:50] wire [7:0] _dataArb_io_in_0_bits_wdata_T_8 = _dataArb_io_in_0_bits_wdata_T[63:56]; // @[package.scala:211:50] wire [15:0] dataArb_io_in_0_bits_wdata_lo_lo = {_dataArb_io_in_0_bits_wdata_T_2, _dataArb_io_in_0_bits_wdata_T_1}; // @[package.scala:45:27, :211:50] wire [15:0] dataArb_io_in_0_bits_wdata_lo_hi = {_dataArb_io_in_0_bits_wdata_T_4, _dataArb_io_in_0_bits_wdata_T_3}; // @[package.scala:45:27, :211:50] wire [31:0] dataArb_io_in_0_bits_wdata_lo = {dataArb_io_in_0_bits_wdata_lo_hi, dataArb_io_in_0_bits_wdata_lo_lo}; // @[package.scala:45:27] wire [15:0] dataArb_io_in_0_bits_wdata_hi_lo = {_dataArb_io_in_0_bits_wdata_T_6, _dataArb_io_in_0_bits_wdata_T_5}; // @[package.scala:45:27, :211:50] wire [15:0] dataArb_io_in_0_bits_wdata_hi_hi = {_dataArb_io_in_0_bits_wdata_T_8, _dataArb_io_in_0_bits_wdata_T_7}; // @[package.scala:45:27, :211:50] wire [31:0] dataArb_io_in_0_bits_wdata_hi = {dataArb_io_in_0_bits_wdata_hi_hi, dataArb_io_in_0_bits_wdata_hi_lo}; // @[package.scala:45:27] assign _dataArb_io_in_0_bits_wdata_T_9 = {dataArb_io_in_0_bits_wdata_hi, dataArb_io_in_0_bits_wdata_lo}; // @[package.scala:45:27] assign dataArb_io_in_0_bits_wdata = _dataArb_io_in_0_bits_wdata_T_9; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T = _dataArb_io_in_0_bits_eccMask_T_17[0]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_1 = _dataArb_io_in_0_bits_eccMask_T_17[1]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_2 = _dataArb_io_in_0_bits_eccMask_T_17[2]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_3 = _dataArb_io_in_0_bits_eccMask_T_17[3]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_4 = _dataArb_io_in_0_bits_eccMask_T_17[4]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_5 = _dataArb_io_in_0_bits_eccMask_T_17[5]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_6 = _dataArb_io_in_0_bits_eccMask_T_17[6]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_7 = _dataArb_io_in_0_bits_eccMask_T_17[7]; // @[package.scala:45:27] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_8 = _dataArb_io_in_0_bits_wordMask_eccMask_T \| _dataArb_io_in_0_bits_wordMask_eccMask_T_1; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_9 = _dataArb_io_in_0_bits_wordMask_eccMask_T_8 \| _dataArb_io_in_0_bits_wordMask_eccMask_T_2; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_10 = _dataArb_io_in_0_bits_wordMask_eccMask_T_9 \| _dataArb_io_in_0_bits_wordMask_eccMask_T_3; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_11 = _dataArb_io_in_0_bits_wordMask_eccMask_T_10 \| _dataArb_io_in_0_bits_wordMask_eccMask_T_4; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_12 = _dataArb_io_in_0_bits_wordMask_eccMask_T_11 \| _dataArb_io_in_0_bits_wordMask_eccMask_T_5; // @[package.scala:81:59] wire _dataArb_io_in_0_bits_wordMask_eccMask_T_13 = _dataArb_io_in_0_bits_wordMask_eccMask_T_12 \| _dataArb_io_in_0_bits_wordMask_eccMask_T_6; // @[package.scala:81:59] wire dataArb_io_in_0_bits_wordMask_eccMask = _dataArb_io_in_0_bits_wordMask_eccMask_T_13 \| _dataArb_io_in_0_bits_wordMask_eccMask_T_7; // @[package.scala:81:59] wire [1:0] _dataArb_io_in_0_bits_wordMask_T_3 = {1'h0, dataArb_io_in_0_bits_wordMask_eccMask}; // @[package.scala:81:59] assign dataArb_io_in_0_bits_wordMask = _dataArb_io_in_0_bits_wordMask_T_3[0]; // @[DCache.scala:152:28, :552:34, :555:55] wire [7:0] _dataArb_io_in_0_bits_eccMask_T = pstore2_valid ? pstore2_storegen_mask : pstore1_mask; // @[DCache.scala:496:31, :501:30, :531:19, :557:47] wire _dataArb_io_in_0_bits_eccMask_T_1 = _dataArb_io_in_0_bits_eccMask_T[0]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_9 = _dataArb_io_in_0_bits_eccMask_T_1; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_2 = _dataArb_io_in_0_bits_eccMask_T[1]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_10 = _dataArb_io_in_0_bits_eccMask_T_2; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_3 = _dataArb_io_in_0_bits_eccMask_T[2]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_11 = _dataArb_io_in_0_bits_eccMask_T_3; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_4 = _dataArb_io_in_0_bits_eccMask_T[3]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_12 = _dataArb_io_in_0_bits_eccMask_T_4; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_5 = _dataArb_io_in_0_bits_eccMask_T[4]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_13 = _dataArb_io_in_0_bits_eccMask_T_5; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_6 = _dataArb_io_in_0_bits_eccMask_T[5]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_14 = _dataArb_io_in_0_bits_eccMask_T_6; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_7 = _dataArb_io_in_0_bits_eccMask_T[6]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_15 = _dataArb_io_in_0_bits_eccMask_T_7; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_8 = _dataArb_io_in_0_bits_eccMask_T[7]; // @[package.scala:211:50] wire _dataArb_io_in_0_bits_eccMask_T_16 = _dataArb_io_in_0_bits_eccMask_T_8; // @[package.scala:211:50] wire [1:0] dataArb_io_in_0_bits_eccMask_lo_lo = {_dataArb_io_in_0_bits_eccMask_T_10, _dataArb_io_in_0_bits_eccMask_T_9}; // @[package.scala:45:27] wire [1:0] dataArb_io_in_0_bits_eccMask_lo_hi = {_dataArb_io_in_0_bits_eccMask_T_12, _dataArb_io_in_0_bits_eccMask_T_11}; // @[package.scala:45:27] wire [3:0] dataArb_io_in_0_bits_eccMask_lo = {dataArb_io_in_0_bits_eccMask_lo_hi, dataArb_io_in_0_bits_eccMask_lo_lo}; // @[package.scala:45:27] wire [1:0] dataArb_io_in_0_bits_eccMask_hi_lo = {_dataArb_io_in_0_bits_eccMask_T_14, _dataArb_io_in_0_bits_eccMask_T_13}; // @[package.scala:45:27] wire [1:0] dataArb_io_in_0_bits_eccMask_hi_hi = {_dataArb_io_in_0_bits_eccMask_T_16, _dataArb_io_in_0_bits_eccMask_T_15}; // @[package.scala:45:27] wire [3:0] dataArb_io_in_0_bits_eccMask_hi = {dataArb_io_in_0_bits_eccMask_hi_hi, dataArb_io_in_0_bits_eccMask_hi_lo}; // @[package.scala:45:27] assign _dataArb_io_in_0_bits_eccMask_T_17 = {dataArb_io_in_0_bits_eccMask_hi, dataArb_io_in_0_bits_eccMask_lo}; // @[package.scala:45:27] assign dataArb_io_in_0_bits_eccMask = _dataArb_io_in_0_bits_eccMask_T_17; // @[package.scala:45:27] wire [8:0] _s1_hazard_T = pstore1_addr[11:3]; // @[DCache.scala:493:31, :561:9] wire [8:0] _s1_hazard_T_1 = s1_vaddr[11:3]; // @[DCache.scala:197:21, :561:43] wire [8:0] _s1_hazard_T_63 = s1_vaddr[11:3]; // @[DCache.scala:197:21, :561:43] wire _s1_hazard_T_2 = _s1_hazard_T == _s1_hazard_T_1; // @[DCache.scala:561:{9,31,43}] wire _s1_hazard_T_11 = _s1_hazard_T_3; // @[package.scala:211:50] wire _s1_hazard_T_12 = _s1_hazard_T_4; // @[package.scala:211:50] wire _s1_hazard_T_13 = _s1_hazard_T_5; // @[package.scala:211:50] wire _s1_hazard_T_14 = _s1_hazard_T_6; // @[package.scala:211:50] wire _s1_hazard_T_15 = _s1_hazard_T_7; // @[package.scala:211:50] wire _s1_hazard_T_16 = _s1_hazard_T_8; // @[package.scala:211:50] wire _s1_hazard_T_17 = _s1_hazard_T_9; // @[package.scala:211:50] wire _s1_hazard_T_18 = _s1_hazard_T_10; // @[package.scala:211:50] wire [1:0] s1_hazard_lo_lo = {_s1_hazard_T_12, _s1_hazard_T_11}; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_hi = {_s1_hazard_T_14, _s1_hazard_T_13}; // @[package.scala:45:27] wire [3:0] s1_hazard_lo = {s1_hazard_lo_hi, s1_hazard_lo_lo}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_lo = {_s1_hazard_T_16, _s1_hazard_T_15}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_hi = {_s1_hazard_T_18, _s1_hazard_T_17}; // @[package.scala:45:27] wire [3:0] s1_hazard_hi = {s1_hazard_hi_hi, s1_hazard_hi_lo}; // @[package.scala:45:27] wire [7:0] _s1_hazard_T_19 = {s1_hazard_hi, s1_hazard_lo}; // @[package.scala:45:27] wire _s1_hazard_T_20 = _s1_hazard_T_19[0]; // @[package.scala:45:27] wire _s1_hazard_T_21 = _s1_hazard_T_19[1]; // @[package.scala:45:27] wire _s1_hazard_T_22 = _s1_hazard_T_19[2]; // @[package.scala:45:27] wire _s1_hazard_T_23 = _s1_hazard_T_19[3]; // @[package.scala:45:27] wire _s1_hazard_T_24 = _s1_hazard_T_19[4]; // @[package.scala:45:27] wire _s1_hazard_T_25 = _s1_hazard_T_19[5]; // @[package.scala:45:27] wire _s1_hazard_T_26 = _s1_hazard_T_19[6]; // @[package.scala:45:27] wire _s1_hazard_T_27 = _s1_hazard_T_19[7]; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_lo_1 = {_s1_hazard_T_21, _s1_hazard_T_20}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_lo_hi_1 = {_s1_hazard_T_23, _s1_hazard_T_22}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_lo_1 = {s1_hazard_lo_hi_1, s1_hazard_lo_lo_1}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_lo_1 = {_s1_hazard_T_25, _s1_hazard_T_24}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_hi_1 = {_s1_hazard_T_27, _s1_hazard_T_26}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_hi_1 = {s1_hazard_hi_hi_1, s1_hazard_hi_lo_1}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_28 = {s1_hazard_hi_1, s1_hazard_lo_1}; // @[DCache.scala:1182:52] wire _s1_hazard_T_29 = s1_mask_xwr[0]; // @[package.scala:211:50] wire _s1_hazard_T_91 = s1_mask_xwr[0]; // @[package.scala:211:50] wire _s1_hazard_T_37 = _s1_hazard_T_29; // @[package.scala:211:50] wire _s1_hazard_T_30 = s1_mask_xwr[1]; // @[package.scala:211:50] wire _s1_hazard_T_92 = s1_mask_xwr[1]; // @[package.scala:211:50] wire _s1_hazard_T_38 = _s1_hazard_T_30; // @[package.scala:211:50] wire _s1_hazard_T_31 = s1_mask_xwr[2]; // @[package.scala:211:50] wire _s1_hazard_T_93 = s1_mask_xwr[2]; // @[package.scala:211:50] wire _s1_hazard_T_39 = _s1_hazard_T_31; // @[package.scala:211:50] wire _s1_hazard_T_32 = s1_mask_xwr[3]; // @[package.scala:211:50] wire _s1_hazard_T_94 = s1_mask_xwr[3]; // @[package.scala:211:50] wire _s1_hazard_T_40 = _s1_hazard_T_32; // @[package.scala:211:50] wire _s1_hazard_T_33 = s1_mask_xwr[4]; // @[package.scala:211:50] wire _s1_hazard_T_95 = s1_mask_xwr[4]; // @[package.scala:211:50] wire _s1_hazard_T_41 = _s1_hazard_T_33; // @[package.scala:211:50] wire _s1_hazard_T_34 = s1_mask_xwr[5]; // @[package.scala:211:50] wire _s1_hazard_T_96 = s1_mask_xwr[5]; // @[package.scala:211:50] wire _s1_hazard_T_42 = _s1_hazard_T_34; // @[package.scala:211:50] wire _s1_hazard_T_35 = s1_mask_xwr[6]; // @[package.scala:211:50] wire _s1_hazard_T_97 = s1_mask_xwr[6]; // @[package.scala:211:50] wire _s1_hazard_T_43 = _s1_hazard_T_35; // @[package.scala:211:50] wire _s1_hazard_T_36 = s1_mask_xwr[7]; // @[package.scala:211:50] wire _s1_hazard_T_98 = s1_mask_xwr[7]; // @[package.scala:211:50] wire _s1_hazard_T_44 = _s1_hazard_T_36; // @[package.scala:211:50] wire [1:0] s1_hazard_lo_lo_2 = {_s1_hazard_T_38, _s1_hazard_T_37}; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_hi_2 = {_s1_hazard_T_40, _s1_hazard_T_39}; // @[package.scala:45:27] wire [3:0] s1_hazard_lo_2 = {s1_hazard_lo_hi_2, s1_hazard_lo_lo_2}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_lo_2 = {_s1_hazard_T_42, _s1_hazard_T_41}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_hi_2 = {_s1_hazard_T_44, _s1_hazard_T_43}; // @[package.scala:45:27] wire [3:0] s1_hazard_hi_2 = {s1_hazard_hi_hi_2, s1_hazard_hi_lo_2}; // @[package.scala:45:27] wire [7:0] _s1_hazard_T_45 = {s1_hazard_hi_2, s1_hazard_lo_2}; // @[package.scala:45:27] wire _s1_hazard_T_46 = _s1_hazard_T_45[0]; // @[package.scala:45:27] wire _s1_hazard_T_47 = _s1_hazard_T_45[1]; // @[package.scala:45:27] wire _s1_hazard_T_48 = _s1_hazard_T_45[2]; // @[package.scala:45:27] wire _s1_hazard_T_49 = _s1_hazard_T_45[3]; // @[package.scala:45:27] wire _s1_hazard_T_50 = _s1_hazard_T_45[4]; // @[package.scala:45:27] wire _s1_hazard_T_51 = _s1_hazard_T_45[5]; // @[package.scala:45:27] wire _s1_hazard_T_52 = _s1_hazard_T_45[6]; // @[package.scala:45:27] wire _s1_hazard_T_53 = _s1_hazard_T_45[7]; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_lo_3 = {_s1_hazard_T_47, _s1_hazard_T_46}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_lo_hi_3 = {_s1_hazard_T_49, _s1_hazard_T_48}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_lo_3 = {s1_hazard_lo_hi_3, s1_hazard_lo_lo_3}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_lo_3 = {_s1_hazard_T_51, _s1_hazard_T_50}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_hi_3 = {_s1_hazard_T_53, _s1_hazard_T_52}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_hi_3 = {s1_hazard_hi_hi_3, s1_hazard_hi_lo_3}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_54 = {s1_hazard_hi_3, s1_hazard_lo_3}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_55 = _s1_hazard_T_28 & _s1_hazard_T_54; // @[DCache.scala:562:38, :1182:52] wire _s1_hazard_T_56 = \|_s1_hazard_T_55; // @[DCache.scala:562:{38,66}] wire [7:0] _s1_hazard_T_57 = pstore1_mask & s1_mask_xwr; // @[DCache.scala:496:31, :562:77] wire _s1_hazard_T_58 = \|_s1_hazard_T_57; // @[DCache.scala:562:{77,92}] wire _s1_hazard_T_59 = s1_write ? _s1_hazard_T_56 : _s1_hazard_T_58; // @[DCache.scala:562:{8,66,92}] wire _s1_hazard_T_60 = _s1_hazard_T_2 & _s1_hazard_T_59; // @[DCache.scala:561:{31,65}, :562:8] wire _s1_hazard_T_61 = pstore1_valid_likely & _s1_hazard_T_60; // @[DCache.scala:505:51, :561:65, :564:27] wire [8:0] _s1_hazard_T_62 = pstore2_addr[11:3]; // @[DCache.scala:524:31, :561:9] wire _s1_hazard_T_64 = _s1_hazard_T_62 == _s1_hazard_T_63; // @[DCache.scala:561:{9,31,43}] wire _s1_hazard_T_65 = pstore2_storegen_mask[0]; // @[package.scala:211:50] wire _s1_hazard_T_73 = _s1_hazard_T_65; // @[package.scala:211:50] wire _s1_hazard_T_66 = pstore2_storegen_mask[1]; // @[package.scala:211:50] wire _s1_hazard_T_74 = _s1_hazard_T_66; // @[package.scala:211:50] wire _s1_hazard_T_67 = pstore2_storegen_mask[2]; // @[package.scala:211:50] wire _s1_hazard_T_75 = _s1_hazard_T_67; // @[package.scala:211:50] wire _s1_hazard_T_68 = pstore2_storegen_mask[3]; // @[package.scala:211:50] wire _s1_hazard_T_76 = _s1_hazard_T_68; // @[package.scala:211:50] wire _s1_hazard_T_69 = pstore2_storegen_mask[4]; // @[package.scala:211:50] wire _s1_hazard_T_77 = _s1_hazard_T_69; // @[package.scala:211:50] wire _s1_hazard_T_70 = pstore2_storegen_mask[5]; // @[package.scala:211:50] wire _s1_hazard_T_78 = _s1_hazard_T_70; // @[package.scala:211:50] wire _s1_hazard_T_71 = pstore2_storegen_mask[6]; // @[package.scala:211:50] wire _s1_hazard_T_79 = _s1_hazard_T_71; // @[package.scala:211:50] wire _s1_hazard_T_72 = pstore2_storegen_mask[7]; // @[package.scala:211:50] wire _s1_hazard_T_80 = _s1_hazard_T_72; // @[package.scala:211:50] wire [1:0] s1_hazard_lo_lo_4 = {_s1_hazard_T_74, _s1_hazard_T_73}; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_hi_4 = {_s1_hazard_T_76, _s1_hazard_T_75}; // @[package.scala:45:27] wire [3:0] s1_hazard_lo_4 = {s1_hazard_lo_hi_4, s1_hazard_lo_lo_4}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_lo_4 = {_s1_hazard_T_78, _s1_hazard_T_77}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_hi_4 = {_s1_hazard_T_80, _s1_hazard_T_79}; // @[package.scala:45:27] wire [3:0] s1_hazard_hi_4 = {s1_hazard_hi_hi_4, s1_hazard_hi_lo_4}; // @[package.scala:45:27] wire [7:0] _s1_hazard_T_81 = {s1_hazard_hi_4, s1_hazard_lo_4}; // @[package.scala:45:27] wire _s1_hazard_T_82 = _s1_hazard_T_81[0]; // @[package.scala:45:27] wire _s1_hazard_T_83 = _s1_hazard_T_81[1]; // @[package.scala:45:27] wire _s1_hazard_T_84 = _s1_hazard_T_81[2]; // @[package.scala:45:27] wire _s1_hazard_T_85 = _s1_hazard_T_81[3]; // @[package.scala:45:27] wire _s1_hazard_T_86 = _s1_hazard_T_81[4]; // @[package.scala:45:27] wire _s1_hazard_T_87 = _s1_hazard_T_81[5]; // @[package.scala:45:27] wire _s1_hazard_T_88 = _s1_hazard_T_81[6]; // @[package.scala:45:27] wire _s1_hazard_T_89 = _s1_hazard_T_81[7]; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_lo_5 = {_s1_hazard_T_83, _s1_hazard_T_82}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_lo_hi_5 = {_s1_hazard_T_85, _s1_hazard_T_84}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_lo_5 = {s1_hazard_lo_hi_5, s1_hazard_lo_lo_5}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_lo_5 = {_s1_hazard_T_87, _s1_hazard_T_86}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_hi_5 = {_s1_hazard_T_89, _s1_hazard_T_88}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_hi_5 = {s1_hazard_hi_hi_5, s1_hazard_hi_lo_5}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_90 = {s1_hazard_hi_5, s1_hazard_lo_5}; // @[DCache.scala:1182:52] wire _s1_hazard_T_99 = _s1_hazard_T_91; // @[package.scala:211:50] wire _s1_hazard_T_100 = _s1_hazard_T_92; // @[package.scala:211:50] wire _s1_hazard_T_101 = _s1_hazard_T_93; // @[package.scala:211:50] wire _s1_hazard_T_102 = _s1_hazard_T_94; // @[package.scala:211:50] wire _s1_hazard_T_103 = _s1_hazard_T_95; // @[package.scala:211:50] wire _s1_hazard_T_104 = _s1_hazard_T_96; // @[package.scala:211:50] wire _s1_hazard_T_105 = _s1_hazard_T_97; // @[package.scala:211:50] wire _s1_hazard_T_106 = _s1_hazard_T_98; // @[package.scala:211:50] wire [1:0] s1_hazard_lo_lo_6 = {_s1_hazard_T_100, _s1_hazard_T_99}; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_hi_6 = {_s1_hazard_T_102, _s1_hazard_T_101}; // @[package.scala:45:27] wire [3:0] s1_hazard_lo_6 = {s1_hazard_lo_hi_6, s1_hazard_lo_lo_6}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_lo_6 = {_s1_hazard_T_104, _s1_hazard_T_103}; // @[package.scala:45:27] wire [1:0] s1_hazard_hi_hi_6 = {_s1_hazard_T_106, _s1_hazard_T_105}; // @[package.scala:45:27] wire [3:0] s1_hazard_hi_6 = {s1_hazard_hi_hi_6, s1_hazard_hi_lo_6}; // @[package.scala:45:27] wire [7:0] _s1_hazard_T_107 = {s1_hazard_hi_6, s1_hazard_lo_6}; // @[package.scala:45:27] wire _s1_hazard_T_108 = _s1_hazard_T_107[0]; // @[package.scala:45:27] wire _s1_hazard_T_109 = _s1_hazard_T_107[1]; // @[package.scala:45:27] wire _s1_hazard_T_110 = _s1_hazard_T_107[2]; // @[package.scala:45:27] wire _s1_hazard_T_111 = _s1_hazard_T_107[3]; // @[package.scala:45:27] wire _s1_hazard_T_112 = _s1_hazard_T_107[4]; // @[package.scala:45:27] wire _s1_hazard_T_113 = _s1_hazard_T_107[5]; // @[package.scala:45:27] wire _s1_hazard_T_114 = _s1_hazard_T_107[6]; // @[package.scala:45:27] wire _s1_hazard_T_115 = _s1_hazard_T_107[7]; // @[package.scala:45:27] wire [1:0] s1_hazard_lo_lo_7 = {_s1_hazard_T_109, _s1_hazard_T_108}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_lo_hi_7 = {_s1_hazard_T_111, _s1_hazard_T_110}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_lo_7 = {s1_hazard_lo_hi_7, s1_hazard_lo_lo_7}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_lo_7 = {_s1_hazard_T_113, _s1_hazard_T_112}; // @[DCache.scala:1182:52] wire [1:0] s1_hazard_hi_hi_7 = {_s1_hazard_T_115, _s1_hazard_T_114}; // @[DCache.scala:1182:52] wire [3:0] s1_hazard_hi_7 = {s1_hazard_hi_hi_7, s1_hazard_hi_lo_7}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_116 = {s1_hazard_hi_7, s1_hazard_lo_7}; // @[DCache.scala:1182:52] wire [7:0] _s1_hazard_T_117 = _s1_hazard_T_90 & _s1_hazard_T_116; // @[DCache.scala:562:38, :1182:52] wire _s1_hazard_T_118 = \|_s1_hazard_T_117; // @[DCache.scala:562:{38,66}] wire [7:0] _s1_hazard_T_119 = pstore2_storegen_mask & s1_mask_xwr; // @[DCache.scala:531:19, :562:77] wire _s1_hazard_T_120 = \|_s1_hazard_T_119; // @[DCache.scala:562:{77,92}] wire _s1_hazard_T_121 = s1_write ? _s1_hazard_T_118 : _s1_hazard_T_120; // @[DCache.scala:562:{8,66,92}] wire _s1_hazard_T_122 = _s1_hazard_T_64 & _s1_hazard_T_121; // @[DCache.scala:561:{31,65}, :562:8] wire _s1_hazard_T_123 = pstore2_valid & _s1_hazard_T_122; // @[DCache.scala:501:30, :561:65, :565:21] wire s1_hazard = _s1_hazard_T_61 \| _s1_hazard_T_123; // @[DCache.scala:564:{27,69}, :565:21] wire s1_raw_hazard = s1_read & s1_hazard; // @[DCache.scala:564:69, :566:31] wire _T_60 = s1_valid & s1_raw_hazard; // @[DCache.scala:182:25, :566:31, :571:18] reg io_cpu_s2_nack_cause_raw_REG; // @[DCache.scala:574:38] assign _io_cpu_s2_nack_cause_raw_T_3 = io_cpu_s2_nack_cause_raw_REG; // @[DCache.scala:574:{38,54}] assign io_cpu_s2_nack_cause_raw_0 = _io_cpu_s2_nack_cause_raw_T_3; // @[DCache.scala:101:7, :574:54] wire _a_source_T = ~uncachedInFlight_0; // @[DCache.scala:236:33, :577:34] wire [1:0] _a_source_T_1 = {_a_source_T, 1'h0}; // @[DCache.scala:577:{34,59}] wire _a_source_T_2 = _a_source_T_1[0]; // @[OneHot.scala:48:45] wire _a_source_T_3 = _a_source_T_1[1]; // @[OneHot.scala:48:45] wire a_source = ~_a_source_T_2; // @[OneHot.scala:48:45] wire get_source = a_source; // @[Mux.scala:50:70] wire put_source = a_source; // @[Mux.scala:50:70] wire putpartial_source = a_source; // @[Mux.scala:50:70] wire atomics_a_source = a_source; // @[Mux.scala:50:70] wire atomics_a_1_source = a_source; // @[Mux.scala:50:70] wire atomics_a_2_source = a_source; // @[Mux.scala:50:70] wire atomics_a_3_source = a_source; // @[Mux.scala:50:70] wire atomics_a_4_source = a_source; // @[Mux.scala:50:70] wire atomics_a_5_source = a_source; // @[Mux.scala:50:70] wire atomics_a_6_source = a_source; // @[Mux.scala:50:70] wire atomics_a_7_source = a_source; // @[Mux.scala:50:70] wire atomics_a_8_source = a_source; // @[Mux.scala:50:70] wire a_sel_shiftAmount = a_source; // @[OneHot.scala:64:49] wire [39:0] acquire_address = {_acquire_address_T, 6'h0}; // @[DCache.scala:578:{38,49}] wire [22:0] a_mask = {15'h0, pstore1_mask}; // @[DCache.scala:496:31, :582:29] wire [39:0] _GEN_102 = {s2_req_addr[39:14], s2_req_addr[13:0] ^ 14'h3000}; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_4; // @[Parameters.scala:137:31] assign _get_legal_T_4 = _GEN_102; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_4; // @[Parameters.scala:137:31] assign _put_legal_T_4 = _GEN_102; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_4; // @[Parameters.scala:137:31] assign _putpartial_legal_T_4 = _GEN_102; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_5 = {1'h0, _get_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_6 = _get_legal_T_5 & 41'h9A013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_7 = _get_legal_T_6; // @[Parameters.scala:137:46] wire _get_legal_T_8 = _get_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_9 = _get_legal_T_8; // @[Parameters.scala:684:54] wire _get_legal_T_62 = _get_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [40:0] _get_legal_T_15 = {1'h0, _get_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_16 = _get_legal_T_15 & 41'h9A012000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_17 = _get_legal_T_16; // @[Parameters.scala:137:46] wire _get_legal_T_18 = _get_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_103 = {s2_req_addr[39:17], s2_req_addr[16:0] ^ 17'h10000}; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_19; // @[Parameters.scala:137:31] assign _get_legal_T_19 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_24; // @[Parameters.scala:137:31] assign _get_legal_T_24 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_63; // @[Parameters.scala:137:31] assign _put_legal_T_63 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_63; // @[Parameters.scala:137:31] assign _putpartial_legal_T_63 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_47; // @[Parameters.scala:137:31] assign _atomics_legal_T_47 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_101; // @[Parameters.scala:137:31] assign _atomics_legal_T_101 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_155; // @[Parameters.scala:137:31] assign _atomics_legal_T_155 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_209; // @[Parameters.scala:137:31] assign _atomics_legal_T_209 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_263; // @[Parameters.scala:137:31] assign _atomics_legal_T_263 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_317; // @[Parameters.scala:137:31] assign _atomics_legal_T_317 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_371; // @[Parameters.scala:137:31] assign _atomics_legal_T_371 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_425; // @[Parameters.scala:137:31] assign _atomics_legal_T_425 = _GEN_103; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_479; // @[Parameters.scala:137:31] assign _atomics_legal_T_479 = _GEN_103; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_20 = {1'h0, _get_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_21 = _get_legal_T_20 & 41'h98013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_22 = _get_legal_T_21; // @[Parameters.scala:137:46] wire _get_legal_T_23 = _get_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _get_legal_T_25 = {1'h0, _get_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_26 = _get_legal_T_25 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_27 = _get_legal_T_26; // @[Parameters.scala:137:46] wire _get_legal_T_28 = _get_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_104 = {s2_req_addr[39:26], s2_req_addr[25:0] ^ 26'h2000000}; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_29; // @[Parameters.scala:137:31] assign _get_legal_T_29 = _GEN_104; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_24; // @[Parameters.scala:137:31] assign _put_legal_T_24 = _GEN_104; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_24; // @[Parameters.scala:137:31] assign _putpartial_legal_T_24 = _GEN_104; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_30 = {1'h0, _get_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_31 = _get_legal_T_30 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_32 = _get_legal_T_31; // @[Parameters.scala:137:46] wire _get_legal_T_33 = _get_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_105 = {s2_req_addr[39:28], s2_req_addr[27:0] ^ 28'h8000000}; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_34; // @[Parameters.scala:137:31] assign _get_legal_T_34 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _get_legal_T_39; // @[Parameters.scala:137:31] assign _get_legal_T_39 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_34; // @[Parameters.scala:137:31] assign _put_legal_T_34 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_39; // @[Parameters.scala:137:31] assign _put_legal_T_39 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_34; // @[Parameters.scala:137:31] assign _putpartial_legal_T_34 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_39; // @[Parameters.scala:137:31] assign _putpartial_legal_T_39 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_19; // @[Parameters.scala:137:31] assign _atomics_legal_T_19 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_24; // @[Parameters.scala:137:31] assign _atomics_legal_T_24 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_73; // @[Parameters.scala:137:31] assign _atomics_legal_T_73 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_78; // @[Parameters.scala:137:31] assign _atomics_legal_T_78 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_127; // @[Parameters.scala:137:31] assign _atomics_legal_T_127 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_132; // @[Parameters.scala:137:31] assign _atomics_legal_T_132 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_181; // @[Parameters.scala:137:31] assign _atomics_legal_T_181 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_186; // @[Parameters.scala:137:31] assign _atomics_legal_T_186 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_235; // @[Parameters.scala:137:31] assign _atomics_legal_T_235 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_240; // @[Parameters.scala:137:31] assign _atomics_legal_T_240 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_289; // @[Parameters.scala:137:31] assign _atomics_legal_T_289 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_294; // @[Parameters.scala:137:31] assign _atomics_legal_T_294 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_343; // @[Parameters.scala:137:31] assign _atomics_legal_T_343 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_348; // @[Parameters.scala:137:31] assign _atomics_legal_T_348 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_397; // @[Parameters.scala:137:31] assign _atomics_legal_T_397 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_402; // @[Parameters.scala:137:31] assign _atomics_legal_T_402 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_451; // @[Parameters.scala:137:31] assign _atomics_legal_T_451 = _GEN_105; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_456; // @[Parameters.scala:137:31] assign _atomics_legal_T_456 = _GEN_105; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_35 = {1'h0, _get_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_36 = _get_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_37 = _get_legal_T_36; // @[Parameters.scala:137:46] wire _get_legal_T_38 = _get_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _get_legal_T_40 = {1'h0, _get_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_41 = _get_legal_T_40 & 41'h9A010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_42 = _get_legal_T_41; // @[Parameters.scala:137:46] wire _get_legal_T_43 = _get_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_106 = {s2_req_addr[39:29], s2_req_addr[28:0] ^ 29'h10000000}; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_44; // @[Parameters.scala:137:31] assign _get_legal_T_44 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_44; // @[Parameters.scala:137:31] assign _put_legal_T_44 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_44; // @[Parameters.scala:137:31] assign _putpartial_legal_T_44 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_29; // @[Parameters.scala:137:31] assign _atomics_legal_T_29 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_83; // @[Parameters.scala:137:31] assign _atomics_legal_T_83 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_137; // @[Parameters.scala:137:31] assign _atomics_legal_T_137 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_191; // @[Parameters.scala:137:31] assign _atomics_legal_T_191 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_245; // @[Parameters.scala:137:31] assign _atomics_legal_T_245 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_299; // @[Parameters.scala:137:31] assign _atomics_legal_T_299 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_353; // @[Parameters.scala:137:31] assign _atomics_legal_T_353 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_407; // @[Parameters.scala:137:31] assign _atomics_legal_T_407 = _GEN_106; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_461; // @[Parameters.scala:137:31] assign _atomics_legal_T_461 = _GEN_106; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_45 = {1'h0, _get_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_46 = _get_legal_T_45 & 41'h9A013000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_47 = _get_legal_T_46; // @[Parameters.scala:137:46] wire _get_legal_T_48 = _get_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] assign io_cpu_s2_paddr_0 = s2_req_addr[31:0]; // @[DCache.scala:101:7, :339:19] wire [31:0] get_address = s2_req_addr[31:0]; // @[Edges.scala:460:17] wire [31:0] put_address = s2_req_addr[31:0]; // @[Edges.scala:480:17] wire [31:0] putpartial_address = s2_req_addr[31:0]; // @[Edges.scala:500:17] wire [31:0] atomics_a_address = s2_req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_1_address = s2_req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_2_address = s2_req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_3_address = s2_req_addr[31:0]; // @[Edges.scala:534:17] wire [31:0] atomics_a_4_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_5_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_6_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_7_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [31:0] atomics_a_8_address = s2_req_addr[31:0]; // @[Edges.scala:517:17] wire [39:0] _GEN_107 = {s2_req_addr[39:32], s2_req_addr[31:0] ^ 32'h80000000}; // @[DCache.scala:339:19] wire [39:0] _get_legal_T_49; // @[Parameters.scala:137:31] assign _get_legal_T_49 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _put_legal_T_49; // @[Parameters.scala:137:31] assign _put_legal_T_49 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_49; // @[Parameters.scala:137:31] assign _putpartial_legal_T_49 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_34; // @[Parameters.scala:137:31] assign _atomics_legal_T_34 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_88; // @[Parameters.scala:137:31] assign _atomics_legal_T_88 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_142; // @[Parameters.scala:137:31] assign _atomics_legal_T_142 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_196; // @[Parameters.scala:137:31] assign _atomics_legal_T_196 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_250; // @[Parameters.scala:137:31] assign _atomics_legal_T_250 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_304; // @[Parameters.scala:137:31] assign _atomics_legal_T_304 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_358; // @[Parameters.scala:137:31] assign _atomics_legal_T_358 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_412; // @[Parameters.scala:137:31] assign _atomics_legal_T_412 = _GEN_107; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_466; // @[Parameters.scala:137:31] assign _atomics_legal_T_466 = _GEN_107; // @[Parameters.scala:137:31] wire [40:0] _get_legal_T_50 = {1'h0, _get_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _get_legal_T_51 = _get_legal_T_50 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _get_legal_T_52 = _get_legal_T_51; // @[Parameters.scala:137:46] wire _get_legal_T_53 = _get_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _get_legal_T_54 = _get_legal_T_18 \| _get_legal_T_23; // @[Parameters.scala:685:42] wire _get_legal_T_55 = _get_legal_T_54 \| _get_legal_T_28; // @[Parameters.scala:685:42] wire _get_legal_T_56 = _get_legal_T_55 \| _get_legal_T_33; // @[Parameters.scala:685:42] wire _get_legal_T_57 = _get_legal_T_56 \| _get_legal_T_38; // @[Parameters.scala:685:42] wire _get_legal_T_58 = _get_legal_T_57 \| _get_legal_T_43; // @[Parameters.scala:685:42] wire _get_legal_T_59 = _get_legal_T_58 \| _get_legal_T_48; // @[Parameters.scala:685:42] wire _get_legal_T_60 = _get_legal_T_59 \| _get_legal_T_53; // @[Parameters.scala:685:42] wire _get_legal_T_61 = _get_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire get_legal = _get_legal_T_62 \| _get_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire [7:0] _get_a_mask_T; // @[Misc.scala:222:10] wire [3:0] get_size; // @[Edges.scala:460:17] wire [7:0] get_mask; // @[Edges.scala:460:17] wire [3:0] _GEN_108 = {2'h0, s2_req_size}; // @[Edges.scala:463:15] assign get_size = _GEN_108; // @[Edges.scala:460:17, :463:15] wire [3:0] put_size; // @[Edges.scala:480:17] assign put_size = _GEN_108; // @[Edges.scala:463:15, :480:17] wire [3:0] putpartial_size; // @[Edges.scala:500:17] assign putpartial_size = _GEN_108; // @[Edges.scala:463:15, :500:17] wire [3:0] atomics_a_size; // @[Edges.scala:534:17] assign atomics_a_size = _GEN_108; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_1_size; // @[Edges.scala:534:17] assign atomics_a_1_size = _GEN_108; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_2_size; // @[Edges.scala:534:17] assign atomics_a_2_size = _GEN_108; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_3_size; // @[Edges.scala:534:17] assign atomics_a_3_size = _GEN_108; // @[Edges.scala:463:15, :534:17] wire [3:0] atomics_a_4_size; // @[Edges.scala:517:17] assign atomics_a_4_size = _GEN_108; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_5_size; // @[Edges.scala:517:17] assign atomics_a_5_size = _GEN_108; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_6_size; // @[Edges.scala:517:17] assign atomics_a_6_size = _GEN_108; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_7_size; // @[Edges.scala:517:17] assign atomics_a_7_size = _GEN_108; // @[Edges.scala:463:15, :517:17] wire [3:0] atomics_a_8_size; // @[Edges.scala:517:17] assign atomics_a_8_size = _GEN_108; // @[Edges.scala:463:15, :517:17] wire [2:0] _GEN_109 = {1'h0, s2_req_size}; // @[Misc.scala:202:34] wire [2:0] _get_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _get_a_mask_sizeOH_T = _GEN_109; // @[Misc.scala:202:34] wire [2:0] _put_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _put_a_mask_sizeOH_T = _GEN_109; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T = _GEN_109; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_3; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_3 = _GEN_109; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_6; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_6 = _GEN_109; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_9; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_9 = _GEN_109; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_12; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_12 = _GEN_109; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_15; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_15 = _GEN_109; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_18; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_18 = _GEN_109; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_21; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_21 = _GEN_109; // @[Misc.scala:202:34] wire [2:0] _atomics_a_mask_sizeOH_T_24; // @[Misc.scala:202:34] assign _atomics_a_mask_sizeOH_T_24 = _GEN_109; // @[Misc.scala:202:34] wire [1:0] get_a_mask_sizeOH_shiftAmount = _get_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _get_a_mask_sizeOH_T_1 = 4'h1 << get_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _get_a_mask_sizeOH_T_2 = _get_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] get_a_mask_sizeOH = {_get_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire get_a_mask_sub_sub_sub_0_1 = &s2_req_size; // @[Misc.scala:206:21] wire get_a_mask_sub_sub_size = get_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_sub_bit = s2_req_addr[2]; // @[Misc.scala:210:26] wire put_a_mask_sub_sub_bit = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_1 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_2 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_3 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_4 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_5 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_6 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_7 = s2_req_addr[2]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_sub_bit_8 = s2_req_addr[2]; // @[Misc.scala:210:26] wire _io_cpu_resp_bits_data_shifted_T = s2_req_addr[2]; // @[Misc.scala:210:26] wire _io_cpu_resp_bits_data_word_bypass_shifted_T = s2_req_addr[2]; // @[Misc.scala:210:26] wire get_a_mask_sub_sub_1_2 = get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire get_a_mask_sub_sub_nbit = ~get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_sub_0_2 = get_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_sub_acc_T = get_a_mask_sub_sub_size & get_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_0_1 = get_a_mask_sub_sub_sub_0_1 \| _get_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _get_a_mask_sub_sub_acc_T_1 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_sub_1_1 = get_a_mask_sub_sub_sub_0_1 \| _get_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire get_a_mask_sub_size = get_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_sub_bit = s2_req_addr[1]; // @[Misc.scala:210:26] wire put_a_mask_sub_bit = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_1 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_2 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_3 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_4 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_5 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_6 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_7 = s2_req_addr[1]; // @[Misc.scala:210:26] wire atomics_a_mask_sub_bit_8 = s2_req_addr[1]; // @[Misc.scala:210:26] wire _io_cpu_resp_bits_data_shifted_T_3 = s2_req_addr[1]; // @[Misc.scala:210:26] wire get_a_mask_sub_nbit = ~get_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_sub_0_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T = get_a_mask_sub_size & get_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_0_1 = get_a_mask_sub_sub_0_1 \| _get_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_1_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_1 = get_a_mask_sub_size & get_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_1_1 = get_a_mask_sub_sub_0_1 \| _get_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_2_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_sub_acc_T_2 = get_a_mask_sub_size & get_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_2_1 = get_a_mask_sub_sub_1_1 \| _get_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_sub_3_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_sub_acc_T_3 = get_a_mask_sub_size & get_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_sub_3_1 = get_a_mask_sub_sub_1_1 \| _get_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_size = get_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire get_a_mask_bit = s2_req_addr[0]; // @[Misc.scala:210:26] wire put_a_mask_bit = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_1 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_2 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_3 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_4 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_5 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_6 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_7 = s2_req_addr[0]; // @[Misc.scala:210:26] wire atomics_a_mask_bit_8 = s2_req_addr[0]; // @[Misc.scala:210:26] wire _io_cpu_resp_bits_data_shifted_T_6 = s2_req_addr[0]; // @[Misc.scala:210:26] wire get_a_mask_nbit = ~get_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire get_a_mask_eq = get_a_mask_sub_0_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T = get_a_mask_size & get_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc = get_a_mask_sub_0_1 \| _get_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_1 = get_a_mask_sub_0_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_1 = get_a_mask_size & get_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_1 = get_a_mask_sub_0_1 \| _get_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_2 = get_a_mask_sub_1_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_2 = get_a_mask_size & get_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_2 = get_a_mask_sub_1_1 \| _get_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_3 = get_a_mask_sub_1_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_3 = get_a_mask_size & get_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_3 = get_a_mask_sub_1_1 \| _get_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_4 = get_a_mask_sub_2_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_4 = get_a_mask_size & get_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_4 = get_a_mask_sub_2_1 \| _get_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_5 = get_a_mask_sub_2_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_5 = get_a_mask_size & get_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_5 = get_a_mask_sub_2_1 \| _get_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_6 = get_a_mask_sub_3_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _get_a_mask_acc_T_6 = get_a_mask_size & get_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_6 = get_a_mask_sub_3_1 \| _get_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire get_a_mask_eq_7 = get_a_mask_sub_3_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _get_a_mask_acc_T_7 = get_a_mask_size & get_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire get_a_mask_acc_7 = get_a_mask_sub_3_1 \| _get_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] get_a_mask_lo_lo = {get_a_mask_acc_1, get_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_lo_hi = {get_a_mask_acc_3, get_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_lo = {get_a_mask_lo_hi, get_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] get_a_mask_hi_lo = {get_a_mask_acc_5, get_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] get_a_mask_hi_hi = {get_a_mask_acc_7, get_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] get_a_mask_hi = {get_a_mask_hi_hi, get_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _get_a_mask_T = {get_a_mask_hi, get_a_mask_lo}; // @[Misc.scala:222:10] assign get_mask = _get_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _put_legal_T_5 = {1'h0, _put_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_6 = _put_legal_T_5 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_7 = _put_legal_T_6; // @[Parameters.scala:137:46] wire _put_legal_T_8 = _put_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_9 = _put_legal_T_8; // @[Parameters.scala:684:54] wire _put_legal_T_69 = _put_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [40:0] _put_legal_T_15 = {1'h0, _put_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_16 = _put_legal_T_15 & 41'h9A112000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_17 = _put_legal_T_16; // @[Parameters.scala:137:46] wire _put_legal_T_18 = _put_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_110 = {s2_req_addr[39:21], s2_req_addr[20:0] ^ 21'h100000}; // @[DCache.scala:339:19] wire [39:0] _put_legal_T_19; // @[Parameters.scala:137:31] assign _put_legal_T_19 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_19; // @[Parameters.scala:137:31] assign _putpartial_legal_T_19 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_9; // @[Parameters.scala:137:31] assign _atomics_legal_T_9 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_63; // @[Parameters.scala:137:31] assign _atomics_legal_T_63 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_117; // @[Parameters.scala:137:31] assign _atomics_legal_T_117 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_171; // @[Parameters.scala:137:31] assign _atomics_legal_T_171 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_225; // @[Parameters.scala:137:31] assign _atomics_legal_T_225 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_279; // @[Parameters.scala:137:31] assign _atomics_legal_T_279 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_333; // @[Parameters.scala:137:31] assign _atomics_legal_T_333 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_387; // @[Parameters.scala:137:31] assign _atomics_legal_T_387 = _GEN_110; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_441; // @[Parameters.scala:137:31] assign _atomics_legal_T_441 = _GEN_110; // @[Parameters.scala:137:31] wire [40:0] _put_legal_T_20 = {1'h0, _put_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_21 = _put_legal_T_20 & 41'h9A103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_22 = _put_legal_T_21; // @[Parameters.scala:137:46] wire _put_legal_T_23 = _put_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_25 = {1'h0, _put_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_26 = _put_legal_T_25 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_27 = _put_legal_T_26; // @[Parameters.scala:137:46] wire _put_legal_T_28 = _put_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_111 = {s2_req_addr[39:26], s2_req_addr[25:0] ^ 26'h2010000}; // @[DCache.scala:339:19] wire [39:0] _put_legal_T_29; // @[Parameters.scala:137:31] assign _put_legal_T_29 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _putpartial_legal_T_29; // @[Parameters.scala:137:31] assign _putpartial_legal_T_29 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_14; // @[Parameters.scala:137:31] assign _atomics_legal_T_14 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_68; // @[Parameters.scala:137:31] assign _atomics_legal_T_68 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_122; // @[Parameters.scala:137:31] assign _atomics_legal_T_122 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_176; // @[Parameters.scala:137:31] assign _atomics_legal_T_176 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_230; // @[Parameters.scala:137:31] assign _atomics_legal_T_230 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_284; // @[Parameters.scala:137:31] assign _atomics_legal_T_284 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_338; // @[Parameters.scala:137:31] assign _atomics_legal_T_338 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_392; // @[Parameters.scala:137:31] assign _atomics_legal_T_392 = _GEN_111; // @[Parameters.scala:137:31] wire [39:0] _atomics_legal_T_446; // @[Parameters.scala:137:31] assign _atomics_legal_T_446 = _GEN_111; // @[Parameters.scala:137:31] wire [40:0] _put_legal_T_30 = {1'h0, _put_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_31 = _put_legal_T_30 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_32 = _put_legal_T_31; // @[Parameters.scala:137:46] wire _put_legal_T_33 = _put_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_35 = {1'h0, _put_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_36 = _put_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_37 = _put_legal_T_36; // @[Parameters.scala:137:46] wire _put_legal_T_38 = _put_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_40 = {1'h0, _put_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_41 = _put_legal_T_40 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_42 = _put_legal_T_41; // @[Parameters.scala:137:46] wire _put_legal_T_43 = _put_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_45 = {1'h0, _put_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_46 = _put_legal_T_45 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_47 = _put_legal_T_46; // @[Parameters.scala:137:46] wire _put_legal_T_48 = _put_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _put_legal_T_50 = {1'h0, _put_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_51 = _put_legal_T_50 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_52 = _put_legal_T_51; // @[Parameters.scala:137:46] wire _put_legal_T_53 = _put_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_54 = _put_legal_T_18 \| _put_legal_T_23; // @[Parameters.scala:685:42] wire _put_legal_T_55 = _put_legal_T_54 \| _put_legal_T_28; // @[Parameters.scala:685:42] wire _put_legal_T_56 = _put_legal_T_55 \| _put_legal_T_33; // @[Parameters.scala:685:42] wire _put_legal_T_57 = _put_legal_T_56 \| _put_legal_T_38; // @[Parameters.scala:685:42] wire _put_legal_T_58 = _put_legal_T_57 \| _put_legal_T_43; // @[Parameters.scala:685:42] wire _put_legal_T_59 = _put_legal_T_58 \| _put_legal_T_48; // @[Parameters.scala:685:42] wire _put_legal_T_60 = _put_legal_T_59 \| _put_legal_T_53; // @[Parameters.scala:685:42] wire _put_legal_T_61 = _put_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire [40:0] _put_legal_T_64 = {1'h0, _put_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [40:0] _put_legal_T_65 = _put_legal_T_64 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _put_legal_T_66 = _put_legal_T_65; // @[Parameters.scala:137:46] wire _put_legal_T_67 = _put_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _put_legal_T_70 = _put_legal_T_69 \| _put_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire put_legal = _put_legal_T_70; // @[Parameters.scala:686:26] wire [7:0] _put_a_mask_T; // @[Misc.scala:222:10] wire [7:0] put_mask; // @[Edges.scala:480:17] wire [1:0] put_a_mask_sizeOH_shiftAmount = _put_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _put_a_mask_sizeOH_T_1 = 4'h1 << put_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _put_a_mask_sizeOH_T_2 = _put_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] put_a_mask_sizeOH = {_put_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire put_a_mask_sub_sub_sub_0_1 = &s2_req_size; // @[Misc.scala:206:21] wire put_a_mask_sub_sub_size = put_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_sub_1_2 = put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire put_a_mask_sub_sub_nbit = ~put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_sub_0_2 = put_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_sub_acc_T = put_a_mask_sub_sub_size & put_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_0_1 = put_a_mask_sub_sub_sub_0_1 \| _put_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _put_a_mask_sub_sub_acc_T_1 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_sub_1_1 = put_a_mask_sub_sub_sub_0_1 \| _put_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire put_a_mask_sub_size = put_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_sub_nbit = ~put_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_sub_0_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T = put_a_mask_sub_size & put_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_0_1 = put_a_mask_sub_sub_0_1 \| _put_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_1_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_1 = put_a_mask_sub_size & put_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_1_1 = put_a_mask_sub_sub_0_1 \| _put_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_2_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_sub_acc_T_2 = put_a_mask_sub_size & put_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_2_1 = put_a_mask_sub_sub_1_1 \| _put_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_sub_3_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_sub_acc_T_3 = put_a_mask_sub_size & put_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_sub_3_1 = put_a_mask_sub_sub_1_1 \| _put_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_size = put_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire put_a_mask_nbit = ~put_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire put_a_mask_eq = put_a_mask_sub_0_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T = put_a_mask_size & put_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc = put_a_mask_sub_0_1 \| _put_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_1 = put_a_mask_sub_0_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_1 = put_a_mask_size & put_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_1 = put_a_mask_sub_0_1 \| _put_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_2 = put_a_mask_sub_1_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_2 = put_a_mask_size & put_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_2 = put_a_mask_sub_1_1 \| _put_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_3 = put_a_mask_sub_1_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_3 = put_a_mask_size & put_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_3 = put_a_mask_sub_1_1 \| _put_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_4 = put_a_mask_sub_2_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_4 = put_a_mask_size & put_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_4 = put_a_mask_sub_2_1 \| _put_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_5 = put_a_mask_sub_2_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_5 = put_a_mask_size & put_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_5 = put_a_mask_sub_2_1 \| _put_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_6 = put_a_mask_sub_3_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _put_a_mask_acc_T_6 = put_a_mask_size & put_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_6 = put_a_mask_sub_3_1 \| _put_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire put_a_mask_eq_7 = put_a_mask_sub_3_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _put_a_mask_acc_T_7 = put_a_mask_size & put_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire put_a_mask_acc_7 = put_a_mask_sub_3_1 \| _put_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] put_a_mask_lo_lo = {put_a_mask_acc_1, put_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_lo_hi = {put_a_mask_acc_3, put_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_lo = {put_a_mask_lo_hi, put_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] put_a_mask_hi_lo = {put_a_mask_acc_5, put_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] put_a_mask_hi_hi = {put_a_mask_acc_7, put_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] put_a_mask_hi = {put_a_mask_hi_hi, put_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _put_a_mask_T = {put_a_mask_hi, put_a_mask_lo}; // @[Misc.scala:222:10] assign put_mask = _put_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _putpartial_legal_T_5 = {1'h0, _putpartial_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_6 = _putpartial_legal_T_5 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_7 = _putpartial_legal_T_6; // @[Parameters.scala:137:46] wire _putpartial_legal_T_8 = _putpartial_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _putpartial_legal_T_9 = _putpartial_legal_T_8; // @[Parameters.scala:684:54] wire _putpartial_legal_T_69 = _putpartial_legal_T_9; // @[Parameters.scala:684:54, :686:26] wire [40:0] _putpartial_legal_T_15 = {1'h0, _putpartial_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_16 = _putpartial_legal_T_15 & 41'h9A112000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_17 = _putpartial_legal_T_16; // @[Parameters.scala:137:46] wire _putpartial_legal_T_18 = _putpartial_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_20 = {1'h0, _putpartial_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_21 = _putpartial_legal_T_20 & 41'h9A103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_22 = _putpartial_legal_T_21; // @[Parameters.scala:137:46] wire _putpartial_legal_T_23 = _putpartial_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_25 = {1'h0, _putpartial_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_26 = _putpartial_legal_T_25 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_27 = _putpartial_legal_T_26; // @[Parameters.scala:137:46] wire _putpartial_legal_T_28 = _putpartial_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_30 = {1'h0, _putpartial_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_31 = _putpartial_legal_T_30 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_32 = _putpartial_legal_T_31; // @[Parameters.scala:137:46] wire _putpartial_legal_T_33 = _putpartial_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_35 = {1'h0, _putpartial_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_36 = _putpartial_legal_T_35 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_37 = _putpartial_legal_T_36; // @[Parameters.scala:137:46] wire _putpartial_legal_T_38 = _putpartial_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_40 = {1'h0, _putpartial_legal_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_41 = _putpartial_legal_T_40 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_42 = _putpartial_legal_T_41; // @[Parameters.scala:137:46] wire _putpartial_legal_T_43 = _putpartial_legal_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_45 = {1'h0, _putpartial_legal_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_46 = _putpartial_legal_T_45 & 41'h9A113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_47 = _putpartial_legal_T_46; // @[Parameters.scala:137:46] wire _putpartial_legal_T_48 = _putpartial_legal_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _putpartial_legal_T_50 = {1'h0, _putpartial_legal_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_51 = _putpartial_legal_T_50 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_52 = _putpartial_legal_T_51; // @[Parameters.scala:137:46] wire _putpartial_legal_T_53 = _putpartial_legal_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _putpartial_legal_T_54 = _putpartial_legal_T_18 \| _putpartial_legal_T_23; // @[Parameters.scala:685:42] wire _putpartial_legal_T_55 = _putpartial_legal_T_54 \| _putpartial_legal_T_28; // @[Parameters.scala:685:42] wire _putpartial_legal_T_56 = _putpartial_legal_T_55 \| _putpartial_legal_T_33; // @[Parameters.scala:685:42] wire _putpartial_legal_T_57 = _putpartial_legal_T_56 \| _putpartial_legal_T_38; // @[Parameters.scala:685:42] wire _putpartial_legal_T_58 = _putpartial_legal_T_57 \| _putpartial_legal_T_43; // @[Parameters.scala:685:42] wire _putpartial_legal_T_59 = _putpartial_legal_T_58 \| _putpartial_legal_T_48; // @[Parameters.scala:685:42] wire _putpartial_legal_T_60 = _putpartial_legal_T_59 \| _putpartial_legal_T_53; // @[Parameters.scala:685:42] wire _putpartial_legal_T_61 = _putpartial_legal_T_60; // @[Parameters.scala:684:54, :685:42] wire [40:0] _putpartial_legal_T_64 = {1'h0, _putpartial_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [40:0] _putpartial_legal_T_65 = _putpartial_legal_T_64 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _putpartial_legal_T_66 = _putpartial_legal_T_65; // @[Parameters.scala:137:46] wire _putpartial_legal_T_67 = _putpartial_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _putpartial_legal_T_70 = _putpartial_legal_T_69 \| _putpartial_legal_T_61; // @[Parameters.scala:684:54, :686:26] wire putpartial_legal = _putpartial_legal_T_70; // @[Parameters.scala:686:26] wire [7:0] putpartial_mask; // @[Edges.scala:500:17] assign putpartial_mask = a_mask[7:0]; // @[Edges.scala:500:17, :508:15] wire [40:0] _atomics_legal_T_5 = {1'h0, _atomics_legal_T_4}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_6 = _atomics_legal_T_5 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_7 = _atomics_legal_T_6; // @[Parameters.scala:137:46] wire _atomics_legal_T_8 = _atomics_legal_T_7 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_10 = {1'h0, _atomics_legal_T_9}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_11 = _atomics_legal_T_10 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_12 = _atomics_legal_T_11; // @[Parameters.scala:137:46] wire _atomics_legal_T_13 = _atomics_legal_T_12 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_15 = {1'h0, _atomics_legal_T_14}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_16 = _atomics_legal_T_15 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_17 = _atomics_legal_T_16; // @[Parameters.scala:137:46] wire _atomics_legal_T_18 = _atomics_legal_T_17 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_20 = {1'h0, _atomics_legal_T_19}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_21 = _atomics_legal_T_20 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_22 = _atomics_legal_T_21; // @[Parameters.scala:137:46] wire _atomics_legal_T_23 = _atomics_legal_T_22 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_25 = {1'h0, _atomics_legal_T_24}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_26 = _atomics_legal_T_25 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_27 = _atomics_legal_T_26; // @[Parameters.scala:137:46] wire _atomics_legal_T_28 = _atomics_legal_T_27 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_30 = {1'h0, _atomics_legal_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_31 = _atomics_legal_T_30 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_32 = _atomics_legal_T_31; // @[Parameters.scala:137:46] wire _atomics_legal_T_33 = _atomics_legal_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_35 = {1'h0, _atomics_legal_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_36 = _atomics_legal_T_35 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_37 = _atomics_legal_T_36; // @[Parameters.scala:137:46] wire _atomics_legal_T_38 = _atomics_legal_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_39 = _atomics_legal_T_8 \| _atomics_legal_T_13; // @[Parameters.scala:685:42] wire _atomics_legal_T_40 = _atomics_legal_T_39 \| _atomics_legal_T_18; // @[Parameters.scala:685:42] wire _atomics_legal_T_41 = _atomics_legal_T_40 \| _atomics_legal_T_23; // @[Parameters.scala:685:42] wire _atomics_legal_T_42 = _atomics_legal_T_41 \| _atomics_legal_T_28; // @[Parameters.scala:685:42] wire _atomics_legal_T_43 = _atomics_legal_T_42 \| _atomics_legal_T_33; // @[Parameters.scala:685:42] wire _atomics_legal_T_44 = _atomics_legal_T_43 \| _atomics_legal_T_38; // @[Parameters.scala:685:42] wire _atomics_legal_T_45 = _atomics_legal_T_44; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_53 = _atomics_legal_T_45; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_48 = {1'h0, _atomics_legal_T_47}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_49 = _atomics_legal_T_48 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_50 = _atomics_legal_T_49; // @[Parameters.scala:137:46] wire _atomics_legal_T_51 = _atomics_legal_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal = _atomics_legal_T_53; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T; // @[Misc.scala:222:10] wire [7:0] atomics_a_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount = _atomics_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_1 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_2 = _atomics_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH = {_atomics_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size = atomics_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2 = atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit = ~atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2 = atomics_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1 = atomics_a_mask_sub_sub_sub_0_1 \| _atomics_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_1 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1 = atomics_a_mask_sub_sub_sub_0_1 \| _atomics_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size = atomics_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit = ~atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T = atomics_a_mask_sub_size & atomics_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1 = atomics_a_mask_sub_sub_0_1 \| _atomics_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_1 = atomics_a_mask_sub_size & atomics_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1 = atomics_a_mask_sub_sub_0_1 \| _atomics_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_2 = atomics_a_mask_sub_size & atomics_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1 = atomics_a_mask_sub_sub_1_1 \| _atomics_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_3 = atomics_a_mask_sub_size & atomics_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1 = atomics_a_mask_sub_sub_1_1 \| _atomics_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size = atomics_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit = ~atomics_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq = atomics_a_mask_sub_0_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T = atomics_a_mask_size & atomics_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc = atomics_a_mask_sub_0_1 \| _atomics_a_mask_acc_T; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_1 = atomics_a_mask_sub_0_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_1 = atomics_a_mask_size & atomics_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_1 = atomics_a_mask_sub_0_1 \| _atomics_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_2 = atomics_a_mask_sub_1_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_2 = atomics_a_mask_size & atomics_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_2 = atomics_a_mask_sub_1_1 \| _atomics_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_3 = atomics_a_mask_sub_1_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_3 = atomics_a_mask_size & atomics_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_3 = atomics_a_mask_sub_1_1 \| _atomics_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_4 = atomics_a_mask_sub_2_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_4 = atomics_a_mask_size & atomics_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_4 = atomics_a_mask_sub_2_1 \| _atomics_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_5 = atomics_a_mask_sub_2_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_5 = atomics_a_mask_size & atomics_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_5 = atomics_a_mask_sub_2_1 \| _atomics_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_6 = atomics_a_mask_sub_3_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_6 = atomics_a_mask_size & atomics_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_6 = atomics_a_mask_sub_3_1 \| _atomics_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_7 = atomics_a_mask_sub_3_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_7 = atomics_a_mask_size & atomics_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_7 = atomics_a_mask_sub_3_1 \| _atomics_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo = {atomics_a_mask_acc_1, atomics_a_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi = {atomics_a_mask_acc_3, atomics_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo = {atomics_a_mask_lo_hi, atomics_a_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo = {atomics_a_mask_acc_5, atomics_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi = {atomics_a_mask_acc_7, atomics_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi = {atomics_a_mask_hi_hi, atomics_a_mask_hi_lo}; // @[Misc.scala:222:10] assign _atomics_a_mask_T = {atomics_a_mask_hi, atomics_a_mask_lo}; // @[Misc.scala:222:10] assign atomics_a_mask = _atomics_a_mask_T; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_59 = {1'h0, _atomics_legal_T_58}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_60 = _atomics_legal_T_59 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_61 = _atomics_legal_T_60; // @[Parameters.scala:137:46] wire _atomics_legal_T_62 = _atomics_legal_T_61 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_64 = {1'h0, _atomics_legal_T_63}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_65 = _atomics_legal_T_64 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_66 = _atomics_legal_T_65; // @[Parameters.scala:137:46] wire _atomics_legal_T_67 = _atomics_legal_T_66 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_69 = {1'h0, _atomics_legal_T_68}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_70 = _atomics_legal_T_69 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_71 = _atomics_legal_T_70; // @[Parameters.scala:137:46] wire _atomics_legal_T_72 = _atomics_legal_T_71 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_74 = {1'h0, _atomics_legal_T_73}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_75 = _atomics_legal_T_74 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_76 = _atomics_legal_T_75; // @[Parameters.scala:137:46] wire _atomics_legal_T_77 = _atomics_legal_T_76 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_79 = {1'h0, _atomics_legal_T_78}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_80 = _atomics_legal_T_79 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_81 = _atomics_legal_T_80; // @[Parameters.scala:137:46] wire _atomics_legal_T_82 = _atomics_legal_T_81 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_84 = {1'h0, _atomics_legal_T_83}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_85 = _atomics_legal_T_84 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_86 = _atomics_legal_T_85; // @[Parameters.scala:137:46] wire _atomics_legal_T_87 = _atomics_legal_T_86 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_89 = {1'h0, _atomics_legal_T_88}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_90 = _atomics_legal_T_89 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_91 = _atomics_legal_T_90; // @[Parameters.scala:137:46] wire _atomics_legal_T_92 = _atomics_legal_T_91 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_93 = _atomics_legal_T_62 \| _atomics_legal_T_67; // @[Parameters.scala:685:42] wire _atomics_legal_T_94 = _atomics_legal_T_93 \| _atomics_legal_T_72; // @[Parameters.scala:685:42] wire _atomics_legal_T_95 = _atomics_legal_T_94 \| _atomics_legal_T_77; // @[Parameters.scala:685:42] wire _atomics_legal_T_96 = _atomics_legal_T_95 \| _atomics_legal_T_82; // @[Parameters.scala:685:42] wire _atomics_legal_T_97 = _atomics_legal_T_96 \| _atomics_legal_T_87; // @[Parameters.scala:685:42] wire _atomics_legal_T_98 = _atomics_legal_T_97 \| _atomics_legal_T_92; // @[Parameters.scala:685:42] wire _atomics_legal_T_99 = _atomics_legal_T_98; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_107 = _atomics_legal_T_99; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_102 = {1'h0, _atomics_legal_T_101}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_103 = _atomics_legal_T_102 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_104 = _atomics_legal_T_103; // @[Parameters.scala:137:46] wire _atomics_legal_T_105 = _atomics_legal_T_104 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_1 = _atomics_legal_T_107; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [7:0] atomics_a_1_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_1 = _atomics_a_mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_4 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_5 = _atomics_a_mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_1 = {_atomics_a_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_1 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_1 = atomics_a_mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_1 = atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_1 = ~atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_1 = atomics_a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_2 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 \| _atomics_a_mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_3 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 \| _atomics_a_mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_1 = atomics_a_mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_1 = ~atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_4 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_1 = atomics_a_mask_sub_sub_0_1_1 \| _atomics_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_5 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_1 = atomics_a_mask_sub_sub_0_1_1 \| _atomics_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_6 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_1 = atomics_a_mask_sub_sub_1_1_1 \| _atomics_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_7 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_1 = atomics_a_mask_sub_sub_1_1_1 \| _atomics_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_1 = atomics_a_mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_1 = ~atomics_a_mask_bit_1; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_8 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_8 = atomics_a_mask_size_1 & atomics_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_8 = atomics_a_mask_sub_0_1_1 \| _atomics_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_9 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_9 = atomics_a_mask_size_1 & atomics_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_9 = atomics_a_mask_sub_0_1_1 \| _atomics_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_10 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_10 = atomics_a_mask_size_1 & atomics_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_10 = atomics_a_mask_sub_1_1_1 \| _atomics_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_11 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_11 = atomics_a_mask_size_1 & atomics_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_11 = atomics_a_mask_sub_1_1_1 \| _atomics_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_12 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_12 = atomics_a_mask_size_1 & atomics_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_12 = atomics_a_mask_sub_2_1_1 \| _atomics_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_13 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_13 = atomics_a_mask_size_1 & atomics_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_13 = atomics_a_mask_sub_2_1_1 \| _atomics_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_14 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_14 = atomics_a_mask_size_1 & atomics_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_14 = atomics_a_mask_sub_3_1_1 \| _atomics_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_15 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_15 = atomics_a_mask_size_1 & atomics_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_15 = atomics_a_mask_sub_3_1_1 \| _atomics_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_1 = {atomics_a_mask_acc_9, atomics_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_1 = {atomics_a_mask_acc_11, atomics_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_1 = {atomics_a_mask_lo_hi_1, atomics_a_mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_1 = {atomics_a_mask_acc_13, atomics_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_1 = {atomics_a_mask_acc_15, atomics_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_1 = {atomics_a_mask_hi_hi_1, atomics_a_mask_hi_lo_1}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_1 = {atomics_a_mask_hi_1, atomics_a_mask_lo_1}; // @[Misc.scala:222:10] assign atomics_a_1_mask = _atomics_a_mask_T_1; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_113 = {1'h0, _atomics_legal_T_112}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_114 = _atomics_legal_T_113 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_115 = _atomics_legal_T_114; // @[Parameters.scala:137:46] wire _atomics_legal_T_116 = _atomics_legal_T_115 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_118 = {1'h0, _atomics_legal_T_117}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_119 = _atomics_legal_T_118 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_120 = _atomics_legal_T_119; // @[Parameters.scala:137:46] wire _atomics_legal_T_121 = _atomics_legal_T_120 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_123 = {1'h0, _atomics_legal_T_122}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_124 = _atomics_legal_T_123 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_125 = _atomics_legal_T_124; // @[Parameters.scala:137:46] wire _atomics_legal_T_126 = _atomics_legal_T_125 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_128 = {1'h0, _atomics_legal_T_127}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_129 = _atomics_legal_T_128 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_130 = _atomics_legal_T_129; // @[Parameters.scala:137:46] wire _atomics_legal_T_131 = _atomics_legal_T_130 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_133 = {1'h0, _atomics_legal_T_132}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_134 = _atomics_legal_T_133 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_135 = _atomics_legal_T_134; // @[Parameters.scala:137:46] wire _atomics_legal_T_136 = _atomics_legal_T_135 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_138 = {1'h0, _atomics_legal_T_137}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_139 = _atomics_legal_T_138 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_140 = _atomics_legal_T_139; // @[Parameters.scala:137:46] wire _atomics_legal_T_141 = _atomics_legal_T_140 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_143 = {1'h0, _atomics_legal_T_142}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_144 = _atomics_legal_T_143 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_145 = _atomics_legal_T_144; // @[Parameters.scala:137:46] wire _atomics_legal_T_146 = _atomics_legal_T_145 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_147 = _atomics_legal_T_116 \| _atomics_legal_T_121; // @[Parameters.scala:685:42] wire _atomics_legal_T_148 = _atomics_legal_T_147 \| _atomics_legal_T_126; // @[Parameters.scala:685:42] wire _atomics_legal_T_149 = _atomics_legal_T_148 \| _atomics_legal_T_131; // @[Parameters.scala:685:42] wire _atomics_legal_T_150 = _atomics_legal_T_149 \| _atomics_legal_T_136; // @[Parameters.scala:685:42] wire _atomics_legal_T_151 = _atomics_legal_T_150 \| _atomics_legal_T_141; // @[Parameters.scala:685:42] wire _atomics_legal_T_152 = _atomics_legal_T_151 \| _atomics_legal_T_146; // @[Parameters.scala:685:42] wire _atomics_legal_T_153 = _atomics_legal_T_152; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_161 = _atomics_legal_T_153; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_156 = {1'h0, _atomics_legal_T_155}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_157 = _atomics_legal_T_156 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_158 = _atomics_legal_T_157; // @[Parameters.scala:137:46] wire _atomics_legal_T_159 = _atomics_legal_T_158 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_2 = _atomics_legal_T_161; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [7:0] atomics_a_2_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_2 = _atomics_a_mask_sizeOH_T_6[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_7 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_2; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_8 = _atomics_a_mask_sizeOH_T_7[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_2 = {_atomics_a_mask_sizeOH_T_8[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_2 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_2 = atomics_a_mask_sizeOH_2[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_2 = atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_2 = ~atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_2 = atomics_a_mask_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_4 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 \| _atomics_a_mask_sub_sub_acc_T_4; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_5 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 \| _atomics_a_mask_sub_sub_acc_T_5; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_2 = atomics_a_mask_sizeOH_2[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_2 = ~atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_8 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_2 = atomics_a_mask_sub_sub_0_1_2 \| _atomics_a_mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_9 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_2 = atomics_a_mask_sub_sub_0_1_2 \| _atomics_a_mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_10 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_2_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_2 = atomics_a_mask_sub_sub_1_1_2 \| _atomics_a_mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_11 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_3_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_2 = atomics_a_mask_sub_sub_1_1_2 \| _atomics_a_mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_2 = atomics_a_mask_sizeOH_2[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_2 = ~atomics_a_mask_bit_2; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_16 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_16 = atomics_a_mask_size_2 & atomics_a_mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_16 = atomics_a_mask_sub_0_1_2 \| _atomics_a_mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_17 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_17 = atomics_a_mask_size_2 & atomics_a_mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_17 = atomics_a_mask_sub_0_1_2 \| _atomics_a_mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_18 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_18 = atomics_a_mask_size_2 & atomics_a_mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_18 = atomics_a_mask_sub_1_1_2 \| _atomics_a_mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_19 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_19 = atomics_a_mask_size_2 & atomics_a_mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_19 = atomics_a_mask_sub_1_1_2 \| _atomics_a_mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_20 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_20 = atomics_a_mask_size_2 & atomics_a_mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_20 = atomics_a_mask_sub_2_1_2 \| _atomics_a_mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_21 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_21 = atomics_a_mask_size_2 & atomics_a_mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_21 = atomics_a_mask_sub_2_1_2 \| _atomics_a_mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_22 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_22 = atomics_a_mask_size_2 & atomics_a_mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_22 = atomics_a_mask_sub_3_1_2 \| _atomics_a_mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_23 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_23 = atomics_a_mask_size_2 & atomics_a_mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_23 = atomics_a_mask_sub_3_1_2 \| _atomics_a_mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_2 = {atomics_a_mask_acc_17, atomics_a_mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_2 = {atomics_a_mask_acc_19, atomics_a_mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_2 = {atomics_a_mask_lo_hi_2, atomics_a_mask_lo_lo_2}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_2 = {atomics_a_mask_acc_21, atomics_a_mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_2 = {atomics_a_mask_acc_23, atomics_a_mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_2 = {atomics_a_mask_hi_hi_2, atomics_a_mask_hi_lo_2}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_2 = {atomics_a_mask_hi_2, atomics_a_mask_lo_2}; // @[Misc.scala:222:10] assign atomics_a_2_mask = _atomics_a_mask_T_2; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_167 = {1'h0, _atomics_legal_T_166}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_168 = _atomics_legal_T_167 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_169 = _atomics_legal_T_168; // @[Parameters.scala:137:46] wire _atomics_legal_T_170 = _atomics_legal_T_169 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_172 = {1'h0, _atomics_legal_T_171}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_173 = _atomics_legal_T_172 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_174 = _atomics_legal_T_173; // @[Parameters.scala:137:46] wire _atomics_legal_T_175 = _atomics_legal_T_174 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_177 = {1'h0, _atomics_legal_T_176}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_178 = _atomics_legal_T_177 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_179 = _atomics_legal_T_178; // @[Parameters.scala:137:46] wire _atomics_legal_T_180 = _atomics_legal_T_179 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_182 = {1'h0, _atomics_legal_T_181}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_183 = _atomics_legal_T_182 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_184 = _atomics_legal_T_183; // @[Parameters.scala:137:46] wire _atomics_legal_T_185 = _atomics_legal_T_184 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_187 = {1'h0, _atomics_legal_T_186}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_188 = _atomics_legal_T_187 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_189 = _atomics_legal_T_188; // @[Parameters.scala:137:46] wire _atomics_legal_T_190 = _atomics_legal_T_189 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_192 = {1'h0, _atomics_legal_T_191}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_193 = _atomics_legal_T_192 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_194 = _atomics_legal_T_193; // @[Parameters.scala:137:46] wire _atomics_legal_T_195 = _atomics_legal_T_194 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_197 = {1'h0, _atomics_legal_T_196}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_198 = _atomics_legal_T_197 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_199 = _atomics_legal_T_198; // @[Parameters.scala:137:46] wire _atomics_legal_T_200 = _atomics_legal_T_199 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_201 = _atomics_legal_T_170 \| _atomics_legal_T_175; // @[Parameters.scala:685:42] wire _atomics_legal_T_202 = _atomics_legal_T_201 \| _atomics_legal_T_180; // @[Parameters.scala:685:42] wire _atomics_legal_T_203 = _atomics_legal_T_202 \| _atomics_legal_T_185; // @[Parameters.scala:685:42] wire _atomics_legal_T_204 = _atomics_legal_T_203 \| _atomics_legal_T_190; // @[Parameters.scala:685:42] wire _atomics_legal_T_205 = _atomics_legal_T_204 \| _atomics_legal_T_195; // @[Parameters.scala:685:42] wire _atomics_legal_T_206 = _atomics_legal_T_205 \| _atomics_legal_T_200; // @[Parameters.scala:685:42] wire _atomics_legal_T_207 = _atomics_legal_T_206; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_215 = _atomics_legal_T_207; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_210 = {1'h0, _atomics_legal_T_209}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_211 = _atomics_legal_T_210 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_212 = _atomics_legal_T_211; // @[Parameters.scala:137:46] wire _atomics_legal_T_213 = _atomics_legal_T_212 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_3 = _atomics_legal_T_215; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [7:0] atomics_a_3_mask; // @[Edges.scala:534:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_3 = _atomics_a_mask_sizeOH_T_9[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_10 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_3; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_11 = _atomics_a_mask_sizeOH_T_10[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_3 = {_atomics_a_mask_sizeOH_T_11[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_3 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_3 = atomics_a_mask_sizeOH_3[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_3 = atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_3 = ~atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_3 = atomics_a_mask_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_6 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 \| _atomics_a_mask_sub_sub_acc_T_6; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_7 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 \| _atomics_a_mask_sub_sub_acc_T_7; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_3 = atomics_a_mask_sizeOH_3[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_3 = ~atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_12 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_3 = atomics_a_mask_sub_sub_0_1_3 \| _atomics_a_mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_13 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_3 = atomics_a_mask_sub_sub_0_1_3 \| _atomics_a_mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_14 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_2_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_3 = atomics_a_mask_sub_sub_1_1_3 \| _atomics_a_mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_15 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_3_2_3; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_3 = atomics_a_mask_sub_sub_1_1_3 \| _atomics_a_mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_3 = atomics_a_mask_sizeOH_3[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_3 = ~atomics_a_mask_bit_3; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_24 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_24 = atomics_a_mask_size_3 & atomics_a_mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_24 = atomics_a_mask_sub_0_1_3 \| _atomics_a_mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_25 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_25 = atomics_a_mask_size_3 & atomics_a_mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_25 = atomics_a_mask_sub_0_1_3 \| _atomics_a_mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_26 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_26 = atomics_a_mask_size_3 & atomics_a_mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_26 = atomics_a_mask_sub_1_1_3 \| _atomics_a_mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_27 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_27 = atomics_a_mask_size_3 & atomics_a_mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_27 = atomics_a_mask_sub_1_1_3 \| _atomics_a_mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_28 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_28 = atomics_a_mask_size_3 & atomics_a_mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_28 = atomics_a_mask_sub_2_1_3 \| _atomics_a_mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_29 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_29 = atomics_a_mask_size_3 & atomics_a_mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_29 = atomics_a_mask_sub_2_1_3 \| _atomics_a_mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_30 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_30 = atomics_a_mask_size_3 & atomics_a_mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_30 = atomics_a_mask_sub_3_1_3 \| _atomics_a_mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_31 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_31 = atomics_a_mask_size_3 & atomics_a_mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_31 = atomics_a_mask_sub_3_1_3 \| _atomics_a_mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_3 = {atomics_a_mask_acc_25, atomics_a_mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_3 = {atomics_a_mask_acc_27, atomics_a_mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_3 = {atomics_a_mask_lo_hi_3, atomics_a_mask_lo_lo_3}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_3 = {atomics_a_mask_acc_29, atomics_a_mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_3 = {atomics_a_mask_acc_31, atomics_a_mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_3 = {atomics_a_mask_hi_hi_3, atomics_a_mask_hi_lo_3}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_3 = {atomics_a_mask_hi_3, atomics_a_mask_lo_3}; // @[Misc.scala:222:10] assign atomics_a_3_mask = _atomics_a_mask_T_3; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_221 = {1'h0, _atomics_legal_T_220}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_222 = _atomics_legal_T_221 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_223 = _atomics_legal_T_222; // @[Parameters.scala:137:46] wire _atomics_legal_T_224 = _atomics_legal_T_223 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_226 = {1'h0, _atomics_legal_T_225}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_227 = _atomics_legal_T_226 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_228 = _atomics_legal_T_227; // @[Parameters.scala:137:46] wire _atomics_legal_T_229 = _atomics_legal_T_228 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_231 = {1'h0, _atomics_legal_T_230}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_232 = _atomics_legal_T_231 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_233 = _atomics_legal_T_232; // @[Parameters.scala:137:46] wire _atomics_legal_T_234 = _atomics_legal_T_233 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_236 = {1'h0, _atomics_legal_T_235}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_237 = _atomics_legal_T_236 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_238 = _atomics_legal_T_237; // @[Parameters.scala:137:46] wire _atomics_legal_T_239 = _atomics_legal_T_238 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_241 = {1'h0, _atomics_legal_T_240}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_242 = _atomics_legal_T_241 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_243 = _atomics_legal_T_242; // @[Parameters.scala:137:46] wire _atomics_legal_T_244 = _atomics_legal_T_243 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_246 = {1'h0, _atomics_legal_T_245}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_247 = _atomics_legal_T_246 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_248 = _atomics_legal_T_247; // @[Parameters.scala:137:46] wire _atomics_legal_T_249 = _atomics_legal_T_248 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_251 = {1'h0, _atomics_legal_T_250}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_252 = _atomics_legal_T_251 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_253 = _atomics_legal_T_252; // @[Parameters.scala:137:46] wire _atomics_legal_T_254 = _atomics_legal_T_253 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_255 = _atomics_legal_T_224 \| _atomics_legal_T_229; // @[Parameters.scala:685:42] wire _atomics_legal_T_256 = _atomics_legal_T_255 \| _atomics_legal_T_234; // @[Parameters.scala:685:42] wire _atomics_legal_T_257 = _atomics_legal_T_256 \| _atomics_legal_T_239; // @[Parameters.scala:685:42] wire _atomics_legal_T_258 = _atomics_legal_T_257 \| _atomics_legal_T_244; // @[Parameters.scala:685:42] wire _atomics_legal_T_259 = _atomics_legal_T_258 \| _atomics_legal_T_249; // @[Parameters.scala:685:42] wire _atomics_legal_T_260 = _atomics_legal_T_259 \| _atomics_legal_T_254; // @[Parameters.scala:685:42] wire _atomics_legal_T_261 = _atomics_legal_T_260; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_269 = _atomics_legal_T_261; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_264 = {1'h0, _atomics_legal_T_263}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_265 = _atomics_legal_T_264 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_266 = _atomics_legal_T_265; // @[Parameters.scala:137:46] wire _atomics_legal_T_267 = _atomics_legal_T_266 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_4 = _atomics_legal_T_269; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [7:0] atomics_a_4_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_4 = _atomics_a_mask_sizeOH_T_12[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_13 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_4; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_14 = _atomics_a_mask_sizeOH_T_13[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_4 = {_atomics_a_mask_sizeOH_T_14[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_4 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_4 = atomics_a_mask_sizeOH_4[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_4 = atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_4 = ~atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_4 = atomics_a_mask_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_8 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 \| _atomics_a_mask_sub_sub_acc_T_8; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_9 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 \| _atomics_a_mask_sub_sub_acc_T_9; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_4 = atomics_a_mask_sizeOH_4[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_4 = ~atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_16 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_4 = atomics_a_mask_sub_sub_0_1_4 \| _atomics_a_mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_17 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_4 = atomics_a_mask_sub_sub_0_1_4 \| _atomics_a_mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_18 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_2_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_4 = atomics_a_mask_sub_sub_1_1_4 \| _atomics_a_mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_19 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_3_2_4; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_4 = atomics_a_mask_sub_sub_1_1_4 \| _atomics_a_mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_4 = atomics_a_mask_sizeOH_4[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_4 = ~atomics_a_mask_bit_4; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_32 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_32 = atomics_a_mask_size_4 & atomics_a_mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_32 = atomics_a_mask_sub_0_1_4 \| _atomics_a_mask_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_33 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_33 = atomics_a_mask_size_4 & atomics_a_mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_33 = atomics_a_mask_sub_0_1_4 \| _atomics_a_mask_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_34 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_34 = atomics_a_mask_size_4 & atomics_a_mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_34 = atomics_a_mask_sub_1_1_4 \| _atomics_a_mask_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_35 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_35 = atomics_a_mask_size_4 & atomics_a_mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_35 = atomics_a_mask_sub_1_1_4 \| _atomics_a_mask_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_36 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_36 = atomics_a_mask_size_4 & atomics_a_mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_36 = atomics_a_mask_sub_2_1_4 \| _atomics_a_mask_acc_T_36; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_37 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_37 = atomics_a_mask_size_4 & atomics_a_mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_37 = atomics_a_mask_sub_2_1_4 \| _atomics_a_mask_acc_T_37; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_38 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_38 = atomics_a_mask_size_4 & atomics_a_mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_38 = atomics_a_mask_sub_3_1_4 \| _atomics_a_mask_acc_T_38; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_39 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_39 = atomics_a_mask_size_4 & atomics_a_mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_39 = atomics_a_mask_sub_3_1_4 \| _atomics_a_mask_acc_T_39; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_4 = {atomics_a_mask_acc_33, atomics_a_mask_acc_32}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_4 = {atomics_a_mask_acc_35, atomics_a_mask_acc_34}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_4 = {atomics_a_mask_lo_hi_4, atomics_a_mask_lo_lo_4}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_4 = {atomics_a_mask_acc_37, atomics_a_mask_acc_36}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_4 = {atomics_a_mask_acc_39, atomics_a_mask_acc_38}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_4 = {atomics_a_mask_hi_hi_4, atomics_a_mask_hi_lo_4}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_4 = {atomics_a_mask_hi_4, atomics_a_mask_lo_4}; // @[Misc.scala:222:10] assign atomics_a_4_mask = _atomics_a_mask_T_4; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_275 = {1'h0, _atomics_legal_T_274}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_276 = _atomics_legal_T_275 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_277 = _atomics_legal_T_276; // @[Parameters.scala:137:46] wire _atomics_legal_T_278 = _atomics_legal_T_277 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_280 = {1'h0, _atomics_legal_T_279}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_281 = _atomics_legal_T_280 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_282 = _atomics_legal_T_281; // @[Parameters.scala:137:46] wire _atomics_legal_T_283 = _atomics_legal_T_282 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_285 = {1'h0, _atomics_legal_T_284}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_286 = _atomics_legal_T_285 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_287 = _atomics_legal_T_286; // @[Parameters.scala:137:46] wire _atomics_legal_T_288 = _atomics_legal_T_287 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_290 = {1'h0, _atomics_legal_T_289}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_291 = _atomics_legal_T_290 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_292 = _atomics_legal_T_291; // @[Parameters.scala:137:46] wire _atomics_legal_T_293 = _atomics_legal_T_292 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_295 = {1'h0, _atomics_legal_T_294}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_296 = _atomics_legal_T_295 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_297 = _atomics_legal_T_296; // @[Parameters.scala:137:46] wire _atomics_legal_T_298 = _atomics_legal_T_297 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_300 = {1'h0, _atomics_legal_T_299}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_301 = _atomics_legal_T_300 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_302 = _atomics_legal_T_301; // @[Parameters.scala:137:46] wire _atomics_legal_T_303 = _atomics_legal_T_302 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_305 = {1'h0, _atomics_legal_T_304}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_306 = _atomics_legal_T_305 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_307 = _atomics_legal_T_306; // @[Parameters.scala:137:46] wire _atomics_legal_T_308 = _atomics_legal_T_307 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_309 = _atomics_legal_T_278 \| _atomics_legal_T_283; // @[Parameters.scala:685:42] wire _atomics_legal_T_310 = _atomics_legal_T_309 \| _atomics_legal_T_288; // @[Parameters.scala:685:42] wire _atomics_legal_T_311 = _atomics_legal_T_310 \| _atomics_legal_T_293; // @[Parameters.scala:685:42] wire _atomics_legal_T_312 = _atomics_legal_T_311 \| _atomics_legal_T_298; // @[Parameters.scala:685:42] wire _atomics_legal_T_313 = _atomics_legal_T_312 \| _atomics_legal_T_303; // @[Parameters.scala:685:42] wire _atomics_legal_T_314 = _atomics_legal_T_313 \| _atomics_legal_T_308; // @[Parameters.scala:685:42] wire _atomics_legal_T_315 = _atomics_legal_T_314; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_323 = _atomics_legal_T_315; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_318 = {1'h0, _atomics_legal_T_317}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_319 = _atomics_legal_T_318 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_320 = _atomics_legal_T_319; // @[Parameters.scala:137:46] wire _atomics_legal_T_321 = _atomics_legal_T_320 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_5 = _atomics_legal_T_323; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [7:0] atomics_a_5_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_5 = _atomics_a_mask_sizeOH_T_15[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_16 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_5; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_17 = _atomics_a_mask_sizeOH_T_16[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_5 = {_atomics_a_mask_sizeOH_T_17[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_5 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_5 = atomics_a_mask_sizeOH_5[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_5 = atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_5 = ~atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_5 = atomics_a_mask_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_10 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 \| _atomics_a_mask_sub_sub_acc_T_10; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_11 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 \| _atomics_a_mask_sub_sub_acc_T_11; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_5 = atomics_a_mask_sizeOH_5[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_5 = ~atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_20 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_5 = atomics_a_mask_sub_sub_0_1_5 \| _atomics_a_mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_21 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_5 = atomics_a_mask_sub_sub_0_1_5 \| _atomics_a_mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_22 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_2_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_5 = atomics_a_mask_sub_sub_1_1_5 \| _atomics_a_mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_23 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_3_2_5; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_5 = atomics_a_mask_sub_sub_1_1_5 \| _atomics_a_mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_5 = atomics_a_mask_sizeOH_5[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_5 = ~atomics_a_mask_bit_5; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_40 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_40 = atomics_a_mask_size_5 & atomics_a_mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_40 = atomics_a_mask_sub_0_1_5 \| _atomics_a_mask_acc_T_40; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_41 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_41 = atomics_a_mask_size_5 & atomics_a_mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_41 = atomics_a_mask_sub_0_1_5 \| _atomics_a_mask_acc_T_41; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_42 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_42 = atomics_a_mask_size_5 & atomics_a_mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_42 = atomics_a_mask_sub_1_1_5 \| _atomics_a_mask_acc_T_42; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_43 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_43 = atomics_a_mask_size_5 & atomics_a_mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_43 = atomics_a_mask_sub_1_1_5 \| _atomics_a_mask_acc_T_43; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_44 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_44 = atomics_a_mask_size_5 & atomics_a_mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_44 = atomics_a_mask_sub_2_1_5 \| _atomics_a_mask_acc_T_44; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_45 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_45 = atomics_a_mask_size_5 & atomics_a_mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_45 = atomics_a_mask_sub_2_1_5 \| _atomics_a_mask_acc_T_45; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_46 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_46 = atomics_a_mask_size_5 & atomics_a_mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_46 = atomics_a_mask_sub_3_1_5 \| _atomics_a_mask_acc_T_46; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_47 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_47 = atomics_a_mask_size_5 & atomics_a_mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_47 = atomics_a_mask_sub_3_1_5 \| _atomics_a_mask_acc_T_47; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_5 = {atomics_a_mask_acc_41, atomics_a_mask_acc_40}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_5 = {atomics_a_mask_acc_43, atomics_a_mask_acc_42}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_5 = {atomics_a_mask_lo_hi_5, atomics_a_mask_lo_lo_5}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_5 = {atomics_a_mask_acc_45, atomics_a_mask_acc_44}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_5 = {atomics_a_mask_acc_47, atomics_a_mask_acc_46}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_5 = {atomics_a_mask_hi_hi_5, atomics_a_mask_hi_lo_5}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_5 = {atomics_a_mask_hi_5, atomics_a_mask_lo_5}; // @[Misc.scala:222:10] assign atomics_a_5_mask = _atomics_a_mask_T_5; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_329 = {1'h0, _atomics_legal_T_328}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_330 = _atomics_legal_T_329 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_331 = _atomics_legal_T_330; // @[Parameters.scala:137:46] wire _atomics_legal_T_332 = _atomics_legal_T_331 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_334 = {1'h0, _atomics_legal_T_333}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_335 = _atomics_legal_T_334 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_336 = _atomics_legal_T_335; // @[Parameters.scala:137:46] wire _atomics_legal_T_337 = _atomics_legal_T_336 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_339 = {1'h0, _atomics_legal_T_338}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_340 = _atomics_legal_T_339 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_341 = _atomics_legal_T_340; // @[Parameters.scala:137:46] wire _atomics_legal_T_342 = _atomics_legal_T_341 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_344 = {1'h0, _atomics_legal_T_343}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_345 = _atomics_legal_T_344 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_346 = _atomics_legal_T_345; // @[Parameters.scala:137:46] wire _atomics_legal_T_347 = _atomics_legal_T_346 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_349 = {1'h0, _atomics_legal_T_348}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_350 = _atomics_legal_T_349 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_351 = _atomics_legal_T_350; // @[Parameters.scala:137:46] wire _atomics_legal_T_352 = _atomics_legal_T_351 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_354 = {1'h0, _atomics_legal_T_353}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_355 = _atomics_legal_T_354 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_356 = _atomics_legal_T_355; // @[Parameters.scala:137:46] wire _atomics_legal_T_357 = _atomics_legal_T_356 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_359 = {1'h0, _atomics_legal_T_358}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_360 = _atomics_legal_T_359 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_361 = _atomics_legal_T_360; // @[Parameters.scala:137:46] wire _atomics_legal_T_362 = _atomics_legal_T_361 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_363 = _atomics_legal_T_332 \| _atomics_legal_T_337; // @[Parameters.scala:685:42] wire _atomics_legal_T_364 = _atomics_legal_T_363 \| _atomics_legal_T_342; // @[Parameters.scala:685:42] wire _atomics_legal_T_365 = _atomics_legal_T_364 \| _atomics_legal_T_347; // @[Parameters.scala:685:42] wire _atomics_legal_T_366 = _atomics_legal_T_365 \| _atomics_legal_T_352; // @[Parameters.scala:685:42] wire _atomics_legal_T_367 = _atomics_legal_T_366 \| _atomics_legal_T_357; // @[Parameters.scala:685:42] wire _atomics_legal_T_368 = _atomics_legal_T_367 \| _atomics_legal_T_362; // @[Parameters.scala:685:42] wire _atomics_legal_T_369 = _atomics_legal_T_368; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_377 = _atomics_legal_T_369; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_372 = {1'h0, _atomics_legal_T_371}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_373 = _atomics_legal_T_372 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_374 = _atomics_legal_T_373; // @[Parameters.scala:137:46] wire _atomics_legal_T_375 = _atomics_legal_T_374 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_6 = _atomics_legal_T_377; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [7:0] atomics_a_6_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_6 = _atomics_a_mask_sizeOH_T_18[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_19 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_6; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_20 = _atomics_a_mask_sizeOH_T_19[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_6 = {_atomics_a_mask_sizeOH_T_20[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_6 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_6 = atomics_a_mask_sizeOH_6[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_6 = atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_6 = ~atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_6 = atomics_a_mask_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_12 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 \| _atomics_a_mask_sub_sub_acc_T_12; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_13 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 \| _atomics_a_mask_sub_sub_acc_T_13; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_6 = atomics_a_mask_sizeOH_6[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_6 = ~atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_24 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_6 = atomics_a_mask_sub_sub_0_1_6 \| _atomics_a_mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_25 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_6 = atomics_a_mask_sub_sub_0_1_6 \| _atomics_a_mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_26 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_2_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_6 = atomics_a_mask_sub_sub_1_1_6 \| _atomics_a_mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_27 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_3_2_6; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_6 = atomics_a_mask_sub_sub_1_1_6 \| _atomics_a_mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_6 = atomics_a_mask_sizeOH_6[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_6 = ~atomics_a_mask_bit_6; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_48 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_48 = atomics_a_mask_size_6 & atomics_a_mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_48 = atomics_a_mask_sub_0_1_6 \| _atomics_a_mask_acc_T_48; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_49 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_49 = atomics_a_mask_size_6 & atomics_a_mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_49 = atomics_a_mask_sub_0_1_6 \| _atomics_a_mask_acc_T_49; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_50 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_50 = atomics_a_mask_size_6 & atomics_a_mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_50 = atomics_a_mask_sub_1_1_6 \| _atomics_a_mask_acc_T_50; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_51 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_51 = atomics_a_mask_size_6 & atomics_a_mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_51 = atomics_a_mask_sub_1_1_6 \| _atomics_a_mask_acc_T_51; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_52 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_52 = atomics_a_mask_size_6 & atomics_a_mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_52 = atomics_a_mask_sub_2_1_6 \| _atomics_a_mask_acc_T_52; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_53 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_53 = atomics_a_mask_size_6 & atomics_a_mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_53 = atomics_a_mask_sub_2_1_6 \| _atomics_a_mask_acc_T_53; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_54 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_54 = atomics_a_mask_size_6 & atomics_a_mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_54 = atomics_a_mask_sub_3_1_6 \| _atomics_a_mask_acc_T_54; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_55 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_55 = atomics_a_mask_size_6 & atomics_a_mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_55 = atomics_a_mask_sub_3_1_6 \| _atomics_a_mask_acc_T_55; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_6 = {atomics_a_mask_acc_49, atomics_a_mask_acc_48}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_6 = {atomics_a_mask_acc_51, atomics_a_mask_acc_50}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_6 = {atomics_a_mask_lo_hi_6, atomics_a_mask_lo_lo_6}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_6 = {atomics_a_mask_acc_53, atomics_a_mask_acc_52}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_6 = {atomics_a_mask_acc_55, atomics_a_mask_acc_54}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_6 = {atomics_a_mask_hi_hi_6, atomics_a_mask_hi_lo_6}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_6 = {atomics_a_mask_hi_6, atomics_a_mask_lo_6}; // @[Misc.scala:222:10] assign atomics_a_6_mask = _atomics_a_mask_T_6; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_383 = {1'h0, _atomics_legal_T_382}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_384 = _atomics_legal_T_383 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_385 = _atomics_legal_T_384; // @[Parameters.scala:137:46] wire _atomics_legal_T_386 = _atomics_legal_T_385 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_388 = {1'h0, _atomics_legal_T_387}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_389 = _atomics_legal_T_388 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_390 = _atomics_legal_T_389; // @[Parameters.scala:137:46] wire _atomics_legal_T_391 = _atomics_legal_T_390 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_393 = {1'h0, _atomics_legal_T_392}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_394 = _atomics_legal_T_393 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_395 = _atomics_legal_T_394; // @[Parameters.scala:137:46] wire _atomics_legal_T_396 = _atomics_legal_T_395 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_398 = {1'h0, _atomics_legal_T_397}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_399 = _atomics_legal_T_398 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_400 = _atomics_legal_T_399; // @[Parameters.scala:137:46] wire _atomics_legal_T_401 = _atomics_legal_T_400 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_403 = {1'h0, _atomics_legal_T_402}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_404 = _atomics_legal_T_403 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_405 = _atomics_legal_T_404; // @[Parameters.scala:137:46] wire _atomics_legal_T_406 = _atomics_legal_T_405 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_408 = {1'h0, _atomics_legal_T_407}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_409 = _atomics_legal_T_408 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_410 = _atomics_legal_T_409; // @[Parameters.scala:137:46] wire _atomics_legal_T_411 = _atomics_legal_T_410 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_413 = {1'h0, _atomics_legal_T_412}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_414 = _atomics_legal_T_413 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_415 = _atomics_legal_T_414; // @[Parameters.scala:137:46] wire _atomics_legal_T_416 = _atomics_legal_T_415 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_417 = _atomics_legal_T_386 \| _atomics_legal_T_391; // @[Parameters.scala:685:42] wire _atomics_legal_T_418 = _atomics_legal_T_417 \| _atomics_legal_T_396; // @[Parameters.scala:685:42] wire _atomics_legal_T_419 = _atomics_legal_T_418 \| _atomics_legal_T_401; // @[Parameters.scala:685:42] wire _atomics_legal_T_420 = _atomics_legal_T_419 \| _atomics_legal_T_406; // @[Parameters.scala:685:42] wire _atomics_legal_T_421 = _atomics_legal_T_420 \| _atomics_legal_T_411; // @[Parameters.scala:685:42] wire _atomics_legal_T_422 = _atomics_legal_T_421 \| _atomics_legal_T_416; // @[Parameters.scala:685:42] wire _atomics_legal_T_423 = _atomics_legal_T_422; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_431 = _atomics_legal_T_423; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_426 = {1'h0, _atomics_legal_T_425}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_427 = _atomics_legal_T_426 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_428 = _atomics_legal_T_427; // @[Parameters.scala:137:46] wire _atomics_legal_T_429 = _atomics_legal_T_428 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_7 = _atomics_legal_T_431; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [7:0] atomics_a_7_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_7 = _atomics_a_mask_sizeOH_T_21[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_22 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_7; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_23 = _atomics_a_mask_sizeOH_T_22[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_7 = {_atomics_a_mask_sizeOH_T_23[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_7 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_7 = atomics_a_mask_sizeOH_7[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_7 = atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_7 = ~atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_7 = atomics_a_mask_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_14 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 \| _atomics_a_mask_sub_sub_acc_T_14; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_15 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 \| _atomics_a_mask_sub_sub_acc_T_15; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_7 = atomics_a_mask_sizeOH_7[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_7 = ~atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_28 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_7 = atomics_a_mask_sub_sub_0_1_7 \| _atomics_a_mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_29 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_7 = atomics_a_mask_sub_sub_0_1_7 \| _atomics_a_mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_30 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_2_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_7 = atomics_a_mask_sub_sub_1_1_7 \| _atomics_a_mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_31 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_3_2_7; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_7 = atomics_a_mask_sub_sub_1_1_7 \| _atomics_a_mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_7 = atomics_a_mask_sizeOH_7[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_7 = ~atomics_a_mask_bit_7; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_56 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_56 = atomics_a_mask_size_7 & atomics_a_mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_56 = atomics_a_mask_sub_0_1_7 \| _atomics_a_mask_acc_T_56; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_57 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_57 = atomics_a_mask_size_7 & atomics_a_mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_57 = atomics_a_mask_sub_0_1_7 \| _atomics_a_mask_acc_T_57; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_58 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_58 = atomics_a_mask_size_7 & atomics_a_mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_58 = atomics_a_mask_sub_1_1_7 \| _atomics_a_mask_acc_T_58; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_59 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_59 = atomics_a_mask_size_7 & atomics_a_mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_59 = atomics_a_mask_sub_1_1_7 \| _atomics_a_mask_acc_T_59; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_60 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_60 = atomics_a_mask_size_7 & atomics_a_mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_60 = atomics_a_mask_sub_2_1_7 \| _atomics_a_mask_acc_T_60; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_61 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_61 = atomics_a_mask_size_7 & atomics_a_mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_61 = atomics_a_mask_sub_2_1_7 \| _atomics_a_mask_acc_T_61; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_62 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_62 = atomics_a_mask_size_7 & atomics_a_mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_62 = atomics_a_mask_sub_3_1_7 \| _atomics_a_mask_acc_T_62; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_63 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_63 = atomics_a_mask_size_7 & atomics_a_mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_63 = atomics_a_mask_sub_3_1_7 \| _atomics_a_mask_acc_T_63; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_7 = {atomics_a_mask_acc_57, atomics_a_mask_acc_56}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_7 = {atomics_a_mask_acc_59, atomics_a_mask_acc_58}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_7 = {atomics_a_mask_lo_hi_7, atomics_a_mask_lo_lo_7}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_7 = {atomics_a_mask_acc_61, atomics_a_mask_acc_60}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_7 = {atomics_a_mask_acc_63, atomics_a_mask_acc_62}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_7 = {atomics_a_mask_hi_hi_7, atomics_a_mask_hi_lo_7}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_7 = {atomics_a_mask_hi_7, atomics_a_mask_lo_7}; // @[Misc.scala:222:10] assign atomics_a_7_mask = _atomics_a_mask_T_7; // @[Misc.scala:222:10] wire [40:0] _atomics_legal_T_437 = {1'h0, _atomics_legal_T_436}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_438 = _atomics_legal_T_437 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_439 = _atomics_legal_T_438; // @[Parameters.scala:137:46] wire _atomics_legal_T_440 = _atomics_legal_T_439 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_442 = {1'h0, _atomics_legal_T_441}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_443 = _atomics_legal_T_442 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_444 = _atomics_legal_T_443; // @[Parameters.scala:137:46] wire _atomics_legal_T_445 = _atomics_legal_T_444 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_447 = {1'h0, _atomics_legal_T_446}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_448 = _atomics_legal_T_447 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_449 = _atomics_legal_T_448; // @[Parameters.scala:137:46] wire _atomics_legal_T_450 = _atomics_legal_T_449 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_452 = {1'h0, _atomics_legal_T_451}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_453 = _atomics_legal_T_452 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_454 = _atomics_legal_T_453; // @[Parameters.scala:137:46] wire _atomics_legal_T_455 = _atomics_legal_T_454 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_457 = {1'h0, _atomics_legal_T_456}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_458 = _atomics_legal_T_457 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_459 = _atomics_legal_T_458; // @[Parameters.scala:137:46] wire _atomics_legal_T_460 = _atomics_legal_T_459 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_462 = {1'h0, _atomics_legal_T_461}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_463 = _atomics_legal_T_462 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_464 = _atomics_legal_T_463; // @[Parameters.scala:137:46] wire _atomics_legal_T_465 = _atomics_legal_T_464 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _atomics_legal_T_467 = {1'h0, _atomics_legal_T_466}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_468 = _atomics_legal_T_467 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_469 = _atomics_legal_T_468; // @[Parameters.scala:137:46] wire _atomics_legal_T_470 = _atomics_legal_T_469 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _atomics_legal_T_471 = _atomics_legal_T_440 \| _atomics_legal_T_445; // @[Parameters.scala:685:42] wire _atomics_legal_T_472 = _atomics_legal_T_471 \| _atomics_legal_T_450; // @[Parameters.scala:685:42] wire _atomics_legal_T_473 = _atomics_legal_T_472 \| _atomics_legal_T_455; // @[Parameters.scala:685:42] wire _atomics_legal_T_474 = _atomics_legal_T_473 \| _atomics_legal_T_460; // @[Parameters.scala:685:42] wire _atomics_legal_T_475 = _atomics_legal_T_474 \| _atomics_legal_T_465; // @[Parameters.scala:685:42] wire _atomics_legal_T_476 = _atomics_legal_T_475 \| _atomics_legal_T_470; // @[Parameters.scala:685:42] wire _atomics_legal_T_477 = _atomics_legal_T_476; // @[Parameters.scala:684:54, :685:42] wire _atomics_legal_T_485 = _atomics_legal_T_477; // @[Parameters.scala:684:54, :686:26] wire [40:0] _atomics_legal_T_480 = {1'h0, _atomics_legal_T_479}; // @[Parameters.scala:137:{31,41}] wire [40:0] _atomics_legal_T_481 = _atomics_legal_T_480 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _atomics_legal_T_482 = _atomics_legal_T_481; // @[Parameters.scala:137:46] wire _atomics_legal_T_483 = _atomics_legal_T_482 == 41'h0; // @[Parameters.scala:137:{46,59}] wire atomics_legal_8 = _atomics_legal_T_485; // @[Parameters.scala:686:26] wire [7:0] _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire [7:0] atomics_a_8_mask; // @[Edges.scala:517:17] wire [1:0] atomics_a_mask_sizeOH_shiftAmount_8 = _atomics_a_mask_sizeOH_T_24[1:0]; // @[OneHot.scala:64:49] wire [3:0] _atomics_a_mask_sizeOH_T_25 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_8; // @[OneHot.scala:64:49, :65:12] wire [2:0] _atomics_a_mask_sizeOH_T_26 = _atomics_a_mask_sizeOH_T_25[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] atomics_a_mask_sizeOH_8 = {_atomics_a_mask_sizeOH_T_26[2:1], 1'h1}; // @[OneHot.scala:65:27] wire atomics_a_mask_sub_sub_sub_0_1_8 = &s2_req_size; // @[Misc.scala:206:21] wire atomics_a_mask_sub_sub_size_8 = atomics_a_mask_sizeOH_8[2]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_sub_1_2_8 = atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire atomics_a_mask_sub_sub_nbit_8 = ~atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_sub_0_2_8 = atomics_a_mask_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_sub_acc_T_16 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_0_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 \| _atomics_a_mask_sub_sub_acc_T_16; // @[Misc.scala:206:21, :215:{29,38}] wire _atomics_a_mask_sub_sub_acc_T_17 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_sub_1_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 \| _atomics_a_mask_sub_sub_acc_T_17; // @[Misc.scala:206:21, :215:{29,38}] wire atomics_a_mask_sub_size_8 = atomics_a_mask_sizeOH_8[1]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_sub_nbit_8 = ~atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_sub_0_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_32 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_0_1_8 = atomics_a_mask_sub_sub_0_1_8 \| _atomics_a_mask_sub_acc_T_32; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_1_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_33 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_1_1_8 = atomics_a_mask_sub_sub_0_1_8 \| _atomics_a_mask_sub_acc_T_33; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_2_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_sub_acc_T_34 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_2_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_2_1_8 = atomics_a_mask_sub_sub_1_1_8 \| _atomics_a_mask_sub_acc_T_34; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_sub_3_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_sub_acc_T_35 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_3_2_8; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_sub_3_1_8 = atomics_a_mask_sub_sub_1_1_8 \| _atomics_a_mask_sub_acc_T_35; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_size_8 = atomics_a_mask_sizeOH_8[0]; // @[Misc.scala:202:81, :209:26] wire atomics_a_mask_nbit_8 = ~atomics_a_mask_bit_8; // @[Misc.scala:210:26, :211:20] wire atomics_a_mask_eq_64 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_64 = atomics_a_mask_size_8 & atomics_a_mask_eq_64; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_64 = atomics_a_mask_sub_0_1_8 \| _atomics_a_mask_acc_T_64; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_65 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_65 = atomics_a_mask_size_8 & atomics_a_mask_eq_65; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_65 = atomics_a_mask_sub_0_1_8 \| _atomics_a_mask_acc_T_65; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_66 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_66 = atomics_a_mask_size_8 & atomics_a_mask_eq_66; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_66 = atomics_a_mask_sub_1_1_8 \| _atomics_a_mask_acc_T_66; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_67 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_67 = atomics_a_mask_size_8 & atomics_a_mask_eq_67; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_67 = atomics_a_mask_sub_1_1_8 \| _atomics_a_mask_acc_T_67; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_68 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_68 = atomics_a_mask_size_8 & atomics_a_mask_eq_68; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_68 = atomics_a_mask_sub_2_1_8 \| _atomics_a_mask_acc_T_68; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_69 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_69 = atomics_a_mask_size_8 & atomics_a_mask_eq_69; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_69 = atomics_a_mask_sub_2_1_8 \| _atomics_a_mask_acc_T_69; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_70 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27] wire _atomics_a_mask_acc_T_70 = atomics_a_mask_size_8 & atomics_a_mask_eq_70; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_70 = atomics_a_mask_sub_3_1_8 \| _atomics_a_mask_acc_T_70; // @[Misc.scala:215:{29,38}] wire atomics_a_mask_eq_71 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27] wire _atomics_a_mask_acc_T_71 = atomics_a_mask_size_8 & atomics_a_mask_eq_71; // @[Misc.scala:209:26, :214:27, :215:38] wire atomics_a_mask_acc_71 = atomics_a_mask_sub_3_1_8 \| _atomics_a_mask_acc_T_71; // @[Misc.scala:215:{29,38}] wire [1:0] atomics_a_mask_lo_lo_8 = {atomics_a_mask_acc_65, atomics_a_mask_acc_64}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_lo_hi_8 = {atomics_a_mask_acc_67, atomics_a_mask_acc_66}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_lo_8 = {atomics_a_mask_lo_hi_8, atomics_a_mask_lo_lo_8}; // @[Misc.scala:222:10] wire [1:0] atomics_a_mask_hi_lo_8 = {atomics_a_mask_acc_69, atomics_a_mask_acc_68}; // @[Misc.scala:215:29, :222:10] wire [1:0] atomics_a_mask_hi_hi_8 = {atomics_a_mask_acc_71, atomics_a_mask_acc_70}; // @[Misc.scala:215:29, :222:10] wire [3:0] atomics_a_mask_hi_8 = {atomics_a_mask_hi_hi_8, atomics_a_mask_hi_lo_8}; // @[Misc.scala:222:10] assign _atomics_a_mask_T_8 = {atomics_a_mask_hi_8, atomics_a_mask_lo_8}; // @[Misc.scala:222:10] assign atomics_a_8_mask = _atomics_a_mask_T_8; // @[Misc.scala:222:10] wire [2:0] _GEN_112 = _atomics_T ? 3'h3 : 3'h0; // @[DCache.scala:587:81] wire [2:0] _atomics_T_1_opcode; // @[DCache.scala:587:81] assign _atomics_T_1_opcode = _GEN_112; // @[DCache.scala:587:81] wire [2:0] _atomics_T_1_param; // @[DCache.scala:587:81] assign _atomics_T_1_param = _GEN_112; // @[DCache.scala:587:81] wire [3:0] _atomics_T_1_size = _atomics_T ? atomics_a_size : 4'h0; // @[Edges.scala:534:17] wire _atomics_T_1_source = _atomics_T & atomics_a_source; // @[Edges.scala:534:17] wire [31:0] _atomics_T_1_address = _atomics_T ? atomics_a_address : 32'h0; // @[Edges.scala:534:17] wire [7:0] _atomics_T_1_mask = _atomics_T ? atomics_a_mask : 8'h0; // @[Edges.scala:534:17] wire [63:0] _atomics_T_1_data = _atomics_T ? atomics_a_data : 64'h0; // @[Edges.scala:534:17] wire [2:0] _atomics_T_3_opcode = _atomics_T_2 ? 3'h3 : _atomics_T_1_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_3_param = _atomics_T_2 ? 3'h0 : _atomics_T_1_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_3_size = _atomics_T_2 ? atomics_a_1_size : _atomics_T_1_size; // @[Edges.scala:534:17] wire _atomics_T_3_source = _atomics_T_2 ? atomics_a_1_source : _atomics_T_1_source; // @[Edges.scala:534:17] wire [31:0] _atomics_T_3_address = _atomics_T_2 ? atomics_a_1_address : _atomics_T_1_address; // @[Edges.scala:534:17] wire [7:0] _atomics_T_3_mask = _atomics_T_2 ? atomics_a_1_mask : _atomics_T_1_mask; // @[Edges.scala:534:17] wire [63:0] _atomics_T_3_data = _atomics_T_2 ? atomics_a_1_data : _atomics_T_1_data; // @[Edges.scala:534:17] wire [2:0] _atomics_T_5_opcode = _atomics_T_4 ? 3'h3 : _atomics_T_3_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_5_param = _atomics_T_4 ? 3'h1 : _atomics_T_3_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_5_size = _atomics_T_4 ? atomics_a_2_size : _atomics_T_3_size; // @[Edges.scala:534:17] wire _atomics_T_5_source = _atomics_T_4 ? atomics_a_2_source : _atomics_T_3_source; // @[Edges.scala:534:17] wire [31:0] _atomics_T_5_address = _atomics_T_4 ? atomics_a_2_address : _atomics_T_3_address; // @[Edges.scala:534:17] wire [7:0] _atomics_T_5_mask = _atomics_T_4 ? atomics_a_2_mask : _atomics_T_3_mask; // @[Edges.scala:534:17] wire [63:0] _atomics_T_5_data = _atomics_T_4 ? atomics_a_2_data : _atomics_T_3_data; // @[Edges.scala:534:17] wire [2:0] _atomics_T_7_opcode = _atomics_T_6 ? 3'h3 : _atomics_T_5_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_7_param = _atomics_T_6 ? 3'h2 : _atomics_T_5_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_7_size = _atomics_T_6 ? atomics_a_3_size : _atomics_T_5_size; // @[Edges.scala:534:17] wire _atomics_T_7_source = _atomics_T_6 ? atomics_a_3_source : _atomics_T_5_source; // @[Edges.scala:534:17] wire [31:0] _atomics_T_7_address = _atomics_T_6 ? atomics_a_3_address : _atomics_T_5_address; // @[Edges.scala:534:17] wire [7:0] _atomics_T_7_mask = _atomics_T_6 ? atomics_a_3_mask : _atomics_T_5_mask; // @[Edges.scala:534:17] wire [63:0] _atomics_T_7_data = _atomics_T_6 ? atomics_a_3_data : _atomics_T_5_data; // @[Edges.scala:534:17] wire [2:0] _atomics_T_9_opcode = _atomics_T_8 ? 3'h2 : _atomics_T_7_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_9_param = _atomics_T_8 ? 3'h4 : _atomics_T_7_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_9_size = _atomics_T_8 ? atomics_a_4_size : _atomics_T_7_size; // @[Edges.scala:517:17] wire _atomics_T_9_source = _atomics_T_8 ? atomics_a_4_source : _atomics_T_7_source; // @[Edges.scala:517:17] wire [31:0] _atomics_T_9_address = _atomics_T_8 ? atomics_a_4_address : _atomics_T_7_address; // @[Edges.scala:517:17] wire [7:0] _atomics_T_9_mask = _atomics_T_8 ? atomics_a_4_mask : _atomics_T_7_mask; // @[Edges.scala:517:17] wire [63:0] _atomics_T_9_data = _atomics_T_8 ? atomics_a_4_data : _atomics_T_7_data; // @[Edges.scala:517:17] wire [2:0] _atomics_T_11_opcode = _atomics_T_10 ? 3'h2 : _atomics_T_9_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_11_param = _atomics_T_10 ? 3'h0 : _atomics_T_9_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_11_size = _atomics_T_10 ? atomics_a_5_size : _atomics_T_9_size; // @[Edges.scala:517:17] wire _atomics_T_11_source = _atomics_T_10 ? atomics_a_5_source : _atomics_T_9_source; // @[Edges.scala:517:17] wire [31:0] _atomics_T_11_address = _atomics_T_10 ? atomics_a_5_address : _atomics_T_9_address; // @[Edges.scala:517:17] wire [7:0] _atomics_T_11_mask = _atomics_T_10 ? atomics_a_5_mask : _atomics_T_9_mask; // @[Edges.scala:517:17] wire [63:0] _atomics_T_11_data = _atomics_T_10 ? atomics_a_5_data : _atomics_T_9_data; // @[Edges.scala:517:17] wire [2:0] _atomics_T_13_opcode = _atomics_T_12 ? 3'h2 : _atomics_T_11_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_13_param = _atomics_T_12 ? 3'h1 : _atomics_T_11_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_13_size = _atomics_T_12 ? atomics_a_6_size : _atomics_T_11_size; // @[Edges.scala:517:17] wire _atomics_T_13_source = _atomics_T_12 ? atomics_a_6_source : _atomics_T_11_source; // @[Edges.scala:517:17] wire [31:0] _atomics_T_13_address = _atomics_T_12 ? atomics_a_6_address : _atomics_T_11_address; // @[Edges.scala:517:17] wire [7:0] _atomics_T_13_mask = _atomics_T_12 ? atomics_a_6_mask : _atomics_T_11_mask; // @[Edges.scala:517:17] wire [63:0] _atomics_T_13_data = _atomics_T_12 ? atomics_a_6_data : _atomics_T_11_data; // @[Edges.scala:517:17] wire [2:0] _atomics_T_15_opcode = _atomics_T_14 ? 3'h2 : _atomics_T_13_opcode; // @[DCache.scala:587:81] wire [2:0] _atomics_T_15_param = _atomics_T_14 ? 3'h2 : _atomics_T_13_param; // @[DCache.scala:587:81] wire [3:0] _atomics_T_15_size = _atomics_T_14 ? atomics_a_7_size : _atomics_T_13_size; // @[Edges.scala:517:17] wire _atomics_T_15_source = _atomics_T_14 ? atomics_a_7_source : _atomics_T_13_source; // @[Edges.scala:517:17] wire [31:0] _atomics_T_15_address = _atomics_T_14 ? atomics_a_7_address : _atomics_T_13_address; // @[Edges.scala:517:17] wire [7:0] _atomics_T_15_mask = _atomics_T_14 ? atomics_a_7_mask : _atomics_T_13_mask; // @[Edges.scala:517:17] wire [63:0] _atomics_T_15_data = _atomics_T_14 ? atomics_a_7_data : _atomics_T_13_data; // @[Edges.scala:517:17] wire [2:0] atomics_opcode = _atomics_T_16 ? 3'h2 : _atomics_T_15_opcode; // @[DCache.scala:587:81] wire [2:0] atomics_param = _atomics_T_16 ? 3'h3 : _atomics_T_15_param; // @[DCache.scala:587:81] wire [3:0] atomics_size = _atomics_T_16 ? atomics_a_8_size : _atomics_T_15_size; // @[Edges.scala:517:17] wire atomics_source = _atomics_T_16 ? atomics_a_8_source : _atomics_T_15_source; // @[Edges.scala:517:17] wire [31:0] atomics_address = _atomics_T_16 ? atomics_a_8_address : _atomics_T_15_address; // @[Edges.scala:517:17] wire [7:0] atomics_mask = _atomics_T_16 ? atomics_a_8_mask : _atomics_T_15_mask; // @[Edges.scala:517:17] wire [63:0] atomics_data = _atomics_T_16 ? atomics_a_8_data : _atomics_T_15_data; // @[Edges.scala:517:17] wire [39:0] _tl_out_a_valid_T_1 = {s2_req_addr[39:32], s2_req_addr[31:0] ^ release_ack_addr}; // @[DCache.scala:227:29, :339:19, :606:43] wire [14:0] _tl_out_a_valid_T_2 = _tl_out_a_valid_T_1[20:6]; // @[DCache.scala:606:{43,62}] wire _tl_out_a_valid_T_3 = _tl_out_a_valid_T_2 == 15'h0; // @[DCache.scala:582:29, :606:{62,118}] wire _tl_out_a_valid_T_4 = release_ack_wait & _tl_out_a_valid_T_3; // @[DCache.scala:226:33, :606:{27,118}] wire _tl_out_a_valid_T_5 = ~_tl_out_a_valid_T_4; // @[DCache.scala:606:{8,27}] wire _tl_out_a_valid_T_6 = s2_valid_cached_miss & _tl_out_a_valid_T_5; // @[DCache.scala:425:60, :605:29, :606:8] wire _tl_out_a_valid_T_7 = ~release_ack_wait; // @[DCache.scala:226:33, :607:47] wire _tl_out_a_valid_T_10 = ~s2_victim_dirty; // @[Misc.scala:38:9] wire _tl_out_a_valid_T_11 = _tl_out_a_valid_T_10; // @[DCache.scala:607:{88,91}] wire _tl_out_a_valid_T_12 = _tl_out_a_valid_T_6 & _tl_out_a_valid_T_11; // @[DCache.scala:605:29, :606:127, :607:88] wire _tl_out_a_valid_T_13 = s2_valid_uncached_pending \| _tl_out_a_valid_T_12; // @[DCache.scala:430:64, :604:32, :606:127] assign _tl_out_a_valid_T_14 = _tl_out_a_valid_T_13; // @[DCache.scala:603:37, :604:32] assign tl_out_a_valid = _tl_out_a_valid_T_14; // @[DCache.scala:159:22, :603:37] wire _tl_out_a_bits_T = ~s2_uncached; // @[DCache.scala:424:39, :425:47, :608:24] wire [39:0] _tl_out_a_bits_T_2 = {_tl_out_a_bits_T_1, 6'h0}; // @[DCache.scala:1210:{39,60}] wire [39:0] _tl_out_a_bits_legal_T_1 = _tl_out_a_bits_T_2; // @[DCache.scala:1210:60] wire [40:0] _tl_out_a_bits_legal_T_2 = {1'h0, _tl_out_a_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}] wire [40:0] _tl_out_a_bits_legal_T_3 = _tl_out_a_bits_legal_T_2 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _tl_out_a_bits_legal_T_4 = _tl_out_a_bits_legal_T_3; // @[Parameters.scala:137:46] wire _tl_out_a_bits_legal_T_5 = _tl_out_a_bits_legal_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _tl_out_a_bits_legal_T_6 = {_tl_out_a_bits_T_2[39:17], _tl_out_a_bits_T_2[16:0] ^ 17'h10000}; // @[DCache.scala:1210:60] wire [40:0] _tl_out_a_bits_legal_T_7 = {1'h0, _tl_out_a_bits_legal_T_6}; // @[Parameters.scala:137:{31,41}] wire [40:0] _tl_out_a_bits_legal_T_8 = _tl_out_a_bits_legal_T_7 & 41'h8C011000; // @[Parameters.scala:137:{41,46}] wire [40:0] _tl_out_a_bits_legal_T_9 = _tl_out_a_bits_legal_T_8; // @[Parameters.scala:137:46] wire _tl_out_a_bits_legal_T_10 = _tl_out_a_bits_legal_T_9 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _tl_out_a_bits_legal_T_11 = {_tl_out_a_bits_T_2[39:28], _tl_out_a_bits_T_2[27:0] ^ 28'hC000000}; // @[DCache.scala:1210:60] wire [40:0] _tl_out_a_bits_legal_T_12 = {1'h0, _tl_out_a_bits_legal_T_11}; // @[Parameters.scala:137:{31,41}] wire [40:0] _tl_out_a_bits_legal_T_13 = _tl_out_a_bits_legal_T_12 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _tl_out_a_bits_legal_T_14 = _tl_out_a_bits_legal_T_13; // @[Parameters.scala:137:46] wire _tl_out_a_bits_legal_T_15 = _tl_out_a_bits_legal_T_14 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _tl_out_a_bits_legal_T_16 = _tl_out_a_bits_legal_T_5 \| _tl_out_a_bits_legal_T_10; // @[Parameters.scala:685:42] wire _tl_out_a_bits_legal_T_17 = _tl_out_a_bits_legal_T_16 \| _tl_out_a_bits_legal_T_15; // @[Parameters.scala:685:42] wire [39:0] _tl_out_a_bits_legal_T_21 = {_tl_out_a_bits_T_2[39:28], _tl_out_a_bits_T_2[27:0] ^ 28'h8000000}; // @[DCache.scala:1210:60] wire [40:0] _tl_out_a_bits_legal_T_22 = {1'h0, _tl_out_a_bits_legal_T_21}; // @[Parameters.scala:137:{31,41}] wire [40:0] _tl_out_a_bits_legal_T_23 = _tl_out_a_bits_legal_T_22 & 41'h8C010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _tl_out_a_bits_legal_T_24 = _tl_out_a_bits_legal_T_23; // @[Parameters.scala:137:46] wire _tl_out_a_bits_legal_T_25 = _tl_out_a_bits_legal_T_24 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [31:0] tl_out_a_bits_a_address = _tl_out_a_bits_T_2[31:0]; // @[Edges.scala:346:17] wire [39:0] _tl_out_a_bits_legal_T_26 = {_tl_out_a_bits_T_2[39:32], tl_out_a_bits_a_address ^ 32'h80000000}; // @[Edges.scala:346:17] wire [40:0] _tl_out_a_bits_legal_T_27 = {1'h0, _tl_out_a_bits_legal_T_26}; // @[Parameters.scala:137:{31,41}] wire [40:0] _tl_out_a_bits_legal_T_28 = _tl_out_a_bits_legal_T_27 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _tl_out_a_bits_legal_T_29 = _tl_out_a_bits_legal_T_28; // @[Parameters.scala:137:46] wire _tl_out_a_bits_legal_T_30 = _tl_out_a_bits_legal_T_29 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _tl_out_a_bits_legal_T_31 = _tl_out_a_bits_legal_T_25 \| _tl_out_a_bits_legal_T_30; // @[Parameters.scala:685:42] wire _tl_out_a_bits_legal_T_32 = _tl_out_a_bits_legal_T_31; // @[Parameters.scala:684:54, :685:42] wire tl_out_a_bits_legal = _tl_out_a_bits_legal_T_32; // @[Parameters.scala:684:54, :686:26] wire [2:0] tl_out_a_bits_a_param; // @[Edges.scala:346:17] assign tl_out_a_bits_a_param = {1'h0, s2_grow_param}; // @[Misc.scala:35:36] wire tl_out_a_bits_a_mask_sub_sub_bit = _tl_out_a_bits_T_2[2]; // @[Misc.scala:210:26] wire tl_out_a_bits_a_mask_sub_sub_1_2 = tl_out_a_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire tl_out_a_bits_a_mask_sub_sub_nbit = ~tl_out_a_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire tl_out_a_bits_a_mask_sub_sub_0_2 = tl_out_a_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_sub_sub_acc_T = tl_out_a_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire _tl_out_a_bits_a_mask_sub_sub_acc_T_1 = tl_out_a_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_sub_bit = _tl_out_a_bits_T_2[1]; // @[Misc.scala:210:26] wire tl_out_a_bits_a_mask_sub_nbit = ~tl_out_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire tl_out_a_bits_a_mask_sub_0_2 = tl_out_a_bits_a_mask_sub_sub_0_2 & tl_out_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire tl_out_a_bits_a_mask_sub_1_2 = tl_out_a_bits_a_mask_sub_sub_0_2 & tl_out_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire tl_out_a_bits_a_mask_sub_2_2 = tl_out_a_bits_a_mask_sub_sub_1_2 & tl_out_a_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire tl_out_a_bits_a_mask_sub_3_2 = tl_out_a_bits_a_mask_sub_sub_1_2 & tl_out_a_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire tl_out_a_bits_a_mask_bit = _tl_out_a_bits_T_2[0]; // @[Misc.scala:210:26] wire tl_out_a_bits_a_mask_nbit = ~tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire tl_out_a_bits_a_mask_eq = tl_out_a_bits_a_mask_sub_0_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T = tl_out_a_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_1 = tl_out_a_bits_a_mask_sub_0_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_1 = tl_out_a_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_2 = tl_out_a_bits_a_mask_sub_1_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T_2 = tl_out_a_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_3 = tl_out_a_bits_a_mask_sub_1_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_3 = tl_out_a_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_4 = tl_out_a_bits_a_mask_sub_2_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T_4 = tl_out_a_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_5 = tl_out_a_bits_a_mask_sub_2_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_5 = tl_out_a_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_6 = tl_out_a_bits_a_mask_sub_3_2 & tl_out_a_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _tl_out_a_bits_a_mask_acc_T_6 = tl_out_a_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire tl_out_a_bits_a_mask_eq_7 = tl_out_a_bits_a_mask_sub_3_2 & tl_out_a_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _tl_out_a_bits_a_mask_acc_T_7 = tl_out_a_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38] wire _tl_out_a_bits_T_3 = ~s2_write; // @[DCache.scala:609:9] wire _tl_out_a_bits_T_5 = ~s2_read; // @[DCache.scala:611:9] wire [2:0] _tl_out_a_bits_T_6_opcode = _tl_out_a_bits_T_5 ? 3'h0 : atomics_opcode; // @[DCache.scala:587:81, :611:{8,9}] wire [2:0] _tl_out_a_bits_T_6_param = _tl_out_a_bits_T_5 ? 3'h0 : atomics_param; // @[DCache.scala:587:81, :611:{8,9}] wire [3:0] _tl_out_a_bits_T_6_size = _tl_out_a_bits_T_5 ? put_size : atomics_size; // @[Edges.scala:480:17] wire _tl_out_a_bits_T_6_source = _tl_out_a_bits_T_5 ? put_source : atomics_source; // @[Edges.scala:480:17] wire [31:0] _tl_out_a_bits_T_6_address = _tl_out_a_bits_T_5 ? put_address : atomics_address; // @[Edges.scala:480:17] wire [7:0] _tl_out_a_bits_T_6_mask = _tl_out_a_bits_T_5 ? put_mask : atomics_mask; // @[Edges.scala:480:17] wire [63:0] _tl_out_a_bits_T_6_data = _tl_out_a_bits_T_5 ? put_data : atomics_data; // @[Edges.scala:480:17] wire [2:0] _tl_out_a_bits_T_7_opcode = _tl_out_a_bits_T_4 ? 3'h1 : _tl_out_a_bits_T_6_opcode; // @[DCache.scala:610:{8,20}, :611:8] wire [2:0] _tl_out_a_bits_T_7_param = _tl_out_a_bits_T_4 ? 3'h0 : _tl_out_a_bits_T_6_param; // @[DCache.scala:610:{8,20}, :611:8] wire [3:0] _tl_out_a_bits_T_7_size = _tl_out_a_bits_T_4 ? putpartial_size : _tl_out_a_bits_T_6_size; // @[Edges.scala:500:17] wire _tl_out_a_bits_T_7_source = _tl_out_a_bits_T_4 ? putpartial_source : _tl_out_a_bits_T_6_source; // @[Edges.scala:500:17] wire [31:0] _tl_out_a_bits_T_7_address = _tl_out_a_bits_T_4 ? putpartial_address : _tl_out_a_bits_T_6_address; // @[Edges.scala:500:17] wire [7:0] _tl_out_a_bits_T_7_mask = _tl_out_a_bits_T_4 ? putpartial_mask : _tl_out_a_bits_T_6_mask; // @[Edges.scala:500:17] wire [63:0] _tl_out_a_bits_T_7_data = _tl_out_a_bits_T_4 ? putpartial_data : _tl_out_a_bits_T_6_data; // @[Edges.scala:500:17] wire [2:0] _tl_out_a_bits_T_8_opcode = _tl_out_a_bits_T_3 ? 3'h4 : _tl_out_a_bits_T_7_opcode; // @[DCache.scala:609:{8,9}, :610:8] wire [2:0] _tl_out_a_bits_T_8_param = _tl_out_a_bits_T_3 ? 3'h0 : _tl_out_a_bits_T_7_param; // @[DCache.scala:609:{8,9}, :610:8] wire [3:0] _tl_out_a_bits_T_8_size = _tl_out_a_bits_T_3 ? get_size : _tl_out_a_bits_T_7_size; // @[Edges.scala:460:17] wire _tl_out_a_bits_T_8_source = _tl_out_a_bits_T_3 ? get_source : _tl_out_a_bits_T_7_source; // @[Edges.scala:460:17] wire [31:0] _tl_out_a_bits_T_8_address = _tl_out_a_bits_T_3 ? get_address : _tl_out_a_bits_T_7_address; // @[Edges.scala:460:17] wire [7:0] _tl_out_a_bits_T_8_mask = _tl_out_a_bits_T_3 ? get_mask : _tl_out_a_bits_T_7_mask; // @[Edges.scala:460:17] wire [63:0] _tl_out_a_bits_T_8_data = _tl_out_a_bits_T_3 ? 64'h0 : _tl_out_a_bits_T_7_data; // @[DCache.scala:609:{8,9}, :610:8] assign _tl_out_a_bits_T_9_opcode = _tl_out_a_bits_T ? 3'h6 : _tl_out_a_bits_T_8_opcode; // @[DCache.scala:608:{23,24}, :609:8] assign _tl_out_a_bits_T_9_param = _tl_out_a_bits_T ? tl_out_a_bits_a_param : _tl_out_a_bits_T_8_param; // @[Edges.scala:346:17] assign _tl_out_a_bits_T_9_size = _tl_out_a_bits_T ? 4'h6 : _tl_out_a_bits_T_8_size; // @[DCache.scala:608:{23,24}, :609:8] assign _tl_out_a_bits_T_9_source = ~_tl_out_a_bits_T & _tl_out_a_bits_T_8_source; // @[DCache.scala:608:{23,24}, :609:8] assign _tl_out_a_bits_T_9_address = _tl_out_a_bits_T ? tl_out_a_bits_a_address : _tl_out_a_bits_T_8_address; // @[Edges.scala:346:17] assign _tl_out_a_bits_T_9_mask = _tl_out_a_bits_T ? 8'hFF : _tl_out_a_bits_T_8_mask; // @[DCache.scala:608:{23,24}, :609:8] assign _tl_out_a_bits_T_9_data = _tl_out_a_bits_T ? 64'h0 : _tl_out_a_bits_T_8_data; // @[DCache.scala:608:{23,24}, :609:8] assign tl_out_a_bits_opcode = _tl_out_a_bits_T_9_opcode; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_param = _tl_out_a_bits_T_9_param; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_size = _tl_out_a_bits_T_9_size; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_source = _tl_out_a_bits_T_9_source; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_address = _tl_out_a_bits_T_9_address; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_mask = _tl_out_a_bits_T_9_mask; // @[DCache.scala:159:22, :608:23] assign tl_out_a_bits_data = _tl_out_a_bits_T_9_data; // @[DCache.scala:159:22, :608:23] wire [1:0] _a_sel_T = 2'h1 << a_sel_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _a_sel_T_1 = _a_sel_T; // @[OneHot.scala:65:{12,27}] wire a_sel = _a_sel_T_1[1]; // @[OneHot.scala:65:27] wire _io_cpu_perf_acquire_T = tl_out_a_ready & tl_out_a_valid; // @[Decoupled.scala:51:35] wire [4:0] _uncachedReqs_0_cmd_T_1 = {_uncachedReqs_0_cmd_T, 4'h1}; // @[DCache.scala:637:{37,49}] wire [4:0] _uncachedReqs_0_cmd_T_2 = s2_write ? _uncachedReqs_0_cmd_T_1 : 5'h0; // @[DCache.scala:637:{23,37}] wire _T_82 = nodeOut_d_ready & nodeOut_d_valid; // @[Decoupled.scala:51:35] wire _io_cpu_replay_next_T; // @[Decoupled.scala:51:35] assign _io_cpu_replay_next_T = _T_82; // @[Decoupled.scala:51:35] wire _io_cpu_perf_blocked_near_end_of_refill_T; // @[Decoupled.scala:51:35] assign _io_cpu_perf_blocked_near_end_of_refill_T = _T_82; // @[Decoupled.scala:51:35] wire _io_errors_bus_valid_T; // @[Decoupled.scala:51:35] assign _io_errors_bus_valid_T = _T_82; // @[Decoupled.scala:51:35] wire [26:0] _r_beats1_decode_T = 27'hFFF << nodeOut_d_bits_size; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire r_beats1_opdata = nodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36] wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] r_counter; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_last = _r_last_T \| _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_done = d_last & _T_82; // @[Decoupled.scala:51:35] wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T = d_first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] d_address_inc = {r_4, 3'h0}; // @[Edges.scala:234:25, :269:29] wire grantIsUncachedData = nodeOut_d_bits_opcode == 3'h1; // @[package.scala:16:47] wire grantIsUncached = grantIsUncachedData \| nodeOut_d_bits_opcode == 3'h0 \| nodeOut_d_bits_opcode == 3'h2; // @[package.scala:16:47, :81:59] wire _tl_d_data_encoded_T_9 = io_ptw_customCSRs_csrs_0_value_0[9]; // @[CustomCSRs.scala:47:65] wire _tl_d_data_encoded_T_10 = ~_tl_d_data_encoded_T_9; // @[CustomCSRs.scala:47:65] wire _tl_d_data_encoded_T_11 = nodeOut_d_bits_corrupt & _tl_d_data_encoded_T_10; // @[DCache.scala:663:{77,80}] wire _tl_d_data_encoded_T_12 = ~grantIsUncached; // @[package.scala:81:59] wire _tl_d_data_encoded_T_13 = _tl_d_data_encoded_T_11 & _tl_d_data_encoded_T_12; // @[DCache.scala:663:{77,126,129}] wire [15:0] tl_d_data_encoded_lo_lo_1 = {_tl_d_data_encoded_T_15, _tl_d_data_encoded_T_14}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_lo_hi_1 = {_tl_d_data_encoded_T_17, _tl_d_data_encoded_T_16}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_lo_1 = {tl_d_data_encoded_lo_hi_1, tl_d_data_encoded_lo_lo_1}; // @[package.scala:45:27] wire [15:0] tl_d_data_encoded_hi_lo_1 = {_tl_d_data_encoded_T_19, _tl_d_data_encoded_T_18}; // @[package.scala:45:27, :211:50] wire [15:0] tl_d_data_encoded_hi_hi_1 = {_tl_d_data_encoded_T_21, _tl_d_data_encoded_T_20}; // @[package.scala:45:27, :211:50] wire [31:0] tl_d_data_encoded_hi_1 = {tl_d_data_encoded_hi_hi_1, tl_d_data_encoded_hi_lo_1}; // @[package.scala:45:27] assign _tl_d_data_encoded_T_22 = {tl_d_data_encoded_hi_1, tl_d_data_encoded_lo_1}; // @[package.scala:45:27] assign tl_d_data_encoded = _tl_d_data_encoded_T_22; // @[package.scala:45:27] wire _grantIsCached_T = nodeOut_d_bits_opcode == 3'h4; // @[package.scala:16:47] wire _GEN_113 = nodeOut_d_bits_opcode == 3'h5; // @[package.scala:16:47] wire _grantIsCached_T_1; // @[package.scala:16:47] assign _grantIsCached_T_1 = _GEN_113; // @[package.scala:16:47] wire grantIsRefill; // @[DCache.scala:666:29] assign grantIsRefill = _GEN_113; // @[package.scala:16:47] wire grantIsCached = _grantIsCached_T \| _grantIsCached_T_1; // @[package.scala:16:47, :81:59] wire grantIsVoluntary = nodeOut_d_bits_opcode == 3'h6; // @[DCache.scala:665:32] reg grantInProgress; // @[DCache.scala:667:32] reg [2:0] blockProbeAfterGrantCount; // @[DCache.scala:668:42] wire [3:0] _blockProbeAfterGrantCount_T = {1'h0, blockProbeAfterGrantCount} - 4'h1; // @[DCache.scala:668:42, :669:99] wire [2:0] _blockProbeAfterGrantCount_T_1 = _blockProbeAfterGrantCount_T[2:0]; // @[DCache.scala:669:99] wire _T_107 = release_state == 4'h6; // @[package.scala:16:47] wire _canAcceptCachedGrant_T_1; // @[package.scala:16:47] assign _canAcceptCachedGrant_T_1 = _T_107; // @[package.scala:16:47] wire _metaArb_io_in_4_valid_T; // @[package.scala:16:47] assign _metaArb_io_in_4_valid_T = _T_107; // @[package.scala:16:47] wire _T_111 = release_state == 4'h9; // @[package.scala:16:47] wire _canAcceptCachedGrant_T_2; // @[package.scala:16:47] assign _canAcceptCachedGrant_T_2 = _T_111; // @[package.scala:16:47] wire _nodeOut_c_valid_T_1; // @[DCache.scala:810:91] assign _nodeOut_c_valid_T_1 = _T_111; // @[package.scala:16:47] wire _canAcceptCachedGrant_T_3 = _canAcceptCachedGrant_T \| _canAcceptCachedGrant_T_1; // @[package.scala:16:47, :81:59] wire _canAcceptCachedGrant_T_4 = _canAcceptCachedGrant_T_3 \| _canAcceptCachedGrant_T_2; // @[package.scala:16:47, :81:59] wire canAcceptCachedGrant = ~_canAcceptCachedGrant_T_4; // @[package.scala:81:59] wire _nodeOut_d_ready_T = ~d_first; // @[Edges.scala:231:25] wire _nodeOut_d_ready_T_1 = _nodeOut_d_ready_T \| nodeOut_e_ready; // @[DCache.scala:671:{41,50}] wire _nodeOut_d_ready_T_2 = _nodeOut_d_ready_T_1 & canAcceptCachedGrant; // @[DCache.scala:670:30, :671:{50,69}] wire _nodeOut_d_ready_T_3 = ~grantIsCached \| _nodeOut_d_ready_T_2; // @[package.scala:81:59] wire [1:0] _uncachedRespIdxOH_T = 2'h1 << uncachedRespIdxOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _uncachedRespIdxOH_T_1 = _uncachedRespIdxOH_T; // @[OneHot.scala:65:{12,27}] wire uncachedRespIdxOH = _uncachedRespIdxOH_T_1[1]; // @[OneHot.scala:65:27] wire _uncachedResp_T = uncachedRespIdxOH; // @[Mux.scala:32:36] wire _GEN_114 = _T_82 & grantIsCached; // @[Decoupled.scala:51:35] assign replace = _GEN_114 & d_last; // @[Replacement.scala:37:29, :38:11] wire _T_74 = uncachedRespIdxOH & d_last; // @[Edges.scala:232:33] assign s1_data_way = ~_T_82 \| grantIsCached \| ~(grantIsUncached & grantIsUncachedData) ? {1'h0, _s1_data_way_T} : 9'h100; // @[Decoupled.scala:51:35] wire [28:0] _s2_req_addr_dontCareBits_T = s1_paddr[31:3]; // @[DCache.scala:298:21, :701:41] wire [31:0] s2_req_addr_dontCareBits = {_s2_req_addr_dontCareBits_T, 3'h0}; // @[DCache.scala:701:{41,55}] wire [2:0] _s2_req_addr_T = uncachedResp_addr[2:0]; // @[DCache.scala:238:30, :702:45] wire [31:0] _s2_req_addr_T_1 = {s2_req_addr_dontCareBits[31:3], s2_req_addr_dontCareBits[2:0] \| _s2_req_addr_T}; // @[DCache.scala:701:55, :702:{26,45}] wire _nodeOut_e_valid_T = nodeOut_d_valid & d_first; // @[Edges.scala:231:25] wire _nodeOut_e_valid_T_1 = _nodeOut_e_valid_T & grantIsCached; // @[package.scala:81:59] wire _nodeOut_e_valid_T_2 = _nodeOut_e_valid_T_1 & canAcceptCachedGrant; // @[DCache.scala:670:30, :714:{47,64}] assign nodeOut_e_bits_sink = nodeOut_e_bits_e_sink; // @[Edges.scala:451:17] wire _dataArb_io_in_1_valid_T = nodeOut_d_valid & grantIsRefill; // @[DCache.scala:666:29, :721:44] wire _dataArb_io_in_1_valid_T_1 = _dataArb_io_in_1_valid_T & canAcceptCachedGrant; // @[DCache.scala:670:30, :721:{44,61}] wire _T_90 = grantIsRefill & ~dataArb_io_in_1_ready; // @[DCache.scala:152:28, :666:29, :722:{23,26}] assign nodeOut_e_valid = ~_T_90 & _nodeOut_e_valid_T_2; // @[DCache.scala:714:{18,64}, :722:{23,51}, :723:20] wire [33:0] _dataArb_io_in_1_bits_addr_T = s2_vaddr[39:6]; // @[DCache.scala:351:21, :728:46] wire [39:0] _dataArb_io_in_1_bits_addr_T_1 = {_dataArb_io_in_1_bits_addr_T, 6'h0}; // @[DCache.scala:728:{46,57}] wire [39:0] _dataArb_io_in_1_bits_addr_T_2 = {_dataArb_io_in_1_bits_addr_T_1[39:12], _dataArb_io_in_1_bits_addr_T_1[11:0] \| d_address_inc}; // @[Edges.scala:269:29] assign dataArb_io_in_1_bits_addr = _dataArb_io_in_1_bits_addr_T_2[11:0]; // @[DCache.scala:152:28, :728:{32,67}] wire _metaArb_io_in_3_valid_T = grantIsCached & d_done; // @[package.scala:81:59] wire _metaArb_io_in_3_valid_T_1 = ~nodeOut_d_bits_denied; // @[DCache.scala:741:56] assign _metaArb_io_in_3_valid_T_2 = _metaArb_io_in_3_valid_T & _metaArb_io_in_3_valid_T_1; // @[DCache.scala:741:{43,53,56}] assign metaArb_io_in_3_valid = _metaArb_io_in_3_valid_T_2; // @[DCache.scala:135:28, :741:53] assign metaArb_io_in_3_bits_idx = _metaArb_io_in_3_bits_idx_T; // @[DCache.scala:135:28, :744:40] assign _metaArb_io_in_3_bits_addr_T_2 = {_metaArb_io_in_3_bits_addr_T, _metaArb_io_in_3_bits_addr_T_1}; // @[DCache.scala:745:{36,58,80}] assign metaArb_io_in_3_bits_addr = _metaArb_io_in_3_bits_addr_T_2; // @[DCache.scala:135:28, :745:36] wire _metaArb_io_in_3_bits_data_c_cat_T_2 = _metaArb_io_in_3_bits_data_c_cat_T \| _metaArb_io_in_3_bits_data_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _metaArb_io_in_3_bits_data_c_cat_T_4 = _metaArb_io_in_3_bits_data_c_cat_T_2 \| _metaArb_io_in_3_bits_data_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _metaArb_io_in_3_bits_data_c_cat_T_9 = _metaArb_io_in_3_bits_data_c_cat_T_5 \| _metaArb_io_in_3_bits_data_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_10 = _metaArb_io_in_3_bits_data_c_cat_T_9 \| _metaArb_io_in_3_bits_data_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_11 = _metaArb_io_in_3_bits_data_c_cat_T_10 \| _metaArb_io_in_3_bits_data_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_17 = _metaArb_io_in_3_bits_data_c_cat_T_12 \| _metaArb_io_in_3_bits_data_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_18 = _metaArb_io_in_3_bits_data_c_cat_T_17 \| _metaArb_io_in_3_bits_data_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_19 = _metaArb_io_in_3_bits_data_c_cat_T_18 \| _metaArb_io_in_3_bits_data_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_20 = _metaArb_io_in_3_bits_data_c_cat_T_19 \| _metaArb_io_in_3_bits_data_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_21 = _metaArb_io_in_3_bits_data_c_cat_T_11 \| _metaArb_io_in_3_bits_data_c_cat_T_20; // @[package.scala:81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_22 = _metaArb_io_in_3_bits_data_c_cat_T_4 \| _metaArb_io_in_3_bits_data_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _metaArb_io_in_3_bits_data_c_cat_T_25 = _metaArb_io_in_3_bits_data_c_cat_T_23 \| _metaArb_io_in_3_bits_data_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _metaArb_io_in_3_bits_data_c_cat_T_27 = _metaArb_io_in_3_bits_data_c_cat_T_25 \| _metaArb_io_in_3_bits_data_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _metaArb_io_in_3_bits_data_c_cat_T_32 = _metaArb_io_in_3_bits_data_c_cat_T_28 \| _metaArb_io_in_3_bits_data_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_33 = _metaArb_io_in_3_bits_data_c_cat_T_32 \| _metaArb_io_in_3_bits_data_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_34 = _metaArb_io_in_3_bits_data_c_cat_T_33 \| _metaArb_io_in_3_bits_data_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_40 = _metaArb_io_in_3_bits_data_c_cat_T_35 \| _metaArb_io_in_3_bits_data_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_41 = _metaArb_io_in_3_bits_data_c_cat_T_40 \| _metaArb_io_in_3_bits_data_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_42 = _metaArb_io_in_3_bits_data_c_cat_T_41 \| _metaArb_io_in_3_bits_data_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_43 = _metaArb_io_in_3_bits_data_c_cat_T_42 \| _metaArb_io_in_3_bits_data_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_44 = _metaArb_io_in_3_bits_data_c_cat_T_34 \| _metaArb_io_in_3_bits_data_c_cat_T_43; // @[package.scala:81:59] wire _metaArb_io_in_3_bits_data_c_cat_T_45 = _metaArb_io_in_3_bits_data_c_cat_T_27 \| _metaArb_io_in_3_bits_data_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _metaArb_io_in_3_bits_data_c_cat_T_47 = _metaArb_io_in_3_bits_data_c_cat_T_45 \| _metaArb_io_in_3_bits_data_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _metaArb_io_in_3_bits_data_c_cat_T_49 = _metaArb_io_in_3_bits_data_c_cat_T_47 \| _metaArb_io_in_3_bits_data_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] metaArb_io_in_3_bits_data_c = {_metaArb_io_in_3_bits_data_c_cat_T_22, _metaArb_io_in_3_bits_data_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _metaArb_io_in_3_bits_data_T_1 = {metaArb_io_in_3_bits_data_c, nodeOut_d_bits_param}; // @[Metadata.scala:29:18, :84:18] wire _metaArb_io_in_3_bits_data_T_10 = _metaArb_io_in_3_bits_data_T_1 == 4'h1; // @[Metadata.scala:84:{18,38}] wire [1:0] _metaArb_io_in_3_bits_data_T_11 = {1'h0, _metaArb_io_in_3_bits_data_T_10}; // @[Metadata.scala:84:38] wire _metaArb_io_in_3_bits_data_T_12 = _metaArb_io_in_3_bits_data_T_1 == 4'h0; // @[Metadata.scala:84:{18,38}] wire [1:0] _metaArb_io_in_3_bits_data_T_13 = _metaArb_io_in_3_bits_data_T_12 ? 2'h2 : _metaArb_io_in_3_bits_data_T_11; // @[Metadata.scala:84:38] wire _metaArb_io_in_3_bits_data_T_14 = _metaArb_io_in_3_bits_data_T_1 == 4'h4; // @[Metadata.scala:84:{18,38}] wire [1:0] _metaArb_io_in_3_bits_data_T_15 = _metaArb_io_in_3_bits_data_T_14 ? 2'h2 : _metaArb_io_in_3_bits_data_T_13; // @[Metadata.scala:84:38] wire _metaArb_io_in_3_bits_data_T_16 = _metaArb_io_in_3_bits_data_T_1 == 4'hC; // @[Metadata.scala:84:{18,38}] wire [1:0] _metaArb_io_in_3_bits_data_T_17 = _metaArb_io_in_3_bits_data_T_16 ? 2'h3 : _metaArb_io_in_3_bits_data_T_15; // @[Metadata.scala:84:38] wire [1:0] metaArb_io_in_3_bits_data_meta_state = _metaArb_io_in_3_bits_data_T_17; // @[Metadata.scala:84:38, :160:20] wire [1:0] metaArb_io_in_3_bits_data_meta_1_coh_state = metaArb_io_in_3_bits_data_meta_state; // @[Metadata.scala:160:20] wire [19:0] metaArb_io_in_3_bits_data_meta_1_tag; // @[HellaCache.scala:305:20] assign metaArb_io_in_3_bits_data_meta_1_tag = _metaArb_io_in_3_bits_data_T[19:0]; // @[HellaCache.scala:305:20, :306:14] assign _metaArb_io_in_3_bits_data_T_18 = {metaArb_io_in_3_bits_data_meta_1_coh_state, metaArb_io_in_3_bits_data_meta_1_tag}; // @[HellaCache.scala:305:20] assign metaArb_io_in_3_bits_data = _metaArb_io_in_3_bits_data_T_18; // @[DCache.scala:135:28, :746:134] reg blockUncachedGrant; // @[DCache.scala:750:33] wire _T_92 = grantIsUncachedData & (blockUncachedGrant \| s1_valid); // @[package.scala:16:47] assign nodeOut_d_ready = ~(_T_92 \| _T_90) & _nodeOut_d_ready_T_3; // @[DCache.scala:671:{18,24}, :722:{23,51}, :724:20, :752:{31,68}, :753:22] assign io_cpu_req_ready_0 = _T_92 ? ~(nodeOut_d_valid \| _T_10 \| ~metaArb_io_in_7_ready \| _T_4) & _io_cpu_req_ready_T_4 : ~(_T_10 \| ~metaArb_io_in_7_ready \| _T_4) & _io_cpu_req_ready_T_4; // @[DCache.scala:101:7, :135:28, :195:9, :233:{20,73}, :258:{33,45,64}, :267:{34,53}, :275:{27,53,79,98}, :752:{31,68}, :755:29, :756:26] wire _GEN_115 = _T_92 & nodeOut_d_valid; // @[DCache.scala:721:26, :752:{31,68}, :755:29, :757:32] assign dataArb_io_in_1_valid = _GEN_115 \| _dataArb_io_in_1_valid_T_1; // @[DCache.scala:152:28, :721:{26,61}, :752:68, :755:29, :757:32] assign dataArb_io_in_1_bits_write = ~_T_92 \| ~nodeOut_d_valid; // @[DCache.scala:152:28, :727:33, :752:{31,68}, :755:29, :758:37] wire _blockUncachedGrant_T = ~dataArb_io_in_1_ready; // @[DCache.scala:152:28, :722:26, :759:31] wire _block_probe_for_core_progress_T = \|blockProbeAfterGrantCount; // @[DCache.scala:668:42, :669:35, :766:65] wire block_probe_for_core_progress = _block_probe_for_core_progress_T \| lrscValid; // @[DCache.scala:473:29, :766:{65,71}] wire [31:0] _block_probe_for_pending_release_ack_T = nodeOut_b_bits_address ^ release_ack_addr; // @[DCache.scala:227:29, :767:88] wire [14:0] _block_probe_for_pending_release_ack_T_1 = _block_probe_for_pending_release_ack_T[20:6]; // @[DCache.scala:767:{88,107}] wire _block_probe_for_pending_release_ack_T_2 = _block_probe_for_pending_release_ack_T_1 == 15'h0; // @[DCache.scala:582:29, :767:{107,163}] wire block_probe_for_pending_release_ack = release_ack_wait & _block_probe_for_pending_release_ack_T_2; // @[DCache.scala:226:33, :767:{62,163}] wire _block_probe_for_ordering_T = releaseInFlight \| block_probe_for_pending_release_ack; // @[DCache.scala:334:46, :767:62, :768:50] wire block_probe_for_ordering = _block_probe_for_ordering_T \| grantInProgress; // @[DCache.scala:667:32, :768:{50,89}] wire _metaArb_io_in_6_valid_T = ~block_probe_for_core_progress; // @[DCache.scala:766:71, :769:48] wire _metaArb_io_in_6_valid_T_1 = _metaArb_io_in_6_valid_T \| lrscBackingOff; // @[DCache.scala:474:40, :769:{48,79}] wire _metaArb_io_in_6_valid_T_2 = nodeOut_b_valid & _metaArb_io_in_6_valid_T_1; // @[DCache.scala:769:{44,79}] wire _nodeOut_b_ready_T = block_probe_for_core_progress \| block_probe_for_ordering; // @[DCache.scala:766:71, :768:89, :770:79] wire _nodeOut_b_ready_T_1 = _nodeOut_b_ready_T \| s1_valid; // @[DCache.scala:182:25, :770:{79,107}] wire _nodeOut_b_ready_T_2 = _nodeOut_b_ready_T_1 \| s2_valid; // @[DCache.scala:331:25, :770:{107,119}] wire _nodeOut_b_ready_T_3 = ~_nodeOut_b_ready_T_2; // @[DCache.scala:770:{47,119}] assign _nodeOut_b_ready_T_4 = metaArb_io_in_6_ready & _nodeOut_b_ready_T_3; // @[DCache.scala:135:28, :770:{44,47}] assign nodeOut_b_ready = _nodeOut_b_ready_T_4; // @[DCache.scala:770:44] wire [5:0] _metaArb_io_in_6_bits_idx_T = nodeOut_b_bits_address[11:6]; // @[DCache.scala:1200:47] wire [7:0] _metaArb_io_in_6_bits_addr_T = io_cpu_req_bits_addr_0[39:32]; // @[DCache.scala:101:7, :773:58] wire [7:0] _metaArb_io_in_6_bits_addr_T_2 = io_cpu_req_bits_addr_0[39:32]; // @[DCache.scala:101:7, :773:58, :844:62] wire [39:0] _metaArb_io_in_6_bits_addr_T_1 = {_metaArb_io_in_6_bits_addr_T, nodeOut_b_bits_address}; // @[DCache.scala:773:{36,58}] assign _s1_victim_way_T = lfsr[2:0]; // @[PRNG.scala:95:17] assign s1_victim_way = _s1_victim_way_T; // @[package.scala:163:13] wire _T_126 = nodeOut_c_ready & nodeOut_c_valid; // @[Decoupled.scala:51:35] wire _releaseRejected_T; // @[Decoupled.scala:51:35] assign _releaseRejected_T = _T_126; // @[Decoupled.scala:51:35] wire _io_cpu_perf_release_T; // @[Decoupled.scala:51:35] assign _io_cpu_perf_release_T = _T_126; // @[Decoupled.scala:51:35] wire [26:0] _GEN_116 = 27'hFFF << nodeOut_c_bits_size; // @[package.scala:243:71] wire [26:0] _r_beats1_decode_T_3; // @[package.scala:243:71] assign _r_beats1_decode_T_3 = _GEN_116; // @[package.scala:243:71] wire [26:0] _io_cpu_perf_release_beats1_decode_T; // @[package.scala:243:71] assign _io_cpu_perf_release_beats1_decode_T = _GEN_116; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_4 = _r_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_5 = ~_r_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] r_beats1_decode_1 = _r_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire r_beats1_opdata_1 = nodeOut_c_bits_opcode[0]; // @[Edges.scala:102:36] wire io_cpu_perf_release_beats1_opdata = nodeOut_c_bits_opcode[0]; // @[Edges.scala:102:36] wire [8:0] r_beats1_1 = r_beats1_opdata_1 ? r_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] r_counter_1; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T_1 = {1'h0, r_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1_1 = _r_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first = r_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T_2 = r_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_3 = r_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_last = _r_last_T_2 \| _r_last_T_3; // @[Edges.scala:232:{25,33,43}] wire releaseDone = c_last & _T_126; // @[Decoupled.scala:51:35] wire [8:0] _r_count_T_1 = ~r_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_count = r_beats1_1 & _r_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T_1 = c_first ? r_beats1_1 : r_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire _releaseRejected_T_2; // @[DCache.scala:803:44] wire releaseRejected; // @[DCache.scala:800:29] wire _s1_release_data_valid_T = dataArb_io_in_2_ready & _dataArb_io_in_2_valid_T_1; // @[Decoupled.scala:51:35] reg s1_release_data_valid; // @[DCache.scala:801:38] wire _s2_release_data_valid_T = ~releaseRejected; // @[DCache.scala:800:29, :802:64] wire _s2_release_data_valid_T_1 = s1_release_data_valid & _s2_release_data_valid_T; // @[DCache.scala:801:38, :802:{61,64}] reg s2_release_data_valid; // @[DCache.scala:802:38] wire _nodeOut_c_valid_T_3 = s2_release_data_valid; // @[DCache.scala:802:38, :810:44] wire _releaseRejected_T_1 = ~_releaseRejected_T; // @[Decoupled.scala:51:35] assign _releaseRejected_T_2 = s2_release_data_valid & _releaseRejected_T_1; // @[DCache.scala:802:38, :803:{44,47}] assign releaseRejected = _releaseRejected_T_2; // @[DCache.scala:800:29, :803:44] wire [9:0] _releaseDataBeat_T = {1'h0, c_count}; // @[Edges.scala:234:25] wire [1:0] _releaseDataBeat_T_1 = {1'h0, s2_release_data_valid}; // @[DCache.scala:802:38, :804:98] wire [2:0] _releaseDataBeat_T_2 = {2'h0, s1_release_data_valid} + {1'h0, _releaseDataBeat_T_1}; // @[DCache.scala:801:38, :804:{93,98}] wire [1:0] _releaseDataBeat_T_3 = _releaseDataBeat_T_2[1:0]; // @[DCache.scala:804:93] wire [1:0] _releaseDataBeat_T_4 = releaseRejected ? 2'h0 : _releaseDataBeat_T_3; // @[DCache.scala:800:29, :804:{48,93}] wire [10:0] _releaseDataBeat_T_5 = {1'h0, _releaseDataBeat_T} + {9'h0, _releaseDataBeat_T_4}; // @[DCache.scala:804:{28,43,48}] wire [9:0] releaseDataBeat = _releaseDataBeat_T_5[9:0]; // @[DCache.scala:804:43] wire _nodeOut_c_valid_T_4 = c_first & release_ack_wait; // @[Edges.scala:231:25] wire _nodeOut_c_valid_T_5 = ~_nodeOut_c_valid_T_4; // @[DCache.scala:810:{120,130}] wire _nodeOut_c_valid_T_6 = _nodeOut_c_valid_T_3 & _nodeOut_c_valid_T_5; // @[DCache.scala:810:{44,117,120}] wire [1:0] newCoh_state; // @[DCache.scala:812:27] wire [1:0] metaArb_io_in_4_bits_data_meta_coh_state = newCoh_state; // @[HellaCache.scala:305:20] wire _release_state_T_8 = s2_valid_flush_line \| s2_flush_valid; // @[DCache.scala:363:51, :419:75, :817:34, :820:151] wire _discard_line_T = s2_req_size[1]; // @[DCache.scala:339:19, :818:60] wire _discard_line_T_1 = s2_valid_flush_line & _discard_line_T; // @[DCache.scala:419:75, :818:{46,60}] wire _discard_line_T_3 = s2_flush_valid & _discard_line_T_2; // @[DCache.scala:363:51, :818:{82,102}] wire discard_line = _discard_line_T_1 \| _discard_line_T_3; // @[DCache.scala:818:{46,64,82}] wire _release_state_T = ~discard_line; // @[DCache.scala:818:64, :819:47] wire _release_state_T_1 = s2_victim_dirty & _release_state_T; // @[Misc.scala:38:9] wire _release_state_T_3 = ~release_ack_wait; // @[DCache.scala:226:33, :607:47, :820:57] wire _release_state_T_6 = \|s2_victim_state_state; // @[Metadata.scala:50:45] wire _release_state_T_9 = ~s2_hit_valid; // @[Metadata.scala:50:45] wire _release_state_T_10 = s2_readwrite & _release_state_T_9; // @[DCache.scala:354:30, :820:{185,188}] wire _release_state_T_11 = _release_state_T_8 \| _release_state_T_10; // @[DCache.scala:820:{151,169,185}] wire [3:0] _release_state_T_14 = _release_state_T_1 ? 4'h1 : 4'h6; // @[DCache.scala:819:{27,44}] wire [5:0] _probe_bits_T_1 = s2_req_addr[11:6]; // @[DCache.scala:339:19, :822:76] wire [25:0] _probe_bits_T_2 = {s2_victim_tag, _probe_bits_T_1}; // @[DCache.scala:433:26, :822:{49,76}] wire [31:0] _probe_bits_T_3 = {_probe_bits_T_2, 6'h0}; // @[DCache.scala:822:{49,96}] wire [31:0] probe_bits_res_address = _probe_bits_T_3; // @[DCache.scala:822:96, :1202:19] wire probeNack; // @[DCache.scala:825:34] wire [3:0] _release_state_T_15 = {1'h0, releaseDone, 2'h3}; // @[Edges.scala:233:22] wire _probeNack_T = ~releaseDone; // @[Edges.scala:233:22] assign probeNack = s2_prb_ack_data \| (\|s2_probe_state_state) \| _probeNack_T; // @[Misc.scala:38:9] wire [3:0] _release_state_T_16 = releaseDone ? 4'h0 : 4'h5; // @[Edges.scala:233:22] assign s1_nack = s2_probe ? probeNack \| _T_60 \| _T_40 \| _T_14 : _T_60 \| _T_40 \| _T_14; // @[DCache.scala:185:28, :276:{39,58,79}, :288:{75,85}, :333:25, :446:{24,82,92}, :571:{18,36,46}, :824:21, :825:34, :839:{24,34}] wire _T_102 = release_state == 4'h4; // @[DCache.scala:228:30, :841:25] assign metaArb_io_in_6_valid = _T_102 \| _metaArb_io_in_6_valid_T_2; // @[DCache.scala:135:28, :769:{26,44}, :841:{25,44}, :842:30] assign metaArb_io_in_6_bits_idx = _T_102 ? _metaArb_io_in_6_bits_idx_T_1 : _metaArb_io_in_6_bits_idx_T; // @[DCache.scala:135:28, :772:29, :841:{25,44}, :843:33, :1200:47] wire [39:0] _metaArb_io_in_6_bits_addr_T_3 = {_metaArb_io_in_6_bits_addr_T_2, probe_bits_address}; // @[DCache.scala:184:29, :844:{40,62}] assign metaArb_io_in_6_bits_addr = _T_102 ? _metaArb_io_in_6_bits_addr_T_3 : _metaArb_io_in_6_bits_addr_T_1; // @[DCache.scala:135:28, :773:{30,36}, :841:{25,44}, :844:{34,40}] wire _T_103 = release_state == 4'h5; // @[DCache.scala:228:30, :850:25] wire _T_104 = release_state == 4'h3; // @[DCache.scala:228:30, :854:25] assign nodeOut_c_valid = _T_104 \| _T_103 \| s2_probe & ~s2_prb_ack_data \| _nodeOut_c_valid_T_6; // @[Misc.scala:38:9] wire _GEN_117 = _T_104 \| ~(~s2_probe \| s2_prb_ack_data \| ~(\|s2_probe_state_state)); // @[Misc.scala:38:9] wire _T_110 = _T_106 \| _T_107 \| _T_111; // @[package.scala:16:47, :81:59] assign nodeOut_c_bits_opcode = _T_110 ? {2'h3, ~_T_111} : {2'h2, _inWriteback_T_1}; // @[package.scala:16:47, :81:59] assign nodeOut_c_bits_param = _T_110 ? (_T_111 ? nodeOut_c_bits_c_param : nodeOut_c_bits_c_1_param) : _inWriteback_T_1 ? dirtyReleaseMessage_param : _GEN_117 ? cleanReleaseMessage_param : 3'h5; // @[package.scala:16:47, :81:59] assign nodeOut_c_bits_size = _T_110 ? 4'h6 : _inWriteback_T_1 ? dirtyReleaseMessage_size : _GEN_117 ? cleanReleaseMessage_size : nackResponseMessage_size; // @[package.scala:16:47, :81:59] assign newCoh_state = _T_110 ? voluntaryNewCoh_state : probeNewCoh_state; // @[package.scala:81:59] assign releaseWay = _T_110 ? s2_victim_or_hit_way : s2_probe_way; // @[package.scala:81:59] wire _dataArb_io_in_2_valid_T = releaseDataBeat < 10'h8; // @[DCache.scala:804:43, :900:60] assign _dataArb_io_in_2_valid_T_1 = inWriteback & _dataArb_io_in_2_valid_T; // @[package.scala:81:59] assign dataArb_io_in_2_valid = _dataArb_io_in_2_valid_T_1; // @[DCache.scala:152:28, :900:41] wire [11:0] _dataArb_io_in_2_bits_addr_T_1 = {_dataArb_io_in_2_bits_addr_T, 6'h0}; // @[DCache.scala:903:55, :1200:47] wire [2:0] _dataArb_io_in_2_bits_addr_T_2 = releaseDataBeat[2:0]; // @[DCache.scala:804:43, :903:90] wire [5:0] _dataArb_io_in_2_bits_addr_T_3 = {_dataArb_io_in_2_bits_addr_T_2, 3'h0}; // @[DCache.scala:903:{90,117}] assign _dataArb_io_in_2_bits_addr_T_4 = {_dataArb_io_in_2_bits_addr_T_1[11:6], _dataArb_io_in_2_bits_addr_T_1[5:0] \| _dataArb_io_in_2_bits_addr_T_3}; // @[DCache.scala:903:{55,72,117}] assign dataArb_io_in_2_bits_addr = _dataArb_io_in_2_bits_addr_T_4; // @[DCache.scala:152:28, :903:72] wire _metaArb_io_in_4_valid_T_1 = release_state == 4'h7; // @[package.scala:16:47] assign _metaArb_io_in_4_valid_T_2 = _metaArb_io_in_4_valid_T \| _metaArb_io_in_4_valid_T_1; // @[package.scala:16:47, :81:59] assign metaArb_io_in_4_valid = _metaArb_io_in_4_valid_T_2; // @[package.scala:81:59] assign metaArb_io_in_4_bits_idx = _metaArb_io_in_4_bits_idx_T; // @[DCache.scala:135:28, :1200:47] wire [11:0] _metaArb_io_in_4_bits_addr_T_1 = probe_bits_address[11:0]; // @[DCache.scala:184:29, :912:90] assign _metaArb_io_in_4_bits_addr_T_2 = {_metaArb_io_in_4_bits_addr_T, _metaArb_io_in_4_bits_addr_T_1}; // @[DCache.scala:912:{36,58,90}] assign metaArb_io_in_4_bits_addr = _metaArb_io_in_4_bits_addr_T_2; // @[DCache.scala:135:28, :912:36] wire [19:0] _metaArb_io_in_4_bits_data_T = nodeOut_c_bits_address[31:12]; // @[DCache.scala:913:78] wire [19:0] metaArb_io_in_4_bits_data_meta_tag = _metaArb_io_in_4_bits_data_T; // @[HellaCache.scala:305:20] assign _metaArb_io_in_4_bits_data_T_1 = {metaArb_io_in_4_bits_data_meta_coh_state, metaArb_io_in_4_bits_data_meta_tag}; // @[HellaCache.scala:305:20] assign metaArb_io_in_4_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97] assign metaArb_io_in_5_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97] assign metaArb_io_in_6_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97] assign metaArb_io_in_7_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97] wire _io_cpu_s2_uncached_T = ~s2_hit; // @[Misc.scala:35:9] assign _io_cpu_s2_uncached_T_1 = s2_uncached & _io_cpu_s2_uncached_T; // @[DCache.scala:424:39, :920:{37,40}] assign io_cpu_s2_uncached_0 = _io_cpu_s2_uncached_T_1; // @[DCache.scala:101:7, :920:37] wire _io_cpu_ordered_T_2 = ~s2_req_no_xcpt; // @[DCache.scala:339:19, :929:72] wire _io_cpu_ordered_T_3 = s2_valid & _io_cpu_ordered_T_2; // @[DCache.scala:331:25, :929:{69,72}] wire _io_cpu_ordered_T_4 = _io_cpu_ordered_T_1 \| _io_cpu_ordered_T_3; // @[DCache.scala:929:{32,57,69}] wire _io_cpu_ordered_T_5 = _io_cpu_ordered_T_4 \| cached_grant_wait; // @[DCache.scala:223:34, :929:{57,94}] wire _io_cpu_ordered_T_7 = _io_cpu_ordered_T_5 \| _io_cpu_ordered_T_6; // @[DCache.scala:929:{94,115,142}] assign _io_cpu_ordered_T_8 = ~_io_cpu_ordered_T_7; // @[DCache.scala:929:{21,115}] assign io_cpu_ordered_0 = _io_cpu_ordered_T_8; // @[DCache.scala:101:7, :929:21] wire _io_cpu_store_pending_T_2 = _io_cpu_store_pending_T \| _io_cpu_store_pending_T_1; // @[Consts.scala:90:{32,42,49}] wire _io_cpu_store_pending_T_4 = _io_cpu_store_pending_T_2 \| _io_cpu_store_pending_T_3; // @[Consts.scala:90:{42,59,66}] wire _io_cpu_store_pending_T_9 = _io_cpu_store_pending_T_5 \| _io_cpu_store_pending_T_6; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_10 = _io_cpu_store_pending_T_9 \| _io_cpu_store_pending_T_7; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_11 = _io_cpu_store_pending_T_10 \| _io_cpu_store_pending_T_8; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_17 = _io_cpu_store_pending_T_12 \| _io_cpu_store_pending_T_13; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_18 = _io_cpu_store_pending_T_17 \| _io_cpu_store_pending_T_14; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_19 = _io_cpu_store_pending_T_18 \| _io_cpu_store_pending_T_15; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_20 = _io_cpu_store_pending_T_19 \| _io_cpu_store_pending_T_16; // @[package.scala:16:47, :81:59] wire _io_cpu_store_pending_T_21 = _io_cpu_store_pending_T_11 \| _io_cpu_store_pending_T_20; // @[package.scala:81:59] wire _io_cpu_store_pending_T_22 = _io_cpu_store_pending_T_4 \| _io_cpu_store_pending_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _io_cpu_store_pending_T_23 = cached_grant_wait & _io_cpu_store_pending_T_22; // @[DCache.scala:223:34, :930:46] assign _io_cpu_store_pending_T_25 = _io_cpu_store_pending_T_23 \| _io_cpu_store_pending_T_24; // @[DCache.scala:930:{46,70,97}] assign io_cpu_store_pending_0 = _io_cpu_store_pending_T_25; // @[DCache.scala:101:7, :930:70] wire _s1_xcpt_valid_T_2 = ~s1_nack; // @[DCache.scala:185:28, :187:41, :932:68] wire s1_xcpt_valid = _s1_xcpt_valid_T_1 & _s1_xcpt_valid_T_2; // @[DCache.scala:932:{40,65,68}] reg io_cpu_s2_xcpt_REG; // @[DCache.scala:933:32] wire _io_cpu_s2_xcpt_T_miss = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_miss; // @[DCache.scala:342:24, :933:{24,32}] wire [31:0] _io_cpu_s2_xcpt_T_paddr = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_paddr : 32'h0; // @[DCache.scala:342:24, :933:{24,32}] wire [39:0] _io_cpu_s2_xcpt_T_gpa = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_gpa : 40'h0; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_pf_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_ld; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_pf_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_st; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_pf_inst = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_inst; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_ae_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_ld; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_ae_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_st; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_ae_inst = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_inst; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_ma_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ma_ld; // @[DCache.scala:342:24, :933:{24,32}] assign _io_cpu_s2_xcpt_T_ma_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ma_st; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_cacheable = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_cacheable; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_must_alloc = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_must_alloc; // @[DCache.scala:342:24, :933:{24,32}] wire _io_cpu_s2_xcpt_T_prefetchable = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_prefetchable; // @[DCache.scala:342:24, :933:{24,32}] wire [1:0] _io_cpu_s2_xcpt_T_size = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_size : 2'h0; // @[DCache.scala:342:24, :933:{24,32}] wire [4:0] _io_cpu_s2_xcpt_T_cmd = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_cmd : 5'h0; // @[DCache.scala:342:24, :933:{24,32}] assign io_cpu_s2_xcpt_pf_ld_0 = _io_cpu_s2_xcpt_T_pf_ld; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_pf_st_0 = _io_cpu_s2_xcpt_T_pf_st; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_ae_ld_0 = _io_cpu_s2_xcpt_T_ae_ld; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_ae_st_0 = _io_cpu_s2_xcpt_T_ae_st; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_ma_ld_0 = _io_cpu_s2_xcpt_T_ma_ld; // @[DCache.scala:101:7, :933:24] assign io_cpu_s2_xcpt_ma_st_0 = _io_cpu_s2_xcpt_T_ma_st; // @[DCache.scala:101:7, :933:24] reg [63:0] s2_uncached_data_word; // @[DCache.scala:947:40] reg doUncachedResp; // @[DCache.scala:948:31] assign io_cpu_resp_bits_replay_0 = doUncachedResp; // @[DCache.scala:101:7, :948:31] wire _io_cpu_resp_valid_T = s2_valid_hit_pre_data_ecc \| doUncachedResp; // @[DCache.scala:420:69, :948:31, :949:51] assign _io_cpu_resp_valid_T_2 = _io_cpu_resp_valid_T; // @[DCache.scala:949:{51,70}] assign io_cpu_resp_valid_0 = _io_cpu_resp_valid_T_2; // @[DCache.scala:101:7, :949:70] wire _io_cpu_replay_next_T_1 = _io_cpu_replay_next_T & grantIsUncachedData; // @[Decoupled.scala:51:35] assign _io_cpu_replay_next_T_3 = _io_cpu_replay_next_T_1; // @[DCache.scala:950:{39,62}] assign io_cpu_replay_next_0 = _io_cpu_replay_next_T_3; // @[DCache.scala:101:7, :950:62]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_29( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [27:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_54 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_72 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_74 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_78 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_80 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_84 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_86 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_90 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_92 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_first_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_first_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_wo_ready_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_wo_ready_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_interm_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_interm_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_opcodes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_opcodes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_sizes_set_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_sizes_set_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _c_probe_ack_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _c_probe_ack_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_1_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_2_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_3_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [27:0] _same_cycle_resp_WIRE_4_bits_address = 28'h0; // @[Bundles.scala:265:74] wire [27:0] _same_cycle_resp_WIRE_5_bits_address = 28'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_66 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_67 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_68 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_69 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_70 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_71 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_72 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_73 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_74 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_75 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_76 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_12 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_13 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'hB; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_31 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_37 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_32 = _source_ok_T_31 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_38 = _source_ok_T_37 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_7 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire _source_ok_T_43 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire _source_ok_T_44 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_50 = _source_ok_T_49 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_50 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [27:0] _is_aligned_T = {22'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 28'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_20 = _uncommonBits_T_20[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_26 = _uncommonBits_T_26[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_27 = _uncommonBits_T_27[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_32 = _uncommonBits_T_32[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_33 = _uncommonBits_T_33[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_55 = _uncommonBits_T_55[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_58 = _uncommonBits_T_58[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_59 = _uncommonBits_T_59[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_60 = _uncommonBits_T_60[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_61 = _uncommonBits_T_61[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_62 = _uncommonBits_T_62[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_64 = _uncommonBits_T_64[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_65 = _uncommonBits_T_65[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_66 = _uncommonBits_T_66[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_67 = _uncommonBits_T_67[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_68 = _uncommonBits_T_68[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_69 = _uncommonBits_T_69[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_70 = _uncommonBits_T_70[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_71 = _uncommonBits_T_71[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_72 = _uncommonBits_T_72[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_73 = _uncommonBits_T_73[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_74 = _uncommonBits_T_74[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_75 = _uncommonBits_T_75[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_76 = _uncommonBits_T_76[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_51 = io_in_d_bits_source_0 == 7'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_51; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_52 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_58 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_64 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_70 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_53 = _source_ok_T_52 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_55 = _source_ok_T_53; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_57; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_59 = _source_ok_T_58 == 5'h9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_63; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_65 = _source_ok_T_64 == 5'hA; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_69; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_71 = _source_ok_T_70 == 5'hB; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_73 = _source_ok_T_71; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_75 = _source_ok_T_73; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_75; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_76 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_82 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_88 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_77 = _source_ok_T_76 == 4'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_79 = _source_ok_T_77; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_81 = _source_ok_T_79; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_81; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_12 = _source_ok_uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_83 = _source_ok_T_82 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_85 = _source_ok_T_83; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_87 = _source_ok_T_85; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_6 = _source_ok_T_87; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_13 = _source_ok_uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_89 = _source_ok_T_88 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_91 = _source_ok_T_89; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_93 = _source_ok_T_91; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_7 = _source_ok_T_93; // @[Parameters.scala:1138:31] wire _source_ok_T_94 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_94; // @[Parameters.scala:1138:31] wire _source_ok_T_95 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_96 = _source_ok_T_95 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_97 = _source_ok_T_96 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_98 = _source_ok_T_97 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_99 = _source_ok_T_98 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_100 = _source_ok_T_99 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_101 = _source_ok_T_100 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_101 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1266 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1266; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1266; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [27:0] address; // @[Monitor.scala:391:22] wire _T_1339 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1339; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1339; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1339; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1192 = _T_1266 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1192 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1192 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1192 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1192 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1192 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1238 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1238 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1207 = _T_1339 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1207 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1207 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1207 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1310 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1310 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1292 = _T_1339 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1292 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1292 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1292 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File TilelinkAdapters.scala: package constellation.protocol import chisel3._ import chisel3.util._ import constellation.channel._ import constellation.noc._ import constellation.soc.{CanAttachToGlobalNoC} import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import scala.collection.immutable.{ListMap} abstract class TLChannelToNoC[T <: TLChannel](gen: => T, edge: TLEdge, idToEgress: Int => Int)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Flipped(Decoupled(gen)) val flit = Decoupled(new IngressFlit(flitWidth)) }) def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B // convert decoupled to irrevocable val q = Module(new Queue(gen, 1, pipe=true, flow=true)) val protocol = q.io.deq val has_body = Wire(Bool()) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val head = edge.first(protocol.bits, protocol.fire) val tail = edge.last(protocol.bits, protocol.fire) def requestOH: Seq[Bool] val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt)) val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt)) val is_body = RegInit(false.B) io.flit.valid := protocol.valid protocol.ready := io.flit.ready && (is_body \|\| !has_body) io.flit.bits.head := head && !is_body io.flit.bits.tail := tail && (is_body \|\| !has_body) io.flit.bits.egress_id := Mux1H(requestOH.zipWithIndex.map { case (r, i) => r -> idToEgress(i).U }) io.flit.bits.payload := Mux(is_body, body, const) when (io.flit.fire && io.flit.bits.head) { is_body := true.B } when (io.flit.fire && io.flit.bits.tail) { is_body := false.B } } abstract class TLChannelFromNoC[T <: TLChannel](gen: => T)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Decoupled(gen) val flit = Flipped(Decoupled(new EgressFlit(flitWidth))) }) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) val protocol = Wire(Decoupled(gen)) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val is_const = RegInit(true.B) val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W)) val const = Mux(io.flit.bits.head, io.flit.bits.payload, const_reg) io.flit.ready := (is_const && !io.flit.bits.tail) \|\| protocol.ready protocol.valid := (!is_const \|\| io.flit.bits.tail) && io.flit.valid def assign(i: UInt, sigs: Seq[Data]) = { var t = i for (s <- sigs.reverse) { s := t.asTypeOf(s.cloneType) t = t >> s.getWidth } } assign(const, const_fields) assign(io.flit.bits.payload, body_fields) when (io.flit.fire && io.flit.bits.head) { is_const := false.B; const_reg := io.flit.bits.payload } when (io.flit.fire && io.flit.bits.tail) { is_const := true.B } } trait HasAddressDecoder { // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) val edgeIn: TLEdge val edgesOut: Seq[TLEdge] lazy val reacheableIO = edgesOut.map { mp => edgeIn.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} }.toVector lazy val releaseIO = (edgesOut zip reacheableIO).map { case (mp, reachable) => reachable && edgeIn.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector def outputPortFn(connectIO: Seq[Boolean]) = { val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectIO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_\|\|_)) } } class TLAToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToAEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleA(bundle), edgeIn, slaveToAEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) \|\| (~protocol.bits.mask =/= 0.U) lazy val connectAIO = reacheableIO lazy val requestOH = outputPortFn(connectAIO).zipWithIndex.map { case (o, j) => connectAIO(j).B && (unique(connectAIO) \|\| o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source \| sourceStart.U } class TLAFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleA(bundle))(p) { io.protocol <> protocol when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLBToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToBIngress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleB(bundle), edgeOut, masterToBIngress)(p) { has_body := edgeOut.hasData(protocol.bits) \|\| (~protocol.bits.mask =/= 0.U) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol } class TLBFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleB(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLCToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToCEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleC(bundle), edgeIn, slaveToCEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) lazy val connectCIO = releaseIO lazy val requestOH = outputPortFn(connectCIO).zipWithIndex.map { case (o, j) => connectCIO(j).B && (unique(connectCIO) \|\| o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source \| sourceStart.U } class TLCFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleC(bundle))(p) { io.protocol <> protocol } class TLDToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToDIngress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleD(bundle), edgeOut, masterToDIngress)(p) { has_body := edgeOut.hasData(protocol.bits) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol q.io.enq.bits.sink := io.protocol.bits.sink \| sourceStart.U } class TLDFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleD(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) } class TLEToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToEEgress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleE(bundle), edgeIn, slaveToEEgress)(p) { has_body := edgeIn.hasData(protocol.bits) lazy val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) lazy val requestOH = outputIdRanges.map { o => o.contains(protocol.bits.sink) } q.io.enq <> io.protocol } class TLEFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleE(bundle))(p) { io.protocol <> protocol io.protocol.bits.sink := trim(protocol.bits.sink, sourceSize) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLDToNoC_3( // @[TilelinkAdapters.scala:171:7] input clock, // @[TilelinkAdapters.scala:171:7] input reset, // @[TilelinkAdapters.scala:171:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [1:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [4:0] io_protocol_bits_sink, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_denied, // @[TilelinkAdapters.scala:19:14] input [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [64:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [3:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [1:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [5:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [4:0] _q_io_deq_bits_sink; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_denied; // @[TilelinkAdapters.scala:26:17] wire [63:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [20:0] _tail_beats1_decode_T = 21'h3F << _q_io_deq_bits_size; // @[package.scala:243:71] reg [2:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire [2:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[5:3]) : 3'h0; // @[package.scala:243:{46,71,76}] reg [2:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire q_io_deq_ready = io_flit_ready & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:106:36] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 3'h1 \| tail_beats1 == 3'h0) & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:106:36, :221:14, :229:27, :232:{25,33,43}] wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:171:7] if (reset) begin // @[TilelinkAdapters.scala:171:7] head_counter <= 3'h0; // @[Edges.scala:229:27] tail_counter <= 3'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :171:7] end else begin // @[TilelinkAdapters.scala:171:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[5:3]) : 3'h0) : head_counter - 3'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 3'h0 ? tail_beats1 : tail_counter - 3'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 \| is_body); // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v3.common.{MicroOp} import boom.v3.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask) } def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U} def apply(ip: UInt, isel: UInt): SInt = { val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt } } /* * Object to get the FP rounding mode out of a packed immediate. / object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } } /* * Object to get the FP function fype from a packed immediate. * Note: only works if !(IS_B or IS_S) / object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v3.common.BoomModule()(p) with boom.v3.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop) uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop)) io.deq.bits := out io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop) // For flow queue behavior. if (flow) { when (io.empty) { io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop) io.deq.bits := io.enq.bits io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) do_deq := false.B when (io.deq.ready) { do_enq := false.B } } } private val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } File tage.scala: package boom.v3.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc} import scala.math.min class TageResp extends Bundle { val ctr = UInt(3.W) val u = UInt(2.W) } class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int) (implicit p: Parameters) extends BoomModule()(p) with HasBoomFrontendParameters { require(histLength <= globalHistoryLength) val nWrBypassEntries = 2 val io = IO( new Bundle { val f1_req_valid = Input(Bool()) val f1_req_pc = Input(UInt(vaddrBitsExtended.W)) val f1_req_ghist = Input(UInt(globalHistoryLength.W)) val f3_resp = Output(Vec(bankWidth, Valid(new TageResp))) val update_mask = Input(Vec(bankWidth, Bool())) val update_taken = Input(Vec(bankWidth, Bool())) val update_alloc = Input(Vec(bankWidth, Bool())) val update_old_ctr = Input(Vec(bankWidth, UInt(3.W))) val update_pc = Input(UInt()) val update_hist = Input(UInt()) val update_u_mask = Input(Vec(bankWidth, Bool())) val update_u = Input(Vec(bankWidth, UInt(2.W))) }) def compute_folded_hist(hist: UInt, l: Int) = { val nChunks = (histLength + l - 1) / l val hist_chunks = (0 until nChunks) map {i => hist(min((i+1)l, histLength)-1, il) } hist_chunks.reduce(_^_) } def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = { val idx_history = compute_folded_hist(hist, log2Ceil(nRows)) val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0) val tag_history = compute_folded_hist(hist, tagSz) val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0) (idx, tag) } def inc_ctr(ctr: UInt, taken: Bool): UInt = { Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U), Mux(ctr === 7.U, 7.U, ctr + 1.U)) } val doing_reset = RegInit(true.B) val reset_idx = RegInit(0.U(log2Ceil(nRows).W)) reset_idx := reset_idx + doing_reset when (reset_idx === (nRows-1).U) { doing_reset := false.B } class TageEntry extends Bundle { val valid = Bool() // TODO: Remove this valid bit val tag = UInt(tagSz.W) val ctr = UInt(3.W) } val tageEntrySz = 1 + tagSz + 3 val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist) val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool())) val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool())) val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W))) val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz)) val s2_tag = RegNext(s1_tag) val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry))) val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid) val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid) val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset)) for (w <- 0 until bankWidth) { // This bit indicates the TAGE table matched here io.f3_resp(w).valid := RegNext(s2_req_rhits(w)) io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w))) io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr) } val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W)) when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U } val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod) val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist) val update_wdata = Wire(Vec(bankWidth, new TageEntry)) table.write( Mux(doing_reset, reset_idx , update_idx), Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))), Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools ) val update_hi_wdata = Wire(Vec(bankWidth, Bool())) hi_us.write( Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)), Mux(doing_reset \|\| doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata), Mux(doing_reset \|\| doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools ) val update_lo_wdata = Wire(Vec(bankWidth, Bool())) lo_us.write( Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)), Mux(doing_reset \|\| doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata), Mux(doing_reset \|\| doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools ) val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W))) val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W))) val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W)))) val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W)) val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i => !doing_reset && wrbypass_tags(i) === update_tag && wrbypass_idxs(i) === update_idx }) val wrbypass_hit = wrbypass_hits.reduce(_\|\|_) val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits) for (w <- 0 until bankWidth) { update_wdata(w).ctr := Mux(io.update_alloc(w), Mux(io.update_taken(w), 4.U, 3.U ), Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)), inc_ctr(io.update_old_ctr(w), io.update_taken(w)) ) ) update_wdata(w).valid := true.B update_wdata(w).tag := update_tag update_hi_wdata(w) := io.update_u(w)(1) update_lo_wdata(w) := io.update_u(w)(0) } when (io.update_mask.reduce(_\|\|_)) { when (wrbypass_hits.reduce(_\|\|_)) { wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr)) } .otherwise { wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr)) wrbypass_tags(wrbypass_enq_idx) := update_tag wrbypass_idxs(wrbypass_enq_idx) := update_idx wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries) } } } case class BoomTageParams( // nSets, histLen, tagSz tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7), ( 128, 4, 7), ( 256, 8, 8), ( 256, 16, 8), ( 128, 32, 9), ( 128, 64, 9)), uBitPeriod: Int = 2048 ) class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p) { val tageUBitPeriod = params.uBitPeriod val tageNTables = params.tableInfo.size class TageMeta extends Bundle { val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W))) val alt_differs = Vec(bankWidth, Output(Bool())) val provider_u = Vec(bankWidth, Output(UInt(2.W))) val provider_ctr = Vec(bankWidth, Output(UInt(3.W))) val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W))) } val f3_meta = Wire(new TageMeta) override val metaSz = f3_meta.asUInt.getWidth require(metaSz <= bpdMaxMetaLength) def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = { Mux(!alt_differs, u, Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U), Mux(u === 3.U, 3.U, u + 1.U))) } val tt = params.tableInfo map { case (n, l, s) => { val t = Module(new TageTable(n, s, l, params.uBitPeriod)) t.io.f1_req_valid := RegNext(io.f0_valid) t.io.f1_req_pc := RegNext(io.f0_pc) t.io.f1_req_ghist := io.f1_ghist (t, t.mems) } } val tables = tt.map(_._1) val mems = tt.map(_._2).flatten val f3_resps = VecInit(tables.map(_.io.f3_resp)) val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta) val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) & Fill(bankWidth, s1_update.bits.cfi_mispredicted) val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool())))) val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W))))) val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool()))) val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W)))) val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool()))) val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W)))) s1_update_taken := DontCare s1_update_old_ctr := DontCare s1_update_alloc := DontCare s1_update_u := DontCare for (w <- 0 until bankWidth) { var altpred = io.resp_in(0).f3(w).taken val final_altpred = WireInit(io.resp_in(0).f3(w).taken) var provided = false.B var provider = 0.U io.resp.f3(w).taken := io.resp_in(0).f3(w).taken for (i <- 0 until tageNTables) { val hit = f3_resps(i)(w).valid val ctr = f3_resps(i)(w).bits.ctr when (hit) { io.resp.f3(w).taken := Mux(ctr === 3.U \|\| ctr === 4.U, altpred, ctr(2)) final_altpred := altpred } provided = provided \|\| hit provider = Mux(hit, i.U, provider) altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred) } f3_meta.provider(w).valid := provided f3_meta.provider(w).bits := provider f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr // Create a mask of tables which did not hit our query, and also contain useless entries // and also uses a longer history than the provider val allocatable_slots = ( VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt & ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided)) ) val alloc_lfsr = random.LFSR(tageNTables max 2) val first_entry = PriorityEncoder(allocatable_slots) val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr) val alloc_entry = Mux(allocatable_slots(masked_entry), masked_entry, first_entry) f3_meta.allocate(w).valid := allocatable_slots =/= 0.U f3_meta.allocate(w).bits := alloc_entry val update_was_taken = (s1_update.bits.cfi_idx.valid && (s1_update.bits.cfi_idx.bits === w.U) && s1_update.bits.cfi_taken) when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) { when (s1_update_meta.provider(w).valid) { val provider = s1_update_meta.provider(w).bits s1_update_mask(provider)(w) := true.B s1_update_u_mask(provider)(w) := true.B val new_u = inc_u(s1_update_meta.provider_u(w), s1_update_meta.alt_differs(w), s1_update_mispredict_mask(w)) s1_update_u (provider)(w) := new_u s1_update_taken (provider)(w) := update_was_taken s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w) s1_update_alloc (provider)(w) := false.B } } } when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) { val idx = s1_update.bits.cfi_idx.bits val allocate = s1_update_meta.allocate(idx) when (allocate.valid) { s1_update_mask (allocate.bits)(idx) := true.B s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken s1_update_alloc(allocate.bits)(idx) := true.B s1_update_u_mask(allocate.bits)(idx) := true.B s1_update_u (allocate.bits)(idx) := 0.U } .otherwise { val provider = s1_update_meta.provider(idx) val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U) for (i <- 0 until tageNTables) { when (decr_mask(i)) { s1_update_u_mask(i)(idx) := true.B s1_update_u (i)(idx) := 0.U } } } } for (i <- 0 until tageNTables) { for (w <- 0 until bankWidth) { tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w)) tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w)) tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w)) tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w)) tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w)) tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w)) } tables(i).io.update_pc := RegNext(s1_update.bits.pc) tables(i).io.update_hist := RegNext(s1_update.bits.ghist) } //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0)) io.f3_meta := f3_meta.asUInt }	module TageTable_6( // @[tage.scala:24:7] input clock, // @[tage.scala:24:7] input reset, // @[tage.scala:24:7] input io_f1_req_valid, // @[tage.scala:31:14] input [39:0] io_f1_req_pc, // @[tage.scala:31:14] input [63:0] io_f1_req_ghist, // @[tage.scala:31:14] output io_f3_resp_0_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_0_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_0_bits_u, // @[tage.scala:31:14] output io_f3_resp_1_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_1_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_1_bits_u, // @[tage.scala:31:14] output io_f3_resp_2_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_2_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_2_bits_u, // @[tage.scala:31:14] output io_f3_resp_3_valid, // @[tage.scala:31:14] output [2:0] io_f3_resp_3_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f3_resp_3_bits_u, // @[tage.scala:31:14] input io_update_mask_0, // @[tage.scala:31:14] input io_update_mask_1, // @[tage.scala:31:14] input io_update_mask_2, // @[tage.scala:31:14] input io_update_mask_3, // @[tage.scala:31:14] input io_update_taken_0, // @[tage.scala:31:14] input io_update_taken_1, // @[tage.scala:31:14] input io_update_taken_2, // @[tage.scala:31:14] input io_update_taken_3, // @[tage.scala:31:14] input io_update_alloc_0, // @[tage.scala:31:14] input io_update_alloc_1, // @[tage.scala:31:14] input io_update_alloc_2, // @[tage.scala:31:14] input io_update_alloc_3, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_0, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_1, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_2, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_3, // @[tage.scala:31:14] input [39:0] io_update_pc, // @[tage.scala:31:14] input [63:0] io_update_hist, // @[tage.scala:31:14] input io_update_u_mask_0, // @[tage.scala:31:14] input io_update_u_mask_1, // @[tage.scala:31:14] input io_update_u_mask_2, // @[tage.scala:31:14] input io_update_u_mask_3, // @[tage.scala:31:14] input [1:0] io_update_u_0, // @[tage.scala:31:14] input [1:0] io_update_u_1, // @[tage.scala:31:14] input [1:0] io_update_u_2, // @[tage.scala:31:14] input [1:0] io_update_u_3 // @[tage.scala:31:14] ); wire lo_us_MPORT_2_data_3; // @[tage.scala:137:8] wire lo_us_MPORT_2_data_2; // @[tage.scala:137:8] wire lo_us_MPORT_2_data_1; // @[tage.scala:137:8] wire lo_us_MPORT_2_data_0; // @[tage.scala:137:8] wire hi_us_MPORT_1_data_3; // @[tage.scala:130:8] wire hi_us_MPORT_1_data_2; // @[tage.scala:130:8] wire hi_us_MPORT_1_data_1; // @[tage.scala:130:8] wire hi_us_MPORT_1_data_0; // @[tage.scala:130:8] wire [10:0] table_MPORT_data_3; // @[tage.scala:123:8] wire [10:0] table_MPORT_data_2; // @[tage.scala:123:8] wire [10:0] table_MPORT_data_1; // @[tage.scala:123:8] wire [10:0] table_MPORT_data_0; // @[tage.scala:123:8] wire _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:87] wire _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:87] wire _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:87] wire _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:87] wire [2:0] _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:87] wire [43:0] _table_R0_data; // @[tage.scala:91:27] wire [3:0] _lo_us_R0_data; // @[tage.scala:90:27] wire [3:0] _hi_us_R0_data; // @[tage.scala:89:27] wire io_f1_req_valid_0 = io_f1_req_valid; // @[tage.scala:24:7] wire [39:0] io_f1_req_pc_0 = io_f1_req_pc; // @[tage.scala:24:7] wire [63:0] io_f1_req_ghist_0 = io_f1_req_ghist; // @[tage.scala:24:7] wire io_update_mask_0_0 = io_update_mask_0; // @[tage.scala:24:7] wire io_update_mask_1_0 = io_update_mask_1; // @[tage.scala:24:7] wire io_update_mask_2_0 = io_update_mask_2; // @[tage.scala:24:7] wire io_update_mask_3_0 = io_update_mask_3; // @[tage.scala:24:7] wire io_update_taken_0_0 = io_update_taken_0; // @[tage.scala:24:7] wire io_update_taken_1_0 = io_update_taken_1; // @[tage.scala:24:7] wire io_update_taken_2_0 = io_update_taken_2; // @[tage.scala:24:7] wire io_update_taken_3_0 = io_update_taken_3; // @[tage.scala:24:7] wire io_update_alloc_0_0 = io_update_alloc_0; // @[tage.scala:24:7] wire io_update_alloc_1_0 = io_update_alloc_1; // @[tage.scala:24:7] wire io_update_alloc_2_0 = io_update_alloc_2; // @[tage.scala:24:7] wire io_update_alloc_3_0 = io_update_alloc_3; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_0_0 = io_update_old_ctr_0; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_1_0 = io_update_old_ctr_1; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_2_0 = io_update_old_ctr_2; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_3_0 = io_update_old_ctr_3; // @[tage.scala:24:7] wire [39:0] io_update_pc_0 = io_update_pc; // @[tage.scala:24:7] wire [63:0] io_update_hist_0 = io_update_hist; // @[tage.scala:24:7] wire io_update_u_mask_0_0 = io_update_u_mask_0; // @[tage.scala:24:7] wire io_update_u_mask_1_0 = io_update_u_mask_1; // @[tage.scala:24:7] wire io_update_u_mask_2_0 = io_update_u_mask_2; // @[tage.scala:24:7] wire io_update_u_mask_3_0 = io_update_u_mask_3; // @[tage.scala:24:7] wire [1:0] io_update_u_0_0 = io_update_u_0; // @[tage.scala:24:7] wire [1:0] io_update_u_1_0 = io_update_u_1; // @[tage.scala:24:7] wire [1:0] io_update_u_2_0 = io_update_u_2; // @[tage.scala:24:7] wire [1:0] io_update_u_3_0 = io_update_u_3; // @[tage.scala:24:7] wire update_wdata_0_valid = 1'h1; // @[tage.scala:119:26] wire update_wdata_1_valid = 1'h1; // @[tage.scala:119:26] wire update_wdata_2_valid = 1'h1; // @[tage.scala:119:26] wire update_wdata_3_valid = 1'h1; // @[tage.scala:119:26] wire [2:0] io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_0_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_0_valid_0; // @[tage.scala:24:7] wire [2:0] io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_1_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_1_valid_0; // @[tage.scala:24:7] wire [2:0] io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_2_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_2_valid_0; // @[tage.scala:24:7] wire [2:0] io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f3_resp_3_bits_u_0; // @[tage.scala:24:7] wire io_f3_resp_3_valid_0; // @[tage.scala:24:7] reg doing_reset; // @[tage.scala:72:28] reg [6:0] reset_idx; // @[tage.scala:73:26] wire [7:0] _reset_idx_T = {1'h0, reset_idx} + {7'h0, doing_reset}; // @[tage.scala:72:28, :73:26, :74:26] wire [6:0] _reset_idx_T_1 = _reset_idx_T[6:0]; // @[tage.scala:74:26] wire [1:0] idx_history = io_f1_req_ghist_0[1:0]; // @[tage.scala:24:7, :53:11] wire [1:0] tag_history = io_f1_req_ghist_0[1:0]; // @[tage.scala:24:7, :53:11] wire [36:0] _idx_T = {io_f1_req_pc_0[39:5], io_f1_req_pc_0[4:3] ^ idx_history}; // @[frontend.scala:162:35] wire [6:0] s1_hashed_idx = _idx_T[6:0]; // @[tage.scala:60:{29,43}] wire [6:0] _s2_req_rtage_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :97:40] wire [6:0] _s2_req_rhius_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :98:32] wire [6:0] _s2_req_rlous_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :99:32] wire [29:0] _tag_T = io_f1_req_pc_0[39:10]; // @[frontend.scala:162:35] wire [29:0] _tag_T_1 = {_tag_T[29:2], _tag_T[1:0] ^ tag_history}; // @[tage.scala:53:11, :62:{30,50}] wire [6:0] s1_tag = _tag_T_1[6:0]; // @[tage.scala:62:{50,64}] wire [10:0] _s2_req_rtage_WIRE_2 = _table_R0_data[10:0]; // @[tage.scala:91:27, :97:87] wire [10:0] _s2_req_rtage_WIRE_4 = _table_R0_data[21:11]; // @[tage.scala:91:27, :97:87] wire [10:0] _s2_req_rtage_WIRE_6 = _table_R0_data[32:22]; // @[tage.scala:91:27, :97:87] wire [10:0] _s2_req_rtage_WIRE_8 = _table_R0_data[43:33]; // @[tage.scala:91:27, :97:87] reg [6:0] s2_tag; // @[tage.scala:95:29] wire _s2_req_rtage_T_2; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_T_1; // @[tage.scala:97:87] wire s2_req_rtage_0_valid = _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T; // @[tage.scala:97:87] wire [6:0] s2_req_rtage_0_tag = _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_0_ctr = _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T = _s2_req_rtage_WIRE_2[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_1_ctr = _s2_req_rtage_T; // @[tage.scala:97:87] assign _s2_req_rtage_T_1 = _s2_req_rtage_WIRE_2[9:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_1_tag = _s2_req_rtage_T_1; // @[tage.scala:97:87] assign _s2_req_rtage_T_2 = _s2_req_rtage_WIRE_2[10]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_1_valid = _s2_req_rtage_T_2; // @[tage.scala:97:87] wire _s2_req_rtage_T_5; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_T_4; // @[tage.scala:97:87] wire s2_req_rtage_1_valid = _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T_3; // @[tage.scala:97:87] wire [6:0] s2_req_rtage_1_tag = _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_1_ctr = _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T_3 = _s2_req_rtage_WIRE_4[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_3_ctr = _s2_req_rtage_T_3; // @[tage.scala:97:87] assign _s2_req_rtage_T_4 = _s2_req_rtage_WIRE_4[9:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_3_tag = _s2_req_rtage_T_4; // @[tage.scala:97:87] assign _s2_req_rtage_T_5 = _s2_req_rtage_WIRE_4[10]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_3_valid = _s2_req_rtage_T_5; // @[tage.scala:97:87] wire _s2_req_rtage_T_8; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_T_7; // @[tage.scala:97:87] wire s2_req_rtage_2_valid = _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T_6; // @[tage.scala:97:87] wire [6:0] s2_req_rtage_2_tag = _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_2_ctr = _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T_6 = _s2_req_rtage_WIRE_6[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_5_ctr = _s2_req_rtage_T_6; // @[tage.scala:97:87] assign _s2_req_rtage_T_7 = _s2_req_rtage_WIRE_6[9:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_5_tag = _s2_req_rtage_T_7; // @[tage.scala:97:87] assign _s2_req_rtage_T_8 = _s2_req_rtage_WIRE_6[10]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_5_valid = _s2_req_rtage_T_8; // @[tage.scala:97:87] wire _s2_req_rtage_T_11; // @[tage.scala:97:87] wire [6:0] _s2_req_rtage_T_10; // @[tage.scala:97:87] wire s2_req_rtage_3_valid = _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:{29,87}] wire [2:0] _s2_req_rtage_T_9; // @[tage.scala:97:87] wire [6:0] s2_req_rtage_3_tag = _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:{29,87}] wire [2:0] s2_req_rtage_3_ctr = _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:{29,87}] assign _s2_req_rtage_T_9 = _s2_req_rtage_WIRE_8[2:0]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_7_ctr = _s2_req_rtage_T_9; // @[tage.scala:97:87] assign _s2_req_rtage_T_10 = _s2_req_rtage_WIRE_8[9:3]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_7_tag = _s2_req_rtage_T_10; // @[tage.scala:97:87] assign _s2_req_rtage_T_11 = _s2_req_rtage_WIRE_8[10]; // @[tage.scala:97:87] assign _s2_req_rtage_WIRE_7_valid = _s2_req_rtage_T_11; // @[tage.scala:97:87] wire _s2_req_rhits_T = s2_req_rtage_0_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_1 = s2_req_rtage_0_valid & _s2_req_rhits_T; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_2 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_3 = _s2_req_rhits_T_1 & _s2_req_rhits_T_2; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_0 = _s2_req_rhits_T_3; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_4 = s2_req_rtage_1_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_5 = s2_req_rtage_1_valid & _s2_req_rhits_T_4; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_6 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_7 = _s2_req_rhits_T_5 & _s2_req_rhits_T_6; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_1 = _s2_req_rhits_T_7; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_8 = s2_req_rtage_2_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_9 = s2_req_rtage_2_valid & _s2_req_rhits_T_8; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_10 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_11 = _s2_req_rhits_T_9 & _s2_req_rhits_T_10; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_2 = _s2_req_rhits_T_11; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_12 = s2_req_rtage_3_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69] wire _s2_req_rhits_T_13 = s2_req_rtage_3_valid & _s2_req_rhits_T_12; // @[tage.scala:97:29, :100:{60,69}] wire _s2_req_rhits_T_14 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_15 = _s2_req_rhits_T_13 & _s2_req_rhits_T_14; // @[tage.scala:100:{60,80,83}] wire s2_req_rhits_3 = _s2_req_rhits_T_15; // @[tage.scala:100:{29,80}] reg io_f3_resp_0_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_0_valid_0 = io_f3_resp_0_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_0_bits_u_T = {_hi_us_R0_data[0], _lo_us_R0_data[0]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_0_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_0_bits_u_0 = io_f3_resp_0_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_0_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_0_bits_ctr_0 = io_f3_resp_0_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg io_f3_resp_1_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_1_valid_0 = io_f3_resp_1_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_1_bits_u_T = {_hi_us_R0_data[1], _lo_us_R0_data[1]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_1_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_1_bits_u_0 = io_f3_resp_1_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_1_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_1_bits_ctr_0 = io_f3_resp_1_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg io_f3_resp_2_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_2_valid_0 = io_f3_resp_2_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_2_bits_u_T = {_hi_us_R0_data[2], _lo_us_R0_data[2]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_2_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_2_bits_u_0 = io_f3_resp_2_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_2_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_2_bits_ctr_0 = io_f3_resp_2_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg io_f3_resp_3_valid_REG; // @[tage.scala:104:38] assign io_f3_resp_3_valid_0 = io_f3_resp_3_valid_REG; // @[tage.scala:24:7, :104:38] wire [1:0] _io_f3_resp_3_bits_u_T = {_hi_us_R0_data[3], _lo_us_R0_data[3]}; // @[tage.scala:89:27, :90:27, :105:42] reg [1:0] io_f3_resp_3_bits_u_REG; // @[tage.scala:105:38] assign io_f3_resp_3_bits_u_0 = io_f3_resp_3_bits_u_REG; // @[tage.scala:24:7, :105:38] reg [2:0] io_f3_resp_3_bits_ctr_REG; // @[tage.scala:106:38] assign io_f3_resp_3_bits_ctr_0 = io_f3_resp_3_bits_ctr_REG; // @[tage.scala:24:7, :106:38] reg [18:0] clear_u_ctr; // @[tage.scala:109:28] wire [19:0] _clear_u_ctr_T = {1'h0, clear_u_ctr} + 20'h1; // @[tage.scala:109:28, :110:85] wire [18:0] _clear_u_ctr_T_1 = _clear_u_ctr_T[18:0]; // @[tage.scala:110:85] wire [10:0] _doing_clear_u_T = clear_u_ctr[10:0]; // @[tage.scala:109:28, :112:34] wire doing_clear_u = _doing_clear_u_T == 11'h0; // @[tage.scala:112:{34,61}] wire _doing_clear_u_hi_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:54] wire _doing_clear_u_lo_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:54, :114:54] wire _doing_clear_u_hi_T_1 = _doing_clear_u_hi_T; // @[tage.scala:113:{54,95}] wire doing_clear_u_hi = doing_clear_u & _doing_clear_u_hi_T_1; // @[tage.scala:112:61, :113:{40,95}] wire _doing_clear_u_lo_T_1 = ~_doing_clear_u_lo_T; // @[tage.scala:114:{54,95}] wire doing_clear_u_lo = doing_clear_u & _doing_clear_u_lo_T_1; // @[tage.scala:112:61, :114:{40,95}] wire [7:0] clear_u_idx = clear_u_ctr[18:11]; // @[tage.scala:109:28, :115:33] wire [1:0] idx_history_1 = io_update_hist_0[1:0]; // @[tage.scala:24:7, :53:11] wire [1:0] tag_history_1 = io_update_hist_0[1:0]; // @[tage.scala:24:7, :53:11] wire [36:0] _idx_T_1 = {io_update_pc_0[39:5], io_update_pc_0[4:3] ^ idx_history_1}; // @[frontend.scala:162:35] wire [6:0] update_idx = _idx_T_1[6:0]; // @[tage.scala:60:{29,43}] wire [29:0] _tag_T_2 = io_update_pc_0[39:10]; // @[frontend.scala:162:35] wire [29:0] _tag_T_3 = {_tag_T_2[29:2], _tag_T_2[1:0] ^ tag_history_1}; // @[tage.scala:53:11, :62:{30,50}] wire [6:0] update_tag = _tag_T_3[6:0]; // @[tage.scala:62:{50,64}] wire [6:0] update_wdata_0_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [6:0] update_wdata_1_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [6:0] update_wdata_2_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [6:0] update_wdata_3_tag = update_tag; // @[tage.scala:62:64, :119:26] wire [2:0] _update_wdata_0_ctr_T_22; // @[tage.scala:155:33] wire [2:0] _update_wdata_1_ctr_T_22; // @[tage.scala:155:33] wire [2:0] _update_wdata_2_ctr_T_22; // @[tage.scala:155:33] wire [2:0] _update_wdata_3_ctr_T_22; // @[tage.scala:155:33] wire [2:0] update_wdata_0_ctr; // @[tage.scala:119:26] wire [2:0] update_wdata_1_ctr; // @[tage.scala:119:26] wire [2:0] update_wdata_2_ctr; // @[tage.scala:119:26] wire [2:0] update_wdata_3_ctr; // @[tage.scala:119:26] wire [7:0] hi = {1'h1, update_wdata_0_tag}; // @[tage.scala:119:26, :123:102] wire [7:0] hi_1 = {1'h1, update_wdata_1_tag}; // @[tage.scala:119:26, :123:102] wire [7:0] hi_2 = {1'h1, update_wdata_2_tag}; // @[tage.scala:119:26, :123:102] wire [7:0] hi_3 = {1'h1, update_wdata_3_tag}; // @[tage.scala:119:26, :123:102] assign table_MPORT_data_0 = doing_reset ? 11'h0 : {hi, update_wdata_0_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] assign table_MPORT_data_1 = doing_reset ? 11'h0 : {hi_1, update_wdata_1_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] assign table_MPORT_data_2 = doing_reset ? 11'h0 : {hi_2, update_wdata_2_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] assign table_MPORT_data_3 = doing_reset ? 11'h0 : {hi_3, update_wdata_3_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}] wire [1:0] lo = {io_update_mask_1_0, io_update_mask_0_0}; // @[tage.scala:24:7, :124:90] wire [1:0] hi_4 = {io_update_mask_3_0, io_update_mask_2_0}; // @[tage.scala:24:7, :124:90] wire _update_hi_wdata_0_T; // @[tage.scala:166:44] wire _update_hi_wdata_1_T; // @[tage.scala:166:44] wire _update_hi_wdata_2_T; // @[tage.scala:166:44] wire _update_hi_wdata_3_T; // @[tage.scala:166:44] wire update_hi_wdata_0; // @[tage.scala:127:29] wire update_hi_wdata_1; // @[tage.scala:127:29] wire update_hi_wdata_2; // @[tage.scala:127:29] wire update_hi_wdata_3; // @[tage.scala:127:29] wire _T_20 = doing_reset \| doing_clear_u_hi; // @[tage.scala:72:28, :113:40, :130:21] assign hi_us_MPORT_1_data_0 = ~_T_20 & update_hi_wdata_0; // @[tage.scala:127:29, :130:{8,21}] assign hi_us_MPORT_1_data_1 = ~_T_20 & update_hi_wdata_1; // @[tage.scala:127:29, :130:{8,21}] assign hi_us_MPORT_1_data_2 = ~_T_20 & update_hi_wdata_2; // @[tage.scala:127:29, :130:{8,21}] assign hi_us_MPORT_1_data_3 = ~_T_20 & update_hi_wdata_3; // @[tage.scala:127:29, :130:{8,21}] wire [1:0] _GEN = {io_update_u_mask_1_0, io_update_u_mask_0_0}; // @[tage.scala:24:7, :131:80] wire [1:0] lo_1; // @[tage.scala:131:80] assign lo_1 = _GEN; // @[tage.scala:131:80] wire [1:0] lo_2; // @[tage.scala:138:80] assign lo_2 = _GEN; // @[tage.scala:131:80, :138:80] wire [1:0] _GEN_0 = {io_update_u_mask_3_0, io_update_u_mask_2_0}; // @[tage.scala:24:7, :131:80] wire [1:0] hi_5; // @[tage.scala:131:80] assign hi_5 = _GEN_0; // @[tage.scala:131:80] wire [1:0] hi_6; // @[tage.scala:138:80] assign hi_6 = _GEN_0; // @[tage.scala:131:80, :138:80] wire _update_lo_wdata_0_T; // @[tage.scala:167:44] wire _update_lo_wdata_1_T; // @[tage.scala:167:44] wire _update_lo_wdata_2_T; // @[tage.scala:167:44] wire _update_lo_wdata_3_T; // @[tage.scala:167:44] wire update_lo_wdata_0; // @[tage.scala:134:29] wire update_lo_wdata_1; // @[tage.scala:134:29] wire update_lo_wdata_2; // @[tage.scala:134:29] wire update_lo_wdata_3; // @[tage.scala:134:29] wire _T_33 = doing_reset \| doing_clear_u_lo; // @[tage.scala:72:28, :114:40, :137:21] assign lo_us_MPORT_2_data_0 = ~_T_33 & update_lo_wdata_0; // @[tage.scala:134:29, :137:{8,21}] assign lo_us_MPORT_2_data_1 = ~_T_33 & update_lo_wdata_1; // @[tage.scala:134:29, :137:{8,21}] assign lo_us_MPORT_2_data_2 = ~_T_33 & update_lo_wdata_2; // @[tage.scala:134:29, :137:{8,21}] assign lo_us_MPORT_2_data_3 = ~_T_33 & update_lo_wdata_3; // @[tage.scala:134:29, :137:{8,21}] reg [6:0] wrbypass_tags_0; // @[tage.scala:141:29] reg [6:0] wrbypass_tags_1; // @[tage.scala:141:29] reg [6:0] wrbypass_idxs_0; // @[tage.scala:142:29] reg [6:0] wrbypass_idxs_1; // @[tage.scala:142:29] reg [2:0] wrbypass_0_0; // @[tage.scala:143:29] reg [2:0] wrbypass_0_1; // @[tage.scala:143:29] reg [2:0] wrbypass_0_2; // @[tage.scala:143:29] reg [2:0] wrbypass_0_3; // @[tage.scala:143:29] reg [2:0] wrbypass_1_0; // @[tage.scala:143:29] reg [2:0] wrbypass_1_1; // @[tage.scala:143:29] reg [2:0] wrbypass_1_2; // @[tage.scala:143:29] reg [2:0] wrbypass_1_3; // @[tage.scala:143:29] reg wrbypass_enq_idx; // @[tage.scala:144:33] wire _wrbypass_hits_T = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5] wire _wrbypass_hits_T_1 = wrbypass_tags_0 == update_tag; // @[tage.scala:62:64, :141:29, :148:22] wire _wrbypass_hits_T_2 = _wrbypass_hits_T & _wrbypass_hits_T_1; // @[tage.scala:147:{5,18}, :148:22] wire _wrbypass_hits_T_3 = wrbypass_idxs_0 == update_idx; // @[tage.scala:60:43, :142:29, :149:22] wire _wrbypass_hits_T_4 = _wrbypass_hits_T_2 & _wrbypass_hits_T_3; // @[tage.scala:147:18, :148:37, :149:22] wire wrbypass_hits_0 = _wrbypass_hits_T_4; // @[tage.scala:146:33, :148:37] wire _wrbypass_hits_T_5 = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5] wire _wrbypass_hits_T_6 = wrbypass_tags_1 == update_tag; // @[tage.scala:62:64, :141:29, :148:22] wire _wrbypass_hits_T_7 = _wrbypass_hits_T_5 & _wrbypass_hits_T_6; // @[tage.scala:147:{5,18}, :148:22] wire _wrbypass_hits_T_8 = wrbypass_idxs_1 == update_idx; // @[tage.scala:60:43, :142:29, :149:22] wire _wrbypass_hits_T_9 = _wrbypass_hits_T_7 & _wrbypass_hits_T_8; // @[tage.scala:147:18, :148:37, :149:22] wire wrbypass_hits_1 = _wrbypass_hits_T_9; // @[tage.scala:146:33, :148:37] wire wrbypass_hit = wrbypass_hits_0 \| wrbypass_hits_1; // @[tage.scala:146:33, :151:48] wire wrbypass_hit_idx = ~wrbypass_hits_0; // @[Mux.scala:50:70] wire [2:0] _update_wdata_0_ctr_T = io_update_taken_0_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_0_ctr_T_1 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire [2:0] _GEN_1 = wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0; // @[Mux.scala:50:70] wire [2:0] _GEN_2 = wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1; // @[Mux.scala:50:70] wire [2:0] _GEN_3 = wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2; // @[Mux.scala:50:70] wire [2:0] _GEN_4 = wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3; // @[Mux.scala:50:70] wire _update_wdata_0_ctr_T_2 = _GEN_1 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_5 = {1'h0, _GEN_1}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_0_ctr_T_3 = _GEN_5 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_4 = _update_wdata_0_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_5 = _update_wdata_0_ctr_T_2 ? 3'h0 : _update_wdata_0_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_6 = &_GEN_1; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_0_ctr_T_7 = _GEN_5 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_8 = _update_wdata_0_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_9 = _update_wdata_0_ctr_T_6 ? 3'h7 : _update_wdata_0_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_10 = _update_wdata_0_ctr_T_1 ? _update_wdata_0_ctr_T_5 : _update_wdata_0_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_0_ctr_T_11 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_0_ctr_T_12 = io_update_old_ctr_0_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_6 = {1'h0, io_update_old_ctr_0_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_0_ctr_T_13 = _GEN_6 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_14 = _update_wdata_0_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_15 = _update_wdata_0_ctr_T_12 ? 3'h0 : _update_wdata_0_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_16 = &io_update_old_ctr_0_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_0_ctr_T_17 = _GEN_6 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_18 = _update_wdata_0_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_19 = _update_wdata_0_ctr_T_16 ? 3'h7 : _update_wdata_0_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_20 = _update_wdata_0_ctr_T_11 ? _update_wdata_0_ctr_T_15 : _update_wdata_0_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_0_ctr_T_21 = wrbypass_hit ? _update_wdata_0_ctr_T_10 : _update_wdata_0_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_0_ctr_T_22 = io_update_alloc_0_0 ? _update_wdata_0_ctr_T : _update_wdata_0_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_0_ctr = _update_wdata_0_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_0_T = io_update_u_0_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_0 = _update_hi_wdata_0_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_0_T = io_update_u_0_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_0 = _update_lo_wdata_0_T; // @[tage.scala:134:29, :167:44] wire [2:0] _update_wdata_1_ctr_T = io_update_taken_1_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_1_ctr_T_1 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_2 = _GEN_2 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_7 = {1'h0, _GEN_2}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_1_ctr_T_3 = _GEN_7 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_4 = _update_wdata_1_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_5 = _update_wdata_1_ctr_T_2 ? 3'h0 : _update_wdata_1_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_6 = &_GEN_2; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_1_ctr_T_7 = _GEN_7 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_8 = _update_wdata_1_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_9 = _update_wdata_1_ctr_T_6 ? 3'h7 : _update_wdata_1_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_10 = _update_wdata_1_ctr_T_1 ? _update_wdata_1_ctr_T_5 : _update_wdata_1_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_1_ctr_T_11 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_12 = io_update_old_ctr_1_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_8 = {1'h0, io_update_old_ctr_1_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_1_ctr_T_13 = _GEN_8 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_14 = _update_wdata_1_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_15 = _update_wdata_1_ctr_T_12 ? 3'h0 : _update_wdata_1_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_16 = &io_update_old_ctr_1_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_1_ctr_T_17 = _GEN_8 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_18 = _update_wdata_1_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_19 = _update_wdata_1_ctr_T_16 ? 3'h7 : _update_wdata_1_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_20 = _update_wdata_1_ctr_T_11 ? _update_wdata_1_ctr_T_15 : _update_wdata_1_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_1_ctr_T_21 = wrbypass_hit ? _update_wdata_1_ctr_T_10 : _update_wdata_1_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_1_ctr_T_22 = io_update_alloc_1_0 ? _update_wdata_1_ctr_T : _update_wdata_1_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_1_ctr = _update_wdata_1_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_1_T = io_update_u_1_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_1 = _update_hi_wdata_1_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_1_T = io_update_u_1_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_1 = _update_lo_wdata_1_T; // @[tage.scala:134:29, :167:44] wire [2:0] _update_wdata_2_ctr_T = io_update_taken_2_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_2_ctr_T_1 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_2 = _GEN_3 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_9 = {1'h0, _GEN_3}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_2_ctr_T_3 = _GEN_9 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_4 = _update_wdata_2_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_5 = _update_wdata_2_ctr_T_2 ? 3'h0 : _update_wdata_2_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_6 = &_GEN_3; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_2_ctr_T_7 = _GEN_9 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_8 = _update_wdata_2_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_9 = _update_wdata_2_ctr_T_6 ? 3'h7 : _update_wdata_2_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_10 = _update_wdata_2_ctr_T_1 ? _update_wdata_2_ctr_T_5 : _update_wdata_2_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_2_ctr_T_11 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_12 = io_update_old_ctr_2_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_10 = {1'h0, io_update_old_ctr_2_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_2_ctr_T_13 = _GEN_10 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_14 = _update_wdata_2_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_15 = _update_wdata_2_ctr_T_12 ? 3'h0 : _update_wdata_2_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_16 = &io_update_old_ctr_2_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_2_ctr_T_17 = _GEN_10 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_18 = _update_wdata_2_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_19 = _update_wdata_2_ctr_T_16 ? 3'h7 : _update_wdata_2_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_20 = _update_wdata_2_ctr_T_11 ? _update_wdata_2_ctr_T_15 : _update_wdata_2_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_2_ctr_T_21 = wrbypass_hit ? _update_wdata_2_ctr_T_10 : _update_wdata_2_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_2_ctr_T_22 = io_update_alloc_2_0 ? _update_wdata_2_ctr_T : _update_wdata_2_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_2_ctr = _update_wdata_2_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_2_T = io_update_u_2_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_2 = _update_hi_wdata_2_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_2_T = io_update_u_2_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_2 = _update_lo_wdata_2_T; // @[tage.scala:134:29, :167:44] wire [2:0] _update_wdata_3_ctr_T = io_update_taken_3_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10] wire _update_wdata_3_ctr_T_1 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_2 = _GEN_4 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_11 = {1'h0, _GEN_4}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_3_ctr_T_3 = _GEN_11 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_4 = _update_wdata_3_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_5 = _update_wdata_3_ctr_T_2 ? 3'h0 : _update_wdata_3_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_6 = &_GEN_4; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_3_ctr_T_7 = _GEN_11 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_8 = _update_wdata_3_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_9 = _update_wdata_3_ctr_T_6 ? 3'h7 : _update_wdata_3_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_10 = _update_wdata_3_ctr_T_1 ? _update_wdata_3_ctr_T_5 : _update_wdata_3_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_3_ctr_T_11 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_12 = io_update_old_ctr_3_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_12 = {1'h0, io_update_old_ctr_3_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_3_ctr_T_13 = _GEN_12 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_14 = _update_wdata_3_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_15 = _update_wdata_3_ctr_T_12 ? 3'h0 : _update_wdata_3_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_16 = &io_update_old_ctr_3_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_3_ctr_T_17 = _GEN_12 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_18 = _update_wdata_3_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_19 = _update_wdata_3_ctr_T_16 ? 3'h7 : _update_wdata_3_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_20 = _update_wdata_3_ctr_T_11 ? _update_wdata_3_ctr_T_15 : _update_wdata_3_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_3_ctr_T_21 = wrbypass_hit ? _update_wdata_3_ctr_T_10 : _update_wdata_3_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10] assign _update_wdata_3_ctr_T_22 = io_update_alloc_3_0 ? _update_wdata_3_ctr_T : _update_wdata_3_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10] assign update_wdata_3_ctr = _update_wdata_3_ctr_T_22; // @[tage.scala:119:26, :155:33] assign _update_hi_wdata_3_T = io_update_u_3_0[1]; // @[tage.scala:24:7, :166:44] assign update_hi_wdata_3 = _update_hi_wdata_3_T; // @[tage.scala:127:29, :166:44] assign _update_lo_wdata_3_T = io_update_u_3_0[0]; // @[tage.scala:24:7, :167:44] assign update_lo_wdata_3 = _update_lo_wdata_3_T; // @[tage.scala:134:29, :167:44] wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1; // @[util.scala:203:14] wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0]; // @[util.scala:203:14] wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1; // @[util.scala:203:{14,20}] wire _T_44 = io_update_mask_0_0 \| io_update_mask_1_0 \| io_update_mask_2_0 \| io_update_mask_3_0; // @[tage.scala:24:7, :170:32] wire _GEN_13 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx; // @[Mux.scala:50:70] wire _GEN_14 = ~_T_44 \| wrbypass_hit \| wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39] wire _GEN_15 = ~_T_44 \| wrbypass_hit \| ~wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39] always @(posedge clock) begin // @[tage.scala:24:7] if (reset) begin // @[tage.scala:24:7] doing_reset <= 1'h1; // @[tage.scala:72:28] reset_idx <= 7'h0; // @[tage.scala:73:26] clear_u_ctr <= 19'h0; // @[tage.scala:109:28] wrbypass_enq_idx <= 1'h0; // @[tage.scala:144:33] end else begin // @[tage.scala:24:7] doing_reset <= reset_idx != 7'h7F & doing_reset; // @[tage.scala:72:28, :73:26, :75:{19,36,50}] reset_idx <= _reset_idx_T_1; // @[tage.scala:73:26, :74:26] clear_u_ctr <= doing_reset ? 19'h1 : _clear_u_ctr_T_1; // @[tage.scala:72:28, :109:28, :110:{22,36,70,85}] if (~_T_44 \| wrbypass_hit) begin // @[tage.scala:143:29, :144:33, :151:48, :170:{32,38}, :171:39] end else // @[tage.scala:144:33, :170:38, :171:39] wrbypass_enq_idx <= _wrbypass_enq_idx_T_2; // @[util.scala:203:20] end s2_tag <= s1_tag; // @[tage.scala:62:64, :95:29] io_f3_resp_0_valid_REG <= s2_req_rhits_0; // @[tage.scala:100:29, :104:38] io_f3_resp_0_bits_u_REG <= _io_f3_resp_0_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_0_bits_ctr_REG <= s2_req_rtage_0_ctr; // @[tage.scala:97:29, :106:38] io_f3_resp_1_valid_REG <= s2_req_rhits_1; // @[tage.scala:100:29, :104:38] io_f3_resp_1_bits_u_REG <= _io_f3_resp_1_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_1_bits_ctr_REG <= s2_req_rtage_1_ctr; // @[tage.scala:97:29, :106:38] io_f3_resp_2_valid_REG <= s2_req_rhits_2; // @[tage.scala:100:29, :104:38] io_f3_resp_2_bits_u_REG <= _io_f3_resp_2_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_2_bits_ctr_REG <= s2_req_rtage_2_ctr; // @[tage.scala:97:29, :106:38] io_f3_resp_3_valid_REG <= s2_req_rhits_3; // @[tage.scala:100:29, :104:38] io_f3_resp_3_bits_u_REG <= _io_f3_resp_3_bits_u_T; // @[tage.scala:105:{38,42}] io_f3_resp_3_bits_ctr_REG <= s2_req_rtage_3_ctr; // @[tage.scala:97:29, :106:38] if (_GEN_14) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39] end else // @[tage.scala:141:29, :170:38, :171:39, :175:39] wrbypass_tags_0 <= update_tag; // @[tage.scala:62:64, :141:29] if (_GEN_15) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39] end else // @[tage.scala:141:29, :170:38, :171:39, :175:39] wrbypass_tags_1 <= update_tag; // @[tage.scala:62:64, :141:29] if (_GEN_14) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39] end else // @[tage.scala:142:29, :170:38, :171:39, :176:39] wrbypass_idxs_0 <= update_idx; // @[tage.scala:60:43, :142:29] if (_GEN_15) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39] end else // @[tage.scala:142:29, :170:38, :171:39, :176:39] wrbypass_idxs_1 <= update_idx; // @[tage.scala:60:43, :142:29] if (~_T_44 \| _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39] end else begin // @[tage.scala:143:29, :170:38, :171:39] wrbypass_0_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29] wrbypass_0_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29] wrbypass_0_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29] wrbypass_0_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29] end if (_T_44 & _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39] wrbypass_1_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29] wrbypass_1_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29] wrbypass_1_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29] wrbypass_1_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29] end always @(posedge) hi_us_5 hi_us ( // @[tage.scala:89:27] .R0_addr (_s2_req_rhius_WIRE), // @[tage.scala:98:32] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_hi_us_R0_data), .W0_addr (doing_reset ? reset_idx : doing_clear_u_hi ? clear_u_idx[6:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :113:40, :115:33, :129:{8,36}] .W0_clk (clock), .W0_data ({hi_us_MPORT_1_data_3, hi_us_MPORT_1_data_2, hi_us_MPORT_1_data_1, hi_us_MPORT_1_data_0}), // @[tage.scala:89:27, :130:8] .W0_mask (_T_20 ? 4'hF : {hi_5, lo_1}) // @[tage.scala:130:21, :131:{8,80}] ); // @[tage.scala:89:27] lo_us_5 lo_us ( // @[tage.scala:90:27] .R0_addr (_s2_req_rlous_WIRE), // @[tage.scala:99:32] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_lo_us_R0_data), .W0_addr (doing_reset ? reset_idx : doing_clear_u_lo ? clear_u_idx[6:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :114:40, :115:33, :136:{8,36}] .W0_clk (clock), .W0_data ({lo_us_MPORT_2_data_3, lo_us_MPORT_2_data_2, lo_us_MPORT_2_data_1, lo_us_MPORT_2_data_0}), // @[tage.scala:90:27, :137:8] .W0_mask (_T_33 ? 4'hF : {hi_6, lo_2}) // @[tage.scala:137:21, :138:{8,80}] ); // @[tage.scala:90:27] table_5 table_0 ( // @[tage.scala:91:27] .R0_addr (_s2_req_rtage_WIRE), // @[tage.scala:97:40] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_table_R0_data), .W0_addr (doing_reset ? reset_idx : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :122:8] .W0_clk (clock), .W0_data ({table_MPORT_data_3, table_MPORT_data_2, table_MPORT_data_1, table_MPORT_data_0}), // @[tage.scala:91:27, :123:8] .W0_mask (doing_reset ? 4'hF : {hi_4, lo}) // @[tage.scala:72:28, :124:{8,90}] ); // @[tage.scala:91:27] assign io_f3_resp_0_valid = io_f3_resp_0_valid_0; // @[tage.scala:24:7] assign io_f3_resp_0_bits_ctr = io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_0_bits_u = io_f3_resp_0_bits_u_0; // @[tage.scala:24:7] assign io_f3_resp_1_valid = io_f3_resp_1_valid_0; // @[tage.scala:24:7] assign io_f3_resp_1_bits_ctr = io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_1_bits_u = io_f3_resp_1_bits_u_0; // @[tage.scala:24:7] assign io_f3_resp_2_valid = io_f3_resp_2_valid_0; // @[tage.scala:24:7] assign io_f3_resp_2_bits_ctr = io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_2_bits_u = io_f3_resp_2_bits_u_0; // @[tage.scala:24:7] assign io_f3_resp_3_valid = io_f3_resp_3_valid_0; // @[tage.scala:24:7] assign io_f3_resp_3_bits_ctr = io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7] assign io_f3_resp_3_bits_u = io_f3_resp_3_bits_u_0; // @[tage.scala:24:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File MulAddRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //* POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //* UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //* REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero \|\| rawB.isZero \|\| (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign \|\| (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //* NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR \|\| reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) \|\| isSigNaNRawFloat(rawB) \|\| isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN \|\| rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR \|\| CDom_reduced4SigExtra \|\| CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR \|\| notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA \|\| io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd \|\| io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA \|\| io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny \|\| (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) \|\| (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) \|\| (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA \|\| io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB \|\| io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros \|\| (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) \|\| (io.fromPreMul.isInfC && opSignC) \|\| (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) \|\| (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd \|\| opSignC)) \|\| (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }	module MulAddRecFN_e8_s24_17( // @[MulAddRecFN.scala:300:7] input [32:0] io_a, // @[MulAddRecFN.scala:303:16] input [32:0] io_b, // @[MulAddRecFN.scala:303:16] output [32:0] io_out // @[MulAddRecFN.scala:303:16] ); wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15] wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15] wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15] wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15] wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddB; // @[MulAddRecFN.scala:317:15] wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15] wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15] wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15] wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15] wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7] wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:300:7] wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :317:15, :319:15, :339:15] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15] wire [32:0] io_c = 33'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7] wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7] wire [47:0] _mulAddResult_T = {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddA} * {24'h0, _mulAddRecFNToRaw_preMul_io_mulAddB}; // @[MulAddRecFN.scala:317:15, :327:45] wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50] MulAddRecFNToRaw_preMul_e8_s24_17 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15] .io_a (io_a_0), // @[MulAddRecFN.scala:300:7] .io_b (io_b_0), // @[MulAddRecFN.scala:300:7] .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA), .io_mulAddB (_mulAddRecFNToRaw_preMul_io_mulAddB), .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), .io_toPostMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), .io_toPostMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) ); // @[MulAddRecFN.scala:317:15] MulAddRecFNToRaw_postMul_e8_s24_17 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15] .io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfB (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroB (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15] .io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) ); // @[MulAddRecFN.scala:319:15] RoundRawFNToRecFN_e8_s24_17 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15] .io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15] .io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15] .io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15] .io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15] .io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15] .io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulAddRecFN.scala:339:15] assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_317( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File RegisterRouter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.resources.{Device, Resource, ResourceBindings} import freechips.rocketchip.prci.{NoCrossing} import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno} import scala.math.min class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle { val source = UInt((sourceBits max 1).W) val size = UInt((sizeBits max 1).W) } case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra") case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => { x.size := 0.U x.source := 0.U }) /* TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers. * It provides functionality for describing and outputting metdata about the registers in several formats. * It also provides a concrete implementation of a regmap function that will be used * to wire a map of internal registers associated with this node to the node's interconnect port. / case class TLRegisterNode( address: Seq[AddressSet], device: Device, deviceKey: String = "reg/control", concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)( implicit valName: ValName) extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1( Seq(TLSlaveParameters.v1( address = address, resources = Seq(Resource(device, deviceKey)), executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), fifoId = Some(0))), // requests are handled in order beatBytes = beatBytes, minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle { val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min) require (size >= beatBytes) address.foreach { case a => require (a.widen(size-1).base == address.head.widen(size-1).base, s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}") } // Calling this method causes the matching TL2 bundle to be // configured to route all requests to the listed RegFields. def regmap(mapping: RegField.Map) = { val (bundleIn, edge) = this.in(0) val a = bundleIn.a val d = bundleIn.d val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields) val in = Wire(Decoupled(new RegMapperInput(params))) in.bits.read := a.bits.opcode === TLMessages.Get in.bits.index := edge.addr_hi(a.bits) in.bits.data := a.bits.data in.bits.mask := a.bits.mask Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = in.bits.extra(TLRegisterRouterExtra) a_extra.source := a.bits.source a_extra.size := a.bits.size // Invoke the register map builder val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_) // No flow control needed in.valid := a.valid a.ready := in.ready d.valid := out.valid out.ready := d.ready // We must restore the size to enable width adapters to work val d_extra = out.bits.extra(TLRegisterRouterExtra) d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size) // avoid a Mux on the data bus by manually overriding two fields d.bits.data := out.bits.data Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match { case (lhs, rhs) => lhs :<= rhs } d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck) // Tie off unused channels bundleIn.b.valid := false.B bundleIn.c.ready := true.B bundleIn.e.ready := true.B genRegDescsJson(mapping:_) } def genRegDescsJson(mapping: RegField.Map): Unit = { // Dump out the register map for documentation purposes. val base = address.head.base val baseHex = s"0x${base.toInt.toHexString}" val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}" val json = GenRegDescsAnno.serialize(base, name, mapping:_) var suffix = 0 while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) { suffix = suffix + 1 } ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json) val module = Module.currentModule.get.asInstanceOf[RawModule] GenRegDescsAnno.anno( module, base, mapping:_) } } /* Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink. * - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers. * - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect. * - Use the mapping helper function regmap to internally fill out the space of device control registers. / trait HasTLControlRegMap { this: RegisterRouter => protected val controlNode = TLRegisterNode( address = address, device = device, deviceKey = "reg/control", concurrency = concurrency, beatBytes = beatBytes, undefZero = undefZero, executable = executable) // Externally, this helper should be used to connect the register control port to a bus val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode) // Backwards-compatibility default node accessor with no clock crossing lazy val node: TLInwardNode = controlXing(NoCrossing) // Internally, this function should be used to populate the control port with registers protected def regmap(mapping: RegField.Map): Unit = { controlNode.regmap(mapping:_) } } File MuxLiteral.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.log2Ceil import scala.reflect.ClassTag / MuxLiteral creates a lookup table from a key to a list of values. * Unlike MuxLookup, the table keys must be exclusive literals. / object MuxLiteral { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (UInt, T), rest: (UInt, T)): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(UInt, T)]): T = MuxTable(index, default, cases.map { case (k, v) => (k.litValue, v) }) } object MuxSeq { def apply[T <: Data:ClassTag](index: UInt, default: T, first: T, rest: T): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[T]): T = MuxTable(index, default, cases.zipWithIndex.map { case (v, i) => (BigInt(i), v) }) } object MuxTable { def apply[T <: Data:ClassTag](index: UInt, default: T, first: (BigInt, T), rest: (BigInt, T)): T = apply(index, default, first :: rest.toList) def apply[T <: Data:ClassTag](index: UInt, default: T, cases: Seq[(BigInt, T)]): T = { /* All keys must be >= 0 and distinct / cases.foreach { case (k, _) => require (k >= 0) } require (cases.map(_._1).distinct.size == cases.size) / Filter out any cases identical to the default / val simple = cases.filter { case (k, v) => !default.isLit \|\| !v.isLit \|\| v.litValue != default.litValue } val maxKey = (BigInt(0) +: simple.map(_._1)).max val endIndex = BigInt(1) << log2Ceil(maxKey+1) if (simple.isEmpty) { default } else if (endIndex <= 2simple.size) { /* The dense encoding case uses a Vec / val table = Array.fill(endIndex.toInt) { default } simple.foreach { case (k, v) => table(k.toInt) = v } Mux(index >= endIndex.U, default, VecInit(table)(index)) } else { / The sparse encoding case uses switch / val out = WireDefault(default) simple.foldLeft(new chisel3.util.SwitchContext(index, None, Set.empty)) { case (acc, (k, v)) => acc.is (k.U) { out := v } } out } } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File Plic.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.tilelink import chisel3._ import chisel3.experimental._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet} import freechips.rocketchip.resources.{Description, Resource, ResourceBinding, ResourceBindings, ResourceInt, SimpleDevice} import freechips.rocketchip.interrupts.{IntNexusNode, IntSinkParameters, IntSinkPortParameters, IntSourceParameters, IntSourcePortParameters} import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldRdAction, RegFieldWrType, RegReadFn, RegWriteFn} import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, TLBusWrapperLocation} import freechips.rocketchip.tilelink.{TLFragmenter, TLRegisterNode} import freechips.rocketchip.util.{Annotated, MuxT, property} import scala.math.min import freechips.rocketchip.util.UIntToAugmentedUInt import freechips.rocketchip.util.SeqToAugmentedSeq class GatewayPLICIO extends Bundle { val valid = Output(Bool()) val ready = Input(Bool()) val complete = Input(Bool()) } class LevelGateway extends Module { val io = IO(new Bundle { val interrupt = Input(Bool()) val plic = new GatewayPLICIO }) val inFlight = RegInit(false.B) when (io.interrupt && io.plic.ready) { inFlight := true.B } when (io.plic.complete) { inFlight := false.B } io.plic.valid := io.interrupt && !inFlight } object PLICConsts { def maxDevices = 1023 def maxMaxHarts = 15872 def priorityBase = 0x0 def pendingBase = 0x1000 def enableBase = 0x2000 def hartBase = 0x200000 def claimOffset = 4 def priorityBytes = 4 def enableOffset(i: Int) = i * ((maxDevices+7)/8) def hartOffset(i: Int) = i * 0x1000 def enableBase(i: Int):Int = enableOffset(i) + enableBase def hartBase(i: Int):Int = hartOffset(i) + hartBase def size(maxHarts: Int): Int = { require(maxHarts > 0 && maxHarts <= maxMaxHarts, s"Must be: maxHarts=$maxHarts > 0 && maxHarts <= PLICConsts.maxMaxHarts=${PLICConsts.maxMaxHarts}") 1 << log2Ceil(hartBase(maxHarts)) } require(hartBase >= enableBase(maxMaxHarts)) } case class PLICParams(baseAddress: BigInt = 0xC000000, maxPriorities: Int = 7, intStages: Int = 0, maxHarts: Int = PLICConsts.maxMaxHarts) { require (maxPriorities >= 0) def address = AddressSet(baseAddress, PLICConsts.size(maxHarts)-1) } case object PLICKey extends Field[Option[PLICParams]](None) case class PLICAttachParams( slaveWhere: TLBusWrapperLocation = CBUS ) case object PLICAttachKey extends Field(PLICAttachParams()) /** Platform-Level Interrupt Controller / class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends LazyModule { // plic0 => max devices 1023 val device: SimpleDevice = new SimpleDevice("interrupt-controller", Seq("riscv,plic0")) { override val alwaysExtended = true override def describe(resources: ResourceBindings): Description = { val Description(name, mapping) = super.describe(resources) val extra = Map( "interrupt-controller" -> Nil, "riscv,ndev" -> Seq(ResourceInt(nDevices)), "riscv,max-priority" -> Seq(ResourceInt(nPriorities)), "#interrupt-cells" -> Seq(ResourceInt(1))) Description(name, mapping ++ extra) } } val node : TLRegisterNode = TLRegisterNode( address = Seq(params.address), device = device, beatBytes = beatBytes, undefZero = true, concurrency = 1) // limiting concurrency handles RAW hazards on claim registers val intnode: IntNexusNode = IntNexusNode( sourceFn = { _ => IntSourcePortParameters(Seq(IntSourceParameters(1, Seq(Resource(device, "int"))))) }, sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, outputRequiresInput = false, inputRequiresOutput = false) / Negotiated sizes / def nDevices: Int = intnode.edges.in.map(_.source.num).sum def minPriorities = min(params.maxPriorities, nDevices) def nPriorities = (1 << log2Ceil(minPriorities+1)) - 1 // round up to next 2^n-1 def nHarts = intnode.edges.out.map(_.source.num).sum // Assign all the devices unique ranges lazy val sources = intnode.edges.in.map(_.source) lazy val flatSources = (sources zip sources.map(_.num).scanLeft(0)(_+_).init).map { case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o))) }.flatten ResourceBinding { flatSources.foreach { s => s.resources.foreach { r => // +1 because interrupt 0 is reserved (s.range.start until s.range.end).foreach { i => r.bind(device, ResourceInt(i+1)) } } } } lazy val module = new Impl class Impl extends LazyModuleImp(this) { Annotated.params(this, params) val (io_devices, edgesIn) = intnode.in.unzip val (io_harts, _) = intnode.out.unzip // Compact the interrupt vector the same way val interrupts = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten // This flattens the harts into an MSMSMSMSMS... or MMMMM.... sequence val harts = io_harts.flatten def getNInterrupts = interrupts.size println(s"Interrupt map (${nHarts} harts ${nDevices} interrupts):") flatSources.foreach { s => // +1 because 0 is reserved, +1-1 because the range is half-open println(s" [${s.range.start+1}, ${s.range.end}] => ${s.name}") } println("") require (nDevices == interrupts.size, s"Must be: nDevices=$nDevices == interrupts.size=${interrupts.size}") require (nHarts == harts.size, s"Must be: nHarts=$nHarts == harts.size=${harts.size}") require(nDevices <= PLICConsts.maxDevices, s"Must be: nDevices=$nDevices <= PLICConsts.maxDevices=${PLICConsts.maxDevices}") require(nHarts > 0 && nHarts <= params.maxHarts, s"Must be: nHarts=$nHarts > 0 && nHarts <= PLICParams.maxHarts=${params.maxHarts}") // For now, use LevelGateways for all TL2 interrupts val gateways = interrupts.map { case i => val gateway = Module(new LevelGateway) gateway.io.interrupt := i gateway.io.plic } val prioBits = log2Ceil(nPriorities+1) val priority = if (nPriorities > 0) Reg(Vec(nDevices, UInt(prioBits.W))) else WireDefault(VecInit.fill(nDevices max 1)(1.U)) val threshold = if (nPriorities > 0) Reg(Vec(nHarts, UInt(prioBits.W))) else WireDefault(VecInit.fill(nHarts)(0.U)) val pending = RegInit(VecInit.fill(nDevices max 1){false.B}) / Construct the enable registers, chunked into 8-bit segments to reduce verilog size / val firstEnable = nDevices min 7 val fullEnables = (nDevices - firstEnable) / 8 val tailEnable = nDevices - firstEnable - 8fullEnables def enableRegs = (Reg(UInt(firstEnable.W)) +: Seq.fill(fullEnables) { Reg(UInt(8.W)) }) ++ (if (tailEnable > 0) Some(Reg(UInt(tailEnable.W))) else None) val enables = Seq.fill(nHarts) { enableRegs } val enableVec = VecInit(enables.map(x => Cat(x.reverse))) val enableVec0 = VecInit(enableVec.map(x => Cat(x, 0.U(1.W)))) val maxDevs = Reg(Vec(nHarts, UInt(log2Ceil(nDevices+1).W))) val pendingUInt = Cat(pending.reverse) if(nDevices > 0) { for (hart <- 0 until nHarts) { val fanin = Module(new PLICFanIn(nDevices, prioBits)) fanin.io.prio := priority fanin.io.ip := enableVec(hart) & pendingUInt maxDevs(hart) := fanin.io.dev harts(hart) := ShiftRegister(RegNext(fanin.io.max) > threshold(hart), params.intStages) } } // Priority registers are 32-bit aligned so treat each as its own group. // Otherwise, the off-by-one nature of the priority registers gets confusing. require(PLICConsts.priorityBytes == 4, s"PLIC Priority register descriptions assume 32-bits per priority, not ${PLICConsts.priorityBytes}") def priorityRegDesc(i: Int) = RegFieldDesc( name = s"priority_$i", desc = s"Acting priority of interrupt source $i", group = Some(s"priority_${i}"), groupDesc = Some(s"Acting priority of interrupt source ${i}"), reset = if (nPriorities > 0) None else Some(1)) def pendingRegDesc(i: Int) = RegFieldDesc( name = s"pending_$i", desc = s"Set to 1 if interrupt source $i is pending, regardless of its enable or priority setting.", group = Some("pending"), groupDesc = Some("Pending Bit Array. 1 Bit for each interrupt source."), volatile = true) def enableRegDesc(i: Int, j: Int, wide: Int) = { val low = if (j == 0) 1 else j8 val high = low + wide - 1 RegFieldDesc( name = s"enables_${j}", desc = s"Targets ${low}-${high}. Set bits to 1 if interrupt should be enabled.", group = Some(s"enables_${i}"), groupDesc = Some(s"Enable bits for each interrupt source for target $i. 1 bit for each interrupt source.")) } def priorityRegField(x: UInt, i: Int) = if (nPriorities > 0) { RegField(prioBits, x, priorityRegDesc(i)) } else { RegField.r(prioBits, x, priorityRegDesc(i)) } val priorityRegFields = priority.zipWithIndex.map { case (p, i) => PLICConsts.priorityBase+PLICConsts.priorityBytes(i+1) -> Seq(priorityRegField(p, i+1)) } val pendingRegFields = Seq(PLICConsts.pendingBase -> (RegField(1) +: pending.zipWithIndex.map { case (b, i) => RegField.r(1, b, pendingRegDesc(i+1))})) val enableRegFields = enables.zipWithIndex.map { case (e, i) => PLICConsts.enableBase(i) -> (RegField(1) +: e.zipWithIndex.map { case (x, j) => RegField(x.getWidth, x, enableRegDesc(i, j, x.getWidth)) }) } // When a hart reads a claim/complete register, then the // device which is currently its highest priority is no longer pending. // This code exploits the fact that, practically, only one claim/complete // register can be read at a time. We check for this because if the address map // were to change, it may no longer be true. // Note: PLIC doesn't care which hart reads the register. val claimer = Wire(Vec(nHarts, Bool())) assert((claimer.asUInt & (claimer.asUInt - 1.U)) === 0.U) // One-Hot val claiming = Seq.tabulate(nHarts){i => Mux(claimer(i), maxDevs(i), 0.U)}.reduceLeft(_\|_) val claimedDevs = VecInit(UIntToOH(claiming, nDevices+1).asBools) ((pending zip gateways) zip claimedDevs.tail) foreach { case ((p, g), c) => g.ready := !p when (c \|\| g.valid) { p := !c } } // When a hart writes a claim/complete register, then // the written device (as long as it is actually enabled for that // hart) is marked complete. // This code exploits the fact that, practically, only one claim/complete register // can be written at a time. We check for this because if the address map // were to change, it may no longer be true. // Note -- PLIC doesn't care which hart writes the register. val completer = Wire(Vec(nHarts, Bool())) assert((completer.asUInt & (completer.asUInt - 1.U)) === 0.U) // One-Hot val completerDev = Wire(UInt(log2Up(nDevices + 1).W)) val completedDevs = Mux(completer.reduce(_ \|\| _), UIntToOH(completerDev, nDevices+1), 0.U) (gateways zip completedDevs.asBools.tail) foreach { case (g, c) => g.complete := c } def thresholdRegDesc(i: Int) = RegFieldDesc( name = s"threshold_$i", desc = s"Interrupt & claim threshold for target $i. Maximum value is ${nPriorities}.", reset = if (nPriorities > 0) None else Some(1)) def thresholdRegField(x: UInt, i: Int) = if (nPriorities > 0) { RegField(prioBits, x, thresholdRegDesc(i)) } else { RegField.r(prioBits, x, thresholdRegDesc(i)) } val hartRegFields = Seq.tabulate(nHarts) { i => PLICConsts.hartBase(i) -> Seq( thresholdRegField(threshold(i), i), RegField(32-prioBits), RegField(32, RegReadFn { valid => claimer(i) := valid (true.B, maxDevs(i)) }, RegWriteFn { (valid, data) => assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0), "completerDev should be consistent for all harts") completerDev := data.extract(log2Ceil(nDevices+1)-1, 0) completer(i) := valid && enableVec0(i)(completerDev) true.B }, Some(RegFieldDesc(s"claim_complete_$i", s"Claim/Complete register for Target $i. Reading this register returns the claimed interrupt number and makes it no longer pending." + s"Writing the interrupt number back completes the interrupt.", reset = None, wrType = Some(RegFieldWrType.MODIFY), rdAction = Some(RegFieldRdAction.MODIFY), volatile = true)) ) ) } node.regmap((priorityRegFields ++ pendingRegFields ++ enableRegFields ++ hartRegFields):_) if (nDevices >= 2) { val claimed = claimer(0) && maxDevs(0) > 0.U val completed = completer(0) property.cover(claimed && RegEnable(claimed, false.B, claimed \|\| completed), "TWO_CLAIMS", "two claims with no intervening complete") property.cover(completed && RegEnable(completed, false.B, claimed \|\| completed), "TWO_COMPLETES", "two completes with no intervening claim") val ep = enables(0).asUInt & pending.asUInt val ep2 = RegNext(ep) val diff = ep & ~ep2 property.cover((diff & (diff - 1.U)) =/= 0.U, "TWO_INTS_PENDING", "two enabled interrupts became pending on same cycle") if (nPriorities > 0) ccover(maxDevs(0) > (1.U << priority(0).getWidth) && maxDevs(0) <= Cat(1.U, threshold(0)), "THRESHOLD", "interrupt pending but less than threshold") } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"PLIC_$label", "Interrupts;;" + desc) } } class PLICFanIn(nDevices: Int, prioBits: Int) extends Module { val io = IO(new Bundle { val prio = Flipped(Vec(nDevices, UInt(prioBits.W))) val ip = Flipped(UInt(nDevices.W)) val dev = UInt(log2Ceil(nDevices+1).W) val max = UInt(prioBits.W) }) def findMax(x: Seq[UInt]): (UInt, UInt) = { if (x.length > 1) { val half = 1 << (log2Ceil(x.length) - 1) val left = findMax(x take half) val right = findMax(x drop half) MuxT(left._1 >= right._1, left, (right._1, half.U \| right._2)) } else (x.head, 0.U) } val effectivePriority = (1.U << prioBits) +: (io.ip.asBools zip io.prio).map { case (p, x) => Cat(p, x) } val (maxPri, maxDev) = findMax(effectivePriority) io.max := maxPri // strips the always-constant high '1' bit io.dev := maxDev } /* Trait that will connect a PLIC to a subsystem / trait CanHavePeripheryPLIC { this: BaseSubsystem => val (plicOpt, plicDomainOpt) = p(PLICKey).map { params => val tlbus = locateTLBusWrapper(p(PLICAttachKey).slaveWhere) val plicDomainWrapper = tlbus.generateSynchronousDomain("PLIC").suggestName("plic_domain") val plic = plicDomainWrapper { LazyModule(new TLPLIC(params, tlbus.beatBytes)) } plicDomainWrapper { plic.node := tlbus.coupleTo("plic") { TLFragmenter(tlbus, Some("PLIC")) := _ } } plicDomainWrapper { plic.intnode := ibus.toPLIC } (plic, plicDomainWrapper) }.unzip }	module TLPLIC( // @[Plic.scala:132:9] input clock, // @[Plic.scala:132:9] input reset, // @[Plic.scala:132:9] input auto_int_in_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_1_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_0_0, // @[LazyModuleImp.scala:107:25] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [12:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [12:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [12:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [22:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire _out_back_front_q_io_deq_valid; // @[RegisterRouter.scala:87:24] wire _out_back_front_q_io_deq_bits_read; // @[RegisterRouter.scala:87:24] wire [22:0] _out_back_front_q_io_deq_bits_index; // @[RegisterRouter.scala:87:24] wire [63:0] _out_back_front_q_io_deq_bits_data; // @[RegisterRouter.scala:87:24] wire [7:0] _out_back_front_q_io_deq_bits_mask; // @[RegisterRouter.scala:87:24] wire _fanin_1_io_dev; // @[Plic.scala:189:27] wire _fanin_1_io_max; // @[Plic.scala:189:27] wire _fanin_io_dev; // @[Plic.scala:189:27] wire _fanin_io_max; // @[Plic.scala:189:27] wire _gateways_gateway_io_plic_valid; // @[Plic.scala:160:27] wire auto_int_in_0_0 = auto_int_in_0; // @[Plic.scala:132:9] wire auto_in_a_valid_0 = auto_in_a_valid; // @[Plic.scala:132:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Plic.scala:132:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Plic.scala:132:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Plic.scala:132:9] wire [12:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Plic.scala:132:9] wire [27:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Plic.scala:132:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Plic.scala:132:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Plic.scala:132:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Plic.scala:132:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Plic.scala:132:9] wire _out_T_73 = reset; // @[Plic.scala:298:19] wire _out_T_109 = reset; // @[Plic.scala:298:19] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_21 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_25 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_29 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_33 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_37 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_41 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_45 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_49 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_53 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_57 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_61 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_65 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_4 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_22 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_26 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_30 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_7 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_34 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_8 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_38 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_42 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_46 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_11 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_50 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_12 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_54 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_58 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_62 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_15 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_66 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_4 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_5 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_6 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_7 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_8 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_9 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_10 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_11 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_12 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_13 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_14 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_15 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire [1:0] auto_in_d_bits_param = 2'h0; // @[Plic.scala:132:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire auto_in_d_bits_sink = 1'h0; // @[Plic.scala:132:9] wire auto_in_d_bits_denied = 1'h0; // @[Plic.scala:132:9] wire auto_in_d_bits_corrupt = 1'h0; // @[Plic.scala:132:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _pending_WIRE_0 = 1'h0; // @[Plic.scala:172:55] wire _out_T_19 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_20 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_prepend_T = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_39 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_40 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_1 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_129 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_T_130 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_6 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_28 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_32 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_40 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_48 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_52 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_56 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_60 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_64 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_66 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_29 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_33 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_41 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_49 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_53 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_57 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_61 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_65 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_67 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_8 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_28 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_32 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_40 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_48 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_52 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_56 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_60 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_64 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_66 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_9 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_29 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_33 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_41 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_49 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_53 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_57 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_61 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_65 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_67 = 1'h0; // @[MuxLiteral.scala:49:17] wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [63:0] nodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire [2:0] nodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [31:0] _out_prepend_T_7 = 32'h0; // @[RegisterRouter.scala:87:24] wire [22:0] out_maskMatch = 23'h7BF9EF; // @[RegisterRouter.scala:87:24] wire intnodeIn_0 = auto_int_in_0_0; // @[Plic.scala:132:9] wire x1_intnodeOut_0; // @[MixedNode.scala:542:17] wire intnodeOut_0; // @[MixedNode.scala:542:17] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Plic.scala:132:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Plic.scala:132:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Plic.scala:132:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Plic.scala:132:9] wire [12:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Plic.scala:132:9] wire [27:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Plic.scala:132:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Plic.scala:132:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Plic.scala:132:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Plic.scala:132:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Plic.scala:132:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [12:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_int_out_1_0_0; // @[Plic.scala:132:9] wire auto_int_out_0_0_0; // @[Plic.scala:132:9] wire auto_in_a_ready_0; // @[Plic.scala:132:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Plic.scala:132:9] wire [1:0] auto_in_d_bits_size_0; // @[Plic.scala:132:9] wire [12:0] auto_in_d_bits_source_0; // @[Plic.scala:132:9] wire [63:0] auto_in_d_bits_data_0; // @[Plic.scala:132:9] wire auto_in_d_valid_0; // @[Plic.scala:132:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Plic.scala:132:9] wire in_valid = nodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = nodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [12:0] in_bits_extra_tlrr_extra_source = nodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = nodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = nodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = nodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Plic.scala:132:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Plic.scala:132:9] wire [1:0] nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Plic.scala:132:9] wire [12:0] nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Plic.scala:132:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Plic.scala:132:9] wire _intnodeOut_0_T; // @[Plic.scala:193:60] assign auto_int_out_0_0_0 = intnodeOut_0; // @[Plic.scala:132:9] wire _intnodeOut_0_T_1; // @[Plic.scala:193:60] assign auto_int_out_1_0_0 = x1_intnodeOut_0; // @[Plic.scala:132:9] reg priority_0; // @[Plic.scala:167:31] reg threshold_0; // @[Plic.scala:170:31] wire _out_T_95 = threshold_0; // @[RegisterRouter.scala:87:24] reg threshold_1; // @[Plic.scala:170:31] wire _out_T_59 = threshold_1; // @[RegisterRouter.scala:87:24] reg pending_0; // @[Plic.scala:172:26] reg enables_0_0; // @[Plic.scala:178:26] wire enableVec_0 = enables_0_0; // @[Plic.scala:178:26, :182:28] reg enables_1_0; // @[Plic.scala:178:26] wire enableVec_1 = enables_1_0; // @[Plic.scala:178:26, :182:28] wire [1:0] _enableVec0_T = {enableVec_0, 1'h0}; // @[Plic.scala:182:28, :183:52] wire [1:0] enableVec0_0 = _enableVec0_T; // @[Plic.scala:183:{29,52}] wire [1:0] _enableVec0_T_1 = {enableVec_1, 1'h0}; // @[Plic.scala:182:28, :183:52] wire [1:0] enableVec0_1 = _enableVec0_T_1; // @[Plic.scala:183:{29,52}] reg maxDevs_0; // @[Plic.scala:185:22] reg maxDevs_1; // @[Plic.scala:185:22] wire _fanin_io_ip_T = enableVec_0 & pending_0; // @[Plic.scala:172:26, :182:28, :191:40] reg intnodeOut_0_REG; // @[Plic.scala:193:45] assign _intnodeOut_0_T = intnodeOut_0_REG > threshold_0; // @[Plic.scala:170:31, :193:{45,60}] assign intnodeOut_0 = _intnodeOut_0_T; // @[Plic.scala:193:60] wire _fanin_io_ip_T_1 = enableVec_1 & pending_0; // @[Plic.scala:172:26, :182:28, :191:40] reg intnodeOut_0_REG_1; // @[Plic.scala:193:45] assign _intnodeOut_0_T_1 = intnodeOut_0_REG_1 > threshold_1; // @[Plic.scala:170:31, :193:{45,60}] assign x1_intnodeOut_0 = _intnodeOut_0_T_1; // @[Plic.scala:193:60] wire out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_roready_6; // @[RegisterRouter.scala:87:24] wire claimer_0; // @[Plic.scala:250:23] wire claimer_1; // @[Plic.scala:250:23] wire _claiming_T = claimer_0 & maxDevs_0; // @[Plic.scala:185:22, :250:23, :252:49] wire _claiming_T_1 = claimer_1 & maxDevs_1; // @[Plic.scala:185:22, :250:23, :252:49] wire claiming = _claiming_T \| _claiming_T_1; // @[Plic.scala:252:{49,92}] wire claimedDevs_shiftAmount = claiming; // @[OneHot.scala:64:49] wire [1:0] _claimedDevs_T = 2'h1 << claimedDevs_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _claimedDevs_T_1 = _claimedDevs_T; // @[OneHot.scala:65:{12,27}] wire _claimedDevs_T_2 = _claimedDevs_T_1[0]; // @[OneHot.scala:65:27] wire claimedDevs_0 = _claimedDevs_T_2; // @[Plic.scala:253:{30,62}] wire _claimedDevs_T_3 = _claimedDevs_T_1[1]; // @[OneHot.scala:65:27] wire claimedDevs_1 = _claimedDevs_T_3; // @[Plic.scala:253:{30,62}] wire _gateway_io_plic_ready_T = ~pending_0; // @[Plic.scala:172:26, :256:18] wire _pending_0_T = ~claimedDevs_1; // @[Plic.scala:253:30, :257:34] wire _out_completer_0_T_2; // @[Plic.scala:301:35] wire _out_completer_1_T_2; // @[Plic.scala:301:35] wire completer_0; // @[Plic.scala:267:25] wire completer_1; // @[Plic.scala:267:25] wire _out_completerDev_T_1; // @[package.scala:163:13] wire completerDev; // @[Plic.scala:269:28] wire completedDevs_shiftAmount = completerDev; // @[OneHot.scala:64:49] wire _completedDevs_T = completer_0 \| completer_1; // @[Plic.scala:267:25, :270:48] wire [1:0] _completedDevs_T_1 = 2'h1 << completedDevs_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _completedDevs_T_2 = _completedDevs_T_1; // @[OneHot.scala:65:{12,27}] wire [1:0] completedDevs = _completedDevs_T ? _completedDevs_T_2 : 2'h0; // @[OneHot.scala:65:27] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign nodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [22:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [12:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = nodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [24:0] _in_bits_index_T = nodeIn_a_bits_address[27:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[22:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_q_io_deq_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign nodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_12; // @[RegisterRouter.scala:87:24] wire _nodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign nodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] wire out_front_valid; // @[RegisterRouter.scala:87:24] wire [22:0] out_findex = out_front_bits_index & 23'h7BF9EF; // @[RegisterRouter.scala:87:24] wire [22:0] out_bindex = _out_back_front_q_io_deq_bits_index & 23'h7BF9EF; // @[RegisterRouter.scala:87:24] wire _GEN = out_findex == 23'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN; // @[RegisterRouter.scala:87:24] wire _out_T_2; // @[RegisterRouter.scala:87:24] assign _out_T_2 = _GEN; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN; // @[RegisterRouter.scala:87:24] wire _out_T_6; // @[RegisterRouter.scala:87:24] assign _out_T_6 = _GEN; // @[RegisterRouter.scala:87:24] wire _out_T_8; // @[RegisterRouter.scala:87:24] assign _out_T_8 = _GEN; // @[RegisterRouter.scala:87:24] wire _out_T_10; // @[RegisterRouter.scala:87:24] assign _out_T_10 = _GEN; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_bindex == 23'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_3; // @[RegisterRouter.scala:87:24] assign _out_T_3 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_7; // @[RegisterRouter.scala:87:24] assign _out_T_7 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_9; // @[RegisterRouter.scala:87:24] assign _out_T_9 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_11; // @[RegisterRouter.scala:87:24] assign _out_T_11 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_23; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_43; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_35; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_44; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_36; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_12; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_23; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_43; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_35; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_19; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire out_roready_8; // @[RegisterRouter.scala:87:24] wire out_roready_9; // @[RegisterRouter.scala:87:24] wire out_roready_10; // @[RegisterRouter.scala:87:24] wire out_roready_11; // @[RegisterRouter.scala:87:24] wire out_roready_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_24; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_44; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_36; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_20; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire out_woready_10; // @[RegisterRouter.scala:87:24] wire out_woready_11; // @[RegisterRouter.scala:87:24] wire out_woready_12; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = _out_back_front_q_io_deq_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = _out_back_front_q_io_deq_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = _out_back_front_q_io_deq_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = _out_back_front_q_io_deq_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = _out_back_front_q_io_deq_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = _out_back_front_q_io_deq_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = _out_back_front_q_io_deq_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = _out_back_front_q_io_deq_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_2 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_2 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_4 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_4 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_7 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_7 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_10 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_10 = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_2 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_2 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_4 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_4 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_7 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_7 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_10 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_10 = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_13 = out_f_rivalid; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_14 = out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_12 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_32 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_50 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_86 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_122 = _out_back_front_q_io_deq_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_15 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_16 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_17 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_18 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_1 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_1 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_3 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_3 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_rimask_T_11 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T_11 = out_frontMask[1]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = _out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = _out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire _out_romask_T_1 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_1 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_3 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_3 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_romask_T_11 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire _out_womask_T_11 = out_backMask[1]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = _out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = _out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_22 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_23 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_24 = out_f_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire _out_T_25 = out_f_woready_1; // @[RegisterRouter.scala:87:24] wire _out_T_21 = _out_back_front_q_io_deq_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_41 = _out_back_front_q_io_deq_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_131 = _out_back_front_q_io_deq_bits_data[1]; // @[RegisterRouter.scala:87:24] wire _out_T_26 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_27 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_28 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_29 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend = {enables_1_0, 1'h0}; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_30 = out_prepend; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_31 = _out_T_30; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = _out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = _out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire out_romask_2 = _out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = _out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_33 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_34 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] wire _out_T_35 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_36 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_37 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_38 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = _out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = _out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire out_romask_3 = _out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = _out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_42 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_43 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] wire _out_T_44 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_45 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_46 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_47 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_1 = {pending_0, 1'h0}; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_48 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [1:0] _out_T_49 = _out_T_48; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = _out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = _out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire out_romask_4 = _out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = _out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_51 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_52 = out_f_roready_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_53 = out_f_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] wire _out_T_54 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_55 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_56 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_57 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_58 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire _out_T_60 = _out_T_59; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_2 = _out_T_60; // @[RegisterRouter.scala:87:24] wire [30:0] _out_rimask_T_5 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_wimask_T_5 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_rimask_T_8 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_wimask_T_8 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = \|_out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire [30:0] _out_romask_T_5 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_womask_T_5 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_romask_T_8 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_womask_T_8 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = \|_out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_62 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_63 = out_f_roready_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_61 = _out_back_front_q_io_deq_bits_data[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_97 = _out_back_front_q_io_deq_bits_data[31:1]; // @[RegisterRouter.scala:87:24] wire _out_T_64 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_65 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_66 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_67 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_2 = {1'h0, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_68 = {30'h0, out_prepend_2}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_69 = _out_T_68; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_3 = _out_T_69; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_6 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_6 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_rimask_T_9 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_wimask_T_9 = out_frontMask[63:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = \|_out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_6 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_6 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_romask_T_9 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_womask_T_9 = out_backMask[63:32]; // @[RegisterRouter.scala:87:24] wire out_romask_6 = \|_out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_76 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24] assign out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] assign claimer_1 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire _out_T_77 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_78 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] wire _out_T_79 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_70 = _out_back_front_q_io_deq_bits_data[63:32]; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_106 = _out_back_front_q_io_deq_bits_data[63:32]; // @[RegisterRouter.scala:87:24] wire _out_T_71 = _out_T_70[0]; // @[package.scala:163:13] wire _out_completerDev_T = _out_T_70[0]; // @[package.scala:163:13] wire _out_T_72 = completerDev == _out_T_71; // @[package.scala:163:13] wire _out_T_74 = ~_out_T_73; // @[Plic.scala:298:19] wire _out_T_75 = ~_out_T_72; // @[Plic.scala:298:{19,33}] wire [1:0] _GEN_1 = {1'h0, completerDev}; // @[Plic.scala:269:28, :301:51] wire [1:0] _out_completer_1_T = enableVec0_1 >> _GEN_1; // @[Plic.scala:183:29, :301:51] wire _out_completer_1_T_1 = _out_completer_1_T[0]; // @[Plic.scala:301:51] assign _out_completer_1_T_2 = out_f_woready_6 & _out_completer_1_T_1; // @[RegisterRouter.scala:87:24] assign completer_1 = _out_completer_1_T_2; // @[Plic.scala:267:25, :301:35] wire _out_T_80 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_81 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_82 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_83 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire [32:0] out_prepend_3 = {maxDevs_1, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_84 = {31'h0, out_prepend_3}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_85 = _out_T_84; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = _out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = _out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire out_romask_7 = _out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = _out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_87 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_88 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_89 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] wire _out_T_90 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire _out_T_91 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_92 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_93 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_94 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire _out_T_96 = _out_T_95; // @[RegisterRouter.scala:87:24] wire _out_prepend_T_4 = _out_T_96; // @[RegisterRouter.scala:87:24] wire out_rimask_8 = \|_out_rimask_T_8; // @[RegisterRouter.scala:87:24] wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24] wire out_romask_8 = \|_out_romask_T_8; // @[RegisterRouter.scala:87:24] wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_98 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_99 = out_f_roready_8; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24] wire out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24] wire _out_T_100 = ~out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_101 = ~out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_102 = ~out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_103 = ~out_womask_8; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend_4 = {1'h0, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_104 = {30'h0, out_prepend_4}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_105 = _out_T_104; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_5 = _out_T_105; // @[RegisterRouter.scala:87:24] wire out_rimask_9 = \|_out_rimask_T_9; // @[RegisterRouter.scala:87:24] wire out_wimask_9 = &_out_wimask_T_9; // @[RegisterRouter.scala:87:24] wire out_romask_9 = \|_out_romask_T_9; // @[RegisterRouter.scala:87:24] wire out_womask_9 = &_out_womask_T_9; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_112 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24] assign out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24] assign claimer_0 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire _out_T_113 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_114 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24] wire _out_T_115 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire _out_T_107 = _out_T_106[0]; // @[package.scala:163:13] assign _out_completerDev_T_1 = _out_T_106[0]; // @[package.scala:163:13] wire _out_T_108 = completerDev == _out_T_107; // @[package.scala:163:13] wire _out_T_110 = ~_out_T_109; // @[Plic.scala:298:19] wire _out_T_111 = ~_out_T_108; // @[Plic.scala:298:{19,33}]
Generate the Verilog code corresponding to the following Chisel files. File primitives.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object lowMask { def apply(in: UInt, topBound: BigInt, bottomBound: BigInt): UInt = { require(topBound != bottomBound) val numInVals = BigInt(1)<<in.getWidth if (topBound < bottomBound) { lowMask(~in, numInVals - 1 - topBound, numInVals - 1 - bottomBound) } else if (numInVals > 64 /* Empirical /) { // For simulation performance, we should avoid generating // exteremely wide shifters, so we divide and conquer. // Empirically, this does not impact synthesis QoR. val mid = numInVals / 2 val msb = in(in.getWidth - 1) val lsbs = in(in.getWidth - 2, 0) if (mid < topBound) { if (mid <= bottomBound) { Mux(msb, lowMask(lsbs, topBound - mid, bottomBound - mid), 0.U ) } else { Mux(msb, lowMask(lsbs, topBound - mid, 0) ## ((BigInt(1)<<(mid - bottomBound).toInt) - 1).U, lowMask(lsbs, mid, bottomBound) ) } } else { ~Mux(msb, 0.U, ~lowMask(lsbs, topBound, bottomBound)) } } else { val shift = (BigInt(-1)<<numInVals.toInt).S>>in Reverse( shift( (numInVals - 1 - bottomBound).toInt, (numInVals - topBound).toInt ) ) } } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object countLeadingZeros { def apply(in: UInt): UInt = PriorityEncoder(in.asBools.reverse) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy2 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 1)>>1 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix 2 + 1, ix * 2).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 2).orR reducedVec.asUInt } } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- object orReduceBy4 { def apply(in: UInt): UInt = { val reducedWidth = (in.getWidth + 3)>>2 val reducedVec = Wire(Vec(reducedWidth, Bool())) for (ix <- 0 until reducedWidth - 1) { reducedVec(ix) := in(ix * 4 + 3, ix * 4).orR } reducedVec(reducedWidth - 1) := in(in.getWidth - 1, (reducedWidth - 1) * 4).orR reducedVec.asUInt } } File RoundAnyRawFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util.Fill import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundAnyRawFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int, options: Int ) extends RawModule { override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(inExpWidth, inSigWidth)) // (allowed exponent range has limits) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0) val effectiveInSigWidth = if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1 val neverUnderflows = ((options & (flRoundOpt_neverUnderflows \| flRoundOpt_subnormsAlwaysExact) ) != 0) \|\| (inExpWidth < outExpWidth) val neverOverflows = ((options & flRoundOpt_neverOverflows) != 0) \|\| (inExpWidth < outExpWidth) val outNaNExp = BigInt(7)<<(outExpWidth - 2) val outInfExp = BigInt(6)<<(outExpWidth - 2) val outMaxFiniteExp = outInfExp - 1 val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2 val outMinNonzeroExp = outMinNormExp - outSigWidth + 1 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_near_even = (io.roundingMode === round_near_even) val roundingMode_minMag = (io.roundingMode === round_minMag) val roundingMode_min = (io.roundingMode === round_min) val roundingMode_max = (io.roundingMode === round_max) val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag) val roundingMode_odd = (io.roundingMode === round_odd) val roundMagUp = (roundingMode_min && io.in.sign) \|\| (roundingMode_max && ! io.in.sign) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sAdjustedExp = if (inExpWidth < outExpWidth) (io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S )(outExpWidth, 0).zext else if (inExpWidth == outExpWidth) io.in.sExp else io.in.sExp +& ((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S val adjustedSig = if (inSigWidth <= outSigWidth + 2) io.in.sig<<(outSigWidth - inSigWidth + 2) else (io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ## io.in.sig(inSigWidth - outSigWidth - 2, 0).orR ) val doShiftSigDown1 = if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2) val common_expOut = Wire(UInt((outExpWidth + 1).W)) val common_fractOut = Wire(UInt((outSigWidth - 1).W)) val common_overflow = Wire(Bool()) val common_totalUnderflow = Wire(Bool()) val common_underflow = Wire(Bool()) val common_inexact = Wire(Bool()) if ( neverOverflows && neverUnderflows && (effectiveInSigWidth <= outSigWidth) ) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1 common_fractOut := Mux(doShiftSigDown1, adjustedSig(outSigWidth + 1, 3), adjustedSig(outSigWidth, 2) ) common_overflow := false.B common_totalUnderflow := false.B common_underflow := false.B common_inexact := false.B } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundMask = if (neverUnderflows) 0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W) else (lowMask( sAdjustedExp(outExpWidth, 0), outMinNormExp - outSigWidth - 1, outMinNormExp ) \| doShiftSigDown1) ## 3.U(2.W) val shiftedRoundMask = 0.U(1.W) ## roundMask>>1 val roundPosMask = ~shiftedRoundMask & roundMask val roundPosBit = (adjustedSig & roundPosMask).orR val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR val anyRound = roundPosBit \|\| anyRoundExtra val roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && roundPosBit) \|\| (roundMagUp && anyRound) val roundedSig: Bits = Mux(roundIncr, (((adjustedSig \| roundMask)>>2) +& 1.U) & ~Mux(roundingMode_near_even && roundPosBit && ! anyRoundExtra, roundMask>>1, 0.U((outSigWidth + 2).W) ), (adjustedSig & ~roundMask)>>2 \| Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U) ) //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext common_expOut := sRoundedExp(outExpWidth, 0) common_fractOut := Mux(doShiftSigDown1, roundedSig(outSigWidth - 1, 1), roundedSig(outSigWidth - 2, 0) ) common_overflow := (if (neverOverflows) false.B else //* REWRITE BASED ON BEFORE-ROUNDING EXPONENT?: (sRoundedExp>>(outExpWidth - 1) >= 3.S)) common_totalUnderflow := (if (neverUnderflows) false.B else //* WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?: (sRoundedExp < outMinNonzeroExp.S)) val unboundedRange_roundPosBit = Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1)) val unboundedRange_anyRound = (doShiftSigDown1 && adjustedSig(2)) \|\| adjustedSig(1, 0).orR val unboundedRange_roundIncr = ((roundingMode_near_even \|\| roundingMode_near_maxMag) && unboundedRange_roundPosBit) \|\| (roundMagUp && unboundedRange_anyRound) val roundCarry = Mux(doShiftSigDown1, roundedSig(outSigWidth + 1), roundedSig(outSigWidth) ) common_underflow := (if (neverUnderflows) false.B else common_totalUnderflow \|\| //* IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING //* M.S. BIT OF SUBNORMAL SIG? (anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) && Mux(doShiftSigDown1, roundMask(3), roundMask(2)) && ! ((io.detectTininess === tininess_afterRounding) && ! Mux(doShiftSigDown1, roundMask(4), roundMask(3) ) && roundCarry && roundPosBit && unboundedRange_roundIncr))) common_inexact := common_totalUnderflow \|\| anyRound } //------------------------------------------------------------------------ //------------------------------------------------------------------------ val isNaNOut = io.invalidExc \|\| io.in.isNaN val notNaN_isSpecialInfOut = io.infiniteExc \|\| io.in.isInf val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero val overflow = commonCase && common_overflow val underflow = commonCase && common_underflow val inexact = overflow \|\| (commonCase && common_inexact) val overflow_roundMagUp = roundingMode_near_even \|\| roundingMode_near_maxMag \|\| roundMagUp val pegMinNonzeroMagOut = commonCase && common_totalUnderflow && (roundMagUp \|\| roundingMode_odd) val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp val notNaN_isInfOut = notNaN_isSpecialInfOut \|\| (overflow && overflow_roundMagUp) val signOut = Mux(isNaNOut, false.B, io.in.sign) val expOut = (common_expOut & ~Mux(io.in.isZero \|\| common_totalUnderflow, (BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMinNonzeroMagOut, ~outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) & ~Mux(pegMaxFiniteMagOut, (BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W), 0.U ) & ~Mux(notNaN_isInfOut, (BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W), 0.U )) \| Mux(pegMinNonzeroMagOut, outMinNonzeroExp.U((outExpWidth + 1).W), 0.U ) \| Mux(pegMaxFiniteMagOut, outMaxFiniteExp.U((outExpWidth + 1).W), 0.U ) \| Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) \| Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U) val fractOut = Mux(isNaNOut \|\| io.in.isZero \|\| common_totalUnderflow, Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U), common_fractOut ) \| Fill(outSigWidth - 1, pegMaxFiniteMagOut) io.out := signOut ## expOut ## fractOut io.exceptionFlags := io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int) extends RawModule { override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in' val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign' val in = Input(new RawFloat(expWidth, sigWidth + 2)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( expWidth, sigWidth + 2, expWidth, sigWidth, options)) roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc roundAnyRawFNToRecFN.io.in := io.in roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags }	module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_85( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 \| _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 \| _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 \| _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 \| _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] \| doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = \|_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = \|_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit \| anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig \| roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = \|_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 \| _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow \| _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow \| anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 \| io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow \| _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut \| _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 \| _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 \| _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut \| io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T \| common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_487( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_43( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_299 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire \|\| io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) \|\| !io.outCol.fire) assert(!(state === 1.U) \|\| !io.inRow.fire) }	module PE_131( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File regfile.scala: //**************************************************************************** // Copyright (c) 2013 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Register File (Abstract class and Synthesizable RegFile) //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.exu import scala.collection.mutable.ArrayBuffer import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix} / * IO bundle for a register read port * * @param addrWidth size of register address in bits * @param dataWidth size of register in bits / class RegisterFileReadPortIO(val addrWidth: Int, val dataWidth: Int)(implicit p: Parameters) extends BoomBundle { val addr = Input(UInt(addrWidth.W)) val data = Output(UInt(dataWidth.W)) } /* * IO bundle for the register write port * * @param addrWidth size of register address in bits * @param dataWidth size of register in bits / class RegisterFileWritePort(val addrWidth: Int, val dataWidth: Int)(implicit p: Parameters) extends BoomBundle { val addr = UInt(addrWidth.W) val data = UInt(dataWidth.W) } /* * Utility function to turn ExeUnitResps to match the regfile's WritePort I/Os. / object WritePort { def apply(enq: DecoupledIO[ExeUnitResp], addrWidth: Int, dataWidth: Int, rtype: UInt) (implicit p: Parameters): Valid[RegisterFileWritePort] = { val wport = Wire(Valid(new RegisterFileWritePort(addrWidth, dataWidth))) wport.valid := enq.valid && enq.bits.uop.dst_rtype === rtype wport.bits.addr := enq.bits.uop.pdst wport.bits.data := enq.bits.data enq.ready := true.B wport } } /* * Register file abstract class * * @param numRegisters number of registers * @param numReadPorts number of read ports * @param numWritePorts number of write ports * @param registerWidth size of registers in bits * @param bypassableArray list of write ports from func units to the read port of the regfile / abstract class RegisterFile( numRegisters: Int, numReadPorts: Int, numWritePorts: Int, registerWidth: Int, bypassableArray: Seq[Boolean]) // which write ports can be bypassed to the read ports? (implicit p: Parameters) extends BoomModule { val io = IO(new BoomBundle { val read_ports = Vec(numReadPorts, new RegisterFileReadPortIO(maxPregSz, registerWidth)) val write_ports = Flipped(Vec(numWritePorts, Valid(new RegisterFileWritePort(maxPregSz, registerWidth)))) }) private val rf_cost = (numReadPorts + numWritePorts) (numReadPorts + 2numWritePorts) private val type_str = if (registerWidth == fLen+1) "Floating Point" else "Integer" override def toString: String = BoomCoreStringPrefix( "==" + type_str + " Regfile==", "Num RF Read Ports : " + numReadPorts, "Num RF Write Ports : " + numWritePorts, "RF Cost (R+W)(R+2W) : " + rf_cost, "Bypassable Units : " + bypassableArray) } /** * A synthesizable model of a Register File. You will likely want to blackbox this for more than modest port counts. * * @param numRegisters number of registers * @param numReadPorts number of read ports * @param numWritePorts number of write ports * @param registerWidth size of registers in bits * @param bypassableArray list of write ports from func units to the read port of the regfile */ class RegisterFileSynthesizable( numRegisters: Int, numReadPorts: Int, numWritePorts: Int, registerWidth: Int, bypassableArray: Seq[Boolean]) (implicit p: Parameters) extends RegisterFile(numRegisters, numReadPorts, numWritePorts, registerWidth, bypassableArray) { // -------------------------------------------------------------- val regfile = Mem(numRegisters, UInt(registerWidth.W)) // -------------------------------------------------------------- // Read ports. val read_data = Wire(Vec(numReadPorts, UInt(registerWidth.W))) // Register the read port addresses to give a full cycle to the RegisterRead Stage (if desired). val read_addrs = io.read_ports.map(p => RegNext(p.addr)) for (i <- 0 until numReadPorts) { read_data(i) := regfile(read_addrs(i)) } // -------------------------------------------------------------- // Bypass out of the ALU's write ports. // We are assuming we cannot bypass a writer to a reader within the regfile memory // for a write that occurs at the end of cycle S1 and a read that returns data on cycle S1. // But since these bypasses are expensive, and not all write ports need to bypass their data, // only perform the w->r bypass on a select number of write ports. require (bypassableArray.length == io.write_ports.length) if (bypassableArray.reduce(_\|\|_)) { val bypassable_wports = ArrayBuffer[Valid[RegisterFileWritePort]]() io.write_ports zip bypassableArray map { case (wport, b) => if (b) { bypassable_wports += wport} } for (i <- 0 until numReadPorts) { val bypass_ens = bypassable_wports.map(x => x.valid && x.bits.addr === read_addrs(i)) val bypass_data = Mux1H(VecInit(bypass_ens.toSeq), VecInit(bypassable_wports.map(_.bits.data).toSeq)) io.read_ports(i).data := Mux(bypass_ens.reduce(_\|_), bypass_data, read_data(i)) } } else { for (i <- 0 until numReadPorts) { io.read_ports(i).data := read_data(i) } } // -------------------------------------------------------------- // Write ports. for (wport <- io.write_ports) { when (wport.valid) { regfile(wport.bits.addr) := wport.bits.data } } // ensure there is only 1 writer per register (unless to preg0) if (numWritePorts > 1) { for (i <- 0 until (numWritePorts - 1)) { for (j <- (i + 1) until numWritePorts) { assert(!io.write_ports(i).valid \|\| !io.write_ports(j).valid \|\| (io.write_ports(i).bits.addr =/= io.write_ports(j).bits.addr) \|\| (io.write_ports(i).bits.addr === 0.U), // note: you only have to check one here "[regfile] too many writers a register") } } } }	module RegisterFileSynthesizable_5( // @[regfile.scala:106:7] input clock, // @[regfile.scala:106:7] input reset // @[regfile.scala:106:7] ); wire io_write_ports_0_valid = 1'h0; // @[regfile.scala:106:7] wire io_write_ports_0_bits_data = 1'h0; // @[regfile.scala:106:7] wire read_data_0 = 1'h0; // @[regfile.scala:122:23] wire read_data_1 = 1'h0; // @[regfile.scala:122:23] wire bypass_ens_0 = 1'h0; // @[regfile.scala:145:59] wire _bypass_data_WIRE_0 = 1'h0; // @[regfile.scala:148:38] wire _bypass_data_WIRE_1_0 = 1'h0; // @[regfile.scala:148:65] wire bypass_ens_0_1 = 1'h0; // @[regfile.scala:145:59] wire _bypass_data_WIRE_2_0 = 1'h0; // @[regfile.scala:148:38] wire _bypass_data_WIRE_3_0 = 1'h0; // @[regfile.scala:148:65] wire [5:0] io_read_ports_0_addr = 6'h0; // @[regfile.scala:82:14, :106:7] wire [5:0] io_read_ports_1_addr = 6'h0; // @[regfile.scala:82:14, :106:7] wire [5:0] io_write_ports_0_bits_addr = 6'h0; // @[regfile.scala:82:14, :106:7] wire [5:0] _read_data_0_T = 6'h0; // @[regfile.scala:82:14, :106:7, :128:28] wire [5:0] _read_data_1_T = 6'h0; // @[regfile.scala:82:14, :106:7, :128:28] wire [3:0] _read_data_0_T_1 = 4'h0; // @[regfile.scala:128:28] wire [3:0] _read_data_1_T_1 = 4'h0; // @[regfile.scala:128:28] wire _bypass_ens_T = 1'h1; // @[regfile.scala:146:21] wire _bypass_ens_T_1 = 1'h1; // @[regfile.scala:146:21] wire _io_read_ports_0_data_T; // @[regfile.scala:150:35] wire _io_read_ports_1_data_T; // @[regfile.scala:150:35] wire io_read_ports_0_data; // @[regfile.scala:106:7] wire io_read_ports_1_data; // @[regfile.scala:106:7] assign _io_read_ports_0_data_T = read_data_0; // @[regfile.scala:122:23, :150:35] assign _io_read_ports_1_data_T = read_data_1; // @[regfile.scala:122:23, :150:35] assign io_read_ports_0_data = _io_read_ports_0_data_T; // @[regfile.scala:106:7, :150:35] assign io_read_ports_1_data = _io_read_ports_1_data_T; // @[regfile.scala:106:7, :150:35] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_131( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_387 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }	module IntSyncSyncCrossingSink_n0x0_2(); // @[Crossing.scala:96:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) \|\| flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask \| lo_mask)(n-1,0) } } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire \|\| !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v4.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v4.common._ import boom.v4.util._ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val grant = Input(Bool()) val iss_uop = Output(new MicroOp()) val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val squash_grant = Input(Bool()) val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val child_rebusys = Input(UInt(aluWidth.W)) } class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters) extends BoomModule { val io = IO(new IssueSlotIO(numWakeupPorts)) val slot_valid = RegInit(false.B) val slot_uop = Reg(new MicroOp()) val next_valid = WireInit(slot_valid) val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop)) val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop) io.valid := slot_valid io.out_uop := next_uop io.will_be_valid := next_valid && !killed when (io.kill) { slot_valid := false.B } .elsewhen (io.in_uop.valid) { slot_valid := true.B } .elsewhen (io.clear) { slot_valid := false.B } .otherwise { slot_valid := next_valid && !killed } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (!slot_valid \|\| io.clear \|\| io.kill) } .otherwise { slot_uop := next_uop } // Wakeups next_uop.iw_p1_bypass_hint := false.B next_uop.iw_p2_bypass_hint := false.B next_uop.iw_p3_bypass_hint := false.B next_uop.iw_p1_speculative_child := 0.U next_uop.iw_p2_speculative_child := 0.U val rebusied_prs1 = WireInit(false.B) val rebusied_prs2 = WireInit(false.B) val rebusied = rebusied_prs1 \|\| rebusied_prs2 val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 } val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 } val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 } val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m } val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m } val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m } val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m } val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m } val bypassables = io.wakeup_ports.map { w => w.bits.bypassable } val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask } when (prs1_wakeups.reduce(_\|\|_)) { next_uop.prs1_busy := false.B next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks) next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables) } when ((prs1_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) && slot_uop.lrs1_rtype === RT_FIX) { next_uop.prs1_busy := true.B rebusied_prs1 := true.B } when (prs2_wakeups.reduce(_\|\|_)) { next_uop.prs2_busy := false.B next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks) next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables) } when ((prs2_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) && slot_uop.lrs2_rtype === RT_FIX) { next_uop.prs2_busy := true.B rebusied_prs2 := true.B } when (prs3_wakeups.reduce(_\|\|_)) { next_uop.prs3_busy := false.B next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables) } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) { next_uop.ppred_busy := false.B } val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B) val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) io.request := slot_valid && !slot_uop.iw_issued && ( iss_ready \|\| agen_ready \|\| dgen_ready ) io.iss_uop := slot_uop // Update state for current micro-op based on grant next_uop.iw_issued := false.B next_uop.iw_issued_partial_agen := false.B next_uop.iw_issued_partial_dgen := false.B when (io.grant && !io.squash_grant) { next_uop.iw_issued := true.B } if (isMem) { when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) { when (agen_ready) { // Issue the AGEN, next slot entry is a DGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_agen := true.B } io.iss_uop.fu_code(FC_AGEN) := true.B io.iss_uop.fu_code(FC_DGEN) := false.B } .otherwise { // Issue the DGEN, next slot entry is the AGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_dgen := true.B } io.iss_uop.fu_code(FC_AGEN) := false.B io.iss_uop.fu_code(FC_DGEN) := true.B io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } } .elsewhen (slot_uop.fu_code(FC_DGEN)) { io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } io.iss_uop.lrs2_rtype := RT_X io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE } when (slot_valid && slot_uop.iw_issued) { next_valid := rebusied if (isMem) { when (slot_uop.iw_issued_partial_agen) { next_valid := true.B when (!rebusied_prs1) { next_uop.fu_code(FC_AGEN) := false.B next_uop.fu_code(FC_DGEN) := true.B } } .elsewhen (slot_uop.iw_issued_partial_dgen) { next_valid := true.B when (!rebusied_prs2) { next_uop.fu_code(FC_AGEN) := true.B next_uop.fu_code(FC_DGEN) := false.B } } } } }	module IssueSlot_23( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [11:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [11:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [1:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [11:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire [1:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:49:7] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire [1:0] io_iss_uop_lrs2_rtype = 2'h2; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-slot.scala:49:7] wire [1:0] _next_uop_iw_p1_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _next_uop_iw_p2_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [1:0] io_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0 = io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_agen; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen; // @[issue-slot.scala:59:28] wire [1:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [1:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [11:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [5:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [3:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [3:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [11:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [11:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg slot_uop_iw_issued_partial_agen; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_partial_agen_0 = slot_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued_partial_agen = slot_uop_iw_issued_partial_agen; // @[util.scala:104:23] reg slot_uop_iw_issued_partial_dgen; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_partial_dgen_0 = slot_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued_partial_dgen = slot_uop_iw_issued_partial_dgen; // @[util.scala:104:23] reg [1:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [1:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [1:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [11:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [5:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [3:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [3:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [11:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_ppred_busy = next_uop_out_ppred_busy; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [11:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_partial_agen_0 = next_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_partial_dgen_0 = next_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [11:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = \|_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 \| io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to the following Chisel files. File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ class IntXbar()(implicit p: Parameters) extends LazyModule { val intnode = new IntNexusNode( sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, sourceFn = { seq => IntSourcePortParameters((seq zip seq.map(_.num).scanLeft(0)(_+_).init).map { case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o))) }.flatten) }) { override def circuitIdentity = outputs == 1 && inputs == 1 } lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { override def desiredName = s"IntXbar_i${intnode.in.size}_o${intnode.out.size}" val cat = intnode.in.map { case (i, e) => i.take(e.source.num) }.flatten intnode.out.foreach { case (o, _) => o := cat } } } class IntSyncXbar()(implicit p: Parameters) extends LazyModule { val intnode = new IntSyncNexusNode( sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, sourceFn = { seq => IntSourcePortParameters((seq zip seq.map(_.num).scanLeft(0)(_+_).init).map { case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o))) }.flatten) }) { override def circuitIdentity = outputs == 1 && inputs == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncXbar_i${intnode.in.size}_o${intnode.out.size}" val cat = intnode.in.map { case (i, e) => i.sync.take(e.source.num) }.flatten intnode.out.foreach { case (o, _) => o.sync := cat } } } object IntXbar { def apply()(implicit p: Parameters): IntNode = { val xbar = LazyModule(new IntXbar) xbar.intnode } } object IntSyncXbar { def apply()(implicit p: Parameters): IntSyncNode = { val xbar = LazyModule(new IntSyncXbar) xbar.intnode } }	module IntXbar_i4_o1_7( // @[Xbar.scala:22:9] input auto_anon_in_3_0, // @[LazyModuleImp.scala:107:25] input auto_anon_in_2_0, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_0, // @[LazyModuleImp.scala:107:25] input auto_anon_in_1_1, // @[LazyModuleImp.scala:107:25] input auto_anon_in_0_0, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1, // @[LazyModuleImp.scala:107:25] output auto_anon_out_2, // @[LazyModuleImp.scala:107:25] output auto_anon_out_3, // @[LazyModuleImp.scala:107:25] output auto_anon_out_4 // @[LazyModuleImp.scala:107:25] ); wire auto_anon_in_3_0_0 = auto_anon_in_3_0; // @[Xbar.scala:22:9] wire auto_anon_in_2_0_0 = auto_anon_in_2_0; // @[Xbar.scala:22:9] wire auto_anon_in_1_0_0 = auto_anon_in_1_0; // @[Xbar.scala:22:9] wire auto_anon_in_1_1_0 = auto_anon_in_1_1; // @[Xbar.scala:22:9] wire auto_anon_in_0_0_0 = auto_anon_in_0_0; // @[Xbar.scala:22:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire anonIn_3_0 = auto_anon_in_3_0_0; // @[Xbar.scala:22:9] wire anonIn_2_0 = auto_anon_in_2_0_0; // @[Xbar.scala:22:9] wire anonIn_1_0 = auto_anon_in_1_0_0; // @[Xbar.scala:22:9] wire anonIn_1_1 = auto_anon_in_1_1_0; // @[Xbar.scala:22:9] wire anonIn_0 = auto_anon_in_0_0_0; // @[Xbar.scala:22:9] wire anonOut_0; // @[MixedNode.scala:542:17] wire anonOut_1; // @[MixedNode.scala:542:17] wire anonOut_2; // @[MixedNode.scala:542:17] wire anonOut_3; // @[MixedNode.scala:542:17] wire anonOut_4; // @[MixedNode.scala:542:17] wire auto_anon_out_0_0; // @[Xbar.scala:22:9] wire auto_anon_out_1_0; // @[Xbar.scala:22:9] wire auto_anon_out_2_0; // @[Xbar.scala:22:9] wire auto_anon_out_3_0; // @[Xbar.scala:22:9] wire auto_anon_out_4_0; // @[Xbar.scala:22:9] assign anonOut_0 = anonIn_0; // @[MixedNode.scala:542:17, :551:17] assign anonOut_1 = anonIn_1_0; // @[MixedNode.scala:542:17, :551:17] assign anonOut_2 = anonIn_1_1; // @[MixedNode.scala:542:17, :551:17] assign anonOut_3 = anonIn_2_0; // @[MixedNode.scala:542:17, :551:17] assign anonOut_4 = anonIn_3_0; // @[MixedNode.scala:542:17, :551:17] assign auto_anon_out_0_0 = anonOut_0; // @[Xbar.scala:22:9] assign auto_anon_out_1_0 = anonOut_1; // @[Xbar.scala:22:9] assign auto_anon_out_2_0 = anonOut_2; // @[Xbar.scala:22:9] assign auto_anon_out_3_0 = anonOut_3; // @[Xbar.scala:22:9] assign auto_anon_out_4_0 = anonOut_4; // @[Xbar.scala:22:9] assign auto_anon_out_0 = auto_anon_out_0_0; // @[Xbar.scala:22:9] assign auto_anon_out_1 = auto_anon_out_1_0; // @[Xbar.scala:22:9] assign auto_anon_out_2 = auto_anon_out_2_0; // @[Xbar.scala:22:9] assign auto_anon_out_3 = auto_anon_out_3_0; // @[Xbar.scala:22:9] assign auto_anon_out_4 = auto_anon_out_4_0; // @[Xbar.scala:22:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_27( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [11:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [11:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_first_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_first_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_wo_ready_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_wo_ready_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_interm_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_interm_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_opcodes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_opcodes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_sizes_set_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_sizes_set_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _c_probe_ack_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _c_probe_ack_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_1_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_2_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_3_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [11:0] _same_cycle_resp_WIRE_4_bits_address = 12'h0; // @[Bundles.scala:265:74] wire [11:0] _same_cycle_resp_WIRE_5_bits_address = 12'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34] wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34] wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34] wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 8'h50; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 6'h10; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 6'h11; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 6'h12; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 6'h13; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 8'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_27 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_33 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire _source_ok_T_28 = _source_ok_T_27 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = _source_ok_T_33 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 8'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire _source_ok_T_41 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 \| _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_49 \| _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [11:0] _is_aligned_T = {6'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 12'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_22 = _uncommonBits_T_22[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_23 = _uncommonBits_T_23[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_28 = _uncommonBits_T_28[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_29 = _uncommonBits_T_29[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_34 = _uncommonBits_T_34[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_35 = _uncommonBits_T_35[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_40 = _uncommonBits_T_40[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_41 = _uncommonBits_T_41[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_46 = _uncommonBits_T_46[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_47 = _uncommonBits_T_47[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_52 = _uncommonBits_T_52[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_53 = _uncommonBits_T_53[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_58 = _uncommonBits_T_58[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_59 = _uncommonBits_T_59[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_64 = _uncommonBits_T_64[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_65 = _uncommonBits_T_65[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = io_in_d_bits_source_0 == 8'h50; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_51 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_57 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_63 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_69 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_52 = _source_ok_T_51 == 6'h10; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_58 = _source_ok_T_57 == 6'h11; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_64 = _source_ok_T_63 == 6'h12; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_70 = _source_ok_T_69 == 6'h13; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = io_in_d_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_75; // @[Parameters.scala:1138:31] wire _source_ok_T_76 = io_in_d_bits_source_0 == 8'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_77 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_83 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire _source_ok_T_78 = _source_ok_T_77 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_7 = _source_ok_T_82; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_84 = _source_ok_T_83 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31] wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire _source_ok_T_91 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_92 = _source_ok_T_91 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_93 = _source_ok_T_92 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_94 = _source_ok_T_93 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_95 = _source_ok_T_94 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_96 = _source_ok_T_95 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_97 = _source_ok_T_96 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_98 = _source_ok_T_97 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_99 = _source_ok_T_98 \| _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_99 \| _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _T_1266 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1266; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1266; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [11:0] address; // @[Monitor.scala:391:22] wire _T_1334 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1334; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1334; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1334; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [515:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [128:0] a_set; // @[Monitor.scala:626:34] wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [515:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1199 = _T_1266 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1199 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1199 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1199 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1199 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1199 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [128:0] d_clr; // @[Monitor.scala:664:34] wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1245 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1245 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1214 = _T_1334 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1214 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1214 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1214 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [128:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [515:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [515:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [128:0] inflight_1; // @[Monitor.scala:726:35] wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [128:0] d_clr_1; // @[Monitor.scala:774:34] wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [515:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1310 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1310 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1292 = _T_1334 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1292 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1292 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1292 ? _d_sizes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [515:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File SinkA.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class PutBufferAEntry(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val data = UInt(params.inner.bundle.dataBits.W) val mask = UInt((params.inner.bundle.dataBits/8).W) val corrupt = Bool() } class PutBufferPop(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val index = UInt(params.putBits.W) val last = Bool() } class SinkA(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val req = Decoupled(new FullRequest(params)) val a = Flipped(Decoupled(new TLBundleA(params.inner.bundle))) // for use by SourceD: val pb_pop = Flipped(Decoupled(new PutBufferPop(params))) val pb_beat = new PutBufferAEntry(params) }) // No restrictions on the type of buffer val a = params.micro.innerBuf.a(io.a) val putbuffer = Module(new ListBuffer(ListBufferParameters(new PutBufferAEntry(params), params.putLists, params.putBeats, false))) val lists = RegInit((0.U(params.putLists.W))) val lists_set = WireInit(init = 0.U(params.putLists.W)) val lists_clr = WireInit(init = 0.U(params.putLists.W)) lists := (lists \| lists_set) & ~lists_clr val free = !lists.andR val freeOH = ~(leftOR(~lists) << 1) & ~lists val freeIdx = OHToUInt(freeOH) val first = params.inner.first(a) val hasData = params.inner.hasData(a.bits) // We need to split the A input to three places: // If it is the first beat, it must go to req // If it has Data, it must go to the putbuffer // If it has Data AND is the first beat, it must claim a list val req_block = first && !io.req.ready val buf_block = hasData && !putbuffer.io.push.ready val set_block = hasData && first && !free params.ccover(a.valid && req_block, "SINKA_REQ_STALL", "No MSHR available to sink request") params.ccover(a.valid && buf_block, "SINKA_BUF_STALL", "No space in putbuffer for beat") params.ccover(a.valid && set_block, "SINKA_SET_STALL", "No space in putbuffer for request") a.ready := !req_block && !buf_block && !set_block io.req.valid := a.valid && first && !buf_block && !set_block putbuffer.io.push.valid := a.valid && hasData && !req_block && !set_block when (a.valid && first && hasData && !req_block && !buf_block) { lists_set := freeOH } val (tag, set, offset) = params.parseAddress(a.bits.address) val put = Mux(first, freeIdx, RegEnable(freeIdx, first)) io.req.bits.prio := VecInit(1.U(3.W).asBools) io.req.bits.control:= false.B io.req.bits.opcode := a.bits.opcode io.req.bits.param := a.bits.param io.req.bits.size := a.bits.size io.req.bits.source := a.bits.source io.req.bits.offset := offset io.req.bits.set := set io.req.bits.tag := tag io.req.bits.put := put putbuffer.io.push.bits.index := put putbuffer.io.push.bits.data.data := a.bits.data putbuffer.io.push.bits.data.mask := a.bits.mask putbuffer.io.push.bits.data.corrupt := a.bits.corrupt // Grant access to pop the data putbuffer.io.pop.bits := io.pb_pop.bits.index putbuffer.io.pop.valid := io.pb_pop.fire io.pb_pop.ready := putbuffer.io.valid(io.pb_pop.bits.index) io.pb_beat := putbuffer.io.data when (io.pb_pop.fire && io.pb_pop.bits.last) { lists_clr := UIntToOH(io.pb_pop.bits.index, params.putLists) } } File Parameters.scala: / * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relListscache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_\|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x \| 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ \|\| _) (matches, bits.U) } expanded \| Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) \|\| (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) \|\| ((opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm \|\| opcode === TLMessages.Get \|\| (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN \|\| param === TLPermissions.BtoN \|\| param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB \|\| param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module SinkA( // @[SinkA.scala:38:7] input clock, // @[SinkA.scala:38:7] input reset, // @[SinkA.scala:38:7] input io_req_ready, // @[SinkA.scala:40:14] output io_req_valid, // @[SinkA.scala:40:14] output [2:0] io_req_bits_opcode, // @[SinkA.scala:40:14] output [2:0] io_req_bits_param, // @[SinkA.scala:40:14] output [2:0] io_req_bits_size, // @[SinkA.scala:40:14] output [8:0] io_req_bits_source, // @[SinkA.scala:40:14] output [12:0] io_req_bits_tag, // @[SinkA.scala:40:14] output [5:0] io_req_bits_offset, // @[SinkA.scala:40:14] output [5:0] io_req_bits_put, // @[SinkA.scala:40:14] output [9:0] io_req_bits_set, // @[SinkA.scala:40:14] output io_a_ready, // @[SinkA.scala:40:14] input io_a_valid, // @[SinkA.scala:40:14] input [2:0] io_a_bits_opcode, // @[SinkA.scala:40:14] input [2:0] io_a_bits_param, // @[SinkA.scala:40:14] input [2:0] io_a_bits_size, // @[SinkA.scala:40:14] input [8:0] io_a_bits_source, // @[SinkA.scala:40:14] input [31:0] io_a_bits_address, // @[SinkA.scala:40:14] input [7:0] io_a_bits_mask, // @[SinkA.scala:40:14] input [63:0] io_a_bits_data, // @[SinkA.scala:40:14] input io_a_bits_corrupt, // @[SinkA.scala:40:14] output io_pb_pop_ready, // @[SinkA.scala:40:14] input io_pb_pop_valid, // @[SinkA.scala:40:14] input [5:0] io_pb_pop_bits_index, // @[SinkA.scala:40:14] input io_pb_pop_bits_last, // @[SinkA.scala:40:14] output [63:0] io_pb_beat_data, // @[SinkA.scala:40:14] output [7:0] io_pb_beat_mask, // @[SinkA.scala:40:14] output io_pb_beat_corrupt // @[SinkA.scala:40:14] ); wire _putbuffer_io_push_ready; // @[SinkA.scala:51:25] wire [39:0] _putbuffer_io_valid; // @[SinkA.scala:51:25] wire io_req_ready_0 = io_req_ready; // @[SinkA.scala:38:7] wire io_a_valid_0 = io_a_valid; // @[SinkA.scala:38:7] wire [2:0] io_a_bits_opcode_0 = io_a_bits_opcode; // @[SinkA.scala:38:7] wire [2:0] io_a_bits_param_0 = io_a_bits_param; // @[SinkA.scala:38:7] wire [2:0] io_a_bits_size_0 = io_a_bits_size; // @[SinkA.scala:38:7] wire [8:0] io_a_bits_source_0 = io_a_bits_source; // @[SinkA.scala:38:7] wire [31:0] io_a_bits_address_0 = io_a_bits_address; // @[SinkA.scala:38:7] wire [7:0] io_a_bits_mask_0 = io_a_bits_mask; // @[SinkA.scala:38:7] wire [63:0] io_a_bits_data_0 = io_a_bits_data; // @[SinkA.scala:38:7] wire io_a_bits_corrupt_0 = io_a_bits_corrupt; // @[SinkA.scala:38:7] wire io_pb_pop_valid_0 = io_pb_pop_valid; // @[SinkA.scala:38:7] wire [5:0] io_pb_pop_bits_index_0 = io_pb_pop_bits_index; // @[SinkA.scala:38:7] wire io_pb_pop_bits_last_0 = io_pb_pop_bits_last; // @[SinkA.scala:38:7] wire io_req_bits_prio_1 = 1'h0; // @[SinkA.scala:38:7] wire io_req_bits_prio_2 = 1'h0; // @[SinkA.scala:38:7] wire io_req_bits_control = 1'h0; // @[SinkA.scala:38:7] wire io_req_bits_prio_0 = 1'h1; // @[SinkA.scala:38:7] wire _io_req_valid_T_4; // @[SinkA.scala:79:50] wire [12:0] tag_1; // @[Parameters.scala:217:9] wire [5:0] offset_1; // @[Parameters.scala:217:50] wire [5:0] put; // @[SinkA.scala:84:16] wire [9:0] set_1; // @[Parameters.scala:217:28] wire _io_a_ready_T_4; // @[SinkA.scala:78:39] wire [2:0] io_req_bits_opcode_0 = io_a_bits_opcode_0; // @[SinkA.scala:38:7] wire [2:0] io_req_bits_param_0 = io_a_bits_param_0; // @[SinkA.scala:38:7] wire [2:0] io_req_bits_size_0 = io_a_bits_size_0; // @[SinkA.scala:38:7] wire [8:0] io_req_bits_source_0 = io_a_bits_source_0; // @[SinkA.scala:38:7] wire _io_pb_pop_ready_T_1; // @[SinkA.scala:105:40] wire [5:0] lists_clr_shiftAmount = io_pb_pop_bits_index_0; // @[OneHot.scala:64:49] wire [12:0] io_req_bits_tag_0; // @[SinkA.scala:38:7] wire [5:0] io_req_bits_offset_0; // @[SinkA.scala:38:7] wire [5:0] io_req_bits_put_0; // @[SinkA.scala:38:7] wire [9:0] io_req_bits_set_0; // @[SinkA.scala:38:7] wire io_req_valid_0; // @[SinkA.scala:38:7] wire io_a_ready_0; // @[SinkA.scala:38:7] wire io_pb_pop_ready_0; // @[SinkA.scala:38:7] wire [63:0] io_pb_beat_data_0; // @[SinkA.scala:38:7] wire [7:0] io_pb_beat_mask_0; // @[SinkA.scala:38:7] wire io_pb_beat_corrupt_0; // @[SinkA.scala:38:7] reg [39:0] lists; // @[SinkA.scala:52:22] wire [39:0] lists_set; // @[SinkA.scala:54:27] wire [39:0] lists_clr; // @[SinkA.scala:55:27] wire [39:0] _lists_T = lists \| lists_set; // @[SinkA.scala:52:22, :54:27, :56:19] wire [39:0] _lists_T_1 = ~lists_clr; // @[SinkA.scala:55:27, :56:34] wire [39:0] _lists_T_2 = _lists_T & _lists_T_1; // @[SinkA.scala:56:{19,32,34}] wire _free_T = &lists; // @[SinkA.scala:52:22, :58:21] wire free = ~_free_T; // @[SinkA.scala:58:{14,21}] wire [39:0] _freeOH_T = ~lists; // @[SinkA.scala:52:22, :59:25] wire [40:0] _freeOH_T_1 = {_freeOH_T, 1'h0}; // @[package.scala:253:48] wire [39:0] _freeOH_T_2 = _freeOH_T_1[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_3 = _freeOH_T \| _freeOH_T_2; // @[package.scala:253:{43,53}] wire [41:0] _freeOH_T_4 = {_freeOH_T_3, 2'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_5 = _freeOH_T_4[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_6 = _freeOH_T_3 \| _freeOH_T_5; // @[package.scala:253:{43,53}] wire [43:0] _freeOH_T_7 = {_freeOH_T_6, 4'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_8 = _freeOH_T_7[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_9 = _freeOH_T_6 \| _freeOH_T_8; // @[package.scala:253:{43,53}] wire [47:0] _freeOH_T_10 = {_freeOH_T_9, 8'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_11 = _freeOH_T_10[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_12 = _freeOH_T_9 \| _freeOH_T_11; // @[package.scala:253:{43,53}] wire [55:0] _freeOH_T_13 = {_freeOH_T_12, 16'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_14 = _freeOH_T_13[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_15 = _freeOH_T_12 \| _freeOH_T_14; // @[package.scala:253:{43,53}] wire [71:0] _freeOH_T_16 = {_freeOH_T_15, 32'h0}; // @[package.scala:253:{43,48}] wire [39:0] _freeOH_T_17 = _freeOH_T_16[39:0]; // @[package.scala:253:{48,53}] wire [39:0] _freeOH_T_18 = _freeOH_T_15 \| _freeOH_T_17; // @[package.scala:253:{43,53}] wire [39:0] _freeOH_T_19 = _freeOH_T_18; // @[package.scala:253:43, :254:17] wire [40:0] _freeOH_T_20 = {_freeOH_T_19, 1'h0}; // @[package.scala:254:17] wire [40:0] _freeOH_T_21 = ~_freeOH_T_20; // @[SinkA.scala:59:{16,33}] wire [39:0] _freeOH_T_22 = ~lists; // @[SinkA.scala:52:22, :59:{25,41}] wire [40:0] freeOH = {1'h0, _freeOH_T_21[39:0] & _freeOH_T_22}; // @[SinkA.scala:59:{16,39,41}] wire [8:0] freeIdx_hi = freeOH[40:32]; // @[OneHot.scala:30:18] wire [31:0] freeIdx_lo = freeOH[31:0]; // @[OneHot.scala:31:18] wire _freeIdx_T = \|freeIdx_hi; // @[OneHot.scala:30:18, :32:14] wire [31:0] _freeIdx_T_1 = {23'h0, freeIdx_hi} \| freeIdx_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [15:0] freeIdx_hi_1 = _freeIdx_T_1[31:16]; // @[OneHot.scala:30:18, :32:28] wire [15:0] freeIdx_lo_1 = _freeIdx_T_1[15:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_2 = \|freeIdx_hi_1; // @[OneHot.scala:30:18, :32:14] wire [15:0] _freeIdx_T_3 = freeIdx_hi_1 \| freeIdx_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] freeIdx_hi_2 = _freeIdx_T_3[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] freeIdx_lo_2 = _freeIdx_T_3[7:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_4 = \|freeIdx_hi_2; // @[OneHot.scala:30:18, :32:14] wire [7:0] _freeIdx_T_5 = freeIdx_hi_2 \| freeIdx_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] freeIdx_hi_3 = _freeIdx_T_5[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] freeIdx_lo_3 = _freeIdx_T_5[3:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_6 = \|freeIdx_hi_3; // @[OneHot.scala:30:18, :32:14] wire [3:0] _freeIdx_T_7 = freeIdx_hi_3 \| freeIdx_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] freeIdx_hi_4 = _freeIdx_T_7[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] freeIdx_lo_4 = _freeIdx_T_7[1:0]; // @[OneHot.scala:31:18, :32:28] wire _freeIdx_T_8 = \|freeIdx_hi_4; // @[OneHot.scala:30:18, :32:14] wire [1:0] _freeIdx_T_9 = freeIdx_hi_4 \| freeIdx_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28] wire _freeIdx_T_10 = _freeIdx_T_9[1]; // @[OneHot.scala:32:28] wire [1:0] _freeIdx_T_11 = {_freeIdx_T_8, _freeIdx_T_10}; // @[OneHot.scala:32:{10,14}] wire [2:0] _freeIdx_T_12 = {_freeIdx_T_6, _freeIdx_T_11}; // @[OneHot.scala:32:{10,14}] wire [3:0] _freeIdx_T_13 = {_freeIdx_T_4, _freeIdx_T_12}; // @[OneHot.scala:32:{10,14}] wire [4:0] _freeIdx_T_14 = {_freeIdx_T_2, _freeIdx_T_13}; // @[OneHot.scala:32:{10,14}] wire [5:0] freeIdx = {_freeIdx_T, _freeIdx_T_14}; // @[OneHot.scala:32:{10,14}] wire _first_T = io_a_ready_0 & io_a_valid_0; // @[Decoupled.scala:51:35] wire [12:0] _first_beats1_decode_T = 13'h3F << io_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _first_beats1_decode_T_1 = _first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _first_beats1_decode_T_2 = ~_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] first_beats1_decode = _first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _first_beats1_opdata_T = io_a_bits_opcode_0[2]; // @[Edges.scala:92:37] wire _hasData_opdata_T = io_a_bits_opcode_0[2]; // @[Edges.scala:92:37] wire first_beats1_opdata = ~_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] first_beats1 = first_beats1_opdata ? first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] first_counter; // @[Edges.scala:229:27] wire [3:0] _first_counter1_T = {1'h0, first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] first_counter1 = _first_counter1_T[2:0]; // @[Edges.scala:230:28] wire first = first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _first_last_T = first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _first_last_T_1 = first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire first_last = _first_last_T \| _first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire first_done = first_last & _first_T; // @[Decoupled.scala:51:35] wire [2:0] _first_count_T = ~first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] first_count = first_beats1 & _first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _first_counter_T = first ? first_beats1 : first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire hasData = ~_hasData_opdata_T; // @[Edges.scala:92:{28,37}] wire _req_block_T = ~io_req_ready_0; // @[SinkA.scala:38:7, :70:28] wire req_block = first & _req_block_T; // @[Edges.scala:231:25] wire _buf_block_T = ~_putbuffer_io_push_ready; // @[SinkA.scala:51:25, :71:30] wire buf_block = hasData & _buf_block_T; // @[Edges.scala:92:28] wire _set_block_T = hasData & first; // @[Edges.scala:92:28, :231:25] wire _set_block_T_1 = ~free; // @[SinkA.scala:58:14, :72:39] wire set_block = _set_block_T & _set_block_T_1; // @[SinkA.scala:72:{27,36,39}] wire _io_a_ready_T = ~req_block; // @[SinkA.scala:70:25, :78:14] wire _io_a_ready_T_1 = ~buf_block; // @[SinkA.scala:71:27, :78:28] wire _io_a_ready_T_2 = _io_a_ready_T & _io_a_ready_T_1; // @[SinkA.scala:78:{14,25,28}] wire _io_a_ready_T_3 = ~set_block; // @[SinkA.scala:72:36, :78:42] assign _io_a_ready_T_4 = _io_a_ready_T_2 & _io_a_ready_T_3; // @[SinkA.scala:78:{25,39,42}] assign io_a_ready_0 = _io_a_ready_T_4; // @[SinkA.scala:38:7, :78:39] wire _io_req_valid_T = io_a_valid_0 & first; // @[Edges.scala:231:25] wire _io_req_valid_T_1 = ~buf_block; // @[SinkA.scala:71:27, :78:28, :79:39] wire _io_req_valid_T_2 = _io_req_valid_T & _io_req_valid_T_1; // @[SinkA.scala:79:{27,36,39}] wire _io_req_valid_T_3 = ~set_block; // @[SinkA.scala:72:36, :78:42, :79:53] assign _io_req_valid_T_4 = _io_req_valid_T_2 & _io_req_valid_T_3; // @[SinkA.scala:79:{36,50,53}] assign io_req_valid_0 = _io_req_valid_T_4; // @[SinkA.scala:38:7, :79:50] wire _putbuffer_io_push_valid_T = io_a_valid_0 & hasData; // @[Edges.scala:92:28] wire _putbuffer_io_push_valid_T_1 = ~req_block; // @[SinkA.scala:70:25, :78:14, :80:52] wire _putbuffer_io_push_valid_T_2 = _putbuffer_io_push_valid_T & _putbuffer_io_push_valid_T_1; // @[SinkA.scala:80:{38,49,52}] wire _putbuffer_io_push_valid_T_3 = ~set_block; // @[SinkA.scala:72:36, :78:42, :80:66] wire _putbuffer_io_push_valid_T_4 = _putbuffer_io_push_valid_T_2 & _putbuffer_io_push_valid_T_3; // @[SinkA.scala:80:{49,63,66}] assign lists_set = _io_req_valid_T & hasData & ~req_block & ~buf_block ? freeOH[39:0] : 40'h0; // @[Edges.scala:92:28] wire _offset_T = io_a_bits_address_0[0]; // @[SinkA.scala:38:7] wire _offset_T_1 = io_a_bits_address_0[1]; // @[SinkA.scala:38:7] wire _offset_T_2 = io_a_bits_address_0[2]; // @[SinkA.scala:38:7] wire _offset_T_3 = io_a_bits_address_0[3]; // @[SinkA.scala:38:7] wire _offset_T_4 = io_a_bits_address_0[4]; // @[SinkA.scala:38:7] wire _offset_T_5 = io_a_bits_address_0[5]; // @[SinkA.scala:38:7] wire _offset_T_6 = io_a_bits_address_0[6]; // @[SinkA.scala:38:7] wire _offset_T_7 = io_a_bits_address_0[7]; // @[SinkA.scala:38:7] wire _offset_T_8 = io_a_bits_address_0[8]; // @[SinkA.scala:38:7] wire _offset_T_9 = io_a_bits_address_0[9]; // @[SinkA.scala:38:7] wire _offset_T_10 = io_a_bits_address_0[10]; // @[SinkA.scala:38:7] wire _offset_T_11 = io_a_bits_address_0[11]; // @[SinkA.scala:38:7] wire _offset_T_12 = io_a_bits_address_0[12]; // @[SinkA.scala:38:7] wire _offset_T_13 = io_a_bits_address_0[13]; // @[SinkA.scala:38:7] wire _offset_T_14 = io_a_bits_address_0[14]; // @[SinkA.scala:38:7] wire _offset_T_15 = io_a_bits_address_0[15]; // @[SinkA.scala:38:7] wire _offset_T_16 = io_a_bits_address_0[16]; // @[SinkA.scala:38:7] wire _offset_T_17 = io_a_bits_address_0[17]; // @[SinkA.scala:38:7] wire _offset_T_18 = io_a_bits_address_0[18]; // @[SinkA.scala:38:7] wire _offset_T_19 = io_a_bits_address_0[19]; // @[SinkA.scala:38:7] wire _offset_T_20 = io_a_bits_address_0[20]; // @[SinkA.scala:38:7] wire _offset_T_21 = io_a_bits_address_0[21]; // @[SinkA.scala:38:7] wire _offset_T_22 = io_a_bits_address_0[22]; // @[SinkA.scala:38:7] wire _offset_T_23 = io_a_bits_address_0[23]; // @[SinkA.scala:38:7] wire _offset_T_24 = io_a_bits_address_0[24]; // @[SinkA.scala:38:7] wire _offset_T_25 = io_a_bits_address_0[25]; // @[SinkA.scala:38:7] wire _offset_T_26 = io_a_bits_address_0[26]; // @[SinkA.scala:38:7] wire _offset_T_27 = io_a_bits_address_0[27]; // @[SinkA.scala:38:7] wire _offset_T_28 = io_a_bits_address_0[31]; // @[SinkA.scala:38:7] wire [1:0] offset_lo_lo_lo_hi = {_offset_T_2, _offset_T_1}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_lo_lo_lo = {offset_lo_lo_lo_hi, _offset_T}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_lo_hi_lo = {_offset_T_4, _offset_T_3}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_lo_hi_hi = {_offset_T_6, _offset_T_5}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_lo_lo_hi = {offset_lo_lo_hi_hi, offset_lo_lo_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_lo_lo = {offset_lo_lo_hi, offset_lo_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_lo_hi_lo_hi = {_offset_T_9, _offset_T_8}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_lo_hi_lo = {offset_lo_hi_lo_hi, _offset_T_7}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_hi_hi_lo = {_offset_T_11, _offset_T_10}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_lo_hi_hi_hi = {_offset_T_13, _offset_T_12}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_lo_hi_hi = {offset_lo_hi_hi_hi, offset_lo_hi_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_lo_hi = {offset_lo_hi_hi, offset_lo_hi_lo}; // @[Parameters.scala:214:21] wire [13:0] offset_lo = {offset_lo_hi, offset_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_hi_lo_lo_hi = {_offset_T_16, _offset_T_15}; // @[Parameters.scala:214:{21,47}] wire [2:0] offset_hi_lo_lo = {offset_hi_lo_lo_hi, _offset_T_14}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_lo_hi_lo = {_offset_T_18, _offset_T_17}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_lo_hi_hi = {_offset_T_20, _offset_T_19}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_hi_lo_hi = {offset_hi_lo_hi_hi, offset_hi_lo_hi_lo}; // @[Parameters.scala:214:21] wire [6:0] offset_hi_lo = {offset_hi_lo_hi, offset_hi_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_hi_hi_lo_lo = {_offset_T_22, _offset_T_21}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_hi_lo_hi = {_offset_T_24, _offset_T_23}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_hi_hi_lo = {offset_hi_hi_lo_hi, offset_hi_hi_lo_lo}; // @[Parameters.scala:214:21] wire [1:0] offset_hi_hi_hi_lo = {_offset_T_26, _offset_T_25}; // @[Parameters.scala:214:{21,47}] wire [1:0] offset_hi_hi_hi_hi = {_offset_T_28, _offset_T_27}; // @[Parameters.scala:214:{21,47}] wire [3:0] offset_hi_hi_hi = {offset_hi_hi_hi_hi, offset_hi_hi_hi_lo}; // @[Parameters.scala:214:21] wire [7:0] offset_hi_hi = {offset_hi_hi_hi, offset_hi_hi_lo}; // @[Parameters.scala:214:21] wire [14:0] offset_hi = {offset_hi_hi, offset_hi_lo}; // @[Parameters.scala:214:21] wire [28:0] offset = {offset_hi, offset_lo}; // @[Parameters.scala:214:21] wire [22:0] set = offset[28:6]; // @[Parameters.scala:214:21, :215:22] wire [12:0] tag = set[22:10]; // @[Parameters.scala:215:22, :216:19] assign tag_1 = tag; // @[Parameters.scala:216:19, :217:9] assign io_req_bits_tag_0 = tag_1; // @[SinkA.scala:38:7] assign set_1 = set[9:0]; // @[Parameters.scala:215:22, :217:28] assign io_req_bits_set_0 = set_1; // @[SinkA.scala:38:7] assign offset_1 = offset[5:0]; // @[Parameters.scala:214:21, :217:50] assign io_req_bits_offset_0 = offset_1; // @[SinkA.scala:38:7] reg [5:0] put_r; // @[SinkA.scala:84:42] assign put = first ? freeIdx : put_r; // @[OneHot.scala:32:10] assign io_req_bits_put_0 = put; // @[SinkA.scala:38:7, :84:16] wire _putbuffer_io_pop_valid_T = io_pb_pop_ready_0 & io_pb_pop_valid_0; // @[Decoupled.scala:51:35] wire [39:0] _io_pb_pop_ready_T = _putbuffer_io_valid >> io_pb_pop_bits_index_0; // @[SinkA.scala:38:7, :51:25, :105:40] assign _io_pb_pop_ready_T_1 = _io_pb_pop_ready_T[0]; // @[SinkA.scala:105:40] assign io_pb_pop_ready_0 = _io_pb_pop_ready_T_1; // @[SinkA.scala:38:7, :105:40] wire [63:0] _lists_clr_T = 64'h1 << lists_clr_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [39:0] _lists_clr_T_1 = _lists_clr_T[39:0]; // @[OneHot.scala:65:{12,27}] assign lists_clr = _putbuffer_io_pop_valid_T & io_pb_pop_bits_last_0 ? _lists_clr_T_1 : 40'h0; // @[OneHot.scala:65:27] always @(posedge clock) begin // @[SinkA.scala:38:7] if (reset) begin // @[SinkA.scala:38:7] lists <= 40'h0; // @[SinkA.scala:52:22] first_counter <= 3'h0; // @[Edges.scala:229:27] end else begin // @[SinkA.scala:38:7] lists <= _lists_T_2; // @[SinkA.scala:52:22, :56:32] if (_first_T) // @[Decoupled.scala:51:35] first_counter <= _first_counter_T; // @[Edges.scala:229:27, :236:21] end if (first) // @[Edges.scala:231:25] put_r <= freeIdx; // @[OneHot.scala:32:10] always @(posedge) ListBuffer_PutBufferAEntry_q40_e40 putbuffer ( // @[SinkA.scala:51:25] .clock (clock), .reset (reset), .io_push_ready (_putbuffer_io_push_ready), .io_push_valid (_putbuffer_io_push_valid_T_4), // @[SinkA.scala:80:63] .io_push_bits_index (put), // @[SinkA.scala:84:16] .io_push_bits_data_data (io_a_bits_data_0), // @[SinkA.scala:38:7] .io_push_bits_data_mask (io_a_bits_mask_0), // @[SinkA.scala:38:7] .io_push_bits_data_corrupt (io_a_bits_corrupt_0), // @[SinkA.scala:38:7] .io_valid (_putbuffer_io_valid), .io_pop_valid (_putbuffer_io_pop_valid_T), // @[Decoupled.scala:51:35] .io_pop_bits (io_pb_pop_bits_index_0), // @[SinkA.scala:38:7] .io_data_data (io_pb_beat_data_0), .io_data_mask (io_pb_beat_mask_0), .io_data_corrupt (io_pb_beat_corrupt_0) ); // @[SinkA.scala:51:25] assign io_req_valid = io_req_valid_0; // @[SinkA.scala:38:7] assign io_req_bits_opcode = io_req_bits_opcode_0; // @[SinkA.scala:38:7] assign io_req_bits_param = io_req_bits_param_0; // @[SinkA.scala:38:7] assign io_req_bits_size = io_req_bits_size_0; // @[SinkA.scala:38:7] assign io_req_bits_source = io_req_bits_source_0; // @[SinkA.scala:38:7] assign io_req_bits_tag = io_req_bits_tag_0; // @[SinkA.scala:38:7] assign io_req_bits_offset = io_req_bits_offset_0; // @[SinkA.scala:38:7] assign io_req_bits_put = io_req_bits_put_0; // @[SinkA.scala:38:7] assign io_req_bits_set = io_req_bits_set_0; // @[SinkA.scala:38:7] assign io_a_ready = io_a_ready_0; // @[SinkA.scala:38:7] assign io_pb_pop_ready = io_pb_pop_ready_0; // @[SinkA.scala:38:7] assign io_pb_beat_data = io_pb_beat_data_0; // @[SinkA.scala:38:7] assign io_pb_beat_mask = io_pb_beat_mask_0; // @[SinkA.scala:38:7] assign io_pb_beat_corrupt = io_pb_beat_corrupt_0; // @[SinkA.scala:38:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire \|\| io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) \|\| !io.outCol.fire) assert(!(state === 1.U) \|\| !io.inRow.fire) }	module PE_20( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_57( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [12:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [12:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [12:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [12:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [12:0] _c_first_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_first_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_first_WIRE_2_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_first_WIRE_3_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_set_wo_ready_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_set_wo_ready_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_set_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_set_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_opcodes_set_interm_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_opcodes_set_interm_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_sizes_set_interm_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_sizes_set_interm_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_opcodes_set_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_opcodes_set_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_sizes_set_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_sizes_set_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_probe_ack_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_probe_ack_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _c_probe_ack_WIRE_2_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _c_probe_ack_WIRE_3_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_1_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_2_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_3_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [12:0] _same_cycle_resp_WIRE_4_bits_source = 13'h0; // @[Bundles.scala:265:74] wire [12:0] _same_cycle_resp_WIRE_5_bits_source = 13'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [65537:0] _c_sizes_set_T_1 = 65538'h0; // @[Monitor.scala:768:52] wire [15:0] _c_opcodes_set_T = 16'h0; // @[Monitor.scala:767:79] wire [15:0] _c_sizes_set_T = 16'h0; // @[Monitor.scala:768:77] wire [65538:0] _c_opcodes_set_T_1 = 65539'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [8191:0] _c_set_wo_ready_T = 8192'h1; // @[OneHot.scala:58:35] wire [8191:0] _c_set_T = 8192'h1; // @[OneHot.scala:58:35] wire [16447:0] c_opcodes_set = 16448'h0; // @[Monitor.scala:740:34] wire [16447:0] c_sizes_set = 16448'h0; // @[Monitor.scala:741:34] wire [4111:0] c_set = 4112'h0; // @[Monitor.scala:738:34] wire [4111:0] c_set_wo_ready = 4112'h0; // @[Monitor.scala:739:34] wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76] wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [12:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [12:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 13'h1010; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {18'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [12:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [12:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [12:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 13'h1010; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_665; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [12:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [12:0] source_1; // @[Monitor.scala:541:22] reg [4111:0] inflight; // @[Monitor.scala:614:27] reg [16447:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [16447:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [4111:0] a_set; // @[Monitor.scala:626:34] wire [4111:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [16447:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [16447:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [15:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [15:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [15:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [15:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [15:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [15:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [15:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [15:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [16447:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [16447:0] _a_opcode_lookup_T_6 = {16444'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [16447:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[16447:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [16447:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [16447:0] _a_size_lookup_T_6 = {16444'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [16447:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[16447:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [8191:0] _GEN_2 = 8192'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [8191:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [8191:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [15:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [15:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [15:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [65538:0] _a_opcodes_set_T_1 = {65535'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[16447:0] : 16448'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [65537:0] _a_sizes_set_T_1 = {65535'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[16447:0] : 16448'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [4111:0] d_clr; // @[Monitor.scala:664:34] wire [4111:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [16447:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [16447:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [8191:0] _GEN_5 = 8192'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [8191:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [8191:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [8191:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [8191:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[4111:0] : 4112'h0; // @[OneHot.scala:58:35] wire [65550:0] _d_opcodes_clr_T_5 = 65551'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[16447:0] : 16448'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [65550:0] _d_sizes_clr_T_5 = 65551'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[16447:0] : 16448'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [4111:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [4111:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [4111:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [16447:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [16447:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [16447:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [16447:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [16447:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [16447:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [4111:0] inflight_1; // @[Monitor.scala:726:35] wire [4111:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [16447:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [16447:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [16447:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [16447:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [16447:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [16447:0] _c_opcode_lookup_T_6 = {16444'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [16447:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[16447:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [16447:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [16447:0] _c_size_lookup_T_6 = {16444'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [16447:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[16447:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [4111:0] d_clr_1; // @[Monitor.scala:774:34] wire [4111:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [16447:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [16447:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[4111:0] : 4112'h0; // @[OneHot.scala:58:35] wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_691 ? _d_clr_T_1[4111:0] : 4112'h0; // @[OneHot.scala:58:35] wire [65550:0] _d_opcodes_clr_T_11 = 65551'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[16447:0] : 16448'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [65550:0] _d_sizes_clr_T_11 = 65551'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[16447:0] : 16448'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 13'h0; // @[Monitor.scala:36:7, :795:113] wire [4111:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [4111:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [16447:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [16447:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [16447:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [16447:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File AtomicAutomata.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.util.leftOR import scala.math.{min,max} // Ensures that all downstream RW managers support Atomic operations. // If !passthrough, intercept all Atomics. Otherwise, only intercept those unsupported downstream. class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(implicit p: Parameters) extends LazyModule { require (concurrency >= 1) val node = TLAdapterNode( managerFn = { case mp => mp.v1copy(managers = mp.managers.map { m => val ourSupport = TransferSizes(1, mp.beatBytes) def widen(x: TransferSizes) = if (passthrough && x.min <= 2mp.beatBytes) TransferSizes(1, max(mp.beatBytes, x.max)) else ourSupport val canDoit = m.supportsPutFull.contains(ourSupport) && m.supportsGet.contains(ourSupport) // Blow up if there are devices to which we cannot add Atomics, because their R\|W are too inflexible require (!m.supportsPutFull \|\| !m.supportsGet \|\| canDoit, s"${m.name} has $ourSupport, needed PutFull(${m.supportsPutFull}) or Get(${m.supportsGet})") m.v1copy( supportsArithmetic = if (!arithmetic \|\| !canDoit) m.supportsArithmetic else widen(m.supportsArithmetic), supportsLogical = if (!logical \|\| !canDoit) m.supportsLogical else widen(m.supportsLogical), mayDenyGet = m.mayDenyGet \|\| m.mayDenyPut) })}) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val managers = edgeOut.manager.managers val beatBytes = edgeOut.manager.beatBytes // To which managers are we adding atomic support? val ourSupport = TransferSizes(1, beatBytes) val managersNeedingHelp = managers.filter { m => m.supportsPutFull.contains(ourSupport) && m.supportsGet.contains(ourSupport) && ((logical && !m.supportsLogical .contains(ourSupport)) \|\| (arithmetic && !m.supportsArithmetic.contains(ourSupport)) \|\| !passthrough) // we will do atomics for everyone we can } // Managers that need help with atomics must necessarily have this node as the root of a tree in the node graph. // (But they must also ensure no sideband operations can get between the read and write.) val violations = managersNeedingHelp.flatMap(_.findTreeViolation()).map { node => (node.name, node.inputs.map(_._1.name)) } require(violations.isEmpty, s"AtomicAutomata can only help nodes for which it is at the root of a diplomatic node tree," + "but the following violations were found:\n" + violations.map(v => s"(${v._1} has parents ${v._2})").mkString("\n")) // We cannot add atomics to a non-FIFO manager managersNeedingHelp foreach { m => require (m.fifoId.isDefined) } // We need to preserve FIFO semantics across FIFO domains, not managers // Suppose you have Put(42) Atomic(+1) both inflight; valid results: 42 or 43 // If we allow Put(42) Get() Put(+1) concurrent; valid results: 42 43 OR undef // Making non-FIFO work requires waiting for all Acks to come back (=> use FIFOFixer) val domainsNeedingHelp = managersNeedingHelp.map(_.fifoId.get).distinct // Don't overprovision the CAM val camSize = min(domainsNeedingHelp.size, concurrency) // Compact the fifoIds to only those we care about def camFifoId(m: TLSlaveParameters) = m.fifoId.map(id => max(0, domainsNeedingHelp.indexOf(id))).getOrElse(0) // CAM entry state machine val FREE = 0.U // unused waiting on Atomic from A val GET = 3.U // Get sent down A waiting on AccessDataAck from D val AMO = 2.U // AccessDataAck sent up D waiting for A availability val ACK = 1.U // Put sent down A waiting for PutAck from D val params = TLAtomicAutomata.CAMParams(out.a.bits.params, domainsNeedingHelp.size) // Do we need to do anything at all? if (camSize > 0) { val initval = Wire(new TLAtomicAutomata.CAM_S(params)) initval.state := FREE val cam_s = RegInit(VecInit.fill(camSize)(initval)) val cam_a = Reg(Vec(camSize, new TLAtomicAutomata.CAM_A(params))) val cam_d = Reg(Vec(camSize, new TLAtomicAutomata.CAM_D(params))) val cam_free = cam_s.map(_.state === FREE) val cam_amo = cam_s.map(_.state === AMO) val cam_abusy = cam_s.map(e => e.state === GET \|\| e.state === AMO) // A is blocked val cam_dmatch = cam_s.map(e => e.state =/= FREE) // D should inspect these entries // Can the manager already handle this message? val a_address = edgeIn.address(in.a.bits) val a_size = edgeIn.size(in.a.bits) val a_canLogical = passthrough.B && edgeOut.manager.supportsLogicalFast (a_address, a_size) val a_canArithmetic = passthrough.B && edgeOut.manager.supportsArithmeticFast(a_address, a_size) val a_isLogical = in.a.bits.opcode === TLMessages.LogicalData val a_isArithmetic = in.a.bits.opcode === TLMessages.ArithmeticData val a_isSupported = Mux(a_isLogical, a_canLogical, Mux(a_isArithmetic, a_canArithmetic, true.B)) // Must we do a Put? val a_cam_any_put = cam_amo.reduce(_ \|\| _) val a_cam_por_put = cam_amo.scanLeft(false.B)(_\|\|_).init val a_cam_sel_put = (cam_amo zip a_cam_por_put) map { case (a, b) => a && !b } val a_cam_a = PriorityMux(cam_amo, cam_a) val a_cam_d = PriorityMux(cam_amo, cam_d) val a_a = a_cam_a.bits.data val a_d = a_cam_d.data // Does the A request conflict with an inflight AMO? val a_fifoId = edgeOut.manager.fastProperty(a_address, camFifoId _, (i:Int) => i.U) val a_cam_busy = (cam_abusy zip cam_a.map(_.fifoId === a_fifoId)) map { case (a,b) => a&&b } reduce (_\|\|_) // (Where) are we are allocating in the CAM? val a_cam_any_free = cam_free.reduce(_ \|\| _) val a_cam_por_free = cam_free.scanLeft(false.B)(_\|\|_).init val a_cam_sel_free = (cam_free zip a_cam_por_free) map { case (a,b) => a && !b } // Logical AMO val indexes = Seq.tabulate(beatBytes8) { i => Cat(a_a(i,i), a_d(i,i)) } val logic_out = Cat(indexes.map(x => a_cam_a.lut(x).asUInt).reverse) // Arithmetic AMO val unsigned = a_cam_a.bits.param(1) val take_max = a_cam_a.bits.param(0) val adder = a_cam_a.bits.param(2) val mask = a_cam_a.bits.mask val signSel = ~(~mask \| (mask >> 1)) val signbits_a = Cat(Seq.tabulate(beatBytes) { i => a_a(8i+7,8i+7) } .reverse) val signbits_d = Cat(Seq.tabulate(beatBytes) { i => a_d(8i+7,8i+7) } .reverse) // Move the selected sign bit into the first byte position it will extend val signbit_a = ((signbits_a & signSel) << 1)(beatBytes-1, 0) val signbit_d = ((signbits_d & signSel) << 1)(beatBytes-1, 0) val signext_a = FillInterleaved(8, leftOR(signbit_a)) val signext_d = FillInterleaved(8, leftOR(signbit_d)) // NOTE: sign-extension does not change the relative ordering in EITHER unsigned or signed arithmetic val wide_mask = FillInterleaved(8, mask) val a_a_ext = (a_a & wide_mask) \| signext_a val a_d_ext = (a_d & wide_mask) \| signext_d val a_d_inv = Mux(adder, a_d_ext, ~a_d_ext) val adder_out = a_a_ext + a_d_inv val h = 8beatBytes-1 // now sign-extended; use biggest bit val a_bigger_uneq = unsigned === a_a_ext(h) // result if high bits are unequal val a_bigger = Mux(a_a_ext(h) === a_d_ext(h), !adder_out(h), a_bigger_uneq) val pick_a = take_max === a_bigger val arith_out = Mux(adder, adder_out, Mux(pick_a, a_a, a_d)) // AMO result data val amo_data = if (!logical) arith_out else if (!arithmetic) logic_out else Mux(a_cam_a.bits.opcode(0), logic_out, arith_out) // Potentially mutate the message from inner val source_i = Wire(chiselTypeOf(in.a)) val a_allow = !a_cam_busy && (a_isSupported \|\| a_cam_any_free) in.a.ready := source_i.ready && a_allow source_i.valid := in.a.valid && a_allow source_i.bits := in.a.bits when (!a_isSupported) { // minimal mux difference source_i.bits.opcode := TLMessages.Get source_i.bits.param := 0.U } // Potentially take the message from the CAM val source_c = Wire(chiselTypeOf(in.a)) source_c.valid := a_cam_any_put source_c.bits := edgeOut.Put( fromSource = a_cam_a.bits.source, toAddress = edgeIn.address(a_cam_a.bits), lgSize = a_cam_a.bits.size, data = amo_data, corrupt = a_cam_a.bits.corrupt \|\| a_cam_d.corrupt)._2 source_c.bits.user :<= a_cam_a.bits.user source_c.bits.echo :<= a_cam_a.bits.echo // Finishing an AMO from the CAM has highest priority TLArbiter(TLArbiter.lowestIndexFirst)(out.a, (0.U, source_c), (edgeOut.numBeats1(in.a.bits), source_i)) // Capture the A state into the CAM when (source_i.fire && !a_isSupported) { (a_cam_sel_free zip cam_a) foreach { case (en, r) => when (en) { r.fifoId := a_fifoId r.bits := in.a.bits r.lut := MuxLookup(in.a.bits.param(1, 0), 0.U(4.W))(Array( TLAtomics.AND -> 0x8.U, TLAtomics.OR -> 0xe.U, TLAtomics.XOR -> 0x6.U, TLAtomics.SWAP -> 0xc.U)) } } (a_cam_sel_free zip cam_s) foreach { case (en, r) => when (en) { r.state := GET } } } // Advance the put state when (source_c.fire) { (a_cam_sel_put zip cam_s) foreach { case (en, r) => when (en) { r.state := ACK } } } // We need to deal with a potential D response in the same cycle as the A request val d_first = edgeOut.first(out.d) val d_cam_sel_raw = cam_a.map(_.bits.source === in.d.bits.source) val d_cam_sel_match = (d_cam_sel_raw zip cam_dmatch) map { case (a,b) => a&&b } val d_cam_data = Mux1H(d_cam_sel_match, cam_d.map(_.data)) val d_cam_denied = Mux1H(d_cam_sel_match, cam_d.map(_.denied)) val d_cam_corrupt = Mux1H(d_cam_sel_match, cam_d.map(_.corrupt)) val d_cam_sel_bypass = if (edgeOut.manager.minLatency > 0) false.B else out.d.bits.source === in.a.bits.source && in.a.valid && !a_isSupported val d_cam_sel = (a_cam_sel_free zip d_cam_sel_match) map { case (a,d) => Mux(d_cam_sel_bypass, a, d) } val d_cam_sel_any = d_cam_sel_bypass \|\| d_cam_sel_match.reduce(_ \|\| _) val d_ackd = out.d.bits.opcode === TLMessages.AccessAckData val d_ack = out.d.bits.opcode === TLMessages.AccessAck when (out.d.fire && d_first) { (d_cam_sel zip cam_d) foreach { case (en, r) => when (en && d_ackd) { r.data := out.d.bits.data r.denied := out.d.bits.denied r.corrupt := out.d.bits.corrupt } } (d_cam_sel zip cam_s) foreach { case (en, r) => when (en) { // Note: it is important that this comes AFTER the := GET, so we can go FREE=>GET=>AMO in one cycle r.state := Mux(d_ackd, AMO, FREE) } } } val d_drop = d_first && d_ackd && d_cam_sel_any val d_replace = d_first && d_ack && d_cam_sel_match.reduce(_ \|\| _) in.d.valid := out.d.valid && !d_drop out.d.ready := in.d.ready \|\| d_drop in.d.bits := out.d.bits when (d_replace) { // minimal muxes in.d.bits.opcode := TLMessages.AccessAckData in.d.bits.data := d_cam_data in.d.bits.corrupt := d_cam_corrupt \|\| out.d.bits.denied in.d.bits.denied := d_cam_denied \|\| out.d.bits.denied } } else { out.a.valid := in.a.valid in.a.ready := out.a.ready out.a.bits := in.a.bits in.d.valid := out.d.valid out.d.ready := in.d.ready in.d.bits := out.d.bits } if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { in.b.valid := out.b.valid out.b.ready := in.b.ready in.b.bits := out.b.bits out.c.valid := in.c.valid in.c.ready := out.c.ready out.c.bits := in.c.bits out.e.valid := in.e.valid in.e.ready := out.e.ready out.e.bits := in.e.bits } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLAtomicAutomata { def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val atomics = LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough) { override lazy val desiredName = (Seq("TLAtomicAutomata") ++ nameSuffix).mkString("_") }) atomics.node } case class CAMParams(a: TLBundleParameters, domainsNeedingHelp: Int) class CAM_S(val params: CAMParams) extends Bundle { val state = UInt(2.W) } class CAM_A(val params: CAMParams) extends Bundle { val bits = new TLBundleA(params.a) val fifoId = UInt(log2Up(params.domainsNeedingHelp).W) val lut = UInt(4.W) } class CAM_D(val params: CAMParams) extends Bundle { val data = UInt(params.a.dataBits.W) val denied = Bool() val corrupt = Bool() } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMAtomicAutomata(txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("AtomicAutomata")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) // Confirm that the AtomicAutomata combines read + write errors import TLMessages._ val test = new RequestPattern({a: TLBundleA => val doesA = a.opcode === ArithmeticData \|\| a.opcode === LogicalData val doesR = a.opcode === Get \|\| doesA val doesW = a.opcode === PutFullData \|\| a.opcode === PutPartialData \|\| doesA (doesR && RequestPattern.overlaps(Seq(AddressSet(0x08, ~0x08)))(a)) \|\| (doesW && RequestPattern.overlaps(Seq(AddressSet(0x10, ~0x10)))(a)) }) (ram.node := TLErrorEvaluator(test) := TLFragmenter(4, 256) := TLDelayer(0.1) := TLAtomicAutomata() := TLDelayer(0.1) := TLErrorEvaluator(test, testOn=true, testOff=true) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMAtomicAutomataTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMAtomicAutomata(txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File PeripheryBus.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.{BuiltInZeroDeviceParams, BuiltInErrorDeviceParams, HasBuiltInDeviceParams, BuiltInDevices} import freechips.rocketchip.diplomacy.BufferParams import freechips.rocketchip.tilelink.{ RegionReplicator, ReplicatedRegion, HasTLBusParams, HasRegionReplicatorParams, TLBusWrapper, TLBusWrapperInstantiationLike, TLFIFOFixer, TLNode, TLXbar, TLInwardNode, TLOutwardNode, TLBuffer, TLWidthWidget, TLAtomicAutomata, TLEdge } import freechips.rocketchip.util.Location case class BusAtomics( arithmetic: Boolean = true, buffer: BufferParams = BufferParams.default, widenBytes: Option[Int] = None ) case class PeripheryBusParams( beatBytes: Int, blockBytes: Int, atomics: Option[BusAtomics] = Some(BusAtomics()), dtsFrequency: Option[BigInt] = None, zeroDevice: Option[BuiltInZeroDeviceParams] = None, errorDevice: Option[BuiltInErrorDeviceParams] = None, replication: Option[ReplicatedRegion] = None) extends HasTLBusParams with HasBuiltInDeviceParams with HasRegionReplicatorParams with TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): PeripheryBus = { val pbus = LazyModule(new PeripheryBus(this, loc.name)) pbus.suggestName(loc.name) context.tlBusWrapperLocationMap += (loc -> pbus) pbus } } class PeripheryBus(params: PeripheryBusParams, name: String)(implicit p: Parameters) extends TLBusWrapper(params, name) { override lazy val desiredName = s"PeripheryBus_$name" private val replicator = params.replication.map(r => LazyModule(new RegionReplicator(r))) val prefixNode = replicator.map { r => r.prefix := addressPrefixNexusNode addressPrefixNexusNode } private val fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all)) private val node: TLNode = params.atomics.map { pa => val in_xbar = LazyModule(new TLXbar(nameSuffix = Some(s"${name}_in"))) val out_xbar = LazyModule(new TLXbar(nameSuffix = Some(s"${name}_out"))) val fixer_node = replicator.map(fixer.node := _.node).getOrElse(fixer.node) (out_xbar.node := fixer_node := TLBuffer(pa.buffer) := (pa.widenBytes.filter(_ > beatBytes).map { w => TLWidthWidget(w) := TLAtomicAutomata(arithmetic = pa.arithmetic, nameSuffix = Some(name)) } .getOrElse { TLAtomicAutomata(arithmetic = pa.arithmetic, nameSuffix = Some(name)) }) := in_xbar.node) } .getOrElse { TLXbar() := fixer.node } def inwardNode: TLInwardNode = node def outwardNode: TLOutwardNode = node def busView: TLEdge = fixer.node.edges.in.head val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode) } File ClockGroup.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.prci import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.resources.FixedClockResource case class ClockGroupingNode(groupName: String)(implicit valName: ValName) extends MixedNexusNode(ClockGroupImp, ClockImp)( dFn = { _ => ClockSourceParameters() }, uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq) }) { override def circuitIdentity = outputs.size == 1 } class ClockGroup(groupName: String)(implicit p: Parameters) extends LazyModule { val node = ClockGroupingNode(groupName) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in(0) val (out, _) = node.out.unzip require (node.in.size == 1) require (in.member.size == out.size) (in.member.data zip out) foreach { case (i, o) => o := i } } } object ClockGroup { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroup(valName.name)).node } case class ClockGroupAggregateNode(groupName: String)(implicit valName: ValName) extends NexusNode(ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq.flatMap(_.members))}) { override def circuitIdentity = outputs.size == 1 } class ClockGroupAggregator(groupName: String)(implicit p: Parameters) extends LazyModule { val node = ClockGroupAggregateNode(groupName) override lazy val desiredName = s"ClockGroupAggregator_$groupName" lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in.unzip val (out, _) = node.out.unzip val outputs = out.flatMap(_.member.data) require (node.in.size == 1, s"Aggregator for groupName: ${groupName} had ${node.in.size} inward edges instead of 1") require (in.head.member.size == outputs.size) in.head.member.data.zip(outputs).foreach { case (i, o) => o := i } } } object ClockGroupAggregator { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupAggregator(valName.name)).node } class SimpleClockGroupSource(numSources: Int = 1)(implicit p: Parameters) extends LazyModule { val node = ClockGroupSourceNode(List.fill(numSources) { ClockGroupSourceParameters() }) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val (out, _) = node.out.unzip out.map { out: ClockGroupBundle => out.member.data.foreach { o => o.clock := clock; o.reset := reset } } } } object SimpleClockGroupSource { def apply(num: Int = 1)(implicit p: Parameters, valName: ValName) = LazyModule(new SimpleClockGroupSource(num)).node } case class FixedClockBroadcastNode(fixedClockOpt: Option[ClockParameters])(implicit valName: ValName) extends NexusNode(ClockImp)( dFn = { seq => fixedClockOpt.map(_ => ClockSourceParameters(give = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSourceParameters()) }, uFn = { seq => fixedClockOpt.map(_ => ClockSinkParameters(take = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSinkParameters()) }, inputRequiresOutput = false) { def fixedClockResources(name: String, prefix: String = "soc/"): Seq[Option[FixedClockResource]] = Seq(fixedClockOpt.map(t => new FixedClockResource(name, t.freqMHz, prefix))) } class FixedClockBroadcast(fixedClockOpt: Option[ClockParameters])(implicit p: Parameters) extends LazyModule { val node = new FixedClockBroadcastNode(fixedClockOpt) { override def circuitIdentity = outputs.size == 1 } lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in(0) val (out, _) = node.out.unzip override def desiredName = s"FixedClockBroadcast_${out.size}" require (node.in.size == 1, "FixedClockBroadcast can only broadcast a single clock") out.foreach { _ := in } } } object FixedClockBroadcast { def apply(fixedClockOpt: Option[ClockParameters] = None)(implicit p: Parameters, valName: ValName) = LazyModule(new FixedClockBroadcast(fixedClockOpt)).node } case class PRCIClockGroupNode()(implicit valName: ValName) extends NexusNode(ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, uFn = { _ => ClockGroupSinkParameters("prci", Nil) }, outputRequiresInput = false) File WidthWidget.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.util.{Repeater, UIntToOH1} // innBeatBytes => the new client-facing bus width class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule { private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes val node = new TLAdapterNode( clientFn = { case c => c }, managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){ override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired) } override lazy val desiredName = s"TLWidthWidget$innerBeatBytes" lazy val module = new Impl class Impl extends LazyModuleImp(this) { def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = outBytes / inBytes val keepBits = log2Ceil(outBytes) val dropBits = log2Ceil(inBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit \|\| !hasData val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR } val corrupt_reg = RegInit(false.B) val corrupt_in = edgeIn.corrupt(in.bits) val corrupt_out = corrupt_in \|\| corrupt_reg when (in.fire) { count := count + 1.U corrupt_reg := corrupt_out when (last) { count := 0.U corrupt_reg := false.B } } def helper(idata: UInt): UInt = { // rdata is X until the first time a multi-beat write occurs. // Prevent the X from leaking outside by jamming the mux control until // the first time rdata is written (and hence no longer X). val rdata_written_once = RegInit(false.B) val masked_enable = enable.map(_ \|\| !rdata_written_once) val odata = Seq.fill(ratio) { WireInit(idata) } val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata))) val pdata = rdata :+ idata val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) } when (in.fire && !last) { rdata_written_once := true.B (rdata zip mdata) foreach { case (r, m) => r := m } } Cat(mdata.reverse) } in.ready := out.ready \|\| !last out.valid := in.valid && last out.bits := in.bits // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits))) edgeOut.corrupt(out.bits) := corrupt_out (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleC, i: TLBundleC) => () case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossible bundle combination in WidthWidget") } } def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = inBytes / outBytes val keepBits = log2Ceil(inBytes) val dropBits = log2Ceil(outBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit \|\| !hasData when (out.fire) { count := count + 1.U when (last) { count := 0.U } } // For sub-beat transfer, extract which part matters val sel = in.bits match { case a: TLBundleA => a.address(keepBits-1, dropBits) case b: TLBundleB => b.address(keepBits-1, dropBits) case c: TLBundleC => c.address(keepBits-1, dropBits) case d: TLBundleD => { val sel = sourceMap(d.source) val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway } } val index = sel \| count def helper(idata: UInt, width: Int): UInt = { val mux = VecInit.tabulate(ratio) { i => idata((i+1)outByteswidth-1, ioutByteswidth) } mux(index) } out.bits := in.bits out.valid := in.valid in.ready := out.ready // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8)) (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1) case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1) case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossbile bundle combination in WidthWidget") } // Repeat the input if we're not last !last } def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) { // nothing to do; pass it through out.bits := in.bits out.valid := in.valid in.ready := out.ready } else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) { // split input to output val repeat = Wire(Bool()) val repeated = Repeater(in, repeat) val cated = Wire(chiselTypeOf(repeated)) cated <> repeated edgeIn.data(cated.bits) := Cat( edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes8-1, edgeOut.manager.beatBytes8), edgeIn.data(in.bits)(edgeOut.manager.beatBytes8-1, 0)) repeat := split(edgeIn, cated, edgeOut, out, sourceMap) } else { // merge input to output merge(edgeIn, in, edgeOut, out) } } (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => // If the master is narrower than the slave, the D channel must be narrowed. // This is tricky, because the D channel has no address data. // Thus, you don't know which part of a sub-beat transfer to extract. // To fix this, we record the relevant address bits for all sources. // The assumption is that this sort of situation happens only where // you connect a narrow master to the system bus, so there are few sources. def sourceMap(source_bits: UInt) = { val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes) val keepBits = log2Ceil(edgeOut.manager.beatBytes) val dropBits = log2Ceil(edgeIn.manager.beatBytes) val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W))) val a_sel = in.a.bits.address(keepBits-1, dropBits) when (in.a.fire) { if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning sources(0) := a_sel } else { sources(in.a.bits.source) := a_sel } } // depopulate unused source registers: edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U } val bypass = in.a.valid && in.a.bits.source === source if (edgeIn.manager.minLatency > 0) sources(source) else Mux(bypass, a_sel, sources(source)) } splice(edgeIn, in.a, edgeOut, out.a, sourceMap) splice(edgeOut, out.d, edgeIn, in.d, sourceMap) if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { splice(edgeOut, out.b, edgeIn, in.b, sourceMap) splice(edgeIn, in.c, edgeOut, out.c, sourceMap) out.e.valid := in.e.valid out.e.bits := in.e.bits in.e.ready := out.e.ready } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLWidthWidget { def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode = { val widget = LazyModule(new TLWidthWidget(innerBeatBytes)) widget.node } def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("WidthWidget")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) (ram.node := TLDelayer(0.1) := TLFragmenter(4, 256) := TLWidthWidget(second) := TLWidthWidget(first) := TLDelayer(0.1) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module) dut.io.start := DontCare io.finished := dut.io.finished } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} \|acquireB = ${acquireB} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT \|\| supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB \|\| regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED \|\| supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED \|\| supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB \|\| supportsGet, w = supportsAcquireT \|\| supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} \|Slave Address = ${address} \|supports = ${supports.infoString} \| \|""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ \|\| _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ \|\| _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_\|\|_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ \|\| _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B \|\| s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} \|visibility = ${visibility} \|emits = ${emits.infoString} \|sourceId = ${sourceId} \| \|""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ \|\| _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ \|\| _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ \|\| _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ \|\| _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ \|\| _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ \|\| _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ \|\| _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ \|\| _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE \|\| x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps / class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File CustomBootPin.scala: package testchipip.boot import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ case class CustomBootPinParams( customBootAddress: BigInt = 0x80000000L, // Default is DRAM_BASE masterWhere: TLBusWrapperLocation = CBUS // This needs to write to clint and bootaddrreg, which are on CBUS/PBUS ) case object CustomBootPinKey extends Field[Option[CustomBootPinParams]](None) trait CanHavePeripheryCustomBootPin { this: BaseSubsystem => val custom_boot_pin = p(CustomBootPinKey).map { params => require(p(BootAddrRegKey).isDefined, "CustomBootPin relies on existence of BootAddrReg") val tlbus = locateTLBusWrapper(params.masterWhere) val clientParams = TLMasterPortParameters.v1( clients = Seq(TLMasterParameters.v1( name = "custom-boot", sourceId = IdRange(0, 1), )), minLatency = 1 ) val inner_io = tlbus { val node = TLClientNode(Seq(clientParams)) tlbus.coupleFrom(s"port_named_custom_boot_pin") ({ _ := node }) InModuleBody { val custom_boot = IO(Input(Bool())).suggestName("custom_boot") val (tl, edge) = node.out(0) val inactive :: waiting_bootaddr_reg_a :: waiting_bootaddr_reg_d :: waiting_msip_a :: waiting_msip_d :: dead :: Nil = Enum(6) val state = RegInit(inactive) tl.a.valid := false.B tl.a.bits := DontCare tl.d.ready := true.B switch (state) { is (inactive) { when (custom_boot) { state := waiting_bootaddr_reg_a } } is (waiting_bootaddr_reg_a) { tl.a.valid := true.B tl.a.bits := edge.Put( toAddress = p(BootAddrRegKey).get.bootRegAddress.U, fromSource = 0.U, lgSize = 2.U, data = params.customBootAddress.U )._2 when (tl.a.fire) { state := waiting_bootaddr_reg_d } } is (waiting_bootaddr_reg_d) { when (tl.d.fire) { state := waiting_msip_a } } is (waiting_msip_a) { tl.a.valid := true.B tl.a.bits := edge.Put( toAddress = (p(CLINTKey).get.baseAddress + CLINTConsts.msipOffset(0)).U, // msip for hart0 fromSource = 0.U, lgSize = log2Ceil(CLINTConsts.msipBytes).U, data = 1.U )._2 when (tl.a.fire) { state := waiting_msip_d } } is (waiting_msip_d) { when (tl.d.fire) { state := dead } } is (dead) { when (!custom_boot) { state := inactive } } } custom_boot } } val outer_io = InModuleBody { val custom_boot = IO(Input(Bool())).suggestName("custom_boot") inner_io := custom_boot custom_boot } outer_io } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File LazyScope.scala: package org.chipsalliance.diplomacy.lazymodule import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.ValName /** Allows dynamic creation of [[Module]] hierarchy and "shoving" logic into a [[LazyModule]]. / trait LazyScope { this: LazyModule => override def toString: String = s"LazyScope named $name" /* Evaluate `body` in the current [[LazyModule.scope]] / def apply[T](body: => T): T = { // Preserve the previous value of the [[LazyModule.scope]], because when calling [[apply]] function, // [[LazyModule.scope]] will be altered. val saved = LazyModule.scope // [[LazyModule.scope]] stack push. LazyModule.scope = Some(this) // Evaluate [[body]] in the current `scope`, saving the result to [[out]]. val out = body // Check that the `scope` after evaluating `body` is the same as when we started. require(LazyModule.scope.isDefined, s"LazyScope $name tried to exit, but scope was empty!") require( LazyModule.scope.get eq this, s"LazyScope $name exited before LazyModule ${LazyModule.scope.get.name} was closed" ) // [[LazyModule.scope]] stack pop. LazyModule.scope = saved out } } /* Used to automatically create a level of module hierarchy (a [[SimpleLazyModule]]) within which [[LazyModule]]s can * be instantiated and connected. * * It will instantiate a [[SimpleLazyModule]] to manage evaluation of `body` and evaluate `body` code snippets in this * scope. / object LazyScope { /* Create a [[LazyScope]] with an implicit instance name. * * @param body * code executed within the generated [[SimpleLazyModule]]. * @param valName * instance name of generated [[SimpleLazyModule]]. * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. / def apply[T]( body: => T )( implicit valName: ValName, p: Parameters ): T = { apply(valName.value, "SimpleLazyModule", None)(body)(p) } /* Create a [[LazyScope]] with an explicitly defined instance name. * * @param name * instance name of generated [[SimpleLazyModule]]. * @param body * code executed within the generated `SimpleLazyModule` * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. / def apply[T]( name: String )(body: => T )( implicit p: Parameters ): T = { apply(name, "SimpleLazyModule", None)(body)(p) } /* Create a [[LazyScope]] with an explicit instance and class name, and control inlining. * * @param name * instance name of generated [[SimpleLazyModule]]. * @param desiredModuleName * class name of generated [[SimpleLazyModule]]. * @param overrideInlining * tell FIRRTL that this [[SimpleLazyModule]]'s module should be inlined. * @param body * code executed within the generated `SimpleLazyModule` * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. / def apply[T]( name: String, desiredModuleName: String, overrideInlining: Option[Boolean] = None )(body: => T )( implicit p: Parameters ): T = { val scope = LazyModule(new SimpleLazyModule with LazyScope { override lazy val desiredName = desiredModuleName override def shouldBeInlined = overrideInlining.getOrElse(super.shouldBeInlined) }).suggestName(name) scope { body } } /* Create a [[LazyScope]] to temporarily group children for some reason, but tell Firrtl to inline it. * * For example, we might want to control a set of children's clocks but then not keep the parent wrapper. * * @param body * code executed within the generated `SimpleLazyModule` * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. */ def inline[T]( body: => T )( implicit p: Parameters ): T = { apply("noname", "ShouldBeInlined", Some(false))(body)(p) } }	module PeripheryBus_cbus( // @[ClockDomain.scala:14:9] input auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [20:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bootrom_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bootrom_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [16:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bootrom_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bootrom_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_debug_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_debug_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [11:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_debug_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_debug_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_plic_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_plic_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_plic_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_plic_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_clint_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_clint_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_clint_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_clint_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_l2_ctrl_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_l2_ctrl_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_l2_ctrl_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_l2_ctrl_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_5_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_5_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_4_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_4_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_3_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_3_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_2_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_2_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_1_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_1_reset, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_0_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_0_reset, // @[LazyModuleImp.scala:107:25] input auto_cbus_clock_groups_in_member_cbus_0_clock, // @[LazyModuleImp.scala:107:25] input auto_cbus_clock_groups_in_member_cbus_0_reset, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_bus_xing_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_bus_xing_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_bus_xing_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bus_xing_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_bus_xing_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_bus_xing_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input custom_boot // @[CustomBootPin.scala:36:29] ); wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_valid; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_a_ready; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_valid; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_a_valid; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_a_ready; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [28:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_address; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire [6:0] coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire [28:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [6:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_auto_widget_anon_in_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_widget_anon_in_a_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_data; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [28:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [6:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire buffer_1_auto_out_d_valid; // @[Buffer.scala:40:9] wire buffer_1_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_1_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire buffer_1_auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_1_auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire [5:0] buffer_1_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_1_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_1_auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_1_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_1_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_1_auto_in_d_valid; // @[Buffer.scala:40:9] wire buffer_1_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_1_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_1_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire buffer_1_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_1_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [5:0] buffer_1_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_1_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] buffer_1_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_1_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire buffer_1_auto_in_a_valid; // @[Buffer.scala:40:9] wire buffer_1_auto_in_a_ready; // @[Buffer.scala:40:9] wire buffer_1_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire [63:0] buffer_1_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire [7:0] buffer_1_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [28:0] buffer_1_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [5:0] buffer_1_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [3:0] buffer_1_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [2:0] buffer_1_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] buffer_1_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire cbus_clock_groups_auto_out_member_cbus_0_reset; // @[ClockGroup.scala:53:9] wire cbus_clock_groups_auto_out_member_cbus_0_clock; // @[ClockGroup.scala:53:9] wire _coupler_to_prci_ctrl_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_prci_ctrl_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [1:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_param; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire _coupler_to_prci_ctrl_auto_tl_in_d_bits_sink; // @[LazyScope.scala:98:27] wire _coupler_to_prci_ctrl_auto_tl_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_prci_ctrl_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_prci_ctrl_auto_tl_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_to_bootrom_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_bootrom_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_bootrom_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_bootrom_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_bootrom_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_debug_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_debug_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_debug_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_debug_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_debug_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_debug_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_plic_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_plic_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_plic_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_plic_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_plic_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_plic_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_clint_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_clint_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_clint_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_clint_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_clint_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_clint_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_l2_ctrl_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_l2_ctrl_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [1:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_param; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire _coupler_to_l2_ctrl_auto_tl_in_d_bits_sink; // @[LazyScope.scala:98:27] wire _coupler_to_l2_ctrl_auto_tl_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_l2_ctrl_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_l2_ctrl_auto_tl_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _wrapped_error_device_auto_buffer_in_a_ready; // @[LazyScope.scala:98:27] wire _wrapped_error_device_auto_buffer_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _wrapped_error_device_auto_buffer_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [1:0] _wrapped_error_device_auto_buffer_in_d_bits_param; // @[LazyScope.scala:98:27] wire [3:0] _wrapped_error_device_auto_buffer_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _wrapped_error_device_auto_buffer_in_d_bits_source; // @[LazyScope.scala:98:27] wire _wrapped_error_device_auto_buffer_in_d_bits_sink; // @[LazyScope.scala:98:27] wire _wrapped_error_device_auto_buffer_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _wrapped_error_device_auto_buffer_in_d_bits_data; // @[LazyScope.scala:98:27] wire _wrapped_error_device_auto_buffer_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _atomics_auto_in_a_ready; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_valid; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_in_d_bits_opcode; // @[AtomicAutomata.scala:289:29] wire [1:0] _atomics_auto_in_d_bits_param; // @[AtomicAutomata.scala:289:29] wire [3:0] _atomics_auto_in_d_bits_size; // @[AtomicAutomata.scala:289:29] wire [6:0] _atomics_auto_in_d_bits_source; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_bits_sink; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_bits_denied; // @[AtomicAutomata.scala:289:29] wire [63:0] _atomics_auto_in_d_bits_data; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_in_d_bits_corrupt; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_valid; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_opcode; // @[AtomicAutomata.scala:289:29] wire [2:0] _atomics_auto_out_a_bits_param; // @[AtomicAutomata.scala:289:29] wire [3:0] _atomics_auto_out_a_bits_size; // @[AtomicAutomata.scala:289:29] wire [6:0] _atomics_auto_out_a_bits_source; // @[AtomicAutomata.scala:289:29] wire [28:0] _atomics_auto_out_a_bits_address; // @[AtomicAutomata.scala:289:29] wire [7:0] _atomics_auto_out_a_bits_mask; // @[AtomicAutomata.scala:289:29] wire [63:0] _atomics_auto_out_a_bits_data; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_a_bits_corrupt; // @[AtomicAutomata.scala:289:29] wire _atomics_auto_out_d_ready; // @[AtomicAutomata.scala:289:29] wire _buffer_auto_in_a_ready; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_in_d_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_auto_in_d_bits_param; // @[Buffer.scala:75:28] wire [3:0] _buffer_auto_in_d_bits_size; // @[Buffer.scala:75:28] wire [6:0] _buffer_auto_in_d_bits_source; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_sink; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_denied; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_in_d_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28] wire _buffer_auto_out_a_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_out_a_bits_opcode; // @[Buffer.scala:75:28] wire [2:0] _buffer_auto_out_a_bits_param; // @[Buffer.scala:75:28] wire [3:0] _buffer_auto_out_a_bits_size; // @[Buffer.scala:75:28] wire [6:0] _buffer_auto_out_a_bits_source; // @[Buffer.scala:75:28] wire [28:0] _buffer_auto_out_a_bits_address; // @[Buffer.scala:75:28] wire [7:0] _buffer_auto_out_a_bits_mask; // @[Buffer.scala:75:28] wire [63:0] _buffer_auto_out_a_bits_data; // @[Buffer.scala:75:28] wire _buffer_auto_out_a_bits_corrupt; // @[Buffer.scala:75:28] wire _buffer_auto_out_d_ready; // @[Buffer.scala:75:28] wire _out_xbar_auto_anon_in_a_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_in_d_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_in_d_bits_opcode; // @[PeripheryBus.scala:57:30] wire [1:0] _out_xbar_auto_anon_in_d_bits_param; // @[PeripheryBus.scala:57:30] wire [3:0] _out_xbar_auto_anon_in_d_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_in_d_bits_source; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_in_d_bits_sink; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_in_d_bits_denied; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_in_d_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_in_d_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_7_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_7_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_7_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_7_a_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_out_7_a_bits_source; // @[PeripheryBus.scala:57:30] wire [20:0] _out_xbar_auto_anon_out_7_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_7_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_7_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_7_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_7_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_6_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_6_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_6_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_6_a_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_out_6_a_bits_source; // @[PeripheryBus.scala:57:30] wire [16:0] _out_xbar_auto_anon_out_6_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_6_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_6_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_6_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_6_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_5_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_5_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_5_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_5_a_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_out_5_a_bits_source; // @[PeripheryBus.scala:57:30] wire [11:0] _out_xbar_auto_anon_out_5_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_5_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_5_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_5_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_5_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_4_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_4_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_4_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_4_a_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_out_4_a_bits_source; // @[PeripheryBus.scala:57:30] wire [27:0] _out_xbar_auto_anon_out_4_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_4_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_4_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_4_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_4_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_3_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_3_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_3_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_3_a_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_out_3_a_bits_source; // @[PeripheryBus.scala:57:30] wire [25:0] _out_xbar_auto_anon_out_3_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_3_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_3_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_3_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_3_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_param; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_1_a_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_out_1_a_bits_source; // @[PeripheryBus.scala:57:30] wire [25:0] _out_xbar_auto_anon_out_1_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_1_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_1_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_1_d_ready; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_a_valid; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_opcode; // @[PeripheryBus.scala:57:30] wire [2:0] _out_xbar_auto_anon_out_0_a_bits_param; // @[PeripheryBus.scala:57:30] wire [3:0] _out_xbar_auto_anon_out_0_a_bits_size; // @[PeripheryBus.scala:57:30] wire [6:0] _out_xbar_auto_anon_out_0_a_bits_source; // @[PeripheryBus.scala:57:30] wire [13:0] _out_xbar_auto_anon_out_0_a_bits_address; // @[PeripheryBus.scala:57:30] wire [7:0] _out_xbar_auto_anon_out_0_a_bits_mask; // @[PeripheryBus.scala:57:30] wire [63:0] _out_xbar_auto_anon_out_0_a_bits_data; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_a_bits_corrupt; // @[PeripheryBus.scala:57:30] wire _out_xbar_auto_anon_out_0_d_ready; // @[PeripheryBus.scala:57:30] wire _in_xbar_auto_anon_out_a_valid; // @[PeripheryBus.scala:56:29] wire [2:0] _in_xbar_auto_anon_out_a_bits_opcode; // @[PeripheryBus.scala:56:29] wire [2:0] _in_xbar_auto_anon_out_a_bits_param; // @[PeripheryBus.scala:56:29] wire [3:0] _in_xbar_auto_anon_out_a_bits_size; // @[PeripheryBus.scala:56:29] wire [6:0] _in_xbar_auto_anon_out_a_bits_source; // @[PeripheryBus.scala:56:29] wire [28:0] _in_xbar_auto_anon_out_a_bits_address; // @[PeripheryBus.scala:56:29] wire [7:0] _in_xbar_auto_anon_out_a_bits_mask; // @[PeripheryBus.scala:56:29] wire [63:0] _in_xbar_auto_anon_out_a_bits_data; // @[PeripheryBus.scala:56:29] wire _in_xbar_auto_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:56:29] wire _in_xbar_auto_anon_out_d_ready; // @[PeripheryBus.scala:56:29] wire _fixer_auto_anon_in_a_ready; // @[PeripheryBus.scala:54:33] wire _fixer_auto_anon_in_d_valid; // @[PeripheryBus.scala:54:33] wire [2:0] _fixer_auto_anon_in_d_bits_opcode; // @[PeripheryBus.scala:54:33] wire [1:0] _fixer_auto_anon_in_d_bits_param; // @[PeripheryBus.scala:54:33] wire [3:0] _fixer_auto_anon_in_d_bits_size; // @[PeripheryBus.scala:54:33] wire [6:0] _fixer_auto_anon_in_d_bits_source; // @[PeripheryBus.scala:54:33] wire _fixer_auto_anon_in_d_bits_sink; // @[PeripheryBus.scala:54:33] wire _fixer_auto_anon_in_d_bits_denied; // @[PeripheryBus.scala:54:33] wire [63:0] _fixer_auto_anon_in_d_bits_data; // @[PeripheryBus.scala:54:33] wire _fixer_auto_anon_in_d_bits_corrupt; // @[PeripheryBus.scala:54:33] wire _fixer_auto_anon_out_a_valid; // @[PeripheryBus.scala:54:33] wire [2:0] _fixer_auto_anon_out_a_bits_opcode; // @[PeripheryBus.scala:54:33] wire [2:0] _fixer_auto_anon_out_a_bits_param; // @[PeripheryBus.scala:54:33] wire [3:0] _fixer_auto_anon_out_a_bits_size; // @[PeripheryBus.scala:54:33] wire [6:0] _fixer_auto_anon_out_a_bits_source; // @[PeripheryBus.scala:54:33] wire [28:0] _fixer_auto_anon_out_a_bits_address; // @[PeripheryBus.scala:54:33] wire [7:0] _fixer_auto_anon_out_a_bits_mask; // @[PeripheryBus.scala:54:33] wire [63:0] _fixer_auto_anon_out_a_bits_data; // @[PeripheryBus.scala:54:33] wire _fixer_auto_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:54:33] wire _fixer_auto_anon_out_d_ready; // @[PeripheryBus.scala:54:33] wire auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [6:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data_0 = auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_a_ready_0 = auto_coupler_to_bootrom_fragmenter_anon_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_d_valid_0 = auto_coupler_to_bootrom_fragmenter_anon_out_d_valid; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size_0 = auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [10:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source_0 = auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data_0 = auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_a_ready_0 = auto_coupler_to_debug_fragmenter_anon_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_d_valid_0 = auto_coupler_to_debug_fragmenter_anon_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode_0 = auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_size_0 = auto_coupler_to_debug_fragmenter_anon_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [10:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_source_0 = auto_coupler_to_debug_fragmenter_anon_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_data_0 = auto_coupler_to_debug_fragmenter_anon_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_a_ready_0 = auto_coupler_to_plic_fragmenter_anon_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_d_valid_0 = auto_coupler_to_plic_fragmenter_anon_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode_0 = auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_size_0 = auto_coupler_to_plic_fragmenter_anon_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [10:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_source_0 = auto_coupler_to_plic_fragmenter_anon_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_data_0 = auto_coupler_to_plic_fragmenter_anon_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_a_ready_0 = auto_coupler_to_clint_fragmenter_anon_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_d_valid_0 = auto_coupler_to_clint_fragmenter_anon_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode_0 = auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_size_0 = auto_coupler_to_clint_fragmenter_anon_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [10:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_source_0 = auto_coupler_to_clint_fragmenter_anon_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_data_0 = auto_coupler_to_clint_fragmenter_anon_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [6:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt_0 = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_a_ready_0 = auto_coupler_to_l2_ctrl_buffer_out_a_ready; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_d_valid_0 = auto_coupler_to_l2_ctrl_buffer_out_d_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode_0 = auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_size_0 = auto_coupler_to_l2_ctrl_buffer_out_d_bits_size; // @[ClockDomain.scala:14:9] wire [10:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_source_0 = auto_coupler_to_l2_ctrl_buffer_out_d_bits_source; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_data_0 = auto_coupler_to_l2_ctrl_buffer_out_d_bits_data; // @[ClockDomain.scala:14:9] wire auto_cbus_clock_groups_in_member_cbus_0_clock_0 = auto_cbus_clock_groups_in_member_cbus_0_clock; // @[ClockDomain.scala:14:9] wire auto_cbus_clock_groups_in_member_cbus_0_reset_0 = auto_cbus_clock_groups_in_member_cbus_0_reset; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_valid_0 = auto_bus_xing_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_opcode_0 = auto_bus_xing_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_a_bits_param_0 = auto_bus_xing_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [3:0] auto_bus_xing_in_a_bits_size_0 = auto_bus_xing_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [5:0] auto_bus_xing_in_a_bits_source_0 = auto_bus_xing_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [28:0] auto_bus_xing_in_a_bits_address_0 = auto_bus_xing_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_bus_xing_in_a_bits_mask_0 = auto_bus_xing_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_bus_xing_in_a_bits_data_0 = auto_bus_xing_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_bits_corrupt_0 = auto_bus_xing_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_ready_0 = auto_bus_xing_in_d_ready; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_debug_fragmenter_anon_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_plic_fragmenter_anon_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_clint_fragmenter_anon_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_l2_ctrl_buffer_out_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire [1:0] nodeOut_a_bits_a_mask_hi_lo = 2'h0; // @[Misc.scala:222:10] wire [1:0] nodeOut_a_bits_a_mask_hi_hi = 2'h0; // @[Misc.scala:222:10] wire [1:0] nodeOut_a_bits_a_mask_hi_lo_1 = 2'h0; // @[Misc.scala:222:10] wire [1:0] nodeOut_a_bits_a_mask_hi_hi_1 = 2'h0; // @[Misc.scala:222:10] wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire cbus_clock_groups_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire cbus_clock_groups_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire cbus_clock_groups__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockGroup_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire clockGroup_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire clockGroup__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_source = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_source = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_source = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_corrupt = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_source = 1'h0; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_tlOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire coupler_from_port_named_custom_boot_pin_tlIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire coupler_from_port_named_custom_boot_pin_tlIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire _nodeOut_a_bits_legal_T_8 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_9 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_a_bits_legal_T_23 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_28 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_33 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_38 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_43 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_50 = 1'h0; // @[Parameters.scala:684:29] wire _nodeOut_a_bits_legal_T_55 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_56 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_a_bits_legal_T_57 = 1'h0; // @[Parameters.scala:686:26] wire nodeOut_a_bits_a_source = 1'h0; // @[Edges.scala:480:17] wire nodeOut_a_bits_a_corrupt = 1'h0; // @[Edges.scala:480:17] wire nodeOut_a_bits_a_mask_sub_sub_sub_0_1 = 1'h0; // @[Misc.scala:206:21] wire nodeOut_a_bits_a_mask_sub_sub_1_2 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_sub_1_1 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _nodeOut_a_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_1_2 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_2_2 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_2_1 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_3_2 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_3_1 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_1 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_eq_2 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_eq_3 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_eq_4 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_4 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_5 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_5 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_6 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_6 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_7 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_7 = 1'h0; // @[Misc.scala:215:29] wire _nodeOut_a_bits_legal_T_67 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_68 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_a_bits_legal_T_77 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_82 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_92 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_97 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_102 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_103 = 1'h0; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_109 = 1'h0; // @[Parameters.scala:684:29] wire _nodeOut_a_bits_legal_T_114 = 1'h0; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_115 = 1'h0; // @[Parameters.scala:684:54] wire _nodeOut_a_bits_legal_T_116 = 1'h0; // @[Parameters.scala:686:26] wire nodeOut_a_bits_a_1_source = 1'h0; // @[Edges.scala:480:17] wire nodeOut_a_bits_a_1_corrupt = 1'h0; // @[Edges.scala:480:17] wire nodeOut_a_bits_a_mask_sub_sub_sub_0_1_1 = 1'h0; // @[Misc.scala:206:21] wire nodeOut_a_bits_a_mask_sub_sub_1_2_1 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_sub_1_1_1 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire _nodeOut_a_bits_a_mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_1_2_1 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_2_2_1 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_2_1_1 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_3_2_1 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_3_1_1 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_9 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_eq_10 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_eq_11 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_eq_12 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_12 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_13 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_13 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_14 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_14 = 1'h0; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_eq_15 = 1'h0; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_15 = 1'h0; // @[Misc.scala:215:29] wire [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_opcode = 3'h1; // @[ClockDomain.scala:14:9] wire [7:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_mask = 8'hF; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_mask = 8'hF; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_mask = 8'hF; // @[MixedNode.scala:542:17] wire [7:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_mask = 8'hF; // @[MixedNode.scala:551:17] wire [7:0] nodeOut_a_bits_mask = 8'hF; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_a_mask = 8'hF; // @[Edges.scala:480:17] wire [7:0] _nodeOut_a_bits_a_mask_T = 8'hF; // @[Misc.scala:222:10] wire [7:0] nodeOut_a_bits_a_1_mask = 8'hF; // @[Edges.scala:480:17] wire [7:0] _nodeOut_a_bits_a_mask_T_1 = 8'hF; // @[Misc.scala:222:10] wire [3:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_size = 4'h2; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_size = 4'h2; // @[LazyModuleImp.scala:138:7] wire [3:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_size = 4'h2; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_size = 4'h2; // @[MixedNode.scala:551:17] wire [3:0] nodeOut_a_bits_size = 4'h2; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_a_size = 4'h2; // @[Edges.scala:480:17] wire [3:0] nodeOut_a_bits_a_1_size = 4'h2; // @[Edges.scala:480:17] wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_opcode = 3'h0; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_param = 3'h0; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_opcode = 3'h0; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_param = 3'h0; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_opcode = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_bits_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_a_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] nodeOut_a_bits_a_param = 3'h0; // @[Edges.scala:480:17] wire [2:0] nodeOut_a_bits_a_1_opcode = 3'h0; // @[Edges.scala:480:17] wire [2:0] nodeOut_a_bits_a_1_param = 3'h0; // @[Edges.scala:480:17] wire [3:0] nodeOut_a_bits_a_mask_hi = 4'h0; // @[Misc.scala:222:10] wire [3:0] nodeOut_a_bits_a_mask_hi_1 = 4'h0; // @[Misc.scala:222:10] wire [3:0] nodeOut_a_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] nodeOut_a_bits_a_mask_lo_1 = 4'hF; // @[Misc.scala:222:10] wire [1:0] nodeOut_a_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] nodeOut_a_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] nodeOut_a_bits_a_mask_lo_lo_1 = 2'h3; // @[Misc.scala:222:10] wire [1:0] nodeOut_a_bits_a_mask_lo_hi_1 = 2'h3; // @[Misc.scala:222:10] wire coupler_from_port_named_custom_boot_pin_auto_tl_in_d_ready = 1'h1; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_d_ready = 1'h1; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_tlOut_d_ready = 1'h1; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlIn_d_ready = 1'h1; // @[MixedNode.scala:551:17] wire nodeOut_d_ready = 1'h1; // @[MixedNode.scala:542:17] wire _nodeOut_a_bits_legal_T = 1'h1; // @[Parameters.scala:92:28] wire _nodeOut_a_bits_legal_T_1 = 1'h1; // @[Parameters.scala:92:38] wire _nodeOut_a_bits_legal_T_2 = 1'h1; // @[Parameters.scala:92:33] wire _nodeOut_a_bits_legal_T_3 = 1'h1; // @[Parameters.scala:684:29] wire _nodeOut_a_bits_legal_T_10 = 1'h1; // @[Parameters.scala:92:28] wire _nodeOut_a_bits_legal_T_11 = 1'h1; // @[Parameters.scala:92:38] wire _nodeOut_a_bits_legal_T_12 = 1'h1; // @[Parameters.scala:92:33] wire _nodeOut_a_bits_legal_T_13 = 1'h1; // @[Parameters.scala:684:29] wire _nodeOut_a_bits_legal_T_18 = 1'h1; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_44 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_45 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_46 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_47 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_48 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_49 = 1'h1; // @[Parameters.scala:684:54] wire _nodeOut_a_bits_legal_T_58 = 1'h1; // @[Parameters.scala:686:26] wire nodeOut_a_bits_legal = 1'h1; // @[Parameters.scala:686:26] wire nodeOut_a_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire nodeOut_a_bits_a_mask_sub_sub_nbit = 1'h1; // @[Misc.scala:211:20] wire nodeOut_a_bits_a_mask_sub_sub_0_2 = 1'h1; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_sub_acc_T = 1'h1; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_nbit = 1'h1; // @[Misc.scala:211:20] wire nodeOut_a_bits_a_mask_sub_0_2 = 1'h1; // @[Misc.scala:214:27] wire nodeOut_a_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire nodeOut_a_bits_a_mask_nbit = 1'h1; // @[Misc.scala:211:20] wire nodeOut_a_bits_a_mask_eq = 1'h1; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T = 1'h1; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _nodeOut_a_bits_legal_T_59 = 1'h1; // @[Parameters.scala:92:28] wire _nodeOut_a_bits_legal_T_60 = 1'h1; // @[Parameters.scala:92:38] wire _nodeOut_a_bits_legal_T_61 = 1'h1; // @[Parameters.scala:92:33] wire _nodeOut_a_bits_legal_T_62 = 1'h1; // @[Parameters.scala:684:29] wire _nodeOut_a_bits_legal_T_69 = 1'h1; // @[Parameters.scala:92:28] wire _nodeOut_a_bits_legal_T_70 = 1'h1; // @[Parameters.scala:92:38] wire _nodeOut_a_bits_legal_T_71 = 1'h1; // @[Parameters.scala:92:33] wire _nodeOut_a_bits_legal_T_72 = 1'h1; // @[Parameters.scala:684:29] wire _nodeOut_a_bits_legal_T_87 = 1'h1; // @[Parameters.scala:137:59] wire _nodeOut_a_bits_legal_T_104 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_105 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_106 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_107 = 1'h1; // @[Parameters.scala:685:42] wire _nodeOut_a_bits_legal_T_108 = 1'h1; // @[Parameters.scala:684:54] wire _nodeOut_a_bits_legal_T_117 = 1'h1; // @[Parameters.scala:686:26] wire nodeOut_a_bits_legal_1 = 1'h1; // @[Parameters.scala:686:26] wire nodeOut_a_bits_a_mask_sub_sub_size_1 = 1'h1; // @[Misc.scala:209:26] wire nodeOut_a_bits_a_mask_sub_sub_nbit_1 = 1'h1; // @[Misc.scala:211:20] wire nodeOut_a_bits_a_mask_sub_sub_0_2_1 = 1'h1; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_sub_sub_acc_T_2 = 1'h1; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_sub_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_nbit_1 = 1'h1; // @[Misc.scala:211:20] wire nodeOut_a_bits_a_mask_sub_0_2_1 = 1'h1; // @[Misc.scala:214:27] wire nodeOut_a_bits_a_mask_sub_0_1_1 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_sub_1_1_1 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire nodeOut_a_bits_a_mask_nbit_1 = 1'h1; // @[Misc.scala:211:20] wire nodeOut_a_bits_a_mask_eq_8 = 1'h1; // @[Misc.scala:214:27] wire _nodeOut_a_bits_a_mask_acc_T_8 = 1'h1; // @[Misc.scala:215:38] wire nodeOut_a_bits_a_mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire nodeOut_a_bits_a_mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire [2:0] nodeOut_a_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [2:0] nodeOut_a_bits_a_mask_sizeOH_1 = 3'h5; // @[Misc.scala:202:81] wire [2:0] _nodeOut_a_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [2:0] _nodeOut_a_bits_a_mask_sizeOH_T_5 = 3'h4; // @[OneHot.scala:65:27] wire [3:0] _nodeOut_a_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _nodeOut_a_bits_a_mask_sizeOH_T_4 = 4'h4; // @[OneHot.scala:65:12] wire [1:0] nodeOut_a_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [1:0] nodeOut_a_bits_a_mask_sizeOH_shiftAmount_1 = 2'h2; // @[OneHot.scala:64:49] wire [63:0] nodeOut_a_bits_a_1_data = 64'h1; // @[Edges.scala:480:17] wire [28:0] nodeOut_a_bits_a_1_address = 29'h2000000; // @[Edges.scala:480:17] wire [29:0] _nodeOut_a_bits_legal_T_112 = 30'h2010000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_113 = 30'h2010000; // @[Parameters.scala:137:46] wire [26:0] _nodeOut_a_bits_legal_T_111 = 27'h2010000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_99 = 30'h12000000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_100 = 30'h12000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_101 = 30'h12000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_36 = 30'h8000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_37 = 30'h8000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_95 = 30'h8000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_96 = 30'h8000000; // @[Parameters.scala:137:46] wire [28:0] _nodeOut_a_bits_legal_T_94 = 29'hA000000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_53 = 30'h10000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_54 = 30'h10000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_90 = 30'h10000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_91 = 30'h10000; // @[Parameters.scala:137:46] wire [26:0] _nodeOut_a_bits_legal_T_89 = 27'h10000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_16 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_17 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_85 = 30'h0; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_86 = 30'h0; // @[Parameters.scala:137:46] wire [26:0] _nodeOut_a_bits_legal_T_84 = 27'h0; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_80 = 30'h2100000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_81 = 30'h2100000; // @[Parameters.scala:137:46] wire [26:0] _nodeOut_a_bits_legal_T_79 = 27'h2100000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_26 = 30'h2000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_27 = 30'h2000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_75 = 30'h2000000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_76 = 30'h2000000; // @[Parameters.scala:137:46] wire [26:0] _nodeOut_a_bits_legal_T_74 = 27'h2000000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_65 = 30'h2003000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_66 = 30'h2003000; // @[Parameters.scala:137:46] wire [26:0] _nodeOut_a_bits_legal_T_64 = 27'h2003000; // @[Parameters.scala:137:41] wire [63:0] nodeOut_a_bits_a_data = 64'h80000000; // @[Edges.scala:480:17] wire [28:0] nodeOut_a_bits_a_address = 29'h1000; // @[Edges.scala:480:17] wire [17:0] _nodeOut_a_bits_legal_T_52 = 18'h11000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_40 = 30'h10001000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_41 = 30'h10001000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_42 = 30'h10001000; // @[Parameters.scala:137:46] wire [28:0] _nodeOut_a_bits_legal_T_35 = 29'h8001000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_31 = 30'h2011000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_32 = 30'h2011000; // @[Parameters.scala:137:46] wire [26:0] _nodeOut_a_bits_legal_T_30 = 27'h2011000; // @[Parameters.scala:137:41] wire [26:0] _nodeOut_a_bits_legal_T_25 = 27'h2001000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_21 = 30'h101000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_22 = 30'h101000; // @[Parameters.scala:137:46] wire [21:0] _nodeOut_a_bits_legal_T_20 = 22'h101000; // @[Parameters.scala:137:41] wire [13:0] _nodeOut_a_bits_legal_T_15 = 14'h1000; // @[Parameters.scala:137:41] wire [29:0] _nodeOut_a_bits_legal_T_6 = 30'h2000; // @[Parameters.scala:137:46] wire [29:0] _nodeOut_a_bits_legal_T_7 = 30'h2000; // @[Parameters.scala:137:46] wire [14:0] _nodeOut_a_bits_legal_T_5 = 15'h2000; // @[Parameters.scala:137:41] wire [25:0] _nodeOut_a_bits_legal_T_110 = 26'h2010000; // @[Parameters.scala:137:31] wire [28:0] _nodeOut_a_bits_legal_T_98 = 29'h12000000; // @[Parameters.scala:137:31] wire [27:0] _nodeOut_a_bits_legal_T_93 = 28'hA000000; // @[Parameters.scala:137:31] wire [25:0] _nodeOut_a_bits_legal_T_88 = 26'h10000; // @[Parameters.scala:137:31] wire [25:0] _nodeOut_a_bits_legal_T_83 = 26'h0; // @[Parameters.scala:137:31] wire [25:0] _nodeOut_a_bits_legal_T_78 = 26'h2100000; // @[Parameters.scala:137:31] wire [25:0] _nodeOut_a_bits_legal_T_63 = 26'h2003000; // @[Parameters.scala:137:31] wire [16:0] _nodeOut_a_bits_legal_T_51 = 17'h11000; // @[Parameters.scala:137:31] wire [28:0] _nodeOut_a_bits_legal_T_39 = 29'h10001000; // @[Parameters.scala:137:31] wire [27:0] _nodeOut_a_bits_legal_T_34 = 28'h8001000; // @[Parameters.scala:137:31] wire [25:0] _nodeOut_a_bits_legal_T_29 = 26'h2011000; // @[Parameters.scala:137:31] wire [25:0] _nodeOut_a_bits_legal_T_24 = 26'h2001000; // @[Parameters.scala:137:31] wire [20:0] _nodeOut_a_bits_legal_T_19 = 21'h101000; // @[Parameters.scala:137:31] wire [13:0] _nodeOut_a_bits_legal_T_4 = 14'h2000; // @[Parameters.scala:137:31] wire [2:0] _nodeOut_a_bits_a_mask_sizeOH_T = 3'h2; // @[Misc.scala:202:34] wire [2:0] _nodeOut_a_bits_a_mask_sizeOH_T_3 = 3'h2; // @[Misc.scala:202:34] wire [25:0] _nodeOut_a_bits_legal_T_73 = 26'h2000000; // @[Parameters.scala:137:31] wire [12:0] _nodeOut_a_bits_legal_T_14 = 13'h1000; // @[Parameters.scala:137:31] wire coupler_to_bus_named_pbus_auto_bus_xing_out_a_ready = auto_coupler_to_bus_named_pbus_bus_xing_out_a_ready_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_pbus_auto_bus_xing_out_a_valid; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_size; // @[LazyModuleImp.scala:138:7] wire [6:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_source; // @[LazyModuleImp.scala:138:7] wire [28:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [7:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_mask; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_bus_xing_out_d_ready; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_bus_xing_out_d_valid = auto_coupler_to_bus_named_pbus_bus_xing_out_d_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_opcode = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_param = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_size = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [6:0] coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_source = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_source_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_sink = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_denied = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_data = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_data_0; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_corrupt = auto_coupler_to_bus_named_pbus_bus_xing_out_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire cbus_clock_groups_auto_in_member_cbus_0_clock = auto_cbus_clock_groups_in_member_cbus_0_clock_0; // @[ClockGroup.scala:53:9] wire cbus_clock_groups_auto_in_member_cbus_0_reset = auto_cbus_clock_groups_in_member_cbus_0_reset_0; // @[ClockGroup.scala:53:9] wire bus_xingIn_a_ready; // @[MixedNode.scala:551:17] wire bus_xingIn_a_valid = auto_bus_xing_in_a_valid_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_opcode = auto_bus_xing_in_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] bus_xingIn_a_bits_param = auto_bus_xing_in_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] bus_xingIn_a_bits_size = auto_bus_xing_in_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] bus_xingIn_a_bits_source = auto_bus_xing_in_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [28:0] bus_xingIn_a_bits_address = auto_bus_xing_in_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] bus_xingIn_a_bits_mask = auto_bus_xing_in_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] bus_xingIn_a_bits_data = auto_bus_xing_in_a_bits_data_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_a_bits_corrupt = auto_bus_xing_in_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_d_ready = auto_bus_xing_in_d_ready_0; // @[ClockDomain.scala:14:9] wire bus_xingIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17] wire [5:0] bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17] wire bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [6:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [20:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [10:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [16:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bootrom_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [10:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [11:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_debug_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_debug_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [10:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [27:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_plic_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_plic_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [10:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [25:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_clint_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_clint_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [6:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [28:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_param_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_size_0; // @[ClockDomain.scala:14:9] wire [10:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_source_0; // @[ClockDomain.scala:14:9] wire [25:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_address_0; // @[ClockDomain.scala:14:9] wire [7:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_coupler_to_l2_ctrl_buffer_out_a_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_a_valid_0; // @[ClockDomain.scala:14:9] wire auto_coupler_to_l2_ctrl_buffer_out_d_ready_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_5_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_5_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_4_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_4_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_3_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_3_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_2_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_2_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9] wire auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [1:0] auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] wire [3:0] auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [5:0] auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] wire auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] wire clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] wire clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] wire cbus_clock_groups_nodeIn_member_cbus_0_clock = cbus_clock_groups_auto_in_member_cbus_0_clock; // @[ClockGroup.scala:53:9] wire cbus_clock_groups_nodeOut_member_cbus_0_clock; // @[MixedNode.scala:542:17] wire cbus_clock_groups_nodeIn_member_cbus_0_reset = cbus_clock_groups_auto_in_member_cbus_0_reset; // @[ClockGroup.scala:53:9] wire cbus_clock_groups_nodeOut_member_cbus_0_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_in_member_cbus_0_clock = cbus_clock_groups_auto_out_member_cbus_0_clock; // @[ClockGroup.scala:24:9, :53:9] wire clockGroup_auto_in_member_cbus_0_reset = cbus_clock_groups_auto_out_member_cbus_0_reset; // @[ClockGroup.scala:24:9, :53:9] assign cbus_clock_groups_auto_out_member_cbus_0_clock = cbus_clock_groups_nodeOut_member_cbus_0_clock; // @[ClockGroup.scala:53:9] assign cbus_clock_groups_auto_out_member_cbus_0_reset = cbus_clock_groups_nodeOut_member_cbus_0_reset; // @[ClockGroup.scala:53:9] assign cbus_clock_groups_nodeOut_member_cbus_0_clock = cbus_clock_groups_nodeIn_member_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign cbus_clock_groups_nodeOut_member_cbus_0_reset = cbus_clock_groups_nodeIn_member_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17] wire clockGroup_nodeIn_member_cbus_0_clock = clockGroup_auto_in_member_cbus_0_clock; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_clock; // @[MixedNode.scala:542:17] wire clockGroup_nodeIn_member_cbus_0_reset = clockGroup_auto_in_member_cbus_0_reset; // @[ClockGroup.scala:24:9] wire clockGroup_nodeOut_reset; // @[MixedNode.scala:542:17] wire clockGroup_auto_out_clock; // @[ClockGroup.scala:24:9] wire clockGroup_auto_out_reset; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_clock = clockGroup_nodeOut_clock; // @[ClockGroup.scala:24:9] assign clockGroup_auto_out_reset = clockGroup_nodeOut_reset; // @[ClockGroup.scala:24:9] assign clockGroup_nodeOut_clock = clockGroup_nodeIn_member_cbus_0_clock; // @[MixedNode.scala:542:17, :551:17] assign clockGroup_nodeOut_reset = clockGroup_nodeIn_member_cbus_0_reset; // @[MixedNode.scala:542:17, :551:17] wire buffer_1_nodeIn_a_ready; // @[MixedNode.scala:551:17] wire bus_xingOut_a_ready = buffer_1_auto_in_a_ready; // @[Buffer.scala:40:9] wire bus_xingOut_a_valid; // @[MixedNode.scala:542:17] wire buffer_1_nodeIn_a_valid = buffer_1_auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_1_nodeIn_a_bits_opcode = buffer_1_auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] buffer_1_nodeIn_a_bits_param = buffer_1_auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] buffer_1_nodeIn_a_bits_size = buffer_1_auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [5:0] bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] wire [5:0] buffer_1_nodeIn_a_bits_source = buffer_1_auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [28:0] bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] wire [28:0] buffer_1_nodeIn_a_bits_address = buffer_1_auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [7:0] buffer_1_nodeIn_a_bits_mask = buffer_1_auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] buffer_1_nodeIn_a_bits_data = buffer_1_auto_in_a_bits_data; // @[Buffer.scala:40:9] wire bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_1_nodeIn_a_bits_corrupt = buffer_1_auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire bus_xingOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_1_nodeIn_d_ready = buffer_1_auto_in_d_ready; // @[Buffer.scala:40:9] wire buffer_1_nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] buffer_1_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire bus_xingOut_d_valid = buffer_1_auto_in_d_valid; // @[Buffer.scala:40:9] wire [1:0] buffer_1_nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] bus_xingOut_d_bits_opcode = buffer_1_auto_in_d_bits_opcode; // @[Buffer.scala:40:9] wire [3:0] buffer_1_nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] bus_xingOut_d_bits_param = buffer_1_auto_in_d_bits_param; // @[Buffer.scala:40:9] wire [5:0] buffer_1_nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] bus_xingOut_d_bits_size = buffer_1_auto_in_d_bits_size; // @[Buffer.scala:40:9] wire buffer_1_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire [5:0] bus_xingOut_d_bits_source = buffer_1_auto_in_d_bits_source; // @[Buffer.scala:40:9] wire buffer_1_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire bus_xingOut_d_bits_sink = buffer_1_auto_in_d_bits_sink; // @[Buffer.scala:40:9] wire [63:0] buffer_1_nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire bus_xingOut_d_bits_denied = buffer_1_auto_in_d_bits_denied; // @[Buffer.scala:40:9] wire buffer_1_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] bus_xingOut_d_bits_data = buffer_1_auto_in_d_bits_data; // @[Buffer.scala:40:9] wire bus_xingOut_d_bits_corrupt = buffer_1_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_1_nodeOut_a_ready = buffer_1_auto_out_a_ready; // @[Buffer.scala:40:9] wire buffer_1_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] buffer_1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] buffer_1_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] buffer_1_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [5:0] buffer_1_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [28:0] buffer_1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] buffer_1_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] buffer_1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire buffer_1_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire buffer_1_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire buffer_1_nodeOut_d_valid = buffer_1_auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] buffer_1_nodeOut_d_bits_opcode = buffer_1_auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] buffer_1_nodeOut_d_bits_param = buffer_1_auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_1_nodeOut_d_bits_size = buffer_1_auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [5:0] buffer_1_nodeOut_d_bits_source = buffer_1_auto_out_d_bits_source; // @[Buffer.scala:40:9] wire buffer_1_nodeOut_d_bits_sink = buffer_1_auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire buffer_1_nodeOut_d_bits_denied = buffer_1_auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] buffer_1_nodeOut_d_bits_data = buffer_1_auto_out_d_bits_data; // @[Buffer.scala:40:9] wire buffer_1_nodeOut_d_bits_corrupt = buffer_1_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire [2:0] buffer_1_auto_out_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] buffer_1_auto_out_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] buffer_1_auto_out_a_bits_size; // @[Buffer.scala:40:9] wire [5:0] buffer_1_auto_out_a_bits_source; // @[Buffer.scala:40:9] wire [28:0] buffer_1_auto_out_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] buffer_1_auto_out_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] buffer_1_auto_out_a_bits_data; // @[Buffer.scala:40:9] wire buffer_1_auto_out_a_bits_corrupt; // @[Buffer.scala:40:9] wire buffer_1_auto_out_a_valid; // @[Buffer.scala:40:9] wire buffer_1_auto_out_d_ready; // @[Buffer.scala:40:9] assign buffer_1_nodeIn_a_ready = buffer_1_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_auto_out_a_valid = buffer_1_nodeOut_a_valid; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_opcode = buffer_1_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_param = buffer_1_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_size = buffer_1_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_source = buffer_1_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_address = buffer_1_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_mask = buffer_1_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_data = buffer_1_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_1_auto_out_a_bits_corrupt = buffer_1_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_1_auto_out_d_ready = buffer_1_nodeOut_d_ready; // @[Buffer.scala:40:9] assign buffer_1_nodeIn_d_valid = buffer_1_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_opcode = buffer_1_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_param = buffer_1_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_size = buffer_1_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_source = buffer_1_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_sink = buffer_1_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_denied = buffer_1_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_data = buffer_1_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeIn_d_bits_corrupt = buffer_1_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_auto_in_a_ready = buffer_1_nodeIn_a_ready; // @[Buffer.scala:40:9] assign buffer_1_nodeOut_a_valid = buffer_1_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_opcode = buffer_1_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_param = buffer_1_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_size = buffer_1_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_source = buffer_1_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_address = buffer_1_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_mask = buffer_1_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_data = buffer_1_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_a_bits_corrupt = buffer_1_nodeIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_nodeOut_d_ready = buffer_1_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_auto_in_d_valid = buffer_1_nodeIn_d_valid; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_opcode = buffer_1_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_param = buffer_1_nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_size = buffer_1_nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_source = buffer_1_nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_sink = buffer_1_nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_denied = buffer_1_nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_data = buffer_1_nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_bits_corrupt = buffer_1_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_a_valid = coupler_to_bus_named_pbus_auto_widget_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_opcode = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_param = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_size = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [6:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_source = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [28:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_address = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_mask = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_data = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_corrupt = coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_d_ready = coupler_to_bus_named_pbus_auto_widget_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [6:0] coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_bus_xingOut_a_ready = coupler_to_bus_named_pbus_auto_bus_xing_out_a_ready; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_pbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_size; // @[ClockDomain.scala:14:9] wire [6:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_source; // @[ClockDomain.scala:14:9] wire [28:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] coupler_to_bus_named_pbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_data; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_pbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_pbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17] assign auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready_0 = coupler_to_bus_named_pbus_auto_bus_xing_out_d_ready; // @[ClockDomain.scala:14:9] wire coupler_to_bus_named_pbus_bus_xingOut_d_valid = coupler_to_bus_named_pbus_auto_bus_xing_out_d_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_pbus_bus_xingOut_d_bits_opcode = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_to_bus_named_pbus_bus_xingOut_d_bits_param = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_param; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_pbus_bus_xingOut_d_bits_size = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_size; // @[MixedNode.scala:542:17] wire [6:0] coupler_to_bus_named_pbus_bus_xingOut_d_bits_source = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_source; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_pbus_bus_xingOut_d_bits_sink = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_sink; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_pbus_bus_xingOut_d_bits_denied = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_denied; // @[MixedNode.scala:542:17] wire [63:0] coupler_to_bus_named_pbus_bus_xingOut_d_bits_data = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_data; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_pbus_bus_xingOut_d_bits_corrupt = coupler_to_bus_named_pbus_auto_bus_xing_out_d_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_pbus_auto_widget_anon_in_a_ready; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_opcode; // @[LazyModuleImp.scala:138:7] wire [1:0] coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_param; // @[LazyModuleImp.scala:138:7] wire [2:0] coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_size; // @[LazyModuleImp.scala:138:7] wire [6:0] coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_source; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_sink; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_denied; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_corrupt; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_auto_widget_anon_in_d_valid; // @[LazyModuleImp.scala:138:7] wire coupler_to_bus_named_pbus_widget_anonIn_a_ready; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_a_ready = coupler_to_bus_named_pbus_widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonIn_a_valid = coupler_to_bus_named_pbus_widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_opcode = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_param = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_size = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [6:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_source = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [28:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_address = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_mask = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_widget_anonIn_a_bits_data = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonIn_a_bits_corrupt = coupler_to_bus_named_pbus_widget_auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonIn_d_ready = coupler_to_bus_named_pbus_widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonIn_d_valid; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_valid = coupler_to_bus_named_pbus_widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_opcode = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_pbus_widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_param = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_size = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire [6:0] coupler_to_bus_named_pbus_widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_source = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_sink = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_denied = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_data = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_corrupt = coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_bus_xingIn_a_ready; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_pbus_widget_anonOut_a_ready = coupler_to_bus_named_pbus_widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_pbus_bus_xingIn_a_valid = coupler_to_bus_named_pbus_widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_opcode = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_param = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [6:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [2:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_size = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire [28:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [6:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_source = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire [7:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [28:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_address = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire [7:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_mask = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire [63:0] coupler_to_bus_named_pbus_bus_xingIn_a_bits_data = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_widget_anonOut_d_ready; // @[MixedNode.scala:542:17] wire coupler_to_bus_named_pbus_bus_xingIn_a_bits_corrupt = coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_bus_xingIn_d_ready = coupler_to_bus_named_pbus_widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_bus_xingIn_d_valid; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_pbus_widget_anonOut_d_valid = coupler_to_bus_named_pbus_widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_bus_xingIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_pbus_widget_anonOut_d_bits_opcode = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] coupler_to_bus_named_pbus_bus_xingIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] coupler_to_bus_named_pbus_widget_anonOut_d_bits_param = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] coupler_to_bus_named_pbus_bus_xingIn_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] coupler_to_bus_named_pbus_widget_anonOut_d_bits_size = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [6:0] coupler_to_bus_named_pbus_bus_xingIn_d_bits_source; // @[MixedNode.scala:551:17] wire [6:0] coupler_to_bus_named_pbus_widget_anonOut_d_bits_source = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_bus_xingIn_d_bits_sink; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_pbus_widget_anonOut_d_bits_sink = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_bus_xingIn_d_bits_denied; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_pbus_widget_anonOut_d_bits_denied = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] coupler_to_bus_named_pbus_bus_xingIn_d_bits_data; // @[MixedNode.scala:551:17] wire [63:0] coupler_to_bus_named_pbus_widget_anonOut_d_bits_data = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire coupler_to_bus_named_pbus_bus_xingIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire coupler_to_bus_named_pbus_widget_anonOut_d_bits_corrupt = coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_anonIn_a_ready = coupler_to_bus_named_pbus_widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_valid = coupler_to_bus_named_pbus_widget_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_opcode = coupler_to_bus_named_pbus_widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_param = coupler_to_bus_named_pbus_widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_size = coupler_to_bus_named_pbus_widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_source = coupler_to_bus_named_pbus_widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_address = coupler_to_bus_named_pbus_widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_mask = coupler_to_bus_named_pbus_widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_data = coupler_to_bus_named_pbus_widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_bits_corrupt = coupler_to_bus_named_pbus_widget_anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_ready = coupler_to_bus_named_pbus_widget_anonOut_d_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_anonIn_d_valid = coupler_to_bus_named_pbus_widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_opcode = coupler_to_bus_named_pbus_widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_param = coupler_to_bus_named_pbus_widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_size = coupler_to_bus_named_pbus_widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_source = coupler_to_bus_named_pbus_widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_sink = coupler_to_bus_named_pbus_widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_denied = coupler_to_bus_named_pbus_widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_data = coupler_to_bus_named_pbus_widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonIn_d_bits_corrupt = coupler_to_bus_named_pbus_widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_auto_anon_in_a_ready = coupler_to_bus_named_pbus_widget_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_anonOut_a_valid = coupler_to_bus_named_pbus_widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_opcode = coupler_to_bus_named_pbus_widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_param = coupler_to_bus_named_pbus_widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_size = coupler_to_bus_named_pbus_widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_source = coupler_to_bus_named_pbus_widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_address = coupler_to_bus_named_pbus_widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_mask = coupler_to_bus_named_pbus_widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_data = coupler_to_bus_named_pbus_widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_a_bits_corrupt = coupler_to_bus_named_pbus_widget_anonIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_anonOut_d_ready = coupler_to_bus_named_pbus_widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_valid = coupler_to_bus_named_pbus_widget_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_opcode = coupler_to_bus_named_pbus_widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_param = coupler_to_bus_named_pbus_widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_size = coupler_to_bus_named_pbus_widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_source = coupler_to_bus_named_pbus_widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_sink = coupler_to_bus_named_pbus_widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_denied = coupler_to_bus_named_pbus_widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_data = coupler_to_bus_named_pbus_widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_in_d_bits_corrupt = coupler_to_bus_named_pbus_widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_bus_xingIn_a_ready = coupler_to_bus_named_pbus_bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_valid = coupler_to_bus_named_pbus_bus_xingOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_opcode = coupler_to_bus_named_pbus_bus_xingOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_param = coupler_to_bus_named_pbus_bus_xingOut_a_bits_param; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_size = coupler_to_bus_named_pbus_bus_xingOut_a_bits_size; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_source = coupler_to_bus_named_pbus_bus_xingOut_a_bits_source; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_address = coupler_to_bus_named_pbus_bus_xingOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_mask = coupler_to_bus_named_pbus_bus_xingOut_a_bits_mask; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_data = coupler_to_bus_named_pbus_bus_xingOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_a_bits_corrupt = coupler_to_bus_named_pbus_bus_xingOut_a_bits_corrupt; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_auto_bus_xing_out_d_ready = coupler_to_bus_named_pbus_bus_xingOut_d_ready; // @[MixedNode.scala:542:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_valid = coupler_to_bus_named_pbus_bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_opcode = coupler_to_bus_named_pbus_bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_param = coupler_to_bus_named_pbus_bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_size = coupler_to_bus_named_pbus_bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_source = coupler_to_bus_named_pbus_bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_sink = coupler_to_bus_named_pbus_bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_denied = coupler_to_bus_named_pbus_bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_data = coupler_to_bus_named_pbus_bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingIn_d_bits_corrupt = coupler_to_bus_named_pbus_bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_auto_anon_out_a_ready = coupler_to_bus_named_pbus_bus_xingIn_a_ready; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_bus_xingOut_a_valid = coupler_to_bus_named_pbus_bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_opcode = coupler_to_bus_named_pbus_bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_param = coupler_to_bus_named_pbus_bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_size = coupler_to_bus_named_pbus_bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_source = coupler_to_bus_named_pbus_bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_address = coupler_to_bus_named_pbus_bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_mask = coupler_to_bus_named_pbus_bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_data = coupler_to_bus_named_pbus_bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_a_bits_corrupt = coupler_to_bus_named_pbus_bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_bus_xingOut_d_ready = coupler_to_bus_named_pbus_bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_valid = coupler_to_bus_named_pbus_bus_xingIn_d_valid; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_opcode = coupler_to_bus_named_pbus_bus_xingIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_param = coupler_to_bus_named_pbus_bus_xingIn_d_bits_param; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_size = coupler_to_bus_named_pbus_bus_xingIn_d_bits_size; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_source = coupler_to_bus_named_pbus_bus_xingIn_d_bits_source; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_sink = coupler_to_bus_named_pbus_bus_xingIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_denied = coupler_to_bus_named_pbus_bus_xingIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_data = coupler_to_bus_named_pbus_bus_xingIn_d_bits_data; // @[WidthWidget.scala:27:9] assign coupler_to_bus_named_pbus_widget_auto_anon_out_d_bits_corrupt = coupler_to_bus_named_pbus_bus_xingIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire coupler_from_port_named_custom_boot_pin_tlIn_a_ready; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = coupler_from_port_named_custom_boot_pin_auto_tl_in_a_ready; // @[MixedNode.scala:542:17] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlIn_a_valid = coupler_from_port_named_custom_boot_pin_auto_tl_in_a_valid; // @[MixedNode.scala:551:17] wire [28:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [28:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_address = coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_address; // @[MixedNode.scala:551:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_port_named_custom_boot_pin_tlIn_a_bits_data = coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_data; // @[MixedNode.scala:551:17] wire coupler_from_port_named_custom_boot_pin_tlIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] coupler_from_port_named_custom_boot_pin_tlIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire nodeOut_d_valid = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_valid; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_port_named_custom_boot_pin_tlIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_d_bits_opcode = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_port_named_custom_boot_pin_tlIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_d_bits_param = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_d_bits_size = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_size; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlIn_d_bits_sink; // @[MixedNode.scala:551:17] wire coupler_from_port_named_custom_boot_pin_tlIn_d_bits_denied; // @[MixedNode.scala:551:17] wire nodeOut_d_bits_sink = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_sink; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_port_named_custom_boot_pin_tlIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeOut_d_bits_denied = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_denied; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] nodeOut_d_bits_data = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_corrupt = coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_corrupt; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_a_ready = coupler_from_port_named_custom_boot_pin_auto_tl_out_a_ready; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_a_valid; // @[MixedNode.scala:542:17] wire [28:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_address; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_port_named_custom_boot_pin_tlOut_a_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_d_valid = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_valid; // @[MixedNode.scala:542:17] wire [2:0] coupler_from_port_named_custom_boot_pin_tlOut_d_bits_opcode = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_opcode; // @[MixedNode.scala:542:17] wire [1:0] coupler_from_port_named_custom_boot_pin_tlOut_d_bits_param = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_param; // @[MixedNode.scala:542:17] wire [3:0] coupler_from_port_named_custom_boot_pin_tlOut_d_bits_size = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_size; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_d_bits_sink = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_sink; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_d_bits_denied = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_denied; // @[MixedNode.scala:542:17] wire [63:0] coupler_from_port_named_custom_boot_pin_tlOut_d_bits_data = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_data; // @[MixedNode.scala:542:17] wire coupler_from_port_named_custom_boot_pin_tlOut_d_bits_corrupt = coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_corrupt; // @[MixedNode.scala:542:17] wire [28:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_address; // @[LazyModuleImp.scala:138:7] wire [63:0] coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_data; // @[LazyModuleImp.scala:138:7] wire coupler_from_port_named_custom_boot_pin_auto_tl_out_a_valid; // @[LazyModuleImp.scala:138:7] assign coupler_from_port_named_custom_boot_pin_tlIn_a_ready = coupler_from_port_named_custom_boot_pin_tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_out_a_valid = coupler_from_port_named_custom_boot_pin_tlOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_address = coupler_from_port_named_custom_boot_pin_tlOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_data = coupler_from_port_named_custom_boot_pin_tlOut_a_bits_data; // @[MixedNode.scala:542:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_valid = coupler_from_port_named_custom_boot_pin_tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_opcode = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_param = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_size = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_sink = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_denied = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_data = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlIn_d_bits_corrupt = coupler_from_port_named_custom_boot_pin_tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_a_ready = coupler_from_port_named_custom_boot_pin_tlIn_a_ready; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_tlOut_a_valid = coupler_from_port_named_custom_boot_pin_tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlOut_a_bits_address = coupler_from_port_named_custom_boot_pin_tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_tlOut_a_bits_data = coupler_from_port_named_custom_boot_pin_tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_valid = coupler_from_port_named_custom_boot_pin_tlIn_d_valid; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_opcode = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_opcode; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_param = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_param; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_size = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_size; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_sink = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_sink; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_denied = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_denied; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_data = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_data; // @[MixedNode.scala:551:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_d_bits_corrupt = coupler_from_port_named_custom_boot_pin_tlIn_d_bits_corrupt; // @[MixedNode.scala:551:17] assign childClock = clockSinkNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockSinkNodeIn_reset; // @[MixedNode.scala:551:17] assign bus_xingIn_a_ready = bus_xingOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign buffer_1_auto_in_a_valid = bus_xingOut_a_valid; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_opcode = bus_xingOut_a_bits_opcode; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_param = bus_xingOut_a_bits_param; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_size = bus_xingOut_a_bits_size; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_source = bus_xingOut_a_bits_source; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_address = bus_xingOut_a_bits_address; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_mask = bus_xingOut_a_bits_mask; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_data = bus_xingOut_a_bits_data; // @[Buffer.scala:40:9] assign buffer_1_auto_in_a_bits_corrupt = bus_xingOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign buffer_1_auto_in_d_ready = bus_xingOut_d_ready; // @[Buffer.scala:40:9] assign bus_xingIn_d_valid = bus_xingOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_opcode = bus_xingOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_param = bus_xingOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_size = bus_xingOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_source = bus_xingOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_sink = bus_xingOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_denied = bus_xingOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_data = bus_xingOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign bus_xingIn_d_bits_corrupt = bus_xingOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign auto_bus_xing_in_a_ready_0 = bus_xingIn_a_ready; // @[ClockDomain.scala:14:9] assign bus_xingOut_a_valid = bus_xingIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_opcode = bus_xingIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_param = bus_xingIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_size = bus_xingIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_source = bus_xingIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_address = bus_xingIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_mask = bus_xingIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_data = bus_xingIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_a_bits_corrupt = bus_xingIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign bus_xingOut_d_ready = bus_xingIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_bus_xing_in_d_valid_0 = bus_xingIn_d_valid; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_opcode_0 = bus_xingIn_d_bits_opcode; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_param_0 = bus_xingIn_d_bits_param; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_size_0 = bus_xingIn_d_bits_size; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_source_0 = bus_xingIn_d_bits_source; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_sink_0 = bus_xingIn_d_bits_sink; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_denied_0 = bus_xingIn_d_bits_denied; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_data_0 = bus_xingIn_d_bits_data; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_corrupt_0 = bus_xingIn_d_bits_corrupt; // @[ClockDomain.scala:14:9] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_a_valid = nodeOut_a_valid; // @[MixedNode.scala:542:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_address = nodeOut_a_bits_address; // @[MixedNode.scala:542:17] assign coupler_from_port_named_custom_boot_pin_auto_tl_in_a_bits_data = nodeOut_a_bits_data; // @[MixedNode.scala:542:17] reg [2:0] state; // @[CustomBootPin.scala:39:28] wire _T_1 = state == 3'h1; // @[CustomBootPin.scala:39:28, :43:24] assign nodeOut_a_valid = (\|state) & (_T_1 \| state != 3'h2 & state == 3'h3); // @[CustomBootPin.scala:39:28, :40:20, :43:24, :46:24] assign nodeOut_a_bits_address = _T_1 ? 29'h1000 : 29'h2000000; // @[CustomBootPin.scala:43:24, :47:23] assign nodeOut_a_bits_data = _T_1 ? 64'h80000000 : 64'h1; // @[CustomBootPin.scala:43:24, :47:23] wire [2:0] _GEN = state == 3'h5 & ~custom_boot ? 3'h0 : state; // @[CustomBootPin.scala:39:28, :43:24, :67:{29,43,51}] wire [7:0][2:0] _GEN_0 = {{_GEN}, {_GEN}, {_GEN}, {nodeOut_d_valid ? 3'h5 : state}, {nodeOut_a_ready & nodeOut_a_valid ? 3'h4 : state}, {nodeOut_d_valid ? 3'h3 : state}, {nodeOut_a_ready & nodeOut_a_valid ? 3'h2 : state}, {custom_boot ? 3'h1 : state}}; // @[Decoupled.scala:51:35] always @(posedge childClock) begin // @[LazyModuleImp.scala:155:31] if (childReset) // @[LazyModuleImp.scala:155:31, :158:31] state <= 3'h0; // @[CustomBootPin.scala:39:28] else // @[LazyModuleImp.scala:155:31] state <= _GEN_0[state]; // @[CustomBootPin.scala:39:28, :43:24, :44:46, :53:30, :55:58, :64:30, :66:50] always @(posedge) FixedClockBroadcast_7 fixedClockNode ( // @[ClockGroup.scala:115:114] .auto_anon_in_clock (clockGroup_auto_out_clock), // @[ClockGroup.scala:24:9] .auto_anon_in_reset (clockGroup_auto_out_reset), // @[ClockGroup.scala:24:9] .auto_anon_out_6_clock (auto_fixedClockNode_anon_out_5_clock_0), .auto_anon_out_6_reset (auto_fixedClockNode_anon_out_5_reset_0), .auto_anon_out_5_clock (auto_fixedClockNode_anon_out_4_clock_0), .auto_anon_out_5_reset (auto_fixedClockNode_anon_out_4_reset_0), .auto_anon_out_4_clock (auto_fixedClockNode_anon_out_3_clock_0), .auto_anon_out_4_reset (auto_fixedClockNode_anon_out_3_reset_0), .auto_anon_out_3_clock (auto_fixedClockNode_anon_out_2_clock_0), .auto_anon_out_3_reset (auto_fixedClockNode_anon_out_2_reset_0), .auto_anon_out_2_clock (auto_fixedClockNode_anon_out_1_clock_0), .auto_anon_out_2_reset (auto_fixedClockNode_anon_out_1_reset_0), .auto_anon_out_1_clock (auto_fixedClockNode_anon_out_0_clock_0), .auto_anon_out_1_reset (auto_fixedClockNode_anon_out_0_reset_0), .auto_anon_out_0_clock (clockSinkNodeIn_clock), .auto_anon_out_0_reset (clockSinkNodeIn_reset) ); // @[ClockGroup.scala:115:114] TLFIFOFixer_2 fixer ( // @[PeripheryBus.scala:54:33] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_a_ready (_fixer_auto_anon_in_a_ready), .auto_anon_in_a_valid (_buffer_auto_out_a_valid), // @[Buffer.scala:75:28] .auto_anon_in_a_bits_opcode (_buffer_auto_out_a_bits_opcode), // @[Buffer.scala:75:28] .auto_anon_in_a_bits_param (_buffer_auto_out_a_bits_param), // @[Buffer.scala:75:28] .auto_anon_in_a_bits_size (_buffer_auto_out_a_bits_size), // @[Buffer.scala:75:28] .auto_anon_in_a_bits_source (_buffer_auto_out_a_bits_source), // @[Buffer.scala:75:28] .auto_anon_in_a_bits_address (_buffer_auto_out_a_bits_address), // @[Buffer.scala:75:28] .auto_anon_in_a_bits_mask (_buffer_auto_out_a_bits_mask), // @[Buffer.scala:75:28] .auto_anon_in_a_bits_data (_buffer_auto_out_a_bits_data), // @[Buffer.scala:75:28] .auto_anon_in_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt), // @[Buffer.scala:75:28] .auto_anon_in_d_ready (_buffer_auto_out_d_ready), // @[Buffer.scala:75:28] .auto_anon_in_d_valid (_fixer_auto_anon_in_d_valid), .auto_anon_in_d_bits_opcode (_fixer_auto_anon_in_d_bits_opcode), .auto_anon_in_d_bits_param (_fixer_auto_anon_in_d_bits_param), .auto_anon_in_d_bits_size (_fixer_auto_anon_in_d_bits_size), .auto_anon_in_d_bits_source (_fixer_auto_anon_in_d_bits_source), .auto_anon_in_d_bits_sink (_fixer_auto_anon_in_d_bits_sink), .auto_anon_in_d_bits_denied (_fixer_auto_anon_in_d_bits_denied), .auto_anon_in_d_bits_data (_fixer_auto_anon_in_d_bits_data), .auto_anon_in_d_bits_corrupt (_fixer_auto_anon_in_d_bits_corrupt), .auto_anon_out_a_ready (_out_xbar_auto_anon_in_a_ready), // @[PeripheryBus.scala:57:30] .auto_anon_out_a_valid (_fixer_auto_anon_out_a_valid), .auto_anon_out_a_bits_opcode (_fixer_auto_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (_fixer_auto_anon_out_a_bits_param), .auto_anon_out_a_bits_size (_fixer_auto_anon_out_a_bits_size), .auto_anon_out_a_bits_source (_fixer_auto_anon_out_a_bits_source), .auto_anon_out_a_bits_address (_fixer_auto_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (_fixer_auto_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (_fixer_auto_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (_fixer_auto_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (_fixer_auto_anon_out_d_ready), .auto_anon_out_d_valid (_out_xbar_auto_anon_in_d_valid), // @[PeripheryBus.scala:57:30] .auto_anon_out_d_bits_opcode (_out_xbar_auto_anon_in_d_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_anon_out_d_bits_param (_out_xbar_auto_anon_in_d_bits_param), // @[PeripheryBus.scala:57:30] .auto_anon_out_d_bits_size (_out_xbar_auto_anon_in_d_bits_size), // @[PeripheryBus.scala:57:30] .auto_anon_out_d_bits_source (_out_xbar_auto_anon_in_d_bits_source), // @[PeripheryBus.scala:57:30] .auto_anon_out_d_bits_sink (_out_xbar_auto_anon_in_d_bits_sink), // @[PeripheryBus.scala:57:30] .auto_anon_out_d_bits_denied (_out_xbar_auto_anon_in_d_bits_denied), // @[PeripheryBus.scala:57:30] .auto_anon_out_d_bits_data (_out_xbar_auto_anon_in_d_bits_data), // @[PeripheryBus.scala:57:30] .auto_anon_out_d_bits_corrupt (_out_xbar_auto_anon_in_d_bits_corrupt) // @[PeripheryBus.scala:57:30] ); // @[PeripheryBus.scala:54:33] TLXbar_cbus_in_i2_o1_a29d64s7k1z4u in_xbar ( // @[PeripheryBus.scala:56:29] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_1_a_ready (coupler_from_port_named_custom_boot_pin_auto_tl_out_a_ready), .auto_anon_in_1_a_valid (coupler_from_port_named_custom_boot_pin_auto_tl_out_a_valid), // @[LazyModuleImp.scala:138:7] .auto_anon_in_1_a_bits_address (coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_address), // @[LazyModuleImp.scala:138:7] .auto_anon_in_1_a_bits_data (coupler_from_port_named_custom_boot_pin_auto_tl_out_a_bits_data), // @[LazyModuleImp.scala:138:7] .auto_anon_in_1_d_valid (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_valid), .auto_anon_in_1_d_bits_opcode (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_opcode), .auto_anon_in_1_d_bits_param (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_param), .auto_anon_in_1_d_bits_size (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_size), .auto_anon_in_1_d_bits_sink (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_sink), .auto_anon_in_1_d_bits_denied (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_denied), .auto_anon_in_1_d_bits_data (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_data), .auto_anon_in_1_d_bits_corrupt (coupler_from_port_named_custom_boot_pin_auto_tl_out_d_bits_corrupt), .auto_anon_in_0_a_ready (buffer_1_auto_out_a_ready), .auto_anon_in_0_a_valid (buffer_1_auto_out_a_valid), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_opcode (buffer_1_auto_out_a_bits_opcode), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_param (buffer_1_auto_out_a_bits_param), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_size (buffer_1_auto_out_a_bits_size), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_source (buffer_1_auto_out_a_bits_source), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_address (buffer_1_auto_out_a_bits_address), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_mask (buffer_1_auto_out_a_bits_mask), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_data (buffer_1_auto_out_a_bits_data), // @[Buffer.scala:40:9] .auto_anon_in_0_a_bits_corrupt (buffer_1_auto_out_a_bits_corrupt), // @[Buffer.scala:40:9] .auto_anon_in_0_d_ready (buffer_1_auto_out_d_ready), // @[Buffer.scala:40:9] .auto_anon_in_0_d_valid (buffer_1_auto_out_d_valid), .auto_anon_in_0_d_bits_opcode (buffer_1_auto_out_d_bits_opcode), .auto_anon_in_0_d_bits_param (buffer_1_auto_out_d_bits_param), .auto_anon_in_0_d_bits_size (buffer_1_auto_out_d_bits_size), .auto_anon_in_0_d_bits_source (buffer_1_auto_out_d_bits_source), .auto_anon_in_0_d_bits_sink (buffer_1_auto_out_d_bits_sink), .auto_anon_in_0_d_bits_denied (buffer_1_auto_out_d_bits_denied), .auto_anon_in_0_d_bits_data (buffer_1_auto_out_d_bits_data), .auto_anon_in_0_d_bits_corrupt (buffer_1_auto_out_d_bits_corrupt), .auto_anon_out_a_ready (_atomics_auto_in_a_ready), // @[AtomicAutomata.scala:289:29] .auto_anon_out_a_valid (_in_xbar_auto_anon_out_a_valid), .auto_anon_out_a_bits_opcode (_in_xbar_auto_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (_in_xbar_auto_anon_out_a_bits_param), .auto_anon_out_a_bits_size (_in_xbar_auto_anon_out_a_bits_size), .auto_anon_out_a_bits_source (_in_xbar_auto_anon_out_a_bits_source), .auto_anon_out_a_bits_address (_in_xbar_auto_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (_in_xbar_auto_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (_in_xbar_auto_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (_in_xbar_auto_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (_in_xbar_auto_anon_out_d_ready), .auto_anon_out_d_valid (_atomics_auto_in_d_valid), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_opcode (_atomics_auto_in_d_bits_opcode), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_param (_atomics_auto_in_d_bits_param), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_size (_atomics_auto_in_d_bits_size), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_source (_atomics_auto_in_d_bits_source), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_sink (_atomics_auto_in_d_bits_sink), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_denied (_atomics_auto_in_d_bits_denied), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_data (_atomics_auto_in_d_bits_data), // @[AtomicAutomata.scala:289:29] .auto_anon_out_d_bits_corrupt (_atomics_auto_in_d_bits_corrupt) // @[AtomicAutomata.scala:289:29] ); // @[PeripheryBus.scala:56:29] TLXbar_cbus_out_i1_o8_a29d64s7k1z4u out_xbar ( // @[PeripheryBus.scala:57:30] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_a_ready (_out_xbar_auto_anon_in_a_ready), .auto_anon_in_a_valid (_fixer_auto_anon_out_a_valid), // @[PeripheryBus.scala:54:33] .auto_anon_in_a_bits_opcode (_fixer_auto_anon_out_a_bits_opcode), // @[PeripheryBus.scala:54:33] .auto_anon_in_a_bits_param (_fixer_auto_anon_out_a_bits_param), // @[PeripheryBus.scala:54:33] .auto_anon_in_a_bits_size (_fixer_auto_anon_out_a_bits_size), // @[PeripheryBus.scala:54:33] .auto_anon_in_a_bits_source (_fixer_auto_anon_out_a_bits_source), // @[PeripheryBus.scala:54:33] .auto_anon_in_a_bits_address (_fixer_auto_anon_out_a_bits_address), // @[PeripheryBus.scala:54:33] .auto_anon_in_a_bits_mask (_fixer_auto_anon_out_a_bits_mask), // @[PeripheryBus.scala:54:33] .auto_anon_in_a_bits_data (_fixer_auto_anon_out_a_bits_data), // @[PeripheryBus.scala:54:33] .auto_anon_in_a_bits_corrupt (_fixer_auto_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:54:33] .auto_anon_in_d_ready (_fixer_auto_anon_out_d_ready), // @[PeripheryBus.scala:54:33] .auto_anon_in_d_valid (_out_xbar_auto_anon_in_d_valid), .auto_anon_in_d_bits_opcode (_out_xbar_auto_anon_in_d_bits_opcode), .auto_anon_in_d_bits_param (_out_xbar_auto_anon_in_d_bits_param), .auto_anon_in_d_bits_size (_out_xbar_auto_anon_in_d_bits_size), .auto_anon_in_d_bits_source (_out_xbar_auto_anon_in_d_bits_source), .auto_anon_in_d_bits_sink (_out_xbar_auto_anon_in_d_bits_sink), .auto_anon_in_d_bits_denied (_out_xbar_auto_anon_in_d_bits_denied), .auto_anon_in_d_bits_data (_out_xbar_auto_anon_in_d_bits_data), .auto_anon_in_d_bits_corrupt (_out_xbar_auto_anon_in_d_bits_corrupt), .auto_anon_out_7_a_ready (_coupler_to_prci_ctrl_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_7_a_valid (_out_xbar_auto_anon_out_7_a_valid), .auto_anon_out_7_a_bits_opcode (_out_xbar_auto_anon_out_7_a_bits_opcode), .auto_anon_out_7_a_bits_param (_out_xbar_auto_anon_out_7_a_bits_param), .auto_anon_out_7_a_bits_size (_out_xbar_auto_anon_out_7_a_bits_size), .auto_anon_out_7_a_bits_source (_out_xbar_auto_anon_out_7_a_bits_source), .auto_anon_out_7_a_bits_address (_out_xbar_auto_anon_out_7_a_bits_address), .auto_anon_out_7_a_bits_mask (_out_xbar_auto_anon_out_7_a_bits_mask), .auto_anon_out_7_a_bits_data (_out_xbar_auto_anon_out_7_a_bits_data), .auto_anon_out_7_a_bits_corrupt (_out_xbar_auto_anon_out_7_a_bits_corrupt), .auto_anon_out_7_d_ready (_out_xbar_auto_anon_out_7_d_ready), .auto_anon_out_7_d_valid (_coupler_to_prci_ctrl_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_opcode (_coupler_to_prci_ctrl_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_param (_coupler_to_prci_ctrl_auto_tl_in_d_bits_param), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_size (_coupler_to_prci_ctrl_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_source (_coupler_to_prci_ctrl_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_sink (_coupler_to_prci_ctrl_auto_tl_in_d_bits_sink), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_denied (_coupler_to_prci_ctrl_auto_tl_in_d_bits_denied), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_data (_coupler_to_prci_ctrl_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_7_d_bits_corrupt (_coupler_to_prci_ctrl_auto_tl_in_d_bits_corrupt), // @[LazyScope.scala:98:27] .auto_anon_out_6_a_ready (_coupler_to_bootrom_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_6_a_valid (_out_xbar_auto_anon_out_6_a_valid), .auto_anon_out_6_a_bits_opcode (_out_xbar_auto_anon_out_6_a_bits_opcode), .auto_anon_out_6_a_bits_param (_out_xbar_auto_anon_out_6_a_bits_param), .auto_anon_out_6_a_bits_size (_out_xbar_auto_anon_out_6_a_bits_size), .auto_anon_out_6_a_bits_source (_out_xbar_auto_anon_out_6_a_bits_source), .auto_anon_out_6_a_bits_address (_out_xbar_auto_anon_out_6_a_bits_address), .auto_anon_out_6_a_bits_mask (_out_xbar_auto_anon_out_6_a_bits_mask), .auto_anon_out_6_a_bits_data (_out_xbar_auto_anon_out_6_a_bits_data), .auto_anon_out_6_a_bits_corrupt (_out_xbar_auto_anon_out_6_a_bits_corrupt), .auto_anon_out_6_d_ready (_out_xbar_auto_anon_out_6_d_ready), .auto_anon_out_6_d_valid (_coupler_to_bootrom_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_6_d_bits_size (_coupler_to_bootrom_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_6_d_bits_source (_coupler_to_bootrom_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_6_d_bits_data (_coupler_to_bootrom_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_5_a_ready (_coupler_to_debug_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_5_a_valid (_out_xbar_auto_anon_out_5_a_valid), .auto_anon_out_5_a_bits_opcode (_out_xbar_auto_anon_out_5_a_bits_opcode), .auto_anon_out_5_a_bits_param (_out_xbar_auto_anon_out_5_a_bits_param), .auto_anon_out_5_a_bits_size (_out_xbar_auto_anon_out_5_a_bits_size), .auto_anon_out_5_a_bits_source (_out_xbar_auto_anon_out_5_a_bits_source), .auto_anon_out_5_a_bits_address (_out_xbar_auto_anon_out_5_a_bits_address), .auto_anon_out_5_a_bits_mask (_out_xbar_auto_anon_out_5_a_bits_mask), .auto_anon_out_5_a_bits_data (_out_xbar_auto_anon_out_5_a_bits_data), .auto_anon_out_5_a_bits_corrupt (_out_xbar_auto_anon_out_5_a_bits_corrupt), .auto_anon_out_5_d_ready (_out_xbar_auto_anon_out_5_d_ready), .auto_anon_out_5_d_valid (_coupler_to_debug_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_5_d_bits_opcode (_coupler_to_debug_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_5_d_bits_size (_coupler_to_debug_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_5_d_bits_source (_coupler_to_debug_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_5_d_bits_data (_coupler_to_debug_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_4_a_ready (_coupler_to_plic_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_4_a_valid (_out_xbar_auto_anon_out_4_a_valid), .auto_anon_out_4_a_bits_opcode (_out_xbar_auto_anon_out_4_a_bits_opcode), .auto_anon_out_4_a_bits_param (_out_xbar_auto_anon_out_4_a_bits_param), .auto_anon_out_4_a_bits_size (_out_xbar_auto_anon_out_4_a_bits_size), .auto_anon_out_4_a_bits_source (_out_xbar_auto_anon_out_4_a_bits_source), .auto_anon_out_4_a_bits_address (_out_xbar_auto_anon_out_4_a_bits_address), .auto_anon_out_4_a_bits_mask (_out_xbar_auto_anon_out_4_a_bits_mask), .auto_anon_out_4_a_bits_data (_out_xbar_auto_anon_out_4_a_bits_data), .auto_anon_out_4_a_bits_corrupt (_out_xbar_auto_anon_out_4_a_bits_corrupt), .auto_anon_out_4_d_ready (_out_xbar_auto_anon_out_4_d_ready), .auto_anon_out_4_d_valid (_coupler_to_plic_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_4_d_bits_opcode (_coupler_to_plic_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_4_d_bits_size (_coupler_to_plic_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_4_d_bits_source (_coupler_to_plic_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_4_d_bits_data (_coupler_to_plic_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_3_a_ready (_coupler_to_clint_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_3_a_valid (_out_xbar_auto_anon_out_3_a_valid), .auto_anon_out_3_a_bits_opcode (_out_xbar_auto_anon_out_3_a_bits_opcode), .auto_anon_out_3_a_bits_param (_out_xbar_auto_anon_out_3_a_bits_param), .auto_anon_out_3_a_bits_size (_out_xbar_auto_anon_out_3_a_bits_size), .auto_anon_out_3_a_bits_source (_out_xbar_auto_anon_out_3_a_bits_source), .auto_anon_out_3_a_bits_address (_out_xbar_auto_anon_out_3_a_bits_address), .auto_anon_out_3_a_bits_mask (_out_xbar_auto_anon_out_3_a_bits_mask), .auto_anon_out_3_a_bits_data (_out_xbar_auto_anon_out_3_a_bits_data), .auto_anon_out_3_a_bits_corrupt (_out_xbar_auto_anon_out_3_a_bits_corrupt), .auto_anon_out_3_d_ready (_out_xbar_auto_anon_out_3_d_ready), .auto_anon_out_3_d_valid (_coupler_to_clint_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_3_d_bits_opcode (_coupler_to_clint_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_3_d_bits_size (_coupler_to_clint_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_3_d_bits_source (_coupler_to_clint_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_3_d_bits_data (_coupler_to_clint_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_2_a_ready (coupler_to_bus_named_pbus_auto_widget_anon_in_a_ready), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_a_valid (coupler_to_bus_named_pbus_auto_widget_anon_in_a_valid), .auto_anon_out_2_a_bits_opcode (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_opcode), .auto_anon_out_2_a_bits_param (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_param), .auto_anon_out_2_a_bits_size (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_size), .auto_anon_out_2_a_bits_source (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_source), .auto_anon_out_2_a_bits_address (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_address), .auto_anon_out_2_a_bits_mask (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_mask), .auto_anon_out_2_a_bits_data (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_data), .auto_anon_out_2_a_bits_corrupt (coupler_to_bus_named_pbus_auto_widget_anon_in_a_bits_corrupt), .auto_anon_out_2_d_ready (coupler_to_bus_named_pbus_auto_widget_anon_in_d_ready), .auto_anon_out_2_d_valid (coupler_to_bus_named_pbus_auto_widget_anon_in_d_valid), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_opcode (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_opcode), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_param (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_param), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_size (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_size), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_source (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_source), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_sink (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_sink), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_denied (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_denied), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_data (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_data), // @[LazyModuleImp.scala:138:7] .auto_anon_out_2_d_bits_corrupt (coupler_to_bus_named_pbus_auto_widget_anon_in_d_bits_corrupt), // @[LazyModuleImp.scala:138:7] .auto_anon_out_1_a_ready (_coupler_to_l2_ctrl_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_1_a_valid (_out_xbar_auto_anon_out_1_a_valid), .auto_anon_out_1_a_bits_opcode (_out_xbar_auto_anon_out_1_a_bits_opcode), .auto_anon_out_1_a_bits_param (_out_xbar_auto_anon_out_1_a_bits_param), .auto_anon_out_1_a_bits_size (_out_xbar_auto_anon_out_1_a_bits_size), .auto_anon_out_1_a_bits_source (_out_xbar_auto_anon_out_1_a_bits_source), .auto_anon_out_1_a_bits_address (_out_xbar_auto_anon_out_1_a_bits_address), .auto_anon_out_1_a_bits_mask (_out_xbar_auto_anon_out_1_a_bits_mask), .auto_anon_out_1_a_bits_data (_out_xbar_auto_anon_out_1_a_bits_data), .auto_anon_out_1_a_bits_corrupt (_out_xbar_auto_anon_out_1_a_bits_corrupt), .auto_anon_out_1_d_ready (_out_xbar_auto_anon_out_1_d_ready), .auto_anon_out_1_d_valid (_coupler_to_l2_ctrl_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_opcode (_coupler_to_l2_ctrl_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_param (_coupler_to_l2_ctrl_auto_tl_in_d_bits_param), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_size (_coupler_to_l2_ctrl_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_source (_coupler_to_l2_ctrl_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_sink (_coupler_to_l2_ctrl_auto_tl_in_d_bits_sink), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_denied (_coupler_to_l2_ctrl_auto_tl_in_d_bits_denied), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_data (_coupler_to_l2_ctrl_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_1_d_bits_corrupt (_coupler_to_l2_ctrl_auto_tl_in_d_bits_corrupt), // @[LazyScope.scala:98:27] .auto_anon_out_0_a_ready (_wrapped_error_device_auto_buffer_in_a_ready), // @[LazyScope.scala:98:27] .auto_anon_out_0_a_valid (_out_xbar_auto_anon_out_0_a_valid), .auto_anon_out_0_a_bits_opcode (_out_xbar_auto_anon_out_0_a_bits_opcode), .auto_anon_out_0_a_bits_param (_out_xbar_auto_anon_out_0_a_bits_param), .auto_anon_out_0_a_bits_size (_out_xbar_auto_anon_out_0_a_bits_size), .auto_anon_out_0_a_bits_source (_out_xbar_auto_anon_out_0_a_bits_source), .auto_anon_out_0_a_bits_address (_out_xbar_auto_anon_out_0_a_bits_address), .auto_anon_out_0_a_bits_mask (_out_xbar_auto_anon_out_0_a_bits_mask), .auto_anon_out_0_a_bits_data (_out_xbar_auto_anon_out_0_a_bits_data), .auto_anon_out_0_a_bits_corrupt (_out_xbar_auto_anon_out_0_a_bits_corrupt), .auto_anon_out_0_d_ready (_out_xbar_auto_anon_out_0_d_ready), .auto_anon_out_0_d_valid (_wrapped_error_device_auto_buffer_in_d_valid), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_opcode (_wrapped_error_device_auto_buffer_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_param (_wrapped_error_device_auto_buffer_in_d_bits_param), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_size (_wrapped_error_device_auto_buffer_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_source (_wrapped_error_device_auto_buffer_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_sink (_wrapped_error_device_auto_buffer_in_d_bits_sink), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_denied (_wrapped_error_device_auto_buffer_in_d_bits_denied), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_data (_wrapped_error_device_auto_buffer_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_anon_out_0_d_bits_corrupt (_wrapped_error_device_auto_buffer_in_d_bits_corrupt) // @[LazyScope.scala:98:27] ); // @[PeripheryBus.scala:57:30] TLBuffer_a29d64s7k1z4u buffer ( // @[Buffer.scala:75:28] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (_buffer_auto_in_a_ready), .auto_in_a_valid (_atomics_auto_out_a_valid), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_opcode (_atomics_auto_out_a_bits_opcode), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_param (_atomics_auto_out_a_bits_param), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_size (_atomics_auto_out_a_bits_size), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_source (_atomics_auto_out_a_bits_source), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_address (_atomics_auto_out_a_bits_address), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_mask (_atomics_auto_out_a_bits_mask), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_data (_atomics_auto_out_a_bits_data), // @[AtomicAutomata.scala:289:29] .auto_in_a_bits_corrupt (_atomics_auto_out_a_bits_corrupt), // @[AtomicAutomata.scala:289:29] .auto_in_d_ready (_atomics_auto_out_d_ready), // @[AtomicAutomata.scala:289:29] .auto_in_d_valid (_buffer_auto_in_d_valid), .auto_in_d_bits_opcode (_buffer_auto_in_d_bits_opcode), .auto_in_d_bits_param (_buffer_auto_in_d_bits_param), .auto_in_d_bits_size (_buffer_auto_in_d_bits_size), .auto_in_d_bits_source (_buffer_auto_in_d_bits_source), .auto_in_d_bits_sink (_buffer_auto_in_d_bits_sink), .auto_in_d_bits_denied (_buffer_auto_in_d_bits_denied), .auto_in_d_bits_data (_buffer_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt), .auto_out_a_ready (_fixer_auto_anon_in_a_ready), // @[PeripheryBus.scala:54:33] .auto_out_a_valid (_buffer_auto_out_a_valid), .auto_out_a_bits_opcode (_buffer_auto_out_a_bits_opcode), .auto_out_a_bits_param (_buffer_auto_out_a_bits_param), .auto_out_a_bits_size (_buffer_auto_out_a_bits_size), .auto_out_a_bits_source (_buffer_auto_out_a_bits_source), .auto_out_a_bits_address (_buffer_auto_out_a_bits_address), .auto_out_a_bits_mask (_buffer_auto_out_a_bits_mask), .auto_out_a_bits_data (_buffer_auto_out_a_bits_data), .auto_out_a_bits_corrupt (_buffer_auto_out_a_bits_corrupt), .auto_out_d_ready (_buffer_auto_out_d_ready), .auto_out_d_valid (_fixer_auto_anon_in_d_valid), // @[PeripheryBus.scala:54:33] .auto_out_d_bits_opcode (_fixer_auto_anon_in_d_bits_opcode), // @[PeripheryBus.scala:54:33] .auto_out_d_bits_param (_fixer_auto_anon_in_d_bits_param), // @[PeripheryBus.scala:54:33] .auto_out_d_bits_size (_fixer_auto_anon_in_d_bits_size), // @[PeripheryBus.scala:54:33] .auto_out_d_bits_source (_fixer_auto_anon_in_d_bits_source), // @[PeripheryBus.scala:54:33] .auto_out_d_bits_sink (_fixer_auto_anon_in_d_bits_sink), // @[PeripheryBus.scala:54:33] .auto_out_d_bits_denied (_fixer_auto_anon_in_d_bits_denied), // @[PeripheryBus.scala:54:33] .auto_out_d_bits_data (_fixer_auto_anon_in_d_bits_data), // @[PeripheryBus.scala:54:33] .auto_out_d_bits_corrupt (_fixer_auto_anon_in_d_bits_corrupt) // @[PeripheryBus.scala:54:33] ); // @[Buffer.scala:75:28] TLAtomicAutomata_cbus atomics ( // @[AtomicAutomata.scala:289:29] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_in_a_ready (_atomics_auto_in_a_ready), .auto_in_a_valid (_in_xbar_auto_anon_out_a_valid), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_opcode (_in_xbar_auto_anon_out_a_bits_opcode), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_param (_in_xbar_auto_anon_out_a_bits_param), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_size (_in_xbar_auto_anon_out_a_bits_size), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_source (_in_xbar_auto_anon_out_a_bits_source), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_address (_in_xbar_auto_anon_out_a_bits_address), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_mask (_in_xbar_auto_anon_out_a_bits_mask), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_data (_in_xbar_auto_anon_out_a_bits_data), // @[PeripheryBus.scala:56:29] .auto_in_a_bits_corrupt (_in_xbar_auto_anon_out_a_bits_corrupt), // @[PeripheryBus.scala:56:29] .auto_in_d_ready (_in_xbar_auto_anon_out_d_ready), // @[PeripheryBus.scala:56:29] .auto_in_d_valid (_atomics_auto_in_d_valid), .auto_in_d_bits_opcode (_atomics_auto_in_d_bits_opcode), .auto_in_d_bits_param (_atomics_auto_in_d_bits_param), .auto_in_d_bits_size (_atomics_auto_in_d_bits_size), .auto_in_d_bits_source (_atomics_auto_in_d_bits_source), .auto_in_d_bits_sink (_atomics_auto_in_d_bits_sink), .auto_in_d_bits_denied (_atomics_auto_in_d_bits_denied), .auto_in_d_bits_data (_atomics_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_atomics_auto_in_d_bits_corrupt), .auto_out_a_ready (_buffer_auto_in_a_ready), // @[Buffer.scala:75:28] .auto_out_a_valid (_atomics_auto_out_a_valid), .auto_out_a_bits_opcode (_atomics_auto_out_a_bits_opcode), .auto_out_a_bits_param (_atomics_auto_out_a_bits_param), .auto_out_a_bits_size (_atomics_auto_out_a_bits_size), .auto_out_a_bits_source (_atomics_auto_out_a_bits_source), .auto_out_a_bits_address (_atomics_auto_out_a_bits_address), .auto_out_a_bits_mask (_atomics_auto_out_a_bits_mask), .auto_out_a_bits_data (_atomics_auto_out_a_bits_data), .auto_out_a_bits_corrupt (_atomics_auto_out_a_bits_corrupt), .auto_out_d_ready (_atomics_auto_out_d_ready), .auto_out_d_valid (_buffer_auto_in_d_valid), // @[Buffer.scala:75:28] .auto_out_d_bits_opcode (_buffer_auto_in_d_bits_opcode), // @[Buffer.scala:75:28] .auto_out_d_bits_param (_buffer_auto_in_d_bits_param), // @[Buffer.scala:75:28] .auto_out_d_bits_size (_buffer_auto_in_d_bits_size), // @[Buffer.scala:75:28] .auto_out_d_bits_source (_buffer_auto_in_d_bits_source), // @[Buffer.scala:75:28] .auto_out_d_bits_sink (_buffer_auto_in_d_bits_sink), // @[Buffer.scala:75:28] .auto_out_d_bits_denied (_buffer_auto_in_d_bits_denied), // @[Buffer.scala:75:28] .auto_out_d_bits_data (_buffer_auto_in_d_bits_data), // @[Buffer.scala:75:28] .auto_out_d_bits_corrupt (_buffer_auto_in_d_bits_corrupt) // @[Buffer.scala:75:28] ); // @[AtomicAutomata.scala:289:29] ErrorDeviceWrapper wrapped_error_device ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_buffer_in_a_ready (_wrapped_error_device_auto_buffer_in_a_ready), .auto_buffer_in_a_valid (_out_xbar_auto_anon_out_0_a_valid), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_opcode (_out_xbar_auto_anon_out_0_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_param (_out_xbar_auto_anon_out_0_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_size (_out_xbar_auto_anon_out_0_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_source (_out_xbar_auto_anon_out_0_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_address (_out_xbar_auto_anon_out_0_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_mask (_out_xbar_auto_anon_out_0_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_data (_out_xbar_auto_anon_out_0_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_buffer_in_a_bits_corrupt (_out_xbar_auto_anon_out_0_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_buffer_in_d_ready (_out_xbar_auto_anon_out_0_d_ready), // @[PeripheryBus.scala:57:30] .auto_buffer_in_d_valid (_wrapped_error_device_auto_buffer_in_d_valid), .auto_buffer_in_d_bits_opcode (_wrapped_error_device_auto_buffer_in_d_bits_opcode), .auto_buffer_in_d_bits_param (_wrapped_error_device_auto_buffer_in_d_bits_param), .auto_buffer_in_d_bits_size (_wrapped_error_device_auto_buffer_in_d_bits_size), .auto_buffer_in_d_bits_source (_wrapped_error_device_auto_buffer_in_d_bits_source), .auto_buffer_in_d_bits_sink (_wrapped_error_device_auto_buffer_in_d_bits_sink), .auto_buffer_in_d_bits_denied (_wrapped_error_device_auto_buffer_in_d_bits_denied), .auto_buffer_in_d_bits_data (_wrapped_error_device_auto_buffer_in_d_bits_data), .auto_buffer_in_d_bits_corrupt (_wrapped_error_device_auto_buffer_in_d_bits_corrupt) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_cbus_to_l2_ctrl coupler_to_l2_ctrl ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_buffer_out_a_ready (auto_coupler_to_l2_ctrl_buffer_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_a_valid (auto_coupler_to_l2_ctrl_buffer_out_a_valid_0), .auto_buffer_out_a_bits_opcode (auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode_0), .auto_buffer_out_a_bits_param (auto_coupler_to_l2_ctrl_buffer_out_a_bits_param_0), .auto_buffer_out_a_bits_size (auto_coupler_to_l2_ctrl_buffer_out_a_bits_size_0), .auto_buffer_out_a_bits_source (auto_coupler_to_l2_ctrl_buffer_out_a_bits_source_0), .auto_buffer_out_a_bits_address (auto_coupler_to_l2_ctrl_buffer_out_a_bits_address_0), .auto_buffer_out_a_bits_mask (auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask_0), .auto_buffer_out_a_bits_data (auto_coupler_to_l2_ctrl_buffer_out_a_bits_data_0), .auto_buffer_out_a_bits_corrupt (auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt_0), .auto_buffer_out_d_ready (auto_coupler_to_l2_ctrl_buffer_out_d_ready_0), .auto_buffer_out_d_valid (auto_coupler_to_l2_ctrl_buffer_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_opcode (auto_coupler_to_l2_ctrl_buffer_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_size (auto_coupler_to_l2_ctrl_buffer_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_source (auto_coupler_to_l2_ctrl_buffer_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_buffer_out_d_bits_data (auto_coupler_to_l2_ctrl_buffer_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_l2_ctrl_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_1_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_1_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_1_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_1_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_1_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_1_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_1_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_1_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_1_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_1_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_l2_ctrl_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_l2_ctrl_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_param (_coupler_to_l2_ctrl_auto_tl_in_d_bits_param), .auto_tl_in_d_bits_size (_coupler_to_l2_ctrl_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_l2_ctrl_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_sink (_coupler_to_l2_ctrl_auto_tl_in_d_bits_sink), .auto_tl_in_d_bits_denied (_coupler_to_l2_ctrl_auto_tl_in_d_bits_denied), .auto_tl_in_d_bits_data (_coupler_to_l2_ctrl_auto_tl_in_d_bits_data), .auto_tl_in_d_bits_corrupt (_coupler_to_l2_ctrl_auto_tl_in_d_bits_corrupt) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_cbus_to_clint coupler_to_clint ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_fragmenter_anon_out_a_ready (auto_coupler_to_clint_fragmenter_anon_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_a_valid (auto_coupler_to_clint_fragmenter_anon_out_a_valid_0), .auto_fragmenter_anon_out_a_bits_opcode (auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode_0), .auto_fragmenter_anon_out_a_bits_param (auto_coupler_to_clint_fragmenter_anon_out_a_bits_param_0), .auto_fragmenter_anon_out_a_bits_size (auto_coupler_to_clint_fragmenter_anon_out_a_bits_size_0), .auto_fragmenter_anon_out_a_bits_source (auto_coupler_to_clint_fragmenter_anon_out_a_bits_source_0), .auto_fragmenter_anon_out_a_bits_address (auto_coupler_to_clint_fragmenter_anon_out_a_bits_address_0), .auto_fragmenter_anon_out_a_bits_mask (auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask_0), .auto_fragmenter_anon_out_a_bits_data (auto_coupler_to_clint_fragmenter_anon_out_a_bits_data_0), .auto_fragmenter_anon_out_a_bits_corrupt (auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt_0), .auto_fragmenter_anon_out_d_ready (auto_coupler_to_clint_fragmenter_anon_out_d_ready_0), .auto_fragmenter_anon_out_d_valid (auto_coupler_to_clint_fragmenter_anon_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_opcode (auto_coupler_to_clint_fragmenter_anon_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_size (auto_coupler_to_clint_fragmenter_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_source (auto_coupler_to_clint_fragmenter_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_data (auto_coupler_to_clint_fragmenter_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_clint_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_3_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_3_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_3_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_3_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_3_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_3_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_3_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_3_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_3_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_3_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_clint_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_clint_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_clint_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_clint_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_data (_coupler_to_clint_auto_tl_in_d_bits_data) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_cbus_to_plic coupler_to_plic ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_fragmenter_anon_out_a_ready (auto_coupler_to_plic_fragmenter_anon_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_a_valid (auto_coupler_to_plic_fragmenter_anon_out_a_valid_0), .auto_fragmenter_anon_out_a_bits_opcode (auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode_0), .auto_fragmenter_anon_out_a_bits_param (auto_coupler_to_plic_fragmenter_anon_out_a_bits_param_0), .auto_fragmenter_anon_out_a_bits_size (auto_coupler_to_plic_fragmenter_anon_out_a_bits_size_0), .auto_fragmenter_anon_out_a_bits_source (auto_coupler_to_plic_fragmenter_anon_out_a_bits_source_0), .auto_fragmenter_anon_out_a_bits_address (auto_coupler_to_plic_fragmenter_anon_out_a_bits_address_0), .auto_fragmenter_anon_out_a_bits_mask (auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask_0), .auto_fragmenter_anon_out_a_bits_data (auto_coupler_to_plic_fragmenter_anon_out_a_bits_data_0), .auto_fragmenter_anon_out_a_bits_corrupt (auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt_0), .auto_fragmenter_anon_out_d_ready (auto_coupler_to_plic_fragmenter_anon_out_d_ready_0), .auto_fragmenter_anon_out_d_valid (auto_coupler_to_plic_fragmenter_anon_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_opcode (auto_coupler_to_plic_fragmenter_anon_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_size (auto_coupler_to_plic_fragmenter_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_source (auto_coupler_to_plic_fragmenter_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_data (auto_coupler_to_plic_fragmenter_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_plic_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_4_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_4_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_4_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_4_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_4_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_4_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_4_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_4_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_4_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_4_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_plic_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_plic_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_plic_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_plic_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_data (_coupler_to_plic_auto_tl_in_d_bits_data) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_cbus_to_debug coupler_to_debug ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_fragmenter_anon_out_a_ready (auto_coupler_to_debug_fragmenter_anon_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_a_valid (auto_coupler_to_debug_fragmenter_anon_out_a_valid_0), .auto_fragmenter_anon_out_a_bits_opcode (auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode_0), .auto_fragmenter_anon_out_a_bits_param (auto_coupler_to_debug_fragmenter_anon_out_a_bits_param_0), .auto_fragmenter_anon_out_a_bits_size (auto_coupler_to_debug_fragmenter_anon_out_a_bits_size_0), .auto_fragmenter_anon_out_a_bits_source (auto_coupler_to_debug_fragmenter_anon_out_a_bits_source_0), .auto_fragmenter_anon_out_a_bits_address (auto_coupler_to_debug_fragmenter_anon_out_a_bits_address_0), .auto_fragmenter_anon_out_a_bits_mask (auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask_0), .auto_fragmenter_anon_out_a_bits_data (auto_coupler_to_debug_fragmenter_anon_out_a_bits_data_0), .auto_fragmenter_anon_out_a_bits_corrupt (auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt_0), .auto_fragmenter_anon_out_d_ready (auto_coupler_to_debug_fragmenter_anon_out_d_ready_0), .auto_fragmenter_anon_out_d_valid (auto_coupler_to_debug_fragmenter_anon_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_opcode (auto_coupler_to_debug_fragmenter_anon_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_size (auto_coupler_to_debug_fragmenter_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_source (auto_coupler_to_debug_fragmenter_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_data (auto_coupler_to_debug_fragmenter_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_debug_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_5_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_5_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_5_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_5_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_5_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_5_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_5_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_5_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_5_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_5_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_debug_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_debug_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_debug_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_debug_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_data (_coupler_to_debug_auto_tl_in_d_bits_data) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_cbus_to_bootrom coupler_to_bootrom ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_fragmenter_anon_out_a_ready (auto_coupler_to_bootrom_fragmenter_anon_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_a_valid (auto_coupler_to_bootrom_fragmenter_anon_out_a_valid_0), .auto_fragmenter_anon_out_a_bits_opcode (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode_0), .auto_fragmenter_anon_out_a_bits_param (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param_0), .auto_fragmenter_anon_out_a_bits_size (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size_0), .auto_fragmenter_anon_out_a_bits_source (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source_0), .auto_fragmenter_anon_out_a_bits_address (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address_0), .auto_fragmenter_anon_out_a_bits_mask (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask_0), .auto_fragmenter_anon_out_a_bits_data (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data_0), .auto_fragmenter_anon_out_a_bits_corrupt (auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt_0), .auto_fragmenter_anon_out_d_ready (auto_coupler_to_bootrom_fragmenter_anon_out_d_ready_0), .auto_fragmenter_anon_out_d_valid (auto_coupler_to_bootrom_fragmenter_anon_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_size (auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_source (auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_fragmenter_anon_out_d_bits_data (auto_coupler_to_bootrom_fragmenter_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_bootrom_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_6_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_6_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_6_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_6_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_6_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_6_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_6_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_6_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_6_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_6_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_bootrom_auto_tl_in_d_valid), .auto_tl_in_d_bits_size (_coupler_to_bootrom_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_bootrom_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_data (_coupler_to_bootrom_auto_tl_in_d_bits_data) ); // @[LazyScope.scala:98:27] TLInterconnectCoupler_cbus_to_prci_ctrl coupler_to_prci_ctrl ( // @[LazyScope.scala:98:27] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_fixer_anon_out_a_ready (auto_coupler_to_prci_ctrl_fixer_anon_out_a_ready_0), // @[ClockDomain.scala:14:9] .auto_fixer_anon_out_a_valid (auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid_0), .auto_fixer_anon_out_a_bits_opcode (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode_0), .auto_fixer_anon_out_a_bits_param (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param_0), .auto_fixer_anon_out_a_bits_size (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size_0), .auto_fixer_anon_out_a_bits_source (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source_0), .auto_fixer_anon_out_a_bits_address (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address_0), .auto_fixer_anon_out_a_bits_mask (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask_0), .auto_fixer_anon_out_a_bits_data (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data_0), .auto_fixer_anon_out_a_bits_corrupt (auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt_0), .auto_fixer_anon_out_d_ready (auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready_0), .auto_fixer_anon_out_d_valid (auto_coupler_to_prci_ctrl_fixer_anon_out_d_valid_0), // @[ClockDomain.scala:14:9] .auto_fixer_anon_out_d_bits_opcode (auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_fixer_anon_out_d_bits_size (auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_size_0), // @[ClockDomain.scala:14:9] .auto_fixer_anon_out_d_bits_source (auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_source_0), // @[ClockDomain.scala:14:9] .auto_fixer_anon_out_d_bits_data (auto_coupler_to_prci_ctrl_fixer_anon_out_d_bits_data_0), // @[ClockDomain.scala:14:9] .auto_tl_in_a_ready (_coupler_to_prci_ctrl_auto_tl_in_a_ready), .auto_tl_in_a_valid (_out_xbar_auto_anon_out_7_a_valid), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_opcode (_out_xbar_auto_anon_out_7_a_bits_opcode), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_param (_out_xbar_auto_anon_out_7_a_bits_param), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_size (_out_xbar_auto_anon_out_7_a_bits_size), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_source (_out_xbar_auto_anon_out_7_a_bits_source), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_address (_out_xbar_auto_anon_out_7_a_bits_address), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_mask (_out_xbar_auto_anon_out_7_a_bits_mask), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_data (_out_xbar_auto_anon_out_7_a_bits_data), // @[PeripheryBus.scala:57:30] .auto_tl_in_a_bits_corrupt (_out_xbar_auto_anon_out_7_a_bits_corrupt), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_ready (_out_xbar_auto_anon_out_7_d_ready), // @[PeripheryBus.scala:57:30] .auto_tl_in_d_valid (_coupler_to_prci_ctrl_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_prci_ctrl_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_param (_coupler_to_prci_ctrl_auto_tl_in_d_bits_param), .auto_tl_in_d_bits_size (_coupler_to_prci_ctrl_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_prci_ctrl_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_sink (_coupler_to_prci_ctrl_auto_tl_in_d_bits_sink), .auto_tl_in_d_bits_denied (_coupler_to_prci_ctrl_auto_tl_in_d_bits_denied), .auto_tl_in_d_bits_data (_coupler_to_prci_ctrl_auto_tl_in_d_bits_data), .auto_tl_in_d_bits_corrupt (_coupler_to_prci_ctrl_auto_tl_in_d_bits_corrupt) ); // @[LazyScope.scala:98:27] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid = auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt = auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready = auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_valid = auto_coupler_to_bootrom_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt = auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bootrom_fragmenter_anon_out_d_ready = auto_coupler_to_bootrom_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_valid = auto_coupler_to_debug_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode = auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_param = auto_coupler_to_debug_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_size = auto_coupler_to_debug_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_source = auto_coupler_to_debug_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_address = auto_coupler_to_debug_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask = auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_data = auto_coupler_to_debug_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt = auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_debug_fragmenter_anon_out_d_ready = auto_coupler_to_debug_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_valid = auto_coupler_to_plic_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode = auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_param = auto_coupler_to_plic_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_size = auto_coupler_to_plic_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_source = auto_coupler_to_plic_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_address = auto_coupler_to_plic_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask = auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_data = auto_coupler_to_plic_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt = auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_plic_fragmenter_anon_out_d_ready = auto_coupler_to_plic_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_valid = auto_coupler_to_clint_fragmenter_anon_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode = auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_param = auto_coupler_to_clint_fragmenter_anon_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_size = auto_coupler_to_clint_fragmenter_anon_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_source = auto_coupler_to_clint_fragmenter_anon_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_address = auto_coupler_to_clint_fragmenter_anon_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask = auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_data = auto_coupler_to_clint_fragmenter_anon_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt = auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_clint_fragmenter_anon_out_d_ready = auto_coupler_to_clint_fragmenter_anon_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid = auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt = auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready = auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_valid = auto_coupler_to_l2_ctrl_buffer_out_a_valid_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode = auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_param = auto_coupler_to_l2_ctrl_buffer_out_a_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_size = auto_coupler_to_l2_ctrl_buffer_out_a_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_source = auto_coupler_to_l2_ctrl_buffer_out_a_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_address = auto_coupler_to_l2_ctrl_buffer_out_a_bits_address_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask = auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_data = auto_coupler_to_l2_ctrl_buffer_out_a_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt = auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt_0; // @[ClockDomain.scala:14:9] assign auto_coupler_to_l2_ctrl_buffer_out_d_ready = auto_coupler_to_l2_ctrl_buffer_out_d_ready_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_5_clock = auto_fixedClockNode_anon_out_5_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_5_reset = auto_fixedClockNode_anon_out_5_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_4_clock = auto_fixedClockNode_anon_out_4_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_4_reset = auto_fixedClockNode_anon_out_4_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_3_clock = auto_fixedClockNode_anon_out_3_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_3_reset = auto_fixedClockNode_anon_out_3_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_2_clock = auto_fixedClockNode_anon_out_2_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_2_reset = auto_fixedClockNode_anon_out_2_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_1_clock = auto_fixedClockNode_anon_out_1_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_1_reset = auto_fixedClockNode_anon_out_1_reset_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_0_clock = auto_fixedClockNode_anon_out_0_clock_0; // @[ClockDomain.scala:14:9] assign auto_fixedClockNode_anon_out_0_reset = auto_fixedClockNode_anon_out_0_reset_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_a_ready = auto_bus_xing_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_valid = auto_bus_xing_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_opcode = auto_bus_xing_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_param = auto_bus_xing_in_d_bits_param_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_size = auto_bus_xing_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_source = auto_bus_xing_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_sink = auto_bus_xing_in_d_bits_sink_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_denied = auto_bus_xing_in_d_bits_denied_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_data = auto_bus_xing_in_d_bits_data_0; // @[ClockDomain.scala:14:9] assign auto_bus_xing_in_d_bits_corrupt = auto_bus_xing_in_d_bits_corrupt_0; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File EgressUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} class EgressUnit(coupleSAVA: Boolean, combineSAST: Boolean, inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: EgressChannelParams) (implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) { class EgressUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) { val out = Decoupled(new EgressFlit(cParam.payloadBits)) } val io = IO(new EgressUnitIO) val channel_empty = RegInit(true.B) val flow = Reg(new FlowRoutingBundle) val q = Module(new Queue(new EgressFlit(cParam.payloadBits), 3 - (if (combineSAST) 1 else 0), flow=true)) q.io.enq.valid := io.in(0).valid q.io.enq.bits.head := io.in(0).bits.head q.io.enq.bits.tail := io.in(0).bits.tail val flows = cParam.possibleFlows.toSeq if (flows.size == 0) { q.io.enq.bits.ingress_id := 0.U(1.W) } else { q.io.enq.bits.ingress_id := Mux1H( flows.map(f => (f.ingressNode.U === io.in(0).bits.flow.ingress_node && f.ingressNodeId.U === io.in(0).bits.flow.ingress_node_id)), flows.map(f => f.ingressId.U(ingressIdBits.W)) ) } q.io.enq.bits.payload := io.in(0).bits.payload io.out <> q.io.deq assert(!(q.io.enq.valid && !q.io.enq.ready)) io.credit_available(0) := q.io.count === 0.U io.channel_status(0).occupied := !channel_empty io.channel_status(0).flow := flow when (io.credit_alloc(0).alloc && io.credit_alloc(0).tail) { channel_empty := true.B if (coupleSAVA) io.channel_status(0).occupied := false.B } when (io.allocs(0).alloc) { channel_empty := false.B flow := io.allocs(0).flow } }	module EgressUnit_14( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [144:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14] input [2:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] input io_out_ready, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [144:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30] wire _q_io_enq_bits_ingress_id_T_37 = io_in_0_bits_flow_ingress_node_id == 3'h0; // @[EgressUnit.scala:32:27]
Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 \|\| cParam.destSpeedup > 1 \|\| fullSize <= 1) \|\| !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_\|\|_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) \| (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_\|\|_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow \|\| routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }	module mem_20x75( // @[InputUnit.scala:85:18] input [4:0] R0_addr, input R0_en, input R0_clk, output [74:0] R0_data, input [4:0] R1_addr, input R1_en, input R1_clk, output [74:0] R1_data, input [4:0] R2_addr, input R2_en, input R2_clk, output [74:0] R2_data, input [4:0] R3_addr, input R3_en, input R3_clk, output [74:0] R3_data, input [4:0] R4_addr, input R4_en, input R4_clk, output [74:0] R4_data, input [4:0] R5_addr, input R5_en, input R5_clk, output [74:0] R5_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [74:0] W0_data ); reg [74:0] Memory[0:19]; // @[InputUnit.scala:85:18] always @(posedge W0_clk) begin // @[InputUnit.scala:85:18] if (W0_en & 1'h1) // @[InputUnit.scala:85:18] Memory[W0_addr] <= W0_data; // @[InputUnit.scala:85:18] always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File AtomicAutomata.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes} import freechips.rocketchip.util.leftOR import scala.math.{min,max} // Ensures that all downstream RW managers support Atomic operations. // If !passthrough, intercept all Atomics. Otherwise, only intercept those unsupported downstream. class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(implicit p: Parameters) extends LazyModule { require (concurrency >= 1) val node = TLAdapterNode( managerFn = { case mp => mp.v1copy(managers = mp.managers.map { m => val ourSupport = TransferSizes(1, mp.beatBytes) def widen(x: TransferSizes) = if (passthrough && x.min <= 2mp.beatBytes) TransferSizes(1, max(mp.beatBytes, x.max)) else ourSupport val canDoit = m.supportsPutFull.contains(ourSupport) && m.supportsGet.contains(ourSupport) // Blow up if there are devices to which we cannot add Atomics, because their R\|W are too inflexible require (!m.supportsPutFull \|\| !m.supportsGet \|\| canDoit, s"${m.name} has $ourSupport, needed PutFull(${m.supportsPutFull}) or Get(${m.supportsGet})") m.v1copy( supportsArithmetic = if (!arithmetic \|\| !canDoit) m.supportsArithmetic else widen(m.supportsArithmetic), supportsLogical = if (!logical \|\| !canDoit) m.supportsLogical else widen(m.supportsLogical), mayDenyGet = m.mayDenyGet \|\| m.mayDenyPut) })}) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val managers = edgeOut.manager.managers val beatBytes = edgeOut.manager.beatBytes // To which managers are we adding atomic support? val ourSupport = TransferSizes(1, beatBytes) val managersNeedingHelp = managers.filter { m => m.supportsPutFull.contains(ourSupport) && m.supportsGet.contains(ourSupport) && ((logical && !m.supportsLogical .contains(ourSupport)) \|\| (arithmetic && !m.supportsArithmetic.contains(ourSupport)) \|\| !passthrough) // we will do atomics for everyone we can } // Managers that need help with atomics must necessarily have this node as the root of a tree in the node graph. // (But they must also ensure no sideband operations can get between the read and write.) val violations = managersNeedingHelp.flatMap(_.findTreeViolation()).map { node => (node.name, node.inputs.map(_._1.name)) } require(violations.isEmpty, s"AtomicAutomata can only help nodes for which it is at the root of a diplomatic node tree," + "but the following violations were found:\n" + violations.map(v => s"(${v._1} has parents ${v._2})").mkString("\n")) // We cannot add atomics to a non-FIFO manager managersNeedingHelp foreach { m => require (m.fifoId.isDefined) } // We need to preserve FIFO semantics across FIFO domains, not managers // Suppose you have Put(42) Atomic(+1) both inflight; valid results: 42 or 43 // If we allow Put(42) Get() Put(+1) concurrent; valid results: 42 43 OR undef // Making non-FIFO work requires waiting for all Acks to come back (=> use FIFOFixer) val domainsNeedingHelp = managersNeedingHelp.map(_.fifoId.get).distinct // Don't overprovision the CAM val camSize = min(domainsNeedingHelp.size, concurrency) // Compact the fifoIds to only those we care about def camFifoId(m: TLSlaveParameters) = m.fifoId.map(id => max(0, domainsNeedingHelp.indexOf(id))).getOrElse(0) // CAM entry state machine val FREE = 0.U // unused waiting on Atomic from A val GET = 3.U // Get sent down A waiting on AccessDataAck from D val AMO = 2.U // AccessDataAck sent up D waiting for A availability val ACK = 1.U // Put sent down A waiting for PutAck from D val params = TLAtomicAutomata.CAMParams(out.a.bits.params, domainsNeedingHelp.size) // Do we need to do anything at all? if (camSize > 0) { val initval = Wire(new TLAtomicAutomata.CAM_S(params)) initval.state := FREE val cam_s = RegInit(VecInit.fill(camSize)(initval)) val cam_a = Reg(Vec(camSize, new TLAtomicAutomata.CAM_A(params))) val cam_d = Reg(Vec(camSize, new TLAtomicAutomata.CAM_D(params))) val cam_free = cam_s.map(_.state === FREE) val cam_amo = cam_s.map(_.state === AMO) val cam_abusy = cam_s.map(e => e.state === GET \|\| e.state === AMO) // A is blocked val cam_dmatch = cam_s.map(e => e.state =/= FREE) // D should inspect these entries // Can the manager already handle this message? val a_address = edgeIn.address(in.a.bits) val a_size = edgeIn.size(in.a.bits) val a_canLogical = passthrough.B && edgeOut.manager.supportsLogicalFast (a_address, a_size) val a_canArithmetic = passthrough.B && edgeOut.manager.supportsArithmeticFast(a_address, a_size) val a_isLogical = in.a.bits.opcode === TLMessages.LogicalData val a_isArithmetic = in.a.bits.opcode === TLMessages.ArithmeticData val a_isSupported = Mux(a_isLogical, a_canLogical, Mux(a_isArithmetic, a_canArithmetic, true.B)) // Must we do a Put? val a_cam_any_put = cam_amo.reduce(_ \|\| _) val a_cam_por_put = cam_amo.scanLeft(false.B)(_\|\|_).init val a_cam_sel_put = (cam_amo zip a_cam_por_put) map { case (a, b) => a && !b } val a_cam_a = PriorityMux(cam_amo, cam_a) val a_cam_d = PriorityMux(cam_amo, cam_d) val a_a = a_cam_a.bits.data val a_d = a_cam_d.data // Does the A request conflict with an inflight AMO? val a_fifoId = edgeOut.manager.fastProperty(a_address, camFifoId _, (i:Int) => i.U) val a_cam_busy = (cam_abusy zip cam_a.map(_.fifoId === a_fifoId)) map { case (a,b) => a&&b } reduce (_\|\|_) // (Where) are we are allocating in the CAM? val a_cam_any_free = cam_free.reduce(_ \|\| _) val a_cam_por_free = cam_free.scanLeft(false.B)(_\|\|_).init val a_cam_sel_free = (cam_free zip a_cam_por_free) map { case (a,b) => a && !b } // Logical AMO val indexes = Seq.tabulate(beatBytes8) { i => Cat(a_a(i,i), a_d(i,i)) } val logic_out = Cat(indexes.map(x => a_cam_a.lut(x).asUInt).reverse) // Arithmetic AMO val unsigned = a_cam_a.bits.param(1) val take_max = a_cam_a.bits.param(0) val adder = a_cam_a.bits.param(2) val mask = a_cam_a.bits.mask val signSel = ~(~mask \| (mask >> 1)) val signbits_a = Cat(Seq.tabulate(beatBytes) { i => a_a(8i+7,8i+7) } .reverse) val signbits_d = Cat(Seq.tabulate(beatBytes) { i => a_d(8i+7,8i+7) } .reverse) // Move the selected sign bit into the first byte position it will extend val signbit_a = ((signbits_a & signSel) << 1)(beatBytes-1, 0) val signbit_d = ((signbits_d & signSel) << 1)(beatBytes-1, 0) val signext_a = FillInterleaved(8, leftOR(signbit_a)) val signext_d = FillInterleaved(8, leftOR(signbit_d)) // NOTE: sign-extension does not change the relative ordering in EITHER unsigned or signed arithmetic val wide_mask = FillInterleaved(8, mask) val a_a_ext = (a_a & wide_mask) \| signext_a val a_d_ext = (a_d & wide_mask) \| signext_d val a_d_inv = Mux(adder, a_d_ext, ~a_d_ext) val adder_out = a_a_ext + a_d_inv val h = 8beatBytes-1 // now sign-extended; use biggest bit val a_bigger_uneq = unsigned === a_a_ext(h) // result if high bits are unequal val a_bigger = Mux(a_a_ext(h) === a_d_ext(h), !adder_out(h), a_bigger_uneq) val pick_a = take_max === a_bigger val arith_out = Mux(adder, adder_out, Mux(pick_a, a_a, a_d)) // AMO result data val amo_data = if (!logical) arith_out else if (!arithmetic) logic_out else Mux(a_cam_a.bits.opcode(0), logic_out, arith_out) // Potentially mutate the message from inner val source_i = Wire(chiselTypeOf(in.a)) val a_allow = !a_cam_busy && (a_isSupported \|\| a_cam_any_free) in.a.ready := source_i.ready && a_allow source_i.valid := in.a.valid && a_allow source_i.bits := in.a.bits when (!a_isSupported) { // minimal mux difference source_i.bits.opcode := TLMessages.Get source_i.bits.param := 0.U } // Potentially take the message from the CAM val source_c = Wire(chiselTypeOf(in.a)) source_c.valid := a_cam_any_put source_c.bits := edgeOut.Put( fromSource = a_cam_a.bits.source, toAddress = edgeIn.address(a_cam_a.bits), lgSize = a_cam_a.bits.size, data = amo_data, corrupt = a_cam_a.bits.corrupt \|\| a_cam_d.corrupt)._2 source_c.bits.user :<= a_cam_a.bits.user source_c.bits.echo :<= a_cam_a.bits.echo // Finishing an AMO from the CAM has highest priority TLArbiter(TLArbiter.lowestIndexFirst)(out.a, (0.U, source_c), (edgeOut.numBeats1(in.a.bits), source_i)) // Capture the A state into the CAM when (source_i.fire && !a_isSupported) { (a_cam_sel_free zip cam_a) foreach { case (en, r) => when (en) { r.fifoId := a_fifoId r.bits := in.a.bits r.lut := MuxLookup(in.a.bits.param(1, 0), 0.U(4.W))(Array( TLAtomics.AND -> 0x8.U, TLAtomics.OR -> 0xe.U, TLAtomics.XOR -> 0x6.U, TLAtomics.SWAP -> 0xc.U)) } } (a_cam_sel_free zip cam_s) foreach { case (en, r) => when (en) { r.state := GET } } } // Advance the put state when (source_c.fire) { (a_cam_sel_put zip cam_s) foreach { case (en, r) => when (en) { r.state := ACK } } } // We need to deal with a potential D response in the same cycle as the A request val d_first = edgeOut.first(out.d) val d_cam_sel_raw = cam_a.map(_.bits.source === in.d.bits.source) val d_cam_sel_match = (d_cam_sel_raw zip cam_dmatch) map { case (a,b) => a&&b } val d_cam_data = Mux1H(d_cam_sel_match, cam_d.map(_.data)) val d_cam_denied = Mux1H(d_cam_sel_match, cam_d.map(_.denied)) val d_cam_corrupt = Mux1H(d_cam_sel_match, cam_d.map(_.corrupt)) val d_cam_sel_bypass = if (edgeOut.manager.minLatency > 0) false.B else out.d.bits.source === in.a.bits.source && in.a.valid && !a_isSupported val d_cam_sel = (a_cam_sel_free zip d_cam_sel_match) map { case (a,d) => Mux(d_cam_sel_bypass, a, d) } val d_cam_sel_any = d_cam_sel_bypass \|\| d_cam_sel_match.reduce(_ \|\| _) val d_ackd = out.d.bits.opcode === TLMessages.AccessAckData val d_ack = out.d.bits.opcode === TLMessages.AccessAck when (out.d.fire && d_first) { (d_cam_sel zip cam_d) foreach { case (en, r) => when (en && d_ackd) { r.data := out.d.bits.data r.denied := out.d.bits.denied r.corrupt := out.d.bits.corrupt } } (d_cam_sel zip cam_s) foreach { case (en, r) => when (en) { // Note: it is important that this comes AFTER the := GET, so we can go FREE=>GET=>AMO in one cycle r.state := Mux(d_ackd, AMO, FREE) } } } val d_drop = d_first && d_ackd && d_cam_sel_any val d_replace = d_first && d_ack && d_cam_sel_match.reduce(_ \|\| _) in.d.valid := out.d.valid && !d_drop out.d.ready := in.d.ready \|\| d_drop in.d.bits := out.d.bits when (d_replace) { // minimal muxes in.d.bits.opcode := TLMessages.AccessAckData in.d.bits.data := d_cam_data in.d.bits.corrupt := d_cam_corrupt \|\| out.d.bits.denied in.d.bits.denied := d_cam_denied \|\| out.d.bits.denied } } else { out.a.valid := in.a.valid in.a.ready := out.a.ready out.a.bits := in.a.bits in.d.valid := out.d.valid out.d.ready := in.d.ready in.d.bits := out.d.bits } if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { in.b.valid := out.b.valid out.b.ready := in.b.ready in.b.bits := out.b.bits out.c.valid := in.c.valid in.c.ready := out.c.ready out.c.bits := in.c.bits out.e.valid := in.e.valid in.e.ready := out.e.ready out.e.bits := in.e.bits } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLAtomicAutomata { def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val atomics = LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough) { override lazy val desiredName = (Seq("TLAtomicAutomata") ++ nameSuffix).mkString("_") }) atomics.node } case class CAMParams(a: TLBundleParameters, domainsNeedingHelp: Int) class CAM_S(val params: CAMParams) extends Bundle { val state = UInt(2.W) } class CAM_A(val params: CAMParams) extends Bundle { val bits = new TLBundleA(params.a) val fifoId = UInt(log2Up(params.domainsNeedingHelp).W) val lut = UInt(4.W) } class CAM_D(val params: CAMParams) extends Bundle { val data = UInt(params.a.dataBits.W) val denied = Bool() val corrupt = Bool() } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMAtomicAutomata(txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("AtomicAutomata")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) // Confirm that the AtomicAutomata combines read + write errors import TLMessages._ val test = new RequestPattern({a: TLBundleA => val doesA = a.opcode === ArithmeticData \|\| a.opcode === LogicalData val doesR = a.opcode === Get \|\| doesA val doesW = a.opcode === PutFullData \|\| a.opcode === PutPartialData \|\| doesA (doesR && RequestPattern.overlaps(Seq(AddressSet(0x08, ~0x08)))(a)) \|\| (doesW && RequestPattern.overlaps(Seq(AddressSet(0x10, ~0x10)))(a)) }) (ram.node := TLErrorEvaluator(test) := TLFragmenter(4, 256) := TLDelayer(0.1) := TLAtomicAutomata() := TLDelayer(0.1) := TLErrorEvaluator(test, testOn=true, testOff=true) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMAtomicAutomataTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMAtomicAutomata(txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /** Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File Arbiter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ object TLArbiter { // (valids, select) => readys type Policy = (Integer, UInt, Bool) => UInt val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0) val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width)) val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else { val valid = valids(width-1, 0) assert (valid === valids) val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0)) val filter = Cat(valid & ~mask, valid) val unready = (rightOR(filter, width2, width) >> 1) \| (mask << width) val readys = ~((unready >> width) & unready(width-1, 0)) when (select && valid.orR) { mask := leftOR(readys & valid, width) } readys(width-1, 0) } def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = { apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_) } def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])): Unit = { if (sources.isEmpty) { sink.bits := DontCare } else if (sources.size == 1) { sink :<>= sources.head._2 } else { val pairs = sources.toList val beatsIn = pairs.map(_._1) val sourcesIn = pairs.map(_._2) // The number of beats which remain to be sent val beatsLeft = RegInit(0.U) val idle = beatsLeft === 0.U val latch = idle && sink.ready // winner (if any) claims sink // Who wants access to the sink? val valids = sourcesIn.map(_.valid) // Arbitrate amongst the requests val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools) // Which request wins arbitration? val winner = VecInit((readys zip valids) map { case (r,v) => r&&v }) // Confirm the policy works properly require (readys.size == valids.size) // Never two winners val prefixOR = winner.scanLeft(false.B)(_\|\|_).init assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _}) // If there was any request, there is a winner assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_)) // Track remaining beats val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) } val initBeats = maskedBeats.reduce(_ \| _) // no winner => 0 beats beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire) // The one-hot source granted access in the previous cycle val state = RegInit(VecInit(Seq.fill(sources.size)(false.B))) val muxState = Mux(idle, winner, state) state := muxState val allowed = Mux(idle, readys, state) (sourcesIn zip allowed) foreach { case (s, r) => s.ready := sink.ready && r } sink.valid := Mux(idle, valids.reduce(_\|\|_), Mux1H(state, valids)) sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits)) } } } // Synthesizable unit tests import freechips.rocketchip.unittest._ abstract class DecoupledArbiterTest( policy: TLArbiter.Policy, txns: Int, timeout: Int, val numSources: Int, beatsLeftFromIdx: Int => UInt) (implicit p: Parameters) extends UnitTest(timeout) { val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W)))) dontTouch(sources.suggestName("sources")) val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W))) dontTouch(sink.suggestName("sink")) val count = RegInit(0.U(log2Ceil(txns).W)) val lfsr = LFSR(16, true.B) sources.zipWithIndex.map { case (z, i) => z.bits := i.U } TLArbiter(policy)(sink, sources.zipWithIndex.map { case (z, i) => (beatsLeftFromIdx(i), z) }:_) count := count + 1.U io.finished := count >= txns.U } /** This tests that when a specific pattern of source valids are driven, * a new index from amongst that pattern is always selected, * unless one of those sources takes multiple beats, * in which case the same index should be selected until the arbiter goes idle. / class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false) (implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U) { val lastWinner = RegInit((numSources+1).U) val beatsLeft = RegInit(0.U(log2Ceil(numSources).W)) val first = lastWinner > numSources.U val valid = lfsr(0) val ready = lfsr(15) sink.ready := ready sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid) } when (sink.fire) { if (print) { printf("TestRobin: %d\n", sink.bits) } when (beatsLeft === 0.U) { assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.") lastWinner := sink.bits beatsLeft := sink.bits } .otherwise { assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats") beatsLeft := beatsLeft - 1.U } } if (print) { when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) } } } /* This tests that the lowest index is always selected across random single cycle transactions. / class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertLowest(id: Int): Unit = { when (sources(id).valid) { assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) } } /* This tests that the highest index is always selected across random single cycle transactions. */ class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertHighest(id: Int): Unit = { when (sources(id).valid) { assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) } }	module TLAtomicAutomata( // @[AtomicAutomata.scala:36:9] input clock, // @[AtomicAutomata.scala:36:9] input reset, // @[AtomicAutomata.scala:36:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [28:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [28:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire source_i_ready; // @[Arbiter.scala:94:31] reg [1:0] cam_s_0_state; // @[AtomicAutomata.scala:82:28] reg [2:0] cam_a_0_bits_opcode; // @[AtomicAutomata.scala:83:24] reg [2:0] cam_a_0_bits_param; // @[AtomicAutomata.scala:83:24] reg [3:0] cam_a_0_bits_size; // @[AtomicAutomata.scala:83:24] reg [6:0] cam_a_0_bits_source; // @[AtomicAutomata.scala:83:24] reg [28:0] cam_a_0_bits_address; // @[AtomicAutomata.scala:83:24] reg [7:0] cam_a_0_bits_mask; // @[AtomicAutomata.scala:83:24] reg [63:0] cam_a_0_bits_data; // @[AtomicAutomata.scala:83:24] reg cam_a_0_bits_corrupt; // @[AtomicAutomata.scala:83:24] reg [3:0] cam_a_0_lut; // @[AtomicAutomata.scala:83:24] reg [63:0] cam_d_0_data; // @[AtomicAutomata.scala:84:24] reg cam_d_0_denied; // @[AtomicAutomata.scala:84:24] reg cam_d_0_corrupt; // @[AtomicAutomata.scala:84:24] wire cam_free_0 = cam_s_0_state == 2'h0; // @[AtomicAutomata.scala:82:28, :86:44] wire winner_0 = cam_s_0_state == 2'h2; // @[AtomicAutomata.scala:82:28, :87:44] wire _a_canArithmetic_T_3 = auto_in_a_bits_size < 4'h4; // @[Parameters.scala:92:38] wire [4:0] _GEN = {auto_in_a_bits_address[28:27], auto_in_a_bits_address[25], auto_in_a_bits_address[16], ~(auto_in_a_bits_address[12])}; // @[Parameters.scala:137:{31,41,46}] wire [4:0] _GEN_0 = {auto_in_a_bits_address[28:27] ^ 2'h2, auto_in_a_bits_address[25], auto_in_a_bits_address[16], auto_in_a_bits_address[12]}; // @[Parameters.scala:137:{31,41,46}] wire a_isSupported = auto_in_a_bits_opcode == 3'h3 ? _a_canArithmetic_T_3 & (~(\|_GEN) \| ~(\|_GEN_0)) : auto_in_a_bits_opcode != 3'h2 \| _a_canArithmetic_T_3 & (~(\|_GEN) \| ~(\|_GEN_0)); // @[Parameters.scala:684:54, :685:42] wire [3:0] _logic_out_T = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[0], cam_d_0_data[0]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_2 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[1], cam_d_0_data[1]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_4 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[2], cam_d_0_data[2]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_6 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[3], cam_d_0_data[3]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_8 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[4], cam_d_0_data[4]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_10 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[5], cam_d_0_data[5]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_12 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[6], cam_d_0_data[6]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_14 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[7], cam_d_0_data[7]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_16 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[8], cam_d_0_data[8]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_18 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[9], cam_d_0_data[9]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_20 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[10], cam_d_0_data[10]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_22 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[11], cam_d_0_data[11]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_24 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[12], cam_d_0_data[12]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_26 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[13], cam_d_0_data[13]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_28 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[14], cam_d_0_data[14]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_30 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[15], cam_d_0_data[15]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_32 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[16], cam_d_0_data[16]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_34 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[17], cam_d_0_data[17]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_36 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[18], cam_d_0_data[18]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_38 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[19], cam_d_0_data[19]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_40 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[20], cam_d_0_data[20]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_42 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[21], cam_d_0_data[21]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_44 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[22], cam_d_0_data[22]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_46 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[23], cam_d_0_data[23]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_48 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[24], cam_d_0_data[24]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_50 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[25], cam_d_0_data[25]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_52 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[26], cam_d_0_data[26]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_54 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[27], cam_d_0_data[27]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_56 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[28], cam_d_0_data[28]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_58 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[29], cam_d_0_data[29]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_60 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[30], cam_d_0_data[30]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_62 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[31], cam_d_0_data[31]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_64 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[32], cam_d_0_data[32]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_66 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[33], cam_d_0_data[33]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_68 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[34], cam_d_0_data[34]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_70 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[35], cam_d_0_data[35]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_72 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[36], cam_d_0_data[36]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_74 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[37], cam_d_0_data[37]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_76 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[38], cam_d_0_data[38]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_78 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[39], cam_d_0_data[39]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_80 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[40], cam_d_0_data[40]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_82 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[41], cam_d_0_data[41]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_84 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[42], cam_d_0_data[42]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_86 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[43], cam_d_0_data[43]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_88 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[44], cam_d_0_data[44]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_90 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[45], cam_d_0_data[45]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_92 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[46], cam_d_0_data[46]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_94 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[47], cam_d_0_data[47]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_96 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[48], cam_d_0_data[48]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_98 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[49], cam_d_0_data[49]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_100 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[50], cam_d_0_data[50]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_102 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[51], cam_d_0_data[51]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_104 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[52], cam_d_0_data[52]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_106 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[53], cam_d_0_data[53]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_108 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[54], cam_d_0_data[54]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_110 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[55], cam_d_0_data[55]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_112 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[56], cam_d_0_data[56]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_114 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[57], cam_d_0_data[57]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_116 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[58], cam_d_0_data[58]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_118 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[59], cam_d_0_data[59]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_120 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[60], cam_d_0_data[60]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_122 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[61], cam_d_0_data[61]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_124 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[62], cam_d_0_data[62]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [3:0] _logic_out_T_126 = cam_a_0_lut >> {2'h0, cam_a_0_bits_data[63], cam_d_0_data[63]}; // @[AtomicAutomata.scala:83:24, :84:24, :119:{63,73}, :120:57] wire [6:0] _GEN_1 = ~(cam_a_0_bits_mask[6:0]) \| cam_a_0_bits_mask[7:1]; // @[AtomicAutomata.scala:83:24, :127:{25,31,39}] wire [6:0] _signbit_a_T = {cam_a_0_bits_data[55], cam_a_0_bits_data[47], cam_a_0_bits_data[39], cam_a_0_bits_data[31], cam_a_0_bits_data[23], cam_a_0_bits_data[15], cam_a_0_bits_data[7]} & ~_GEN_1; // @[AtomicAutomata.scala:83:24, :119:63, :127:{23,31}, :128:29, :131:38] wire [6:0] _signbit_d_T = {cam_d_0_data[55], cam_d_0_data[47], cam_d_0_data[39], cam_d_0_data[31], cam_d_0_data[23], cam_d_0_data[15], cam_d_0_data[7]} & ~_GEN_1; // @[AtomicAutomata.scala:84:24, :119:73, :127:{23,31}, :129:29, :132:38] wire [5:0] _GEN_2 = _signbit_a_T[6:1] \| _signbit_a_T[5:0]; // @[package.scala:253:{43,53}] wire [3:0] _GEN_3 = _GEN_2[5:2] \| _GEN_2[3:0]; // @[package.scala:253:{43,53}] wire _signext_a_T_13 = _GEN_2[1] \| _signbit_a_T[0]; // @[package.scala:253:43] wire [5:0] _GEN_4 = _signbit_d_T[6:1] \| _signbit_d_T[5:0]; // @[package.scala:253:{43,53}] wire [3:0] _GEN_5 = _GEN_4[5:2] \| _GEN_4[3:0]; // @[package.scala:253:{43,53}] wire _signext_d_T_13 = _GEN_4[1] \| _signbit_d_T[0]; // @[package.scala:253:43] wire [63:0] wide_mask = {{8{cam_a_0_bits_mask[7]}}, {8{cam_a_0_bits_mask[6]}}, {8{cam_a_0_bits_mask[5]}}, {8{cam_a_0_bits_mask[4]}}, {8{cam_a_0_bits_mask[3]}}, {8{cam_a_0_bits_mask[2]}}, {8{cam_a_0_bits_mask[1]}}, {8{cam_a_0_bits_mask[0]}}}; // @[AtomicAutomata.scala:83:24, :136:40] wire [63:0] a_a_ext = cam_a_0_bits_data & wide_mask \| {{8{_GEN_3[3] \| _signext_a_T_13}}, {8{_GEN_3[2] \| _GEN_2[0]}}, {8{_GEN_3[1] \| _signbit_a_T[0]}}, {8{_GEN_3[0]}}, {8{_signext_a_T_13}}, {8{_GEN_2[0]}}, {8{_signbit_a_T[0]}}, 8'h0}; // @[package.scala:253:43] wire [63:0] a_d_ext = cam_d_0_data & wide_mask \| {{8{_GEN_5[3] \| _signext_d_T_13}}, {8{_GEN_5[2] \| _GEN_4[0]}}, {8{_GEN_5[1] \| _signbit_d_T[0]}}, {8{_GEN_5[0]}}, {8{_signext_d_T_13}}, {8{_GEN_4[0]}}, {8{_signbit_d_T[0]}}, 8'h0}; // @[package.scala:253:43] wire [63:0] _adder_out_T = a_a_ext + ({64{~(cam_a_0_bits_param[2])}} ^ a_d_ext); // @[AtomicAutomata.scala:83:24, :125:39, :137:41, :138:41, :139:26, :140:33] wire a_allow = ~((&cam_s_0_state) \| winner_0) & (a_isSupported \| cam_free_0); // @[AtomicAutomata.scala:82:28, :86:44, :87:44, :88:{49,57}, :98:32, :155:{23,35,53}] wire nodeIn_a_ready = source_i_ready & a_allow; // @[AtomicAutomata.scala:155:35, :156:38] wire source_i_valid = auto_in_a_valid & a_allow; // @[AtomicAutomata.scala:155:35, :157:38] wire source_c_bits_a_mask_sub_sub_sub_0_1 = cam_a_0_bits_size > 4'h2; // @[Misc.scala:206:21] wire source_c_bits_a_mask_sub_sub_size = cam_a_0_bits_size[1:0] == 2'h2; // @[OneHot.scala:64:49] wire source_c_bits_a_mask_sub_sub_0_1 = source_c_bits_a_mask_sub_sub_sub_0_1 \| source_c_bits_a_mask_sub_sub_size & ~(cam_a_0_bits_address[2]); // @[Misc.scala:206:21, :209:26, :210:26, :211:20, :215:{29,38}] wire source_c_bits_a_mask_sub_sub_1_1 = source_c_bits_a_mask_sub_sub_sub_0_1 \| source_c_bits_a_mask_sub_sub_size & cam_a_0_bits_address[2]; // @[Misc.scala:206:21, :209:26, :210:26, :215:{29,38}] wire source_c_bits_a_mask_sub_size = cam_a_0_bits_size[1:0] == 2'h1; // @[OneHot.scala:64:49] wire source_c_bits_a_mask_sub_0_2 = ~(cam_a_0_bits_address[2]) & ~(cam_a_0_bits_address[1]); // @[Misc.scala:210:26, :211:20, :214:27] wire source_c_bits_a_mask_sub_0_1 = source_c_bits_a_mask_sub_sub_0_1 \| source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}] wire source_c_bits_a_mask_sub_1_2 = ~(cam_a_0_bits_address[2]) & cam_a_0_bits_address[1]; // @[Misc.scala:210:26, :211:20, :214:27] wire source_c_bits_a_mask_sub_1_1 = source_c_bits_a_mask_sub_sub_0_1 \| source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}] wire source_c_bits_a_mask_sub_2_2 = cam_a_0_bits_address[2] & ~(cam_a_0_bits_address[1]); // @[Misc.scala:210:26, :211:20, :214:27] wire source_c_bits_a_mask_sub_2_1 = source_c_bits_a_mask_sub_sub_1_1 \| source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}] wire source_c_bits_a_mask_sub_3_2 = cam_a_0_bits_address[2] & cam_a_0_bits_address[1]; // @[Misc.scala:210:26, :214:27] wire source_c_bits_a_mask_sub_3_1 = source_c_bits_a_mask_sub_sub_1_1 \| source_c_bits_a_mask_sub_size & source_c_bits_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:{29,38}] reg [8:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28] wire winner_1 = ~winner_0 & source_i_valid; // @[AtomicAutomata.scala:87:44, :157:38] wire _nodeOut_a_valid_T = winner_0 \| source_i_valid; // @[AtomicAutomata.scala:87:44, :157:38]
Generate the Verilog code corresponding to the following Chisel files. File btb.scala: package boom.v3.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix} import scala.math.min case class BoomBTBParams( nSets: Int = 128, nWays: Int = 2, offsetSz: Int = 13, extendedNSets: Int = 128 ) class BTBBranchPredictorBank(params: BoomBTBParams = BoomBTBParams())(implicit p: Parameters) extends BranchPredictorBank()(p) { override val nSets = params.nSets override val nWays = params.nWays val tagSz = vaddrBitsExtended - log2Ceil(nSets) - log2Ceil(fetchWidth) - 1 val offsetSz = params.offsetSz val extendedNSets = params.extendedNSets require(isPow2(nSets)) require(isPow2(extendedNSets) \|\| extendedNSets == 0) require(extendedNSets <= nSets) require(extendedNSets >= 1) class BTBEntry extends Bundle { val offset = SInt(offsetSz.W) val extended = Bool() } val btbEntrySz = offsetSz + 1 class BTBMeta extends Bundle { val is_br = Bool() val tag = UInt(tagSz.W) } val btbMetaSz = tagSz + 1 class BTBPredictMeta extends Bundle { val write_way = UInt(log2Ceil(nWays).W) } val s1_meta = Wire(new BTBPredictMeta) val f3_meta = RegNext(RegNext(s1_meta)) io.f3_meta := f3_meta.asUInt override val metaSz = s1_meta.asUInt.getWidth val doing_reset = RegInit(true.B) val reset_idx = RegInit(0.U(log2Ceil(nSets).W)) reset_idx := reset_idx + doing_reset when (reset_idx === (nSets-1).U) { doing_reset := false.B } val meta = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbMetaSz.W))) } val btb = Seq.fill(nWays) { SyncReadMem(nSets, Vec(bankWidth, UInt(btbEntrySz.W))) } val ebtb = SyncReadMem(extendedNSets, UInt(vaddrBitsExtended.W)) val mems = (((0 until nWays) map ({w:Int => Seq( (f"btb_meta_way$w", nSets, bankWidth * btbMetaSz), (f"btb_data_way$w", nSets, bankWidth * btbEntrySz))})).flatten ++ Seq(("ebtb", extendedNSets, vaddrBitsExtended))) val s1_req_rbtb = VecInit(btb.map { b => VecInit(b.read(s0_idx , s0_valid).map(_.asTypeOf(new BTBEntry))) }) val s1_req_rmeta = VecInit(meta.map { m => VecInit(m.read(s0_idx, s0_valid).map(_.asTypeOf(new BTBMeta))) }) val s1_req_rebtb = ebtb.read(s0_idx, s0_valid) val s1_req_tag = s1_idx >> log2Ceil(nSets) val s1_resp = Wire(Vec(bankWidth, Valid(UInt(vaddrBitsExtended.W)))) val s1_is_br = Wire(Vec(bankWidth, Bool())) val s1_is_jal = Wire(Vec(bankWidth, Bool())) val s1_hit_ohs = VecInit((0 until bankWidth) map { i => VecInit((0 until nWays) map { w => s1_req_rmeta(w)(i).tag === s1_req_tag(tagSz-1,0) }) }) val s1_hits = s1_hit_ohs.map { oh => oh.reduce(_\|\|_) } val s1_hit_ways = s1_hit_ohs.map { oh => PriorityEncoder(oh) } for (w <- 0 until bankWidth) { val entry_meta = s1_req_rmeta(s1_hit_ways(w))(w) val entry_btb = s1_req_rbtb(s1_hit_ways(w))(w) s1_resp(w).valid := !doing_reset && s1_valid && s1_hits(w) s1_resp(w).bits := Mux( entry_btb.extended, s1_req_rebtb, (s1_pc.asSInt + (w << 1).S + entry_btb.offset).asUInt) s1_is_br(w) := !doing_reset && s1_resp(w).valid && entry_meta.is_br s1_is_jal(w) := !doing_reset && s1_resp(w).valid && !entry_meta.is_br io.resp.f2(w) := io.resp_in(0).f2(w) io.resp.f3(w) := io.resp_in(0).f3(w) when (RegNext(s1_hits(w))) { io.resp.f2(w).predicted_pc := RegNext(s1_resp(w)) io.resp.f2(w).is_br := RegNext(s1_is_br(w)) io.resp.f2(w).is_jal := RegNext(s1_is_jal(w)) when (RegNext(s1_is_jal(w))) { io.resp.f2(w).taken := true.B } } when (RegNext(RegNext(s1_hits(w)))) { io.resp.f3(w).predicted_pc := RegNext(io.resp.f2(w).predicted_pc) io.resp.f3(w).is_br := RegNext(io.resp.f2(w).is_br) io.resp.f3(w).is_jal := RegNext(io.resp.f2(w).is_jal) when (RegNext(RegNext(s1_is_jal(w)))) { io.resp.f3(w).taken := true.B } } } val alloc_way = if (nWays > 1) { val r_metas = Cat(VecInit(s1_req_rmeta.map { w => VecInit(w.map(_.tag)) }).asUInt, s1_req_tag(tagSz-1,0)) val l = log2Ceil(nWays) val nChunks = (r_metas.getWidth + l - 1) / l val chunks = (0 until nChunks) map { i => r_metas(min((i+1)l, r_metas.getWidth)-1, il) } chunks.reduce(_^_) } else { 0.U } s1_meta.write_way := Mux(s1_hits.reduce(_\|\|_), PriorityEncoder(s1_hit_ohs.map(_.asUInt).reduce(_\|_)), alloc_way) val s1_update_cfi_idx = s1_update.bits.cfi_idx.bits val s1_update_meta = s1_update.bits.meta.asTypeOf(new BTBPredictMeta) val max_offset_value = Cat(0.B, ~(0.U((offsetSz-1).W))).asSInt val min_offset_value = Cat(1.B, (0.U((offsetSz-1).W))).asSInt val new_offset_value = (s1_update.bits.target.asSInt - (s1_update.bits.pc + (s1_update.bits.cfi_idx.bits << 1)).asSInt) val offset_is_extended = (new_offset_value > max_offset_value \|\| new_offset_value < min_offset_value) val s1_update_wbtb_data = Wire(new BTBEntry) s1_update_wbtb_data.extended := offset_is_extended s1_update_wbtb_data.offset := new_offset_value val s1_update_wbtb_mask = (UIntToOH(s1_update_cfi_idx) & Fill(bankWidth, s1_update.bits.cfi_idx.valid && s1_update.valid && s1_update.bits.cfi_taken && s1_update.bits.is_commit_update)) val s1_update_wmeta_mask = ((s1_update_wbtb_mask \| s1_update.bits.br_mask) & (Fill(bankWidth, s1_update.valid && s1_update.bits.is_commit_update) \| (Fill(bankWidth, s1_update.valid) & s1_update.bits.btb_mispredicts) ) ) val s1_update_wmeta_data = Wire(Vec(bankWidth, new BTBMeta)) for (w <- 0 until bankWidth) { s1_update_wmeta_data(w).tag := Mux(s1_update.bits.btb_mispredicts(w), 0.U, s1_update_idx >> log2Ceil(nSets)) s1_update_wmeta_data(w).is_br := s1_update.bits.br_mask(w) } for (w <- 0 until nWays) { when (doing_reset \|\| s1_update_meta.write_way === w.U \|\| (w == 0 && nWays == 1).B) { btb(w).write( Mux(doing_reset, reset_idx, s1_update_idx), Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(btbEntrySz.W) }), VecInit(Seq.fill(bankWidth) { s1_update_wbtb_data.asUInt })), Mux(doing_reset, (~(0.U(bankWidth.W))), s1_update_wbtb_mask).asBools ) meta(w).write( Mux(doing_reset, reset_idx, s1_update_idx), Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(btbMetaSz.W) }), VecInit(s1_update_wmeta_data.map(_.asUInt))), Mux(doing_reset, (~(0.U(bankWidth.W))), s1_update_wmeta_mask).asBools ) } } when (s1_update_wbtb_mask =/= 0.U && offset_is_extended) { ebtb.write(s1_update_idx, s1_update.bits.target) } }	module btb_0_1( // @[btb.scala:66:47] input [6:0] R0_addr, input R0_en, input R0_clk, output [55:0] R0_data, input [6:0] W0_addr, input W0_en, input W0_clk, input [55:0] W0_data, input [3:0] W0_mask ); btb_0_ext btb_0_ext ( // @[btb.scala:66:47] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data), .W0_mask (W0_mask) ); // @[btb.scala:66:47] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File SourceD.scala: / * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import TLMessages._ import TLAtomics._ import TLPermissions._ class SourceDRequest(params: InclusiveCacheParameters) extends FullRequest(params) { val sink = UInt(params.inner.bundle.sinkBits.W) val way = UInt(params.wayBits.W) val bad = Bool() } class SourceDHazard(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val way = UInt(params.wayBits.W) } class PutBufferACEntry(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val data = UInt(params.inner.bundle.dataBits.W) val mask = UInt((params.inner.bundle.dataBits/8).W) val corrupt = Bool() } class SourceD(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val req = Flipped(Decoupled(new SourceDRequest(params))) val d = Decoupled(new TLBundleD(params.inner.bundle)) // Put data from SinkA val pb_pop = Decoupled(new PutBufferPop(params)) val pb_beat = Flipped(new PutBufferAEntry(params)) // Release data from SinkC val rel_pop = Decoupled(new PutBufferPop(params)) val rel_beat = Flipped(new PutBufferCEntry(params)) // Access to the BankedStore val bs_radr = Decoupled(new BankedStoreInnerAddress(params)) val bs_rdat = Flipped(new BankedStoreInnerDecoded(params)) val bs_wadr = Decoupled(new BankedStoreInnerAddress(params)) val bs_wdat = new BankedStoreInnerPoison(params) // Is it safe to evict/replace this way? val evict_req = Flipped(new SourceDHazard(params)) val evict_safe = Bool() val grant_req = Flipped(new SourceDHazard(params)) val grant_safe = Bool() }) val beatBytes = params.inner.manager.beatBytes val writeBytes = params.micro.writeBytes val s1_valid = Wire(Bool()) val s2_valid = Wire(Bool()) val s3_valid = Wire(Bool()) val s2_ready = Wire(Bool()) val s3_ready = Wire(Bool()) val s4_ready = Wire(Bool()) ////////////////////////////////////// STAGE 1 ////////////////////////////////////// // Reform the request beats val busy = RegInit(false.B) val s1_block_r = RegInit(false.B) val s1_counter = RegInit(0.U(params.innerBeatBits.W)) val s1_req_reg = RegEnable(io.req.bits, !busy && io.req.valid) val s1_req = Mux(!busy, io.req.bits, s1_req_reg) val s1_x_bypass = Wire(UInt((beatBytes/writeBytes).W)) // might go from high=>low during stall val s1_latch_bypass = RegNext(!(busy \|\| io.req.valid) \|\| s2_ready) val s1_bypass = Mux(s1_latch_bypass, s1_x_bypass, RegEnable(s1_x_bypass, s1_latch_bypass)) val s1_mask = MaskGen(s1_req.offset, s1_req.size, beatBytes, writeBytes) & ~s1_bypass val s1_grant = (s1_req.opcode === AcquireBlock && s1_req.param === BtoT) \|\| s1_req.opcode === AcquirePerm val s1_need_r = s1_mask.orR && s1_req.prio(0) && s1_req.opcode =/= Hint && !s1_grant && (s1_req.opcode =/= PutFullData \|\| s1_req.size < log2Ceil(writeBytes).U ) val s1_valid_r = (busy \|\| io.req.valid) && s1_need_r && !s1_block_r val s1_need_pb = Mux(s1_req.prio(0), !s1_req.opcode(2), s1_req.opcode(0)) // hasData val s1_single = Mux(s1_req.prio(0), s1_req.opcode === Hint \|\| s1_grant, s1_req.opcode === Release) val s1_retires = !s1_single // retire all operations with data in s3 for bypass (saves energy) // Alternatively: val s1_retires = s1_need_pb // retire only updates for bypass (less backpressure from WB) val s1_beats1 = Mux(s1_single, 0.U, UIntToOH1(s1_req.size, log2Up(params.cache.blockBytes)) >> log2Ceil(beatBytes)) val s1_beat = (s1_req.offset >> log2Ceil(beatBytes)) \| s1_counter val s1_last = s1_counter === s1_beats1 val s1_first = s1_counter === 0.U params.ccover(s1_block_r, "SOURCED_1_SRAM_HOLD", "SRAM read-out successful, but stalled by stage 2") params.ccover(!s1_latch_bypass, "SOURCED_1_BYPASS_HOLD", "Bypass match successful, but stalled by stage 2") params.ccover((busy \|\| io.req.valid) && !s1_need_r, "SOURCED_1_NO_MODIFY", "Transaction servicable without SRAM") io.bs_radr.valid := s1_valid_r io.bs_radr.bits.noop := false.B io.bs_radr.bits.way := s1_req.way io.bs_radr.bits.set := s1_req.set io.bs_radr.bits.beat := s1_beat io.bs_radr.bits.mask := s1_mask params.ccover(io.bs_radr.valid && !io.bs_radr.ready, "SOURCED_1_READ_STALL", "Data readout stalled") // Make a queue to catch BS readout during stalls val queue = Module(new Queue(chiselTypeOf(io.bs_rdat), 3, flow=true)) queue.io.enq.valid := RegNext(RegNext(io.bs_radr.fire)) queue.io.enq.bits := io.bs_rdat assert (!queue.io.enq.valid \|\| queue.io.enq.ready) params.ccover(!queue.io.enq.ready, "SOURCED_1_QUEUE_FULL", "Filled SRAM skidpad queue completely") when (io.bs_radr.fire) { s1_block_r := true.B } when (io.req.valid) { busy := true.B } when (s1_valid && s2_ready) { s1_counter := s1_counter + 1.U s1_block_r := false.B when (s1_last) { s1_counter := 0.U busy := false.B } } params.ccover(s1_valid && !s2_ready, "SOURCED_1_STALL", "Stage 1 pipeline blocked") io.req.ready := !busy s1_valid := (busy \|\| io.req.valid) && (!s1_valid_r \|\| io.bs_radr.ready) ////////////////////////////////////// STAGE 2 ////////////////////////////////////// // Fetch the request data val s2_latch = s1_valid && s2_ready val s2_full = RegInit(false.B) val s2_valid_pb = RegInit(false.B) val s2_beat = RegEnable(s1_beat, s2_latch) val s2_bypass = RegEnable(s1_bypass, s2_latch) val s2_req = RegEnable(s1_req, s2_latch) val s2_last = RegEnable(s1_last, s2_latch) val s2_need_r = RegEnable(s1_need_r, s2_latch) val s2_need_pb = RegEnable(s1_need_pb, s2_latch) val s2_retires = RegEnable(s1_retires, s2_latch) val s2_need_d = RegEnable(!s1_need_pb \|\| s1_first, s2_latch) val s2_pdata_raw = Wire(new PutBufferACEntry(params)) val s2_pdata = s2_pdata_raw holdUnless s2_valid_pb s2_pdata_raw.data := Mux(s2_req.prio(0), io.pb_beat.data, io.rel_beat.data) s2_pdata_raw.mask := Mux(s2_req.prio(0), io.pb_beat.mask, ~0.U(params.inner.manager.beatBytes.W)) s2_pdata_raw.corrupt := Mux(s2_req.prio(0), io.pb_beat.corrupt, io.rel_beat.corrupt) io.pb_pop.valid := s2_valid_pb && s2_req.prio(0) io.pb_pop.bits.index := s2_req.put io.pb_pop.bits.last := s2_last io.rel_pop.valid := s2_valid_pb && !s2_req.prio(0) io.rel_pop.bits.index := s2_req.put io.rel_pop.bits.last := s2_last params.ccover(io.pb_pop.valid && !io.pb_pop.ready, "SOURCED_2_PUTA_STALL", "Channel A put buffer was not ready in time") if (!params.firstLevel) params.ccover(io.rel_pop.valid && !io.rel_pop.ready, "SOURCED_2_PUTC_STALL", "Channel C put buffer was not ready in time") val pb_ready = Mux(s2_req.prio(0), io.pb_pop.ready, io.rel_pop.ready) when (pb_ready) { s2_valid_pb := false.B } when (s2_valid && s3_ready) { s2_full := false.B } when (s2_latch) { s2_valid_pb := s1_need_pb } when (s2_latch) { s2_full := true.B } params.ccover(s2_valid && !s3_ready, "SOURCED_2_STALL", "Stage 2 pipeline blocked") s2_valid := s2_full && (!s2_valid_pb \|\| pb_ready) s2_ready := !s2_full \|\| (s3_ready && (!s2_valid_pb \|\| pb_ready)) ////////////////////////////////////// STAGE 3 ////////////////////////////////////// // Send D response val s3_latch = s2_valid && s3_ready val s3_full = RegInit(false.B) val s3_valid_d = RegInit(false.B) val s3_beat = RegEnable(s2_beat, s3_latch) val s3_bypass = RegEnable(s2_bypass, s3_latch) val s3_req = RegEnable(s2_req, s3_latch) val s3_adjusted_opcode = Mux(s3_req.bad, Get, s3_req.opcode) // kill update when denied val s3_last = RegEnable(s2_last, s3_latch) val s3_pdata = RegEnable(s2_pdata, s3_latch) val s3_need_pb = RegEnable(s2_need_pb, s3_latch) val s3_retires = RegEnable(s2_retires, s3_latch) val s3_need_r = RegEnable(s2_need_r, s3_latch) val s3_need_bs = s3_need_pb val s3_acq = s3_req.opcode === AcquireBlock \|\| s3_req.opcode === AcquirePerm // Collect s3's data from either the BankedStore or bypass // NOTE: we use the s3_bypass passed down from s1_bypass, because s2-s4 were guarded by the hazard checks and not stale val s3_bypass_data = Wire(UInt()) def chunk(x: UInt): Seq[UInt] = Seq.tabulate(beatBytes/writeBytes) { i => x((i+1)writeBytes8-1, iwriteBytes*8) } def chop (x: UInt): Seq[Bool] = Seq.tabulate(beatBytes/writeBytes) { i => x(i) } def bypass(sel: UInt, x: UInt, y: UInt) = (chop(sel) zip (chunk(x) zip chunk(y))) .map { case (s, (x, y)) => Mux(s, x, y) } .asUInt val s3_rdata = bypass(s3_bypass, s3_bypass_data, queue.io.deq.bits.data) // Lookup table for response codes val grant = Mux(s3_req.param === BtoT, Grant, GrantData) val resp_opcode = VecInit(Seq(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, grant, Grant)) // No restrictions on the type of buffer used here val d = Wire(chiselTypeOf(io.d)) io.d <> params.micro.innerBuf.d(d) d.valid := s3_valid_d d.bits.opcode := Mux(s3_req.prio(0), resp_opcode(s3_req.opcode), ReleaseAck) d.bits.param := Mux(s3_req.prio(0) && s3_acq, Mux(s3_req.param =/= NtoB, toT, toB), 0.U) d.bits.size := s3_req.size d.bits.source := s3_req.source d.bits.sink := s3_req.sink d.bits.denied := s3_req.bad d.bits.data := s3_rdata d.bits.corrupt := s3_req.bad && d.bits.opcode(0) queue.io.deq.ready := s3_valid && s4_ready && s3_need_r assert (!s3_full \|\| !s3_need_r \|\| queue.io.deq.valid) when (d.ready) { s3_valid_d := false.B } when (s3_valid && s4_ready) { s3_full := false.B } when (s3_latch) { s3_valid_d := s2_need_d } when (s3_latch) { s3_full := true.B } params.ccover(s3_valid && !s4_ready, "SOURCED_3_STALL", "Stage 3 pipeline blocked") s3_valid := s3_full && (!s3_valid_d \|\| d.ready) s3_ready := !s3_full \|\| (s4_ready && (!s3_valid_d \|\| d.ready)) ////////////////////////////////////// STAGE 4 ////////////////////////////////////// // Writeback updated data val s4_latch = s3_valid && s3_retires && s4_ready val s4_full = RegInit(false.B) val s4_beat = RegEnable(s3_beat, s4_latch) val s4_need_r = RegEnable(s3_need_r, s4_latch) val s4_need_bs = RegEnable(s3_need_bs, s4_latch) val s4_need_pb = RegEnable(s3_need_pb, s4_latch) val s4_req = RegEnable(s3_req, s4_latch) val s4_adjusted_opcode = RegEnable(s3_adjusted_opcode, s4_latch) val s4_pdata = RegEnable(s3_pdata, s4_latch) val s4_rdata = RegEnable(s3_rdata, s4_latch) val atomics = Module(new Atomics(params.inner.bundle)) atomics.io.write := s4_req.prio(2) atomics.io.a.opcode := s4_adjusted_opcode atomics.io.a.param := s4_req.param atomics.io.a.size := 0.U atomics.io.a.source := 0.U atomics.io.a.address := 0.U atomics.io.a.mask := s4_pdata.mask atomics.io.a.data := s4_pdata.data atomics.io.a.corrupt := DontCare atomics.io.data_in := s4_rdata io.bs_wadr.valid := s4_full && s4_need_bs io.bs_wadr.bits.noop := false.B io.bs_wadr.bits.way := s4_req.way io.bs_wadr.bits.set := s4_req.set io.bs_wadr.bits.beat := s4_beat io.bs_wadr.bits.mask := Cat(s4_pdata.mask.asBools.grouped(writeBytes).map(_.reduce(_\|\|_)).toList.reverse) io.bs_wdat.data := atomics.io.data_out assert (!(s4_full && s4_need_pb && s4_pdata.corrupt), "Data poisoning unsupported") params.ccover(io.bs_wadr.valid && !io.bs_wadr.ready, "SOURCED_4_WRITEBACK_STALL", "Data writeback stalled") params.ccover(s4_req.prio(0) && s4_req.opcode === ArithmeticData && s4_req.param === MIN, "SOURCED_4_ATOMIC_MIN", "Evaluated a signed minimum atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === ArithmeticData && s4_req.param === MAX, "SOURCED_4_ATOMIC_MAX", "Evaluated a signed maximum atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === ArithmeticData && s4_req.param === MINU, "SOURCED_4_ATOMIC_MINU", "Evaluated an unsigned minimum atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === ArithmeticData && s4_req.param === MAXU, "SOURCED_4_ATOMIC_MAXU", "Evaluated an unsigned minimum atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === ArithmeticData && s4_req.param === ADD, "SOURCED_4_ATOMIC_ADD", "Evaluated an addition atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === LogicalData && s4_req.param === XOR, "SOURCED_4_ATOMIC_XOR", "Evaluated a bitwise XOR atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === LogicalData && s4_req.param === OR, "SOURCED_4_ATOMIC_OR", "Evaluated a bitwise OR atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === LogicalData && s4_req.param === AND, "SOURCED_4_ATOMIC_AND", "Evaluated a bitwise AND atomic") params.ccover(s4_req.prio(0) && s4_req.opcode === LogicalData && s4_req.param === SWAP, "SOURCED_4_ATOMIC_SWAP", "Evaluated a bitwise SWAP atomic") when (io.bs_wadr.ready \|\| !s4_need_bs) { s4_full := false.B } when (s4_latch) { s4_full := true.B } s4_ready := !s3_retires \|\| !s4_full \|\| io.bs_wadr.ready \|\| !s4_need_bs ////////////////////////////////////// RETIRED ////////////////////////////////////// // Record for bypass the last three retired writebacks // We need 3 slots to collect what was in s2, s3, s4 when the request was in s1 // ... you can't rely on s4 being full if bubbles got introduced between s1 and s2 val retire = s4_full && (io.bs_wadr.ready \|\| !s4_need_bs) val s5_req = RegEnable(s4_req, retire) val s5_beat = RegEnable(s4_beat, retire) val s5_dat = RegEnable(atomics.io.data_out, retire) val s6_req = RegEnable(s5_req, retire) val s6_beat = RegEnable(s5_beat, retire) val s6_dat = RegEnable(s5_dat, retire) val s7_dat = RegEnable(s6_dat, retire) ////////////////////////////////////// BYPASSS ////////////////////////////////////// // Manually retime this circuit to pull a register stage forward val pre_s3_req = Mux(s3_latch, s2_req, s3_req) val pre_s4_req = Mux(s4_latch, s3_req, s4_req) val pre_s5_req = Mux(retire, s4_req, s5_req) val pre_s6_req = Mux(retire, s5_req, s6_req) val pre_s3_beat = Mux(s3_latch, s2_beat, s3_beat) val pre_s4_beat = Mux(s4_latch, s3_beat, s4_beat) val pre_s5_beat = Mux(retire, s4_beat, s5_beat) val pre_s6_beat = Mux(retire, s5_beat, s6_beat) val pre_s5_dat = Mux(retire, atomics.io.data_out, s5_dat) val pre_s6_dat = Mux(retire, s5_dat, s6_dat) val pre_s7_dat = Mux(retire, s6_dat, s7_dat) val pre_s4_full = s4_latch \|\| (!(io.bs_wadr.ready \|\| !s4_need_bs) && s4_full) val pre_s3_4_match = pre_s4_req.set === pre_s3_req.set && pre_s4_req.way === pre_s3_req.way && pre_s4_beat === pre_s3_beat && pre_s4_full val pre_s3_5_match = pre_s5_req.set === pre_s3_req.set && pre_s5_req.way === pre_s3_req.way && pre_s5_beat === pre_s3_beat val pre_s3_6_match = pre_s6_req.set === pre_s3_req.set && pre_s6_req.way === pre_s3_req.way && pre_s6_beat === pre_s3_beat val pre_s3_4_bypass = Mux(pre_s3_4_match, MaskGen(pre_s4_req.offset, pre_s4_req.size, beatBytes, writeBytes), 0.U) val pre_s3_5_bypass = Mux(pre_s3_5_match, MaskGen(pre_s5_req.offset, pre_s5_req.size, beatBytes, writeBytes), 0.U) val pre_s3_6_bypass = Mux(pre_s3_6_match, MaskGen(pre_s6_req.offset, pre_s6_req.size, beatBytes, writeBytes), 0.U) s3_bypass_data := bypass(RegNext(pre_s3_4_bypass), atomics.io.data_out, RegNext( bypass(pre_s3_5_bypass, pre_s5_dat, bypass(pre_s3_6_bypass, pre_s6_dat, pre_s7_dat)))) // Detect which parts of s1 will be bypassed from later pipeline stages (s1-s4) // Note: we also bypass from reads ahead in the pipeline to save power val s1_2_match = s2_req.set === s1_req.set && s2_req.way === s1_req.way && s2_beat === s1_beat && s2_full && s2_retires val s1_3_match = s3_req.set === s1_req.set && s3_req.way === s1_req.way && s3_beat === s1_beat && s3_full && s3_retires val s1_4_match = s4_req.set === s1_req.set && s4_req.way === s1_req.way && s4_beat === s1_beat && s4_full for (i <- 0 until 8) { val cover = 1.U val s2 = s1_2_match === cover(0) val s3 = s1_3_match === cover(1) val s4 = s1_4_match === cover(2) params.ccover(io.req.valid && s2 && s3 && s4, "SOURCED_BYPASS_CASE_" + i, "Bypass data from all subsets of pipeline stages") } val s1_2_bypass = Mux(s1_2_match, MaskGen(s2_req.offset, s2_req.size, beatBytes, writeBytes), 0.U) val s1_3_bypass = Mux(s1_3_match, MaskGen(s3_req.offset, s3_req.size, beatBytes, writeBytes), 0.U) val s1_4_bypass = Mux(s1_4_match, MaskGen(s4_req.offset, s4_req.size, beatBytes, writeBytes), 0.U) s1_x_bypass := s1_2_bypass \| s1_3_bypass \| s1_4_bypass ////////////////////////////////////// HAZARDS ////////////////////////////////////// // SinkC, SourceC, and SinkD can never interfer with each other because their operation // is fully contained with an execution plan of an MSHR. That MSHR owns the entire set, so // there is no way for a data race. // However, SourceD is special. We allow it to run ahead after the MSHR and scheduler have // released control of a set+way. This is necessary to allow single cycle occupancy for // hits. Thus, we need to be careful about data hazards between SourceD and the other ports // of the BankedStore. We can at least compare to registers 's1_req_reg', because the first // cycle of SourceD falls within the occupancy of the MSHR's plan. // Must ReleaseData=> be interlocked? RaW hazard io.evict_safe := (!busy \|\| io.evict_req.way =/= s1_req_reg.way \|\| io.evict_req.set =/= s1_req_reg.set) && (!s2_full \|\| io.evict_req.way =/= s2_req.way \|\| io.evict_req.set =/= s2_req.set) && (!s3_full \|\| io.evict_req.way =/= s3_req.way \|\| io.evict_req.set =/= s3_req.set) && (!s4_full \|\| io.evict_req.way =/= s4_req.way \|\| io.evict_req.set =/= s4_req.set) // Must =>GrantData be interlocked? WaR hazard io.grant_safe := (!busy \|\| io.grant_req.way =/= s1_req_reg.way \|\| io.grant_req.set =/= s1_req_reg.set) && (!s2_full \|\| io.grant_req.way =/= s2_req.way \|\| io.grant_req.set =/= s2_req.set) && (!s3_full \|\| io.grant_req.way =/= s3_req.way \|\| io.grant_req.set =/= s3_req.set) && (!s4_full \|\| io.grant_req.way =/= s4_req.way \|\| io.grant_req.set =/= s4_req.set) // SourceD cannot overlap with SinkC b/c the only way inner caches could become // dirty such that they want to put data in via SinkC is if we Granted them permissions, // which must flow through the SourecD pipeline. }	module SourceD( // @[SourceD.scala:48:7] input clock, // @[SourceD.scala:48:7] input reset, // @[SourceD.scala:48:7] output io_req_ready, // @[SourceD.scala:50:14] input io_req_valid, // @[SourceD.scala:50:14] input io_req_bits_prio_0, // @[SourceD.scala:50:14] input io_req_bits_prio_1, // @[SourceD.scala:50:14] input io_req_bits_prio_2, // @[SourceD.scala:50:14] input io_req_bits_control, // @[SourceD.scala:50:14] input [2:0] io_req_bits_opcode, // @[SourceD.scala:50:14] input [2:0] io_req_bits_param, // @[SourceD.scala:50:14] input [2:0] io_req_bits_size, // @[SourceD.scala:50:14] input [7:0] io_req_bits_source, // @[SourceD.scala:50:14] input [12:0] io_req_bits_tag, // @[SourceD.scala:50:14] input [5:0] io_req_bits_offset, // @[SourceD.scala:50:14] input [5:0] io_req_bits_put, // @[SourceD.scala:50:14] input [9:0] io_req_bits_set, // @[SourceD.scala:50:14] input [3:0] io_req_bits_sink, // @[SourceD.scala:50:14] input [2:0] io_req_bits_way, // @[SourceD.scala:50:14] input io_req_bits_bad, // @[SourceD.scala:50:14] input io_d_ready, // @[SourceD.scala:50:14] output io_d_valid, // @[SourceD.scala:50:14] output [2:0] io_d_bits_opcode, // @[SourceD.scala:50:14] output [1:0] io_d_bits_param, // @[SourceD.scala:50:14] output [2:0] io_d_bits_size, // @[SourceD.scala:50:14] output [7:0] io_d_bits_source, // @[SourceD.scala:50:14] output [3:0] io_d_bits_sink, // @[SourceD.scala:50:14] output io_d_bits_denied, // @[SourceD.scala:50:14] output [127:0] io_d_bits_data, // @[SourceD.scala:50:14] output io_d_bits_corrupt, // @[SourceD.scala:50:14] input io_pb_pop_ready, // @[SourceD.scala:50:14] output io_pb_pop_valid, // @[SourceD.scala:50:14] output [5:0] io_pb_pop_bits_index, // @[SourceD.scala:50:14] output io_pb_pop_bits_last, // @[SourceD.scala:50:14] input [127:0] io_pb_beat_data, // @[SourceD.scala:50:14] input [15:0] io_pb_beat_mask, // @[SourceD.scala:50:14] input io_pb_beat_corrupt, // @[SourceD.scala:50:14] input io_rel_pop_ready, // @[SourceD.scala:50:14] output io_rel_pop_valid, // @[SourceD.scala:50:14] output [5:0] io_rel_pop_bits_index, // @[SourceD.scala:50:14] output io_rel_pop_bits_last, // @[SourceD.scala:50:14] input [127:0] io_rel_beat_data, // @[SourceD.scala:50:14] input io_rel_beat_corrupt, // @[SourceD.scala:50:14] input io_bs_radr_ready, // @[SourceD.scala:50:14] output io_bs_radr_valid, // @[SourceD.scala:50:14] output [2:0] io_bs_radr_bits_way, // @[SourceD.scala:50:14] output [9:0] io_bs_radr_bits_set, // @[SourceD.scala:50:14] output [1:0] io_bs_radr_bits_beat, // @[SourceD.scala:50:14] output [1:0] io_bs_radr_bits_mask, // @[SourceD.scala:50:14] input [127:0] io_bs_rdat_data, // @[SourceD.scala:50:14] input io_bs_wadr_ready, // @[SourceD.scala:50:14] output io_bs_wadr_valid, // @[SourceD.scala:50:14] output [2:0] io_bs_wadr_bits_way, // @[SourceD.scala:50:14] output [9:0] io_bs_wadr_bits_set, // @[SourceD.scala:50:14] output [1:0] io_bs_wadr_bits_beat, // @[SourceD.scala:50:14] output [1:0] io_bs_wadr_bits_mask, // @[SourceD.scala:50:14] output [127:0] io_bs_wdat_data, // @[SourceD.scala:50:14] input [9:0] io_evict_req_set, // @[SourceD.scala:50:14] input [2:0] io_evict_req_way, // @[SourceD.scala:50:14] output io_evict_safe, // @[SourceD.scala:50:14] input [9:0] io_grant_req_set, // @[SourceD.scala:50:14] input [2:0] io_grant_req_way, // @[SourceD.scala:50:14] output io_grant_safe // @[SourceD.scala:50:14] ); wire [127:0] _atomics_io_data_out; // @[SourceD.scala:258:23] wire _queue_io_enq_ready; // @[SourceD.scala:120:21] wire _queue_io_deq_valid; // @[SourceD.scala:120:21] wire [127:0] _queue_io_deq_bits_data; // @[SourceD.scala:120:21] wire io_req_valid_0 = io_req_valid; // @[SourceD.scala:48:7] wire io_req_bits_prio_0_0 = io_req_bits_prio_0; // @[SourceD.scala:48:7] wire io_req_bits_prio_1_0 = io_req_bits_prio_1; // @[SourceD.scala:48:7] wire io_req_bits_prio_2_0 = io_req_bits_prio_2; // @[SourceD.scala:48:7] wire io_req_bits_control_0 = io_req_bits_control; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_opcode_0 = io_req_bits_opcode; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_size_0 = io_req_bits_size; // @[SourceD.scala:48:7] wire [7:0] io_req_bits_source_0 = io_req_bits_source; // @[SourceD.scala:48:7] wire [12:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_offset_0 = io_req_bits_offset; // @[SourceD.scala:48:7] wire [5:0] io_req_bits_put_0 = io_req_bits_put; // @[SourceD.scala:48:7] wire [9:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceD.scala:48:7] wire [3:0] io_req_bits_sink_0 = io_req_bits_sink; // @[SourceD.scala:48:7] wire [2:0] io_req_bits_way_0 = io_req_bits_way; // @[SourceD.scala:48:7] wire io_req_bits_bad_0 = io_req_bits_bad; // @[SourceD.scala:48:7] wire io_d_ready_0 = io_d_ready; // @[SourceD.scala:48:7] wire io_pb_pop_ready_0 = io_pb_pop_ready; // @[SourceD.scala:48:7] wire [127:0] io_pb_beat_data_0 = io_pb_beat_data; // @[SourceD.scala:48:7] wire [15:0] io_pb_beat_mask_0 = io_pb_beat_mask; // @[SourceD.scala:48:7] wire io_pb_beat_corrupt_0 = io_pb_beat_corrupt; // @[SourceD.scala:48:7] wire io_rel_pop_ready_0 = io_rel_pop_ready; // @[SourceD.scala:48:7] wire [127:0] io_rel_beat_data_0 = io_rel_beat_data; // @[SourceD.scala:48:7] wire io_rel_beat_corrupt_0 = io_rel_beat_corrupt; // @[SourceD.scala:48:7] wire io_bs_radr_ready_0 = io_bs_radr_ready; // @[SourceD.scala:48:7] wire [127:0] io_bs_rdat_data_0 = io_bs_rdat_data; // @[SourceD.scala:48:7] wire io_bs_wadr_ready_0 = io_bs_wadr_ready; // @[SourceD.scala:48:7] wire [9:0] io_evict_req_set_0 = io_evict_req_set; // @[SourceD.scala:48:7] wire [2:0] io_evict_req_way_0 = io_evict_req_way; // @[SourceD.scala:48:7] wire [9:0] io_grant_req_set_0 = io_grant_req_set; // @[SourceD.scala:48:7] wire [2:0] io_grant_req_way_0 = io_grant_req_way; // @[SourceD.scala:48:7] wire io_bs_radr_bits_noop = 1'h0; // @[SourceD.scala:48:7] wire io_bs_wadr_bits_noop = 1'h0; // @[SourceD.scala:48:7] wire s1_mask_size = 1'h1; // @[Misc.scala:209:26] wire pre_s3_4_bypass_size = 1'h1; // @[Misc.scala:209:26] wire pre_s3_5_bypass_size = 1'h1; // @[Misc.scala:209:26] wire pre_s3_6_bypass_size = 1'h1; // @[Misc.scala:209:26] wire s1_2_bypass_size = 1'h1; // @[Misc.scala:209:26] wire s1_3_bypass_size = 1'h1; // @[Misc.scala:209:26] wire s1_4_bypass_size = 1'h1; // @[Misc.scala:209:26] wire [3:0] s1_mask_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_4_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_5_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] pre_s3_6_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_2_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_3_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [3:0] s1_4_bypass_sizeOH = 4'hF; // @[Misc.scala:202:81] wire [2:0] resp_opcode_0 = 3'h0; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_1 = 3'h0; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_7 = 3'h4; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_5 = 3'h2; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_2 = 3'h1; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_3 = 3'h1; // @[SourceD.scala:215:28] wire [2:0] resp_opcode_4 = 3'h1; // @[SourceD.scala:215:28] wire [15:0] _s2_pdata_raw_mask_T = 16'hFFFF; // @[SourceD.scala:161:64] wire _io_req_ready_T; // @[SourceD.scala:140:19] wire d_ready = io_d_ready_0; // @[SourceD.scala:48:7, :218:15] wire d_valid; // @[SourceD.scala:218:15] wire [2:0] d_bits_opcode; // @[SourceD.scala:218:15] wire [1:0] d_bits_param; // @[SourceD.scala:218:15] wire [2:0] d_bits_size; // @[SourceD.scala:218:15] wire [7:0] d_bits_source; // @[SourceD.scala:218:15] wire [3:0] d_bits_sink; // @[SourceD.scala:218:15] wire d_bits_denied; // @[SourceD.scala:218:15] wire [127:0] d_bits_data; // @[SourceD.scala:218:15] wire d_bits_corrupt; // @[SourceD.scala:218:15] wire _io_pb_pop_valid_T; // @[SourceD.scala:164:34] wire _io_rel_pop_valid_T_1; // @[SourceD.scala:167:35] wire s1_valid_r; // @[SourceD.scala:96:56] wire [2:0] s1_req_way; // @[SourceD.scala:88:19] wire [9:0] s1_req_set; // @[SourceD.scala:88:19] wire [1:0] s1_beat; // @[SourceD.scala:102:56] wire [1:0] s1_mask; // @[SourceD.scala:92:76] wire _io_bs_wadr_valid_T; // @[SourceD.scala:270:31] wire [1:0] _io_bs_wadr_bits_mask_T_30; // @[SourceD.scala:275:30] wire _io_evict_safe_T_22; // @[SourceD.scala:378:90] wire _io_grant_safe_T_22; // @[SourceD.scala:385:90] wire io_req_ready_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_opcode_0; // @[SourceD.scala:48:7] wire [1:0] io_d_bits_param_0; // @[SourceD.scala:48:7] wire [2:0] io_d_bits_size_0; // @[SourceD.scala:48:7] wire [7:0] io_d_bits_source_0; // @[SourceD.scala:48:7] wire [3:0] io_d_bits_sink_0; // @[SourceD.scala:48:7] wire io_d_bits_denied_0; // @[SourceD.scala:48:7] wire [127:0] io_d_bits_data_0; // @[SourceD.scala:48:7] wire io_d_bits_corrupt_0; // @[SourceD.scala:48:7] wire io_d_valid_0; // @[SourceD.scala:48:7] wire [5:0] io_pb_pop_bits_index_0; // @[SourceD.scala:48:7] wire io_pb_pop_bits_last_0; // @[SourceD.scala:48:7] wire io_pb_pop_valid_0; // @[SourceD.scala:48:7] wire [5:0] io_rel_pop_bits_index_0; // @[SourceD.scala:48:7] wire io_rel_pop_bits_last_0; // @[SourceD.scala:48:7] wire io_rel_pop_valid_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_radr_bits_way_0; // @[SourceD.scala:48:7] wire [9:0] io_bs_radr_bits_set_0; // @[SourceD.scala:48:7] wire [1:0] io_bs_radr_bits_beat_0; // @[SourceD.scala:48:7] wire [1:0] io_bs_radr_bits_mask_0; // @[SourceD.scala:48:7] wire io_bs_radr_valid_0; // @[SourceD.scala:48:7] wire [2:0] io_bs_wadr_bits_way_0; // @[SourceD.scala:48:7] wire [9:0] io_bs_wadr_bits_set_0; // @[SourceD.scala:48:7] wire [1:0] io_bs_wadr_bits_beat_0; // @[SourceD.scala:48:7] wire [1:0] io_bs_wadr_bits_mask_0; // @[SourceD.scala:48:7] wire io_bs_wadr_valid_0; // @[SourceD.scala:48:7] wire [127:0] io_bs_wdat_data_0; // @[SourceD.scala:48:7] wire io_evict_safe_0; // @[SourceD.scala:48:7] wire io_grant_safe_0; // @[SourceD.scala:48:7] wire _s1_valid_T_3; // @[SourceD.scala:141:38] wire s1_valid; // @[SourceD.scala:74:22] wire _s2_valid_T_2; // @[SourceD.scala:183:23] wire s2_valid; // @[SourceD.scala:75:22] wire _s3_valid_T_2; // @[SourceD.scala:241:23] wire s3_valid; // @[SourceD.scala:76:22] wire _s2_ready_T_4; // @[SourceD.scala:184:24] wire s2_ready; // @[SourceD.scala:77:22] wire _s3_ready_T_4; // @[SourceD.scala:242:24] wire s3_ready; // @[SourceD.scala:78:22] wire _s4_ready_T_5; // @[SourceD.scala:293:59] wire s4_ready; // @[SourceD.scala:79:22] reg busy; // @[SourceD.scala:84:21] reg s1_block_r; // @[SourceD.scala:85:27] reg [1:0] s1_counter; // @[SourceD.scala:86:27] wire _s1_req_reg_T = ~busy; // @[SourceD.scala:84:21, :87:43] wire _s1_req_reg_T_1 = _s1_req_reg_T & io_req_valid_0; // @[SourceD.scala:48:7, :87:{43,49}] reg s1_req_reg_prio_0; // @[SourceD.scala:87:29] reg s1_req_reg_prio_1; // @[SourceD.scala:87:29] reg s1_req_reg_prio_2; // @[SourceD.scala:87:29] reg s1_req_reg_control; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_opcode; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_param; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_size; // @[SourceD.scala:87:29] reg [7:0] s1_req_reg_source; // @[SourceD.scala:87:29] reg [12:0] s1_req_reg_tag; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_offset; // @[SourceD.scala:87:29] reg [5:0] s1_req_reg_put; // @[SourceD.scala:87:29] reg [9:0] s1_req_reg_set; // @[SourceD.scala:87:29] reg [3:0] s1_req_reg_sink; // @[SourceD.scala:87:29] reg [2:0] s1_req_reg_way; // @[SourceD.scala:87:29] reg s1_req_reg_bad; // @[SourceD.scala:87:29] wire _s1_req_T = ~busy; // @[SourceD.scala:84:21, :87:43, :88:20] wire s1_req_prio_0 = _s1_req_T ? io_req_bits_prio_0_0 : s1_req_reg_prio_0; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_prio_1 = _s1_req_T ? io_req_bits_prio_1_0 : s1_req_reg_prio_1; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_prio_2 = _s1_req_T ? io_req_bits_prio_2_0 : s1_req_reg_prio_2; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_control = _s1_req_T ? io_req_bits_control_0 : s1_req_reg_control; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_opcode = _s1_req_T ? io_req_bits_opcode_0 : s1_req_reg_opcode; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_param = _s1_req_T ? io_req_bits_param_0 : s1_req_reg_param; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [2:0] s1_req_size = _s1_req_T ? io_req_bits_size_0 : s1_req_reg_size; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [7:0] s1_req_source = _s1_req_T ? io_req_bits_source_0 : s1_req_reg_source; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [12:0] s1_req_tag = _s1_req_T ? io_req_bits_tag_0 : s1_req_reg_tag; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_offset = _s1_req_T ? io_req_bits_offset_0 : s1_req_reg_offset; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [5:0] s1_req_put = _s1_req_T ? io_req_bits_put_0 : s1_req_reg_put; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign s1_req_set = _s1_req_T ? io_req_bits_set_0 : s1_req_reg_set; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire [3:0] s1_req_sink = _s1_req_T ? io_req_bits_sink_0 : s1_req_reg_sink; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign s1_req_way = _s1_req_T ? io_req_bits_way_0 : s1_req_reg_way; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] wire s1_req_bad = _s1_req_T ? io_req_bits_bad_0 : s1_req_reg_bad; // @[SourceD.scala:48:7, :87:29, :88:{19,20}] assign io_bs_radr_bits_set_0 = s1_req_set; // @[SourceD.scala:48:7, :88:19] assign io_bs_radr_bits_way_0 = s1_req_way; // @[SourceD.scala:48:7, :88:19] wire [1:0] _s1_x_bypass_T_1; // @[SourceD.scala:360:44] wire [1:0] s1_x_bypass; // @[SourceD.scala:89:25] wire _T_1 = busy \| io_req_valid_0; // @[SourceD.scala:48:7, :84:21, :90:40] wire _s1_latch_bypass_T; // @[SourceD.scala:90:40] assign _s1_latch_bypass_T = _T_1; // @[SourceD.scala:90:40] wire _s1_valid_r_T; // @[SourceD.scala:96:26] assign _s1_valid_r_T = _T_1; // @[SourceD.scala:90:40, :96:26] wire _s1_valid_T; // @[SourceD.scala:141:21] assign _s1_valid_T = _T_1; // @[SourceD.scala:90:40, :141:21] wire _s1_latch_bypass_T_1 = ~_s1_latch_bypass_T; // @[SourceD.scala:90:{33,40}] wire _s1_latch_bypass_T_2 = _s1_latch_bypass_T_1 \| s2_ready; // @[SourceD.scala:77:22, :90:{33,57}] reg s1_latch_bypass; // @[SourceD.scala:90:32] reg [1:0] s1_bypass_r; // @[SourceD.scala:91:62] wire [1:0] s1_bypass = s1_latch_bypass ? s1_x_bypass : s1_bypass_r; // @[SourceD.scala:89:25, :90:32, :91:{22,62}] wire [3:0] _s1_mask_sizeOH_T = {1'h0, s1_req_size}; // @[Misc.scala:202:34] wire [1:0] s1_mask_sizeOH_shiftAmount = _s1_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _s1_mask_sizeOH_T_1 = 4'h1 << s1_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _s1_mask_sizeOH_T_2 = _s1_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire s1_mask_sub_0_1 = s1_req_size[2]; // @[Misc.scala:206:21] wire s1_mask_bit = s1_req_offset[3]; // @[Misc.scala:210:26] wire s1_mask_eq_1 = s1_mask_bit; // @[Misc.scala:210:26, :214:27] wire s1_mask_nbit = ~s1_mask_bit; // @[Misc.scala:210:26, :211:20] wire s1_mask_eq = s1_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _s1_mask_acc_T = s1_mask_eq; // @[Misc.scala:214:27, :215:38] wire s1_mask_acc = s1_mask_sub_0_1 \| _s1_mask_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _s1_mask_acc_T_1 = s1_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire s1_mask_acc_1 = s1_mask_sub_0_1 \| _s1_mask_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire [1:0] _s1_mask_T = {s1_mask_acc_1, s1_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] _s1_mask_T_1 = ~s1_bypass; // @[SourceD.scala:91:22, :92:78] assign s1_mask = _s1_mask_T & _s1_mask_T_1; // @[Misc.scala:222:10] assign io_bs_radr_bits_mask_0 = s1_mask; // @[SourceD.scala:48:7, :92:76] wire _GEN = s1_req_opcode == 3'h6; // @[SourceD.scala:88:19, :93:33] wire _s1_grant_T; // @[SourceD.scala:93:33] assign _s1_grant_T = _GEN; // @[SourceD.scala:93:33] wire _s1_single_T_2; // @[SourceD.scala:98:89] assign _s1_single_T_2 = _GEN; // @[SourceD.scala:93:33, :98:89] wire _s1_grant_T_1 = s1_req_param == 3'h2; // @[SourceD.scala:88:19, :93:66] wire _s1_grant_T_2 = _s1_grant_T & _s1_grant_T_1; // @[SourceD.scala:93:{33,50,66}] wire _s1_grant_T_3 = &s1_req_opcode; // @[SourceD.scala:88:19, :93:93] wire s1_grant = _s1_grant_T_2 \| _s1_grant_T_3; // @[SourceD.scala:93:{50,76,93}] wire _s1_need_r_T = \|s1_mask; // @[SourceD.scala:92:76, :94:27] wire _s1_need_r_T_1 = _s1_need_r_T & s1_req_prio_0; // @[SourceD.scala:88:19, :94:{27,31}] wire _s1_need_r_T_2 = s1_req_opcode != 3'h5; // @[SourceD.scala:88:19, :94:66] wire _s1_need_r_T_3 = _s1_need_r_T_1 & _s1_need_r_T_2; // @[SourceD.scala:94:{31,49,66}] wire _s1_need_r_T_4 = ~s1_grant; // @[SourceD.scala:93:76, :94:78] wire _s1_need_r_T_5 = _s1_need_r_T_3 & _s1_need_r_T_4; // @[SourceD.scala:94:{49,75,78}] wire _s1_need_r_T_6 = \|s1_req_opcode; // @[SourceD.scala:88:19, :95:34] wire _s1_need_r_T_7 = s1_req_size < 3'h3; // @[SourceD.scala:88:19, :95:65] wire _s1_need_r_T_8 = _s1_need_r_T_6 \| _s1_need_r_T_7; // @[SourceD.scala:95:{34,50,65}] wire s1_need_r = _s1_need_r_T_5 & _s1_need_r_T_8; // @[SourceD.scala:94:{75,88}, :95:50] wire _s1_valid_r_T_1 = _s1_valid_r_T & s1_need_r; // @[SourceD.scala:94:88, :96:{26,43}] wire _s1_valid_r_T_2 = ~s1_block_r; // @[SourceD.scala:85:27, :96:59] assign s1_valid_r = _s1_valid_r_T_1 & _s1_valid_r_T_2; // @[SourceD.scala:96:{43,56,59}] assign io_bs_radr_valid_0 = s1_valid_r; // @[SourceD.scala:48:7, :96:56] wire _s1_need_pb_T = s1_req_opcode[2]; // @[SourceD.scala:88:19, :97:54] wire _s1_need_pb_T_1 = ~_s1_need_pb_T; // @[SourceD.scala:97:{40,54}] wire _s1_need_pb_T_2 = s1_req_opcode[0]; // @[SourceD.scala:88:19, :97:72] wire s1_need_pb = s1_req_prio_0 ? _s1_need_pb_T_1 : _s1_need_pb_T_2; // @[SourceD.scala:88:19, :97:{23,40,72}] wire _s1_single_T = s1_req_opcode == 3'h5; // @[SourceD.scala:88:19, :98:53] wire _s1_single_T_1 = _s1_single_T \| s1_grant; // @[SourceD.scala:93:76, :98:{53,62}] wire s1_single = s1_req_prio_0 ? _s1_single_T_1 : _s1_single_T_2; // @[SourceD.scala:88:19, :98:{22,62,89}] wire s1_retires = ~s1_single; // @[SourceD.scala:98:22, :99:20] wire [12:0] _s1_beats1_T = 13'h3F << s1_req_size; // @[package.scala:243:71] wire [5:0] _s1_beats1_T_1 = _s1_beats1_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _s1_beats1_T_2 = ~_s1_beats1_T_1; // @[package.scala:243:{46,76}] wire [1:0] _s1_beats1_T_3 = _s1_beats1_T_2[5:4]; // @[package.scala:243:46] wire [1:0] s1_beats1 = s1_single ? 2'h0 : _s1_beats1_T_3; // @[SourceD.scala:98:22, :101:{22,95}] wire [1:0] _s1_beat_T = s1_req_offset[5:4]; // @[SourceD.scala:88:19, :102:32] assign s1_beat = _s1_beat_T \| s1_counter; // @[SourceD.scala:86:27, :102:{32,56}] assign io_bs_radr_bits_beat_0 = s1_beat; // @[SourceD.scala:48:7, :102:56] wire s1_last = s1_counter == s1_beats1; // @[SourceD.scala:86:27, :101:22, :103:28] wire s1_first = s1_counter == 2'h0; // @[SourceD.scala:86:27, :104:29] wire _queue_io_enq_valid_T = io_bs_radr_ready_0 & io_bs_radr_valid_0; // @[Decoupled.scala:51:35] reg queue_io_enq_valid_REG; // @[SourceD.scala:121:40] reg queue_io_enq_valid_REG_1; // @[SourceD.scala:121:32] wire s2_latch = s1_valid & s2_ready; // @[SourceD.scala:74:22, :77:22, :129:18, :146:27] wire [2:0] _s1_counter_T = {1'h0, s1_counter} + 3'h1; // @[SourceD.scala:86:27, :130:30] wire [1:0] _s1_counter_T_1 = _s1_counter_T[1:0]; // @[SourceD.scala:130:30] assign _io_req_ready_T = ~busy; // @[SourceD.scala:84:21, :87:43, :140:19] assign io_req_ready_0 = _io_req_ready_T; // @[SourceD.scala:48:7, :140:19] wire _s1_valid_T_1 = ~s1_valid_r; // @[SourceD.scala:96:56, :141:42] wire _s1_valid_T_2 = _s1_valid_T_1 \| io_bs_radr_ready_0; // @[SourceD.scala:48:7, :141:{42,54}] assign _s1_valid_T_3 = _s1_valid_T & _s1_valid_T_2; // @[SourceD.scala:141:{21,38,54}] assign s1_valid = _s1_valid_T_3; // @[SourceD.scala:74:22, :141:38] reg s2_full; // @[SourceD.scala:147:24] reg s2_valid_pb; // @[SourceD.scala:148:28] reg [1:0] s2_beat; // @[SourceD.scala:149:26] reg [1:0] s2_bypass; // @[SourceD.scala:150:28] reg s2_req_prio_0; // @[SourceD.scala:151:25] reg s2_req_prio_1; // @[SourceD.scala:151:25] reg s2_req_prio_2; // @[SourceD.scala:151:25] reg s2_req_control; // @[SourceD.scala:151:25] reg [2:0] s2_req_opcode; // @[SourceD.scala:151:25] reg [2:0] s2_req_param; // @[SourceD.scala:151:25] reg [2:0] s2_req_size; // @[SourceD.scala:151:25] reg [7:0] s2_req_source; // @[SourceD.scala:151:25] reg [12:0] s2_req_tag; // @[SourceD.scala:151:25] reg [5:0] s2_req_offset; // @[SourceD.scala:151:25] reg [5:0] s2_req_put; // @[SourceD.scala:151:25] assign io_pb_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25] assign io_rel_pop_bits_index_0 = s2_req_put; // @[SourceD.scala:48:7, :151:25] reg [9:0] s2_req_set; // @[SourceD.scala:151:25] reg [3:0] s2_req_sink; // @[SourceD.scala:151:25] reg [2:0] s2_req_way; // @[SourceD.scala:151:25] reg s2_req_bad; // @[SourceD.scala:151:25] reg s2_last; // @[SourceD.scala:152:26] assign io_pb_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26] assign io_rel_pop_bits_last_0 = s2_last; // @[SourceD.scala:48:7, :152:26] reg s2_need_r; // @[SourceD.scala:153:28] reg s2_need_pb; // @[SourceD.scala:154:29] reg s2_retires; // @[SourceD.scala:155:29] wire _s2_need_d_T = ~s1_need_pb; // @[SourceD.scala:97:23, :156:29] wire _s2_need_d_T_1 = _s2_need_d_T \| s1_first; // @[SourceD.scala:104:29, :156:{29,41}] reg s2_need_d; // @[SourceD.scala:156:28] wire [127:0] _s2_pdata_raw_data_T; // @[SourceD.scala:160:30] wire [15:0] _s2_pdata_raw_mask_T_1; // @[SourceD.scala:161:30] wire _s2_pdata_raw_corrupt_T; // @[SourceD.scala:162:30] wire [127:0] s2_pdata_raw_data; // @[SourceD.scala:157:26] wire [15:0] s2_pdata_raw_mask; // @[SourceD.scala:157:26] wire s2_pdata_raw_corrupt; // @[SourceD.scala:157:26] reg [127:0] s2_pdata_r_data; // @[package.scala:88:63] reg [15:0] s2_pdata_r_mask; // @[package.scala:88:63] reg s2_pdata_r_corrupt; // @[package.scala:88:63] wire [127:0] s2_pdata_data = s2_valid_pb ? s2_pdata_raw_data : s2_pdata_r_data; // @[package.scala:88:{42,63}] wire [15:0] s2_pdata_mask = s2_valid_pb ? s2_pdata_raw_mask : s2_pdata_r_mask; // @[package.scala:88:{42,63}] wire s2_pdata_corrupt = s2_valid_pb ? s2_pdata_raw_corrupt : s2_pdata_r_corrupt; // @[package.scala:88:{42,63}] assign _s2_pdata_raw_data_T = s2_req_prio_0 ? io_pb_beat_data_0 : io_rel_beat_data_0; // @[SourceD.scala:48:7, :151:25, :160:30] assign s2_pdata_raw_data = _s2_pdata_raw_data_T; // @[SourceD.scala:157:26, :160:30] assign _s2_pdata_raw_mask_T_1 = s2_req_prio_0 ? io_pb_beat_mask_0 : 16'hFFFF; // @[SourceD.scala:48:7, :151:25, :161:30] assign s2_pdata_raw_mask = _s2_pdata_raw_mask_T_1; // @[SourceD.scala:157:26, :161:30] assign _s2_pdata_raw_corrupt_T = s2_req_prio_0 ? io_pb_beat_corrupt_0 : io_rel_beat_corrupt_0; // @[SourceD.scala:48:7, :151:25, :162:30] assign s2_pdata_raw_corrupt = _s2_pdata_raw_corrupt_T; // @[SourceD.scala:157:26, :162:30] assign _io_pb_pop_valid_T = s2_valid_pb & s2_req_prio_0; // @[SourceD.scala:148:28, :151:25, :164:34] assign io_pb_pop_valid_0 = _io_pb_pop_valid_T; // @[SourceD.scala:48:7, :164:34] wire _io_rel_pop_valid_T = ~s2_req_prio_0; // @[SourceD.scala:151:25, :167:38] assign _io_rel_pop_valid_T_1 = s2_valid_pb & _io_rel_pop_valid_T; // @[SourceD.scala:148:28, :167:{35,38}] assign io_rel_pop_valid_0 = _io_rel_pop_valid_T_1; // @[SourceD.scala:48:7, :167:35] wire pb_ready = s2_req_prio_0 ? io_pb_pop_ready_0 : io_rel_pop_ready_0; // @[SourceD.scala:48:7, :151:25, :175:21] wire s3_latch = s2_valid & s3_ready; // @[SourceD.scala:75:22, :78:22, :177:18, :189:27] wire _s2_valid_T = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27] wire _s2_valid_T_1 = _s2_valid_T \| pb_ready; // @[SourceD.scala:175:21, :183:{27,40}] assign _s2_valid_T_2 = s2_full & _s2_valid_T_1; // @[SourceD.scala:147:24, :183:{23,40}] assign s2_valid = _s2_valid_T_2; // @[SourceD.scala:75:22, :183:23] wire _s2_ready_T = ~s2_full; // @[SourceD.scala:147:24, :184:15] wire _s2_ready_T_1 = ~s2_valid_pb; // @[SourceD.scala:148:28, :183:27, :184:41] wire _s2_ready_T_2 = _s2_ready_T_1 \| pb_ready; // @[SourceD.scala:175:21, :184:{41,54}] wire _s2_ready_T_3 = s3_ready & _s2_ready_T_2; // @[SourceD.scala:78:22, :184:{37,54}] assign _s2_ready_T_4 = _s2_ready_T \| _s2_ready_T_3; // @[SourceD.scala:184:{15,24,37}] assign s2_ready = _s2_ready_T_4; // @[SourceD.scala:77:22, :184:24] reg s3_full; // @[SourceD.scala:190:24] reg s3_valid_d; // @[SourceD.scala:191:27] assign d_valid = s3_valid_d; // @[SourceD.scala:191:27, :218:15] reg [1:0] s3_beat; // @[SourceD.scala:192:26] wire [1:0] pre_s3_beat = s3_latch ? s2_beat : s3_beat; // @[SourceD.scala:149:26, :189:27, :192:26, :319:24] reg [1:0] s3_bypass; // @[SourceD.scala:193:28] reg s3_req_prio_0; // @[SourceD.scala:194:25] reg s3_req_prio_1; // @[SourceD.scala:194:25] reg s3_req_prio_2; // @[SourceD.scala:194:25] reg s3_req_control; // @[SourceD.scala:194:25] reg [2:0] s3_req_opcode; // @[SourceD.scala:194:25] reg [2:0] s3_req_param; // @[SourceD.scala:194:25] reg [2:0] s3_req_size; // @[SourceD.scala:194:25] assign d_bits_size = s3_req_size; // @[SourceD.scala:194:25, :218:15] reg [7:0] s3_req_source; // @[SourceD.scala:194:25] assign d_bits_source = s3_req_source; // @[SourceD.scala:194:25, :218:15] reg [12:0] s3_req_tag; // @[SourceD.scala:194:25] reg [5:0] s3_req_offset; // @[SourceD.scala:194:25] reg [5:0] s3_req_put; // @[SourceD.scala:194:25] reg [9:0] s3_req_set; // @[SourceD.scala:194:25] reg [3:0] s3_req_sink; // @[SourceD.scala:194:25] assign d_bits_sink = s3_req_sink; // @[SourceD.scala:194:25, :218:15] reg [2:0] s3_req_way; // @[SourceD.scala:194:25] reg s3_req_bad; // @[SourceD.scala:194:25] assign d_bits_denied = s3_req_bad; // @[SourceD.scala:194:25, :218:15] wire pre_s3_req_prio_0 = s3_latch ? s2_req_prio_0 : s3_req_prio_0; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_prio_1 = s3_latch ? s2_req_prio_1 : s3_req_prio_1; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_prio_2 = s3_latch ? s2_req_prio_2 : s3_req_prio_2; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_control = s3_latch ? s2_req_control : s3_req_control; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_opcode = s3_latch ? s2_req_opcode : s3_req_opcode; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_param = s3_latch ? s2_req_param : s3_req_param; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_size = s3_latch ? s2_req_size : s3_req_size; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [7:0] pre_s3_req_source = s3_latch ? s2_req_source : s3_req_source; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [12:0] pre_s3_req_tag = s3_latch ? s2_req_tag : s3_req_tag; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_offset = s3_latch ? s2_req_offset : s3_req_offset; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [5:0] pre_s3_req_put = s3_latch ? s2_req_put : s3_req_put; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [9:0] pre_s3_req_set = s3_latch ? s2_req_set : s3_req_set; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [3:0] pre_s3_req_sink = s3_latch ? s2_req_sink : s3_req_sink; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] pre_s3_req_way = s3_latch ? s2_req_way : s3_req_way; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire pre_s3_req_bad = s3_latch ? s2_req_bad : s3_req_bad; // @[SourceD.scala:151:25, :189:27, :194:25, :315:24] wire [2:0] s3_adjusted_opcode = s3_req_bad ? 3'h4 : s3_req_opcode; // @[SourceD.scala:194:25, :195:31] reg s3_last; // @[SourceD.scala:196:26] reg [127:0] s3_pdata_data; // @[SourceD.scala:197:27] reg [15:0] s3_pdata_mask; // @[SourceD.scala:197:27] reg s3_pdata_corrupt; // @[SourceD.scala:197:27] reg s3_need_pb; // @[SourceD.scala:198:29] reg s3_retires; // @[SourceD.scala:199:29] reg s3_need_r; // @[SourceD.scala:200:28] wire _s3_acq_T = s3_req_opcode == 3'h6; // @[SourceD.scala:194:25, :202:30] wire _s3_acq_T_1 = &s3_req_opcode; // @[SourceD.scala:194:25, :202:64] wire s3_acq = _s3_acq_T \| _s3_acq_T_1; // @[SourceD.scala:202:{30,47,64}] wire [127:0] _s3_bypass_data_T_26; // @[package.scala:45:27] wire [127:0] s3_bypass_data; // @[SourceD.scala:206:28] wire _s3_rdata_T = s3_bypass[0]; // @[SourceD.scala:193:28, :208:78] wire _s3_rdata_T_1 = s3_bypass[1]; // @[SourceD.scala:193:28, :208:78] wire [63:0] _s3_rdata_T_2 = s3_bypass_data[63:0]; // @[SourceD.scala:206:28, :207:78] wire [63:0] _s3_rdata_T_3 = s3_bypass_data[127:64]; // @[SourceD.scala:206:28, :207:78] wire [63:0] _s3_rdata_T_4 = _queue_io_deq_bits_data[63:0]; // @[SourceD.scala:120:21, :207:78] wire [63:0] _s3_rdata_T_5 = _queue_io_deq_bits_data[127:64]; // @[SourceD.scala:120:21, :207:78] wire [63:0] _s3_rdata_T_6 = _s3_rdata_T ? _s3_rdata_T_2 : _s3_rdata_T_4; // @[SourceD.scala:207:78, :208:78, :210:75] wire [63:0] _s3_rdata_T_7 = _s3_rdata_T_1 ? _s3_rdata_T_3 : _s3_rdata_T_5; // @[SourceD.scala:207:78, :208:78, :210:75] wire [127:0] s3_rdata = {_s3_rdata_T_7, _s3_rdata_T_6}; // @[package.scala:45:27] assign d_bits_data = s3_rdata; // @[package.scala:45:27] wire _grant_T = s3_req_param == 3'h2; // @[SourceD.scala:194:25, :214:32] wire [2:0] grant = {2'h2, ~_grant_T}; // @[SourceD.scala:214:{18,32}] wire [2:0] resp_opcode_6 = grant; // @[SourceD.scala:214:18, :215:28] assign io_d_valid_0 = d_valid; // @[SourceD.scala:48:7, :218:15] wire [2:0] _d_bits_opcode_T; // @[SourceD.scala:222:24] assign io_d_bits_opcode_0 = d_bits_opcode; // @[SourceD.scala:48:7, :218:15] wire [1:0] _d_bits_param_T_3; // @[SourceD.scala:223:24] assign io_d_bits_param_0 = d_bits_param; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_size_0 = d_bits_size; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_source_0 = d_bits_source; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_sink_0 = d_bits_sink; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_denied_0 = d_bits_denied; // @[SourceD.scala:48:7, :218:15] assign io_d_bits_data_0 = d_bits_data; // @[SourceD.scala:48:7, :218:15] wire _d_bits_corrupt_T_1; // @[SourceD.scala:229:32] assign io_d_bits_corrupt_0 = d_bits_corrupt; // @[SourceD.scala:48:7, :218:15] wire [7:0][2:0] _GEN_0 = {{3'h4}, {resp_opcode_6}, {3'h2}, {3'h1}, {3'h1}, {3'h1}, {3'h0}, {3'h0}}; // @[SourceD.scala:215:28, :222:24] assign _d_bits_opcode_T = s3_req_prio_0 ? _GEN_0[s3_req_opcode] : 3'h6; // @[SourceD.scala:194:25, :222:24] assign d_bits_opcode = _d_bits_opcode_T; // @[SourceD.scala:218:15, :222:24] wire _d_bits_param_T = s3_req_prio_0 & s3_acq; // @[SourceD.scala:194:25, :202:47, :223:40] wire _d_bits_param_T_1 = \|s3_req_param; // @[SourceD.scala:194:25, :223:68] wire [1:0] _d_bits_param_T_2 = {1'h0, ~_d_bits_param_T_1}; // @[SourceD.scala:223:{54,68}] assign _d_bits_param_T_3 = _d_bits_param_T ? _d_bits_param_T_2 : 2'h0; // @[SourceD.scala:223:{24,40,54}] assign d_bits_param = _d_bits_param_T_3; // @[SourceD.scala:218:15, :223:24] wire _d_bits_corrupt_T = d_bits_opcode[0]; // @[SourceD.scala:218:15, :229:48] assign _d_bits_corrupt_T_1 = s3_req_bad & _d_bits_corrupt_T; // @[SourceD.scala:194:25, :229:{32,48}] assign d_bits_corrupt = _d_bits_corrupt_T_1; // @[SourceD.scala:218:15, :229:32] wire _queue_io_deq_ready_T = s3_valid & s4_ready; // @[SourceD.scala:76:22, :79:22, :231:34] wire _queue_io_deq_ready_T_1 = _queue_io_deq_ready_T & s3_need_r; // @[SourceD.scala:200:28, :231:{34,46}] wire _s3_valid_T = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27] wire _s3_valid_T_1 = _s3_valid_T \| d_ready; // @[SourceD.scala:218:15, :241:{27,39}] assign _s3_valid_T_2 = s3_full & _s3_valid_T_1; // @[SourceD.scala:190:24, :241:{23,39}] assign s3_valid = _s3_valid_T_2; // @[SourceD.scala:76:22, :241:23] wire _s3_ready_T = ~s3_full; // @[SourceD.scala:190:24, :232:11, :242:15] wire _s3_ready_T_1 = ~s3_valid_d; // @[SourceD.scala:191:27, :241:27, :242:41] wire _s3_ready_T_2 = _s3_ready_T_1 \| d_ready; // @[SourceD.scala:218:15, :242:{41,53}] wire _s3_ready_T_3 = s4_ready & _s3_ready_T_2; // @[SourceD.scala:79:22, :242:{37,53}] assign _s3_ready_T_4 = _s3_ready_T \| _s3_ready_T_3; // @[SourceD.scala:242:{15,24,37}] assign s3_ready = _s3_ready_T_4; // @[SourceD.scala:78:22, :242:24] wire _s4_latch_T = s3_valid & s3_retires; // @[SourceD.scala:76:22, :199:29, :247:27] wire s4_latch = _s4_latch_T & s4_ready; // @[SourceD.scala:79:22, :247:{27,41}] reg s4_full; // @[SourceD.scala:248:24] reg [1:0] s4_beat; // @[SourceD.scala:249:26] assign io_bs_wadr_bits_beat_0 = s4_beat; // @[SourceD.scala:48:7, :249:26] wire [1:0] pre_s4_beat = s4_latch ? s3_beat : s4_beat; // @[SourceD.scala:192:26, :247:41, :249:26, :320:24] reg s4_need_r; // @[SourceD.scala:250:28] reg s4_need_bs; // @[SourceD.scala:251:29] reg s4_need_pb; // @[SourceD.scala:252:29] reg s4_req_prio_0; // @[SourceD.scala:253:25] reg s4_req_prio_1; // @[SourceD.scala:253:25] reg s4_req_prio_2; // @[SourceD.scala:253:25] reg s4_req_control; // @[SourceD.scala:253:25] reg [2:0] s4_req_opcode; // @[SourceD.scala:253:25] reg [2:0] s4_req_param; // @[SourceD.scala:253:25] reg [2:0] s4_req_size; // @[SourceD.scala:253:25] reg [7:0] s4_req_source; // @[SourceD.scala:253:25] reg [12:0] s4_req_tag; // @[SourceD.scala:253:25] reg [5:0] s4_req_offset; // @[SourceD.scala:253:25] reg [5:0] s4_req_put; // @[SourceD.scala:253:25] reg [9:0] s4_req_set; // @[SourceD.scala:253:25] assign io_bs_wadr_bits_set_0 = s4_req_set; // @[SourceD.scala:48:7, :253:25] reg [3:0] s4_req_sink; // @[SourceD.scala:253:25] reg [2:0] s4_req_way; // @[SourceD.scala:253:25] assign io_bs_wadr_bits_way_0 = s4_req_way; // @[SourceD.scala:48:7, :253:25] reg s4_req_bad; // @[SourceD.scala:253:25] wire pre_s4_req_prio_0 = s4_latch ? s3_req_prio_0 : s4_req_prio_0; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_prio_1 = s4_latch ? s3_req_prio_1 : s4_req_prio_1; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_prio_2 = s4_latch ? s3_req_prio_2 : s4_req_prio_2; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_control = s4_latch ? s3_req_control : s4_req_control; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_opcode = s4_latch ? s3_req_opcode : s4_req_opcode; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_param = s4_latch ? s3_req_param : s4_req_param; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_size = s4_latch ? s3_req_size : s4_req_size; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [7:0] pre_s4_req_source = s4_latch ? s3_req_source : s4_req_source; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [12:0] pre_s4_req_tag = s4_latch ? s3_req_tag : s4_req_tag; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_offset = s4_latch ? s3_req_offset : s4_req_offset; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [5:0] pre_s4_req_put = s4_latch ? s3_req_put : s4_req_put; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [9:0] pre_s4_req_set = s4_latch ? s3_req_set : s4_req_set; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [3:0] pre_s4_req_sink = s4_latch ? s3_req_sink : s4_req_sink; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire [2:0] pre_s4_req_way = s4_latch ? s3_req_way : s4_req_way; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] wire pre_s4_req_bad = s4_latch ? s3_req_bad : s4_req_bad; // @[SourceD.scala:194:25, :247:41, :253:25, :316:24] reg [2:0] s4_adjusted_opcode; // @[SourceD.scala:254:37] reg [127:0] s4_pdata_data; // @[SourceD.scala:255:27] reg [15:0] s4_pdata_mask; // @[SourceD.scala:255:27] reg s4_pdata_corrupt; // @[SourceD.scala:255:27] reg [127:0] s4_rdata; // @[SourceD.scala:256:27] assign _io_bs_wadr_valid_T = s4_full & s4_need_bs; // @[SourceD.scala:248:24, :251:29, :270:31] assign io_bs_wadr_valid_0 = _io_bs_wadr_valid_T; // @[SourceD.scala:48:7, :270:31] wire _io_bs_wadr_bits_mask_T = s4_pdata_mask[0]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_1 = s4_pdata_mask[1]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_2 = s4_pdata_mask[2]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_3 = s4_pdata_mask[3]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_4 = s4_pdata_mask[4]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_5 = s4_pdata_mask[5]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_6 = s4_pdata_mask[6]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_7 = s4_pdata_mask[7]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_8 = s4_pdata_mask[8]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_9 = s4_pdata_mask[9]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_10 = s4_pdata_mask[10]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_11 = s4_pdata_mask[11]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_12 = s4_pdata_mask[12]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_13 = s4_pdata_mask[13]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_14 = s4_pdata_mask[14]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_15 = s4_pdata_mask[15]; // @[SourceD.scala:255:27, :275:45] wire _io_bs_wadr_bits_mask_T_16 = _io_bs_wadr_bits_mask_T \| _io_bs_wadr_bits_mask_T_1; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_17 = _io_bs_wadr_bits_mask_T_16 \| _io_bs_wadr_bits_mask_T_2; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_18 = _io_bs_wadr_bits_mask_T_17 \| _io_bs_wadr_bits_mask_T_3; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_19 = _io_bs_wadr_bits_mask_T_18 \| _io_bs_wadr_bits_mask_T_4; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_20 = _io_bs_wadr_bits_mask_T_19 \| _io_bs_wadr_bits_mask_T_5; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_21 = _io_bs_wadr_bits_mask_T_20 \| _io_bs_wadr_bits_mask_T_6; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_22 = _io_bs_wadr_bits_mask_T_21 \| _io_bs_wadr_bits_mask_T_7; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_23 = _io_bs_wadr_bits_mask_T_8 \| _io_bs_wadr_bits_mask_T_9; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_24 = _io_bs_wadr_bits_mask_T_23 \| _io_bs_wadr_bits_mask_T_10; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_25 = _io_bs_wadr_bits_mask_T_24 \| _io_bs_wadr_bits_mask_T_11; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_26 = _io_bs_wadr_bits_mask_T_25 \| _io_bs_wadr_bits_mask_T_12; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_27 = _io_bs_wadr_bits_mask_T_26 \| _io_bs_wadr_bits_mask_T_13; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_28 = _io_bs_wadr_bits_mask_T_27 \| _io_bs_wadr_bits_mask_T_14; // @[SourceD.scala:275:{45,87}] wire _io_bs_wadr_bits_mask_T_29 = _io_bs_wadr_bits_mask_T_28 \| _io_bs_wadr_bits_mask_T_15; // @[SourceD.scala:275:{45,87}] assign _io_bs_wadr_bits_mask_T_30 = {_io_bs_wadr_bits_mask_T_29, _io_bs_wadr_bits_mask_T_22}; // @[SourceD.scala:275:{30,87}] assign io_bs_wadr_bits_mask_0 = _io_bs_wadr_bits_mask_T_30; // @[SourceD.scala:48:7, :275:30]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_213( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_389 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File util.scala: //**************************************************************************** // Copyright (c) 2015 - 2019, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Utility Functions //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.util import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util.{Str} import org.chipsalliance.cde.config.{Parameters} import freechips.rocketchip.tile.{TileKey} import boom.v4.common.{MicroOp} import boom.v4.exu.{BrUpdateInfo} / * Object to XOR fold a input register of fullLength into a compressedLength. / object Fold { def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = { val clen = compressedLength val hlen = fullLength if (hlen <= clen) { input } else { var res = 0.U(clen.W) var remaining = input.asUInt for (i <- 0 to hlen-1 by clen) { val len = if (i + clen > hlen ) (hlen - i) else clen require(len > 0) res = res(clen-1,0) ^ remaining(len-1,0) remaining = remaining >> len.U } res } } } /* * Object to check if MicroOp was killed due to a branch mispredict. * Uses "Fast" branch masks / object IsKilledByBranch { def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = { return apply(brupdate, flush, uop.br_mask) } def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = { return maskMatch(brupdate.b1.mispredict_mask, uop_mask) \|\| flush } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = { return apply(brupdate, flush, bundle.uop) } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = { return apply(brupdate, flush, bundle.bits) } } /* * Object to return new MicroOp with a new BR mask given a MicroOp mask * and old BR mask. / object GetNewUopAndBrMask { def apply(uop: MicroOp, brupdate: BrUpdateInfo) (implicit p: Parameters): MicroOp = { val newuop = WireInit(uop) newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask newuop } } /* * Object to return a BR mask given a MicroOp mask and old BR mask. / object GetNewBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = { return uop.br_mask & ~brupdate.b1.resolve_mask } def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = { return br_mask & ~brupdate.b1.resolve_mask } } object UpdateBrMask { def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = { val out = WireInit(uop) out.br_mask := GetNewBrMask(brupdate, uop) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = { val out = WireInit(bundle) out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask) out } def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = { val out = WireInit(bundle) out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask) out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask) out } } /* * Object to check if at least 1 bit matches in two masks / object maskMatch { def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U } /* * Object to clear one bit in a mask given an index / object clearMaskBit { def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0) } /* * Object to shift a register over by one bit and concat a new one / object PerformShiftRegister { def apply(reg_val: UInt, new_bit: Bool): UInt = { reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt reg_val } } /* * Object to shift a register over by one bit, wrapping the top bit around to the bottom * (XOR'ed with a new-bit), and evicting a bit at index HLEN. * This is used to simulate a longer HLEN-width shift register that is folded * down to a compressed CLEN. / object PerformCircularShiftRegister { def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = { val carry = csr(clen-1) val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U) newval } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapAdd { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, amt: UInt, n: Int): UInt = { if (isPow2(n)) { (value + amt)(log2Ceil(n)-1,0) } else { val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt) Mux(sum >= n.U, sum - n.U, sum) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapSub { // "n" is the number of increments, so we wrap to n-1. def apply(value: UInt, amt: Int, n: Int): UInt = { if (isPow2(n)) { (value - amt.U)(log2Ceil(n)-1,0) } else { val v = Cat(0.U(1.W), value) val b = Cat(0.U(1.W), amt.U) Mux(value >= amt.U, value - amt.U, n.U - amt.U + value) } } } /* * Object to increment an input value, wrapping it if * necessary. / object WrapInc { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value + 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === (n-1).U) Mux(wrap, 0.U, value + 1.U) } } } /* * Object to decrement an input value, wrapping it if * necessary. / object WrapDec { // "n" is the number of increments, so we wrap at n-1. def apply(value: UInt, n: Int): UInt = { if (isPow2(n)) { (value - 1.U)(log2Ceil(n)-1,0) } else { val wrap = (value === 0.U) Mux(wrap, (n-1).U, value - 1.U) } } } /* * Object to mask off lower bits of a PC to align to a "b" * Byte boundary. / object AlignPCToBoundary { def apply(pc: UInt, b: Int): UInt = { // Invert for scenario where pc longer than b // (which would clear all bits above size(b)). ~(~pc \| (b-1).U) } } /* * Object to rotate a signal left by one / object RotateL1 { def apply(signal: UInt): UInt = { val w = signal.getWidth val out = Cat(signal(w-2,0), signal(w-1)) return out } } /* * Object to sext a value to a particular length. / object Sext { def apply(x: UInt, length: Int): UInt = { if (x.getWidth == length) return x else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x) } } /* * Object to translate from BOOM's special "packed immediate" to a 32b signed immediate * Asking for U-type gives it shifted up 12 bits. / object ImmGen { import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N} def apply(i: UInt, isel: UInt): UInt = { val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i) val sign = ip(LONGEST_IMM_SZ-1).asSInt val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign) val i19_12 = Mux(isel === IS_U \|\| isel === IS_J, ip(7,0).asSInt, sign) val i11 = Mux(isel === IS_U, 0.S, Mux(isel === IS_J \|\| isel === IS_B, ip(8).asSInt, sign)) val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt) val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt) val i0 = Mux(isel === IS_S \|\| isel === IS_I, ip(8).asSInt, 0.S) return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0) } } /* * Object to see if an instruction is a JALR. / object DebugIsJALR { def apply(inst: UInt): Bool = { // TODO Chisel not sure why this won't compile // val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)), // Array( // JALR -> Bool(true))) inst(6,0) === "b1100111".U } } /* * Object to take an instruction and output its branch or jal target. Only used * for a debug assert (no where else would we jump straight from instruction * bits to a target). / object DebugGetBJImm { def apply(inst: UInt): UInt = { // TODO Chisel not sure why this won't compile //val csignals = //rocket.DecodeLogic(inst, // List(Bool(false), Bool(false)), // Array( // BEQ -> List(Bool(true ), Bool(false)), // BNE -> List(Bool(true ), Bool(false)), // BGE -> List(Bool(true ), Bool(false)), // BGEU -> List(Bool(true ), Bool(false)), // BLT -> List(Bool(true ), Bool(false)), // BLTU -> List(Bool(true ), Bool(false)) // )) //val is_br :: nothing :: Nil = csignals val is_br = (inst(6,0) === "b1100011".U) val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W)) val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W)) Mux(is_br, br_targ, jal_targ) } } /* * Object to return the lowest bit position after the head. / object AgePriorityEncoder { def apply(in: Seq[Bool], head: UInt): UInt = { val n = in.size val width = log2Ceil(in.size) val n_padded = 1 << width val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in val idx = PriorityEncoder(temp_vec) idx(width-1, 0) //discard msb } } /* * Object to determine whether queue * index i0 is older than index i1. / object IsOlder { def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head)) } object IsYoungerMask { def apply(i: UInt, head: UInt, n: Integer): UInt = { val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0)) val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0)) Mux(i < head, hi_mask & lo_mask, hi_mask \| lo_mask)(n-1,0) } } /* * Set all bits at or below the highest order '1'. / object MaskLower { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => in >> i.U).reduce(_\|_) } } /* * Set all bits at or above the lowest order '1'. / object MaskUpper { def apply(in: UInt) = { val n = in.getWidth (0 until n).map(i => (in << i.U)(n-1,0)).reduce(_\|_) } } /* * Transpose a matrix of Chisel Vecs. / object Transpose { def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = { val n = in(0).size VecInit((0 until n).map(i => VecInit(in.map(row => row(i))))) } } /* * N-wide one-hot priority encoder. / object SelectFirstN { def apply(in: UInt, n: Int) = { val sels = Wire(Vec(n, UInt(in.getWidth.W))) var mask = in for (i <- 0 until n) { sels(i) := PriorityEncoderOH(mask) mask = mask & ~sels(i) } sels } } /* * Connect the first k of n valid input interfaces to k output interfaces. / class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module { require(n >= k) val io = IO(new Bundle { val in = Vec(n, Flipped(DecoupledIO(gen))) val out = Vec(k, DecoupledIO(gen)) }) if (n == k) { io.out <> io.in } else { val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c)) val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col => (col zip io.in.map(_.valid)) map {case (c,v) => c && v}) val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_\|\|_)) val out_valids = sels map (col => col.reduce(_\|\|_)) val out_data = sels map (s => Mux1H(s, io.in.map(_.bits))) in_readys zip io.in foreach {case (r,i) => i.ready := r} out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d} } } /* * Create a queue that can be killed with a branch kill signal. * Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq). / class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val enq = Flipped(Decoupled(gen)) val deq = Decoupled(gen) val brupdate = Input(new BrUpdateInfo()) val flush = Input(Bool()) val empty = Output(Bool()) val count = Output(UInt(log2Ceil(entries).W)) }) if (fastDeq && entries > 1) { // Pipeline dequeue selection so the mux gets an entire cycle val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false)) val out_reg = Reg(gen) val out_valid = RegInit(false.B) val out_uop = Reg(new MicroOp) main.io.enq <> io.enq main.io.brupdate := io.brupdate main.io.flush := io.flush io.empty := main.io.empty && !out_valid io.count := main.io.count + out_valid io.deq.valid := out_valid io.deq.bits := out_reg io.deq.bits.uop := out_uop out_uop := UpdateBrMask(io.brupdate, out_uop) out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop)) main.io.deq.ready := false.B when (io.deq.fire \|\| !out_valid) { out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop)) out_reg := main.io.deq.bits out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop) main.io.deq.ready := true.B } } else { val ram = Mem(entries, gen) val valids = RegInit(VecInit(Seq.fill(entries) {false.B})) val uops = Reg(Vec(entries, new MicroOp)) val enq_ptr = Counter(entries) val deq_ptr = Counter(entries) val maybe_full = RegInit(false.B) val ptr_match = enq_ptr.value === deq_ptr.value io.empty := ptr_match && !maybe_full val full = ptr_match && maybe_full val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop))) val do_deq = WireInit((io.deq.ready \|\| !valids(deq_ptr.value)) && !io.empty) for (i <- 0 until entries) { val mask = uops(i).br_mask val uop = uops(i) valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop)) when (valids(i)) { uops(i).br_mask := GetNewBrMask(io.brupdate, mask) } } when (do_enq) { ram(enq_ptr.value) := io.enq.bits valids(enq_ptr.value) := true.B uops(enq_ptr.value) := io.enq.bits.uop uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop) enq_ptr.inc() } when (do_deq) { valids(deq_ptr.value) := false.B deq_ptr.inc() } when (do_enq =/= do_deq) { maybe_full := do_enq } io.enq.ready := !full val out = Wire(gen) out := ram(deq_ptr.value) out.uop := uops(deq_ptr.value) io.deq.valid := !io.empty && valids(deq_ptr.value) io.deq.bits := out val ptr_diff = enq_ptr.value - deq_ptr.value if (isPow2(entries)) { io.count := Cat(maybe_full && ptr_match, ptr_diff) } else { io.count := Mux(ptr_match, Mux(maybe_full, entries.asUInt, 0.U), Mux(deq_ptr.value > enq_ptr.value, entries.asUInt + ptr_diff, ptr_diff)) } } } // ------------------------------------------ // Printf helper functions // ------------------------------------------ object BoolToChar { /* * Take in a Chisel Bool and convert it into a Str * based on the Chars given * * @param c_bool Chisel Bool * @param trueChar Scala Char if bool is true * @param falseChar Scala Char if bool is false * @return UInt ASCII Char for "trueChar" or "falseChar" / def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = { Mux(c_bool, Str(trueChar), Str(falseChar)) } } object CfiTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param cfi_type specific cfi type * @return Vec of Strs (must be indexed to get specific char) / def apply(cfi_type: UInt) = { val strings = Seq("----", "BR ", "JAL ", "JALR") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(cfi_type) } } object BpdTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param bpd_type specific bpd type * @return Vec of Strs (must be indexed to get specific char) / def apply(bpd_type: UInt) = { val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(bpd_type) } } object RobTypeToChars { /* * Get a Vec of Strs that can be used for printing * * @param rob_type specific rob type * @return Vec of Strs (must be indexed to get specific char) / def apply(rob_type: UInt) = { val strings = Seq("RST", "NML", "RBK", " WT") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(rob_type) } } object XRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param xreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(xreg: UInt) = { val strings = Seq(" x0", " ra", " sp", " gp", " tp", " t0", " t1", " t2", " s0", " s1", " a0", " a1", " a2", " a3", " a4", " a5", " a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7", " s8", " s9", "s10", "s11", " t3", " t4", " t5", " t6") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(xreg) } } object FPRegToChars { /* * Get a Vec of Strs that can be used for printing * * @param fpreg specific register number * @return Vec of Strs (must be indexed to get specific char) / def apply(fpreg: UInt) = { val strings = Seq(" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7", " fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5", " fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7", " fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11") val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) }) multiVec(fpreg) } } object BoomCoreStringPrefix { /* * Add prefix to BOOM strings (currently only adds the hartId) * * @param strs list of strings * @return String combining the list with the prefix per line / def apply(strs: String)(implicit p: Parameters) = { val prefix = "[C" + s"${p(TileKey).tileId}" + "] " strs.map(str => prefix + str + "\n").mkString("") } } class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int) (implicit p: org.chipsalliance.cde.config.Parameters) extends boom.v4.common.BoomModule()(p) with boom.v4.common.HasBoomCoreParameters { val io = IO(new Bundle { val req = Input(Valid(gen)) val flush = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val resp = Output(Vec(stages, Valid(gen))) }) require(stages > 0) val uops = Reg(Vec(stages, Valid(gen))) uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits) uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits) for (i <- 1 until stages) { uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits) uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits) } for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } } io.resp := uops } File issue-slot.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Slot Logic //-------------------------------------------------------------------------- //------------------------------------------------------------------------------ // // Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot. // TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores. // TODO Disable ldspec for FP queue. package boom.v4.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import boom.v4.common._ import boom.v4.util._ class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle { val valid = Output(Bool()) val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely? val request = Output(Bool()) val grant = Input(Bool()) val iss_uop = Output(new MicroOp()) val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry! val out_uop = Output(new MicroOp()) val brupdate = Input(new BrUpdateInfo()) val kill = Input(Bool()) // pipeline flush val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant) val squash_grant = Input(Bool()) val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val child_rebusys = Input(UInt(aluWidth.W)) } class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters) extends BoomModule { val io = IO(new IssueSlotIO(numWakeupPorts)) val slot_valid = RegInit(false.B) val slot_uop = Reg(new MicroOp()) val next_valid = WireInit(slot_valid) val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop)) val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop) io.valid := slot_valid io.out_uop := next_uop io.will_be_valid := next_valid && !killed when (io.kill) { slot_valid := false.B } .elsewhen (io.in_uop.valid) { slot_valid := true.B } .elsewhen (io.clear) { slot_valid := false.B } .otherwise { slot_valid := next_valid && !killed } when (io.in_uop.valid) { slot_uop := io.in_uop.bits assert (!slot_valid \|\| io.clear \|\| io.kill) } .otherwise { slot_uop := next_uop } // Wakeups next_uop.iw_p1_bypass_hint := false.B next_uop.iw_p2_bypass_hint := false.B next_uop.iw_p3_bypass_hint := false.B next_uop.iw_p1_speculative_child := 0.U next_uop.iw_p2_speculative_child := 0.U val rebusied_prs1 = WireInit(false.B) val rebusied_prs2 = WireInit(false.B) val rebusied = rebusied_prs1 \|\| rebusied_prs2 val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 } val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 } val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 } val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m } val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m } val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m } val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m } val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m } val bypassables = io.wakeup_ports.map { w => w.bits.bypassable } val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask } when (prs1_wakeups.reduce(_\|\|_)) { next_uop.prs1_busy := false.B next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks) next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables) } when ((prs1_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) && slot_uop.lrs1_rtype === RT_FIX) { next_uop.prs1_busy := true.B rebusied_prs1 := true.B } when (prs2_wakeups.reduce(_\|\|_)) { next_uop.prs2_busy := false.B next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks) next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables) } when ((prs2_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) && slot_uop.lrs2_rtype === RT_FIX) { next_uop.prs2_busy := true.B rebusied_prs2 := true.B } when (prs3_wakeups.reduce(_\|\|_)) { next_uop.prs3_busy := false.B next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables) } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) { next_uop.ppred_busy := false.B } val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B) val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B) io.request := slot_valid && !slot_uop.iw_issued && ( iss_ready \|\| agen_ready \|\| dgen_ready ) io.iss_uop := slot_uop // Update state for current micro-op based on grant next_uop.iw_issued := false.B next_uop.iw_issued_partial_agen := false.B next_uop.iw_issued_partial_dgen := false.B when (io.grant && !io.squash_grant) { next_uop.iw_issued := true.B } if (isMem) { when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) { when (agen_ready) { // Issue the AGEN, next slot entry is a DGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_agen := true.B } io.iss_uop.fu_code(FC_AGEN) := true.B io.iss_uop.fu_code(FC_DGEN) := false.B } .otherwise { // Issue the DGEN, next slot entry is the AGEN when (io.grant && !io.squash_grant) { next_uop.iw_issued_partial_dgen := true.B } io.iss_uop.fu_code(FC_AGEN) := false.B io.iss_uop.fu_code(FC_DGEN) := true.B io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } } .elsewhen (slot_uop.fu_code(FC_DGEN)) { io.iss_uop.imm_sel := IS_N io.iss_uop.prs1 := slot_uop.prs2 io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint } io.iss_uop.lrs2_rtype := RT_X io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE } when (slot_valid && slot_uop.iw_issued) { next_valid := rebusied if (isMem) { when (slot_uop.iw_issued_partial_agen) { next_valid := true.B when (!rebusied_prs1) { next_uop.fu_code(FC_AGEN) := false.B next_uop.fu_code(FC_DGEN) := true.B } } .elsewhen (slot_uop.iw_issued_partial_dgen) { next_valid := true.B when (!rebusied_prs2) { next_uop.fu_code(FC_AGEN) := true.B next_uop.fu_code(FC_DGEN) := false.B } } } } }	module IssueSlot_29( // @[issue-slot.scala:49:7] input clock, // @[issue-slot.scala:49:7] input reset, // @[issue-slot.scala:49:7] output io_valid, // @[issue-slot.scala:52:14] output io_will_be_valid, // @[issue-slot.scala:52:14] output io_request, // @[issue-slot.scala:52:14] input io_grant, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14] output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [11:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14] output io_iss_uop_is_fence, // @[issue-slot.scala:52:14] output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14] output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14] output io_iss_uop_is_amo, // @[issue-slot.scala:52:14] output io_iss_uop_is_eret, // @[issue-slot.scala:52:14] output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14] output io_iss_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14] output io_iss_uop_taken, // @[issue-slot.scala:52:14] output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14] output [3:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14] output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_iss_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14] output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14] output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14] output io_iss_uop_is_unique, // @[issue-slot.scala:52:14] output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14] output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14] output io_iss_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_in_uop_valid, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14] input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14] input io_in_uop_bits_taken, // @[issue-slot.scala:52:14] input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14] input io_in_uop_bits_exception, // @[issue-slot.scala:52:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14] input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14] output io_out_uop_is_rvc, // @[issue-slot.scala:52:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14] output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14] output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14] output io_out_uop_iw_issued, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14] output [11:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14] output io_out_uop_is_sfb, // @[issue-slot.scala:52:14] output io_out_uop_is_fence, // @[issue-slot.scala:52:14] output io_out_uop_is_fencei, // @[issue-slot.scala:52:14] output io_out_uop_is_sfence, // @[issue-slot.scala:52:14] output io_out_uop_is_amo, // @[issue-slot.scala:52:14] output io_out_uop_is_eret, // @[issue-slot.scala:52:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] output io_out_uop_is_rocc, // @[issue-slot.scala:52:14] output io_out_uop_is_mov, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14] output io_out_uop_edge_inst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14] output io_out_uop_taken, // @[issue-slot.scala:52:14] output io_out_uop_imm_rename, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14] output [3:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14] output io_out_uop_exception, // @[issue-slot.scala:52:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14] output io_out_uop_mem_signed, // @[issue-slot.scala:52:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14] output io_out_uop_uses_stq, // @[issue-slot.scala:52:14] output io_out_uop_is_unique, // @[issue-slot.scala:52:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14] output io_out_uop_frs3_en, // @[issue-slot.scala:52:14] output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14] output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14] output io_out_uop_fp_val, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14] output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14] output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14] input io_brupdate_b2_taken, // @[issue-slot.scala:52:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14] input io_kill, // @[issue-slot.scala:52:14] input io_clear, // @[issue-slot.scala:52:14] input io_squash_grant, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14] input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14] input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14] input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14] input [11:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14] input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14] input [3:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14] input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14] input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14] input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14] input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14] input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14] input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14] input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14] input [1:0] io_child_rebusys // @[issue-slot.scala:52:14] ); wire [11:0] next_uop_out_br_mask; // @[util.scala:104:23] wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7] wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7] wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7] wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7] wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7] wire [11:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7] wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7] wire [3:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7] wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7] wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7] wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7] wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7] wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7] wire [1:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:49:7] wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23] wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23] wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28] wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28] wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91] wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91] wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91] wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91] wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73] wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131] wire agen_ready = 1'h0; // @[issue-slot.scala:137:114] wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114] wire [1:0] io_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-slot.scala:49:7] wire [1:0] _next_uop_iw_p1_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73] wire [1:0] _next_uop_iw_p2_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73] wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7] wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110] wire [1:0] io_wakeup_ports_2_bits_speculative_mask = 2'h1; // @[issue-slot.scala:49:7] wire [1:0] io_wakeup_ports_3_bits_speculative_mask = 2'h2; // @[issue-slot.scala:49:7] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:49:7] wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34] wire _io_request_T_4; // @[issue-slot.scala:140:51] wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28] wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28] wire next_uop_is_rvc; // @[issue-slot.scala:59:28] wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28] wire next_uop_iq_type_0; // @[issue-slot.scala:59:28] wire next_uop_iq_type_1; // @[issue-slot.scala:59:28] wire next_uop_iq_type_2; // @[issue-slot.scala:59:28] wire next_uop_iq_type_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_0; // @[issue-slot.scala:59:28] wire next_uop_fu_code_1; // @[issue-slot.scala:59:28] wire next_uop_fu_code_2; // @[issue-slot.scala:59:28] wire next_uop_fu_code_3; // @[issue-slot.scala:59:28] wire next_uop_fu_code_4; // @[issue-slot.scala:59:28] wire next_uop_fu_code_5; // @[issue-slot.scala:59:28] wire next_uop_fu_code_6; // @[issue-slot.scala:59:28] wire next_uop_fu_code_7; // @[issue-slot.scala:59:28] wire next_uop_fu_code_8; // @[issue-slot.scala:59:28] wire next_uop_fu_code_9; // @[issue-slot.scala:59:28] wire next_uop_iw_issued; // @[issue-slot.scala:59:28] wire [1:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28] wire [1:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28] wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28] wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28] wire [11:0] next_uop_br_mask; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28] wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28] wire next_uop_is_sfb; // @[issue-slot.scala:59:28] wire next_uop_is_fence; // @[issue-slot.scala:59:28] wire next_uop_is_fencei; // @[issue-slot.scala:59:28] wire next_uop_is_sfence; // @[issue-slot.scala:59:28] wire next_uop_is_amo; // @[issue-slot.scala:59:28] wire next_uop_is_eret; // @[issue-slot.scala:59:28] wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28] wire next_uop_is_rocc; // @[issue-slot.scala:59:28] wire next_uop_is_mov; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28] wire next_uop_edge_inst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28] wire next_uop_taken; // @[issue-slot.scala:59:28] wire next_uop_imm_rename; // @[issue-slot.scala:59:28] wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28] wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28] wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28] wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28] wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28] wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28] wire [5:0] next_uop_rob_idx; // @[issue-slot.scala:59:28] wire [3:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28] wire [3:0] next_uop_stq_idx; // @[issue-slot.scala:59:28] wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28] wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28] wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28] wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28] wire next_uop_prs1_busy; // @[issue-slot.scala:59:28] wire next_uop_prs2_busy; // @[issue-slot.scala:59:28] wire next_uop_prs3_busy; // @[issue-slot.scala:59:28] wire next_uop_ppred_busy; // @[issue-slot.scala:59:28] wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28] wire next_uop_exception; // @[issue-slot.scala:59:28] wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28] wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28] wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28] wire next_uop_mem_signed; // @[issue-slot.scala:59:28] wire next_uop_uses_ldq; // @[issue-slot.scala:59:28] wire next_uop_uses_stq; // @[issue-slot.scala:59:28] wire next_uop_is_unique; // @[issue-slot.scala:59:28] wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28] wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28] wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28] wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28] wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28] wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28] wire next_uop_frs3_en; // @[issue-slot.scala:59:28] wire next_uop_fcn_dw; // @[issue-slot.scala:59:28] wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28] wire next_uop_fp_val; // @[issue-slot.scala:59:28] wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28] wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28] wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28] wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28] wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28] wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28] wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28] wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [11:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7] wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7] wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7] wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7] wire [11:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7] wire io_out_uop_taken_0; // @[issue-slot.scala:49:7] wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7] wire [3:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7] wire io_out_uop_exception_0; // @[issue-slot.scala:49:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7] wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7] wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7] wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7] wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7] wire io_valid_0; // @[issue-slot.scala:49:7] wire io_will_be_valid_0; // @[issue-slot.scala:49:7] wire io_request_0; // @[issue-slot.scala:49:7] reg slot_valid; // @[issue-slot.scala:55:27] assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27] reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21] wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23] reg slot_uop_is_rvc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21] wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23] reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23] reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23] reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23] reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21] assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23] reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23] reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23] reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23] reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23] reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23] reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23] reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23] reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23] reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23] reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21] assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23] reg slot_uop_iw_issued; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23] reg [1:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23] reg [1:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23] reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23] reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21] assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23] reg [1:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23] reg [11:0] slot_uop_br_mask; // @[issue-slot.scala:56:21] assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21] assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23] reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21] assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23] reg slot_uop_is_sfb; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23] reg slot_uop_is_fence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23] reg slot_uop_is_fencei; // @[issue-slot.scala:56:21] assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23] reg slot_uop_is_sfence; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23] reg slot_uop_is_amo; // @[issue-slot.scala:56:21] assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23] reg slot_uop_is_eret; // @[issue-slot.scala:56:21] assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23] reg slot_uop_is_rocc; // @[issue-slot.scala:56:21] assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23] reg slot_uop_is_mov; // @[issue-slot.scala:56:21] assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23] reg slot_uop_edge_inst; // @[issue-slot.scala:56:21] assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21] assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23] reg slot_uop_taken; // @[issue-slot.scala:56:21] assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23] reg slot_uop_imm_rename; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23] reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23] reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21] assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21] assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21] wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23] reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23] reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21] assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23] reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23] reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23] reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23] reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23] reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23] reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23] reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23] reg [5:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23] reg [3:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23] reg [3:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21] wire [3:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21] assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23] reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23] reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23] reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23] reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21] assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23] wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88] wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95] wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21] assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21] wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23] reg slot_uop_exception; // @[issue-slot.scala:56:21] assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21] assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21] wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23] reg slot_uop_mem_signed; // @[issue-slot.scala:56:21] assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23] reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23] reg slot_uop_uses_stq; // @[issue-slot.scala:56:21] assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23] reg slot_uop_is_unique; // @[issue-slot.scala:56:21] assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23] reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21] assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23] reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21] assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21] assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21] wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21] assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23] reg slot_uop_frs3_en; // @[issue-slot.scala:56:21] assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23] reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23] reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21] assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21] wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23] reg slot_uop_fp_val; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23] reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23] reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21] assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21] wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21] assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23] reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21] assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21] wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23] reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21] assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21] wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23] wire next_valid; // @[issue-slot.scala:58:28] assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23] assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23] assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23] assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23] assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23] assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23] assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23] assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23] assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23] assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23] assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23] assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23] assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23] assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23] assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23] assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23] assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23] assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23] wire [11:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25] assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23] assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23] assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23] assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23] assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23] assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23] assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23] assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23] assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23] assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23] assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23] assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23] assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23] assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23] assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23] assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23] assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23] assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23] assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23] assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23] assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23] assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23] assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23] assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23] assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23] assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23] assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23] assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23] assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23] assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23] assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23] assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23] assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23] assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23] assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23] assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23] assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23] assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23] assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23] assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23] assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23] assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23] assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23] assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23] assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23] assign next_uop_ppred_busy = next_uop_out_ppred_busy; // @[util.scala:104:23] assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23] assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23] assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23] assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23] assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23] assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23] assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23] assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23] assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23] assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23] assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23] assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23] assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23] assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23] assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23] assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23] assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23] assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23] assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23] assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23] assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23] assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23] assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23] assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23] assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23] assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23] assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23] assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23] assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23] assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23] assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23] assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23] wire [11:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}] assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28] assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28] wire [11:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51] wire _killed_T_1 = \|_killed_T; // @[util.scala:126:{51,59}] wire killed = _killed_T_1 \| io_kill_0; // @[util.scala:61:61, :126:59] wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61] assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}] assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34] wire _slot_valid_T = ~killed; // @[util.scala:61:61] wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
Generate the Verilog code corresponding to the following Chisel files. File ShiftRegisterPriorityQueue.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.util._ // TODO : support enq & deq at the same cycle class PriorityQueueStageIO(keyWidth: Int, value: ValueInfo) extends Bundle { val output_prev = KeyValue(keyWidth, value) val output_nxt = KeyValue(keyWidth, value) val input_prev = Flipped(KeyValue(keyWidth, value)) val input_nxt = Flipped(KeyValue(keyWidth, value)) val cmd = Flipped(Valid(UInt(1.W))) val insert_here = Input(Bool()) val cur_input_keyval = Flipped(KeyValue(keyWidth, value)) val cur_output_keyval = KeyValue(keyWidth, value) } class PriorityQueueStage(keyWidth: Int, value: ValueInfo) extends Module { val io = IO(new PriorityQueueStageIO(keyWidth, value)) dontTouch(io) val CMD_DEQ = 0.U val CMD_ENQ = 1.U val MAX_VALUE = (1 << keyWidth) - 1 val key_reg = RegInit(MAX_VALUE.U(keyWidth.W)) val value_reg = Reg(value) io.output_prev.key := key_reg io.output_prev.value := value_reg io.output_nxt.key := key_reg io.output_nxt.value := value_reg io.cur_output_keyval.key := key_reg io.cur_output_keyval.value := value_reg when (io.cmd.valid) { switch (io.cmd.bits) { is (CMD_DEQ) { key_reg := io.input_nxt.key value_reg := io.input_nxt.value } is (CMD_ENQ) { when (io.insert_here) { key_reg := io.cur_input_keyval.key value_reg := io.cur_input_keyval.value } .elsewhen (key_reg >= io.cur_input_keyval.key) { key_reg := io.input_prev.key value_reg := io.input_prev.value } .otherwise { // do nothing } } } } } object PriorityQueueStage { def apply(keyWidth: Int, v: ValueInfo): PriorityQueueStage = new PriorityQueueStage(keyWidth, v) } // TODO // - This design is not scalable as the enqued_keyval is broadcasted to all the stages // - Add pipeline registers later class PriorityQueueIO(queSize: Int, keyWidth: Int, value: ValueInfo) extends Bundle { val cnt_bits = log2Ceil(queSize+1) val counter = Output(UInt(cnt_bits.W)) val enq = Flipped(Decoupled(KeyValue(keyWidth, value))) val deq = Decoupled(KeyValue(keyWidth, value)) } class PriorityQueue(queSize: Int, keyWidth: Int, value: ValueInfo) extends Module { val keyWidthInternal = keyWidth + 1 val CMD_DEQ = 0.U val CMD_ENQ = 1.U val io = IO(new PriorityQueueIO(queSize, keyWidthInternal, value)) dontTouch(io) val MAX_VALUE = ((1 << keyWidthInternal) - 1).U val cnt_bits = log2Ceil(queSize+1) // do not consider cases where we are inserting more entries then the queSize val counter = RegInit(0.U(cnt_bits.W)) io.counter := counter val full = (counter === queSize.U) val empty = (counter === 0.U) io.deq.valid := !empty io.enq.ready := !full when (io.enq.fire) { counter := counter + 1.U } when (io.deq.fire) { counter := counter - 1.U } val cmd_valid = io.enq.valid \|\| io.deq.ready val cmd = Mux(io.enq.valid, CMD_ENQ, CMD_DEQ) assert(!(io.enq.valid && io.deq.ready)) val stages = Seq.fill(queSize)(Module(new PriorityQueueStage(keyWidthInternal, value))) for (i <- 0 until (queSize - 1)) { stages(i+1).io.input_prev <> stages(i).io.output_nxt stages(i).io.input_nxt <> stages(i+1).io.output_prev } stages(queSize-1).io.input_nxt.key := MAX_VALUE // stages(queSize-1).io.input_nxt.value := stages(queSize-1).io.input_nxt.value.symbol := 0.U // stages(queSize-1).io.input_nxt.value.child(0) := 0.U // stages(queSize-1).io.input_nxt.value.child(1) := 0.U stages(0).io.input_prev.key := io.enq.bits.key stages(0).io.input_prev.value <> io.enq.bits.value for (i <- 0 until queSize) { stages(i).io.cmd.valid := cmd_valid stages(i).io.cmd.bits := cmd stages(i).io.cur_input_keyval <> io.enq.bits } val is_large_or_equal = WireInit(VecInit(Seq.fill(queSize)(false.B))) for (i <- 0 until queSize) { is_large_or_equal(i) := (stages(i).io.cur_output_keyval.key >= io.enq.bits.key) } val is_large_or_equal_cat = Wire(UInt(queSize.W)) is_large_or_equal_cat := Cat(is_large_or_equal.reverse) val insert_here_idx = PriorityEncoder(is_large_or_equal_cat) for (i <- 0 until queSize) { when (i.U === insert_here_idx) { stages(i).io.insert_here := true.B } .otherwise { stages(i).io.insert_here := false.B } } io.deq.bits <> stages(0).io.output_prev }	module PriorityQueueStage_38( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module MacUnit_50( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /** Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_17( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_26 = _source_ok_T_25 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_29 = source_ok_uncommonBits_4 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h23; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = _source_ok_WIRE_0 \| _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 \| _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 \| _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 \| _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 \| _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_39 = _source_ok_T_38 \| _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_40 = _source_ok_T_39 \| _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_40 \| _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 \| _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 \| _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 \| _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 \| _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 \| _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 \| _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 \| _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 \| _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 \| _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 \| _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 \| _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_41 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_42 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_48 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_54 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_60 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_66 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_43 = _source_ok_T_42 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_49 = _source_ok_T_48 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_53; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_55 = _source_ok_T_54 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_61 = _source_ok_T_60 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_65; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_67 = _source_ok_T_66 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = source_ok_uncommonBits_9 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_71 = _source_ok_T_69 & _source_ok_T_70; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_5 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = io_in_d_bits_source_0 == 7'h23; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = _source_ok_WIRE_1_0 \| _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 \| _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 \| _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_78 = _source_ok_T_77 \| _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_79 = _source_ok_T_78 \| _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_80 = _source_ok_T_79 \| _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_81 = _source_ok_T_80 \| _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_81 \| _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1610 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1610; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1610; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T \| _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1683 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1683; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1683; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1683; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T \| _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 \| _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 \| _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [519:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1536 = _T_1610 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1536 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1536 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1536 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1536 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1536 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1582 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1582 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1551 = _T_1683 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1551 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1551 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1551 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight \| a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [519:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 \| _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1654 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1654 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1636 = _T_1683 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1636 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1636 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1636 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_2( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_2 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RecFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import consts._ class RecFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val in = Input(Bits((inExpWidth + inSigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in); if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- io.out := io.in<<(outSigWidth - inSigWidth) io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W) } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( inExpWidth, inSigWidth, outExpWidth, outSigWidth, flRoundOpt_sigMSBitAlwaysZero )) roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn) roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := rawIn roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } } File rawFloatFromRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ /---------------------------------------------------------------------------- \| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be \| set. ----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }	module RecFNToRecFN_28( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncQueueSource_TLBundleA_a32d64s2k3z4c( // @[AsyncQueue.scala:70:7] input clock, // @[AsyncQueue.scala:70:7] input reset, // @[AsyncQueue.scala:70:7] output io_enq_ready, // @[AsyncQueue.scala:73:14] input io_enq_valid, // @[AsyncQueue.scala:73:14] input [2:0] io_enq_bits_opcode, // @[AsyncQueue.scala:73:14] input [2:0] io_enq_bits_param, // @[AsyncQueue.scala:73:14] input [3:0] io_enq_bits_size, // @[AsyncQueue.scala:73:14] input [1:0] io_enq_bits_source, // @[AsyncQueue.scala:73:14] input [31:0] io_enq_bits_address, // @[AsyncQueue.scala:73:14] input [7:0] io_enq_bits_mask, // @[AsyncQueue.scala:73:14] input [63:0] io_enq_bits_data, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_0_opcode, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_0_param, // @[AsyncQueue.scala:73:14] output [3:0] io_async_mem_0_size, // @[AsyncQueue.scala:73:14] output [1:0] io_async_mem_0_source, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_0_address, // @[AsyncQueue.scala:73:14] output [7:0] io_async_mem_0_mask, // @[AsyncQueue.scala:73:14] output [63:0] io_async_mem_0_data, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_1_opcode, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_1_param, // @[AsyncQueue.scala:73:14] output [3:0] io_async_mem_1_size, // @[AsyncQueue.scala:73:14] output [1:0] io_async_mem_1_source, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_1_address, // @[AsyncQueue.scala:73:14] output [7:0] io_async_mem_1_mask, // @[AsyncQueue.scala:73:14] output [63:0] io_async_mem_1_data, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_2_opcode, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_2_param, // @[AsyncQueue.scala:73:14] output [3:0] io_async_mem_2_size, // @[AsyncQueue.scala:73:14] output [1:0] io_async_mem_2_source, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_2_address, // @[AsyncQueue.scala:73:14] output [7:0] io_async_mem_2_mask, // @[AsyncQueue.scala:73:14] output [63:0] io_async_mem_2_data, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_3_opcode, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_3_param, // @[AsyncQueue.scala:73:14] output [3:0] io_async_mem_3_size, // @[AsyncQueue.scala:73:14] output [1:0] io_async_mem_3_source, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_3_address, // @[AsyncQueue.scala:73:14] output [7:0] io_async_mem_3_mask, // @[AsyncQueue.scala:73:14] output [63:0] io_async_mem_3_data, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_4_opcode, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_4_param, // @[AsyncQueue.scala:73:14] output [3:0] io_async_mem_4_size, // @[AsyncQueue.scala:73:14] output [1:0] io_async_mem_4_source, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_4_address, // @[AsyncQueue.scala:73:14] output [7:0] io_async_mem_4_mask, // @[AsyncQueue.scala:73:14] output [63:0] io_async_mem_4_data, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_5_opcode, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_5_param, // @[AsyncQueue.scala:73:14] output [3:0] io_async_mem_5_size, // @[AsyncQueue.scala:73:14] output [1:0] io_async_mem_5_source, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_5_address, // @[AsyncQueue.scala:73:14] output [7:0] io_async_mem_5_mask, // @[AsyncQueue.scala:73:14] output [63:0] io_async_mem_5_data, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_6_opcode, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_6_param, // @[AsyncQueue.scala:73:14] output [3:0] io_async_mem_6_size, // @[AsyncQueue.scala:73:14] output [1:0] io_async_mem_6_source, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_6_address, // @[AsyncQueue.scala:73:14] output [7:0] io_async_mem_6_mask, // @[AsyncQueue.scala:73:14] output [63:0] io_async_mem_6_data, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_7_opcode, // @[AsyncQueue.scala:73:14] output [2:0] io_async_mem_7_param, // @[AsyncQueue.scala:73:14] output [3:0] io_async_mem_7_size, // @[AsyncQueue.scala:73:14] output [1:0] io_async_mem_7_source, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_7_address, // @[AsyncQueue.scala:73:14] output [7:0] io_async_mem_7_mask, // @[AsyncQueue.scala:73:14] output [63:0] io_async_mem_7_data, // @[AsyncQueue.scala:73:14] input [3:0] io_async_ridx, // @[AsyncQueue.scala:73:14] output [3:0] io_async_widx, // @[AsyncQueue.scala:73:14] input io_async_safe_ridx_valid, // @[AsyncQueue.scala:73:14] output io_async_safe_widx_valid, // @[AsyncQueue.scala:73:14] output io_async_safe_source_reset_n, // @[AsyncQueue.scala:73:14] input io_async_safe_sink_reset_n // @[AsyncQueue.scala:73:14] ); wire _sink_extend_io_out; // @[AsyncQueue.scala:105:30] wire _source_valid_0_io_out; // @[AsyncQueue.scala:102:32] wire io_enq_valid_0 = io_enq_valid; // @[AsyncQueue.scala:70:7] wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[AsyncQueue.scala:70:7] wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[AsyncQueue.scala:70:7] wire [3:0] io_enq_bits_size_0 = io_enq_bits_size; // @[AsyncQueue.scala:70:7] wire [1:0] io_enq_bits_source_0 = io_enq_bits_source; // @[AsyncQueue.scala:70:7] wire [31:0] io_enq_bits_address_0 = io_enq_bits_address; // @[AsyncQueue.scala:70:7] wire [7:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[AsyncQueue.scala:70:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[AsyncQueue.scala:70:7] wire [3:0] io_async_ridx_0 = io_async_ridx; // @[AsyncQueue.scala:70:7] wire io_async_safe_ridx_valid_0 = io_async_safe_ridx_valid; // @[AsyncQueue.scala:70:7] wire io_async_safe_sink_reset_n_0 = io_async_safe_sink_reset_n; // @[AsyncQueue.scala:70:7] wire _widx_T = reset; // @[AsyncQueue.scala:83:30] wire _ready_reg_T = reset; // @[AsyncQueue.scala:90:35] wire _widx_reg_T = reset; // @[AsyncQueue.scala:93:34] wire _source_valid_0_reset_T = reset; // @[AsyncQueue.scala:107:36] wire _source_valid_1_reset_T = reset; // @[AsyncQueue.scala:108:36] wire _sink_extend_reset_T = reset; // @[AsyncQueue.scala:109:36] wire _sink_valid_reset_T = reset; // @[AsyncQueue.scala:110:35] wire _io_async_safe_source_reset_n_T = reset; // @[AsyncQueue.scala:123:34] wire io_enq_bits_corrupt = 1'h0; // @[AsyncQueue.scala:70:7] wire io_async_mem_0_corrupt = 1'h0; // @[AsyncQueue.scala:70:7] wire io_async_mem_1_corrupt = 1'h0; // @[AsyncQueue.scala:70:7] wire io_async_mem_2_corrupt = 1'h0; // @[AsyncQueue.scala:70:7] wire io_async_mem_3_corrupt = 1'h0; // @[AsyncQueue.scala:70:7] wire io_async_mem_4_corrupt = 1'h0; // @[AsyncQueue.scala:70:7] wire io_async_mem_5_corrupt = 1'h0; // @[AsyncQueue.scala:70:7] wire io_async_mem_6_corrupt = 1'h0; // @[AsyncQueue.scala:70:7] wire io_async_mem_7_corrupt = 1'h0; // @[AsyncQueue.scala:70:7] wire _io_enq_ready_T; // @[AsyncQueue.scala:91:29] wire _io_async_safe_source_reset_n_T_1; // @[AsyncQueue.scala:123:27] wire io_enq_ready_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_0_opcode_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_0_param_0; // @[AsyncQueue.scala:70:7] wire [3:0] io_async_mem_0_size_0; // @[AsyncQueue.scala:70:7] wire [1:0] io_async_mem_0_source_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_0_address_0; // @[AsyncQueue.scala:70:7] wire [7:0] io_async_mem_0_mask_0; // @[AsyncQueue.scala:70:7] wire [63:0] io_async_mem_0_data_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_1_opcode_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_1_param_0; // @[AsyncQueue.scala:70:7] wire [3:0] io_async_mem_1_size_0; // @[AsyncQueue.scala:70:7] wire [1:0] io_async_mem_1_source_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_1_address_0; // @[AsyncQueue.scala:70:7] wire [7:0] io_async_mem_1_mask_0; // @[AsyncQueue.scala:70:7] wire [63:0] io_async_mem_1_data_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_2_opcode_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_2_param_0; // @[AsyncQueue.scala:70:7] wire [3:0] io_async_mem_2_size_0; // @[AsyncQueue.scala:70:7] wire [1:0] io_async_mem_2_source_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_2_address_0; // @[AsyncQueue.scala:70:7] wire [7:0] io_async_mem_2_mask_0; // @[AsyncQueue.scala:70:7] wire [63:0] io_async_mem_2_data_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_3_opcode_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_3_param_0; // @[AsyncQueue.scala:70:7] wire [3:0] io_async_mem_3_size_0; // @[AsyncQueue.scala:70:7] wire [1:0] io_async_mem_3_source_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_3_address_0; // @[AsyncQueue.scala:70:7] wire [7:0] io_async_mem_3_mask_0; // @[AsyncQueue.scala:70:7] wire [63:0] io_async_mem_3_data_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_4_opcode_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_4_param_0; // @[AsyncQueue.scala:70:7] wire [3:0] io_async_mem_4_size_0; // @[AsyncQueue.scala:70:7] wire [1:0] io_async_mem_4_source_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_4_address_0; // @[AsyncQueue.scala:70:7] wire [7:0] io_async_mem_4_mask_0; // @[AsyncQueue.scala:70:7] wire [63:0] io_async_mem_4_data_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_5_opcode_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_5_param_0; // @[AsyncQueue.scala:70:7] wire [3:0] io_async_mem_5_size_0; // @[AsyncQueue.scala:70:7] wire [1:0] io_async_mem_5_source_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_5_address_0; // @[AsyncQueue.scala:70:7] wire [7:0] io_async_mem_5_mask_0; // @[AsyncQueue.scala:70:7] wire [63:0] io_async_mem_5_data_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_6_opcode_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_6_param_0; // @[AsyncQueue.scala:70:7] wire [3:0] io_async_mem_6_size_0; // @[AsyncQueue.scala:70:7] wire [1:0] io_async_mem_6_source_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_6_address_0; // @[AsyncQueue.scala:70:7] wire [7:0] io_async_mem_6_mask_0; // @[AsyncQueue.scala:70:7] wire [63:0] io_async_mem_6_data_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_7_opcode_0; // @[AsyncQueue.scala:70:7] wire [2:0] io_async_mem_7_param_0; // @[AsyncQueue.scala:70:7] wire [3:0] io_async_mem_7_size_0; // @[AsyncQueue.scala:70:7] wire [1:0] io_async_mem_7_source_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_7_address_0; // @[AsyncQueue.scala:70:7] wire [7:0] io_async_mem_7_mask_0; // @[AsyncQueue.scala:70:7] wire [63:0] io_async_mem_7_data_0; // @[AsyncQueue.scala:70:7] wire io_async_safe_widx_valid_0; // @[AsyncQueue.scala:70:7] wire io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:70:7] wire [3:0] io_async_widx_0; // @[AsyncQueue.scala:70:7] wire sink_ready; // @[AsyncQueue.scala:81:28] reg [2:0] mem_0_opcode; // @[AsyncQueue.scala:82:16] assign io_async_mem_0_opcode_0 = mem_0_opcode; // @[AsyncQueue.scala:70:7, :82:16] reg [2:0] mem_0_param; // @[AsyncQueue.scala:82:16] assign io_async_mem_0_param_0 = mem_0_param; // @[AsyncQueue.scala:70:7, :82:16] reg [3:0] mem_0_size; // @[AsyncQueue.scala:82:16] assign io_async_mem_0_size_0 = mem_0_size; // @[AsyncQueue.scala:70:7, :82:16] reg [1:0] mem_0_source; // @[AsyncQueue.scala:82:16] assign io_async_mem_0_source_0 = mem_0_source; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_0_address; // @[AsyncQueue.scala:82:16] assign io_async_mem_0_address_0 = mem_0_address; // @[AsyncQueue.scala:70:7, :82:16] reg [7:0] mem_0_mask; // @[AsyncQueue.scala:82:16] assign io_async_mem_0_mask_0 = mem_0_mask; // @[AsyncQueue.scala:70:7, :82:16] reg [63:0] mem_0_data; // @[AsyncQueue.scala:82:16] assign io_async_mem_0_data_0 = mem_0_data; // @[AsyncQueue.scala:70:7, :82:16] reg [2:0] mem_1_opcode; // @[AsyncQueue.scala:82:16] assign io_async_mem_1_opcode_0 = mem_1_opcode; // @[AsyncQueue.scala:70:7, :82:16] reg [2:0] mem_1_param; // @[AsyncQueue.scala:82:16] assign io_async_mem_1_param_0 = mem_1_param; // @[AsyncQueue.scala:70:7, :82:16] reg [3:0] mem_1_size; // @[AsyncQueue.scala:82:16] assign io_async_mem_1_size_0 = mem_1_size; // @[AsyncQueue.scala:70:7, :82:16] reg [1:0] mem_1_source; // @[AsyncQueue.scala:82:16] assign io_async_mem_1_source_0 = mem_1_source; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_1_address; // @[AsyncQueue.scala:82:16] assign io_async_mem_1_address_0 = mem_1_address; // @[AsyncQueue.scala:70:7, :82:16] reg [7:0] mem_1_mask; // @[AsyncQueue.scala:82:16] assign io_async_mem_1_mask_0 = mem_1_mask; // @[AsyncQueue.scala:70:7, :82:16] reg [63:0] mem_1_data; // @[AsyncQueue.scala:82:16] assign io_async_mem_1_data_0 = mem_1_data; // @[AsyncQueue.scala:70:7, :82:16] reg [2:0] mem_2_opcode; // @[AsyncQueue.scala:82:16] assign io_async_mem_2_opcode_0 = mem_2_opcode; // @[AsyncQueue.scala:70:7, :82:16] reg [2:0] mem_2_param; // @[AsyncQueue.scala:82:16] assign io_async_mem_2_param_0 = mem_2_param; // @[AsyncQueue.scala:70:7, :82:16] reg [3:0] mem_2_size; // @[AsyncQueue.scala:82:16] assign io_async_mem_2_size_0 = mem_2_size; // @[AsyncQueue.scala:70:7, :82:16] reg [1:0] mem_2_source; // @[AsyncQueue.scala:82:16] assign io_async_mem_2_source_0 = mem_2_source; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_2_address; // @[AsyncQueue.scala:82:16] assign io_async_mem_2_address_0 = mem_2_address; // @[AsyncQueue.scala:70:7, :82:16] reg [7:0] mem_2_mask; // @[AsyncQueue.scala:82:16] assign io_async_mem_2_mask_0 = mem_2_mask; // @[AsyncQueue.scala:70:7, :82:16] reg [63:0] mem_2_data; // @[AsyncQueue.scala:82:16] assign io_async_mem_2_data_0 = mem_2_data; // @[AsyncQueue.scala:70:7, :82:16] reg [2:0] mem_3_opcode; // @[AsyncQueue.scala:82:16] assign io_async_mem_3_opcode_0 = mem_3_opcode; // @[AsyncQueue.scala:70:7, :82:16] reg [2:0] mem_3_param; // @[AsyncQueue.scala:82:16] assign io_async_mem_3_param_0 = mem_3_param; // @[AsyncQueue.scala:70:7, :82:16] reg [3:0] mem_3_size; // @[AsyncQueue.scala:82:16] assign io_async_mem_3_size_0 = mem_3_size; // @[AsyncQueue.scala:70:7, :82:16] reg [1:0] mem_3_source; // @[AsyncQueue.scala:82:16] assign io_async_mem_3_source_0 = mem_3_source; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_3_address; // @[AsyncQueue.scala:82:16] assign io_async_mem_3_address_0 = mem_3_address; // @[AsyncQueue.scala:70:7, :82:16] reg [7:0] mem_3_mask; // @[AsyncQueue.scala:82:16] assign io_async_mem_3_mask_0 = mem_3_mask; // @[AsyncQueue.scala:70:7, :82:16] reg [63:0] mem_3_data; // @[AsyncQueue.scala:82:16] assign io_async_mem_3_data_0 = mem_3_data; // @[AsyncQueue.scala:70:7, :82:16] reg [2:0] mem_4_opcode; // @[AsyncQueue.scala:82:16] assign io_async_mem_4_opcode_0 = mem_4_opcode; // @[AsyncQueue.scala:70:7, :82:16] reg [2:0] mem_4_param; // @[AsyncQueue.scala:82:16] assign io_async_mem_4_param_0 = mem_4_param; // @[AsyncQueue.scala:70:7, :82:16] reg [3:0] mem_4_size; // @[AsyncQueue.scala:82:16] assign io_async_mem_4_size_0 = mem_4_size; // @[AsyncQueue.scala:70:7, :82:16] reg [1:0] mem_4_source; // @[AsyncQueue.scala:82:16] assign io_async_mem_4_source_0 = mem_4_source; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_4_address; // @[AsyncQueue.scala:82:16] assign io_async_mem_4_address_0 = mem_4_address; // @[AsyncQueue.scala:70:7, :82:16] reg [7:0] mem_4_mask; // @[AsyncQueue.scala:82:16] assign io_async_mem_4_mask_0 = mem_4_mask; // @[AsyncQueue.scala:70:7, :82:16] reg [63:0] mem_4_data; // @[AsyncQueue.scala:82:16] assign io_async_mem_4_data_0 = mem_4_data; // @[AsyncQueue.scala:70:7, :82:16] reg [2:0] mem_5_opcode; // @[AsyncQueue.scala:82:16] assign io_async_mem_5_opcode_0 = mem_5_opcode; // @[AsyncQueue.scala:70:7, :82:16] reg [2:0] mem_5_param; // @[AsyncQueue.scala:82:16] assign io_async_mem_5_param_0 = mem_5_param; // @[AsyncQueue.scala:70:7, :82:16] reg [3:0] mem_5_size; // @[AsyncQueue.scala:82:16] assign io_async_mem_5_size_0 = mem_5_size; // @[AsyncQueue.scala:70:7, :82:16] reg [1:0] mem_5_source; // @[AsyncQueue.scala:82:16] assign io_async_mem_5_source_0 = mem_5_source; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_5_address; // @[AsyncQueue.scala:82:16] assign io_async_mem_5_address_0 = mem_5_address; // @[AsyncQueue.scala:70:7, :82:16] reg [7:0] mem_5_mask; // @[AsyncQueue.scala:82:16] assign io_async_mem_5_mask_0 = mem_5_mask; // @[AsyncQueue.scala:70:7, :82:16] reg [63:0] mem_5_data; // @[AsyncQueue.scala:82:16] assign io_async_mem_5_data_0 = mem_5_data; // @[AsyncQueue.scala:70:7, :82:16] reg [2:0] mem_6_opcode; // @[AsyncQueue.scala:82:16] assign io_async_mem_6_opcode_0 = mem_6_opcode; // @[AsyncQueue.scala:70:7, :82:16] reg [2:0] mem_6_param; // @[AsyncQueue.scala:82:16] assign io_async_mem_6_param_0 = mem_6_param; // @[AsyncQueue.scala:70:7, :82:16] reg [3:0] mem_6_size; // @[AsyncQueue.scala:82:16] assign io_async_mem_6_size_0 = mem_6_size; // @[AsyncQueue.scala:70:7, :82:16] reg [1:0] mem_6_source; // @[AsyncQueue.scala:82:16] assign io_async_mem_6_source_0 = mem_6_source; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_6_address; // @[AsyncQueue.scala:82:16] assign io_async_mem_6_address_0 = mem_6_address; // @[AsyncQueue.scala:70:7, :82:16] reg [7:0] mem_6_mask; // @[AsyncQueue.scala:82:16] assign io_async_mem_6_mask_0 = mem_6_mask; // @[AsyncQueue.scala:70:7, :82:16] reg [63:0] mem_6_data; // @[AsyncQueue.scala:82:16] assign io_async_mem_6_data_0 = mem_6_data; // @[AsyncQueue.scala:70:7, :82:16] reg [2:0] mem_7_opcode; // @[AsyncQueue.scala:82:16] assign io_async_mem_7_opcode_0 = mem_7_opcode; // @[AsyncQueue.scala:70:7, :82:16] reg [2:0] mem_7_param; // @[AsyncQueue.scala:82:16] assign io_async_mem_7_param_0 = mem_7_param; // @[AsyncQueue.scala:70:7, :82:16] reg [3:0] mem_7_size; // @[AsyncQueue.scala:82:16] assign io_async_mem_7_size_0 = mem_7_size; // @[AsyncQueue.scala:70:7, :82:16] reg [1:0] mem_7_source; // @[AsyncQueue.scala:82:16] assign io_async_mem_7_source_0 = mem_7_source; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_7_address; // @[AsyncQueue.scala:82:16] assign io_async_mem_7_address_0 = mem_7_address; // @[AsyncQueue.scala:70:7, :82:16] reg [7:0] mem_7_mask; // @[AsyncQueue.scala:82:16] assign io_async_mem_7_mask_0 = mem_7_mask; // @[AsyncQueue.scala:70:7, :82:16] reg [63:0] mem_7_data; // @[AsyncQueue.scala:82:16] assign io_async_mem_7_data_0 = mem_7_data; // @[AsyncQueue.scala:70:7, :82:16] wire _widx_T_1 = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire _widx_T_2 = ~sink_ready; // @[AsyncQueue.scala:81:28, :83:77] wire [3:0] _widx_incremented_T_2; // @[AsyncQueue.scala:53:23] wire [3:0] widx_incremented; // @[AsyncQueue.scala:51:27] reg [3:0] widx_widx_bin; // @[AsyncQueue.scala:52:25] wire [4:0] _widx_incremented_T = {1'h0, widx_widx_bin} + {4'h0, _widx_T_1}; // @[Decoupled.scala:51:35] wire [3:0] _widx_incremented_T_1 = _widx_incremented_T[3:0]; // @[AsyncQueue.scala:53:43] assign _widx_incremented_T_2 = _widx_T_2 ? 4'h0 : _widx_incremented_T_1; // @[AsyncQueue.scala:52:25, :53:{23,43}, :83:77] assign widx_incremented = _widx_incremented_T_2; // @[AsyncQueue.scala:51:27, :53:23] wire [2:0] _widx_T_3 = widx_incremented[3:1]; // @[AsyncQueue.scala:51:27, :54:32] wire [3:0] widx = {widx_incremented[3], widx_incremented[2:0] ^ _widx_T_3}; // @[AsyncQueue.scala:51:27, :54:{17,32}] wire [3:0] ridx; // @[ShiftReg.scala:48:24] wire [3:0] _ready_T = ridx ^ 4'hC; // @[ShiftReg.scala:48:24] wire _ready_T_1 = widx != _ready_T; // @[AsyncQueue.scala:54:17, :85:{34,44}] wire ready = sink_ready & _ready_T_1; // @[AsyncQueue.scala:81:28, :85:{26,34}] wire [2:0] _index_T = io_async_widx_0[2:0]; // @[AsyncQueue.scala:70:7, :87:52] wire _index_T_1 = io_async_widx_0[3]; // @[AsyncQueue.scala:70:7, :87:80] wire [2:0] _index_T_2 = {_index_T_1, 2'h0}; // @[AsyncQueue.scala:87:{80,93}] wire [2:0] index = _index_T ^ _index_T_2; // @[AsyncQueue.scala:87:{52,64,93}] reg ready_reg; // @[AsyncQueue.scala:90:56] assign _io_enq_ready_T = ready_reg & sink_ready; // @[AsyncQueue.scala:81:28, :90:56, :91:29] assign io_enq_ready_0 = _io_enq_ready_T; // @[AsyncQueue.scala:70:7, :91:29] reg [3:0] widx_gray; // @[AsyncQueue.scala:93:55] assign io_async_widx_0 = widx_gray; // @[AsyncQueue.scala:70:7, :93:55] wire _source_valid_0_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46] wire _source_valid_0_reset_T_2 = _source_valid_0_reset_T \| _source_valid_0_reset_T_1; // @[AsyncQueue.scala:107:{36,43,46}] wire _source_valid_0_reset_T_3 = _source_valid_0_reset_T_2; // @[AsyncQueue.scala:107:{43,65}] wire _source_valid_1_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46, :108:46] wire _source_valid_1_reset_T_2 = _source_valid_1_reset_T \| _source_valid_1_reset_T_1; // @[AsyncQueue.scala:108:{36,43,46}] wire _source_valid_1_reset_T_3 = _source_valid_1_reset_T_2; // @[AsyncQueue.scala:108:{43,65}] wire _sink_extend_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46, :109:46] wire _sink_extend_reset_T_2 = _sink_extend_reset_T \| _sink_extend_reset_T_1; // @[AsyncQueue.scala:109:{36,43,46}] wire _sink_extend_reset_T_3 = _sink_extend_reset_T_2; // @[AsyncQueue.scala:109:{43,65}] assign _io_async_safe_source_reset_n_T_1 = ~_io_async_safe_source_reset_n_T; // @[AsyncQueue.scala:123:{27,34}] assign io_async_safe_source_reset_n_0 = _io_async_safe_source_reset_n_T_1; // @[AsyncQueue.scala:70:7, :123:27] always @(posedge clock) begin // @[AsyncQueue.scala:70:7] if (_widx_T_1 & index == 3'h0) begin // @[Decoupled.scala:51:35] mem_0_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16] mem_0_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16] mem_0_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16] mem_0_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16] mem_0_address <= io_enq_bits_address_0; // @[AsyncQueue.scala:70:7, :82:16] mem_0_mask <= io_enq_bits_mask_0; // @[AsyncQueue.scala:70:7, :82:16] mem_0_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16] end if (_widx_T_1 & index == 3'h1) begin // @[Decoupled.scala:51:35] mem_1_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16] mem_1_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16] mem_1_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16] mem_1_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16] mem_1_address <= io_enq_bits_address_0; // @[AsyncQueue.scala:70:7, :82:16] mem_1_mask <= io_enq_bits_mask_0; // @[AsyncQueue.scala:70:7, :82:16] mem_1_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16] end if (_widx_T_1 & index == 3'h2) begin // @[Decoupled.scala:51:35] mem_2_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16] mem_2_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16] mem_2_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16] mem_2_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16] mem_2_address <= io_enq_bits_address_0; // @[AsyncQueue.scala:70:7, :82:16] mem_2_mask <= io_enq_bits_mask_0; // @[AsyncQueue.scala:70:7, :82:16] mem_2_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16] end if (_widx_T_1 & index == 3'h3) begin // @[Decoupled.scala:51:35] mem_3_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16] mem_3_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16] mem_3_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16] mem_3_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16] mem_3_address <= io_enq_bits_address_0; // @[AsyncQueue.scala:70:7, :82:16] mem_3_mask <= io_enq_bits_mask_0; // @[AsyncQueue.scala:70:7, :82:16] mem_3_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16] end if (_widx_T_1 & index == 3'h4) begin // @[Decoupled.scala:51:35] mem_4_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16] mem_4_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16] mem_4_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16] mem_4_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16] mem_4_address <= io_enq_bits_address_0; // @[AsyncQueue.scala:70:7, :82:16] mem_4_mask <= io_enq_bits_mask_0; // @[AsyncQueue.scala:70:7, :82:16] mem_4_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16] end if (_widx_T_1 & index == 3'h5) begin // @[Decoupled.scala:51:35] mem_5_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16] mem_5_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16] mem_5_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16] mem_5_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16] mem_5_address <= io_enq_bits_address_0; // @[AsyncQueue.scala:70:7, :82:16] mem_5_mask <= io_enq_bits_mask_0; // @[AsyncQueue.scala:70:7, :82:16] mem_5_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16] end if (_widx_T_1 & index == 3'h6) begin // @[Decoupled.scala:51:35] mem_6_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16] mem_6_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16] mem_6_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16] mem_6_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16] mem_6_address <= io_enq_bits_address_0; // @[AsyncQueue.scala:70:7, :82:16] mem_6_mask <= io_enq_bits_mask_0; // @[AsyncQueue.scala:70:7, :82:16] mem_6_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16] end if (_widx_T_1 & (&index)) begin // @[Decoupled.scala:51:35] mem_7_opcode <= io_enq_bits_opcode_0; // @[AsyncQueue.scala:70:7, :82:16] mem_7_param <= io_enq_bits_param_0; // @[AsyncQueue.scala:70:7, :82:16] mem_7_size <= io_enq_bits_size_0; // @[AsyncQueue.scala:70:7, :82:16] mem_7_source <= io_enq_bits_source_0; // @[AsyncQueue.scala:70:7, :82:16] mem_7_address <= io_enq_bits_address_0; // @[AsyncQueue.scala:70:7, :82:16] mem_7_mask <= io_enq_bits_mask_0; // @[AsyncQueue.scala:70:7, :82:16] mem_7_data <= io_enq_bits_data_0; // @[AsyncQueue.scala:70:7, :82:16] end always @(posedge) always @(posedge clock or posedge _widx_T) begin // @[AsyncQueue.scala:70:7, :83:30] if (_widx_T) // @[AsyncQueue.scala:70:7, :83:30] widx_widx_bin <= 4'h0; // @[AsyncQueue.scala:52:25] else // @[AsyncQueue.scala:70:7] widx_widx_bin <= widx_incremented; // @[AsyncQueue.scala:51:27, :52:25] always @(posedge, posedge) always @(posedge clock or posedge _ready_reg_T) begin // @[AsyncQueue.scala:70:7, :90:35] if (_ready_reg_T) // @[AsyncQueue.scala:70:7, :90:35] ready_reg <= 1'h0; // @[AsyncQueue.scala:90:56] else // @[AsyncQueue.scala:70:7] ready_reg <= ready; // @[AsyncQueue.scala:85:26, :90:56] always @(posedge, posedge) always @(posedge clock or posedge _widx_reg_T) begin // @[AsyncQueue.scala:70:7, :93:34] if (_widx_reg_T) // @[AsyncQueue.scala:70:7, :93:34] widx_gray <= 4'h0; // @[AsyncQueue.scala:52:25, :93:55] else // @[AsyncQueue.scala:70:7] widx_gray <= widx; // @[AsyncQueue.scala:54:17, :93:55] always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_63( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_95 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RecFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import consts._ class RecFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val in = Input(Bits((inExpWidth + inSigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in); if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- io.out := io.in<<(outSigWidth - inSigWidth) io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W) } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( inExpWidth, inSigWidth, outExpWidth, outSigWidth, flRoundOpt_sigMSBitAlwaysZero )) roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn) roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := rawIn roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } } File rawFloatFromRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ /---------------------------------------------------------------------------- \| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be \| set. ----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }	module RecFNToRecFN_31( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File Manager.scala: package rerocc.manager import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.prci._ import freechips.rocketchip.subsystem._ import rerocc.bus._ case class ReRoCCManagerParams( managerId: Int, ) case object ReRoCCManagerControlAddress extends Field[BigInt](0x20000) // For local PTW class MiniDCache(reRoCCId: Int, crossing: ClockCrossingType)(implicit p: Parameters) extends DCache(0, crossing)(p) { override def cacheClientParameters = Seq(TLMasterParameters.v1( name = s"ReRoCC ${reRoCCId} DCache", sourceId = IdRange(0, 1), supportsProbe = TransferSizes(cfg.blockBytes, cfg.blockBytes))) override def mmioClientParameters = Seq(TLMasterParameters.v1( name = s"ReRoCC ${reRoCCId} DCache MMIO", sourceId = IdRange(firstMMIO, firstMMIO + cfg.nMMIOs), requestFifo = true)) } class ReRoCCManager(reRoCCTileParams: ReRoCCTileParams, roccOpcode: UInt)(implicit p: Parameters) extends LazyModule { val node = ReRoCCManagerNode(ReRoCCManagerParams(reRoCCTileParams.reroccId)) val ibufEntries = p(ReRoCCIBufEntriesKey) override lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val manager_id = Input(UInt(log2Ceil(p(ReRoCCTileKey).size).W)) val cmd = Decoupled(new RoCCCommand) val resp = Flipped(Decoupled(new RoCCResponse)) val busy = Input(Bool()) val ptw = Flipped(new DatapathPTWIO) }) val (rerocc, edge) = node.in(0) val s_idle :: s_active :: s_rel_wait :: s_sfence :: s_unbusy :: Nil = Enum(5) val numClients = edge.cParams.clients.map(_.nCfgs).sum val client = Reg(UInt(log2Ceil(numClients).W)) val status = Reg(new MStatus) val ptbr = Reg(new PTBR) val state = RegInit(s_idle) io.ptw.ptbr := ptbr io.ptw.hgatp := 0.U.asTypeOf(new PTBR) io.ptw.vsatp := 0.U.asTypeOf(new PTBR) io.ptw.sfence.valid := state === s_sfence io.ptw.sfence.bits.rs1 := false.B io.ptw.sfence.bits.rs2 := false.B io.ptw.sfence.bits.addr := 0.U io.ptw.sfence.bits.asid := 0.U io.ptw.sfence.bits.hv := false.B io.ptw.sfence.bits.hg := false.B io.ptw.status := status io.ptw.hstatus := 0.U.asTypeOf(new HStatus) io.ptw.gstatus := 0.U.asTypeOf(new MStatus) io.ptw.pmp.foreach(_ := 0.U.asTypeOf(new PMP)) val rr_req = Queue(rerocc.req) val (req_first, req_last, req_beat) = ReRoCCMsgFirstLast(rr_req, true) val rr_resp = rerocc.resp rr_req.ready := false.B val inst_q = Module(new Queue(new RoCCCommand, ibufEntries)) val enq_inst = Reg(new RoCCCommand) val next_enq_inst = WireInit(enq_inst) inst_q.io.enq.valid := false.B inst_q.io.enq.bits := next_enq_inst inst_q.io.enq.bits.inst.opcode := roccOpcode // 0 -> acquire ack // 1 -> inst ack // 2 -> writeback // 3 -> rel // 4 -> unbusyack val resp_arb = Module(new ReRoCCMsgArbiter(edge.bundle, 5, false)) rr_resp <> resp_arb.io.out resp_arb.io.in.foreach { i => i.valid := false.B } val status_lower = Reg(UInt(64.W)) when (rr_req.valid) { when (rr_req.bits.opcode === ReRoCCProtocol.mAcquire) { rr_req.ready := resp_arb.io.in(0).ready resp_arb.io.in(0).valid := true.B when (state === s_idle && rr_req.fire) { state := s_active client := rr_req.bits.client_id } } .elsewhen (rr_req.bits.opcode === ReRoCCProtocol.mUStatus) { rr_req.ready := !inst_q.io.deq.valid && !io.busy when (!inst_q.io.deq.valid && !io.busy) { when (req_first) { status_lower := rr_req.bits.data } when (req_last) { status := Cat(rr_req.bits.data, status_lower).asTypeOf(new MStatus) } } } .elsewhen (rr_req.bits.opcode === ReRoCCProtocol.mUPtbr) { rr_req.ready := !inst_q.io.deq.valid && !io.busy when (!inst_q.io.deq.valid && !io.busy) { ptbr := rr_req.bits.data.asTypeOf(new PTBR) } } .elsewhen (rr_req.bits.opcode === ReRoCCProtocol.mInst) { assert(state === s_active && inst_q.io.enq.ready) rr_req.ready := true.B when (req_beat === 0.U) { val inst = rr_req.bits.data.asTypeOf(new RoCCInstruction) enq_inst.inst := inst when (!inst.xs1 ) { enq_inst.rs1 := 0.U } when (!inst.xs2 ) { enq_inst.rs2 := 0.U } } .otherwise { val enq_inst_rs1 = enq_inst.inst.xs1 && req_beat === 1.U val enq_inst_rs2 = enq_inst.inst.xs2 && req_beat === Mux(enq_inst.inst.xs1, 2.U, 1.U) when (enq_inst_rs1) { next_enq_inst.rs1 := rr_req.bits.data } when (enq_inst_rs2) { next_enq_inst.rs2 := rr_req.bits.data } enq_inst := next_enq_inst } when (req_last) { inst_q.io.enq.valid := true.B assert(inst_q.io.enq.ready) } } .elsewhen (rr_req.bits.opcode === ReRoCCProtocol.mRelease) { rr_req.ready := true.B state := s_rel_wait } .elsewhen (rr_req.bits.opcode === ReRoCCProtocol.mUnbusy) { rr_req.ready := true.B state := s_unbusy } .otherwise { assert(false.B) } } // acquire->ack/nack resp_arb.io.in(0).bits.opcode := ReRoCCProtocol.sAcqResp resp_arb.io.in(0).bits.client_id := rr_req.bits.client_id resp_arb.io.in(0).bits.manager_id := io.manager_id resp_arb.io.in(0).bits.data := state === s_idle // insts -> (inst_q, inst_ack) io.cmd.valid := inst_q.io.deq.valid && resp_arb.io.in(1).ready io.cmd.bits := inst_q.io.deq.bits inst_q.io.deq.ready := io.cmd.ready && resp_arb.io.in(1).ready resp_arb.io.in(1).valid := inst_q.io.deq.valid && io.cmd.ready resp_arb.io.in(1).bits.opcode := ReRoCCProtocol.sInstAck resp_arb.io.in(1).bits.client_id := client resp_arb.io.in(1).bits.manager_id := io.manager_id resp_arb.io.in(1).bits.data := 0.U // writebacks val resp = Queue(io.resp) val resp_rd = RegInit(false.B) resp_arb.io.in(2).valid := resp.valid resp_arb.io.in(2).bits.opcode := ReRoCCProtocol.sWrite resp_arb.io.in(2).bits.client_id := client resp_arb.io.in(2).bits.manager_id := io.manager_id resp_arb.io.in(2).bits.data := Mux(resp_rd, resp.bits.rd, resp.bits.data) when (resp_arb.io.in(2).fire) { resp_rd := !resp_rd } resp.ready := resp_arb.io.in(2).ready && resp_rd // release resp_arb.io.in(3).valid := state === s_rel_wait && !io.busy && inst_q.io.count === 0.U resp_arb.io.in(3).bits.opcode := ReRoCCProtocol.sRelResp resp_arb.io.in(3).bits.client_id := client resp_arb.io.in(3).bits.manager_id := io.manager_id resp_arb.io.in(3).bits.data := 0.U when (resp_arb.io.in(3).fire) { state := s_sfence } when (state === s_sfence) { state := s_idle } // unbusyack resp_arb.io.in(4).valid := state === s_unbusy && !io.busy && inst_q.io.count === 0.U resp_arb.io.in(4).bits.opcode := ReRoCCProtocol.sUnbusyAck resp_arb.io.in(4).bits.client_id := client resp_arb.io.in(4).bits.manager_id := io.manager_id resp_arb.io.in(4).bits.data := 0.U when (resp_arb.io.in(4).fire) { state := s_active } } } class ReRoCCManagerTile()(implicit p: Parameters) extends LazyModule { val reRoCCParams = p(TileKey).asInstanceOf[ReRoCCTileParams] val reRoCCId = reRoCCParams.reroccId def this(tileParams: ReRoCCTileParams, p: Parameters) = { this()(p.alterMap(Map( TileKey -> tileParams, TileVisibilityNodeKey -> TLEphemeralNode()(ValName("rerocc_manager")) ))) } val reroccManagerIdSinkNode = BundleBridgeSink[UInt]() val rocc = reRoCCParams.genRoCC.get(p) require(rocc.opcodes.opcodes.size == 1) val rerocc_manager = LazyModule(new ReRoCCManager(reRoCCParams, rocc.opcodes.opcodes.head)) val reRoCCNode = ReRoCCIdentityNode() rerocc_manager.node := ReRoCCBuffer() := reRoCCNode val tlNode = p(TileVisibilityNodeKey) // throttle before TL Node (merged -> val tlXbar = TLXbar() val stlNode = TLIdentityNode() tlXbar :=* rocc.atlNode if (reRoCCParams.mergeTLNodes) { tlXbar :=* rocc.tlNode } else { tlNode :=* rocc.tlNode } tlNode :=* TLBuffer() :=* tlXbar rocc.stlNode := stlNode // minicache val dcache = reRoCCParams.dcacheParams.map(_ => LazyModule(new MiniDCache(reRoCCId, SynchronousCrossing())(p))) dcache.map(d => tlXbar := TLWidthWidget(reRoCCParams.rowBits/8) := d.node) val hellammio: Option[HellaMMIO] = if (!dcache.isDefined) { val h = LazyModule(new HellaMMIO(s"ReRoCC $reRoCCId MMIO")) tlXbar := h.node Some(h) } else { None } val ctrl = LazyModule(new ReRoCCManagerControl(reRoCCId, 8)) override lazy val module = new LazyModuleImp(this) { val dcacheArb = Module(new HellaCacheArbiter(2)(p)) dcache.map(_.module.io.cpu).getOrElse(hellammio.get.module.io) <> dcacheArb.io.mem val edge = dcache.map(_.node.edges.out(0)).getOrElse(hellammio.get.node.edges.out(0)) val ptw = Module(new PTW(1 + rocc.nPTWPorts)(edge, p)) if (dcache.isDefined) { dcache.get.module.io.tlb_port := DontCare dcache.get.module.io.tlb_port.req.valid := false.B ptw.io.requestor(0) <> dcache.get.module.io.ptw } else { ptw.io.requestor(0) := DontCare ptw.io.requestor(0).req.valid := false.B } dcacheArb.io.requestor(0) <> ptw.io.mem val dcIF = Module(new SimpleHellaCacheIF) dcIF.io.requestor <> rocc.module.io.mem dcacheArb.io.requestor(1) <> dcIF.io.cache for (i <- 0 until rocc.nPTWPorts) { ptw.io.requestor(1+i) <> rocc.module.io.ptw(i) } rerocc_manager.module.io.manager_id := reroccManagerIdSinkNode.bundle rocc.module.io.cmd <> rerocc_manager.module.io.cmd rerocc_manager.module.io.resp <> rocc.module.io.resp rerocc_manager.module.io.busy := rocc.module.io.busy ptw.io.dpath <> rerocc_manager.module.io.ptw rocc.module.io.fpu_req.ready := false.B assert(!rocc.module.io.fpu_req.valid) rocc.module.io.fpu_resp.valid := false.B rocc.module.io.fpu_resp.bits := DontCare rocc.module.io.exception := false.B ctrl.module.io.mgr_busy := rerocc_manager.module.io.busy ctrl.module.io.rocc_busy := rocc.module.io.busy } } File LazyRoCC.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util._ import chisel3.experimental.IntParam import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.rocket.{ MStatus, HellaCacheIO, TLBPTWIO, CanHavePTW, CanHavePTWModule, SimpleHellaCacheIF, M_XRD, PTE, PRV, M_SZ } import freechips.rocketchip.tilelink.{ TLNode, TLIdentityNode, TLClientNode, TLMasterParameters, TLMasterPortParameters } import freechips.rocketchip.util.InOrderArbiter case object BuildRoCC extends Field[Seq[Parameters => LazyRoCC]](Nil) class RoCCInstruction extends Bundle { val funct = Bits(7.W) val rs2 = Bits(5.W) val rs1 = Bits(5.W) val xd = Bool() val xs1 = Bool() val xs2 = Bool() val rd = Bits(5.W) val opcode = Bits(7.W) } class RoCCCommand(implicit p: Parameters) extends CoreBundle()(p) { val inst = new RoCCInstruction val rs1 = Bits(xLen.W) val rs2 = Bits(xLen.W) val status = new MStatus } class RoCCResponse(implicit p: Parameters) extends CoreBundle()(p) { val rd = Bits(5.W) val data = Bits(xLen.W) } class RoCCCoreIO(val nRoCCCSRs: Int = 0)(implicit p: Parameters) extends CoreBundle()(p) { val cmd = Flipped(Decoupled(new RoCCCommand)) val resp = Decoupled(new RoCCResponse) val mem = new HellaCacheIO val busy = Output(Bool()) val interrupt = Output(Bool()) val exception = Input(Bool()) val csrs = Flipped(Vec(nRoCCCSRs, new CustomCSRIO)) } class RoCCIO(val nPTWPorts: Int, nRoCCCSRs: Int)(implicit p: Parameters) extends RoCCCoreIO(nRoCCCSRs)(p) { val ptw = Vec(nPTWPorts, new TLBPTWIO) val fpu_req = Decoupled(new FPInput) val fpu_resp = Flipped(Decoupled(new FPResult)) } /* Base classes for Diplomatic TL2 RoCC units / abstract class LazyRoCC( val opcodes: OpcodeSet, val nPTWPorts: Int = 0, val usesFPU: Boolean = false, val roccCSRs: Seq[CustomCSR] = Nil )(implicit p: Parameters) extends LazyModule { val module: LazyRoCCModuleImp require(roccCSRs.map(_.id).toSet.size == roccCSRs.size) val atlNode: TLNode = TLIdentityNode() val tlNode: TLNode = TLIdentityNode() val stlNode: TLNode = TLIdentityNode() } class LazyRoCCModuleImp(outer: LazyRoCC) extends LazyModuleImp(outer) { val io = IO(new RoCCIO(outer.nPTWPorts, outer.roccCSRs.size)) io := DontCare } / Mixins for including RoCC */ trait HasLazyRoCC extends CanHavePTW { this: BaseTile => val roccs = p(BuildRoCC).map(_(p)) val roccCSRs = roccs.map(_.roccCSRs) // the set of custom CSRs requested by all roccs require(roccCSRs.flatten.map(_.id).toSet.size == roccCSRs.flatten.size, "LazyRoCC instantiations require overlapping CSRs") roccs.map(_.atlNode).foreach { atl => tlMasterXbar.node := atl } roccs.map(_.tlNode).foreach { tl => tlOtherMastersNode :=* tl } roccs.map(_.stlNode).foreach { stl => stl := tlSlaveXbar.node } nPTWPorts += roccs.map(_.nPTWPorts).sum nDCachePorts += roccs.size } trait HasLazyRoCCModule extends CanHavePTWModule with HasCoreParameters { this: RocketTileModuleImp => val (respArb, cmdRouter) = if(outer.roccs.nonEmpty) { val respArb = Module(new RRArbiter(new RoCCResponse()(outer.p), outer.roccs.size)) val cmdRouter = Module(new RoccCommandRouter(outer.roccs.map(_.opcodes))(outer.p)) outer.roccs.zipWithIndex.foreach { case (rocc, i) => rocc.module.io.ptw ++=: ptwPorts rocc.module.io.cmd <> cmdRouter.io.out(i) val dcIF = Module(new SimpleHellaCacheIF()(outer.p)) dcIF.io.requestor <> rocc.module.io.mem dcachePorts += dcIF.io.cache respArb.io.in(i) <> Queue(rocc.module.io.resp) } (Some(respArb), Some(cmdRouter)) } else { (None, None) } val roccCSRIOs = outer.roccs.map(_.module.io.csrs) } class AccumulatorExample(opcodes: OpcodeSet, val n: Int = 4)(implicit p: Parameters) extends LazyRoCC(opcodes) { override lazy val module = new AccumulatorExampleModuleImp(this) } class AccumulatorExampleModuleImp(outer: AccumulatorExample)(implicit p: Parameters) extends LazyRoCCModuleImp(outer) with HasCoreParameters { val regfile = Mem(outer.n, UInt(xLen.W)) val busy = RegInit(VecInit(Seq.fill(outer.n){false.B})) val cmd = Queue(io.cmd) val funct = cmd.bits.inst.funct val addr = cmd.bits.rs2(log2Up(outer.n)-1,0) val doWrite = funct === 0.U val doRead = funct === 1.U val doLoad = funct === 2.U val doAccum = funct === 3.U val memRespTag = io.mem.resp.bits.tag(log2Up(outer.n)-1,0) // datapath val addend = cmd.bits.rs1 val accum = regfile(addr) val wdata = Mux(doWrite, addend, accum + addend) when (cmd.fire && (doWrite \|\| doAccum)) { regfile(addr) := wdata } when (io.mem.resp.valid) { regfile(memRespTag) := io.mem.resp.bits.data busy(memRespTag) := false.B } // control when (io.mem.req.fire) { busy(addr) := true.B } val doResp = cmd.bits.inst.xd val stallReg = busy(addr) val stallLoad = doLoad && !io.mem.req.ready val stallResp = doResp && !io.resp.ready cmd.ready := !stallReg && !stallLoad && !stallResp // command resolved if no stalls AND not issuing a load that will need a request // PROC RESPONSE INTERFACE io.resp.valid := cmd.valid && doResp && !stallReg && !stallLoad // valid response if valid command, need a response, and no stalls io.resp.bits.rd := cmd.bits.inst.rd // Must respond with the appropriate tag or undefined behavior io.resp.bits.data := accum // Semantics is to always send out prior accumulator register value io.busy := cmd.valid \|\| busy.reduce(_\|\|_) // Be busy when have pending memory requests or committed possibility of pending requests io.interrupt := false.B // Set this true to trigger an interrupt on the processor (please refer to supervisor documentation) // MEMORY REQUEST INTERFACE io.mem.req.valid := cmd.valid && doLoad && !stallReg && !stallResp io.mem.req.bits.addr := addend io.mem.req.bits.tag := addr io.mem.req.bits.cmd := M_XRD // perform a load (M_XWR for stores) io.mem.req.bits.size := log2Ceil(8).U io.mem.req.bits.signed := false.B io.mem.req.bits.data := 0.U // we're not performing any stores... io.mem.req.bits.phys := false.B io.mem.req.bits.dprv := cmd.bits.status.dprv io.mem.req.bits.dv := cmd.bits.status.dv io.mem.req.bits.no_resp := false.B } class TranslatorExample(opcodes: OpcodeSet)(implicit p: Parameters) extends LazyRoCC(opcodes, nPTWPorts = 1) { override lazy val module = new TranslatorExampleModuleImp(this) } class TranslatorExampleModuleImp(outer: TranslatorExample)(implicit p: Parameters) extends LazyRoCCModuleImp(outer) with HasCoreParameters { val req_addr = Reg(UInt(coreMaxAddrBits.W)) val req_rd = Reg(chiselTypeOf(io.resp.bits.rd)) val req_offset = req_addr(pgIdxBits - 1, 0) val req_vpn = req_addr(coreMaxAddrBits - 1, pgIdxBits) val pte = Reg(new PTE) val s_idle :: s_ptw_req :: s_ptw_resp :: s_resp :: Nil = Enum(4) val state = RegInit(s_idle) io.cmd.ready := (state === s_idle) when (io.cmd.fire) { req_rd := io.cmd.bits.inst.rd req_addr := io.cmd.bits.rs1 state := s_ptw_req } private val ptw = io.ptw(0) when (ptw.req.fire) { state := s_ptw_resp } when (state === s_ptw_resp && ptw.resp.valid) { pte := ptw.resp.bits.pte state := s_resp } when (io.resp.fire) { state := s_idle } ptw.req.valid := (state === s_ptw_req) ptw.req.bits.valid := true.B ptw.req.bits.bits.addr := req_vpn io.resp.valid := (state === s_resp) io.resp.bits.rd := req_rd io.resp.bits.data := Mux(pte.leaf(), Cat(pte.ppn, req_offset), -1.S(xLen.W).asUInt) io.busy := (state =/= s_idle) io.interrupt := false.B io.mem.req.valid := false.B } class CharacterCountExample(opcodes: OpcodeSet)(implicit p: Parameters) extends LazyRoCC(opcodes) { override lazy val module = new CharacterCountExampleModuleImp(this) override val atlNode = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1("CharacterCountRoCC"))))) } class CharacterCountExampleModuleImp(outer: CharacterCountExample)(implicit p: Parameters) extends LazyRoCCModuleImp(outer) with HasCoreParameters with HasL1CacheParameters { val cacheParams = tileParams.dcache.get private val blockOffset = blockOffBits private val beatOffset = log2Up(cacheDataBits/8) val needle = Reg(UInt(8.W)) val addr = Reg(UInt(coreMaxAddrBits.W)) val count = Reg(UInt(xLen.W)) val resp_rd = Reg(chiselTypeOf(io.resp.bits.rd)) val addr_block = addr(coreMaxAddrBits - 1, blockOffset) val offset = addr(blockOffset - 1, 0) val next_addr = (addr_block + 1.U) << blockOffset.U val s_idle :: s_acq :: s_gnt :: s_check :: s_resp :: Nil = Enum(5) val state = RegInit(s_idle) val (tl_out, edgesOut) = outer.atlNode.out(0) val gnt = tl_out.d.bits val recv_data = Reg(UInt(cacheDataBits.W)) val recv_beat = RegInit(0.U(log2Up(cacheDataBeats+1).W)) val data_bytes = VecInit(Seq.tabulate(cacheDataBits/8) { i => recv_data(8 (i + 1) - 1, 8 * i) }) val zero_match = data_bytes.map(_ === 0.U) val needle_match = data_bytes.map(_ === needle) val first_zero = PriorityEncoder(zero_match) val chars_found = PopCount(needle_match.zipWithIndex.map { case (matches, i) => val idx = Cat(recv_beat - 1.U, i.U(beatOffset.W)) matches && idx >= offset && i.U <= first_zero }) val zero_found = zero_match.reduce(_ \|\| _) val finished = Reg(Bool()) io.cmd.ready := (state === s_idle) io.resp.valid := (state === s_resp) io.resp.bits.rd := resp_rd io.resp.bits.data := count tl_out.a.valid := (state === s_acq) tl_out.a.bits := edgesOut.Get( fromSource = 0.U, toAddress = addr_block << blockOffset, lgSize = lgCacheBlockBytes.U)._2 tl_out.d.ready := (state === s_gnt) when (io.cmd.fire) { addr := io.cmd.bits.rs1 needle := io.cmd.bits.rs2 resp_rd := io.cmd.bits.inst.rd count := 0.U finished := false.B state := s_acq } when (tl_out.a.fire) { state := s_gnt } when (tl_out.d.fire) { recv_beat := recv_beat + 1.U recv_data := gnt.data state := s_check } when (state === s_check) { when (!finished) { count := count + chars_found } when (zero_found) { finished := true.B } when (recv_beat === cacheDataBeats.U) { addr := next_addr state := Mux(zero_found \|\| finished, s_resp, s_acq) recv_beat := 0.U } .otherwise { state := s_gnt } } when (io.resp.fire) { state := s_idle } io.busy := (state =/= s_idle) io.interrupt := false.B io.mem.req.valid := false.B // Tie off unused channels tl_out.b.ready := true.B tl_out.c.valid := false.B tl_out.e.valid := false.B } class BlackBoxExample(opcodes: OpcodeSet, blackBoxFile: String)(implicit p: Parameters) extends LazyRoCC(opcodes) { override lazy val module = new BlackBoxExampleModuleImp(this, blackBoxFile) } class BlackBoxExampleModuleImp(outer: BlackBoxExample, blackBoxFile: String)(implicit p: Parameters) extends LazyRoCCModuleImp(outer) with RequireSyncReset with HasCoreParameters { val blackbox = { val roccIo = io Module( new BlackBox( Map( "xLen" -> IntParam(xLen), "PRV_SZ" -> IntParam(PRV.SZ), "coreMaxAddrBits" -> IntParam(coreMaxAddrBits), "dcacheReqTagBits" -> IntParam(roccIo.mem.req.bits.tag.getWidth), "M_SZ" -> IntParam(M_SZ), "mem_req_bits_size_width" -> IntParam(roccIo.mem.req.bits.size.getWidth), "coreDataBits" -> IntParam(coreDataBits), "coreDataBytes" -> IntParam(coreDataBytes), "paddrBits" -> IntParam(paddrBits), "vaddrBitsExtended" -> IntParam(vaddrBitsExtended), "FPConstants_RM_SZ" -> IntParam(FPConstants.RM_SZ), "fLen" -> IntParam(fLen), "FPConstants_FLAGS_SZ" -> IntParam(FPConstants.FLAGS_SZ) ) ) with HasBlackBoxResource { val io = IO( new Bundle { val clock = Input(Clock()) val reset = Input(Reset()) val rocc = chiselTypeOf(roccIo) }) override def desiredName: String = blackBoxFile addResource(s"/vsrc/$blackBoxFile.v") } ) } blackbox.io.clock := clock blackbox.io.reset := reset blackbox.io.rocc.cmd <> io.cmd io.resp <> blackbox.io.rocc.resp io.mem <> blackbox.io.rocc.mem io.busy := blackbox.io.rocc.busy io.interrupt := blackbox.io.rocc.interrupt blackbox.io.rocc.exception := io.exception io.ptw <> blackbox.io.rocc.ptw io.fpu_req <> blackbox.io.rocc.fpu_req blackbox.io.rocc.fpu_resp <> io.fpu_resp } class OpcodeSet(val opcodes: Seq[UInt]) { def \|(set: OpcodeSet) = new OpcodeSet(this.opcodes ++ set.opcodes) def matches(oc: UInt) = opcodes.map(_ === oc).reduce(_ \|\| _) } object OpcodeSet { def custom0 = new OpcodeSet(Seq("b0001011".U)) def custom1 = new OpcodeSet(Seq("b0101011".U)) def custom2 = new OpcodeSet(Seq("b1011011".U)) def custom3 = new OpcodeSet(Seq("b1111011".U)) def all = custom0 \| custom1 \| custom2 \| custom3 } class RoccCommandRouter(opcodes: Seq[OpcodeSet])(implicit p: Parameters) extends CoreModule()(p) { val io = IO(new Bundle { val in = Flipped(Decoupled(new RoCCCommand)) val out = Vec(opcodes.size, Decoupled(new RoCCCommand)) val busy = Output(Bool()) }) val cmd = Queue(io.in) val cmdReadys = io.out.zip(opcodes).map { case (out, opcode) => val me = opcode.matches(cmd.bits.inst.opcode) out.valid := cmd.valid && me out.bits := cmd.bits out.ready && me } cmd.ready := cmdReadys.reduce(_ \|\| _) io.busy := cmd.valid assert(PopCount(cmdReadys) <= 1.U, "Custom opcode matched for more than one accelerator") } File Protocol.scala: package rerocc.bus import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tile._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import rerocc.client.{ReRoCCClientParams} import rerocc.manager.{ReRoCCManagerParams} object ReRoCCProtocol { val width = 3 val mAcquire = 0.U(width.W) // beat0: data = inst // beat1: data = mstatus[63:0] // beat2: data = mstatus[127:64] val mInst = 1.U(width.W) // beat0: data = mstatus[63:0] // beat1: data = mstatus[127:0] val mUStatus = 2.U(width.W) // beat0: data = ptbr val mUPtbr = 3.U(width.W) val mRelease = 4.U(width.W) val mUnbusy = 5.U(width.W) // data // data = acquired val sAcqResp = 0.U(width.W) // data = 0 val sInstAck = 1.U(width.W) // beat0: data = data // beat1: data = rd val sWrite = 2.U(width.W) val sRelResp = 3.U(width.W) val sUnbusyAck = 4.U(width.W) val MAX_BEATS = 3 } class ReRoCCMsgBundle(val params: ReRoCCBundleParams) extends Bundle { val opcode = UInt(ReRoCCProtocol.width.W) val client_id = UInt(params.clientIdBits.W) val manager_id = UInt(params.managerIdBits.W) val data = UInt(64.W) } object ReRoCCMsgFirstLast { def apply(m: DecoupledIO[ReRoCCMsgBundle], isReq: Boolean): (Bool, Bool, UInt) = { val beat = RegInit(0.U(log2Ceil(ReRoCCProtocol.MAX_BEATS).W)) val max_beat = RegInit(0.U(log2Ceil(ReRoCCProtocol.MAX_BEATS).W)) val first = beat === 0.U val last = Wire(Bool()) val inst = m.bits.data.asTypeOf(new RoCCInstruction) when (m.fire && first) { max_beat := 0.U if (isReq) { when (m.bits.opcode === ReRoCCProtocol.mInst) { max_beat := inst.xs1 +& inst.xs2 } .elsewhen (m.bits.opcode === ReRoCCProtocol.mUStatus) { max_beat := 1.U } } else { when (m.bits.opcode === ReRoCCProtocol.sWrite) { max_beat := 1.U } } } last := true.B if (isReq) { when (m.bits.opcode === ReRoCCProtocol.mUStatus) { last := beat === max_beat && !first } .elsewhen (m.bits.opcode === ReRoCCProtocol.mInst) { last := Mux(first, !inst.xs1 && !inst.xs2, beat === max_beat) } } else { when (m.bits.opcode === ReRoCCProtocol.sWrite) { last := beat === max_beat && !first } } when (m.fire) { beat := beat + 1.U } when (m.fire && last) { max_beat := 0.U beat := 0.U } (first, last, beat) } } class ReRoCCBundle(val params: ReRoCCBundleParams) extends Bundle { val req = Decoupled(new ReRoCCMsgBundle(params)) val resp = Flipped(Decoupled(new ReRoCCMsgBundle(params))) } case class EmptyParams() object ReRoCCImp extends SimpleNodeImp[ReRoCCClientPortParams, ReRoCCManagerPortParams, ReRoCCEdgeParams, ReRoCCBundle] { def edge(pd: ReRoCCClientPortParams, pu: ReRoCCManagerPortParams, p: Parameters, sourceInfo: SourceInfo) = { ReRoCCEdgeParams(pu, pd) } def bundle(e: ReRoCCEdgeParams) = new ReRoCCBundle(e.bundle) def render(ei: ReRoCCEdgeParams) = RenderedEdge(colour = "#000000" /* black /) } case class ReRoCCClientNode(clientParams: ReRoCCClientParams)(implicit valName: ValName) extends SourceNode(ReRoCCImp)(Seq(ReRoCCClientPortParams(Seq(clientParams)))) case class ReRoCCManagerNode(managerParams: ReRoCCManagerParams)(implicit valName: ValName) extends SinkNode(ReRoCCImp)(Seq(ReRoCCManagerPortParams(Seq(managerParams)))) class ReRoCCBuffer(b: BufferParams = BufferParams.default)(implicit p: Parameters) extends LazyModule { val node = new AdapterNode(ReRoCCImp)({s => s}, {s => s}) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, _), (out, _)) => out.req <> b(in.req) in.resp <> b(out.resp) } } } object ReRoCCBuffer { def apply(b: BufferParams = BufferParams.default)(implicit p: Parameters) = { val rerocc_buffer = LazyModule(new ReRoCCBuffer(b)(p)) rerocc_buffer.node } } case class ReRoCCIdentityNode()(implicit valName: ValName) extends IdentityNode(ReRoCCImp)() File WidthWidget.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.util.{Repeater, UIntToOH1} // innBeatBytes => the new client-facing bus width class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule { private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes val node = new TLAdapterNode( clientFn = { case c => c }, managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){ override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired) } override lazy val desiredName = s"TLWidthWidget$innerBeatBytes" lazy val module = new Impl class Impl extends LazyModuleImp(this) { def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = outBytes / inBytes val keepBits = log2Ceil(outBytes) val dropBits = log2Ceil(inBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit \|\| !hasData val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR } val corrupt_reg = RegInit(false.B) val corrupt_in = edgeIn.corrupt(in.bits) val corrupt_out = corrupt_in \|\| corrupt_reg when (in.fire) { count := count + 1.U corrupt_reg := corrupt_out when (last) { count := 0.U corrupt_reg := false.B } } def helper(idata: UInt): UInt = { // rdata is X until the first time a multi-beat write occurs. // Prevent the X from leaking outside by jamming the mux control until // the first time rdata is written (and hence no longer X). val rdata_written_once = RegInit(false.B) val masked_enable = enable.map(_ \|\| !rdata_written_once) val odata = Seq.fill(ratio) { WireInit(idata) } val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata))) val pdata = rdata :+ idata val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) } when (in.fire && !last) { rdata_written_once := true.B (rdata zip mdata) foreach { case (r, m) => r := m } } Cat(mdata.reverse) } in.ready := out.ready \|\| !last out.valid := in.valid && last out.bits := in.bits // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits))) edgeOut.corrupt(out.bits) := corrupt_out (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W)) case (o: TLBundleC, i: TLBundleC) => () case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossible bundle combination in WidthWidget") } } def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { val inBytes = edgeIn.manager.beatBytes val outBytes = edgeOut.manager.beatBytes val ratio = inBytes / outBytes val keepBits = log2Ceil(inBytes) val dropBits = log2Ceil(outBytes) val countBits = log2Ceil(ratio) val size = edgeIn.size(in.bits) val hasData = edgeIn.hasData(in.bits) val limit = UIntToOH1(size, keepBits) >> dropBits val count = RegInit(0.U(countBits.W)) val first = count === 0.U val last = count === limit \|\| !hasData when (out.fire) { count := count + 1.U when (last) { count := 0.U } } // For sub-beat transfer, extract which part matters val sel = in.bits match { case a: TLBundleA => a.address(keepBits-1, dropBits) case b: TLBundleB => b.address(keepBits-1, dropBits) case c: TLBundleC => c.address(keepBits-1, dropBits) case d: TLBundleD => { val sel = sourceMap(d.source) val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway } } val index = sel \| count def helper(idata: UInt, width: Int): UInt = { val mux = VecInit.tabulate(ratio) { i => idata((i+1)outByteswidth-1, ioutByteswidth) } mux(index) } out.bits := in.bits out.valid := in.valid in.ready := out.ready // Don't put down hardware if we never carry data edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8)) (out.bits, in.bits) match { case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1) case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1) case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok case (o: TLBundleD, i: TLBundleD) => () case _ => require(false, "Impossbile bundle combination in WidthWidget") } // Repeat the input if we're not last !last } def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = { if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) { // nothing to do; pass it through out.bits := in.bits out.valid := in.valid in.ready := out.ready } else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) { // split input to output val repeat = Wire(Bool()) val repeated = Repeater(in, repeat) val cated = Wire(chiselTypeOf(repeated)) cated <> repeated edgeIn.data(cated.bits) := Cat( edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes8-1, edgeOut.manager.beatBytes8), edgeIn.data(in.bits)(edgeOut.manager.beatBytes8-1, 0)) repeat := split(edgeIn, cated, edgeOut, out, sourceMap) } else { // merge input to output merge(edgeIn, in, edgeOut, out) } } (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => // If the master is narrower than the slave, the D channel must be narrowed. // This is tricky, because the D channel has no address data. // Thus, you don't know which part of a sub-beat transfer to extract. // To fix this, we record the relevant address bits for all sources. // The assumption is that this sort of situation happens only where // you connect a narrow master to the system bus, so there are few sources. def sourceMap(source_bits: UInt) = { val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes) val keepBits = log2Ceil(edgeOut.manager.beatBytes) val dropBits = log2Ceil(edgeIn.manager.beatBytes) val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W))) val a_sel = in.a.bits.address(keepBits-1, dropBits) when (in.a.fire) { if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning sources(0) := a_sel } else { sources(in.a.bits.source) := a_sel } } // depopulate unused source registers: edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U } val bypass = in.a.valid && in.a.bits.source === source if (edgeIn.manager.minLatency > 0) sources(source) else Mux(bypass, a_sel, sources(source)) } splice(edgeIn, in.a, edgeOut, out.a, sourceMap) splice(edgeOut, out.d, edgeIn, in.d, sourceMap) if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { splice(edgeOut, out.b, edgeIn, in.b, sourceMap) splice(edgeIn, in.c, edgeOut, out.c, sourceMap) out.e.valid := in.e.valid out.e.bits := in.e.bits in.e.ready := out.e.ready } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLWidthWidget { def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode = { val widget = LazyModule(new TLWidthWidget(innerBeatBytes)) widget.node } def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("WidthWidget")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) (ram.node := TLDelayer(0.1) := TLFragmenter(4, 256) := TLWidthWidget(second) := TLWidthWidget(first) := TLDelayer(0.1) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module) dut.io.start := DontCare io.finished := dut.io.finished } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size * node.out.size) > (832)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source \| r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source \| r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink \| r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ \|\| _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) \|\| o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) \|\| o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) \|\| (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }	module ReRoCCManagerTile_3( // @[Manager.scala:237:34] input clock, // @[Manager.scala:237:34] input reset, // @[Manager.scala:237:34] output auto_ctrl_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_ctrl_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrl_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrl_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_ctrl_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_ctrl_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [11:0] auto_ctrl_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_ctrl_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_ctrl_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_ctrl_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_ctrl_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_ctrl_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_ctrl_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_ctrl_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_ctrl_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_ctrl_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_buffer_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_buffer_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_buffer_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_buffer_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_re_ro_cc_in_req_ready, // @[LazyModuleImp.scala:107:25] input auto_re_ro_cc_in_req_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_re_ro_cc_in_req_bits_opcode, // @[LazyModuleImp.scala:107:25] input [3:0] auto_re_ro_cc_in_req_bits_client_id, // @[LazyModuleImp.scala:107:25] input auto_re_ro_cc_in_req_bits_manager_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_re_ro_cc_in_req_bits_data, // @[LazyModuleImp.scala:107:25] input auto_re_ro_cc_in_resp_ready, // @[LazyModuleImp.scala:107:25] output auto_re_ro_cc_in_resp_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_re_ro_cc_in_resp_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_re_ro_cc_in_resp_bits_client_id, // @[LazyModuleImp.scala:107:25] output auto_re_ro_cc_in_resp_bits_manager_id, // @[LazyModuleImp.scala:107:25] output [63:0] auto_re_ro_cc_in_resp_bits_data, // @[LazyModuleImp.scala:107:25] input [6:0] auto_rerocc_manager_id_sink_in // @[LazyModuleImp.scala:107:25] ); wire reRoCCNodeOut_resp_valid; // @[MixedNode.scala:542:17] wire [63:0] reRoCCNodeOut_resp_bits_data; // @[MixedNode.scala:542:17] wire reRoCCNodeOut_resp_bits_manager_id; // @[MixedNode.scala:542:17] wire [3:0] reRoCCNodeOut_resp_bits_client_id; // @[MixedNode.scala:542:17] wire [2:0] reRoCCNodeOut_resp_bits_opcode; // @[MixedNode.scala:542:17] wire reRoCCNodeOut_req_ready; // @[MixedNode.scala:542:17] wire widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] xbar_out_0_e_bits_sink; // @[Xbar.scala:216:19] wire [2:0] xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19] wire xbar_in_0_d_bits_source; // @[Xbar.scala:159:18] wire xbar_in_0_c_bits_source; // @[Xbar.scala:159:18] wire xbar_in_0_b_bits_source; // @[Xbar.scala:159:18] wire xbar_in_0_a_bits_source; // @[Xbar.scala:159:18] wire xbar_auto_anon_out_e_ready; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire [63:0] xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire [3:0] xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire [1:0] xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_c_ready; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_b_valid; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_b_bits_corrupt; // @[Xbar.scala:74:9] wire [63:0] xbar_auto_anon_out_b_bits_data; // @[Xbar.scala:74:9] wire [7:0] xbar_auto_anon_out_b_bits_mask; // @[Xbar.scala:74:9] wire [31:0] xbar_auto_anon_out_b_bits_address; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_b_bits_source; // @[Xbar.scala:74:9] wire [3:0] xbar_auto_anon_out_b_bits_size; // @[Xbar.scala:74:9] wire [1:0] xbar_auto_anon_out_b_bits_param; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_out_b_bits_opcode; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_e_valid; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_e_ready; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_in_e_bits_sink; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_d_valid; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_d_bits_corrupt; // @[Xbar.scala:74:9] wire [63:0] xbar_auto_anon_in_d_bits_data; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_d_bits_denied; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_in_d_bits_sink; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_d_bits_source; // @[Xbar.scala:74:9] wire [3:0] xbar_auto_anon_in_d_bits_size; // @[Xbar.scala:74:9] wire [1:0] xbar_auto_anon_in_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_in_d_bits_opcode; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_c_valid; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_c_ready; // @[Xbar.scala:74:9] wire [63:0] xbar_auto_anon_in_c_bits_data; // @[Xbar.scala:74:9] wire [31:0] xbar_auto_anon_in_c_bits_address; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_c_bits_source; // @[Xbar.scala:74:9] wire [3:0] xbar_auto_anon_in_c_bits_size; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_in_c_bits_param; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_in_c_bits_opcode; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_b_valid; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_b_ready; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_b_bits_corrupt; // @[Xbar.scala:74:9] wire [63:0] xbar_auto_anon_in_b_bits_data; // @[Xbar.scala:74:9] wire [7:0] xbar_auto_anon_in_b_bits_mask; // @[Xbar.scala:74:9] wire [31:0] xbar_auto_anon_in_b_bits_address; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_b_bits_source; // @[Xbar.scala:74:9] wire [3:0] xbar_auto_anon_in_b_bits_size; // @[Xbar.scala:74:9] wire [1:0] xbar_auto_anon_in_b_bits_param; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_in_b_bits_opcode; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_a_ready; // @[Xbar.scala:74:9] wire [63:0] xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire [7:0] xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [31:0] xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [3:0] xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire _dcIF_io_cache_req_valid; // @[Manager.scala:255:22] wire [39:0] _dcIF_io_cache_req_bits_addr; // @[Manager.scala:255:22] wire [7:0] _dcIF_io_cache_req_bits_tag; // @[Manager.scala:255:22] wire [1:0] _dcIF_io_cache_req_bits_dprv; // @[Manager.scala:255:22] wire _dcIF_io_cache_req_bits_dv; // @[Manager.scala:255:22] wire [63:0] _dcIF_io_cache_s1_data_data; // @[Manager.scala:255:22] wire [7:0] _dcIF_io_cache_s1_data_mask; // @[Manager.scala:255:22] wire _ptw_io_requestor_0_req_ready; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_valid; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_ae_ptw; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_ae_final; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_pf; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_gf; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_hr; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_hw; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_hx; // @[Manager.scala:243:21] wire [9:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_future; // @[Manager.scala:243:21] wire [43:0] _ptw_io_requestor_0_resp_bits_pte_ppn; // @[Manager.scala:243:21] wire [1:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_software; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_pte_d; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_pte_a; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_pte_g; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_pte_u; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_pte_x; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_pte_w; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_pte_r; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_pte_v; // @[Manager.scala:243:21] wire [1:0] _ptw_io_requestor_0_resp_bits_level; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_homogeneous; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_gpa_valid; // @[Manager.scala:243:21] wire [38:0] _ptw_io_requestor_0_resp_bits_gpa_bits; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_resp_bits_gpa_is_pte; // @[Manager.scala:243:21] wire [3:0] _ptw_io_requestor_0_ptbr_mode; // @[Manager.scala:243:21] wire [15:0] _ptw_io_requestor_0_ptbr_asid; // @[Manager.scala:243:21] wire [43:0] _ptw_io_requestor_0_ptbr_ppn; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_debug; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_cease; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_wfi; // @[Manager.scala:243:21] wire [31:0] _ptw_io_requestor_0_status_isa; // @[Manager.scala:243:21] wire [1:0] _ptw_io_requestor_0_status_dprv; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_dv; // @[Manager.scala:243:21] wire [1:0] _ptw_io_requestor_0_status_prv; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_v; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_sd; // @[Manager.scala:243:21] wire [22:0] _ptw_io_requestor_0_status_zero2; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_mpv; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_gva; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_mbe; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_sbe; // @[Manager.scala:243:21] wire [1:0] _ptw_io_requestor_0_status_sxl; // @[Manager.scala:243:21] wire [1:0] _ptw_io_requestor_0_status_uxl; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_sd_rv32; // @[Manager.scala:243:21] wire [7:0] _ptw_io_requestor_0_status_zero1; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_tsr; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_tw; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_tvm; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_mxr; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_sum; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_mprv; // @[Manager.scala:243:21] wire [1:0] _ptw_io_requestor_0_status_xs; // @[Manager.scala:243:21] wire [1:0] _ptw_io_requestor_0_status_fs; // @[Manager.scala:243:21] wire [1:0] _ptw_io_requestor_0_status_mpp; // @[Manager.scala:243:21] wire [1:0] _ptw_io_requestor_0_status_vs; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_spp; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_mpie; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_ube; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_spie; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_upie; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_mie; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_hie; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_sie; // @[Manager.scala:243:21] wire _ptw_io_requestor_0_status_uie; // @[Manager.scala:243:21] wire _ptw_io_mem_req_valid; // @[Manager.scala:243:21] wire [39:0] _ptw_io_mem_req_bits_addr; // @[Manager.scala:243:21] wire _ptw_io_mem_req_bits_dv; // @[Manager.scala:243:21] wire _ptw_io_mem_s1_kill; // @[Manager.scala:243:21] wire _ptw_io_dpath_perf_pte_miss; // @[Manager.scala:243:21] wire _ptw_io_dpath_clock_enabled; // @[Manager.scala:243:21] wire _dcacheArb_io_requestor_0_req_ready; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_s2_nack; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_s2_nack_cause_raw; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_s2_uncached; // @[Manager.scala:238:27] wire [31:0] _dcacheArb_io_requestor_0_s2_paddr; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_resp_valid; // @[Manager.scala:238:27] wire [39:0] _dcacheArb_io_requestor_0_resp_bits_addr; // @[Manager.scala:238:27] wire [7:0] _dcacheArb_io_requestor_0_resp_bits_tag; // @[Manager.scala:238:27] wire [4:0] _dcacheArb_io_requestor_0_resp_bits_cmd; // @[Manager.scala:238:27] wire [1:0] _dcacheArb_io_requestor_0_resp_bits_size; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_resp_bits_signed; // @[Manager.scala:238:27] wire [1:0] _dcacheArb_io_requestor_0_resp_bits_dprv; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_resp_bits_dv; // @[Manager.scala:238:27] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data; // @[Manager.scala:238:27] wire [7:0] _dcacheArb_io_requestor_0_resp_bits_mask; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_resp_bits_replay; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_resp_bits_has_data; // @[Manager.scala:238:27] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data_word_bypass; // @[Manager.scala:238:27] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data_raw; // @[Manager.scala:238:27] wire [63:0] _dcacheArb_io_requestor_0_resp_bits_store_data; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_replay_next; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_s2_xcpt_ma_ld; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_s2_xcpt_ma_st; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_s2_xcpt_pf_ld; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_s2_xcpt_pf_st; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_s2_xcpt_ae_ld; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_s2_xcpt_ae_st; // @[Manager.scala:238:27] wire [39:0] _dcacheArb_io_requestor_0_s2_gpa; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_ordered; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_store_pending; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_perf_acquire; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_perf_release; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_perf_grant; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_perf_tlbMiss; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_perf_blocked; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_req_ready; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_s2_nack; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_s2_nack_cause_raw; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_s2_uncached; // @[Manager.scala:238:27] wire [31:0] _dcacheArb_io_requestor_1_s2_paddr; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_resp_valid; // @[Manager.scala:238:27] wire [39:0] _dcacheArb_io_requestor_1_resp_bits_addr; // @[Manager.scala:238:27] wire [7:0] _dcacheArb_io_requestor_1_resp_bits_tag; // @[Manager.scala:238:27] wire [4:0] _dcacheArb_io_requestor_1_resp_bits_cmd; // @[Manager.scala:238:27] wire [1:0] _dcacheArb_io_requestor_1_resp_bits_size; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_resp_bits_signed; // @[Manager.scala:238:27] wire [1:0] _dcacheArb_io_requestor_1_resp_bits_dprv; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_resp_bits_dv; // @[Manager.scala:238:27] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data; // @[Manager.scala:238:27] wire [7:0] _dcacheArb_io_requestor_1_resp_bits_mask; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_resp_bits_replay; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_resp_bits_has_data; // @[Manager.scala:238:27] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data_word_bypass; // @[Manager.scala:238:27] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data_raw; // @[Manager.scala:238:27] wire [63:0] _dcacheArb_io_requestor_1_resp_bits_store_data; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_replay_next; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_s2_xcpt_ma_ld; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_s2_xcpt_ma_st; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_s2_xcpt_pf_ld; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_s2_xcpt_pf_st; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_s2_xcpt_ae_ld; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_s2_xcpt_ae_st; // @[Manager.scala:238:27] wire [39:0] _dcacheArb_io_requestor_1_s2_gpa; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_ordered; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_store_pending; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_perf_acquire; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_perf_release; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_perf_grant; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_perf_tlbMiss; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_perf_blocked; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad; // @[Manager.scala:238:27] wire _dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore; // @[Manager.scala:238:27] wire _dcacheArb_io_mem_req_valid; // @[Manager.scala:238:27] wire [39:0] _dcacheArb_io_mem_req_bits_addr; // @[Manager.scala:238:27] wire [7:0] _dcacheArb_io_mem_req_bits_tag; // @[Manager.scala:238:27] wire [1:0] _dcacheArb_io_mem_req_bits_dprv; // @[Manager.scala:238:27] wire _dcacheArb_io_mem_req_bits_dv; // @[Manager.scala:238:27] wire _dcacheArb_io_mem_req_bits_phys; // @[Manager.scala:238:27] wire _dcacheArb_io_mem_s1_kill; // @[Manager.scala:238:27] wire [63:0] _dcacheArb_io_mem_s1_data_data; // @[Manager.scala:238:27] wire [7:0] _dcacheArb_io_mem_s1_data_mask; // @[Manager.scala:238:27] wire _dcache_io_cpu_req_ready; // @[Manager.scala:226:61] wire _dcache_io_cpu_s2_nack; // @[Manager.scala:226:61] wire _dcache_io_cpu_s2_nack_cause_raw; // @[Manager.scala:226:61] wire _dcache_io_cpu_s2_uncached; // @[Manager.scala:226:61] wire [31:0] _dcache_io_cpu_s2_paddr; // @[Manager.scala:226:61] wire _dcache_io_cpu_resp_valid; // @[Manager.scala:226:61] wire [39:0] _dcache_io_cpu_resp_bits_addr; // @[Manager.scala:226:61] wire [7:0] _dcache_io_cpu_resp_bits_tag; // @[Manager.scala:226:61] wire [4:0] _dcache_io_cpu_resp_bits_cmd; // @[Manager.scala:226:61] wire [1:0] _dcache_io_cpu_resp_bits_size; // @[Manager.scala:226:61] wire _dcache_io_cpu_resp_bits_signed; // @[Manager.scala:226:61] wire [1:0] _dcache_io_cpu_resp_bits_dprv; // @[Manager.scala:226:61] wire _dcache_io_cpu_resp_bits_dv; // @[Manager.scala:226:61] wire [63:0] _dcache_io_cpu_resp_bits_data; // @[Manager.scala:226:61] wire [7:0] _dcache_io_cpu_resp_bits_mask; // @[Manager.scala:226:61] wire _dcache_io_cpu_resp_bits_replay; // @[Manager.scala:226:61] wire _dcache_io_cpu_resp_bits_has_data; // @[Manager.scala:226:61] wire [63:0] _dcache_io_cpu_resp_bits_data_word_bypass; // @[Manager.scala:226:61] wire [63:0] _dcache_io_cpu_resp_bits_data_raw; // @[Manager.scala:226:61] wire [63:0] _dcache_io_cpu_resp_bits_store_data; // @[Manager.scala:226:61] wire _dcache_io_cpu_replay_next; // @[Manager.scala:226:61] wire _dcache_io_cpu_s2_xcpt_ma_ld; // @[Manager.scala:226:61] wire _dcache_io_cpu_s2_xcpt_ma_st; // @[Manager.scala:226:61] wire _dcache_io_cpu_s2_xcpt_pf_ld; // @[Manager.scala:226:61] wire _dcache_io_cpu_s2_xcpt_pf_st; // @[Manager.scala:226:61] wire _dcache_io_cpu_s2_xcpt_ae_ld; // @[Manager.scala:226:61] wire _dcache_io_cpu_s2_xcpt_ae_st; // @[Manager.scala:226:61] wire [39:0] _dcache_io_cpu_s2_gpa; // @[Manager.scala:226:61] wire _dcache_io_cpu_ordered; // @[Manager.scala:226:61] wire _dcache_io_cpu_store_pending; // @[Manager.scala:226:61] wire _dcache_io_cpu_perf_acquire; // @[Manager.scala:226:61] wire _dcache_io_cpu_perf_release; // @[Manager.scala:226:61] wire _dcache_io_cpu_perf_grant; // @[Manager.scala:226:61] wire _dcache_io_cpu_perf_tlbMiss; // @[Manager.scala:226:61] wire _dcache_io_cpu_perf_blocked; // @[Manager.scala:226:61] wire _dcache_io_cpu_perf_canAcceptStoreThenLoad; // @[Manager.scala:226:61] wire _dcache_io_cpu_perf_canAcceptStoreThenRMW; // @[Manager.scala:226:61] wire _dcache_io_cpu_perf_canAcceptLoadThenLoad; // @[Manager.scala:226:61] wire _dcache_io_cpu_perf_storeBufferEmptyAfterLoad; // @[Manager.scala:226:61] wire _dcache_io_cpu_perf_storeBufferEmptyAfterStore; // @[Manager.scala:226:61] wire _dcache_io_ptw_req_valid; // @[Manager.scala:226:61] wire [26:0] _dcache_io_ptw_req_bits_bits_addr; // @[Manager.scala:226:61] wire _dcache_io_ptw_req_bits_bits_need_gpa; // @[Manager.scala:226:61] wire _rerocc_buffer_auto_out_req_valid; // @[Protocol.scala:134:35] wire [2:0] _rerocc_buffer_auto_out_req_bits_opcode; // @[Protocol.scala:134:35] wire [3:0] _rerocc_buffer_auto_out_req_bits_client_id; // @[Protocol.scala:134:35] wire _rerocc_buffer_auto_out_req_bits_manager_id; // @[Protocol.scala:134:35] wire [63:0] _rerocc_buffer_auto_out_req_bits_data; // @[Protocol.scala:134:35] wire _rerocc_buffer_auto_out_resp_ready; // @[Protocol.scala:134:35] wire _rerocc_manager_auto_in_req_ready; // @[Manager.scala:209:34] wire _rerocc_manager_auto_in_resp_valid; // @[Manager.scala:209:34] wire [2:0] _rerocc_manager_auto_in_resp_bits_opcode; // @[Manager.scala:209:34] wire [3:0] _rerocc_manager_auto_in_resp_bits_client_id; // @[Manager.scala:209:34] wire _rerocc_manager_auto_in_resp_bits_manager_id; // @[Manager.scala:209:34] wire [63:0] _rerocc_manager_auto_in_resp_bits_data; // @[Manager.scala:209:34] wire [3:0] _rerocc_manager_io_ptw_ptbr_mode; // @[Manager.scala:209:34] wire [15:0] _rerocc_manager_io_ptw_ptbr_asid; // @[Manager.scala:209:34] wire [43:0] _rerocc_manager_io_ptw_ptbr_ppn; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_sfence_valid; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_debug; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_cease; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_wfi; // @[Manager.scala:209:34] wire [31:0] _rerocc_manager_io_ptw_status_isa; // @[Manager.scala:209:34] wire [1:0] _rerocc_manager_io_ptw_status_dprv; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_dv; // @[Manager.scala:209:34] wire [1:0] _rerocc_manager_io_ptw_status_prv; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_v; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_sd; // @[Manager.scala:209:34] wire [22:0] _rerocc_manager_io_ptw_status_zero2; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_mpv; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_gva; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_mbe; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_sbe; // @[Manager.scala:209:34] wire [1:0] _rerocc_manager_io_ptw_status_sxl; // @[Manager.scala:209:34] wire [1:0] _rerocc_manager_io_ptw_status_uxl; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_sd_rv32; // @[Manager.scala:209:34] wire [7:0] _rerocc_manager_io_ptw_status_zero1; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_tsr; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_tw; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_tvm; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_mxr; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_sum; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_mprv; // @[Manager.scala:209:34] wire [1:0] _rerocc_manager_io_ptw_status_xs; // @[Manager.scala:209:34] wire [1:0] _rerocc_manager_io_ptw_status_fs; // @[Manager.scala:209:34] wire [1:0] _rerocc_manager_io_ptw_status_mpp; // @[Manager.scala:209:34] wire [1:0] _rerocc_manager_io_ptw_status_vs; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_spp; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_mpie; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_ube; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_spie; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_upie; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_mie; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_hie; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_sie; // @[Manager.scala:209:34] wire _rerocc_manager_io_ptw_status_uie; // @[Manager.scala:209:34] wire _accumulator_cmd_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [6:0] _accumulator_cmd_q_io_deq_bits_inst_funct; // @[Decoupled.scala:362:21] wire _accumulator_cmd_q_io_deq_bits_inst_xd; // @[Decoupled.scala:362:21] wire [63:0] _accumulator_cmd_q_io_deq_bits_rs1; // @[Decoupled.scala:362:21] wire [63:0] _accumulator_cmd_q_io_deq_bits_rs2; // @[Decoupled.scala:362:21] wire [63:0] _regfile_ext_R0_data; // @[LazyRoCC.scala:124:20] wire auto_ctrl_ctrl_in_a_valid_0 = auto_ctrl_ctrl_in_a_valid; // @[Manager.scala:237:34] wire [2:0] auto_ctrl_ctrl_in_a_bits_opcode_0 = auto_ctrl_ctrl_in_a_bits_opcode; // @[Manager.scala:237:34] wire [2:0] auto_ctrl_ctrl_in_a_bits_param_0 = auto_ctrl_ctrl_in_a_bits_param; // @[Manager.scala:237:34] wire [2:0] auto_ctrl_ctrl_in_a_bits_size_0 = auto_ctrl_ctrl_in_a_bits_size; // @[Manager.scala:237:34] wire [6:0] auto_ctrl_ctrl_in_a_bits_source_0 = auto_ctrl_ctrl_in_a_bits_source; // @[Manager.scala:237:34] wire [11:0] auto_ctrl_ctrl_in_a_bits_address_0 = auto_ctrl_ctrl_in_a_bits_address; // @[Manager.scala:237:34] wire [7:0] auto_ctrl_ctrl_in_a_bits_mask_0 = auto_ctrl_ctrl_in_a_bits_mask; // @[Manager.scala:237:34] wire [63:0] auto_ctrl_ctrl_in_a_bits_data_0 = auto_ctrl_ctrl_in_a_bits_data; // @[Manager.scala:237:34] wire auto_ctrl_ctrl_in_a_bits_corrupt_0 = auto_ctrl_ctrl_in_a_bits_corrupt; // @[Manager.scala:237:34] wire auto_ctrl_ctrl_in_d_ready_0 = auto_ctrl_ctrl_in_d_ready; // @[Manager.scala:237:34] wire auto_buffer_out_a_ready_0 = auto_buffer_out_a_ready; // @[Manager.scala:237:34] wire auto_buffer_out_b_valid_0 = auto_buffer_out_b_valid; // @[Manager.scala:237:34] wire [2:0] auto_buffer_out_b_bits_opcode_0 = auto_buffer_out_b_bits_opcode; // @[Manager.scala:237:34] wire [1:0] auto_buffer_out_b_bits_param_0 = auto_buffer_out_b_bits_param; // @[Manager.scala:237:34] wire [3:0] auto_buffer_out_b_bits_size_0 = auto_buffer_out_b_bits_size; // @[Manager.scala:237:34] wire auto_buffer_out_b_bits_source_0 = auto_buffer_out_b_bits_source; // @[Manager.scala:237:34] wire [31:0] auto_buffer_out_b_bits_address_0 = auto_buffer_out_b_bits_address; // @[Manager.scala:237:34] wire [7:0] auto_buffer_out_b_bits_mask_0 = auto_buffer_out_b_bits_mask; // @[Manager.scala:237:34] wire [63:0] auto_buffer_out_b_bits_data_0 = auto_buffer_out_b_bits_data; // @[Manager.scala:237:34] wire auto_buffer_out_b_bits_corrupt_0 = auto_buffer_out_b_bits_corrupt; // @[Manager.scala:237:34] wire auto_buffer_out_c_ready_0 = auto_buffer_out_c_ready; // @[Manager.scala:237:34] wire auto_buffer_out_d_valid_0 = auto_buffer_out_d_valid; // @[Manager.scala:237:34] wire [2:0] auto_buffer_out_d_bits_opcode_0 = auto_buffer_out_d_bits_opcode; // @[Manager.scala:237:34] wire [1:0] auto_buffer_out_d_bits_param_0 = auto_buffer_out_d_bits_param; // @[Manager.scala:237:34] wire [3:0] auto_buffer_out_d_bits_size_0 = auto_buffer_out_d_bits_size; // @[Manager.scala:237:34] wire auto_buffer_out_d_bits_source_0 = auto_buffer_out_d_bits_source; // @[Manager.scala:237:34] wire [2:0] auto_buffer_out_d_bits_sink_0 = auto_buffer_out_d_bits_sink; // @[Manager.scala:237:34] wire auto_buffer_out_d_bits_denied_0 = auto_buffer_out_d_bits_denied; // @[Manager.scala:237:34] wire [63:0] auto_buffer_out_d_bits_data_0 = auto_buffer_out_d_bits_data; // @[Manager.scala:237:34] wire auto_buffer_out_d_bits_corrupt_0 = auto_buffer_out_d_bits_corrupt; // @[Manager.scala:237:34] wire auto_buffer_out_e_ready_0 = auto_buffer_out_e_ready; // @[Manager.scala:237:34] wire auto_re_ro_cc_in_req_valid_0 = auto_re_ro_cc_in_req_valid; // @[Manager.scala:237:34] wire [2:0] auto_re_ro_cc_in_req_bits_opcode_0 = auto_re_ro_cc_in_req_bits_opcode; // @[Manager.scala:237:34] wire [3:0] auto_re_ro_cc_in_req_bits_client_id_0 = auto_re_ro_cc_in_req_bits_client_id; // @[Manager.scala:237:34] wire auto_re_ro_cc_in_req_bits_manager_id_0 = auto_re_ro_cc_in_req_bits_manager_id; // @[Manager.scala:237:34] wire [63:0] auto_re_ro_cc_in_req_bits_data_0 = auto_re_ro_cc_in_req_bits_data; // @[Manager.scala:237:34] wire auto_re_ro_cc_in_resp_ready_0 = auto_re_ro_cc_in_resp_ready; // @[Manager.scala:237:34] wire [6:0] auto_rerocc_manager_id_sink_in_0 = auto_rerocc_manager_id_sink_in; // @[Manager.scala:237:34] wire xbar__requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire xbar_requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107] wire xbar__requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire xbar_requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire xbar__requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire xbar__requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire xbar__requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire xbar__requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire xbar_requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire xbar__requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire xbar__requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire xbar__requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire xbar__requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire xbar_requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire xbar__requestEIO_T_1 = 1'h1; // @[Parameters.scala:54:32] wire xbar__requestEIO_T_2 = 1'h1; // @[Parameters.scala:56:32] wire xbar__requestEIO_T_3 = 1'h1; // @[Parameters.scala:54:67] wire xbar__requestEIO_T_4 = 1'h1; // @[Parameters.scala:57:20] wire xbar_requestEIO_0_0 = 1'h1; // @[Parameters.scala:56:48] wire xbar__portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire xbar__portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire xbar__portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire xbar__portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire xbar__portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire [2:0] accumulator_io_fpu_req_bits_rm = 3'h0; // @[LazyRoCC.scala:122:7] wire [64:0] accumulator_io_fpu_req_bits_in1 = 65'h0; // @[LazyRoCC.scala:122:7] wire [64:0] accumulator_io_fpu_req_bits_in2 = 65'h0; // @[LazyRoCC.scala:122:7] wire [64:0] accumulator_io_fpu_req_bits_in3 = 65'h0; // @[LazyRoCC.scala:122:7] wire [64:0] accumulator_io_fpu_resp_bits_data = 65'h0; // @[LazyRoCC.scala:122:7] wire [32:0] xbar__requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] xbar__requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] xbar__requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] xbar__requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [8:0] xbar_beatsBO_0 = 9'h0; // @[Edges.scala:221:14] wire [39:0] accumulator_io_mem_s2_gpa = 40'h0; // @[LazyRoCC.scala:122:7] wire [31:0] accumulator_io_mem_s2_paddr = 32'h0; // @[LazyRoCC.scala:122:7] wire [4:0] accumulator_io_mem_req_bits_cmd = 5'h0; // @[LazyRoCC.scala:122:7] wire [4:0] accumulator_io_fpu_resp_bits_exc = 5'h0; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_mem_req_bits_size = 2'h3; // @[LazyRoCC.scala:122:7] wire [63:0] accumulator_io_mem_req_bits_data = 64'h0; // @[LazyRoCC.scala:122:7] wire [63:0] accumulator_io_mem_s1_data_data = 64'h0; // @[LazyRoCC.scala:122:7] wire [7:0] accumulator_io_mem_req_bits_mask = 8'h0; // @[LazyRoCC.scala:122:7] wire [7:0] accumulator_io_mem_s1_data_mask = 8'h0; // @[LazyRoCC.scala:122:7] wire auto_ctrl_ctrl_in_d_bits_sink = 1'h0; // @[Manager.scala:237:34] wire auto_ctrl_ctrl_in_d_bits_denied = 1'h0; // @[Manager.scala:237:34] wire auto_ctrl_ctrl_in_d_bits_corrupt = 1'h0; // @[Manager.scala:237:34] wire accumulator_io_mem_req_bits_signed = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_req_bits_phys = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_req_bits_no_resp = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_req_bits_no_alloc = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_req_bits_no_xcpt = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_s1_kill = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_s2_nack = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_s2_nack_cause_raw = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_s2_kill = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_s2_uncached = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_replay_next = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_s2_xcpt_ma_ld = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_s2_xcpt_ma_st = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_s2_xcpt_pf_ld = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_s2_xcpt_pf_st = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_s2_xcpt_gf_ld = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_s2_xcpt_gf_st = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_s2_xcpt_ae_ld = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_s2_xcpt_ae_st = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_s2_gpa_is_pte = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_ordered = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_store_pending = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_perf_acquire = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_perf_release = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_perf_grant = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_perf_tlbMiss = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_perf_blocked = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_keep_clock_enabled = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_clock_enabled = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_interrupt = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_exception = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_ready = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_valid = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_bits_ldst = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_bits_wen = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_bits_ren1 = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_bits_ren2 = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_bits_ren3 = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_bits_swap12 = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_bits_swap23 = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_bits_fromint = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_bits_toint = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_bits_fastpipe = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_bits_fma = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_bits_div = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_bits_sqrt = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_bits_wflags = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_req_bits_vec = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_resp_ready = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator_io_fpu_resp_valid = 1'h0; // @[LazyRoCC.scala:122:7] wire accumulator__busy_WIRE_0 = 1'h0; // @[LazyRoCC.scala:125:29] wire accumulator__busy_WIRE_1 = 1'h0; // @[LazyRoCC.scala:125:29] wire accumulator__busy_WIRE_2 = 1'h0; // @[LazyRoCC.scala:125:29] wire accumulator__busy_WIRE_3 = 1'h0; // @[LazyRoCC.scala:125:29] wire xbar_auto_anon_in_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire xbar_auto_anon_in_c_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_c_bits_corrupt = 1'h0; // @[Xbar.scala:74:9] wire xbar_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire xbar_anonOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire xbar_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire xbar_anonIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire xbar_in_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire xbar_in_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18] wire xbar_out_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire xbar_out_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:216:19] wire xbar__requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire xbar__requestDOI_T = 1'h0; // @[Parameters.scala:54:10] wire xbar__requestEIO_T = 1'h0; // @[Parameters.scala:54:10] wire xbar_portsAOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire xbar_portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire widget_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_auto_anon_out_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire widget_anonOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire widget_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire widget_anonIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire [1:0] auto_ctrl_ctrl_in_d_bits_param = 2'h0; // @[Manager.scala:237:34] wire [1:0] accumulator_io_fpu_req_bits_typeTagIn = 2'h0; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_fpu_req_bits_typeTagOut = 2'h0; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_fpu_req_bits_fmaCmd = 2'h0; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_fpu_req_bits_typ = 2'h0; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_fpu_req_bits_fmt = 2'h0; // @[LazyRoCC.scala:122:7] wire reRoCCNodeIn_req_ready; // @[MixedNode.scala:551:17] wire reRoCCNodeIn_req_valid = auto_re_ro_cc_in_req_valid_0; // @[Manager.scala:237:34] wire [2:0] reRoCCNodeIn_req_bits_opcode = auto_re_ro_cc_in_req_bits_opcode_0; // @[Manager.scala:237:34] wire [3:0] reRoCCNodeIn_req_bits_client_id = auto_re_ro_cc_in_req_bits_client_id_0; // @[Manager.scala:237:34] wire reRoCCNodeIn_req_bits_manager_id = auto_re_ro_cc_in_req_bits_manager_id_0; // @[Manager.scala:237:34] wire [63:0] reRoCCNodeIn_req_bits_data = auto_re_ro_cc_in_req_bits_data_0; // @[Manager.scala:237:34] wire reRoCCNodeIn_resp_ready = auto_re_ro_cc_in_resp_ready_0; // @[Manager.scala:237:34] wire reRoCCNodeIn_resp_valid; // @[MixedNode.scala:551:17] wire [2:0] reRoCCNodeIn_resp_bits_opcode; // @[MixedNode.scala:551:17] wire [3:0] reRoCCNodeIn_resp_bits_client_id; // @[MixedNode.scala:551:17] wire reRoCCNodeIn_resp_bits_manager_id; // @[MixedNode.scala:551:17] wire [63:0] reRoCCNodeIn_resp_bits_data; // @[MixedNode.scala:551:17] wire [6:0] reroccManagerIdSinkNodeIn = auto_rerocc_manager_id_sink_in_0; // @[Manager.scala:237:34] wire auto_ctrl_ctrl_in_a_ready_0; // @[Manager.scala:237:34] wire [2:0] auto_ctrl_ctrl_in_d_bits_opcode_0; // @[Manager.scala:237:34] wire [2:0] auto_ctrl_ctrl_in_d_bits_size_0; // @[Manager.scala:237:34] wire [6:0] auto_ctrl_ctrl_in_d_bits_source_0; // @[Manager.scala:237:34] wire [63:0] auto_ctrl_ctrl_in_d_bits_data_0; // @[Manager.scala:237:34] wire auto_ctrl_ctrl_in_d_valid_0; // @[Manager.scala:237:34] wire [2:0] auto_buffer_out_a_bits_opcode_0; // @[Manager.scala:237:34] wire [2:0] auto_buffer_out_a_bits_param_0; // @[Manager.scala:237:34] wire [3:0] auto_buffer_out_a_bits_size_0; // @[Manager.scala:237:34] wire auto_buffer_out_a_bits_source_0; // @[Manager.scala:237:34] wire [31:0] auto_buffer_out_a_bits_address_0; // @[Manager.scala:237:34] wire [7:0] auto_buffer_out_a_bits_mask_0; // @[Manager.scala:237:34] wire [63:0] auto_buffer_out_a_bits_data_0; // @[Manager.scala:237:34] wire auto_buffer_out_a_bits_corrupt_0; // @[Manager.scala:237:34] wire auto_buffer_out_a_valid_0; // @[Manager.scala:237:34] wire auto_buffer_out_b_ready_0; // @[Manager.scala:237:34] wire [2:0] auto_buffer_out_c_bits_opcode_0; // @[Manager.scala:237:34] wire [2:0] auto_buffer_out_c_bits_param_0; // @[Manager.scala:237:34] wire [3:0] auto_buffer_out_c_bits_size_0; // @[Manager.scala:237:34] wire auto_buffer_out_c_bits_source_0; // @[Manager.scala:237:34] wire [31:0] auto_buffer_out_c_bits_address_0; // @[Manager.scala:237:34] wire [63:0] auto_buffer_out_c_bits_data_0; // @[Manager.scala:237:34] wire auto_buffer_out_c_bits_corrupt_0; // @[Manager.scala:237:34] wire auto_buffer_out_c_valid_0; // @[Manager.scala:237:34] wire auto_buffer_out_d_ready_0; // @[Manager.scala:237:34] wire [2:0] auto_buffer_out_e_bits_sink_0; // @[Manager.scala:237:34] wire auto_buffer_out_e_valid_0; // @[Manager.scala:237:34] wire auto_re_ro_cc_in_req_ready_0; // @[Manager.scala:237:34] wire [2:0] auto_re_ro_cc_in_resp_bits_opcode_0; // @[Manager.scala:237:34] wire [3:0] auto_re_ro_cc_in_resp_bits_client_id_0; // @[Manager.scala:237:34] wire auto_re_ro_cc_in_resp_bits_manager_id_0; // @[Manager.scala:237:34] wire [63:0] auto_re_ro_cc_in_resp_bits_data_0; // @[Manager.scala:237:34] wire auto_re_ro_cc_in_resp_valid_0; // @[Manager.scala:237:34] wire accumulator__io_resp_valid_T_4; // @[LazyRoCC.scala:164:53] wire accumulator__io_mem_req_valid_T_4; // @[LazyRoCC.scala:177:56] wire accumulator__io_busy_T_3; // @[LazyRoCC.scala:171:24] wire [6:0] accumulator_io_cmd_bits_inst_funct; // @[LazyRoCC.scala:122:7] wire [4:0] accumulator_io_cmd_bits_inst_rs2; // @[LazyRoCC.scala:122:7] wire [4:0] accumulator_io_cmd_bits_inst_rs1; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_inst_xd; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_inst_xs1; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_inst_xs2; // @[LazyRoCC.scala:122:7] wire [4:0] accumulator_io_cmd_bits_inst_rd; // @[LazyRoCC.scala:122:7] wire [6:0] accumulator_io_cmd_bits_inst_opcode; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_debug; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_cease; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_wfi; // @[LazyRoCC.scala:122:7] wire [31:0] accumulator_io_cmd_bits_status_isa; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_cmd_bits_status_dprv; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_dv; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_cmd_bits_status_prv; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_v; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_sd; // @[LazyRoCC.scala:122:7] wire [22:0] accumulator_io_cmd_bits_status_zero2; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_mpv; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_gva; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_mbe; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_sbe; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_cmd_bits_status_sxl; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_cmd_bits_status_uxl; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_sd_rv32; // @[LazyRoCC.scala:122:7] wire [7:0] accumulator_io_cmd_bits_status_zero1; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_tsr; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_tw; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_tvm; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_mxr; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_sum; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_mprv; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_cmd_bits_status_xs; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_cmd_bits_status_fs; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_cmd_bits_status_mpp; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_cmd_bits_status_vs; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_spp; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_mpie; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_ube; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_spie; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_upie; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_mie; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_hie; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_sie; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_bits_status_uie; // @[LazyRoCC.scala:122:7] wire [63:0] accumulator_io_cmd_bits_rs1; // @[LazyRoCC.scala:122:7] wire [63:0] accumulator_io_cmd_bits_rs2; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_ready; // @[LazyRoCC.scala:122:7] wire accumulator_io_cmd_valid; // @[LazyRoCC.scala:122:7] wire [4:0] accumulator_io_resp_bits_rd; // @[LazyRoCC.scala:122:7] wire [63:0] accumulator_io_resp_bits_data; // @[LazyRoCC.scala:122:7] wire accumulator_io_resp_ready; // @[LazyRoCC.scala:122:7] wire accumulator_io_resp_valid; // @[LazyRoCC.scala:122:7] wire [39:0] accumulator_io_mem_req_bits_addr; // @[LazyRoCC.scala:122:7] wire [7:0] accumulator_io_mem_req_bits_tag; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_mem_req_bits_dprv; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_req_bits_dv; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_req_ready; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_req_valid; // @[LazyRoCC.scala:122:7] wire [39:0] accumulator_io_mem_resp_bits_addr; // @[LazyRoCC.scala:122:7] wire [7:0] accumulator_io_mem_resp_bits_tag; // @[LazyRoCC.scala:122:7] wire [4:0] accumulator_io_mem_resp_bits_cmd; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_mem_resp_bits_size; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_resp_bits_signed; // @[LazyRoCC.scala:122:7] wire [1:0] accumulator_io_mem_resp_bits_dprv; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_resp_bits_dv; // @[LazyRoCC.scala:122:7] wire [63:0] accumulator_io_mem_resp_bits_data; // @[LazyRoCC.scala:122:7] wire [7:0] accumulator_io_mem_resp_bits_mask; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_resp_bits_replay; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_resp_bits_has_data; // @[LazyRoCC.scala:122:7] wire [63:0] accumulator_io_mem_resp_bits_data_word_bypass; // @[LazyRoCC.scala:122:7] wire [63:0] accumulator_io_mem_resp_bits_data_raw; // @[LazyRoCC.scala:122:7] wire [63:0] accumulator_io_mem_resp_bits_store_data; // @[LazyRoCC.scala:122:7] wire accumulator_io_mem_resp_valid; // @[LazyRoCC.scala:122:7] wire accumulator_io_busy; // @[LazyRoCC.scala:122:7] reg accumulator_busy_0; // @[LazyRoCC.scala:125:21] reg accumulator_busy_1; // @[LazyRoCC.scala:125:21] reg accumulator_busy_2; // @[LazyRoCC.scala:125:21] reg accumulator_busy_3; // @[LazyRoCC.scala:125:21] wire [1:0] accumulator_addr = _accumulator_cmd_q_io_deq_bits_rs2[1:0]; // @[Decoupled.scala:362:21] wire accumulator_doWrite = _accumulator_cmd_q_io_deq_bits_inst_funct == 7'h0; // @[Decoupled.scala:362:21] wire accumulator_doRead = _accumulator_cmd_q_io_deq_bits_inst_funct == 7'h1; // @[Decoupled.scala:362:21] wire accumulator_doLoad = _accumulator_cmd_q_io_deq_bits_inst_funct == 7'h2; // @[Decoupled.scala:362:21] wire accumulator_doAccum = _accumulator_cmd_q_io_deq_bits_inst_funct == 7'h3; // @[Decoupled.scala:362:21] wire [1:0] accumulator_memRespTag = accumulator_io_mem_resp_bits_tag[1:0]; // @[LazyRoCC.scala:122:7, :134:40] wire [64:0] accumulator__wdata_T = {1'h0, _regfile_ext_R0_data} + {1'h0, _accumulator_cmd_q_io_deq_bits_rs1}; // @[Decoupled.scala:362:21] wire [63:0] accumulator__wdata_T_1 = accumulator__wdata_T[63:0]; // @[LazyRoCC.scala:139:42] wire [63:0] accumulator_wdata = accumulator_doWrite ? _accumulator_cmd_q_io_deq_bits_rs1 : accumulator__wdata_T_1; // @[Decoupled.scala:362:21] wire accumulator__q_io_deq_ready_T_4; // @[LazyRoCC.scala:160:40] wire accumulator__stallLoad_T = ~accumulator_io_mem_req_ready; // @[LazyRoCC.scala:122:7, :157:29] wire accumulator_stallLoad = accumulator_doLoad & accumulator__stallLoad_T; // @[LazyRoCC.scala:132:22, :157:{26,29}] wire accumulator__stallResp_T = ~accumulator_io_resp_ready; // @[LazyRoCC.scala:122:7, :158:29] wire accumulator_stallResp = _accumulator_cmd_q_io_deq_bits_inst_xd & accumulator__stallResp_T; // @[Decoupled.scala:362:21] wire [3:0] _GEN = {{accumulator_busy_3}, {accumulator_busy_2}, {accumulator_busy_1}, {accumulator_busy_0}}; // @[LazyRoCC.scala:125:21, :160:16] wire accumulator__q_io_deq_ready_T = ~_GEN[accumulator_addr]; // @[LazyRoCC.scala:129:26, :160:16] wire accumulator__q_io_deq_ready_T_1 = ~accumulator_stallLoad; // @[LazyRoCC.scala:157:26, :160:29] wire accumulator__q_io_deq_ready_T_2 = accumulator__q_io_deq_ready_T & accumulator__q_io_deq_ready_T_1; // @[LazyRoCC.scala:160:{16,26,29}] wire accumulator__q_io_deq_ready_T_3 = ~accumulator_stallResp; // @[LazyRoCC.scala:158:26, :160:43] assign accumulator__q_io_deq_ready_T_4 = accumulator__q_io_deq_ready_T_2 & accumulator__q_io_deq_ready_T_3; // @[LazyRoCC.scala:160:{26,40,43}] wire accumulator__io_resp_valid_T = _accumulator_cmd_q_io_deq_valid & _accumulator_cmd_q_io_deq_bits_inst_xd; // @[Decoupled.scala:362:21] wire accumulator__io_resp_valid_T_1 = ~_GEN[accumulator_addr]; // @[LazyRoCC.scala:129:26, :160:16, :164:43] wire accumulator__io_resp_valid_T_2 = accumulator__io_resp_valid_T & accumulator__io_resp_valid_T_1; // @[LazyRoCC.scala:164:{30,40,43}] wire accumulator__io_resp_valid_T_3 = ~accumulator_stallLoad; // @[LazyRoCC.scala:157:26, :160:29, :164:56] assign accumulator__io_resp_valid_T_4 = accumulator__io_resp_valid_T_2 & accumulator__io_resp_valid_T_3; // @[LazyRoCC.scala:164:{40,53,56}] assign accumulator_io_resp_valid = accumulator__io_resp_valid_T_4; // @[LazyRoCC.scala:122:7, :164:53] wire accumulator__io_busy_T = accumulator_busy_0 \| accumulator_busy_1; // @[LazyRoCC.scala:125:21, :171:40] wire accumulator__io_busy_T_1 = accumulator__io_busy_T \| accumulator_busy_2; // @[LazyRoCC.scala:125:21, :171:40] wire accumulator__io_busy_T_2 = accumulator__io_busy_T_1 \| accumulator_busy_3; // @[LazyRoCC.scala:125:21, :171:40] assign accumulator__io_busy_T_3 = _accumulator_cmd_q_io_deq_valid \| accumulator__io_busy_T_2; // @[Decoupled.scala:362:21] assign accumulator_io_busy = accumulator__io_busy_T_3; // @[LazyRoCC.scala:122:7, :171:24] wire accumulator__io_mem_req_valid_T = _accumulator_cmd_q_io_deq_valid & accumulator_doLoad; // @[Decoupled.scala:362:21] wire accumulator__io_mem_req_valid_T_1 = ~_GEN[accumulator_addr]; // @[LazyRoCC.scala:129:26, :160:16, :177:46] wire accumulator__io_mem_req_valid_T_2 = accumulator__io_mem_req_valid_T & accumulator__io_mem_req_valid_T_1; // @[LazyRoCC.scala:177:{33,43,46}] wire accumulator__io_mem_req_valid_T_3 = ~accumulator_stallResp; // @[LazyRoCC.scala:158:26, :160:43, :177:59] assign accumulator__io_mem_req_valid_T_4 = accumulator__io_mem_req_valid_T_2 & accumulator__io_mem_req_valid_T_3; // @[LazyRoCC.scala:177:{43,56,59}] assign accumulator_io_mem_req_valid = accumulator__io_mem_req_valid_T_4; // @[LazyRoCC.scala:122:7, :177:56] assign accumulator_io_mem_req_bits_addr = _accumulator_cmd_q_io_deq_bits_rs1[39:0]; // @[Decoupled.scala:362:21] assign accumulator_io_mem_req_bits_tag = {6'h0, accumulator_addr}; // @[LazyRoCC.scala:122:7, :129:26, :131:22, :179:23] wire xbar_anonIn_a_ready; // @[MixedNode.scala:551:17] wire widget_auto_anon_out_a_ready = xbar_auto_anon_in_a_ready; // @[Xbar.scala:74:9] wire widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9] wire xbar_anonIn_a_valid = xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire [2:0] widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] xbar_anonIn_a_bits_opcode = xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] xbar_anonIn_a_bits_param = xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9] wire [3:0] xbar_anonIn_a_bits_size = xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9] wire xbar_anonIn_a_bits_source = xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9] wire [31:0] xbar_anonIn_a_bits_address = xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9] wire [7:0] xbar_anonIn_a_bits_mask = xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9] wire [63:0] xbar_anonIn_a_bits_data = xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire widget_auto_anon_out_b_ready; // @[WidthWidget.scala:27:9] wire xbar_anonIn_b_ready = xbar_auto_anon_in_b_ready; // @[Xbar.scala:74:9] wire xbar_anonIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] xbar_anonIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire widget_auto_anon_out_b_valid = xbar_auto_anon_in_b_valid; // @[Xbar.scala:74:9] wire [1:0] xbar_anonIn_b_bits_param; // @[MixedNode.scala:551:17] wire [2:0] widget_auto_anon_out_b_bits_opcode = xbar_auto_anon_in_b_bits_opcode; // @[Xbar.scala:74:9] wire [3:0] xbar_anonIn_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] widget_auto_anon_out_b_bits_param = xbar_auto_anon_in_b_bits_param; // @[Xbar.scala:74:9] wire xbar_anonIn_b_bits_source; // @[MixedNode.scala:551:17] wire [3:0] widget_auto_anon_out_b_bits_size = xbar_auto_anon_in_b_bits_size; // @[Xbar.scala:74:9] wire [31:0] xbar_anonIn_b_bits_address; // @[MixedNode.scala:551:17] wire widget_auto_anon_out_b_bits_source = xbar_auto_anon_in_b_bits_source; // @[Xbar.scala:74:9] wire [7:0] xbar_anonIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [31:0] widget_auto_anon_out_b_bits_address = xbar_auto_anon_in_b_bits_address; // @[Xbar.scala:74:9] wire [63:0] xbar_anonIn_b_bits_data; // @[MixedNode.scala:551:17] wire [7:0] widget_auto_anon_out_b_bits_mask = xbar_auto_anon_in_b_bits_mask; // @[Xbar.scala:74:9] wire xbar_anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] widget_auto_anon_out_b_bits_data = xbar_auto_anon_in_b_bits_data; // @[Xbar.scala:74:9] wire xbar_anonIn_c_ready; // @[MixedNode.scala:551:17] wire widget_auto_anon_out_b_bits_corrupt = xbar_auto_anon_in_b_bits_corrupt; // @[Xbar.scala:74:9] wire widget_auto_anon_out_c_ready = xbar_auto_anon_in_c_ready; // @[Xbar.scala:74:9] wire widget_auto_anon_out_c_valid; // @[WidthWidget.scala:27:9] wire xbar_anonIn_c_valid = xbar_auto_anon_in_c_valid; // @[Xbar.scala:74:9] wire [2:0] widget_auto_anon_out_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] xbar_anonIn_c_bits_opcode = xbar_auto_anon_in_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] widget_auto_anon_out_c_bits_param; // @[WidthWidget.scala:27:9] wire [2:0] xbar_anonIn_c_bits_param = xbar_auto_anon_in_c_bits_param; // @[Xbar.scala:74:9] wire [3:0] widget_auto_anon_out_c_bits_size; // @[WidthWidget.scala:27:9] wire [3:0] xbar_anonIn_c_bits_size = xbar_auto_anon_in_c_bits_size; // @[Xbar.scala:74:9] wire widget_auto_anon_out_c_bits_source; // @[WidthWidget.scala:27:9] wire xbar_anonIn_c_bits_source = xbar_auto_anon_in_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] widget_auto_anon_out_c_bits_address; // @[WidthWidget.scala:27:9] wire [31:0] xbar_anonIn_c_bits_address = xbar_auto_anon_in_c_bits_address; // @[Xbar.scala:74:9] wire [63:0] widget_auto_anon_out_c_bits_data; // @[WidthWidget.scala:27:9] wire [63:0] xbar_anonIn_c_bits_data = xbar_auto_anon_in_c_bits_data; // @[Xbar.scala:74:9] wire widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9] wire xbar_anonIn_d_ready = xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire xbar_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] xbar_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire widget_auto_anon_out_d_valid = xbar_auto_anon_in_d_valid; // @[Xbar.scala:74:9] wire [1:0] xbar_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] widget_auto_anon_out_d_bits_opcode = xbar_auto_anon_in_d_bits_opcode; // @[Xbar.scala:74:9] wire [3:0] xbar_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] widget_auto_anon_out_d_bits_param = xbar_auto_anon_in_d_bits_param; // @[Xbar.scala:74:9] wire xbar_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] widget_auto_anon_out_d_bits_size = xbar_auto_anon_in_d_bits_size; // @[Xbar.scala:74:9] wire [2:0] xbar_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire widget_auto_anon_out_d_bits_source = xbar_auto_anon_in_d_bits_source; // @[Xbar.scala:74:9] wire xbar_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [2:0] widget_auto_anon_out_d_bits_sink = xbar_auto_anon_in_d_bits_sink; // @[Xbar.scala:74:9] wire [63:0] xbar_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire widget_auto_anon_out_d_bits_denied = xbar_auto_anon_in_d_bits_denied; // @[Xbar.scala:74:9] wire xbar_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [63:0] widget_auto_anon_out_d_bits_data = xbar_auto_anon_in_d_bits_data; // @[Xbar.scala:74:9] wire xbar_anonIn_e_ready; // @[MixedNode.scala:551:17] wire widget_auto_anon_out_d_bits_corrupt = xbar_auto_anon_in_d_bits_corrupt; // @[Xbar.scala:74:9] wire widget_auto_anon_out_e_ready = xbar_auto_anon_in_e_ready; // @[Xbar.scala:74:9] wire widget_auto_anon_out_e_valid; // @[WidthWidget.scala:27:9] wire xbar_anonIn_e_valid = xbar_auto_anon_in_e_valid; // @[Xbar.scala:74:9] wire [2:0] widget_auto_anon_out_e_bits_sink; // @[WidthWidget.scala:27:9] wire [2:0] xbar_anonIn_e_bits_sink = xbar_auto_anon_in_e_bits_sink; // @[Xbar.scala:74:9] wire xbar_anonOut_a_ready = xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9] wire xbar_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] xbar_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] xbar_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] xbar_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire xbar_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] xbar_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] xbar_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] xbar_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire xbar_anonOut_b_ready; // @[MixedNode.scala:542:17] wire xbar_anonOut_b_valid = xbar_auto_anon_out_b_valid; // @[Xbar.scala:74:9] wire [2:0] xbar_anonOut_b_bits_opcode = xbar_auto_anon_out_b_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] xbar_anonOut_b_bits_param = xbar_auto_anon_out_b_bits_param; // @[Xbar.scala:74:9] wire [3:0] xbar_anonOut_b_bits_size = xbar_auto_anon_out_b_bits_size; // @[Xbar.scala:74:9] wire xbar_anonOut_b_bits_source = xbar_auto_anon_out_b_bits_source; // @[Xbar.scala:74:9] wire [31:0] xbar_anonOut_b_bits_address = xbar_auto_anon_out_b_bits_address; // @[Xbar.scala:74:9] wire [7:0] xbar_anonOut_b_bits_mask = xbar_auto_anon_out_b_bits_mask; // @[Xbar.scala:74:9] wire [63:0] xbar_anonOut_b_bits_data = xbar_auto_anon_out_b_bits_data; // @[Xbar.scala:74:9] wire xbar_anonOut_b_bits_corrupt = xbar_auto_anon_out_b_bits_corrupt; // @[Xbar.scala:74:9] wire xbar_anonOut_c_ready = xbar_auto_anon_out_c_ready; // @[Xbar.scala:74:9] wire xbar_anonOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] xbar_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] xbar_anonOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] xbar_anonOut_c_bits_size; // @[MixedNode.scala:542:17] wire xbar_anonOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] xbar_anonOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] xbar_anonOut_c_bits_data; // @[MixedNode.scala:542:17] wire xbar_anonOut_d_ready; // @[MixedNode.scala:542:17] wire xbar_anonOut_d_valid = xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9] wire [2:0] xbar_anonOut_d_bits_opcode = xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] xbar_anonOut_d_bits_param = xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] xbar_anonOut_d_bits_size = xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9] wire xbar_anonOut_d_bits_source = xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9] wire [2:0] xbar_anonOut_d_bits_sink = xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9] wire xbar_anonOut_d_bits_denied = xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] xbar_anonOut_d_bits_data = xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9] wire xbar_anonOut_d_bits_corrupt = xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9] wire xbar_anonOut_e_ready = xbar_auto_anon_out_e_ready; // @[Xbar.scala:74:9] wire xbar_anonOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] xbar_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] wire [2:0] xbar_auto_anon_out_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_out_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] xbar_auto_anon_out_a_bits_size; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] xbar_auto_anon_out_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] xbar_auto_anon_out_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] xbar_auto_anon_out_a_bits_data; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_a_valid; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_b_ready; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_out_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_out_c_bits_param; // @[Xbar.scala:74:9] wire [3:0] xbar_auto_anon_out_c_bits_size; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] xbar_auto_anon_out_c_bits_address; // @[Xbar.scala:74:9] wire [63:0] xbar_auto_anon_out_c_bits_data; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_c_valid; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_d_ready; // @[Xbar.scala:74:9] wire [2:0] xbar_auto_anon_out_e_bits_sink; // @[Xbar.scala:74:9] wire xbar_auto_anon_out_e_valid; // @[Xbar.scala:74:9] wire xbar_out_0_a_ready = xbar_anonOut_a_ready; // @[Xbar.scala:216:19] wire xbar_out_0_a_valid; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_valid = xbar_anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_bits_opcode = xbar_anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] xbar_out_0_a_bits_param; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_bits_param = xbar_anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] xbar_out_0_a_bits_size; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_bits_size = xbar_anonOut_a_bits_size; // @[Xbar.scala:74:9] wire xbar_out_0_a_bits_source; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_bits_source = xbar_anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] xbar_out_0_a_bits_address; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_bits_address = xbar_anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_bits_mask = xbar_anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] xbar_out_0_a_bits_data; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_a_bits_data = xbar_anonOut_a_bits_data; // @[Xbar.scala:74:9] wire xbar_out_0_b_ready; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_b_ready = xbar_anonOut_b_ready; // @[Xbar.scala:74:9] wire xbar_out_0_b_valid = xbar_anonOut_b_valid; // @[Xbar.scala:216:19] wire [2:0] xbar_out_0_b_bits_opcode = xbar_anonOut_b_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] xbar_out_0_b_bits_param = xbar_anonOut_b_bits_param; // @[Xbar.scala:216:19] wire [3:0] xbar_out_0_b_bits_size = xbar_anonOut_b_bits_size; // @[Xbar.scala:216:19] wire xbar_out_0_b_bits_source = xbar_anonOut_b_bits_source; // @[Xbar.scala:216:19] wire [31:0] xbar_out_0_b_bits_address = xbar_anonOut_b_bits_address; // @[Xbar.scala:216:19] wire [7:0] xbar_out_0_b_bits_mask = xbar_anonOut_b_bits_mask; // @[Xbar.scala:216:19] wire [63:0] xbar_out_0_b_bits_data = xbar_anonOut_b_bits_data; // @[Xbar.scala:216:19] wire xbar_out_0_b_bits_corrupt = xbar_anonOut_b_bits_corrupt; // @[Xbar.scala:216:19] wire xbar_out_0_c_ready = xbar_anonOut_c_ready; // @[Xbar.scala:216:19] wire xbar_out_0_c_valid; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_c_valid = xbar_anonOut_c_valid; // @[Xbar.scala:74:9] wire [2:0] xbar_out_0_c_bits_opcode; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_c_bits_opcode = xbar_anonOut_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] xbar_out_0_c_bits_param; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_c_bits_param = xbar_anonOut_c_bits_param; // @[Xbar.scala:74:9] wire [3:0] xbar_out_0_c_bits_size; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_c_bits_size = xbar_anonOut_c_bits_size; // @[Xbar.scala:74:9] wire xbar_out_0_c_bits_source; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_c_bits_source = xbar_anonOut_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] xbar_out_0_c_bits_address; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_c_bits_address = xbar_anonOut_c_bits_address; // @[Xbar.scala:74:9] wire [63:0] xbar_out_0_c_bits_data; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_c_bits_data = xbar_anonOut_c_bits_data; // @[Xbar.scala:74:9] wire xbar_out_0_d_ready; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_d_ready = xbar_anonOut_d_ready; // @[Xbar.scala:74:9] wire xbar_out_0_d_valid = xbar_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] xbar_out_0_d_bits_opcode = xbar_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] xbar_out_0_d_bits_param = xbar_anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [3:0] xbar_out_0_d_bits_size = xbar_anonOut_d_bits_size; // @[Xbar.scala:216:19] wire xbar_out_0_d_bits_source = xbar_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire [2:0] xbar__out_0_d_bits_sink_T = xbar_anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire xbar_out_0_d_bits_denied = xbar_anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] xbar_out_0_d_bits_data = xbar_anonOut_d_bits_data; // @[Xbar.scala:216:19] wire xbar_out_0_d_bits_corrupt = xbar_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire xbar_out_0_e_ready = xbar_anonOut_e_ready; // @[Xbar.scala:216:19] wire xbar_out_0_e_valid; // @[Xbar.scala:216:19] assign xbar_auto_anon_out_e_valid = xbar_anonOut_e_valid; // @[Xbar.scala:74:9] wire [2:0] xbar__anonOut_e_bits_sink_T; // @[Xbar.scala:156:69] assign xbar_auto_anon_out_e_bits_sink = xbar_anonOut_e_bits_sink; // @[Xbar.scala:74:9] wire xbar_in_0_a_ready; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_a_ready = xbar_anonIn_a_ready; // @[Xbar.scala:74:9] wire xbar_in_0_a_valid = xbar_anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] xbar_in_0_a_bits_opcode = xbar_anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] xbar_in_0_a_bits_param = xbar_anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [3:0] xbar_in_0_a_bits_size = xbar_anonIn_a_bits_size; // @[Xbar.scala:159:18] wire xbar__in_0_a_bits_source_T = xbar_anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [31:0] xbar_in_0_a_bits_address = xbar_anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] xbar_in_0_a_bits_mask = xbar_anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] xbar_in_0_a_bits_data = xbar_anonIn_a_bits_data; // @[Xbar.scala:159:18] wire xbar_in_0_b_ready = xbar_anonIn_b_ready; // @[Xbar.scala:159:18] wire xbar_in_0_b_valid; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_b_valid = xbar_anonIn_b_valid; // @[Xbar.scala:74:9] wire [2:0] xbar_in_0_b_bits_opcode; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_b_bits_opcode = xbar_anonIn_b_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] xbar_in_0_b_bits_param; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_b_bits_param = xbar_anonIn_b_bits_param; // @[Xbar.scala:74:9] wire [3:0] xbar_in_0_b_bits_size; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_b_bits_size = xbar_anonIn_b_bits_size; // @[Xbar.scala:74:9] wire xbar__anonIn_b_bits_source_T; // @[Xbar.scala:156:69] assign xbar_auto_anon_in_b_bits_source = xbar_anonIn_b_bits_source; // @[Xbar.scala:74:9] wire [31:0] xbar_in_0_b_bits_address; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_b_bits_address = xbar_anonIn_b_bits_address; // @[Xbar.scala:74:9] wire [7:0] xbar_in_0_b_bits_mask; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_b_bits_mask = xbar_anonIn_b_bits_mask; // @[Xbar.scala:74:9] wire [63:0] xbar_in_0_b_bits_data; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_b_bits_data = xbar_anonIn_b_bits_data; // @[Xbar.scala:74:9] wire xbar_in_0_b_bits_corrupt; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_b_bits_corrupt = xbar_anonIn_b_bits_corrupt; // @[Xbar.scala:74:9] wire xbar_in_0_c_ready; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_c_ready = xbar_anonIn_c_ready; // @[Xbar.scala:74:9] wire xbar_in_0_c_valid = xbar_anonIn_c_valid; // @[Xbar.scala:159:18] wire [2:0] xbar_in_0_c_bits_opcode = xbar_anonIn_c_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] xbar_in_0_c_bits_param = xbar_anonIn_c_bits_param; // @[Xbar.scala:159:18] wire [3:0] xbar_in_0_c_bits_size = xbar_anonIn_c_bits_size; // @[Xbar.scala:159:18] wire xbar__in_0_c_bits_source_T = xbar_anonIn_c_bits_source; // @[Xbar.scala:187:55] wire [31:0] xbar_in_0_c_bits_address = xbar_anonIn_c_bits_address; // @[Xbar.scala:159:18] wire [63:0] xbar_in_0_c_bits_data = xbar_anonIn_c_bits_data; // @[Xbar.scala:159:18] wire xbar_in_0_d_ready = xbar_anonIn_d_ready; // @[Xbar.scala:159:18] wire xbar_in_0_d_valid; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_d_valid = xbar_anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_d_bits_opcode = xbar_anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] xbar_in_0_d_bits_param; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_d_bits_param = xbar_anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [3:0] xbar_in_0_d_bits_size; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_d_bits_size = xbar_anonIn_d_bits_size; // @[Xbar.scala:74:9] wire xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign xbar_auto_anon_in_d_bits_source = xbar_anonIn_d_bits_source; // @[Xbar.scala:74:9] wire [2:0] xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_d_bits_sink = xbar_anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_d_bits_denied = xbar_anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] xbar_in_0_d_bits_data; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_d_bits_data = xbar_anonIn_d_bits_data; // @[Xbar.scala:74:9] wire xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_d_bits_corrupt = xbar_anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire xbar_in_0_e_ready; // @[Xbar.scala:159:18] assign xbar_auto_anon_in_e_ready = xbar_anonIn_e_ready; // @[Xbar.scala:74:9] wire xbar_in_0_e_valid = xbar_anonIn_e_valid; // @[Xbar.scala:159:18] wire [2:0] xbar_in_0_e_bits_sink = xbar_anonIn_e_bits_sink; // @[Xbar.scala:159:18] wire xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:352:24] assign xbar_anonIn_a_ready = xbar_in_0_a_ready; // @[Xbar.scala:159:18] wire xbar__portsAOI_filtered_0_valid_T_1 = xbar_in_0_a_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] xbar_portsAOI_filtered_0_bits_opcode = xbar_in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] xbar_portsAOI_filtered_0_bits_param = xbar_in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] xbar_portsAOI_filtered_0_bits_size = xbar_in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire xbar_portsAOI_filtered_0_bits_source = xbar_in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] xbar__requestAIO_T = xbar_in_0_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] xbar_portsAOI_filtered_0_bits_address = xbar_in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] xbar_portsAOI_filtered_0_bits_mask = xbar_in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] xbar_portsAOI_filtered_0_bits_data = xbar_in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire xbar_portsBIO_filtered_0_ready = xbar_in_0_b_ready; // @[Xbar.scala:159:18, :352:24] wire xbar_portsBIO_filtered_0_valid; // @[Xbar.scala:352:24] assign xbar_anonIn_b_valid = xbar_in_0_b_valid; // @[Xbar.scala:159:18] wire [2:0] xbar_portsBIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign xbar_anonIn_b_bits_opcode = xbar_in_0_b_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] xbar_portsBIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign xbar_anonIn_b_bits_param = xbar_in_0_b_bits_param; // @[Xbar.scala:159:18] wire [3:0] xbar_portsBIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign xbar_anonIn_b_bits_size = xbar_in_0_b_bits_size; // @[Xbar.scala:159:18] wire xbar_portsBIO_filtered_0_bits_source; // @[Xbar.scala:352:24] assign xbar__anonIn_b_bits_source_T = xbar_in_0_b_bits_source; // @[Xbar.scala:156:69, :159:18] wire [31:0] xbar_portsBIO_filtered_0_bits_address; // @[Xbar.scala:352:24] assign xbar_anonIn_b_bits_address = xbar_in_0_b_bits_address; // @[Xbar.scala:159:18] wire [7:0] xbar_portsBIO_filtered_0_bits_mask; // @[Xbar.scala:352:24] assign xbar_anonIn_b_bits_mask = xbar_in_0_b_bits_mask; // @[Xbar.scala:159:18] wire [63:0] xbar_portsBIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign xbar_anonIn_b_bits_data = xbar_in_0_b_bits_data; // @[Xbar.scala:159:18] wire xbar_portsBIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign xbar_anonIn_b_bits_corrupt = xbar_in_0_b_bits_corrupt; // @[Xbar.scala:159:18] wire xbar_portsCOI_filtered_0_ready; // @[Xbar.scala:352:24] assign xbar_anonIn_c_ready = xbar_in_0_c_ready; // @[Xbar.scala:159:18] wire xbar__portsCOI_filtered_0_valid_T_1 = xbar_in_0_c_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] xbar_portsCOI_filtered_0_bits_opcode = xbar_in_0_c_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] xbar_portsCOI_filtered_0_bits_param = xbar_in_0_c_bits_param; // @[Xbar.scala:159:18, :352:24] wire [3:0] xbar_portsCOI_filtered_0_bits_size = xbar_in_0_c_bits_size; // @[Xbar.scala:159:18, :352:24] wire xbar_portsCOI_filtered_0_bits_source = xbar_in_0_c_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] xbar__requestCIO_T = xbar_in_0_c_bits_address; // @[Xbar.scala:159:18] wire [31:0] xbar_portsCOI_filtered_0_bits_address = xbar_in_0_c_bits_address; // @[Xbar.scala:159:18, :352:24] wire [63:0] xbar_portsCOI_filtered_0_bits_data = xbar_in_0_c_bits_data; // @[Xbar.scala:159:18, :352:24] wire xbar_portsDIO_filtered_0_ready = xbar_in_0_d_ready; // @[Xbar.scala:159:18, :352:24] wire xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign xbar_anonIn_d_valid = xbar_in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24] assign xbar_anonIn_d_bits_opcode = xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24] assign xbar_anonIn_d_bits_param = xbar_in_0_d_bits_param; // @[Xbar.scala:159:18] wire [3:0] xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24] assign xbar_anonIn_d_bits_size = xbar_in_0_d_bits_size; // @[Xbar.scala:159:18] wire xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24] assign xbar__anonIn_d_bits_source_T = xbar_in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18] wire [2:0] xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24] assign xbar_anonIn_d_bits_sink = xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18] wire xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24] assign xbar_anonIn_d_bits_denied = xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24] assign xbar_anonIn_d_bits_data = xbar_in_0_d_bits_data; // @[Xbar.scala:159:18] wire xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24] assign xbar_anonIn_d_bits_corrupt = xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18] wire xbar_portsEOI_filtered_0_ready; // @[Xbar.scala:352:24] assign xbar_anonIn_e_ready = xbar_in_0_e_ready; // @[Xbar.scala:159:18] wire xbar__portsEOI_filtered_0_valid_T_1 = xbar_in_0_e_valid; // @[Xbar.scala:159:18, :355:40] wire [2:0] xbar__requestEIO_uncommonBits_T = xbar_in_0_e_bits_sink; // @[Xbar.scala:159:18] wire [2:0] xbar_portsEOI_filtered_0_bits_sink = xbar_in_0_e_bits_sink; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_a_bits_source = xbar__in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign xbar_anonIn_b_bits_source = xbar__anonIn_b_bits_source_T; // @[Xbar.scala:156:69] assign xbar_in_0_c_bits_source = xbar__in_0_c_bits_source_T; // @[Xbar.scala:159:18, :187:55] assign xbar_anonIn_d_bits_source = xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign xbar_portsAOI_filtered_0_ready = xbar_out_0_a_ready; // @[Xbar.scala:216:19, :352:24] wire xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign xbar_anonOut_a_valid = xbar_out_0_a_valid; // @[Xbar.scala:216:19] assign xbar_anonOut_a_bits_opcode = xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign xbar_anonOut_a_bits_param = xbar_out_0_a_bits_param; // @[Xbar.scala:216:19] assign xbar_anonOut_a_bits_size = xbar_out_0_a_bits_size; // @[Xbar.scala:216:19] assign xbar_anonOut_a_bits_source = xbar_out_0_a_bits_source; // @[Xbar.scala:216:19] assign xbar_anonOut_a_bits_address = xbar_out_0_a_bits_address; // @[Xbar.scala:216:19] assign xbar_anonOut_a_bits_mask = xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19] assign xbar_anonOut_a_bits_data = xbar_out_0_a_bits_data; // @[Xbar.scala:216:19] assign xbar_anonOut_b_ready = xbar_out_0_b_ready; // @[Xbar.scala:216:19] wire xbar__portsBIO_filtered_0_valid_T_1 = xbar_out_0_b_valid; // @[Xbar.scala:216:19, :355:40] assign xbar_portsBIO_filtered_0_bits_opcode = xbar_out_0_b_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign xbar_portsBIO_filtered_0_bits_param = xbar_out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24] assign xbar_portsBIO_filtered_0_bits_size = xbar_out_0_b_bits_size; // @[Xbar.scala:216:19, :352:24] wire xbar__requestBOI_uncommonBits_T = xbar_out_0_b_bits_source; // @[Xbar.scala:216:19] assign xbar_portsBIO_filtered_0_bits_source = xbar_out_0_b_bits_source; // @[Xbar.scala:216:19, :352:24] assign xbar_portsBIO_filtered_0_bits_address = xbar_out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24] assign xbar_portsBIO_filtered_0_bits_mask = xbar_out_0_b_bits_mask; // @[Xbar.scala:216:19, :352:24] assign xbar_portsBIO_filtered_0_bits_data = xbar_out_0_b_bits_data; // @[Xbar.scala:216:19, :352:24] assign xbar_portsBIO_filtered_0_bits_corrupt = xbar_out_0_b_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign xbar_portsCOI_filtered_0_ready = xbar_out_0_c_ready; // @[Xbar.scala:216:19, :352:24] wire xbar_portsCOI_filtered_0_valid; // @[Xbar.scala:352:24] assign xbar_anonOut_c_valid = xbar_out_0_c_valid; // @[Xbar.scala:216:19] assign xbar_anonOut_c_bits_opcode = xbar_out_0_c_bits_opcode; // @[Xbar.scala:216:19] assign xbar_anonOut_c_bits_param = xbar_out_0_c_bits_param; // @[Xbar.scala:216:19] assign xbar_anonOut_c_bits_size = xbar_out_0_c_bits_size; // @[Xbar.scala:216:19] assign xbar_anonOut_c_bits_source = xbar_out_0_c_bits_source; // @[Xbar.scala:216:19] assign xbar_anonOut_c_bits_address = xbar_out_0_c_bits_address; // @[Xbar.scala:216:19] assign xbar_anonOut_c_bits_data = xbar_out_0_c_bits_data; // @[Xbar.scala:216:19] assign xbar_anonOut_d_ready = xbar_out_0_d_ready; // @[Xbar.scala:216:19] wire xbar__portsDIO_filtered_0_valid_T_1 = xbar_out_0_d_valid; // @[Xbar.scala:216:19, :355:40] assign xbar_portsDIO_filtered_0_bits_opcode = xbar_out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign xbar_portsDIO_filtered_0_bits_param = xbar_out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24] assign xbar_portsDIO_filtered_0_bits_size = xbar_out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire xbar__requestDOI_uncommonBits_T = xbar_out_0_d_bits_source; // @[Xbar.scala:216:19] assign xbar_portsDIO_filtered_0_bits_source = xbar_out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] assign xbar_portsDIO_filtered_0_bits_sink = xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24] assign xbar_portsDIO_filtered_0_bits_denied = xbar_out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] assign xbar_portsDIO_filtered_0_bits_data = xbar_out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] assign xbar_portsDIO_filtered_0_bits_corrupt = xbar_out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign xbar_portsEOI_filtered_0_ready = xbar_out_0_e_ready; // @[Xbar.scala:216:19, :352:24] wire xbar_portsEOI_filtered_0_valid; // @[Xbar.scala:352:24] assign xbar_anonOut_e_valid = xbar_out_0_e_valid; // @[Xbar.scala:216:19] assign xbar__anonOut_e_bits_sink_T = xbar_out_0_e_bits_sink; // @[Xbar.scala:156:69, :216:19] assign xbar_out_0_d_bits_sink = xbar__out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] assign xbar_anonOut_e_bits_sink = xbar__anonOut_e_bits_sink_T; // @[Xbar.scala:156:69] wire [32:0] xbar__requestAIO_T_1 = {1'h0, xbar__requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] xbar__requestCIO_T_1 = {1'h0, xbar__requestCIO_T}; // @[Parameters.scala:137:{31,41}] wire xbar_requestBOI_uncommonBits = xbar__requestBOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire xbar_requestDOI_uncommonBits = xbar__requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [2:0] xbar_requestEIO_uncommonBits = xbar__requestEIO_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [26:0] xbar__beatsAI_decode_T = 27'hFFF << xbar_in_0_a_bits_size; // @[package.scala:243:71] wire [11:0] xbar__beatsAI_decode_T_1 = xbar__beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] xbar__beatsAI_decode_T_2 = ~xbar__beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] xbar_beatsAI_decode = xbar__beatsAI_decode_T_2[11:3]; // @[package.scala:243:46] wire xbar__beatsAI_opdata_T = xbar_in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire xbar_beatsAI_opdata = ~xbar__beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] xbar_beatsAI_0 = xbar_beatsAI_opdata ? xbar_beatsAI_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [26:0] xbar__beatsBO_decode_T = 27'hFFF << xbar_out_0_b_bits_size; // @[package.scala:243:71] wire [11:0] xbar__beatsBO_decode_T_1 = xbar__beatsBO_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] xbar__beatsBO_decode_T_2 = ~xbar__beatsBO_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] xbar_beatsBO_decode = xbar__beatsBO_decode_T_2[11:3]; // @[package.scala:243:46] wire xbar__beatsBO_opdata_T = xbar_out_0_b_bits_opcode[2]; // @[Xbar.scala:216:19] wire xbar_beatsBO_opdata = ~xbar__beatsBO_opdata_T; // @[Edges.scala:97:{28,37}] wire [26:0] xbar__beatsCI_decode_T = 27'hFFF << xbar_in_0_c_bits_size; // @[package.scala:243:71] wire [11:0] xbar__beatsCI_decode_T_1 = xbar__beatsCI_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] xbar__beatsCI_decode_T_2 = ~xbar__beatsCI_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] xbar_beatsCI_decode = xbar__beatsCI_decode_T_2[11:3]; // @[package.scala:243:46] wire xbar_beatsCI_opdata = xbar_in_0_c_bits_opcode[0]; // @[Xbar.scala:159:18] wire [8:0] xbar_beatsCI_0 = xbar_beatsCI_opdata ? xbar_beatsCI_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] wire [26:0] xbar__beatsDO_decode_T = 27'hFFF << xbar_out_0_d_bits_size; // @[package.scala:243:71] wire [11:0] xbar__beatsDO_decode_T_1 = xbar__beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] xbar__beatsDO_decode_T_2 = ~xbar__beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] xbar_beatsDO_decode = xbar__beatsDO_decode_T_2[11:3]; // @[package.scala:243:46] wire xbar_beatsDO_opdata = xbar_out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [8:0] xbar_beatsDO_0 = xbar_beatsDO_opdata ? xbar_beatsDO_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] assign xbar_in_0_a_ready = xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign xbar_out_0_a_valid = xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_a_bits_opcode = xbar_portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_a_bits_param = xbar_portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_a_bits_size = xbar_portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_a_bits_source = xbar_portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_a_bits_address = xbar_portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_a_bits_mask = xbar_portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_a_bits_data = xbar_portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign xbar_portsAOI_filtered_0_valid = xbar__portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign xbar_out_0_b_ready = xbar_portsBIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] assign xbar_in_0_b_valid = xbar_portsBIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_b_bits_opcode = xbar_portsBIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_b_bits_param = xbar_portsBIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_b_bits_size = xbar_portsBIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_b_bits_source = xbar_portsBIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_b_bits_address = xbar_portsBIO_filtered_0_bits_address; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_b_bits_mask = xbar_portsBIO_filtered_0_bits_mask; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_b_bits_data = xbar_portsBIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_b_bits_corrupt = xbar_portsBIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] assign xbar_portsBIO_filtered_0_valid = xbar__portsBIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign xbar_in_0_c_ready = xbar_portsCOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign xbar_out_0_c_valid = xbar_portsCOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_c_bits_opcode = xbar_portsCOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_c_bits_param = xbar_portsCOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_c_bits_size = xbar_portsCOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_c_bits_source = xbar_portsCOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_c_bits_address = xbar_portsCOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_c_bits_data = xbar_portsCOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign xbar_portsCOI_filtered_0_valid = xbar__portsCOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign xbar_out_0_d_ready = xbar_portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] assign xbar_in_0_d_valid = xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_d_bits_opcode = xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_d_bits_param = xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_d_bits_size = xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_d_bits_source = xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_d_bits_sink = xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_d_bits_denied = xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_d_bits_data = xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24] assign xbar_in_0_d_bits_corrupt = xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24] assign xbar_portsDIO_filtered_0_valid = xbar__portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign xbar_in_0_e_ready = xbar_portsEOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24] assign xbar_out_0_e_valid = xbar_portsEOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign xbar_out_0_e_bits_sink = xbar_portsEOI_filtered_0_bits_sink; // @[Xbar.scala:216:19, :352:24] assign xbar_portsEOI_filtered_0_valid = xbar__portsEOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire widget_anonIn_a_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_a_valid = widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_a_bits_opcode = widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_a_bits_param = widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonIn_a_bits_size = widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonIn_a_bits_source = widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonIn_a_bits_address = widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_anonIn_a_bits_mask = widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonIn_a_bits_data = widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonIn_b_ready = widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9] wire widget_anonIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] widget_anonIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] widget_anonIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] widget_anonIn_b_bits_size; // @[MixedNode.scala:551:17] wire widget_anonIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] widget_anonIn_b_bits_address; // @[MixedNode.scala:551:17] wire [7:0] widget_anonIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] widget_anonIn_b_bits_data; // @[MixedNode.scala:551:17] wire widget_anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire widget_anonIn_c_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_c_valid = widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_c_bits_opcode = widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_c_bits_param = widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonIn_c_bits_size = widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonIn_c_bits_source = widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonIn_c_bits_address = widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonIn_c_bits_data = widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonIn_d_ready = widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire widget_anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire widget_anonIn_e_ready; // @[MixedNode.scala:551:17] wire widget_anonIn_e_valid = widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonIn_e_bits_sink = widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_ready = widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_a_valid; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_a_valid = widget_auto_anon_out_a_valid; // @[Xbar.scala:74:9] wire [2:0] widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_a_bits_opcode = widget_auto_anon_out_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_a_bits_param = widget_auto_anon_out_a_bits_param; // @[Xbar.scala:74:9] wire [3:0] widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_a_bits_size = widget_auto_anon_out_a_bits_size; // @[Xbar.scala:74:9] wire widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_a_bits_source = widget_auto_anon_out_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_a_bits_address = widget_auto_anon_out_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_a_bits_mask = widget_auto_anon_out_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_a_bits_data = widget_auto_anon_out_a_bits_data; // @[Xbar.scala:74:9] wire widget_anonOut_b_ready; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_b_ready = widget_auto_anon_out_b_ready; // @[Xbar.scala:74:9] wire widget_anonOut_b_valid = widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_b_bits_opcode = widget_auto_anon_out_b_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonOut_b_bits_param = widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonOut_b_bits_size = widget_auto_anon_out_b_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonOut_b_bits_source = widget_auto_anon_out_b_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_anonOut_b_bits_address = widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_anonOut_b_bits_mask = widget_auto_anon_out_b_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonOut_b_bits_data = widget_auto_anon_out_b_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonOut_b_bits_corrupt = widget_auto_anon_out_b_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_anonOut_c_ready = widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_c_valid; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_c_valid = widget_auto_anon_out_c_valid; // @[Xbar.scala:74:9] wire [2:0] widget_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_c_bits_opcode = widget_auto_anon_out_c_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] widget_anonOut_c_bits_param; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_c_bits_param = widget_auto_anon_out_c_bits_param; // @[Xbar.scala:74:9] wire [3:0] widget_anonOut_c_bits_size; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_c_bits_size = widget_auto_anon_out_c_bits_size; // @[Xbar.scala:74:9] wire widget_anonOut_c_bits_source; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_c_bits_source = widget_auto_anon_out_c_bits_source; // @[Xbar.scala:74:9] wire [31:0] widget_anonOut_c_bits_address; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_c_bits_address = widget_auto_anon_out_c_bits_address; // @[Xbar.scala:74:9] wire [63:0] widget_anonOut_c_bits_data; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_c_bits_data = widget_auto_anon_out_c_bits_data; // @[Xbar.scala:74:9] wire widget_anonOut_d_ready; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_d_ready = widget_auto_anon_out_d_ready; // @[Xbar.scala:74:9] wire widget_anonOut_d_valid = widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_d_bits_opcode = widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_anonOut_d_bits_param = widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_anonOut_d_bits_size = widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_source = widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] widget_anonOut_d_bits_sink = widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_denied = widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_anonOut_d_bits_data = widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_anonOut_d_bits_corrupt = widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_anonOut_e_ready = widget_auto_anon_out_e_ready; // @[WidthWidget.scala:27:9] wire widget_anonOut_e_valid; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_e_valid = widget_auto_anon_out_e_valid; // @[Xbar.scala:74:9] wire [2:0] widget_anonOut_e_bits_sink; // @[MixedNode.scala:542:17] assign xbar_auto_anon_in_e_bits_sink = widget_auto_anon_out_e_bits_sink; // @[Xbar.scala:74:9] wire widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_b_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_b_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_b_bits_size; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] widget_auto_anon_in_b_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] widget_auto_anon_in_b_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_b_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_b_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_c_ready; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9] wire [2:0] widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9] wire [63:0] widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9] wire widget_auto_anon_in_e_ready; // @[WidthWidget.scala:27:9] assign widget_anonIn_a_ready = widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_a_valid = widget_anonOut_a_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_opcode = widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_param = widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_size = widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_source = widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_address = widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_mask = widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_a_bits_data = widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_b_ready = widget_anonOut_b_ready; // @[WidthWidget.scala:27:9] assign widget_anonIn_b_valid = widget_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_opcode = widget_anonOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_param = widget_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_size = widget_anonOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_source = widget_anonOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_address = widget_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_mask = widget_anonOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_data = widget_anonOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_b_bits_corrupt = widget_anonOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_c_ready = widget_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_c_valid = widget_anonOut_c_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_opcode = widget_anonOut_c_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_param = widget_anonOut_c_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_size = widget_anonOut_c_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_source = widget_anonOut_c_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_address = widget_anonOut_c_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_c_bits_data = widget_anonOut_c_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_d_ready = widget_anonOut_d_ready; // @[WidthWidget.scala:27:9] assign widget_anonIn_d_valid = widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_opcode = widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_param = widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_size = widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_source = widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_sink = widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_denied = widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_data = widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_d_bits_corrupt = widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17] assign widget_anonIn_e_ready = widget_anonOut_e_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_out_e_valid = widget_anonOut_e_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_out_e_bits_sink = widget_anonOut_e_bits_sink; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_a_ready = widget_anonIn_a_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_a_valid = widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_opcode = widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_param = widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_size = widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_source = widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_address = widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_mask = widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_a_bits_data = widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_b_ready = widget_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_in_b_valid = widget_anonIn_b_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_opcode = widget_anonIn_b_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_param = widget_anonIn_b_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_size = widget_anonIn_b_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_source = widget_anonIn_b_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_address = widget_anonIn_b_bits_address; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_mask = widget_anonIn_b_bits_mask; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_data = widget_anonIn_b_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_b_bits_corrupt = widget_anonIn_b_bits_corrupt; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_c_ready = widget_anonIn_c_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_c_valid = widget_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_opcode = widget_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_param = widget_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_size = widget_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_source = widget_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_address = widget_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_c_bits_data = widget_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_d_ready = widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17] assign widget_auto_anon_in_d_valid = widget_anonIn_d_valid; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_opcode = widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_param = widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_size = widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_source = widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_sink = widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_denied = widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_data = widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_d_bits_corrupt = widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] assign widget_auto_anon_in_e_ready = widget_anonIn_e_ready; // @[WidthWidget.scala:27:9] assign widget_anonOut_e_valid = widget_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17] assign widget_anonOut_e_bits_sink = widget_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17] assign reRoCCNodeIn_req_ready = reRoCCNodeOut_req_ready; // @[MixedNode.scala:542:17, :551:17] assign reRoCCNodeIn_resp_valid = reRoCCNodeOut_resp_valid; // @[MixedNode.scala:542:17, :551:17] assign reRoCCNodeIn_resp_bits_opcode = reRoCCNodeOut_resp_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign reRoCCNodeIn_resp_bits_client_id = reRoCCNodeOut_resp_bits_client_id; // @[MixedNode.scala:542:17, :551:17] assign reRoCCNodeIn_resp_bits_manager_id = reRoCCNodeOut_resp_bits_manager_id; // @[MixedNode.scala:542:17, :551:17] wire [2:0] reRoCCNodeOut_req_bits_opcode; // @[MixedNode.scala:542:17] wire [3:0] reRoCCNodeOut_req_bits_client_id; // @[MixedNode.scala:542:17] wire reRoCCNodeOut_req_bits_manager_id; // @[MixedNode.scala:542:17] wire [63:0] reRoCCNodeOut_req_bits_data; // @[MixedNode.scala:542:17] assign reRoCCNodeIn_resp_bits_data = reRoCCNodeOut_resp_bits_data; // @[MixedNode.scala:542:17, :551:17] wire reRoCCNodeOut_req_valid; // @[MixedNode.scala:542:17] wire reRoCCNodeOut_resp_ready; // @[MixedNode.scala:542:17] assign auto_re_ro_cc_in_req_ready_0 = reRoCCNodeIn_req_ready; // @[Manager.scala:237:34] assign reRoCCNodeOut_req_valid = reRoCCNodeIn_req_valid; // @[MixedNode.scala:542:17, :551:17] assign reRoCCNodeOut_req_bits_opcode = reRoCCNodeIn_req_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign reRoCCNodeOut_req_bits_client_id = reRoCCNodeIn_req_bits_client_id; // @[MixedNode.scala:542:17, :551:17] assign reRoCCNodeOut_req_bits_manager_id = reRoCCNodeIn_req_bits_manager_id; // @[MixedNode.scala:542:17, :551:17] assign reRoCCNodeOut_req_bits_data = reRoCCNodeIn_req_bits_data; // @[MixedNode.scala:542:17, :551:17] assign reRoCCNodeOut_resp_ready = reRoCCNodeIn_resp_ready; // @[MixedNode.scala:542:17, :551:17] assign auto_re_ro_cc_in_resp_valid_0 = reRoCCNodeIn_resp_valid; // @[Manager.scala:237:34] assign auto_re_ro_cc_in_resp_bits_opcode_0 = reRoCCNodeIn_resp_bits_opcode; // @[Manager.scala:237:34] assign auto_re_ro_cc_in_resp_bits_client_id_0 = reRoCCNodeIn_resp_bits_client_id; // @[Manager.scala:237:34] assign auto_re_ro_cc_in_resp_bits_manager_id_0 = reRoCCNodeIn_resp_bits_manager_id; // @[Manager.scala:237:34] assign auto_re_ro_cc_in_resp_bits_data_0 = reRoCCNodeIn_resp_bits_data; // @[Manager.scala:237:34] wire accumulator__T_3 = accumulator_io_mem_req_ready & accumulator_io_mem_req_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Manager.scala:237:34] if (reset) begin // @[Manager.scala:237:34] accumulator_busy_0 <= 1'h0; // @[LazyRoCC.scala:125:21] accumulator_busy_1 <= 1'h0; // @[LazyRoCC.scala:125:21] accumulator_busy_2 <= 1'h0; // @[LazyRoCC.scala:125:21] accumulator_busy_3 <= 1'h0; // @[LazyRoCC.scala:125:21] end else begin // @[Manager.scala:237:34] accumulator_busy_0 <= accumulator__T_3 & accumulator_addr == 2'h0 \| ~(accumulator_io_mem_resp_valid & accumulator_memRespTag == 2'h0) & accumulator_busy_0; // @[Decoupled.scala:51:35] accumulator_busy_1 <= accumulator__T_3 & accumulator_addr == 2'h1 \| ~(accumulator_io_mem_resp_valid & accumulator_memRespTag == 2'h1) & accumulator_busy_1; // @[Decoupled.scala:51:35] accumulator_busy_2 <= accumulator__T_3 & accumulator_addr == 2'h2 \| ~(accumulator_io_mem_resp_valid & accumulator_memRespTag == 2'h2) & accumulator_busy_2; // @[Decoupled.scala:51:35] accumulator_busy_3 <= accumulator__T_3 & (&accumulator_addr) \| ~(accumulator_io_mem_resp_valid & (&accumulator_memRespTag)) & accumulator_busy_3; // @[Decoupled.scala:51:35] end always @(posedge) regfile_4x64 regfile_ext ( // @[LazyRoCC.scala:124:20] .R0_addr (accumulator_addr), // @[LazyRoCC.scala:129:26] .R0_en (1'h1), // @[Manager.scala:237:34] .R0_clk (clock), .R0_data (_regfile_ext_R0_data), .W0_addr (accumulator_memRespTag), // @[LazyRoCC.scala:134:40] .W0_en (accumulator_io_mem_resp_valid), // @[LazyRoCC.scala:122:7] .W0_clk (clock), .W0_data (accumulator_io_mem_resp_bits_data), // @[LazyRoCC.scala:122:7] .W1_addr (accumulator_addr), // @[LazyRoCC.scala:129:26] .W1_en (accumulator__q_io_deq_ready_T_4 & _accumulator_cmd_q_io_deq_valid & (accumulator_doWrite \| accumulator_doAccum)), // @[Decoupled.scala:51:35, :362:21] .W1_clk (clock), .W1_data (accumulator_wdata) // @[LazyRoCC.scala:139:18] ); // @[LazyRoCC.scala:124:20] assign accumulator_io_resp_bits_data = _regfile_ext_R0_data; // @[LazyRoCC.scala:122:7, :124:20] Queue2_RoCCCommand_4 accumulator_cmd_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (accumulator_io_cmd_ready), .io_enq_valid (accumulator_io_cmd_valid), // @[LazyRoCC.scala:122:7] .io_enq_bits_inst_funct (accumulator_io_cmd_bits_inst_funct), // @[LazyRoCC.scala:122:7] .io_enq_bits_inst_rs2 (accumulator_io_cmd_bits_inst_rs2), // @[LazyRoCC.scala:122:7] .io_enq_bits_inst_rs1 (accumulator_io_cmd_bits_inst_rs1), // @[LazyRoCC.scala:122:7] .io_enq_bits_inst_xd (accumulator_io_cmd_bits_inst_xd), // @[LazyRoCC.scala:122:7] .io_enq_bits_inst_xs1 (accumulator_io_cmd_bits_inst_xs1), // @[LazyRoCC.scala:122:7] .io_enq_bits_inst_xs2 (accumulator_io_cmd_bits_inst_xs2), // @[LazyRoCC.scala:122:7] .io_enq_bits_inst_rd (accumulator_io_cmd_bits_inst_rd), // @[LazyRoCC.scala:122:7] .io_enq_bits_inst_opcode (accumulator_io_cmd_bits_inst_opcode), // @[LazyRoCC.scala:122:7] .io_enq_bits_rs1 (accumulator_io_cmd_bits_rs1), // @[LazyRoCC.scala:122:7] .io_enq_bits_rs2 (accumulator_io_cmd_bits_rs2), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_debug (accumulator_io_cmd_bits_status_debug), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_cease (accumulator_io_cmd_bits_status_cease), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_wfi (accumulator_io_cmd_bits_status_wfi), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_isa (accumulator_io_cmd_bits_status_isa), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_dprv (accumulator_io_cmd_bits_status_dprv), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_dv (accumulator_io_cmd_bits_status_dv), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_prv (accumulator_io_cmd_bits_status_prv), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_v (accumulator_io_cmd_bits_status_v), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_sd (accumulator_io_cmd_bits_status_sd), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_zero2 (accumulator_io_cmd_bits_status_zero2), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_mpv (accumulator_io_cmd_bits_status_mpv), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_gva (accumulator_io_cmd_bits_status_gva), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_mbe (accumulator_io_cmd_bits_status_mbe), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_sbe (accumulator_io_cmd_bits_status_sbe), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_sxl (accumulator_io_cmd_bits_status_sxl), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_uxl (accumulator_io_cmd_bits_status_uxl), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_sd_rv32 (accumulator_io_cmd_bits_status_sd_rv32), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_zero1 (accumulator_io_cmd_bits_status_zero1), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_tsr (accumulator_io_cmd_bits_status_tsr), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_tw (accumulator_io_cmd_bits_status_tw), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_tvm (accumulator_io_cmd_bits_status_tvm), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_mxr (accumulator_io_cmd_bits_status_mxr), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_sum (accumulator_io_cmd_bits_status_sum), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_mprv (accumulator_io_cmd_bits_status_mprv), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_xs (accumulator_io_cmd_bits_status_xs), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_fs (accumulator_io_cmd_bits_status_fs), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_mpp (accumulator_io_cmd_bits_status_mpp), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_vs (accumulator_io_cmd_bits_status_vs), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_spp (accumulator_io_cmd_bits_status_spp), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_mpie (accumulator_io_cmd_bits_status_mpie), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_ube (accumulator_io_cmd_bits_status_ube), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_spie (accumulator_io_cmd_bits_status_spie), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_upie (accumulator_io_cmd_bits_status_upie), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_mie (accumulator_io_cmd_bits_status_mie), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_hie (accumulator_io_cmd_bits_status_hie), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_sie (accumulator_io_cmd_bits_status_sie), // @[LazyRoCC.scala:122:7] .io_enq_bits_status_uie (accumulator_io_cmd_bits_status_uie), // @[LazyRoCC.scala:122:7] .io_deq_ready (accumulator__q_io_deq_ready_T_4), // @[LazyRoCC.scala:160:40] .io_deq_valid (_accumulator_cmd_q_io_deq_valid), .io_deq_bits_inst_funct (_accumulator_cmd_q_io_deq_bits_inst_funct), .io_deq_bits_inst_xd (_accumulator_cmd_q_io_deq_bits_inst_xd), .io_deq_bits_inst_rd (accumulator_io_resp_bits_rd), .io_deq_bits_rs1 (_accumulator_cmd_q_io_deq_bits_rs1), .io_deq_bits_rs2 (_accumulator_cmd_q_io_deq_bits_rs2), .io_deq_bits_status_dprv (accumulator_io_mem_req_bits_dprv), .io_deq_bits_status_dv (accumulator_io_mem_req_bits_dv) ); // @[Decoupled.scala:362:21] ReRoCCManager_3 rerocc_manager ( // @[Manager.scala:209:34] .clock (clock), .reset (reset), .auto_in_req_ready (_rerocc_manager_auto_in_req_ready), .auto_in_req_valid (_rerocc_buffer_auto_out_req_valid), // @[Protocol.scala:134:35] .auto_in_req_bits_opcode (_rerocc_buffer_auto_out_req_bits_opcode), // @[Protocol.scala:134:35] .auto_in_req_bits_client_id (_rerocc_buffer_auto_out_req_bits_client_id), // @[Protocol.scala:134:35] .auto_in_req_bits_manager_id (_rerocc_buffer_auto_out_req_bits_manager_id), // @[Protocol.scala:134:35] .auto_in_req_bits_data (_rerocc_buffer_auto_out_req_bits_data), // @[Protocol.scala:134:35] .auto_in_resp_ready (_rerocc_buffer_auto_out_resp_ready), // @[Protocol.scala:134:35] .auto_in_resp_valid (_rerocc_manager_auto_in_resp_valid), .auto_in_resp_bits_opcode (_rerocc_manager_auto_in_resp_bits_opcode), .auto_in_resp_bits_client_id (_rerocc_manager_auto_in_resp_bits_client_id), .auto_in_resp_bits_manager_id (_rerocc_manager_auto_in_resp_bits_manager_id), .auto_in_resp_bits_data (_rerocc_manager_auto_in_resp_bits_data), .io_manager_id (reroccManagerIdSinkNodeIn[2:0]), // @[Manager.scala:262:41] .io_cmd_ready (accumulator_io_cmd_ready), // @[LazyRoCC.scala:122:7] .io_cmd_valid (accumulator_io_cmd_valid), .io_cmd_bits_inst_funct (accumulator_io_cmd_bits_inst_funct), .io_cmd_bits_inst_rs2 (accumulator_io_cmd_bits_inst_rs2), .io_cmd_bits_inst_rs1 (accumulator_io_cmd_bits_inst_rs1), .io_cmd_bits_inst_xd (accumulator_io_cmd_bits_inst_xd), .io_cmd_bits_inst_xs1 (accumulator_io_cmd_bits_inst_xs1), .io_cmd_bits_inst_xs2 (accumulator_io_cmd_bits_inst_xs2), .io_cmd_bits_inst_rd (accumulator_io_cmd_bits_inst_rd), .io_cmd_bits_inst_opcode (accumulator_io_cmd_bits_inst_opcode), .io_cmd_bits_rs1 (accumulator_io_cmd_bits_rs1), .io_cmd_bits_rs2 (accumulator_io_cmd_bits_rs2), .io_cmd_bits_status_debug (accumulator_io_cmd_bits_status_debug), .io_cmd_bits_status_cease (accumulator_io_cmd_bits_status_cease), .io_cmd_bits_status_wfi (accumulator_io_cmd_bits_status_wfi), .io_cmd_bits_status_isa (accumulator_io_cmd_bits_status_isa), .io_cmd_bits_status_dprv (accumulator_io_cmd_bits_status_dprv), .io_cmd_bits_status_dv (accumulator_io_cmd_bits_status_dv), .io_cmd_bits_status_prv (accumulator_io_cmd_bits_status_prv), .io_cmd_bits_status_v (accumulator_io_cmd_bits_status_v), .io_cmd_bits_status_sd (accumulator_io_cmd_bits_status_sd), .io_cmd_bits_status_zero2 (accumulator_io_cmd_bits_status_zero2), .io_cmd_bits_status_mpv (accumulator_io_cmd_bits_status_mpv), .io_cmd_bits_status_gva (accumulator_io_cmd_bits_status_gva), .io_cmd_bits_status_mbe (accumulator_io_cmd_bits_status_mbe), .io_cmd_bits_status_sbe (accumulator_io_cmd_bits_status_sbe), .io_cmd_bits_status_sxl (accumulator_io_cmd_bits_status_sxl), .io_cmd_bits_status_uxl (accumulator_io_cmd_bits_status_uxl), .io_cmd_bits_status_sd_rv32 (accumulator_io_cmd_bits_status_sd_rv32), .io_cmd_bits_status_zero1 (accumulator_io_cmd_bits_status_zero1), .io_cmd_bits_status_tsr (accumulator_io_cmd_bits_status_tsr), .io_cmd_bits_status_tw (accumulator_io_cmd_bits_status_tw), .io_cmd_bits_status_tvm (accumulator_io_cmd_bits_status_tvm), .io_cmd_bits_status_mxr (accumulator_io_cmd_bits_status_mxr), .io_cmd_bits_status_sum (accumulator_io_cmd_bits_status_sum), .io_cmd_bits_status_mprv (accumulator_io_cmd_bits_status_mprv), .io_cmd_bits_status_xs (accumulator_io_cmd_bits_status_xs), .io_cmd_bits_status_fs (accumulator_io_cmd_bits_status_fs), .io_cmd_bits_status_mpp (accumulator_io_cmd_bits_status_mpp), .io_cmd_bits_status_vs (accumulator_io_cmd_bits_status_vs), .io_cmd_bits_status_spp (accumulator_io_cmd_bits_status_spp), .io_cmd_bits_status_mpie (accumulator_io_cmd_bits_status_mpie), .io_cmd_bits_status_ube (accumulator_io_cmd_bits_status_ube), .io_cmd_bits_status_spie (accumulator_io_cmd_bits_status_spie), .io_cmd_bits_status_upie (accumulator_io_cmd_bits_status_upie), .io_cmd_bits_status_mie (accumulator_io_cmd_bits_status_mie), .io_cmd_bits_status_hie (accumulator_io_cmd_bits_status_hie), .io_cmd_bits_status_sie (accumulator_io_cmd_bits_status_sie), .io_cmd_bits_status_uie (accumulator_io_cmd_bits_status_uie), .io_resp_ready (accumulator_io_resp_ready), .io_resp_valid (accumulator_io_resp_valid), // @[LazyRoCC.scala:122:7] .io_resp_bits_rd (accumulator_io_resp_bits_rd), // @[LazyRoCC.scala:122:7] .io_resp_bits_data (accumulator_io_resp_bits_data), // @[LazyRoCC.scala:122:7] .io_busy (accumulator_io_busy), // @[LazyRoCC.scala:122:7] .io_ptw_ptbr_mode (_rerocc_manager_io_ptw_ptbr_mode), .io_ptw_ptbr_asid (_rerocc_manager_io_ptw_ptbr_asid), .io_ptw_ptbr_ppn (_rerocc_manager_io_ptw_ptbr_ppn), .io_ptw_sfence_valid (_rerocc_manager_io_ptw_sfence_valid), .io_ptw_status_debug (_rerocc_manager_io_ptw_status_debug), .io_ptw_status_cease (_rerocc_manager_io_ptw_status_cease), .io_ptw_status_wfi (_rerocc_manager_io_ptw_status_wfi), .io_ptw_status_isa (_rerocc_manager_io_ptw_status_isa), .io_ptw_status_dprv (_rerocc_manager_io_ptw_status_dprv), .io_ptw_status_dv (_rerocc_manager_io_ptw_status_dv), .io_ptw_status_prv (_rerocc_manager_io_ptw_status_prv), .io_ptw_status_v (_rerocc_manager_io_ptw_status_v), .io_ptw_status_sd (_rerocc_manager_io_ptw_status_sd), .io_ptw_status_zero2 (_rerocc_manager_io_ptw_status_zero2), .io_ptw_status_mpv (_rerocc_manager_io_ptw_status_mpv), .io_ptw_status_gva (_rerocc_manager_io_ptw_status_gva), .io_ptw_status_mbe (_rerocc_manager_io_ptw_status_mbe), .io_ptw_status_sbe (_rerocc_manager_io_ptw_status_sbe), .io_ptw_status_sxl (_rerocc_manager_io_ptw_status_sxl), .io_ptw_status_uxl (_rerocc_manager_io_ptw_status_uxl), .io_ptw_status_sd_rv32 (_rerocc_manager_io_ptw_status_sd_rv32), .io_ptw_status_zero1 (_rerocc_manager_io_ptw_status_zero1), .io_ptw_status_tsr (_rerocc_manager_io_ptw_status_tsr), .io_ptw_status_tw (_rerocc_manager_io_ptw_status_tw), .io_ptw_status_tvm (_rerocc_manager_io_ptw_status_tvm), .io_ptw_status_mxr (_rerocc_manager_io_ptw_status_mxr), .io_ptw_status_sum (_rerocc_manager_io_ptw_status_sum), .io_ptw_status_mprv (_rerocc_manager_io_ptw_status_mprv), .io_ptw_status_xs (_rerocc_manager_io_ptw_status_xs), .io_ptw_status_fs (_rerocc_manager_io_ptw_status_fs), .io_ptw_status_mpp (_rerocc_manager_io_ptw_status_mpp), .io_ptw_status_vs (_rerocc_manager_io_ptw_status_vs), .io_ptw_status_spp (_rerocc_manager_io_ptw_status_spp), .io_ptw_status_mpie (_rerocc_manager_io_ptw_status_mpie), .io_ptw_status_ube (_rerocc_manager_io_ptw_status_ube), .io_ptw_status_spie (_rerocc_manager_io_ptw_status_spie), .io_ptw_status_upie (_rerocc_manager_io_ptw_status_upie), .io_ptw_status_mie (_rerocc_manager_io_ptw_status_mie), .io_ptw_status_hie (_rerocc_manager_io_ptw_status_hie), .io_ptw_status_sie (_rerocc_manager_io_ptw_status_sie), .io_ptw_status_uie (_rerocc_manager_io_ptw_status_uie), .io_ptw_perf_pte_miss (_ptw_io_dpath_perf_pte_miss), // @[Manager.scala:243:21] .io_ptw_clock_enabled (_ptw_io_dpath_clock_enabled) // @[Manager.scala:243:21] ); // @[Manager.scala:209:34] ReRoCCBuffer_4 rerocc_buffer ( // @[Protocol.scala:134:35] .clock (clock), .reset (reset), .auto_in_req_ready (reRoCCNodeOut_req_ready), .auto_in_req_valid (reRoCCNodeOut_req_valid), // @[MixedNode.scala:542:17] .auto_in_req_bits_opcode (reRoCCNodeOut_req_bits_opcode), // @[MixedNode.scala:542:17] .auto_in_req_bits_client_id (reRoCCNodeOut_req_bits_client_id), // @[MixedNode.scala:542:17] .auto_in_req_bits_manager_id (reRoCCNodeOut_req_bits_manager_id), // @[MixedNode.scala:542:17] .auto_in_req_bits_data (reRoCCNodeOut_req_bits_data), // @[MixedNode.scala:542:17] .auto_in_resp_ready (reRoCCNodeOut_resp_ready), // @[MixedNode.scala:542:17] .auto_in_resp_valid (reRoCCNodeOut_resp_valid), .auto_in_resp_bits_opcode (reRoCCNodeOut_resp_bits_opcode), .auto_in_resp_bits_client_id (reRoCCNodeOut_resp_bits_client_id), .auto_in_resp_bits_manager_id (reRoCCNodeOut_resp_bits_manager_id), .auto_in_resp_bits_data (reRoCCNodeOut_resp_bits_data), .auto_out_req_ready (_rerocc_manager_auto_in_req_ready), // @[Manager.scala:209:34] .auto_out_req_valid (_rerocc_buffer_auto_out_req_valid), .auto_out_req_bits_opcode (_rerocc_buffer_auto_out_req_bits_opcode), .auto_out_req_bits_client_id (_rerocc_buffer_auto_out_req_bits_client_id), .auto_out_req_bits_manager_id (_rerocc_buffer_auto_out_req_bits_manager_id), .auto_out_req_bits_data (_rerocc_buffer_auto_out_req_bits_data), .auto_out_resp_ready (_rerocc_buffer_auto_out_resp_ready), .auto_out_resp_valid (_rerocc_manager_auto_in_resp_valid), // @[Manager.scala:209:34] .auto_out_resp_bits_opcode (_rerocc_manager_auto_in_resp_bits_opcode), // @[Manager.scala:209:34] .auto_out_resp_bits_client_id (_rerocc_manager_auto_in_resp_bits_client_id), // @[Manager.scala:209:34] .auto_out_resp_bits_manager_id (_rerocc_manager_auto_in_resp_bits_manager_id), // @[Manager.scala:209:34] .auto_out_resp_bits_data (_rerocc_manager_auto_in_resp_bits_data) // @[Manager.scala:209:34] ); // @[Protocol.scala:134:35] TLBuffer_a32d64s1k3z4c_7 buffer ( // @[Buffer.scala:75:28] .clock (clock), .reset (reset), .auto_in_a_ready (xbar_auto_anon_out_a_ready), .auto_in_a_valid (xbar_auto_anon_out_a_valid), // @[Xbar.scala:74:9] .auto_in_a_bits_opcode (xbar_auto_anon_out_a_bits_opcode), // @[Xbar.scala:74:9] .auto_in_a_bits_param (xbar_auto_anon_out_a_bits_param), // @[Xbar.scala:74:9] .auto_in_a_bits_size (xbar_auto_anon_out_a_bits_size), // @[Xbar.scala:74:9] .auto_in_a_bits_source (xbar_auto_anon_out_a_bits_source), // @[Xbar.scala:74:9] .auto_in_a_bits_address (xbar_auto_anon_out_a_bits_address), // @[Xbar.scala:74:9] .auto_in_a_bits_mask (xbar_auto_anon_out_a_bits_mask), // @[Xbar.scala:74:9] .auto_in_a_bits_data (xbar_auto_anon_out_a_bits_data), // @[Xbar.scala:74:9] .auto_in_b_ready (xbar_auto_anon_out_b_ready), // @[Xbar.scala:74:9] .auto_in_b_valid (xbar_auto_anon_out_b_valid), .auto_in_b_bits_opcode (xbar_auto_anon_out_b_bits_opcode), .auto_in_b_bits_param (xbar_auto_anon_out_b_bits_param), .auto_in_b_bits_size (xbar_auto_anon_out_b_bits_size), .auto_in_b_bits_source (xbar_auto_anon_out_b_bits_source), .auto_in_b_bits_address (xbar_auto_anon_out_b_bits_address), .auto_in_b_bits_mask (xbar_auto_anon_out_b_bits_mask), .auto_in_b_bits_data (xbar_auto_anon_out_b_bits_data), .auto_in_b_bits_corrupt (xbar_auto_anon_out_b_bits_corrupt), .auto_in_c_ready (xbar_auto_anon_out_c_ready), .auto_in_c_valid (xbar_auto_anon_out_c_valid), // @[Xbar.scala:74:9] .auto_in_c_bits_opcode (xbar_auto_anon_out_c_bits_opcode), // @[Xbar.scala:74:9] .auto_in_c_bits_param (xbar_auto_anon_out_c_bits_param), // @[Xbar.scala:74:9] .auto_in_c_bits_size (xbar_auto_anon_out_c_bits_size), // @[Xbar.scala:74:9] .auto_in_c_bits_source (xbar_auto_anon_out_c_bits_source), // @[Xbar.scala:74:9] .auto_in_c_bits_address (xbar_auto_anon_out_c_bits_address), // @[Xbar.scala:74:9] .auto_in_c_bits_data (xbar_auto_anon_out_c_bits_data), // @[Xbar.scala:74:9] .auto_in_d_ready (xbar_auto_anon_out_d_ready), // @[Xbar.scala:74:9] .auto_in_d_valid (xbar_auto_anon_out_d_valid), .auto_in_d_bits_opcode (xbar_auto_anon_out_d_bits_opcode), .auto_in_d_bits_param (xbar_auto_anon_out_d_bits_param), .auto_in_d_bits_size (xbar_auto_anon_out_d_bits_size), .auto_in_d_bits_source (xbar_auto_anon_out_d_bits_source), .auto_in_d_bits_sink (xbar_auto_anon_out_d_bits_sink), .auto_in_d_bits_denied (xbar_auto_anon_out_d_bits_denied), .auto_in_d_bits_data (xbar_auto_anon_out_d_bits_data), .auto_in_d_bits_corrupt (xbar_auto_anon_out_d_bits_corrupt), .auto_in_e_ready (xbar_auto_anon_out_e_ready), .auto_in_e_valid (xbar_auto_anon_out_e_valid), // @[Xbar.scala:74:9] .auto_in_e_bits_sink (xbar_auto_anon_out_e_bits_sink), // @[Xbar.scala:74:9] .auto_out_a_ready (auto_buffer_out_a_ready_0), // @[Manager.scala:237:34] .auto_out_a_valid (auto_buffer_out_a_valid_0), .auto_out_a_bits_opcode (auto_buffer_out_a_bits_opcode_0), .auto_out_a_bits_param (auto_buffer_out_a_bits_param_0), .auto_out_a_bits_size (auto_buffer_out_a_bits_size_0), .auto_out_a_bits_source (auto_buffer_out_a_bits_source_0), .auto_out_a_bits_address (auto_buffer_out_a_bits_address_0), .auto_out_a_bits_mask (auto_buffer_out_a_bits_mask_0), .auto_out_a_bits_data (auto_buffer_out_a_bits_data_0), .auto_out_a_bits_corrupt (auto_buffer_out_a_bits_corrupt_0), .auto_out_b_ready (auto_buffer_out_b_ready_0), .auto_out_b_valid (auto_buffer_out_b_valid_0), // @[Manager.scala:237:34] .auto_out_b_bits_opcode (auto_buffer_out_b_bits_opcode_0), // @[Manager.scala:237:34] .auto_out_b_bits_param (auto_buffer_out_b_bits_param_0), // @[Manager.scala:237:34] .auto_out_b_bits_size (auto_buffer_out_b_bits_size_0), // @[Manager.scala:237:34] .auto_out_b_bits_source (auto_buffer_out_b_bits_source_0), // @[Manager.scala:237:34] .auto_out_b_bits_address (auto_buffer_out_b_bits_address_0), // @[Manager.scala:237:34] .auto_out_b_bits_mask (auto_buffer_out_b_bits_mask_0), // @[Manager.scala:237:34] .auto_out_b_bits_data (auto_buffer_out_b_bits_data_0), // @[Manager.scala:237:34] .auto_out_b_bits_corrupt (auto_buffer_out_b_bits_corrupt_0), // @[Manager.scala:237:34] .auto_out_c_ready (auto_buffer_out_c_ready_0), // @[Manager.scala:237:34] .auto_out_c_valid (auto_buffer_out_c_valid_0), .auto_out_c_bits_opcode (auto_buffer_out_c_bits_opcode_0), .auto_out_c_bits_param (auto_buffer_out_c_bits_param_0), .auto_out_c_bits_size (auto_buffer_out_c_bits_size_0), .auto_out_c_bits_source (auto_buffer_out_c_bits_source_0), .auto_out_c_bits_address (auto_buffer_out_c_bits_address_0), .auto_out_c_bits_data (auto_buffer_out_c_bits_data_0), .auto_out_c_bits_corrupt (auto_buffer_out_c_bits_corrupt_0), .auto_out_d_ready (auto_buffer_out_d_ready_0), .auto_out_d_valid (auto_buffer_out_d_valid_0), // @[Manager.scala:237:34] .auto_out_d_bits_opcode (auto_buffer_out_d_bits_opcode_0), // @[Manager.scala:237:34] .auto_out_d_bits_param (auto_buffer_out_d_bits_param_0), // @[Manager.scala:237:34] .auto_out_d_bits_size (auto_buffer_out_d_bits_size_0), // @[Manager.scala:237:34] .auto_out_d_bits_source (auto_buffer_out_d_bits_source_0), // @[Manager.scala:237:34] .auto_out_d_bits_sink (auto_buffer_out_d_bits_sink_0), // @[Manager.scala:237:34] .auto_out_d_bits_denied (auto_buffer_out_d_bits_denied_0), // @[Manager.scala:237:34] .auto_out_d_bits_data (auto_buffer_out_d_bits_data_0), // @[Manager.scala:237:34] .auto_out_d_bits_corrupt (auto_buffer_out_d_bits_corrupt_0), // @[Manager.scala:237:34] .auto_out_e_ready (auto_buffer_out_e_ready_0), // @[Manager.scala:237:34] .auto_out_e_valid (auto_buffer_out_e_valid_0), .auto_out_e_bits_sink (auto_buffer_out_e_bits_sink_0) ); // @[Buffer.scala:75:28] MiniDCache_3 dcache ( // @[Manager.scala:226:61] .clock (clock), .reset (reset), .auto_out_a_ready (widget_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9] .auto_out_a_valid (widget_auto_anon_in_a_valid), .auto_out_a_bits_opcode (widget_auto_anon_in_a_bits_opcode), .auto_out_a_bits_param (widget_auto_anon_in_a_bits_param), .auto_out_a_bits_size (widget_auto_anon_in_a_bits_size), .auto_out_a_bits_source (widget_auto_anon_in_a_bits_source), .auto_out_a_bits_address (widget_auto_anon_in_a_bits_address), .auto_out_a_bits_mask (widget_auto_anon_in_a_bits_mask), .auto_out_a_bits_data (widget_auto_anon_in_a_bits_data), .auto_out_b_ready (widget_auto_anon_in_b_ready), .auto_out_b_valid (widget_auto_anon_in_b_valid), // @[WidthWidget.scala:27:9] .auto_out_b_bits_opcode (widget_auto_anon_in_b_bits_opcode), // @[WidthWidget.scala:27:9] .auto_out_b_bits_param (widget_auto_anon_in_b_bits_param), // @[WidthWidget.scala:27:9] .auto_out_b_bits_size (widget_auto_anon_in_b_bits_size), // @[WidthWidget.scala:27:9] .auto_out_b_bits_source (widget_auto_anon_in_b_bits_source), // @[WidthWidget.scala:27:9] .auto_out_b_bits_address (widget_auto_anon_in_b_bits_address), // @[WidthWidget.scala:27:9] .auto_out_b_bits_mask (widget_auto_anon_in_b_bits_mask), // @[WidthWidget.scala:27:9] .auto_out_b_bits_data (widget_auto_anon_in_b_bits_data), // @[WidthWidget.scala:27:9] .auto_out_b_bits_corrupt (widget_auto_anon_in_b_bits_corrupt), // @[WidthWidget.scala:27:9] .auto_out_c_ready (widget_auto_anon_in_c_ready), // @[WidthWidget.scala:27:9] .auto_out_c_valid (widget_auto_anon_in_c_valid), .auto_out_c_bits_opcode (widget_auto_anon_in_c_bits_opcode), .auto_out_c_bits_param (widget_auto_anon_in_c_bits_param), .auto_out_c_bits_size (widget_auto_anon_in_c_bits_size), .auto_out_c_bits_source (widget_auto_anon_in_c_bits_source), .auto_out_c_bits_address (widget_auto_anon_in_c_bits_address), .auto_out_c_bits_data (widget_auto_anon_in_c_bits_data), .auto_out_d_ready (widget_auto_anon_in_d_ready), .auto_out_d_valid (widget_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9] .auto_out_d_bits_opcode (widget_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9] .auto_out_d_bits_param (widget_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9] .auto_out_d_bits_size (widget_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9] .auto_out_d_bits_source (widget_auto_anon_in_d_bits_source), // @[WidthWidget.scala:27:9] .auto_out_d_bits_sink (widget_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9] .auto_out_d_bits_denied (widget_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9] .auto_out_d_bits_data (widget_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9] .auto_out_d_bits_corrupt (widget_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9] .auto_out_e_ready (widget_auto_anon_in_e_ready), // @[WidthWidget.scala:27:9] .auto_out_e_valid (widget_auto_anon_in_e_valid), .auto_out_e_bits_sink (widget_auto_anon_in_e_bits_sink), .io_cpu_req_ready (_dcache_io_cpu_req_ready), .io_cpu_req_valid (_dcacheArb_io_mem_req_valid), // @[Manager.scala:238:27] .io_cpu_req_bits_addr (_dcacheArb_io_mem_req_bits_addr), // @[Manager.scala:238:27] .io_cpu_req_bits_tag (_dcacheArb_io_mem_req_bits_tag), // @[Manager.scala:238:27] .io_cpu_req_bits_dprv (_dcacheArb_io_mem_req_bits_dprv), // @[Manager.scala:238:27] .io_cpu_req_bits_dv (_dcacheArb_io_mem_req_bits_dv), // @[Manager.scala:238:27] .io_cpu_req_bits_phys (_dcacheArb_io_mem_req_bits_phys), // @[Manager.scala:238:27] .io_cpu_s1_kill (_dcacheArb_io_mem_s1_kill), // @[Manager.scala:238:27] .io_cpu_s1_data_data (_dcacheArb_io_mem_s1_data_data), // @[Manager.scala:238:27] .io_cpu_s1_data_mask (_dcacheArb_io_mem_s1_data_mask), // @[Manager.scala:238:27] .io_cpu_s2_nack (_dcache_io_cpu_s2_nack), .io_cpu_s2_nack_cause_raw (_dcache_io_cpu_s2_nack_cause_raw), .io_cpu_s2_uncached (_dcache_io_cpu_s2_uncached), .io_cpu_s2_paddr (_dcache_io_cpu_s2_paddr), .io_cpu_resp_valid (_dcache_io_cpu_resp_valid), .io_cpu_resp_bits_addr (_dcache_io_cpu_resp_bits_addr), .io_cpu_resp_bits_tag (_dcache_io_cpu_resp_bits_tag), .io_cpu_resp_bits_cmd (_dcache_io_cpu_resp_bits_cmd), .io_cpu_resp_bits_size (_dcache_io_cpu_resp_bits_size), .io_cpu_resp_bits_signed (_dcache_io_cpu_resp_bits_signed), .io_cpu_resp_bits_dprv (_dcache_io_cpu_resp_bits_dprv), .io_cpu_resp_bits_dv (_dcache_io_cpu_resp_bits_dv), .io_cpu_resp_bits_data (_dcache_io_cpu_resp_bits_data), .io_cpu_resp_bits_mask (_dcache_io_cpu_resp_bits_mask), .io_cpu_resp_bits_replay (_dcache_io_cpu_resp_bits_replay), .io_cpu_resp_bits_has_data (_dcache_io_cpu_resp_bits_has_data), .io_cpu_resp_bits_data_word_bypass (_dcache_io_cpu_resp_bits_data_word_bypass), .io_cpu_resp_bits_data_raw (_dcache_io_cpu_resp_bits_data_raw), .io_cpu_resp_bits_store_data (_dcache_io_cpu_resp_bits_store_data), .io_cpu_replay_next (_dcache_io_cpu_replay_next), .io_cpu_s2_xcpt_ma_ld (_dcache_io_cpu_s2_xcpt_ma_ld), .io_cpu_s2_xcpt_ma_st (_dcache_io_cpu_s2_xcpt_ma_st), .io_cpu_s2_xcpt_pf_ld (_dcache_io_cpu_s2_xcpt_pf_ld), .io_cpu_s2_xcpt_pf_st (_dcache_io_cpu_s2_xcpt_pf_st), .io_cpu_s2_xcpt_ae_ld (_dcache_io_cpu_s2_xcpt_ae_ld), .io_cpu_s2_xcpt_ae_st (_dcache_io_cpu_s2_xcpt_ae_st), .io_cpu_s2_gpa (_dcache_io_cpu_s2_gpa), .io_cpu_ordered (_dcache_io_cpu_ordered), .io_cpu_store_pending (_dcache_io_cpu_store_pending), .io_cpu_perf_acquire (_dcache_io_cpu_perf_acquire), .io_cpu_perf_release (_dcache_io_cpu_perf_release), .io_cpu_perf_grant (_dcache_io_cpu_perf_grant), .io_cpu_perf_tlbMiss (_dcache_io_cpu_perf_tlbMiss), .io_cpu_perf_blocked (_dcache_io_cpu_perf_blocked), .io_cpu_perf_canAcceptStoreThenLoad (_dcache_io_cpu_perf_canAcceptStoreThenLoad), .io_cpu_perf_canAcceptStoreThenRMW (_dcache_io_cpu_perf_canAcceptStoreThenRMW), .io_cpu_perf_canAcceptLoadThenLoad (_dcache_io_cpu_perf_canAcceptLoadThenLoad), .io_cpu_perf_storeBufferEmptyAfterLoad (_dcache_io_cpu_perf_storeBufferEmptyAfterLoad), .io_cpu_perf_storeBufferEmptyAfterStore (_dcache_io_cpu_perf_storeBufferEmptyAfterStore), .io_ptw_req_ready (_ptw_io_requestor_0_req_ready), // @[Manager.scala:243:21] .io_ptw_req_valid (_dcache_io_ptw_req_valid), .io_ptw_req_bits_bits_addr (_dcache_io_ptw_req_bits_bits_addr), .io_ptw_req_bits_bits_need_gpa (_dcache_io_ptw_req_bits_bits_need_gpa), .io_ptw_resp_valid (_ptw_io_requestor_0_resp_valid), // @[Manager.scala:243:21] .io_ptw_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw), // @[Manager.scala:243:21] .io_ptw_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final), // @[Manager.scala:243:21] .io_ptw_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf), // @[Manager.scala:243:21] .io_ptw_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf), // @[Manager.scala:243:21] .io_ptw_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr), // @[Manager.scala:243:21] .io_ptw_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw), // @[Manager.scala:243:21] .io_ptw_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx), // @[Manager.scala:243:21] .io_ptw_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future), // @[Manager.scala:243:21] .io_ptw_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn), // @[Manager.scala:243:21] .io_ptw_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software), // @[Manager.scala:243:21] .io_ptw_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d), // @[Manager.scala:243:21] .io_ptw_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a), // @[Manager.scala:243:21] .io_ptw_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g), // @[Manager.scala:243:21] .io_ptw_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u), // @[Manager.scala:243:21] .io_ptw_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x), // @[Manager.scala:243:21] .io_ptw_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w), // @[Manager.scala:243:21] .io_ptw_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r), // @[Manager.scala:243:21] .io_ptw_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v), // @[Manager.scala:243:21] .io_ptw_resp_bits_level (_ptw_io_requestor_0_resp_bits_level), // @[Manager.scala:243:21] .io_ptw_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous), // @[Manager.scala:243:21] .io_ptw_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid), // @[Manager.scala:243:21] .io_ptw_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits), // @[Manager.scala:243:21] .io_ptw_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte), // @[Manager.scala:243:21] .io_ptw_ptbr_mode (_ptw_io_requestor_0_ptbr_mode), // @[Manager.scala:243:21] .io_ptw_ptbr_asid (_ptw_io_requestor_0_ptbr_asid), // @[Manager.scala:243:21] .io_ptw_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn), // @[Manager.scala:243:21] .io_ptw_status_debug (_ptw_io_requestor_0_status_debug), // @[Manager.scala:243:21] .io_ptw_status_cease (_ptw_io_requestor_0_status_cease), // @[Manager.scala:243:21] .io_ptw_status_wfi (_ptw_io_requestor_0_status_wfi), // @[Manager.scala:243:21] .io_ptw_status_isa (_ptw_io_requestor_0_status_isa), // @[Manager.scala:243:21] .io_ptw_status_dprv (_ptw_io_requestor_0_status_dprv), // @[Manager.scala:243:21] .io_ptw_status_dv (_ptw_io_requestor_0_status_dv), // @[Manager.scala:243:21] .io_ptw_status_prv (_ptw_io_requestor_0_status_prv), // @[Manager.scala:243:21] .io_ptw_status_v (_ptw_io_requestor_0_status_v), // @[Manager.scala:243:21] .io_ptw_status_sd (_ptw_io_requestor_0_status_sd), // @[Manager.scala:243:21] .io_ptw_status_zero2 (_ptw_io_requestor_0_status_zero2), // @[Manager.scala:243:21] .io_ptw_status_mpv (_ptw_io_requestor_0_status_mpv), // @[Manager.scala:243:21] .io_ptw_status_gva (_ptw_io_requestor_0_status_gva), // @[Manager.scala:243:21] .io_ptw_status_mbe (_ptw_io_requestor_0_status_mbe), // @[Manager.scala:243:21] .io_ptw_status_sbe (_ptw_io_requestor_0_status_sbe), // @[Manager.scala:243:21] .io_ptw_status_sxl (_ptw_io_requestor_0_status_sxl), // @[Manager.scala:243:21] .io_ptw_status_uxl (_ptw_io_requestor_0_status_uxl), // @[Manager.scala:243:21] .io_ptw_status_sd_rv32 (_ptw_io_requestor_0_status_sd_rv32), // @[Manager.scala:243:21] .io_ptw_status_zero1 (_ptw_io_requestor_0_status_zero1), // @[Manager.scala:243:21] .io_ptw_status_tsr (_ptw_io_requestor_0_status_tsr), // @[Manager.scala:243:21] .io_ptw_status_tw (_ptw_io_requestor_0_status_tw), // @[Manager.scala:243:21] .io_ptw_status_tvm (_ptw_io_requestor_0_status_tvm), // @[Manager.scala:243:21] .io_ptw_status_mxr (_ptw_io_requestor_0_status_mxr), // @[Manager.scala:243:21] .io_ptw_status_sum (_ptw_io_requestor_0_status_sum), // @[Manager.scala:243:21] .io_ptw_status_mprv (_ptw_io_requestor_0_status_mprv), // @[Manager.scala:243:21] .io_ptw_status_xs (_ptw_io_requestor_0_status_xs), // @[Manager.scala:243:21] .io_ptw_status_fs (_ptw_io_requestor_0_status_fs), // @[Manager.scala:243:21] .io_ptw_status_mpp (_ptw_io_requestor_0_status_mpp), // @[Manager.scala:243:21] .io_ptw_status_vs (_ptw_io_requestor_0_status_vs), // @[Manager.scala:243:21] .io_ptw_status_spp (_ptw_io_requestor_0_status_spp), // @[Manager.scala:243:21] .io_ptw_status_mpie (_ptw_io_requestor_0_status_mpie), // @[Manager.scala:243:21] .io_ptw_status_ube (_ptw_io_requestor_0_status_ube), // @[Manager.scala:243:21] .io_ptw_status_spie (_ptw_io_requestor_0_status_spie), // @[Manager.scala:243:21] .io_ptw_status_upie (_ptw_io_requestor_0_status_upie), // @[Manager.scala:243:21] .io_ptw_status_mie (_ptw_io_requestor_0_status_mie), // @[Manager.scala:243:21] .io_ptw_status_hie (_ptw_io_requestor_0_status_hie), // @[Manager.scala:243:21] .io_ptw_status_sie (_ptw_io_requestor_0_status_sie), // @[Manager.scala:243:21] .io_ptw_status_uie (_ptw_io_requestor_0_status_uie) // @[Manager.scala:243:21] ); // @[Manager.scala:226:61] ReRoCCManagerControl_3 ctrl ( // @[Manager.scala:235:24] .clock (clock), .reset (reset), .auto_ctrl_in_a_ready (auto_ctrl_ctrl_in_a_ready_0), .auto_ctrl_in_a_valid (auto_ctrl_ctrl_in_a_valid_0), // @[Manager.scala:237:34] .auto_ctrl_in_a_bits_opcode (auto_ctrl_ctrl_in_a_bits_opcode_0), // @[Manager.scala:237:34] .auto_ctrl_in_a_bits_param (auto_ctrl_ctrl_in_a_bits_param_0), // @[Manager.scala:237:34] .auto_ctrl_in_a_bits_size (auto_ctrl_ctrl_in_a_bits_size_0), // @[Manager.scala:237:34] .auto_ctrl_in_a_bits_source (auto_ctrl_ctrl_in_a_bits_source_0), // @[Manager.scala:237:34] .auto_ctrl_in_a_bits_address (auto_ctrl_ctrl_in_a_bits_address_0), // @[Manager.scala:237:34] .auto_ctrl_in_a_bits_mask (auto_ctrl_ctrl_in_a_bits_mask_0), // @[Manager.scala:237:34] .auto_ctrl_in_a_bits_data (auto_ctrl_ctrl_in_a_bits_data_0), // @[Manager.scala:237:34] .auto_ctrl_in_a_bits_corrupt (auto_ctrl_ctrl_in_a_bits_corrupt_0), // @[Manager.scala:237:34] .auto_ctrl_in_d_ready (auto_ctrl_ctrl_in_d_ready_0), // @[Manager.scala:237:34] .auto_ctrl_in_d_valid (auto_ctrl_ctrl_in_d_valid_0), .auto_ctrl_in_d_bits_opcode (auto_ctrl_ctrl_in_d_bits_opcode_0), .auto_ctrl_in_d_bits_size (auto_ctrl_ctrl_in_d_bits_size_0), .auto_ctrl_in_d_bits_source (auto_ctrl_ctrl_in_d_bits_source_0), .auto_ctrl_in_d_bits_data (auto_ctrl_ctrl_in_d_bits_data_0), .io_mgr_busy (accumulator_io_busy), // @[LazyRoCC.scala:122:7] .io_rocc_busy (accumulator_io_busy) // @[LazyRoCC.scala:122:7] ); // @[Manager.scala:235:24] HellaCacheArbiter_4 dcacheArb ( // @[Manager.scala:238:27] .clock (clock), .reset (reset), .io_requestor_0_req_ready (_dcacheArb_io_requestor_0_req_ready), .io_requestor_0_req_valid (_ptw_io_mem_req_valid), // @[Manager.scala:243:21] .io_requestor_0_req_bits_addr (_ptw_io_mem_req_bits_addr), // @[Manager.scala:243:21] .io_requestor_0_req_bits_dv (_ptw_io_mem_req_bits_dv), // @[Manager.scala:243:21] .io_requestor_0_s1_kill (_ptw_io_mem_s1_kill), // @[Manager.scala:243:21] .io_requestor_0_s2_nack (_dcacheArb_io_requestor_0_s2_nack), .io_requestor_0_s2_nack_cause_raw (_dcacheArb_io_requestor_0_s2_nack_cause_raw), .io_requestor_0_s2_uncached (_dcacheArb_io_requestor_0_s2_uncached), .io_requestor_0_s2_paddr (_dcacheArb_io_requestor_0_s2_paddr), .io_requestor_0_resp_valid (_dcacheArb_io_requestor_0_resp_valid), .io_requestor_0_resp_bits_addr (_dcacheArb_io_requestor_0_resp_bits_addr), .io_requestor_0_resp_bits_tag (_dcacheArb_io_requestor_0_resp_bits_tag), .io_requestor_0_resp_bits_cmd (_dcacheArb_io_requestor_0_resp_bits_cmd), .io_requestor_0_resp_bits_size (_dcacheArb_io_requestor_0_resp_bits_size), .io_requestor_0_resp_bits_signed (_dcacheArb_io_requestor_0_resp_bits_signed), .io_requestor_0_resp_bits_dprv (_dcacheArb_io_requestor_0_resp_bits_dprv), .io_requestor_0_resp_bits_dv (_dcacheArb_io_requestor_0_resp_bits_dv), .io_requestor_0_resp_bits_data (_dcacheArb_io_requestor_0_resp_bits_data), .io_requestor_0_resp_bits_mask (_dcacheArb_io_requestor_0_resp_bits_mask), .io_requestor_0_resp_bits_replay (_dcacheArb_io_requestor_0_resp_bits_replay), .io_requestor_0_resp_bits_has_data (_dcacheArb_io_requestor_0_resp_bits_has_data), .io_requestor_0_resp_bits_data_word_bypass (_dcacheArb_io_requestor_0_resp_bits_data_word_bypass), .io_requestor_0_resp_bits_data_raw (_dcacheArb_io_requestor_0_resp_bits_data_raw), .io_requestor_0_resp_bits_store_data (_dcacheArb_io_requestor_0_resp_bits_store_data), .io_requestor_0_replay_next (_dcacheArb_io_requestor_0_replay_next), .io_requestor_0_s2_xcpt_ma_ld (_dcacheArb_io_requestor_0_s2_xcpt_ma_ld), .io_requestor_0_s2_xcpt_ma_st (_dcacheArb_io_requestor_0_s2_xcpt_ma_st), .io_requestor_0_s2_xcpt_pf_ld (_dcacheArb_io_requestor_0_s2_xcpt_pf_ld), .io_requestor_0_s2_xcpt_pf_st (_dcacheArb_io_requestor_0_s2_xcpt_pf_st), .io_requestor_0_s2_xcpt_ae_ld (_dcacheArb_io_requestor_0_s2_xcpt_ae_ld), .io_requestor_0_s2_xcpt_ae_st (_dcacheArb_io_requestor_0_s2_xcpt_ae_st), .io_requestor_0_s2_gpa (_dcacheArb_io_requestor_0_s2_gpa), .io_requestor_0_ordered (_dcacheArb_io_requestor_0_ordered), .io_requestor_0_store_pending (_dcacheArb_io_requestor_0_store_pending), .io_requestor_0_perf_acquire (_dcacheArb_io_requestor_0_perf_acquire), .io_requestor_0_perf_release (_dcacheArb_io_requestor_0_perf_release), .io_requestor_0_perf_grant (_dcacheArb_io_requestor_0_perf_grant), .io_requestor_0_perf_tlbMiss (_dcacheArb_io_requestor_0_perf_tlbMiss), .io_requestor_0_perf_blocked (_dcacheArb_io_requestor_0_perf_blocked), .io_requestor_0_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad), .io_requestor_0_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW), .io_requestor_0_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad), .io_requestor_0_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad), .io_requestor_0_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore), .io_requestor_1_req_ready (_dcacheArb_io_requestor_1_req_ready), .io_requestor_1_req_valid (_dcIF_io_cache_req_valid), // @[Manager.scala:255:22] .io_requestor_1_req_bits_addr (_dcIF_io_cache_req_bits_addr), // @[Manager.scala:255:22] .io_requestor_1_req_bits_tag (_dcIF_io_cache_req_bits_tag), // @[Manager.scala:255:22] .io_requestor_1_req_bits_dprv (_dcIF_io_cache_req_bits_dprv), // @[Manager.scala:255:22] .io_requestor_1_req_bits_dv (_dcIF_io_cache_req_bits_dv), // @[Manager.scala:255:22] .io_requestor_1_s1_data_data (_dcIF_io_cache_s1_data_data), // @[Manager.scala:255:22] .io_requestor_1_s1_data_mask (_dcIF_io_cache_s1_data_mask), // @[Manager.scala:255:22] .io_requestor_1_s2_nack (_dcacheArb_io_requestor_1_s2_nack), .io_requestor_1_s2_nack_cause_raw (_dcacheArb_io_requestor_1_s2_nack_cause_raw), .io_requestor_1_s2_uncached (_dcacheArb_io_requestor_1_s2_uncached), .io_requestor_1_s2_paddr (_dcacheArb_io_requestor_1_s2_paddr), .io_requestor_1_resp_valid (_dcacheArb_io_requestor_1_resp_valid), .io_requestor_1_resp_bits_addr (_dcacheArb_io_requestor_1_resp_bits_addr), .io_requestor_1_resp_bits_tag (_dcacheArb_io_requestor_1_resp_bits_tag), .io_requestor_1_resp_bits_cmd (_dcacheArb_io_requestor_1_resp_bits_cmd), .io_requestor_1_resp_bits_size (_dcacheArb_io_requestor_1_resp_bits_size), .io_requestor_1_resp_bits_signed (_dcacheArb_io_requestor_1_resp_bits_signed), .io_requestor_1_resp_bits_dprv (_dcacheArb_io_requestor_1_resp_bits_dprv), .io_requestor_1_resp_bits_dv (_dcacheArb_io_requestor_1_resp_bits_dv), .io_requestor_1_resp_bits_data (_dcacheArb_io_requestor_1_resp_bits_data), .io_requestor_1_resp_bits_mask (_dcacheArb_io_requestor_1_resp_bits_mask), .io_requestor_1_resp_bits_replay (_dcacheArb_io_requestor_1_resp_bits_replay), .io_requestor_1_resp_bits_has_data (_dcacheArb_io_requestor_1_resp_bits_has_data), .io_requestor_1_resp_bits_data_word_bypass (_dcacheArb_io_requestor_1_resp_bits_data_word_bypass), .io_requestor_1_resp_bits_data_raw (_dcacheArb_io_requestor_1_resp_bits_data_raw), .io_requestor_1_resp_bits_store_data (_dcacheArb_io_requestor_1_resp_bits_store_data), .io_requestor_1_replay_next (_dcacheArb_io_requestor_1_replay_next), .io_requestor_1_s2_xcpt_ma_ld (_dcacheArb_io_requestor_1_s2_xcpt_ma_ld), .io_requestor_1_s2_xcpt_ma_st (_dcacheArb_io_requestor_1_s2_xcpt_ma_st), .io_requestor_1_s2_xcpt_pf_ld (_dcacheArb_io_requestor_1_s2_xcpt_pf_ld), .io_requestor_1_s2_xcpt_pf_st (_dcacheArb_io_requestor_1_s2_xcpt_pf_st), .io_requestor_1_s2_xcpt_ae_ld (_dcacheArb_io_requestor_1_s2_xcpt_ae_ld), .io_requestor_1_s2_xcpt_ae_st (_dcacheArb_io_requestor_1_s2_xcpt_ae_st), .io_requestor_1_s2_gpa (_dcacheArb_io_requestor_1_s2_gpa), .io_requestor_1_ordered (_dcacheArb_io_requestor_1_ordered), .io_requestor_1_store_pending (_dcacheArb_io_requestor_1_store_pending), .io_requestor_1_perf_acquire (_dcacheArb_io_requestor_1_perf_acquire), .io_requestor_1_perf_release (_dcacheArb_io_requestor_1_perf_release), .io_requestor_1_perf_grant (_dcacheArb_io_requestor_1_perf_grant), .io_requestor_1_perf_tlbMiss (_dcacheArb_io_requestor_1_perf_tlbMiss), .io_requestor_1_perf_blocked (_dcacheArb_io_requestor_1_perf_blocked), .io_requestor_1_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad), .io_requestor_1_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW), .io_requestor_1_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad), .io_requestor_1_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad), .io_requestor_1_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore), .io_mem_req_ready (_dcache_io_cpu_req_ready), // @[Manager.scala:226:61] .io_mem_req_valid (_dcacheArb_io_mem_req_valid), .io_mem_req_bits_addr (_dcacheArb_io_mem_req_bits_addr), .io_mem_req_bits_tag (_dcacheArb_io_mem_req_bits_tag), .io_mem_req_bits_dprv (_dcacheArb_io_mem_req_bits_dprv), .io_mem_req_bits_dv (_dcacheArb_io_mem_req_bits_dv), .io_mem_req_bits_phys (_dcacheArb_io_mem_req_bits_phys), .io_mem_s1_kill (_dcacheArb_io_mem_s1_kill), .io_mem_s1_data_data (_dcacheArb_io_mem_s1_data_data), .io_mem_s1_data_mask (_dcacheArb_io_mem_s1_data_mask), .io_mem_s2_nack (_dcache_io_cpu_s2_nack), // @[Manager.scala:226:61] .io_mem_s2_nack_cause_raw (_dcache_io_cpu_s2_nack_cause_raw), // @[Manager.scala:226:61] .io_mem_s2_uncached (_dcache_io_cpu_s2_uncached), // @[Manager.scala:226:61] .io_mem_s2_paddr (_dcache_io_cpu_s2_paddr), // @[Manager.scala:226:61] .io_mem_resp_valid (_dcache_io_cpu_resp_valid), // @[Manager.scala:226:61] .io_mem_resp_bits_addr (_dcache_io_cpu_resp_bits_addr), // @[Manager.scala:226:61] .io_mem_resp_bits_tag (_dcache_io_cpu_resp_bits_tag), // @[Manager.scala:226:61] .io_mem_resp_bits_cmd (_dcache_io_cpu_resp_bits_cmd), // @[Manager.scala:226:61] .io_mem_resp_bits_size (_dcache_io_cpu_resp_bits_size), // @[Manager.scala:226:61] .io_mem_resp_bits_signed (_dcache_io_cpu_resp_bits_signed), // @[Manager.scala:226:61] .io_mem_resp_bits_dprv (_dcache_io_cpu_resp_bits_dprv), // @[Manager.scala:226:61] .io_mem_resp_bits_dv (_dcache_io_cpu_resp_bits_dv), // @[Manager.scala:226:61] .io_mem_resp_bits_data (_dcache_io_cpu_resp_bits_data), // @[Manager.scala:226:61] .io_mem_resp_bits_mask (_dcache_io_cpu_resp_bits_mask), // @[Manager.scala:226:61] .io_mem_resp_bits_replay (_dcache_io_cpu_resp_bits_replay), // @[Manager.scala:226:61] .io_mem_resp_bits_has_data (_dcache_io_cpu_resp_bits_has_data), // @[Manager.scala:226:61] .io_mem_resp_bits_data_word_bypass (_dcache_io_cpu_resp_bits_data_word_bypass), // @[Manager.scala:226:61] .io_mem_resp_bits_data_raw (_dcache_io_cpu_resp_bits_data_raw), // @[Manager.scala:226:61] .io_mem_resp_bits_store_data (_dcache_io_cpu_resp_bits_store_data), // @[Manager.scala:226:61] .io_mem_replay_next (_dcache_io_cpu_replay_next), // @[Manager.scala:226:61] .io_mem_s2_xcpt_ma_ld (_dcache_io_cpu_s2_xcpt_ma_ld), // @[Manager.scala:226:61] .io_mem_s2_xcpt_ma_st (_dcache_io_cpu_s2_xcpt_ma_st), // @[Manager.scala:226:61] .io_mem_s2_xcpt_pf_ld (_dcache_io_cpu_s2_xcpt_pf_ld), // @[Manager.scala:226:61] .io_mem_s2_xcpt_pf_st (_dcache_io_cpu_s2_xcpt_pf_st), // @[Manager.scala:226:61] .io_mem_s2_xcpt_ae_ld (_dcache_io_cpu_s2_xcpt_ae_ld), // @[Manager.scala:226:61] .io_mem_s2_xcpt_ae_st (_dcache_io_cpu_s2_xcpt_ae_st), // @[Manager.scala:226:61] .io_mem_s2_gpa (_dcache_io_cpu_s2_gpa), // @[Manager.scala:226:61] .io_mem_ordered (_dcache_io_cpu_ordered), // @[Manager.scala:226:61] .io_mem_store_pending (_dcache_io_cpu_store_pending), // @[Manager.scala:226:61] .io_mem_perf_acquire (_dcache_io_cpu_perf_acquire), // @[Manager.scala:226:61] .io_mem_perf_release (_dcache_io_cpu_perf_release), // @[Manager.scala:226:61] .io_mem_perf_grant (_dcache_io_cpu_perf_grant), // @[Manager.scala:226:61] .io_mem_perf_tlbMiss (_dcache_io_cpu_perf_tlbMiss), // @[Manager.scala:226:61] .io_mem_perf_blocked (_dcache_io_cpu_perf_blocked), // @[Manager.scala:226:61] .io_mem_perf_canAcceptStoreThenLoad (_dcache_io_cpu_perf_canAcceptStoreThenLoad), // @[Manager.scala:226:61] .io_mem_perf_canAcceptStoreThenRMW (_dcache_io_cpu_perf_canAcceptStoreThenRMW), // @[Manager.scala:226:61] .io_mem_perf_canAcceptLoadThenLoad (_dcache_io_cpu_perf_canAcceptLoadThenLoad), // @[Manager.scala:226:61] .io_mem_perf_storeBufferEmptyAfterLoad (_dcache_io_cpu_perf_storeBufferEmptyAfterLoad), // @[Manager.scala:226:61] .io_mem_perf_storeBufferEmptyAfterStore (_dcache_io_cpu_perf_storeBufferEmptyAfterStore) // @[Manager.scala:226:61] ); // @[Manager.scala:238:27] PTW_4 ptw ( // @[Manager.scala:243:21] .clock (clock), .reset (reset), .io_requestor_0_req_ready (_ptw_io_requestor_0_req_ready), .io_requestor_0_req_valid (_dcache_io_ptw_req_valid), // @[Manager.scala:226:61] .io_requestor_0_req_bits_bits_addr (_dcache_io_ptw_req_bits_bits_addr), // @[Manager.scala:226:61] .io_requestor_0_req_bits_bits_need_gpa (_dcache_io_ptw_req_bits_bits_need_gpa), // @[Manager.scala:226:61] .io_requestor_0_resp_valid (_ptw_io_requestor_0_resp_valid), .io_requestor_0_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw), .io_requestor_0_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final), .io_requestor_0_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf), .io_requestor_0_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf), .io_requestor_0_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr), .io_requestor_0_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw), .io_requestor_0_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx), .io_requestor_0_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future), .io_requestor_0_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn), .io_requestor_0_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software), .io_requestor_0_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d), .io_requestor_0_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a), .io_requestor_0_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g), .io_requestor_0_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u), .io_requestor_0_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x), .io_requestor_0_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w), .io_requestor_0_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r), .io_requestor_0_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v), .io_requestor_0_resp_bits_level (_ptw_io_requestor_0_resp_bits_level), .io_requestor_0_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous), .io_requestor_0_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid), .io_requestor_0_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits), .io_requestor_0_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte), .io_requestor_0_ptbr_mode (_ptw_io_requestor_0_ptbr_mode), .io_requestor_0_ptbr_asid (_ptw_io_requestor_0_ptbr_asid), .io_requestor_0_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn), .io_requestor_0_status_debug (_ptw_io_requestor_0_status_debug), .io_requestor_0_status_cease (_ptw_io_requestor_0_status_cease), .io_requestor_0_status_wfi (_ptw_io_requestor_0_status_wfi), .io_requestor_0_status_isa (_ptw_io_requestor_0_status_isa), .io_requestor_0_status_dprv (_ptw_io_requestor_0_status_dprv), .io_requestor_0_status_dv (_ptw_io_requestor_0_status_dv), .io_requestor_0_status_prv (_ptw_io_requestor_0_status_prv), .io_requestor_0_status_v (_ptw_io_requestor_0_status_v), .io_requestor_0_status_sd (_ptw_io_requestor_0_status_sd), .io_requestor_0_status_zero2 (_ptw_io_requestor_0_status_zero2), .io_requestor_0_status_mpv (_ptw_io_requestor_0_status_mpv), .io_requestor_0_status_gva (_ptw_io_requestor_0_status_gva), .io_requestor_0_status_mbe (_ptw_io_requestor_0_status_mbe), .io_requestor_0_status_sbe (_ptw_io_requestor_0_status_sbe), .io_requestor_0_status_sxl (_ptw_io_requestor_0_status_sxl), .io_requestor_0_status_uxl (_ptw_io_requestor_0_status_uxl), .io_requestor_0_status_sd_rv32 (_ptw_io_requestor_0_status_sd_rv32), .io_requestor_0_status_zero1 (_ptw_io_requestor_0_status_zero1), .io_requestor_0_status_tsr (_ptw_io_requestor_0_status_tsr), .io_requestor_0_status_tw (_ptw_io_requestor_0_status_tw), .io_requestor_0_status_tvm (_ptw_io_requestor_0_status_tvm), .io_requestor_0_status_mxr (_ptw_io_requestor_0_status_mxr), .io_requestor_0_status_sum (_ptw_io_requestor_0_status_sum), .io_requestor_0_status_mprv (_ptw_io_requestor_0_status_mprv), .io_requestor_0_status_xs (_ptw_io_requestor_0_status_xs), .io_requestor_0_status_fs (_ptw_io_requestor_0_status_fs), .io_requestor_0_status_mpp (_ptw_io_requestor_0_status_mpp), .io_requestor_0_status_vs (_ptw_io_requestor_0_status_vs), .io_requestor_0_status_spp (_ptw_io_requestor_0_status_spp), .io_requestor_0_status_mpie (_ptw_io_requestor_0_status_mpie), .io_requestor_0_status_ube (_ptw_io_requestor_0_status_ube), .io_requestor_0_status_spie (_ptw_io_requestor_0_status_spie), .io_requestor_0_status_upie (_ptw_io_requestor_0_status_upie), .io_requestor_0_status_mie (_ptw_io_requestor_0_status_mie), .io_requestor_0_status_hie (_ptw_io_requestor_0_status_hie), .io_requestor_0_status_sie (_ptw_io_requestor_0_status_sie), .io_requestor_0_status_uie (_ptw_io_requestor_0_status_uie), .io_mem_req_ready (_dcacheArb_io_requestor_0_req_ready), // @[Manager.scala:238:27] .io_mem_req_valid (_ptw_io_mem_req_valid), .io_mem_req_bits_addr (_ptw_io_mem_req_bits_addr), .io_mem_req_bits_dv (_ptw_io_mem_req_bits_dv), .io_mem_s1_kill (_ptw_io_mem_s1_kill), .io_mem_s2_nack (_dcacheArb_io_requestor_0_s2_nack), // @[Manager.scala:238:27] .io_mem_s2_nack_cause_raw (_dcacheArb_io_requestor_0_s2_nack_cause_raw), // @[Manager.scala:238:27] .io_mem_s2_uncached (_dcacheArb_io_requestor_0_s2_uncached), // @[Manager.scala:238:27] .io_mem_s2_paddr (_dcacheArb_io_requestor_0_s2_paddr), // @[Manager.scala:238:27] .io_mem_resp_valid (_dcacheArb_io_requestor_0_resp_valid), // @[Manager.scala:238:27] .io_mem_resp_bits_addr (_dcacheArb_io_requestor_0_resp_bits_addr), // @[Manager.scala:238:27] .io_mem_resp_bits_tag (_dcacheArb_io_requestor_0_resp_bits_tag), // @[Manager.scala:238:27] .io_mem_resp_bits_cmd (_dcacheArb_io_requestor_0_resp_bits_cmd), // @[Manager.scala:238:27] .io_mem_resp_bits_size (_dcacheArb_io_requestor_0_resp_bits_size), // @[Manager.scala:238:27] .io_mem_resp_bits_signed (_dcacheArb_io_requestor_0_resp_bits_signed), // @[Manager.scala:238:27] .io_mem_resp_bits_dprv (_dcacheArb_io_requestor_0_resp_bits_dprv), // @[Manager.scala:238:27] .io_mem_resp_bits_dv (_dcacheArb_io_requestor_0_resp_bits_dv), // @[Manager.scala:238:27] .io_mem_resp_bits_data (_dcacheArb_io_requestor_0_resp_bits_data), // @[Manager.scala:238:27] .io_mem_resp_bits_mask (_dcacheArb_io_requestor_0_resp_bits_mask), // @[Manager.scala:238:27] .io_mem_resp_bits_replay (_dcacheArb_io_requestor_0_resp_bits_replay), // @[Manager.scala:238:27] .io_mem_resp_bits_has_data (_dcacheArb_io_requestor_0_resp_bits_has_data), // @[Manager.scala:238:27] .io_mem_resp_bits_data_word_bypass (_dcacheArb_io_requestor_0_resp_bits_data_word_bypass), // @[Manager.scala:238:27] .io_mem_resp_bits_data_raw (_dcacheArb_io_requestor_0_resp_bits_data_raw), // @[Manager.scala:238:27] .io_mem_resp_bits_store_data (_dcacheArb_io_requestor_0_resp_bits_store_data), // @[Manager.scala:238:27] .io_mem_replay_next (_dcacheArb_io_requestor_0_replay_next), // @[Manager.scala:238:27] .io_mem_s2_xcpt_ma_ld (_dcacheArb_io_requestor_0_s2_xcpt_ma_ld), // @[Manager.scala:238:27] .io_mem_s2_xcpt_ma_st (_dcacheArb_io_requestor_0_s2_xcpt_ma_st), // @[Manager.scala:238:27] .io_mem_s2_xcpt_pf_ld (_dcacheArb_io_requestor_0_s2_xcpt_pf_ld), // @[Manager.scala:238:27] .io_mem_s2_xcpt_pf_st (_dcacheArb_io_requestor_0_s2_xcpt_pf_st), // @[Manager.scala:238:27] .io_mem_s2_xcpt_ae_ld (_dcacheArb_io_requestor_0_s2_xcpt_ae_ld), // @[Manager.scala:238:27] .io_mem_s2_xcpt_ae_st (_dcacheArb_io_requestor_0_s2_xcpt_ae_st), // @[Manager.scala:238:27] .io_mem_s2_gpa (_dcacheArb_io_requestor_0_s2_gpa), // @[Manager.scala:238:27] .io_mem_ordered (_dcacheArb_io_requestor_0_ordered), // @[Manager.scala:238:27] .io_mem_store_pending (_dcacheArb_io_requestor_0_store_pending), // @[Manager.scala:238:27] .io_mem_perf_acquire (_dcacheArb_io_requestor_0_perf_acquire), // @[Manager.scala:238:27] .io_mem_perf_release (_dcacheArb_io_requestor_0_perf_release), // @[Manager.scala:238:27] .io_mem_perf_grant (_dcacheArb_io_requestor_0_perf_grant), // @[Manager.scala:238:27] .io_mem_perf_tlbMiss (_dcacheArb_io_requestor_0_perf_tlbMiss), // @[Manager.scala:238:27] .io_mem_perf_blocked (_dcacheArb_io_requestor_0_perf_blocked), // @[Manager.scala:238:27] .io_mem_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad), // @[Manager.scala:238:27] .io_mem_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW), // @[Manager.scala:238:27] .io_mem_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad), // @[Manager.scala:238:27] .io_mem_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad), // @[Manager.scala:238:27] .io_mem_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore), // @[Manager.scala:238:27] .io_dpath_ptbr_mode (_rerocc_manager_io_ptw_ptbr_mode), // @[Manager.scala:209:34] .io_dpath_ptbr_asid (_rerocc_manager_io_ptw_ptbr_asid), // @[Manager.scala:209:34] .io_dpath_ptbr_ppn (_rerocc_manager_io_ptw_ptbr_ppn), // @[Manager.scala:209:34] .io_dpath_sfence_valid (_rerocc_manager_io_ptw_sfence_valid), // @[Manager.scala:209:34] .io_dpath_status_debug (_rerocc_manager_io_ptw_status_debug), // @[Manager.scala:209:34] .io_dpath_status_cease (_rerocc_manager_io_ptw_status_cease), // @[Manager.scala:209:34] .io_dpath_status_wfi (_rerocc_manager_io_ptw_status_wfi), // @[Manager.scala:209:34] .io_dpath_status_isa (_rerocc_manager_io_ptw_status_isa), // @[Manager.scala:209:34] .io_dpath_status_dprv (_rerocc_manager_io_ptw_status_dprv), // @[Manager.scala:209:34] .io_dpath_status_dv (_rerocc_manager_io_ptw_status_dv), // @[Manager.scala:209:34] .io_dpath_status_prv (_rerocc_manager_io_ptw_status_prv), // @[Manager.scala:209:34] .io_dpath_status_v (_rerocc_manager_io_ptw_status_v), // @[Manager.scala:209:34] .io_dpath_status_sd (_rerocc_manager_io_ptw_status_sd), // @[Manager.scala:209:34] .io_dpath_status_zero2 (_rerocc_manager_io_ptw_status_zero2), // @[Manager.scala:209:34] .io_dpath_status_mpv (_rerocc_manager_io_ptw_status_mpv), // @[Manager.scala:209:34] .io_dpath_status_gva (_rerocc_manager_io_ptw_status_gva), // @[Manager.scala:209:34] .io_dpath_status_mbe (_rerocc_manager_io_ptw_status_mbe), // @[Manager.scala:209:34] .io_dpath_status_sbe (_rerocc_manager_io_ptw_status_sbe), // @[Manager.scala:209:34] .io_dpath_status_sxl (_rerocc_manager_io_ptw_status_sxl), // @[Manager.scala:209:34] .io_dpath_status_uxl (_rerocc_manager_io_ptw_status_uxl), // @[Manager.scala:209:34] .io_dpath_status_sd_rv32 (_rerocc_manager_io_ptw_status_sd_rv32), // @[Manager.scala:209:34] .io_dpath_status_zero1 (_rerocc_manager_io_ptw_status_zero1), // @[Manager.scala:209:34] .io_dpath_status_tsr (_rerocc_manager_io_ptw_status_tsr), // @[Manager.scala:209:34] .io_dpath_status_tw (_rerocc_manager_io_ptw_status_tw), // @[Manager.scala:209:34] .io_dpath_status_tvm (_rerocc_manager_io_ptw_status_tvm), // @[Manager.scala:209:34] .io_dpath_status_mxr (_rerocc_manager_io_ptw_status_mxr), // @[Manager.scala:209:34] .io_dpath_status_sum (_rerocc_manager_io_ptw_status_sum), // @[Manager.scala:209:34] .io_dpath_status_mprv (_rerocc_manager_io_ptw_status_mprv), // @[Manager.scala:209:34] .io_dpath_status_xs (_rerocc_manager_io_ptw_status_xs), // @[Manager.scala:209:34] .io_dpath_status_fs (_rerocc_manager_io_ptw_status_fs), // @[Manager.scala:209:34] .io_dpath_status_mpp (_rerocc_manager_io_ptw_status_mpp), // @[Manager.scala:209:34] .io_dpath_status_vs (_rerocc_manager_io_ptw_status_vs), // @[Manager.scala:209:34] .io_dpath_status_spp (_rerocc_manager_io_ptw_status_spp), // @[Manager.scala:209:34] .io_dpath_status_mpie (_rerocc_manager_io_ptw_status_mpie), // @[Manager.scala:209:34] .io_dpath_status_ube (_rerocc_manager_io_ptw_status_ube), // @[Manager.scala:209:34] .io_dpath_status_spie (_rerocc_manager_io_ptw_status_spie), // @[Manager.scala:209:34] .io_dpath_status_upie (_rerocc_manager_io_ptw_status_upie), // @[Manager.scala:209:34] .io_dpath_status_mie (_rerocc_manager_io_ptw_status_mie), // @[Manager.scala:209:34] .io_dpath_status_hie (_rerocc_manager_io_ptw_status_hie), // @[Manager.scala:209:34] .io_dpath_status_sie (_rerocc_manager_io_ptw_status_sie), // @[Manager.scala:209:34] .io_dpath_status_uie (_rerocc_manager_io_ptw_status_uie), // @[Manager.scala:209:34] .io_dpath_perf_pte_miss (_ptw_io_dpath_perf_pte_miss), .io_dpath_clock_enabled (_ptw_io_dpath_clock_enabled) ); // @[Manager.scala:243:21] SimpleHellaCacheIF_4 dcIF ( // @[Manager.scala:255:22] .clock (clock), .reset (reset), .io_requestor_req_ready (accumulator_io_mem_req_ready), .io_requestor_req_valid (accumulator_io_mem_req_valid), // @[LazyRoCC.scala:122:7] .io_requestor_req_bits_addr (accumulator_io_mem_req_bits_addr), // @[LazyRoCC.scala:122:7] .io_requestor_req_bits_tag (accumulator_io_mem_req_bits_tag), // @[LazyRoCC.scala:122:7] .io_requestor_req_bits_dprv (accumulator_io_mem_req_bits_dprv), // @[LazyRoCC.scala:122:7] .io_requestor_req_bits_dv (accumulator_io_mem_req_bits_dv), // @[LazyRoCC.scala:122:7] .io_requestor_resp_valid (accumulator_io_mem_resp_valid), .io_requestor_resp_bits_addr (accumulator_io_mem_resp_bits_addr), .io_requestor_resp_bits_tag (accumulator_io_mem_resp_bits_tag), .io_requestor_resp_bits_cmd (accumulator_io_mem_resp_bits_cmd), .io_requestor_resp_bits_size (accumulator_io_mem_resp_bits_size), .io_requestor_resp_bits_signed (accumulator_io_mem_resp_bits_signed), .io_requestor_resp_bits_dprv (accumulator_io_mem_resp_bits_dprv), .io_requestor_resp_bits_dv (accumulator_io_mem_resp_bits_dv), .io_requestor_resp_bits_data (accumulator_io_mem_resp_bits_data), .io_requestor_resp_bits_mask (accumulator_io_mem_resp_bits_mask), .io_requestor_resp_bits_replay (accumulator_io_mem_resp_bits_replay), .io_requestor_resp_bits_has_data (accumulator_io_mem_resp_bits_has_data), .io_requestor_resp_bits_data_word_bypass (accumulator_io_mem_resp_bits_data_word_bypass), .io_requestor_resp_bits_data_raw (accumulator_io_mem_resp_bits_data_raw), .io_requestor_resp_bits_store_data (accumulator_io_mem_resp_bits_store_data), .io_cache_req_ready (_dcacheArb_io_requestor_1_req_ready), // @[Manager.scala:238:27] .io_cache_req_valid (_dcIF_io_cache_req_valid), .io_cache_req_bits_addr (_dcIF_io_cache_req_bits_addr), .io_cache_req_bits_tag (_dcIF_io_cache_req_bits_tag), .io_cache_req_bits_dprv (_dcIF_io_cache_req_bits_dprv), .io_cache_req_bits_dv (_dcIF_io_cache_req_bits_dv), .io_cache_s1_data_data (_dcIF_io_cache_s1_data_data), .io_cache_s1_data_mask (_dcIF_io_cache_s1_data_mask), .io_cache_s2_nack (_dcacheArb_io_requestor_1_s2_nack), // @[Manager.scala:238:27] .io_cache_s2_nack_cause_raw (_dcacheArb_io_requestor_1_s2_nack_cause_raw), // @[Manager.scala:238:27] .io_cache_s2_uncached (_dcacheArb_io_requestor_1_s2_uncached), // @[Manager.scala:238:27] .io_cache_s2_paddr (_dcacheArb_io_requestor_1_s2_paddr), // @[Manager.scala:238:27] .io_cache_resp_valid (_dcacheArb_io_requestor_1_resp_valid), // @[Manager.scala:238:27] .io_cache_resp_bits_addr (_dcacheArb_io_requestor_1_resp_bits_addr), // @[Manager.scala:238:27] .io_cache_resp_bits_tag (_dcacheArb_io_requestor_1_resp_bits_tag), // @[Manager.scala:238:27] .io_cache_resp_bits_cmd (_dcacheArb_io_requestor_1_resp_bits_cmd), // @[Manager.scala:238:27] .io_cache_resp_bits_size (_dcacheArb_io_requestor_1_resp_bits_size), // @[Manager.scala:238:27] .io_cache_resp_bits_signed (_dcacheArb_io_requestor_1_resp_bits_signed), // @[Manager.scala:238:27] .io_cache_resp_bits_dprv (_dcacheArb_io_requestor_1_resp_bits_dprv), // @[Manager.scala:238:27] .io_cache_resp_bits_dv (_dcacheArb_io_requestor_1_resp_bits_dv), // @[Manager.scala:238:27] .io_cache_resp_bits_data (_dcacheArb_io_requestor_1_resp_bits_data), // @[Manager.scala:238:27] .io_cache_resp_bits_mask (_dcacheArb_io_requestor_1_resp_bits_mask), // @[Manager.scala:238:27] .io_cache_resp_bits_replay (_dcacheArb_io_requestor_1_resp_bits_replay), // @[Manager.scala:238:27] .io_cache_resp_bits_has_data (_dcacheArb_io_requestor_1_resp_bits_has_data), // @[Manager.scala:238:27] .io_cache_resp_bits_data_word_bypass (_dcacheArb_io_requestor_1_resp_bits_data_word_bypass), // @[Manager.scala:238:27] .io_cache_resp_bits_data_raw (_dcacheArb_io_requestor_1_resp_bits_data_raw), // @[Manager.scala:238:27] .io_cache_resp_bits_store_data (_dcacheArb_io_requestor_1_resp_bits_store_data), // @[Manager.scala:238:27] .io_cache_replay_next (_dcacheArb_io_requestor_1_replay_next), // @[Manager.scala:238:27] .io_cache_s2_xcpt_ma_ld (_dcacheArb_io_requestor_1_s2_xcpt_ma_ld), // @[Manager.scala:238:27] .io_cache_s2_xcpt_ma_st (_dcacheArb_io_requestor_1_s2_xcpt_ma_st), // @[Manager.scala:238:27] .io_cache_s2_xcpt_pf_ld (_dcacheArb_io_requestor_1_s2_xcpt_pf_ld), // @[Manager.scala:238:27] .io_cache_s2_xcpt_pf_st (_dcacheArb_io_requestor_1_s2_xcpt_pf_st), // @[Manager.scala:238:27] .io_cache_s2_xcpt_ae_ld (_dcacheArb_io_requestor_1_s2_xcpt_ae_ld), // @[Manager.scala:238:27] .io_cache_s2_xcpt_ae_st (_dcacheArb_io_requestor_1_s2_xcpt_ae_st), // @[Manager.scala:238:27] .io_cache_s2_gpa (_dcacheArb_io_requestor_1_s2_gpa), // @[Manager.scala:238:27] .io_cache_ordered (_dcacheArb_io_requestor_1_ordered), // @[Manager.scala:238:27] .io_cache_store_pending (_dcacheArb_io_requestor_1_store_pending), // @[Manager.scala:238:27] .io_cache_perf_acquire (_dcacheArb_io_requestor_1_perf_acquire), // @[Manager.scala:238:27] .io_cache_perf_release (_dcacheArb_io_requestor_1_perf_release), // @[Manager.scala:238:27] .io_cache_perf_grant (_dcacheArb_io_requestor_1_perf_grant), // @[Manager.scala:238:27] .io_cache_perf_tlbMiss (_dcacheArb_io_requestor_1_perf_tlbMiss), // @[Manager.scala:238:27] .io_cache_perf_blocked (_dcacheArb_io_requestor_1_perf_blocked), // @[Manager.scala:238:27] .io_cache_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad), // @[Manager.scala:238:27] .io_cache_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW), // @[Manager.scala:238:27] .io_cache_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad), // @[Manager.scala:238:27] .io_cache_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad), // @[Manager.scala:238:27] .io_cache_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore) // @[Manager.scala:238:27] ); // @[Manager.scala:255:22] assign auto_ctrl_ctrl_in_a_ready = auto_ctrl_ctrl_in_a_ready_0; // @[Manager.scala:237:34] assign auto_ctrl_ctrl_in_d_valid = auto_ctrl_ctrl_in_d_valid_0; // @[Manager.scala:237:34] assign auto_ctrl_ctrl_in_d_bits_opcode = auto_ctrl_ctrl_in_d_bits_opcode_0; // @[Manager.scala:237:34] assign auto_ctrl_ctrl_in_d_bits_size = auto_ctrl_ctrl_in_d_bits_size_0; // @[Manager.scala:237:34] assign auto_ctrl_ctrl_in_d_bits_source = auto_ctrl_ctrl_in_d_bits_source_0; // @[Manager.scala:237:34] assign auto_ctrl_ctrl_in_d_bits_data = auto_ctrl_ctrl_in_d_bits_data_0; // @[Manager.scala:237:34] assign auto_buffer_out_a_valid = auto_buffer_out_a_valid_0; // @[Manager.scala:237:34] assign auto_buffer_out_a_bits_opcode = auto_buffer_out_a_bits_opcode_0; // @[Manager.scala:237:34] assign auto_buffer_out_a_bits_param = auto_buffer_out_a_bits_param_0; // @[Manager.scala:237:34] assign auto_buffer_out_a_bits_size = auto_buffer_out_a_bits_size_0; // @[Manager.scala:237:34] assign auto_buffer_out_a_bits_source = auto_buffer_out_a_bits_source_0; // @[Manager.scala:237:34] assign auto_buffer_out_a_bits_address = auto_buffer_out_a_bits_address_0; // @[Manager.scala:237:34] assign auto_buffer_out_a_bits_mask = auto_buffer_out_a_bits_mask_0; // @[Manager.scala:237:34] assign auto_buffer_out_a_bits_data = auto_buffer_out_a_bits_data_0; // @[Manager.scala:237:34] assign auto_buffer_out_a_bits_corrupt = auto_buffer_out_a_bits_corrupt_0; // @[Manager.scala:237:34] assign auto_buffer_out_b_ready = auto_buffer_out_b_ready_0; // @[Manager.scala:237:34] assign auto_buffer_out_c_valid = auto_buffer_out_c_valid_0; // @[Manager.scala:237:34] assign auto_buffer_out_c_bits_opcode = auto_buffer_out_c_bits_opcode_0; // @[Manager.scala:237:34] assign auto_buffer_out_c_bits_param = auto_buffer_out_c_bits_param_0; // @[Manager.scala:237:34] assign auto_buffer_out_c_bits_size = auto_buffer_out_c_bits_size_0; // @[Manager.scala:237:34] assign auto_buffer_out_c_bits_source = auto_buffer_out_c_bits_source_0; // @[Manager.scala:237:34] assign auto_buffer_out_c_bits_address = auto_buffer_out_c_bits_address_0; // @[Manager.scala:237:34] assign auto_buffer_out_c_bits_data = auto_buffer_out_c_bits_data_0; // @[Manager.scala:237:34] assign auto_buffer_out_c_bits_corrupt = auto_buffer_out_c_bits_corrupt_0; // @[Manager.scala:237:34] assign auto_buffer_out_d_ready = auto_buffer_out_d_ready_0; // @[Manager.scala:237:34] assign auto_buffer_out_e_valid = auto_buffer_out_e_valid_0; // @[Manager.scala:237:34] assign auto_buffer_out_e_bits_sink = auto_buffer_out_e_bits_sink_0; // @[Manager.scala:237:34] assign auto_re_ro_cc_in_req_ready = auto_re_ro_cc_in_req_ready_0; // @[Manager.scala:237:34] assign auto_re_ro_cc_in_resp_valid = auto_re_ro_cc_in_resp_valid_0; // @[Manager.scala:237:34] assign auto_re_ro_cc_in_resp_bits_opcode = auto_re_ro_cc_in_resp_bits_opcode_0; // @[Manager.scala:237:34] assign auto_re_ro_cc_in_resp_bits_client_id = auto_re_ro_cc_in_resp_bits_client_id_0; // @[Manager.scala:237:34] assign auto_re_ro_cc_in_resp_bits_manager_id = auto_re_ro_cc_in_resp_bits_manager_id_0; // @[Manager.scala:237:34] assign auto_re_ro_cc_in_resp_bits_data = auto_re_ro_cc_in_resp_bits_data_0; // @[Manager.scala:237:34] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_182( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_326 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File ZstdCompressorMemWriter.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.{Printable, VecInit} import freechips.rocketchip.tile._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket.{TLBConfig} import freechips.rocketchip.util.DecoupledHelper import freechips.rocketchip.rocket.constants.MemoryOpConstants import freechips.rocketchip.tilelink._ // class WriterBundle extends Bundle { // val data = UInt(128.W) // val validbytes = UInt(6.W) // val end_of_message = Bool() // } class ZstdCompressorMemWriter(val circularQueDepth: Int = 16, val writeCmpFlag: Boolean = true, val printinfo: String = "zcmw") (implicit p: Parameters) extends ZstdCompressorModule with MemoryOpConstants { val io = IO(new Bundle { val memwrites_in = Flipped(Decoupled(new WriterBundle)) val l2io = new L2MemHelperBundle val dest_info = Flipped((Decoupled(new DstWithValInfo))) val bufs_completed = Output(UInt(64.W)) val no_writes_inflight = Output(Bool()) }) val incoming_writes_Q = Module(new Queue(new WriterBundle, queDepth)) incoming_writes_Q.io.enq <> io.memwrites_in val dest_info_Q = Module(new Queue(new DstWithValInfo, queDepth)) dest_info_Q.io.enq <> io.dest_info val decompress_dest_last_fire = RegNext(dest_info_Q.io.deq.fire) val decompress_dest_last_valid = RegNext(dest_info_Q.io.deq.valid) val decompress_dest_printhelp = dest_info_Q.io.deq.valid && (decompress_dest_last_fire \|\| (!decompress_dest_last_valid)) when (decompress_dest_printhelp) { CompressAccelLogger.logInfo("[config-memwriter] got dest info op: 0x%x, cmpflag 0x%x\n", dest_info_Q.io.deq.bits.op, dest_info_Q.io.deq.bits.cmpflag) } val buf_lens_Q = Module(new Queue(UInt(64.W), 10)) when (buf_lens_Q.io.enq.fire) { CompressAccelLogger.logInfo("[" + printinfo + "] enqueued buf len: %d\n", buf_lens_Q.io.enq.bits) } val buf_len_tracker = RegInit(0.U(64.W)) when (incoming_writes_Q.io.deq.fire) { when (incoming_writes_Q.io.deq.bits.end_of_message) { buf_len_tracker := 0.U } .otherwise { buf_len_tracker := buf_len_tracker +& incoming_writes_Q.io.deq.bits.validbytes } } when (incoming_writes_Q.io.deq.fire) { CompressAccelLogger.logInfo("[" + printinfo + "] dat: 0x%x, bytes: 0x%x, EOM: %d\n", incoming_writes_Q.io.deq.bits.data, incoming_writes_Q.io.deq.bits.validbytes, incoming_writes_Q.io.deq.bits.end_of_message ) } val NUM_QUEUES = 32 val QUEUE_DEPTHS = circularQueDepth val write_start_index = RegInit(0.U(log2Up(NUM_QUEUES+1).W)) val mem_resp_queues = Seq.fill(NUM_QUEUES)(Module(new Queue(UInt(8.W), QUEUE_DEPTHS)).io) val len_to_write = incoming_writes_Q.io.deq.bits.validbytes for ( queueno <- 0 until NUM_QUEUES ) { mem_resp_queues(queueno).enq.bits := 0.U } for ( queueno <- 0 until NUM_QUEUES ) { val idx = (write_start_index +& queueno.U) % NUM_QUEUES.U for (j <- 0 until NUM_QUEUES) { when (j.U === idx) { mem_resp_queues(j).enq.bits := (incoming_writes_Q.io.deq.bits.data >> (queueno.U << 3))(7, 0) } } } val wrap_len_index_wide = write_start_index +& len_to_write val wrap_len_index_end = wrap_len_index_wide % NUM_QUEUES.U val wrapped = wrap_len_index_wide >= NUM_QUEUES.U val all_queues_ready = mem_resp_queues.map(_.enq.ready).reduce(_ && _) val end_of_buf = incoming_writes_Q.io.deq.bits.end_of_message val account_for_buf_lens_Q = (!end_of_buf) \|\| (end_of_buf && buf_lens_Q.io.enq.ready) val input_fire_allqueues = DecoupledHelper( incoming_writes_Q.io.deq.valid, all_queues_ready, account_for_buf_lens_Q ) buf_lens_Q.io.enq.valid := input_fire_allqueues.fire(account_for_buf_lens_Q) && end_of_buf buf_lens_Q.io.enq.bits := buf_len_tracker +& incoming_writes_Q.io.deq.bits.validbytes incoming_writes_Q.io.deq.ready := input_fire_allqueues.fire(incoming_writes_Q.io.deq.valid) // when (input_fire_allqueues.fire && !end_of_buf) { when (input_fire_allqueues.fire) { write_start_index := wrap_len_index_end } for ( queueno <- 0 until NUM_QUEUES ) { val use_this_queue = Mux(wrapped, (queueno.U >= write_start_index) \|\| (queueno.U < wrap_len_index_end), (queueno.U >= write_start_index) && (queueno.U < wrap_len_index_end) ) mem_resp_queues(queueno).enq.valid := input_fire_allqueues.fire && use_this_queue } for ( queueno <- 0 until NUM_QUEUES ) { when (mem_resp_queues(queueno).deq.valid) { CompressAccelLogger.logInfo("qi%d,0x%x\n", queueno.U, mem_resp_queues(queueno).deq.bits) } } val read_start_index = RegInit(0.U(log2Up(NUM_QUEUES+1).W)) val remapVecData = Wire(Vec(NUM_QUEUES, UInt(8.W))) val remapVecValids = Wire(Vec(NUM_QUEUES, Bool())) val remapVecReadys = Wire(Vec(NUM_QUEUES, Bool())) for (queueno <- 0 until NUM_QUEUES) { remapVecData(queueno) := 0.U remapVecValids(queueno) := false.B mem_resp_queues(queueno).deq.ready := false.B } for (queueno <- 0 until NUM_QUEUES) { val remapindex = (queueno.U +& read_start_index) % NUM_QUEUES.U for (j <- 0 until NUM_QUEUES) { when (j.U === remapindex) { remapVecData(queueno) := mem_resp_queues(j).deq.bits remapVecValids(queueno) := mem_resp_queues(j).deq.valid mem_resp_queues(j).deq.ready := remapVecReadys(queueno) } } } val count_valids = remapVecValids.map(_.asUInt).reduce(_ +& _) val backend_bytes_written = RegInit(0.U(64.W)) val backend_next_write_addr = dest_info_Q.io.deq.bits.op + backend_bytes_written val throttle_end = Mux(buf_lens_Q.io.deq.valid, buf_lens_Q.io.deq.bits - backend_bytes_written, 32.U) val throttle_end_writeable = Mux(throttle_end >= 32.U, 32.U, Mux(throttle_end(4), 16.U, Mux(throttle_end(3), 8.U, Mux(throttle_end(2), 4.U, Mux(throttle_end(1), 2.U, Mux(throttle_end(0), 1.U, 0.U)))))) val throttle_end_writeable_log2 = Mux(throttle_end >= 32.U, 5.U, Mux(throttle_end(4), 4.U, Mux(throttle_end(3), 3.U, Mux(throttle_end(2), 2.U, Mux(throttle_end(1), 1.U, Mux(throttle_end(0), 0.U, 0.U)))))) val ptr_align_max_bytes_writeable = Mux(backend_next_write_addr(0), 1.U, Mux(backend_next_write_addr(1), 2.U, Mux(backend_next_write_addr(2), 4.U, Mux(backend_next_write_addr(3), 8.U, Mux(backend_next_write_addr(4), 16.U, 32.U))))) val ptr_align_max_bytes_writeable_log2 = Mux(backend_next_write_addr(0), 0.U, Mux(backend_next_write_addr(1), 1.U, Mux(backend_next_write_addr(2), 2.U, Mux(backend_next_write_addr(3), 3.U, Mux(backend_next_write_addr(4), 4.U, 5.U))))) val count_valids_largest_aligned = Mux(count_valids(5), 32.U, Mux(count_valids(4), 16.U, Mux(count_valids(3), 8.U, Mux(count_valids(2), 4.U, Mux(count_valids(1), 2.U, Mux(count_valids(0), 1.U, 0.U)))))) val count_valids_largest_aligned_log2 = Mux(count_valids(5), 5.U, Mux(count_valids(4), 4.U, Mux(count_valids(3), 3.U, Mux(count_valids(2), 2.U, Mux(count_valids(1), 1.U, Mux(count_valids(0), 0.U, 0.U)))))) // TODO: when choosing bytes_to_write, account for amount left in this buf val bytes_to_write = Mux( ptr_align_max_bytes_writeable < count_valids_largest_aligned, Mux(ptr_align_max_bytes_writeable < throttle_end_writeable, ptr_align_max_bytes_writeable, throttle_end_writeable), Mux(count_valids_largest_aligned < throttle_end_writeable, count_valids_largest_aligned, throttle_end_writeable) ) val remapped_write_data = Cat(remapVecData.reverse) // >> ((NUM_QUEUES.U - bytes_to_write) << 3) val enough_data = bytes_to_write =/= 0.U val bytes_to_write_log2 = Mux( ptr_align_max_bytes_writeable_log2 < count_valids_largest_aligned_log2, Mux(ptr_align_max_bytes_writeable_log2 < throttle_end_writeable_log2, ptr_align_max_bytes_writeable_log2, throttle_end_writeable_log2), Mux(count_valids_largest_aligned_log2 < throttle_end_writeable_log2, count_valids_largest_aligned_log2, throttle_end_writeable_log2) ) val write_ptr_override = buf_lens_Q.io.deq.valid && (buf_lens_Q.io.deq.bits === backend_bytes_written) val mem_write_fire = DecoupledHelper( io.l2io.req.ready, enough_data, !write_ptr_override, dest_info_Q.io.deq.valid ) val bool_ptr_write_fire = DecoupledHelper( io.l2io.req.ready, buf_lens_Q.io.deq.valid, buf_lens_Q.io.deq.bits === backend_bytes_written, dest_info_Q.io.deq.valid ) for (queueno <- 0 until NUM_QUEUES) { remapVecReadys(queueno) := (queueno.U < bytes_to_write) && mem_write_fire.fire } when (mem_write_fire.fire) { read_start_index := (read_start_index +& bytes_to_write) % NUM_QUEUES.U backend_bytes_written := backend_bytes_written + bytes_to_write CompressAccelLogger.logInfo("[" + printinfo + "] writefire: addr: 0x%x, data 0x%x, size %d\n", io.l2io.req.bits.addr, io.l2io.req.bits.data, io.l2io.req.bits.size ) } if (writeCmpFlag) { io.l2io.req.valid := mem_write_fire.fire(io.l2io.req.ready) \|\| bool_ptr_write_fire.fire(io.l2io.req.ready) } else { io.l2io.req.valid := mem_write_fire.fire(io.l2io.req.ready) } io.l2io.req.bits.size := Mux(write_ptr_override, 2.U, bytes_to_write_log2) io.l2io.req.bits.addr := Mux(write_ptr_override, dest_info_Q.io.deq.bits.cmpflag, backend_next_write_addr) io.l2io.req.bits.data := Mux(write_ptr_override, dest_info_Q.io.deq.bits.cmpval, remapped_write_data) io.l2io.req.bits.cmd := M_XWR buf_lens_Q.io.deq.ready := bool_ptr_write_fire.fire(buf_lens_Q.io.deq.valid) dest_info_Q.io.deq.ready := bool_ptr_write_fire.fire(dest_info_Q.io.deq.valid) val bufs_completed = RegInit(0.U(64.W)) io.bufs_completed := bufs_completed io.l2io.resp.ready := true.B io.no_writes_inflight := io.l2io.no_memops_inflight when (bool_ptr_write_fire.fire) { bufs_completed := bufs_completed + 1.U backend_bytes_written := 0.U CompressAccelLogger.logInfo("[" + printinfo + "] write cmpflag addr: 0x%x, write ptr val 0x%x\n", dest_info_Q.io.deq.bits.cmpflag, dest_info_Q.io.deq.bits.cmpval) } when (count_valids =/= 0.U) { CompressAccelLogger.logInfo("[" + printinfo + "] write_start_index %d, backend_bytes_written %d, count_valids %d, ptr_align_max_bytes_writeable %d, bytes_to_write %d, bytes_to_write_log2 %d\n", read_start_index, backend_bytes_written, count_valids, ptr_align_max_bytes_writeable, bytes_to_write, bytes_to_write_log2 ) } } File Util.scala: package compressacc import chisel3._ import chisel3.util._ import chisel3.{Printable} import freechips.rocketchip.tile._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.rocket.{TLBConfig} import freechips.rocketchip.util.DecoupledHelper import freechips.rocketchip.rocket.constants.MemoryOpConstants object CompressAccelLogger { def logInfo(format: String, args: Bits)(implicit p: Parameters) { val loginfo_cycles = RegInit(0.U(64.W)) loginfo_cycles := loginfo_cycles + 1.U printf("cy: %d, ", loginfo_cycles) printf(Printable.pack(format, args:_)) } def logCritical(format: String, args: Bits)(implicit p: Parameters) { val loginfo_cycles = RegInit(0.U(64.W)) loginfo_cycles := loginfo_cycles + 1.U if (p(CompressAccelPrintfEnable)) { printf(midas.targetutils.SynthesizePrintf("cy: %d, ", loginfo_cycles)) printf(midas.targetutils.SynthesizePrintf(format, args:_)) } else { printf("cy: %d, ", loginfo_cycles) printf(Printable.pack(format, args:_)) } } def logWaveStyle(format: String, args: Bits)(implicit p: Parameters) { } } object CompressAccelParams { }	module ZstdCompressorMemWriter_2( // @[ZstdCompressorMemWriter.scala:23:7] input clock, // @[ZstdCompressorMemWriter.scala:23:7] input reset, // @[ZstdCompressorMemWriter.scala:23:7] output io_memwrites_in_ready, // @[ZstdCompressorMemWriter.scala:26:14] input io_memwrites_in_valid, // @[ZstdCompressorMemWriter.scala:26:14] input [255:0] io_memwrites_in_bits_data, // @[ZstdCompressorMemWriter.scala:26:14] input [5:0] io_memwrites_in_bits_validbytes, // @[ZstdCompressorMemWriter.scala:26:14] input io_memwrites_in_bits_end_of_message, // @[ZstdCompressorMemWriter.scala:26:14] input io_l2io_req_ready, // @[ZstdCompressorMemWriter.scala:26:14] output io_l2io_req_valid, // @[ZstdCompressorMemWriter.scala:26:14] output [63:0] io_l2io_req_bits_addr, // @[ZstdCompressorMemWriter.scala:26:14] output [2:0] io_l2io_req_bits_size, // @[ZstdCompressorMemWriter.scala:26:14] output [255:0] io_l2io_req_bits_data, // @[ZstdCompressorMemWriter.scala:26:14] input io_l2io_resp_valid, // @[ZstdCompressorMemWriter.scala:26:14] input [255:0] io_l2io_resp_bits_data, // @[ZstdCompressorMemWriter.scala:26:14] input io_l2io_no_memops_inflight, // @[ZstdCompressorMemWriter.scala:26:14] output io_dest_info_ready, // @[ZstdCompressorMemWriter.scala:26:14] input io_dest_info_valid, // @[ZstdCompressorMemWriter.scala:26:14] input [63:0] io_dest_info_bits_op, // @[ZstdCompressorMemWriter.scala:26:14] input [63:0] io_dest_info_bits_cmpflag, // @[ZstdCompressorMemWriter.scala:26:14] input [63:0] io_dest_info_bits_cmpval, // @[ZstdCompressorMemWriter.scala:26:14] output [63:0] io_bufs_completed, // @[ZstdCompressorMemWriter.scala:26:14] output io_no_writes_inflight // @[ZstdCompressorMemWriter.scala:26:14] ); wire _Queue16_UInt8_31_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_31_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_31_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_30_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_30_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_30_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_29_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_29_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_29_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_28_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_28_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_28_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_27_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_27_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_27_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_26_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_26_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_26_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_25_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_25_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_25_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_24_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_24_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_24_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_23_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_23_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_23_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_22_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_22_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_22_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_21_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_21_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_21_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_20_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_20_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_20_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_19_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_19_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_19_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_18_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_18_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_18_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_17_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_17_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_17_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_16_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_16_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_16_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_15_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_15_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_15_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_14_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_14_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_14_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_13_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_13_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_13_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_12_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_12_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_12_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_11_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_11_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_11_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_10_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_10_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_10_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_9_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_9_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_9_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_8_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_8_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_7_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_7_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_7_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_6_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_6_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_6_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_5_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_5_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_5_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_4_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_4_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_4_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_3_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_3_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_3_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_2_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_2_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_2_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_1_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_1_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_1_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52] wire _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52] wire [7:0] _Queue16_UInt8_io_deq_bits; // @[ZstdCompressorMemWriter.scala:77:52] wire _buf_lens_Q_io_enq_ready; // @[ZstdCompressorMemWriter.scala:52:26] wire _buf_lens_Q_io_deq_valid; // @[ZstdCompressorMemWriter.scala:52:26] wire [63:0] _buf_lens_Q_io_deq_bits; // @[ZstdCompressorMemWriter.scala:52:26] wire _dest_info_Q_io_deq_valid; // @[ZstdCompressorMemWriter.scala:39:27] wire [63:0] _dest_info_Q_io_deq_bits_op; // @[ZstdCompressorMemWriter.scala:39:27] wire [63:0] _dest_info_Q_io_deq_bits_cmpflag; // @[ZstdCompressorMemWriter.scala:39:27] wire [63:0] _dest_info_Q_io_deq_bits_cmpval; // @[ZstdCompressorMemWriter.scala:39:27] wire _incoming_writes_Q_io_deq_valid; // @[ZstdCompressorMemWriter.scala:35:33] wire [255:0] _incoming_writes_Q_io_deq_bits_data; // @[ZstdCompressorMemWriter.scala:35:33] wire [5:0] _incoming_writes_Q_io_deq_bits_validbytes; // @[ZstdCompressorMemWriter.scala:35:33] wire _incoming_writes_Q_io_deq_bits_end_of_message; // @[ZstdCompressorMemWriter.scala:35:33] wire io_memwrites_in_valid_0 = io_memwrites_in_valid; // @[ZstdCompressorMemWriter.scala:23:7] wire [255:0] io_memwrites_in_bits_data_0 = io_memwrites_in_bits_data; // @[ZstdCompressorMemWriter.scala:23:7] wire [5:0] io_memwrites_in_bits_validbytes_0 = io_memwrites_in_bits_validbytes; // @[ZstdCompressorMemWriter.scala:23:7] wire io_memwrites_in_bits_end_of_message_0 = io_memwrites_in_bits_end_of_message; // @[ZstdCompressorMemWriter.scala:23:7] wire io_l2io_req_ready_0 = io_l2io_req_ready; // @[ZstdCompressorMemWriter.scala:23:7] wire io_l2io_resp_valid_0 = io_l2io_resp_valid; // @[ZstdCompressorMemWriter.scala:23:7] wire [255:0] io_l2io_resp_bits_data_0 = io_l2io_resp_bits_data; // @[ZstdCompressorMemWriter.scala:23:7] wire io_l2io_no_memops_inflight_0 = io_l2io_no_memops_inflight; // @[ZstdCompressorMemWriter.scala:23:7] wire io_dest_info_valid_0 = io_dest_info_valid; // @[ZstdCompressorMemWriter.scala:23:7] wire [63:0] io_dest_info_bits_op_0 = io_dest_info_bits_op; // @[ZstdCompressorMemWriter.scala:23:7] wire [63:0] io_dest_info_bits_cmpflag_0 = io_dest_info_bits_cmpflag; // @[ZstdCompressorMemWriter.scala:23:7] wire [63:0] io_dest_info_bits_cmpval_0 = io_dest_info_bits_cmpval; // @[ZstdCompressorMemWriter.scala:23:7] wire io_l2io_req_bits_cmd = 1'h1; // @[ZstdCompressorMemWriter.scala:23:7] wire io_l2io_resp_ready = 1'h1; // @[ZstdCompressorMemWriter.scala:23:7] wire _throttle_end_writeable_log2_T_6 = 1'h0; // @[ZstdCompressorMemWriter.scala:187:50] wire _count_valids_largest_aligned_log2_T_6 = 1'h0; // @[ZstdCompressorMemWriter.scala:218:56] wire _io_l2io_req_valid_T_1; // @[Misc.scala:26:53] wire [63:0] _io_l2io_req_bits_addr_T; // @[ZstdCompressorMemWriter.scala:283:31] wire [2:0] _io_l2io_req_bits_size_T; // @[ZstdCompressorMemWriter.scala:282:31] wire [255:0] _io_l2io_req_bits_data_T; // @[ZstdCompressorMemWriter.scala:284:31] wire io_no_writes_inflight_0 = io_l2io_no_memops_inflight_0; // @[ZstdCompressorMemWriter.scala:23:7] wire io_memwrites_in_ready_0; // @[ZstdCompressorMemWriter.scala:23:7] wire [63:0] io_l2io_req_bits_addr_0; // @[ZstdCompressorMemWriter.scala:23:7] wire [2:0] io_l2io_req_bits_size_0; // @[ZstdCompressorMemWriter.scala:23:7] wire [255:0] io_l2io_req_bits_data_0; // @[ZstdCompressorMemWriter.scala:23:7] wire io_l2io_req_valid_0; // @[ZstdCompressorMemWriter.scala:23:7] wire io_dest_info_ready_0; // @[ZstdCompressorMemWriter.scala:23:7] wire [63:0] io_bufs_completed_0; // @[ZstdCompressorMemWriter.scala:23:7] wire _dest_info_Q_io_deq_ready_T_1; // @[Misc.scala:26:53] wire _decompress_dest_last_fire_T = _dest_info_Q_io_deq_ready_T_1 & _dest_info_Q_io_deq_valid; // @[Decoupled.scala:51:35] reg decompress_dest_last_fire; // @[ZstdCompressorMemWriter.scala:42:42] reg decompress_dest_last_valid; // @[ZstdCompressorMemWriter.scala:43:43] wire _decompress_dest_printhelp_T = ~decompress_dest_last_valid; // @[ZstdCompressorMemWriter.scala:43:43, :44:94] wire _decompress_dest_printhelp_T_1 = decompress_dest_last_fire \| _decompress_dest_printhelp_T; // @[ZstdCompressorMemWriter.scala:42:42, :44:{90,94}] wire decompress_dest_printhelp = _dest_info_Q_io_deq_valid & _decompress_dest_printhelp_T_1; // @[ZstdCompressorMemWriter.scala:39:27, :44:{60,90}] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38] reg [63:0] buf_len_tracker; // @[ZstdCompressorMemWriter.scala:57:32] wire _incoming_writes_Q_io_deq_ready_T; // @[Misc.scala:26:53] wire _T_10 = _incoming_writes_Q_io_deq_ready_T & _incoming_writes_Q_io_deq_valid; // @[Decoupled.scala:51:35] wire [64:0] _GEN = {1'h0, buf_len_tracker} + {59'h0, _incoming_writes_Q_io_deq_bits_validbytes}; // @[ZstdCompressorMemWriter.scala:35:33, :57:32, :62:42] wire [64:0] _buf_len_tracker_T; // @[ZstdCompressorMemWriter.scala:62:42] assign _buf_len_tracker_T = _GEN; // @[ZstdCompressorMemWriter.scala:62:42] wire [64:0] _buf_lens_Q_io_enq_bits_T; // @[ZstdCompressorMemWriter.scala:112:45] assign _buf_lens_Q_io_enq_bits_T = _GEN; // @[ZstdCompressorMemWriter.scala:62:42, :112:45] reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38] reg [5:0] write_start_index; // @[ZstdCompressorMemWriter.scala:76:34] wire [6:0] _idx_T = {1'h0, write_start_index}; // @[ZstdCompressorMemWriter.scala:76:34, :86:34] wire [6:0] _GEN_0 = _idx_T % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx = _GEN_0[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_1 = _idx_T + 7'h1; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_1 = _idx_T_1 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_1 = _GEN_1[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_2 = _idx_T + 7'h2; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_2 = _idx_T_2 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_2 = _GEN_2[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_3 = _idx_T + 7'h3; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_3 = _idx_T_3 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_3 = _GEN_3[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_4 = _idx_T + 7'h4; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_4 = _idx_T_4 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_4 = _GEN_4[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_5 = _idx_T + 7'h5; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_5 = _idx_T_5 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_5 = _GEN_5[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_6 = _idx_T + 7'h6; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_6 = _idx_T_6 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_6 = _GEN_6[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_7 = _idx_T + 7'h7; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_7 = _idx_T_7 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_7 = _GEN_7[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_8 = _idx_T + 7'h8; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_8 = _idx_T_8 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_8 = _GEN_8[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_9 = _idx_T + 7'h9; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_9 = _idx_T_9 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_9 = _GEN_9[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_10 = _idx_T + 7'hA; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_10 = _idx_T_10 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_10 = _GEN_10[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_11 = _idx_T + 7'hB; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_11 = _idx_T_11 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_11 = _GEN_11[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_12 = _idx_T + 7'hC; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_12 = _idx_T_12 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_12 = _GEN_12[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_13 = _idx_T + 7'hD; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_13 = _idx_T_13 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_13 = _GEN_13[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_14 = _idx_T + 7'hE; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_14 = _idx_T_14 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_14 = _GEN_14[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_15 = _idx_T + 7'hF; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_15 = _idx_T_15 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_15 = _GEN_15[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_16 = _idx_T + 7'h10; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_16 = _idx_T_16 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_16 = _GEN_16[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_17 = _idx_T + 7'h11; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_17 = _idx_T_17 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_17 = _GEN_17[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_18 = _idx_T + 7'h12; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_18 = _idx_T_18 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_18 = _GEN_18[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_19 = _idx_T + 7'h13; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_19 = _idx_T_19 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_19 = _GEN_19[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_20 = _idx_T + 7'h14; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_20 = _idx_T_20 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_20 = _GEN_20[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_21 = _idx_T + 7'h15; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_21 = _idx_T_21 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_21 = _GEN_21[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_22 = _idx_T + 7'h16; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_22 = _idx_T_22 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_22 = _GEN_22[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_23 = _idx_T + 7'h17; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_23 = _idx_T_23 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_23 = _GEN_23[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_24 = _idx_T + 7'h18; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_24 = _idx_T_24 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_24 = _GEN_24[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_25 = _idx_T + 7'h19; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_25 = _idx_T_25 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_25 = _GEN_25[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_26 = _idx_T + 7'h1A; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_26 = _idx_T_26 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_26 = _GEN_26[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_27 = _idx_T + 7'h1B; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_27 = _idx_T_27 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_27 = _GEN_27[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_28 = _idx_T + 7'h1C; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_28 = _idx_T_28 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_28 = _GEN_28[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_29 = _idx_T + 7'h1D; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_29 = _idx_T_29 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_29 = _GEN_29[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_30 = _idx_T + 7'h1E; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_30 = _idx_T_30 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_30 = _GEN_30[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] _idx_T_31 = _idx_T + 7'h1F; // @[ZstdCompressorMemWriter.scala:86:34] wire [6:0] _GEN_31 = _idx_T_31 % 7'h20; // @[ZstdCompressorMemWriter.scala:86:{34,48}] wire [5:0] idx_31 = _GEN_31[5:0]; // @[ZstdCompressorMemWriter.scala:86:48] wire [6:0] wrap_len_index_wide = _idx_T + {1'h0, _incoming_writes_Q_io_deq_bits_validbytes}; // @[ZstdCompressorMemWriter.scala:35:33, :86:34, :95:47] wire [6:0] _GEN_32 = wrap_len_index_wide % 7'h20; // @[ZstdCompressorMemWriter.scala:95:47, :96:48] wire [5:0] wrap_len_index_end = _GEN_32[5:0]; // @[ZstdCompressorMemWriter.scala:96:48] wire wrapped = \|(wrap_len_index_wide[6:5]); // @[ZstdCompressorMemWriter.scala:95:47, :97:37] wire _all_queues_ready_T = _Queue16_UInt8_io_enq_ready & _Queue16_UInt8_1_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_1 = _all_queues_ready_T & _Queue16_UInt8_2_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_2 = _all_queues_ready_T_1 & _Queue16_UInt8_3_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_3 = _all_queues_ready_T_2 & _Queue16_UInt8_4_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_4 = _all_queues_ready_T_3 & _Queue16_UInt8_5_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_5 = _all_queues_ready_T_4 & _Queue16_UInt8_6_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_6 = _all_queues_ready_T_5 & _Queue16_UInt8_7_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_7 = _all_queues_ready_T_6 & _Queue16_UInt8_8_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_8 = _all_queues_ready_T_7 & _Queue16_UInt8_9_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_9 = _all_queues_ready_T_8 & _Queue16_UInt8_10_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_10 = _all_queues_ready_T_9 & _Queue16_UInt8_11_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_11 = _all_queues_ready_T_10 & _Queue16_UInt8_12_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_12 = _all_queues_ready_T_11 & _Queue16_UInt8_13_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_13 = _all_queues_ready_T_12 & _Queue16_UInt8_14_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_14 = _all_queues_ready_T_13 & _Queue16_UInt8_15_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_15 = _all_queues_ready_T_14 & _Queue16_UInt8_16_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_16 = _all_queues_ready_T_15 & _Queue16_UInt8_17_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_17 = _all_queues_ready_T_16 & _Queue16_UInt8_18_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_18 = _all_queues_ready_T_17 & _Queue16_UInt8_19_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_19 = _all_queues_ready_T_18 & _Queue16_UInt8_20_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_20 = _all_queues_ready_T_19 & _Queue16_UInt8_21_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_21 = _all_queues_ready_T_20 & _Queue16_UInt8_22_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_22 = _all_queues_ready_T_21 & _Queue16_UInt8_23_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_23 = _all_queues_ready_T_22 & _Queue16_UInt8_24_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_24 = _all_queues_ready_T_23 & _Queue16_UInt8_25_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_25 = _all_queues_ready_T_24 & _Queue16_UInt8_26_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_26 = _all_queues_ready_T_25 & _Queue16_UInt8_27_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_27 = _all_queues_ready_T_26 & _Queue16_UInt8_28_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_28 = _all_queues_ready_T_27 & _Queue16_UInt8_29_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _all_queues_ready_T_29 = _all_queues_ready_T_28 & _Queue16_UInt8_30_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire all_queues_ready = _all_queues_ready_T_29 & _Queue16_UInt8_31_io_enq_ready; // @[ZstdCompressorMemWriter.scala:77:52, :99:68] wire _account_for_buf_lens_Q_T = ~_incoming_writes_Q_io_deq_bits_end_of_message; // @[ZstdCompressorMemWriter.scala:35:33, :103:33] wire _account_for_buf_lens_Q_T_1 = _incoming_writes_Q_io_deq_bits_end_of_message & _buf_lens_Q_io_enq_ready; // @[ZstdCompressorMemWriter.scala:35:33, :52:26, :103:61] wire account_for_buf_lens_Q = _account_for_buf_lens_Q_T \| _account_for_buf_lens_Q_T_1; // @[ZstdCompressorMemWriter.scala:103:{33,46,61}] wire _buf_lens_Q_io_enq_valid_T = _incoming_writes_Q_io_deq_valid & all_queues_ready; // @[Misc.scala:26:53] wire _buf_lens_Q_io_enq_valid_T_1 = _buf_lens_Q_io_enq_valid_T & _incoming_writes_Q_io_deq_bits_end_of_message; // @[Misc.scala:26:53] assign _incoming_writes_Q_io_deq_ready_T = all_queues_ready & account_for_buf_lens_Q; // @[Misc.scala:26:53] wire _GEN_33 = write_start_index == 6'h0; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T = _GEN_33; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_3; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_3 = _GEN_33; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _use_this_queue_T_1 = \|wrap_len_index_end; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_2 = _use_this_queue_T \| _use_this_queue_T_1; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_4 = \|wrap_len_index_end; // @[ZstdCompressorMemWriter.scala:96:48, :124:77, :125:77] wire _use_this_queue_T_5 = _use_this_queue_T_3 & _use_this_queue_T_4; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue = wrapped ? _use_this_queue_T_2 : _use_this_queue_T_5; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_34 = write_start_index < 6'h2; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_6; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_6 = _GEN_34; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_9; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_9 = _GEN_34; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _use_this_queue_T_7 = \|(wrap_len_index_end[5:1]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_8 = _use_this_queue_T_6 \| _use_this_queue_T_7; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_10 = \|(wrap_len_index_end[5:1]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77, :125:77] wire _use_this_queue_T_11 = _use_this_queue_T_9 & _use_this_queue_T_10; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_1 = wrapped ? _use_this_queue_T_8 : _use_this_queue_T_11; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_35 = write_start_index < 6'h3; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_12; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_12 = _GEN_35; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_15; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_15 = _GEN_35; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_36 = wrap_len_index_end > 6'h2; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_13; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_13 = _GEN_36; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_16; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_16 = _GEN_36; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_14 = _use_this_queue_T_12 \| _use_this_queue_T_13; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_17 = _use_this_queue_T_15 & _use_this_queue_T_16; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_2 = wrapped ? _use_this_queue_T_14 : _use_this_queue_T_17; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_37 = write_start_index < 6'h4; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_18; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_18 = _GEN_37; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_21; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_21 = _GEN_37; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _use_this_queue_T_19 = \|(wrap_len_index_end[5:2]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_20 = _use_this_queue_T_18 \| _use_this_queue_T_19; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_22 = \|(wrap_len_index_end[5:2]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77, :125:77] wire _use_this_queue_T_23 = _use_this_queue_T_21 & _use_this_queue_T_22; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_3 = wrapped ? _use_this_queue_T_20 : _use_this_queue_T_23; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_38 = write_start_index < 6'h5; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_24; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_24 = _GEN_38; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_27; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_27 = _GEN_38; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_39 = wrap_len_index_end > 6'h4; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_25; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_25 = _GEN_39; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_28; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_28 = _GEN_39; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_26 = _use_this_queue_T_24 \| _use_this_queue_T_25; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_29 = _use_this_queue_T_27 & _use_this_queue_T_28; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_4 = wrapped ? _use_this_queue_T_26 : _use_this_queue_T_29; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_40 = write_start_index < 6'h6; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_30; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_30 = _GEN_40; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_33; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_33 = _GEN_40; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_41 = wrap_len_index_end > 6'h5; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_31; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_31 = _GEN_41; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_34; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_34 = _GEN_41; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_32 = _use_this_queue_T_30 \| _use_this_queue_T_31; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_35 = _use_this_queue_T_33 & _use_this_queue_T_34; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_5 = wrapped ? _use_this_queue_T_32 : _use_this_queue_T_35; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_42 = write_start_index < 6'h7; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_36; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_36 = _GEN_42; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_39; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_39 = _GEN_42; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_43 = wrap_len_index_end > 6'h6; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_37; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_37 = _GEN_43; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_40; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_40 = _GEN_43; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_38 = _use_this_queue_T_36 \| _use_this_queue_T_37; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_41 = _use_this_queue_T_39 & _use_this_queue_T_40; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_6 = wrapped ? _use_this_queue_T_38 : _use_this_queue_T_41; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_44 = write_start_index < 6'h8; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_42; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_42 = _GEN_44; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_45; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_45 = _GEN_44; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _use_this_queue_T_43 = \|(wrap_len_index_end[5:3]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_44 = _use_this_queue_T_42 \| _use_this_queue_T_43; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_46 = \|(wrap_len_index_end[5:3]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77, :125:77] wire _use_this_queue_T_47 = _use_this_queue_T_45 & _use_this_queue_T_46; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_7 = wrapped ? _use_this_queue_T_44 : _use_this_queue_T_47; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_45 = write_start_index < 6'h9; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_48; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_48 = _GEN_45; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_51; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_51 = _GEN_45; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_46 = wrap_len_index_end > 6'h8; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_49; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_49 = _GEN_46; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_52; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_52 = _GEN_46; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_50 = _use_this_queue_T_48 \| _use_this_queue_T_49; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_53 = _use_this_queue_T_51 & _use_this_queue_T_52; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_8 = wrapped ? _use_this_queue_T_50 : _use_this_queue_T_53; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_47 = write_start_index < 6'hA; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_54; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_54 = _GEN_47; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_57; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_57 = _GEN_47; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_48 = wrap_len_index_end > 6'h9; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_55; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_55 = _GEN_48; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_58; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_58 = _GEN_48; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_56 = _use_this_queue_T_54 \| _use_this_queue_T_55; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_59 = _use_this_queue_T_57 & _use_this_queue_T_58; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_9 = wrapped ? _use_this_queue_T_56 : _use_this_queue_T_59; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_49 = write_start_index < 6'hB; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_60; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_60 = _GEN_49; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_63; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_63 = _GEN_49; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_50 = wrap_len_index_end > 6'hA; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_61; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_61 = _GEN_50; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_64; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_64 = _GEN_50; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_62 = _use_this_queue_T_60 \| _use_this_queue_T_61; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_65 = _use_this_queue_T_63 & _use_this_queue_T_64; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_10 = wrapped ? _use_this_queue_T_62 : _use_this_queue_T_65; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_51 = write_start_index < 6'hC; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_66; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_66 = _GEN_51; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_69; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_69 = _GEN_51; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_52 = wrap_len_index_end > 6'hB; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_67; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_67 = _GEN_52; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_70; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_70 = _GEN_52; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_68 = _use_this_queue_T_66 \| _use_this_queue_T_67; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_71 = _use_this_queue_T_69 & _use_this_queue_T_70; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_11 = wrapped ? _use_this_queue_T_68 : _use_this_queue_T_71; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_53 = write_start_index < 6'hD; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_72; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_72 = _GEN_53; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_75; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_75 = _GEN_53; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_54 = wrap_len_index_end > 6'hC; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_73; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_73 = _GEN_54; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_76; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_76 = _GEN_54; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_74 = _use_this_queue_T_72 \| _use_this_queue_T_73; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_77 = _use_this_queue_T_75 & _use_this_queue_T_76; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_12 = wrapped ? _use_this_queue_T_74 : _use_this_queue_T_77; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_55 = write_start_index < 6'hE; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_78; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_78 = _GEN_55; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_81; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_81 = _GEN_55; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_56 = wrap_len_index_end > 6'hD; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_79; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_79 = _GEN_56; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_82; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_82 = _GEN_56; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_80 = _use_this_queue_T_78 \| _use_this_queue_T_79; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_83 = _use_this_queue_T_81 & _use_this_queue_T_82; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_13 = wrapped ? _use_this_queue_T_80 : _use_this_queue_T_83; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_57 = write_start_index < 6'hF; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_84; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_84 = _GEN_57; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_87; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_87 = _GEN_57; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_58 = wrap_len_index_end > 6'hE; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_85; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_85 = _GEN_58; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_88; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_88 = _GEN_58; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_86 = _use_this_queue_T_84 \| _use_this_queue_T_85; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_89 = _use_this_queue_T_87 & _use_this_queue_T_88; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_14 = wrapped ? _use_this_queue_T_86 : _use_this_queue_T_89; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_59 = write_start_index < 6'h10; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_90; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_90 = _GEN_59; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_93; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_93 = _GEN_59; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _use_this_queue_T_91 = \|(wrap_len_index_end[5:4]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_92 = _use_this_queue_T_90 \| _use_this_queue_T_91; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_94 = \|(wrap_len_index_end[5:4]); // @[ZstdCompressorMemWriter.scala:96:48, :124:77, :125:77] wire _use_this_queue_T_95 = _use_this_queue_T_93 & _use_this_queue_T_94; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_15 = wrapped ? _use_this_queue_T_92 : _use_this_queue_T_95; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_60 = write_start_index < 6'h11; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_96; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_96 = _GEN_60; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_99; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_99 = _GEN_60; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_61 = wrap_len_index_end > 6'h10; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_97; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_97 = _GEN_61; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_100; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_100 = _GEN_61; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_98 = _use_this_queue_T_96 \| _use_this_queue_T_97; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_101 = _use_this_queue_T_99 & _use_this_queue_T_100; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_16 = wrapped ? _use_this_queue_T_98 : _use_this_queue_T_101; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_62 = write_start_index < 6'h12; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_102; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_102 = _GEN_62; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_105; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_105 = _GEN_62; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_63 = wrap_len_index_end > 6'h11; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_103; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_103 = _GEN_63; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_106; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_106 = _GEN_63; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_104 = _use_this_queue_T_102 \| _use_this_queue_T_103; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_107 = _use_this_queue_T_105 & _use_this_queue_T_106; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_17 = wrapped ? _use_this_queue_T_104 : _use_this_queue_T_107; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_64 = write_start_index < 6'h13; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_108; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_108 = _GEN_64; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_111; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_111 = _GEN_64; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_65 = wrap_len_index_end > 6'h12; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_109; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_109 = _GEN_65; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_112; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_112 = _GEN_65; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_110 = _use_this_queue_T_108 \| _use_this_queue_T_109; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_113 = _use_this_queue_T_111 & _use_this_queue_T_112; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_18 = wrapped ? _use_this_queue_T_110 : _use_this_queue_T_113; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_66 = write_start_index < 6'h14; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_114; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_114 = _GEN_66; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_117; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_117 = _GEN_66; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_67 = wrap_len_index_end > 6'h13; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_115; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_115 = _GEN_67; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_118; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_118 = _GEN_67; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_116 = _use_this_queue_T_114 \| _use_this_queue_T_115; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_119 = _use_this_queue_T_117 & _use_this_queue_T_118; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_19 = wrapped ? _use_this_queue_T_116 : _use_this_queue_T_119; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_68 = write_start_index < 6'h15; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_120; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_120 = _GEN_68; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_123; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_123 = _GEN_68; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_69 = wrap_len_index_end > 6'h14; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_121; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_121 = _GEN_69; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_124; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_124 = _GEN_69; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_122 = _use_this_queue_T_120 \| _use_this_queue_T_121; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_125 = _use_this_queue_T_123 & _use_this_queue_T_124; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_20 = wrapped ? _use_this_queue_T_122 : _use_this_queue_T_125; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_70 = write_start_index < 6'h16; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_126; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_126 = _GEN_70; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_129; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_129 = _GEN_70; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_71 = wrap_len_index_end > 6'h15; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_127; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_127 = _GEN_71; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_130; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_130 = _GEN_71; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_128 = _use_this_queue_T_126 \| _use_this_queue_T_127; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_131 = _use_this_queue_T_129 & _use_this_queue_T_130; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_21 = wrapped ? _use_this_queue_T_128 : _use_this_queue_T_131; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_72 = write_start_index < 6'h17; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_132; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_132 = _GEN_72; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_135; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_135 = _GEN_72; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_73 = wrap_len_index_end > 6'h16; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_133; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_133 = _GEN_73; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_136; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_136 = _GEN_73; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_134 = _use_this_queue_T_132 \| _use_this_queue_T_133; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_137 = _use_this_queue_T_135 & _use_this_queue_T_136; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_22 = wrapped ? _use_this_queue_T_134 : _use_this_queue_T_137; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_74 = write_start_index < 6'h18; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_138; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_138 = _GEN_74; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_141; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_141 = _GEN_74; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_75 = wrap_len_index_end > 6'h17; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_139; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_139 = _GEN_75; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_142; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_142 = _GEN_75; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_140 = _use_this_queue_T_138 \| _use_this_queue_T_139; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_143 = _use_this_queue_T_141 & _use_this_queue_T_142; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_23 = wrapped ? _use_this_queue_T_140 : _use_this_queue_T_143; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_76 = write_start_index < 6'h19; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_144; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_144 = _GEN_76; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_147; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_147 = _GEN_76; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_77 = wrap_len_index_end > 6'h18; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_145; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_145 = _GEN_77; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_148; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_148 = _GEN_77; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_146 = _use_this_queue_T_144 \| _use_this_queue_T_145; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_149 = _use_this_queue_T_147 & _use_this_queue_T_148; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_24 = wrapped ? _use_this_queue_T_146 : _use_this_queue_T_149; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_78 = write_start_index < 6'h1A; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_150; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_150 = _GEN_78; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_153; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_153 = _GEN_78; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_79 = wrap_len_index_end > 6'h19; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_151; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_151 = _GEN_79; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_154; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_154 = _GEN_79; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_152 = _use_this_queue_T_150 \| _use_this_queue_T_151; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_155 = _use_this_queue_T_153 & _use_this_queue_T_154; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_25 = wrapped ? _use_this_queue_T_152 : _use_this_queue_T_155; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_80 = write_start_index < 6'h1B; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_156; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_156 = _GEN_80; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_159; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_159 = _GEN_80; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_81 = wrap_len_index_end > 6'h1A; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_157; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_157 = _GEN_81; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_160; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_160 = _GEN_81; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_158 = _use_this_queue_T_156 \| _use_this_queue_T_157; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_161 = _use_this_queue_T_159 & _use_this_queue_T_160; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_26 = wrapped ? _use_this_queue_T_158 : _use_this_queue_T_161; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_82 = write_start_index < 6'h1C; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_162; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_162 = _GEN_82; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_165; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_165 = _GEN_82; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_83 = wrap_len_index_end > 6'h1B; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_163; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_163 = _GEN_83; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_166; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_166 = _GEN_83; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_164 = _use_this_queue_T_162 \| _use_this_queue_T_163; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_167 = _use_this_queue_T_165 & _use_this_queue_T_166; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_27 = wrapped ? _use_this_queue_T_164 : _use_this_queue_T_167; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_84 = write_start_index < 6'h1D; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_168; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_168 = _GEN_84; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_171; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_171 = _GEN_84; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_85 = wrap_len_index_end > 6'h1C; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_169; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_169 = _GEN_85; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_172; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_172 = _GEN_85; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_170 = _use_this_queue_T_168 \| _use_this_queue_T_169; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_173 = _use_this_queue_T_171 & _use_this_queue_T_172; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_28 = wrapped ? _use_this_queue_T_170 : _use_this_queue_T_173; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_86 = write_start_index < 6'h1E; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_174; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_174 = _GEN_86; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_177; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_177 = _GEN_86; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_87 = wrap_len_index_end > 6'h1D; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_175; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_175 = _GEN_87; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_178; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_178 = _GEN_87; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_176 = _use_this_queue_T_174 \| _use_this_queue_T_175; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_179 = _use_this_queue_T_177 & _use_this_queue_T_178; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_29 = wrapped ? _use_this_queue_T_176 : _use_this_queue_T_179; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _GEN_88 = write_start_index < 6'h1F; // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_180; // @[ZstdCompressorMemWriter.scala:124:41] assign _use_this_queue_T_180 = _GEN_88; // @[ZstdCompressorMemWriter.scala:124:41] wire _use_this_queue_T_183; // @[ZstdCompressorMemWriter.scala:125:41] assign _use_this_queue_T_183 = _GEN_88; // @[ZstdCompressorMemWriter.scala:124:41, :125:41] wire _GEN_89 = wrap_len_index_end > 6'h1E; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_181; // @[ZstdCompressorMemWriter.scala:124:77] assign _use_this_queue_T_181 = _GEN_89; // @[ZstdCompressorMemWriter.scala:124:77] wire _use_this_queue_T_184; // @[ZstdCompressorMemWriter.scala:125:77] assign _use_this_queue_T_184 = _GEN_89; // @[ZstdCompressorMemWriter.scala:124:77, :125:77] wire _use_this_queue_T_182 = _use_this_queue_T_180 \| _use_this_queue_T_181; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_185 = _use_this_queue_T_183 & _use_this_queue_T_184; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_30 = wrapped ? _use_this_queue_T_182 : _use_this_queue_T_185; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] wire _use_this_queue_T_186 = ~(write_start_index[5]); // @[ZstdCompressorMemWriter.scala:76:34, :124:41] wire _use_this_queue_T_187 = wrap_len_index_end[5]; // @[ZstdCompressorMemWriter.scala:96:48, :124:77] wire _use_this_queue_T_190 = wrap_len_index_end[5]; // @[ZstdCompressorMemWriter.scala:96:48, :124:77, :125:77] wire _use_this_queue_T_188 = _use_this_queue_T_186 \| _use_this_queue_T_187; // @[ZstdCompressorMemWriter.scala:124:{41,63,77}] wire _use_this_queue_T_189 = ~(write_start_index[5]); // @[ZstdCompressorMemWriter.scala:76:34, :124:41, :125:41] wire _use_this_queue_T_191 = _use_this_queue_T_189 & _use_this_queue_T_190; // @[ZstdCompressorMemWriter.scala:125:{41,63,77}] wire use_this_queue_31 = wrapped ? _use_this_queue_T_188 : _use_this_queue_T_191; // @[ZstdCompressorMemWriter.scala:97:37, :123:29, :124:63, :125:63] reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_6; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_12; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_24 = {1'h0, loginfo_cycles_12} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_13; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_26 = {1'h0, loginfo_cycles_13} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_14; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_28 = {1'h0, loginfo_cycles_14} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_15; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_30 = {1'h0, loginfo_cycles_15} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_31 = _loginfo_cycles_T_30[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_16; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_32 = {1'h0, loginfo_cycles_16} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_33 = _loginfo_cycles_T_32[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_17; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_34 = {1'h0, loginfo_cycles_17} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_35 = _loginfo_cycles_T_34[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_18; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_36 = {1'h0, loginfo_cycles_18} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_37 = _loginfo_cycles_T_36[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_19; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_38 = {1'h0, loginfo_cycles_19} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_39 = _loginfo_cycles_T_38[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_20; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_40 = {1'h0, loginfo_cycles_20} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_41 = _loginfo_cycles_T_40[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_21; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_42 = {1'h0, loginfo_cycles_21} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_43 = _loginfo_cycles_T_42[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_22; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_44 = {1'h0, loginfo_cycles_22} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_45 = _loginfo_cycles_T_44[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_23; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_46 = {1'h0, loginfo_cycles_23} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_47 = _loginfo_cycles_T_46[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_24; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_48 = {1'h0, loginfo_cycles_24} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_49 = _loginfo_cycles_T_48[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_25; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_50 = {1'h0, loginfo_cycles_25} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_51 = _loginfo_cycles_T_50[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_26; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_52 = {1'h0, loginfo_cycles_26} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_53 = _loginfo_cycles_T_52[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_27; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_54 = {1'h0, loginfo_cycles_27} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_55 = _loginfo_cycles_T_54[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_28; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_56 = {1'h0, loginfo_cycles_28} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_57 = _loginfo_cycles_T_56[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_29; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_58 = {1'h0, loginfo_cycles_29} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_59 = _loginfo_cycles_T_58[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_30; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_60 = {1'h0, loginfo_cycles_30} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_61 = _loginfo_cycles_T_60[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_31; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_62 = {1'h0, loginfo_cycles_31} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_63 = _loginfo_cycles_T_62[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_32; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_64 = {1'h0, loginfo_cycles_32} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_65 = _loginfo_cycles_T_64[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_33; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_66 = {1'h0, loginfo_cycles_33} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_67 = _loginfo_cycles_T_66[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_34; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_68 = {1'h0, loginfo_cycles_34} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_69 = _loginfo_cycles_T_68[63:0]; // @[Util.scala:19:38] reg [5:0] read_start_index; // @[ZstdCompressorMemWriter.scala:139:33] wire [7:0] remapVecData_0; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_1; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_2; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_3; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_4; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_5; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_6; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_7; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_8; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_9; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_10; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_11; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_12; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_13; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_14; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_15; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_16; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_17; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_18; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_19; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_20; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_21; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_22; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_23; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_24; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_25; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_26; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_27; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_28; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_29; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_30; // @[ZstdCompressorMemWriter.scala:141:26] wire [7:0] remapVecData_31; // @[ZstdCompressorMemWriter.scala:141:26] wire remapVecValids_0; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_1; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_2; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_3; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_4; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_5; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_6; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_7; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_8; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_9; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_10; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_11; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_12; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_13; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_14; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_15; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_16; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_17; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_18; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_19; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_20; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_21; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_22; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_23; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_24; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_25; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_26; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_27; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_28; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_29; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_30; // @[ZstdCompressorMemWriter.scala:142:28] wire remapVecValids_31; // @[ZstdCompressorMemWriter.scala:142:28] wire _remapVecReadys_0_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_1_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_2_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_3_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_4_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_5_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_6_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_7_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_8_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_9_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_10_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_11_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_12_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_13_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_14_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_15_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_16_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_17_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_18_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_19_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_20_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_21_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_22_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_23_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_24_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_25_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_26_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_27_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_28_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_29_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_30_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire _remapVecReadys_31_T_4; // @[ZstdCompressorMemWriter.scala:264:61] wire remapVecReadys_0; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_1; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_2; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_3; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_4; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_5; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_6; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_7; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_8; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_9; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_10; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_11; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_12; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_13; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_14; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_15; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_16; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_17; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_18; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_19; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_20; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_21; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_22; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_23; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_24; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_25; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_26; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_27; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_28; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_29; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_30; // @[ZstdCompressorMemWriter.scala:143:28] wire remapVecReadys_31; // @[ZstdCompressorMemWriter.scala:143:28] wire [6:0] _remapindex_T = {1'h0, read_start_index}; // @[ZstdCompressorMemWriter.scala:139:33, :153:33] wire [6:0] _GEN_90 = _remapindex_T % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex = _GEN_90[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4337 = remapindex == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4338 = remapindex == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4339 = remapindex == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4340 = remapindex == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4341 = remapindex == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4342 = remapindex == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4343 = remapindex == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4344 = remapindex == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4345 = remapindex == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4346 = remapindex == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4347 = remapindex == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4348 = remapindex == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4349 = remapindex == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4350 = remapindex == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4351 = remapindex == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4352 = remapindex == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4353 = remapindex == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4354 = remapindex == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4355 = remapindex == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4356 = remapindex == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4357 = remapindex == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4358 = remapindex == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4359 = remapindex == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4360 = remapindex == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4361 = remapindex == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4362 = remapindex == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4363 = remapindex == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4364 = remapindex == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4365 = remapindex == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4366 = remapindex == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4367 = remapindex == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4368 = remapindex == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_0 = _T_4368 ? _Queue16_UInt8_31_io_deq_bits : _T_4367 ? _Queue16_UInt8_30_io_deq_bits : _T_4366 ? _Queue16_UInt8_29_io_deq_bits : _T_4365 ? _Queue16_UInt8_28_io_deq_bits : _T_4364 ? _Queue16_UInt8_27_io_deq_bits : _T_4363 ? _Queue16_UInt8_26_io_deq_bits : _T_4362 ? _Queue16_UInt8_25_io_deq_bits : _T_4361 ? _Queue16_UInt8_24_io_deq_bits : _T_4360 ? _Queue16_UInt8_23_io_deq_bits : _T_4359 ? _Queue16_UInt8_22_io_deq_bits : _T_4358 ? _Queue16_UInt8_21_io_deq_bits : _T_4357 ? _Queue16_UInt8_20_io_deq_bits : _T_4356 ? _Queue16_UInt8_19_io_deq_bits : _T_4355 ? _Queue16_UInt8_18_io_deq_bits : _T_4354 ? _Queue16_UInt8_17_io_deq_bits : _T_4353 ? _Queue16_UInt8_16_io_deq_bits : _T_4352 ? _Queue16_UInt8_15_io_deq_bits : _T_4351 ? _Queue16_UInt8_14_io_deq_bits : _T_4350 ? _Queue16_UInt8_13_io_deq_bits : _T_4349 ? _Queue16_UInt8_12_io_deq_bits : _T_4348 ? _Queue16_UInt8_11_io_deq_bits : _T_4347 ? _Queue16_UInt8_10_io_deq_bits : _T_4346 ? _Queue16_UInt8_9_io_deq_bits : _T_4345 ? _Queue16_UInt8_8_io_deq_bits : _T_4344 ? _Queue16_UInt8_7_io_deq_bits : _T_4343 ? _Queue16_UInt8_6_io_deq_bits : _T_4342 ? _Queue16_UInt8_5_io_deq_bits : _T_4341 ? _Queue16_UInt8_4_io_deq_bits : _T_4340 ? _Queue16_UInt8_3_io_deq_bits : _T_4339 ? _Queue16_UInt8_2_io_deq_bits : _T_4338 ? _Queue16_UInt8_1_io_deq_bits : _T_4337 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_0 = _T_4368 ? _Queue16_UInt8_31_io_deq_valid : _T_4367 ? _Queue16_UInt8_30_io_deq_valid : _T_4366 ? _Queue16_UInt8_29_io_deq_valid : _T_4365 ? _Queue16_UInt8_28_io_deq_valid : _T_4364 ? _Queue16_UInt8_27_io_deq_valid : _T_4363 ? _Queue16_UInt8_26_io_deq_valid : _T_4362 ? _Queue16_UInt8_25_io_deq_valid : _T_4361 ? _Queue16_UInt8_24_io_deq_valid : _T_4360 ? _Queue16_UInt8_23_io_deq_valid : _T_4359 ? _Queue16_UInt8_22_io_deq_valid : _T_4358 ? _Queue16_UInt8_21_io_deq_valid : _T_4357 ? _Queue16_UInt8_20_io_deq_valid : _T_4356 ? _Queue16_UInt8_19_io_deq_valid : _T_4355 ? _Queue16_UInt8_18_io_deq_valid : _T_4354 ? _Queue16_UInt8_17_io_deq_valid : _T_4353 ? _Queue16_UInt8_16_io_deq_valid : _T_4352 ? _Queue16_UInt8_15_io_deq_valid : _T_4351 ? _Queue16_UInt8_14_io_deq_valid : _T_4350 ? _Queue16_UInt8_13_io_deq_valid : _T_4349 ? _Queue16_UInt8_12_io_deq_valid : _T_4348 ? _Queue16_UInt8_11_io_deq_valid : _T_4347 ? _Queue16_UInt8_10_io_deq_valid : _T_4346 ? _Queue16_UInt8_9_io_deq_valid : _T_4345 ? _Queue16_UInt8_8_io_deq_valid : _T_4344 ? _Queue16_UInt8_7_io_deq_valid : _T_4343 ? _Queue16_UInt8_6_io_deq_valid : _T_4342 ? _Queue16_UInt8_5_io_deq_valid : _T_4341 ? _Queue16_UInt8_4_io_deq_valid : _T_4340 ? _Queue16_UInt8_3_io_deq_valid : _T_4339 ? _Queue16_UInt8_2_io_deq_valid : _T_4338 ? _Queue16_UInt8_1_io_deq_valid : _T_4337 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_1 = _remapindex_T + 7'h1; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_91 = _remapindex_T_1 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_1 = _GEN_91[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4369 = remapindex_1 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4370 = remapindex_1 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4371 = remapindex_1 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4372 = remapindex_1 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4373 = remapindex_1 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4374 = remapindex_1 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4375 = remapindex_1 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4376 = remapindex_1 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4377 = remapindex_1 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4378 = remapindex_1 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4379 = remapindex_1 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4380 = remapindex_1 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4381 = remapindex_1 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4382 = remapindex_1 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4383 = remapindex_1 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4384 = remapindex_1 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4385 = remapindex_1 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4386 = remapindex_1 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4387 = remapindex_1 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4388 = remapindex_1 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4389 = remapindex_1 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4390 = remapindex_1 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4391 = remapindex_1 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4392 = remapindex_1 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4393 = remapindex_1 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4394 = remapindex_1 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4395 = remapindex_1 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4396 = remapindex_1 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4397 = remapindex_1 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4398 = remapindex_1 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4399 = remapindex_1 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4400 = remapindex_1 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_1 = _T_4400 ? _Queue16_UInt8_31_io_deq_bits : _T_4399 ? _Queue16_UInt8_30_io_deq_bits : _T_4398 ? _Queue16_UInt8_29_io_deq_bits : _T_4397 ? _Queue16_UInt8_28_io_deq_bits : _T_4396 ? _Queue16_UInt8_27_io_deq_bits : _T_4395 ? _Queue16_UInt8_26_io_deq_bits : _T_4394 ? _Queue16_UInt8_25_io_deq_bits : _T_4393 ? _Queue16_UInt8_24_io_deq_bits : _T_4392 ? _Queue16_UInt8_23_io_deq_bits : _T_4391 ? _Queue16_UInt8_22_io_deq_bits : _T_4390 ? _Queue16_UInt8_21_io_deq_bits : _T_4389 ? _Queue16_UInt8_20_io_deq_bits : _T_4388 ? _Queue16_UInt8_19_io_deq_bits : _T_4387 ? _Queue16_UInt8_18_io_deq_bits : _T_4386 ? _Queue16_UInt8_17_io_deq_bits : _T_4385 ? _Queue16_UInt8_16_io_deq_bits : _T_4384 ? _Queue16_UInt8_15_io_deq_bits : _T_4383 ? _Queue16_UInt8_14_io_deq_bits : _T_4382 ? _Queue16_UInt8_13_io_deq_bits : _T_4381 ? _Queue16_UInt8_12_io_deq_bits : _T_4380 ? _Queue16_UInt8_11_io_deq_bits : _T_4379 ? _Queue16_UInt8_10_io_deq_bits : _T_4378 ? _Queue16_UInt8_9_io_deq_bits : _T_4377 ? _Queue16_UInt8_8_io_deq_bits : _T_4376 ? _Queue16_UInt8_7_io_deq_bits : _T_4375 ? _Queue16_UInt8_6_io_deq_bits : _T_4374 ? _Queue16_UInt8_5_io_deq_bits : _T_4373 ? _Queue16_UInt8_4_io_deq_bits : _T_4372 ? _Queue16_UInt8_3_io_deq_bits : _T_4371 ? _Queue16_UInt8_2_io_deq_bits : _T_4370 ? _Queue16_UInt8_1_io_deq_bits : _T_4369 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_1 = _T_4400 ? _Queue16_UInt8_31_io_deq_valid : _T_4399 ? _Queue16_UInt8_30_io_deq_valid : _T_4398 ? _Queue16_UInt8_29_io_deq_valid : _T_4397 ? _Queue16_UInt8_28_io_deq_valid : _T_4396 ? _Queue16_UInt8_27_io_deq_valid : _T_4395 ? _Queue16_UInt8_26_io_deq_valid : _T_4394 ? _Queue16_UInt8_25_io_deq_valid : _T_4393 ? _Queue16_UInt8_24_io_deq_valid : _T_4392 ? _Queue16_UInt8_23_io_deq_valid : _T_4391 ? _Queue16_UInt8_22_io_deq_valid : _T_4390 ? _Queue16_UInt8_21_io_deq_valid : _T_4389 ? _Queue16_UInt8_20_io_deq_valid : _T_4388 ? _Queue16_UInt8_19_io_deq_valid : _T_4387 ? _Queue16_UInt8_18_io_deq_valid : _T_4386 ? _Queue16_UInt8_17_io_deq_valid : _T_4385 ? _Queue16_UInt8_16_io_deq_valid : _T_4384 ? _Queue16_UInt8_15_io_deq_valid : _T_4383 ? _Queue16_UInt8_14_io_deq_valid : _T_4382 ? _Queue16_UInt8_13_io_deq_valid : _T_4381 ? _Queue16_UInt8_12_io_deq_valid : _T_4380 ? _Queue16_UInt8_11_io_deq_valid : _T_4379 ? _Queue16_UInt8_10_io_deq_valid : _T_4378 ? _Queue16_UInt8_9_io_deq_valid : _T_4377 ? _Queue16_UInt8_8_io_deq_valid : _T_4376 ? _Queue16_UInt8_7_io_deq_valid : _T_4375 ? _Queue16_UInt8_6_io_deq_valid : _T_4374 ? _Queue16_UInt8_5_io_deq_valid : _T_4373 ? _Queue16_UInt8_4_io_deq_valid : _T_4372 ? _Queue16_UInt8_3_io_deq_valid : _T_4371 ? _Queue16_UInt8_2_io_deq_valid : _T_4370 ? _Queue16_UInt8_1_io_deq_valid : _T_4369 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_2 = _remapindex_T + 7'h2; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_92 = _remapindex_T_2 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_2 = _GEN_92[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4401 = remapindex_2 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4402 = remapindex_2 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4403 = remapindex_2 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4404 = remapindex_2 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4405 = remapindex_2 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4406 = remapindex_2 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4407 = remapindex_2 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4408 = remapindex_2 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4409 = remapindex_2 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4410 = remapindex_2 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4411 = remapindex_2 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4412 = remapindex_2 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4413 = remapindex_2 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4414 = remapindex_2 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4415 = remapindex_2 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4416 = remapindex_2 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4417 = remapindex_2 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4418 = remapindex_2 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4419 = remapindex_2 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4420 = remapindex_2 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4421 = remapindex_2 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4422 = remapindex_2 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4423 = remapindex_2 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4424 = remapindex_2 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4425 = remapindex_2 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4426 = remapindex_2 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4427 = remapindex_2 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4428 = remapindex_2 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4429 = remapindex_2 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4430 = remapindex_2 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4431 = remapindex_2 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4432 = remapindex_2 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_2 = _T_4432 ? _Queue16_UInt8_31_io_deq_bits : _T_4431 ? _Queue16_UInt8_30_io_deq_bits : _T_4430 ? _Queue16_UInt8_29_io_deq_bits : _T_4429 ? _Queue16_UInt8_28_io_deq_bits : _T_4428 ? _Queue16_UInt8_27_io_deq_bits : _T_4427 ? _Queue16_UInt8_26_io_deq_bits : _T_4426 ? _Queue16_UInt8_25_io_deq_bits : _T_4425 ? _Queue16_UInt8_24_io_deq_bits : _T_4424 ? _Queue16_UInt8_23_io_deq_bits : _T_4423 ? _Queue16_UInt8_22_io_deq_bits : _T_4422 ? _Queue16_UInt8_21_io_deq_bits : _T_4421 ? _Queue16_UInt8_20_io_deq_bits : _T_4420 ? _Queue16_UInt8_19_io_deq_bits : _T_4419 ? _Queue16_UInt8_18_io_deq_bits : _T_4418 ? _Queue16_UInt8_17_io_deq_bits : _T_4417 ? _Queue16_UInt8_16_io_deq_bits : _T_4416 ? _Queue16_UInt8_15_io_deq_bits : _T_4415 ? _Queue16_UInt8_14_io_deq_bits : _T_4414 ? _Queue16_UInt8_13_io_deq_bits : _T_4413 ? _Queue16_UInt8_12_io_deq_bits : _T_4412 ? _Queue16_UInt8_11_io_deq_bits : _T_4411 ? _Queue16_UInt8_10_io_deq_bits : _T_4410 ? _Queue16_UInt8_9_io_deq_bits : _T_4409 ? _Queue16_UInt8_8_io_deq_bits : _T_4408 ? _Queue16_UInt8_7_io_deq_bits : _T_4407 ? _Queue16_UInt8_6_io_deq_bits : _T_4406 ? _Queue16_UInt8_5_io_deq_bits : _T_4405 ? _Queue16_UInt8_4_io_deq_bits : _T_4404 ? _Queue16_UInt8_3_io_deq_bits : _T_4403 ? _Queue16_UInt8_2_io_deq_bits : _T_4402 ? _Queue16_UInt8_1_io_deq_bits : _T_4401 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_2 = _T_4432 ? _Queue16_UInt8_31_io_deq_valid : _T_4431 ? _Queue16_UInt8_30_io_deq_valid : _T_4430 ? _Queue16_UInt8_29_io_deq_valid : _T_4429 ? _Queue16_UInt8_28_io_deq_valid : _T_4428 ? _Queue16_UInt8_27_io_deq_valid : _T_4427 ? _Queue16_UInt8_26_io_deq_valid : _T_4426 ? _Queue16_UInt8_25_io_deq_valid : _T_4425 ? _Queue16_UInt8_24_io_deq_valid : _T_4424 ? _Queue16_UInt8_23_io_deq_valid : _T_4423 ? _Queue16_UInt8_22_io_deq_valid : _T_4422 ? _Queue16_UInt8_21_io_deq_valid : _T_4421 ? _Queue16_UInt8_20_io_deq_valid : _T_4420 ? _Queue16_UInt8_19_io_deq_valid : _T_4419 ? _Queue16_UInt8_18_io_deq_valid : _T_4418 ? _Queue16_UInt8_17_io_deq_valid : _T_4417 ? _Queue16_UInt8_16_io_deq_valid : _T_4416 ? _Queue16_UInt8_15_io_deq_valid : _T_4415 ? _Queue16_UInt8_14_io_deq_valid : _T_4414 ? _Queue16_UInt8_13_io_deq_valid : _T_4413 ? _Queue16_UInt8_12_io_deq_valid : _T_4412 ? _Queue16_UInt8_11_io_deq_valid : _T_4411 ? _Queue16_UInt8_10_io_deq_valid : _T_4410 ? _Queue16_UInt8_9_io_deq_valid : _T_4409 ? _Queue16_UInt8_8_io_deq_valid : _T_4408 ? _Queue16_UInt8_7_io_deq_valid : _T_4407 ? _Queue16_UInt8_6_io_deq_valid : _T_4406 ? _Queue16_UInt8_5_io_deq_valid : _T_4405 ? _Queue16_UInt8_4_io_deq_valid : _T_4404 ? _Queue16_UInt8_3_io_deq_valid : _T_4403 ? _Queue16_UInt8_2_io_deq_valid : _T_4402 ? _Queue16_UInt8_1_io_deq_valid : _T_4401 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_3 = _remapindex_T + 7'h3; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_93 = _remapindex_T_3 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_3 = _GEN_93[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4433 = remapindex_3 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4434 = remapindex_3 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4435 = remapindex_3 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4436 = remapindex_3 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4437 = remapindex_3 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4438 = remapindex_3 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4439 = remapindex_3 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4440 = remapindex_3 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4441 = remapindex_3 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4442 = remapindex_3 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4443 = remapindex_3 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4444 = remapindex_3 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4445 = remapindex_3 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4446 = remapindex_3 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4447 = remapindex_3 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4448 = remapindex_3 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4449 = remapindex_3 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4450 = remapindex_3 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4451 = remapindex_3 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4452 = remapindex_3 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4453 = remapindex_3 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4454 = remapindex_3 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4455 = remapindex_3 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4456 = remapindex_3 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4457 = remapindex_3 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4458 = remapindex_3 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4459 = remapindex_3 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4460 = remapindex_3 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4461 = remapindex_3 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4462 = remapindex_3 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4463 = remapindex_3 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4464 = remapindex_3 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_3 = _T_4464 ? _Queue16_UInt8_31_io_deq_bits : _T_4463 ? _Queue16_UInt8_30_io_deq_bits : _T_4462 ? _Queue16_UInt8_29_io_deq_bits : _T_4461 ? _Queue16_UInt8_28_io_deq_bits : _T_4460 ? _Queue16_UInt8_27_io_deq_bits : _T_4459 ? _Queue16_UInt8_26_io_deq_bits : _T_4458 ? _Queue16_UInt8_25_io_deq_bits : _T_4457 ? _Queue16_UInt8_24_io_deq_bits : _T_4456 ? _Queue16_UInt8_23_io_deq_bits : _T_4455 ? _Queue16_UInt8_22_io_deq_bits : _T_4454 ? _Queue16_UInt8_21_io_deq_bits : _T_4453 ? _Queue16_UInt8_20_io_deq_bits : _T_4452 ? _Queue16_UInt8_19_io_deq_bits : _T_4451 ? _Queue16_UInt8_18_io_deq_bits : _T_4450 ? _Queue16_UInt8_17_io_deq_bits : _T_4449 ? _Queue16_UInt8_16_io_deq_bits : _T_4448 ? _Queue16_UInt8_15_io_deq_bits : _T_4447 ? _Queue16_UInt8_14_io_deq_bits : _T_4446 ? _Queue16_UInt8_13_io_deq_bits : _T_4445 ? _Queue16_UInt8_12_io_deq_bits : _T_4444 ? _Queue16_UInt8_11_io_deq_bits : _T_4443 ? _Queue16_UInt8_10_io_deq_bits : _T_4442 ? _Queue16_UInt8_9_io_deq_bits : _T_4441 ? _Queue16_UInt8_8_io_deq_bits : _T_4440 ? _Queue16_UInt8_7_io_deq_bits : _T_4439 ? _Queue16_UInt8_6_io_deq_bits : _T_4438 ? _Queue16_UInt8_5_io_deq_bits : _T_4437 ? _Queue16_UInt8_4_io_deq_bits : _T_4436 ? _Queue16_UInt8_3_io_deq_bits : _T_4435 ? _Queue16_UInt8_2_io_deq_bits : _T_4434 ? _Queue16_UInt8_1_io_deq_bits : _T_4433 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_3 = _T_4464 ? _Queue16_UInt8_31_io_deq_valid : _T_4463 ? _Queue16_UInt8_30_io_deq_valid : _T_4462 ? _Queue16_UInt8_29_io_deq_valid : _T_4461 ? _Queue16_UInt8_28_io_deq_valid : _T_4460 ? _Queue16_UInt8_27_io_deq_valid : _T_4459 ? _Queue16_UInt8_26_io_deq_valid : _T_4458 ? _Queue16_UInt8_25_io_deq_valid : _T_4457 ? _Queue16_UInt8_24_io_deq_valid : _T_4456 ? _Queue16_UInt8_23_io_deq_valid : _T_4455 ? _Queue16_UInt8_22_io_deq_valid : _T_4454 ? _Queue16_UInt8_21_io_deq_valid : _T_4453 ? _Queue16_UInt8_20_io_deq_valid : _T_4452 ? _Queue16_UInt8_19_io_deq_valid : _T_4451 ? _Queue16_UInt8_18_io_deq_valid : _T_4450 ? _Queue16_UInt8_17_io_deq_valid : _T_4449 ? _Queue16_UInt8_16_io_deq_valid : _T_4448 ? _Queue16_UInt8_15_io_deq_valid : _T_4447 ? _Queue16_UInt8_14_io_deq_valid : _T_4446 ? _Queue16_UInt8_13_io_deq_valid : _T_4445 ? _Queue16_UInt8_12_io_deq_valid : _T_4444 ? _Queue16_UInt8_11_io_deq_valid : _T_4443 ? _Queue16_UInt8_10_io_deq_valid : _T_4442 ? _Queue16_UInt8_9_io_deq_valid : _T_4441 ? _Queue16_UInt8_8_io_deq_valid : _T_4440 ? _Queue16_UInt8_7_io_deq_valid : _T_4439 ? _Queue16_UInt8_6_io_deq_valid : _T_4438 ? _Queue16_UInt8_5_io_deq_valid : _T_4437 ? _Queue16_UInt8_4_io_deq_valid : _T_4436 ? _Queue16_UInt8_3_io_deq_valid : _T_4435 ? _Queue16_UInt8_2_io_deq_valid : _T_4434 ? _Queue16_UInt8_1_io_deq_valid : _T_4433 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_4 = _remapindex_T + 7'h4; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_94 = _remapindex_T_4 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_4 = _GEN_94[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4465 = remapindex_4 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4466 = remapindex_4 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4467 = remapindex_4 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4468 = remapindex_4 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4469 = remapindex_4 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4470 = remapindex_4 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4471 = remapindex_4 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4472 = remapindex_4 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4473 = remapindex_4 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4474 = remapindex_4 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4475 = remapindex_4 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4476 = remapindex_4 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4477 = remapindex_4 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4478 = remapindex_4 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4479 = remapindex_4 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4480 = remapindex_4 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4481 = remapindex_4 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4482 = remapindex_4 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4483 = remapindex_4 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4484 = remapindex_4 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4485 = remapindex_4 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4486 = remapindex_4 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4487 = remapindex_4 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4488 = remapindex_4 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4489 = remapindex_4 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4490 = remapindex_4 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4491 = remapindex_4 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4492 = remapindex_4 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4493 = remapindex_4 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4494 = remapindex_4 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4495 = remapindex_4 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4496 = remapindex_4 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_4 = _T_4496 ? _Queue16_UInt8_31_io_deq_bits : _T_4495 ? _Queue16_UInt8_30_io_deq_bits : _T_4494 ? _Queue16_UInt8_29_io_deq_bits : _T_4493 ? _Queue16_UInt8_28_io_deq_bits : _T_4492 ? _Queue16_UInt8_27_io_deq_bits : _T_4491 ? _Queue16_UInt8_26_io_deq_bits : _T_4490 ? _Queue16_UInt8_25_io_deq_bits : _T_4489 ? _Queue16_UInt8_24_io_deq_bits : _T_4488 ? _Queue16_UInt8_23_io_deq_bits : _T_4487 ? _Queue16_UInt8_22_io_deq_bits : _T_4486 ? _Queue16_UInt8_21_io_deq_bits : _T_4485 ? _Queue16_UInt8_20_io_deq_bits : _T_4484 ? _Queue16_UInt8_19_io_deq_bits : _T_4483 ? _Queue16_UInt8_18_io_deq_bits : _T_4482 ? _Queue16_UInt8_17_io_deq_bits : _T_4481 ? _Queue16_UInt8_16_io_deq_bits : _T_4480 ? _Queue16_UInt8_15_io_deq_bits : _T_4479 ? _Queue16_UInt8_14_io_deq_bits : _T_4478 ? _Queue16_UInt8_13_io_deq_bits : _T_4477 ? _Queue16_UInt8_12_io_deq_bits : _T_4476 ? _Queue16_UInt8_11_io_deq_bits : _T_4475 ? _Queue16_UInt8_10_io_deq_bits : _T_4474 ? _Queue16_UInt8_9_io_deq_bits : _T_4473 ? _Queue16_UInt8_8_io_deq_bits : _T_4472 ? _Queue16_UInt8_7_io_deq_bits : _T_4471 ? _Queue16_UInt8_6_io_deq_bits : _T_4470 ? _Queue16_UInt8_5_io_deq_bits : _T_4469 ? _Queue16_UInt8_4_io_deq_bits : _T_4468 ? _Queue16_UInt8_3_io_deq_bits : _T_4467 ? _Queue16_UInt8_2_io_deq_bits : _T_4466 ? _Queue16_UInt8_1_io_deq_bits : _T_4465 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_4 = _T_4496 ? _Queue16_UInt8_31_io_deq_valid : _T_4495 ? _Queue16_UInt8_30_io_deq_valid : _T_4494 ? _Queue16_UInt8_29_io_deq_valid : _T_4493 ? _Queue16_UInt8_28_io_deq_valid : _T_4492 ? _Queue16_UInt8_27_io_deq_valid : _T_4491 ? _Queue16_UInt8_26_io_deq_valid : _T_4490 ? _Queue16_UInt8_25_io_deq_valid : _T_4489 ? _Queue16_UInt8_24_io_deq_valid : _T_4488 ? _Queue16_UInt8_23_io_deq_valid : _T_4487 ? _Queue16_UInt8_22_io_deq_valid : _T_4486 ? _Queue16_UInt8_21_io_deq_valid : _T_4485 ? _Queue16_UInt8_20_io_deq_valid : _T_4484 ? _Queue16_UInt8_19_io_deq_valid : _T_4483 ? _Queue16_UInt8_18_io_deq_valid : _T_4482 ? _Queue16_UInt8_17_io_deq_valid : _T_4481 ? _Queue16_UInt8_16_io_deq_valid : _T_4480 ? _Queue16_UInt8_15_io_deq_valid : _T_4479 ? _Queue16_UInt8_14_io_deq_valid : _T_4478 ? _Queue16_UInt8_13_io_deq_valid : _T_4477 ? _Queue16_UInt8_12_io_deq_valid : _T_4476 ? _Queue16_UInt8_11_io_deq_valid : _T_4475 ? _Queue16_UInt8_10_io_deq_valid : _T_4474 ? _Queue16_UInt8_9_io_deq_valid : _T_4473 ? _Queue16_UInt8_8_io_deq_valid : _T_4472 ? _Queue16_UInt8_7_io_deq_valid : _T_4471 ? _Queue16_UInt8_6_io_deq_valid : _T_4470 ? _Queue16_UInt8_5_io_deq_valid : _T_4469 ? _Queue16_UInt8_4_io_deq_valid : _T_4468 ? _Queue16_UInt8_3_io_deq_valid : _T_4467 ? _Queue16_UInt8_2_io_deq_valid : _T_4466 ? _Queue16_UInt8_1_io_deq_valid : _T_4465 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_5 = _remapindex_T + 7'h5; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_95 = _remapindex_T_5 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_5 = _GEN_95[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4497 = remapindex_5 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4498 = remapindex_5 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4499 = remapindex_5 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4500 = remapindex_5 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4501 = remapindex_5 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4502 = remapindex_5 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4503 = remapindex_5 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4504 = remapindex_5 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4505 = remapindex_5 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4506 = remapindex_5 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4507 = remapindex_5 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4508 = remapindex_5 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4509 = remapindex_5 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4510 = remapindex_5 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4511 = remapindex_5 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4512 = remapindex_5 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4513 = remapindex_5 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4514 = remapindex_5 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4515 = remapindex_5 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4516 = remapindex_5 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4517 = remapindex_5 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4518 = remapindex_5 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4519 = remapindex_5 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4520 = remapindex_5 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4521 = remapindex_5 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4522 = remapindex_5 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4523 = remapindex_5 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4524 = remapindex_5 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4525 = remapindex_5 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4526 = remapindex_5 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4527 = remapindex_5 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4528 = remapindex_5 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_5 = _T_4528 ? _Queue16_UInt8_31_io_deq_bits : _T_4527 ? _Queue16_UInt8_30_io_deq_bits : _T_4526 ? _Queue16_UInt8_29_io_deq_bits : _T_4525 ? _Queue16_UInt8_28_io_deq_bits : _T_4524 ? _Queue16_UInt8_27_io_deq_bits : _T_4523 ? _Queue16_UInt8_26_io_deq_bits : _T_4522 ? _Queue16_UInt8_25_io_deq_bits : _T_4521 ? _Queue16_UInt8_24_io_deq_bits : _T_4520 ? _Queue16_UInt8_23_io_deq_bits : _T_4519 ? _Queue16_UInt8_22_io_deq_bits : _T_4518 ? _Queue16_UInt8_21_io_deq_bits : _T_4517 ? _Queue16_UInt8_20_io_deq_bits : _T_4516 ? _Queue16_UInt8_19_io_deq_bits : _T_4515 ? _Queue16_UInt8_18_io_deq_bits : _T_4514 ? _Queue16_UInt8_17_io_deq_bits : _T_4513 ? _Queue16_UInt8_16_io_deq_bits : _T_4512 ? _Queue16_UInt8_15_io_deq_bits : _T_4511 ? _Queue16_UInt8_14_io_deq_bits : _T_4510 ? _Queue16_UInt8_13_io_deq_bits : _T_4509 ? _Queue16_UInt8_12_io_deq_bits : _T_4508 ? _Queue16_UInt8_11_io_deq_bits : _T_4507 ? _Queue16_UInt8_10_io_deq_bits : _T_4506 ? _Queue16_UInt8_9_io_deq_bits : _T_4505 ? _Queue16_UInt8_8_io_deq_bits : _T_4504 ? _Queue16_UInt8_7_io_deq_bits : _T_4503 ? _Queue16_UInt8_6_io_deq_bits : _T_4502 ? _Queue16_UInt8_5_io_deq_bits : _T_4501 ? _Queue16_UInt8_4_io_deq_bits : _T_4500 ? _Queue16_UInt8_3_io_deq_bits : _T_4499 ? _Queue16_UInt8_2_io_deq_bits : _T_4498 ? _Queue16_UInt8_1_io_deq_bits : _T_4497 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_5 = _T_4528 ? _Queue16_UInt8_31_io_deq_valid : _T_4527 ? _Queue16_UInt8_30_io_deq_valid : _T_4526 ? _Queue16_UInt8_29_io_deq_valid : _T_4525 ? _Queue16_UInt8_28_io_deq_valid : _T_4524 ? _Queue16_UInt8_27_io_deq_valid : _T_4523 ? _Queue16_UInt8_26_io_deq_valid : _T_4522 ? _Queue16_UInt8_25_io_deq_valid : _T_4521 ? _Queue16_UInt8_24_io_deq_valid : _T_4520 ? _Queue16_UInt8_23_io_deq_valid : _T_4519 ? _Queue16_UInt8_22_io_deq_valid : _T_4518 ? _Queue16_UInt8_21_io_deq_valid : _T_4517 ? _Queue16_UInt8_20_io_deq_valid : _T_4516 ? _Queue16_UInt8_19_io_deq_valid : _T_4515 ? _Queue16_UInt8_18_io_deq_valid : _T_4514 ? _Queue16_UInt8_17_io_deq_valid : _T_4513 ? _Queue16_UInt8_16_io_deq_valid : _T_4512 ? _Queue16_UInt8_15_io_deq_valid : _T_4511 ? _Queue16_UInt8_14_io_deq_valid : _T_4510 ? _Queue16_UInt8_13_io_deq_valid : _T_4509 ? _Queue16_UInt8_12_io_deq_valid : _T_4508 ? _Queue16_UInt8_11_io_deq_valid : _T_4507 ? _Queue16_UInt8_10_io_deq_valid : _T_4506 ? _Queue16_UInt8_9_io_deq_valid : _T_4505 ? _Queue16_UInt8_8_io_deq_valid : _T_4504 ? _Queue16_UInt8_7_io_deq_valid : _T_4503 ? _Queue16_UInt8_6_io_deq_valid : _T_4502 ? _Queue16_UInt8_5_io_deq_valid : _T_4501 ? _Queue16_UInt8_4_io_deq_valid : _T_4500 ? _Queue16_UInt8_3_io_deq_valid : _T_4499 ? _Queue16_UInt8_2_io_deq_valid : _T_4498 ? _Queue16_UInt8_1_io_deq_valid : _T_4497 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_6 = _remapindex_T + 7'h6; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_96 = _remapindex_T_6 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_6 = _GEN_96[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4529 = remapindex_6 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4530 = remapindex_6 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4531 = remapindex_6 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4532 = remapindex_6 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4533 = remapindex_6 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4534 = remapindex_6 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4535 = remapindex_6 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4536 = remapindex_6 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4537 = remapindex_6 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4538 = remapindex_6 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4539 = remapindex_6 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4540 = remapindex_6 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4541 = remapindex_6 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4542 = remapindex_6 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4543 = remapindex_6 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4544 = remapindex_6 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4545 = remapindex_6 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4546 = remapindex_6 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4547 = remapindex_6 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4548 = remapindex_6 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4549 = remapindex_6 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4550 = remapindex_6 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4551 = remapindex_6 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4552 = remapindex_6 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4553 = remapindex_6 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4554 = remapindex_6 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4555 = remapindex_6 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4556 = remapindex_6 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4557 = remapindex_6 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4558 = remapindex_6 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4559 = remapindex_6 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4560 = remapindex_6 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_6 = _T_4560 ? _Queue16_UInt8_31_io_deq_bits : _T_4559 ? _Queue16_UInt8_30_io_deq_bits : _T_4558 ? _Queue16_UInt8_29_io_deq_bits : _T_4557 ? _Queue16_UInt8_28_io_deq_bits : _T_4556 ? _Queue16_UInt8_27_io_deq_bits : _T_4555 ? _Queue16_UInt8_26_io_deq_bits : _T_4554 ? _Queue16_UInt8_25_io_deq_bits : _T_4553 ? _Queue16_UInt8_24_io_deq_bits : _T_4552 ? _Queue16_UInt8_23_io_deq_bits : _T_4551 ? _Queue16_UInt8_22_io_deq_bits : _T_4550 ? _Queue16_UInt8_21_io_deq_bits : _T_4549 ? _Queue16_UInt8_20_io_deq_bits : _T_4548 ? _Queue16_UInt8_19_io_deq_bits : _T_4547 ? _Queue16_UInt8_18_io_deq_bits : _T_4546 ? _Queue16_UInt8_17_io_deq_bits : _T_4545 ? _Queue16_UInt8_16_io_deq_bits : _T_4544 ? _Queue16_UInt8_15_io_deq_bits : _T_4543 ? _Queue16_UInt8_14_io_deq_bits : _T_4542 ? _Queue16_UInt8_13_io_deq_bits : _T_4541 ? _Queue16_UInt8_12_io_deq_bits : _T_4540 ? _Queue16_UInt8_11_io_deq_bits : _T_4539 ? _Queue16_UInt8_10_io_deq_bits : _T_4538 ? _Queue16_UInt8_9_io_deq_bits : _T_4537 ? _Queue16_UInt8_8_io_deq_bits : _T_4536 ? _Queue16_UInt8_7_io_deq_bits : _T_4535 ? _Queue16_UInt8_6_io_deq_bits : _T_4534 ? _Queue16_UInt8_5_io_deq_bits : _T_4533 ? _Queue16_UInt8_4_io_deq_bits : _T_4532 ? _Queue16_UInt8_3_io_deq_bits : _T_4531 ? _Queue16_UInt8_2_io_deq_bits : _T_4530 ? _Queue16_UInt8_1_io_deq_bits : _T_4529 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_6 = _T_4560 ? _Queue16_UInt8_31_io_deq_valid : _T_4559 ? _Queue16_UInt8_30_io_deq_valid : _T_4558 ? _Queue16_UInt8_29_io_deq_valid : _T_4557 ? _Queue16_UInt8_28_io_deq_valid : _T_4556 ? _Queue16_UInt8_27_io_deq_valid : _T_4555 ? _Queue16_UInt8_26_io_deq_valid : _T_4554 ? _Queue16_UInt8_25_io_deq_valid : _T_4553 ? _Queue16_UInt8_24_io_deq_valid : _T_4552 ? _Queue16_UInt8_23_io_deq_valid : _T_4551 ? _Queue16_UInt8_22_io_deq_valid : _T_4550 ? _Queue16_UInt8_21_io_deq_valid : _T_4549 ? _Queue16_UInt8_20_io_deq_valid : _T_4548 ? _Queue16_UInt8_19_io_deq_valid : _T_4547 ? _Queue16_UInt8_18_io_deq_valid : _T_4546 ? _Queue16_UInt8_17_io_deq_valid : _T_4545 ? _Queue16_UInt8_16_io_deq_valid : _T_4544 ? _Queue16_UInt8_15_io_deq_valid : _T_4543 ? _Queue16_UInt8_14_io_deq_valid : _T_4542 ? _Queue16_UInt8_13_io_deq_valid : _T_4541 ? _Queue16_UInt8_12_io_deq_valid : _T_4540 ? _Queue16_UInt8_11_io_deq_valid : _T_4539 ? _Queue16_UInt8_10_io_deq_valid : _T_4538 ? _Queue16_UInt8_9_io_deq_valid : _T_4537 ? _Queue16_UInt8_8_io_deq_valid : _T_4536 ? _Queue16_UInt8_7_io_deq_valid : _T_4535 ? _Queue16_UInt8_6_io_deq_valid : _T_4534 ? _Queue16_UInt8_5_io_deq_valid : _T_4533 ? _Queue16_UInt8_4_io_deq_valid : _T_4532 ? _Queue16_UInt8_3_io_deq_valid : _T_4531 ? _Queue16_UInt8_2_io_deq_valid : _T_4530 ? _Queue16_UInt8_1_io_deq_valid : _T_4529 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_7 = _remapindex_T + 7'h7; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_97 = _remapindex_T_7 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_7 = _GEN_97[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4561 = remapindex_7 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4562 = remapindex_7 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4563 = remapindex_7 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4564 = remapindex_7 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4565 = remapindex_7 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4566 = remapindex_7 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4567 = remapindex_7 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4568 = remapindex_7 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4569 = remapindex_7 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4570 = remapindex_7 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4571 = remapindex_7 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4572 = remapindex_7 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4573 = remapindex_7 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4574 = remapindex_7 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4575 = remapindex_7 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4576 = remapindex_7 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4577 = remapindex_7 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4578 = remapindex_7 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4579 = remapindex_7 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4580 = remapindex_7 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4581 = remapindex_7 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4582 = remapindex_7 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4583 = remapindex_7 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4584 = remapindex_7 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4585 = remapindex_7 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4586 = remapindex_7 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4587 = remapindex_7 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4588 = remapindex_7 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4589 = remapindex_7 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4590 = remapindex_7 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4591 = remapindex_7 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4592 = remapindex_7 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_7 = _T_4592 ? _Queue16_UInt8_31_io_deq_bits : _T_4591 ? _Queue16_UInt8_30_io_deq_bits : _T_4590 ? _Queue16_UInt8_29_io_deq_bits : _T_4589 ? _Queue16_UInt8_28_io_deq_bits : _T_4588 ? _Queue16_UInt8_27_io_deq_bits : _T_4587 ? _Queue16_UInt8_26_io_deq_bits : _T_4586 ? _Queue16_UInt8_25_io_deq_bits : _T_4585 ? _Queue16_UInt8_24_io_deq_bits : _T_4584 ? _Queue16_UInt8_23_io_deq_bits : _T_4583 ? _Queue16_UInt8_22_io_deq_bits : _T_4582 ? _Queue16_UInt8_21_io_deq_bits : _T_4581 ? _Queue16_UInt8_20_io_deq_bits : _T_4580 ? _Queue16_UInt8_19_io_deq_bits : _T_4579 ? _Queue16_UInt8_18_io_deq_bits : _T_4578 ? _Queue16_UInt8_17_io_deq_bits : _T_4577 ? _Queue16_UInt8_16_io_deq_bits : _T_4576 ? _Queue16_UInt8_15_io_deq_bits : _T_4575 ? _Queue16_UInt8_14_io_deq_bits : _T_4574 ? _Queue16_UInt8_13_io_deq_bits : _T_4573 ? _Queue16_UInt8_12_io_deq_bits : _T_4572 ? _Queue16_UInt8_11_io_deq_bits : _T_4571 ? _Queue16_UInt8_10_io_deq_bits : _T_4570 ? _Queue16_UInt8_9_io_deq_bits : _T_4569 ? _Queue16_UInt8_8_io_deq_bits : _T_4568 ? _Queue16_UInt8_7_io_deq_bits : _T_4567 ? _Queue16_UInt8_6_io_deq_bits : _T_4566 ? _Queue16_UInt8_5_io_deq_bits : _T_4565 ? _Queue16_UInt8_4_io_deq_bits : _T_4564 ? _Queue16_UInt8_3_io_deq_bits : _T_4563 ? _Queue16_UInt8_2_io_deq_bits : _T_4562 ? _Queue16_UInt8_1_io_deq_bits : _T_4561 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_7 = _T_4592 ? _Queue16_UInt8_31_io_deq_valid : _T_4591 ? _Queue16_UInt8_30_io_deq_valid : _T_4590 ? _Queue16_UInt8_29_io_deq_valid : _T_4589 ? _Queue16_UInt8_28_io_deq_valid : _T_4588 ? _Queue16_UInt8_27_io_deq_valid : _T_4587 ? _Queue16_UInt8_26_io_deq_valid : _T_4586 ? _Queue16_UInt8_25_io_deq_valid : _T_4585 ? _Queue16_UInt8_24_io_deq_valid : _T_4584 ? _Queue16_UInt8_23_io_deq_valid : _T_4583 ? _Queue16_UInt8_22_io_deq_valid : _T_4582 ? _Queue16_UInt8_21_io_deq_valid : _T_4581 ? _Queue16_UInt8_20_io_deq_valid : _T_4580 ? _Queue16_UInt8_19_io_deq_valid : _T_4579 ? _Queue16_UInt8_18_io_deq_valid : _T_4578 ? _Queue16_UInt8_17_io_deq_valid : _T_4577 ? _Queue16_UInt8_16_io_deq_valid : _T_4576 ? _Queue16_UInt8_15_io_deq_valid : _T_4575 ? _Queue16_UInt8_14_io_deq_valid : _T_4574 ? _Queue16_UInt8_13_io_deq_valid : _T_4573 ? _Queue16_UInt8_12_io_deq_valid : _T_4572 ? _Queue16_UInt8_11_io_deq_valid : _T_4571 ? _Queue16_UInt8_10_io_deq_valid : _T_4570 ? _Queue16_UInt8_9_io_deq_valid : _T_4569 ? _Queue16_UInt8_8_io_deq_valid : _T_4568 ? _Queue16_UInt8_7_io_deq_valid : _T_4567 ? _Queue16_UInt8_6_io_deq_valid : _T_4566 ? _Queue16_UInt8_5_io_deq_valid : _T_4565 ? _Queue16_UInt8_4_io_deq_valid : _T_4564 ? _Queue16_UInt8_3_io_deq_valid : _T_4563 ? _Queue16_UInt8_2_io_deq_valid : _T_4562 ? _Queue16_UInt8_1_io_deq_valid : _T_4561 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_8 = _remapindex_T + 7'h8; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_98 = _remapindex_T_8 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_8 = _GEN_98[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4593 = remapindex_8 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4594 = remapindex_8 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4595 = remapindex_8 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4596 = remapindex_8 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4597 = remapindex_8 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4598 = remapindex_8 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4599 = remapindex_8 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4600 = remapindex_8 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4601 = remapindex_8 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4602 = remapindex_8 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4603 = remapindex_8 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4604 = remapindex_8 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4605 = remapindex_8 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4606 = remapindex_8 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4607 = remapindex_8 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4608 = remapindex_8 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4609 = remapindex_8 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4610 = remapindex_8 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4611 = remapindex_8 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4612 = remapindex_8 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4613 = remapindex_8 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4614 = remapindex_8 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4615 = remapindex_8 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4616 = remapindex_8 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4617 = remapindex_8 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4618 = remapindex_8 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4619 = remapindex_8 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4620 = remapindex_8 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4621 = remapindex_8 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4622 = remapindex_8 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4623 = remapindex_8 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4624 = remapindex_8 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_8 = _T_4624 ? _Queue16_UInt8_31_io_deq_bits : _T_4623 ? _Queue16_UInt8_30_io_deq_bits : _T_4622 ? _Queue16_UInt8_29_io_deq_bits : _T_4621 ? _Queue16_UInt8_28_io_deq_bits : _T_4620 ? _Queue16_UInt8_27_io_deq_bits : _T_4619 ? _Queue16_UInt8_26_io_deq_bits : _T_4618 ? _Queue16_UInt8_25_io_deq_bits : _T_4617 ? _Queue16_UInt8_24_io_deq_bits : _T_4616 ? _Queue16_UInt8_23_io_deq_bits : _T_4615 ? _Queue16_UInt8_22_io_deq_bits : _T_4614 ? _Queue16_UInt8_21_io_deq_bits : _T_4613 ? _Queue16_UInt8_20_io_deq_bits : _T_4612 ? _Queue16_UInt8_19_io_deq_bits : _T_4611 ? _Queue16_UInt8_18_io_deq_bits : _T_4610 ? _Queue16_UInt8_17_io_deq_bits : _T_4609 ? _Queue16_UInt8_16_io_deq_bits : _T_4608 ? _Queue16_UInt8_15_io_deq_bits : _T_4607 ? _Queue16_UInt8_14_io_deq_bits : _T_4606 ? _Queue16_UInt8_13_io_deq_bits : _T_4605 ? _Queue16_UInt8_12_io_deq_bits : _T_4604 ? _Queue16_UInt8_11_io_deq_bits : _T_4603 ? _Queue16_UInt8_10_io_deq_bits : _T_4602 ? _Queue16_UInt8_9_io_deq_bits : _T_4601 ? _Queue16_UInt8_8_io_deq_bits : _T_4600 ? _Queue16_UInt8_7_io_deq_bits : _T_4599 ? _Queue16_UInt8_6_io_deq_bits : _T_4598 ? _Queue16_UInt8_5_io_deq_bits : _T_4597 ? _Queue16_UInt8_4_io_deq_bits : _T_4596 ? _Queue16_UInt8_3_io_deq_bits : _T_4595 ? _Queue16_UInt8_2_io_deq_bits : _T_4594 ? _Queue16_UInt8_1_io_deq_bits : _T_4593 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_8 = _T_4624 ? _Queue16_UInt8_31_io_deq_valid : _T_4623 ? _Queue16_UInt8_30_io_deq_valid : _T_4622 ? _Queue16_UInt8_29_io_deq_valid : _T_4621 ? _Queue16_UInt8_28_io_deq_valid : _T_4620 ? _Queue16_UInt8_27_io_deq_valid : _T_4619 ? _Queue16_UInt8_26_io_deq_valid : _T_4618 ? _Queue16_UInt8_25_io_deq_valid : _T_4617 ? _Queue16_UInt8_24_io_deq_valid : _T_4616 ? _Queue16_UInt8_23_io_deq_valid : _T_4615 ? _Queue16_UInt8_22_io_deq_valid : _T_4614 ? _Queue16_UInt8_21_io_deq_valid : _T_4613 ? _Queue16_UInt8_20_io_deq_valid : _T_4612 ? _Queue16_UInt8_19_io_deq_valid : _T_4611 ? _Queue16_UInt8_18_io_deq_valid : _T_4610 ? _Queue16_UInt8_17_io_deq_valid : _T_4609 ? _Queue16_UInt8_16_io_deq_valid : _T_4608 ? _Queue16_UInt8_15_io_deq_valid : _T_4607 ? _Queue16_UInt8_14_io_deq_valid : _T_4606 ? _Queue16_UInt8_13_io_deq_valid : _T_4605 ? _Queue16_UInt8_12_io_deq_valid : _T_4604 ? _Queue16_UInt8_11_io_deq_valid : _T_4603 ? _Queue16_UInt8_10_io_deq_valid : _T_4602 ? _Queue16_UInt8_9_io_deq_valid : _T_4601 ? _Queue16_UInt8_8_io_deq_valid : _T_4600 ? _Queue16_UInt8_7_io_deq_valid : _T_4599 ? _Queue16_UInt8_6_io_deq_valid : _T_4598 ? _Queue16_UInt8_5_io_deq_valid : _T_4597 ? _Queue16_UInt8_4_io_deq_valid : _T_4596 ? _Queue16_UInt8_3_io_deq_valid : _T_4595 ? _Queue16_UInt8_2_io_deq_valid : _T_4594 ? _Queue16_UInt8_1_io_deq_valid : _T_4593 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_9 = _remapindex_T + 7'h9; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_99 = _remapindex_T_9 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_9 = _GEN_99[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4625 = remapindex_9 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4626 = remapindex_9 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4627 = remapindex_9 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4628 = remapindex_9 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4629 = remapindex_9 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4630 = remapindex_9 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4631 = remapindex_9 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4632 = remapindex_9 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4633 = remapindex_9 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4634 = remapindex_9 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4635 = remapindex_9 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4636 = remapindex_9 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4637 = remapindex_9 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4638 = remapindex_9 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4639 = remapindex_9 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4640 = remapindex_9 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4641 = remapindex_9 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4642 = remapindex_9 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4643 = remapindex_9 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4644 = remapindex_9 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4645 = remapindex_9 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4646 = remapindex_9 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4647 = remapindex_9 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4648 = remapindex_9 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4649 = remapindex_9 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4650 = remapindex_9 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4651 = remapindex_9 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4652 = remapindex_9 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4653 = remapindex_9 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4654 = remapindex_9 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4655 = remapindex_9 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4656 = remapindex_9 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_9 = _T_4656 ? _Queue16_UInt8_31_io_deq_bits : _T_4655 ? _Queue16_UInt8_30_io_deq_bits : _T_4654 ? _Queue16_UInt8_29_io_deq_bits : _T_4653 ? _Queue16_UInt8_28_io_deq_bits : _T_4652 ? _Queue16_UInt8_27_io_deq_bits : _T_4651 ? _Queue16_UInt8_26_io_deq_bits : _T_4650 ? _Queue16_UInt8_25_io_deq_bits : _T_4649 ? _Queue16_UInt8_24_io_deq_bits : _T_4648 ? _Queue16_UInt8_23_io_deq_bits : _T_4647 ? _Queue16_UInt8_22_io_deq_bits : _T_4646 ? _Queue16_UInt8_21_io_deq_bits : _T_4645 ? _Queue16_UInt8_20_io_deq_bits : _T_4644 ? _Queue16_UInt8_19_io_deq_bits : _T_4643 ? _Queue16_UInt8_18_io_deq_bits : _T_4642 ? _Queue16_UInt8_17_io_deq_bits : _T_4641 ? _Queue16_UInt8_16_io_deq_bits : _T_4640 ? _Queue16_UInt8_15_io_deq_bits : _T_4639 ? _Queue16_UInt8_14_io_deq_bits : _T_4638 ? _Queue16_UInt8_13_io_deq_bits : _T_4637 ? _Queue16_UInt8_12_io_deq_bits : _T_4636 ? _Queue16_UInt8_11_io_deq_bits : _T_4635 ? _Queue16_UInt8_10_io_deq_bits : _T_4634 ? _Queue16_UInt8_9_io_deq_bits : _T_4633 ? _Queue16_UInt8_8_io_deq_bits : _T_4632 ? _Queue16_UInt8_7_io_deq_bits : _T_4631 ? _Queue16_UInt8_6_io_deq_bits : _T_4630 ? _Queue16_UInt8_5_io_deq_bits : _T_4629 ? _Queue16_UInt8_4_io_deq_bits : _T_4628 ? _Queue16_UInt8_3_io_deq_bits : _T_4627 ? _Queue16_UInt8_2_io_deq_bits : _T_4626 ? _Queue16_UInt8_1_io_deq_bits : _T_4625 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_9 = _T_4656 ? _Queue16_UInt8_31_io_deq_valid : _T_4655 ? _Queue16_UInt8_30_io_deq_valid : _T_4654 ? _Queue16_UInt8_29_io_deq_valid : _T_4653 ? _Queue16_UInt8_28_io_deq_valid : _T_4652 ? _Queue16_UInt8_27_io_deq_valid : _T_4651 ? _Queue16_UInt8_26_io_deq_valid : _T_4650 ? _Queue16_UInt8_25_io_deq_valid : _T_4649 ? _Queue16_UInt8_24_io_deq_valid : _T_4648 ? _Queue16_UInt8_23_io_deq_valid : _T_4647 ? _Queue16_UInt8_22_io_deq_valid : _T_4646 ? _Queue16_UInt8_21_io_deq_valid : _T_4645 ? _Queue16_UInt8_20_io_deq_valid : _T_4644 ? _Queue16_UInt8_19_io_deq_valid : _T_4643 ? _Queue16_UInt8_18_io_deq_valid : _T_4642 ? _Queue16_UInt8_17_io_deq_valid : _T_4641 ? _Queue16_UInt8_16_io_deq_valid : _T_4640 ? _Queue16_UInt8_15_io_deq_valid : _T_4639 ? _Queue16_UInt8_14_io_deq_valid : _T_4638 ? _Queue16_UInt8_13_io_deq_valid : _T_4637 ? _Queue16_UInt8_12_io_deq_valid : _T_4636 ? _Queue16_UInt8_11_io_deq_valid : _T_4635 ? _Queue16_UInt8_10_io_deq_valid : _T_4634 ? _Queue16_UInt8_9_io_deq_valid : _T_4633 ? _Queue16_UInt8_8_io_deq_valid : _T_4632 ? _Queue16_UInt8_7_io_deq_valid : _T_4631 ? _Queue16_UInt8_6_io_deq_valid : _T_4630 ? _Queue16_UInt8_5_io_deq_valid : _T_4629 ? _Queue16_UInt8_4_io_deq_valid : _T_4628 ? _Queue16_UInt8_3_io_deq_valid : _T_4627 ? _Queue16_UInt8_2_io_deq_valid : _T_4626 ? _Queue16_UInt8_1_io_deq_valid : _T_4625 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_10 = _remapindex_T + 7'hA; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_100 = _remapindex_T_10 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_10 = _GEN_100[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4657 = remapindex_10 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4658 = remapindex_10 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4659 = remapindex_10 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4660 = remapindex_10 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4661 = remapindex_10 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4662 = remapindex_10 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4663 = remapindex_10 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4664 = remapindex_10 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4665 = remapindex_10 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4666 = remapindex_10 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4667 = remapindex_10 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4668 = remapindex_10 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4669 = remapindex_10 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4670 = remapindex_10 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4671 = remapindex_10 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4672 = remapindex_10 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4673 = remapindex_10 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4674 = remapindex_10 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4675 = remapindex_10 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4676 = remapindex_10 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4677 = remapindex_10 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4678 = remapindex_10 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4679 = remapindex_10 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4680 = remapindex_10 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4681 = remapindex_10 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4682 = remapindex_10 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4683 = remapindex_10 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4684 = remapindex_10 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4685 = remapindex_10 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4686 = remapindex_10 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4687 = remapindex_10 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4688 = remapindex_10 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_10 = _T_4688 ? _Queue16_UInt8_31_io_deq_bits : _T_4687 ? _Queue16_UInt8_30_io_deq_bits : _T_4686 ? _Queue16_UInt8_29_io_deq_bits : _T_4685 ? _Queue16_UInt8_28_io_deq_bits : _T_4684 ? _Queue16_UInt8_27_io_deq_bits : _T_4683 ? _Queue16_UInt8_26_io_deq_bits : _T_4682 ? _Queue16_UInt8_25_io_deq_bits : _T_4681 ? _Queue16_UInt8_24_io_deq_bits : _T_4680 ? _Queue16_UInt8_23_io_deq_bits : _T_4679 ? _Queue16_UInt8_22_io_deq_bits : _T_4678 ? _Queue16_UInt8_21_io_deq_bits : _T_4677 ? _Queue16_UInt8_20_io_deq_bits : _T_4676 ? _Queue16_UInt8_19_io_deq_bits : _T_4675 ? _Queue16_UInt8_18_io_deq_bits : _T_4674 ? _Queue16_UInt8_17_io_deq_bits : _T_4673 ? _Queue16_UInt8_16_io_deq_bits : _T_4672 ? _Queue16_UInt8_15_io_deq_bits : _T_4671 ? _Queue16_UInt8_14_io_deq_bits : _T_4670 ? _Queue16_UInt8_13_io_deq_bits : _T_4669 ? _Queue16_UInt8_12_io_deq_bits : _T_4668 ? _Queue16_UInt8_11_io_deq_bits : _T_4667 ? _Queue16_UInt8_10_io_deq_bits : _T_4666 ? _Queue16_UInt8_9_io_deq_bits : _T_4665 ? _Queue16_UInt8_8_io_deq_bits : _T_4664 ? _Queue16_UInt8_7_io_deq_bits : _T_4663 ? _Queue16_UInt8_6_io_deq_bits : _T_4662 ? _Queue16_UInt8_5_io_deq_bits : _T_4661 ? _Queue16_UInt8_4_io_deq_bits : _T_4660 ? _Queue16_UInt8_3_io_deq_bits : _T_4659 ? _Queue16_UInt8_2_io_deq_bits : _T_4658 ? _Queue16_UInt8_1_io_deq_bits : _T_4657 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_10 = _T_4688 ? _Queue16_UInt8_31_io_deq_valid : _T_4687 ? _Queue16_UInt8_30_io_deq_valid : _T_4686 ? _Queue16_UInt8_29_io_deq_valid : _T_4685 ? _Queue16_UInt8_28_io_deq_valid : _T_4684 ? _Queue16_UInt8_27_io_deq_valid : _T_4683 ? _Queue16_UInt8_26_io_deq_valid : _T_4682 ? _Queue16_UInt8_25_io_deq_valid : _T_4681 ? _Queue16_UInt8_24_io_deq_valid : _T_4680 ? _Queue16_UInt8_23_io_deq_valid : _T_4679 ? _Queue16_UInt8_22_io_deq_valid : _T_4678 ? _Queue16_UInt8_21_io_deq_valid : _T_4677 ? _Queue16_UInt8_20_io_deq_valid : _T_4676 ? _Queue16_UInt8_19_io_deq_valid : _T_4675 ? _Queue16_UInt8_18_io_deq_valid : _T_4674 ? _Queue16_UInt8_17_io_deq_valid : _T_4673 ? _Queue16_UInt8_16_io_deq_valid : _T_4672 ? _Queue16_UInt8_15_io_deq_valid : _T_4671 ? _Queue16_UInt8_14_io_deq_valid : _T_4670 ? _Queue16_UInt8_13_io_deq_valid : _T_4669 ? _Queue16_UInt8_12_io_deq_valid : _T_4668 ? _Queue16_UInt8_11_io_deq_valid : _T_4667 ? _Queue16_UInt8_10_io_deq_valid : _T_4666 ? _Queue16_UInt8_9_io_deq_valid : _T_4665 ? _Queue16_UInt8_8_io_deq_valid : _T_4664 ? _Queue16_UInt8_7_io_deq_valid : _T_4663 ? _Queue16_UInt8_6_io_deq_valid : _T_4662 ? _Queue16_UInt8_5_io_deq_valid : _T_4661 ? _Queue16_UInt8_4_io_deq_valid : _T_4660 ? _Queue16_UInt8_3_io_deq_valid : _T_4659 ? _Queue16_UInt8_2_io_deq_valid : _T_4658 ? _Queue16_UInt8_1_io_deq_valid : _T_4657 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_11 = _remapindex_T + 7'hB; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_101 = _remapindex_T_11 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_11 = _GEN_101[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4689 = remapindex_11 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4690 = remapindex_11 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4691 = remapindex_11 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4692 = remapindex_11 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4693 = remapindex_11 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4694 = remapindex_11 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4695 = remapindex_11 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4696 = remapindex_11 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4697 = remapindex_11 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4698 = remapindex_11 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4699 = remapindex_11 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4700 = remapindex_11 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4701 = remapindex_11 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4702 = remapindex_11 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4703 = remapindex_11 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4704 = remapindex_11 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4705 = remapindex_11 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4706 = remapindex_11 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4707 = remapindex_11 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4708 = remapindex_11 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4709 = remapindex_11 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4710 = remapindex_11 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4711 = remapindex_11 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4712 = remapindex_11 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4713 = remapindex_11 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4714 = remapindex_11 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4715 = remapindex_11 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4716 = remapindex_11 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4717 = remapindex_11 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4718 = remapindex_11 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4719 = remapindex_11 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4720 = remapindex_11 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_11 = _T_4720 ? _Queue16_UInt8_31_io_deq_bits : _T_4719 ? _Queue16_UInt8_30_io_deq_bits : _T_4718 ? _Queue16_UInt8_29_io_deq_bits : _T_4717 ? _Queue16_UInt8_28_io_deq_bits : _T_4716 ? _Queue16_UInt8_27_io_deq_bits : _T_4715 ? _Queue16_UInt8_26_io_deq_bits : _T_4714 ? _Queue16_UInt8_25_io_deq_bits : _T_4713 ? _Queue16_UInt8_24_io_deq_bits : _T_4712 ? _Queue16_UInt8_23_io_deq_bits : _T_4711 ? _Queue16_UInt8_22_io_deq_bits : _T_4710 ? _Queue16_UInt8_21_io_deq_bits : _T_4709 ? _Queue16_UInt8_20_io_deq_bits : _T_4708 ? _Queue16_UInt8_19_io_deq_bits : _T_4707 ? _Queue16_UInt8_18_io_deq_bits : _T_4706 ? _Queue16_UInt8_17_io_deq_bits : _T_4705 ? _Queue16_UInt8_16_io_deq_bits : _T_4704 ? _Queue16_UInt8_15_io_deq_bits : _T_4703 ? _Queue16_UInt8_14_io_deq_bits : _T_4702 ? _Queue16_UInt8_13_io_deq_bits : _T_4701 ? _Queue16_UInt8_12_io_deq_bits : _T_4700 ? _Queue16_UInt8_11_io_deq_bits : _T_4699 ? _Queue16_UInt8_10_io_deq_bits : _T_4698 ? _Queue16_UInt8_9_io_deq_bits : _T_4697 ? _Queue16_UInt8_8_io_deq_bits : _T_4696 ? _Queue16_UInt8_7_io_deq_bits : _T_4695 ? _Queue16_UInt8_6_io_deq_bits : _T_4694 ? _Queue16_UInt8_5_io_deq_bits : _T_4693 ? _Queue16_UInt8_4_io_deq_bits : _T_4692 ? _Queue16_UInt8_3_io_deq_bits : _T_4691 ? _Queue16_UInt8_2_io_deq_bits : _T_4690 ? _Queue16_UInt8_1_io_deq_bits : _T_4689 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_11 = _T_4720 ? _Queue16_UInt8_31_io_deq_valid : _T_4719 ? _Queue16_UInt8_30_io_deq_valid : _T_4718 ? _Queue16_UInt8_29_io_deq_valid : _T_4717 ? _Queue16_UInt8_28_io_deq_valid : _T_4716 ? _Queue16_UInt8_27_io_deq_valid : _T_4715 ? _Queue16_UInt8_26_io_deq_valid : _T_4714 ? _Queue16_UInt8_25_io_deq_valid : _T_4713 ? _Queue16_UInt8_24_io_deq_valid : _T_4712 ? _Queue16_UInt8_23_io_deq_valid : _T_4711 ? _Queue16_UInt8_22_io_deq_valid : _T_4710 ? _Queue16_UInt8_21_io_deq_valid : _T_4709 ? _Queue16_UInt8_20_io_deq_valid : _T_4708 ? _Queue16_UInt8_19_io_deq_valid : _T_4707 ? _Queue16_UInt8_18_io_deq_valid : _T_4706 ? _Queue16_UInt8_17_io_deq_valid : _T_4705 ? _Queue16_UInt8_16_io_deq_valid : _T_4704 ? _Queue16_UInt8_15_io_deq_valid : _T_4703 ? _Queue16_UInt8_14_io_deq_valid : _T_4702 ? _Queue16_UInt8_13_io_deq_valid : _T_4701 ? _Queue16_UInt8_12_io_deq_valid : _T_4700 ? _Queue16_UInt8_11_io_deq_valid : _T_4699 ? _Queue16_UInt8_10_io_deq_valid : _T_4698 ? _Queue16_UInt8_9_io_deq_valid : _T_4697 ? _Queue16_UInt8_8_io_deq_valid : _T_4696 ? _Queue16_UInt8_7_io_deq_valid : _T_4695 ? _Queue16_UInt8_6_io_deq_valid : _T_4694 ? _Queue16_UInt8_5_io_deq_valid : _T_4693 ? _Queue16_UInt8_4_io_deq_valid : _T_4692 ? _Queue16_UInt8_3_io_deq_valid : _T_4691 ? _Queue16_UInt8_2_io_deq_valid : _T_4690 ? _Queue16_UInt8_1_io_deq_valid : _T_4689 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_12 = _remapindex_T + 7'hC; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_102 = _remapindex_T_12 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_12 = _GEN_102[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4721 = remapindex_12 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4722 = remapindex_12 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4723 = remapindex_12 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4724 = remapindex_12 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4725 = remapindex_12 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4726 = remapindex_12 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4727 = remapindex_12 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4728 = remapindex_12 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4729 = remapindex_12 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4730 = remapindex_12 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4731 = remapindex_12 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4732 = remapindex_12 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4733 = remapindex_12 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4734 = remapindex_12 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4735 = remapindex_12 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4736 = remapindex_12 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4737 = remapindex_12 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4738 = remapindex_12 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4739 = remapindex_12 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4740 = remapindex_12 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4741 = remapindex_12 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4742 = remapindex_12 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4743 = remapindex_12 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4744 = remapindex_12 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4745 = remapindex_12 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4746 = remapindex_12 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4747 = remapindex_12 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4748 = remapindex_12 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4749 = remapindex_12 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4750 = remapindex_12 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4751 = remapindex_12 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4752 = remapindex_12 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_12 = _T_4752 ? _Queue16_UInt8_31_io_deq_bits : _T_4751 ? _Queue16_UInt8_30_io_deq_bits : _T_4750 ? _Queue16_UInt8_29_io_deq_bits : _T_4749 ? _Queue16_UInt8_28_io_deq_bits : _T_4748 ? _Queue16_UInt8_27_io_deq_bits : _T_4747 ? _Queue16_UInt8_26_io_deq_bits : _T_4746 ? _Queue16_UInt8_25_io_deq_bits : _T_4745 ? _Queue16_UInt8_24_io_deq_bits : _T_4744 ? _Queue16_UInt8_23_io_deq_bits : _T_4743 ? _Queue16_UInt8_22_io_deq_bits : _T_4742 ? _Queue16_UInt8_21_io_deq_bits : _T_4741 ? _Queue16_UInt8_20_io_deq_bits : _T_4740 ? _Queue16_UInt8_19_io_deq_bits : _T_4739 ? _Queue16_UInt8_18_io_deq_bits : _T_4738 ? _Queue16_UInt8_17_io_deq_bits : _T_4737 ? _Queue16_UInt8_16_io_deq_bits : _T_4736 ? _Queue16_UInt8_15_io_deq_bits : _T_4735 ? _Queue16_UInt8_14_io_deq_bits : _T_4734 ? _Queue16_UInt8_13_io_deq_bits : _T_4733 ? _Queue16_UInt8_12_io_deq_bits : _T_4732 ? _Queue16_UInt8_11_io_deq_bits : _T_4731 ? _Queue16_UInt8_10_io_deq_bits : _T_4730 ? _Queue16_UInt8_9_io_deq_bits : _T_4729 ? _Queue16_UInt8_8_io_deq_bits : _T_4728 ? _Queue16_UInt8_7_io_deq_bits : _T_4727 ? _Queue16_UInt8_6_io_deq_bits : _T_4726 ? _Queue16_UInt8_5_io_deq_bits : _T_4725 ? _Queue16_UInt8_4_io_deq_bits : _T_4724 ? _Queue16_UInt8_3_io_deq_bits : _T_4723 ? _Queue16_UInt8_2_io_deq_bits : _T_4722 ? _Queue16_UInt8_1_io_deq_bits : _T_4721 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_12 = _T_4752 ? _Queue16_UInt8_31_io_deq_valid : _T_4751 ? _Queue16_UInt8_30_io_deq_valid : _T_4750 ? _Queue16_UInt8_29_io_deq_valid : _T_4749 ? _Queue16_UInt8_28_io_deq_valid : _T_4748 ? _Queue16_UInt8_27_io_deq_valid : _T_4747 ? _Queue16_UInt8_26_io_deq_valid : _T_4746 ? _Queue16_UInt8_25_io_deq_valid : _T_4745 ? _Queue16_UInt8_24_io_deq_valid : _T_4744 ? _Queue16_UInt8_23_io_deq_valid : _T_4743 ? _Queue16_UInt8_22_io_deq_valid : _T_4742 ? _Queue16_UInt8_21_io_deq_valid : _T_4741 ? _Queue16_UInt8_20_io_deq_valid : _T_4740 ? _Queue16_UInt8_19_io_deq_valid : _T_4739 ? _Queue16_UInt8_18_io_deq_valid : _T_4738 ? _Queue16_UInt8_17_io_deq_valid : _T_4737 ? _Queue16_UInt8_16_io_deq_valid : _T_4736 ? _Queue16_UInt8_15_io_deq_valid : _T_4735 ? _Queue16_UInt8_14_io_deq_valid : _T_4734 ? _Queue16_UInt8_13_io_deq_valid : _T_4733 ? _Queue16_UInt8_12_io_deq_valid : _T_4732 ? _Queue16_UInt8_11_io_deq_valid : _T_4731 ? _Queue16_UInt8_10_io_deq_valid : _T_4730 ? _Queue16_UInt8_9_io_deq_valid : _T_4729 ? _Queue16_UInt8_8_io_deq_valid : _T_4728 ? _Queue16_UInt8_7_io_deq_valid : _T_4727 ? _Queue16_UInt8_6_io_deq_valid : _T_4726 ? _Queue16_UInt8_5_io_deq_valid : _T_4725 ? _Queue16_UInt8_4_io_deq_valid : _T_4724 ? _Queue16_UInt8_3_io_deq_valid : _T_4723 ? _Queue16_UInt8_2_io_deq_valid : _T_4722 ? _Queue16_UInt8_1_io_deq_valid : _T_4721 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_13 = _remapindex_T + 7'hD; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_103 = _remapindex_T_13 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_13 = _GEN_103[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4753 = remapindex_13 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4754 = remapindex_13 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4755 = remapindex_13 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4756 = remapindex_13 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4757 = remapindex_13 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4758 = remapindex_13 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4759 = remapindex_13 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4760 = remapindex_13 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4761 = remapindex_13 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4762 = remapindex_13 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4763 = remapindex_13 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4764 = remapindex_13 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4765 = remapindex_13 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4766 = remapindex_13 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4767 = remapindex_13 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4768 = remapindex_13 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4769 = remapindex_13 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4770 = remapindex_13 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4771 = remapindex_13 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4772 = remapindex_13 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4773 = remapindex_13 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4774 = remapindex_13 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4775 = remapindex_13 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4776 = remapindex_13 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4777 = remapindex_13 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4778 = remapindex_13 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4779 = remapindex_13 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4780 = remapindex_13 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4781 = remapindex_13 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4782 = remapindex_13 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4783 = remapindex_13 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4784 = remapindex_13 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_13 = _T_4784 ? _Queue16_UInt8_31_io_deq_bits : _T_4783 ? _Queue16_UInt8_30_io_deq_bits : _T_4782 ? _Queue16_UInt8_29_io_deq_bits : _T_4781 ? _Queue16_UInt8_28_io_deq_bits : _T_4780 ? _Queue16_UInt8_27_io_deq_bits : _T_4779 ? _Queue16_UInt8_26_io_deq_bits : _T_4778 ? _Queue16_UInt8_25_io_deq_bits : _T_4777 ? _Queue16_UInt8_24_io_deq_bits : _T_4776 ? _Queue16_UInt8_23_io_deq_bits : _T_4775 ? _Queue16_UInt8_22_io_deq_bits : _T_4774 ? _Queue16_UInt8_21_io_deq_bits : _T_4773 ? _Queue16_UInt8_20_io_deq_bits : _T_4772 ? _Queue16_UInt8_19_io_deq_bits : _T_4771 ? _Queue16_UInt8_18_io_deq_bits : _T_4770 ? _Queue16_UInt8_17_io_deq_bits : _T_4769 ? _Queue16_UInt8_16_io_deq_bits : _T_4768 ? _Queue16_UInt8_15_io_deq_bits : _T_4767 ? _Queue16_UInt8_14_io_deq_bits : _T_4766 ? _Queue16_UInt8_13_io_deq_bits : _T_4765 ? _Queue16_UInt8_12_io_deq_bits : _T_4764 ? _Queue16_UInt8_11_io_deq_bits : _T_4763 ? _Queue16_UInt8_10_io_deq_bits : _T_4762 ? _Queue16_UInt8_9_io_deq_bits : _T_4761 ? _Queue16_UInt8_8_io_deq_bits : _T_4760 ? _Queue16_UInt8_7_io_deq_bits : _T_4759 ? _Queue16_UInt8_6_io_deq_bits : _T_4758 ? _Queue16_UInt8_5_io_deq_bits : _T_4757 ? _Queue16_UInt8_4_io_deq_bits : _T_4756 ? _Queue16_UInt8_3_io_deq_bits : _T_4755 ? _Queue16_UInt8_2_io_deq_bits : _T_4754 ? _Queue16_UInt8_1_io_deq_bits : _T_4753 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_13 = _T_4784 ? _Queue16_UInt8_31_io_deq_valid : _T_4783 ? _Queue16_UInt8_30_io_deq_valid : _T_4782 ? _Queue16_UInt8_29_io_deq_valid : _T_4781 ? _Queue16_UInt8_28_io_deq_valid : _T_4780 ? _Queue16_UInt8_27_io_deq_valid : _T_4779 ? _Queue16_UInt8_26_io_deq_valid : _T_4778 ? _Queue16_UInt8_25_io_deq_valid : _T_4777 ? _Queue16_UInt8_24_io_deq_valid : _T_4776 ? _Queue16_UInt8_23_io_deq_valid : _T_4775 ? _Queue16_UInt8_22_io_deq_valid : _T_4774 ? _Queue16_UInt8_21_io_deq_valid : _T_4773 ? _Queue16_UInt8_20_io_deq_valid : _T_4772 ? _Queue16_UInt8_19_io_deq_valid : _T_4771 ? _Queue16_UInt8_18_io_deq_valid : _T_4770 ? _Queue16_UInt8_17_io_deq_valid : _T_4769 ? _Queue16_UInt8_16_io_deq_valid : _T_4768 ? _Queue16_UInt8_15_io_deq_valid : _T_4767 ? _Queue16_UInt8_14_io_deq_valid : _T_4766 ? _Queue16_UInt8_13_io_deq_valid : _T_4765 ? _Queue16_UInt8_12_io_deq_valid : _T_4764 ? _Queue16_UInt8_11_io_deq_valid : _T_4763 ? _Queue16_UInt8_10_io_deq_valid : _T_4762 ? _Queue16_UInt8_9_io_deq_valid : _T_4761 ? _Queue16_UInt8_8_io_deq_valid : _T_4760 ? _Queue16_UInt8_7_io_deq_valid : _T_4759 ? _Queue16_UInt8_6_io_deq_valid : _T_4758 ? _Queue16_UInt8_5_io_deq_valid : _T_4757 ? _Queue16_UInt8_4_io_deq_valid : _T_4756 ? _Queue16_UInt8_3_io_deq_valid : _T_4755 ? _Queue16_UInt8_2_io_deq_valid : _T_4754 ? _Queue16_UInt8_1_io_deq_valid : _T_4753 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_14 = _remapindex_T + 7'hE; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_104 = _remapindex_T_14 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_14 = _GEN_104[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4785 = remapindex_14 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4786 = remapindex_14 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4787 = remapindex_14 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4788 = remapindex_14 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4789 = remapindex_14 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4790 = remapindex_14 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4791 = remapindex_14 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4792 = remapindex_14 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4793 = remapindex_14 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4794 = remapindex_14 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4795 = remapindex_14 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4796 = remapindex_14 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4797 = remapindex_14 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4798 = remapindex_14 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4799 = remapindex_14 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4800 = remapindex_14 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4801 = remapindex_14 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4802 = remapindex_14 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4803 = remapindex_14 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4804 = remapindex_14 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4805 = remapindex_14 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4806 = remapindex_14 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4807 = remapindex_14 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4808 = remapindex_14 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4809 = remapindex_14 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4810 = remapindex_14 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4811 = remapindex_14 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4812 = remapindex_14 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4813 = remapindex_14 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4814 = remapindex_14 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4815 = remapindex_14 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4816 = remapindex_14 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_14 = _T_4816 ? _Queue16_UInt8_31_io_deq_bits : _T_4815 ? _Queue16_UInt8_30_io_deq_bits : _T_4814 ? _Queue16_UInt8_29_io_deq_bits : _T_4813 ? _Queue16_UInt8_28_io_deq_bits : _T_4812 ? _Queue16_UInt8_27_io_deq_bits : _T_4811 ? _Queue16_UInt8_26_io_deq_bits : _T_4810 ? _Queue16_UInt8_25_io_deq_bits : _T_4809 ? _Queue16_UInt8_24_io_deq_bits : _T_4808 ? _Queue16_UInt8_23_io_deq_bits : _T_4807 ? _Queue16_UInt8_22_io_deq_bits : _T_4806 ? _Queue16_UInt8_21_io_deq_bits : _T_4805 ? _Queue16_UInt8_20_io_deq_bits : _T_4804 ? _Queue16_UInt8_19_io_deq_bits : _T_4803 ? _Queue16_UInt8_18_io_deq_bits : _T_4802 ? _Queue16_UInt8_17_io_deq_bits : _T_4801 ? _Queue16_UInt8_16_io_deq_bits : _T_4800 ? _Queue16_UInt8_15_io_deq_bits : _T_4799 ? _Queue16_UInt8_14_io_deq_bits : _T_4798 ? _Queue16_UInt8_13_io_deq_bits : _T_4797 ? _Queue16_UInt8_12_io_deq_bits : _T_4796 ? _Queue16_UInt8_11_io_deq_bits : _T_4795 ? _Queue16_UInt8_10_io_deq_bits : _T_4794 ? _Queue16_UInt8_9_io_deq_bits : _T_4793 ? _Queue16_UInt8_8_io_deq_bits : _T_4792 ? _Queue16_UInt8_7_io_deq_bits : _T_4791 ? _Queue16_UInt8_6_io_deq_bits : _T_4790 ? _Queue16_UInt8_5_io_deq_bits : _T_4789 ? _Queue16_UInt8_4_io_deq_bits : _T_4788 ? _Queue16_UInt8_3_io_deq_bits : _T_4787 ? _Queue16_UInt8_2_io_deq_bits : _T_4786 ? _Queue16_UInt8_1_io_deq_bits : _T_4785 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_14 = _T_4816 ? _Queue16_UInt8_31_io_deq_valid : _T_4815 ? _Queue16_UInt8_30_io_deq_valid : _T_4814 ? _Queue16_UInt8_29_io_deq_valid : _T_4813 ? _Queue16_UInt8_28_io_deq_valid : _T_4812 ? _Queue16_UInt8_27_io_deq_valid : _T_4811 ? _Queue16_UInt8_26_io_deq_valid : _T_4810 ? _Queue16_UInt8_25_io_deq_valid : _T_4809 ? _Queue16_UInt8_24_io_deq_valid : _T_4808 ? _Queue16_UInt8_23_io_deq_valid : _T_4807 ? _Queue16_UInt8_22_io_deq_valid : _T_4806 ? _Queue16_UInt8_21_io_deq_valid : _T_4805 ? _Queue16_UInt8_20_io_deq_valid : _T_4804 ? _Queue16_UInt8_19_io_deq_valid : _T_4803 ? _Queue16_UInt8_18_io_deq_valid : _T_4802 ? _Queue16_UInt8_17_io_deq_valid : _T_4801 ? _Queue16_UInt8_16_io_deq_valid : _T_4800 ? _Queue16_UInt8_15_io_deq_valid : _T_4799 ? _Queue16_UInt8_14_io_deq_valid : _T_4798 ? _Queue16_UInt8_13_io_deq_valid : _T_4797 ? _Queue16_UInt8_12_io_deq_valid : _T_4796 ? _Queue16_UInt8_11_io_deq_valid : _T_4795 ? _Queue16_UInt8_10_io_deq_valid : _T_4794 ? _Queue16_UInt8_9_io_deq_valid : _T_4793 ? _Queue16_UInt8_8_io_deq_valid : _T_4792 ? _Queue16_UInt8_7_io_deq_valid : _T_4791 ? _Queue16_UInt8_6_io_deq_valid : _T_4790 ? _Queue16_UInt8_5_io_deq_valid : _T_4789 ? _Queue16_UInt8_4_io_deq_valid : _T_4788 ? _Queue16_UInt8_3_io_deq_valid : _T_4787 ? _Queue16_UInt8_2_io_deq_valid : _T_4786 ? _Queue16_UInt8_1_io_deq_valid : _T_4785 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_15 = _remapindex_T + 7'hF; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_105 = _remapindex_T_15 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_15 = _GEN_105[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4817 = remapindex_15 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4818 = remapindex_15 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4819 = remapindex_15 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4820 = remapindex_15 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4821 = remapindex_15 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4822 = remapindex_15 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4823 = remapindex_15 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4824 = remapindex_15 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4825 = remapindex_15 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4826 = remapindex_15 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4827 = remapindex_15 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4828 = remapindex_15 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4829 = remapindex_15 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4830 = remapindex_15 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4831 = remapindex_15 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4832 = remapindex_15 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4833 = remapindex_15 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4834 = remapindex_15 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4835 = remapindex_15 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4836 = remapindex_15 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4837 = remapindex_15 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4838 = remapindex_15 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4839 = remapindex_15 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4840 = remapindex_15 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4841 = remapindex_15 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4842 = remapindex_15 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4843 = remapindex_15 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4844 = remapindex_15 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4845 = remapindex_15 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4846 = remapindex_15 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4847 = remapindex_15 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4848 = remapindex_15 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_15 = _T_4848 ? _Queue16_UInt8_31_io_deq_bits : _T_4847 ? _Queue16_UInt8_30_io_deq_bits : _T_4846 ? _Queue16_UInt8_29_io_deq_bits : _T_4845 ? _Queue16_UInt8_28_io_deq_bits : _T_4844 ? _Queue16_UInt8_27_io_deq_bits : _T_4843 ? _Queue16_UInt8_26_io_deq_bits : _T_4842 ? _Queue16_UInt8_25_io_deq_bits : _T_4841 ? _Queue16_UInt8_24_io_deq_bits : _T_4840 ? _Queue16_UInt8_23_io_deq_bits : _T_4839 ? _Queue16_UInt8_22_io_deq_bits : _T_4838 ? _Queue16_UInt8_21_io_deq_bits : _T_4837 ? _Queue16_UInt8_20_io_deq_bits : _T_4836 ? _Queue16_UInt8_19_io_deq_bits : _T_4835 ? _Queue16_UInt8_18_io_deq_bits : _T_4834 ? _Queue16_UInt8_17_io_deq_bits : _T_4833 ? _Queue16_UInt8_16_io_deq_bits : _T_4832 ? _Queue16_UInt8_15_io_deq_bits : _T_4831 ? _Queue16_UInt8_14_io_deq_bits : _T_4830 ? _Queue16_UInt8_13_io_deq_bits : _T_4829 ? _Queue16_UInt8_12_io_deq_bits : _T_4828 ? _Queue16_UInt8_11_io_deq_bits : _T_4827 ? _Queue16_UInt8_10_io_deq_bits : _T_4826 ? _Queue16_UInt8_9_io_deq_bits : _T_4825 ? _Queue16_UInt8_8_io_deq_bits : _T_4824 ? _Queue16_UInt8_7_io_deq_bits : _T_4823 ? _Queue16_UInt8_6_io_deq_bits : _T_4822 ? _Queue16_UInt8_5_io_deq_bits : _T_4821 ? _Queue16_UInt8_4_io_deq_bits : _T_4820 ? _Queue16_UInt8_3_io_deq_bits : _T_4819 ? _Queue16_UInt8_2_io_deq_bits : _T_4818 ? _Queue16_UInt8_1_io_deq_bits : _T_4817 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_15 = _T_4848 ? _Queue16_UInt8_31_io_deq_valid : _T_4847 ? _Queue16_UInt8_30_io_deq_valid : _T_4846 ? _Queue16_UInt8_29_io_deq_valid : _T_4845 ? _Queue16_UInt8_28_io_deq_valid : _T_4844 ? _Queue16_UInt8_27_io_deq_valid : _T_4843 ? _Queue16_UInt8_26_io_deq_valid : _T_4842 ? _Queue16_UInt8_25_io_deq_valid : _T_4841 ? _Queue16_UInt8_24_io_deq_valid : _T_4840 ? _Queue16_UInt8_23_io_deq_valid : _T_4839 ? _Queue16_UInt8_22_io_deq_valid : _T_4838 ? _Queue16_UInt8_21_io_deq_valid : _T_4837 ? _Queue16_UInt8_20_io_deq_valid : _T_4836 ? _Queue16_UInt8_19_io_deq_valid : _T_4835 ? _Queue16_UInt8_18_io_deq_valid : _T_4834 ? _Queue16_UInt8_17_io_deq_valid : _T_4833 ? _Queue16_UInt8_16_io_deq_valid : _T_4832 ? _Queue16_UInt8_15_io_deq_valid : _T_4831 ? _Queue16_UInt8_14_io_deq_valid : _T_4830 ? _Queue16_UInt8_13_io_deq_valid : _T_4829 ? _Queue16_UInt8_12_io_deq_valid : _T_4828 ? _Queue16_UInt8_11_io_deq_valid : _T_4827 ? _Queue16_UInt8_10_io_deq_valid : _T_4826 ? _Queue16_UInt8_9_io_deq_valid : _T_4825 ? _Queue16_UInt8_8_io_deq_valid : _T_4824 ? _Queue16_UInt8_7_io_deq_valid : _T_4823 ? _Queue16_UInt8_6_io_deq_valid : _T_4822 ? _Queue16_UInt8_5_io_deq_valid : _T_4821 ? _Queue16_UInt8_4_io_deq_valid : _T_4820 ? _Queue16_UInt8_3_io_deq_valid : _T_4819 ? _Queue16_UInt8_2_io_deq_valid : _T_4818 ? _Queue16_UInt8_1_io_deq_valid : _T_4817 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_16 = _remapindex_T + 7'h10; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_106 = _remapindex_T_16 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_16 = _GEN_106[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4849 = remapindex_16 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4850 = remapindex_16 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4851 = remapindex_16 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4852 = remapindex_16 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4853 = remapindex_16 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4854 = remapindex_16 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4855 = remapindex_16 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4856 = remapindex_16 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4857 = remapindex_16 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4858 = remapindex_16 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4859 = remapindex_16 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4860 = remapindex_16 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4861 = remapindex_16 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4862 = remapindex_16 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4863 = remapindex_16 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4864 = remapindex_16 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4865 = remapindex_16 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4866 = remapindex_16 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4867 = remapindex_16 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4868 = remapindex_16 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4869 = remapindex_16 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4870 = remapindex_16 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4871 = remapindex_16 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4872 = remapindex_16 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4873 = remapindex_16 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4874 = remapindex_16 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4875 = remapindex_16 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4876 = remapindex_16 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4877 = remapindex_16 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4878 = remapindex_16 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4879 = remapindex_16 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4880 = remapindex_16 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_16 = _T_4880 ? _Queue16_UInt8_31_io_deq_bits : _T_4879 ? _Queue16_UInt8_30_io_deq_bits : _T_4878 ? _Queue16_UInt8_29_io_deq_bits : _T_4877 ? _Queue16_UInt8_28_io_deq_bits : _T_4876 ? _Queue16_UInt8_27_io_deq_bits : _T_4875 ? _Queue16_UInt8_26_io_deq_bits : _T_4874 ? _Queue16_UInt8_25_io_deq_bits : _T_4873 ? _Queue16_UInt8_24_io_deq_bits : _T_4872 ? _Queue16_UInt8_23_io_deq_bits : _T_4871 ? _Queue16_UInt8_22_io_deq_bits : _T_4870 ? _Queue16_UInt8_21_io_deq_bits : _T_4869 ? _Queue16_UInt8_20_io_deq_bits : _T_4868 ? _Queue16_UInt8_19_io_deq_bits : _T_4867 ? _Queue16_UInt8_18_io_deq_bits : _T_4866 ? _Queue16_UInt8_17_io_deq_bits : _T_4865 ? _Queue16_UInt8_16_io_deq_bits : _T_4864 ? _Queue16_UInt8_15_io_deq_bits : _T_4863 ? _Queue16_UInt8_14_io_deq_bits : _T_4862 ? _Queue16_UInt8_13_io_deq_bits : _T_4861 ? _Queue16_UInt8_12_io_deq_bits : _T_4860 ? _Queue16_UInt8_11_io_deq_bits : _T_4859 ? _Queue16_UInt8_10_io_deq_bits : _T_4858 ? _Queue16_UInt8_9_io_deq_bits : _T_4857 ? _Queue16_UInt8_8_io_deq_bits : _T_4856 ? _Queue16_UInt8_7_io_deq_bits : _T_4855 ? _Queue16_UInt8_6_io_deq_bits : _T_4854 ? _Queue16_UInt8_5_io_deq_bits : _T_4853 ? _Queue16_UInt8_4_io_deq_bits : _T_4852 ? _Queue16_UInt8_3_io_deq_bits : _T_4851 ? _Queue16_UInt8_2_io_deq_bits : _T_4850 ? _Queue16_UInt8_1_io_deq_bits : _T_4849 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_16 = _T_4880 ? _Queue16_UInt8_31_io_deq_valid : _T_4879 ? _Queue16_UInt8_30_io_deq_valid : _T_4878 ? _Queue16_UInt8_29_io_deq_valid : _T_4877 ? _Queue16_UInt8_28_io_deq_valid : _T_4876 ? _Queue16_UInt8_27_io_deq_valid : _T_4875 ? _Queue16_UInt8_26_io_deq_valid : _T_4874 ? _Queue16_UInt8_25_io_deq_valid : _T_4873 ? _Queue16_UInt8_24_io_deq_valid : _T_4872 ? _Queue16_UInt8_23_io_deq_valid : _T_4871 ? _Queue16_UInt8_22_io_deq_valid : _T_4870 ? _Queue16_UInt8_21_io_deq_valid : _T_4869 ? _Queue16_UInt8_20_io_deq_valid : _T_4868 ? _Queue16_UInt8_19_io_deq_valid : _T_4867 ? _Queue16_UInt8_18_io_deq_valid : _T_4866 ? _Queue16_UInt8_17_io_deq_valid : _T_4865 ? _Queue16_UInt8_16_io_deq_valid : _T_4864 ? _Queue16_UInt8_15_io_deq_valid : _T_4863 ? _Queue16_UInt8_14_io_deq_valid : _T_4862 ? _Queue16_UInt8_13_io_deq_valid : _T_4861 ? _Queue16_UInt8_12_io_deq_valid : _T_4860 ? _Queue16_UInt8_11_io_deq_valid : _T_4859 ? _Queue16_UInt8_10_io_deq_valid : _T_4858 ? _Queue16_UInt8_9_io_deq_valid : _T_4857 ? _Queue16_UInt8_8_io_deq_valid : _T_4856 ? _Queue16_UInt8_7_io_deq_valid : _T_4855 ? _Queue16_UInt8_6_io_deq_valid : _T_4854 ? _Queue16_UInt8_5_io_deq_valid : _T_4853 ? _Queue16_UInt8_4_io_deq_valid : _T_4852 ? _Queue16_UInt8_3_io_deq_valid : _T_4851 ? _Queue16_UInt8_2_io_deq_valid : _T_4850 ? _Queue16_UInt8_1_io_deq_valid : _T_4849 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_17 = _remapindex_T + 7'h11; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_107 = _remapindex_T_17 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_17 = _GEN_107[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4881 = remapindex_17 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4882 = remapindex_17 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4883 = remapindex_17 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4884 = remapindex_17 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4885 = remapindex_17 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4886 = remapindex_17 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4887 = remapindex_17 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4888 = remapindex_17 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4889 = remapindex_17 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4890 = remapindex_17 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4891 = remapindex_17 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4892 = remapindex_17 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4893 = remapindex_17 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4894 = remapindex_17 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4895 = remapindex_17 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4896 = remapindex_17 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4897 = remapindex_17 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4898 = remapindex_17 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4899 = remapindex_17 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4900 = remapindex_17 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4901 = remapindex_17 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4902 = remapindex_17 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4903 = remapindex_17 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4904 = remapindex_17 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4905 = remapindex_17 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4906 = remapindex_17 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4907 = remapindex_17 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4908 = remapindex_17 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4909 = remapindex_17 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4910 = remapindex_17 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4911 = remapindex_17 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4912 = remapindex_17 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_17 = _T_4912 ? _Queue16_UInt8_31_io_deq_bits : _T_4911 ? _Queue16_UInt8_30_io_deq_bits : _T_4910 ? _Queue16_UInt8_29_io_deq_bits : _T_4909 ? _Queue16_UInt8_28_io_deq_bits : _T_4908 ? _Queue16_UInt8_27_io_deq_bits : _T_4907 ? _Queue16_UInt8_26_io_deq_bits : _T_4906 ? _Queue16_UInt8_25_io_deq_bits : _T_4905 ? _Queue16_UInt8_24_io_deq_bits : _T_4904 ? _Queue16_UInt8_23_io_deq_bits : _T_4903 ? _Queue16_UInt8_22_io_deq_bits : _T_4902 ? _Queue16_UInt8_21_io_deq_bits : _T_4901 ? _Queue16_UInt8_20_io_deq_bits : _T_4900 ? _Queue16_UInt8_19_io_deq_bits : _T_4899 ? _Queue16_UInt8_18_io_deq_bits : _T_4898 ? _Queue16_UInt8_17_io_deq_bits : _T_4897 ? _Queue16_UInt8_16_io_deq_bits : _T_4896 ? _Queue16_UInt8_15_io_deq_bits : _T_4895 ? _Queue16_UInt8_14_io_deq_bits : _T_4894 ? _Queue16_UInt8_13_io_deq_bits : _T_4893 ? _Queue16_UInt8_12_io_deq_bits : _T_4892 ? _Queue16_UInt8_11_io_deq_bits : _T_4891 ? _Queue16_UInt8_10_io_deq_bits : _T_4890 ? _Queue16_UInt8_9_io_deq_bits : _T_4889 ? _Queue16_UInt8_8_io_deq_bits : _T_4888 ? _Queue16_UInt8_7_io_deq_bits : _T_4887 ? _Queue16_UInt8_6_io_deq_bits : _T_4886 ? _Queue16_UInt8_5_io_deq_bits : _T_4885 ? _Queue16_UInt8_4_io_deq_bits : _T_4884 ? _Queue16_UInt8_3_io_deq_bits : _T_4883 ? _Queue16_UInt8_2_io_deq_bits : _T_4882 ? _Queue16_UInt8_1_io_deq_bits : _T_4881 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_17 = _T_4912 ? _Queue16_UInt8_31_io_deq_valid : _T_4911 ? _Queue16_UInt8_30_io_deq_valid : _T_4910 ? _Queue16_UInt8_29_io_deq_valid : _T_4909 ? _Queue16_UInt8_28_io_deq_valid : _T_4908 ? _Queue16_UInt8_27_io_deq_valid : _T_4907 ? _Queue16_UInt8_26_io_deq_valid : _T_4906 ? _Queue16_UInt8_25_io_deq_valid : _T_4905 ? _Queue16_UInt8_24_io_deq_valid : _T_4904 ? _Queue16_UInt8_23_io_deq_valid : _T_4903 ? _Queue16_UInt8_22_io_deq_valid : _T_4902 ? _Queue16_UInt8_21_io_deq_valid : _T_4901 ? _Queue16_UInt8_20_io_deq_valid : _T_4900 ? _Queue16_UInt8_19_io_deq_valid : _T_4899 ? _Queue16_UInt8_18_io_deq_valid : _T_4898 ? _Queue16_UInt8_17_io_deq_valid : _T_4897 ? _Queue16_UInt8_16_io_deq_valid : _T_4896 ? _Queue16_UInt8_15_io_deq_valid : _T_4895 ? _Queue16_UInt8_14_io_deq_valid : _T_4894 ? _Queue16_UInt8_13_io_deq_valid : _T_4893 ? _Queue16_UInt8_12_io_deq_valid : _T_4892 ? _Queue16_UInt8_11_io_deq_valid : _T_4891 ? _Queue16_UInt8_10_io_deq_valid : _T_4890 ? _Queue16_UInt8_9_io_deq_valid : _T_4889 ? _Queue16_UInt8_8_io_deq_valid : _T_4888 ? _Queue16_UInt8_7_io_deq_valid : _T_4887 ? _Queue16_UInt8_6_io_deq_valid : _T_4886 ? _Queue16_UInt8_5_io_deq_valid : _T_4885 ? _Queue16_UInt8_4_io_deq_valid : _T_4884 ? _Queue16_UInt8_3_io_deq_valid : _T_4883 ? _Queue16_UInt8_2_io_deq_valid : _T_4882 ? _Queue16_UInt8_1_io_deq_valid : _T_4881 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_18 = _remapindex_T + 7'h12; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_108 = _remapindex_T_18 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_18 = _GEN_108[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4913 = remapindex_18 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4914 = remapindex_18 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4915 = remapindex_18 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4916 = remapindex_18 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4917 = remapindex_18 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4918 = remapindex_18 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4919 = remapindex_18 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4920 = remapindex_18 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4921 = remapindex_18 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4922 = remapindex_18 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4923 = remapindex_18 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4924 = remapindex_18 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4925 = remapindex_18 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4926 = remapindex_18 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4927 = remapindex_18 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4928 = remapindex_18 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4929 = remapindex_18 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4930 = remapindex_18 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4931 = remapindex_18 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4932 = remapindex_18 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4933 = remapindex_18 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4934 = remapindex_18 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4935 = remapindex_18 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4936 = remapindex_18 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4937 = remapindex_18 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4938 = remapindex_18 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4939 = remapindex_18 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4940 = remapindex_18 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4941 = remapindex_18 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4942 = remapindex_18 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4943 = remapindex_18 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4944 = remapindex_18 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_18 = _T_4944 ? _Queue16_UInt8_31_io_deq_bits : _T_4943 ? _Queue16_UInt8_30_io_deq_bits : _T_4942 ? _Queue16_UInt8_29_io_deq_bits : _T_4941 ? _Queue16_UInt8_28_io_deq_bits : _T_4940 ? _Queue16_UInt8_27_io_deq_bits : _T_4939 ? _Queue16_UInt8_26_io_deq_bits : _T_4938 ? _Queue16_UInt8_25_io_deq_bits : _T_4937 ? _Queue16_UInt8_24_io_deq_bits : _T_4936 ? _Queue16_UInt8_23_io_deq_bits : _T_4935 ? _Queue16_UInt8_22_io_deq_bits : _T_4934 ? _Queue16_UInt8_21_io_deq_bits : _T_4933 ? _Queue16_UInt8_20_io_deq_bits : _T_4932 ? _Queue16_UInt8_19_io_deq_bits : _T_4931 ? _Queue16_UInt8_18_io_deq_bits : _T_4930 ? _Queue16_UInt8_17_io_deq_bits : _T_4929 ? _Queue16_UInt8_16_io_deq_bits : _T_4928 ? _Queue16_UInt8_15_io_deq_bits : _T_4927 ? _Queue16_UInt8_14_io_deq_bits : _T_4926 ? _Queue16_UInt8_13_io_deq_bits : _T_4925 ? _Queue16_UInt8_12_io_deq_bits : _T_4924 ? _Queue16_UInt8_11_io_deq_bits : _T_4923 ? _Queue16_UInt8_10_io_deq_bits : _T_4922 ? _Queue16_UInt8_9_io_deq_bits : _T_4921 ? _Queue16_UInt8_8_io_deq_bits : _T_4920 ? _Queue16_UInt8_7_io_deq_bits : _T_4919 ? _Queue16_UInt8_6_io_deq_bits : _T_4918 ? _Queue16_UInt8_5_io_deq_bits : _T_4917 ? _Queue16_UInt8_4_io_deq_bits : _T_4916 ? _Queue16_UInt8_3_io_deq_bits : _T_4915 ? _Queue16_UInt8_2_io_deq_bits : _T_4914 ? _Queue16_UInt8_1_io_deq_bits : _T_4913 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_18 = _T_4944 ? _Queue16_UInt8_31_io_deq_valid : _T_4943 ? _Queue16_UInt8_30_io_deq_valid : _T_4942 ? _Queue16_UInt8_29_io_deq_valid : _T_4941 ? _Queue16_UInt8_28_io_deq_valid : _T_4940 ? _Queue16_UInt8_27_io_deq_valid : _T_4939 ? _Queue16_UInt8_26_io_deq_valid : _T_4938 ? _Queue16_UInt8_25_io_deq_valid : _T_4937 ? _Queue16_UInt8_24_io_deq_valid : _T_4936 ? _Queue16_UInt8_23_io_deq_valid : _T_4935 ? _Queue16_UInt8_22_io_deq_valid : _T_4934 ? _Queue16_UInt8_21_io_deq_valid : _T_4933 ? _Queue16_UInt8_20_io_deq_valid : _T_4932 ? _Queue16_UInt8_19_io_deq_valid : _T_4931 ? _Queue16_UInt8_18_io_deq_valid : _T_4930 ? _Queue16_UInt8_17_io_deq_valid : _T_4929 ? _Queue16_UInt8_16_io_deq_valid : _T_4928 ? _Queue16_UInt8_15_io_deq_valid : _T_4927 ? _Queue16_UInt8_14_io_deq_valid : _T_4926 ? _Queue16_UInt8_13_io_deq_valid : _T_4925 ? _Queue16_UInt8_12_io_deq_valid : _T_4924 ? _Queue16_UInt8_11_io_deq_valid : _T_4923 ? _Queue16_UInt8_10_io_deq_valid : _T_4922 ? _Queue16_UInt8_9_io_deq_valid : _T_4921 ? _Queue16_UInt8_8_io_deq_valid : _T_4920 ? _Queue16_UInt8_7_io_deq_valid : _T_4919 ? _Queue16_UInt8_6_io_deq_valid : _T_4918 ? _Queue16_UInt8_5_io_deq_valid : _T_4917 ? _Queue16_UInt8_4_io_deq_valid : _T_4916 ? _Queue16_UInt8_3_io_deq_valid : _T_4915 ? _Queue16_UInt8_2_io_deq_valid : _T_4914 ? _Queue16_UInt8_1_io_deq_valid : _T_4913 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_19 = _remapindex_T + 7'h13; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_109 = _remapindex_T_19 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_19 = _GEN_109[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4945 = remapindex_19 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4946 = remapindex_19 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4947 = remapindex_19 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4948 = remapindex_19 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4949 = remapindex_19 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4950 = remapindex_19 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4951 = remapindex_19 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4952 = remapindex_19 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4953 = remapindex_19 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4954 = remapindex_19 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4955 = remapindex_19 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4956 = remapindex_19 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4957 = remapindex_19 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4958 = remapindex_19 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4959 = remapindex_19 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4960 = remapindex_19 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4961 = remapindex_19 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4962 = remapindex_19 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4963 = remapindex_19 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4964 = remapindex_19 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4965 = remapindex_19 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4966 = remapindex_19 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4967 = remapindex_19 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4968 = remapindex_19 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4969 = remapindex_19 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4970 = remapindex_19 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4971 = remapindex_19 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4972 = remapindex_19 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4973 = remapindex_19 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4974 = remapindex_19 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4975 = remapindex_19 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4976 = remapindex_19 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_19 = _T_4976 ? _Queue16_UInt8_31_io_deq_bits : _T_4975 ? _Queue16_UInt8_30_io_deq_bits : _T_4974 ? _Queue16_UInt8_29_io_deq_bits : _T_4973 ? _Queue16_UInt8_28_io_deq_bits : _T_4972 ? _Queue16_UInt8_27_io_deq_bits : _T_4971 ? _Queue16_UInt8_26_io_deq_bits : _T_4970 ? _Queue16_UInt8_25_io_deq_bits : _T_4969 ? _Queue16_UInt8_24_io_deq_bits : _T_4968 ? _Queue16_UInt8_23_io_deq_bits : _T_4967 ? _Queue16_UInt8_22_io_deq_bits : _T_4966 ? _Queue16_UInt8_21_io_deq_bits : _T_4965 ? _Queue16_UInt8_20_io_deq_bits : _T_4964 ? _Queue16_UInt8_19_io_deq_bits : _T_4963 ? _Queue16_UInt8_18_io_deq_bits : _T_4962 ? _Queue16_UInt8_17_io_deq_bits : _T_4961 ? _Queue16_UInt8_16_io_deq_bits : _T_4960 ? _Queue16_UInt8_15_io_deq_bits : _T_4959 ? _Queue16_UInt8_14_io_deq_bits : _T_4958 ? _Queue16_UInt8_13_io_deq_bits : _T_4957 ? _Queue16_UInt8_12_io_deq_bits : _T_4956 ? _Queue16_UInt8_11_io_deq_bits : _T_4955 ? _Queue16_UInt8_10_io_deq_bits : _T_4954 ? _Queue16_UInt8_9_io_deq_bits : _T_4953 ? _Queue16_UInt8_8_io_deq_bits : _T_4952 ? _Queue16_UInt8_7_io_deq_bits : _T_4951 ? _Queue16_UInt8_6_io_deq_bits : _T_4950 ? _Queue16_UInt8_5_io_deq_bits : _T_4949 ? _Queue16_UInt8_4_io_deq_bits : _T_4948 ? _Queue16_UInt8_3_io_deq_bits : _T_4947 ? _Queue16_UInt8_2_io_deq_bits : _T_4946 ? _Queue16_UInt8_1_io_deq_bits : _T_4945 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_19 = _T_4976 ? _Queue16_UInt8_31_io_deq_valid : _T_4975 ? _Queue16_UInt8_30_io_deq_valid : _T_4974 ? _Queue16_UInt8_29_io_deq_valid : _T_4973 ? _Queue16_UInt8_28_io_deq_valid : _T_4972 ? _Queue16_UInt8_27_io_deq_valid : _T_4971 ? _Queue16_UInt8_26_io_deq_valid : _T_4970 ? _Queue16_UInt8_25_io_deq_valid : _T_4969 ? _Queue16_UInt8_24_io_deq_valid : _T_4968 ? _Queue16_UInt8_23_io_deq_valid : _T_4967 ? _Queue16_UInt8_22_io_deq_valid : _T_4966 ? _Queue16_UInt8_21_io_deq_valid : _T_4965 ? _Queue16_UInt8_20_io_deq_valid : _T_4964 ? _Queue16_UInt8_19_io_deq_valid : _T_4963 ? _Queue16_UInt8_18_io_deq_valid : _T_4962 ? _Queue16_UInt8_17_io_deq_valid : _T_4961 ? _Queue16_UInt8_16_io_deq_valid : _T_4960 ? _Queue16_UInt8_15_io_deq_valid : _T_4959 ? _Queue16_UInt8_14_io_deq_valid : _T_4958 ? _Queue16_UInt8_13_io_deq_valid : _T_4957 ? _Queue16_UInt8_12_io_deq_valid : _T_4956 ? _Queue16_UInt8_11_io_deq_valid : _T_4955 ? _Queue16_UInt8_10_io_deq_valid : _T_4954 ? _Queue16_UInt8_9_io_deq_valid : _T_4953 ? _Queue16_UInt8_8_io_deq_valid : _T_4952 ? _Queue16_UInt8_7_io_deq_valid : _T_4951 ? _Queue16_UInt8_6_io_deq_valid : _T_4950 ? _Queue16_UInt8_5_io_deq_valid : _T_4949 ? _Queue16_UInt8_4_io_deq_valid : _T_4948 ? _Queue16_UInt8_3_io_deq_valid : _T_4947 ? _Queue16_UInt8_2_io_deq_valid : _T_4946 ? _Queue16_UInt8_1_io_deq_valid : _T_4945 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_20 = _remapindex_T + 7'h14; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_110 = _remapindex_T_20 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_20 = _GEN_110[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_4977 = remapindex_20 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4978 = remapindex_20 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4979 = remapindex_20 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4980 = remapindex_20 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4981 = remapindex_20 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4982 = remapindex_20 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4983 = remapindex_20 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4984 = remapindex_20 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4985 = remapindex_20 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4986 = remapindex_20 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4987 = remapindex_20 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4988 = remapindex_20 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4989 = remapindex_20 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4990 = remapindex_20 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4991 = remapindex_20 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4992 = remapindex_20 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4993 = remapindex_20 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4994 = remapindex_20 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4995 = remapindex_20 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4996 = remapindex_20 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4997 = remapindex_20 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4998 = remapindex_20 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_4999 = remapindex_20 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5000 = remapindex_20 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5001 = remapindex_20 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5002 = remapindex_20 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5003 = remapindex_20 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5004 = remapindex_20 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5005 = remapindex_20 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5006 = remapindex_20 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5007 = remapindex_20 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5008 = remapindex_20 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_20 = _T_5008 ? _Queue16_UInt8_31_io_deq_bits : _T_5007 ? _Queue16_UInt8_30_io_deq_bits : _T_5006 ? _Queue16_UInt8_29_io_deq_bits : _T_5005 ? _Queue16_UInt8_28_io_deq_bits : _T_5004 ? _Queue16_UInt8_27_io_deq_bits : _T_5003 ? _Queue16_UInt8_26_io_deq_bits : _T_5002 ? _Queue16_UInt8_25_io_deq_bits : _T_5001 ? _Queue16_UInt8_24_io_deq_bits : _T_5000 ? _Queue16_UInt8_23_io_deq_bits : _T_4999 ? _Queue16_UInt8_22_io_deq_bits : _T_4998 ? _Queue16_UInt8_21_io_deq_bits : _T_4997 ? _Queue16_UInt8_20_io_deq_bits : _T_4996 ? _Queue16_UInt8_19_io_deq_bits : _T_4995 ? _Queue16_UInt8_18_io_deq_bits : _T_4994 ? _Queue16_UInt8_17_io_deq_bits : _T_4993 ? _Queue16_UInt8_16_io_deq_bits : _T_4992 ? _Queue16_UInt8_15_io_deq_bits : _T_4991 ? _Queue16_UInt8_14_io_deq_bits : _T_4990 ? _Queue16_UInt8_13_io_deq_bits : _T_4989 ? _Queue16_UInt8_12_io_deq_bits : _T_4988 ? _Queue16_UInt8_11_io_deq_bits : _T_4987 ? _Queue16_UInt8_10_io_deq_bits : _T_4986 ? _Queue16_UInt8_9_io_deq_bits : _T_4985 ? _Queue16_UInt8_8_io_deq_bits : _T_4984 ? _Queue16_UInt8_7_io_deq_bits : _T_4983 ? _Queue16_UInt8_6_io_deq_bits : _T_4982 ? _Queue16_UInt8_5_io_deq_bits : _T_4981 ? _Queue16_UInt8_4_io_deq_bits : _T_4980 ? _Queue16_UInt8_3_io_deq_bits : _T_4979 ? _Queue16_UInt8_2_io_deq_bits : _T_4978 ? _Queue16_UInt8_1_io_deq_bits : _T_4977 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_20 = _T_5008 ? _Queue16_UInt8_31_io_deq_valid : _T_5007 ? _Queue16_UInt8_30_io_deq_valid : _T_5006 ? _Queue16_UInt8_29_io_deq_valid : _T_5005 ? _Queue16_UInt8_28_io_deq_valid : _T_5004 ? _Queue16_UInt8_27_io_deq_valid : _T_5003 ? _Queue16_UInt8_26_io_deq_valid : _T_5002 ? _Queue16_UInt8_25_io_deq_valid : _T_5001 ? _Queue16_UInt8_24_io_deq_valid : _T_5000 ? _Queue16_UInt8_23_io_deq_valid : _T_4999 ? _Queue16_UInt8_22_io_deq_valid : _T_4998 ? _Queue16_UInt8_21_io_deq_valid : _T_4997 ? _Queue16_UInt8_20_io_deq_valid : _T_4996 ? _Queue16_UInt8_19_io_deq_valid : _T_4995 ? _Queue16_UInt8_18_io_deq_valid : _T_4994 ? _Queue16_UInt8_17_io_deq_valid : _T_4993 ? _Queue16_UInt8_16_io_deq_valid : _T_4992 ? _Queue16_UInt8_15_io_deq_valid : _T_4991 ? _Queue16_UInt8_14_io_deq_valid : _T_4990 ? _Queue16_UInt8_13_io_deq_valid : _T_4989 ? _Queue16_UInt8_12_io_deq_valid : _T_4988 ? _Queue16_UInt8_11_io_deq_valid : _T_4987 ? _Queue16_UInt8_10_io_deq_valid : _T_4986 ? _Queue16_UInt8_9_io_deq_valid : _T_4985 ? _Queue16_UInt8_8_io_deq_valid : _T_4984 ? _Queue16_UInt8_7_io_deq_valid : _T_4983 ? _Queue16_UInt8_6_io_deq_valid : _T_4982 ? _Queue16_UInt8_5_io_deq_valid : _T_4981 ? _Queue16_UInt8_4_io_deq_valid : _T_4980 ? _Queue16_UInt8_3_io_deq_valid : _T_4979 ? _Queue16_UInt8_2_io_deq_valid : _T_4978 ? _Queue16_UInt8_1_io_deq_valid : _T_4977 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_21 = _remapindex_T + 7'h15; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_111 = _remapindex_T_21 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_21 = _GEN_111[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5009 = remapindex_21 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5010 = remapindex_21 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5011 = remapindex_21 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5012 = remapindex_21 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5013 = remapindex_21 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5014 = remapindex_21 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5015 = remapindex_21 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5016 = remapindex_21 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5017 = remapindex_21 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5018 = remapindex_21 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5019 = remapindex_21 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5020 = remapindex_21 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5021 = remapindex_21 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5022 = remapindex_21 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5023 = remapindex_21 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5024 = remapindex_21 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5025 = remapindex_21 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5026 = remapindex_21 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5027 = remapindex_21 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5028 = remapindex_21 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5029 = remapindex_21 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5030 = remapindex_21 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5031 = remapindex_21 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5032 = remapindex_21 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5033 = remapindex_21 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5034 = remapindex_21 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5035 = remapindex_21 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5036 = remapindex_21 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5037 = remapindex_21 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5038 = remapindex_21 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5039 = remapindex_21 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5040 = remapindex_21 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_21 = _T_5040 ? _Queue16_UInt8_31_io_deq_bits : _T_5039 ? _Queue16_UInt8_30_io_deq_bits : _T_5038 ? _Queue16_UInt8_29_io_deq_bits : _T_5037 ? _Queue16_UInt8_28_io_deq_bits : _T_5036 ? _Queue16_UInt8_27_io_deq_bits : _T_5035 ? _Queue16_UInt8_26_io_deq_bits : _T_5034 ? _Queue16_UInt8_25_io_deq_bits : _T_5033 ? _Queue16_UInt8_24_io_deq_bits : _T_5032 ? _Queue16_UInt8_23_io_deq_bits : _T_5031 ? _Queue16_UInt8_22_io_deq_bits : _T_5030 ? _Queue16_UInt8_21_io_deq_bits : _T_5029 ? _Queue16_UInt8_20_io_deq_bits : _T_5028 ? _Queue16_UInt8_19_io_deq_bits : _T_5027 ? _Queue16_UInt8_18_io_deq_bits : _T_5026 ? _Queue16_UInt8_17_io_deq_bits : _T_5025 ? _Queue16_UInt8_16_io_deq_bits : _T_5024 ? _Queue16_UInt8_15_io_deq_bits : _T_5023 ? _Queue16_UInt8_14_io_deq_bits : _T_5022 ? _Queue16_UInt8_13_io_deq_bits : _T_5021 ? _Queue16_UInt8_12_io_deq_bits : _T_5020 ? _Queue16_UInt8_11_io_deq_bits : _T_5019 ? _Queue16_UInt8_10_io_deq_bits : _T_5018 ? _Queue16_UInt8_9_io_deq_bits : _T_5017 ? _Queue16_UInt8_8_io_deq_bits : _T_5016 ? _Queue16_UInt8_7_io_deq_bits : _T_5015 ? _Queue16_UInt8_6_io_deq_bits : _T_5014 ? _Queue16_UInt8_5_io_deq_bits : _T_5013 ? _Queue16_UInt8_4_io_deq_bits : _T_5012 ? _Queue16_UInt8_3_io_deq_bits : _T_5011 ? _Queue16_UInt8_2_io_deq_bits : _T_5010 ? _Queue16_UInt8_1_io_deq_bits : _T_5009 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_21 = _T_5040 ? _Queue16_UInt8_31_io_deq_valid : _T_5039 ? _Queue16_UInt8_30_io_deq_valid : _T_5038 ? _Queue16_UInt8_29_io_deq_valid : _T_5037 ? _Queue16_UInt8_28_io_deq_valid : _T_5036 ? _Queue16_UInt8_27_io_deq_valid : _T_5035 ? _Queue16_UInt8_26_io_deq_valid : _T_5034 ? _Queue16_UInt8_25_io_deq_valid : _T_5033 ? _Queue16_UInt8_24_io_deq_valid : _T_5032 ? _Queue16_UInt8_23_io_deq_valid : _T_5031 ? _Queue16_UInt8_22_io_deq_valid : _T_5030 ? _Queue16_UInt8_21_io_deq_valid : _T_5029 ? _Queue16_UInt8_20_io_deq_valid : _T_5028 ? _Queue16_UInt8_19_io_deq_valid : _T_5027 ? _Queue16_UInt8_18_io_deq_valid : _T_5026 ? _Queue16_UInt8_17_io_deq_valid : _T_5025 ? _Queue16_UInt8_16_io_deq_valid : _T_5024 ? _Queue16_UInt8_15_io_deq_valid : _T_5023 ? _Queue16_UInt8_14_io_deq_valid : _T_5022 ? _Queue16_UInt8_13_io_deq_valid : _T_5021 ? _Queue16_UInt8_12_io_deq_valid : _T_5020 ? _Queue16_UInt8_11_io_deq_valid : _T_5019 ? _Queue16_UInt8_10_io_deq_valid : _T_5018 ? _Queue16_UInt8_9_io_deq_valid : _T_5017 ? _Queue16_UInt8_8_io_deq_valid : _T_5016 ? _Queue16_UInt8_7_io_deq_valid : _T_5015 ? _Queue16_UInt8_6_io_deq_valid : _T_5014 ? _Queue16_UInt8_5_io_deq_valid : _T_5013 ? _Queue16_UInt8_4_io_deq_valid : _T_5012 ? _Queue16_UInt8_3_io_deq_valid : _T_5011 ? _Queue16_UInt8_2_io_deq_valid : _T_5010 ? _Queue16_UInt8_1_io_deq_valid : _T_5009 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_22 = _remapindex_T + 7'h16; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_112 = _remapindex_T_22 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_22 = _GEN_112[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5041 = remapindex_22 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5042 = remapindex_22 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5043 = remapindex_22 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5044 = remapindex_22 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5045 = remapindex_22 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5046 = remapindex_22 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5047 = remapindex_22 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5048 = remapindex_22 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5049 = remapindex_22 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5050 = remapindex_22 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5051 = remapindex_22 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5052 = remapindex_22 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5053 = remapindex_22 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5054 = remapindex_22 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5055 = remapindex_22 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5056 = remapindex_22 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5057 = remapindex_22 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5058 = remapindex_22 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5059 = remapindex_22 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5060 = remapindex_22 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5061 = remapindex_22 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5062 = remapindex_22 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5063 = remapindex_22 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5064 = remapindex_22 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5065 = remapindex_22 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5066 = remapindex_22 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5067 = remapindex_22 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5068 = remapindex_22 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5069 = remapindex_22 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5070 = remapindex_22 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5071 = remapindex_22 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5072 = remapindex_22 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_22 = _T_5072 ? _Queue16_UInt8_31_io_deq_bits : _T_5071 ? _Queue16_UInt8_30_io_deq_bits : _T_5070 ? _Queue16_UInt8_29_io_deq_bits : _T_5069 ? _Queue16_UInt8_28_io_deq_bits : _T_5068 ? _Queue16_UInt8_27_io_deq_bits : _T_5067 ? _Queue16_UInt8_26_io_deq_bits : _T_5066 ? _Queue16_UInt8_25_io_deq_bits : _T_5065 ? _Queue16_UInt8_24_io_deq_bits : _T_5064 ? _Queue16_UInt8_23_io_deq_bits : _T_5063 ? _Queue16_UInt8_22_io_deq_bits : _T_5062 ? _Queue16_UInt8_21_io_deq_bits : _T_5061 ? _Queue16_UInt8_20_io_deq_bits : _T_5060 ? _Queue16_UInt8_19_io_deq_bits : _T_5059 ? _Queue16_UInt8_18_io_deq_bits : _T_5058 ? _Queue16_UInt8_17_io_deq_bits : _T_5057 ? _Queue16_UInt8_16_io_deq_bits : _T_5056 ? _Queue16_UInt8_15_io_deq_bits : _T_5055 ? _Queue16_UInt8_14_io_deq_bits : _T_5054 ? _Queue16_UInt8_13_io_deq_bits : _T_5053 ? _Queue16_UInt8_12_io_deq_bits : _T_5052 ? _Queue16_UInt8_11_io_deq_bits : _T_5051 ? _Queue16_UInt8_10_io_deq_bits : _T_5050 ? _Queue16_UInt8_9_io_deq_bits : _T_5049 ? _Queue16_UInt8_8_io_deq_bits : _T_5048 ? _Queue16_UInt8_7_io_deq_bits : _T_5047 ? _Queue16_UInt8_6_io_deq_bits : _T_5046 ? _Queue16_UInt8_5_io_deq_bits : _T_5045 ? _Queue16_UInt8_4_io_deq_bits : _T_5044 ? _Queue16_UInt8_3_io_deq_bits : _T_5043 ? _Queue16_UInt8_2_io_deq_bits : _T_5042 ? _Queue16_UInt8_1_io_deq_bits : _T_5041 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_22 = _T_5072 ? _Queue16_UInt8_31_io_deq_valid : _T_5071 ? _Queue16_UInt8_30_io_deq_valid : _T_5070 ? _Queue16_UInt8_29_io_deq_valid : _T_5069 ? _Queue16_UInt8_28_io_deq_valid : _T_5068 ? _Queue16_UInt8_27_io_deq_valid : _T_5067 ? _Queue16_UInt8_26_io_deq_valid : _T_5066 ? _Queue16_UInt8_25_io_deq_valid : _T_5065 ? _Queue16_UInt8_24_io_deq_valid : _T_5064 ? _Queue16_UInt8_23_io_deq_valid : _T_5063 ? _Queue16_UInt8_22_io_deq_valid : _T_5062 ? _Queue16_UInt8_21_io_deq_valid : _T_5061 ? _Queue16_UInt8_20_io_deq_valid : _T_5060 ? _Queue16_UInt8_19_io_deq_valid : _T_5059 ? _Queue16_UInt8_18_io_deq_valid : _T_5058 ? _Queue16_UInt8_17_io_deq_valid : _T_5057 ? _Queue16_UInt8_16_io_deq_valid : _T_5056 ? _Queue16_UInt8_15_io_deq_valid : _T_5055 ? _Queue16_UInt8_14_io_deq_valid : _T_5054 ? _Queue16_UInt8_13_io_deq_valid : _T_5053 ? _Queue16_UInt8_12_io_deq_valid : _T_5052 ? _Queue16_UInt8_11_io_deq_valid : _T_5051 ? _Queue16_UInt8_10_io_deq_valid : _T_5050 ? _Queue16_UInt8_9_io_deq_valid : _T_5049 ? _Queue16_UInt8_8_io_deq_valid : _T_5048 ? _Queue16_UInt8_7_io_deq_valid : _T_5047 ? _Queue16_UInt8_6_io_deq_valid : _T_5046 ? _Queue16_UInt8_5_io_deq_valid : _T_5045 ? _Queue16_UInt8_4_io_deq_valid : _T_5044 ? _Queue16_UInt8_3_io_deq_valid : _T_5043 ? _Queue16_UInt8_2_io_deq_valid : _T_5042 ? _Queue16_UInt8_1_io_deq_valid : _T_5041 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_23 = _remapindex_T + 7'h17; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_113 = _remapindex_T_23 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_23 = _GEN_113[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5073 = remapindex_23 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5074 = remapindex_23 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5075 = remapindex_23 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5076 = remapindex_23 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5077 = remapindex_23 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5078 = remapindex_23 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5079 = remapindex_23 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5080 = remapindex_23 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5081 = remapindex_23 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5082 = remapindex_23 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5083 = remapindex_23 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5084 = remapindex_23 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5085 = remapindex_23 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5086 = remapindex_23 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5087 = remapindex_23 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5088 = remapindex_23 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5089 = remapindex_23 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5090 = remapindex_23 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5091 = remapindex_23 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5092 = remapindex_23 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5093 = remapindex_23 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5094 = remapindex_23 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5095 = remapindex_23 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5096 = remapindex_23 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5097 = remapindex_23 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5098 = remapindex_23 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5099 = remapindex_23 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5100 = remapindex_23 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5101 = remapindex_23 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5102 = remapindex_23 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5103 = remapindex_23 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5104 = remapindex_23 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_23 = _T_5104 ? _Queue16_UInt8_31_io_deq_bits : _T_5103 ? _Queue16_UInt8_30_io_deq_bits : _T_5102 ? _Queue16_UInt8_29_io_deq_bits : _T_5101 ? _Queue16_UInt8_28_io_deq_bits : _T_5100 ? _Queue16_UInt8_27_io_deq_bits : _T_5099 ? _Queue16_UInt8_26_io_deq_bits : _T_5098 ? _Queue16_UInt8_25_io_deq_bits : _T_5097 ? _Queue16_UInt8_24_io_deq_bits : _T_5096 ? _Queue16_UInt8_23_io_deq_bits : _T_5095 ? _Queue16_UInt8_22_io_deq_bits : _T_5094 ? _Queue16_UInt8_21_io_deq_bits : _T_5093 ? _Queue16_UInt8_20_io_deq_bits : _T_5092 ? _Queue16_UInt8_19_io_deq_bits : _T_5091 ? _Queue16_UInt8_18_io_deq_bits : _T_5090 ? _Queue16_UInt8_17_io_deq_bits : _T_5089 ? _Queue16_UInt8_16_io_deq_bits : _T_5088 ? _Queue16_UInt8_15_io_deq_bits : _T_5087 ? _Queue16_UInt8_14_io_deq_bits : _T_5086 ? _Queue16_UInt8_13_io_deq_bits : _T_5085 ? _Queue16_UInt8_12_io_deq_bits : _T_5084 ? _Queue16_UInt8_11_io_deq_bits : _T_5083 ? _Queue16_UInt8_10_io_deq_bits : _T_5082 ? _Queue16_UInt8_9_io_deq_bits : _T_5081 ? _Queue16_UInt8_8_io_deq_bits : _T_5080 ? _Queue16_UInt8_7_io_deq_bits : _T_5079 ? _Queue16_UInt8_6_io_deq_bits : _T_5078 ? _Queue16_UInt8_5_io_deq_bits : _T_5077 ? _Queue16_UInt8_4_io_deq_bits : _T_5076 ? _Queue16_UInt8_3_io_deq_bits : _T_5075 ? _Queue16_UInt8_2_io_deq_bits : _T_5074 ? _Queue16_UInt8_1_io_deq_bits : _T_5073 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_23 = _T_5104 ? _Queue16_UInt8_31_io_deq_valid : _T_5103 ? _Queue16_UInt8_30_io_deq_valid : _T_5102 ? _Queue16_UInt8_29_io_deq_valid : _T_5101 ? _Queue16_UInt8_28_io_deq_valid : _T_5100 ? _Queue16_UInt8_27_io_deq_valid : _T_5099 ? _Queue16_UInt8_26_io_deq_valid : _T_5098 ? _Queue16_UInt8_25_io_deq_valid : _T_5097 ? _Queue16_UInt8_24_io_deq_valid : _T_5096 ? _Queue16_UInt8_23_io_deq_valid : _T_5095 ? _Queue16_UInt8_22_io_deq_valid : _T_5094 ? _Queue16_UInt8_21_io_deq_valid : _T_5093 ? _Queue16_UInt8_20_io_deq_valid : _T_5092 ? _Queue16_UInt8_19_io_deq_valid : _T_5091 ? _Queue16_UInt8_18_io_deq_valid : _T_5090 ? _Queue16_UInt8_17_io_deq_valid : _T_5089 ? _Queue16_UInt8_16_io_deq_valid : _T_5088 ? _Queue16_UInt8_15_io_deq_valid : _T_5087 ? _Queue16_UInt8_14_io_deq_valid : _T_5086 ? _Queue16_UInt8_13_io_deq_valid : _T_5085 ? _Queue16_UInt8_12_io_deq_valid : _T_5084 ? _Queue16_UInt8_11_io_deq_valid : _T_5083 ? _Queue16_UInt8_10_io_deq_valid : _T_5082 ? _Queue16_UInt8_9_io_deq_valid : _T_5081 ? _Queue16_UInt8_8_io_deq_valid : _T_5080 ? _Queue16_UInt8_7_io_deq_valid : _T_5079 ? _Queue16_UInt8_6_io_deq_valid : _T_5078 ? _Queue16_UInt8_5_io_deq_valid : _T_5077 ? _Queue16_UInt8_4_io_deq_valid : _T_5076 ? _Queue16_UInt8_3_io_deq_valid : _T_5075 ? _Queue16_UInt8_2_io_deq_valid : _T_5074 ? _Queue16_UInt8_1_io_deq_valid : _T_5073 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_24 = _remapindex_T + 7'h18; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_114 = _remapindex_T_24 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_24 = _GEN_114[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5105 = remapindex_24 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5106 = remapindex_24 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5107 = remapindex_24 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5108 = remapindex_24 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5109 = remapindex_24 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5110 = remapindex_24 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5111 = remapindex_24 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5112 = remapindex_24 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5113 = remapindex_24 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5114 = remapindex_24 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5115 = remapindex_24 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5116 = remapindex_24 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5117 = remapindex_24 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5118 = remapindex_24 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5119 = remapindex_24 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5120 = remapindex_24 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5121 = remapindex_24 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5122 = remapindex_24 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5123 = remapindex_24 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5124 = remapindex_24 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5125 = remapindex_24 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5126 = remapindex_24 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5127 = remapindex_24 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5128 = remapindex_24 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5129 = remapindex_24 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5130 = remapindex_24 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5131 = remapindex_24 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5132 = remapindex_24 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5133 = remapindex_24 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5134 = remapindex_24 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5135 = remapindex_24 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5136 = remapindex_24 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_24 = _T_5136 ? _Queue16_UInt8_31_io_deq_bits : _T_5135 ? _Queue16_UInt8_30_io_deq_bits : _T_5134 ? _Queue16_UInt8_29_io_deq_bits : _T_5133 ? _Queue16_UInt8_28_io_deq_bits : _T_5132 ? _Queue16_UInt8_27_io_deq_bits : _T_5131 ? _Queue16_UInt8_26_io_deq_bits : _T_5130 ? _Queue16_UInt8_25_io_deq_bits : _T_5129 ? _Queue16_UInt8_24_io_deq_bits : _T_5128 ? _Queue16_UInt8_23_io_deq_bits : _T_5127 ? _Queue16_UInt8_22_io_deq_bits : _T_5126 ? _Queue16_UInt8_21_io_deq_bits : _T_5125 ? _Queue16_UInt8_20_io_deq_bits : _T_5124 ? _Queue16_UInt8_19_io_deq_bits : _T_5123 ? _Queue16_UInt8_18_io_deq_bits : _T_5122 ? _Queue16_UInt8_17_io_deq_bits : _T_5121 ? _Queue16_UInt8_16_io_deq_bits : _T_5120 ? _Queue16_UInt8_15_io_deq_bits : _T_5119 ? _Queue16_UInt8_14_io_deq_bits : _T_5118 ? _Queue16_UInt8_13_io_deq_bits : _T_5117 ? _Queue16_UInt8_12_io_deq_bits : _T_5116 ? _Queue16_UInt8_11_io_deq_bits : _T_5115 ? _Queue16_UInt8_10_io_deq_bits : _T_5114 ? _Queue16_UInt8_9_io_deq_bits : _T_5113 ? _Queue16_UInt8_8_io_deq_bits : _T_5112 ? _Queue16_UInt8_7_io_deq_bits : _T_5111 ? _Queue16_UInt8_6_io_deq_bits : _T_5110 ? _Queue16_UInt8_5_io_deq_bits : _T_5109 ? _Queue16_UInt8_4_io_deq_bits : _T_5108 ? _Queue16_UInt8_3_io_deq_bits : _T_5107 ? _Queue16_UInt8_2_io_deq_bits : _T_5106 ? _Queue16_UInt8_1_io_deq_bits : _T_5105 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_24 = _T_5136 ? _Queue16_UInt8_31_io_deq_valid : _T_5135 ? _Queue16_UInt8_30_io_deq_valid : _T_5134 ? _Queue16_UInt8_29_io_deq_valid : _T_5133 ? _Queue16_UInt8_28_io_deq_valid : _T_5132 ? _Queue16_UInt8_27_io_deq_valid : _T_5131 ? _Queue16_UInt8_26_io_deq_valid : _T_5130 ? _Queue16_UInt8_25_io_deq_valid : _T_5129 ? _Queue16_UInt8_24_io_deq_valid : _T_5128 ? _Queue16_UInt8_23_io_deq_valid : _T_5127 ? _Queue16_UInt8_22_io_deq_valid : _T_5126 ? _Queue16_UInt8_21_io_deq_valid : _T_5125 ? _Queue16_UInt8_20_io_deq_valid : _T_5124 ? _Queue16_UInt8_19_io_deq_valid : _T_5123 ? _Queue16_UInt8_18_io_deq_valid : _T_5122 ? _Queue16_UInt8_17_io_deq_valid : _T_5121 ? _Queue16_UInt8_16_io_deq_valid : _T_5120 ? _Queue16_UInt8_15_io_deq_valid : _T_5119 ? _Queue16_UInt8_14_io_deq_valid : _T_5118 ? _Queue16_UInt8_13_io_deq_valid : _T_5117 ? _Queue16_UInt8_12_io_deq_valid : _T_5116 ? _Queue16_UInt8_11_io_deq_valid : _T_5115 ? _Queue16_UInt8_10_io_deq_valid : _T_5114 ? _Queue16_UInt8_9_io_deq_valid : _T_5113 ? _Queue16_UInt8_8_io_deq_valid : _T_5112 ? _Queue16_UInt8_7_io_deq_valid : _T_5111 ? _Queue16_UInt8_6_io_deq_valid : _T_5110 ? _Queue16_UInt8_5_io_deq_valid : _T_5109 ? _Queue16_UInt8_4_io_deq_valid : _T_5108 ? _Queue16_UInt8_3_io_deq_valid : _T_5107 ? _Queue16_UInt8_2_io_deq_valid : _T_5106 ? _Queue16_UInt8_1_io_deq_valid : _T_5105 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_25 = _remapindex_T + 7'h19; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_115 = _remapindex_T_25 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_25 = _GEN_115[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5137 = remapindex_25 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5138 = remapindex_25 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5139 = remapindex_25 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5140 = remapindex_25 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5141 = remapindex_25 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5142 = remapindex_25 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5143 = remapindex_25 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5144 = remapindex_25 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5145 = remapindex_25 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5146 = remapindex_25 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5147 = remapindex_25 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5148 = remapindex_25 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5149 = remapindex_25 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5150 = remapindex_25 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5151 = remapindex_25 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5152 = remapindex_25 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5153 = remapindex_25 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5154 = remapindex_25 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5155 = remapindex_25 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5156 = remapindex_25 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5157 = remapindex_25 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5158 = remapindex_25 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5159 = remapindex_25 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5160 = remapindex_25 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5161 = remapindex_25 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5162 = remapindex_25 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5163 = remapindex_25 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5164 = remapindex_25 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5165 = remapindex_25 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5166 = remapindex_25 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5167 = remapindex_25 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5168 = remapindex_25 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_25 = _T_5168 ? _Queue16_UInt8_31_io_deq_bits : _T_5167 ? _Queue16_UInt8_30_io_deq_bits : _T_5166 ? _Queue16_UInt8_29_io_deq_bits : _T_5165 ? _Queue16_UInt8_28_io_deq_bits : _T_5164 ? _Queue16_UInt8_27_io_deq_bits : _T_5163 ? _Queue16_UInt8_26_io_deq_bits : _T_5162 ? _Queue16_UInt8_25_io_deq_bits : _T_5161 ? _Queue16_UInt8_24_io_deq_bits : _T_5160 ? _Queue16_UInt8_23_io_deq_bits : _T_5159 ? _Queue16_UInt8_22_io_deq_bits : _T_5158 ? _Queue16_UInt8_21_io_deq_bits : _T_5157 ? _Queue16_UInt8_20_io_deq_bits : _T_5156 ? _Queue16_UInt8_19_io_deq_bits : _T_5155 ? _Queue16_UInt8_18_io_deq_bits : _T_5154 ? _Queue16_UInt8_17_io_deq_bits : _T_5153 ? _Queue16_UInt8_16_io_deq_bits : _T_5152 ? _Queue16_UInt8_15_io_deq_bits : _T_5151 ? _Queue16_UInt8_14_io_deq_bits : _T_5150 ? _Queue16_UInt8_13_io_deq_bits : _T_5149 ? _Queue16_UInt8_12_io_deq_bits : _T_5148 ? _Queue16_UInt8_11_io_deq_bits : _T_5147 ? _Queue16_UInt8_10_io_deq_bits : _T_5146 ? _Queue16_UInt8_9_io_deq_bits : _T_5145 ? _Queue16_UInt8_8_io_deq_bits : _T_5144 ? _Queue16_UInt8_7_io_deq_bits : _T_5143 ? _Queue16_UInt8_6_io_deq_bits : _T_5142 ? _Queue16_UInt8_5_io_deq_bits : _T_5141 ? _Queue16_UInt8_4_io_deq_bits : _T_5140 ? _Queue16_UInt8_3_io_deq_bits : _T_5139 ? _Queue16_UInt8_2_io_deq_bits : _T_5138 ? _Queue16_UInt8_1_io_deq_bits : _T_5137 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_25 = _T_5168 ? _Queue16_UInt8_31_io_deq_valid : _T_5167 ? _Queue16_UInt8_30_io_deq_valid : _T_5166 ? _Queue16_UInt8_29_io_deq_valid : _T_5165 ? _Queue16_UInt8_28_io_deq_valid : _T_5164 ? _Queue16_UInt8_27_io_deq_valid : _T_5163 ? _Queue16_UInt8_26_io_deq_valid : _T_5162 ? _Queue16_UInt8_25_io_deq_valid : _T_5161 ? _Queue16_UInt8_24_io_deq_valid : _T_5160 ? _Queue16_UInt8_23_io_deq_valid : _T_5159 ? _Queue16_UInt8_22_io_deq_valid : _T_5158 ? _Queue16_UInt8_21_io_deq_valid : _T_5157 ? _Queue16_UInt8_20_io_deq_valid : _T_5156 ? _Queue16_UInt8_19_io_deq_valid : _T_5155 ? _Queue16_UInt8_18_io_deq_valid : _T_5154 ? _Queue16_UInt8_17_io_deq_valid : _T_5153 ? _Queue16_UInt8_16_io_deq_valid : _T_5152 ? _Queue16_UInt8_15_io_deq_valid : _T_5151 ? _Queue16_UInt8_14_io_deq_valid : _T_5150 ? _Queue16_UInt8_13_io_deq_valid : _T_5149 ? _Queue16_UInt8_12_io_deq_valid : _T_5148 ? _Queue16_UInt8_11_io_deq_valid : _T_5147 ? _Queue16_UInt8_10_io_deq_valid : _T_5146 ? _Queue16_UInt8_9_io_deq_valid : _T_5145 ? _Queue16_UInt8_8_io_deq_valid : _T_5144 ? _Queue16_UInt8_7_io_deq_valid : _T_5143 ? _Queue16_UInt8_6_io_deq_valid : _T_5142 ? _Queue16_UInt8_5_io_deq_valid : _T_5141 ? _Queue16_UInt8_4_io_deq_valid : _T_5140 ? _Queue16_UInt8_3_io_deq_valid : _T_5139 ? _Queue16_UInt8_2_io_deq_valid : _T_5138 ? _Queue16_UInt8_1_io_deq_valid : _T_5137 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_26 = _remapindex_T + 7'h1A; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_116 = _remapindex_T_26 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_26 = _GEN_116[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5169 = remapindex_26 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5170 = remapindex_26 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5171 = remapindex_26 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5172 = remapindex_26 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5173 = remapindex_26 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5174 = remapindex_26 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5175 = remapindex_26 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5176 = remapindex_26 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5177 = remapindex_26 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5178 = remapindex_26 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5179 = remapindex_26 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5180 = remapindex_26 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5181 = remapindex_26 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5182 = remapindex_26 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5183 = remapindex_26 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5184 = remapindex_26 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5185 = remapindex_26 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5186 = remapindex_26 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5187 = remapindex_26 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5188 = remapindex_26 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5189 = remapindex_26 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5190 = remapindex_26 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5191 = remapindex_26 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5192 = remapindex_26 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5193 = remapindex_26 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5194 = remapindex_26 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5195 = remapindex_26 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5196 = remapindex_26 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5197 = remapindex_26 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5198 = remapindex_26 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5199 = remapindex_26 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5200 = remapindex_26 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_26 = _T_5200 ? _Queue16_UInt8_31_io_deq_bits : _T_5199 ? _Queue16_UInt8_30_io_deq_bits : _T_5198 ? _Queue16_UInt8_29_io_deq_bits : _T_5197 ? _Queue16_UInt8_28_io_deq_bits : _T_5196 ? _Queue16_UInt8_27_io_deq_bits : _T_5195 ? _Queue16_UInt8_26_io_deq_bits : _T_5194 ? _Queue16_UInt8_25_io_deq_bits : _T_5193 ? _Queue16_UInt8_24_io_deq_bits : _T_5192 ? _Queue16_UInt8_23_io_deq_bits : _T_5191 ? _Queue16_UInt8_22_io_deq_bits : _T_5190 ? _Queue16_UInt8_21_io_deq_bits : _T_5189 ? _Queue16_UInt8_20_io_deq_bits : _T_5188 ? _Queue16_UInt8_19_io_deq_bits : _T_5187 ? _Queue16_UInt8_18_io_deq_bits : _T_5186 ? _Queue16_UInt8_17_io_deq_bits : _T_5185 ? _Queue16_UInt8_16_io_deq_bits : _T_5184 ? _Queue16_UInt8_15_io_deq_bits : _T_5183 ? _Queue16_UInt8_14_io_deq_bits : _T_5182 ? _Queue16_UInt8_13_io_deq_bits : _T_5181 ? _Queue16_UInt8_12_io_deq_bits : _T_5180 ? _Queue16_UInt8_11_io_deq_bits : _T_5179 ? _Queue16_UInt8_10_io_deq_bits : _T_5178 ? _Queue16_UInt8_9_io_deq_bits : _T_5177 ? _Queue16_UInt8_8_io_deq_bits : _T_5176 ? _Queue16_UInt8_7_io_deq_bits : _T_5175 ? _Queue16_UInt8_6_io_deq_bits : _T_5174 ? _Queue16_UInt8_5_io_deq_bits : _T_5173 ? _Queue16_UInt8_4_io_deq_bits : _T_5172 ? _Queue16_UInt8_3_io_deq_bits : _T_5171 ? _Queue16_UInt8_2_io_deq_bits : _T_5170 ? _Queue16_UInt8_1_io_deq_bits : _T_5169 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_26 = _T_5200 ? _Queue16_UInt8_31_io_deq_valid : _T_5199 ? _Queue16_UInt8_30_io_deq_valid : _T_5198 ? _Queue16_UInt8_29_io_deq_valid : _T_5197 ? _Queue16_UInt8_28_io_deq_valid : _T_5196 ? _Queue16_UInt8_27_io_deq_valid : _T_5195 ? _Queue16_UInt8_26_io_deq_valid : _T_5194 ? _Queue16_UInt8_25_io_deq_valid : _T_5193 ? _Queue16_UInt8_24_io_deq_valid : _T_5192 ? _Queue16_UInt8_23_io_deq_valid : _T_5191 ? _Queue16_UInt8_22_io_deq_valid : _T_5190 ? _Queue16_UInt8_21_io_deq_valid : _T_5189 ? _Queue16_UInt8_20_io_deq_valid : _T_5188 ? _Queue16_UInt8_19_io_deq_valid : _T_5187 ? _Queue16_UInt8_18_io_deq_valid : _T_5186 ? _Queue16_UInt8_17_io_deq_valid : _T_5185 ? _Queue16_UInt8_16_io_deq_valid : _T_5184 ? _Queue16_UInt8_15_io_deq_valid : _T_5183 ? _Queue16_UInt8_14_io_deq_valid : _T_5182 ? _Queue16_UInt8_13_io_deq_valid : _T_5181 ? _Queue16_UInt8_12_io_deq_valid : _T_5180 ? _Queue16_UInt8_11_io_deq_valid : _T_5179 ? _Queue16_UInt8_10_io_deq_valid : _T_5178 ? _Queue16_UInt8_9_io_deq_valid : _T_5177 ? _Queue16_UInt8_8_io_deq_valid : _T_5176 ? _Queue16_UInt8_7_io_deq_valid : _T_5175 ? _Queue16_UInt8_6_io_deq_valid : _T_5174 ? _Queue16_UInt8_5_io_deq_valid : _T_5173 ? _Queue16_UInt8_4_io_deq_valid : _T_5172 ? _Queue16_UInt8_3_io_deq_valid : _T_5171 ? _Queue16_UInt8_2_io_deq_valid : _T_5170 ? _Queue16_UInt8_1_io_deq_valid : _T_5169 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_27 = _remapindex_T + 7'h1B; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_117 = _remapindex_T_27 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_27 = _GEN_117[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5201 = remapindex_27 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5202 = remapindex_27 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5203 = remapindex_27 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5204 = remapindex_27 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5205 = remapindex_27 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5206 = remapindex_27 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5207 = remapindex_27 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5208 = remapindex_27 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5209 = remapindex_27 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5210 = remapindex_27 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5211 = remapindex_27 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5212 = remapindex_27 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5213 = remapindex_27 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5214 = remapindex_27 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5215 = remapindex_27 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5216 = remapindex_27 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5217 = remapindex_27 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5218 = remapindex_27 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5219 = remapindex_27 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5220 = remapindex_27 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5221 = remapindex_27 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5222 = remapindex_27 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5223 = remapindex_27 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5224 = remapindex_27 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5225 = remapindex_27 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5226 = remapindex_27 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5227 = remapindex_27 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5228 = remapindex_27 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5229 = remapindex_27 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5230 = remapindex_27 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5231 = remapindex_27 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5232 = remapindex_27 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_27 = _T_5232 ? _Queue16_UInt8_31_io_deq_bits : _T_5231 ? _Queue16_UInt8_30_io_deq_bits : _T_5230 ? _Queue16_UInt8_29_io_deq_bits : _T_5229 ? _Queue16_UInt8_28_io_deq_bits : _T_5228 ? _Queue16_UInt8_27_io_deq_bits : _T_5227 ? _Queue16_UInt8_26_io_deq_bits : _T_5226 ? _Queue16_UInt8_25_io_deq_bits : _T_5225 ? _Queue16_UInt8_24_io_deq_bits : _T_5224 ? _Queue16_UInt8_23_io_deq_bits : _T_5223 ? _Queue16_UInt8_22_io_deq_bits : _T_5222 ? _Queue16_UInt8_21_io_deq_bits : _T_5221 ? _Queue16_UInt8_20_io_deq_bits : _T_5220 ? _Queue16_UInt8_19_io_deq_bits : _T_5219 ? _Queue16_UInt8_18_io_deq_bits : _T_5218 ? _Queue16_UInt8_17_io_deq_bits : _T_5217 ? _Queue16_UInt8_16_io_deq_bits : _T_5216 ? _Queue16_UInt8_15_io_deq_bits : _T_5215 ? _Queue16_UInt8_14_io_deq_bits : _T_5214 ? _Queue16_UInt8_13_io_deq_bits : _T_5213 ? _Queue16_UInt8_12_io_deq_bits : _T_5212 ? _Queue16_UInt8_11_io_deq_bits : _T_5211 ? _Queue16_UInt8_10_io_deq_bits : _T_5210 ? _Queue16_UInt8_9_io_deq_bits : _T_5209 ? _Queue16_UInt8_8_io_deq_bits : _T_5208 ? _Queue16_UInt8_7_io_deq_bits : _T_5207 ? _Queue16_UInt8_6_io_deq_bits : _T_5206 ? _Queue16_UInt8_5_io_deq_bits : _T_5205 ? _Queue16_UInt8_4_io_deq_bits : _T_5204 ? _Queue16_UInt8_3_io_deq_bits : _T_5203 ? _Queue16_UInt8_2_io_deq_bits : _T_5202 ? _Queue16_UInt8_1_io_deq_bits : _T_5201 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_27 = _T_5232 ? _Queue16_UInt8_31_io_deq_valid : _T_5231 ? _Queue16_UInt8_30_io_deq_valid : _T_5230 ? _Queue16_UInt8_29_io_deq_valid : _T_5229 ? _Queue16_UInt8_28_io_deq_valid : _T_5228 ? _Queue16_UInt8_27_io_deq_valid : _T_5227 ? _Queue16_UInt8_26_io_deq_valid : _T_5226 ? _Queue16_UInt8_25_io_deq_valid : _T_5225 ? _Queue16_UInt8_24_io_deq_valid : _T_5224 ? _Queue16_UInt8_23_io_deq_valid : _T_5223 ? _Queue16_UInt8_22_io_deq_valid : _T_5222 ? _Queue16_UInt8_21_io_deq_valid : _T_5221 ? _Queue16_UInt8_20_io_deq_valid : _T_5220 ? _Queue16_UInt8_19_io_deq_valid : _T_5219 ? _Queue16_UInt8_18_io_deq_valid : _T_5218 ? _Queue16_UInt8_17_io_deq_valid : _T_5217 ? _Queue16_UInt8_16_io_deq_valid : _T_5216 ? _Queue16_UInt8_15_io_deq_valid : _T_5215 ? _Queue16_UInt8_14_io_deq_valid : _T_5214 ? _Queue16_UInt8_13_io_deq_valid : _T_5213 ? _Queue16_UInt8_12_io_deq_valid : _T_5212 ? _Queue16_UInt8_11_io_deq_valid : _T_5211 ? _Queue16_UInt8_10_io_deq_valid : _T_5210 ? _Queue16_UInt8_9_io_deq_valid : _T_5209 ? _Queue16_UInt8_8_io_deq_valid : _T_5208 ? _Queue16_UInt8_7_io_deq_valid : _T_5207 ? _Queue16_UInt8_6_io_deq_valid : _T_5206 ? _Queue16_UInt8_5_io_deq_valid : _T_5205 ? _Queue16_UInt8_4_io_deq_valid : _T_5204 ? _Queue16_UInt8_3_io_deq_valid : _T_5203 ? _Queue16_UInt8_2_io_deq_valid : _T_5202 ? _Queue16_UInt8_1_io_deq_valid : _T_5201 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_28 = _remapindex_T + 7'h1C; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_118 = _remapindex_T_28 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_28 = _GEN_118[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5233 = remapindex_28 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5234 = remapindex_28 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5235 = remapindex_28 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5236 = remapindex_28 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5237 = remapindex_28 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5238 = remapindex_28 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5239 = remapindex_28 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5240 = remapindex_28 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5241 = remapindex_28 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5242 = remapindex_28 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5243 = remapindex_28 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5244 = remapindex_28 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5245 = remapindex_28 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5246 = remapindex_28 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5247 = remapindex_28 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5248 = remapindex_28 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5249 = remapindex_28 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5250 = remapindex_28 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5251 = remapindex_28 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5252 = remapindex_28 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5253 = remapindex_28 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5254 = remapindex_28 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5255 = remapindex_28 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5256 = remapindex_28 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5257 = remapindex_28 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5258 = remapindex_28 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5259 = remapindex_28 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5260 = remapindex_28 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5261 = remapindex_28 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5262 = remapindex_28 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5263 = remapindex_28 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5264 = remapindex_28 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_28 = _T_5264 ? _Queue16_UInt8_31_io_deq_bits : _T_5263 ? _Queue16_UInt8_30_io_deq_bits : _T_5262 ? _Queue16_UInt8_29_io_deq_bits : _T_5261 ? _Queue16_UInt8_28_io_deq_bits : _T_5260 ? _Queue16_UInt8_27_io_deq_bits : _T_5259 ? _Queue16_UInt8_26_io_deq_bits : _T_5258 ? _Queue16_UInt8_25_io_deq_bits : _T_5257 ? _Queue16_UInt8_24_io_deq_bits : _T_5256 ? _Queue16_UInt8_23_io_deq_bits : _T_5255 ? _Queue16_UInt8_22_io_deq_bits : _T_5254 ? _Queue16_UInt8_21_io_deq_bits : _T_5253 ? _Queue16_UInt8_20_io_deq_bits : _T_5252 ? _Queue16_UInt8_19_io_deq_bits : _T_5251 ? _Queue16_UInt8_18_io_deq_bits : _T_5250 ? _Queue16_UInt8_17_io_deq_bits : _T_5249 ? _Queue16_UInt8_16_io_deq_bits : _T_5248 ? _Queue16_UInt8_15_io_deq_bits : _T_5247 ? _Queue16_UInt8_14_io_deq_bits : _T_5246 ? _Queue16_UInt8_13_io_deq_bits : _T_5245 ? _Queue16_UInt8_12_io_deq_bits : _T_5244 ? _Queue16_UInt8_11_io_deq_bits : _T_5243 ? _Queue16_UInt8_10_io_deq_bits : _T_5242 ? _Queue16_UInt8_9_io_deq_bits : _T_5241 ? _Queue16_UInt8_8_io_deq_bits : _T_5240 ? _Queue16_UInt8_7_io_deq_bits : _T_5239 ? _Queue16_UInt8_6_io_deq_bits : _T_5238 ? _Queue16_UInt8_5_io_deq_bits : _T_5237 ? _Queue16_UInt8_4_io_deq_bits : _T_5236 ? _Queue16_UInt8_3_io_deq_bits : _T_5235 ? _Queue16_UInt8_2_io_deq_bits : _T_5234 ? _Queue16_UInt8_1_io_deq_bits : _T_5233 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_28 = _T_5264 ? _Queue16_UInt8_31_io_deq_valid : _T_5263 ? _Queue16_UInt8_30_io_deq_valid : _T_5262 ? _Queue16_UInt8_29_io_deq_valid : _T_5261 ? _Queue16_UInt8_28_io_deq_valid : _T_5260 ? _Queue16_UInt8_27_io_deq_valid : _T_5259 ? _Queue16_UInt8_26_io_deq_valid : _T_5258 ? _Queue16_UInt8_25_io_deq_valid : _T_5257 ? _Queue16_UInt8_24_io_deq_valid : _T_5256 ? _Queue16_UInt8_23_io_deq_valid : _T_5255 ? _Queue16_UInt8_22_io_deq_valid : _T_5254 ? _Queue16_UInt8_21_io_deq_valid : _T_5253 ? _Queue16_UInt8_20_io_deq_valid : _T_5252 ? _Queue16_UInt8_19_io_deq_valid : _T_5251 ? _Queue16_UInt8_18_io_deq_valid : _T_5250 ? _Queue16_UInt8_17_io_deq_valid : _T_5249 ? _Queue16_UInt8_16_io_deq_valid : _T_5248 ? _Queue16_UInt8_15_io_deq_valid : _T_5247 ? _Queue16_UInt8_14_io_deq_valid : _T_5246 ? _Queue16_UInt8_13_io_deq_valid : _T_5245 ? _Queue16_UInt8_12_io_deq_valid : _T_5244 ? _Queue16_UInt8_11_io_deq_valid : _T_5243 ? _Queue16_UInt8_10_io_deq_valid : _T_5242 ? _Queue16_UInt8_9_io_deq_valid : _T_5241 ? _Queue16_UInt8_8_io_deq_valid : _T_5240 ? _Queue16_UInt8_7_io_deq_valid : _T_5239 ? _Queue16_UInt8_6_io_deq_valid : _T_5238 ? _Queue16_UInt8_5_io_deq_valid : _T_5237 ? _Queue16_UInt8_4_io_deq_valid : _T_5236 ? _Queue16_UInt8_3_io_deq_valid : _T_5235 ? _Queue16_UInt8_2_io_deq_valid : _T_5234 ? _Queue16_UInt8_1_io_deq_valid : _T_5233 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_29 = _remapindex_T + 7'h1D; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_119 = _remapindex_T_29 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_29 = _GEN_119[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5265 = remapindex_29 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5266 = remapindex_29 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5267 = remapindex_29 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5268 = remapindex_29 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5269 = remapindex_29 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5270 = remapindex_29 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5271 = remapindex_29 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5272 = remapindex_29 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5273 = remapindex_29 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5274 = remapindex_29 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5275 = remapindex_29 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5276 = remapindex_29 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5277 = remapindex_29 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5278 = remapindex_29 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5279 = remapindex_29 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5280 = remapindex_29 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5281 = remapindex_29 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5282 = remapindex_29 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5283 = remapindex_29 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5284 = remapindex_29 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5285 = remapindex_29 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5286 = remapindex_29 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5287 = remapindex_29 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5288 = remapindex_29 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5289 = remapindex_29 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5290 = remapindex_29 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5291 = remapindex_29 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5292 = remapindex_29 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5293 = remapindex_29 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5294 = remapindex_29 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5295 = remapindex_29 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5296 = remapindex_29 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_29 = _T_5296 ? _Queue16_UInt8_31_io_deq_bits : _T_5295 ? _Queue16_UInt8_30_io_deq_bits : _T_5294 ? _Queue16_UInt8_29_io_deq_bits : _T_5293 ? _Queue16_UInt8_28_io_deq_bits : _T_5292 ? _Queue16_UInt8_27_io_deq_bits : _T_5291 ? _Queue16_UInt8_26_io_deq_bits : _T_5290 ? _Queue16_UInt8_25_io_deq_bits : _T_5289 ? _Queue16_UInt8_24_io_deq_bits : _T_5288 ? _Queue16_UInt8_23_io_deq_bits : _T_5287 ? _Queue16_UInt8_22_io_deq_bits : _T_5286 ? _Queue16_UInt8_21_io_deq_bits : _T_5285 ? _Queue16_UInt8_20_io_deq_bits : _T_5284 ? _Queue16_UInt8_19_io_deq_bits : _T_5283 ? _Queue16_UInt8_18_io_deq_bits : _T_5282 ? _Queue16_UInt8_17_io_deq_bits : _T_5281 ? _Queue16_UInt8_16_io_deq_bits : _T_5280 ? _Queue16_UInt8_15_io_deq_bits : _T_5279 ? _Queue16_UInt8_14_io_deq_bits : _T_5278 ? _Queue16_UInt8_13_io_deq_bits : _T_5277 ? _Queue16_UInt8_12_io_deq_bits : _T_5276 ? _Queue16_UInt8_11_io_deq_bits : _T_5275 ? _Queue16_UInt8_10_io_deq_bits : _T_5274 ? _Queue16_UInt8_9_io_deq_bits : _T_5273 ? _Queue16_UInt8_8_io_deq_bits : _T_5272 ? _Queue16_UInt8_7_io_deq_bits : _T_5271 ? _Queue16_UInt8_6_io_deq_bits : _T_5270 ? _Queue16_UInt8_5_io_deq_bits : _T_5269 ? _Queue16_UInt8_4_io_deq_bits : _T_5268 ? _Queue16_UInt8_3_io_deq_bits : _T_5267 ? _Queue16_UInt8_2_io_deq_bits : _T_5266 ? _Queue16_UInt8_1_io_deq_bits : _T_5265 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_29 = _T_5296 ? _Queue16_UInt8_31_io_deq_valid : _T_5295 ? _Queue16_UInt8_30_io_deq_valid : _T_5294 ? _Queue16_UInt8_29_io_deq_valid : _T_5293 ? _Queue16_UInt8_28_io_deq_valid : _T_5292 ? _Queue16_UInt8_27_io_deq_valid : _T_5291 ? _Queue16_UInt8_26_io_deq_valid : _T_5290 ? _Queue16_UInt8_25_io_deq_valid : _T_5289 ? _Queue16_UInt8_24_io_deq_valid : _T_5288 ? _Queue16_UInt8_23_io_deq_valid : _T_5287 ? _Queue16_UInt8_22_io_deq_valid : _T_5286 ? _Queue16_UInt8_21_io_deq_valid : _T_5285 ? _Queue16_UInt8_20_io_deq_valid : _T_5284 ? _Queue16_UInt8_19_io_deq_valid : _T_5283 ? _Queue16_UInt8_18_io_deq_valid : _T_5282 ? _Queue16_UInt8_17_io_deq_valid : _T_5281 ? _Queue16_UInt8_16_io_deq_valid : _T_5280 ? _Queue16_UInt8_15_io_deq_valid : _T_5279 ? _Queue16_UInt8_14_io_deq_valid : _T_5278 ? _Queue16_UInt8_13_io_deq_valid : _T_5277 ? _Queue16_UInt8_12_io_deq_valid : _T_5276 ? _Queue16_UInt8_11_io_deq_valid : _T_5275 ? _Queue16_UInt8_10_io_deq_valid : _T_5274 ? _Queue16_UInt8_9_io_deq_valid : _T_5273 ? _Queue16_UInt8_8_io_deq_valid : _T_5272 ? _Queue16_UInt8_7_io_deq_valid : _T_5271 ? _Queue16_UInt8_6_io_deq_valid : _T_5270 ? _Queue16_UInt8_5_io_deq_valid : _T_5269 ? _Queue16_UInt8_4_io_deq_valid : _T_5268 ? _Queue16_UInt8_3_io_deq_valid : _T_5267 ? _Queue16_UInt8_2_io_deq_valid : _T_5266 ? _Queue16_UInt8_1_io_deq_valid : _T_5265 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_30 = _remapindex_T + 7'h1E; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_120 = _remapindex_T_30 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_30 = _GEN_120[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5297 = remapindex_30 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5298 = remapindex_30 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5299 = remapindex_30 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5300 = remapindex_30 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5301 = remapindex_30 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5302 = remapindex_30 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5303 = remapindex_30 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5304 = remapindex_30 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5305 = remapindex_30 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5306 = remapindex_30 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5307 = remapindex_30 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5308 = remapindex_30 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5309 = remapindex_30 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5310 = remapindex_30 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5311 = remapindex_30 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5312 = remapindex_30 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5313 = remapindex_30 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5314 = remapindex_30 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5315 = remapindex_30 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5316 = remapindex_30 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5317 = remapindex_30 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5318 = remapindex_30 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5319 = remapindex_30 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5320 = remapindex_30 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5321 = remapindex_30 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5322 = remapindex_30 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5323 = remapindex_30 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5324 = remapindex_30 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5325 = remapindex_30 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5326 = remapindex_30 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5327 = remapindex_30 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5328 = remapindex_30 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_30 = _T_5328 ? _Queue16_UInt8_31_io_deq_bits : _T_5327 ? _Queue16_UInt8_30_io_deq_bits : _T_5326 ? _Queue16_UInt8_29_io_deq_bits : _T_5325 ? _Queue16_UInt8_28_io_deq_bits : _T_5324 ? _Queue16_UInt8_27_io_deq_bits : _T_5323 ? _Queue16_UInt8_26_io_deq_bits : _T_5322 ? _Queue16_UInt8_25_io_deq_bits : _T_5321 ? _Queue16_UInt8_24_io_deq_bits : _T_5320 ? _Queue16_UInt8_23_io_deq_bits : _T_5319 ? _Queue16_UInt8_22_io_deq_bits : _T_5318 ? _Queue16_UInt8_21_io_deq_bits : _T_5317 ? _Queue16_UInt8_20_io_deq_bits : _T_5316 ? _Queue16_UInt8_19_io_deq_bits : _T_5315 ? _Queue16_UInt8_18_io_deq_bits : _T_5314 ? _Queue16_UInt8_17_io_deq_bits : _T_5313 ? _Queue16_UInt8_16_io_deq_bits : _T_5312 ? _Queue16_UInt8_15_io_deq_bits : _T_5311 ? _Queue16_UInt8_14_io_deq_bits : _T_5310 ? _Queue16_UInt8_13_io_deq_bits : _T_5309 ? _Queue16_UInt8_12_io_deq_bits : _T_5308 ? _Queue16_UInt8_11_io_deq_bits : _T_5307 ? _Queue16_UInt8_10_io_deq_bits : _T_5306 ? _Queue16_UInt8_9_io_deq_bits : _T_5305 ? _Queue16_UInt8_8_io_deq_bits : _T_5304 ? _Queue16_UInt8_7_io_deq_bits : _T_5303 ? _Queue16_UInt8_6_io_deq_bits : _T_5302 ? _Queue16_UInt8_5_io_deq_bits : _T_5301 ? _Queue16_UInt8_4_io_deq_bits : _T_5300 ? _Queue16_UInt8_3_io_deq_bits : _T_5299 ? _Queue16_UInt8_2_io_deq_bits : _T_5298 ? _Queue16_UInt8_1_io_deq_bits : _T_5297 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_30 = _T_5328 ? _Queue16_UInt8_31_io_deq_valid : _T_5327 ? _Queue16_UInt8_30_io_deq_valid : _T_5326 ? _Queue16_UInt8_29_io_deq_valid : _T_5325 ? _Queue16_UInt8_28_io_deq_valid : _T_5324 ? _Queue16_UInt8_27_io_deq_valid : _T_5323 ? _Queue16_UInt8_26_io_deq_valid : _T_5322 ? _Queue16_UInt8_25_io_deq_valid : _T_5321 ? _Queue16_UInt8_24_io_deq_valid : _T_5320 ? _Queue16_UInt8_23_io_deq_valid : _T_5319 ? _Queue16_UInt8_22_io_deq_valid : _T_5318 ? _Queue16_UInt8_21_io_deq_valid : _T_5317 ? _Queue16_UInt8_20_io_deq_valid : _T_5316 ? _Queue16_UInt8_19_io_deq_valid : _T_5315 ? _Queue16_UInt8_18_io_deq_valid : _T_5314 ? _Queue16_UInt8_17_io_deq_valid : _T_5313 ? _Queue16_UInt8_16_io_deq_valid : _T_5312 ? _Queue16_UInt8_15_io_deq_valid : _T_5311 ? _Queue16_UInt8_14_io_deq_valid : _T_5310 ? _Queue16_UInt8_13_io_deq_valid : _T_5309 ? _Queue16_UInt8_12_io_deq_valid : _T_5308 ? _Queue16_UInt8_11_io_deq_valid : _T_5307 ? _Queue16_UInt8_10_io_deq_valid : _T_5306 ? _Queue16_UInt8_9_io_deq_valid : _T_5305 ? _Queue16_UInt8_8_io_deq_valid : _T_5304 ? _Queue16_UInt8_7_io_deq_valid : _T_5303 ? _Queue16_UInt8_6_io_deq_valid : _T_5302 ? _Queue16_UInt8_5_io_deq_valid : _T_5301 ? _Queue16_UInt8_4_io_deq_valid : _T_5300 ? _Queue16_UInt8_3_io_deq_valid : _T_5299 ? _Queue16_UInt8_2_io_deq_valid : _T_5298 ? _Queue16_UInt8_1_io_deq_valid : _T_5297 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [6:0] _remapindex_T_31 = _remapindex_T + 7'h1F; // @[ZstdCompressorMemWriter.scala:153:33] wire [6:0] _GEN_121 = _remapindex_T_31 % 7'h20; // @[ZstdCompressorMemWriter.scala:153:{33,54}] wire [5:0] remapindex_31 = _GEN_121[5:0]; // @[ZstdCompressorMemWriter.scala:153:54] wire _T_5329 = remapindex_31 == 6'h0; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5330 = remapindex_31 == 6'h1; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5331 = remapindex_31 == 6'h2; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5332 = remapindex_31 == 6'h3; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5333 = remapindex_31 == 6'h4; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5334 = remapindex_31 == 6'h5; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5335 = remapindex_31 == 6'h6; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5336 = remapindex_31 == 6'h7; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5337 = remapindex_31 == 6'h8; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5338 = remapindex_31 == 6'h9; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5339 = remapindex_31 == 6'hA; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5340 = remapindex_31 == 6'hB; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5341 = remapindex_31 == 6'hC; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5342 = remapindex_31 == 6'hD; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5343 = remapindex_31 == 6'hE; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5344 = remapindex_31 == 6'hF; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5345 = remapindex_31 == 6'h10; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5346 = remapindex_31 == 6'h11; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5347 = remapindex_31 == 6'h12; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5348 = remapindex_31 == 6'h13; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5349 = remapindex_31 == 6'h14; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5350 = remapindex_31 == 6'h15; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5351 = remapindex_31 == 6'h16; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5352 = remapindex_31 == 6'h17; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5353 = remapindex_31 == 6'h18; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5354 = remapindex_31 == 6'h19; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5355 = remapindex_31 == 6'h1A; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5356 = remapindex_31 == 6'h1B; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5357 = remapindex_31 == 6'h1C; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5358 = remapindex_31 == 6'h1D; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5359 = remapindex_31 == 6'h1E; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] wire _T_5360 = remapindex_31 == 6'h1F; // @[ZstdCompressorMemWriter.scala:153:54, :155:17] assign remapVecData_31 = _T_5360 ? _Queue16_UInt8_31_io_deq_bits : _T_5359 ? _Queue16_UInt8_30_io_deq_bits : _T_5358 ? _Queue16_UInt8_29_io_deq_bits : _T_5357 ? _Queue16_UInt8_28_io_deq_bits : _T_5356 ? _Queue16_UInt8_27_io_deq_bits : _T_5355 ? _Queue16_UInt8_26_io_deq_bits : _T_5354 ? _Queue16_UInt8_25_io_deq_bits : _T_5353 ? _Queue16_UInt8_24_io_deq_bits : _T_5352 ? _Queue16_UInt8_23_io_deq_bits : _T_5351 ? _Queue16_UInt8_22_io_deq_bits : _T_5350 ? _Queue16_UInt8_21_io_deq_bits : _T_5349 ? _Queue16_UInt8_20_io_deq_bits : _T_5348 ? _Queue16_UInt8_19_io_deq_bits : _T_5347 ? _Queue16_UInt8_18_io_deq_bits : _T_5346 ? _Queue16_UInt8_17_io_deq_bits : _T_5345 ? _Queue16_UInt8_16_io_deq_bits : _T_5344 ? _Queue16_UInt8_15_io_deq_bits : _T_5343 ? _Queue16_UInt8_14_io_deq_bits : _T_5342 ? _Queue16_UInt8_13_io_deq_bits : _T_5341 ? _Queue16_UInt8_12_io_deq_bits : _T_5340 ? _Queue16_UInt8_11_io_deq_bits : _T_5339 ? _Queue16_UInt8_10_io_deq_bits : _T_5338 ? _Queue16_UInt8_9_io_deq_bits : _T_5337 ? _Queue16_UInt8_8_io_deq_bits : _T_5336 ? _Queue16_UInt8_7_io_deq_bits : _T_5335 ? _Queue16_UInt8_6_io_deq_bits : _T_5334 ? _Queue16_UInt8_5_io_deq_bits : _T_5333 ? _Queue16_UInt8_4_io_deq_bits : _T_5332 ? _Queue16_UInt8_3_io_deq_bits : _T_5331 ? _Queue16_UInt8_2_io_deq_bits : _T_5330 ? _Queue16_UInt8_1_io_deq_bits : _T_5329 ? _Queue16_UInt8_io_deq_bits : 8'h0; // @[ZstdCompressorMemWriter.scala:77:52, :141:26, :147:27, :155:{17,33}, :156:31] assign remapVecValids_31 = _T_5360 ? _Queue16_UInt8_31_io_deq_valid : _T_5359 ? _Queue16_UInt8_30_io_deq_valid : _T_5358 ? _Queue16_UInt8_29_io_deq_valid : _T_5357 ? _Queue16_UInt8_28_io_deq_valid : _T_5356 ? _Queue16_UInt8_27_io_deq_valid : _T_5355 ? _Queue16_UInt8_26_io_deq_valid : _T_5354 ? _Queue16_UInt8_25_io_deq_valid : _T_5353 ? _Queue16_UInt8_24_io_deq_valid : _T_5352 ? _Queue16_UInt8_23_io_deq_valid : _T_5351 ? _Queue16_UInt8_22_io_deq_valid : _T_5350 ? _Queue16_UInt8_21_io_deq_valid : _T_5349 ? _Queue16_UInt8_20_io_deq_valid : _T_5348 ? _Queue16_UInt8_19_io_deq_valid : _T_5347 ? _Queue16_UInt8_18_io_deq_valid : _T_5346 ? _Queue16_UInt8_17_io_deq_valid : _T_5345 ? _Queue16_UInt8_16_io_deq_valid : _T_5344 ? _Queue16_UInt8_15_io_deq_valid : _T_5343 ? _Queue16_UInt8_14_io_deq_valid : _T_5342 ? _Queue16_UInt8_13_io_deq_valid : _T_5341 ? _Queue16_UInt8_12_io_deq_valid : _T_5340 ? _Queue16_UInt8_11_io_deq_valid : _T_5339 ? _Queue16_UInt8_10_io_deq_valid : _T_5338 ? _Queue16_UInt8_9_io_deq_valid : _T_5337 ? _Queue16_UInt8_8_io_deq_valid : _T_5336 ? _Queue16_UInt8_7_io_deq_valid : _T_5335 ? _Queue16_UInt8_6_io_deq_valid : _T_5334 ? _Queue16_UInt8_5_io_deq_valid : _T_5333 ? _Queue16_UInt8_4_io_deq_valid : _T_5332 ? _Queue16_UInt8_3_io_deq_valid : _T_5331 ? _Queue16_UInt8_2_io_deq_valid : _T_5330 ? _Queue16_UInt8_1_io_deq_valid : _T_5329 & _Queue16_UInt8_io_deq_valid; // @[ZstdCompressorMemWriter.scala:77:52, :142:28, :148:29, :155:{17,33}, :157:33] wire [1:0] _count_valids_T = {1'h0, remapVecValids_0} + {1'h0, remapVecValids_1}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [2:0] _count_valids_T_1 = {1'h0, _count_valids_T} + {2'h0, remapVecValids_2}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [3:0] _count_valids_T_2 = {1'h0, _count_valids_T_1} + {3'h0, remapVecValids_3}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [4:0] _count_valids_T_3 = {1'h0, _count_valids_T_2} + {4'h0, remapVecValids_4}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [5:0] _count_valids_T_4 = {1'h0, _count_valids_T_3} + {5'h0, remapVecValids_5}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [6:0] _count_valids_T_5 = {1'h0, _count_valids_T_4} + {6'h0, remapVecValids_6}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [7:0] _count_valids_T_6 = {1'h0, _count_valids_T_5} + {7'h0, remapVecValids_7}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [8:0] _count_valids_T_7 = {1'h0, _count_valids_T_6} + {8'h0, remapVecValids_8}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [9:0] _count_valids_T_8 = {1'h0, _count_valids_T_7} + {9'h0, remapVecValids_9}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [10:0] _count_valids_T_9 = {1'h0, _count_valids_T_8} + {10'h0, remapVecValids_10}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [11:0] _count_valids_T_10 = {1'h0, _count_valids_T_9} + {11'h0, remapVecValids_11}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [12:0] _count_valids_T_11 = {1'h0, _count_valids_T_10} + {12'h0, remapVecValids_12}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [13:0] _count_valids_T_12 = {1'h0, _count_valids_T_11} + {13'h0, remapVecValids_13}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [14:0] _count_valids_T_13 = {1'h0, _count_valids_T_12} + {14'h0, remapVecValids_14}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [15:0] _count_valids_T_14 = {1'h0, _count_valids_T_13} + {15'h0, remapVecValids_15}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [16:0] _count_valids_T_15 = {1'h0, _count_valids_T_14} + {16'h0, remapVecValids_16}; // @[ZstdCompressorMemWriter.scala:89:{76,90}, :142:28, :163:60] wire [17:0] _count_valids_T_16 = {1'h0, _count_valids_T_15} + {17'h0, remapVecValids_17}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [18:0] _count_valids_T_17 = {1'h0, _count_valids_T_16} + {18'h0, remapVecValids_18}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [19:0] _count_valids_T_18 = {1'h0, _count_valids_T_17} + {19'h0, remapVecValids_19}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [20:0] _count_valids_T_19 = {1'h0, _count_valids_T_18} + {20'h0, remapVecValids_20}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [21:0] _count_valids_T_20 = {1'h0, _count_valids_T_19} + {21'h0, remapVecValids_21}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [22:0] _count_valids_T_21 = {1'h0, _count_valids_T_20} + {22'h0, remapVecValids_22}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [23:0] _count_valids_T_22 = {1'h0, _count_valids_T_21} + {23'h0, remapVecValids_23}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [24:0] _count_valids_T_23 = {1'h0, _count_valids_T_22} + {24'h0, remapVecValids_24}; // @[ZstdCompressorMemWriter.scala:89:{76,90}, :142:28, :163:60] wire [25:0] _count_valids_T_24 = {1'h0, _count_valids_T_23} + {25'h0, remapVecValids_25}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [26:0] _count_valids_T_25 = {1'h0, _count_valids_T_24} + {26'h0, remapVecValids_26}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [27:0] _count_valids_T_26 = {1'h0, _count_valids_T_25} + {27'h0, remapVecValids_27}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [28:0] _count_valids_T_27 = {1'h0, _count_valids_T_26} + {28'h0, remapVecValids_28}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [29:0] _count_valids_T_28 = {1'h0, _count_valids_T_27} + {29'h0, remapVecValids_29}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [30:0] _count_valids_T_29 = {1'h0, _count_valids_T_28} + {30'h0, remapVecValids_30}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] wire [31:0] count_valids = {1'h0, _count_valids_T_29} + {31'h0, remapVecValids_31}; // @[ZstdCompressorMemWriter.scala:142:28, :163:60] reg [63:0] backend_bytes_written; // @[ZstdCompressorMemWriter.scala:167:38] wire [64:0] _GEN_122 = {1'h0, backend_bytes_written}; // @[ZstdCompressorMemWriter.scala:167:38, :168:60] wire [64:0] _backend_next_write_addr_T = {1'h0, _dest_info_Q_io_deq_bits_op} + _GEN_122; // @[ZstdCompressorMemWriter.scala:39:27, :168:60] wire [63:0] backend_next_write_addr = _backend_next_write_addr_T[63:0]; // @[ZstdCompressorMemWriter.scala:168:60] wire [64:0] _throttle_end_T = {1'h0, _buf_lens_Q_io_deq_bits} - _GEN_122; // @[ZstdCompressorMemWriter.scala:52:26, :168:60, :171:28] wire [63:0] _throttle_end_T_1 = _throttle_end_T[63:0]; // @[ZstdCompressorMemWriter.scala:171:28] wire [63:0] throttle_end = _buf_lens_Q_io_deq_valid ? _throttle_end_T_1 : 64'h20; // @[ZstdCompressorMemWriter.scala:52:26, :170:25, :171:28] wire _throttle_end_writeable_T = \|(throttle_end[63:5]); // @[ZstdCompressorMemWriter.scala:170:25, :174:49] wire _throttle_end_writeable_T_1 = throttle_end[4]; // @[ZstdCompressorMemWriter.scala:170:25, :175:53] wire _throttle_end_writeable_log2_T_1 = throttle_end[4]; // @[ZstdCompressorMemWriter.scala:170:25, :175:53, :183:55] wire _throttle_end_writeable_T_2 = throttle_end[3]; // @[ZstdCompressorMemWriter.scala:170:25, :176:55] wire _throttle_end_writeable_log2_T_2 = throttle_end[3]; // @[ZstdCompressorMemWriter.scala:170:25, :176:55, :184:57] wire _throttle_end_writeable_T_3 = throttle_end[2]; // @[ZstdCompressorMemWriter.scala:170:25, :177:57] wire _throttle_end_writeable_log2_T_3 = throttle_end[2]; // @[ZstdCompressorMemWriter.scala:170:25, :177:57, :185:59] wire _throttle_end_writeable_T_4 = throttle_end[1]; // @[ZstdCompressorMemWriter.scala:170:25, :178:59] wire _throttle_end_writeable_log2_T_4 = throttle_end[1]; // @[ZstdCompressorMemWriter.scala:170:25, :178:59, :186:61] wire _throttle_end_writeable_T_5 = throttle_end[0]; // @[ZstdCompressorMemWriter.scala:170:25, :179:61] wire _throttle_end_writeable_log2_T_5 = throttle_end[0]; // @[ZstdCompressorMemWriter.scala:170:25, :179:61, :187:63] wire _throttle_end_writeable_T_6 = _throttle_end_writeable_T_5; // @[ZstdCompressorMemWriter.scala:179:{48,61}] wire [1:0] _throttle_end_writeable_T_7 = _throttle_end_writeable_T_4 ? 2'h2 : {1'h0, _throttle_end_writeable_T_6}; // @[ZstdCompressorMemWriter.scala:178:{46,59}, :179:48] wire [2:0] _throttle_end_writeable_T_8 = _throttle_end_writeable_T_3 ? 3'h4 : {1'h0, _throttle_end_writeable_T_7}; // @[ZstdCompressorMemWriter.scala:177:{44,57}, :178:46] wire [3:0] _throttle_end_writeable_T_9 = _throttle_end_writeable_T_2 ? 4'h8 : {1'h0, _throttle_end_writeable_T_8}; // @[ZstdCompressorMemWriter.scala:176:{42,55}, :177:44] wire [4:0] _throttle_end_writeable_T_10 = _throttle_end_writeable_T_1 ? 5'h10 : {1'h0, _throttle_end_writeable_T_9}; // @[ZstdCompressorMemWriter.scala:175:{40,53}, :176:42] wire [5:0] throttle_end_writeable = _throttle_end_writeable_T ? 6'h20 : {1'h0, _throttle_end_writeable_T_10}; // @[ZstdCompressorMemWriter.scala:174:{35,49}, :175:40] wire _throttle_end_writeable_log2_T = \|(throttle_end[63:5]); // @[ZstdCompressorMemWriter.scala:170:25, :174:49, :182:54] wire _throttle_end_writeable_log2_T_7 = _throttle_end_writeable_log2_T_4; // @[ZstdCompressorMemWriter.scala:186:{48,61}] wire [1:0] _throttle_end_writeable_log2_T_8 = _throttle_end_writeable_log2_T_3 ? 2'h2 : {1'h0, _throttle_end_writeable_log2_T_7}; // @[ZstdCompressorMemWriter.scala:185:{46,59}, :186:48] wire [1:0] _throttle_end_writeable_log2_T_9 = _throttle_end_writeable_log2_T_2 ? 2'h3 : _throttle_end_writeable_log2_T_8; // @[ZstdCompressorMemWriter.scala:184:{44,57}, :185:46] wire [2:0] _throttle_end_writeable_log2_T_10 = _throttle_end_writeable_log2_T_1 ? 3'h4 : {1'h0, _throttle_end_writeable_log2_T_9}; // @[ZstdCompressorMemWriter.scala:183:{42,55}, :184:44] wire [2:0] throttle_end_writeable_log2 = _throttle_end_writeable_log2_T ? 3'h5 : _throttle_end_writeable_log2_T_10; // @[ZstdCompressorMemWriter.scala:182:{40,54}, :183:42] wire _ptr_align_max_bytes_writeable_T = backend_next_write_addr[0]; // @[ZstdCompressorMemWriter.scala:168:60, :191:66] wire _ptr_align_max_bytes_writeable_log2_T = backend_next_write_addr[0]; // @[ZstdCompressorMemWriter.scala:168:60, :191:66, :198:71] wire _ptr_align_max_bytes_writeable_T_1 = backend_next_write_addr[1]; // @[ZstdCompressorMemWriter.scala:168:60, :192:68] wire _ptr_align_max_bytes_writeable_log2_T_1 = backend_next_write_addr[1]; // @[ZstdCompressorMemWriter.scala:168:60, :192:68, :199:72] wire _ptr_align_max_bytes_writeable_T_2 = backend_next_write_addr[2]; // @[ZstdCompressorMemWriter.scala:168:60, :193:70] wire _ptr_align_max_bytes_writeable_log2_T_2 = backend_next_write_addr[2]; // @[ZstdCompressorMemWriter.scala:168:60, :193:70, :200:74] wire _ptr_align_max_bytes_writeable_T_3 = backend_next_write_addr[3]; // @[ZstdCompressorMemWriter.scala:168:60, :194:72] wire _ptr_align_max_bytes_writeable_log2_T_3 = backend_next_write_addr[3]; // @[ZstdCompressorMemWriter.scala:168:60, :194:72, :201:76] wire _ptr_align_max_bytes_writeable_T_4 = backend_next_write_addr[4]; // @[ZstdCompressorMemWriter.scala:168:60, :195:74] wire _ptr_align_max_bytes_writeable_log2_T_4 = backend_next_write_addr[4]; // @[ZstdCompressorMemWriter.scala:168:60, :195:74, :202:78] wire [5:0] _ptr_align_max_bytes_writeable_T_5 = _ptr_align_max_bytes_writeable_T_4 ? 6'h10 : 6'h20; // @[ZstdCompressorMemWriter.scala:195:{50,74}] wire [5:0] _ptr_align_max_bytes_writeable_T_6 = _ptr_align_max_bytes_writeable_T_3 ? 6'h8 : _ptr_align_max_bytes_writeable_T_5; // @[ZstdCompressorMemWriter.scala:194:{48,72}, :195:50] wire [5:0] _ptr_align_max_bytes_writeable_T_7 = _ptr_align_max_bytes_writeable_T_2 ? 6'h4 : _ptr_align_max_bytes_writeable_T_6; // @[ZstdCompressorMemWriter.scala:193:{46,70}, :194:48] wire [5:0] _ptr_align_max_bytes_writeable_T_8 = _ptr_align_max_bytes_writeable_T_1 ? 6'h2 : _ptr_align_max_bytes_writeable_T_7; // @[ZstdCompressorMemWriter.scala:192:{44,68}, :193:46] wire [5:0] ptr_align_max_bytes_writeable = _ptr_align_max_bytes_writeable_T ? 6'h1 : _ptr_align_max_bytes_writeable_T_8; // @[ZstdCompressorMemWriter.scala:191:{42,66}, :192:44] wire [2:0] _ptr_align_max_bytes_writeable_log2_T_5 = {2'h2, ~_ptr_align_max_bytes_writeable_log2_T_4}; // @[ZstdCompressorMemWriter.scala:202:{54,78}] wire [2:0] _ptr_align_max_bytes_writeable_log2_T_6 = _ptr_align_max_bytes_writeable_log2_T_3 ? 3'h3 : _ptr_align_max_bytes_writeable_log2_T_5; // @[ZstdCompressorMemWriter.scala:201:{52,76}, :202:54] wire [2:0] _ptr_align_max_bytes_writeable_log2_T_7 = _ptr_align_max_bytes_writeable_log2_T_2 ? 3'h2 : _ptr_align_max_bytes_writeable_log2_T_6; // @[ZstdCompressorMemWriter.scala:200:{50,74}, :201:52] wire [2:0] _ptr_align_max_bytes_writeable_log2_T_8 = _ptr_align_max_bytes_writeable_log2_T_1 ? 3'h1 : _ptr_align_max_bytes_writeable_log2_T_7; // @[ZstdCompressorMemWriter.scala:199:{48,72}, :200:50] wire [2:0] ptr_align_max_bytes_writeable_log2 = _ptr_align_max_bytes_writeable_log2_T ? 3'h0 : _ptr_align_max_bytes_writeable_log2_T_8; // @[ZstdCompressorMemWriter.scala:198:{47,71}, :199:48] wire _count_valids_largest_aligned_T = count_valids[5]; // @[ZstdCompressorMemWriter.scala:163:60, :205:54] wire _count_valids_largest_aligned_log2_T = count_valids[5]; // @[ZstdCompressorMemWriter.scala:163:60, :205:54, :213:59] wire _count_valids_largest_aligned_T_1 = count_valids[4]; // @[ZstdCompressorMemWriter.scala:163:60, :206:55] wire _count_valids_largest_aligned_log2_T_1 = count_valids[4]; // @[ZstdCompressorMemWriter.scala:163:60, :206:55, :214:61] wire _count_valids_largest_aligned_T_2 = count_valids[3]; // @[ZstdCompressorMemWriter.scala:163:60, :207:57] wire _count_valids_largest_aligned_log2_T_2 = count_valids[3]; // @[ZstdCompressorMemWriter.scala:163:60, :207:57, :215:63] wire _count_valids_largest_aligned_T_3 = count_valids[2]; // @[ZstdCompressorMemWriter.scala:163:60, :208:59] wire _count_valids_largest_aligned_log2_T_3 = count_valids[2]; // @[ZstdCompressorMemWriter.scala:163:60, :208:59, :216:65] wire _count_valids_largest_aligned_T_4 = count_valids[1]; // @[ZstdCompressorMemWriter.scala:163:60, :209:61] wire _count_valids_largest_aligned_log2_T_4 = count_valids[1]; // @[ZstdCompressorMemWriter.scala:163:60, :209:61, :217:67] wire _count_valids_largest_aligned_T_5 = count_valids[0]; // @[ZstdCompressorMemWriter.scala:163:60, :210:63] wire _count_valids_largest_aligned_log2_T_5 = count_valids[0]; // @[ZstdCompressorMemWriter.scala:163:60, :210:63, :218:69] wire _count_valids_largest_aligned_T_6 = _count_valids_largest_aligned_T_5; // @[ZstdCompressorMemWriter.scala:210:{50,63}] wire [1:0] _count_valids_largest_aligned_T_7 = _count_valids_largest_aligned_T_4 ? 2'h2 : {1'h0, _count_valids_largest_aligned_T_6}; // @[ZstdCompressorMemWriter.scala:209:{48,61}, :210:50] wire [2:0] _count_valids_largest_aligned_T_8 = _count_valids_largest_aligned_T_3 ? 3'h4 : {1'h0, _count_valids_largest_aligned_T_7}; // @[ZstdCompressorMemWriter.scala:208:{46,59}, :209:48] wire [3:0] _count_valids_largest_aligned_T_9 = _count_valids_largest_aligned_T_2 ? 4'h8 : {1'h0, _count_valids_largest_aligned_T_8}; // @[ZstdCompressorMemWriter.scala:207:{44,57}, :208:46] wire [4:0] _count_valids_largest_aligned_T_10 = _count_valids_largest_aligned_T_1 ? 5'h10 : {1'h0, _count_valids_largest_aligned_T_9}; // @[ZstdCompressorMemWriter.scala:206:{42,55}, :207:44] wire [5:0] count_valids_largest_aligned = _count_valids_largest_aligned_T ? 6'h20 : {1'h0, _count_valids_largest_aligned_T_10}; // @[ZstdCompressorMemWriter.scala:205:{41,54}, :206:42] wire _count_valids_largest_aligned_log2_T_7 = _count_valids_largest_aligned_log2_T_4; // @[ZstdCompressorMemWriter.scala:217:{54,67}] wire [1:0] _count_valids_largest_aligned_log2_T_8 = _count_valids_largest_aligned_log2_T_3 ? 2'h2 : {1'h0, _count_valids_largest_aligned_log2_T_7}; // @[ZstdCompressorMemWriter.scala:216:{52,65}, :217:54] wire [1:0] _count_valids_largest_aligned_log2_T_9 = _count_valids_largest_aligned_log2_T_2 ? 2'h3 : _count_valids_largest_aligned_log2_T_8; // @[ZstdCompressorMemWriter.scala:215:{50,63}, :216:52] wire [2:0] _count_valids_largest_aligned_log2_T_10 = _count_valids_largest_aligned_log2_T_1 ? 3'h4 : {1'h0, _count_valids_largest_aligned_log2_T_9}; // @[ZstdCompressorMemWriter.scala:214:{48,61}, :215:50] wire [2:0] count_valids_largest_aligned_log2 = _count_valids_largest_aligned_log2_T ? 3'h5 : _count_valids_largest_aligned_log2_T_10; // @[ZstdCompressorMemWriter.scala:213:{46,59}, :214:48] wire _bytes_to_write_T = ptr_align_max_bytes_writeable < count_valids_largest_aligned; // @[ZstdCompressorMemWriter.scala:191:42, :205:41, :225:35] wire _bytes_to_write_T_1 = ptr_align_max_bytes_writeable < throttle_end_writeable; // @[ZstdCompressorMemWriter.scala:174:35, :191:42, :226:39] wire [5:0] _bytes_to_write_T_2 = _bytes_to_write_T_1 ? ptr_align_max_bytes_writeable : throttle_end_writeable; // @[ZstdCompressorMemWriter.scala:174:35, :191:42, :226:{8,39}] wire _bytes_to_write_T_3 = count_valids_largest_aligned < throttle_end_writeable; // @[ZstdCompressorMemWriter.scala:174:35, :205:41, :229:38] wire [5:0] _bytes_to_write_T_4 = _bytes_to_write_T_3 ? count_valids_largest_aligned : throttle_end_writeable; // @[ZstdCompressorMemWriter.scala:174:35, :205:41, :229:{8,38}] wire [5:0] bytes_to_write = _bytes_to_write_T ? _bytes_to_write_T_2 : _bytes_to_write_T_4; // @[ZstdCompressorMemWriter.scala:224:27, :225:35, :226:8, :229:8] wire [15:0] remapped_write_data_lo_lo_lo_lo = {remapVecData_1, remapVecData_0}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_lo_lo_lo_hi = {remapVecData_3, remapVecData_2}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_lo_lo_lo = {remapped_write_data_lo_lo_lo_hi, remapped_write_data_lo_lo_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [15:0] remapped_write_data_lo_lo_hi_lo = {remapVecData_5, remapVecData_4}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_lo_lo_hi_hi = {remapVecData_7, remapVecData_6}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_lo_lo_hi = {remapped_write_data_lo_lo_hi_hi, remapped_write_data_lo_lo_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [63:0] remapped_write_data_lo_lo = {remapped_write_data_lo_lo_hi, remapped_write_data_lo_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [15:0] remapped_write_data_lo_hi_lo_lo = {remapVecData_9, remapVecData_8}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_lo_hi_lo_hi = {remapVecData_11, remapVecData_10}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_lo_hi_lo = {remapped_write_data_lo_hi_lo_hi, remapped_write_data_lo_hi_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [15:0] remapped_write_data_lo_hi_hi_lo = {remapVecData_13, remapVecData_12}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_lo_hi_hi_hi = {remapVecData_15, remapVecData_14}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_lo_hi_hi = {remapped_write_data_lo_hi_hi_hi, remapped_write_data_lo_hi_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [63:0] remapped_write_data_lo_hi = {remapped_write_data_lo_hi_hi, remapped_write_data_lo_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [127:0] remapped_write_data_lo = {remapped_write_data_lo_hi, remapped_write_data_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [15:0] remapped_write_data_hi_lo_lo_lo = {remapVecData_17, remapVecData_16}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_hi_lo_lo_hi = {remapVecData_19, remapVecData_18}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_hi_lo_lo = {remapped_write_data_hi_lo_lo_hi, remapped_write_data_hi_lo_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [15:0] remapped_write_data_hi_lo_hi_lo = {remapVecData_21, remapVecData_20}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_hi_lo_hi_hi = {remapVecData_23, remapVecData_22}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_hi_lo_hi = {remapped_write_data_hi_lo_hi_hi, remapped_write_data_hi_lo_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [63:0] remapped_write_data_hi_lo = {remapped_write_data_hi_lo_hi, remapped_write_data_hi_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [15:0] remapped_write_data_hi_hi_lo_lo = {remapVecData_25, remapVecData_24}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_hi_hi_lo_hi = {remapVecData_27, remapVecData_26}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_hi_hi_lo = {remapped_write_data_hi_hi_lo_hi, remapped_write_data_hi_hi_lo_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [15:0] remapped_write_data_hi_hi_hi_lo = {remapVecData_29, remapVecData_28}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [15:0] remapped_write_data_hi_hi_hi_hi = {remapVecData_31, remapVecData_30}; // @[ZstdCompressorMemWriter.scala:141:26, :233:32] wire [31:0] remapped_write_data_hi_hi_hi = {remapped_write_data_hi_hi_hi_hi, remapped_write_data_hi_hi_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [63:0] remapped_write_data_hi_hi = {remapped_write_data_hi_hi_hi, remapped_write_data_hi_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [127:0] remapped_write_data_hi = {remapped_write_data_hi_hi, remapped_write_data_hi_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire [255:0] remapped_write_data = {remapped_write_data_hi, remapped_write_data_lo}; // @[ZstdCompressorMemWriter.scala:233:32] wire enough_data = \|bytes_to_write; // @[ZstdCompressorMemWriter.scala:224:27, :235:36] wire _bytes_to_write_log2_T = ptr_align_max_bytes_writeable_log2 < count_valids_largest_aligned_log2; // @[ZstdCompressorMemWriter.scala:198:47, :213:46, :238:40] wire _bytes_to_write_log2_T_1 = ptr_align_max_bytes_writeable_log2 < throttle_end_writeable_log2; // @[ZstdCompressorMemWriter.scala:182:40, :198:47, :239:44] wire [2:0] _bytes_to_write_log2_T_2 = _bytes_to_write_log2_T_1 ? ptr_align_max_bytes_writeable_log2 : throttle_end_writeable_log2; // @[ZstdCompressorMemWriter.scala:182:40, :198:47, :239:{8,44}] wire _bytes_to_write_log2_T_3 = count_valids_largest_aligned_log2 < throttle_end_writeable_log2; // @[ZstdCompressorMemWriter.scala:182:40, :213:46, :242:43] wire [2:0] _bytes_to_write_log2_T_4 = _bytes_to_write_log2_T_3 ? count_valids_largest_aligned_log2 : throttle_end_writeable_log2; // @[ZstdCompressorMemWriter.scala:182:40, :213:46, :242:{8,43}] wire [2:0] bytes_to_write_log2 = _bytes_to_write_log2_T ? _bytes_to_write_log2_T_2 : _bytes_to_write_log2_T_4; // @[ZstdCompressorMemWriter.scala:237:32, :238:40, :239:8, :242:8] wire _write_ptr_override_T = _buf_lens_Q_io_deq_bits == backend_bytes_written; // @[ZstdCompressorMemWriter.scala:52:26, :167:38, :247:79] wire write_ptr_override = _buf_lens_Q_io_deq_valid & _write_ptr_override_T; // @[ZstdCompressorMemWriter.scala:52:26, :247:{52,79}] wire _remapVecReadys_0_T = \|bytes_to_write; // @[ZstdCompressorMemWriter.scala:224:27, :235:36, :264:43] wire _T_5363 = io_l2io_req_ready_0 & enough_data; // @[Misc.scala:29:18] wire _remapVecReadys_0_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_0_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_1_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_1_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_2_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_2_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_3_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_3_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_4_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_4_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_5_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_5_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_6_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_6_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_7_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_7_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_8_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_8_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_9_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_9_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_10_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_10_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_11_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_11_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_12_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_12_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_13_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_13_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_14_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_14_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_15_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_15_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_16_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_16_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_17_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_17_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_18_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_18_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_19_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_19_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_20_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_20_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_21_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_21_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_22_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_22_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_23_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_23_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_24_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_24_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_25_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_25_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_26_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_26_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_27_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_27_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_28_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_28_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_29_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_29_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_30_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_30_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_31_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_31_T_1 = _T_5363; // @[Misc.scala:29:18] wire _remapVecReadys_0_T_2 = _remapVecReadys_0_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_0_T_3 = _remapVecReadys_0_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_0_T_4 = _remapVecReadys_0_T & _remapVecReadys_0_T_3; // @[Misc.scala:29:18] assign remapVecReadys_0 = _remapVecReadys_0_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_1_T = \|(bytes_to_write[5:1]); // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_1_T_2 = _remapVecReadys_1_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_1_T_3 = _remapVecReadys_1_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_1_T_4 = _remapVecReadys_1_T & _remapVecReadys_1_T_3; // @[Misc.scala:29:18] assign remapVecReadys_1 = _remapVecReadys_1_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_2_T = bytes_to_write > 6'h2; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_2_T_2 = _remapVecReadys_2_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_2_T_3 = _remapVecReadys_2_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_2_T_4 = _remapVecReadys_2_T & _remapVecReadys_2_T_3; // @[Misc.scala:29:18] assign remapVecReadys_2 = _remapVecReadys_2_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_3_T = \|(bytes_to_write[5:2]); // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_3_T_2 = _remapVecReadys_3_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_3_T_3 = _remapVecReadys_3_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_3_T_4 = _remapVecReadys_3_T & _remapVecReadys_3_T_3; // @[Misc.scala:29:18] assign remapVecReadys_3 = _remapVecReadys_3_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_4_T = bytes_to_write > 6'h4; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_4_T_2 = _remapVecReadys_4_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_4_T_3 = _remapVecReadys_4_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_4_T_4 = _remapVecReadys_4_T & _remapVecReadys_4_T_3; // @[Misc.scala:29:18] assign remapVecReadys_4 = _remapVecReadys_4_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_5_T = bytes_to_write > 6'h5; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_5_T_2 = _remapVecReadys_5_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_5_T_3 = _remapVecReadys_5_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_5_T_4 = _remapVecReadys_5_T & _remapVecReadys_5_T_3; // @[Misc.scala:29:18] assign remapVecReadys_5 = _remapVecReadys_5_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_6_T = bytes_to_write > 6'h6; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_6_T_2 = _remapVecReadys_6_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_6_T_3 = _remapVecReadys_6_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_6_T_4 = _remapVecReadys_6_T & _remapVecReadys_6_T_3; // @[Misc.scala:29:18] assign remapVecReadys_6 = _remapVecReadys_6_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_7_T = \|(bytes_to_write[5:3]); // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_7_T_2 = _remapVecReadys_7_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_7_T_3 = _remapVecReadys_7_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_7_T_4 = _remapVecReadys_7_T & _remapVecReadys_7_T_3; // @[Misc.scala:29:18] assign remapVecReadys_7 = _remapVecReadys_7_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_8_T = bytes_to_write > 6'h8; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_8_T_2 = _remapVecReadys_8_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_8_T_3 = _remapVecReadys_8_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_8_T_4 = _remapVecReadys_8_T & _remapVecReadys_8_T_3; // @[Misc.scala:29:18] assign remapVecReadys_8 = _remapVecReadys_8_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_9_T = bytes_to_write > 6'h9; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_9_T_2 = _remapVecReadys_9_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_9_T_3 = _remapVecReadys_9_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_9_T_4 = _remapVecReadys_9_T & _remapVecReadys_9_T_3; // @[Misc.scala:29:18] assign remapVecReadys_9 = _remapVecReadys_9_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_10_T = bytes_to_write > 6'hA; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_10_T_2 = _remapVecReadys_10_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_10_T_3 = _remapVecReadys_10_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_10_T_4 = _remapVecReadys_10_T & _remapVecReadys_10_T_3; // @[Misc.scala:29:18] assign remapVecReadys_10 = _remapVecReadys_10_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_11_T = bytes_to_write > 6'hB; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_11_T_2 = _remapVecReadys_11_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_11_T_3 = _remapVecReadys_11_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_11_T_4 = _remapVecReadys_11_T & _remapVecReadys_11_T_3; // @[Misc.scala:29:18] assign remapVecReadys_11 = _remapVecReadys_11_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_12_T = bytes_to_write > 6'hC; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_12_T_2 = _remapVecReadys_12_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_12_T_3 = _remapVecReadys_12_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_12_T_4 = _remapVecReadys_12_T & _remapVecReadys_12_T_3; // @[Misc.scala:29:18] assign remapVecReadys_12 = _remapVecReadys_12_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_13_T = bytes_to_write > 6'hD; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_13_T_2 = _remapVecReadys_13_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_13_T_3 = _remapVecReadys_13_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_13_T_4 = _remapVecReadys_13_T & _remapVecReadys_13_T_3; // @[Misc.scala:29:18] assign remapVecReadys_13 = _remapVecReadys_13_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_14_T = bytes_to_write > 6'hE; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_14_T_2 = _remapVecReadys_14_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_14_T_3 = _remapVecReadys_14_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_14_T_4 = _remapVecReadys_14_T & _remapVecReadys_14_T_3; // @[Misc.scala:29:18] assign remapVecReadys_14 = _remapVecReadys_14_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_15_T = \|(bytes_to_write[5:4]); // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_15_T_2 = _remapVecReadys_15_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_15_T_3 = _remapVecReadys_15_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_15_T_4 = _remapVecReadys_15_T & _remapVecReadys_15_T_3; // @[Misc.scala:29:18] assign remapVecReadys_15 = _remapVecReadys_15_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_16_T = bytes_to_write > 6'h10; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_16_T_2 = _remapVecReadys_16_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_16_T_3 = _remapVecReadys_16_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_16_T_4 = _remapVecReadys_16_T & _remapVecReadys_16_T_3; // @[Misc.scala:29:18] assign remapVecReadys_16 = _remapVecReadys_16_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_17_T = bytes_to_write > 6'h11; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_17_T_2 = _remapVecReadys_17_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_17_T_3 = _remapVecReadys_17_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_17_T_4 = _remapVecReadys_17_T & _remapVecReadys_17_T_3; // @[Misc.scala:29:18] assign remapVecReadys_17 = _remapVecReadys_17_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_18_T = bytes_to_write > 6'h12; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_18_T_2 = _remapVecReadys_18_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_18_T_3 = _remapVecReadys_18_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_18_T_4 = _remapVecReadys_18_T & _remapVecReadys_18_T_3; // @[Misc.scala:29:18] assign remapVecReadys_18 = _remapVecReadys_18_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_19_T = bytes_to_write > 6'h13; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_19_T_2 = _remapVecReadys_19_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_19_T_3 = _remapVecReadys_19_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_19_T_4 = _remapVecReadys_19_T & _remapVecReadys_19_T_3; // @[Misc.scala:29:18] assign remapVecReadys_19 = _remapVecReadys_19_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_20_T = bytes_to_write > 6'h14; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_20_T_2 = _remapVecReadys_20_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_20_T_3 = _remapVecReadys_20_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_20_T_4 = _remapVecReadys_20_T & _remapVecReadys_20_T_3; // @[Misc.scala:29:18] assign remapVecReadys_20 = _remapVecReadys_20_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_21_T = bytes_to_write > 6'h15; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_21_T_2 = _remapVecReadys_21_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_21_T_3 = _remapVecReadys_21_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_21_T_4 = _remapVecReadys_21_T & _remapVecReadys_21_T_3; // @[Misc.scala:29:18] assign remapVecReadys_21 = _remapVecReadys_21_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_22_T = bytes_to_write > 6'h16; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_22_T_2 = _remapVecReadys_22_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_22_T_3 = _remapVecReadys_22_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_22_T_4 = _remapVecReadys_22_T & _remapVecReadys_22_T_3; // @[Misc.scala:29:18] assign remapVecReadys_22 = _remapVecReadys_22_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_23_T = bytes_to_write > 6'h17; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_23_T_2 = _remapVecReadys_23_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_23_T_3 = _remapVecReadys_23_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_23_T_4 = _remapVecReadys_23_T & _remapVecReadys_23_T_3; // @[Misc.scala:29:18] assign remapVecReadys_23 = _remapVecReadys_23_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_24_T = bytes_to_write > 6'h18; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_24_T_2 = _remapVecReadys_24_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_24_T_3 = _remapVecReadys_24_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_24_T_4 = _remapVecReadys_24_T & _remapVecReadys_24_T_3; // @[Misc.scala:29:18] assign remapVecReadys_24 = _remapVecReadys_24_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_25_T = bytes_to_write > 6'h19; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_25_T_2 = _remapVecReadys_25_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_25_T_3 = _remapVecReadys_25_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_25_T_4 = _remapVecReadys_25_T & _remapVecReadys_25_T_3; // @[Misc.scala:29:18] assign remapVecReadys_25 = _remapVecReadys_25_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_26_T = bytes_to_write > 6'h1A; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_26_T_2 = _remapVecReadys_26_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_26_T_3 = _remapVecReadys_26_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_26_T_4 = _remapVecReadys_26_T & _remapVecReadys_26_T_3; // @[Misc.scala:29:18] assign remapVecReadys_26 = _remapVecReadys_26_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_27_T = bytes_to_write > 6'h1B; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_27_T_2 = _remapVecReadys_27_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_27_T_3 = _remapVecReadys_27_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_27_T_4 = _remapVecReadys_27_T & _remapVecReadys_27_T_3; // @[Misc.scala:29:18] assign remapVecReadys_27 = _remapVecReadys_27_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_28_T = bytes_to_write > 6'h1C; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_28_T_2 = _remapVecReadys_28_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_28_T_3 = _remapVecReadys_28_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_28_T_4 = _remapVecReadys_28_T & _remapVecReadys_28_T_3; // @[Misc.scala:29:18] assign remapVecReadys_28 = _remapVecReadys_28_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_29_T = bytes_to_write > 6'h1D; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_29_T_2 = _remapVecReadys_29_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_29_T_3 = _remapVecReadys_29_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_29_T_4 = _remapVecReadys_29_T & _remapVecReadys_29_T_3; // @[Misc.scala:29:18] assign remapVecReadys_29 = _remapVecReadys_29_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_30_T = bytes_to_write > 6'h1E; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_30_T_2 = _remapVecReadys_30_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_30_T_3 = _remapVecReadys_30_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_30_T_4 = _remapVecReadys_30_T & _remapVecReadys_30_T_3; // @[Misc.scala:29:18] assign remapVecReadys_30 = _remapVecReadys_30_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _remapVecReadys_31_T = bytes_to_write[5]; // @[ZstdCompressorMemWriter.scala:224:27, :264:43] wire _remapVecReadys_31_T_2 = _remapVecReadys_31_T_1 & ~write_ptr_override; // @[Misc.scala:29:18] wire _remapVecReadys_31_T_3 = _remapVecReadys_31_T_2 & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] assign _remapVecReadys_31_T_4 = _remapVecReadys_31_T & _remapVecReadys_31_T_3; // @[Misc.scala:29:18] assign remapVecReadys_31 = _remapVecReadys_31_T_4; // @[ZstdCompressorMemWriter.scala:143:28, :264:61] wire _T_5365 = _T_5363 & ~write_ptr_override & _dest_info_Q_io_deq_valid; // @[Misc.scala:29:18] wire [6:0] _read_start_index_T = _remapindex_T + {1'h0, bytes_to_write}; // @[ZstdCompressorMemWriter.scala:153:33, :224:27, :268:43] wire [6:0] _GEN_123 = _read_start_index_T % 7'h20; // @[ZstdCompressorMemWriter.scala:268:{43,62}] wire [5:0] _read_start_index_T_1 = _GEN_123[5:0]; // @[ZstdCompressorMemWriter.scala:268:62] wire [64:0] _backend_bytes_written_T = _GEN_122 + {59'h0, bytes_to_write}; // @[ZstdCompressorMemWriter.scala:168:60, :224:27, :269:52] wire [63:0] _backend_bytes_written_T_1 = _backend_bytes_written_T[63:0]; // @[ZstdCompressorMemWriter.scala:269:52] reg [63:0] loginfo_cycles_35; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_70 = {1'h0, loginfo_cycles_35} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_71 = _loginfo_cycles_T_70[63:0]; // @[Util.scala:19:38] wire _io_l2io_req_valid_T = enough_data & ~write_ptr_override; // @[Misc.scala:26:53] assign _io_l2io_req_valid_T_1 = _io_l2io_req_valid_T & _dest_info_Q_io_deq_valid; // @[Misc.scala:26:53] assign io_l2io_req_valid_0 = _io_l2io_req_valid_T_1; // @[Misc.scala:26:53] assign _io_l2io_req_bits_size_T = write_ptr_override ? 3'h2 : bytes_to_write_log2; // @[ZstdCompressorMemWriter.scala:237:32, :247:52, :282:31] assign io_l2io_req_bits_size_0 = _io_l2io_req_bits_size_T; // @[ZstdCompressorMemWriter.scala:23:7, :282:31] assign _io_l2io_req_bits_addr_T = write_ptr_override ? _dest_info_Q_io_deq_bits_cmpflag : backend_next_write_addr; // @[ZstdCompressorMemWriter.scala:39:27, :168:60, :247:52, :283:31] assign io_l2io_req_bits_addr_0 = _io_l2io_req_bits_addr_T; // @[ZstdCompressorMemWriter.scala:23:7, :283:31] assign _io_l2io_req_bits_data_T = write_ptr_override ? {192'h0, _dest_info_Q_io_deq_bits_cmpval} : remapped_write_data; // @[ZstdCompressorMemWriter.scala:39:27, :89:{76,90}, :233:32, :247:52, :284:31] assign io_l2io_req_bits_data_0 = _io_l2io_req_bits_data_T; // @[ZstdCompressorMemWriter.scala:23:7, :284:31] wire _buf_lens_Q_io_deq_ready_T = io_l2io_req_ready_0 & _write_ptr_override_T; // @[Misc.scala:26:53] wire _buf_lens_Q_io_deq_ready_T_1 = _buf_lens_Q_io_deq_ready_T & _dest_info_Q_io_deq_valid; // @[Misc.scala:26:53] wire _dest_info_Q_io_deq_ready_T = io_l2io_req_ready_0 & _buf_lens_Q_io_deq_valid; // @[Misc.scala:26:53] assign _dest_info_Q_io_deq_ready_T_1 = _dest_info_Q_io_deq_ready_T & _write_ptr_override_T; // @[Misc.scala:26:53] reg [63:0] bufs_completed; // @[ZstdCompressorMemWriter.scala:290:31] assign io_bufs_completed_0 = bufs_completed; // @[ZstdCompressorMemWriter.scala:23:7, :290:31] wire _T_5372 = _dest_info_Q_io_deq_ready_T & _write_ptr_override_T & _dest_info_Q_io_deq_valid; // @[Misc.scala:26:53, :29:18] wire [64:0] _bufs_completed_T = {1'h0, bufs_completed} + 65'h1; // @[ZstdCompressorMemWriter.scala:290:31, :298:38] wire [63:0] _bufs_completed_T_1 = _bufs_completed_T[63:0]; // @[ZstdCompressorMemWriter.scala:298:38] reg [63:0] loginfo_cycles_36; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_72 = {1'h0, loginfo_cycles_36} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_73 = _loginfo_cycles_T_72[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_37; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_74 = {1'h0, loginfo_cycles_37} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_75 = _loginfo_cycles_T_74[63:0]; // @[Util.scala:19:38]
Generate the Verilog code corresponding to the following Chisel files. File FPU.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util._ import chisel3.{DontCare, WireInit, withClock, withReset} import chisel3.experimental.SourceInfo import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property case class FPUParams( minFLen: Int = 32, fLen: Int = 64, divSqrt: Boolean = true, sfmaLatency: Int = 3, dfmaLatency: Int = 4, fpmuLatency: Int = 2, ifpuLatency: Int = 2 ) object FPConstants { val RM_SZ = 3 val FLAGS_SZ = 5 } trait HasFPUCtrlSigs { val ldst = Bool() val wen = Bool() val ren1 = Bool() val ren2 = Bool() val ren3 = Bool() val swap12 = Bool() val swap23 = Bool() val typeTagIn = UInt(2.W) val typeTagOut = UInt(2.W) val fromint = Bool() val toint = Bool() val fastpipe = Bool() val fma = Bool() val div = Bool() val sqrt = Bool() val wflags = Bool() val vec = Bool() } class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new Bundle { val inst = Input(Bits(32.W)) val sigs = Output(new FPUCtrlSigs()) }) private val X2 = BitPat.dontCare(2) val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N) val h: Array[(BitPat, List[BitPat])] = Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N), FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N), FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N), FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N), FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N), FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N), FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N), FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N), FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N)) val f: Array[(BitPat, List[BitPat])] = Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N), FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N), FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N), FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N), FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N), FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N), FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N)) val d: Array[(BitPat, List[BitPat])] = Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N), FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N), FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N), FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N), FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N), FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N), FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N), FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N), FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N)) val fcvt_hd: Array[(BitPat, List[BitPat])] = Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N), FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N)) val vfmv_f_s: Array[(BitPat, List[BitPat])] = Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y)) val insns = ((minFLen, fLen) match { case (32, 32) => f case (16, 32) => h ++ f case (32, 64) => f ++ d case (16, 64) => h ++ f ++ d ++ fcvt_hd case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration") }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]()) val decoder = DecodeLogic(io.inst, default, insns) val s = io.sigs val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec) sigs zip decoder map {case(s,d) => s := d} } class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val time = Input(UInt(xLen.W)) val inst = Input(Bits(32.W)) val fromint_data = Input(Bits(xLen.W)) val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W)) val v_sew = Input(UInt(3.W)) val store_data = Output(Bits(fLen.W)) val toint_data = Output(Bits(xLen.W)) val ll_resp_val = Input(Bool()) val ll_resp_type = Input(Bits(3.W)) val ll_resp_tag = Input(UInt(5.W)) val ll_resp_data = Input(Bits(fLen.W)) val valid = Input(Bool()) val fcsr_rdy = Output(Bool()) val nack_mem = Output(Bool()) val illegal_rm = Output(Bool()) val killx = Input(Bool()) val killm = Input(Bool()) val dec = Output(new FPUCtrlSigs()) val sboard_set = Output(Bool()) val sboard_clr = Output(Bool()) val sboard_clra = Output(UInt(5.W)) val keep_clock_enabled = Input(Bool()) } class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) { val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs val cp_resp = Decoupled(new FPResult()) } class FPResult(implicit p: Parameters) extends CoreBundle()(p) { val data = Bits((fLen+1).W) val exc = Bits(FPConstants.FLAGS_SZ.W) } class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val typ = Bits(2.W) val in1 = Bits(xLen.W) } class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val fmaCmd = Bits(2.W) val typ = Bits(2.W) val fmt = Bits(2.W) val in1 = Bits((fLen+1).W) val in2 = Bits((fLen+1).W) val in3 = Bits((fLen+1).W) } case class FType(exp: Int, sig: Int) { def ieeeWidth = exp + sig def recodedWidth = ieeeWidth + 1 def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W) def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W) def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2) def classify(x: UInt) = { val sign = x(sig + exp) val code = x(exp + sig - 1, exp + sig - 3) val codeHi = code(2, 1) val isSpecial = codeHi === 3.U val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U val isSubnormal = code === 1.U \|\| codeHi === 1.U && isHighSubnormalIn val isNormal = codeHi === 1.U && !isHighSubnormalIn \|\| codeHi === 2.U val isZero = code === 0.U val isInf = isSpecial && !code(0) val isNaN = code.andR val isSNaN = isNaN && !x(sig-2) val isQNaN = isNaN && x(sig-2) Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign, isSubnormal && !sign, isZero && !sign, isZero && sign, isSubnormal && sign, isNormal && sign, isInf && sign) } // convert between formats, ignoring rounding, range, NaN def unsafeConvert(x: UInt, to: FType) = if (this == to) x else { val sign = x(sig + exp) val fractIn = x(sig - 2, 0) val expIn = x(sig + exp - 1, sig - 1) val fractOut = fractIn << to.sig >> sig val expOut = { val expCode = expIn(exp, exp - 2) val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U Mux(expCode === 0.U \|\| expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0)) } Cat(sign, expOut, fractOut) } private def ieeeBundle = { val expWidth = exp class IEEEBundle extends Bundle { val sign = Bool() val exp = UInt(expWidth.W) val sig = UInt((ieeeWidth-expWidth-1).W) } new IEEEBundle } def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle) def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x) def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x) } object FType { val H = new FType(5, 11) val S = new FType(8, 24) val D = new FType(11, 53) val all = List(H, S, D) } trait HasFPUParameters { require(fLen == 0 \|\| FType.all.exists(_.ieeeWidth == fLen)) val minFLen: Int val fLen: Int def xLen: Int val minXLen = 32 val nIntTypes = log2Ceil(xLen/minXLen) + 1 def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen) def minType = floatTypes.head def maxType = floatTypes.last def prevType(t: FType) = floatTypes(typeTag(t) - 1) def maxExpWidth = maxType.exp def maxSigWidth = maxType.sig def typeTag(t: FType) = floatTypes.indexOf(t) def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U // typeTag def H = typeTagGroup(FType.H) def S = typeTagGroup(FType.S) def D = typeTagGroup(FType.D) def I = typeTag(maxType).U private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = { require(xt.ieeeWidth == 2 * yt.ieeeWidth) val swizzledNaN = Cat( x(xt.sig + xt.exp, xt.sig + xt.exp - 3), x(xt.sig - 2, yt.recodedWidth - 1).andR, x(xt.sig + xt.exp - 5, xt.sig), y(yt.recodedWidth - 2), x(xt.sig - 2, yt.recodedWidth - 1), y(yt.recodedWidth - 1), y(yt.recodedWidth - 3, 0)) Mux(xt.isNaN(x), swizzledNaN, x) } // implement NaN unboxing for FU inputs def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = { val outType = exactType.getOrElse(maxType) def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = { val prev = if (t == minType) { Seq() } else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prev = helper(unswizzled, prevT) val isbox = isBox(x, t) prev.map(p => (isbox && p._1, p._2)) } prev :+ (true.B, t.unsafeConvert(x, outType)) } val (oks, floats) = helper(x, maxType).unzip if (exactType.isEmpty \|\| floatTypes.size == 1) { Mux(oks(tag), floats(tag), maxType.qNaN) } else { val t = exactType.get floats(typeTag(t)) \| Mux(oks(typeTag(t)), 0.U, t.qNaN) } } // make sure that the redundant bits in the NaN-boxed encoding are consistent def consistent(x: UInt): Bool = { def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prevOK = !isBox(x, t) \|\| helper(unswizzled, prevT) val curOK = !t.isNaN(x) \|\| x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR prevOK && curOK } helper(x, maxType) } // generate a NaN box from an FU result def box(x: UInt, t: FType): UInt = { if (t == maxType) { x } else { val nt = floatTypes(typeTag(t) + 1) val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t) bigger \| ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U } } // generate a NaN box from an FU result def box(x: UInt, tag: UInt): UInt = { val opts = floatTypes.map(t => box(x, t)) opts(tag) } // zap bits that hardfloat thinks are don't-cares, but we do care about def sanitizeNaN(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { x } else { val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) \| (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W) Mux(t.isNaN(x), maskedNaN, x) } } // implement NaN boxing and recoding for FL/fmv..x def recode(x: UInt, tag: UInt): UInt = { def helper(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { t.recode(x) } else { val prevT = prevType(t) box(t.recode(x), t, helper(x, prevT), prevT) } } // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U) helper(boxes(tag) \| x, maxType) } // implement NaN unboxing and un-recoding for FS/fmv.x. def ieee(x: UInt, t: FType = maxType): UInt = { if (typeTag(t) == 0) { t.ieee(x) } else { val unrecoded = t.ieee(x) val prevT = prevType(t) val prevRecoded = Cat( x(prevT.recodedWidth-2), x(t.sig-1), x(prevT.recodedWidth-3, 0)) val prevUnrecoded = ieee(prevRecoded, prevT) Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0))) } } } abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { class Output extends Bundle { val in = new FPInput val lt = Bool() val store = Bits(fLen.W) val toint = Bits(xLen.W) val exc = Bits(FPConstants.FLAGS_SZ.W) } val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new Output) }) val in = RegEnable(io.in.bits, io.in.valid) val valid = RegNext(io.in.valid) val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth)) dcmp.io.a := in.in1 dcmp.io.b := in.in2 dcmp.io.signaling := !in.rm(1) val tag = in.typeTagOut val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen)) else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) val toint = WireDefault(toint_ieee) val intType = WireDefault(in.fmt(0)) io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType) io.out.bits.exc := 0.U when (in.rm(0)) { val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag) toint := classify_out \| (toint_ieee >> minXLen << minXLen) intType := false.B } when (in.wflags) { // feq/flt/fle, fcvt toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR \| (toint_ieee >> minXLen << minXLen) io.out.bits.exc := dcmp.io.exceptionFlags intType := false.B when (!in.ren2) { // fcvt val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1) intType := cvtType val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen)) conv.io.in := in.in1 conv.io.roundingMode := in.rm conv.io.signedOut := ~in.typ(0) toint := conv.io.out io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0)) for (i <- 0 until nIntTypes-1) { val w = minXLen << i when (cvtType === i.U) { val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w)) narrow.io.in := in.in1 narrow.io.roundingMode := in.rm narrow.io.signedOut := ~in.typ(0) val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1) val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign)) val invalid = conv.io.intExceptionFlags(2) \|\| narrow.io.intExceptionFlags(1) when (invalid) { toint := Cat(conv.io.out >> w, excOut) } io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0)) } } } } io.out.valid := valid io.out.bits.lt := dcmp.io.lt \|\| (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S) io.out.bits.in := in } class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new IntToFPInput)) val out = Valid(new FPResult) }) val in = Pipe(io.in) val tag = in.bits.typeTagIn val mux = Wire(new FPResult) mux.exc := 0.U mux.data := recode(in.bits.in1, tag) val intValue = { val res = WireDefault(in.bits.in1.asSInt) for (i <- 0 until nIntTypes-1) { val smallInt = in.bits.in1((minXLen << i) - 1, 0) when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) { res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt) } } res.asUInt } when (in.bits.wflags) { // fcvt // could be improved for RVD/RVQ with a single variable-position rounding // unit, rather than N fixed-position ones val i2fResults = for (t <- floatTypes) yield { val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig)) i2f.io.signedIn := ~in.bits.typ(0) i2f.io.in := intValue i2f.io.roundingMode := in.bits.rm i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags) } val (data, exc) = i2fResults.unzip val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last mux.data := dataPadded(tag) mux.exc := exc(tag) } io.out <> Pipe(in.valid, mux, latency-1) } class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) val lt = Input(Bool()) // from FPToInt }) val in = Pipe(io.in) val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2)) val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0)) val fsgnjMux = Wire(new FPResult) fsgnjMux.exc := 0.U fsgnjMux.data := fsgnj when (in.bits.wflags) { // fmin/fmax val isnan1 = maxType.isNaN(in.bits.in1) val isnan2 = maxType.isNaN(in.bits.in2) val isInvalid = maxType.isSNaN(in.bits.in1) \|\| maxType.isSNaN(in.bits.in2) val isNaNOut = isnan1 && isnan2 val isLHS = isnan2 \|\| in.bits.rm(0) =/= io.lt && !isnan1 fsgnjMux.exc := isInvalid << 4 fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2)) } val inTag = in.bits.typeTagIn val outTag = in.bits.typeTagOut val mux = WireDefault(fsgnjMux) for (t <- floatTypes.init) { when (outTag === typeTag(t).U) { mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t)) } } when (in.bits.wflags && !in.bits.ren2) { // fcvt if (floatTypes.size > 1) { // widening conversions simply canonicalize NaN operands val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1) fsgnjMux.data := widened fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4 // narrowing conversions require rounding (for RVQ, this could be // optimized to use a single variable-position rounding unit, rather // than two fixed-position ones) for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B \|\| outTag < inTag)) { val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig)) narrower.io.in := in.bits.in1 narrower.io.roundingMode := in.bits.rm narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding val narrowed = sanitizeNaN(narrower.io.out, outType) mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed) mux.exc := narrower.io.exceptionFlags } } } io.out <> Pipe(in.valid, mux, latency-1) } class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module { override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}" require(latency<=2) val io = IO(new Bundle { val validin = Input(Bool()) val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) val validout = Output(Bool()) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC val valid_stage0 = Wire(Bool()) val roundingMode_stage0 = Wire(UInt(3.W)) val detectTininess_stage0 = Wire(UInt(1.W)) val postmul_regs = if(latency>0) 1 else 0 mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0)) val round_regs = if(latency==2) 1 else 0 roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits io.validout := Pipe(valid_stage0, false.B, round_regs).valid roundRawFNToRecFN.io.infiniteExc := false.B io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } class FPUFMAPipe(val latency: Int, val t: FType) (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}" require(latency>0) val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) }) val valid = RegNext(io.in.valid) val in = Reg(new FPInput) when (io.in.valid) { val one = 1.U << (t.sig + t.exp - 1) val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp)) val cmd_fma = io.in.bits.ren3 val cmd_addsub = io.in.bits.swap23 in := io.in.bits when (cmd_addsub) { in.in2 := one } when (!(cmd_fma \|\| cmd_addsub)) { in.in3 := zero } } val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig)) fma.io.validin := valid fma.io.op := in.fmaCmd fma.io.roundingMode := in.rm fma.io.detectTininess := hardfloat.consts.tininess_afterRounding fma.io.a := in.in1 fma.io.b := in.in2 fma.io.c := in.in3 val res = Wire(new FPResult) res.data := sanitizeNaN(fma.io.out, t) res.exc := fma.io.exceptionFlags io.out := Pipe(fma.io.validout, res, (latency-3) max 0) } class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new FPUIO) val (useClockGating, useDebugROB) = coreParams match { case r: RocketCoreParams => val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1 (r.clockGate, sz < 1) case _ => (false, false) } val clock_en_reg = Reg(Bool()) val clock_en = clock_en_reg \|\| io.cp_req.valid val gated_clock = if (!useClockGating) clock else ClockGate(clock, clock_en, "fpu_clock_gate") val fp_decoder = Module(new FPUDecoder) fp_decoder.io.inst := io.inst val id_ctrl = WireInit(fp_decoder.io.sigs) coreParams match { case r: RocketCoreParams => r.vector.map(v => { val v_decode = v.decoder(p) // Only need to get ren1 v_decode.io.inst := io.inst v_decode.io.vconfig := DontCare // core deals with this when (v_decode.io.legal && v_decode.io.read_frs1) { id_ctrl.ren1 := true.B id_ctrl.swap12 := false.B id_ctrl.toint := true.B id_ctrl.typeTagIn := I id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S) } when (v_decode.io.write_frd) { id_ctrl.wen := true.B } })} val ex_reg_valid = RegNext(io.valid, false.B) val ex_reg_inst = RegEnable(io.inst, io.valid) val ex_reg_ctrl = RegEnable(id_ctrl, io.valid) val ex_ra = List.fill(3)(Reg(UInt())) // load/vector response val load_wb = RegNext(io.ll_resp_val) val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val) val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val) val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val) class FPUImpl { // entering gated-clock domain val req_valid = ex_reg_valid \|\| io.cp_req.valid val ex_cp_valid = io.cp_req.fire val mem_cp_valid = RegNext(ex_cp_valid, false.B) val wb_cp_valid = RegNext(mem_cp_valid, false.B) val mem_reg_valid = RegInit(false.B) val killm = (io.killm \|\| io.nack_mem) && !mem_cp_valid // Kill X-stage instruction if M-stage is killed. This prevents it from // speculatively being sent to the div-sqrt unit, which can cause priority // inversion for two back-to-back divides, the first of which is killed. val killx = io.killx \|\| mem_reg_valid && killm mem_reg_valid := ex_reg_valid && !killx \|\| ex_cp_valid val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid) val wb_reg_valid = RegNext(mem_reg_valid && (!killm \|\| mem_cp_valid), false.B) val cp_ctrl = Wire(new FPUCtrlSigs) cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs) io.cp_resp.valid := false.B io.cp_resp.bits.data := 0.U io.cp_resp.bits.exc := DontCare val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl) val mem_ctrl = RegEnable(ex_ctrl, req_valid) val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid) // CoreMonitorBundle to monitor fp register file writes val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare)) frfWriteBundle.foreach { i => i.clock := clock i.reset := reset i.hartid := io.hartid i.timer := io.time(31,0) i.valid := false.B i.wrenx := false.B i.wrenf := false.B i.excpt := false.B } // regfile val regfile = Mem(32, Bits((fLen+1).W)) when (load_wb) { val wdata = recode(load_wb_data, load_wb_typeTag) regfile(load_wb_tag) := wdata assert(consistent(wdata)) if (enableCommitLog) printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata)) if (useDebugROB) DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata)) frfWriteBundle(0).wrdst := load_wb_tag frfWriteBundle(0).wrenf := true.B frfWriteBundle(0).wrdata := ieee(wdata) } val ex_rs = ex_ra.map(a => regfile(a)) when (io.valid) { when (id_ctrl.ren1) { when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) } when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) } } when (id_ctrl.ren2) { when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) } when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) } when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) } } when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) } } val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12)) def fuInput(minT: Option[FType]): FPInput = { val req = Wire(new FPInput) val tag = ex_ctrl.typeTagIn req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs) req.rm := ex_rm req.in1 := unbox(ex_rs(0), tag, minT) req.in2 := unbox(ex_rs(1), tag, minT) req.in3 := unbox(ex_rs(2), tag, minT) req.typ := ex_reg_inst(21,20) req.fmt := ex_reg_inst(26,25) req.fmaCmd := ex_reg_inst(3,2) \| (!ex_ctrl.ren3 && ex_reg_inst(27)) when (ex_cp_valid) { req := io.cp_req.bits when (io.cp_req.bits.swap12) { req.in1 := io.cp_req.bits.in2 req.in2 := io.cp_req.bits.in1 } when (io.cp_req.bits.swap23) { req.in2 := io.cp_req.bits.in3 req.in3 := io.cp_req.bits.in2 } } req } val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S)) sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S sfma.io.in.bits := fuInput(Some(sfma.t)) val fpiu = Module(new FPToInt) fpiu.io.in.valid := req_valid && (ex_ctrl.toint \|\| ex_ctrl.div \|\| ex_ctrl.sqrt \|\| (ex_ctrl.fastpipe && ex_ctrl.wflags)) fpiu.io.in.bits := fuInput(None) io.store_data := fpiu.io.out.bits.store io.toint_data := fpiu.io.out.bits.toint when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){ io.cp_resp.bits.data := fpiu.io.out.bits.toint io.cp_resp.valid := true.B } val ifpu = Module(new IntToFP(cfg.ifpuLatency)) ifpu.io.in.valid := req_valid && ex_ctrl.fromint ifpu.io.in.bits := fpiu.io.in.bits ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) val fpmu = Module(new FPToFP(cfg.fpmuLatency)) fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe fpmu.io.in.bits := fpiu.io.in.bits fpmu.io.lt := fpiu.io.out.bits.lt val divSqrt_wen = WireDefault(false.B) val divSqrt_inFlight = WireDefault(false.B) val divSqrt_waddr = Reg(UInt(5.W)) val divSqrt_cp = Reg(Bool()) val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W)) val divSqrt_wdata = Wire(UInt((fLen+1).W)) val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W)) divSqrt_typeTag := DontCare divSqrt_wdata := DontCare divSqrt_flags := DontCare // writeback arbitration case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult) val pipes = List( Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits), Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits), Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++ (fLen > 32).option({ val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D)) dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D dfma.io.in.bits := fuInput(Some(dfma.t)) Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits) }) ++ (minFLen == 16).option({ val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H)) hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H hfma.io.in.bits := fuInput(Some(hfma.t)) Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits) }) def latencyMask(c: FPUCtrlSigs, offset: Int) = { require(pipes.forall(_.lat >= offset)) pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_\|_) } def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_\|_) val maxLatency = pipes.map(_.lat).max val memLatencyMask = latencyMask(mem_ctrl, 2) class WBInfo extends Bundle { val rd = UInt(5.W) val typeTag = UInt(log2Up(floatTypes.size).W) val cp = Bool() val pipeid = UInt(log2Ceil(pipes.size).W) } val wen = RegInit(0.U((maxLatency-1).W)) val wbInfo = Reg(Vec(maxLatency-1, new WBInfo)) val mem_wen = mem_reg_valid && (mem_ctrl.fma \|\| mem_ctrl.fastpipe \|\| mem_ctrl.fromint) val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR \|\| (wen & latencyMask(ex_ctrl, 0)).orR, req_valid) ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback") for (i <- 0 until maxLatency-2) { when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) } } wen := wen >> 1 when (mem_wen) { when (!killm) { wen := wen >> 1 \| memLatencyMask } for (i <- 0 until maxLatency-1) { when (!write_port_busy && memLatencyMask(i)) { wbInfo(i).cp := mem_cp_valid wbInfo(i).typeTag := mem_ctrl.typeTagOut wbInfo(i).pipeid := pipeid(mem_ctrl) wbInfo(i).rd := mem_reg_inst(11,7) } } } val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd) val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp) val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag) val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag) val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid) when ((!wbInfo(0).cp && wen(0)) \|\| divSqrt_wen) { assert(consistent(wdata)) regfile(waddr) := wdata if (enableCommitLog) { printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata)) } frfWriteBundle(1).wrdst := waddr frfWriteBundle(1).wrenf := true.B frfWriteBundle(1).wrdata := ieee(wdata) } if (useDebugROB) { DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) \|\| divSqrt_wen, waddr + 32.U, ieee(wdata)) } when (wb_cp && (wen(0) \|\| divSqrt_wen)) { io.cp_resp.bits.data := wdata io.cp_resp.valid := true.B } assert(!io.cp_req.valid \|\| pipes.forall(_.lat == pipes.head.lat).B, s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}") // Avoid structural hazards and nacking of external requests // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight val wb_toint_valid = wb_reg_valid && wb_ctrl.toint val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint) io.fcsr_flags.valid := wb_toint_valid \|\| divSqrt_wen \|\| wen(0) io.fcsr_flags.bits := Mux(wb_toint_valid, wb_toint_exc, 0.U) \| Mux(divSqrt_wen, divSqrt_flags, 0.U) \| Mux(wen(0), wexc, 0.U) val divSqrt_write_port_busy = (mem_ctrl.div \|\| mem_ctrl.sqrt) && wen.orR io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags \|\| mem_reg_valid && mem_ctrl.wflags \|\| wb_reg_valid && wb_ctrl.toint \|\| wen.orR \|\| divSqrt_inFlight) io.nack_mem := (write_port_busy \|\| divSqrt_write_port_busy \|\| divSqrt_inFlight) && !mem_cp_valid io.dec <> id_ctrl def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_\|\|_) io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) \|\| mem_ctrl.div \|\| mem_ctrl.sqrt \|\| mem_ctrl.vec) io.sboard_clr := !wb_cp_valid && (divSqrt_wen \|\| (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U))) io.sboard_clra := waddr ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle") // we don't currently support round-max-magnitude (rm=4) io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) \|\| io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U if (cfg.divSqrt) { val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div \|\| mem_ctrl.sqrt) && !divSqrt_inFlight val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B) when (divSqrt_inValid) { divSqrt_waddr := mem_reg_inst(11,7) divSqrt_cp := mem_cp_valid } ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider") ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div \|\| mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard") ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback") for (t <- floatTypes) { val tag = mem_ctrl.typeTagOut val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) } divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U divSqrt.io.sqrtOp := mem_ctrl.sqrt divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t) divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t) divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight when (divSqrt.io.outValid_div \|\| divSqrt.io.outValid_sqrt) { divSqrt_wen := !divSqrt_killed divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t) divSqrt_flags := divSqrt.io.exceptionFlags divSqrt_typeTag := typeTag(t).U } } when (divSqrt_killed) { divSqrt_inFlight := false.B } } else { when (id_ctrl.div \|\| id_ctrl.sqrt) { io.illegal_rm := true.B } } // gate the clock clock_en_reg := !useClockGating.B \|\| io.keep_clock_enabled \|\| // chicken bit io.valid \|\| // ID stage req_valid \|\| // EX stage mem_reg_valid \|\| mem_cp_valid \|\| // MEM stage wb_reg_valid \|\| wb_cp_valid \|\| // WB stage wen.orR \|\| divSqrt_inFlight \|\| // post-WB stage io.ll_resp_val // load writeback } // leaving gated-clock domain val fpuImpl = withClock (gated_clock) { new FPUImpl } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"FPU_$label", "Core;;" + desc) }	module FPToFP_2( // @[FPU.scala:573:7] input clock, // @[FPU.scala:573:7] input reset, // @[FPU.scala:573:7] input io_in_valid, // @[FPU.scala:574:14] input io_in_bits_ldst, // @[FPU.scala:574:14] input io_in_bits_wen, // @[FPU.scala:574:14] input io_in_bits_ren1, // @[FPU.scala:574:14] input io_in_bits_ren2, // @[FPU.scala:574:14] input io_in_bits_ren3, // @[FPU.scala:574:14] input io_in_bits_swap12, // @[FPU.scala:574:14] input io_in_bits_swap23, // @[FPU.scala:574:14] input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:574:14] input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:574:14] input io_in_bits_fromint, // @[FPU.scala:574:14] input io_in_bits_toint, // @[FPU.scala:574:14] input io_in_bits_fastpipe, // @[FPU.scala:574:14] input io_in_bits_fma, // @[FPU.scala:574:14] input io_in_bits_div, // @[FPU.scala:574:14] input io_in_bits_sqrt, // @[FPU.scala:574:14] input io_in_bits_wflags, // @[FPU.scala:574:14] input io_in_bits_vec, // @[FPU.scala:574:14] input [2:0] io_in_bits_rm, // @[FPU.scala:574:14] input [1:0] io_in_bits_fmaCmd, // @[FPU.scala:574:14] input [1:0] io_in_bits_typ, // @[FPU.scala:574:14] input [1:0] io_in_bits_fmt, // @[FPU.scala:574:14] input [64:0] io_in_bits_in1, // @[FPU.scala:574:14] input [64:0] io_in_bits_in2, // @[FPU.scala:574:14] input [64:0] io_in_bits_in3, // @[FPU.scala:574:14] output [64:0] io_out_bits_data, // @[FPU.scala:574:14] output [4:0] io_out_bits_exc, // @[FPU.scala:574:14] input io_lt // @[FPU.scala:574:14] ); wire [32:0] _narrower_1_io_out; // @[FPU.scala:619:30] wire [4:0] _narrower_1_io_exceptionFlags; // @[FPU.scala:619:30] wire [16:0] _narrower_io_out; // @[FPU.scala:619:30] wire [4:0] _narrower_io_exceptionFlags; // @[FPU.scala:619:30] wire io_in_valid_0 = io_in_valid; // @[FPU.scala:573:7] wire io_in_bits_ldst_0 = io_in_bits_ldst; // @[FPU.scala:573:7] wire io_in_bits_wen_0 = io_in_bits_wen; // @[FPU.scala:573:7] wire io_in_bits_ren1_0 = io_in_bits_ren1; // @[FPU.scala:573:7] wire io_in_bits_ren2_0 = io_in_bits_ren2; // @[FPU.scala:573:7] wire io_in_bits_ren3_0 = io_in_bits_ren3; // @[FPU.scala:573:7] wire io_in_bits_swap12_0 = io_in_bits_swap12; // @[FPU.scala:573:7] wire io_in_bits_swap23_0 = io_in_bits_swap23; // @[FPU.scala:573:7] wire [1:0] io_in_bits_typeTagIn_0 = io_in_bits_typeTagIn; // @[FPU.scala:573:7] wire [1:0] io_in_bits_typeTagOut_0 = io_in_bits_typeTagOut; // @[FPU.scala:573:7] wire io_in_bits_fromint_0 = io_in_bits_fromint; // @[FPU.scala:573:7] wire io_in_bits_toint_0 = io_in_bits_toint; // @[FPU.scala:573:7] wire io_in_bits_fastpipe_0 = io_in_bits_fastpipe; // @[FPU.scala:573:7] wire io_in_bits_fma_0 = io_in_bits_fma; // @[FPU.scala:573:7] wire io_in_bits_div_0 = io_in_bits_div; // @[FPU.scala:573:7] wire io_in_bits_sqrt_0 = io_in_bits_sqrt; // @[FPU.scala:573:7] wire io_in_bits_wflags_0 = io_in_bits_wflags; // @[FPU.scala:573:7] wire io_in_bits_vec_0 = io_in_bits_vec; // @[FPU.scala:573:7] wire [2:0] io_in_bits_rm_0 = io_in_bits_rm; // @[FPU.scala:573:7] wire [1:0] io_in_bits_fmaCmd_0 = io_in_bits_fmaCmd; // @[FPU.scala:573:7] wire [1:0] io_in_bits_typ_0 = io_in_bits_typ; // @[FPU.scala:573:7] wire [1:0] io_in_bits_fmt_0 = io_in_bits_fmt; // @[FPU.scala:573:7] wire [64:0] io_in_bits_in1_0 = io_in_bits_in1; // @[FPU.scala:573:7] wire [64:0] io_in_bits_in2_0 = io_in_bits_in2; // @[FPU.scala:573:7] wire [64:0] io_in_bits_in3_0 = io_in_bits_in3; // @[FPU.scala:573:7] wire io_lt_0 = io_lt; // @[FPU.scala:573:7] wire [32:0] _narrowed_maskedNaN_T = 33'h1EF7FFFFF; // @[FPU.scala:413:27] wire io_out_pipe_out_valid; // @[Valid.scala:135:21] wire [64:0] io_out_pipe_out_bits_data; // @[Valid.scala:135:21] wire [4:0] io_out_pipe_out_bits_exc; // @[Valid.scala:135:21] wire [64:0] io_out_bits_data_0; // @[FPU.scala:573:7] wire [4:0] io_out_bits_exc_0; // @[FPU.scala:573:7] wire io_out_valid; // @[FPU.scala:573:7] reg in_pipe_v; // @[Valid.scala:141:24] wire in_valid = in_pipe_v; // @[Valid.scala:135:21, :141:24] reg in_pipe_b_ldst; // @[Valid.scala:142:26] wire in_bits_ldst = in_pipe_b_ldst; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_wen; // @[Valid.scala:142:26] wire in_bits_wen = in_pipe_b_wen; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_ren1; // @[Valid.scala:142:26] wire in_bits_ren1 = in_pipe_b_ren1; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_ren2; // @[Valid.scala:142:26] wire in_bits_ren2 = in_pipe_b_ren2; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_ren3; // @[Valid.scala:142:26] wire in_bits_ren3 = in_pipe_b_ren3; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_swap12; // @[Valid.scala:142:26] wire in_bits_swap12 = in_pipe_b_swap12; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_swap23; // @[Valid.scala:142:26] wire in_bits_swap23 = in_pipe_b_swap23; // @[Valid.scala:135:21, :142:26] reg [1:0] in_pipe_b_typeTagIn; // @[Valid.scala:142:26] wire [1:0] in_bits_typeTagIn = in_pipe_b_typeTagIn; // @[Valid.scala:135:21, :142:26] reg [1:0] in_pipe_b_typeTagOut; // @[Valid.scala:142:26] wire [1:0] in_bits_typeTagOut = in_pipe_b_typeTagOut; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_fromint; // @[Valid.scala:142:26] wire in_bits_fromint = in_pipe_b_fromint; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_toint; // @[Valid.scala:142:26] wire in_bits_toint = in_pipe_b_toint; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_fastpipe; // @[Valid.scala:142:26] wire in_bits_fastpipe = in_pipe_b_fastpipe; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_fma; // @[Valid.scala:142:26] wire in_bits_fma = in_pipe_b_fma; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_div; // @[Valid.scala:142:26] wire in_bits_div = in_pipe_b_div; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_sqrt; // @[Valid.scala:142:26] wire in_bits_sqrt = in_pipe_b_sqrt; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_wflags; // @[Valid.scala:142:26] wire in_bits_wflags = in_pipe_b_wflags; // @[Valid.scala:135:21, :142:26] reg in_pipe_b_vec; // @[Valid.scala:142:26] wire in_bits_vec = in_pipe_b_vec; // @[Valid.scala:135:21, :142:26] reg [2:0] in_pipe_b_rm; // @[Valid.scala:142:26] wire [2:0] in_bits_rm = in_pipe_b_rm; // @[Valid.scala:135:21, :142:26] reg [1:0] in_pipe_b_fmaCmd; // @[Valid.scala:142:26] wire [1:0] in_bits_fmaCmd = in_pipe_b_fmaCmd; // @[Valid.scala:135:21, :142:26] reg [1:0] in_pipe_b_typ; // @[Valid.scala:142:26] wire [1:0] in_bits_typ = in_pipe_b_typ; // @[Valid.scala:135:21, :142:26] reg [1:0] in_pipe_b_fmt; // @[Valid.scala:142:26] wire [1:0] in_bits_fmt = in_pipe_b_fmt; // @[Valid.scala:135:21, :142:26] reg [64:0] in_pipe_b_in1; // @[Valid.scala:142:26] wire [64:0] in_bits_in1 = in_pipe_b_in1; // @[Valid.scala:135:21, :142:26] reg [64:0] in_pipe_b_in2; // @[Valid.scala:142:26] wire [64:0] in_bits_in2 = in_pipe_b_in2; // @[Valid.scala:135:21, :142:26] reg [64:0] in_pipe_b_in3; // @[Valid.scala:142:26] wire [64:0] in_bits_in3 = in_pipe_b_in3; // @[Valid.scala:135:21, :142:26] wire _signNum_T = in_bits_rm[1]; // @[Valid.scala:135:21] wire [64:0] _signNum_T_1 = in_bits_in1 ^ in_bits_in2; // @[Valid.scala:135:21] wire _signNum_T_2 = in_bits_rm[0]; // @[Valid.scala:135:21] wire _isLHS_T = in_bits_rm[0]; // @[Valid.scala:135:21] wire [64:0] _signNum_T_3 = ~in_bits_in2; // @[Valid.scala:135:21] wire [64:0] _signNum_T_4 = _signNum_T_2 ? _signNum_T_3 : in_bits_in2; // @[Valid.scala:135:21] wire [64:0] signNum = _signNum_T ? _signNum_T_1 : _signNum_T_4; // @[FPU.scala:582:{20,31,48,66}] wire _fsgnj_T = signNum[64]; // @[FPU.scala:582:20, :583:26] wire [63:0] _fsgnj_T_1 = in_bits_in1[63:0]; // @[Valid.scala:135:21] wire [64:0] fsgnj = {_fsgnj_T, _fsgnj_T_1}; // @[FPU.scala:583:{18,26,45}] wire [64:0] fsgnjMux_data; // @[FPU.scala:585:22] wire [4:0] fsgnjMux_exc; // @[FPU.scala:585:22] wire [2:0] _isnan1_T = in_bits_in1[63:61]; // @[Valid.scala:135:21] wire [2:0] _isInvalid_T = in_bits_in1[63:61]; // @[Valid.scala:135:21] wire [2:0] _widened_T = in_bits_in1[63:61]; // @[Valid.scala:135:21] wire [2:0] _fsgnjMux_exc_T_1 = in_bits_in1[63:61]; // @[Valid.scala:135:21] wire isnan1 = &_isnan1_T; // @[FPU.scala:249:{25,56}] wire [2:0] _isnan2_T = in_bits_in2[63:61]; // @[Valid.scala:135:21] wire [2:0] _isInvalid_T_5 = in_bits_in2[63:61]; // @[Valid.scala:135:21] wire isnan2 = &_isnan2_T; // @[FPU.scala:249:{25,56}] wire _isInvalid_T_1 = &_isInvalid_T; // @[FPU.scala:249:{25,56}] wire _isInvalid_T_2 = in_bits_in1[51]; // @[Valid.scala:135:21] wire _fsgnjMux_exc_T_3 = in_bits_in1[51]; // @[Valid.scala:135:21] wire _isInvalid_T_3 = ~_isInvalid_T_2; // @[FPU.scala:250:{37,39}] wire _isInvalid_T_4 = _isInvalid_T_1 & _isInvalid_T_3; // @[FPU.scala:249:56, :250:{34,37}] wire _isInvalid_T_6 = &_isInvalid_T_5; // @[FPU.scala:249:{25,56}] wire _isInvalid_T_7 = in_bits_in2[51]; // @[Valid.scala:135:21] wire _isInvalid_T_8 = ~_isInvalid_T_7; // @[FPU.scala:250:{37,39}] wire _isInvalid_T_9 = _isInvalid_T_6 & _isInvalid_T_8; // @[FPU.scala:249:56, :250:{34,37}] wire isInvalid = _isInvalid_T_4 \| _isInvalid_T_9; // @[FPU.scala:250:34, :592:49] wire isNaNOut = isnan1 & isnan2; // @[FPU.scala:249:56, :593:27] wire _isLHS_T_1 = _isLHS_T != io_lt_0; // @[FPU.scala:573:7, :594:{37,41}] wire _isLHS_T_2 = ~isnan1; // @[FPU.scala:249:56, :594:54] wire _isLHS_T_3 = _isLHS_T_1 & _isLHS_T_2; // @[FPU.scala:594:{41,51,54}] wire isLHS = isnan2 \| _isLHS_T_3; // @[FPU.scala:249:56, :594:{24,51}] wire [4:0] _fsgnjMux_exc_T = {isInvalid, 4'h0}; // @[FPU.scala:592:49, :595:31] wire [64:0] _fsgnjMux_data_T = isLHS ? in_bits_in1 : in_bits_in2; // @[Valid.scala:135:21] wire [64:0] _fsgnjMux_data_T_1 = isNaNOut ? 65'hE008000000000000 : _fsgnjMux_data_T; // @[FPU.scala:593:27, :596:{25,53}] wire [64:0] mux_data; // @[FPU.scala:601:24] wire [4:0] mux_exc; // @[FPU.scala:601:24] wire _T_7 = in_bits_typeTagOut == 2'h0; // @[Valid.scala:135:21] wire [47:0] _mux_data_T = fsgnjMux_data[64:17]; // @[FPU.scala:585:22, :604:37] wire [47:0] _mux_data_T_6 = fsgnjMux_data[64:17]; // @[FPU.scala:585:22, :604:37, :624:39] wire mux_data_sign = fsgnjMux_data[64]; // @[FPU.scala:274:17, :585:22] wire mux_data_sign_1 = fsgnjMux_data[64]; // @[FPU.scala:274:17, :585:22] wire [51:0] mux_data_fractIn = fsgnjMux_data[51:0]; // @[FPU.scala:275:20, :585:22] wire [51:0] mux_data_fractIn_1 = fsgnjMux_data[51:0]; // @[FPU.scala:275:20, :585:22] wire [11:0] mux_data_expIn = fsgnjMux_data[63:52]; // @[FPU.scala:276:18, :585:22] wire [11:0] mux_data_expIn_1 = fsgnjMux_data[63:52]; // @[FPU.scala:276:18, :585:22] wire [62:0] _mux_data_fractOut_T = {mux_data_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28] wire [9:0] mux_data_fractOut = _mux_data_fractOut_T[62:53]; // @[FPU.scala:277:{28,38}] wire [2:0] mux_data_expOut_expCode = mux_data_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _mux_data_expOut_commonCase_T = {1'h0, mux_data_expIn} + 13'h20; // @[FPU.scala:276:18, :280:31] wire [11:0] _mux_data_expOut_commonCase_T_1 = _mux_data_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _mux_data_expOut_commonCase_T_2 = {1'h0, _mux_data_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] mux_data_expOut_commonCase = _mux_data_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _mux_data_expOut_T = mux_data_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _mux_data_expOut_T_1 = mux_data_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _mux_data_expOut_T_2 = _mux_data_expOut_T \| _mux_data_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [2:0] _mux_data_expOut_T_3 = mux_data_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69] wire [5:0] _mux_data_expOut_T_4 = {mux_data_expOut_expCode, _mux_data_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [5:0] _mux_data_expOut_T_5 = mux_data_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97] wire [5:0] mux_data_expOut = _mux_data_expOut_T_2 ? _mux_data_expOut_T_4 : _mux_data_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [6:0] mux_data_hi = {mux_data_sign, mux_data_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [16:0] _mux_data_T_1 = {mux_data_hi, mux_data_fractOut}; // @[FPU.scala:277:38, :283:8] wire [64:0] _mux_data_T_2 = {_mux_data_T, _mux_data_T_1}; // @[FPU.scala:283:8, :604:{22,37}] wire _T_8 = in_bits_typeTagOut == 2'h1; // @[Valid.scala:135:21] wire [31:0] _mux_data_T_3 = fsgnjMux_data[64:33]; // @[FPU.scala:585:22, :604:37] wire [31:0] _mux_data_T_8 = fsgnjMux_data[64:33]; // @[FPU.scala:585:22, :604:37, :624:39] wire [75:0] _mux_data_fractOut_T_1 = {mux_data_fractIn_1, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] mux_data_fractOut_1 = _mux_data_fractOut_T_1[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] mux_data_expOut_expCode_1 = mux_data_expIn_1[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _mux_data_expOut_commonCase_T_3 = {1'h0, mux_data_expIn_1} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _mux_data_expOut_commonCase_T_4 = _mux_data_expOut_commonCase_T_3[11:0]; // @[FPU.scala:280:31] wire [12:0] _mux_data_expOut_commonCase_T_5 = {1'h0, _mux_data_expOut_commonCase_T_4} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] mux_data_expOut_commonCase_1 = _mux_data_expOut_commonCase_T_5[11:0]; // @[FPU.scala:280:50] wire _mux_data_expOut_T_6 = mux_data_expOut_expCode_1 == 3'h0; // @[FPU.scala:279:26, :281:19] wire _mux_data_expOut_T_7 = mux_data_expOut_expCode_1 > 3'h5; // @[FPU.scala:279:26, :281:38] wire _mux_data_expOut_T_8 = _mux_data_expOut_T_6 \| _mux_data_expOut_T_7; // @[FPU.scala:281:{19,27,38}] wire [5:0] _mux_data_expOut_T_9 = mux_data_expOut_commonCase_1[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _mux_data_expOut_T_10 = {mux_data_expOut_expCode_1, _mux_data_expOut_T_9}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _mux_data_expOut_T_11 = mux_data_expOut_commonCase_1[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] mux_data_expOut_1 = _mux_data_expOut_T_8 ? _mux_data_expOut_T_10 : _mux_data_expOut_T_11; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] mux_data_hi_1 = {mux_data_sign_1, mux_data_expOut_1}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] _mux_data_T_4 = {mux_data_hi_1, mux_data_fractOut_1}; // @[FPU.scala:277:38, :283:8] wire [64:0] _mux_data_T_5 = {_mux_data_T_3, _mux_data_T_4}; // @[FPU.scala:283:8, :604:{22,37}] wire _T_3 = in_bits_wflags & ~in_bits_ren2; // @[Valid.scala:135:21] wire _widened_T_1 = &_widened_T; // @[FPU.scala:249:{25,56}] wire [64:0] widened = _widened_T_1 ? 65'hE008000000000000 : in_bits_in1; // @[Valid.scala:135:21] assign fsgnjMux_data = _T_3 ? widened : in_bits_wflags ? _fsgnjMux_data_T_1 : fsgnj; // @[Valid.scala:135:21] wire _fsgnjMux_exc_T_2 = &_fsgnjMux_exc_T_1; // @[FPU.scala:249:{25,56}] wire _fsgnjMux_exc_T_4 = ~_fsgnjMux_exc_T_3; // @[FPU.scala:250:{37,39}] wire _fsgnjMux_exc_T_5 = _fsgnjMux_exc_T_2 & _fsgnjMux_exc_T_4; // @[FPU.scala:249:56, :250:{34,37}] wire [4:0] _fsgnjMux_exc_T_6 = {_fsgnjMux_exc_T_5, 4'h0}; // @[FPU.scala:250:34, :595:31, :613:51] assign fsgnjMux_exc = _T_3 ? _fsgnjMux_exc_T_6 : in_bits_wflags ? _fsgnjMux_exc_T : 5'h0; // @[Valid.scala:135:21] wire [64:0] _mux_data_T_7 = {_mux_data_T_6, _narrower_io_out}; // @[FPU.scala:619:30, :624:{24,39}] wire _T_11 = _T_8 & in_bits_typeTagOut < in_bits_typeTagIn; // @[Valid.scala:135:21] wire [32:0] narrowed_maskedNaN = _narrower_1_io_out & 33'h1EF7FFFFF; // @[FPU.scala:413:25, :619:30] wire [2:0] _narrowed_T = _narrower_1_io_out[31:29]; // @[FPU.scala:249:25, :619:30] wire _narrowed_T_1 = &_narrowed_T; // @[FPU.scala:249:{25,56}] wire [32:0] narrowed = _narrowed_T_1 ? narrowed_maskedNaN : _narrower_1_io_out; // @[FPU.scala:249:56, :413:25, :414:10, :619:30] wire [64:0] _mux_data_T_9 = {_mux_data_T_8, narrowed}; // @[FPU.scala:414:10, :624:{24,39}] assign mux_data = _T_3 ? (_T_11 ? _mux_data_T_9 : _T_7 ? _mux_data_T_7 : _T_8 ? _mux_data_T_5 : fsgnjMux_data) : _T_8 ? _mux_data_T_5 : _T_7 ? _mux_data_T_2 : fsgnjMux_data; // @[FPU.scala:585:22, :601:24, :603:{18,36}, :604:{16,22}, :608:{24,42}, :618:{76,126}, :624:{18,24}] assign mux_exc = _T_3 ? (_T_11 ? _narrower_1_io_exceptionFlags : _T_7 ? _narrower_io_exceptionFlags : fsgnjMux_exc) : fsgnjMux_exc; // @[FPU.scala:585:22, :601:24, :603:18, :608:{24,42}, :618:{76,126}, :619:30, :625:17] reg io_out_pipe_v; // @[Valid.scala:141:24] assign io_out_pipe_out_valid = io_out_pipe_v; // @[Valid.scala:135:21, :141:24] reg [64:0] io_out_pipe_b_data; // @[Valid.scala:142:26] assign io_out_pipe_out_bits_data = io_out_pipe_b_data; // @[Valid.scala:135:21, :142:26] reg [4:0] io_out_pipe_b_exc; // @[Valid.scala:142:26] assign io_out_pipe_out_bits_exc = io_out_pipe_b_exc; // @[Valid.scala:135:21, :142:26] assign io_out_valid = io_out_pipe_out_valid; // @[Valid.scala:135:21] assign io_out_bits_data_0 = io_out_pipe_out_bits_data; // @[Valid.scala:135:21] assign io_out_bits_exc_0 = io_out_pipe_out_bits_exc; // @[Valid.scala:135:21] always @(posedge clock) begin // @[FPU.scala:573:7] if (reset) begin // @[FPU.scala:573:7] in_pipe_v <= 1'h0; // @[Valid.scala:141:24] io_out_pipe_v <= 1'h0; // @[Valid.scala:141:24] end else begin // @[FPU.scala:573:7] in_pipe_v <= io_in_valid_0; // @[Valid.scala:141:24] io_out_pipe_v <= in_valid; // @[Valid.scala:135:21, :141:24] end if (io_in_valid_0) begin // @[FPU.scala:573:7] in_pipe_b_ldst <= io_in_bits_ldst_0; // @[Valid.scala:142:26] in_pipe_b_wen <= io_in_bits_wen_0; // @[Valid.scala:142:26] in_pipe_b_ren1 <= io_in_bits_ren1_0; // @[Valid.scala:142:26] in_pipe_b_ren2 <= io_in_bits_ren2_0; // @[Valid.scala:142:26] in_pipe_b_ren3 <= io_in_bits_ren3_0; // @[Valid.scala:142:26] in_pipe_b_swap12 <= io_in_bits_swap12_0; // @[Valid.scala:142:26] in_pipe_b_swap23 <= io_in_bits_swap23_0; // @[Valid.scala:142:26] in_pipe_b_typeTagIn <= io_in_bits_typeTagIn_0; // @[Valid.scala:142:26] in_pipe_b_typeTagOut <= io_in_bits_typeTagOut_0; // @[Valid.scala:142:26] in_pipe_b_fromint <= io_in_bits_fromint_0; // @[Valid.scala:142:26] in_pipe_b_toint <= io_in_bits_toint_0; // @[Valid.scala:142:26] in_pipe_b_fastpipe <= io_in_bits_fastpipe_0; // @[Valid.scala:142:26] in_pipe_b_fma <= io_in_bits_fma_0; // @[Valid.scala:142:26] in_pipe_b_div <= io_in_bits_div_0; // @[Valid.scala:142:26] in_pipe_b_sqrt <= io_in_bits_sqrt_0; // @[Valid.scala:142:26] in_pipe_b_wflags <= io_in_bits_wflags_0; // @[Valid.scala:142:26] in_pipe_b_vec <= io_in_bits_vec_0; // @[Valid.scala:142:26] in_pipe_b_rm <= io_in_bits_rm_0; // @[Valid.scala:142:26] in_pipe_b_fmaCmd <= io_in_bits_fmaCmd_0; // @[Valid.scala:142:26] in_pipe_b_typ <= io_in_bits_typ_0; // @[Valid.scala:142:26] in_pipe_b_fmt <= io_in_bits_fmt_0; // @[Valid.scala:142:26] in_pipe_b_in1 <= io_in_bits_in1_0; // @[Valid.scala:142:26] in_pipe_b_in2 <= io_in_bits_in2_0; // @[Valid.scala:142:26] in_pipe_b_in3 <= io_in_bits_in3_0; // @[Valid.scala:142:26] end if (in_valid) begin // @[Valid.scala:135:21] io_out_pipe_b_data <= mux_data; // @[Valid.scala:142:26] io_out_pipe_b_exc <= mux_exc; // @[Valid.scala:142:26] end always @(posedge) RecFNToRecFN_4 narrower ( // @[FPU.scala:619:30] .io_in (in_bits_in1), // @[Valid.scala:135:21] .io_roundingMode (in_bits_rm), // @[Valid.scala:135:21] .io_out (_narrower_io_out), .io_exceptionFlags (_narrower_io_exceptionFlags) ); // @[FPU.scala:619:30] RecFNToRecFN_5 narrower_1 ( // @[FPU.scala:619:30] .io_in (in_bits_in1), // @[Valid.scala:135:21] .io_roundingMode (in_bits_rm), // @[Valid.scala:135:21] .io_out (_narrower_1_io_out), .io_exceptionFlags (_narrower_1_io_exceptionFlags) ); // @[FPU.scala:619:30] assign io_out_bits_data = io_out_bits_data_0; // @[FPU.scala:573:7] assign io_out_bits_exc = io_out_bits_exc_0; // @[FPU.scala:573:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File DMACommandTracker.scala: package gemmini import chisel3._ import chisel3.util._ // This module is meant to go inside the Load controller, where it can track which commands are currently // in flight and which are completed class DMACommandTracker[T <: Data](val nCmds: Int, val maxBytes: Int, tag_t: => T) extends Module { def cmd_id_t = UInt((log2Ceil(nCmds) max 1).W) val io = IO(new Bundle { // TODO is there an existing decoupled interface in the standard library which matches this use-case? val alloc = new Bundle { val valid = Input(Bool()) val ready = Output(Bool()) class BitsT(tag_t: => T, cmd_id_t: UInt) extends Bundle { // This was only spun off as its own class to resolve CloneType errors val tag = Input(tag_t.cloneType) val bytes_to_read = Input(UInt(log2Up(maxBytes+1).W)) val cmd_id = Output(cmd_id_t.cloneType) } val bits = new BitsT(tag_t.cloneType, cmd_id_t.cloneType) def fire(dummy: Int = 0) = valid && ready } class RequestReturnedT(cmd_id_t: UInt) extends Bundle { // This was only spun off as its own class to resolve CloneType errors val bytes_read = UInt(log2Up(maxBytes+1).W) val cmd_id = cmd_id_t.cloneType } val request_returned = Flipped(Valid(new RequestReturnedT(cmd_id_t.cloneType))) class CmdCompletedT(cmd_id_t: UInt, tag_t: T) extends Bundle { val cmd_id = cmd_id_t.cloneType val tag = tag_t.cloneType } val cmd_completed = Decoupled(new CmdCompletedT(cmd_id_t.cloneType, tag_t.cloneType)) val busy = Output(Bool()) }) class Entry extends Bundle { val valid = Bool() val tag = tag_t.cloneType val bytes_left = UInt(log2Up(maxBytes+1).W) def init(dummy: Int = 0): Unit = { valid := false.B } } // val cmds = RegInit(VecInit(Seq.fill(nCmds)(entry_init))) val cmds = Reg(Vec(nCmds, new Entry)) val cmd_valids = cmds.map(_.valid) val next_empty_alloc = MuxCase(0.U, cmd_valids.zipWithIndex.map { case (v, i) => (!v) -> i.U }) io.alloc.ready := !cmd_valids.reduce(_ && _) io.alloc.bits.cmd_id := next_empty_alloc io.busy := cmd_valids.reduce(_ \|\| _) val cmd_completed_id = MuxCase(0.U, cmds.zipWithIndex.map { case (cmd, i) => (cmd.valid && cmd.bytes_left === 0.U) -> i.U }) io.cmd_completed.valid := cmds.map(cmd => cmd.valid && cmd.bytes_left === 0.U).reduce(_ \|\| _) io.cmd_completed.bits.cmd_id := cmd_completed_id io.cmd_completed.bits.tag := cmds(cmd_completed_id).tag when (io.alloc.fire()) { cmds(next_empty_alloc).valid := true.B cmds(next_empty_alloc).tag := io.alloc.bits.tag cmds(next_empty_alloc).bytes_left := io.alloc.bits.bytes_to_read } when (io.request_returned.fire) { val cmd_id = io.request_returned.bits.cmd_id cmds(cmd_id).bytes_left := cmds(cmd_id).bytes_left - io.request_returned.bits.bytes_read assert(cmds(cmd_id).valid) assert(cmds(cmd_id).bytes_left >= io.request_returned.bits.bytes_read) } when (io.cmd_completed.fire) { cmds(io.cmd_completed.bits.cmd_id).valid := false.B } when (reset.asBool) { cmds.foreach(_.init()) } } File LocalAddr.scala: package gemmini import chisel3._ import chisel3.util._ class LocalAddr(sp_banks: Int, sp_bank_entries: Int, acc_banks: Int, acc_bank_entries: Int) extends Bundle { private val localAddrBits = 32 // TODO magic number private val spAddrBits = log2Ceil(sp_banks * sp_bank_entries) private val accAddrBits = log2Ceil(acc_banks * acc_bank_entries) private val maxAddrBits = spAddrBits max accAddrBits private val spBankBits = log2Up(sp_banks) private val spBankRowBits = log2Up(sp_bank_entries) private val accBankBits = log2Up(acc_banks) val accBankRowBits = log2Up(acc_bank_entries) val spRows = sp_banks * sp_bank_entries val is_acc_addr = Bool() val accumulate = Bool() val read_full_acc_row = Bool() val norm_cmd = NormCmd() private val metadata_w = is_acc_addr.getWidth + accumulate.getWidth + read_full_acc_row.getWidth + norm_cmd.getWidth assert(maxAddrBits + metadata_w < 32) val garbage = UInt(((localAddrBits - maxAddrBits - metadata_w - 1) max 0).W) val garbage_bit = if (localAddrBits - maxAddrBits >= metadata_w + 1) UInt(1.W) else UInt(0.W) val data = UInt(maxAddrBits.W) def sp_bank(dummy: Int = 0) = if (spAddrBits == spBankRowBits) 0.U else data(spAddrBits - 1, spBankRowBits) def sp_row(dummy: Int = 0) = data(spBankRowBits - 1, 0) def acc_bank(dummy: Int = 0) = if (accAddrBits == accBankRowBits) 0.U else data(accAddrBits - 1, accBankRowBits) def acc_row(dummy: Int = 0) = data(accBankRowBits - 1, 0) def full_sp_addr(dummy: Int = 0) = data(spAddrBits - 1, 0) def full_acc_addr(dummy: Int = 0) = data(accAddrBits - 1, 0) def is_same_address(other: LocalAddr): Bool = is_acc_addr === other.is_acc_addr && data === other.data def is_same_address(other: UInt): Bool = is_same_address(other.asTypeOf(this)) def is_garbage(dummy: Int = 0) = is_acc_addr && accumulate && read_full_acc_row && data.andR && (if (garbage_bit.getWidth > 0) garbage_bit.asBool else true.B) def +(other: UInt) = { require(isPow2(sp_bank_entries)) // TODO remove this requirement require(isPow2(acc_bank_entries)) // TODO remove this requirement val result = WireInit(this) result.data := data + other result } def <=(other: LocalAddr) = is_acc_addr === other.is_acc_addr && Mux(is_acc_addr, full_acc_addr() <= other.full_acc_addr(), full_sp_addr() <= other.full_sp_addr()) def <(other: LocalAddr) = is_acc_addr === other.is_acc_addr && Mux(is_acc_addr, full_acc_addr() < other.full_acc_addr(), full_sp_addr() < other.full_sp_addr()) def >(other: LocalAddr) = is_acc_addr === other.is_acc_addr && Mux(is_acc_addr, full_acc_addr() > other.full_acc_addr(), full_sp_addr() > other.full_sp_addr()) def add_with_overflow(other: UInt): Tuple2[LocalAddr, Bool] = { require(isPow2(sp_bank_entries)) // TODO remove this requirement require(isPow2(acc_bank_entries)) // TODO remove this requirement val sum = data +& other val overflow = Mux(is_acc_addr, sum(accAddrBits), sum(spAddrBits)) val result = WireInit(this) result.data := sum(maxAddrBits - 1, 0) (result, overflow) } // This function can only be used with non-accumulator addresses. Returns both new address and underflow def floorSub(other: UInt, floor: UInt): (LocalAddr, Bool) = { require(isPow2(sp_bank_entries)) // TODO remove this requirement require(isPow2(acc_bank_entries)) // TODO remove this requirement val underflow = data < (floor +& other) val result = WireInit(this) result.data := Mux(underflow, floor, data - other) (result, underflow) } def make_this_garbage(dummy: Int = 0): Unit = { is_acc_addr := true.B accumulate := true.B read_full_acc_row := true.B garbage_bit := 1.U data := ~(0.U(maxAddrBits.W)) } } object LocalAddr { def cast_to_local_addr[T <: Data](local_addr_t: LocalAddr, t: T): LocalAddr = { // This convenience function is basically the same as calling "asTypeOf(local_addr_t)". However, this convenience // function will also cast unnecessary garbage bits to 0, which may help reduce multiplier/adder bitwidths val result = WireInit(t.asTypeOf(local_addr_t)) if (result.garbage_bit.getWidth > 0) result.garbage := 0.U result } def cast_to_sp_addr[T <: Data](local_addr_t: LocalAddr, t: T): LocalAddr = { // This function is a wrapper around cast_to_local_addr, but it assumes that the input will not be the garbage // address val result = WireInit(cast_to_local_addr(local_addr_t, t)) result.is_acc_addr := false.B result.accumulate := false.B result.read_full_acc_row := false.B // assert(!result.garbage_bit, "cast_to_sp_addr doesn't work on garbage addresses") result } def cast_to_acc_addr[T <: Data](local_addr_t: LocalAddr, t: T, accumulate: Bool, read_full: Bool): LocalAddr = { // This function is a wrapper around cast_to_local_addr, but it assumes that the input will not be the garbage // address val result = WireInit(cast_to_local_addr(local_addr_t, t)) result.is_acc_addr := true.B result.accumulate := accumulate result.read_full_acc_row := read_full // assert(!result.garbage_bit, "cast_to_acc_addr doesn't work on garbage addresses") result } def garbage_addr(local_addr_t: LocalAddr): LocalAddr = { val result = Wire(chiselTypeOf(local_addr_t)) result := DontCare result.make_this_garbage() result } } File Util.scala: package gemmini import chisel3._ import chisel3.util._ object Util { def wrappingAdd(u: UInt, n: UInt, max_plus_one: Int): UInt = { val max = max_plus_one - 1 if (max == 0) { 0.U } else { assert(n <= max.U, "cannot wrapAdd when n is larger than max") Mux(u >= max.U - n + 1.U && n =/= 0.U, n - (max.U - u) - 1.U, u + n) } } def wrappingAdd(u: UInt, n: UInt, max_plus_one: UInt, en: Bool = true.B): UInt = { val max = max_plus_one - 1.U assert(n <= max \|\| max === 0.U, "cannot wrapAdd when n is larger than max, unless max is 0") /* Mux(!en, u, Mux (max === 0.U, 0.U, Mux(u >= max - n + 1.U && n =/= 0.U, n - (max - u) - 1.U, u + n))) / MuxCase(u + n, Seq( (!en) -> u, (max === 0.U) -> 0.U, (u >= max - n + 1.U && n =/= 0.U) -> (n - (max - u) - 1.U) )) } def satAdd(u: UInt, v: UInt, max: UInt): UInt = { Mux(u +& v > max, max, u + v) } def floorAdd(u: UInt, n: UInt, max_plus_one: UInt, en: Bool = true.B): UInt = { val max = max_plus_one - 1.U MuxCase(u + n, Seq( (!en) -> u, ((u +& n) > max) -> 0.U )) } def sFloorAdd(s: SInt, n: UInt, max_plus_one: SInt, min: SInt, en: Bool = true.B): SInt = { val max = max_plus_one - 1.S MuxCase(s + n.zext, Seq( (!en) -> s, ((s +& n.zext) > max) -> min )) } def wrappingSub(u: UInt, n: UInt, max_plus_one: Int): UInt = { val max = max_plus_one - 1 assert(n <= max.U, "cannot wrapSub when n is larger than max") Mux(u < n, max.U - (n-u) + 1.U, u - n) } def ceilingDivide(numer: Int, denom: Int): Int = { if (numer % denom == 0) { numer / denom } else { numer / denom + 1} } def closestLowerPowerOf2(u: UInt): UInt = { // TODO figure out a more efficient way of doing this. Is this many muxes really necessary? val exp = u.asBools.zipWithIndex.map { case (b, i) => Mux(b, i.U, 0.U) }.reduce((acc, u) => Mux(acc > u, acc, u)) (1.U << exp).asUInt } def closestAlignedLowerPowerOf2(u: UInt, addr: UInt, stride: UInt, rowBytes: Int): UInt = { val lgRowBytes = log2Ceil(rowBytes) // TODO figure out a more efficient way of doing this. Is this many muxes really necessary? val exp = u.asBools.zipWithIndex.map { case (b, i) => Mux(b && addr(i + lgRowBytes - 1, 0) === 0.U && stride(i + lgRowBytes - 1, 0) === 0.U, i.U, 0.U) }.reduce((acc, u) => Mux(acc > u, acc, u)) (1.U << exp).asUInt } // This function will return "next" with a 0-cycle delay when the "enable" signal is high. It's like a queue with // the "pipe" and "flow" parameters set to "true" def RegEnableThru[T <: Data](next: T, enable: Bool): T = { val buf = RegEnable(next, enable) Mux(enable, next, buf) } def RegEnableThru[T <: Data](next: T, init: T, enable: Bool): T = { val buf = RegEnable(next, init, enable) Mux(enable, next, buf) } def maxOf(u1: UInt, u2: UInt): UInt = { Mux(u1 > u2, u1, u2) } def maxOf[T <: Data](x: T, y: T)(implicit ev: Arithmetic[T]): T = { import ev._ Mux(x > y, x, y) } def minOf(u1: UInt, u2: UInt): UInt = { Mux(u1 < u2, u1, u2) } def accumulateTree[T <: Data](xs: Seq[T])(implicit ev: Arithmetic[T]): T = { import ev._ assert(xs.nonEmpty, "can't accumulate 0 elements") if (xs.length == 1) { xs.head } else { val upperRowLen = 1 << log2Ceil(xs.length) val upperRow = xs.padTo(upperRowLen, xs.head.zero) val pairs = upperRow.grouped(2) val lowerRow = pairs.map { case Seq(a, b) => a + b } accumulateTree(lowerRow.toSeq) } } // An undirectioned Valid bundle class UDValid[T <: Data](t: T) extends Bundle { val valid = Bool() val bits = t.cloneType def push(b: T): Unit = { valid := true.B bits := b } def pop(dummy: Int = 0): T = { valid := false.B bits } } object UDValid { def apply[T <: Data](t: T): UDValid[T] = new UDValid(t) } // creates a Reg and the next-state Wire, and returns both def regwire(bits: Int) = { val wire = Wire(UInt(bits.W)) val reg = RegNext(wire) wire := reg // default wire to read from reg (reg, wire) } } File LoadController.scala: package gemmini import chisel3._ import chisel3.util._ import GemminiISA._ import Util._ import org.chipsalliance.cde.config.Parameters import midas.targetutils.PerfCounter // TODO we need to check for WAW errors here // TODO deal with errors when reading scratchpad responses class LoadController[T <: Data, U <: Data, V <: Data](config: GemminiArrayConfig[T, U, V], coreMaxAddrBits: Int, local_addr_t: LocalAddr) (implicit p: Parameters) extends Module { import config._ val io = IO(new Bundle { val cmd = Flipped(Decoupled(new GemminiCmd(reservation_station_entries))) val dma = new ScratchpadReadMemIO(local_addr_t, mvin_scale_t_bits) val completed = Decoupled(UInt(log2Up(reservation_station_entries).W)) val busy = Output(Bool()) val counter = new CounterEventIO() }) val waiting_for_command :: waiting_for_dma_req_ready :: sending_rows :: Nil = Enum(3) val control_state = RegInit(waiting_for_command) val strides = Reg(Vec(load_states, UInt(coreMaxAddrBits.W))) val scales = Reg(Vec(load_states, UInt(mvin_scale_t_bits.W))) val shrinks = Reg(Vec(load_states, Bool())) // Shrink inputs to accumulator val block_strides = Reg(Vec(load_states, UInt(block_stride_bits.W))) // Spad stride during block move-ins val pixel_repeats = Reg(Vec(load_states, UInt(pixel_repeats_bits.W))) val block_rows = meshRows tileRows val block_cols = meshColumns * tileColumns val row_counter = RegInit(0.U(log2Ceil(block_rows).W)) val cmd = Queue(io.cmd, ld_queue_length) val vaddr = cmd.bits.cmd.rs1 val mvin_rs2 = cmd.bits.cmd.rs2.asTypeOf(new MvinRs2(mvin_rows_bits, mvin_cols_bits, local_addr_t)) val localaddr = mvin_rs2.local_addr val cols = mvin_rs2.num_cols val rows = mvin_rs2.num_rows val config_stride = cmd.bits.cmd.rs2 val config_mvin_rs1 = cmd.bits.cmd.rs1.asTypeOf(new ConfigMvinRs1(mvin_scale_t_bits, block_stride_bits, pixel_repeats_bits)) val config_scale = config_mvin_rs1.scale val config_shrink = config_mvin_rs1.shrink val config_block_stride = config_mvin_rs1.stride val config_pixel_repeats = config_mvin_rs1.pixel_repeats val mstatus = cmd.bits.cmd.status val load_state_id = MuxCase(0.U, Seq((cmd.bits.cmd.inst.funct === LOAD2_CMD) -> 1.U, (cmd.bits.cmd.inst.funct === LOAD3_CMD) -> 2.U)) val config_state_id = config_mvin_rs1.state_id val state_id = Mux(cmd.bits.cmd.inst.funct === CONFIG_CMD, config_state_id, load_state_id) val stride = strides(state_id) val scale = scales(state_id) val shrink = shrinks(state_id) val block_stride = block_strides(state_id) val pixel_repeat = pixel_repeats(state_id) val all_zeros = vaddr === 0.U val localaddr_plus_row_counter = localaddr + row_counter val actual_rows_read = Mux(stride === 0.U && !all_zeros, 1.U, rows) val DoConfig = cmd.bits.cmd.inst.funct === CONFIG_CMD val DoLoad = !DoConfig // TODO change this if more commands are added cmd.ready := false.B // Command tracker instantiation val nCmds = (max_in_flight_mem_reqs / block_rows) + 1 val deps_t = new Bundle { val rob_id = UInt(log2Up(reservation_station_entries).W) } val maxBytesInRowRequest = config.dma_maxbytes max (block_cols * config.inputType.getWidth / 8) max (block_cols * config.accType.getWidth / 8) val maxBytesInMatRequest = block_rows * maxBytesInRowRequest val cmd_tracker = Module(new DMACommandTracker(nCmds, maxBytesInMatRequest, deps_t)) io.busy := cmd.valid \|\| cmd_tracker.io.busy // DMA IO wiring io.dma.req.valid := (control_state === waiting_for_command && cmd.valid && DoLoad && cmd_tracker.io.alloc.ready) \|\| control_state === waiting_for_dma_req_ready \|\| (control_state === sending_rows && row_counter =/= 0.U) io.dma.req.bits.vaddr := vaddr + row_counter * stride io.dma.req.bits.laddr := localaddr_plus_row_counter io.dma.req.bits.cols := cols io.dma.req.bits.repeats := Mux(stride === 0.U && !all_zeros, rows - 1.U, 0.U) io.dma.req.bits.block_stride := block_stride io.dma.req.bits.scale := scale io.dma.req.bits.has_acc_bitwidth := localaddr_plus_row_counter.is_acc_addr && !shrink io.dma.req.bits.all_zeros := all_zeros io.dma.req.bits.status := mstatus io.dma.req.bits.pixel_repeats := pixel_repeat // Command tracker IO cmd_tracker.io.alloc.valid := control_state === waiting_for_command && cmd.valid && DoLoad cmd_tracker.io.alloc.bits.bytes_to_read := Mux(io.dma.req.bits.has_acc_bitwidth, cols * actual_rows_read * config.accType.getWidth.U, cols * actual_rows_read * config.inputType.getWidth.U) >> 3 // We replaced a very clear "/ 8.U" operation here with a ">> 3" operation, solely to satisfy Verilator's linter cmd_tracker.io.alloc.bits.tag.rob_id := cmd.bits.rob_id.bits cmd_tracker.io.request_returned.valid := io.dma.resp.fire // TODO use a bundle connect cmd_tracker.io.request_returned.bits.cmd_id := io.dma.resp.bits.cmd_id // TODO use a bundle connect cmd_tracker.io.request_returned.bits.bytes_read := io.dma.resp.bits.bytesRead cmd_tracker.io.cmd_completed.ready := io.completed.ready val cmd_id = RegEnableThru(cmd_tracker.io.alloc.bits.cmd_id, cmd_tracker.io.alloc.fire()) // TODO is this really better than a simple RegEnable? io.dma.req.bits.cmd_id := cmd_id io.completed.valid := cmd_tracker.io.cmd_completed.valid io.completed.bits := cmd_tracker.io.cmd_completed.bits.tag.rob_id io.busy := cmd.valid \|\| cmd_tracker.io.busy // Row counter when (io.dma.req.fire) { row_counter := wrappingAdd(row_counter, 1.U, actual_rows_read) assert(block_stride >= rows) } // Control logic switch (control_state) { is (waiting_for_command) { when (cmd.valid) { when(DoConfig) { stride := config_stride scale := config_scale shrink := config_shrink block_stride := config_block_stride pixel_repeat := Mux(config_pixel_repeats === 0.U, 1.U, config_pixel_repeats) // TODO this default value was just added to maintain backwards compatibility. we should deprecate and remove it later cmd.ready := true.B } .elsewhen(DoLoad && cmd_tracker.io.alloc.fire()) { control_state := Mux(io.dma.req.fire, sending_rows, waiting_for_dma_req_ready) } } } is (waiting_for_dma_req_ready) { when (io.dma.req.fire) { control_state := sending_rows } } is (sending_rows) { val last_row = row_counter === 0.U \|\| (row_counter === actual_rows_read-1.U && io.dma.req.fire) when (last_row) { control_state := waiting_for_command cmd.ready := true.B } } } // Optimizations based on config parameters if (!has_first_layer_optimizations) pixel_repeats.foreach(_ := 1.U) // Performance counter CounterEventIO.init(io.counter) io.counter.connectEventSignal(CounterEvent.LOAD_ACTIVE_CYCLE, control_state === sending_rows) io.counter.connectEventSignal(CounterEvent.LOAD_DMA_WAIT_CYCLE, control_state === waiting_for_dma_req_ready) io.counter.connectEventSignal(CounterEvent.LOAD_SCRATCHPAD_WAIT_CYCLE, io.dma.req.valid && !io.dma.req.ready) if (use_firesim_simulation_counters) { PerfCounter(io.dma.req.valid && !io.dma.req.ready, "load_dma_wait_cycle", "cycles during which load controller is waiting for DMA to be available") } // Assertions assert(!(cmd_tracker.io.alloc.fire() && cmd_tracker.io.alloc.bits.bytes_to_read === 0.U), "A single mvin instruction must load more than 0 bytes") assert(has_first_layer_optimizations.B \|\| !(cmd.valid && DoConfig && config_pixel_repeats > 1.U), "If first-layer optimizations are not enabled, then pixel-repeats cannot be greater than 1") }	module LoadController( // @[LoadController.scala:13:7] input clock, // @[LoadController.scala:13:7] input reset, // @[LoadController.scala:13:7] output io_cmd_ready, // @[LoadController.scala:18:14] input io_cmd_valid, // @[LoadController.scala:18:14] input [6:0] io_cmd_bits_cmd_inst_funct, // @[LoadController.scala:18:14] input [4:0] io_cmd_bits_cmd_inst_rs2, // @[LoadController.scala:18:14] input [4:0] io_cmd_bits_cmd_inst_rs1, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_inst_xd, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_inst_xs1, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_inst_xs2, // @[LoadController.scala:18:14] input [4:0] io_cmd_bits_cmd_inst_rd, // @[LoadController.scala:18:14] input [6:0] io_cmd_bits_cmd_inst_opcode, // @[LoadController.scala:18:14] input [63:0] io_cmd_bits_cmd_rs1, // @[LoadController.scala:18:14] input [63:0] io_cmd_bits_cmd_rs2, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_debug, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_cease, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_wfi, // @[LoadController.scala:18:14] input [31:0] io_cmd_bits_cmd_status_isa, // @[LoadController.scala:18:14] input [1:0] io_cmd_bits_cmd_status_dprv, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_dv, // @[LoadController.scala:18:14] input [1:0] io_cmd_bits_cmd_status_prv, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_v, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_sd, // @[LoadController.scala:18:14] input [22:0] io_cmd_bits_cmd_status_zero2, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_mpv, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_gva, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_mbe, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_sbe, // @[LoadController.scala:18:14] input [1:0] io_cmd_bits_cmd_status_sxl, // @[LoadController.scala:18:14] input [1:0] io_cmd_bits_cmd_status_uxl, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_sd_rv32, // @[LoadController.scala:18:14] input [7:0] io_cmd_bits_cmd_status_zero1, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_tsr, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_tw, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_tvm, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_mxr, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_sum, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_mprv, // @[LoadController.scala:18:14] input [1:0] io_cmd_bits_cmd_status_xs, // @[LoadController.scala:18:14] input [1:0] io_cmd_bits_cmd_status_fs, // @[LoadController.scala:18:14] input [1:0] io_cmd_bits_cmd_status_mpp, // @[LoadController.scala:18:14] input [1:0] io_cmd_bits_cmd_status_vs, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_spp, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_mpie, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_ube, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_spie, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_upie, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_mie, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_hie, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_sie, // @[LoadController.scala:18:14] input io_cmd_bits_cmd_status_uie, // @[LoadController.scala:18:14] input [5:0] io_cmd_bits_rob_id_bits, // @[LoadController.scala:18:14] input io_cmd_bits_from_matmul_fsm, // @[LoadController.scala:18:14] input io_cmd_bits_from_conv_fsm, // @[LoadController.scala:18:14] input io_dma_req_ready, // @[LoadController.scala:18:14] output io_dma_req_valid, // @[LoadController.scala:18:14] output [39:0] io_dma_req_bits_vaddr, // @[LoadController.scala:18:14] output io_dma_req_bits_laddr_is_acc_addr, // @[LoadController.scala:18:14] output io_dma_req_bits_laddr_accumulate, // @[LoadController.scala:18:14] output io_dma_req_bits_laddr_read_full_acc_row, // @[LoadController.scala:18:14] output [2:0] io_dma_req_bits_laddr_norm_cmd, // @[LoadController.scala:18:14] output [10:0] io_dma_req_bits_laddr_garbage, // @[LoadController.scala:18:14] output io_dma_req_bits_laddr_garbage_bit, // @[LoadController.scala:18:14] output [13:0] io_dma_req_bits_laddr_data, // @[LoadController.scala:18:14] output [15:0] io_dma_req_bits_cols, // @[LoadController.scala:18:14] output [15:0] io_dma_req_bits_repeats, // @[LoadController.scala:18:14] output [31:0] io_dma_req_bits_scale, // @[LoadController.scala:18:14] output io_dma_req_bits_has_acc_bitwidth, // @[LoadController.scala:18:14] output io_dma_req_bits_all_zeros, // @[LoadController.scala:18:14] output [15:0] io_dma_req_bits_block_stride, // @[LoadController.scala:18:14] output [7:0] io_dma_req_bits_pixel_repeats, // @[LoadController.scala:18:14] output [7:0] io_dma_req_bits_cmd_id, // @[LoadController.scala:18:14] output io_dma_req_bits_status_debug, // @[LoadController.scala:18:14] output io_dma_req_bits_status_cease, // @[LoadController.scala:18:14] output io_dma_req_bits_status_wfi, // @[LoadController.scala:18:14] output [31:0] io_dma_req_bits_status_isa, // @[LoadController.scala:18:14] output [1:0] io_dma_req_bits_status_dprv, // @[LoadController.scala:18:14] output io_dma_req_bits_status_dv, // @[LoadController.scala:18:14] output [1:0] io_dma_req_bits_status_prv, // @[LoadController.scala:18:14] output io_dma_req_bits_status_v, // @[LoadController.scala:18:14] output io_dma_req_bits_status_sd, // @[LoadController.scala:18:14] output [22:0] io_dma_req_bits_status_zero2, // @[LoadController.scala:18:14] output io_dma_req_bits_status_mpv, // @[LoadController.scala:18:14] output io_dma_req_bits_status_gva, // @[LoadController.scala:18:14] output io_dma_req_bits_status_mbe, // @[LoadController.scala:18:14] output io_dma_req_bits_status_sbe, // @[LoadController.scala:18:14] output [1:0] io_dma_req_bits_status_sxl, // @[LoadController.scala:18:14] output [1:0] io_dma_req_bits_status_uxl, // @[LoadController.scala:18:14] output io_dma_req_bits_status_sd_rv32, // @[LoadController.scala:18:14] output [7:0] io_dma_req_bits_status_zero1, // @[LoadController.scala:18:14] output io_dma_req_bits_status_tsr, // @[LoadController.scala:18:14] output io_dma_req_bits_status_tw, // @[LoadController.scala:18:14] output io_dma_req_bits_status_tvm, // @[LoadController.scala:18:14] output io_dma_req_bits_status_mxr, // @[LoadController.scala:18:14] output io_dma_req_bits_status_sum, // @[LoadController.scala:18:14] output io_dma_req_bits_status_mprv, // @[LoadController.scala:18:14] output [1:0] io_dma_req_bits_status_xs, // @[LoadController.scala:18:14] output [1:0] io_dma_req_bits_status_fs, // @[LoadController.scala:18:14] output [1:0] io_dma_req_bits_status_mpp, // @[LoadController.scala:18:14] output [1:0] io_dma_req_bits_status_vs, // @[LoadController.scala:18:14] output io_dma_req_bits_status_spp, // @[LoadController.scala:18:14] output io_dma_req_bits_status_mpie, // @[LoadController.scala:18:14] output io_dma_req_bits_status_ube, // @[LoadController.scala:18:14] output io_dma_req_bits_status_spie, // @[LoadController.scala:18:14] output io_dma_req_bits_status_upie, // @[LoadController.scala:18:14] output io_dma_req_bits_status_mie, // @[LoadController.scala:18:14] output io_dma_req_bits_status_hie, // @[LoadController.scala:18:14] output io_dma_req_bits_status_sie, // @[LoadController.scala:18:14] output io_dma_req_bits_status_uie, // @[LoadController.scala:18:14] input io_dma_resp_valid, // @[LoadController.scala:18:14] input [15:0] io_dma_resp_bits_bytesRead, // @[LoadController.scala:18:14] input [7:0] io_dma_resp_bits_cmd_id, // @[LoadController.scala:18:14] input io_completed_ready, // @[LoadController.scala:18:14] output io_completed_valid, // @[LoadController.scala:18:14] output [5:0] io_completed_bits, // @[LoadController.scala:18:14] output io_busy, // @[LoadController.scala:18:14] output io_counter_event_signal_8, // @[LoadController.scala:18:14] output io_counter_event_signal_9, // @[LoadController.scala:18:14] output io_counter_event_signal_10, // @[LoadController.scala:18:14] input io_counter_external_reset // @[LoadController.scala:18:14] ); wire mvin_rs2_local_addr_garbage_bit; // @[LoadController.scala:45:43] wire [10:0] mvin_rs2_local_addr_garbage; // @[LoadController.scala:45:43] wire [2:0] mvin_rs2_local_addr_norm_cmd; // @[LoadController.scala:45:43] wire mvin_rs2_local_addr_read_full_acc_row; // @[LoadController.scala:45:43] wire mvin_rs2_local_addr_accumulate; // @[LoadController.scala:45:43] wire mvin_rs2_local_addr_is_acc_addr; // @[LoadController.scala:45:43] wire _cmd_tracker_io_alloc_ready; // @[LoadController.scala:94:27] wire [2:0] _cmd_tracker_io_alloc_bits_cmd_id; // @[LoadController.scala:94:27] wire _cmd_tracker_io_busy; // @[LoadController.scala:94:27] wire _cmd_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [6:0] _cmd_q_io_deq_bits_cmd_inst_funct; // @[Decoupled.scala:362:21] wire [63:0] _cmd_q_io_deq_bits_cmd_rs1; // @[Decoupled.scala:362:21] wire [63:0] _cmd_q_io_deq_bits_cmd_rs2; // @[Decoupled.scala:362:21] wire [5:0] _cmd_q_io_deq_bits_rob_id_bits; // @[Decoupled.scala:362:21] wire io_cmd_valid_0 = io_cmd_valid; // @[LoadController.scala:13:7] wire [6:0] io_cmd_bits_cmd_inst_funct_0 = io_cmd_bits_cmd_inst_funct; // @[LoadController.scala:13:7] wire [4:0] io_cmd_bits_cmd_inst_rs2_0 = io_cmd_bits_cmd_inst_rs2; // @[LoadController.scala:13:7] wire [4:0] io_cmd_bits_cmd_inst_rs1_0 = io_cmd_bits_cmd_inst_rs1; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_inst_xd_0 = io_cmd_bits_cmd_inst_xd; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_inst_xs1_0 = io_cmd_bits_cmd_inst_xs1; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_inst_xs2_0 = io_cmd_bits_cmd_inst_xs2; // @[LoadController.scala:13:7] wire [4:0] io_cmd_bits_cmd_inst_rd_0 = io_cmd_bits_cmd_inst_rd; // @[LoadController.scala:13:7] wire [6:0] io_cmd_bits_cmd_inst_opcode_0 = io_cmd_bits_cmd_inst_opcode; // @[LoadController.scala:13:7] wire [63:0] io_cmd_bits_cmd_rs1_0 = io_cmd_bits_cmd_rs1; // @[LoadController.scala:13:7] wire [63:0] io_cmd_bits_cmd_rs2_0 = io_cmd_bits_cmd_rs2; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_debug_0 = io_cmd_bits_cmd_status_debug; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_cease_0 = io_cmd_bits_cmd_status_cease; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_wfi_0 = io_cmd_bits_cmd_status_wfi; // @[LoadController.scala:13:7] wire [31:0] io_cmd_bits_cmd_status_isa_0 = io_cmd_bits_cmd_status_isa; // @[LoadController.scala:13:7] wire [1:0] io_cmd_bits_cmd_status_dprv_0 = io_cmd_bits_cmd_status_dprv; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_dv_0 = io_cmd_bits_cmd_status_dv; // @[LoadController.scala:13:7] wire [1:0] io_cmd_bits_cmd_status_prv_0 = io_cmd_bits_cmd_status_prv; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_v_0 = io_cmd_bits_cmd_status_v; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_sd_0 = io_cmd_bits_cmd_status_sd; // @[LoadController.scala:13:7] wire [22:0] io_cmd_bits_cmd_status_zero2_0 = io_cmd_bits_cmd_status_zero2; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_mpv_0 = io_cmd_bits_cmd_status_mpv; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_gva_0 = io_cmd_bits_cmd_status_gva; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_mbe_0 = io_cmd_bits_cmd_status_mbe; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_sbe_0 = io_cmd_bits_cmd_status_sbe; // @[LoadController.scala:13:7] wire [1:0] io_cmd_bits_cmd_status_sxl_0 = io_cmd_bits_cmd_status_sxl; // @[LoadController.scala:13:7] wire [1:0] io_cmd_bits_cmd_status_uxl_0 = io_cmd_bits_cmd_status_uxl; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_sd_rv32_0 = io_cmd_bits_cmd_status_sd_rv32; // @[LoadController.scala:13:7] wire [7:0] io_cmd_bits_cmd_status_zero1_0 = io_cmd_bits_cmd_status_zero1; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_tsr_0 = io_cmd_bits_cmd_status_tsr; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_tw_0 = io_cmd_bits_cmd_status_tw; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_tvm_0 = io_cmd_bits_cmd_status_tvm; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_mxr_0 = io_cmd_bits_cmd_status_mxr; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_sum_0 = io_cmd_bits_cmd_status_sum; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_mprv_0 = io_cmd_bits_cmd_status_mprv; // @[LoadController.scala:13:7] wire [1:0] io_cmd_bits_cmd_status_xs_0 = io_cmd_bits_cmd_status_xs; // @[LoadController.scala:13:7] wire [1:0] io_cmd_bits_cmd_status_fs_0 = io_cmd_bits_cmd_status_fs; // @[LoadController.scala:13:7] wire [1:0] io_cmd_bits_cmd_status_mpp_0 = io_cmd_bits_cmd_status_mpp; // @[LoadController.scala:13:7] wire [1:0] io_cmd_bits_cmd_status_vs_0 = io_cmd_bits_cmd_status_vs; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_spp_0 = io_cmd_bits_cmd_status_spp; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_mpie_0 = io_cmd_bits_cmd_status_mpie; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_ube_0 = io_cmd_bits_cmd_status_ube; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_spie_0 = io_cmd_bits_cmd_status_spie; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_upie_0 = io_cmd_bits_cmd_status_upie; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_mie_0 = io_cmd_bits_cmd_status_mie; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_hie_0 = io_cmd_bits_cmd_status_hie; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_sie_0 = io_cmd_bits_cmd_status_sie; // @[LoadController.scala:13:7] wire io_cmd_bits_cmd_status_uie_0 = io_cmd_bits_cmd_status_uie; // @[LoadController.scala:13:7] wire [5:0] io_cmd_bits_rob_id_bits_0 = io_cmd_bits_rob_id_bits; // @[LoadController.scala:13:7] wire io_cmd_bits_from_matmul_fsm_0 = io_cmd_bits_from_matmul_fsm; // @[LoadController.scala:13:7] wire io_cmd_bits_from_conv_fsm_0 = io_cmd_bits_from_conv_fsm; // @[LoadController.scala:13:7] wire io_dma_req_ready_0 = io_dma_req_ready; // @[LoadController.scala:13:7] wire io_dma_resp_valid_0 = io_dma_resp_valid; // @[LoadController.scala:13:7] wire [15:0] io_dma_resp_bits_bytesRead_0 = io_dma_resp_bits_bytesRead; // @[LoadController.scala:13:7] wire [7:0] io_dma_resp_bits_cmd_id_0 = io_dma_resp_bits_cmd_id; // @[LoadController.scala:13:7] wire io_completed_ready_0 = io_completed_ready; // @[LoadController.scala:13:7] wire io_counter_external_reset_0 = io_counter_external_reset; // @[LoadController.scala:13:7] wire _row_counter_T_3 = reset; // @[Util.scala:19:11] wire io_cmd_bits_rob_id_valid = 1'h1; // @[LoadController.scala:13:7] wire _row_counter_T_15 = 1'h1; // @[Util.scala:30:32] wire io_counter_event_signal_0 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_1 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_2 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_3 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_4 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_5 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_6 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_7 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_11 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_12 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_13 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_14 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_15 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_16 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_17 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_18 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_19 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_20 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_21 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_22 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_23 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_24 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_25 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_26 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_27 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_28 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_29 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_30 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_31 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_32 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_33 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_34 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_35 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_36 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_37 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_38 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_39 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_40 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_41 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_42 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_43 = 1'h0; // @[LoadController.scala:13:7] wire io_counter_event_signal_44 = 1'h0; // @[LoadController.scala:13:7] wire _row_counter_T_8 = 1'h0; // @[Util.scala:28:8] wire [31:0] io_counter_external_values_0 = 32'h0; // @[LoadController.scala:13:7] wire [31:0] io_counter_external_values_1 = 32'h0; // @[LoadController.scala:13:7] wire [31:0] io_counter_external_values_2 = 32'h0; // @[LoadController.scala:13:7] wire [31:0] io_counter_external_values_3 = 32'h0; // @[LoadController.scala:13:7] wire [31:0] io_counter_external_values_4 = 32'h0; // @[LoadController.scala:13:7] wire [31:0] io_counter_external_values_5 = 32'h0; // @[LoadController.scala:13:7] wire [31:0] io_counter_external_values_6 = 32'h0; // @[LoadController.scala:13:7] wire [31:0] io_counter_external_values_7 = 32'h0; // @[LoadController.scala:13:7] wire _io_dma_req_valid_T_9; // @[LoadController.scala:100:49] wire localaddr_plus_row_counter_is_acc_addr; // @[LocalAddr.scala:50:26] wire localaddr_plus_row_counter_accumulate; // @[LocalAddr.scala:50:26] wire localaddr_plus_row_counter_read_full_acc_row; // @[LocalAddr.scala:50:26] wire [2:0] localaddr_plus_row_counter_norm_cmd; // @[LocalAddr.scala:50:26] wire [10:0] localaddr_plus_row_counter_garbage; // @[LocalAddr.scala:50:26] wire localaddr_plus_row_counter_garbage_bit; // @[LocalAddr.scala:50:26] wire [13:0] localaddr_plus_row_counter_data; // @[LocalAddr.scala:50:26] wire _io_dma_req_bits_has_acc_bitwidth_T_1; // @[LoadController.scala:108:78] wire all_zeros; // @[LoadController.scala:72:25] wire _io_busy_T_1; // @[LoadController.scala:130:24] wire io_cmd_ready_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_laddr_is_acc_addr_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_laddr_accumulate_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_laddr_read_full_acc_row_0; // @[LoadController.scala:13:7] wire [2:0] io_dma_req_bits_laddr_norm_cmd_0; // @[LoadController.scala:13:7] wire [10:0] io_dma_req_bits_laddr_garbage_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_laddr_garbage_bit_0; // @[LoadController.scala:13:7] wire [13:0] io_dma_req_bits_laddr_data_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_debug_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_cease_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_wfi_0; // @[LoadController.scala:13:7] wire [31:0] io_dma_req_bits_status_isa_0; // @[LoadController.scala:13:7] wire [1:0] io_dma_req_bits_status_dprv_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_dv_0; // @[LoadController.scala:13:7] wire [1:0] io_dma_req_bits_status_prv_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_v_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_sd_0; // @[LoadController.scala:13:7] wire [22:0] io_dma_req_bits_status_zero2_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_mpv_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_gva_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_mbe_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_sbe_0; // @[LoadController.scala:13:7] wire [1:0] io_dma_req_bits_status_sxl_0; // @[LoadController.scala:13:7] wire [1:0] io_dma_req_bits_status_uxl_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_sd_rv32_0; // @[LoadController.scala:13:7] wire [7:0] io_dma_req_bits_status_zero1_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_tsr_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_tw_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_tvm_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_mxr_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_sum_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_mprv_0; // @[LoadController.scala:13:7] wire [1:0] io_dma_req_bits_status_xs_0; // @[LoadController.scala:13:7] wire [1:0] io_dma_req_bits_status_fs_0; // @[LoadController.scala:13:7] wire [1:0] io_dma_req_bits_status_mpp_0; // @[LoadController.scala:13:7] wire [1:0] io_dma_req_bits_status_vs_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_spp_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_mpie_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_ube_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_spie_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_upie_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_mie_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_hie_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_sie_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_status_uie_0; // @[LoadController.scala:13:7] wire [39:0] io_dma_req_bits_vaddr_0; // @[LoadController.scala:13:7] wire [15:0] io_dma_req_bits_cols_0; // @[LoadController.scala:13:7] wire [15:0] io_dma_req_bits_repeats_0; // @[LoadController.scala:13:7] wire [31:0] io_dma_req_bits_scale_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_has_acc_bitwidth_0; // @[LoadController.scala:13:7] wire io_dma_req_bits_all_zeros_0; // @[LoadController.scala:13:7] wire [15:0] io_dma_req_bits_block_stride_0; // @[LoadController.scala:13:7] wire [7:0] io_dma_req_bits_pixel_repeats_0; // @[LoadController.scala:13:7] wire [7:0] io_dma_req_bits_cmd_id_0; // @[LoadController.scala:13:7] wire io_dma_req_valid_0; // @[LoadController.scala:13:7] wire io_completed_valid_0; // @[LoadController.scala:13:7] wire [5:0] io_completed_bits_0; // @[LoadController.scala:13:7] wire io_counter_event_signal_8_0; // @[LoadController.scala:13:7] wire io_counter_event_signal_9_0; // @[LoadController.scala:13:7] wire io_counter_event_signal_10_0; // @[LoadController.scala:13:7] wire io_busy_0; // @[LoadController.scala:13:7] reg [1:0] control_state; // @[LoadController.scala:31:30] reg [39:0] strides_0; // @[LoadController.scala:33:20] reg [39:0] strides_1; // @[LoadController.scala:33:20] reg [39:0] strides_2; // @[LoadController.scala:33:20] reg [31:0] scales_0; // @[LoadController.scala:34:19] reg [31:0] scales_1; // @[LoadController.scala:34:19] reg [31:0] scales_2; // @[LoadController.scala:34:19] reg shrinks_0; // @[LoadController.scala:35:20] reg shrinks_1; // @[LoadController.scala:35:20] reg shrinks_2; // @[LoadController.scala:35:20] reg [13:0] block_strides_0; // @[LoadController.scala:36:26] reg [13:0] block_strides_1; // @[LoadController.scala:36:26] reg [13:0] block_strides_2; // @[LoadController.scala:36:26] reg [2:0] pixel_repeats_0; // @[LoadController.scala:37:26] reg [2:0] pixel_repeats_1; // @[LoadController.scala:37:26] reg [2:0] pixel_repeats_2; // @[LoadController.scala:37:26] reg [1:0] row_counter; // @[LoadController.scala:40:28] wire [12:0] _mvin_rs2_T_10; // @[LoadController.scala:45:43] wire [2:0] _mvin_rs2_T_9; // @[LoadController.scala:45:43] wire [10:0] _mvin_rs2_T_8; // @[LoadController.scala:45:43] wire [4:0] _mvin_rs2_T_7; // @[LoadController.scala:45:43] wire _mvin_rs2_T_6; // @[LoadController.scala:45:43] wire _mvin_rs2_T_5; // @[LoadController.scala:45:43] assign localaddr_plus_row_counter_is_acc_addr = mvin_rs2_local_addr_is_acc_addr; // @[LocalAddr.scala:50:26] wire _mvin_rs2_T_4; // @[LoadController.scala:45:43] assign localaddr_plus_row_counter_accumulate = mvin_rs2_local_addr_accumulate; // @[LocalAddr.scala:50:26] wire [2:0] _mvin_rs2_WIRE_2; // @[LoadController.scala:45:43] assign localaddr_plus_row_counter_read_full_acc_row = mvin_rs2_local_addr_read_full_acc_row; // @[LocalAddr.scala:50:26] wire [10:0] _mvin_rs2_T_2; // @[LoadController.scala:45:43] assign localaddr_plus_row_counter_norm_cmd = mvin_rs2_local_addr_norm_cmd; // @[LocalAddr.scala:50:26] wire _mvin_rs2_T_1; // @[LoadController.scala:45:43] assign localaddr_plus_row_counter_garbage = mvin_rs2_local_addr_garbage; // @[LocalAddr.scala:50:26] wire [13:0] _mvin_rs2_T; // @[LoadController.scala:45:43] assign localaddr_plus_row_counter_garbage_bit = mvin_rs2_local_addr_garbage_bit; // @[LocalAddr.scala:50:26] wire [13:0] mvin_rs2_local_addr_data; // @[LoadController.scala:45:43] wire [12:0] mvin_rs2__spacer2; // @[LoadController.scala:45:43] wire [2:0] mvin_rs2_num_rows; // @[LoadController.scala:45:43] wire [10:0] mvin_rs2__spacer1; // @[LoadController.scala:45:43] wire [4:0] mvin_rs2_num_cols; // @[LoadController.scala:45:43] wire [63:0] _mvin_rs2_WIRE; // @[LoadController.scala:45:43] assign _mvin_rs2_T = _mvin_rs2_WIRE[13:0]; // @[LoadController.scala:45:43] assign mvin_rs2_local_addr_data = _mvin_rs2_T; // @[LoadController.scala:45:43] assign _mvin_rs2_T_1 = _mvin_rs2_WIRE[14]; // @[LoadController.scala:45:43] assign mvin_rs2_local_addr_garbage_bit = _mvin_rs2_T_1; // @[LoadController.scala:45:43] assign _mvin_rs2_T_2 = _mvin_rs2_WIRE[25:15]; // @[LoadController.scala:45:43] assign mvin_rs2_local_addr_garbage = _mvin_rs2_T_2; // @[LoadController.scala:45:43] wire [2:0] _mvin_rs2_T_3 = _mvin_rs2_WIRE[28:26]; // @[LoadController.scala:45:43] wire [2:0] _mvin_rs2_WIRE_1 = _mvin_rs2_T_3; // @[LoadController.scala:45:43] assign _mvin_rs2_WIRE_2 = _mvin_rs2_WIRE_1; // @[LoadController.scala:45:43] assign mvin_rs2_local_addr_norm_cmd = _mvin_rs2_WIRE_2; // @[LoadController.scala:45:43] assign _mvin_rs2_T_4 = _mvin_rs2_WIRE[29]; // @[LoadController.scala:45:43] assign mvin_rs2_local_addr_read_full_acc_row = _mvin_rs2_T_4; // @[LoadController.scala:45:43] assign _mvin_rs2_T_5 = _mvin_rs2_WIRE[30]; // @[LoadController.scala:45:43] assign mvin_rs2_local_addr_accumulate = _mvin_rs2_T_5; // @[LoadController.scala:45:43] assign _mvin_rs2_T_6 = _mvin_rs2_WIRE[31]; // @[LoadController.scala:45:43] assign mvin_rs2_local_addr_is_acc_addr = _mvin_rs2_T_6; // @[LoadController.scala:45:43] assign _mvin_rs2_T_7 = _mvin_rs2_WIRE[36:32]; // @[LoadController.scala:45:43] assign mvin_rs2_num_cols = _mvin_rs2_T_7; // @[LoadController.scala:45:43] assign _mvin_rs2_T_8 = _mvin_rs2_WIRE[47:37]; // @[LoadController.scala:45:43] assign mvin_rs2__spacer1 = _mvin_rs2_T_8; // @[LoadController.scala:45:43] assign _mvin_rs2_T_9 = _mvin_rs2_WIRE[50:48]; // @[LoadController.scala:45:43] assign mvin_rs2_num_rows = _mvin_rs2_T_9; // @[LoadController.scala:45:43] assign _mvin_rs2_T_10 = _mvin_rs2_WIRE[63:51]; // @[LoadController.scala:45:43] assign mvin_rs2__spacer2 = _mvin_rs2_T_10; // @[LoadController.scala:45:43] wire [31:0] _config_mvin_rs1_T_8; // @[LoadController.scala:52:50] wire [1:0] _config_mvin_rs1_T_7; // @[LoadController.scala:52:50] wire [13:0] _config_mvin_rs1_T_6; // @[LoadController.scala:52:50] wire [4:0] _config_mvin_rs1_T_5; // @[LoadController.scala:52:50] wire [2:0] _config_mvin_rs1_T_4; // @[LoadController.scala:52:50] wire [2:0] _config_mvin_rs1_T_3; // @[LoadController.scala:52:50] wire [1:0] _config_mvin_rs1_T_2; // @[LoadController.scala:52:50] wire _config_mvin_rs1_T_1; // @[LoadController.scala:52:50] wire [1:0] _config_mvin_rs1_T; // @[LoadController.scala:52:50] wire [31:0] config_mvin_rs1_scale; // @[LoadController.scala:52:50] wire [1:0] config_mvin_rs1__spacer2; // @[LoadController.scala:52:50] wire [13:0] config_mvin_rs1_stride; // @[LoadController.scala:52:50] wire [4:0] config_mvin_rs1__spacer1; // @[LoadController.scala:52:50] wire [2:0] config_mvin_rs1_pixel_repeats; // @[LoadController.scala:52:50] wire [2:0] config_mvin_rs1__spacer0; // @[LoadController.scala:52:50] wire [1:0] config_mvin_rs1_state_id; // @[LoadController.scala:52:50] wire config_mvin_rs1_shrink; // @[LoadController.scala:52:50] wire [1:0] config_mvin_rs1__unused; // @[LoadController.scala:52:50] wire [63:0] _config_mvin_rs1_WIRE; // @[LoadController.scala:52:50] assign _config_mvin_rs1_T = _config_mvin_rs1_WIRE[1:0]; // @[LoadController.scala:52:50] assign config_mvin_rs1__unused = _config_mvin_rs1_T; // @[LoadController.scala:52:50] assign _config_mvin_rs1_T_1 = _config_mvin_rs1_WIRE[2]; // @[LoadController.scala:52:50] assign config_mvin_rs1_shrink = _config_mvin_rs1_T_1; // @[LoadController.scala:52:50] assign _config_mvin_rs1_T_2 = _config_mvin_rs1_WIRE[4:3]; // @[LoadController.scala:52:50] assign config_mvin_rs1_state_id = _config_mvin_rs1_T_2; // @[LoadController.scala:52:50] assign _config_mvin_rs1_T_3 = _config_mvin_rs1_WIRE[7:5]; // @[LoadController.scala:52:50] assign config_mvin_rs1__spacer0 = _config_mvin_rs1_T_3; // @[LoadController.scala:52:50] assign _config_mvin_rs1_T_4 = _config_mvin_rs1_WIRE[10:8]; // @[LoadController.scala:52:50] assign config_mvin_rs1_pixel_repeats = _config_mvin_rs1_T_4; // @[LoadController.scala:52:50] assign _config_mvin_rs1_T_5 = _config_mvin_rs1_WIRE[15:11]; // @[LoadController.scala:52:50] assign config_mvin_rs1__spacer1 = _config_mvin_rs1_T_5; // @[LoadController.scala:52:50] assign _config_mvin_rs1_T_6 = _config_mvin_rs1_WIRE[29:16]; // @[LoadController.scala:52:50] assign config_mvin_rs1_stride = _config_mvin_rs1_T_6; // @[LoadController.scala:52:50] assign _config_mvin_rs1_T_7 = _config_mvin_rs1_WIRE[31:30]; // @[LoadController.scala:52:50] assign config_mvin_rs1__spacer2 = _config_mvin_rs1_T_7; // @[LoadController.scala:52:50] assign _config_mvin_rs1_T_8 = _config_mvin_rs1_WIRE[63:32]; // @[LoadController.scala:52:50] assign config_mvin_rs1_scale = _config_mvin_rs1_T_8; // @[LoadController.scala:52:50] wire _load_state_id_T = _cmd_q_io_deq_bits_cmd_inst_funct == 7'h1; // @[Decoupled.scala:362:21] wire _load_state_id_T_1 = _cmd_q_io_deq_bits_cmd_inst_funct == 7'hE; // @[Decoupled.scala:362:21] wire [1:0] _load_state_id_T_2 = {_load_state_id_T_1, 1'h0}; // @[Mux.scala:126:16] wire [1:0] load_state_id = _load_state_id_T ? 2'h1 : _load_state_id_T_2; // @[Mux.scala:126:16] wire _GEN = _cmd_q_io_deq_bits_cmd_inst_funct == 7'h0; // @[Decoupled.scala:362:21] wire _state_id_T; // @[LoadController.scala:64:46] assign _state_id_T = _GEN; // @[LoadController.scala:64:46] wire DoConfig; // @[LoadController.scala:78:42] assign DoConfig = _GEN; // @[LoadController.scala:64:46, :78:42] wire [1:0] state_id = _state_id_T ? config_mvin_rs1_state_id : load_state_id; // @[Mux.scala:126:16] assign all_zeros = _cmd_q_io_deq_bits_cmd_rs1 == 64'h0; // @[Decoupled.scala:362:21] assign io_dma_req_bits_all_zeros_0 = all_zeros; // @[LoadController.scala:13:7, :72:25] assign io_dma_req_bits_laddr_is_acc_addr_0 = localaddr_plus_row_counter_is_acc_addr; // @[LocalAddr.scala:50:26] assign io_dma_req_bits_laddr_accumulate_0 = localaddr_plus_row_counter_accumulate; // @[LocalAddr.scala:50:26] assign io_dma_req_bits_laddr_read_full_acc_row_0 = localaddr_plus_row_counter_read_full_acc_row; // @[LocalAddr.scala:50:26] assign io_dma_req_bits_laddr_norm_cmd_0 = localaddr_plus_row_counter_norm_cmd; // @[LocalAddr.scala:50:26] assign io_dma_req_bits_laddr_garbage_0 = localaddr_plus_row_counter_garbage; // @[LocalAddr.scala:50:26] assign io_dma_req_bits_laddr_garbage_bit_0 = localaddr_plus_row_counter_garbage_bit; // @[LocalAddr.scala:50:26] wire [13:0] _localaddr_plus_row_counter_result_data_T_1; // @[LocalAddr.scala:51:25] assign io_dma_req_bits_laddr_data_0 = localaddr_plus_row_counter_data; // @[LocalAddr.scala:50:26] wire [14:0] _localaddr_plus_row_counter_result_data_T = {1'h0, mvin_rs2_local_addr_data} + {13'h0, row_counter}; // @[LocalAddr.scala:51:25] assign _localaddr_plus_row_counter_result_data_T_1 = _localaddr_plus_row_counter_result_data_T[13:0]; // @[LocalAddr.scala:51:25] assign localaddr_plus_row_counter_data = _localaddr_plus_row_counter_result_data_T_1; // @[LocalAddr.scala:50:26, :51:25] wire [3:0][39:0] _GEN_0 = {{strides_0}, {strides_2}, {strides_1}, {strides_0}}; // @[LoadController.scala:33:20, :76:37] wire _GEN_1 = _GEN_0[state_id] == 40'h0; // @[LoadController.scala:64:21, :76:37] wire _actual_rows_read_T; // @[LoadController.scala:76:37] assign _actual_rows_read_T = _GEN_1; // @[LoadController.scala:76:37] wire _io_dma_req_bits_repeats_T; // @[LoadController.scala:105:41] assign _io_dma_req_bits_repeats_T = _GEN_1; // @[LoadController.scala:76:37, :105:41] wire _actual_rows_read_T_1 = ~all_zeros; // @[LoadController.scala:72:25, :76:48] wire _actual_rows_read_T_2 = _actual_rows_read_T & _actual_rows_read_T_1; // @[LoadController.scala:76:{37,45,48}] wire [2:0] actual_rows_read = _actual_rows_read_T_2 ? 3'h1 : mvin_rs2_num_rows; // @[LoadController.scala:45:43, :76:{29,45}] wire DoLoad = ~DoConfig; // @[LoadController.scala:78:42, :79:16] wire _GEN_2 = _cmd_q_io_deq_valid \| _cmd_tracker_io_busy; // @[Decoupled.scala:362:21] wire _io_busy_T; // @[LoadController.scala:96:24] assign _io_busy_T = _GEN_2; // @[LoadController.scala:96:24] assign _io_busy_T_1 = _GEN_2; // @[LoadController.scala:96:24, :130:24] wire _T_5 = control_state == 2'h0; // @[LoadController.scala:31:30, :99:38] wire _io_dma_req_valid_T; // @[LoadController.scala:99:38] assign _io_dma_req_valid_T = _T_5; // @[LoadController.scala:99:38] wire _cmd_tracker_io_alloc_valid_T; // @[LoadController.scala:114:47] assign _cmd_tracker_io_alloc_valid_T = _T_5; // @[LoadController.scala:99:38, :114:47] wire _io_dma_req_valid_T_1 = _io_dma_req_valid_T & _cmd_q_io_deq_valid; // @[Decoupled.scala:362:21] wire _io_dma_req_valid_T_2 = _io_dma_req_valid_T_1 & DoLoad; // @[LoadController.scala:79:16, :99:{62,75}] wire _io_dma_req_valid_T_3 = _io_dma_req_valid_T_2 & _cmd_tracker_io_alloc_ready; // @[LoadController.scala:94:27, :99:{75,85}] wire _T_12 = control_state == 2'h1; // @[LoadController.scala:31:30, :100:19] assign io_counter_event_signal_8_0 = _T_12; // @[LoadController.scala:13:7, :100:19] wire _io_dma_req_valid_T_4; // @[LoadController.scala:100:19] assign _io_dma_req_valid_T_4 = _T_12; // @[LoadController.scala:100:19] wire _io_dma_req_valid_T_5 = _io_dma_req_valid_T_3 \| _io_dma_req_valid_T_4; // @[LoadController.scala:99:{85,116}, :100:19] wire _T_11 = control_state == 2'h2; // @[LoadController.scala:31:30, :101:20] assign io_counter_event_signal_9_0 = _T_11; // @[LoadController.scala:13:7, :101:20] wire _io_dma_req_valid_T_6; // @[LoadController.scala:101:20] assign _io_dma_req_valid_T_6 = _T_11; // @[LoadController.scala:101:20] wire _io_dma_req_valid_T_7 = \|row_counter; // @[LoadController.scala:40:28, :101:52] wire _io_dma_req_valid_T_8 = _io_dma_req_valid_T_6 & _io_dma_req_valid_T_7; // @[LoadController.scala:101:{20,37,52}] assign _io_dma_req_valid_T_9 = _io_dma_req_valid_T_5 \| _io_dma_req_valid_T_8; // @[LoadController.scala:99:116, :100:49, :101:37] assign io_dma_req_valid_0 = _io_dma_req_valid_T_9; // @[LoadController.scala:13:7, :100:49] wire [41:0] _io_dma_req_bits_vaddr_T = {40'h0, row_counter} * {2'h0, _GEN_0[state_id]}; // @[LoadController.scala:40:28, :64:21, :76:37, :102:48] wire [64:0] _io_dma_req_bits_vaddr_T_1 = {1'h0, _cmd_q_io_deq_bits_cmd_rs1} + {23'h0, _io_dma_req_bits_vaddr_T}; // @[Decoupled.scala:362:21] wire [63:0] _io_dma_req_bits_vaddr_T_2 = _io_dma_req_bits_vaddr_T_1[63:0]; // @[LoadController.scala:102:34] assign io_dma_req_bits_vaddr_0 = _io_dma_req_bits_vaddr_T_2[39:0]; // @[LoadController.scala:13:7, :102:{25,34}] assign io_dma_req_bits_cols_0 = {11'h0, mvin_rs2_num_cols}; // @[LoadController.scala:13:7, :45:43, :104:24] wire _io_dma_req_bits_repeats_T_1 = ~all_zeros; // @[LoadController.scala:72:25, :76:48, :105:52] wire _io_dma_req_bits_repeats_T_2 = _io_dma_req_bits_repeats_T & _io_dma_req_bits_repeats_T_1; // @[LoadController.scala:105:{41,49,52}] wire [3:0] _io_dma_req_bits_repeats_T_3 = {1'h0, mvin_rs2_num_rows} - 4'h1; // @[LoadController.scala:45:43, :105:69] wire [2:0] _io_dma_req_bits_repeats_T_4 = _io_dma_req_bits_repeats_T_3[2:0]; // @[LoadController.scala:105:69] wire [2:0] _io_dma_req_bits_repeats_T_5 = _io_dma_req_bits_repeats_T_2 ? _io_dma_req_bits_repeats_T_4 : 3'h0; // @[LoadController.scala:105:{33,49,69}] assign io_dma_req_bits_repeats_0 = {13'h0, _io_dma_req_bits_repeats_T_5}; // @[LoadController.scala:13:7, :105:{27,33}] wire [3:0][13:0] _GEN_3 = {{block_strides_0}, {block_strides_2}, {block_strides_1}, {block_strides_0}}; // @[LoadController.scala:36:26, :106:32] assign io_dma_req_bits_block_stride_0 = {2'h0, _GEN_3[state_id]}; // @[LoadController.scala:13:7, :64:21, :106:32] wire [3:0][31:0] _GEN_4 = {{scales_0}, {scales_2}, {scales_1}, {scales_0}}; // @[LoadController.scala:34:19, :107:25] assign io_dma_req_bits_scale_0 = _GEN_4[state_id]; // @[LoadController.scala:13:7, :64:21, :107:25] wire [3:0] _GEN_5 = {{shrinks_0}, {shrinks_2}, {shrinks_1}, {shrinks_0}}; // @[LoadController.scala:35:20, :108:81] wire _io_dma_req_bits_has_acc_bitwidth_T = ~_GEN_5[state_id]; // @[LoadController.scala:64:21, :108:81] assign _io_dma_req_bits_has_acc_bitwidth_T_1 = localaddr_plus_row_counter_is_acc_addr & _io_dma_req_bits_has_acc_bitwidth_T; // @[LocalAddr.scala:50:26] assign io_dma_req_bits_has_acc_bitwidth_0 = _io_dma_req_bits_has_acc_bitwidth_T_1; // @[LoadController.scala:13:7, :108:78] wire [3:0][2:0] _GEN_6 = {{pixel_repeats_0}, {pixel_repeats_2}, {pixel_repeats_1}, {pixel_repeats_0}}; // @[LoadController.scala:37:26, :111:33] assign io_dma_req_bits_pixel_repeats_0 = {5'h0, _GEN_6[state_id]}; // @[LoadController.scala:13:7, :64:21, :111:33] wire _cmd_tracker_io_alloc_valid_T_1 = _cmd_tracker_io_alloc_valid_T & _cmd_q_io_deq_valid; // @[Decoupled.scala:362:21] wire _cmd_tracker_io_alloc_valid_T_2 = _cmd_tracker_io_alloc_valid_T_1 & DoLoad; // @[LoadController.scala:79:16, :114:{71,84}] wire [7:0] _GEN_7 = {3'h0, mvin_rs2_num_cols} * {5'h0, actual_rows_read}; // @[LoadController.scala:45:43, :76:29, :116:48] wire [7:0] _cmd_tracker_io_alloc_bits_bytes_to_read_T; // @[LoadController.scala:116:48] assign _cmd_tracker_io_alloc_bits_bytes_to_read_T = _GEN_7; // @[LoadController.scala:116:48] wire [7:0] _cmd_tracker_io_alloc_bits_bytes_to_read_T_2; // @[LoadController.scala:117:12] assign _cmd_tracker_io_alloc_bits_bytes_to_read_T_2 = _GEN_7; // @[LoadController.scala:116:48, :117:12] wire [13:0] _cmd_tracker_io_alloc_bits_bytes_to_read_T_1 = {1'h0, _cmd_tracker_io_alloc_bits_bytes_to_read_T, 5'h0}; // @[LoadController.scala:116:{48,67}] wire [13:0] _cmd_tracker_io_alloc_bits_bytes_to_read_T_3 = {1'h0, _cmd_tracker_io_alloc_bits_bytes_to_read_T_2, 5'h0}; // @[LoadController.scala:117:{12,31}] wire [13:0] _cmd_tracker_io_alloc_bits_bytes_to_read_T_4 = io_dma_req_bits_has_acc_bitwidth_0 ? _cmd_tracker_io_alloc_bits_bytes_to_read_T_1 : _cmd_tracker_io_alloc_bits_bytes_to_read_T_3; // @[LoadController.scala:13:7, :116:{8,67}, :117:31] wire [10:0] _cmd_tracker_io_alloc_bits_bytes_to_read_T_5 = _cmd_tracker_io_alloc_bits_bytes_to_read_T_4[13:3]; // @[LoadController.scala:116:8, :117:62] wire _cmd_id_T = _cmd_tracker_io_alloc_valid_T_2 & _cmd_tracker_io_alloc_ready; // @[LoadController.scala:94:27, :114:84] reg [2:0] cmd_id_buf; // @[Util.scala:90:24] wire [2:0] cmd_id = _cmd_id_T ? _cmd_tracker_io_alloc_bits_cmd_id : cmd_id_buf; // @[Util.scala:90:24, :91:8] assign io_dma_req_bits_cmd_id_0 = {5'h0, cmd_id}; // @[Util.scala:91:8] assign io_busy_0 = _io_busy_T_1; // @[LoadController.scala:13:7, :130:24] wire _T_9 = io_dma_req_ready_0 & io_dma_req_valid_0; // @[Decoupled.scala:51:35] wire _control_state_T; // @[Decoupled.scala:51:35] assign _control_state_T = _T_9; // @[Decoupled.scala:51:35] wire _last_row_T_4; // @[Decoupled.scala:51:35] assign _last_row_T_4 = _T_9; // @[Decoupled.scala:51:35] wire [3:0] _GEN_8 = {1'h0, actual_rows_read} - 4'h1; // @[Util.scala:18:28] wire [3:0] _row_counter_max_T; // @[Util.scala:18:28] assign _row_counter_max_T = _GEN_8; // @[Util.scala:18:28] wire [3:0] _last_row_T_1; // @[LoadController.scala:165:78] assign _last_row_T_1 = _GEN_8; // @[Util.scala:18:28] wire [2:0] row_counter_max = _row_counter_max_T[2:0]; // @[Util.scala:18:28] wire _row_counter_T = \|row_counter_max; // @[Util.scala:18:28, :19:14] wire _GEN_9 = row_counter_max == 3'h0; // @[Util.scala:18:28, :19:28] wire _row_counter_T_1; // @[Util.scala:19:28] assign _row_counter_T_1 = _GEN_9; // @[Util.scala:19:28] wire _row_counter_T_9; // @[Util.scala:29:12] assign _row_counter_T_9 = _GEN_9; // @[Util.scala:19:28, :29:12] wire _row_counter_T_2 = _row_counter_T \| _row_counter_T_1; // @[Util.scala:19:{14,21,28}] wire _row_counter_T_4 = ~_row_counter_T_3; // @[Util.scala:19:11] wire _row_counter_T_5 = ~_row_counter_T_2; // @[Util.scala:19:{11,21}] wire [2:0] _GEN_10 = {1'h0, row_counter}; // @[Util.scala:27:15] wire [2:0] _row_counter_T_6 = _GEN_10 + 3'h1; // @[Util.scala:27:15] wire [1:0] _row_counter_T_7 = _row_counter_T_6[1:0]; // @[Util.scala:27:15] wire [3:0] _GEN_11 = {1'h0, row_counter_max}; // @[Util.scala:18:28, :30:17] wire [3:0] _row_counter_T_10 = _GEN_11 - 4'h1; // @[Util.scala:30:17] wire [2:0] _row_counter_T_11 = _row_counter_T_10[2:0]; // @[Util.scala:30:17] wire [3:0] _row_counter_T_12 = {1'h0, _row_counter_T_11} + 4'h1; // @[Util.scala:30:{17,21}] wire [2:0] _row_counter_T_13 = _row_counter_T_12[2:0]; // @[Util.scala:30:21] wire _row_counter_T_14 = _GEN_10 >= _row_counter_T_13; // @[Util.scala:27:15, :30:{10,21}] wire _row_counter_T_16 = _row_counter_T_14; // @[Util.scala:30:{10,27}] wire [3:0] _row_counter_T_17 = _GEN_11 - {2'h0, row_counter}; // @[Util.scala:30:{17,54}] wire [2:0] _row_counter_T_18 = _row_counter_T_17[2:0]; // @[Util.scala:30:54] wire [3:0] _row_counter_T_19 = 4'h1 - {1'h0, _row_counter_T_18}; // @[Util.scala:30:{47,54}] wire [2:0] _row_counter_T_20 = _row_counter_T_19[2:0]; // @[Util.scala:30:47] wire [3:0] _row_counter_T_21 = {1'h0, _row_counter_T_20} - 4'h1; // @[Util.scala:30:{47,59}] wire [2:0] _row_counter_T_22 = _row_counter_T_21[2:0]; // @[Util.scala:30:59] wire [2:0] _row_counter_T_23 = _row_counter_T_16 ? _row_counter_T_22 : {1'h0, _row_counter_T_7}; // @[Mux.scala:126:16] wire [2:0] _row_counter_T_24 = _row_counter_T_9 ? 3'h0 : _row_counter_T_23; // @[Mux.scala:126:16] wire [2:0] _row_counter_T_25 = _row_counter_T_24; // @[Mux.scala:126:16] wire _pixel_repeats_T = config_mvin_rs1_pixel_repeats == 3'h0; // @[LoadController.scala:52:50, :148:52] wire [2:0] _pixel_repeats_T_1 = _pixel_repeats_T ? 3'h1 : config_mvin_rs1_pixel_repeats; // @[LoadController.scala:52:50, :148:{30,52}] wire [1:0] _control_state_T_1 = _control_state_T ? 2'h2 : 2'h1; // @[Decoupled.scala:51:35] wire _last_row_T = ~(\|row_counter); // @[LoadController.scala:40:28, :101:52, :165:34] wire [2:0] _last_row_T_2 = _last_row_T_1[2:0]; // @[LoadController.scala:165:78] wire _last_row_T_3 = _GEN_10 == _last_row_T_2; // @[Util.scala:27:15] wire _last_row_T_5 = _last_row_T_3 & _last_row_T_4; // @[Decoupled.scala:51:35] wire last_row = _last_row_T \| _last_row_T_5; // @[LoadController.scala:165:{34,42,83}] assign io_counter_event_signal_10_0 = io_dma_req_valid_0 & ~io_dma_req_ready_0; // @[LoadController.scala:13:7, :182:{91,94}]
Generate the Verilog code corresponding to the following Chisel files. File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relListscache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_\|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x \| 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ \|\| _) (matches, bits.U) } expanded \| Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) \|\| (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) \|\| ((opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm \|\| opcode === TLMessages.Get \|\| (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN \|\| param === TLPermissions.BtoN \|\| param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB \|\| param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle File SourceC.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink._ class SourceCRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val opcode = UInt(3.W) val param = UInt(3.W) val source = UInt(params.outer.bundle.sourceBits.W) val tag = UInt(params.tagBits.W) val set = UInt(params.setBits.W) val way = UInt(params.wayBits.W) val dirty = Bool() } class SourceC(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val req = Flipped(Decoupled(new SourceCRequest(params))) val c = Decoupled(new TLBundleC(params.outer.bundle)) // BankedStore port val bs_adr = Decoupled(new BankedStoreOuterAddress(params)) val bs_dat = Flipped(new BankedStoreOuterDecoded(params)) // RaW hazard val evict_req = new SourceDHazard(params) val evict_safe = Flipped(Bool()) }) // We ignore the depth and pipe is useless here (we have to provision for worst-case=stall) require (!params.micro.outerBuf.c.pipe) val beatBytes = params.outer.manager.beatBytes val beats = params.cache.blockBytes / beatBytes val flow = params.micro.outerBuf.c.flow val queue = Module(new Queue(chiselTypeOf(io.c.bits), beats + 3 + (if (flow) 0 else 1), flow = flow)) // queue.io.count is far too slow val fillBits = log2Up(beats + 4) val fill = RegInit(0.U(fillBits.W)) val room = RegInit(true.B) when (queue.io.enq.fire =/= queue.io.deq.fire) { fill := fill + Mux(queue.io.enq.fire, 1.U, ~0.U(fillBits.W)) room := fill === 0.U \|\| ((fill === 1.U \|\| fill === 2.U) && !queue.io.enq.fire) } assert (room === queue.io.count <= 1.U) val busy = RegInit(false.B) val beat = RegInit(0.U(params.outerBeatBits.W)) val last = if (params.cache.blockBytes == params.outer.manager.beatBytes) true.B else (beat === ~(0.U(params.outerBeatBits.W))) val req = Mux(!busy, io.req.bits, RegEnable(io.req.bits, !busy && io.req.valid)) val want_data = busy \|\| (io.req.valid && room && io.req.bits.dirty) io.req.ready := !busy && room io.evict_req.set := req.set io.evict_req.way := req.way io.bs_adr.valid := (beat.orR \|\| io.evict_safe) && want_data io.bs_adr.bits.noop := false.B io.bs_adr.bits.way := req.way io.bs_adr.bits.set := req.set io.bs_adr.bits.beat := beat io.bs_adr.bits.mask := ~0.U(params.outerMaskBits.W) params.ccover(io.req.valid && io.req.bits.dirty && room && !io.evict_safe, "SOURCEC_HAZARD", "Prevented Eviction data hazard with backpressure") params.ccover(io.bs_adr.valid && !io.bs_adr.ready, "SOURCEC_SRAM_STALL", "Data SRAM busy") when (io.req.valid && room && io.req.bits.dirty) { busy := true.B } when (io.bs_adr.fire) { beat := beat + 1.U when (last) { busy := false.B beat := 0.U } } val s2_latch = Mux(want_data, io.bs_adr.fire, io.req.fire) val s2_valid = RegNext(s2_latch) val s2_req = RegEnable(req, s2_latch) val s2_beat = RegEnable(beat, s2_latch) val s2_last = RegEnable(last, s2_latch) val s3_latch = s2_valid val s3_valid = RegNext(s3_latch) val s3_req = RegEnable(s2_req, s3_latch) val s3_beat = RegEnable(s2_beat, s3_latch) val s3_last = RegEnable(s2_last, s3_latch) val c = Wire(chiselTypeOf(io.c)) c.valid := s3_valid c.bits.opcode := s3_req.opcode c.bits.param := s3_req.param c.bits.size := params.offsetBits.U c.bits.source := s3_req.source c.bits.address := params.expandAddress(s3_req.tag, s3_req.set, 0.U) c.bits.data := io.bs_dat.data c.bits.corrupt := false.B // We never accept at the front-end unless we're sure things will fit assert(!c.valid \|\| c.ready) params.ccover(!c.ready, "SOURCEC_QUEUE_FULL", "Eviction queue fully utilized") queue.io.enq <> c io.c <> queue.io.deq }	module SourceC( // @[SourceC.scala:35:7] input clock, // @[SourceC.scala:35:7] input reset, // @[SourceC.scala:35:7] output io_req_ready, // @[SourceC.scala:37:14] input io_req_valid, // @[SourceC.scala:37:14] input [2:0] io_req_bits_opcode, // @[SourceC.scala:37:14] input [2:0] io_req_bits_param, // @[SourceC.scala:37:14] input [4:0] io_req_bits_source, // @[SourceC.scala:37:14] input [12:0] io_req_bits_tag, // @[SourceC.scala:37:14] input [9:0] io_req_bits_set, // @[SourceC.scala:37:14] input [2:0] io_req_bits_way, // @[SourceC.scala:37:14] input io_req_bits_dirty, // @[SourceC.scala:37:14] input io_c_ready, // @[SourceC.scala:37:14] output io_c_valid, // @[SourceC.scala:37:14] output [2:0] io_c_bits_opcode, // @[SourceC.scala:37:14] output [2:0] io_c_bits_param, // @[SourceC.scala:37:14] output [2:0] io_c_bits_size, // @[SourceC.scala:37:14] output [4:0] io_c_bits_source, // @[SourceC.scala:37:14] output [31:0] io_c_bits_address, // @[SourceC.scala:37:14] output [63:0] io_c_bits_data, // @[SourceC.scala:37:14] output io_c_bits_corrupt, // @[SourceC.scala:37:14] input io_bs_adr_ready, // @[SourceC.scala:37:14] output io_bs_adr_valid, // @[SourceC.scala:37:14] output [2:0] io_bs_adr_bits_way, // @[SourceC.scala:37:14] output [9:0] io_bs_adr_bits_set, // @[SourceC.scala:37:14] output [2:0] io_bs_adr_bits_beat, // @[SourceC.scala:37:14] input [63:0] io_bs_dat_data, // @[SourceC.scala:37:14] output [9:0] io_evict_req_set, // @[SourceC.scala:37:14] output [2:0] io_evict_req_way, // @[SourceC.scala:37:14] input io_evict_safe // @[SourceC.scala:37:14] ); wire _queue_io_enq_ready; // @[SourceC.scala:54:21] wire _queue_io_deq_valid; // @[SourceC.scala:54:21] wire [3:0] _queue_io_count; // @[SourceC.scala:54:21] wire io_req_valid_0 = io_req_valid; // @[SourceC.scala:35:7] wire [2:0] io_req_bits_opcode_0 = io_req_bits_opcode; // @[SourceC.scala:35:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceC.scala:35:7] wire [4:0] io_req_bits_source_0 = io_req_bits_source; // @[SourceC.scala:35:7] wire [12:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceC.scala:35:7] wire [9:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceC.scala:35:7] wire [2:0] io_req_bits_way_0 = io_req_bits_way; // @[SourceC.scala:35:7] wire io_req_bits_dirty_0 = io_req_bits_dirty; // @[SourceC.scala:35:7] wire io_c_ready_0 = io_c_ready; // @[SourceC.scala:35:7] wire io_bs_adr_ready_0 = io_bs_adr_ready; // @[SourceC.scala:35:7] wire [63:0] io_bs_dat_data_0 = io_bs_dat_data; // @[SourceC.scala:35:7] wire io_evict_safe_0 = io_evict_safe; // @[SourceC.scala:35:7] wire _c_bits_address_base_T_2 = reset; // @[Parameters.scala:222:12] wire _c_bits_address_base_T_8 = reset; // @[Parameters.scala:222:12] wire _c_bits_address_base_T_14 = reset; // @[Parameters.scala:222:12] wire io_bs_adr_bits_noop = 1'h0; // @[SourceC.scala:35:7] wire c_bits_corrupt = 1'h0; // @[SourceC.scala:108:15] wire _c_bits_address_base_T = 1'h0; // @[Parameters.scala:222:15] wire _c_bits_address_base_T_4 = 1'h0; // @[Parameters.scala:222:12] wire _c_bits_address_base_T_6 = 1'h0; // @[Parameters.scala:222:15] wire _c_bits_address_base_T_10 = 1'h0; // @[Parameters.scala:222:12] wire _c_bits_address_base_T_12 = 1'h0; // @[Parameters.scala:222:15] wire _c_bits_address_base_T_16 = 1'h0; // @[Parameters.scala:222:12] wire io_bs_adr_bits_mask = 1'h1; // @[SourceC.scala:35:7] wire _io_bs_adr_bits_mask_T = 1'h1; // @[SourceC.scala:82:26] wire _c_bits_address_base_T_1 = 1'h1; // @[Parameters.scala:222:24] wire _c_bits_address_base_T_7 = 1'h1; // @[Parameters.scala:222:24] wire _c_bits_address_base_T_13 = 1'h1; // @[Parameters.scala:222:24] wire [1:0] c_bits_address_hi_hi_hi_lo = 2'h0; // @[Parameters.scala:230:8] wire [5:0] c_bits_address_base_y_2 = 6'h0; // @[Parameters.scala:221:15] wire [5:0] _c_bits_address_base_T_17 = 6'h0; // @[Parameters.scala:223:6] wire [2:0] c_bits_size = 3'h6; // @[SourceC.scala:108:15] wire [2:0] _last_T = 3'h7; // @[SourceC.scala:68:99] wire [3:0] _fill_T_1 = 4'hF; // @[SourceC.scala:61:48] wire _io_req_ready_T_1; // @[SourceC.scala:72:25] wire _io_bs_adr_valid_T_2; // @[SourceC.scala:77:50] wire [2:0] req_way; // @[SourceC.scala:69:17] wire [9:0] req_set; // @[SourceC.scala:69:17] wire [63:0] c_bits_data = io_bs_dat_data_0; // @[SourceC.scala:35:7, :108:15] wire io_req_ready_0; // @[SourceC.scala:35:7] wire [2:0] io_c_bits_opcode_0; // @[SourceC.scala:35:7] wire [2:0] io_c_bits_param_0; // @[SourceC.scala:35:7] wire [2:0] io_c_bits_size_0; // @[SourceC.scala:35:7] wire [4:0] io_c_bits_source_0; // @[SourceC.scala:35:7] wire [31:0] io_c_bits_address_0; // @[SourceC.scala:35:7] wire [63:0] io_c_bits_data_0; // @[SourceC.scala:35:7] wire io_c_bits_corrupt_0; // @[SourceC.scala:35:7] wire io_c_valid_0; // @[SourceC.scala:35:7] wire [2:0] io_bs_adr_bits_way_0; // @[SourceC.scala:35:7] wire [9:0] io_bs_adr_bits_set_0; // @[SourceC.scala:35:7] wire [2:0] io_bs_adr_bits_beat_0; // @[SourceC.scala:35:7] wire io_bs_adr_valid_0; // @[SourceC.scala:35:7] wire [9:0] io_evict_req_set_0; // @[SourceC.scala:35:7] wire [2:0] io_evict_req_way_0; // @[SourceC.scala:35:7] reg [3:0] fill; // @[SourceC.scala:58:21] reg room; // @[SourceC.scala:59:21] wire c_valid; // @[SourceC.scala:108:15] wire _T = _queue_io_enq_ready & c_valid; // @[Decoupled.scala:51:35] wire _fill_T; // @[Decoupled.scala:51:35] assign _fill_T = _T; // @[Decoupled.scala:51:35] wire _room_T_4; // @[Decoupled.scala:51:35] assign _room_T_4 = _T; // @[Decoupled.scala:51:35] wire [3:0] _fill_T_2 = _fill_T ? 4'h1 : 4'hF; // @[Decoupled.scala:51:35] wire [4:0] _fill_T_3 = {1'h0, fill} + {1'h0, _fill_T_2}; // @[SourceC.scala:58:21, :61:{18,23}] wire [3:0] _fill_T_4 = _fill_T_3[3:0]; // @[SourceC.scala:61:18] wire _room_T = fill == 4'h0; // @[SourceC.scala:58:21, :62:18] wire _room_T_1 = fill == 4'h1; // @[SourceC.scala:58:21, :62:36] wire _room_T_2 = fill == 4'h2; // @[SourceC.scala:58:21, :62:52] wire _room_T_3 = _room_T_1 \| _room_T_2; // @[SourceC.scala:62:{36,44,52}] wire _room_T_5 = ~_room_T_4; // @[Decoupled.scala:51:35] wire _room_T_6 = _room_T_3 & _room_T_5; // @[SourceC.scala:62:{44,61,64}] wire _room_T_7 = _room_T \| _room_T_6; // @[SourceC.scala:62:{18,26,61}] reg busy; // @[SourceC.scala:66:21] reg [2:0] beat; // @[SourceC.scala:67:21] assign io_bs_adr_bits_beat_0 = beat; // @[SourceC.scala:35:7, :67:21] wire last = &beat; // @[SourceC.scala:67:21, :68:95] wire _req_T = ~busy; // @[SourceC.scala:66:21, :69:18] wire _req_T_1 = ~busy; // @[SourceC.scala:66:21, :69:{18,61}] wire _req_T_2 = _req_T_1 & io_req_valid_0; // @[SourceC.scala:35:7, :69:{61,67}] reg [2:0] req_r_opcode; // @[SourceC.scala:69:47] reg [2:0] req_r_param; // @[SourceC.scala:69:47] reg [4:0] req_r_source; // @[SourceC.scala:69:47] reg [12:0] req_r_tag; // @[SourceC.scala:69:47] reg [9:0] req_r_set; // @[SourceC.scala:69:47] reg [2:0] req_r_way; // @[SourceC.scala:69:47] reg req_r_dirty; // @[SourceC.scala:69:47] wire [2:0] req_opcode = _req_T ? io_req_bits_opcode_0 : req_r_opcode; // @[SourceC.scala:35:7, :69:{17,18,47}] wire [2:0] req_param = _req_T ? io_req_bits_param_0 : req_r_param; // @[SourceC.scala:35:7, :69:{17,18,47}] wire [4:0] req_source = _req_T ? io_req_bits_source_0 : req_r_source; // @[SourceC.scala:35:7, :69:{17,18,47}] wire [12:0] req_tag = _req_T ? io_req_bits_tag_0 : req_r_tag; // @[SourceC.scala:35:7, :69:{17,18,47}] assign req_set = _req_T ? io_req_bits_set_0 : req_r_set; // @[SourceC.scala:35:7, :69:{17,18,47}] assign req_way = _req_T ? io_req_bits_way_0 : req_r_way; // @[SourceC.scala:35:7, :69:{17,18,47}] wire req_dirty = _req_T ? io_req_bits_dirty_0 : req_r_dirty; // @[SourceC.scala:35:7, :69:{17,18,47}] assign io_bs_adr_bits_set_0 = req_set; // @[SourceC.scala:35:7, :69:17] assign io_evict_req_set_0 = req_set; // @[SourceC.scala:35:7, :69:17] assign io_bs_adr_bits_way_0 = req_way; // @[SourceC.scala:35:7, :69:17] assign io_evict_req_way_0 = req_way; // @[SourceC.scala:35:7, :69:17] wire _want_data_T = io_req_valid_0 & room; // @[SourceC.scala:35:7, :59:21, :70:41] wire _want_data_T_1 = _want_data_T & io_req_bits_dirty_0; // @[SourceC.scala:35:7, :70:{41,49}] wire want_data = busy \| _want_data_T_1; // @[SourceC.scala:66:21, :70:{24,49}] wire _io_req_ready_T = ~busy; // @[SourceC.scala:66:21, :69:18, :72:19] assign _io_req_ready_T_1 = _io_req_ready_T & room; // @[SourceC.scala:59:21, :72:{19,25}] assign io_req_ready_0 = _io_req_ready_T_1; // @[SourceC.scala:35:7, :72:25] wire _io_bs_adr_valid_T = \|beat; // @[SourceC.scala:67:21, :77:28] wire _io_bs_adr_valid_T_1 = _io_bs_adr_valid_T \| io_evict_safe_0; // @[SourceC.scala:35:7, :77:{28,32}] assign _io_bs_adr_valid_T_2 = _io_bs_adr_valid_T_1 & want_data; // @[SourceC.scala:70:24, :77:{32,50}] assign io_bs_adr_valid_0 = _io_bs_adr_valid_T_2; // @[SourceC.scala:35:7, :77:50] wire _s2_latch_T = io_bs_adr_ready_0 & io_bs_adr_valid_0; // @[Decoupled.scala:51:35] wire [3:0] _beat_T = {1'h0, beat} + 4'h1; // @[SourceC.scala:67:21, :89:18] wire [2:0] _beat_T_1 = _beat_T[2:0]; // @[SourceC.scala:89:18] wire _s2_latch_T_1 = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] wire s2_latch = want_data ? _s2_latch_T : _s2_latch_T_1; // @[Decoupled.scala:51:35] reg s2_valid; // @[SourceC.scala:97:25] reg [2:0] s2_req_opcode; // @[SourceC.scala:98:25] reg [2:0] s2_req_param; // @[SourceC.scala:98:25] reg [4:0] s2_req_source; // @[SourceC.scala:98:25] reg [12:0] s2_req_tag; // @[SourceC.scala:98:25] reg [9:0] s2_req_set; // @[SourceC.scala:98:25] reg [2:0] s2_req_way; // @[SourceC.scala:98:25] reg s2_req_dirty; // @[SourceC.scala:98:25] reg [2:0] s2_beat; // @[SourceC.scala:99:26] reg s2_last; // @[SourceC.scala:100:26] reg s3_valid; // @[SourceC.scala:103:25] assign c_valid = s3_valid; // @[SourceC.scala:103:25, :108:15] reg [2:0] s3_req_opcode; // @[SourceC.scala:104:25] wire [2:0] c_bits_opcode = s3_req_opcode; // @[SourceC.scala:104:25, :108:15] reg [2:0] s3_req_param; // @[SourceC.scala:104:25] wire [2:0] c_bits_param = s3_req_param; // @[SourceC.scala:104:25, :108:15] reg [4:0] s3_req_source; // @[SourceC.scala:104:25] wire [4:0] c_bits_source = s3_req_source; // @[SourceC.scala:104:25, :108:15] reg [12:0] s3_req_tag; // @[SourceC.scala:104:25] wire [12:0] c_bits_address_base_y = s3_req_tag; // @[SourceC.scala:104:25] reg [9:0] s3_req_set; // @[SourceC.scala:104:25] wire [9:0] c_bits_address_base_y_1 = s3_req_set; // @[SourceC.scala:104:25] reg [2:0] s3_req_way; // @[SourceC.scala:104:25] reg s3_req_dirty; // @[SourceC.scala:104:25] reg [2:0] s3_beat; // @[SourceC.scala:105:26] reg s3_last; // @[SourceC.scala:106:26] wire [31:0] _c_bits_address_T_29; // @[Parameters.scala:230:8] wire [31:0] c_bits_address; // @[SourceC.scala:108:15] wire c_ready; // @[SourceC.scala:108:15] wire [12:0] _c_bits_address_base_T_5 = c_bits_address_base_y; // @[Parameters.scala:221:15, :223:6] wire _c_bits_address_base_T_3 = ~_c_bits_address_base_T_2; // @[Parameters.scala:222:12] wire [9:0] _c_bits_address_base_T_11 = c_bits_address_base_y_1; // @[Parameters.scala:221:15, :223:6] wire _c_bits_address_base_T_9 = ~_c_bits_address_base_T_8; // @[Parameters.scala:222:12] wire _c_bits_address_base_T_15 = ~_c_bits_address_base_T_14; // @[Parameters.scala:222:12] wire [22:0] c_bits_address_base_hi = {_c_bits_address_base_T_5, _c_bits_address_base_T_11}; // @[Parameters.scala:223:6, :227:19] wire [28:0] c_bits_address_base = {c_bits_address_base_hi, 6'h0}; // @[Parameters.scala:227:19] wire _c_bits_address_T = c_bits_address_base[0]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_1 = c_bits_address_base[1]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_2 = c_bits_address_base[2]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_3 = c_bits_address_base[3]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_4 = c_bits_address_base[4]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_5 = c_bits_address_base[5]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_6 = c_bits_address_base[6]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_7 = c_bits_address_base[7]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_8 = c_bits_address_base[8]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_9 = c_bits_address_base[9]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_10 = c_bits_address_base[10]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_11 = c_bits_address_base[11]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_12 = c_bits_address_base[12]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_13 = c_bits_address_base[13]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_14 = c_bits_address_base[14]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_15 = c_bits_address_base[15]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_16 = c_bits_address_base[16]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_17 = c_bits_address_base[17]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_18 = c_bits_address_base[18]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_19 = c_bits_address_base[19]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_20 = c_bits_address_base[20]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_21 = c_bits_address_base[21]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_22 = c_bits_address_base[22]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_23 = c_bits_address_base[23]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_24 = c_bits_address_base[24]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_25 = c_bits_address_base[25]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_26 = c_bits_address_base[26]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_27 = c_bits_address_base[27]; // @[Parameters.scala:227:19, :229:72] wire _c_bits_address_T_28 = c_bits_address_base[28]; // @[Parameters.scala:227:19, :229:72] wire [1:0] c_bits_address_lo_lo_lo_lo = {_c_bits_address_T_1, _c_bits_address_T}; // @[Parameters.scala:229:72, :230:8] wire [1:0] c_bits_address_lo_lo_lo_hi = {_c_bits_address_T_3, _c_bits_address_T_2}; // @[Parameters.scala:229:72, :230:8] wire [3:0] c_bits_address_lo_lo_lo = {c_bits_address_lo_lo_lo_hi, c_bits_address_lo_lo_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] c_bits_address_lo_lo_hi_lo = {_c_bits_address_T_5, _c_bits_address_T_4}; // @[Parameters.scala:229:72, :230:8] wire [1:0] c_bits_address_lo_lo_hi_hi = {_c_bits_address_T_7, _c_bits_address_T_6}; // @[Parameters.scala:229:72, :230:8] wire [3:0] c_bits_address_lo_lo_hi = {c_bits_address_lo_lo_hi_hi, c_bits_address_lo_lo_hi_lo}; // @[Parameters.scala:230:8] wire [7:0] c_bits_address_lo_lo = {c_bits_address_lo_lo_hi, c_bits_address_lo_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] c_bits_address_lo_hi_lo_lo = {_c_bits_address_T_9, _c_bits_address_T_8}; // @[Parameters.scala:229:72, :230:8] wire [1:0] c_bits_address_lo_hi_lo_hi = {_c_bits_address_T_11, _c_bits_address_T_10}; // @[Parameters.scala:229:72, :230:8] wire [3:0] c_bits_address_lo_hi_lo = {c_bits_address_lo_hi_lo_hi, c_bits_address_lo_hi_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] c_bits_address_lo_hi_hi_lo = {_c_bits_address_T_13, _c_bits_address_T_12}; // @[Parameters.scala:229:72, :230:8] wire [1:0] c_bits_address_lo_hi_hi_hi = {_c_bits_address_T_15, _c_bits_address_T_14}; // @[Parameters.scala:229:72, :230:8] wire [3:0] c_bits_address_lo_hi_hi = {c_bits_address_lo_hi_hi_hi, c_bits_address_lo_hi_hi_lo}; // @[Parameters.scala:230:8] wire [7:0] c_bits_address_lo_hi = {c_bits_address_lo_hi_hi, c_bits_address_lo_hi_lo}; // @[Parameters.scala:230:8] wire [15:0] c_bits_address_lo = {c_bits_address_lo_hi, c_bits_address_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] c_bits_address_hi_lo_lo_lo = {_c_bits_address_T_17, _c_bits_address_T_16}; // @[Parameters.scala:229:72, :230:8] wire [1:0] c_bits_address_hi_lo_lo_hi = {_c_bits_address_T_19, _c_bits_address_T_18}; // @[Parameters.scala:229:72, :230:8] wire [3:0] c_bits_address_hi_lo_lo = {c_bits_address_hi_lo_lo_hi, c_bits_address_hi_lo_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] c_bits_address_hi_lo_hi_lo = {_c_bits_address_T_21, _c_bits_address_T_20}; // @[Parameters.scala:229:72, :230:8] wire [1:0] c_bits_address_hi_lo_hi_hi = {_c_bits_address_T_23, _c_bits_address_T_22}; // @[Parameters.scala:229:72, :230:8] wire [3:0] c_bits_address_hi_lo_hi = {c_bits_address_hi_lo_hi_hi, c_bits_address_hi_lo_hi_lo}; // @[Parameters.scala:230:8] wire [7:0] c_bits_address_hi_lo = {c_bits_address_hi_lo_hi, c_bits_address_hi_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] c_bits_address_hi_hi_lo_lo = {_c_bits_address_T_25, _c_bits_address_T_24}; // @[Parameters.scala:229:72, :230:8] wire [1:0] c_bits_address_hi_hi_lo_hi = {_c_bits_address_T_27, _c_bits_address_T_26}; // @[Parameters.scala:229:72, :230:8] wire [3:0] c_bits_address_hi_hi_lo = {c_bits_address_hi_hi_lo_hi, c_bits_address_hi_hi_lo_lo}; // @[Parameters.scala:230:8] wire [1:0] c_bits_address_hi_hi_hi_hi = {_c_bits_address_T_28, 1'h0}; // @[Parameters.scala:229:72, :230:8] wire [3:0] c_bits_address_hi_hi_hi = {c_bits_address_hi_hi_hi_hi, 2'h0}; // @[Parameters.scala:230:8] wire [7:0] c_bits_address_hi_hi = {c_bits_address_hi_hi_hi, c_bits_address_hi_hi_lo}; // @[Parameters.scala:230:8] wire [15:0] c_bits_address_hi = {c_bits_address_hi_hi, c_bits_address_hi_lo}; // @[Parameters.scala:230:8] assign _c_bits_address_T_29 = {c_bits_address_hi, c_bits_address_lo}; // @[Parameters.scala:230:8] assign c_bits_address = _c_bits_address_T_29; // @[SourceC.scala:108:15]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_190( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_346 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_142( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_163 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Periphery.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.debug import chisel3._ import chisel3.experimental.{noPrefix, IntParam} import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.amba.apb.{APBBundle, APBBundleParameters, APBMasterNode, APBMasterParameters, APBMasterPortParameters} import freechips.rocketchip.interrupts.{IntSyncXbar, NullIntSyncSource} import freechips.rocketchip.jtag.JTAGIO import freechips.rocketchip.prci.{ClockSinkNode, ClockSinkParameters} import freechips.rocketchip.subsystem.{BaseSubsystem, CBUS, FBUS, ResetSynchronous, SubsystemResetSchemeKey, TLBusWrapperLocation} import freechips.rocketchip.tilelink.{TLFragmenter, TLWidthWidget} import freechips.rocketchip.util.{AsyncResetSynchronizerShiftReg, CanHavePSDTestModeIO, ClockGate, PSDTestMode, PlusArg, ResetSynchronizerShiftReg} import freechips.rocketchip.util.BooleanToAugmentedBoolean /** Protocols used for communicating with external debugging tools / sealed trait DebugExportProtocol case object DMI extends DebugExportProtocol case object JTAG extends DebugExportProtocol case object CJTAG extends DebugExportProtocol case object APB extends DebugExportProtocol /* Options for possible debug interfaces / case class DebugAttachParams( protocols: Set[DebugExportProtocol] = Set(DMI), externalDisable: Boolean = false, masterWhere: TLBusWrapperLocation = FBUS, slaveWhere: TLBusWrapperLocation = CBUS ) { def dmi = protocols.contains(DMI) def jtag = protocols.contains(JTAG) def cjtag = protocols.contains(CJTAG) def apb = protocols.contains(APB) } case object ExportDebug extends Field(DebugAttachParams()) class ClockedAPBBundle(params: APBBundleParameters) extends APBBundle(params) { val clock = Clock() val reset = Reset() } class DebugIO(implicit val p: Parameters) extends Bundle { val clock = Input(Clock()) val reset = Input(Reset()) val clockeddmi = p(ExportDebug).dmi.option(Flipped(new ClockedDMIIO())) val systemjtag = p(ExportDebug).jtag.option(new SystemJTAGIO) val apb = p(ExportDebug).apb.option(Flipped(new ClockedAPBBundle(APBBundleParameters(addrBits=12, dataBits=32)))) //------------------------------ val ndreset = Output(Bool()) val dmactive = Output(Bool()) val dmactiveAck = Input(Bool()) val extTrigger = (p(DebugModuleKey).get.nExtTriggers > 0).option(new DebugExtTriggerIO()) val disableDebug = p(ExportDebug).externalDisable.option(Input(Bool())) } class PSDIO(implicit val p: Parameters) extends Bundle with CanHavePSDTestModeIO { } class ResetCtrlIO(val nComponents: Int)(implicit val p: Parameters) extends Bundle { val hartResetReq = (p(DebugModuleKey).exists(x=>x.hasHartResets)).option(Output(Vec(nComponents, Bool()))) val hartIsInReset = Input(Vec(nComponents, Bool())) } /* Either adds a JTAG DTM to system, and exports a JTAG interface, * or exports the Debug Module Interface (DMI), or exports and hooks up APB, * based on a global parameter. / trait HasPeripheryDebug { this: BaseSubsystem => private lazy val tlbus = locateTLBusWrapper(p(ExportDebug).slaveWhere) lazy val debugCustomXbarOpt = p(DebugModuleKey).map(params => LazyModule( new DebugCustomXbar(outputRequiresInput = false))) lazy val apbDebugNodeOpt = p(ExportDebug).apb.option(APBMasterNode(Seq(APBMasterPortParameters(Seq(APBMasterParameters("debugAPB")))))) val debugTLDomainOpt = p(DebugModuleKey).map { _ => val domain = ClockSinkNode(Seq(ClockSinkParameters())) domain := tlbus.fixedClockNode domain } lazy val debugOpt = p(DebugModuleKey).map { params => val tlDM = LazyModule(new TLDebugModule(tlbus.beatBytes)) tlDM.node := tlbus.coupleTo("debug"){ TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("Debug")) := _ } tlDM.dmInner.dmInner.customNode := debugCustomXbarOpt.get.node (apbDebugNodeOpt zip tlDM.apbNodeOpt) foreach { case (master, slave) => slave := master } tlDM.dmInner.dmInner.sb2tlOpt.foreach { sb2tl => locateTLBusWrapper(p(ExportDebug).masterWhere).coupleFrom("debug_sb") { _ := TLWidthWidget(1) := sb2tl.node } } tlDM } val debugNode = debugOpt.map(_.intnode) val psd = InModuleBody { val psd = IO(new PSDIO) psd } val resetctrl = InModuleBody { debugOpt.map { debug => debug.module.io.tl_reset := debugTLDomainOpt.get.in.head._1.reset debug.module.io.tl_clock := debugTLDomainOpt.get.in.head._1.clock val resetctrl = IO(new ResetCtrlIO(debug.dmOuter.dmOuter.intnode.edges.out.size)) debug.module.io.hartIsInReset := resetctrl.hartIsInReset resetctrl.hartResetReq.foreach { rcio => debug.module.io.hartResetReq.foreach { rcdm => rcio := rcdm }} resetctrl } } // noPrefix is workaround https://github.com/freechipsproject/chisel3/issues/1603 val debug = InModuleBody { noPrefix(debugOpt.map { debugmod => val debug = IO(new DebugIO) require(!(debug.clockeddmi.isDefined && debug.systemjtag.isDefined), "You cannot have both DMI and JTAG interface in HasPeripheryDebug") require(!(debug.clockeddmi.isDefined && debug.apb.isDefined), "You cannot have both DMI and APB interface in HasPeripheryDebug") require(!(debug.systemjtag.isDefined && debug.apb.isDefined), "You cannot have both APB and JTAG interface in HasPeripheryDebug") debug.clockeddmi.foreach { dbg => debugmod.module.io.dmi.get <> dbg } (debug.apb zip apbDebugNodeOpt zip debugmod.module.io.apb_clock zip debugmod.module.io.apb_reset).foreach { case (((io, apb), c ), r) => apb.out(0)._1 <> io c:= io.clock r:= io.reset } debugmod.module.io.debug_reset := debug.reset debugmod.module.io.debug_clock := debug.clock debug.ndreset := debugmod.module.io.ctrl.ndreset debug.dmactive := debugmod.module.io.ctrl.dmactive debugmod.module.io.ctrl.dmactiveAck := debug.dmactiveAck debug.extTrigger.foreach { x => debugmod.module.io.extTrigger.foreach {y => x <> y}} // TODO in inheriting traits: Set this to something meaningful, e.g. "component is in reset or powered down" debugmod.module.io.ctrl.debugUnavail.foreach { _ := false.B } debug })} val dtm = InModuleBody { debug.flatMap(_.systemjtag.map(instantiateJtagDTM(_))) } def instantiateJtagDTM(sj: SystemJTAGIO): DebugTransportModuleJTAG = { val dtm = Module(new DebugTransportModuleJTAG(p(DebugModuleKey).get.nDMIAddrSize, p(JtagDTMKey))) dtm.io.jtag <> sj.jtag debug.map(_.disableDebug.foreach { x => dtm.io.jtag.TMS := sj.jtag.TMS \| x }) // force TMS high when debug is disabled dtm.io.jtag_clock := sj.jtag.TCK dtm.io.jtag_reset := sj.reset dtm.io.jtag_mfr_id := sj.mfr_id dtm.io.jtag_part_number := sj.part_number dtm.io.jtag_version := sj.version dtm.rf_reset := sj.reset debugOpt.map { outerdebug => outerdebug.module.io.dmi.get.dmi <> dtm.io.dmi outerdebug.module.io.dmi.get.dmiClock := sj.jtag.TCK outerdebug.module.io.dmi.get.dmiReset := sj.reset } dtm } } /* BlackBox to export DMI interface / class SimDTM(implicit p: Parameters) extends BlackBox with HasBlackBoxResource { val io = IO(new Bundle { val clk = Input(Clock()) val reset = Input(Bool()) val debug = new DMIIO val exit = Output(UInt(32.W)) }) def connect(tbclk: Clock, tbreset: Bool, dutio: ClockedDMIIO, tbsuccess: Bool) = { io.clk := tbclk io.reset := tbreset dutio.dmi <> io.debug dutio.dmiClock := tbclk dutio.dmiReset := tbreset tbsuccess := io.exit === 1.U assert(io.exit < 2.U, " FAILED * (exit code = %d)\n", io.exit >> 1.U) } addResource("/vsrc/SimDTM.v") addResource("/csrc/SimDTM.cc") } /** BlackBox to export JTAG interface / class SimJTAG(tickDelay: Int = 50) extends BlackBox(Map("TICK_DELAY" -> IntParam(tickDelay))) with HasBlackBoxResource { val io = IO(new Bundle { val clock = Input(Clock()) val reset = Input(Bool()) val jtag = new JTAGIO(hasTRSTn = true) val enable = Input(Bool()) val init_done = Input(Bool()) val exit = Output(UInt(32.W)) }) def connect(dutio: JTAGIO, tbclock: Clock, tbreset: Bool, init_done: Bool, tbsuccess: Bool) = { dutio.TCK := io.jtag.TCK dutio.TMS := io.jtag.TMS dutio.TDI := io.jtag.TDI io.jtag.TDO := dutio.TDO io.clock := tbclock io.reset := tbreset io.enable := PlusArg("jtag_rbb_enable", 0, "Enable SimJTAG for JTAG Connections. Simulation will pause until connection is made.") io.init_done := init_done // Success is determined by the gdbserver // which is controlling this simulation. tbsuccess := io.exit === 1.U assert(io.exit < 2.U, " FAILED * (exit code = %d)\n", io.exit >> 1.U) } addResource("/vsrc/SimJTAG.v") addResource("/csrc/SimJTAG.cc") addResource("/csrc/remote_bitbang.h") addResource("/csrc/remote_bitbang.cc") } object Debug { def connectDebug( debugOpt: Option[DebugIO], resetctrlOpt: Option[ResetCtrlIO], psdio: PSDIO, c: Clock, r: Bool, out: Bool, tckHalfPeriod: Int = 2, cmdDelay: Int = 2, psd: PSDTestMode = 0.U.asTypeOf(new PSDTestMode())) (implicit p: Parameters): Unit = { connectDebugClockAndReset(debugOpt, c) resetctrlOpt.map { rcio => rcio.hartIsInReset.map { _ := r }} debugOpt.map { debug => debug.clockeddmi.foreach { d => val dtm = Module(new SimDTM).connect(c, r, d, out) } debug.systemjtag.foreach { sj => val jtag = Module(new SimJTAG(tickDelay=3)).connect(sj.jtag, c, r, ~r, out) sj.reset := r.asAsyncReset sj.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) sj.part_number := p(JtagDTMKey).idcodePartNum.U(16.W) sj.version := p(JtagDTMKey).idcodeVersion.U(4.W) } debug.apb.foreach { apb => require(false, "No support for connectDebug for an APB debug connection.") } psdio.psd.foreach { _ <> psd } debug.disableDebug.foreach { x => x := false.B } } } def connectDebugClockAndReset(debugOpt: Option[DebugIO], c: Clock, sync: Boolean = true)(implicit p: Parameters): Unit = { debugOpt.foreach { debug => val dmi_reset = debug.clockeddmi.map(_.dmiReset.asBool).getOrElse(false.B) \| debug.systemjtag.map(_.reset.asBool).getOrElse(false.B) \| debug.apb.map(_.reset.asBool).getOrElse(false.B) connectDebugClockHelper(debug, dmi_reset, c, sync) } } def connectDebugClockHelper(debug: DebugIO, dmi_reset: Reset, c: Clock, sync: Boolean = true)(implicit p: Parameters): Unit = { val debug_reset = Wire(Bool()) withClockAndReset(c, dmi_reset) { val debug_reset_syncd = if(sync) ~AsyncResetSynchronizerShiftReg(in=true.B, sync=3, name=Some("debug_reset_sync")) else dmi_reset debug_reset := debug_reset_syncd } // Need to clock DM during debug_reset because of synchronous reset, so keep // the clock alive for one cycle after debug_reset asserts to action this behavior. // The unit should also be clocked when dmactive is high. withClockAndReset(c, debug_reset.asAsyncReset) { val dmactiveAck = if (sync) ResetSynchronizerShiftReg(in=debug.dmactive, sync=3, name=Some("dmactiveAck")) else debug.dmactive val clock_en = RegNext(next=dmactiveAck, init=true.B) val gated_clock = if (!p(DebugModuleKey).get.clockGate) c else ClockGate(c, clock_en, "debug_clock_gate") debug.clock := gated_clock debug.reset := (if (p(SubsystemResetSchemeKey)==ResetSynchronous) debug_reset else debug_reset.asAsyncReset) debug.dmactiveAck := dmactiveAck } } def tieoffDebug(debugOpt: Option[DebugIO], resetctrlOpt: Option[ResetCtrlIO] = None, psdio: Option[PSDIO] = None)(implicit p: Parameters): Bool = { psdio.foreach(_.psd.foreach { _ <> 0.U.asTypeOf(new PSDTestMode()) } ) resetctrlOpt.map { rcio => rcio.hartIsInReset.map { _ := false.B }} debugOpt.map { debug => debug.clock := true.B.asClock debug.reset := (if (p(SubsystemResetSchemeKey)==ResetSynchronous) true.B else true.B.asAsyncReset) debug.systemjtag.foreach { sj => sj.jtag.TCK := true.B.asClock sj.jtag.TMS := true.B sj.jtag.TDI := true.B sj.jtag.TRSTn.foreach { r => r := true.B } sj.reset := true.B.asAsyncReset sj.mfr_id := 0.U sj.part_number := 0.U sj.version := 0.U } debug.clockeddmi.foreach { d => d.dmi.req.valid := false.B d.dmi.req.bits.addr := 0.U d.dmi.req.bits.data := 0.U d.dmi.req.bits.op := 0.U d.dmi.resp.ready := true.B d.dmiClock := false.B.asClock d.dmiReset := true.B.asAsyncReset } debug.apb.foreach { apb => apb.clock := false.B.asClock apb.reset := true.B.asAsyncReset apb.pready := false.B apb.pslverr := false.B apb.prdata := 0.U apb.pduser := 0.U.asTypeOf(chiselTypeOf(apb.pduser)) apb.psel := false.B apb.penable := false.B } debug.extTrigger.foreach { t => t.in.req := false.B t.out.ack := t.out.req } debug.disableDebug.foreach { x => x := false.B } debug.dmactiveAck := false.B debug.ndreset }.getOrElse(false.B) } } File HasChipyardPRCI.scala: package chipyard.clocking import chisel3._ import scala.collection.mutable.{ArrayBuffer} import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.prci._ import testchipip.boot.{TLTileResetCtrl} import testchipip.clocking.{ClockGroupFakeResetSynchronizer} case class ChipyardPRCIControlParams( slaveWhere: TLBusWrapperLocation = CBUS, baseAddress: BigInt = 0x100000, enableTileClockGating: Boolean = true, enableTileResetSetting: Boolean = true, enableResetSynchronizers: Boolean = true // this should only be disabled to work around verilator async-reset initialization problems ) { def generatePRCIXBar = enableTileClockGating \|\| enableTileResetSetting } case object ChipyardPRCIControlKey extends Field[ChipyardPRCIControlParams](ChipyardPRCIControlParams()) trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElements => require(!p(SubsystemDriveClockGroupsFromIO), "Subsystem allClockGroups cannot be driven from implicit clocks") val prciParams = p(ChipyardPRCIControlKey) // Set up clock domain private val tlbus = locateTLBusWrapper(prciParams.slaveWhere) val prci_ctrl_domain = tlbus.generateSynchronousDomain("ChipyardPRCICtrl") .suggestName("chipyard_prcictrl_domain") val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar(nameSuffix = Some("prcibus")) } } prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar := TLFIFOFixer(TLFIFOFixer.all) := TLBuffer() := _) }) // Aggregate all the clock groups into a single node val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node // The diplomatic clocks in the subsystem are routed to this allClockGroupsNode val clockNamePrefixer = ClockGroupNamePrefixer() (allClockGroupsNode := clockNamePrefixer := aggregator) // Once all the clocks are gathered in the aggregator node, several steps remain // 1. Assign frequencies to any clock groups which did not specify a frequency. // 2. Combine duplicated clock groups (clock groups which physically should be in the same clock domain) // 3. Synchronize reset to each clock group // 4. Clock gate the clock groups corresponding to Tiles (if desired). // 5. Add reset control registers to the tiles (if desired) // The final clock group here contains physically distinct clock domains, which some PRCI node in a // diplomatic IOBinder should drive val frequencySpecifier = ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey)) val clockGroupCombiner = ClockGroupCombiner() val resetSynchronizer = prci_ctrl_domain { if (prciParams.enableResetSynchronizers) ClockGroupResetSynchronizer() else ClockGroupFakeResetSynchronizer() } val tileClockGater = Option.when(prciParams.enableTileClockGating) { prci_ctrl_domain { val clock_gater = LazyModule(new TileClockGater(prciParams.baseAddress + 0x00000, tlbus.beatBytes)) clock_gater.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileClockGater")) := prci_ctrl_bus.get clock_gater } } val tileResetSetter = Option.when(prciParams.enableTileResetSetting) { prci_ctrl_domain { val reset_setter = LazyModule(new TileResetSetter(prciParams.baseAddress + 0x10000, tlbus.beatBytes, tile_prci_domains.map(_._2.tile_reset_domain.clockNode.portParams(0).name.get).toSeq, Nil)) reset_setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileResetSetter")) := prci_ctrl_bus.get reset_setter } } if (!prciParams.enableResetSynchronizers) { println(Console.RED + s""" !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! WARNING: DISABLING THE RESET SYNCHRONIZERS RESULTS IN A BROKEN DESIGN THAT WILL NOT BEHAVE PROPERLY AS ASIC OR FPGA. THESE SHOULD ONLY BE DISABLED TO WORK AROUND LIMITATIONS IN ASYNC RESET INITIALIZATION IN RTL SIMULATORS, NAMELY VERILATOR. !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! """ + Console.RESET) } // The chiptopClockGroupsNode shouuld be what ClockBinders attach to val chiptopClockGroupsNode = ClockGroupEphemeralNode() (aggregator := frequencySpecifier := clockGroupCombiner := resetSynchronizer := tileClockGater.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp"))) := tileResetSetter.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp"))) := chiptopClockGroupsNode) } File UART.scala: package sifive.blocks.devices.uart import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.interrupts._ import freechips.rocketchip.prci._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.util._ import sifive.blocks.util._ /** UART parameters * * @param address uart device TL base address * @param dataBits number of bits in data frame * @param stopBits number of stop bits * @param divisorBits width of baud rate divisor * @param oversample constructs the times of sampling for every data bit * @param nSamples number of reserved Rx sampling result for decide one data bit * @param nTxEntries number of entries in fifo between TL bus and Tx * @param nRxEntries number of entries in fifo between TL bus and Rx * @param includeFourWire additional CTS/RTS ports for flow control * @param includeParity parity support * @param includeIndependentParity Tx and Rx have opposite parity modes * @param initBaudRate initial baud rate * * @note baud rate divisor = clk frequency / baud rate. It means the number of clk period for one data bit. * Calculated in [[UARTAttachParams.attachTo()]] * * @example To configure a 8N1 UART with features below: * {{{ * 8 entries of Tx and Rx fifo * Baud rate = 115200 * Rx samples each data bit 16 times * Uses 3 sample result for each data bit * }}} * Set the stopBits as below and keep the other parameter unchanged * {{{ * stopBits = 1 * }}} * / case class UARTParams( address: BigInt, dataBits: Int = 8, stopBits: Int = 2, divisorBits: Int = 16, oversample: Int = 4, nSamples: Int = 3, nTxEntries: Int = 8, nRxEntries: Int = 8, includeFourWire: Boolean = false, includeParity: Boolean = false, includeIndependentParity: Boolean = false, // Tx and Rx have opposite parity modes initBaudRate: BigInt = BigInt(115200), ) extends DeviceParams { def oversampleFactor = 1 << oversample require(divisorBits > oversample) require(oversampleFactor > nSamples) require((dataBits == 8) \|\| (dataBits == 9)) } class UARTPortIO(val c: UARTParams) extends Bundle { val txd = Output(Bool()) val rxd = Input(Bool()) val cts_n = c.includeFourWire.option(Input(Bool())) val rts_n = c.includeFourWire.option(Output(Bool())) } class UARTInterrupts extends Bundle { val rxwm = Bool() val txwm = Bool() } //abstract class UART(busWidthBytes: Int, val c: UARTParams, divisorInit: Int = 0) /* UART Module organizes Tx and Rx module with fifo and generates control signals for them according to CSRs and UART parameters. * * ==Component== * - Tx * - Tx fifo * - Rx * - Rx fifo * - TL bus to soc * * ==IO== * [[UARTPortIO]] * * ==Datapass== * {{{ * TL bus -> Tx fifo -> Tx * TL bus <- Rx fifo <- Rx * }}} * * @param divisorInit: number of clk period for one data bit / class UART(busWidthBytes: Int, val c: UARTParams, divisorInit: Int = 0) (implicit p: Parameters) extends IORegisterRouter( RegisterRouterParams( name = "serial", compat = Seq("sifive,uart0"), base = c.address, beatBytes = busWidthBytes), new UARTPortIO(c)) //with HasInterruptSources { with HasInterruptSources with HasTLControlRegMap { def nInterrupts = 1 + c.includeParity.toInt ResourceBinding { Resource(ResourceAnchors.aliases, "uart").bind(ResourceAlias(device.label)) } require(divisorInit != 0, "UART divisor wasn't initialized during instantiation") require(divisorInit >> c.divisorBits == 0, s"UART divisor reg (width $c.divisorBits) not wide enough to hold $divisorInit") lazy val module = new LazyModuleImp(this) { val txm = Module(new UARTTx(c)) val txq = Module(new Queue(UInt(c.dataBits.W), c.nTxEntries)) val rxm = Module(new UARTRx(c)) val rxq = Module(new Queue(UInt(c.dataBits.W), c.nRxEntries)) val div = RegInit(divisorInit.U(c.divisorBits.W)) private val stopCountBits = log2Up(c.stopBits) private val txCountBits = log2Floor(c.nTxEntries) + 1 private val rxCountBits = log2Floor(c.nRxEntries) + 1 val txen = RegInit(false.B) val rxen = RegInit(false.B) val enwire4 = RegInit(false.B) val invpol = RegInit(false.B) val enparity = RegInit(false.B) val parity = RegInit(false.B) // Odd parity - 1 , Even parity - 0 val errorparity = RegInit(false.B) val errie = RegInit(false.B) val txwm = RegInit(0.U(txCountBits.W)) val rxwm = RegInit(0.U(rxCountBits.W)) val nstop = RegInit(0.U(stopCountBits.W)) val data8or9 = RegInit(true.B) if (c.includeFourWire){ txm.io.en := txen && (!port.cts_n.get \|\| !enwire4) txm.io.cts_n.get := port.cts_n.get } else txm.io.en := txen txm.io.in <> txq.io.deq txm.io.div := div txm.io.nstop := nstop port.txd := txm.io.out if (c.dataBits == 9) { txm.io.data8or9.get := data8or9 rxm.io.data8or9.get := data8or9 } rxm.io.en := rxen rxm.io.in := port.rxd rxq.io.enq.valid := rxm.io.out.valid rxq.io.enq.bits := rxm.io.out.bits rxm.io.div := div val tx_busy = (txm.io.tx_busy \|\| txq.io.count.orR) && txen port.rts_n.foreach { r => r := Mux(enwire4, !(rxq.io.count < c.nRxEntries.U), tx_busy ^ invpol) } if (c.includeParity) { txm.io.enparity.get := enparity txm.io.parity.get := parity rxm.io.parity.get := parity ^ c.includeIndependentParity.B // independent parity on tx and rx rxm.io.enparity.get := enparity errorparity := rxm.io.errorparity.get \|\| errorparity interrupts(1) := errorparity && errie } val ie = RegInit(0.U.asTypeOf(new UARTInterrupts())) val ip = Wire(new UARTInterrupts) ip.txwm := (txq.io.count < txwm) ip.rxwm := (rxq.io.count > rxwm) interrupts(0) := (ip.txwm && ie.txwm) \|\| (ip.rxwm && ie.rxwm) val mapping = Seq( UARTCtrlRegs.txfifo -> RegFieldGroup("txdata",Some("Transmit data"), NonBlockingEnqueue(txq.io.enq)), UARTCtrlRegs.rxfifo -> RegFieldGroup("rxdata",Some("Receive data"), NonBlockingDequeue(rxq.io.deq)), UARTCtrlRegs.txctrl -> RegFieldGroup("txctrl",Some("Serial transmit control"),Seq( RegField(1, txen, RegFieldDesc("txen","Transmit enable", reset=Some(0))), RegField(stopCountBits, nstop, RegFieldDesc("nstop","Number of stop bits", reset=Some(0))))), UARTCtrlRegs.rxctrl -> Seq(RegField(1, rxen, RegFieldDesc("rxen","Receive enable", reset=Some(0)))), UARTCtrlRegs.txmark -> Seq(RegField(txCountBits, txwm, RegFieldDesc("txcnt","Transmit watermark level", reset=Some(0)))), UARTCtrlRegs.rxmark -> Seq(RegField(rxCountBits, rxwm, RegFieldDesc("rxcnt","Receive watermark level", reset=Some(0)))), UARTCtrlRegs.ie -> RegFieldGroup("ie",Some("Serial interrupt enable"),Seq( RegField(1, ie.txwm, RegFieldDesc("txwm_ie","Transmit watermark interrupt enable", reset=Some(0))), RegField(1, ie.rxwm, RegFieldDesc("rxwm_ie","Receive watermark interrupt enable", reset=Some(0))))), UARTCtrlRegs.ip -> RegFieldGroup("ip",Some("Serial interrupt pending"),Seq( RegField.r(1, ip.txwm, RegFieldDesc("txwm_ip","Transmit watermark interrupt pending", volatile=true)), RegField.r(1, ip.rxwm, RegFieldDesc("rxwm_ip","Receive watermark interrupt pending", volatile=true)))), UARTCtrlRegs.div -> Seq( RegField(c.divisorBits, div, RegFieldDesc("div","Baud rate divisor",reset=Some(divisorInit)))) ) val optionalparity = if (c.includeParity) Seq( UARTCtrlRegs.parity -> RegFieldGroup("paritygenandcheck",Some("Odd/Even Parity Generation/Checking"),Seq( RegField(1, enparity, RegFieldDesc("enparity","Enable Parity Generation/Checking", reset=Some(0))), RegField(1, parity, RegFieldDesc("parity","Odd(1)/Even(0) Parity", reset=Some(0))), RegField(1, errorparity, RegFieldDesc("errorparity","Parity Status Sticky Bit", reset=Some(0))), RegField(1, errie, RegFieldDesc("errie","Interrupt on error in parity enable", reset=Some(0)))))) else Nil val optionalwire4 = if (c.includeFourWire) Seq( UARTCtrlRegs.wire4 -> RegFieldGroup("wire4",Some("Configure Clear-to-send / Request-to-send ports / RS-485"),Seq( RegField(1, enwire4, RegFieldDesc("enwire4","Enable CTS/RTS(1) or RS-485(0)", reset=Some(0))), RegField(1, invpol, RegFieldDesc("invpol","Invert polarity of RTS in RS-485 mode", reset=Some(0))) ))) else Nil val optional8or9 = if (c.dataBits == 9) Seq( UARTCtrlRegs.either8or9 -> RegFieldGroup("ConfigurableDataBits",Some("Configure number of data bits to be transmitted"),Seq( RegField(1, data8or9, RegFieldDesc("databits8or9","Data Bits to be 8(1) or 9(0)", reset=Some(1)))))) else Nil regmap(mapping ++ optionalparity ++ optionalwire4 ++ optional8or9:_) } } class TLUART(busWidthBytes: Int, params: UARTParams, divinit: Int)(implicit p: Parameters) extends UART(busWidthBytes, params, divinit) with HasTLControlRegMap case class UARTLocated(loc: HierarchicalLocation) extends Field[Seq[UARTAttachParams]](Nil) case class UARTAttachParams( device: UARTParams, controlWhere: TLBusWrapperLocation = PBUS, blockerAddr: Option[BigInt] = None, controlXType: ClockCrossingType = NoCrossing, intXType: ClockCrossingType = NoCrossing) extends DeviceAttachParams { def attachTo(where: Attachable)(implicit p: Parameters): TLUART = where { val name = s"uart_${UART.nextId()}" val tlbus = where.locateTLBusWrapper(controlWhere) val divinit = (tlbus.dtsFrequency.get / device.initBaudRate).toInt val uartClockDomainWrapper = LazyModule(new ClockSinkDomain(take = None, name = Some("TLUART"))) val uart = uartClockDomainWrapper { LazyModule(new TLUART(tlbus.beatBytes, device, divinit)) } uart.suggestName(name) tlbus.coupleTo(s"device_named_$name") { bus => val blockerOpt = blockerAddr.map { a => val blocker = LazyModule(new TLClockBlocker(BasicBusBlockerParams(a, tlbus.beatBytes, tlbus.beatBytes))) tlbus.coupleTo(s"bus_blocker_for_$name") { blocker.controlNode := TLFragmenter(tlbus, Some("UART_Blocker")) := _ } blocker } uartClockDomainWrapper.clockNode := (controlXType match { case _: SynchronousCrossing => tlbus.dtsClk.map(_.bind(uart.device)) tlbus.fixedClockNode case _: RationalCrossing => tlbus.clockNode case _: AsynchronousCrossing => val uartClockGroup = ClockGroup() uartClockGroup := where.allClockGroupsNode blockerOpt.map { _.clockNode := uartClockGroup } .getOrElse { uartClockGroup } }) (uart.controlXing(controlXType) := TLFragmenter(tlbus, Some("UART")) := blockerOpt.map { _.node := bus } .getOrElse { bus }) } (intXType match { case _: SynchronousCrossing => where.ibus.fromSync case _: RationalCrossing => where.ibus.fromRational case _: AsynchronousCrossing => where.ibus.fromAsync }) := uart.intXing(intXType) uart } } object UART { val nextId = { var i = -1; () => { i += 1; i} } def makePort(node: BundleBridgeSource[UARTPortIO], name: String)(implicit p: Parameters): ModuleValue[UARTPortIO] = { val uartNode = node.makeSink() InModuleBody { uartNode.makeIO()(ValName(name)) } } def tieoff(port: UARTPortIO) { port.rxd := 1.U if (port.c.includeFourWire) { port.cts_n.foreach { ct => ct := false.B } // active-low } } def loopback(port: UARTPortIO) { port.rxd := port.txd if (port.c.includeFourWire) { port.cts_n.get := port.rts_n.get } } } /* Copyright 2016 SiFive, Inc. Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. / File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File MemoryBus.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.{BuiltInDevices, HasBuiltInDeviceParams, BuiltInErrorDeviceParams, BuiltInZeroDeviceParams} import freechips.rocketchip.tilelink.{ ReplicatedRegion, HasTLBusParams, HasRegionReplicatorParams, TLBusWrapper, TLBusWrapperInstantiationLike, RegionReplicator, TLXbar, TLInwardNode, TLOutwardNode, ProbePicker, TLEdge, TLFIFOFixer } import freechips.rocketchip.util.Location /* Parameterization of the memory-side bus created for each memory channel / case class MemoryBusParams( beatBytes: Int, blockBytes: Int, dtsFrequency: Option[BigInt] = None, zeroDevice: Option[BuiltInZeroDeviceParams] = None, errorDevice: Option[BuiltInErrorDeviceParams] = None, replication: Option[ReplicatedRegion] = None) extends HasTLBusParams with HasBuiltInDeviceParams with HasRegionReplicatorParams with TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): MemoryBus = { val mbus = LazyModule(new MemoryBus(this, loc.name)) mbus.suggestName(loc.name) context.tlBusWrapperLocationMap += (loc -> mbus) mbus } } /* Wrapper for creating TL nodes from a bus connected to the back of each mem channel / class MemoryBus(params: MemoryBusParams, name: String = "memory_bus")(implicit p: Parameters) extends TLBusWrapper(params, name)(p) { private val replicator = params.replication.map(r => LazyModule(new RegionReplicator(r))) val prefixNode = replicator.map { r => r.prefix := addressPrefixNexusNode addressPrefixNexusNode } private val xbar = LazyModule(new TLXbar(nameSuffix = Some(name))).suggestName(busName + "_xbar") val inwardNode: TLInwardNode = replicator.map(xbar.node :=* TLFIFOFixer(TLFIFOFixer.all) := _.node) .getOrElse(xbar.node := TLFIFOFixer(TLFIFOFixer.all)) val outwardNode: TLOutwardNode = ProbePicker() := xbar.node def busView: TLEdge = xbar.node.edges.in.head val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode) } File CanHaveClockTap.scala: package chipyard.clocking import chisel3._ import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.prci._ case object ClockTapKey extends Field[Boolean](true) trait CanHaveClockTap { this: BaseSubsystem => require(!p(SubsystemDriveClockGroupsFromIO), "Subsystem must not drive clocks from IO") val clockTapNode = Option.when(p(ClockTapKey)) { val clockTap = ClockSinkNode(Seq(ClockSinkParameters(name=Some("clock_tap")))) clockTap := ClockGroup() := allClockGroupsNode clockTap } val clockTapIO = clockTapNode.map { node => InModuleBody { val clock_tap = IO(Output(Clock())) clock_tap := node.in.head._1.clock clock_tap }} } File PeripheryBus.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.{BuiltInZeroDeviceParams, BuiltInErrorDeviceParams, HasBuiltInDeviceParams, BuiltInDevices} import freechips.rocketchip.diplomacy.BufferParams import freechips.rocketchip.tilelink.{ RegionReplicator, ReplicatedRegion, HasTLBusParams, HasRegionReplicatorParams, TLBusWrapper, TLBusWrapperInstantiationLike, TLFIFOFixer, TLNode, TLXbar, TLInwardNode, TLOutwardNode, TLBuffer, TLWidthWidget, TLAtomicAutomata, TLEdge } import freechips.rocketchip.util.Location case class BusAtomics( arithmetic: Boolean = true, buffer: BufferParams = BufferParams.default, widenBytes: Option[Int] = None ) case class PeripheryBusParams( beatBytes: Int, blockBytes: Int, atomics: Option[BusAtomics] = Some(BusAtomics()), dtsFrequency: Option[BigInt] = None, zeroDevice: Option[BuiltInZeroDeviceParams] = None, errorDevice: Option[BuiltInErrorDeviceParams] = None, replication: Option[ReplicatedRegion] = None) extends HasTLBusParams with HasBuiltInDeviceParams with HasRegionReplicatorParams with TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): PeripheryBus = { val pbus = LazyModule(new PeripheryBus(this, loc.name)) pbus.suggestName(loc.name) context.tlBusWrapperLocationMap += (loc -> pbus) pbus } } class PeripheryBus(params: PeripheryBusParams, name: String)(implicit p: Parameters) extends TLBusWrapper(params, name) { override lazy val desiredName = s"PeripheryBus_$name" private val replicator = params.replication.map(r => LazyModule(new RegionReplicator(r))) val prefixNode = replicator.map { r => r.prefix := addressPrefixNexusNode addressPrefixNexusNode } private val fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all)) private val node: TLNode = params.atomics.map { pa => val in_xbar = LazyModule(new TLXbar(nameSuffix = Some(s"${name}_in"))) val out_xbar = LazyModule(new TLXbar(nameSuffix = Some(s"${name}_out"))) val fixer_node = replicator.map(fixer.node := _.node).getOrElse(fixer.node) (out_xbar.node := fixer_node := TLBuffer(pa.buffer) := (pa.widenBytes.filter(_ > beatBytes).map { w => TLWidthWidget(w) := TLAtomicAutomata(arithmetic = pa.arithmetic, nameSuffix = Some(name)) } .getOrElse { TLAtomicAutomata(arithmetic = pa.arithmetic, nameSuffix = Some(name)) }) := in_xbar.node) } .getOrElse { TLXbar() := fixer.node } def inwardNode: TLInwardNode = node def outwardNode: TLOutwardNode = node def busView: TLEdge = fixer.node.edges.in.head val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode) } File BankedCoherenceParams.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.BuiltInDevices import freechips.rocketchip.diplomacy.AddressSet import freechips.rocketchip.interrupts.IntOutwardNode import freechips.rocketchip.tilelink.{ TLBroadcast, HasTLBusParams, BroadcastFilter, TLBusWrapper, TLBusWrapperInstantiationLike, TLJbar, TLEdge, TLOutwardNode, TLTempNode, TLInwardNode, BankBinder, TLBroadcastParams, TLBroadcastControlParams, TLBuffer, TLFragmenter, TLNameNode } import freechips.rocketchip.util.Location import CoherenceManagerWrapper._ /** Global cache coherence granularity, which applies to all caches, for now. / case object CacheBlockBytes extends Field[Int](64) /* LLC Broadcast Hub configuration / case object BroadcastKey extends Field(BroadcastParams()) case class BroadcastParams( nTrackers: Int = 4, bufferless: Boolean = false, controlAddress: Option[BigInt] = None, filterFactory: TLBroadcast.ProbeFilterFactory = BroadcastFilter.factory) /* Coherence manager configuration / case object SubsystemBankedCoherenceKey extends Field(BankedCoherenceParams()) case class ClusterBankedCoherenceKey(clusterId: Int) extends Field(BankedCoherenceParams(nBanks=0)) case class BankedCoherenceParams( nBanks: Int = 1, coherenceManager: CoherenceManagerInstantiationFn = broadcastManager ) { require (isPow2(nBanks) \|\| nBanks == 0) } case class CoherenceManagerWrapperParams( blockBytes: Int, beatBytes: Int, nBanks: Int, name: String, dtsFrequency: Option[BigInt] = None) (val coherenceManager: CoherenceManagerInstantiationFn) extends HasTLBusParams with TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): CoherenceManagerWrapper = { val cmWrapper = LazyModule(new CoherenceManagerWrapper(this, context)) cmWrapper.suggestName(loc.name + "_wrapper") cmWrapper.halt.foreach { context.anyLocationMap += loc.halt(_) } context.tlBusWrapperLocationMap += (loc -> cmWrapper) cmWrapper } } class CoherenceManagerWrapper(params: CoherenceManagerWrapperParams, context: HasTileLinkLocations)(implicit p: Parameters) extends TLBusWrapper(params, params.name) { val (tempIn, tempOut, halt) = params.coherenceManager(context) private val coherent_jbar = LazyModule(new TLJbar) def busView: TLEdge = coherent_jbar.node.edges.out.head val inwardNode = tempIn := coherent_jbar.node val builtInDevices = BuiltInDevices.none val prefixNode = None private def banked(node: TLOutwardNode): TLOutwardNode = if (params.nBanks == 0) node else { TLTempNode() :=* BankBinder(params.nBanks, params.blockBytes) := node } val outwardNode = banked(tempOut) } object CoherenceManagerWrapper { type CoherenceManagerInstantiationFn = HasTileLinkLocations => (TLInwardNode, TLOutwardNode, Option[IntOutwardNode]) def broadcastManagerFn( name: String, location: HierarchicalLocation, controlPortsSlaveWhere: TLBusWrapperLocation ): CoherenceManagerInstantiationFn = { context => implicit val p = context.p val cbus = context.locateTLBusWrapper(controlPortsSlaveWhere) val BroadcastParams(nTrackers, bufferless, controlAddress, filterFactory) = p(BroadcastKey) val bh = LazyModule(new TLBroadcast(TLBroadcastParams( lineBytes = p(CacheBlockBytes), numTrackers = nTrackers, bufferless = bufferless, control = controlAddress.map(x => TLBroadcastControlParams(AddressSet(x, 0xfff), cbus.beatBytes)), filterFactory = filterFactory))) bh.suggestName(name) bh.controlNode.foreach { _ := cbus.coupleTo(s"${name}_ctrl") { TLBuffer(1) := TLFragmenter(cbus) := _ } } bh.intNode.foreach { context.ibus.fromSync := _ } (bh.node, bh.node, None) } val broadcastManager = broadcastManagerFn("broadcast", InSystem, CBUS) val incoherentManager: CoherenceManagerInstantiationFn = { _ => val node = TLNameNode("no_coherence_manager") (node, node, None) } } File HasTiles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.debug.TLDebugModule import freechips.rocketchip.diplomacy.{DisableMonitors, FlipRendering} import freechips.rocketchip.interrupts.{IntXbar, IntSinkNode, IntSinkPortSimple, IntSyncAsyncCrossingSink} import freechips.rocketchip.tile.{MaxHartIdBits, BaseTile, InstantiableTileParams, TileParams, TilePRCIDomain, TraceBundle, PriorityMuxHartIdFromSeq} import freechips.rocketchip.tilelink.TLWidthWidget import freechips.rocketchip.prci.{ClockGroup, BundleBridgeBlockDuringReset, NoCrossing, SynchronousCrossing, CreditedCrossing, RationalCrossing, AsynchronousCrossing} import freechips.rocketchip.rocket.TracedInstruction import freechips.rocketchip.util.TraceCoreInterface import scala.collection.immutable.SortedMap /* Entry point for Config-uring the presence of Tiles / case class TilesLocated(loc: HierarchicalLocation) extends Field[Seq[CanAttachTile]](Nil) /* List of HierarchicalLocations which might contain a Tile / case object PossibleTileLocations extends Field[Seq[HierarchicalLocation]](Nil) /* For determining static tile id / case object NumTiles extends Field[Int](0) /* Whether to add timing-closure registers along the path of the hart id * as it propagates through the subsystem and into the tile. * * These are typically only desirable when a dynamically programmable prefix is being combined * with the static hart id via [[freechips.rocketchip.subsystem.HasTiles.tileHartIdNexusNode]]. / case object InsertTimingClosureRegistersOnHartIds extends Field[Boolean](false) /* Whether per-tile hart ids are going to be driven as inputs into a HasTiles block, * and if so, what their width should be. / case object HasTilesExternalHartIdWidthKey extends Field[Option[Int]](None) /* Whether per-tile reset vectors are going to be driven as inputs into a HasTiles block. * * Unlike the hart ids, the reset vector width is determined by the sinks within the tiles, * based on the size of the address map visible to the tiles. / case object HasTilesExternalResetVectorKey extends Field[Boolean](true) /* These are sources of "constants" that are driven into the tile. * * While they are not expected to change dyanmically while the tile is executing code, * they may be either tied to a contant value or programmed during boot or reset. * They need to be instantiated before tiles are attached within the subsystem containing them. / trait HasTileInputConstants { this: LazyModule with Attachable with InstantiatesHierarchicalElements => /* tileHartIdNode is used to collect publishers and subscribers of hartids. / val tileHartIdNodes: SortedMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i => (i, BundleBridgeEphemeralNode[UInt]()) }.to(SortedMap) /* tileHartIdNexusNode is a BundleBridgeNexus that collects dynamic hart prefixes. * * Each "prefix" input is actually the same full width as the outer hart id; the expected usage * is that each prefix source would set only some non-overlapping portion of the bits to non-zero values. * This node orReduces them, and further combines the reduction with the static ids assigned to each tile, * producing a unique, dynamic hart id for each tile. * * If p(InsertTimingClosureRegistersOnHartIds) is set, the input and output values are registered. * * The output values are [[dontTouch]]'d to prevent constant propagation from pulling the values into * the tiles if they are constant, which would ruin deduplication of tiles that are otherwise homogeneous. / val tileHartIdNexusNode = LazyModule(new BundleBridgeNexus[UInt]( inputFn = BundleBridgeNexus.orReduction[UInt](registered = p(InsertTimingClosureRegistersOnHartIds)) _, outputFn = (prefix: UInt, n: Int) => Seq.tabulate(n) { i => val y = dontTouch(prefix \| totalTileIdList(i).U(p(MaxHartIdBits).W)) // dontTouch to keep constant prop from breaking tile dedup if (p(InsertTimingClosureRegistersOnHartIds)) BundleBridgeNexus.safeRegNext(y) else y }, default = Some(() => 0.U(p(MaxHartIdBits).W)), inputRequiresOutput = true, // guard against this being driven but then ignored in tileHartIdIONodes below shouldBeInlined = false // can't inline something whose output we are are dontTouching )).node // TODO: Replace the DebugModuleHartSelFuncs config key with logic to consume the dynamic hart IDs /* tileResetVectorNode is used to collect publishers and subscribers of tile reset vector addresses. / val tileResetVectorNodes: SortedMap[Int, BundleBridgeEphemeralNode[UInt]] = (0 until nTotalTiles).map { i => (i, BundleBridgeEphemeralNode[UInt]()) }.to(SortedMap) /* tileResetVectorNexusNode is a BundleBridgeNexus that accepts a single reset vector source, and broadcasts it to all tiles. / val tileResetVectorNexusNode = BundleBroadcast[UInt]( inputRequiresOutput = true // guard against this being driven but ignored in tileResetVectorIONodes below ) /* tileHartIdIONodes may generate subsystem IOs, one per tile, allowing the parent to assign unique hart ids. * * Or, if such IOs are not configured to exist, tileHartIdNexusNode is used to supply an id to each tile. / val tileHartIdIONodes: Seq[BundleBridgeSource[UInt]] = p(HasTilesExternalHartIdWidthKey) match { case Some(w) => (0 until nTotalTiles).map { i => val hartIdSource = BundleBridgeSource(() => UInt(w.W)) tileHartIdNodes(i) := hartIdSource hartIdSource } case None => { (0 until nTotalTiles).map { i => tileHartIdNodes(i) := tileHartIdNexusNode } Nil } } /** tileResetVectorIONodes may generate subsystem IOs, one per tile, allowing the parent to assign unique reset vectors. * * Or, if such IOs are not configured to exist, tileResetVectorNexusNode is used to supply a single reset vector to every tile. / val tileResetVectorIONodes: Seq[BundleBridgeSource[UInt]] = p(HasTilesExternalResetVectorKey) match { case true => (0 until nTotalTiles).map { i => val resetVectorSource = BundleBridgeSource[UInt]() tileResetVectorNodes(i) := resetVectorSource resetVectorSource } case false => { (0 until nTotalTiles).map { i => tileResetVectorNodes(i) := tileResetVectorNexusNode } Nil } } } /** These are sinks of notifications that are driven out from the tile. * * They need to be instantiated before tiles are attached to the subsystem containing them. / trait HasTileNotificationSinks { this: LazyModule => val tileHaltXbarNode = IntXbar() val tileHaltSinkNode = IntSinkNode(IntSinkPortSimple()) tileHaltSinkNode := tileHaltXbarNode val tileWFIXbarNode = IntXbar() val tileWFISinkNode = IntSinkNode(IntSinkPortSimple()) tileWFISinkNode := tileWFIXbarNode val tileCeaseXbarNode = IntXbar() val tileCeaseSinkNode = IntSinkNode(IntSinkPortSimple()) tileCeaseSinkNode := tileCeaseXbarNode } /* Standardized interface by which parameterized tiles can be attached to contexts containing interconnect resources. * * Sub-classes of this trait can optionally override the individual connect functions in order to specialize * their attachment behaviors, but most use cases should be be handled simply by changing the implementation * of the injectNode functions in crossingParams. / trait CanAttachTile { type TileType <: BaseTile type TileContextType <: DefaultHierarchicalElementContextType def tileParams: InstantiableTileParams[TileType] def crossingParams: HierarchicalElementCrossingParamsLike /* Narrow waist through which all tiles are intended to pass while being instantiated. / def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: SortedMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = { val clockSinkParams = tileParams.clockSinkParams.copy(name = Some(tileParams.uniqueName)) val tile_prci_domain = LazyModule(new TilePRCIDomain[TileType](clockSinkParams, crossingParams) { self => val element = self.element_reset_domain { LazyModule(tileParams.instantiate(crossingParams, PriorityMuxHartIdFromSeq(allTileParams))) } }) tile_prci_domain } /* A default set of connections that need to occur for most tile types / def connect(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { connectMasterPorts(domain, context) connectSlavePorts(domain, context) connectInterrupts(domain, context) connectPRC(domain, context) connectOutputNotifications(domain, context) connectInputConstants(domain, context) connectTrace(domain, context) } /* Connect the port where the tile is the master to a TileLink interconnect. / def connectMasterPorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = { implicit val p = context.p val dataBus = context.locateTLBusWrapper(crossingParams.master.where) dataBus.coupleFrom(tileParams.baseName) { bus => bus := crossingParams.master.injectNode(context) :=* domain.crossMasterPort(crossingParams.crossingType) } } /** Connect the port where the tile is the slave to a TileLink interconnect. / def connectSlavePorts(domain: TilePRCIDomain[TileType], context: Attachable): Unit = { implicit val p = context.p DisableMonitors { implicit p => val controlBus = context.locateTLBusWrapper(crossingParams.slave.where) controlBus.coupleTo(tileParams.baseName) { bus => domain.crossSlavePort(crossingParams.crossingType) := crossingParams.slave.injectNode(context) := TLWidthWidget(controlBus.beatBytes) := bus } } } /** Connect the various interrupts sent to and and raised by the tile. / def connectInterrupts(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p // NOTE: The order of calls to := matters! They must match how interrupts // are decoded from tile.intInwardNode inside the tile. For this reason, // we stub out missing interrupts with constant sources here. // 1. Debug interrupt is definitely asynchronous in all cases. domain.element.intInwardNode := domain { IntSyncAsyncCrossingSink(3) } := context.debugNodes(domain.element.tileId) // 2. The CLINT and PLIC output interrupts are synchronous to the CLINT/PLIC respectively, // so might need to be synchronized depending on the Tile's crossing type. // From CLINT: "msip" and "mtip" context.msipDomain { domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) := context.msipNodes(domain.element.tileId) } // From PLIC: "meip" context.meipDomain { domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) := context.meipNodes(domain.element.tileId) } // From PLIC: "seip" (only if supervisor mode is enabled) if (domain.element.tileParams.core.hasSupervisorMode) { context.seipDomain { domain.crossIntIn(crossingParams.crossingType, domain.element.intInwardNode) := context.seipNodes(domain.element.tileId) } } // 3. Local Interrupts ("lip") are required to already be synchronous to the Tile's clock. // (they are connected to domain.element.intInwardNode in a seperate trait) // 4. Interrupts coming out of the tile are sent to the PLIC, // so might need to be synchronized depending on the Tile's crossing type. context.tileToPlicNodes.get(domain.element.tileId).foreach { node => FlipRendering { implicit p => domain.element.intOutwardNode.foreach { out => context.toPlicDomain { node := domain.crossIntOut(crossingParams.crossingType, out) } }} } // 5. Connect NMI inputs to the tile. These inputs are synchronous to the respective core_clock. domain.element.nmiNode.foreach(_ := context.nmiNodes(domain.element.tileId)) } /* Notifications of tile status are connected to be broadcast without needing to be clock-crossed. / def connectOutputNotifications(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p domain { context.tileHaltXbarNode := domain.crossIntOut(NoCrossing, domain.element.haltNode) context.tileWFIXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.wfiNode) context.tileCeaseXbarNode :=* domain.crossIntOut(NoCrossing, domain.element.ceaseNode) } // TODO should context be forced to have a trace sink connected here? // for now this just ensures domain.trace[Core]Node has been crossed without connecting it externally } /** Connect inputs to the tile that are assumed to be constant during normal operation, and so are not clock-crossed. / def connectInputConstants(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p val tlBusToGetPrefixFrom = context.locateTLBusWrapper(crossingParams.mmioBaseAddressPrefixWhere) domain.element.hartIdNode := context.tileHartIdNodes(domain.element.tileId) domain.element.resetVectorNode := context.tileResetVectorNodes(domain.element.tileId) tlBusToGetPrefixFrom.prefixNode.foreach { domain.element.mmioAddressPrefixNode := _ } } /* Connect power/reset/clock resources. / def connectPRC(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p val tlBusToGetClockDriverFrom = context.locateTLBusWrapper(crossingParams.master.where) (crossingParams.crossingType match { case _: SynchronousCrossing \| _: CreditedCrossing => if (crossingParams.forceSeparateClockReset) { domain.clockNode := tlBusToGetClockDriverFrom.clockNode } else { domain.clockNode := tlBusToGetClockDriverFrom.fixedClockNode } case _: RationalCrossing => domain.clockNode := tlBusToGetClockDriverFrom.clockNode case _: AsynchronousCrossing => { val tileClockGroup = ClockGroup() tileClockGroup := context.allClockGroupsNode domain.clockNode := tileClockGroup } }) domain { domain.element_reset_domain.clockNode := crossingParams.resetCrossingType.injectClockNode := domain.clockNode } } /* Function to handle all trace crossings when tile is instantiated inside domains / def connectTrace(domain: TilePRCIDomain[TileType], context: TileContextType): Unit = { implicit val p = context.p val traceCrossingNode = BundleBridgeBlockDuringReset[TraceBundle]( resetCrossingType = crossingParams.resetCrossingType) context.traceNodes(domain.element.tileId) := traceCrossingNode := domain.element.traceNode val traceCoreCrossingNode = BundleBridgeBlockDuringReset[TraceCoreInterface]( resetCrossingType = crossingParams.resetCrossingType) context.traceCoreNodes(domain.element.tileId) := traceCoreCrossingNode := domain.element.traceCoreNode } } case class CloneTileAttachParams( sourceTileId: Int, cloneParams: CanAttachTile ) extends CanAttachTile { type TileType = cloneParams.TileType type TileContextType = cloneParams.TileContextType def tileParams = cloneParams.tileParams def crossingParams = cloneParams.crossingParams override def instantiate(allTileParams: Seq[TileParams], instantiatedTiles: SortedMap[Int, TilePRCIDomain[_]])(implicit p: Parameters): TilePRCIDomain[TileType] = { require(instantiatedTiles.contains(sourceTileId)) val clockSinkParams = tileParams.clockSinkParams.copy(name = Some(tileParams.uniqueName)) val tile_prci_domain = CloneLazyModule( new TilePRCIDomain[TileType](clockSinkParams, crossingParams) { self => val element = self.element_reset_domain { LazyModule(tileParams.instantiate(crossingParams, PriorityMuxHartIdFromSeq(allTileParams))) } }, instantiatedTiles(sourceTileId).asInstanceOf[TilePRCIDomain[TileType]] ) tile_prci_domain } } File BusWrapper.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.bundlebridge._ import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{AddressSet, NoHandle, NodeHandle, NodeBinding} // TODO This class should be moved to package subsystem to resolve // the dependency awkwardness of the following imports import freechips.rocketchip.devices.tilelink.{BuiltInDevices, CanHaveBuiltInDevices} import freechips.rocketchip.prci.{ ClockParameters, ClockDomain, ClockGroup, ClockGroupAggregator, ClockSinkNode, FixedClockBroadcast, ClockGroupEdgeParameters, ClockSinkParameters, ClockSinkDomain, ClockGroupEphemeralNode, asyncMux, ClockCrossingType, NoCrossing } import freechips.rocketchip.subsystem.{ HasTileLinkLocations, CanConnectWithinContextThatHasTileLinkLocations, CanInstantiateWithinContextThatHasTileLinkLocations } import freechips.rocketchip.util.Location /** Specifies widths of various attachement points in the SoC / trait HasTLBusParams { def beatBytes: Int def blockBytes: Int def beatBits: Int = beatBytes 8 def blockBits: Int = blockBytes * 8 def blockBeats: Int = blockBytes / beatBytes def blockOffset: Int = log2Up(blockBytes) def dtsFrequency: Option[BigInt] def fixedClockOpt = dtsFrequency.map(f => ClockParameters(freqMHz = f.toDouble / 1000000.0)) require (isPow2(beatBytes)) require (isPow2(blockBytes)) } abstract class TLBusWrapper(params: HasTLBusParams, val busName: String)(implicit p: Parameters) extends ClockDomain with HasTLBusParams with CanHaveBuiltInDevices { private val clockGroupAggregator = LazyModule(new ClockGroupAggregator(busName){ override def shouldBeInlined = true }).suggestName(busName + "_clock_groups") private val clockGroup = LazyModule(new ClockGroup(busName){ override def shouldBeInlined = true }) val clockGroupNode = clockGroupAggregator.node // other bus clock groups attach here val clockNode = clockGroup.node val fixedClockNode = FixedClockBroadcast(fixedClockOpt) // device clocks attach here private val clockSinkNode = ClockSinkNode(List(ClockSinkParameters(take = fixedClockOpt))) clockGroup.node := clockGroupAggregator.node fixedClockNode := clockGroup.node // first member of group is always domain's own clock clockSinkNode := fixedClockNode InModuleBody { // make sure the above connections work properly because mismatched-by-name signals will just be ignored. (clockGroup.node.edges.in zip clockGroupAggregator.node.edges.out).zipWithIndex map { case ((in: ClockGroupEdgeParameters , out: ClockGroupEdgeParameters), i) => require(in.members.keys == out.members.keys, s"clockGroup := clockGroupAggregator not working as you expect for index ${i}, becuase clockGroup has ${in.members.keys} and clockGroupAggregator has ${out.members.keys}") } } def clockBundle = clockSinkNode.in.head._1 def beatBytes = params.beatBytes def blockBytes = params.blockBytes def dtsFrequency = params.dtsFrequency val dtsClk = fixedClockNode.fixedClockResources(s"${busName}_clock").flatten.headOption /* If you violate this requirement, you will have a rough time. * The codebase is riddled with the assumption that this is true. / require(blockBytes >= beatBytes) def inwardNode: TLInwardNode def outwardNode: TLOutwardNode def busView: TLEdge def prefixNode: Option[BundleBridgeNode[UInt]] def unifyManagers: List[TLManagerParameters] = ManagerUnification(busView.manager.managers) def crossOutHelper = this.crossOut(outwardNode)(ValName("bus_xing")) def crossInHelper = this.crossIn(inwardNode)(ValName("bus_xing")) def generateSynchronousDomain(domainName: String): ClockSinkDomain = { val domain = LazyModule(new ClockSinkDomain(take = fixedClockOpt, name = Some(domainName))) domain.clockNode := fixedClockNode domain } def generateSynchronousDomain: ClockSinkDomain = generateSynchronousDomain("") protected val addressPrefixNexusNode = BundleBroadcast[UInt](registered = false, default = Some(() => 0.U(1.W))) def to[T](name: String)(body: => T): T = { this { LazyScope(s"coupler_to_${name}", s"TLInterconnectCoupler_${busName}_to_${name}") { body } } } def from[T](name: String)(body: => T): T = { this { LazyScope(s"coupler_from_${name}", s"TLInterconnectCoupler_${busName}_from_${name}") { body } } } def coupleTo[T](name: String)(gen: TLOutwardNode => T): T = to(name) { gen(TLNameNode("tl") :=* outwardNode) } def coupleFrom[T](name: String)(gen: TLInwardNode => T): T = from(name) { gen(inwardNode := TLNameNode("tl")) } def crossToBus(bus: TLBusWrapper, xType: ClockCrossingType, allClockGroupNode: ClockGroupEphemeralNode): NoHandle = { bus.clockGroupNode := asyncMux(xType, allClockGroupNode, this.clockGroupNode) coupleTo(s"bus_named_${bus.busName}") { bus.crossInHelper(xType) := TLWidthWidget(beatBytes) := _ } } def crossFromBus(bus: TLBusWrapper, xType: ClockCrossingType, allClockGroupNode: ClockGroupEphemeralNode): NoHandle = { bus.clockGroupNode := asyncMux(xType, allClockGroupNode, this.clockGroupNode) coupleFrom(s"bus_named_${bus.busName}") { _ :=* TLWidthWidget(bus.beatBytes) :=* bus.crossOutHelper(xType) } } } trait TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): TLBusWrapper } trait TLBusWrapperConnectionLike { val xType: ClockCrossingType def connect(context: HasTileLinkLocations, master: Location[TLBusWrapper], slave: Location[TLBusWrapper])(implicit p: Parameters): Unit } object TLBusWrapperConnection { /** Backwards compatibility factory for master driving clock and slave setting cardinality / def crossTo( xType: ClockCrossingType, driveClockFromMaster: Option[Boolean] = Some(true), nodeBinding: NodeBinding = BIND_STAR, flipRendering: Boolean = false) = { apply(xType, driveClockFromMaster, nodeBinding, flipRendering)( slaveNodeView = { case(w, p) => w.crossInHelper(xType)(p) }) } /* Backwards compatibility factory for slave driving clock and master setting cardinality / def crossFrom( xType: ClockCrossingType, driveClockFromMaster: Option[Boolean] = Some(false), nodeBinding: NodeBinding = BIND_QUERY, flipRendering: Boolean = true) = { apply(xType, driveClockFromMaster, nodeBinding, flipRendering)( masterNodeView = { case(w, p) => w.crossOutHelper(xType)(p) }) } /* Factory for making generic connections between TLBusWrappers / def apply (xType: ClockCrossingType = NoCrossing, driveClockFromMaster: Option[Boolean] = None, nodeBinding: NodeBinding = BIND_ONCE, flipRendering: Boolean = false)( slaveNodeView: (TLBusWrapper, Parameters) => TLInwardNode = { case(w, _) => w.inwardNode }, masterNodeView: (TLBusWrapper, Parameters) => TLOutwardNode = { case(w, _) => w.outwardNode }, inject: Parameters => TLNode = { _ => TLTempNode() }) = { new TLBusWrapperConnection( xType, driveClockFromMaster, nodeBinding, flipRendering)( slaveNodeView, masterNodeView, inject) } } /* TLBusWrapperConnection is a parameterization of a connection between two TLBusWrappers. * It has the following serializable parameters: * - xType: What type of TL clock crossing adapter to insert between the buses. * The appropriate half of the crossing adapter ends up inside each bus. * - driveClockFromMaster: if None, don't bind the bus's diplomatic clockGroupNode, * otherwise have either the master or the slave bus bind the other one's clockGroupNode, * assuming the inserted crossing type is not asynchronous. * - nodeBinding: fine-grained control of multi-edge cardinality resolution for diplomatic bindings within the connection. * - flipRendering: fine-grained control of the graphML rendering of the connection. * If has the following non-serializable parameters: * - slaveNodeView: programmatic control of the specific attachment point within the slave bus. * - masterNodeView: programmatic control of the specific attachment point within the master bus. * - injectNode: programmatic injection of additional nodes into the middle of the connection. * The connect method applies all these parameters to create a diplomatic connection between two Location[TLBusWrapper]s. / class TLBusWrapperConnection (val xType: ClockCrossingType, val driveClockFromMaster: Option[Boolean], val nodeBinding: NodeBinding, val flipRendering: Boolean) (slaveNodeView: (TLBusWrapper, Parameters) => TLInwardNode, masterNodeView: (TLBusWrapper, Parameters) => TLOutwardNode, inject: Parameters => TLNode) extends TLBusWrapperConnectionLike { def connect(context: HasTileLinkLocations, master: Location[TLBusWrapper], slave: Location[TLBusWrapper])(implicit p: Parameters): Unit = { val masterTLBus = context.locateTLBusWrapper(master) val slaveTLBus = context.locateTLBusWrapper(slave) def bindClocks(implicit p: Parameters) = driveClockFromMaster match { case Some(true) => slaveTLBus.clockGroupNode := asyncMux(xType, context.allClockGroupsNode, masterTLBus.clockGroupNode) case Some(false) => masterTLBus.clockGroupNode := asyncMux(xType, context.allClockGroupsNode, slaveTLBus.clockGroupNode) case None => } def bindTLNodes(implicit p: Parameters) = nodeBinding match { case BIND_ONCE => slaveNodeView(slaveTLBus, p) := TLWidthWidget(masterTLBus.beatBytes) := inject(p) := masterNodeView(masterTLBus, p) case BIND_QUERY => slaveNodeView(slaveTLBus, p) := TLWidthWidget(masterTLBus.beatBytes) :=* inject(p) :=* masterNodeView(masterTLBus, p) case BIND_STAR => slaveNodeView(slaveTLBus, p) := TLWidthWidget(masterTLBus.beatBytes) := inject(p) := masterNodeView(masterTLBus, p) case BIND_FLEX => slaveNodeView(slaveTLBus, p) :=* TLWidthWidget(masterTLBus.beatBytes) := inject(p) := masterNodeView(masterTLBus, p) } if (flipRendering) { FlipRendering { implicit p => bindClocks(implicitly[Parameters]) slaveTLBus.from(s"bus_named_${masterTLBus.busName}") { bindTLNodes(implicitly[Parameters]) } } } else { bindClocks(implicitly[Parameters]) masterTLBus.to (s"bus_named_${slaveTLBus.busName}") { bindTLNodes(implicitly[Parameters]) } } } } class TLBusWrapperTopology( val instantiations: Seq[(Location[TLBusWrapper], TLBusWrapperInstantiationLike)], val connections: Seq[(Location[TLBusWrapper], Location[TLBusWrapper], TLBusWrapperConnectionLike)] ) extends CanInstantiateWithinContextThatHasTileLinkLocations with CanConnectWithinContextThatHasTileLinkLocations { def instantiate(context: HasTileLinkLocations)(implicit p: Parameters): Unit = { instantiations.foreach { case (loc, params) => context { params.instantiate(context, loc) } } } def connect(context: HasTileLinkLocations)(implicit p: Parameters): Unit = { connections.foreach { case (master, slave, params) => context { params.connect(context, master, slave) } } } } trait HasTLXbarPhy { this: TLBusWrapper => private val xbar = LazyModule(new TLXbar(nameSuffix = Some(busName))).suggestName(busName + "_xbar") override def shouldBeInlined = xbar.node.circuitIdentity def inwardNode: TLInwardNode = xbar.node def outwardNode: TLOutwardNode = xbar.node def busView: TLEdge = xbar.node.edges.in.head } case class AddressAdjusterWrapperParams( blockBytes: Int, beatBytes: Int, replication: Option[ReplicatedRegion], forceLocal: Seq[AddressSet] = Nil, localBaseAddressDefault: Option[BigInt] = None, policy: TLFIFOFixer.Policy = TLFIFOFixer.allVolatile, ordered: Boolean = true ) extends HasTLBusParams with TLBusWrapperInstantiationLike { val dtsFrequency = None def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): AddressAdjusterWrapper = { val aaWrapper = LazyModule(new AddressAdjusterWrapper(this, context.busContextName + "_" + loc.name)) aaWrapper.suggestName(context.busContextName + "_" + loc.name + "_wrapper") context.tlBusWrapperLocationMap += (loc -> aaWrapper) aaWrapper } } class AddressAdjusterWrapper(params: AddressAdjusterWrapperParams, name: String)(implicit p: Parameters) extends TLBusWrapper(params, name) { private val address_adjuster = params.replication.map { r => LazyModule(new AddressAdjuster(r, params.forceLocal, params.localBaseAddressDefault, params.ordered)) } private val viewNode = TLIdentityNode() val inwardNode: TLInwardNode = address_adjuster.map(_.node := TLFIFOFixer(params.policy) := viewNode).getOrElse(viewNode) def outwardNode: TLOutwardNode = address_adjuster.map(_.node).getOrElse(viewNode) def busView: TLEdge = viewNode.edges.in.head val prefixNode = address_adjuster.map { a => a.prefix := addressPrefixNexusNode addressPrefixNexusNode } val builtInDevices = BuiltInDevices.none override def shouldBeInlined = !params.replication.isDefined } case class TLJBarWrapperParams( blockBytes: Int, beatBytes: Int ) extends HasTLBusParams with TLBusWrapperInstantiationLike { val dtsFrequency = None def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): TLJBarWrapper = { val jbarWrapper = LazyModule(new TLJBarWrapper(this, context.busContextName + "_" + loc.name)) jbarWrapper.suggestName(context.busContextName + "_" + loc.name + "_wrapper") context.tlBusWrapperLocationMap += (loc -> jbarWrapper) jbarWrapper } } class TLJBarWrapper(params: TLJBarWrapperParams, name: String)(implicit p: Parameters) extends TLBusWrapper(params, name) { private val jbar = LazyModule(new TLJbar) val inwardNode: TLInwardNode = jbar.node val outwardNode: TLOutwardNode = jbar.node def busView: TLEdge = jbar.node.edges.in.head val prefixNode = None val builtInDevices = BuiltInDevices.none override def shouldBeInlined = jbar.node.circuitIdentity } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Scratchpad.scala: package testchipip.soc import chisel3._ import freechips.rocketchip.subsystem._ import org.chipsalliance.cde.config.{Field, Config, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.resources.{DiplomacyUtils} import freechips.rocketchip.prci.{ClockSinkDomain, ClockSinkParameters} import scala.collection.immutable.{ListMap} case class BankedScratchpadParams( base: BigInt, size: BigInt, busWhere: TLBusWrapperLocation = SBUS, banks: Int = 4, subBanks: Int = 2, name: String = "banked-scratchpad", disableMonitors: Boolean = false, buffer: BufferParams = BufferParams.none, outerBuffer: BufferParams = BufferParams.none, dtsEnabled: Boolean = false ) case object BankedScratchpadKey extends Field[Seq[BankedScratchpadParams]](Nil) class ScratchpadBank(subBanks: Int, address: AddressSet, beatBytes: Int, devOverride: MemoryDevice, buffer: BufferParams)(implicit p: Parameters) extends ClockSinkDomain(ClockSinkParameters())(p) { val mask = (subBanks - 1) p(CacheBlockBytes) val xbar = TLXbar() (0 until subBanks).map { sb => val ram = LazyModule(new TLRAM( address = AddressSet(address.base + sb * p(CacheBlockBytes), address.mask - mask), beatBytes = beatBytes, devOverride = Some(devOverride)) { override lazy val desiredName = s"TLRAM_ScratchpadBank" }) ram.node := TLFragmenter(beatBytes, p(CacheBlockBytes), nameSuffix = Some("ScratchpadBank")) := TLBuffer(buffer) := xbar } override lazy val desiredName = "ScratchpadBank" } trait CanHaveBankedScratchpad { this: BaseSubsystem => p(BankedScratchpadKey).zipWithIndex.foreach { case (params, si) => val bus = locateTLBusWrapper(params.busWhere) require (params.subBanks >= 1) val name = params.name val banks = params.banks val bankStripe = p(CacheBlockBytes)params.subBanks val mask = (params.banks-1)bankStripe val device = new MemoryDevice { override def describe(resources: ResourceBindings): Description = { Description(describeName("memory", resources), ListMap( "reg" -> resources.map.filterKeys(DiplomacyUtils.regFilter).flatMap(_._2).map(_.value).toList, "device_type" -> Seq(ResourceString("memory")), "status" -> Seq(ResourceString(if (params.dtsEnabled) "okay" else "disabled")) )) } } def genBanks()(implicit p: Parameters) = (0 until banks).map { b => val bank = LazyModule(new ScratchpadBank( params.subBanks, AddressSet(params.base + bankStripe * b, params.size - 1 - mask), bus.beatBytes, device, params.buffer)) bank.clockNode := bus.fixedClockNode bus.coupleTo(s"$name-$si-$b") { bank.xbar := bus { TLBuffer(params.outerBuffer) } := _ } } if (params.disableMonitors) DisableMonitors { implicit p => genBanks()(p) } else genBanks() } } File ClockGroupCombiner.scala: package chipyard.clocking import chisel3._ import chisel3.util._ import chisel3.experimental.Analog import org.chipsalliance.cde.config._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.prci._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ object ClockGroupCombiner { def apply()(implicit p: Parameters, valName: ValName): ClockGroupAdapterNode = { LazyModule(new ClockGroupCombiner()).node } } case object ClockGroupCombinerKey extends Field[Seq[(String, ClockSinkParameters => Boolean)]](Nil) // All clock groups with a name containing any substring in names will be combined into a single clock group class WithClockGroupsCombinedByName(groups: (String, Seq[String], Seq[String])) extends Config((site, here, up) => { case ClockGroupCombinerKey => groups.map { case (grouped_name, matched_names, unmatched_names) => (grouped_name, (m: ClockSinkParameters) => matched_names.exists(n => m.name.get.contains(n)) && !unmatched_names.exists(n => m.name.get.contains(n))) } }) /* This node combines sets of clock groups according to functions provided in the ClockGroupCombinerKey * The ClockGroupCombinersKey contains a list of tuples of: * - The name of the combined group * - A function on the ClockSinkParameters, returning True if the associated clock group should be grouped by this node * This node will fail if * - Multiple grouping functions match a single clock group * - A grouping function matches zero clock groups * - A grouping function matches clock groups with different requested frequncies / class ClockGroupCombiner(implicit p: Parameters, v: ValName) extends LazyModule { val combiners = p(ClockGroupCombinerKey) val sourceFn: ClockGroupSourceParameters => ClockGroupSourceParameters = { m => m } val sinkFn: ClockGroupSinkParameters => ClockGroupSinkParameters = { u => var i = 0 val (grouped, rest) = combiners.map(_._2).foldLeft((Seq[ClockSinkParameters](), u.members)) { case ((grouped, rest), c) => val (g, r) = rest.partition(c(_)) val name = combiners(i)._1 i = i + 1 require(g.size >= 1) val names = g.map(_.name.getOrElse("unamed")) val takes = g.map(_.take).flatten require(takes.distinct.size <= 1, s"Clock group '$name' has non-homogeneous requested ClockParameters ${names.zip(takes)}") require(takes.size > 0, s"Clock group '$name' has no inheritable frequencies") (grouped ++ Seq(ClockSinkParameters(take = takes.headOption, name = Some(name))), r) } ClockGroupSinkParameters( name = u.name, members = grouped ++ rest ) } val node = ClockGroupAdapterNode(sourceFn, sinkFn) lazy val module = new LazyRawModuleImp(this) { (node.out zip node.in).map { case ((o, oe), (i, ie)) => { val inMap = (i.member.data zip ie.sink.members).map { case (id, im) => im.name.get -> id }.toMap (o.member.data zip oe.sink.members).map { case (od, om) => val matches = combiners.filter(c => c._2(om)) require(matches.size <= 1) if (matches.size == 0) { od := inMap(om.name.get) } else { od := inMap(matches(0)._1) } } } } } } File SinkNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, IO} import org.chipsalliance.diplomacy.ValName /* A node which represents a node in the graph which has only inward edges, no outward edges. * * A [[SinkNode]] cannot appear cannot appear right of a `:=`, `:=`, `:=`, or `:=` * * There are no "Mixed" [[SinkNode]]s because each one only has an inward side. / class SinkNode[D, U, EO, EI, B <: Data]( imp: NodeImp[D, U, EO, EI, B] )(pi: Seq[U] )( implicit valName: ValName) extends MixedNode(imp, imp) { override def description = "sink" protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = { def resolveStarInfo: String = s"""$context \|$bindingInfo \|number of known := bindings to inward nodes: $iKnown \|number of known := bindings to outward nodes: $oKnown \|number of binding queries from inward nodes: $iStars \|number of binding queries from outward nodes: $oStars \|${pi.size} inward parameters: [${pi.map(_.toString).mkString(",")}] \|""".stripMargin require( iStars <= 1, s"""Diplomacy has detected a problem with your graph: \|The following node appears left of a := $iStars times; at most once is allowed. \|$resolveStarInfo \|""".stripMargin ) require( oStars == 0, s"""Diplomacy has detected a problem with your graph: \|The following node cannot appear right of a :=* \|$resolveStarInfo \|""".stripMargin ) require( oKnown == 0, s"""Diplomacy has detected a problem with your graph: \|The following node cannot appear right of a := \|$resolveStarInfo \|""".stripMargin ) if (iStars == 0) require( pi.size == iKnown, s"""Diplomacy has detected a problem with your graph: \|The following node has $iKnown inward bindings connected to it, but ${pi.size} sinks were specified to the node constructor. \|Either the number of inward := bindings should be exactly equal to the number of sink, or connect this node on the left-hand side of a := \|$resolveStarInfo \|""".stripMargin ) else require( pi.size >= iKnown, s"""Diplomacy has detected a problem with your graph: \|The following node has $iKnown inward bindings connected to it, but ${pi.size} sinks were specified to the node constructor. \|To resolve :=, size of inward parameters can not be less than bindings. \|$resolveStarInfo \|""".stripMargin ) (pi.size - iKnown, 0) } protected[diplomacy] def mapParamsD(n: Int, p: Seq[D]): Seq[D] = Seq() protected[diplomacy] def mapParamsU(n: Int, p: Seq[U]): Seq[U] = pi def makeIOs( )( implicit valName: ValName ): HeterogeneousBag[B] = { val bundles = this.in.map(_._1) val ios = IO(new HeterogeneousBag(bundles)) ios.suggestName(valName.value) bundles.zip(ios).foreach { case (bundle, io) => io <> bundle } ios } } File DigitalTop.scala: package chipyard import chisel3._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.system._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.devices.tilelink._ // ------------------------------------ // BOOM and/or Rocket Top Level Systems // ------------------------------------ // DOC include start: DigitalTop class DigitalTop(implicit p: Parameters) extends ChipyardSystem with testchipip.tsi.CanHavePeripheryUARTTSI // Enables optional UART-based TSI transport with testchipip.boot.CanHavePeripheryCustomBootPin // Enables optional custom boot pin with testchipip.boot.CanHavePeripheryBootAddrReg // Use programmable boot address register with testchipip.cosim.CanHaveTraceIO // Enables optionally adding trace IO with testchipip.soc.CanHaveBankedScratchpad // Enables optionally adding a banked scratchpad with testchipip.iceblk.CanHavePeripheryBlockDevice // Enables optionally adding the block device with testchipip.serdes.CanHavePeripheryTLSerial // Enables optionally adding the tl-serial interface with testchipip.serdes.old.CanHavePeripheryTLSerial // Enables optionally adding the DEPRECATED tl-serial interface with testchipip.soc.CanHavePeripheryChipIdPin // Enables optional pin to set chip id for multi-chip configs with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C with sifive.blocks.devices.timer.HasPeripheryTimer // Enables optionally adding the timer device with sifive.blocks.devices.pwm.HasPeripheryPWM // Enables optionally adding the sifive PWM with sifive.blocks.devices.uart.HasPeripheryUART // Enables optionally adding the sifive UART with sifive.blocks.devices.gpio.HasPeripheryGPIO // Enables optionally adding the sifive GPIOs with sifive.blocks.devices.spi.HasPeripherySPIFlash // Enables optionally adding the sifive SPI flash controller with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI port with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim with chipyard.example.CanHavePeripheryInitZero // Enables optionally adding the initzero example widget with chipyard.example.CanHavePeripheryGCD // Enables optionally adding the GCD example widget with chipyard.example.CanHavePeripheryStreamingFIR // Enables optionally adding the DSPTools FIR example widget with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA with chipyard.clocking.HasChipyardPRCI // Use Chipyard reset/clock distribution with chipyard.clocking.CanHaveClockTap // Enables optionally adding a clock tap output port with fftgenerator.CanHavePeripheryFFT // Enables optionally having an MMIO-based FFT block with constellation.soc.CanHaveGlobalNoC // Support instantiating a global NoC interconnect with rerocc.CanHaveReRoCCTiles // Support tiles that instantiate rerocc-attached accelerators { override lazy val module = new DigitalTopModule(this) } class DigitalTopModule(l: DigitalTop) extends ChipyardSystemModule(l) with freechips.rocketchip.util.DontTouch // DOC include end: DigitalTop File FrontBus.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.{BuiltInErrorDeviceParams, BuiltInZeroDeviceParams, BuiltInDevices, HasBuiltInDeviceParams} import freechips.rocketchip.tilelink.{HasTLBusParams, TLBusWrapper, TLBusWrapperInstantiationLike, HasTLXbarPhy} import freechips.rocketchip.util.{Location} case class FrontBusParams( beatBytes: Int, blockBytes: Int, dtsFrequency: Option[BigInt] = None, zeroDevice: Option[BuiltInZeroDeviceParams] = None, errorDevice: Option[BuiltInErrorDeviceParams] = None) extends HasTLBusParams with HasBuiltInDeviceParams with TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): FrontBus = { val fbus = LazyModule(new FrontBus(this, loc.name)) fbus.suggestName(loc.name) context.tlBusWrapperLocationMap += (loc -> fbus) fbus } } class FrontBus(params: FrontBusParams, name: String = "front_bus")(implicit p: Parameters) extends TLBusWrapper(params, name) with HasTLXbarPhy { val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode) val prefixNode = None } File PeripheryTLSerial.scala: package testchipip.serdes import chisel3._ import chisel3.util._ import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.{Parameters, Field} import freechips.rocketchip.subsystem._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.prci._ import testchipip.util.{ClockedIO} import testchipip.soc.{OBUS} // Parameters for a read-only-memory that appears over serial-TL case class ManagerROMParams( address: BigInt = 0x20000, size: Int = 0x10000, contentFileName: Option[String] = None) // If unset, generates a JALR to DRAM_BASE // Parameters for a read/write memory that appears over serial-TL case class ManagerRAMParams( address: BigInt, size: BigInt) // Parameters for a coherent cacheable read/write memory that appears over serial-TL case class ManagerCOHParams( address: BigInt, size: BigInt) // Parameters for a set of memory regions that appear over serial-TL case class SerialTLManagerParams( memParams: Seq[ManagerRAMParams] = Nil, romParams: Seq[ManagerROMParams] = Nil, cohParams: Seq[ManagerCOHParams] = Nil, isMemoryDevice: Boolean = false, sinkIdBits: Int = 8, totalIdBits: Int = 8, cacheIdBits: Int = 2, slaveWhere: TLBusWrapperLocation = OBUS ) // Parameters for a TL client which may probe this system over serial-TL case class SerialTLClientParams( totalIdBits: Int = 8, cacheIdBits: Int = 2, masterWhere: TLBusWrapperLocation = FBUS, supportsProbe: Boolean = false ) // The SerialTL can be configured to be bidirectional if serialTLManagerParams is set case class SerialTLParams( client: Option[SerialTLClientParams] = None, manager: Option[SerialTLManagerParams] = None, phyParams: SerialPhyParams = ExternalSyncSerialPhyParams(), bundleParams: TLBundleParameters = TLSerdesser.STANDARD_TLBUNDLE_PARAMS) case object SerialTLKey extends Field[Seq[SerialTLParams]](Nil) trait CanHavePeripheryTLSerial { this: BaseSubsystem => private val portName = "serial-tl" val tlChannels = 5 val (serdessers, serial_tls, serial_tl_debugs) = p(SerialTLKey).zipWithIndex.map { case (params, sid) => val name = s"serial_tl_$sid" lazy val manager_bus = params.manager.map(m => locateTLBusWrapper(m.slaveWhere)) lazy val client_bus = params.client.map(c => locateTLBusWrapper(c.masterWhere)) val clientPortParams = params.client.map { c => TLMasterPortParameters.v1( clients = Seq.tabulate(1 << c.cacheIdBits){ i => TLMasterParameters.v1( name = s"serial_tl_${sid}_${i}", sourceId = IdRange(i << (c.totalIdBits - c.cacheIdBits), (i + 1) << (c.totalIdBits - c.cacheIdBits)), supportsProbe = if (c.supportsProbe) TransferSizes(client_bus.get.blockBytes, client_bus.get.blockBytes) else TransferSizes.none )} )} val managerPortParams = params.manager.map { m => val memParams = m.memParams val romParams = m.romParams val cohParams = m.cohParams val memDevice = if (m.isMemoryDevice) new MemoryDevice else new SimpleDevice("lbwif-readwrite", Nil) val romDevice = new SimpleDevice("lbwif-readonly", Nil) val blockBytes = manager_bus.get.blockBytes TLSlavePortParameters.v1( managers = memParams.map { memParams => TLSlaveParameters.v1( address = AddressSet.misaligned(memParams.address, memParams.size), resources = memDevice.reg, regionType = RegionType.UNCACHED, // cacheable executable = true, supportsGet = TransferSizes(1, blockBytes), supportsPutFull = TransferSizes(1, blockBytes), supportsPutPartial = TransferSizes(1, blockBytes) )} ++ romParams.map { romParams => TLSlaveParameters.v1( address = List(AddressSet(romParams.address, romParams.size-1)), resources = romDevice.reg, regionType = RegionType.UNCACHED, // cacheable executable = true, supportsGet = TransferSizes(1, blockBytes), fifoId = Some(0) )} ++ cohParams.map { cohParams => TLSlaveParameters.v1( address = AddressSet.misaligned(cohParams.address, cohParams.size), regionType = RegionType.TRACKED, // cacheable executable = true, supportsAcquireT = TransferSizes(1, blockBytes), supportsAcquireB = TransferSizes(1, blockBytes), supportsGet = TransferSizes(1, blockBytes), supportsPutFull = TransferSizes(1, blockBytes), supportsPutPartial = TransferSizes(1, blockBytes) )}, beatBytes = manager_bus.get.beatBytes, endSinkId = if (cohParams.isEmpty) 0 else (1 << m.sinkIdBits), minLatency = 1 ) } val serial_tl_domain = LazyModule(new ClockSinkDomain(name=Some(s"SerialTL$sid"))) serial_tl_domain.clockNode := manager_bus.getOrElse(client_bus.get).fixedClockNode if (manager_bus.isDefined) require(manager_bus.get.dtsFrequency.isDefined, s"Manager bus ${manager_bus.get.busName} must provide a frequency") if (client_bus.isDefined) require(client_bus.get.dtsFrequency.isDefined, s"Client bus ${client_bus.get.busName} must provide a frequency") if (manager_bus.isDefined && client_bus.isDefined) { val managerFreq = manager_bus.get.dtsFrequency.get val clientFreq = client_bus.get.dtsFrequency.get require(managerFreq == clientFreq, s"Mismatching manager freq $managerFreq != client freq $clientFreq") } val serdesser = serial_tl_domain { LazyModule(new TLSerdesser( flitWidth = params.phyParams.flitWidth, clientPortParams = clientPortParams, managerPortParams = managerPortParams, bundleParams = params.bundleParams, nameSuffix = Some(name) )) } serdesser.managerNode.foreach { managerNode => val maxClients = 1 << params.manager.get.cacheIdBits val maxIdsPerClient = 1 << (params.manager.get.totalIdBits - params.manager.get.cacheIdBits) manager_bus.get.coupleTo(s"port_named_${name}_out") { (managerNode := TLProbeBlocker(p(CacheBlockBytes)) := TLSourceAdjuster(maxClients, maxIdsPerClient) := TLSourceCombiner(maxIdsPerClient) := TLWidthWidget(manager_bus.get.beatBytes) := _) } } serdesser.clientNode.foreach { clientNode => client_bus.get.coupleFrom(s"port_named_${name}_in") { _ := TLBuffer() := clientNode } } // If we provide a clock, generate a clock domain for the outgoing clock val serial_tl_clock_freqMHz = params.phyParams match { case params: InternalSyncSerialPhyParams => Some(params.freqMHz) case params: ExternalSyncSerialPhyParams => None case params: SourceSyncSerialPhyParams => Some(params.freqMHz) } val serial_tl_clock_node = serial_tl_clock_freqMHz.map { f => serial_tl_domain { ClockSinkNode(Seq(ClockSinkParameters(take=Some(ClockParameters(f))))) } } serial_tl_clock_node.foreach(_ := ClockGroup()(p, ValName(s"${name}_clock")) := allClockGroupsNode) val inner_io = serial_tl_domain { InModuleBody { val inner_io = IO(params.phyParams.genIO).suggestName(name) inner_io match { case io: InternalSyncPhitIO => { // Outer clock comes from the clock node. Synchronize the serdesser's reset to that // clock to get the outer reset val outer_clock = serial_tl_clock_node.get.in.head._1.clock io.clock_out := outer_clock val phy = Module(new DecoupledSerialPhy(tlChannels, params.phyParams)) phy.io.outer_clock := outer_clock phy.io.outer_reset := ResetCatchAndSync(outer_clock, serdesser.module.reset.asBool) phy.io.inner_clock := serdesser.module.clock phy.io.inner_reset := serdesser.module.reset phy.io.outer_ser <> io.viewAsSupertype(new DecoupledPhitIO(io.phitWidth)) phy.io.inner_ser <> serdesser.module.io.ser } case io: ExternalSyncPhitIO => { // Outer clock comes from the IO. Synchronize the serdesser's reset to that // clock to get the outer reset val outer_clock = io.clock_in val outer_reset = ResetCatchAndSync(outer_clock, serdesser.module.reset.asBool) val phy = Module(new DecoupledSerialPhy(tlChannels, params.phyParams)) phy.io.outer_clock := outer_clock phy.io.outer_reset := ResetCatchAndSync(outer_clock, serdesser.module.reset.asBool) phy.io.inner_clock := serdesser.module.clock phy.io.inner_reset := serdesser.module.reset phy.io.outer_ser <> io.viewAsSupertype(new DecoupledPhitIO(params.phyParams.phitWidth)) phy.io.inner_ser <> serdesser.module.io.ser } case io: SourceSyncPhitIO => { // 3 clock domains - // - serdesser's "Inner clock": synchronizes signals going to the digital logic // - outgoing clock: synchronizes signals going out // - incoming clock: synchronizes signals coming in val outgoing_clock = serial_tl_clock_node.get.in.head._1.clock val outgoing_reset = ResetCatchAndSync(outgoing_clock, serdesser.module.reset.asBool) val incoming_clock = io.clock_in val incoming_reset = ResetCatchAndSync(incoming_clock, io.reset_in.asBool) io.clock_out := outgoing_clock io.reset_out := outgoing_reset.asAsyncReset val phy = Module(new CreditedSerialPhy(tlChannels, params.phyParams)) phy.io.incoming_clock := incoming_clock phy.io.incoming_reset := incoming_reset phy.io.outgoing_clock := outgoing_clock phy.io.outgoing_reset := outgoing_reset phy.io.inner_clock := serdesser.module.clock phy.io.inner_reset := serdesser.module.reset phy.io.inner_ser <> serdesser.module.io.ser phy.io.outer_ser <> io.viewAsSupertype(new ValidPhitIO(params.phyParams.phitWidth)) } } inner_io }} val outer_io = InModuleBody { val outer_io = IO(params.phyParams.genIO).suggestName(name) outer_io <> inner_io outer_io } val inner_debug_io = serial_tl_domain { InModuleBody { val inner_debug_io = IO(new SerdesDebugIO).suggestName(s"${name}_debug") inner_debug_io := serdesser.module.io.debug inner_debug_io }} val outer_debug_io = InModuleBody { val outer_debug_io = IO(new SerdesDebugIO).suggestName(s"${name}_debug") outer_debug_io := inner_debug_io outer_debug_io } (serdesser, outer_io, outer_debug_io) }.unzip3 } File CustomBootPin.scala: package testchipip.boot import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ case class CustomBootPinParams( customBootAddress: BigInt = 0x80000000L, // Default is DRAM_BASE masterWhere: TLBusWrapperLocation = CBUS // This needs to write to clint and bootaddrreg, which are on CBUS/PBUS ) case object CustomBootPinKey extends Field[Option[CustomBootPinParams]](None) trait CanHavePeripheryCustomBootPin { this: BaseSubsystem => val custom_boot_pin = p(CustomBootPinKey).map { params => require(p(BootAddrRegKey).isDefined, "CustomBootPin relies on existence of BootAddrReg") val tlbus = locateTLBusWrapper(params.masterWhere) val clientParams = TLMasterPortParameters.v1( clients = Seq(TLMasterParameters.v1( name = "custom-boot", sourceId = IdRange(0, 1), )), minLatency = 1 ) val inner_io = tlbus { val node = TLClientNode(Seq(clientParams)) tlbus.coupleFrom(s"port_named_custom_boot_pin") ({ _ := node }) InModuleBody { val custom_boot = IO(Input(Bool())).suggestName("custom_boot") val (tl, edge) = node.out(0) val inactive :: waiting_bootaddr_reg_a :: waiting_bootaddr_reg_d :: waiting_msip_a :: waiting_msip_d :: dead :: Nil = Enum(6) val state = RegInit(inactive) tl.a.valid := false.B tl.a.bits := DontCare tl.d.ready := true.B switch (state) { is (inactive) { when (custom_boot) { state := waiting_bootaddr_reg_a } } is (waiting_bootaddr_reg_a) { tl.a.valid := true.B tl.a.bits := edge.Put( toAddress = p(BootAddrRegKey).get.bootRegAddress.U, fromSource = 0.U, lgSize = 2.U, data = params.customBootAddress.U )._2 when (tl.a.fire) { state := waiting_bootaddr_reg_d } } is (waiting_bootaddr_reg_d) { when (tl.d.fire) { state := waiting_msip_a } } is (waiting_msip_a) { tl.a.valid := true.B tl.a.bits := edge.Put( toAddress = (p(CLINTKey).get.baseAddress + CLINTConsts.msipOffset(0)).U, // msip for hart0 fromSource = 0.U, lgSize = log2Ceil(CLINTConsts.msipBytes).U, data = 1.U )._2 when (tl.a.fire) { state := waiting_msip_d } } is (waiting_msip_d) { when (tl.d.fire) { state := dead } } is (dead) { when (!custom_boot) { state := inactive } } } custom_boot } } val outer_io = InModuleBody { val custom_boot = IO(Input(Bool())).suggestName("custom_boot") inner_io := custom_boot custom_boot } outer_io } } File SystemBus.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.{ BuiltInDevices, BuiltInZeroDeviceParams, BuiltInErrorDeviceParams, HasBuiltInDeviceParams } import freechips.rocketchip.tilelink.{ TLArbiter, RegionReplicator, ReplicatedRegion, HasTLBusParams, TLBusWrapper, TLBusWrapperInstantiationLike, TLXbar, TLEdge, TLInwardNode, TLOutwardNode, TLFIFOFixer, TLTempNode } import freechips.rocketchip.util.Location case class SystemBusParams( beatBytes: Int, blockBytes: Int, policy: TLArbiter.Policy = TLArbiter.roundRobin, dtsFrequency: Option[BigInt] = None, zeroDevice: Option[BuiltInZeroDeviceParams] = None, errorDevice: Option[BuiltInErrorDeviceParams] = None, replication: Option[ReplicatedRegion] = None) extends HasTLBusParams with HasBuiltInDeviceParams with TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): SystemBus = { val sbus = LazyModule(new SystemBus(this, loc.name)) sbus.suggestName(loc.name) context.tlBusWrapperLocationMap += (loc -> sbus) sbus } } class SystemBus(params: SystemBusParams, name: String = "system_bus")(implicit p: Parameters) extends TLBusWrapper(params, name) { private val replicator = params.replication.map(r => LazyModule(new RegionReplicator(r))) val prefixNode = replicator.map { r => r.prefix := addressPrefixNexusNode addressPrefixNexusNode } private val system_bus_xbar = LazyModule(new TLXbar(policy = params.policy, nameSuffix = Some(name))) val inwardNode: TLInwardNode = system_bus_xbar.node :=* TLFIFOFixer(TLFIFOFixer.allVolatile) :=* replicator.map(_.node).getOrElse(TLTempNode()) val outwardNode: TLOutwardNode = system_bus_xbar.node def busView: TLEdge = system_bus_xbar.node.edges.in.head val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode) } File InterruptBus.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.resources.{Device, DeviceInterrupts, Description, ResourceBindings} import freechips.rocketchip.interrupts.{IntInwardNode, IntOutwardNode, IntXbar, IntNameNode, IntSourceNode, IntSourcePortSimple} import freechips.rocketchip.prci.{ClockCrossingType, AsynchronousCrossing, RationalCrossing, ClockSinkDomain} import freechips.rocketchip.interrupts.IntClockDomainCrossing /** Collects interrupts from internal and external devices and feeds them into the PLIC / class InterruptBusWrapper(implicit p: Parameters) extends ClockSinkDomain { override def shouldBeInlined = true val int_bus = LazyModule(new IntXbar) // Interrupt crossbar private val int_in_xing = this.crossIn(int_bus.intnode) private val int_out_xing = this.crossOut(int_bus.intnode) def from(name: Option[String])(xing: ClockCrossingType) = int_in_xing(xing) := IntNameNode(name) def to(name: Option[String])(xing: ClockCrossingType) = IntNameNode(name) := int_out_xing(xing) def fromAsync: IntInwardNode = from(None)(AsynchronousCrossing(8,3)) def fromRational: IntInwardNode = from(None)(RationalCrossing()) def fromSync: IntInwardNode = int_bus.intnode def toPLIC: IntOutwardNode = int_bus.intnode } /* Specifies the number of external interrupts / case object NExtTopInterrupts extends Field[Int](0) /* This trait adds externally driven interrupts to the system. * However, it should not be used directly; instead one of the below * synchronization wiring child traits should be used. / abstract trait HasExtInterrupts { this: BaseSubsystem => private val device = new Device with DeviceInterrupts { def describe(resources: ResourceBindings): Description = { Description("soc/external-interrupts", describeInterrupts(resources)) } } val nExtInterrupts = p(NExtTopInterrupts) val extInterrupts = IntSourceNode(IntSourcePortSimple(num = nExtInterrupts, resources = device.int)) } /* This trait should be used if the External Interrupts have NOT * already been synchronized to the Periphery (PLIC) Clock. / trait HasAsyncExtInterrupts extends HasExtInterrupts { this: BaseSubsystem => if (nExtInterrupts > 0) { ibus { ibus.fromAsync := extInterrupts } } } /* This trait can be used if the External Interrupts have already been synchronized * to the Periphery (PLIC) Clock. / trait HasSyncExtInterrupts extends HasExtInterrupts { this: BaseSubsystem => if (nExtInterrupts > 0) { ibus { ibus.fromSync := extInterrupts } } } /* Common io name and methods for propagating or tying off the port bundle / trait HasExtInterruptsBundle { val interrupts: UInt def tieOffInterrupts(dummy: Int = 1): Unit = { interrupts := 0.U } } /* This trait performs the translation from a UInt IO into Diplomatic Interrupts. * The wiring must be done in the concrete LazyModuleImp. */ trait HasExtInterruptsModuleImp extends LazyRawModuleImp with HasExtInterruptsBundle { val outer: HasExtInterrupts val interrupts = IO(Input(UInt(outer.nExtInterrupts.W))) outer.extInterrupts.out.map(_._1).flatten.zipWithIndex.foreach { case(o, i) => o := interrupts(i) } } File BundleBridgeSink.scala: package org.chipsalliance.diplomacy.bundlebridge import chisel3.{chiselTypeOf, ActualDirection, Data, IO, Output} import chisel3.reflect.DataMirror import chisel3.reflect.DataMirror.internal.chiselTypeClone import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.nodes.SinkNode case class BundleBridgeSink[T <: Data]( genOpt: Option[() => T] = None )( implicit valName: ValName) extends SinkNode(new BundleBridgeImp[T])(Seq(BundleBridgeParams(genOpt))) { def bundle: T = in(0)._1 private def inferOutput = getElements(bundle).forall { elt => DataMirror.directionOf(elt) == ActualDirection.Unspecified } def makeIO( )( implicit valName: ValName ): T = { val io: T = IO( if (inferOutput) Output(chiselTypeOf(bundle)) else chiselTypeClone(bundle) ) io.suggestName(valName.value) io <> bundle io } def makeIO(name: String): T = makeIO()(ValName(name)) } object BundleBridgeSink { def apply[T <: Data]( )( implicit valName: ValName ): BundleBridgeSink[T] = { BundleBridgeSink(None) } }	module DigitalTop( // @[DigitalTop.scala:47:7] input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_chipyard_prcictrl_domain_reset_setter_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_mbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_cbus_fixedClockNode_anon_out_clock, // @[LazyModuleImp.scala:107:25] output auto_cbus_fixedClockNode_anon_out_reset, // @[LazyModuleImp.scala:107:25] input resetctrl_hartIsInReset_0, // @[Periphery.scala:116:25] input debug_clock, // @[Periphery.scala:125:19] input debug_reset, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TCK, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TMS, // @[Periphery.scala:125:19] input debug_systemjtag_jtag_TDI, // @[Periphery.scala:125:19] output debug_systemjtag_jtag_TDO_data, // @[Periphery.scala:125:19] input debug_systemjtag_reset, // @[Periphery.scala:125:19] output debug_dmactive, // @[Periphery.scala:125:19] input debug_dmactiveAck, // @[Periphery.scala:125:19] input mem_axi4_0_aw_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_aw_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_0_aw_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_aw_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_aw_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_0_aw_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_0_aw_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_aw_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_aw_bits_qos, // @[SinkNode.scala:76:21] input mem_axi4_0_w_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_w_valid, // @[SinkNode.scala:76:21] output [63:0] mem_axi4_0_w_bits_data, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_w_bits_strb, // @[SinkNode.scala:76:21] output mem_axi4_0_w_bits_last, // @[SinkNode.scala:76:21] output mem_axi4_0_b_ready, // @[SinkNode.scala:76:21] input mem_axi4_0_b_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_0_b_bits_id, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_0_b_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_0_ar_ready, // @[SinkNode.scala:76:21] output mem_axi4_0_ar_valid, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_id, // @[SinkNode.scala:76:21] output [31:0] mem_axi4_0_ar_bits_addr, // @[SinkNode.scala:76:21] output [7:0] mem_axi4_0_ar_bits_len, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_ar_bits_size, // @[SinkNode.scala:76:21] output [1:0] mem_axi4_0_ar_bits_burst, // @[SinkNode.scala:76:21] output mem_axi4_0_ar_bits_lock, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_cache, // @[SinkNode.scala:76:21] output [2:0] mem_axi4_0_ar_bits_prot, // @[SinkNode.scala:76:21] output [3:0] mem_axi4_0_ar_bits_qos, // @[SinkNode.scala:76:21] output mem_axi4_0_r_ready, // @[SinkNode.scala:76:21] input mem_axi4_0_r_valid, // @[SinkNode.scala:76:21] input [3:0] mem_axi4_0_r_bits_id, // @[SinkNode.scala:76:21] input [63:0] mem_axi4_0_r_bits_data, // @[SinkNode.scala:76:21] input [1:0] mem_axi4_0_r_bits_resp, // @[SinkNode.scala:76:21] input mem_axi4_0_r_bits_last, // @[SinkNode.scala:76:21] input custom_boot, // @[CustomBootPin.scala:73:27] output serial_tl_0_in_ready, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_in_valid, // @[PeripheryTLSerial.scala:220:24] input [31:0] serial_tl_0_in_bits_phit, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_out_ready, // @[PeripheryTLSerial.scala:220:24] output serial_tl_0_out_valid, // @[PeripheryTLSerial.scala:220:24] output [31:0] serial_tl_0_out_bits_phit, // @[PeripheryTLSerial.scala:220:24] input serial_tl_0_clock_in, // @[PeripheryTLSerial.scala:220:24] output uart_0_txd, // @[BundleBridgeSink.scala:25:19] input uart_0_rxd, // @[BundleBridgeSink.scala:25:19] output clock_tap // @[CanHaveClockTap.scala:23:23] ); wire _dtm_io_dmi_req_valid; // @[Periphery.scala:166:21] wire [6:0] _dtm_io_dmi_req_bits_addr; // @[Periphery.scala:166:21] wire [31:0] _dtm_io_dmi_req_bits_data; // @[Periphery.scala:166:21] wire [1:0] _dtm_io_dmi_req_bits_op; // @[Periphery.scala:166:21] wire _dtm_io_dmi_resp_ready; // @[Periphery.scala:166:21] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_clockTapNode_clock_tap_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_cbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_cbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_mbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_mbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_fbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_fbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_pbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_pbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_1_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_1_reset; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_0_clock; // @[ClockGroupCombiner.scala:19:15] wire _clockGroupCombiner_auto_clock_group_combiner_out_member_allClocks_sbus_0_reset; // @[ClockGroupCombiner.scala:19:15] wire _aggregator_auto_out_4_member_cbus_cbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_4_member_cbus_cbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_3_member_mbus_mbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_3_member_mbus_mbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_2_member_fbus_fbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_2_member_fbus_fbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_1_member_pbus_pbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_1_member_pbus_pbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_0_member_sbus_sbus_1_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_0_member_sbus_sbus_1_reset; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_0_member_sbus_sbus_0_clock; // @[HasChipyardPRCI.scala:51:30] wire _aggregator_auto_out_0_member_sbus_sbus_0_reset; // @[HasChipyardPRCI.scala:51:30] wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_clock; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_resetSynchronizer_out_member_allClocks_uncore_reset; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_xbar_anon_in_a_ready; // @[BusWrapper.scala:89:28] wire _chipyard_prcictrl_domain_auto_xbar_anon_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [2:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [7:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _chipyard_prcictrl_domain_auto_xbar_anon_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _intsink_auto_out_0; // @[Crossing.scala:109:29] wire _uartClockDomainWrapper_auto_uart_0_int_xing_out_sync_0; // @[UART.scala:270:44] wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_a_ready; // @[UART.scala:270:44] wire _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_valid; // @[UART.scala:270:44] wire [2:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_opcode; // @[UART.scala:270:44] wire [1:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_size; // @[UART.scala:270:44] wire [11:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_source; // @[UART.scala:270:44] wire [63:0] _uartClockDomainWrapper_auto_uart_0_control_xing_in_d_bits_data; // @[UART.scala:270:44] wire _serial_tl_domain_auto_serdesser_client_out_a_valid; // @[PeripheryTLSerial.scala:116:38] wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_opcode; // @[PeripheryTLSerial.scala:116:38] wire [2:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_param; // @[PeripheryTLSerial.scala:116:38] wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_size; // @[PeripheryTLSerial.scala:116:38] wire [3:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_source; // @[PeripheryTLSerial.scala:116:38] wire [31:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_address; // @[PeripheryTLSerial.scala:116:38] wire [7:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_mask; // @[PeripheryTLSerial.scala:116:38] wire [63:0] _serial_tl_domain_auto_serdesser_client_out_a_bits_data; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_auto_serdesser_client_out_a_bits_corrupt; // @[PeripheryTLSerial.scala:116:38] wire _serial_tl_domain_auto_serdesser_client_out_d_ready; // @[PeripheryTLSerial.scala:116:38] wire _bank_auto_xbar_anon_in_a_ready; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_valid; // @[Scratchpad.scala:65:28] wire [2:0] _bank_auto_xbar_anon_in_d_bits_opcode; // @[Scratchpad.scala:65:28] wire [1:0] _bank_auto_xbar_anon_in_d_bits_param; // @[Scratchpad.scala:65:28] wire [2:0] _bank_auto_xbar_anon_in_d_bits_size; // @[Scratchpad.scala:65:28] wire [3:0] _bank_auto_xbar_anon_in_d_bits_source; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_sink; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_denied; // @[Scratchpad.scala:65:28] wire [63:0] _bank_auto_xbar_anon_in_d_bits_data; // @[Scratchpad.scala:65:28] wire _bank_auto_xbar_anon_in_d_bits_corrupt; // @[Scratchpad.scala:65:28] wire _bootrom_domain_auto_bootrom_in_a_ready; // @[BusWrapper.scala:89:28] wire _bootrom_domain_auto_bootrom_in_d_valid; // @[BusWrapper.scala:89:28] wire [1:0] _bootrom_domain_auto_bootrom_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [11:0] _bootrom_domain_auto_bootrom_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _bootrom_domain_auto_bootrom_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_valid; // @[Periphery.scala:88:26] wire [2:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_opcode; // @[Periphery.scala:88:26] wire [3:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_size; // @[Periphery.scala:88:26] wire [31:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_address; // @[Periphery.scala:88:26] wire [7:0] _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_a_bits_data; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_sb2tlOpt_out_d_ready; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_tl_in_a_ready; // @[Periphery.scala:88:26] wire _tlDM_auto_dmInner_dmInner_tl_in_d_valid; // @[Periphery.scala:88:26] wire [2:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_opcode; // @[Periphery.scala:88:26] wire [1:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_size; // @[Periphery.scala:88:26] wire [11:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_source; // @[Periphery.scala:88:26] wire [63:0] _tlDM_auto_dmInner_dmInner_tl_in_d_bits_data; // @[Periphery.scala:88:26] wire _tlDM_auto_dmOuter_int_out_sync_0; // @[Periphery.scala:88:26] wire _tlDM_io_dmi_dmi_req_ready; // @[Periphery.scala:88:26] wire _tlDM_io_dmi_dmi_resp_valid; // @[Periphery.scala:88:26] wire [31:0] _tlDM_io_dmi_dmi_resp_bits_data; // @[Periphery.scala:88:26] wire [1:0] _tlDM_io_dmi_dmi_resp_bits_resp; // @[Periphery.scala:88:26] wire _plic_domain_auto_plic_in_a_ready; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_plic_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _plic_domain_auto_plic_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [1:0] _plic_domain_auto_plic_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [11:0] _plic_domain_auto_plic_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _plic_domain_auto_plic_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_1_sync_0; // @[BusWrapper.scala:89:28] wire _plic_domain_auto_int_in_clock_xing_out_0_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_clint_in_a_ready; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_clint_in_d_valid; // @[BusWrapper.scala:89:28] wire [2:0] _clint_domain_auto_clint_in_d_bits_opcode; // @[BusWrapper.scala:89:28] wire [1:0] _clint_domain_auto_clint_in_d_bits_size; // @[BusWrapper.scala:89:28] wire [11:0] _clint_domain_auto_clint_in_d_bits_source; // @[BusWrapper.scala:89:28] wire [63:0] _clint_domain_auto_clint_in_d_bits_data; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_sync_0; // @[BusWrapper.scala:89:28] wire _clint_domain_auto_int_in_clock_xing_out_sync_1; // @[BusWrapper.scala:89:28] wire _clint_domain_clock; // @[BusWrapper.scala:89:28] wire _clint_domain_reset; // @[BusWrapper.scala:89:28] wire _tileHartIdNexusNode_auto_out; // @[HasTiles.scala:75:39] wire _tile_prci_domain_auto_tl_master_clock_xing_out_a_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_size; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_address; // @[HasTiles.scala:163:38] wire [7:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_mask; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_a_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_b_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_c_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_opcode; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_param; // @[HasTiles.scala:163:38] wire [3:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_size; // @[HasTiles.scala:163:38] wire [5:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_source; // @[HasTiles.scala:163:38] wire [31:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_address; // @[HasTiles.scala:163:38] wire [63:0] _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_data; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_c_bits_corrupt; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_d_ready; // @[HasTiles.scala:163:38] wire _tile_prci_domain_auto_tl_master_clock_xing_out_e_valid; // @[HasTiles.scala:163:38] wire [2:0] _tile_prci_domain_auto_tl_master_clock_xing_out_e_bits_sink; // @[HasTiles.scala:163:38] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [3:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_address; // @[BankedCoherenceParams.scala:56:31] wire [7:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_mask; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_a_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coupler_to_bus_named_mbus_bus_xing_out_d_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_b_valid; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_b_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [31:0] _coh_wrapper_auto_coherent_jbar_anon_in_b_bits_address; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_c_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_param; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [6:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_sink; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_denied; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_coherent_jbar_anon_in_d_bits_corrupt; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_l2_ctrls_ctrl_in_a_ready; // @[BankedCoherenceParams.scala:56:31] wire _coh_wrapper_auto_l2_ctrls_ctrl_in_d_valid; // @[BankedCoherenceParams.scala:56:31] wire [2:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_opcode; // @[BankedCoherenceParams.scala:56:31] wire [1:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_size; // @[BankedCoherenceParams.scala:56:31] wire [11:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_source; // @[BankedCoherenceParams.scala:56:31] wire [63:0] _coh_wrapper_auto_l2_ctrls_ctrl_in_d_bits_data; // @[BankedCoherenceParams.scala:56:31] wire _mbus_auto_buffer_out_a_valid; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_opcode; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_param; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_buffer_out_a_bits_size; // @[MemoryBus.scala:30:26] wire [3:0] _mbus_auto_buffer_out_a_bits_source; // @[MemoryBus.scala:30:26] wire [27:0] _mbus_auto_buffer_out_a_bits_address; // @[MemoryBus.scala:30:26] wire [7:0] _mbus_auto_buffer_out_a_bits_mask; // @[MemoryBus.scala:30:26] wire [63:0] _mbus_auto_buffer_out_a_bits_data; // @[MemoryBus.scala:30:26] wire _mbus_auto_buffer_out_a_bits_corrupt; // @[MemoryBus.scala:30:26] wire _mbus_auto_buffer_out_d_ready; // @[MemoryBus.scala:30:26] wire _mbus_auto_fixedClockNode_anon_out_0_clock; // @[MemoryBus.scala:30:26] wire _mbus_auto_fixedClockNode_anon_out_0_reset; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_a_ready; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_valid; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_d_bits_opcode; // @[MemoryBus.scala:30:26] wire [1:0] _mbus_auto_bus_xing_in_d_bits_param; // @[MemoryBus.scala:30:26] wire [2:0] _mbus_auto_bus_xing_in_d_bits_size; // @[MemoryBus.scala:30:26] wire [3:0] _mbus_auto_bus_xing_in_d_bits_source; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_bits_sink; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_bits_denied; // @[MemoryBus.scala:30:26] wire [63:0] _mbus_auto_bus_xing_in_d_bits_data; // @[MemoryBus.scala:30:26] wire _mbus_auto_bus_xing_in_d_bits_corrupt; // @[MemoryBus.scala:30:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [20:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_prci_ctrl_fixer_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [16:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bootrom_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_debug_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [27:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_plic_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [25:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_clint_fragmenter_anon_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [28:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_bus_named_pbus_bus_xing_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [25:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _cbus_auto_coupler_to_l2_ctrl_buffer_out_d_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_4_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_4_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_3_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_3_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_2_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_2_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_1_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_1_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_0_clock; // @[PeripheryBus.scala:37:26] wire _cbus_auto_fixedClockNode_anon_out_0_reset; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _cbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26] wire [1:0] _cbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26] wire [3:0] _cbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26] wire [6:0] _cbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26] wire [63:0] _cbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26] wire _cbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_a_ready; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_opcode; // @[FrontBus.scala:23:26] wire [1:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_size; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_source; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_sink; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_denied; // @[FrontBus.scala:23:26] wire [63:0] _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_port_named_serial_tl_0_in_buffer_in_d_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_a_ready; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_opcode; // @[FrontBus.scala:23:26] wire [1:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_size; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_sink; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_denied; // @[FrontBus.scala:23:26] wire [7:0] _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_coupler_from_debug_sb_widget_anon_in_d_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_fixedClockNode_anon_out_clock; // @[FrontBus.scala:23:26] wire _fbus_auto_fixedClockNode_anon_out_reset; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_a_valid; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_bus_xing_out_a_bits_opcode; // @[FrontBus.scala:23:26] wire [2:0] _fbus_auto_bus_xing_out_a_bits_param; // @[FrontBus.scala:23:26] wire [3:0] _fbus_auto_bus_xing_out_a_bits_size; // @[FrontBus.scala:23:26] wire [4:0] _fbus_auto_bus_xing_out_a_bits_source; // @[FrontBus.scala:23:26] wire [31:0] _fbus_auto_bus_xing_out_a_bits_address; // @[FrontBus.scala:23:26] wire [7:0] _fbus_auto_bus_xing_out_a_bits_mask; // @[FrontBus.scala:23:26] wire [63:0] _fbus_auto_bus_xing_out_a_bits_data; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_a_bits_corrupt; // @[FrontBus.scala:23:26] wire _fbus_auto_bus_xing_out_d_ready; // @[FrontBus.scala:23:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_opcode; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_param; // @[PeripheryBus.scala:37:26] wire [1:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_size; // @[PeripheryBus.scala:37:26] wire [11:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_source; // @[PeripheryBus.scala:37:26] wire [28:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_address; // @[PeripheryBus.scala:37:26] wire [7:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_mask; // @[PeripheryBus.scala:37:26] wire [63:0] _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_data; // @[PeripheryBus.scala:37:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_a_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _pbus_auto_coupler_to_device_named_uart_0_control_xing_out_d_ready; // @[PeripheryBus.scala:37:26] wire _pbus_auto_fixedClockNode_anon_out_clock; // @[PeripheryBus.scala:37:26] wire _pbus_auto_fixedClockNode_anon_out_reset; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_a_ready; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_valid; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_bus_xing_in_d_bits_opcode; // @[PeripheryBus.scala:37:26] wire [1:0] _pbus_auto_bus_xing_in_d_bits_param; // @[PeripheryBus.scala:37:26] wire [2:0] _pbus_auto_bus_xing_in_d_bits_size; // @[PeripheryBus.scala:37:26] wire [7:0] _pbus_auto_bus_xing_in_d_bits_source; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_sink; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_denied; // @[PeripheryBus.scala:37:26] wire [63:0] _pbus_auto_bus_xing_in_d_bits_data; // @[PeripheryBus.scala:37:26] wire _pbus_auto_bus_xing_in_d_bits_corrupt; // @[PeripheryBus.scala:37:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_b_valid; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_param; // @[SystemBus.scala:31:26] wire [31:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_b_bits_address; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_c_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_size; // @[SystemBus.scala:31:26] wire [5:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_source; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_rockettile_tl_master_clock_xing_in_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_opcode; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_param; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_size; // @[SystemBus.scala:31:26] wire [6:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_source; // @[SystemBus.scala:31:26] wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_address; // @[SystemBus.scala:31:26] wire [7:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_mask; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_a_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_b_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_opcode; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_param; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_size; // @[SystemBus.scala:31:26] wire [6:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_source; // @[SystemBus.scala:31:26] wire [31:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_address; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_c_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_d_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_coh_widget_anon_out_e_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_a_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_opcode; // @[SystemBus.scala:31:26] wire [1:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_size; // @[SystemBus.scala:31:26] wire [4:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_source; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_sink; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_denied; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_from_bus_named_fbus_bus_xing_in_d_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_valid; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_opcode; // @[SystemBus.scala:31:26] wire [2:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_param; // @[SystemBus.scala:31:26] wire [3:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_size; // @[SystemBus.scala:31:26] wire [6:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_source; // @[SystemBus.scala:31:26] wire [28:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_address; // @[SystemBus.scala:31:26] wire [7:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_mask; // @[SystemBus.scala:31:26] wire [63:0] _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_data; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_a_bits_corrupt; // @[SystemBus.scala:31:26] wire _sbus_auto_coupler_to_bus_named_cbus_bus_xing_out_d_ready; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_1_clock; // @[SystemBus.scala:31:26] wire _sbus_auto_fixedClockNode_anon_out_1_reset; // @[SystemBus.scala:31:26] wire _sbus_auto_sbus_clock_groups_out_member_coh_0_clock; // @[SystemBus.scala:31:26] wire _sbus_auto_sbus_clock_groups_out_member_coh_0_reset; // @[SystemBus.scala:31:26] wire _ibus_int_bus_auto_anon_out_0; // @[InterruptBus.scala:19:27] reg [9:0] int_rtc_tick_c_value; // @[Counter.scala:61:40] wire int_rtc_tick = int_rtc_tick_c_value == 10'h3E7; // @[Counter.scala:61:40, :73:24] always @(posedge _clint_domain_clock) begin // @[BusWrapper.scala:89:28] if (_clint_domain_reset) // @[BusWrapper.scala:89:28] int_rtc_tick_c_value <= 10'h0; // @[Counter.scala:61:40] else // @[BusWrapper.scala:89:28] int_rtc_tick_c_value <= int_rtc_tick ? 10'h0 : int_rtc_tick_c_value + 10'h1; // @[Counter.scala:61:40, :73:24, :77:{15,24}, :87:{20,28}] always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_74( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_87 io_out_sink_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File loop.scala: package boom.v4.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v4.common._ import boom.v4.util.{BoomCoreStringPrefix} import scala.math.min case class BoomLoopPredictorParams( nWays: Int = 4, threshold: Int = 7 ) class LoopBranchPredictorBank(implicit p: Parameters) extends BranchPredictorBank()(p) { val tagSz = 10 override val nSets = 16 class LoopMeta extends Bundle { val s_cnt = UInt(10.W) } class LoopEntry extends Bundle { val tag = UInt(tagSz.W) val conf = UInt(3.W) val age = UInt(3.W) val p_cnt = UInt(10.W) val s_cnt = UInt(10.W) } class LoopBranchPredictorColumn extends Module { val io = IO(new Bundle { val f2_req_valid = Input(Bool()) val f2_req_idx = Input(UInt()) val f3_req_fire = Input(Bool()) val f3_pred_in = Input(Bool()) val f3_pred = Output(Bool()) val f3_meta = Output(new LoopMeta) val update_mispredict = Input(Bool()) val update_repair = Input(Bool()) val update_idx = Input(UInt()) val update_resolve_dir = Input(Bool()) val update_meta = Input(new LoopMeta) }) val doing_reset = RegInit(true.B) val reset_idx = RegInit(0.U(log2Ceil(nSets).W)) reset_idx := reset_idx + doing_reset when (reset_idx === (nSets-1).U) { doing_reset := false.B } val entries = Reg(Vec(nSets, new LoopEntry)) val f2_entry = WireInit(entries(io.f2_req_idx)) when (io.update_repair && io.update_idx === io.f2_req_idx) { f2_entry.s_cnt := io.update_meta.s_cnt } .elsewhen (io.update_mispredict && io.update_idx === io.f2_req_idx) { f2_entry.s_cnt := 0.U } val f3_entry = RegNext(f2_entry) val f3_scnt = Mux(io.update_repair && io.update_idx === RegNext(io.f2_req_idx), io.update_meta.s_cnt, f3_entry.s_cnt) val f3_tag = RegNext(io.f2_req_idx(tagSz+log2Ceil(nSets)-1,log2Ceil(nSets))) io.f3_pred := io.f3_pred_in io.f3_meta.s_cnt := f3_scnt when (f3_entry.tag === f3_tag) { when (f3_scnt === f3_entry.p_cnt && f3_entry.conf === 7.U) { io.f3_pred := !io.f3_pred_in } } val f4_fire = RegNext(io.f3_req_fire) val f4_entry = RegNext(f3_entry) val f4_tag = RegNext(f3_tag) val f4_scnt = RegNext(f3_scnt) val f4_idx = RegNext(RegNext(io.f2_req_idx)) when (f4_fire) { when (f4_entry.tag === f4_tag) { when (f4_scnt === f4_entry.p_cnt && f4_entry.conf === 7.U) { entries(f4_idx).age := 7.U entries(f4_idx).s_cnt := 0.U } .otherwise { entries(f4_idx).s_cnt := f4_scnt + 1.U entries(f4_idx).age := Mux(f4_entry.age === 7.U, 7.U, f4_entry.age + 1.U) } } } val entry = entries(io.update_idx) val tag = io.update_idx(tagSz+log2Ceil(nSets)-1,log2Ceil(nSets)) val tag_match = entry.tag === tag val ctr_match = entry.p_cnt === io.update_meta.s_cnt val wentry = WireInit(entry) when (io.update_mispredict && !doing_reset) { // Learned, tag match -> decrement confidence when (entry.conf === 7.U && tag_match) { wentry.s_cnt := 0.U wentry.conf := entry.conf - 1.U // Learned, no tag match -> do nothing? Don't evict super-confident entries? } .elsewhen (entry.conf === 7.U && !tag_match) { // Confident, tag match, ctr_match -> increment confidence, reset counter } .elsewhen (entry.conf =/= 0.U && tag_match && ctr_match) { wentry.conf := entry.conf + 1.U wentry.s_cnt := 0.U // Confident, tag match, no ctr match -> zero confidence, reset counter, set previous counter } .elsewhen (entry.conf =/= 0.U && tag_match && !ctr_match) { wentry.conf := 0.U wentry.s_cnt := 0.U wentry.p_cnt := io.update_meta.s_cnt // Confident, no tag match, age is 0 -> replace this entry with our own, set our age high to avoid ping-pong } .elsewhen (entry.conf =/= 0.U && !tag_match && entry.age === 0.U) { wentry.tag := tag wentry.conf := 1.U wentry.s_cnt := 0.U wentry.p_cnt := io.update_meta.s_cnt // Confident, no tag match, age > 0 -> decrement age } .elsewhen (entry.conf =/= 0.U && !tag_match && entry.age =/= 0.U) { wentry.age := entry.age - 1.U // Unconfident, tag match, ctr match -> increment confidence } .elsewhen (entry.conf === 0.U && tag_match && ctr_match) { wentry.conf := 1.U wentry.age := 7.U wentry.s_cnt := 0.U // Unconfident, tag match, no ctr match -> set previous counter } .elsewhen (entry.conf === 0.U && tag_match && !ctr_match) { wentry.p_cnt := io.update_meta.s_cnt wentry.age := 7.U wentry.s_cnt := 0.U // Unconfident, no tag match -> set previous counter and tag } .elsewhen (entry.conf === 0.U && !tag_match) { wentry.tag := tag wentry.conf := 1.U wentry.age := 7.U wentry.s_cnt := 0.U wentry.p_cnt := io.update_meta.s_cnt } entries(io.update_idx) := wentry } .elsewhen (io.update_repair && !doing_reset) { when (tag_match && !(f4_fire && io.update_idx === f4_idx)) { wentry.s_cnt := io.update_meta.s_cnt entries(io.update_idx) := wentry } } when (doing_reset) { entries(reset_idx) := (0.U).asTypeOf(new LoopEntry) } } val columns = Seq.fill(bankWidth) { Module(new LoopBranchPredictorColumn) } val mems = Nil // TODO fix val f3_meta = Wire(Vec(bankWidth, new LoopMeta)) override val metaSz = f3_meta.asUInt.getWidth val update_meta = s1_update.bits.meta.asTypeOf(Vec(bankWidth, new LoopMeta)) for (w <- 0 until bankWidth) { columns(w).io.f2_req_valid := s2_valid columns(w).io.f2_req_idx := s2_idx columns(w).io.f3_req_fire := (s3_valid && s3_mask(w) && io.f3_fire && RegNext(io.resp_in(0).f2(w).predicted_pc.valid && io.resp_in(0).f2(w).is_br)) columns(w).io.f3_pred_in := io.resp_in(0).f3(w).taken io.resp.f3(w).taken := columns(w).io.f3_pred columns(w).io.update_mispredict := (s1_update.valid && s1_update.bits.br_mask(w) && s1_update.bits.is_mispredict_update && s1_update.bits.cfi_mispredicted) columns(w).io.update_repair := (s1_update.valid && s1_update.bits.br_mask(w) && s1_update.bits.is_repair_update) columns(w).io.update_idx := s1_update_idx columns(w).io.update_resolve_dir := s1_update.bits.cfi_taken columns(w).io.update_meta := update_meta(w) f3_meta(w) := columns(w).io.f3_meta } io.f3_meta := f3_meta.asUInt }	module LoopBranchPredictorColumn_6( // @[loop.scala:39:9] input clock, // @[loop.scala:39:9] input reset, // @[loop.scala:39:9] input io_f2_req_valid, // @[loop.scala:43:16] input [35:0] io_f2_req_idx, // @[loop.scala:43:16] input io_f3_req_fire, // @[loop.scala:43:16] input io_f3_pred_in, // @[loop.scala:43:16] output io_f3_pred, // @[loop.scala:43:16] output [9:0] io_f3_meta_s_cnt, // @[loop.scala:43:16] input io_update_mispredict, // @[loop.scala:43:16] input io_update_repair, // @[loop.scala:43:16] input [35:0] io_update_idx, // @[loop.scala:43:16] input io_update_resolve_dir, // @[loop.scala:43:16] input [9:0] io_update_meta_s_cnt // @[loop.scala:43:16] ); wire io_f2_req_valid_0 = io_f2_req_valid; // @[loop.scala:39:9] wire [35:0] io_f2_req_idx_0 = io_f2_req_idx; // @[loop.scala:39:9] wire io_f3_req_fire_0 = io_f3_req_fire; // @[loop.scala:39:9] wire io_f3_pred_in_0 = io_f3_pred_in; // @[loop.scala:39:9] wire io_update_mispredict_0 = io_update_mispredict; // @[loop.scala:39:9] wire io_update_repair_0 = io_update_repair; // @[loop.scala:39:9] wire [35:0] io_update_idx_0 = io_update_idx; // @[loop.scala:39:9] wire io_update_resolve_dir_0 = io_update_resolve_dir; // @[loop.scala:39:9] wire [9:0] io_update_meta_s_cnt_0 = io_update_meta_s_cnt; // @[loop.scala:39:9] wire [2:0] _entries_WIRE_conf = 3'h0; // @[loop.scala:176:43] wire [2:0] _entries_WIRE_age = 3'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_tag = 10'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_p_cnt = 10'h0; // @[loop.scala:176:43] wire [9:0] _entries_WIRE_s_cnt = 10'h0; // @[loop.scala:176:43] wire [35:0] _f2_entry_T = io_f2_req_idx_0; // @[loop.scala:39:9] wire [9:0] f3_scnt; // @[loop.scala:73:23] wire [35:0] _entry_T = io_update_idx_0; // @[loop.scala:39:9] wire [9:0] io_f3_meta_s_cnt_0; // @[loop.scala:39:9] wire io_f3_pred_0; // @[loop.scala:39:9] reg doing_reset; // @[loop.scala:59:30] reg [3:0] reset_idx; // @[loop.scala:60:28] wire [4:0] _reset_idx_T = {1'h0, reset_idx} + {4'h0, doing_reset}; // @[loop.scala:59:30, :60:28, :61:28] wire [3:0] _reset_idx_T_1 = _reset_idx_T[3:0]; // @[loop.scala:61:28] reg [9:0] entries_0_tag; // @[loop.scala:65:22] reg [2:0] entries_0_conf; // @[loop.scala:65:22] reg [2:0] entries_0_age; // @[loop.scala:65:22] reg [9:0] entries_0_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_0_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_1_tag; // @[loop.scala:65:22] reg [2:0] entries_1_conf; // @[loop.scala:65:22] reg [2:0] entries_1_age; // @[loop.scala:65:22] reg [9:0] entries_1_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_1_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_2_tag; // @[loop.scala:65:22] reg [2:0] entries_2_conf; // @[loop.scala:65:22] reg [2:0] entries_2_age; // @[loop.scala:65:22] reg [9:0] entries_2_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_2_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_3_tag; // @[loop.scala:65:22] reg [2:0] entries_3_conf; // @[loop.scala:65:22] reg [2:0] entries_3_age; // @[loop.scala:65:22] reg [9:0] entries_3_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_3_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_4_tag; // @[loop.scala:65:22] reg [2:0] entries_4_conf; // @[loop.scala:65:22] reg [2:0] entries_4_age; // @[loop.scala:65:22] reg [9:0] entries_4_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_4_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_5_tag; // @[loop.scala:65:22] reg [2:0] entries_5_conf; // @[loop.scala:65:22] reg [2:0] entries_5_age; // @[loop.scala:65:22] reg [9:0] entries_5_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_5_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_6_tag; // @[loop.scala:65:22] reg [2:0] entries_6_conf; // @[loop.scala:65:22] reg [2:0] entries_6_age; // @[loop.scala:65:22] reg [9:0] entries_6_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_6_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_7_tag; // @[loop.scala:65:22] reg [2:0] entries_7_conf; // @[loop.scala:65:22] reg [2:0] entries_7_age; // @[loop.scala:65:22] reg [9:0] entries_7_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_7_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_8_tag; // @[loop.scala:65:22] reg [2:0] entries_8_conf; // @[loop.scala:65:22] reg [2:0] entries_8_age; // @[loop.scala:65:22] reg [9:0] entries_8_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_8_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_9_tag; // @[loop.scala:65:22] reg [2:0] entries_9_conf; // @[loop.scala:65:22] reg [2:0] entries_9_age; // @[loop.scala:65:22] reg [9:0] entries_9_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_9_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_10_tag; // @[loop.scala:65:22] reg [2:0] entries_10_conf; // @[loop.scala:65:22] reg [2:0] entries_10_age; // @[loop.scala:65:22] reg [9:0] entries_10_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_10_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_11_tag; // @[loop.scala:65:22] reg [2:0] entries_11_conf; // @[loop.scala:65:22] reg [2:0] entries_11_age; // @[loop.scala:65:22] reg [9:0] entries_11_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_11_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_12_tag; // @[loop.scala:65:22] reg [2:0] entries_12_conf; // @[loop.scala:65:22] reg [2:0] entries_12_age; // @[loop.scala:65:22] reg [9:0] entries_12_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_12_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_13_tag; // @[loop.scala:65:22] reg [2:0] entries_13_conf; // @[loop.scala:65:22] reg [2:0] entries_13_age; // @[loop.scala:65:22] reg [9:0] entries_13_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_13_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_14_tag; // @[loop.scala:65:22] reg [2:0] entries_14_conf; // @[loop.scala:65:22] reg [2:0] entries_14_age; // @[loop.scala:65:22] reg [9:0] entries_14_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_14_s_cnt; // @[loop.scala:65:22] reg [9:0] entries_15_tag; // @[loop.scala:65:22] reg [2:0] entries_15_conf; // @[loop.scala:65:22] reg [2:0] entries_15_age; // @[loop.scala:65:22] reg [9:0] entries_15_p_cnt; // @[loop.scala:65:22] reg [9:0] entries_15_s_cnt; // @[loop.scala:65:22] wire [3:0] _f2_entry_T_1 = _f2_entry_T[3:0]; wire [9:0] f2_entry_tag; // @[loop.scala:66:28] wire [2:0] f2_entry_conf; // @[loop.scala:66:28] wire [2:0] f2_entry_age; // @[loop.scala:66:28] wire [9:0] f2_entry_p_cnt; // @[loop.scala:66:28] wire [9:0] f2_entry_s_cnt; // @[loop.scala:66:28] wire [15:0][9:0] _GEN = {{entries_15_tag}, {entries_14_tag}, {entries_13_tag}, {entries_12_tag}, {entries_11_tag}, {entries_10_tag}, {entries_9_tag}, {entries_8_tag}, {entries_7_tag}, {entries_6_tag}, {entries_5_tag}, {entries_4_tag}, {entries_3_tag}, {entries_2_tag}, {entries_1_tag}, {entries_0_tag}}; // @[loop.scala:65:22, :66:28] assign f2_entry_tag = _GEN[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][2:0] _GEN_0 = {{entries_15_conf}, {entries_14_conf}, {entries_13_conf}, {entries_12_conf}, {entries_11_conf}, {entries_10_conf}, {entries_9_conf}, {entries_8_conf}, {entries_7_conf}, {entries_6_conf}, {entries_5_conf}, {entries_4_conf}, {entries_3_conf}, {entries_2_conf}, {entries_1_conf}, {entries_0_conf}}; // @[loop.scala:65:22, :66:28] assign f2_entry_conf = _GEN_0[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][2:0] _GEN_1 = {{entries_15_age}, {entries_14_age}, {entries_13_age}, {entries_12_age}, {entries_11_age}, {entries_10_age}, {entries_9_age}, {entries_8_age}, {entries_7_age}, {entries_6_age}, {entries_5_age}, {entries_4_age}, {entries_3_age}, {entries_2_age}, {entries_1_age}, {entries_0_age}}; // @[loop.scala:65:22, :66:28] assign f2_entry_age = _GEN_1[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][9:0] _GEN_2 = {{entries_15_p_cnt}, {entries_14_p_cnt}, {entries_13_p_cnt}, {entries_12_p_cnt}, {entries_11_p_cnt}, {entries_10_p_cnt}, {entries_9_p_cnt}, {entries_8_p_cnt}, {entries_7_p_cnt}, {entries_6_p_cnt}, {entries_5_p_cnt}, {entries_4_p_cnt}, {entries_3_p_cnt}, {entries_2_p_cnt}, {entries_1_p_cnt}, {entries_0_p_cnt}}; // @[loop.scala:65:22, :66:28] assign f2_entry_p_cnt = _GEN_2[_f2_entry_T_1]; // @[loop.scala:66:28] wire [15:0][9:0] _GEN_3 = {{entries_15_s_cnt}, {entries_14_s_cnt}, {entries_13_s_cnt}, {entries_12_s_cnt}, {entries_11_s_cnt}, {entries_10_s_cnt}, {entries_9_s_cnt}, {entries_8_s_cnt}, {entries_7_s_cnt}, {entries_6_s_cnt}, {entries_5_s_cnt}, {entries_4_s_cnt}, {entries_3_s_cnt}, {entries_2_s_cnt}, {entries_1_s_cnt}, {entries_0_s_cnt}}; // @[loop.scala:65:22, :66:28] wire _T_3 = io_update_idx_0 == io_f2_req_idx_0; // @[loop.scala:39:9, :67:45] assign f2_entry_s_cnt = io_update_repair_0 & _T_3 ? io_update_meta_s_cnt_0 : io_update_mispredict_0 & _T_3 ? 10'h0 : _GEN_3[_f2_entry_T_1]; // @[loop.scala:39:9, :66:28, :67:{28,45,64}, :68:22, :69:{39,75}, :70:22] reg [9:0] f3_entry_tag; // @[loop.scala:72:27] reg [2:0] f3_entry_conf; // @[loop.scala:72:27] reg [2:0] f3_entry_age; // @[loop.scala:72:27] reg [9:0] f3_entry_p_cnt; // @[loop.scala:72:27] reg [9:0] f3_entry_s_cnt; // @[loop.scala:72:27] reg [35:0] f3_scnt_REG; // @[loop.scala:73:69] wire _f3_scnt_T = io_update_idx_0 == f3_scnt_REG; // @[loop.scala:39:9, :73:{58,69}] wire _f3_scnt_T_1 = io_update_repair_0 & _f3_scnt_T; // @[loop.scala:39:9, :73:{41,58}] assign f3_scnt = _f3_scnt_T_1 ? io_update_meta_s_cnt_0 : f3_entry_s_cnt; // @[loop.scala:39:9, :72:27, :73:{23,41}] assign io_f3_meta_s_cnt_0 = f3_scnt; // @[loop.scala:39:9, :73:23] wire [9:0] _f3_tag_T = io_f2_req_idx_0[13:4]; // @[loop.scala:39:9, :76:41] reg [9:0] f3_tag; // @[loop.scala:76:27] wire _io_f3_pred_T = ~io_f3_pred_in_0; // @[loop.scala:39:9, :83:23] assign io_f3_pred_0 = f3_entry_tag == f3_tag & f3_scnt == f3_entry_p_cnt & (&f3_entry_conf) ? _io_f3_pred_T : io_f3_pred_in_0; // @[loop.scala:39:9, :72:27, :73:23, :76:27, :78:16, :81:{24,36}, :82:{21,40,57,66}, :83:{20,23}] reg f4_fire; // @[loop.scala:88:27] reg [9:0] f4_entry_tag; // @[loop.scala:89:27] reg [2:0] f4_entry_conf; // @[loop.scala:89:27] reg [2:0] f4_entry_age; // @[loop.scala:89:27] reg [9:0] f4_entry_p_cnt; // @[loop.scala:89:27] reg [9:0] f4_entry_s_cnt; // @[loop.scala:89:27] reg [9:0] f4_tag; // @[loop.scala:90:27] reg [9:0] f4_scnt; // @[loop.scala:91:27] reg [35:0] f4_idx_REG; // @[loop.scala:92:35] reg [35:0] f4_idx; // @[loop.scala:92:27] wire [10:0] _entries_s_cnt_T = {1'h0, f4_scnt} + 11'h1; // @[loop.scala:91:27, :101:44] wire [9:0] _entries_s_cnt_T_1 = _entries_s_cnt_T[9:0]; // @[loop.scala:101:44] wire _entries_age_T = &f4_entry_age; // @[loop.scala:89:27, :102:53] wire [3:0] _entries_age_T_1 = {1'h0, f4_entry_age} + 4'h1; // @[loop.scala:89:27, :102:80] wire [2:0] _entries_age_T_2 = _entries_age_T_1[2:0]; // @[loop.scala:102:80] wire [2:0] _entries_age_T_3 = _entries_age_T ? 3'h7 : _entries_age_T_2; // @[loop.scala:102:{39,53,80}] wire [3:0] _entry_T_1 = _entry_T[3:0]; wire [9:0] tag = io_update_idx_0[13:4]; // @[loop.scala:39:9, :109:28] wire tag_match = _GEN[_entry_T_1] == tag; // @[loop.scala:66:28, :109:28, :110:31] wire ctr_match = _GEN_2[_entry_T_1] == io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :111:33] wire [9:0] wentry_tag; // @[loop.scala:112:26] wire [2:0] wentry_conf; // @[loop.scala:112:26] wire [2:0] wentry_age; // @[loop.scala:112:26] wire [9:0] wentry_p_cnt; // @[loop.scala:112:26] wire [9:0] wentry_s_cnt; // @[loop.scala:112:26] wire _T_22 = io_update_mispredict_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:{32,35}] wire _T_24 = (&_GEN_0[_entry_T_1]) & tag_match; // @[loop.scala:66:28, :110:31, :117:{24,32}] wire [3:0] _GEN_4 = {1'h0, _GEN_0[_entry_T_1]}; // @[loop.scala:66:28, :110:31, :119:36] wire [3:0] _wentry_conf_T = _GEN_4 - 4'h1; // @[loop.scala:119:36] wire [2:0] _wentry_conf_T_1 = _wentry_conf_T[2:0]; // @[loop.scala:119:36] wire _T_27 = (&_GEN_0[_entry_T_1]) & ~tag_match; // @[loop.scala:66:28, :110:31, :117:24, :122:{39,42}] wire _T_30 = (\|_GEN_0[_entry_T_1]) & tag_match & ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:{31,39,52}] wire [3:0] _wentry_conf_T_2 = _GEN_4 + 4'h1; // @[loop.scala:102:80, :119:36, :126:36] wire [2:0] _wentry_conf_T_3 = _wentry_conf_T_2[2:0]; // @[loop.scala:126:36] wire _T_34 = (\|_GEN_0[_entry_T_1]) & tag_match & ~ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:31, :130:{39,52,55}] wire _T_39 = (\|_GEN_0[_entry_T_1]) & ~tag_match & _GEN_1[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :122:42, :125:31, :136:{39,53,66}] wire _T_44 = (\|_GEN_0[_entry_T_1]) & ~tag_match & (\|_GEN_1[_entry_T_1]); // @[loop.scala:66:28, :110:31, :122:42, :125:31, :143:{39,53,66}] wire [3:0] _wentry_age_T = {1'h0, _GEN_1[_entry_T_1]} - 4'h1; // @[loop.scala:66:28, :110:31, :144:33] wire [2:0] _wentry_age_T_1 = _wentry_age_T[2:0]; // @[loop.scala:144:33] wire _T_52 = _GEN_0[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :147:31] wire _T_47 = _T_52 & tag_match & ctr_match; // @[loop.scala:110:31, :111:33, :147:{31,39,52}] wire _T_51 = _T_52 & tag_match & ~ctr_match; // @[loop.scala:110:31, :111:33, :130:55, :147:31, :153:{39,52}] wire _T_54 = _T_52 & ~tag_match; // @[loop.scala:110:31, :122:42, :147:31, :159:39] wire _GEN_5 = _T_47 \| _T_51; // @[loop.scala:112:26, :147:{39,52,66}, :153:{39,52,67}, :159:54] wire _GEN_6 = _T_30 \| _T_34; // @[loop.scala:112:26, :125:{39,52,66}, :130:{39,52,67}, :136:75] assign wentry_tag = ~_T_22 \| _T_24 \| _T_27 \| _GEN_6 \| ~(_T_39 \| ~(_T_44 \| _GEN_5 \| ~_T_54)) ? _GEN[_entry_T_1] : tag; // @[loop.scala:66:28, :109:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:66, :130:67, :136:{39,53,75}, :137:22, :143:{39,53,75}, :147:66, :153:67, :159:{39,54}] assign wentry_conf = _T_22 ? (_T_24 ? _wentry_conf_T_1 : _T_27 ? _GEN_0[_entry_T_1] : _T_30 ? _wentry_conf_T_3 : _T_34 ? 3'h0 : _T_39 \| ~(_T_44 \| ~(_T_47 \| ~(_T_51 \| ~_T_54))) ? 3'h1 : _GEN_0[_entry_T_1]) : _GEN_0[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :119:{22,36}, :122:{39,54}, :125:{39,52,66}, :126:{22,36}, :130:{39,52,67}, :131:22, :136:{39,53,75}, :138:22, :143:{39,53,75}, :147:{39,52,66}, :148:22, :153:{39,52,67}, :159:{39,54}] wire _GEN_7 = _T_51 \| _T_54; // @[loop.scala:112:26, :153:{39,52,67}, :155:22, :159:{39,54}, :162:22] wire _GEN_8 = _T_34 \| _T_39; // @[loop.scala:112:26, :130:{39,52,67}, :136:{39,53,75}, :143:75] assign wentry_age = ~_T_22 \| _T_24 \| _T_27 \| _T_30 \| _GEN_8 ? _GEN_1[_entry_T_1] : _T_44 ? _wentry_age_T_1 : _T_47 \| _GEN_7 ? 3'h7 : _GEN_1[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :136:75, :143:{39,53,75}, :144:{20,33}, :147:{39,52,66}, :149:22, :153:67, :155:22, :159:54, :162:22] assign wentry_p_cnt = ~_T_22 \| _T_24 \| _T_27 \| _T_30 \| ~(_GEN_8 \| ~(_T_44 \| _T_47 \| ~_GEN_7)) ? _GEN_2[_entry_T_1] : io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :133:22, :136:75, :140:22, :143:{39,53,75}, :147:{39,52,66}, :153:67, :155:22, :159:54, :162:22] wire _T_58 = io_update_repair_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:35, :168:35] wire _T_62 = tag_match & ~(f4_fire & io_update_idx_0 == f4_idx); // @[loop.scala:39:9, :88:27, :92:27, :110:31, :169:{23,26,36,53}] assign wentry_s_cnt = _T_22 ? (_T_24 \| ~(_T_27 \| ~(_GEN_6 \| _T_39 \| ~(_T_44 \| ~(_GEN_5 \| _T_54)))) ? 10'h0 : _GEN_3[_entry_T_1]) : _T_58 & _T_62 ? io_update_meta_s_cnt_0 : _GEN_3[_entry_T_1]; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :118:22, :122:{39,54}, :125:66, :127:22, :130:67, :132:22, :136:{39,53,75}, :139:22, :143:{39,53,75}, :147:66, :150:22, :153:67, :156:22, :159:{39,54}, :163:22, :168:{35,52}, :169:{23,66}, :170:22] wire _T_12 = f4_scnt == f4_entry_p_cnt & (&f4_entry_conf); // @[loop.scala:89:27, :91:27, :97:{23,42,59}] wire _GEN_9 = f4_fire & f4_entry_tag == f4_tag; // @[loop.scala:65:22, :88:27, :89:27, :90:27, :95:20, :96:{26,38}, :97:68] always @(posedge clock) begin // @[loop.scala:39:9] if (reset) begin // @[loop.scala:39:9] doing_reset <= 1'h1; // @[loop.scala:59:30] reset_idx <= 4'h0; // @[loop.scala:60:28] end else begin // @[loop.scala:39:9] doing_reset <= reset_idx != 4'hF & doing_reset; // @[loop.scala:59:30, :60:28, :62:{21,38,52}] reset_idx <= _reset_idx_T_1; // @[loop.scala:60:28, :61:28] end if (doing_reset & reset_idx == 4'h0) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_0_tag <= 10'h0; // @[loop.scala:65:22] entries_0_conf <= 3'h0; // @[loop.scala:65:22] entries_0_age <= 3'h0; // @[loop.scala:65:22] entries_0_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h0 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h0) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_0_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_0_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_0_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_0_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_0_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :98:33] entries_0_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :99:33] entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :102:33] entries_0_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :101:33] entries_0_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h1) begin // @[loop.scala:59:30, :60:28, :102:80, :114:49, :175:24, :176:26] entries_1_tag <= 10'h0; // @[loop.scala:65:22] entries_1_conf <= 3'h0; // @[loop.scala:65:22] entries_1_age <= 3'h0; // @[loop.scala:65:22] entries_1_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h1 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h1) begin // @[loop.scala:39:9, :65:22, :95:20, :102:80, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_1_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_1_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_1_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_1_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_1_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :98:33, :102:80] entries_1_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :99:33, :102:80] entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :102:{33,80}] entries_1_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :101:33, :102:80] entries_1_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h2) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_2_tag <= 10'h0; // @[loop.scala:65:22] entries_2_conf <= 3'h0; // @[loop.scala:65:22] entries_2_age <= 3'h0; // @[loop.scala:65:22] entries_2_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h2 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h2) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_2_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_2_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_2_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_2_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_2_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :98:33] entries_2_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :99:33] entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :102:33] entries_2_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :101:33] entries_2_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h3) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_3_tag <= 10'h0; // @[loop.scala:65:22] entries_3_conf <= 3'h0; // @[loop.scala:65:22] entries_3_age <= 3'h0; // @[loop.scala:65:22] entries_3_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h3 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h3) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_3_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_3_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_3_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_3_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_3_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :98:33] entries_3_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :99:33] entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :102:33] entries_3_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :101:33] entries_3_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h4) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_4_tag <= 10'h0; // @[loop.scala:65:22] entries_4_conf <= 3'h0; // @[loop.scala:65:22] entries_4_age <= 3'h0; // @[loop.scala:65:22] entries_4_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h4 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h4) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_4_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_4_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_4_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_4_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_4_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :98:33] entries_4_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :99:33] entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :102:33] entries_4_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :101:33] entries_4_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h5) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_5_tag <= 10'h0; // @[loop.scala:65:22] entries_5_conf <= 3'h0; // @[loop.scala:65:22] entries_5_age <= 3'h0; // @[loop.scala:65:22] entries_5_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h5 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h5) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_5_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_5_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_5_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_5_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_5_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :98:33] entries_5_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :99:33] entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :102:33] entries_5_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :101:33] entries_5_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h6) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_6_tag <= 10'h0; // @[loop.scala:65:22] entries_6_conf <= 3'h0; // @[loop.scala:65:22] entries_6_age <= 3'h0; // @[loop.scala:65:22] entries_6_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h6 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h6) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_6_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_6_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_6_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_6_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_6_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :98:33] entries_6_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :99:33] entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :102:33] entries_6_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :101:33] entries_6_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h7) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_7_tag <= 10'h0; // @[loop.scala:65:22] entries_7_conf <= 3'h0; // @[loop.scala:65:22] entries_7_age <= 3'h0; // @[loop.scala:65:22] entries_7_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h7 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h7) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_7_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_7_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_7_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_7_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_7_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :98:33] entries_7_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :99:33] entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :102:33] entries_7_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :101:33] entries_7_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h8) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_8_tag <= 10'h0; // @[loop.scala:65:22] entries_8_conf <= 3'h0; // @[loop.scala:65:22] entries_8_age <= 3'h0; // @[loop.scala:65:22] entries_8_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h8 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h8) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_8_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_8_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_8_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_8_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_8_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :98:33] entries_8_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :99:33] entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :102:33] entries_8_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :101:33] entries_8_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'h9) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_9_tag <= 10'h0; // @[loop.scala:65:22] entries_9_conf <= 3'h0; // @[loop.scala:65:22] entries_9_age <= 3'h0; // @[loop.scala:65:22] entries_9_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'h9 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h9) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_9_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_9_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_9_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_9_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_9_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :98:33] entries_9_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :99:33] entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :102:33] entries_9_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :101:33] entries_9_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hA) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_10_tag <= 10'h0; // @[loop.scala:65:22] entries_10_conf <= 3'h0; // @[loop.scala:65:22] entries_10_age <= 3'h0; // @[loop.scala:65:22] entries_10_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hA : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hA) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_10_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_10_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_10_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_10_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_10_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :98:33] entries_10_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :99:33] entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :102:33] entries_10_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :101:33] entries_10_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hB) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_11_tag <= 10'h0; // @[loop.scala:65:22] entries_11_conf <= 3'h0; // @[loop.scala:65:22] entries_11_age <= 3'h0; // @[loop.scala:65:22] entries_11_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hB : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hB) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_11_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_11_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_11_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_11_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_11_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :98:33] entries_11_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :99:33] entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :102:33] entries_11_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :101:33] entries_11_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hC) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_12_tag <= 10'h0; // @[loop.scala:65:22] entries_12_conf <= 3'h0; // @[loop.scala:65:22] entries_12_age <= 3'h0; // @[loop.scala:65:22] entries_12_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hC : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hC) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_12_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_12_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_12_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_12_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_12_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :98:33] entries_12_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :99:33] entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :102:33] entries_12_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :101:33] entries_12_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hD) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_13_tag <= 10'h0; // @[loop.scala:65:22] entries_13_conf <= 3'h0; // @[loop.scala:65:22] entries_13_age <= 3'h0; // @[loop.scala:65:22] entries_13_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hD : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hD) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_13_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_13_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_13_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_13_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_13_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :98:33] entries_13_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :99:33] entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :102:33] entries_13_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :101:33] entries_13_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & reset_idx == 4'hE) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_14_tag <= 10'h0; // @[loop.scala:65:22] entries_14_conf <= 3'h0; // @[loop.scala:65:22] entries_14_age <= 3'h0; // @[loop.scala:65:22] entries_14_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? io_update_idx_0[3:0] == 4'hE : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hE) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_14_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_14_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_14_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_14_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_14_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :98:33] entries_14_age <= 3'h7; // @[loop.scala:65:22] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :99:33] entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :102:33] entries_14_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :101:33] entries_14_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end if (doing_reset & (&reset_idx)) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26] entries_15_tag <= 10'h0; // @[loop.scala:65:22] entries_15_conf <= 3'h0; // @[loop.scala:65:22] entries_15_age <= 3'h0; // @[loop.scala:65:22] entries_15_p_cnt <= 10'h0; // @[loop.scala:65:22] entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22] end else if (_T_22 ? (&(io_update_idx_0[3:0])) : _T_58 & _T_62 & (&(io_update_idx_0[3:0]))) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32] entries_15_tag <= wentry_tag; // @[loop.scala:65:22, :112:26] entries_15_conf <= wentry_conf; // @[loop.scala:65:22, :112:26] entries_15_age <= wentry_age; // @[loop.scala:65:22, :112:26] entries_15_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26] entries_15_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26] end else if (_GEN_9) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68] if (_T_12) begin // @[loop.scala:97:42] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :98:33] entries_15_age <= 3'h7; // @[loop.scala:65:22] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :99:33] entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22] end else begin // @[loop.scala:97:42] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :102:33] entries_15_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39] if (&(f4_idx[3:0])) // @[loop.scala:92:27, :101:33] entries_15_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44] end end f3_entry_tag <= f2_entry_tag; // @[loop.scala:66:28, :72:27] f3_entry_conf <= f2_entry_conf; // @[loop.scala:66:28, :72:27] f3_entry_age <= f2_entry_age; // @[loop.scala:66:28, :72:27] f3_entry_p_cnt <= f2_entry_p_cnt; // @[loop.scala:66:28, :72:27] f3_entry_s_cnt <= f2_entry_s_cnt; // @[loop.scala:66:28, :72:27] f3_scnt_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :73:69] f3_tag <= _f3_tag_T; // @[loop.scala:76:{27,41}] f4_fire <= io_f3_req_fire_0; // @[loop.scala:39:9, :88:27] f4_entry_tag <= f3_entry_tag; // @[loop.scala:72:27, :89:27] f4_entry_conf <= f3_entry_conf; // @[loop.scala:72:27, :89:27] f4_entry_age <= f3_entry_age; // @[loop.scala:72:27, :89:27] f4_entry_p_cnt <= f3_entry_p_cnt; // @[loop.scala:72:27, :89:27] f4_entry_s_cnt <= f3_entry_s_cnt; // @[loop.scala:72:27, :89:27] f4_tag <= f3_tag; // @[loop.scala:76:27, :90:27] f4_scnt <= f3_scnt; // @[loop.scala:73:23, :91:27] f4_idx_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :92:35] f4_idx <= f4_idx_REG; // @[loop.scala:92:{27,35}] always @(posedge) assign io_f3_pred = io_f3_pred_0; // @[loop.scala:39:9] assign io_f3_meta_s_cnt = io_f3_meta_s_cnt_0; // @[loop.scala:39:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_145( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_401 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File PE.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle { val dataflow = UInt(1.W) // TODO make this an Enum val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)? val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats } class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module { import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(inputType) val in_c = Input(cType) val out_d = Output(dType) }) io.out_d := io.in_c.mac(io.in_a, io.in_b) } // TODO update documentation /** * A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh. * @param width Data width of operands / class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int) (implicit ev: Arithmetic[T]) extends Module { // Debugging variables import ev._ val io = IO(new Bundle { val in_a = Input(inputType) val in_b = Input(outputType) val in_d = Input(outputType) val out_a = Output(inputType) val out_b = Output(outputType) val out_c = Output(outputType) val in_control = Input(new PEControl(accType)) val out_control = Output(new PEControl(accType)) val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W)) val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W)) val in_last = Input(Bool()) val out_last = Output(Bool()) val in_valid = Input(Bool()) val out_valid = Output(Bool()) val bad_dataflow = Output(Bool()) }) val cType = if (df == Dataflow.WS) inputType else accType // When creating PEs that support multiple dataflows, the // elaboration/synthesis tools often fail to consolidate and de-duplicate // MAC units. To force mac circuitry to be re-used, we create a "mac_unit" // module here which just performs a single MAC operation val mac_unit = Module(new MacUnit(inputType, if (df == Dataflow.WS) outputType else accType, outputType)) val a = io.in_a val b = io.in_b val d = io.in_d val c1 = Reg(cType) val c2 = Reg(cType) val dataflow = io.in_control.dataflow val prop = io.in_control.propagate val shift = io.in_control.shift val id = io.in_id val last = io.in_last val valid = io.in_valid io.out_a := a io.out_control.dataflow := dataflow io.out_control.propagate := prop io.out_control.shift := shift io.out_id := id io.out_last := last io.out_valid := valid mac_unit.io.in_a := a val last_s = RegEnable(prop, valid) val flip = last_s =/= prop val shift_offset = Mux(flip, shift, 0.U) // Which dataflow are we using? val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W) val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W) // Is c1 being computed on, or propagated forward (in the output-stationary dataflow)? val COMPUTE = 0.U(1.W) val PROPAGATE = 1.U(1.W) io.bad_dataflow := false.B when ((df == Dataflow.OS).B \|\| ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 c2 := mac_unit.io.out_d c1 := d.withWidthOf(cType) }.otherwise { io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType) io.out_b := b mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c1 c1 := mac_unit.io.out_d c2 := d.withWidthOf(cType) } }.elsewhen ((df == Dataflow.WS).B \|\| ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) { when(prop === PROPAGATE) { io.out_c := c1 mac_unit.io.in_b := c2.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c1 := d }.otherwise { io.out_c := c2 mac_unit.io.in_b := c1.asTypeOf(inputType) mac_unit.io.in_c := b io.out_b := mac_unit.io.out_d c2 := d } }.otherwise { io.bad_dataflow := true.B //assert(false.B, "unknown dataflow") io.out_c := DontCare io.out_b := DontCare mac_unit.io.in_b := b.asTypeOf(inputType) mac_unit.io.in_c := c2 } when (!valid) { c1 := c1 c2 := c2 mac_unit.io.in_b := DontCare mac_unit.io.in_c := DontCare } } File Arithmetic.scala: // A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own: // implicit MyTypeArithmetic extends Arithmetic[MyType] { ... } package gemmini import chisel3._ import chisel3.util._ import hardfloat._ // Bundles that represent the raw bits of custom datatypes case class Float(expWidth: Int, sigWidth: Int) extends Bundle { val bits = UInt((expWidth + sigWidth).W) val bias: Int = (1 << (expWidth-1)) - 1 } case class DummySInt(w: Int) extends Bundle { val bits = UInt(w.W) def dontCare: DummySInt = { val o = Wire(new DummySInt(w)) o.bits := 0.U o } } // The Arithmetic typeclass which implements various arithmetic operations on custom datatypes abstract class Arithmetic[T <: Data] { implicit def cast(t: T): ArithmeticOps[T] } abstract class ArithmeticOps[T <: Data](self: T) { def (t: T): T def mac(m1: T, m2: T): T // Returns (m1 * m2 + self) def +(t: T): T def -(t: T): T def >>(u: UInt): T // This is a rounding shift! Rounds away from 0 def >(t: T): Bool def identity: T def withWidthOf(t: T): T def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates def relu: T def zero: T def minimum: T // Optional parameters, which only need to be defined if you want to enable various optimizations for transformers def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None def mult_with_reciprocal[U <: Data](reciprocal: U) = self } object Arithmetic { implicit object UIntArithmetic extends Arithmetic[UInt] { override implicit def cast(self: UInt) = new ArithmeticOps(self) { override def (t: UInt) = self t override def mac(m1: UInt, m2: UInt) = m1 * m2 + self override def +(t: UInt) = self + t override def -(t: UInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = point_five & (zeros \| ones_digit) (self >> u).asUInt + r } override def >(t: UInt): Bool = self > t override def withWidthOf(t: UInt) = self.asTypeOf(t) override def clippedToWidthOf(t: UInt) = { val sat = ((1 << (t.getWidth-1))-1).U Mux(self > sat, sat, self)(t.getWidth-1, 0) } override def relu: UInt = self override def zero: UInt = 0.U override def identity: UInt = 1.U override def minimum: UInt = 0.U } } implicit object SIntArithmetic extends Arithmetic[SInt] { override implicit def cast(self: SInt) = new ArithmeticOps(self) { override def (t: SInt) = self t override def mac(m1: SInt, m2: SInt) = m1 * m2 + self override def +(t: SInt) = self + t override def -(t: SInt) = self - t override def >>(u: UInt) = { // The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm // TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here? val point_five = Mux(u === 0.U, 0.U, self(u - 1.U)) val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U val ones_digit = self(u) val r = (point_five & (zeros \| ones_digit)).asBool (self >> u).asSInt + Mux(r, 1.S, 0.S) } override def >(t: SInt): Bool = self > t override def withWidthOf(t: SInt) = { if (self.getWidth >= t.getWidth) self(t.getWidth-1, 0).asSInt else { val sign_bits = t.getWidth - self.getWidth val sign = self(self.getWidth-1) Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t) } } override def clippedToWidthOf(t: SInt): SInt = { val maxsat = ((1 << (t.getWidth-1))-1).S val minsat = (-(1 << (t.getWidth-1))).S MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt } override def relu: SInt = Mux(self >= 0.S, self, 0.S) override def zero: SInt = 0.S override def identity: SInt = 1.S override def minimum: SInt = (-(1 << (self.getWidth-1))).S override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(denom_t.cloneType)) val output = Wire(Decoupled(self.cloneType)) // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def sin_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def uin_to_float(x: UInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := x in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = sin_to_float(self) val denom_rec = uin_to_float(input.bits) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := self_rec divider.io.b := denom_rec divider.io.roundingMode := consts.round_minMag divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := float_to_in(divider.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = { // TODO this uses a floating point divider, but we should use an integer divider instead val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(self.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider val expWidth = log2Up(self.getWidth) + 1 val sigWidth = self.getWidth def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) // Instantiate the hardloat sqrt val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0)) input.ready := sqrter.io.inReady sqrter.io.inValid := input.valid sqrter.io.sqrtOp := true.B sqrter.io.a := self_rec sqrter.io.b := DontCare sqrter.io.roundingMode := consts.round_minMag sqrter.io.detectTininess := consts.tininess_afterRounding output.valid := sqrter.io.outValid_sqrt output.bits := float_to_in(sqrter.io.out) assert(!output.valid \|\| output.ready) Some((input, output)) } override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match { case Float(expWidth, sigWidth) => val input = Wire(Decoupled(UInt(0.W))) val output = Wire(Decoupled(u.cloneType)) input.bits := DontCare // We translate our integer to floating-point form so that we can use the hardfloat divider def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } val self_rec = in_to_float(self) val one_rec = in_to_float(1.S) // Instantiate the hardloat divider val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options)) input.ready := divider.io.inReady divider.io.inValid := input.valid divider.io.sqrtOp := false.B divider.io.a := one_rec divider.io.b := self_rec divider.io.roundingMode := consts.round_near_even divider.io.detectTininess := consts.tininess_afterRounding output.valid := divider.io.outValid_div output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u) assert(!output.valid \|\| output.ready) Some((input, output)) case _ => None } override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match { case recip @ Float(expWidth, sigWidth) => def in_to_float(x: SInt) = { val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth)) in_to_rec_fn.io.signedIn := true.B in_to_rec_fn.io.in := x.asUInt in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding in_to_rec_fn.io.out } def float_to_in(x: UInt) = { val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth)) rec_fn_to_in.io.signedOut := true.B rec_fn_to_in.io.in := x rec_fn_to_in.io.roundingMode := consts.round_minMag rec_fn_to_in.io.out.asSInt } val self_rec = in_to_float(self) val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits) // Instantiate the hardloat divider val muladder = Module(new MulRecFN(expWidth, sigWidth)) muladder.io.roundingMode := consts.round_near_even muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := reciprocal_rec float_to_in(muladder.io.out) case _ => self } } } implicit object FloatArithmetic extends Arithmetic[Float] { // TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) { override def (t: Float): Float = { val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := t_rec_resized val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def mac(m1: Float, m2: Float): Float = { // Recode all operands val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits) val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize m1 to self's width val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth)) m1_resizer.io.in := m1_rec m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m1_resizer.io.detectTininess := consts.tininess_afterRounding val m1_rec_resized = m1_resizer.io.out // Resize m2 to self's width val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth)) m2_resizer.io.in := m2_rec m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag m2_resizer.io.detectTininess := consts.tininess_afterRounding val m2_rec_resized = m2_resizer.io.out // Perform multiply-add val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := m1_rec_resized muladder.io.b := m2_rec_resized muladder.io.c := self_rec // Convert result to standard format // TODO remove these intermediate recodings val out = Wire(Float(self.expWidth, self.sigWidth)) out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) out } override def +(t: Float): Float = { require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Generate 1 as a float val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth)) in_to_rec_fn.io.signedIn := false.B in_to_rec_fn.io.in := 1.U in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding val one_rec = in_to_rec_fn.io.out // Resize t val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out // Perform addition val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth)) muladder.io.op := 0.U muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := t_rec_resized muladder.io.b := one_rec muladder.io.c := self_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def -(t: Float): Float = { val t_sgn = t.bits(t.getWidth-1) val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t) self + neg_t } override def >>(u: UInt): Float = { // Recode self val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Get 2^(-u) as a recoded float val shift_exp = Wire(UInt(self.expWidth.W)) shift_exp := self.bias.U - u val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W)) val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn) assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported") // Multiply self and 2^(-u) val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth)) muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag muladder.io.detectTininess := consts.tininess_afterRounding muladder.io.a := self_rec muladder.io.b := shift_rec val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out) result } override def >(t: Float): Bool = { // Recode all operands val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits) val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) // Resize t to self's width val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth)) t_resizer.io.in := t_rec t_resizer.io.roundingMode := consts.round_near_even t_resizer.io.detectTininess := consts.tininess_afterRounding val t_rec_resized = t_resizer.io.out val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth)) comparator.io.a := self_rec comparator.io.b := t_rec_resized comparator.io.signaling := false.B comparator.io.gt } override def withWidthOf(t: Float): Float = { val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def clippedToWidthOf(t: Float): Float = { // TODO check for overflow. Right now, we just assume that overflow doesn't happen val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits) val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth)) resizer.io.in := self_rec resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag resizer.io.detectTininess := consts.tininess_afterRounding val result = Wire(Float(t.expWidth, t.sigWidth)) result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out) result } override def relu: Float = { val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits) val result = Wire(Float(self.expWidth, self.sigWidth)) result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits) result } override def zero: Float = 0.U.asTypeOf(self) override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self) } } implicit object DummySIntArithmetic extends Arithmetic[DummySInt] { override implicit def cast(self: DummySInt) = new ArithmeticOps(self) { override def (t: DummySInt) = self.dontCare override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare override def +(t: DummySInt) = self.dontCare override def -(t: DummySInt) = self.dontCare override def >>(t: UInt) = self.dontCare override def >(t: DummySInt): Bool = false.B override def identity = self.dontCare override def withWidthOf(t: DummySInt) = self.dontCare override def clippedToWidthOf(t: DummySInt) = self.dontCare override def relu = self.dontCare override def zero = self.dontCare override def minimum: DummySInt = self.dontCare } } }	module PE_330( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = \|_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros \| io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = \|_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 \| io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 \| io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_74 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File tracegen.scala: package boom.v4.lsu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy.{SimpleDevice, LazyModule, BundleBridgeSource} import freechips.rocketchip.prci.{SynchronousCrossing, ClockCrossingType} import freechips.rocketchip.groundtest._ import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket.constants.{MemoryOpConstants} import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink.{TLInwardNode, TLIdentityNode, TLOutwardNode, TLTempNode} import freechips.rocketchip.interrupts._ import freechips.rocketchip.subsystem._ import boom.v4.lsu.{BoomNonBlockingDCache, LSU, LSUCoreIO} import boom.v4.common.{BoomTileParams, MicroOp, BoomCoreParams, BoomModule} import freechips.rocketchip.prci.ClockSinkParameters class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p) with MemoryOpConstants { val io = IO(new Bundle { val lsu = Flipped(new LSUCoreIO) val tracegen = Flipped(new HellaCacheIO) }) io.lsu := DontCare io.lsu.tsc_reg := 0.U(1.W) val rob_sz = numRobEntries val rob = Reg(Vec(rob_sz, new HellaCacheReq)) val rob_respd = RegInit(VecInit((~(0.U(rob_sz.W))).asBools)) val rob_uop = Reg(Vec(rob_sz, new MicroOp)) val rob_bsy = RegInit(VecInit(0.U(rob_sz.W).asBools)) val rob_head = RegInit(0.U(log2Up(rob_sz).W)) val rob_tail = RegInit(0.U(log2Up(rob_sz).W)) val rob_wait_till_empty = RegInit(false.B) val ready_for_amo = rob_tail === rob_head && io.lsu.fencei_rdy when (ready_for_amo) { rob_wait_till_empty := false.B } def WrapInc(idx: UInt, max: Int): UInt = { Mux(idx === (max-1).U, 0.U, idx + 1.U) } io.tracegen := DontCare io.tracegen.req.ready := (!rob_bsy(rob_tail) && !rob_wait_till_empty && (ready_for_amo \|\| !(isAMO(io.tracegen.req.bits.cmd) \|\| io.tracegen.req.bits.cmd === M_XLR \|\| io.tracegen.req.bits.cmd === M_XSC)) && (WrapInc(rob_tail, rob_sz) =/= rob_head) && !(io.lsu.ldq_full(0) && isRead(io.tracegen.req.bits.cmd)) && !(io.lsu.stq_full(0) && isWrite(io.tracegen.req.bits.cmd)) ) val tracegen_uop = WireInit((0.U).asTypeOf(new MicroOp)) tracegen_uop.uses_ldq := isRead(io.tracegen.req.bits.cmd) && !isWrite(io.tracegen.req.bits.cmd) tracegen_uop.uses_stq := isWrite(io.tracegen.req.bits.cmd) tracegen_uop.rob_idx := rob_tail tracegen_uop.debug_inst := io.tracegen.req.bits.tag tracegen_uop.mem_size := io.tracegen.req.bits.size tracegen_uop.mem_cmd := io.tracegen.req.bits.cmd tracegen_uop.mem_signed := io.tracegen.req.bits.signed tracegen_uop.ldq_idx := io.lsu.dis_ldq_idx(0) tracegen_uop.stq_idx := io.lsu.dis_stq_idx(0) tracegen_uop.is_amo := isAMO(io.tracegen.req.bits.cmd) \|\| io.tracegen.req.bits.cmd === M_XSC tracegen_uop.uses_ldq := isRead(io.tracegen.req.bits.cmd) && !isWrite(io.tracegen.req.bits.cmd) tracegen_uop.uses_stq := isWrite(io.tracegen.req.bits.cmd) io.lsu.dis_uops(0).valid := io.tracegen.req.fire io.lsu.dis_uops(0).bits := tracegen_uop when (io.tracegen.req.fire) { rob_tail := WrapInc(rob_tail, rob_sz) rob_bsy(rob_tail) := true.B rob_uop(rob_tail) := tracegen_uop rob_respd(rob_tail) := false.B rob(rob_tail) := io.tracegen.req.bits when ( isAMO(io.tracegen.req.bits.cmd) \|\| io.tracegen.req.bits.cmd === M_XLR \|\| io.tracegen.req.bits.cmd === M_XSC ) { rob_wait_till_empty := true.B } } io.lsu.dgen(1).valid := false.B io.lsu.dgen(1).bits := DontCare io.lsu.commit.valids(0) := (!rob_bsy(rob_head) && rob_head =/= rob_tail && rob_respd(rob_head)) io.lsu.commit.uops(0) := rob_uop(rob_head) io.lsu.commit.fflags := DontCare when (io.lsu.commit.valids(0)) { rob_head := WrapInc(rob_head, rob_sz) } when (io.lsu.clr_bsy(0).valid) { rob_bsy(io.lsu.clr_bsy(0).bits) := false.B } when (io.lsu.clr_unsafe(0).valid && rob(io.lsu.clr_unsafe(0).bits).cmd =/= M_XLR) { rob_bsy(io.lsu.clr_unsafe(0).bits) := false.B } when (io.lsu.iresp(0).valid) { rob_bsy(io.lsu.iresp(0).bits.uop.rob_idx) := false.B } assert(!io.lsu.lxcpt.valid) io.lsu.agen(0).valid := ShiftRegister(io.tracegen.req.fire, 2) io.lsu.agen(0).bits := DontCare io.lsu.agen(0).bits.uop := ShiftRegister(tracegen_uop, 2) io.lsu.agen(0).bits.data := ShiftRegister(io.tracegen.req.bits.addr, 2) io.lsu.dgen(0).valid := ShiftRegister(io.tracegen.req.fire && tracegen_uop.uses_stq, 2) io.lsu.dgen(0).bits := DontCare io.lsu.dgen(0).bits.uop := ShiftRegister(tracegen_uop, 2) io.lsu.dgen(0).bits.data := ShiftRegister(io.tracegen.req.bits.data, 2) io.tracegen.resp.valid := io.lsu.iresp(0).valid io.tracegen.resp.bits := DontCare io.tracegen.resp.bits.tag := io.lsu.iresp(0).bits.uop.debug_inst io.tracegen.resp.bits.size := io.lsu.iresp(0).bits.uop.mem_size io.tracegen.resp.bits.data := io.lsu.iresp(0).bits.data val store_resp_idx = PriorityEncoder((0 until rob_sz) map {i => !rob_respd(i) && isWrite(rob(i).cmd) }) val can_do_store_resp = ~rob_respd(store_resp_idx) && isWrite(rob(store_resp_idx).cmd) && !isRead(rob(store_resp_idx).cmd) when (can_do_store_resp && !io.lsu.iresp(0).valid) { rob_respd(store_resp_idx) := true.B io.tracegen.resp.valid := true.B io.tracegen.resp.bits.tag := rob(store_resp_idx).tag } when (io.lsu.iresp(0).valid) { rob_respd(io.lsu.iresp(0).bits.uop.rob_idx) := true.B } io.lsu.exception := false.B io.lsu.fence_dmem := false.B io.lsu.rob_pnr_idx := rob_tail io.lsu.commit_load_at_rob_head := false.B io.lsu.brupdate.b1 := (0.U).asTypeOf(new boom.v4.exu.BrUpdateMasks) io.lsu.brupdate.b2.uop := DontCare io.lsu.brupdate.b2.mispredict := false.B io.lsu.brupdate.b2.taken := false.B io.lsu.brupdate.b2.cfi_type := 0.U io.lsu.brupdate.b2.pc_sel := 0.U io.lsu.brupdate.b2.jalr_target := 0.U io.lsu.brupdate.b2.target_offset := 0.S(2.W) io.lsu.rob_head_idx := rob_head io.tracegen.ordered := ready_for_amo && io.lsu.fencei_rdy io.lsu.mcontext := 0.U(1.W) io.lsu.scontext := 0.U(1.W) } case class BoomTraceGenTileAttachParams( tileParams: BoomTraceGenParams, crossingParams: HierarchicalElementCrossingParamsLike ) extends CanAttachTile { type TileType = BoomTraceGenTile val lookup: LookupByHartIdImpl = HartsWontDeduplicate(tileParams) } case class BoomTraceGenParams( wordBits: Int, addrBits: Int, addrBag: List[BigInt], maxRequests: Int, memStart: BigInt, numGens: Int, dcache: Option[DCacheParams] = Some(DCacheParams()), tileId: Int = 0 ) extends InstantiableTileParams[BoomTraceGenTile] { def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): BoomTraceGenTile = { new BoomTraceGenTile(this, crossing, lookup) } val core = RocketCoreParams(nPMPs = 0) //TODO remove this val btb = None val icache = Some(ICacheParams()) val beuAddr = None val blockerCtrlAddr = None val name = None val traceParams = TraceGenParams(wordBits, addrBits, addrBag, maxRequests, memStart, numGens, dcache, tileId) val clockSinkParams: ClockSinkParameters = ClockSinkParameters() val baseName = "boom_l1_tracegen" val uniqueName = s"${baseName}_$tileId" } class BoomTraceGenTile private( val params: BoomTraceGenParams, crossing: ClockCrossingType, lookup: LookupByHartIdImpl, q: Parameters) extends BaseTile(params, crossing, lookup, q) with SinksExternalInterrupts with SourcesExternalNotifications { def this(params: BoomTraceGenParams, crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) = this(params, crossing.crossingType, lookup, p) val cpuDevice: SimpleDevice = new SimpleDevice("groundtest", Nil) val intOutwardNode = None val slaveNode: TLInwardNode = TLIdentityNode() val statusNode = BundleBridgeSource(() => new GroundTestStatus) val boom_params = p.alterMap(Map(TileKey -> BoomTileParams( dcache=params.dcache, core=BoomCoreParams(nPMPs=0, numLdqEntries=16, numStqEntries=16, useVM=false)))) val dcache = LazyModule(new BoomNonBlockingDCache(tileId)(boom_params)) val masterNode: TLOutwardNode = TLIdentityNode() := visibilityNode := dcache.node override lazy val module = new BoomTraceGenTileModuleImp(this) } class BoomTraceGenTileModuleImp(outer: BoomTraceGenTile) extends BaseTileModuleImp(outer){ val status = outer.statusNode.bundle val halt_and_catch_fire = None val tracegen = Module(new TraceGenerator(outer.params.traceParams)) tracegen.io.hartid := outer.hartIdSinkNode.bundle val ptw = Module(new DummyPTW(1)) val lsu = Module(new LSU()(outer.boom_params, outer.dcache.module.edge)) val boom_shim = Module(new BoomLSUShim()(outer.boom_params)) ptw.io.requestors.head <> lsu.io.ptw outer.dcache.module.io.lsu <> lsu.io.dmem boom_shim.io.tracegen <> tracegen.io.mem tracegen.io.fence_rdy := boom_shim.io.tracegen.ordered boom_shim.io.lsu <> lsu.io.core // Normally the PTW would use this port lsu.io.hellacache := DontCare lsu.io.hellacache.req.valid := false.B outer.reportCease(Some(tracegen.io.finished)) outer.reportHalt(Some(tracegen.io.timeout)) outer.reportWFI(None) status.timeout.valid := tracegen.io.timeout status.timeout.bits := 0.U status.error.valid := false.B assert(!tracegen.io.timeout, s"TraceGen tile ${outer.tileParams.tileId}: request timed out") } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) \|\| isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR \|\| cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) \|\| isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR \|\| cmd === M_PWR \|\| cmd === M_XSC \|\| isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) \|\| cmd === M_PFW \|\| cmd === M_XLR }	module BoomLSUShim( // @[tracegen.scala:19:7] input clock, // @[tracegen.scala:19:7] input reset, // @[tracegen.scala:19:7] output io_lsu_agen_0_valid, // @[tracegen.scala:21:14] output [31:0] io_lsu_agen_0_bits_uop_debug_inst, // @[tracegen.scala:21:14] output io_lsu_agen_0_bits_uop_is_amo, // @[tracegen.scala:21:14] output [4:0] io_lsu_agen_0_bits_uop_rob_idx, // @[tracegen.scala:21:14] output [3:0] io_lsu_agen_0_bits_uop_ldq_idx, // @[tracegen.scala:21:14] output [3:0] io_lsu_agen_0_bits_uop_stq_idx, // @[tracegen.scala:21:14] output [4:0] io_lsu_agen_0_bits_uop_mem_cmd, // @[tracegen.scala:21:14] output io_lsu_agen_0_bits_uop_uses_ldq, // @[tracegen.scala:21:14] output io_lsu_agen_0_bits_uop_uses_stq, // @[tracegen.scala:21:14] output [63:0] io_lsu_agen_0_bits_data, // @[tracegen.scala:21:14] output io_lsu_dgen_0_valid, // @[tracegen.scala:21:14] output [31:0] io_lsu_dgen_0_bits_uop_debug_inst, // @[tracegen.scala:21:14] output io_lsu_dgen_0_bits_uop_is_amo, // @[tracegen.scala:21:14] output [4:0] io_lsu_dgen_0_bits_uop_rob_idx, // @[tracegen.scala:21:14] output [3:0] io_lsu_dgen_0_bits_uop_ldq_idx, // @[tracegen.scala:21:14] output [3:0] io_lsu_dgen_0_bits_uop_stq_idx, // @[tracegen.scala:21:14] output [4:0] io_lsu_dgen_0_bits_uop_mem_cmd, // @[tracegen.scala:21:14] output io_lsu_dgen_0_bits_uop_uses_ldq, // @[tracegen.scala:21:14] output io_lsu_dgen_0_bits_uop_uses_stq, // @[tracegen.scala:21:14] output [63:0] io_lsu_dgen_0_bits_data, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_valid, // @[tracegen.scala:21:14] input [31:0] io_lsu_iwakeups_0_bits_uop_inst, // @[tracegen.scala:21:14] input [31:0] io_lsu_iwakeups_0_bits_uop_debug_inst, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_is_rvc, // @[tracegen.scala:21:14] input [33:0] io_lsu_iwakeups_0_bits_uop_debug_pc, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_iq_type_0, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_iq_type_1, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_iq_type_2, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_iq_type_3, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fu_code_0, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fu_code_1, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fu_code_2, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fu_code_3, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fu_code_4, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fu_code_5, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fu_code_6, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fu_code_7, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fu_code_8, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fu_code_9, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_iw_issued, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_iw_issued_partial_agen, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_iw_issued_partial_dgen, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_iw_p1_speculative_child, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_iw_p2_speculative_child, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_iw_p1_bypass_hint, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_iw_p2_bypass_hint, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_iw_p3_bypass_hint, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_dis_col_sel, // @[tracegen.scala:21:14] input [3:0] io_lsu_iwakeups_0_bits_uop_br_mask, // @[tracegen.scala:21:14] input [1:0] io_lsu_iwakeups_0_bits_uop_br_tag, // @[tracegen.scala:21:14] input [3:0] io_lsu_iwakeups_0_bits_uop_br_type, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_is_sfb, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_is_fence, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_is_fencei, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_is_sfence, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_is_amo, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_is_eret, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_is_sys_pc2epc, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_is_rocc, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_is_mov, // @[tracegen.scala:21:14] input [3:0] io_lsu_iwakeups_0_bits_uop_ftq_idx, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_edge_inst, // @[tracegen.scala:21:14] input [5:0] io_lsu_iwakeups_0_bits_uop_pc_lob, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_taken, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_imm_rename, // @[tracegen.scala:21:14] input [2:0] io_lsu_iwakeups_0_bits_uop_imm_sel, // @[tracegen.scala:21:14] input [4:0] io_lsu_iwakeups_0_bits_uop_pimm, // @[tracegen.scala:21:14] input [19:0] io_lsu_iwakeups_0_bits_uop_imm_packed, // @[tracegen.scala:21:14] input [1:0] io_lsu_iwakeups_0_bits_uop_op1_sel, // @[tracegen.scala:21:14] input [2:0] io_lsu_iwakeups_0_bits_uop_op2_sel, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_ldst, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_wen, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren1, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren2, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren3, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_swap12, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_swap23, // @[tracegen.scala:21:14] input [1:0] io_lsu_iwakeups_0_bits_uop_fp_ctrl_typeTagIn, // @[tracegen.scala:21:14] input [1:0] io_lsu_iwakeups_0_bits_uop_fp_ctrl_typeTagOut, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_fromint, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_toint, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_fastpipe, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_fma, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_div, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_sqrt, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_wflags, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_vec, // @[tracegen.scala:21:14] input [4:0] io_lsu_iwakeups_0_bits_uop_rob_idx, // @[tracegen.scala:21:14] input [3:0] io_lsu_iwakeups_0_bits_uop_ldq_idx, // @[tracegen.scala:21:14] input [3:0] io_lsu_iwakeups_0_bits_uop_stq_idx, // @[tracegen.scala:21:14] input [1:0] io_lsu_iwakeups_0_bits_uop_rxq_idx, // @[tracegen.scala:21:14] input [5:0] io_lsu_iwakeups_0_bits_uop_pdst, // @[tracegen.scala:21:14] input [5:0] io_lsu_iwakeups_0_bits_uop_prs1, // @[tracegen.scala:21:14] input [5:0] io_lsu_iwakeups_0_bits_uop_prs2, // @[tracegen.scala:21:14] input [5:0] io_lsu_iwakeups_0_bits_uop_prs3, // @[tracegen.scala:21:14] input [3:0] io_lsu_iwakeups_0_bits_uop_ppred, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_prs1_busy, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_prs2_busy, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_prs3_busy, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_ppred_busy, // @[tracegen.scala:21:14] input [5:0] io_lsu_iwakeups_0_bits_uop_stale_pdst, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_exception, // @[tracegen.scala:21:14] input [63:0] io_lsu_iwakeups_0_bits_uop_exc_cause, // @[tracegen.scala:21:14] input [4:0] io_lsu_iwakeups_0_bits_uop_mem_cmd, // @[tracegen.scala:21:14] input [1:0] io_lsu_iwakeups_0_bits_uop_mem_size, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_mem_signed, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_uses_ldq, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_uses_stq, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_is_unique, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_flush_on_commit, // @[tracegen.scala:21:14] input [2:0] io_lsu_iwakeups_0_bits_uop_csr_cmd, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_ldst_is_rs1, // @[tracegen.scala:21:14] input [5:0] io_lsu_iwakeups_0_bits_uop_ldst, // @[tracegen.scala:21:14] input [5:0] io_lsu_iwakeups_0_bits_uop_lrs1, // @[tracegen.scala:21:14] input [5:0] io_lsu_iwakeups_0_bits_uop_lrs2, // @[tracegen.scala:21:14] input [5:0] io_lsu_iwakeups_0_bits_uop_lrs3, // @[tracegen.scala:21:14] input [1:0] io_lsu_iwakeups_0_bits_uop_dst_rtype, // @[tracegen.scala:21:14] input [1:0] io_lsu_iwakeups_0_bits_uop_lrs1_rtype, // @[tracegen.scala:21:14] input [1:0] io_lsu_iwakeups_0_bits_uop_lrs2_rtype, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_frs3_en, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fcn_dw, // @[tracegen.scala:21:14] input [4:0] io_lsu_iwakeups_0_bits_uop_fcn_op, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_fp_val, // @[tracegen.scala:21:14] input [2:0] io_lsu_iwakeups_0_bits_uop_fp_rm, // @[tracegen.scala:21:14] input [1:0] io_lsu_iwakeups_0_bits_uop_fp_typ, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_xcpt_pf_if, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_xcpt_ae_if, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_xcpt_ma_if, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_bp_debug_if, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_uop_bp_xcpt_if, // @[tracegen.scala:21:14] input [2:0] io_lsu_iwakeups_0_bits_uop_debug_fsrc, // @[tracegen.scala:21:14] input [2:0] io_lsu_iwakeups_0_bits_uop_debug_tsrc, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_bypassable, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_speculative_mask, // @[tracegen.scala:21:14] input io_lsu_iwakeups_0_bits_rebusy, // @[tracegen.scala:21:14] input io_lsu_iresp_0_valid, // @[tracegen.scala:21:14] input [31:0] io_lsu_iresp_0_bits_uop_inst, // @[tracegen.scala:21:14] input [31:0] io_lsu_iresp_0_bits_uop_debug_inst, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_is_rvc, // @[tracegen.scala:21:14] input [33:0] io_lsu_iresp_0_bits_uop_debug_pc, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_iq_type_0, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_iq_type_1, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_iq_type_2, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_iq_type_3, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fu_code_0, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fu_code_1, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fu_code_2, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fu_code_3, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fu_code_4, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fu_code_5, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fu_code_6, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fu_code_7, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fu_code_8, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fu_code_9, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_iw_issued, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_iw_issued_partial_agen, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_iw_issued_partial_dgen, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_iw_p1_speculative_child, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_iw_p2_speculative_child, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_iw_p1_bypass_hint, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_iw_p2_bypass_hint, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_iw_p3_bypass_hint, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_dis_col_sel, // @[tracegen.scala:21:14] input [3:0] io_lsu_iresp_0_bits_uop_br_mask, // @[tracegen.scala:21:14] input [1:0] io_lsu_iresp_0_bits_uop_br_tag, // @[tracegen.scala:21:14] input [3:0] io_lsu_iresp_0_bits_uop_br_type, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_is_sfb, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_is_fence, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_is_fencei, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_is_sfence, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_is_amo, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_is_eret, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_is_sys_pc2epc, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_is_rocc, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_is_mov, // @[tracegen.scala:21:14] input [3:0] io_lsu_iresp_0_bits_uop_ftq_idx, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_edge_inst, // @[tracegen.scala:21:14] input [5:0] io_lsu_iresp_0_bits_uop_pc_lob, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_taken, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_imm_rename, // @[tracegen.scala:21:14] input [2:0] io_lsu_iresp_0_bits_uop_imm_sel, // @[tracegen.scala:21:14] input [4:0] io_lsu_iresp_0_bits_uop_pimm, // @[tracegen.scala:21:14] input [19:0] io_lsu_iresp_0_bits_uop_imm_packed, // @[tracegen.scala:21:14] input [1:0] io_lsu_iresp_0_bits_uop_op1_sel, // @[tracegen.scala:21:14] input [2:0] io_lsu_iresp_0_bits_uop_op2_sel, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_ldst, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_wen, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_ren1, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_ren2, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_ren3, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_swap12, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_swap23, // @[tracegen.scala:21:14] input [1:0] io_lsu_iresp_0_bits_uop_fp_ctrl_typeTagIn, // @[tracegen.scala:21:14] input [1:0] io_lsu_iresp_0_bits_uop_fp_ctrl_typeTagOut, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_fromint, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_toint, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_fastpipe, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_fma, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_div, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_sqrt, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_wflags, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_vec, // @[tracegen.scala:21:14] input [4:0] io_lsu_iresp_0_bits_uop_rob_idx, // @[tracegen.scala:21:14] input [3:0] io_lsu_iresp_0_bits_uop_ldq_idx, // @[tracegen.scala:21:14] input [3:0] io_lsu_iresp_0_bits_uop_stq_idx, // @[tracegen.scala:21:14] input [1:0] io_lsu_iresp_0_bits_uop_rxq_idx, // @[tracegen.scala:21:14] input [5:0] io_lsu_iresp_0_bits_uop_pdst, // @[tracegen.scala:21:14] input [5:0] io_lsu_iresp_0_bits_uop_prs1, // @[tracegen.scala:21:14] input [5:0] io_lsu_iresp_0_bits_uop_prs2, // @[tracegen.scala:21:14] input [5:0] io_lsu_iresp_0_bits_uop_prs3, // @[tracegen.scala:21:14] input [3:0] io_lsu_iresp_0_bits_uop_ppred, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_prs1_busy, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_prs2_busy, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_prs3_busy, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_ppred_busy, // @[tracegen.scala:21:14] input [5:0] io_lsu_iresp_0_bits_uop_stale_pdst, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_exception, // @[tracegen.scala:21:14] input [63:0] io_lsu_iresp_0_bits_uop_exc_cause, // @[tracegen.scala:21:14] input [4:0] io_lsu_iresp_0_bits_uop_mem_cmd, // @[tracegen.scala:21:14] input [1:0] io_lsu_iresp_0_bits_uop_mem_size, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_mem_signed, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_uses_ldq, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_uses_stq, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_is_unique, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_flush_on_commit, // @[tracegen.scala:21:14] input [2:0] io_lsu_iresp_0_bits_uop_csr_cmd, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_ldst_is_rs1, // @[tracegen.scala:21:14] input [5:0] io_lsu_iresp_0_bits_uop_ldst, // @[tracegen.scala:21:14] input [5:0] io_lsu_iresp_0_bits_uop_lrs1, // @[tracegen.scala:21:14] input [5:0] io_lsu_iresp_0_bits_uop_lrs2, // @[tracegen.scala:21:14] input [5:0] io_lsu_iresp_0_bits_uop_lrs3, // @[tracegen.scala:21:14] input [1:0] io_lsu_iresp_0_bits_uop_dst_rtype, // @[tracegen.scala:21:14] input [1:0] io_lsu_iresp_0_bits_uop_lrs1_rtype, // @[tracegen.scala:21:14] input [1:0] io_lsu_iresp_0_bits_uop_lrs2_rtype, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_frs3_en, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fcn_dw, // @[tracegen.scala:21:14] input [4:0] io_lsu_iresp_0_bits_uop_fcn_op, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_fp_val, // @[tracegen.scala:21:14] input [2:0] io_lsu_iresp_0_bits_uop_fp_rm, // @[tracegen.scala:21:14] input [1:0] io_lsu_iresp_0_bits_uop_fp_typ, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_xcpt_pf_if, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_xcpt_ae_if, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_xcpt_ma_if, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_bp_debug_if, // @[tracegen.scala:21:14] input io_lsu_iresp_0_bits_uop_bp_xcpt_if, // @[tracegen.scala:21:14] input [2:0] io_lsu_iresp_0_bits_uop_debug_fsrc, // @[tracegen.scala:21:14] input [2:0] io_lsu_iresp_0_bits_uop_debug_tsrc, // @[tracegen.scala:21:14] input [63:0] io_lsu_iresp_0_bits_data, // @[tracegen.scala:21:14] input io_lsu_fresp_0_valid, // @[tracegen.scala:21:14] input [31:0] io_lsu_fresp_0_bits_uop_inst, // @[tracegen.scala:21:14] input [31:0] io_lsu_fresp_0_bits_uop_debug_inst, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_is_rvc, // @[tracegen.scala:21:14] input [33:0] io_lsu_fresp_0_bits_uop_debug_pc, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_iq_type_0, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_iq_type_1, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_iq_type_2, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_iq_type_3, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fu_code_0, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fu_code_1, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fu_code_2, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fu_code_3, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fu_code_4, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fu_code_5, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fu_code_6, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fu_code_7, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fu_code_8, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fu_code_9, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_iw_issued, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_iw_issued_partial_agen, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_iw_issued_partial_dgen, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_iw_p1_speculative_child, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_iw_p2_speculative_child, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_iw_p1_bypass_hint, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_iw_p2_bypass_hint, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_iw_p3_bypass_hint, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_dis_col_sel, // @[tracegen.scala:21:14] input [3:0] io_lsu_fresp_0_bits_uop_br_mask, // @[tracegen.scala:21:14] input [1:0] io_lsu_fresp_0_bits_uop_br_tag, // @[tracegen.scala:21:14] input [3:0] io_lsu_fresp_0_bits_uop_br_type, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_is_sfb, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_is_fence, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_is_fencei, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_is_sfence, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_is_amo, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_is_eret, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_is_sys_pc2epc, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_is_rocc, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_is_mov, // @[tracegen.scala:21:14] input [3:0] io_lsu_fresp_0_bits_uop_ftq_idx, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_edge_inst, // @[tracegen.scala:21:14] input [5:0] io_lsu_fresp_0_bits_uop_pc_lob, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_taken, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_imm_rename, // @[tracegen.scala:21:14] input [2:0] io_lsu_fresp_0_bits_uop_imm_sel, // @[tracegen.scala:21:14] input [4:0] io_lsu_fresp_0_bits_uop_pimm, // @[tracegen.scala:21:14] input [19:0] io_lsu_fresp_0_bits_uop_imm_packed, // @[tracegen.scala:21:14] input [1:0] io_lsu_fresp_0_bits_uop_op1_sel, // @[tracegen.scala:21:14] input [2:0] io_lsu_fresp_0_bits_uop_op2_sel, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_ldst, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_wen, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_ren1, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_ren2, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_ren3, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_swap12, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_swap23, // @[tracegen.scala:21:14] input [1:0] io_lsu_fresp_0_bits_uop_fp_ctrl_typeTagIn, // @[tracegen.scala:21:14] input [1:0] io_lsu_fresp_0_bits_uop_fp_ctrl_typeTagOut, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_fromint, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_toint, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_fastpipe, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_fma, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_div, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_sqrt, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_wflags, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_vec, // @[tracegen.scala:21:14] input [4:0] io_lsu_fresp_0_bits_uop_rob_idx, // @[tracegen.scala:21:14] input [3:0] io_lsu_fresp_0_bits_uop_ldq_idx, // @[tracegen.scala:21:14] input [3:0] io_lsu_fresp_0_bits_uop_stq_idx, // @[tracegen.scala:21:14] input [1:0] io_lsu_fresp_0_bits_uop_rxq_idx, // @[tracegen.scala:21:14] input [5:0] io_lsu_fresp_0_bits_uop_pdst, // @[tracegen.scala:21:14] input [5:0] io_lsu_fresp_0_bits_uop_prs1, // @[tracegen.scala:21:14] input [5:0] io_lsu_fresp_0_bits_uop_prs2, // @[tracegen.scala:21:14] input [5:0] io_lsu_fresp_0_bits_uop_prs3, // @[tracegen.scala:21:14] input [3:0] io_lsu_fresp_0_bits_uop_ppred, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_prs1_busy, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_prs2_busy, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_prs3_busy, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_ppred_busy, // @[tracegen.scala:21:14] input [5:0] io_lsu_fresp_0_bits_uop_stale_pdst, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_exception, // @[tracegen.scala:21:14] input [63:0] io_lsu_fresp_0_bits_uop_exc_cause, // @[tracegen.scala:21:14] input [4:0] io_lsu_fresp_0_bits_uop_mem_cmd, // @[tracegen.scala:21:14] input [1:0] io_lsu_fresp_0_bits_uop_mem_size, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_mem_signed, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_uses_ldq, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_uses_stq, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_is_unique, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_flush_on_commit, // @[tracegen.scala:21:14] input [2:0] io_lsu_fresp_0_bits_uop_csr_cmd, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_ldst_is_rs1, // @[tracegen.scala:21:14] input [5:0] io_lsu_fresp_0_bits_uop_ldst, // @[tracegen.scala:21:14] input [5:0] io_lsu_fresp_0_bits_uop_lrs1, // @[tracegen.scala:21:14] input [5:0] io_lsu_fresp_0_bits_uop_lrs2, // @[tracegen.scala:21:14] input [5:0] io_lsu_fresp_0_bits_uop_lrs3, // @[tracegen.scala:21:14] input [1:0] io_lsu_fresp_0_bits_uop_dst_rtype, // @[tracegen.scala:21:14] input [1:0] io_lsu_fresp_0_bits_uop_lrs1_rtype, // @[tracegen.scala:21:14] input [1:0] io_lsu_fresp_0_bits_uop_lrs2_rtype, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_frs3_en, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fcn_dw, // @[tracegen.scala:21:14] input [4:0] io_lsu_fresp_0_bits_uop_fcn_op, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_fp_val, // @[tracegen.scala:21:14] input [2:0] io_lsu_fresp_0_bits_uop_fp_rm, // @[tracegen.scala:21:14] input [1:0] io_lsu_fresp_0_bits_uop_fp_typ, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_xcpt_pf_if, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_xcpt_ae_if, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_xcpt_ma_if, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_bp_debug_if, // @[tracegen.scala:21:14] input io_lsu_fresp_0_bits_uop_bp_xcpt_if, // @[tracegen.scala:21:14] input [2:0] io_lsu_fresp_0_bits_uop_debug_fsrc, // @[tracegen.scala:21:14] input [2:0] io_lsu_fresp_0_bits_uop_debug_tsrc, // @[tracegen.scala:21:14] input [63:0] io_lsu_fresp_0_bits_data, // @[tracegen.scala:21:14] output io_lsu_dis_uops_0_valid, // @[tracegen.scala:21:14] output [31:0] io_lsu_dis_uops_0_bits_debug_inst, // @[tracegen.scala:21:14] output io_lsu_dis_uops_0_bits_is_amo, // @[tracegen.scala:21:14] output [4:0] io_lsu_dis_uops_0_bits_rob_idx, // @[tracegen.scala:21:14] output [3:0] io_lsu_dis_uops_0_bits_ldq_idx, // @[tracegen.scala:21:14] output [3:0] io_lsu_dis_uops_0_bits_stq_idx, // @[tracegen.scala:21:14] output [4:0] io_lsu_dis_uops_0_bits_mem_cmd, // @[tracegen.scala:21:14] output io_lsu_dis_uops_0_bits_uses_ldq, // @[tracegen.scala:21:14] output io_lsu_dis_uops_0_bits_uses_stq, // @[tracegen.scala:21:14] input [3:0] io_lsu_dis_ldq_idx_0, // @[tracegen.scala:21:14] input [3:0] io_lsu_dis_stq_idx_0, // @[tracegen.scala:21:14] input io_lsu_ldq_full_0, // @[tracegen.scala:21:14] input io_lsu_stq_full_0, // @[tracegen.scala:21:14] output io_lsu_commit_valids_0, // @[tracegen.scala:21:14] output [31:0] io_lsu_commit_uops_0_inst, // @[tracegen.scala:21:14] output [31:0] io_lsu_commit_uops_0_debug_inst, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_is_rvc, // @[tracegen.scala:21:14] output [33:0] io_lsu_commit_uops_0_debug_pc, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_iq_type_0, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_iq_type_1, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_iq_type_2, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_iq_type_3, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fu_code_0, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fu_code_1, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fu_code_2, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fu_code_3, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fu_code_4, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fu_code_5, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fu_code_6, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fu_code_7, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fu_code_8, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fu_code_9, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_iw_issued, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_iw_issued_partial_agen, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_iw_issued_partial_dgen, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_iw_p1_speculative_child, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_iw_p2_speculative_child, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_iw_p1_bypass_hint, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_iw_p2_bypass_hint, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_iw_p3_bypass_hint, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_dis_col_sel, // @[tracegen.scala:21:14] output [3:0] io_lsu_commit_uops_0_br_mask, // @[tracegen.scala:21:14] output [1:0] io_lsu_commit_uops_0_br_tag, // @[tracegen.scala:21:14] output [3:0] io_lsu_commit_uops_0_br_type, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_is_sfb, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_is_fence, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_is_fencei, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_is_sfence, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_is_amo, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_is_eret, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_is_sys_pc2epc, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_is_rocc, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_is_mov, // @[tracegen.scala:21:14] output [3:0] io_lsu_commit_uops_0_ftq_idx, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_edge_inst, // @[tracegen.scala:21:14] output [5:0] io_lsu_commit_uops_0_pc_lob, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_taken, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_imm_rename, // @[tracegen.scala:21:14] output [2:0] io_lsu_commit_uops_0_imm_sel, // @[tracegen.scala:21:14] output [4:0] io_lsu_commit_uops_0_pimm, // @[tracegen.scala:21:14] output [19:0] io_lsu_commit_uops_0_imm_packed, // @[tracegen.scala:21:14] output [1:0] io_lsu_commit_uops_0_op1_sel, // @[tracegen.scala:21:14] output [2:0] io_lsu_commit_uops_0_op2_sel, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_ctrl_ldst, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_ctrl_wen, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_ctrl_ren1, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_ctrl_ren2, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_ctrl_ren3, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_ctrl_swap12, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_ctrl_swap23, // @[tracegen.scala:21:14] output [1:0] io_lsu_commit_uops_0_fp_ctrl_typeTagIn, // @[tracegen.scala:21:14] output [1:0] io_lsu_commit_uops_0_fp_ctrl_typeTagOut, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_ctrl_fromint, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_ctrl_toint, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_ctrl_fastpipe, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_ctrl_fma, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_ctrl_div, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_ctrl_sqrt, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_ctrl_wflags, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_ctrl_vec, // @[tracegen.scala:21:14] output [4:0] io_lsu_commit_uops_0_rob_idx, // @[tracegen.scala:21:14] output [3:0] io_lsu_commit_uops_0_ldq_idx, // @[tracegen.scala:21:14] output [3:0] io_lsu_commit_uops_0_stq_idx, // @[tracegen.scala:21:14] output [1:0] io_lsu_commit_uops_0_rxq_idx, // @[tracegen.scala:21:14] output [5:0] io_lsu_commit_uops_0_pdst, // @[tracegen.scala:21:14] output [5:0] io_lsu_commit_uops_0_prs1, // @[tracegen.scala:21:14] output [5:0] io_lsu_commit_uops_0_prs2, // @[tracegen.scala:21:14] output [5:0] io_lsu_commit_uops_0_prs3, // @[tracegen.scala:21:14] output [3:0] io_lsu_commit_uops_0_ppred, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_prs1_busy, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_prs2_busy, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_prs3_busy, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_ppred_busy, // @[tracegen.scala:21:14] output [5:0] io_lsu_commit_uops_0_stale_pdst, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_exception, // @[tracegen.scala:21:14] output [63:0] io_lsu_commit_uops_0_exc_cause, // @[tracegen.scala:21:14] output [4:0] io_lsu_commit_uops_0_mem_cmd, // @[tracegen.scala:21:14] output [1:0] io_lsu_commit_uops_0_mem_size, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_mem_signed, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_uses_ldq, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_uses_stq, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_is_unique, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_flush_on_commit, // @[tracegen.scala:21:14] output [2:0] io_lsu_commit_uops_0_csr_cmd, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_ldst_is_rs1, // @[tracegen.scala:21:14] output [5:0] io_lsu_commit_uops_0_ldst, // @[tracegen.scala:21:14] output [5:0] io_lsu_commit_uops_0_lrs1, // @[tracegen.scala:21:14] output [5:0] io_lsu_commit_uops_0_lrs2, // @[tracegen.scala:21:14] output [5:0] io_lsu_commit_uops_0_lrs3, // @[tracegen.scala:21:14] output [1:0] io_lsu_commit_uops_0_dst_rtype, // @[tracegen.scala:21:14] output [1:0] io_lsu_commit_uops_0_lrs1_rtype, // @[tracegen.scala:21:14] output [1:0] io_lsu_commit_uops_0_lrs2_rtype, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_frs3_en, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fcn_dw, // @[tracegen.scala:21:14] output [4:0] io_lsu_commit_uops_0_fcn_op, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_fp_val, // @[tracegen.scala:21:14] output [2:0] io_lsu_commit_uops_0_fp_rm, // @[tracegen.scala:21:14] output [1:0] io_lsu_commit_uops_0_fp_typ, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_xcpt_pf_if, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_xcpt_ae_if, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_xcpt_ma_if, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_bp_debug_if, // @[tracegen.scala:21:14] output io_lsu_commit_uops_0_bp_xcpt_if, // @[tracegen.scala:21:14] output [2:0] io_lsu_commit_uops_0_debug_fsrc, // @[tracegen.scala:21:14] output [2:0] io_lsu_commit_uops_0_debug_tsrc, // @[tracegen.scala:21:14] input io_lsu_clr_bsy_0_valid, // @[tracegen.scala:21:14] input [4:0] io_lsu_clr_bsy_0_bits, // @[tracegen.scala:21:14] input io_lsu_clr_unsafe_0_valid, // @[tracegen.scala:21:14] input [4:0] io_lsu_clr_unsafe_0_bits, // @[tracegen.scala:21:14] output [4:0] io_lsu_rob_pnr_idx, // @[tracegen.scala:21:14] output [4:0] io_lsu_rob_head_idx, // @[tracegen.scala:21:14] input io_lsu_fencei_rdy, // @[tracegen.scala:21:14] input io_lsu_lxcpt_valid, // @[tracegen.scala:21:14] input [31:0] io_lsu_lxcpt_bits_uop_inst, // @[tracegen.scala:21:14] input [31:0] io_lsu_lxcpt_bits_uop_debug_inst, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_is_rvc, // @[tracegen.scala:21:14] input [33:0] io_lsu_lxcpt_bits_uop_debug_pc, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_iq_type_0, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_iq_type_1, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_iq_type_2, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_iq_type_3, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fu_code_0, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fu_code_1, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fu_code_2, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fu_code_3, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fu_code_4, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fu_code_5, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fu_code_6, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fu_code_7, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fu_code_8, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fu_code_9, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_iw_issued, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_iw_issued_partial_agen, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_iw_issued_partial_dgen, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_iw_p1_speculative_child, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_iw_p2_speculative_child, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_iw_p1_bypass_hint, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_iw_p2_bypass_hint, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_iw_p3_bypass_hint, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_dis_col_sel, // @[tracegen.scala:21:14] input [3:0] io_lsu_lxcpt_bits_uop_br_mask, // @[tracegen.scala:21:14] input [1:0] io_lsu_lxcpt_bits_uop_br_tag, // @[tracegen.scala:21:14] input [3:0] io_lsu_lxcpt_bits_uop_br_type, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_is_sfb, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_is_fence, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_is_fencei, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_is_sfence, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_is_amo, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_is_eret, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_is_sys_pc2epc, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_is_rocc, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_is_mov, // @[tracegen.scala:21:14] input [3:0] io_lsu_lxcpt_bits_uop_ftq_idx, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_edge_inst, // @[tracegen.scala:21:14] input [5:0] io_lsu_lxcpt_bits_uop_pc_lob, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_taken, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_imm_rename, // @[tracegen.scala:21:14] input [2:0] io_lsu_lxcpt_bits_uop_imm_sel, // @[tracegen.scala:21:14] input [4:0] io_lsu_lxcpt_bits_uop_pimm, // @[tracegen.scala:21:14] input [19:0] io_lsu_lxcpt_bits_uop_imm_packed, // @[tracegen.scala:21:14] input [1:0] io_lsu_lxcpt_bits_uop_op1_sel, // @[tracegen.scala:21:14] input [2:0] io_lsu_lxcpt_bits_uop_op2_sel, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_ldst, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_wen, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_ren1, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_ren2, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_ren3, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_swap12, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_swap23, // @[tracegen.scala:21:14] input [1:0] io_lsu_lxcpt_bits_uop_fp_ctrl_typeTagIn, // @[tracegen.scala:21:14] input [1:0] io_lsu_lxcpt_bits_uop_fp_ctrl_typeTagOut, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_fromint, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_toint, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_fastpipe, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_fma, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_div, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_sqrt, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_wflags, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_vec, // @[tracegen.scala:21:14] input [4:0] io_lsu_lxcpt_bits_uop_rob_idx, // @[tracegen.scala:21:14] input [3:0] io_lsu_lxcpt_bits_uop_ldq_idx, // @[tracegen.scala:21:14] input [3:0] io_lsu_lxcpt_bits_uop_stq_idx, // @[tracegen.scala:21:14] input [1:0] io_lsu_lxcpt_bits_uop_rxq_idx, // @[tracegen.scala:21:14] input [5:0] io_lsu_lxcpt_bits_uop_pdst, // @[tracegen.scala:21:14] input [5:0] io_lsu_lxcpt_bits_uop_prs1, // @[tracegen.scala:21:14] input [5:0] io_lsu_lxcpt_bits_uop_prs2, // @[tracegen.scala:21:14] input [5:0] io_lsu_lxcpt_bits_uop_prs3, // @[tracegen.scala:21:14] input [3:0] io_lsu_lxcpt_bits_uop_ppred, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_prs1_busy, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_prs2_busy, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_prs3_busy, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_ppred_busy, // @[tracegen.scala:21:14] input [5:0] io_lsu_lxcpt_bits_uop_stale_pdst, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_exception, // @[tracegen.scala:21:14] input [63:0] io_lsu_lxcpt_bits_uop_exc_cause, // @[tracegen.scala:21:14] input [4:0] io_lsu_lxcpt_bits_uop_mem_cmd, // @[tracegen.scala:21:14] input [1:0] io_lsu_lxcpt_bits_uop_mem_size, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_mem_signed, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_uses_ldq, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_uses_stq, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_is_unique, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_flush_on_commit, // @[tracegen.scala:21:14] input [2:0] io_lsu_lxcpt_bits_uop_csr_cmd, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_ldst_is_rs1, // @[tracegen.scala:21:14] input [5:0] io_lsu_lxcpt_bits_uop_ldst, // @[tracegen.scala:21:14] input [5:0] io_lsu_lxcpt_bits_uop_lrs1, // @[tracegen.scala:21:14] input [5:0] io_lsu_lxcpt_bits_uop_lrs2, // @[tracegen.scala:21:14] input [5:0] io_lsu_lxcpt_bits_uop_lrs3, // @[tracegen.scala:21:14] input [1:0] io_lsu_lxcpt_bits_uop_dst_rtype, // @[tracegen.scala:21:14] input [1:0] io_lsu_lxcpt_bits_uop_lrs1_rtype, // @[tracegen.scala:21:14] input [1:0] io_lsu_lxcpt_bits_uop_lrs2_rtype, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_frs3_en, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fcn_dw, // @[tracegen.scala:21:14] input [4:0] io_lsu_lxcpt_bits_uop_fcn_op, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_fp_val, // @[tracegen.scala:21:14] input [2:0] io_lsu_lxcpt_bits_uop_fp_rm, // @[tracegen.scala:21:14] input [1:0] io_lsu_lxcpt_bits_uop_fp_typ, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_xcpt_pf_if, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_xcpt_ae_if, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_xcpt_ma_if, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_bp_debug_if, // @[tracegen.scala:21:14] input io_lsu_lxcpt_bits_uop_bp_xcpt_if, // @[tracegen.scala:21:14] input [2:0] io_lsu_lxcpt_bits_uop_debug_fsrc, // @[tracegen.scala:21:14] input [2:0] io_lsu_lxcpt_bits_uop_debug_tsrc, // @[tracegen.scala:21:14] input [4:0] io_lsu_lxcpt_bits_cause, // @[tracegen.scala:21:14] input [33:0] io_lsu_lxcpt_bits_badvaddr, // @[tracegen.scala:21:14] input io_lsu_perf_acquire, // @[tracegen.scala:21:14] input io_lsu_perf_release, // @[tracegen.scala:21:14] output io_tracegen_req_ready, // @[tracegen.scala:21:14] input io_tracegen_req_valid, // @[tracegen.scala:21:14] input [33:0] io_tracegen_req_bits_addr, // @[tracegen.scala:21:14] input [5:0] io_tracegen_req_bits_tag, // @[tracegen.scala:21:14] input [4:0] io_tracegen_req_bits_cmd, // @[tracegen.scala:21:14] input [63:0] io_tracegen_req_bits_data, // @[tracegen.scala:21:14] input [63:0] io_tracegen_s1_data_data, // @[tracegen.scala:21:14] output io_tracegen_resp_valid, // @[tracegen.scala:21:14] output [5:0] io_tracegen_resp_bits_tag, // @[tracegen.scala:21:14] output [1:0] io_tracegen_resp_bits_size, // @[tracegen.scala:21:14] output [63:0] io_tracegen_resp_bits_data, // @[tracegen.scala:21:14] output io_tracegen_ordered // @[tracegen.scala:21:14] ); wire io_lsu_iwakeups_0_valid_0 = io_lsu_iwakeups_0_valid; // @[tracegen.scala:19:7] wire [31:0] io_lsu_iwakeups_0_bits_uop_inst_0 = io_lsu_iwakeups_0_bits_uop_inst; // @[tracegen.scala:19:7] wire [31:0] io_lsu_iwakeups_0_bits_uop_debug_inst_0 = io_lsu_iwakeups_0_bits_uop_debug_inst; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_is_rvc_0 = io_lsu_iwakeups_0_bits_uop_is_rvc; // @[tracegen.scala:19:7] wire [33:0] io_lsu_iwakeups_0_bits_uop_debug_pc_0 = io_lsu_iwakeups_0_bits_uop_debug_pc; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_iq_type_0_0 = io_lsu_iwakeups_0_bits_uop_iq_type_0; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_iq_type_1_0 = io_lsu_iwakeups_0_bits_uop_iq_type_1; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_iq_type_2_0 = io_lsu_iwakeups_0_bits_uop_iq_type_2; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_iq_type_3_0 = io_lsu_iwakeups_0_bits_uop_iq_type_3; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fu_code_0_0 = io_lsu_iwakeups_0_bits_uop_fu_code_0; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fu_code_1_0 = io_lsu_iwakeups_0_bits_uop_fu_code_1; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fu_code_2_0 = io_lsu_iwakeups_0_bits_uop_fu_code_2; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fu_code_3_0 = io_lsu_iwakeups_0_bits_uop_fu_code_3; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fu_code_4_0 = io_lsu_iwakeups_0_bits_uop_fu_code_4; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fu_code_5_0 = io_lsu_iwakeups_0_bits_uop_fu_code_5; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fu_code_6_0 = io_lsu_iwakeups_0_bits_uop_fu_code_6; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fu_code_7_0 = io_lsu_iwakeups_0_bits_uop_fu_code_7; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fu_code_8_0 = io_lsu_iwakeups_0_bits_uop_fu_code_8; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fu_code_9_0 = io_lsu_iwakeups_0_bits_uop_fu_code_9; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_iw_issued_0 = io_lsu_iwakeups_0_bits_uop_iw_issued; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_iw_issued_partial_agen_0 = io_lsu_iwakeups_0_bits_uop_iw_issued_partial_agen; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_iw_issued_partial_dgen_0 = io_lsu_iwakeups_0_bits_uop_iw_issued_partial_dgen; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_iw_p1_speculative_child_0 = io_lsu_iwakeups_0_bits_uop_iw_p1_speculative_child; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_iw_p2_speculative_child_0 = io_lsu_iwakeups_0_bits_uop_iw_p2_speculative_child; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_iw_p1_bypass_hint_0 = io_lsu_iwakeups_0_bits_uop_iw_p1_bypass_hint; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_iw_p2_bypass_hint_0 = io_lsu_iwakeups_0_bits_uop_iw_p2_bypass_hint; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_iw_p3_bypass_hint_0 = io_lsu_iwakeups_0_bits_uop_iw_p3_bypass_hint; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_dis_col_sel_0 = io_lsu_iwakeups_0_bits_uop_dis_col_sel; // @[tracegen.scala:19:7] wire [3:0] io_lsu_iwakeups_0_bits_uop_br_mask_0 = io_lsu_iwakeups_0_bits_uop_br_mask; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_br_tag_0 = io_lsu_iwakeups_0_bits_uop_br_tag; // @[tracegen.scala:19:7] wire [3:0] io_lsu_iwakeups_0_bits_uop_br_type_0 = io_lsu_iwakeups_0_bits_uop_br_type; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_is_sfb_0 = io_lsu_iwakeups_0_bits_uop_is_sfb; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_is_fence_0 = io_lsu_iwakeups_0_bits_uop_is_fence; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_is_fencei_0 = io_lsu_iwakeups_0_bits_uop_is_fencei; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_is_sfence_0 = io_lsu_iwakeups_0_bits_uop_is_sfence; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_is_amo_0 = io_lsu_iwakeups_0_bits_uop_is_amo; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_is_eret_0 = io_lsu_iwakeups_0_bits_uop_is_eret; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_is_sys_pc2epc_0 = io_lsu_iwakeups_0_bits_uop_is_sys_pc2epc; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_is_rocc_0 = io_lsu_iwakeups_0_bits_uop_is_rocc; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_is_mov_0 = io_lsu_iwakeups_0_bits_uop_is_mov; // @[tracegen.scala:19:7] wire [3:0] io_lsu_iwakeups_0_bits_uop_ftq_idx_0 = io_lsu_iwakeups_0_bits_uop_ftq_idx; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_edge_inst_0 = io_lsu_iwakeups_0_bits_uop_edge_inst; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iwakeups_0_bits_uop_pc_lob_0 = io_lsu_iwakeups_0_bits_uop_pc_lob; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_taken_0 = io_lsu_iwakeups_0_bits_uop_taken; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_imm_rename_0 = io_lsu_iwakeups_0_bits_uop_imm_rename; // @[tracegen.scala:19:7] wire [2:0] io_lsu_iwakeups_0_bits_uop_imm_sel_0 = io_lsu_iwakeups_0_bits_uop_imm_sel; // @[tracegen.scala:19:7] wire [4:0] io_lsu_iwakeups_0_bits_uop_pimm_0 = io_lsu_iwakeups_0_bits_uop_pimm; // @[tracegen.scala:19:7] wire [19:0] io_lsu_iwakeups_0_bits_uop_imm_packed_0 = io_lsu_iwakeups_0_bits_uop_imm_packed; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_op1_sel_0 = io_lsu_iwakeups_0_bits_uop_op1_sel; // @[tracegen.scala:19:7] wire [2:0] io_lsu_iwakeups_0_bits_uop_op2_sel_0 = io_lsu_iwakeups_0_bits_uop_op2_sel; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_ldst_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_ldst; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_wen_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_wen; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren1_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren1; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren2_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren2; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren3_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren3; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_swap12_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_swap12; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_swap23_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_swap23; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_fp_ctrl_typeTagIn_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_fp_ctrl_typeTagOut_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_fromint_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_fromint; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_toint_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_toint; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_fastpipe_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_fastpipe; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_fma_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_fma; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_div_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_div; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_sqrt_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_sqrt; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_wflags_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_wflags; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_vec_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_vec; // @[tracegen.scala:19:7] wire [4:0] io_lsu_iwakeups_0_bits_uop_rob_idx_0 = io_lsu_iwakeups_0_bits_uop_rob_idx; // @[tracegen.scala:19:7] wire [3:0] io_lsu_iwakeups_0_bits_uop_ldq_idx_0 = io_lsu_iwakeups_0_bits_uop_ldq_idx; // @[tracegen.scala:19:7] wire [3:0] io_lsu_iwakeups_0_bits_uop_stq_idx_0 = io_lsu_iwakeups_0_bits_uop_stq_idx; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_rxq_idx_0 = io_lsu_iwakeups_0_bits_uop_rxq_idx; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iwakeups_0_bits_uop_pdst_0 = io_lsu_iwakeups_0_bits_uop_pdst; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iwakeups_0_bits_uop_prs1_0 = io_lsu_iwakeups_0_bits_uop_prs1; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iwakeups_0_bits_uop_prs2_0 = io_lsu_iwakeups_0_bits_uop_prs2; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iwakeups_0_bits_uop_prs3_0 = io_lsu_iwakeups_0_bits_uop_prs3; // @[tracegen.scala:19:7] wire [3:0] io_lsu_iwakeups_0_bits_uop_ppred_0 = io_lsu_iwakeups_0_bits_uop_ppred; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_prs1_busy_0 = io_lsu_iwakeups_0_bits_uop_prs1_busy; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_prs2_busy_0 = io_lsu_iwakeups_0_bits_uop_prs2_busy; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_prs3_busy_0 = io_lsu_iwakeups_0_bits_uop_prs3_busy; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_ppred_busy_0 = io_lsu_iwakeups_0_bits_uop_ppred_busy; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iwakeups_0_bits_uop_stale_pdst_0 = io_lsu_iwakeups_0_bits_uop_stale_pdst; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_exception_0 = io_lsu_iwakeups_0_bits_uop_exception; // @[tracegen.scala:19:7] wire [63:0] io_lsu_iwakeups_0_bits_uop_exc_cause_0 = io_lsu_iwakeups_0_bits_uop_exc_cause; // @[tracegen.scala:19:7] wire [4:0] io_lsu_iwakeups_0_bits_uop_mem_cmd_0 = io_lsu_iwakeups_0_bits_uop_mem_cmd; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_mem_size_0 = io_lsu_iwakeups_0_bits_uop_mem_size; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_mem_signed_0 = io_lsu_iwakeups_0_bits_uop_mem_signed; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_uses_ldq_0 = io_lsu_iwakeups_0_bits_uop_uses_ldq; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_uses_stq_0 = io_lsu_iwakeups_0_bits_uop_uses_stq; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_is_unique_0 = io_lsu_iwakeups_0_bits_uop_is_unique; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_flush_on_commit_0 = io_lsu_iwakeups_0_bits_uop_flush_on_commit; // @[tracegen.scala:19:7] wire [2:0] io_lsu_iwakeups_0_bits_uop_csr_cmd_0 = io_lsu_iwakeups_0_bits_uop_csr_cmd; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_ldst_is_rs1_0 = io_lsu_iwakeups_0_bits_uop_ldst_is_rs1; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iwakeups_0_bits_uop_ldst_0 = io_lsu_iwakeups_0_bits_uop_ldst; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iwakeups_0_bits_uop_lrs1_0 = io_lsu_iwakeups_0_bits_uop_lrs1; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iwakeups_0_bits_uop_lrs2_0 = io_lsu_iwakeups_0_bits_uop_lrs2; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iwakeups_0_bits_uop_lrs3_0 = io_lsu_iwakeups_0_bits_uop_lrs3; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_dst_rtype_0 = io_lsu_iwakeups_0_bits_uop_dst_rtype; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_lrs1_rtype_0 = io_lsu_iwakeups_0_bits_uop_lrs1_rtype; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_lrs2_rtype_0 = io_lsu_iwakeups_0_bits_uop_lrs2_rtype; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_frs3_en_0 = io_lsu_iwakeups_0_bits_uop_frs3_en; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fcn_dw_0 = io_lsu_iwakeups_0_bits_uop_fcn_dw; // @[tracegen.scala:19:7] wire [4:0] io_lsu_iwakeups_0_bits_uop_fcn_op_0 = io_lsu_iwakeups_0_bits_uop_fcn_op; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_fp_val_0 = io_lsu_iwakeups_0_bits_uop_fp_val; // @[tracegen.scala:19:7] wire [2:0] io_lsu_iwakeups_0_bits_uop_fp_rm_0 = io_lsu_iwakeups_0_bits_uop_fp_rm; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_fp_typ_0 = io_lsu_iwakeups_0_bits_uop_fp_typ; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_xcpt_pf_if_0 = io_lsu_iwakeups_0_bits_uop_xcpt_pf_if; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_xcpt_ae_if_0 = io_lsu_iwakeups_0_bits_uop_xcpt_ae_if; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_xcpt_ma_if_0 = io_lsu_iwakeups_0_bits_uop_xcpt_ma_if; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_bp_debug_if_0 = io_lsu_iwakeups_0_bits_uop_bp_debug_if; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_uop_bp_xcpt_if_0 = io_lsu_iwakeups_0_bits_uop_bp_xcpt_if; // @[tracegen.scala:19:7] wire [2:0] io_lsu_iwakeups_0_bits_uop_debug_fsrc_0 = io_lsu_iwakeups_0_bits_uop_debug_fsrc; // @[tracegen.scala:19:7] wire [2:0] io_lsu_iwakeups_0_bits_uop_debug_tsrc_0 = io_lsu_iwakeups_0_bits_uop_debug_tsrc; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_bypassable_0 = io_lsu_iwakeups_0_bits_bypassable; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_speculative_mask_0 = io_lsu_iwakeups_0_bits_speculative_mask; // @[tracegen.scala:19:7] wire io_lsu_iwakeups_0_bits_rebusy_0 = io_lsu_iwakeups_0_bits_rebusy; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_valid_0 = io_lsu_iresp_0_valid; // @[tracegen.scala:19:7] wire [31:0] io_lsu_iresp_0_bits_uop_inst_0 = io_lsu_iresp_0_bits_uop_inst; // @[tracegen.scala:19:7] wire [31:0] io_lsu_iresp_0_bits_uop_debug_inst_0 = io_lsu_iresp_0_bits_uop_debug_inst; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_is_rvc_0 = io_lsu_iresp_0_bits_uop_is_rvc; // @[tracegen.scala:19:7] wire [33:0] io_lsu_iresp_0_bits_uop_debug_pc_0 = io_lsu_iresp_0_bits_uop_debug_pc; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_iq_type_0_0 = io_lsu_iresp_0_bits_uop_iq_type_0; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_iq_type_1_0 = io_lsu_iresp_0_bits_uop_iq_type_1; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_iq_type_2_0 = io_lsu_iresp_0_bits_uop_iq_type_2; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_iq_type_3_0 = io_lsu_iresp_0_bits_uop_iq_type_3; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fu_code_0_0 = io_lsu_iresp_0_bits_uop_fu_code_0; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fu_code_1_0 = io_lsu_iresp_0_bits_uop_fu_code_1; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fu_code_2_0 = io_lsu_iresp_0_bits_uop_fu_code_2; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fu_code_3_0 = io_lsu_iresp_0_bits_uop_fu_code_3; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fu_code_4_0 = io_lsu_iresp_0_bits_uop_fu_code_4; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fu_code_5_0 = io_lsu_iresp_0_bits_uop_fu_code_5; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fu_code_6_0 = io_lsu_iresp_0_bits_uop_fu_code_6; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fu_code_7_0 = io_lsu_iresp_0_bits_uop_fu_code_7; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fu_code_8_0 = io_lsu_iresp_0_bits_uop_fu_code_8; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fu_code_9_0 = io_lsu_iresp_0_bits_uop_fu_code_9; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_iw_issued_0 = io_lsu_iresp_0_bits_uop_iw_issued; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_iw_issued_partial_agen_0 = io_lsu_iresp_0_bits_uop_iw_issued_partial_agen; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_iw_issued_partial_dgen_0 = io_lsu_iresp_0_bits_uop_iw_issued_partial_dgen; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_iw_p1_speculative_child_0 = io_lsu_iresp_0_bits_uop_iw_p1_speculative_child; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_iw_p2_speculative_child_0 = io_lsu_iresp_0_bits_uop_iw_p2_speculative_child; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_iw_p1_bypass_hint_0 = io_lsu_iresp_0_bits_uop_iw_p1_bypass_hint; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_iw_p2_bypass_hint_0 = io_lsu_iresp_0_bits_uop_iw_p2_bypass_hint; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_iw_p3_bypass_hint_0 = io_lsu_iresp_0_bits_uop_iw_p3_bypass_hint; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_dis_col_sel_0 = io_lsu_iresp_0_bits_uop_dis_col_sel; // @[tracegen.scala:19:7] wire [3:0] io_lsu_iresp_0_bits_uop_br_mask_0 = io_lsu_iresp_0_bits_uop_br_mask; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iresp_0_bits_uop_br_tag_0 = io_lsu_iresp_0_bits_uop_br_tag; // @[tracegen.scala:19:7] wire [3:0] io_lsu_iresp_0_bits_uop_br_type_0 = io_lsu_iresp_0_bits_uop_br_type; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_is_sfb_0 = io_lsu_iresp_0_bits_uop_is_sfb; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_is_fence_0 = io_lsu_iresp_0_bits_uop_is_fence; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_is_fencei_0 = io_lsu_iresp_0_bits_uop_is_fencei; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_is_sfence_0 = io_lsu_iresp_0_bits_uop_is_sfence; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_is_amo_0 = io_lsu_iresp_0_bits_uop_is_amo; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_is_eret_0 = io_lsu_iresp_0_bits_uop_is_eret; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_is_sys_pc2epc_0 = io_lsu_iresp_0_bits_uop_is_sys_pc2epc; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_is_rocc_0 = io_lsu_iresp_0_bits_uop_is_rocc; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_is_mov_0 = io_lsu_iresp_0_bits_uop_is_mov; // @[tracegen.scala:19:7] wire [3:0] io_lsu_iresp_0_bits_uop_ftq_idx_0 = io_lsu_iresp_0_bits_uop_ftq_idx; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_edge_inst_0 = io_lsu_iresp_0_bits_uop_edge_inst; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iresp_0_bits_uop_pc_lob_0 = io_lsu_iresp_0_bits_uop_pc_lob; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_taken_0 = io_lsu_iresp_0_bits_uop_taken; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_imm_rename_0 = io_lsu_iresp_0_bits_uop_imm_rename; // @[tracegen.scala:19:7] wire [2:0] io_lsu_iresp_0_bits_uop_imm_sel_0 = io_lsu_iresp_0_bits_uop_imm_sel; // @[tracegen.scala:19:7] wire [4:0] io_lsu_iresp_0_bits_uop_pimm_0 = io_lsu_iresp_0_bits_uop_pimm; // @[tracegen.scala:19:7] wire [19:0] io_lsu_iresp_0_bits_uop_imm_packed_0 = io_lsu_iresp_0_bits_uop_imm_packed; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iresp_0_bits_uop_op1_sel_0 = io_lsu_iresp_0_bits_uop_op1_sel; // @[tracegen.scala:19:7] wire [2:0] io_lsu_iresp_0_bits_uop_op2_sel_0 = io_lsu_iresp_0_bits_uop_op2_sel; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_ldst_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_ldst; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_wen_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_wen; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_ren1_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_ren1; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_ren2_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_ren2; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_ren3_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_ren3; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_swap12_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_swap12; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_swap23_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_swap23; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iresp_0_bits_uop_fp_ctrl_typeTagIn_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_typeTagIn; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iresp_0_bits_uop_fp_ctrl_typeTagOut_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_typeTagOut; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_fromint_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_fromint; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_toint_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_toint; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_fastpipe_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_fastpipe; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_fma_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_fma; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_div_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_div; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_sqrt_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_sqrt; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_wflags_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_wflags; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_vec_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_vec; // @[tracegen.scala:19:7] wire [4:0] io_lsu_iresp_0_bits_uop_rob_idx_0 = io_lsu_iresp_0_bits_uop_rob_idx; // @[tracegen.scala:19:7] wire [3:0] io_lsu_iresp_0_bits_uop_ldq_idx_0 = io_lsu_iresp_0_bits_uop_ldq_idx; // @[tracegen.scala:19:7] wire [3:0] io_lsu_iresp_0_bits_uop_stq_idx_0 = io_lsu_iresp_0_bits_uop_stq_idx; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iresp_0_bits_uop_rxq_idx_0 = io_lsu_iresp_0_bits_uop_rxq_idx; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iresp_0_bits_uop_pdst_0 = io_lsu_iresp_0_bits_uop_pdst; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iresp_0_bits_uop_prs1_0 = io_lsu_iresp_0_bits_uop_prs1; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iresp_0_bits_uop_prs2_0 = io_lsu_iresp_0_bits_uop_prs2; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iresp_0_bits_uop_prs3_0 = io_lsu_iresp_0_bits_uop_prs3; // @[tracegen.scala:19:7] wire [3:0] io_lsu_iresp_0_bits_uop_ppred_0 = io_lsu_iresp_0_bits_uop_ppred; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_prs1_busy_0 = io_lsu_iresp_0_bits_uop_prs1_busy; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_prs2_busy_0 = io_lsu_iresp_0_bits_uop_prs2_busy; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_prs3_busy_0 = io_lsu_iresp_0_bits_uop_prs3_busy; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_ppred_busy_0 = io_lsu_iresp_0_bits_uop_ppred_busy; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iresp_0_bits_uop_stale_pdst_0 = io_lsu_iresp_0_bits_uop_stale_pdst; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_exception_0 = io_lsu_iresp_0_bits_uop_exception; // @[tracegen.scala:19:7] wire [63:0] io_lsu_iresp_0_bits_uop_exc_cause_0 = io_lsu_iresp_0_bits_uop_exc_cause; // @[tracegen.scala:19:7] wire [4:0] io_lsu_iresp_0_bits_uop_mem_cmd_0 = io_lsu_iresp_0_bits_uop_mem_cmd; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iresp_0_bits_uop_mem_size_0 = io_lsu_iresp_0_bits_uop_mem_size; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_mem_signed_0 = io_lsu_iresp_0_bits_uop_mem_signed; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_uses_ldq_0 = io_lsu_iresp_0_bits_uop_uses_ldq; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_uses_stq_0 = io_lsu_iresp_0_bits_uop_uses_stq; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_is_unique_0 = io_lsu_iresp_0_bits_uop_is_unique; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_flush_on_commit_0 = io_lsu_iresp_0_bits_uop_flush_on_commit; // @[tracegen.scala:19:7] wire [2:0] io_lsu_iresp_0_bits_uop_csr_cmd_0 = io_lsu_iresp_0_bits_uop_csr_cmd; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_ldst_is_rs1_0 = io_lsu_iresp_0_bits_uop_ldst_is_rs1; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iresp_0_bits_uop_ldst_0 = io_lsu_iresp_0_bits_uop_ldst; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iresp_0_bits_uop_lrs1_0 = io_lsu_iresp_0_bits_uop_lrs1; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iresp_0_bits_uop_lrs2_0 = io_lsu_iresp_0_bits_uop_lrs2; // @[tracegen.scala:19:7] wire [5:0] io_lsu_iresp_0_bits_uop_lrs3_0 = io_lsu_iresp_0_bits_uop_lrs3; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iresp_0_bits_uop_dst_rtype_0 = io_lsu_iresp_0_bits_uop_dst_rtype; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iresp_0_bits_uop_lrs1_rtype_0 = io_lsu_iresp_0_bits_uop_lrs1_rtype; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iresp_0_bits_uop_lrs2_rtype_0 = io_lsu_iresp_0_bits_uop_lrs2_rtype; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_frs3_en_0 = io_lsu_iresp_0_bits_uop_frs3_en; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fcn_dw_0 = io_lsu_iresp_0_bits_uop_fcn_dw; // @[tracegen.scala:19:7] wire [4:0] io_lsu_iresp_0_bits_uop_fcn_op_0 = io_lsu_iresp_0_bits_uop_fcn_op; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_fp_val_0 = io_lsu_iresp_0_bits_uop_fp_val; // @[tracegen.scala:19:7] wire [2:0] io_lsu_iresp_0_bits_uop_fp_rm_0 = io_lsu_iresp_0_bits_uop_fp_rm; // @[tracegen.scala:19:7] wire [1:0] io_lsu_iresp_0_bits_uop_fp_typ_0 = io_lsu_iresp_0_bits_uop_fp_typ; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_xcpt_pf_if_0 = io_lsu_iresp_0_bits_uop_xcpt_pf_if; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_xcpt_ae_if_0 = io_lsu_iresp_0_bits_uop_xcpt_ae_if; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_xcpt_ma_if_0 = io_lsu_iresp_0_bits_uop_xcpt_ma_if; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_bp_debug_if_0 = io_lsu_iresp_0_bits_uop_bp_debug_if; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_uop_bp_xcpt_if_0 = io_lsu_iresp_0_bits_uop_bp_xcpt_if; // @[tracegen.scala:19:7] wire [2:0] io_lsu_iresp_0_bits_uop_debug_fsrc_0 = io_lsu_iresp_0_bits_uop_debug_fsrc; // @[tracegen.scala:19:7] wire [2:0] io_lsu_iresp_0_bits_uop_debug_tsrc_0 = io_lsu_iresp_0_bits_uop_debug_tsrc; // @[tracegen.scala:19:7] wire [63:0] io_lsu_iresp_0_bits_data_0 = io_lsu_iresp_0_bits_data; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_valid_0 = io_lsu_fresp_0_valid; // @[tracegen.scala:19:7] wire [31:0] io_lsu_fresp_0_bits_uop_inst_0 = io_lsu_fresp_0_bits_uop_inst; // @[tracegen.scala:19:7] wire [31:0] io_lsu_fresp_0_bits_uop_debug_inst_0 = io_lsu_fresp_0_bits_uop_debug_inst; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_is_rvc_0 = io_lsu_fresp_0_bits_uop_is_rvc; // @[tracegen.scala:19:7] wire [33:0] io_lsu_fresp_0_bits_uop_debug_pc_0 = io_lsu_fresp_0_bits_uop_debug_pc; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_iq_type_0_0 = io_lsu_fresp_0_bits_uop_iq_type_0; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_iq_type_1_0 = io_lsu_fresp_0_bits_uop_iq_type_1; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_iq_type_2_0 = io_lsu_fresp_0_bits_uop_iq_type_2; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_iq_type_3_0 = io_lsu_fresp_0_bits_uop_iq_type_3; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fu_code_0_0 = io_lsu_fresp_0_bits_uop_fu_code_0; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fu_code_1_0 = io_lsu_fresp_0_bits_uop_fu_code_1; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fu_code_2_0 = io_lsu_fresp_0_bits_uop_fu_code_2; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fu_code_3_0 = io_lsu_fresp_0_bits_uop_fu_code_3; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fu_code_4_0 = io_lsu_fresp_0_bits_uop_fu_code_4; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fu_code_5_0 = io_lsu_fresp_0_bits_uop_fu_code_5; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fu_code_6_0 = io_lsu_fresp_0_bits_uop_fu_code_6; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fu_code_7_0 = io_lsu_fresp_0_bits_uop_fu_code_7; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fu_code_8_0 = io_lsu_fresp_0_bits_uop_fu_code_8; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fu_code_9_0 = io_lsu_fresp_0_bits_uop_fu_code_9; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_iw_issued_0 = io_lsu_fresp_0_bits_uop_iw_issued; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_iw_issued_partial_agen_0 = io_lsu_fresp_0_bits_uop_iw_issued_partial_agen; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_iw_issued_partial_dgen_0 = io_lsu_fresp_0_bits_uop_iw_issued_partial_dgen; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_iw_p1_speculative_child_0 = io_lsu_fresp_0_bits_uop_iw_p1_speculative_child; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_iw_p2_speculative_child_0 = io_lsu_fresp_0_bits_uop_iw_p2_speculative_child; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_iw_p1_bypass_hint_0 = io_lsu_fresp_0_bits_uop_iw_p1_bypass_hint; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_iw_p2_bypass_hint_0 = io_lsu_fresp_0_bits_uop_iw_p2_bypass_hint; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_iw_p3_bypass_hint_0 = io_lsu_fresp_0_bits_uop_iw_p3_bypass_hint; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_dis_col_sel_0 = io_lsu_fresp_0_bits_uop_dis_col_sel; // @[tracegen.scala:19:7] wire [3:0] io_lsu_fresp_0_bits_uop_br_mask_0 = io_lsu_fresp_0_bits_uop_br_mask; // @[tracegen.scala:19:7] wire [1:0] io_lsu_fresp_0_bits_uop_br_tag_0 = io_lsu_fresp_0_bits_uop_br_tag; // @[tracegen.scala:19:7] wire [3:0] io_lsu_fresp_0_bits_uop_br_type_0 = io_lsu_fresp_0_bits_uop_br_type; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_is_sfb_0 = io_lsu_fresp_0_bits_uop_is_sfb; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_is_fence_0 = io_lsu_fresp_0_bits_uop_is_fence; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_is_fencei_0 = io_lsu_fresp_0_bits_uop_is_fencei; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_is_sfence_0 = io_lsu_fresp_0_bits_uop_is_sfence; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_is_amo_0 = io_lsu_fresp_0_bits_uop_is_amo; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_is_eret_0 = io_lsu_fresp_0_bits_uop_is_eret; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_is_sys_pc2epc_0 = io_lsu_fresp_0_bits_uop_is_sys_pc2epc; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_is_rocc_0 = io_lsu_fresp_0_bits_uop_is_rocc; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_is_mov_0 = io_lsu_fresp_0_bits_uop_is_mov; // @[tracegen.scala:19:7] wire [3:0] io_lsu_fresp_0_bits_uop_ftq_idx_0 = io_lsu_fresp_0_bits_uop_ftq_idx; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_edge_inst_0 = io_lsu_fresp_0_bits_uop_edge_inst; // @[tracegen.scala:19:7] wire [5:0] io_lsu_fresp_0_bits_uop_pc_lob_0 = io_lsu_fresp_0_bits_uop_pc_lob; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_taken_0 = io_lsu_fresp_0_bits_uop_taken; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_imm_rename_0 = io_lsu_fresp_0_bits_uop_imm_rename; // @[tracegen.scala:19:7] wire [2:0] io_lsu_fresp_0_bits_uop_imm_sel_0 = io_lsu_fresp_0_bits_uop_imm_sel; // @[tracegen.scala:19:7] wire [4:0] io_lsu_fresp_0_bits_uop_pimm_0 = io_lsu_fresp_0_bits_uop_pimm; // @[tracegen.scala:19:7] wire [19:0] io_lsu_fresp_0_bits_uop_imm_packed_0 = io_lsu_fresp_0_bits_uop_imm_packed; // @[tracegen.scala:19:7] wire [1:0] io_lsu_fresp_0_bits_uop_op1_sel_0 = io_lsu_fresp_0_bits_uop_op1_sel; // @[tracegen.scala:19:7] wire [2:0] io_lsu_fresp_0_bits_uop_op2_sel_0 = io_lsu_fresp_0_bits_uop_op2_sel; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_ldst_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_ldst; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_wen_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_wen; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_ren1_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_ren1; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_ren2_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_ren2; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_ren3_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_ren3; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_swap12_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_swap12; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_swap23_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_swap23; // @[tracegen.scala:19:7] wire [1:0] io_lsu_fresp_0_bits_uop_fp_ctrl_typeTagIn_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_typeTagIn; // @[tracegen.scala:19:7] wire [1:0] io_lsu_fresp_0_bits_uop_fp_ctrl_typeTagOut_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_typeTagOut; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_fromint_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_fromint; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_toint_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_toint; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_fastpipe_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_fastpipe; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_fma_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_fma; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_div_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_div; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_sqrt_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_sqrt; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_wflags_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_wflags; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_vec_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_vec; // @[tracegen.scala:19:7] wire [4:0] io_lsu_fresp_0_bits_uop_rob_idx_0 = io_lsu_fresp_0_bits_uop_rob_idx; // @[tracegen.scala:19:7] wire [3:0] io_lsu_fresp_0_bits_uop_ldq_idx_0 = io_lsu_fresp_0_bits_uop_ldq_idx; // @[tracegen.scala:19:7] wire [3:0] io_lsu_fresp_0_bits_uop_stq_idx_0 = io_lsu_fresp_0_bits_uop_stq_idx; // @[tracegen.scala:19:7] wire [1:0] io_lsu_fresp_0_bits_uop_rxq_idx_0 = io_lsu_fresp_0_bits_uop_rxq_idx; // @[tracegen.scala:19:7] wire [5:0] io_lsu_fresp_0_bits_uop_pdst_0 = io_lsu_fresp_0_bits_uop_pdst; // @[tracegen.scala:19:7] wire [5:0] io_lsu_fresp_0_bits_uop_prs1_0 = io_lsu_fresp_0_bits_uop_prs1; // @[tracegen.scala:19:7] wire [5:0] io_lsu_fresp_0_bits_uop_prs2_0 = io_lsu_fresp_0_bits_uop_prs2; // @[tracegen.scala:19:7] wire [5:0] io_lsu_fresp_0_bits_uop_prs3_0 = io_lsu_fresp_0_bits_uop_prs3; // @[tracegen.scala:19:7] wire [3:0] io_lsu_fresp_0_bits_uop_ppred_0 = io_lsu_fresp_0_bits_uop_ppred; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_prs1_busy_0 = io_lsu_fresp_0_bits_uop_prs1_busy; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_prs2_busy_0 = io_lsu_fresp_0_bits_uop_prs2_busy; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_prs3_busy_0 = io_lsu_fresp_0_bits_uop_prs3_busy; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_ppred_busy_0 = io_lsu_fresp_0_bits_uop_ppred_busy; // @[tracegen.scala:19:7] wire [5:0] io_lsu_fresp_0_bits_uop_stale_pdst_0 = io_lsu_fresp_0_bits_uop_stale_pdst; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_exception_0 = io_lsu_fresp_0_bits_uop_exception; // @[tracegen.scala:19:7] wire [63:0] io_lsu_fresp_0_bits_uop_exc_cause_0 = io_lsu_fresp_0_bits_uop_exc_cause; // @[tracegen.scala:19:7] wire [4:0] io_lsu_fresp_0_bits_uop_mem_cmd_0 = io_lsu_fresp_0_bits_uop_mem_cmd; // @[tracegen.scala:19:7] wire [1:0] io_lsu_fresp_0_bits_uop_mem_size_0 = io_lsu_fresp_0_bits_uop_mem_size; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_mem_signed_0 = io_lsu_fresp_0_bits_uop_mem_signed; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_uses_ldq_0 = io_lsu_fresp_0_bits_uop_uses_ldq; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_uses_stq_0 = io_lsu_fresp_0_bits_uop_uses_stq; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_is_unique_0 = io_lsu_fresp_0_bits_uop_is_unique; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_flush_on_commit_0 = io_lsu_fresp_0_bits_uop_flush_on_commit; // @[tracegen.scala:19:7] wire [2:0] io_lsu_fresp_0_bits_uop_csr_cmd_0 = io_lsu_fresp_0_bits_uop_csr_cmd; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_ldst_is_rs1_0 = io_lsu_fresp_0_bits_uop_ldst_is_rs1; // @[tracegen.scala:19:7] wire [5:0] io_lsu_fresp_0_bits_uop_ldst_0 = io_lsu_fresp_0_bits_uop_ldst; // @[tracegen.scala:19:7] wire [5:0] io_lsu_fresp_0_bits_uop_lrs1_0 = io_lsu_fresp_0_bits_uop_lrs1; // @[tracegen.scala:19:7] wire [5:0] io_lsu_fresp_0_bits_uop_lrs2_0 = io_lsu_fresp_0_bits_uop_lrs2; // @[tracegen.scala:19:7] wire [5:0] io_lsu_fresp_0_bits_uop_lrs3_0 = io_lsu_fresp_0_bits_uop_lrs3; // @[tracegen.scala:19:7] wire [1:0] io_lsu_fresp_0_bits_uop_dst_rtype_0 = io_lsu_fresp_0_bits_uop_dst_rtype; // @[tracegen.scala:19:7] wire [1:0] io_lsu_fresp_0_bits_uop_lrs1_rtype_0 = io_lsu_fresp_0_bits_uop_lrs1_rtype; // @[tracegen.scala:19:7] wire [1:0] io_lsu_fresp_0_bits_uop_lrs2_rtype_0 = io_lsu_fresp_0_bits_uop_lrs2_rtype; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_frs3_en_0 = io_lsu_fresp_0_bits_uop_frs3_en; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fcn_dw_0 = io_lsu_fresp_0_bits_uop_fcn_dw; // @[tracegen.scala:19:7] wire [4:0] io_lsu_fresp_0_bits_uop_fcn_op_0 = io_lsu_fresp_0_bits_uop_fcn_op; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_fp_val_0 = io_lsu_fresp_0_bits_uop_fp_val; // @[tracegen.scala:19:7] wire [2:0] io_lsu_fresp_0_bits_uop_fp_rm_0 = io_lsu_fresp_0_bits_uop_fp_rm; // @[tracegen.scala:19:7] wire [1:0] io_lsu_fresp_0_bits_uop_fp_typ_0 = io_lsu_fresp_0_bits_uop_fp_typ; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_xcpt_pf_if_0 = io_lsu_fresp_0_bits_uop_xcpt_pf_if; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_xcpt_ae_if_0 = io_lsu_fresp_0_bits_uop_xcpt_ae_if; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_xcpt_ma_if_0 = io_lsu_fresp_0_bits_uop_xcpt_ma_if; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_bp_debug_if_0 = io_lsu_fresp_0_bits_uop_bp_debug_if; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_uop_bp_xcpt_if_0 = io_lsu_fresp_0_bits_uop_bp_xcpt_if; // @[tracegen.scala:19:7] wire [2:0] io_lsu_fresp_0_bits_uop_debug_fsrc_0 = io_lsu_fresp_0_bits_uop_debug_fsrc; // @[tracegen.scala:19:7] wire [2:0] io_lsu_fresp_0_bits_uop_debug_tsrc_0 = io_lsu_fresp_0_bits_uop_debug_tsrc; // @[tracegen.scala:19:7] wire [63:0] io_lsu_fresp_0_bits_data_0 = io_lsu_fresp_0_bits_data; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dis_ldq_idx_0_0 = io_lsu_dis_ldq_idx_0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dis_stq_idx_0_0 = io_lsu_dis_stq_idx_0; // @[tracegen.scala:19:7] wire io_lsu_ldq_full_0_0 = io_lsu_ldq_full_0; // @[tracegen.scala:19:7] wire io_lsu_stq_full_0_0 = io_lsu_stq_full_0; // @[tracegen.scala:19:7] wire io_lsu_clr_bsy_0_valid_0 = io_lsu_clr_bsy_0_valid; // @[tracegen.scala:19:7] wire [4:0] io_lsu_clr_bsy_0_bits_0 = io_lsu_clr_bsy_0_bits; // @[tracegen.scala:19:7] wire io_lsu_clr_unsafe_0_valid_0 = io_lsu_clr_unsafe_0_valid; // @[tracegen.scala:19:7] wire [4:0] io_lsu_clr_unsafe_0_bits_0 = io_lsu_clr_unsafe_0_bits; // @[tracegen.scala:19:7] wire io_lsu_fencei_rdy_0 = io_lsu_fencei_rdy; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_valid_0 = io_lsu_lxcpt_valid; // @[tracegen.scala:19:7] wire [31:0] io_lsu_lxcpt_bits_uop_inst_0 = io_lsu_lxcpt_bits_uop_inst; // @[tracegen.scala:19:7] wire [31:0] io_lsu_lxcpt_bits_uop_debug_inst_0 = io_lsu_lxcpt_bits_uop_debug_inst; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_is_rvc_0 = io_lsu_lxcpt_bits_uop_is_rvc; // @[tracegen.scala:19:7] wire [33:0] io_lsu_lxcpt_bits_uop_debug_pc_0 = io_lsu_lxcpt_bits_uop_debug_pc; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_iq_type_0_0 = io_lsu_lxcpt_bits_uop_iq_type_0; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_iq_type_1_0 = io_lsu_lxcpt_bits_uop_iq_type_1; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_iq_type_2_0 = io_lsu_lxcpt_bits_uop_iq_type_2; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_iq_type_3_0 = io_lsu_lxcpt_bits_uop_iq_type_3; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fu_code_0_0 = io_lsu_lxcpt_bits_uop_fu_code_0; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fu_code_1_0 = io_lsu_lxcpt_bits_uop_fu_code_1; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fu_code_2_0 = io_lsu_lxcpt_bits_uop_fu_code_2; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fu_code_3_0 = io_lsu_lxcpt_bits_uop_fu_code_3; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fu_code_4_0 = io_lsu_lxcpt_bits_uop_fu_code_4; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fu_code_5_0 = io_lsu_lxcpt_bits_uop_fu_code_5; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fu_code_6_0 = io_lsu_lxcpt_bits_uop_fu_code_6; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fu_code_7_0 = io_lsu_lxcpt_bits_uop_fu_code_7; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fu_code_8_0 = io_lsu_lxcpt_bits_uop_fu_code_8; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fu_code_9_0 = io_lsu_lxcpt_bits_uop_fu_code_9; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_iw_issued_0 = io_lsu_lxcpt_bits_uop_iw_issued; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_iw_issued_partial_agen_0 = io_lsu_lxcpt_bits_uop_iw_issued_partial_agen; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_iw_issued_partial_dgen_0 = io_lsu_lxcpt_bits_uop_iw_issued_partial_dgen; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_iw_p1_speculative_child_0 = io_lsu_lxcpt_bits_uop_iw_p1_speculative_child; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_iw_p2_speculative_child_0 = io_lsu_lxcpt_bits_uop_iw_p2_speculative_child; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_iw_p1_bypass_hint_0 = io_lsu_lxcpt_bits_uop_iw_p1_bypass_hint; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_iw_p2_bypass_hint_0 = io_lsu_lxcpt_bits_uop_iw_p2_bypass_hint; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_iw_p3_bypass_hint_0 = io_lsu_lxcpt_bits_uop_iw_p3_bypass_hint; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_dis_col_sel_0 = io_lsu_lxcpt_bits_uop_dis_col_sel; // @[tracegen.scala:19:7] wire [3:0] io_lsu_lxcpt_bits_uop_br_mask_0 = io_lsu_lxcpt_bits_uop_br_mask; // @[tracegen.scala:19:7] wire [1:0] io_lsu_lxcpt_bits_uop_br_tag_0 = io_lsu_lxcpt_bits_uop_br_tag; // @[tracegen.scala:19:7] wire [3:0] io_lsu_lxcpt_bits_uop_br_type_0 = io_lsu_lxcpt_bits_uop_br_type; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_is_sfb_0 = io_lsu_lxcpt_bits_uop_is_sfb; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_is_fence_0 = io_lsu_lxcpt_bits_uop_is_fence; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_is_fencei_0 = io_lsu_lxcpt_bits_uop_is_fencei; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_is_sfence_0 = io_lsu_lxcpt_bits_uop_is_sfence; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_is_amo_0 = io_lsu_lxcpt_bits_uop_is_amo; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_is_eret_0 = io_lsu_lxcpt_bits_uop_is_eret; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_is_sys_pc2epc_0 = io_lsu_lxcpt_bits_uop_is_sys_pc2epc; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_is_rocc_0 = io_lsu_lxcpt_bits_uop_is_rocc; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_is_mov_0 = io_lsu_lxcpt_bits_uop_is_mov; // @[tracegen.scala:19:7] wire [3:0] io_lsu_lxcpt_bits_uop_ftq_idx_0 = io_lsu_lxcpt_bits_uop_ftq_idx; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_edge_inst_0 = io_lsu_lxcpt_bits_uop_edge_inst; // @[tracegen.scala:19:7] wire [5:0] io_lsu_lxcpt_bits_uop_pc_lob_0 = io_lsu_lxcpt_bits_uop_pc_lob; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_taken_0 = io_lsu_lxcpt_bits_uop_taken; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_imm_rename_0 = io_lsu_lxcpt_bits_uop_imm_rename; // @[tracegen.scala:19:7] wire [2:0] io_lsu_lxcpt_bits_uop_imm_sel_0 = io_lsu_lxcpt_bits_uop_imm_sel; // @[tracegen.scala:19:7] wire [4:0] io_lsu_lxcpt_bits_uop_pimm_0 = io_lsu_lxcpt_bits_uop_pimm; // @[tracegen.scala:19:7] wire [19:0] io_lsu_lxcpt_bits_uop_imm_packed_0 = io_lsu_lxcpt_bits_uop_imm_packed; // @[tracegen.scala:19:7] wire [1:0] io_lsu_lxcpt_bits_uop_op1_sel_0 = io_lsu_lxcpt_bits_uop_op1_sel; // @[tracegen.scala:19:7] wire [2:0] io_lsu_lxcpt_bits_uop_op2_sel_0 = io_lsu_lxcpt_bits_uop_op2_sel; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_ldst_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_ldst; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_wen_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_wen; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_ren1_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_ren1; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_ren2_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_ren2; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_ren3_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_ren3; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_swap12_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_swap12; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_swap23_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_swap23; // @[tracegen.scala:19:7] wire [1:0] io_lsu_lxcpt_bits_uop_fp_ctrl_typeTagIn_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_typeTagIn; // @[tracegen.scala:19:7] wire [1:0] io_lsu_lxcpt_bits_uop_fp_ctrl_typeTagOut_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_typeTagOut; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_fromint_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_fromint; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_toint_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_toint; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_fastpipe_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_fastpipe; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_fma_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_fma; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_div_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_div; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_sqrt_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_sqrt; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_wflags_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_wflags; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_vec_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_vec; // @[tracegen.scala:19:7] wire [4:0] io_lsu_lxcpt_bits_uop_rob_idx_0 = io_lsu_lxcpt_bits_uop_rob_idx; // @[tracegen.scala:19:7] wire [3:0] io_lsu_lxcpt_bits_uop_ldq_idx_0 = io_lsu_lxcpt_bits_uop_ldq_idx; // @[tracegen.scala:19:7] wire [3:0] io_lsu_lxcpt_bits_uop_stq_idx_0 = io_lsu_lxcpt_bits_uop_stq_idx; // @[tracegen.scala:19:7] wire [1:0] io_lsu_lxcpt_bits_uop_rxq_idx_0 = io_lsu_lxcpt_bits_uop_rxq_idx; // @[tracegen.scala:19:7] wire [5:0] io_lsu_lxcpt_bits_uop_pdst_0 = io_lsu_lxcpt_bits_uop_pdst; // @[tracegen.scala:19:7] wire [5:0] io_lsu_lxcpt_bits_uop_prs1_0 = io_lsu_lxcpt_bits_uop_prs1; // @[tracegen.scala:19:7] wire [5:0] io_lsu_lxcpt_bits_uop_prs2_0 = io_lsu_lxcpt_bits_uop_prs2; // @[tracegen.scala:19:7] wire [5:0] io_lsu_lxcpt_bits_uop_prs3_0 = io_lsu_lxcpt_bits_uop_prs3; // @[tracegen.scala:19:7] wire [3:0] io_lsu_lxcpt_bits_uop_ppred_0 = io_lsu_lxcpt_bits_uop_ppred; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_prs1_busy_0 = io_lsu_lxcpt_bits_uop_prs1_busy; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_prs2_busy_0 = io_lsu_lxcpt_bits_uop_prs2_busy; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_prs3_busy_0 = io_lsu_lxcpt_bits_uop_prs3_busy; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_ppred_busy_0 = io_lsu_lxcpt_bits_uop_ppred_busy; // @[tracegen.scala:19:7] wire [5:0] io_lsu_lxcpt_bits_uop_stale_pdst_0 = io_lsu_lxcpt_bits_uop_stale_pdst; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_exception_0 = io_lsu_lxcpt_bits_uop_exception; // @[tracegen.scala:19:7] wire [63:0] io_lsu_lxcpt_bits_uop_exc_cause_0 = io_lsu_lxcpt_bits_uop_exc_cause; // @[tracegen.scala:19:7] wire [4:0] io_lsu_lxcpt_bits_uop_mem_cmd_0 = io_lsu_lxcpt_bits_uop_mem_cmd; // @[tracegen.scala:19:7] wire [1:0] io_lsu_lxcpt_bits_uop_mem_size_0 = io_lsu_lxcpt_bits_uop_mem_size; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_mem_signed_0 = io_lsu_lxcpt_bits_uop_mem_signed; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_uses_ldq_0 = io_lsu_lxcpt_bits_uop_uses_ldq; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_uses_stq_0 = io_lsu_lxcpt_bits_uop_uses_stq; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_is_unique_0 = io_lsu_lxcpt_bits_uop_is_unique; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_flush_on_commit_0 = io_lsu_lxcpt_bits_uop_flush_on_commit; // @[tracegen.scala:19:7] wire [2:0] io_lsu_lxcpt_bits_uop_csr_cmd_0 = io_lsu_lxcpt_bits_uop_csr_cmd; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_ldst_is_rs1_0 = io_lsu_lxcpt_bits_uop_ldst_is_rs1; // @[tracegen.scala:19:7] wire [5:0] io_lsu_lxcpt_bits_uop_ldst_0 = io_lsu_lxcpt_bits_uop_ldst; // @[tracegen.scala:19:7] wire [5:0] io_lsu_lxcpt_bits_uop_lrs1_0 = io_lsu_lxcpt_bits_uop_lrs1; // @[tracegen.scala:19:7] wire [5:0] io_lsu_lxcpt_bits_uop_lrs2_0 = io_lsu_lxcpt_bits_uop_lrs2; // @[tracegen.scala:19:7] wire [5:0] io_lsu_lxcpt_bits_uop_lrs3_0 = io_lsu_lxcpt_bits_uop_lrs3; // @[tracegen.scala:19:7] wire [1:0] io_lsu_lxcpt_bits_uop_dst_rtype_0 = io_lsu_lxcpt_bits_uop_dst_rtype; // @[tracegen.scala:19:7] wire [1:0] io_lsu_lxcpt_bits_uop_lrs1_rtype_0 = io_lsu_lxcpt_bits_uop_lrs1_rtype; // @[tracegen.scala:19:7] wire [1:0] io_lsu_lxcpt_bits_uop_lrs2_rtype_0 = io_lsu_lxcpt_bits_uop_lrs2_rtype; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_frs3_en_0 = io_lsu_lxcpt_bits_uop_frs3_en; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fcn_dw_0 = io_lsu_lxcpt_bits_uop_fcn_dw; // @[tracegen.scala:19:7] wire [4:0] io_lsu_lxcpt_bits_uop_fcn_op_0 = io_lsu_lxcpt_bits_uop_fcn_op; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_fp_val_0 = io_lsu_lxcpt_bits_uop_fp_val; // @[tracegen.scala:19:7] wire [2:0] io_lsu_lxcpt_bits_uop_fp_rm_0 = io_lsu_lxcpt_bits_uop_fp_rm; // @[tracegen.scala:19:7] wire [1:0] io_lsu_lxcpt_bits_uop_fp_typ_0 = io_lsu_lxcpt_bits_uop_fp_typ; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_xcpt_pf_if_0 = io_lsu_lxcpt_bits_uop_xcpt_pf_if; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_xcpt_ae_if_0 = io_lsu_lxcpt_bits_uop_xcpt_ae_if; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_xcpt_ma_if_0 = io_lsu_lxcpt_bits_uop_xcpt_ma_if; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_bp_debug_if_0 = io_lsu_lxcpt_bits_uop_bp_debug_if; // @[tracegen.scala:19:7] wire io_lsu_lxcpt_bits_uop_bp_xcpt_if_0 = io_lsu_lxcpt_bits_uop_bp_xcpt_if; // @[tracegen.scala:19:7] wire [2:0] io_lsu_lxcpt_bits_uop_debug_fsrc_0 = io_lsu_lxcpt_bits_uop_debug_fsrc; // @[tracegen.scala:19:7] wire [2:0] io_lsu_lxcpt_bits_uop_debug_tsrc_0 = io_lsu_lxcpt_bits_uop_debug_tsrc; // @[tracegen.scala:19:7] wire [4:0] io_lsu_lxcpt_bits_cause_0 = io_lsu_lxcpt_bits_cause; // @[tracegen.scala:19:7] wire [33:0] io_lsu_lxcpt_bits_badvaddr_0 = io_lsu_lxcpt_bits_badvaddr; // @[tracegen.scala:19:7] wire io_lsu_perf_acquire_0 = io_lsu_perf_acquire; // @[tracegen.scala:19:7] wire io_lsu_perf_release_0 = io_lsu_perf_release; // @[tracegen.scala:19:7] wire io_tracegen_req_valid_0 = io_tracegen_req_valid; // @[tracegen.scala:19:7] wire [33:0] io_tracegen_req_bits_addr_0 = io_tracegen_req_bits_addr; // @[tracegen.scala:19:7] wire [5:0] io_tracegen_req_bits_tag_0 = io_tracegen_req_bits_tag; // @[tracegen.scala:19:7] wire [4:0] io_tracegen_req_bits_cmd_0 = io_tracegen_req_bits_cmd; // @[tracegen.scala:19:7] wire [63:0] io_tracegen_req_bits_data_0 = io_tracegen_req_bits_data; // @[tracegen.scala:19:7] wire [63:0] io_tracegen_s1_data_data_0 = io_tracegen_s1_data_data; // @[tracegen.scala:19:7] wire [31:0] io_lsu_agen_0_bits_uop_inst = 32'h0; // @[tracegen.scala:19:7] wire [31:0] io_lsu_dgen_0_bits_uop_inst = 32'h0; // @[tracegen.scala:19:7] wire [31:0] io_lsu_dgen_1_bits_uop_inst = 32'h0; // @[tracegen.scala:19:7] wire [31:0] io_lsu_dgen_1_bits_uop_debug_inst = 32'h0; // @[tracegen.scala:19:7] wire [31:0] io_lsu_dgen_2_bits_uop_inst = 32'h0; // @[tracegen.scala:19:7] wire [31:0] io_lsu_dgen_2_bits_uop_debug_inst = 32'h0; // @[tracegen.scala:19:7] wire [31:0] io_lsu_dis_uops_0_bits_inst = 32'h0; // @[tracegen.scala:19:7] wire [31:0] io_lsu_commit_uops_0_inst_0 = 32'h0; // @[tracegen.scala:19:7] wire [31:0] io_lsu_commit_debug_insts_0 = 32'h0; // @[tracegen.scala:19:7] wire [31:0] io_lsu_brupdate_b2_uop_inst = 32'h0; // @[tracegen.scala:19:7] wire [31:0] io_lsu_brupdate_b2_uop_debug_inst = 32'h0; // @[tracegen.scala:19:7] wire [31:0] io_lsu_status_isa = 32'h0; // @[tracegen.scala:19:7] wire [31:0] io_tracegen_s2_paddr = 32'h0; // @[tracegen.scala:19:7] wire [31:0] _tracegen_uop_WIRE_inst = 32'h0; // @[tracegen.scala:55:45] wire [31:0] _tracegen_uop_WIRE_debug_inst = 32'h0; // @[tracegen.scala:55:45] wire [31:0] tracegen_uop_inst = 32'h0; // @[tracegen.scala:55:30] wire io_lsu_agen_0_bits_uop_is_rvc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_iq_type_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_iq_type_1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_iq_type_2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_iq_type_3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fu_code_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fu_code_1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fu_code_2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fu_code_3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fu_code_4 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fu_code_5 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fu_code_6 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fu_code_7 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fu_code_8 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fu_code_9 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_iw_issued = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_iw_issued_partial_agen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_iw_issued_partial_dgen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_iw_p1_speculative_child = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_iw_p2_speculative_child = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_iw_p1_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_iw_p2_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_iw_p3_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_dis_col_sel = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_is_sfb = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_is_fence = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_is_fencei = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_is_sfence = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_is_eret = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_is_rocc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_is_mov = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_edge_inst = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_taken = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_imm_rename = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_ldst = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_wen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_ren1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_ren2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_ren3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_swap12 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_swap23 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_fromint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_toint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_fastpipe = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_fma = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_div = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_sqrt = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_wflags = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_vec = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_prs1_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_prs2_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_prs3_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_ppred_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_exception = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_mem_signed = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_is_unique = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_flush_on_commit = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_frs3_en = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fcn_dw = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_fp_val = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_bp_debug_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_is_rvc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_iq_type_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_iq_type_1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_iq_type_2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_iq_type_3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fu_code_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fu_code_1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fu_code_2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fu_code_3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fu_code_4 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fu_code_5 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fu_code_6 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fu_code_7 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fu_code_8 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fu_code_9 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_iw_issued = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_iw_issued_partial_agen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_iw_issued_partial_dgen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_iw_p1_speculative_child = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_iw_p2_speculative_child = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_iw_p1_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_iw_p2_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_iw_p3_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_dis_col_sel = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_is_sfb = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_is_fence = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_is_fencei = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_is_sfence = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_is_eret = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_is_rocc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_is_mov = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_edge_inst = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_taken = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_imm_rename = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_ldst = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_wen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_ren1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_ren2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_ren3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_swap12 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_swap23 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_fromint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_toint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_fastpipe = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_fma = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_div = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_sqrt = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_wflags = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_vec = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_prs1_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_prs2_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_prs3_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_ppred_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_exception = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_mem_signed = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_is_unique = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_flush_on_commit = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_frs3_en = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fcn_dw = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_fp_val = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_bp_debug_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_valid = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_is_rvc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_iq_type_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_iq_type_1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_iq_type_2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_iq_type_3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fu_code_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fu_code_1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fu_code_2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fu_code_3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fu_code_4 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fu_code_5 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fu_code_6 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fu_code_7 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fu_code_8 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fu_code_9 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_iw_issued = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_iw_issued_partial_agen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_iw_issued_partial_dgen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_iw_p1_speculative_child = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_iw_p2_speculative_child = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_iw_p1_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_iw_p2_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_iw_p3_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_dis_col_sel = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_is_sfb = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_is_fence = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_is_fencei = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_is_sfence = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_is_amo = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_is_eret = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_is_rocc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_is_mov = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_edge_inst = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_taken = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_imm_rename = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_ldst = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_wen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_ren1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_ren2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_ren3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_swap12 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_swap23 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_fromint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_toint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_fastpipe = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_fma = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_div = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_sqrt = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_wflags = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_vec = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_prs1_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_prs2_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_prs3_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_ppred_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_exception = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_mem_signed = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_uses_ldq = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_uses_stq = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_is_unique = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_flush_on_commit = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_frs3_en = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fcn_dw = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_fp_val = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_bp_debug_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_1_bits_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_valid = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_is_rvc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_iq_type_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_iq_type_1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_iq_type_2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_iq_type_3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fu_code_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fu_code_1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fu_code_2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fu_code_3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fu_code_4 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fu_code_5 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fu_code_6 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fu_code_7 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fu_code_8 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fu_code_9 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_iw_issued = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_iw_p1_speculative_child = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_iw_p2_speculative_child = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_iw_p1_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_iw_p2_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_iw_p3_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_dis_col_sel = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_is_sfb = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_is_fence = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_is_fencei = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_is_sfence = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_is_amo = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_is_eret = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_is_rocc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_is_mov = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_edge_inst = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_taken = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_imm_rename = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_ldst = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_wen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_ren1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_ren2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_ren3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_swap12 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_swap23 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_fromint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_toint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_fastpipe = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_fma = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_div = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_sqrt = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_wflags = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_vec = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_prs1_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_prs2_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_prs3_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_ppred_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_exception = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_mem_signed = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_uses_ldq = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_uses_stq = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_is_unique = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_flush_on_commit = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_frs3_en = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fcn_dw = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_fp_val = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_bp_debug_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dgen_2_bits_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_predicated = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_iresp_0_bits_fflags_valid = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_predicated = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_fresp_0_bits_fflags_valid = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_sfence_valid = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_sfence_bits_rs1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_sfence_bits_rs2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_sfence_bits_asid = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_sfence_bits_hv = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_sfence_bits_hg = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_is_rvc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_iq_type_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_iq_type_1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_iq_type_2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_iq_type_3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fu_code_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fu_code_1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fu_code_2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fu_code_3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fu_code_4 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fu_code_5 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fu_code_6 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fu_code_7 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fu_code_8 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fu_code_9 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_iw_issued = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_iw_issued_partial_agen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_iw_issued_partial_dgen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_iw_p1_speculative_child = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_iw_p2_speculative_child = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_iw_p1_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_iw_p2_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_iw_p3_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_dis_col_sel = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_is_sfb = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_is_fence = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_is_fencei = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_is_sfence = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_is_eret = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_is_sys_pc2epc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_is_rocc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_is_mov = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_edge_inst = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_taken = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_imm_rename = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_ldst = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_wen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_ren1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_ren2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_ren3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_swap12 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_swap23 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_fromint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_toint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_fastpipe = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_fma = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_div = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_sqrt = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_wflags = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_vec = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_prs1_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_prs2_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_prs3_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_ppred_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_exception = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_mem_signed = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_is_unique = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_flush_on_commit = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_ldst_is_rs1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_frs3_en = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fcn_dw = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_fp_val = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_xcpt_pf_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_xcpt_ae_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_xcpt_ma_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_bp_debug_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_bp_xcpt_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_arch_valids_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_is_rvc_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_iq_type_0_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_iq_type_1_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_iq_type_2_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_iq_type_3_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fu_code_0_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fu_code_1_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fu_code_2_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fu_code_3_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fu_code_4_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fu_code_5_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fu_code_6_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fu_code_7_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fu_code_8_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fu_code_9_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_iw_issued_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_iw_issued_partial_agen_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_iw_issued_partial_dgen_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_iw_p1_speculative_child_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_iw_p2_speculative_child_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_iw_p1_bypass_hint_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_iw_p2_bypass_hint_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_iw_p3_bypass_hint_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_dis_col_sel_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_is_sfb_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_is_fence_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_is_fencei_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_is_sfence_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_is_eret_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_is_sys_pc2epc_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_is_rocc_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_is_mov_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_edge_inst_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_taken_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_imm_rename_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_ctrl_ldst_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_ctrl_wen_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_ctrl_ren1_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_ctrl_ren2_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_ctrl_ren3_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_ctrl_swap12_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_ctrl_swap23_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_ctrl_fromint_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_ctrl_toint_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_ctrl_fastpipe_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_ctrl_fma_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_ctrl_div_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_ctrl_sqrt_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_ctrl_wflags_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_ctrl_vec_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_prs1_busy_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_prs2_busy_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_prs3_busy_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_ppred_busy_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_exception_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_mem_signed_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_is_unique_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_flush_on_commit_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_ldst_is_rs1_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_frs3_en_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fcn_dw_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_fp_val_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_xcpt_pf_if_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_xcpt_ae_if_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_xcpt_ma_if_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_bp_debug_if_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_bp_xcpt_if_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_fflags_valid = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_commit_load_at_rob_head = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_fence_dmem = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_is_rvc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_iq_type_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_iq_type_1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_iq_type_2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_iq_type_3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fu_code_0 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fu_code_1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fu_code_2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fu_code_3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fu_code_4 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fu_code_5 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fu_code_6 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fu_code_7 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fu_code_8 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fu_code_9 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_iw_issued = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_iw_issued_partial_agen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_iw_issued_partial_dgen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_iw_p1_speculative_child = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_iw_p2_speculative_child = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_iw_p1_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_iw_p2_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_iw_p3_bypass_hint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_dis_col_sel = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_is_sfb = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_is_fence = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_is_fencei = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_is_sfence = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_is_amo = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_is_eret = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_is_rocc = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_is_mov = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_edge_inst = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_taken = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_imm_rename = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_ldst = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_wen = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_ren1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_ren2 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_ren3 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_swap12 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_swap23 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_fromint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_toint = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_fastpipe = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_fma = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_div = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_sqrt = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_wflags = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_vec = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_prs1_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_prs2_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_prs3_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_ppred_busy = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_exception = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_mem_signed = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_uses_ldq = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_uses_stq = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_is_unique = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_flush_on_commit = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_frs3_en = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fcn_dw = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_fp_val = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_bp_debug_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_mispredict = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_brupdate_b2_taken = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_exception = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_tsc_reg = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_debug = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_cease = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_wfi = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_dv = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_v = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_sd = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_mpv = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_gva = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_mbe = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_sbe = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_sd_rv32 = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_tsr = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_tw = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_tvm = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_mxr = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_sum = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_mprv = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_spp = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_mpie = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_ube = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_spie = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_upie = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_mie = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_hie = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_sie = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_status_uie = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_mcontext = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_scontext = 1'h0; // @[tracegen.scala:19:7] wire io_lsu_perf_tlbMiss = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_req_bits_signed = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_req_bits_dv = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_req_bits_phys = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_req_bits_no_resp = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_req_bits_no_alloc = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_req_bits_no_xcpt = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_s1_kill = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_s2_nack = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_s2_nack_cause_raw = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_s2_kill = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_s2_uncached = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_resp_bits_signed = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_resp_bits_dv = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_resp_bits_replay = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_resp_bits_has_data = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_replay_next = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_s2_xcpt_ma_ld = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_s2_xcpt_ma_st = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_s2_xcpt_pf_ld = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_s2_xcpt_pf_st = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_s2_xcpt_gf_ld = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_s2_xcpt_gf_st = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_s2_xcpt_ae_ld = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_s2_xcpt_ae_st = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_s2_gpa_is_pte = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_store_pending = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_perf_acquire = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_perf_release = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_perf_grant = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_perf_tlbMiss = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_perf_blocked = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_perf_canAcceptStoreThenLoad = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_perf_canAcceptStoreThenRMW = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_perf_canAcceptLoadThenLoad = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_perf_storeBufferEmptyAfterLoad = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_perf_storeBufferEmptyAfterStore = 1'h0; // @[tracegen.scala:19:7] wire io_tracegen_clock_enabled = 1'h0; // @[tracegen.scala:19:7] wire _rob_bsy_WIRE_0 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_1 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_2 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_3 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_4 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_5 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_6 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_7 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_8 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_9 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_10 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_11 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_12 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_13 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_14 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_15 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_16 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_17 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_18 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_19 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_20 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_21 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_22 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_23 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_24 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_25 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_26 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_27 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_28 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_29 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_30 = 1'h0; // @[tracegen.scala:33:33] wire _rob_bsy_WIRE_31 = 1'h0; // @[tracegen.scala:33:33] wire _tracegen_uop_WIRE_is_rvc = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_iq_type_0 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_iq_type_1 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_iq_type_2 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_iq_type_3 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fu_code_0 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fu_code_1 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fu_code_2 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fu_code_3 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fu_code_4 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fu_code_5 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fu_code_6 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fu_code_7 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fu_code_8 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fu_code_9 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_iw_issued = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_iw_issued_partial_agen = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_iw_issued_partial_dgen = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_iw_p1_speculative_child = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_iw_p2_speculative_child = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_iw_p1_bypass_hint = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_iw_p2_bypass_hint = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_iw_p3_bypass_hint = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_dis_col_sel = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_is_sfb = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_is_fence = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_is_fencei = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_is_sfence = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_is_amo = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_is_eret = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_is_sys_pc2epc = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_is_rocc = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_is_mov = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_edge_inst = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_taken = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_imm_rename = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_ctrl_ldst = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_ctrl_wen = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_ctrl_ren1 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_ctrl_ren2 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_ctrl_ren3 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_ctrl_swap12 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_ctrl_swap23 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_ctrl_fromint = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_ctrl_toint = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_ctrl_fastpipe = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_ctrl_fma = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_ctrl_div = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_ctrl_sqrt = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_ctrl_wflags = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_ctrl_vec = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_prs1_busy = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_prs2_busy = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_prs3_busy = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_ppred_busy = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_exception = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_mem_signed = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_uses_ldq = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_uses_stq = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_is_unique = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_flush_on_commit = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_ldst_is_rs1 = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_frs3_en = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fcn_dw = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_fp_val = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_xcpt_pf_if = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_xcpt_ae_if = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_xcpt_ma_if = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_bp_debug_if = 1'h0; // @[tracegen.scala:55:45] wire _tracegen_uop_WIRE_bp_xcpt_if = 1'h0; // @[tracegen.scala:55:45] wire tracegen_uop_is_rvc = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_iq_type_0 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_iq_type_1 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_iq_type_2 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_iq_type_3 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fu_code_0 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fu_code_1 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fu_code_2 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fu_code_3 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fu_code_4 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fu_code_5 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fu_code_6 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fu_code_7 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fu_code_8 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fu_code_9 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_iw_issued = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_iw_issued_partial_agen = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_iw_issued_partial_dgen = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_iw_p1_speculative_child = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_iw_p2_speculative_child = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_iw_p1_bypass_hint = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_iw_p2_bypass_hint = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_iw_p3_bypass_hint = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_dis_col_sel = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_is_sfb = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_is_fence = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_is_fencei = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_is_sfence = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_is_eret = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_is_sys_pc2epc = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_is_rocc = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_is_mov = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_edge_inst = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_taken = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_imm_rename = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_ctrl_ldst = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_ctrl_wen = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_ctrl_ren1 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_ctrl_ren2 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_ctrl_ren3 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_ctrl_swap12 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_ctrl_swap23 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_ctrl_fromint = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_ctrl_toint = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_ctrl_fastpipe = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_ctrl_fma = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_ctrl_div = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_ctrl_sqrt = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_ctrl_wflags = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_ctrl_vec = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_prs1_busy = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_prs2_busy = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_prs3_busy = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_ppred_busy = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_exception = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_mem_signed = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_is_unique = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_flush_on_commit = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_ldst_is_rs1 = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_frs3_en = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fcn_dw = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_fp_val = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_xcpt_pf_if = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_xcpt_ae_if = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_xcpt_ma_if = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_bp_debug_if = 1'h0; // @[tracegen.scala:55:30] wire tracegen_uop_bp_xcpt_if = 1'h0; // @[tracegen.scala:55:30] wire [33:0] io_lsu_agen_0_bits_uop_debug_pc = 34'h0; // @[tracegen.scala:19:7] wire [33:0] io_lsu_dgen_0_bits_uop_debug_pc = 34'h0; // @[tracegen.scala:19:7] wire [33:0] io_lsu_dgen_1_bits_uop_debug_pc = 34'h0; // @[tracegen.scala:19:7] wire [33:0] io_lsu_dgen_2_bits_uop_debug_pc = 34'h0; // @[tracegen.scala:19:7] wire [33:0] io_lsu_dis_uops_0_bits_debug_pc = 34'h0; // @[tracegen.scala:19:7] wire [33:0] io_lsu_commit_uops_0_debug_pc_0 = 34'h0; // @[tracegen.scala:19:7] wire [33:0] io_lsu_brupdate_b2_uop_debug_pc = 34'h0; // @[tracegen.scala:19:7] wire [33:0] io_lsu_brupdate_b2_jalr_target = 34'h0; // @[tracegen.scala:19:7] wire [33:0] io_tracegen_resp_bits_addr = 34'h0; // @[tracegen.scala:19:7] wire [33:0] io_tracegen_s2_gpa = 34'h0; // @[tracegen.scala:19:7] wire [33:0] _tracegen_uop_WIRE_debug_pc = 34'h0; // @[tracegen.scala:55:45] wire [33:0] tracegen_uop_debug_pc = 34'h0; // @[tracegen.scala:55:30] wire [3:0] io_lsu_agen_0_bits_uop_br_mask = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_agen_0_bits_uop_br_type = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_agen_0_bits_uop_ftq_idx = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_agen_0_bits_uop_ppred = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_0_bits_uop_br_mask = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_0_bits_uop_br_type = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_0_bits_uop_ftq_idx = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_0_bits_uop_ppred = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_1_bits_uop_br_mask = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_1_bits_uop_br_type = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_1_bits_uop_ftq_idx = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_1_bits_uop_ldq_idx = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_1_bits_uop_stq_idx = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_1_bits_uop_ppred = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_2_bits_uop_br_mask = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_2_bits_uop_br_type = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_2_bits_uop_ftq_idx = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_2_bits_uop_ldq_idx = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_2_bits_uop_stq_idx = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_2_bits_uop_ppred = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dis_uops_0_bits_br_mask = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dis_uops_0_bits_br_type = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dis_uops_0_bits_ftq_idx = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dis_uops_0_bits_ppred = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_commit_uops_0_br_mask_0 = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_commit_uops_0_br_type_0 = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_commit_uops_0_ftq_idx_0 = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_commit_uops_0_ppred_0 = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_brupdate_b1_resolve_mask = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_brupdate_b1_mispredict_mask = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_brupdate_b2_uop_br_mask = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_brupdate_b2_uop_br_type = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_brupdate_b2_uop_ftq_idx = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_brupdate_b2_uop_ldq_idx = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_brupdate_b2_uop_stq_idx = 4'h0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_brupdate_b2_uop_ppred = 4'h0; // @[tracegen.scala:19:7] wire [3:0] _tracegen_uop_WIRE_br_mask = 4'h0; // @[tracegen.scala:55:45] wire [3:0] _tracegen_uop_WIRE_br_type = 4'h0; // @[tracegen.scala:55:45] wire [3:0] _tracegen_uop_WIRE_ftq_idx = 4'h0; // @[tracegen.scala:55:45] wire [3:0] _tracegen_uop_WIRE_ldq_idx = 4'h0; // @[tracegen.scala:55:45] wire [3:0] _tracegen_uop_WIRE_stq_idx = 4'h0; // @[tracegen.scala:55:45] wire [3:0] _tracegen_uop_WIRE_ppred = 4'h0; // @[tracegen.scala:55:45] wire [3:0] tracegen_uop_br_mask = 4'h0; // @[tracegen.scala:55:30] wire [3:0] tracegen_uop_br_type = 4'h0; // @[tracegen.scala:55:30] wire [3:0] tracegen_uop_ftq_idx = 4'h0; // @[tracegen.scala:55:30] wire [3:0] tracegen_uop_ppred = 4'h0; // @[tracegen.scala:55:30] wire [3:0] _io_lsu_brupdate_b1_WIRE_resolve_mask = 4'h0; // @[tracegen.scala:151:39] wire [3:0] _io_lsu_brupdate_b1_WIRE_mispredict_mask = 4'h0; // @[tracegen.scala:151:39] wire [1:0] io_lsu_agen_0_bits_uop_br_tag = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_agen_0_bits_uop_op1_sel = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_agen_0_bits_uop_fp_ctrl_typeTagIn = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_agen_0_bits_uop_fp_ctrl_typeTagOut = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_agen_0_bits_uop_rxq_idx = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_agen_0_bits_uop_dst_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_agen_0_bits_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_agen_0_bits_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_agen_0_bits_uop_fp_typ = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_0_bits_uop_br_tag = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_0_bits_uop_op1_sel = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_0_bits_uop_fp_ctrl_typeTagIn = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_0_bits_uop_fp_ctrl_typeTagOut = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_0_bits_uop_rxq_idx = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_0_bits_uop_dst_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_0_bits_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_0_bits_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_0_bits_uop_fp_typ = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_1_bits_uop_br_tag = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_1_bits_uop_op1_sel = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_1_bits_uop_fp_ctrl_typeTagIn = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_1_bits_uop_fp_ctrl_typeTagOut = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_1_bits_uop_rxq_idx = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_1_bits_uop_mem_size = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_1_bits_uop_dst_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_1_bits_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_1_bits_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_1_bits_uop_fp_typ = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_2_bits_uop_br_tag = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_2_bits_uop_op1_sel = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_2_bits_uop_fp_ctrl_typeTagIn = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_2_bits_uop_fp_ctrl_typeTagOut = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_2_bits_uop_rxq_idx = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_2_bits_uop_mem_size = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_2_bits_uop_dst_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_2_bits_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_2_bits_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_2_bits_uop_fp_typ = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dis_uops_0_bits_br_tag = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dis_uops_0_bits_op1_sel = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dis_uops_0_bits_fp_ctrl_typeTagIn = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dis_uops_0_bits_fp_ctrl_typeTagOut = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dis_uops_0_bits_rxq_idx = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dis_uops_0_bits_dst_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dis_uops_0_bits_lrs1_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dis_uops_0_bits_lrs2_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dis_uops_0_bits_fp_typ = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_commit_uops_0_br_tag_0 = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_commit_uops_0_op1_sel_0 = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_commit_uops_0_fp_ctrl_typeTagIn_0 = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_commit_uops_0_fp_ctrl_typeTagOut_0 = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_commit_uops_0_rxq_idx_0 = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_commit_uops_0_dst_rtype_0 = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_commit_uops_0_lrs1_rtype_0 = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_commit_uops_0_lrs2_rtype_0 = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_commit_uops_0_fp_typ_0 = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_brupdate_b2_uop_br_tag = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_brupdate_b2_uop_op1_sel = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_brupdate_b2_uop_fp_ctrl_typeTagIn = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_brupdate_b2_uop_fp_ctrl_typeTagOut = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_brupdate_b2_uop_rxq_idx = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_brupdate_b2_uop_mem_size = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_brupdate_b2_uop_dst_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_brupdate_b2_uop_fp_typ = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_brupdate_b2_pc_sel = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_status_dprv = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_status_prv = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_status_sxl = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_status_uxl = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_status_xs = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_status_fs = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_status_mpp = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_lsu_status_vs = 2'h0; // @[tracegen.scala:19:7] wire [1:0] io_tracegen_resp_bits_dprv = 2'h0; // @[tracegen.scala:19:7] wire [1:0] _tracegen_uop_WIRE_br_tag = 2'h0; // @[tracegen.scala:55:45] wire [1:0] _tracegen_uop_WIRE_op1_sel = 2'h0; // @[tracegen.scala:55:45] wire [1:0] _tracegen_uop_WIRE_fp_ctrl_typeTagIn = 2'h0; // @[tracegen.scala:55:45] wire [1:0] _tracegen_uop_WIRE_fp_ctrl_typeTagOut = 2'h0; // @[tracegen.scala:55:45] wire [1:0] _tracegen_uop_WIRE_rxq_idx = 2'h0; // @[tracegen.scala:55:45] wire [1:0] _tracegen_uop_WIRE_mem_size = 2'h0; // @[tracegen.scala:55:45] wire [1:0] _tracegen_uop_WIRE_dst_rtype = 2'h0; // @[tracegen.scala:55:45] wire [1:0] _tracegen_uop_WIRE_lrs1_rtype = 2'h0; // @[tracegen.scala:55:45] wire [1:0] _tracegen_uop_WIRE_lrs2_rtype = 2'h0; // @[tracegen.scala:55:45] wire [1:0] _tracegen_uop_WIRE_fp_typ = 2'h0; // @[tracegen.scala:55:45] wire [1:0] tracegen_uop_br_tag = 2'h0; // @[tracegen.scala:55:30] wire [1:0] tracegen_uop_op1_sel = 2'h0; // @[tracegen.scala:55:30] wire [1:0] tracegen_uop_fp_ctrl_typeTagIn = 2'h0; // @[tracegen.scala:55:30] wire [1:0] tracegen_uop_fp_ctrl_typeTagOut = 2'h0; // @[tracegen.scala:55:30] wire [1:0] tracegen_uop_rxq_idx = 2'h0; // @[tracegen.scala:55:30] wire [1:0] tracegen_uop_dst_rtype = 2'h0; // @[tracegen.scala:55:30] wire [1:0] tracegen_uop_lrs1_rtype = 2'h0; // @[tracegen.scala:55:30] wire [1:0] tracegen_uop_lrs2_rtype = 2'h0; // @[tracegen.scala:55:30] wire [1:0] tracegen_uop_fp_typ = 2'h0; // @[tracegen.scala:55:30] wire [5:0] io_lsu_agen_0_bits_uop_pc_lob = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_agen_0_bits_uop_pdst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_agen_0_bits_uop_prs1 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_agen_0_bits_uop_prs2 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_agen_0_bits_uop_prs3 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_agen_0_bits_uop_stale_pdst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_agen_0_bits_uop_ldst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_agen_0_bits_uop_lrs1 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_agen_0_bits_uop_lrs2 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_agen_0_bits_uop_lrs3 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_0_bits_uop_pc_lob = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_0_bits_uop_pdst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_0_bits_uop_prs1 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_0_bits_uop_prs2 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_0_bits_uop_prs3 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_0_bits_uop_stale_pdst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_0_bits_uop_ldst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_0_bits_uop_lrs1 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_0_bits_uop_lrs2 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_0_bits_uop_lrs3 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_1_bits_uop_pc_lob = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_1_bits_uop_pdst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_1_bits_uop_prs1 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_1_bits_uop_prs2 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_1_bits_uop_prs3 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_1_bits_uop_stale_pdst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_1_bits_uop_ldst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_1_bits_uop_lrs1 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_1_bits_uop_lrs2 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_1_bits_uop_lrs3 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_2_bits_uop_pc_lob = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_2_bits_uop_pdst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_2_bits_uop_prs1 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_2_bits_uop_prs2 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_2_bits_uop_prs3 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_2_bits_uop_stale_pdst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_2_bits_uop_ldst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_2_bits_uop_lrs1 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_2_bits_uop_lrs2 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dgen_2_bits_uop_lrs3 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dis_uops_0_bits_pc_lob = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dis_uops_0_bits_pdst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dis_uops_0_bits_prs1 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dis_uops_0_bits_prs2 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dis_uops_0_bits_prs3 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dis_uops_0_bits_stale_pdst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dis_uops_0_bits_ldst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dis_uops_0_bits_lrs1 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dis_uops_0_bits_lrs2 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_dis_uops_0_bits_lrs3 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_commit_uops_0_pc_lob_0 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_commit_uops_0_pdst_0 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_commit_uops_0_prs1_0 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_commit_uops_0_prs2_0 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_commit_uops_0_prs3_0 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_commit_uops_0_stale_pdst_0 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_commit_uops_0_ldst_0 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_commit_uops_0_lrs1_0 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_commit_uops_0_lrs2_0 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_commit_uops_0_lrs3_0 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_brupdate_b2_uop_pc_lob = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_brupdate_b2_uop_pdst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_brupdate_b2_uop_prs1 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_brupdate_b2_uop_prs2 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_brupdate_b2_uop_prs3 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_brupdate_b2_uop_stale_pdst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_brupdate_b2_uop_ldst = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_brupdate_b2_uop_lrs1 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_brupdate_b2_uop_lrs2 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] io_lsu_brupdate_b2_uop_lrs3 = 6'h0; // @[tracegen.scala:19:7] wire [5:0] _tracegen_uop_WIRE_pc_lob = 6'h0; // @[tracegen.scala:55:45] wire [5:0] _tracegen_uop_WIRE_pdst = 6'h0; // @[tracegen.scala:55:45] wire [5:0] _tracegen_uop_WIRE_prs1 = 6'h0; // @[tracegen.scala:55:45] wire [5:0] _tracegen_uop_WIRE_prs2 = 6'h0; // @[tracegen.scala:55:45] wire [5:0] _tracegen_uop_WIRE_prs3 = 6'h0; // @[tracegen.scala:55:45] wire [5:0] _tracegen_uop_WIRE_stale_pdst = 6'h0; // @[tracegen.scala:55:45] wire [5:0] _tracegen_uop_WIRE_ldst = 6'h0; // @[tracegen.scala:55:45] wire [5:0] _tracegen_uop_WIRE_lrs1 = 6'h0; // @[tracegen.scala:55:45] wire [5:0] _tracegen_uop_WIRE_lrs2 = 6'h0; // @[tracegen.scala:55:45] wire [5:0] _tracegen_uop_WIRE_lrs3 = 6'h0; // @[tracegen.scala:55:45] wire [5:0] tracegen_uop_pc_lob = 6'h0; // @[tracegen.scala:55:30] wire [5:0] tracegen_uop_pdst = 6'h0; // @[tracegen.scala:55:30] wire [5:0] tracegen_uop_prs1 = 6'h0; // @[tracegen.scala:55:30] wire [5:0] tracegen_uop_prs2 = 6'h0; // @[tracegen.scala:55:30] wire [5:0] tracegen_uop_prs3 = 6'h0; // @[tracegen.scala:55:30] wire [5:0] tracegen_uop_stale_pdst = 6'h0; // @[tracegen.scala:55:30] wire [5:0] tracegen_uop_ldst = 6'h0; // @[tracegen.scala:55:30] wire [5:0] tracegen_uop_lrs1 = 6'h0; // @[tracegen.scala:55:30] wire [5:0] tracegen_uop_lrs2 = 6'h0; // @[tracegen.scala:55:30] wire [5:0] tracegen_uop_lrs3 = 6'h0; // @[tracegen.scala:55:30] wire [2:0] io_lsu_agen_0_bits_uop_imm_sel = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_agen_0_bits_uop_op2_sel = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_agen_0_bits_uop_csr_cmd = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_agen_0_bits_uop_fp_rm = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_agen_0_bits_uop_debug_fsrc = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_agen_0_bits_uop_debug_tsrc = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_0_bits_uop_imm_sel = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_0_bits_uop_op2_sel = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_0_bits_uop_csr_cmd = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_0_bits_uop_fp_rm = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_0_bits_uop_debug_fsrc = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_0_bits_uop_debug_tsrc = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_1_bits_uop_imm_sel = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_1_bits_uop_op2_sel = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_1_bits_uop_csr_cmd = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_1_bits_uop_fp_rm = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_1_bits_uop_debug_fsrc = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_1_bits_uop_debug_tsrc = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_2_bits_uop_imm_sel = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_2_bits_uop_op2_sel = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_2_bits_uop_csr_cmd = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_2_bits_uop_fp_rm = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_2_bits_uop_debug_fsrc = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dgen_2_bits_uop_debug_tsrc = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dis_uops_0_bits_imm_sel = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dis_uops_0_bits_op2_sel = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dis_uops_0_bits_csr_cmd = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dis_uops_0_bits_fp_rm = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dis_uops_0_bits_debug_fsrc = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_dis_uops_0_bits_debug_tsrc = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_commit_uops_0_imm_sel_0 = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_commit_uops_0_op2_sel_0 = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_commit_uops_0_csr_cmd_0 = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_commit_uops_0_fp_rm_0 = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_commit_uops_0_debug_fsrc_0 = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_commit_uops_0_debug_tsrc_0 = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_brupdate_b2_uop_imm_sel = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_brupdate_b2_uop_op2_sel = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_brupdate_b2_uop_csr_cmd = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_brupdate_b2_uop_fp_rm = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_brupdate_b2_uop_debug_fsrc = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_brupdate_b2_uop_debug_tsrc = 3'h0; // @[tracegen.scala:19:7] wire [2:0] io_lsu_brupdate_b2_cfi_type = 3'h0; // @[tracegen.scala:19:7] wire [2:0] _tracegen_uop_WIRE_imm_sel = 3'h0; // @[tracegen.scala:55:45] wire [2:0] _tracegen_uop_WIRE_op2_sel = 3'h0; // @[tracegen.scala:55:45] wire [2:0] _tracegen_uop_WIRE_csr_cmd = 3'h0; // @[tracegen.scala:55:45] wire [2:0] _tracegen_uop_WIRE_fp_rm = 3'h0; // @[tracegen.scala:55:45] wire [2:0] _tracegen_uop_WIRE_debug_fsrc = 3'h0; // @[tracegen.scala:55:45] wire [2:0] _tracegen_uop_WIRE_debug_tsrc = 3'h0; // @[tracegen.scala:55:45] wire [2:0] tracegen_uop_imm_sel = 3'h0; // @[tracegen.scala:55:30] wire [2:0] tracegen_uop_op2_sel = 3'h0; // @[tracegen.scala:55:30] wire [2:0] tracegen_uop_csr_cmd = 3'h0; // @[tracegen.scala:55:30] wire [2:0] tracegen_uop_fp_rm = 3'h0; // @[tracegen.scala:55:30] wire [2:0] tracegen_uop_debug_fsrc = 3'h0; // @[tracegen.scala:55:30] wire [2:0] tracegen_uop_debug_tsrc = 3'h0; // @[tracegen.scala:55:30] wire [4:0] io_lsu_agen_0_bits_uop_pimm = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_agen_0_bits_uop_fcn_op = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dgen_0_bits_uop_pimm = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dgen_0_bits_uop_fcn_op = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dgen_1_bits_uop_pimm = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dgen_1_bits_uop_rob_idx = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dgen_1_bits_uop_mem_cmd = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dgen_1_bits_uop_fcn_op = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dgen_2_bits_uop_pimm = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dgen_2_bits_uop_rob_idx = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dgen_2_bits_uop_mem_cmd = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dgen_2_bits_uop_fcn_op = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_iresp_0_bits_fflags_bits = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_fresp_0_bits_fflags_bits = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dis_uops_0_bits_pimm = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dis_uops_0_bits_fcn_op = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_commit_uops_0_pimm_0 = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_commit_uops_0_fcn_op_0 = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_commit_fflags_bits = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_brupdate_b2_uop_pimm = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_brupdate_b2_uop_rob_idx = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_brupdate_b2_uop_mem_cmd = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_brupdate_b2_uop_fcn_op = 5'h0; // @[tracegen.scala:19:7] wire [4:0] io_tracegen_resp_bits_cmd = 5'h0; // @[tracegen.scala:19:7] wire [4:0] _tracegen_uop_WIRE_pimm = 5'h0; // @[tracegen.scala:55:45] wire [4:0] _tracegen_uop_WIRE_rob_idx = 5'h0; // @[tracegen.scala:55:45] wire [4:0] _tracegen_uop_WIRE_mem_cmd = 5'h0; // @[tracegen.scala:55:45] wire [4:0] _tracegen_uop_WIRE_fcn_op = 5'h0; // @[tracegen.scala:55:45] wire [4:0] tracegen_uop_pimm = 5'h0; // @[tracegen.scala:55:30] wire [4:0] tracegen_uop_fcn_op = 5'h0; // @[tracegen.scala:55:30] wire [19:0] io_lsu_agen_0_bits_uop_imm_packed = 20'h0; // @[tracegen.scala:19:7] wire [19:0] io_lsu_dgen_0_bits_uop_imm_packed = 20'h0; // @[tracegen.scala:19:7] wire [19:0] io_lsu_dgen_1_bits_uop_imm_packed = 20'h0; // @[tracegen.scala:19:7] wire [19:0] io_lsu_dgen_2_bits_uop_imm_packed = 20'h0; // @[tracegen.scala:19:7] wire [19:0] io_lsu_dis_uops_0_bits_imm_packed = 20'h0; // @[tracegen.scala:19:7] wire [19:0] io_lsu_commit_uops_0_imm_packed_0 = 20'h0; // @[tracegen.scala:19:7] wire [19:0] io_lsu_brupdate_b2_uop_imm_packed = 20'h0; // @[tracegen.scala:19:7] wire [19:0] _tracegen_uop_WIRE_imm_packed = 20'h0; // @[tracegen.scala:55:45] wire [19:0] tracegen_uop_imm_packed = 20'h0; // @[tracegen.scala:55:30] wire [63:0] io_lsu_agen_0_bits_uop_exc_cause = 64'h0; // @[tracegen.scala:19:7] wire [63:0] io_lsu_dgen_0_bits_uop_exc_cause = 64'h0; // @[tracegen.scala:19:7] wire [63:0] io_lsu_dgen_1_bits_uop_exc_cause = 64'h0; // @[tracegen.scala:19:7] wire [63:0] io_lsu_dgen_1_bits_data = 64'h0; // @[tracegen.scala:19:7] wire [63:0] io_lsu_dgen_2_bits_uop_exc_cause = 64'h0; // @[tracegen.scala:19:7] wire [63:0] io_lsu_dgen_2_bits_data = 64'h0; // @[tracegen.scala:19:7] wire [63:0] io_lsu_dis_uops_0_bits_exc_cause = 64'h0; // @[tracegen.scala:19:7] wire [63:0] io_lsu_commit_uops_0_exc_cause_0 = 64'h0; // @[tracegen.scala:19:7] wire [63:0] io_lsu_commit_debug_wdata_0 = 64'h0; // @[tracegen.scala:19:7] wire [63:0] io_lsu_brupdate_b2_uop_exc_cause = 64'h0; // @[tracegen.scala:19:7] wire [63:0] io_tracegen_resp_bits_data_word_bypass = 64'h0; // @[tracegen.scala:19:7] wire [63:0] io_tracegen_resp_bits_data_raw = 64'h0; // @[tracegen.scala:19:7] wire [63:0] io_tracegen_resp_bits_store_data = 64'h0; // @[tracegen.scala:19:7] wire [63:0] _tracegen_uop_WIRE_exc_cause = 64'h0; // @[tracegen.scala:55:45] wire [63:0] tracegen_uop_exc_cause = 64'h0; // @[tracegen.scala:55:30] wire [1:0] io_lsu_agen_0_bits_uop_mem_size = 2'h3; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dgen_0_bits_uop_mem_size = 2'h3; // @[tracegen.scala:19:7] wire [1:0] io_lsu_dis_uops_0_bits_mem_size = 2'h3; // @[tracegen.scala:19:7] wire [1:0] io_lsu_commit_uops_0_mem_size_0 = 2'h3; // @[tracegen.scala:19:7] wire [1:0] io_tracegen_req_bits_size = 2'h3; // @[tracegen.scala:19:7] wire [1:0] io_tracegen_req_bits_dprv = 2'h3; // @[tracegen.scala:19:7] wire [1:0] tracegen_uop_mem_size = 2'h3; // @[tracegen.scala:55:30] wire [7:0] io_tracegen_req_bits_mask = 8'hFF; // @[tracegen.scala:19:7] wire [7:0] io_tracegen_s1_data_mask = 8'hFF; // @[tracegen.scala:19:7] wire [32:0] io_lsu_sfence_bits_addr = 33'h0; // @[tracegen.scala:19:7] wire [20:0] io_lsu_brupdate_b2_target_offset = 21'h0; // @[tracegen.scala:19:7] wire [22:0] io_lsu_status_zero2 = 23'h0; // @[tracegen.scala:19:7] wire [7:0] io_lsu_status_zero1 = 8'h0; // @[tracegen.scala:19:7] wire [7:0] io_tracegen_resp_bits_mask = 8'h0; // @[tracegen.scala:19:7] wire io_tracegen_keep_clock_enabled = 1'h1; // @[tracegen.scala:19:7] wire _rob_respd_T_1 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_2 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_3 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_4 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_5 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_6 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_7 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_8 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_9 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_10 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_11 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_12 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_13 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_14 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_15 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_16 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_17 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_18 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_19 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_20 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_21 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_22 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_23 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_24 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_25 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_26 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_27 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_28 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_29 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_30 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_31 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_T_32 = 1'h1; // @[tracegen.scala:31:54] wire _rob_respd_WIRE_0 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_1 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_2 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_3 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_4 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_5 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_6 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_7 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_8 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_9 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_10 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_11 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_12 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_13 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_14 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_15 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_16 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_17 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_18 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_19 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_20 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_21 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_22 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_23 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_24 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_25 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_26 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_27 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_28 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_29 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_30 = 1'h1; // @[tracegen.scala:31:34] wire _rob_respd_WIRE_31 = 1'h1; // @[tracegen.scala:31:34] wire [31:0] _rob_respd_T = 32'hFFFFFFFF; // @[tracegen.scala:31:36] wire [1:0] io_tracegen_resp_bits_size_0 = io_lsu_iresp_0_bits_uop_mem_size_0; // @[tracegen.scala:19:7] wire [63:0] io_tracegen_resp_bits_data_0 = io_lsu_iresp_0_bits_data_0; // @[tracegen.scala:19:7] wire _io_lsu_dis_uops_0_valid_T; // @[Decoupled.scala:51:35] wire [31:0] tracegen_uop_debug_inst; // @[tracegen.scala:55:30] wire tracegen_uop_is_amo; // @[tracegen.scala:55:30] wire [4:0] tracegen_uop_rob_idx; // @[tracegen.scala:55:30] wire [3:0] tracegen_uop_ldq_idx; // @[tracegen.scala:55:30] wire [3:0] tracegen_uop_stq_idx; // @[tracegen.scala:55:30] wire [4:0] tracegen_uop_mem_cmd; // @[tracegen.scala:55:30] wire tracegen_uop_uses_ldq; // @[tracegen.scala:55:30] wire tracegen_uop_uses_stq; // @[tracegen.scala:55:30] assign tracegen_uop_ldq_idx = io_lsu_dis_ldq_idx_0_0; // @[tracegen.scala:19:7, :55:30] assign tracegen_uop_stq_idx = io_lsu_dis_stq_idx_0_0; // @[tracegen.scala:19:7, :55:30] wire _io_lsu_commit_valids_0_T_3; // @[tracegen.scala:92:75] wire _io_tracegen_req_ready_T_86; // @[tracegen.scala:51:63] assign tracegen_uop_mem_cmd = io_tracegen_req_bits_cmd_0; // @[tracegen.scala:19:7, :55:30] wire _io_tracegen_ordered_T; // @[tracegen.scala:162:40] wire [31:0] io_lsu_agen_0_bits_uop_debug_inst_0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_is_amo_0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_agen_0_bits_uop_rob_idx_0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_agen_0_bits_uop_ldq_idx_0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_agen_0_bits_uop_stq_idx_0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_agen_0_bits_uop_mem_cmd_0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_uses_ldq_0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_bits_uop_uses_stq_0; // @[tracegen.scala:19:7] wire [63:0] io_lsu_agen_0_bits_data_0; // @[tracegen.scala:19:7] wire io_lsu_agen_0_valid_0; // @[tracegen.scala:19:7] wire [31:0] io_lsu_dgen_0_bits_uop_debug_inst_0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_is_amo_0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dgen_0_bits_uop_rob_idx_0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_0_bits_uop_ldq_idx_0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dgen_0_bits_uop_stq_idx_0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dgen_0_bits_uop_mem_cmd_0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_uses_ldq_0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_bits_uop_uses_stq_0; // @[tracegen.scala:19:7] wire [63:0] io_lsu_dgen_0_bits_data_0; // @[tracegen.scala:19:7] wire io_lsu_dgen_0_valid_0; // @[tracegen.scala:19:7] wire [31:0] io_lsu_dis_uops_0_bits_debug_inst_0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_is_amo_0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dis_uops_0_bits_rob_idx_0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dis_uops_0_bits_ldq_idx_0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_dis_uops_0_bits_stq_idx_0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_dis_uops_0_bits_mem_cmd_0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_uses_ldq_0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_bits_uses_stq_0; // @[tracegen.scala:19:7] wire io_lsu_dis_uops_0_valid_0; // @[tracegen.scala:19:7] wire io_lsu_commit_valids_0_0; // @[tracegen.scala:19:7] wire [31:0] io_lsu_commit_uops_0_debug_inst_0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_is_amo_0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_commit_uops_0_rob_idx_0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_commit_uops_0_ldq_idx_0; // @[tracegen.scala:19:7] wire [3:0] io_lsu_commit_uops_0_stq_idx_0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_commit_uops_0_mem_cmd_0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_uses_ldq_0; // @[tracegen.scala:19:7] wire io_lsu_commit_uops_0_uses_stq_0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_rob_pnr_idx_0; // @[tracegen.scala:19:7] wire [4:0] io_lsu_rob_head_idx_0; // @[tracegen.scala:19:7] wire io_tracegen_req_ready_0; // @[tracegen.scala:19:7] wire [5:0] io_tracegen_resp_bits_tag_0; // @[tracegen.scala:19:7] wire io_tracegen_resp_valid_0; // @[tracegen.scala:19:7] wire io_tracegen_ordered_0; // @[tracegen.scala:19:7] reg [33:0] rob_0_addr; // @[tracegen.scala:30:16] reg [5:0] rob_0_tag; // @[tracegen.scala:30:16] reg [4:0] rob_0_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_0_data; // @[tracegen.scala:30:16] reg [33:0] rob_1_addr; // @[tracegen.scala:30:16] reg [5:0] rob_1_tag; // @[tracegen.scala:30:16] reg [4:0] rob_1_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_1_data; // @[tracegen.scala:30:16] reg [33:0] rob_2_addr; // @[tracegen.scala:30:16] reg [5:0] rob_2_tag; // @[tracegen.scala:30:16] reg [4:0] rob_2_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_2_data; // @[tracegen.scala:30:16] reg [33:0] rob_3_addr; // @[tracegen.scala:30:16] reg [5:0] rob_3_tag; // @[tracegen.scala:30:16] reg [4:0] rob_3_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_3_data; // @[tracegen.scala:30:16] reg [33:0] rob_4_addr; // @[tracegen.scala:30:16] reg [5:0] rob_4_tag; // @[tracegen.scala:30:16] reg [4:0] rob_4_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_4_data; // @[tracegen.scala:30:16] reg [33:0] rob_5_addr; // @[tracegen.scala:30:16] reg [5:0] rob_5_tag; // @[tracegen.scala:30:16] reg [4:0] rob_5_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_5_data; // @[tracegen.scala:30:16] reg [33:0] rob_6_addr; // @[tracegen.scala:30:16] reg [5:0] rob_6_tag; // @[tracegen.scala:30:16] reg [4:0] rob_6_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_6_data; // @[tracegen.scala:30:16] reg [33:0] rob_7_addr; // @[tracegen.scala:30:16] reg [5:0] rob_7_tag; // @[tracegen.scala:30:16] reg [4:0] rob_7_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_7_data; // @[tracegen.scala:30:16] reg [33:0] rob_8_addr; // @[tracegen.scala:30:16] reg [5:0] rob_8_tag; // @[tracegen.scala:30:16] reg [4:0] rob_8_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_8_data; // @[tracegen.scala:30:16] reg [33:0] rob_9_addr; // @[tracegen.scala:30:16] reg [5:0] rob_9_tag; // @[tracegen.scala:30:16] reg [4:0] rob_9_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_9_data; // @[tracegen.scala:30:16] reg [33:0] rob_10_addr; // @[tracegen.scala:30:16] reg [5:0] rob_10_tag; // @[tracegen.scala:30:16] reg [4:0] rob_10_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_10_data; // @[tracegen.scala:30:16] reg [33:0] rob_11_addr; // @[tracegen.scala:30:16] reg [5:0] rob_11_tag; // @[tracegen.scala:30:16] reg [4:0] rob_11_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_11_data; // @[tracegen.scala:30:16] reg [33:0] rob_12_addr; // @[tracegen.scala:30:16] reg [5:0] rob_12_tag; // @[tracegen.scala:30:16] reg [4:0] rob_12_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_12_data; // @[tracegen.scala:30:16] reg [33:0] rob_13_addr; // @[tracegen.scala:30:16] reg [5:0] rob_13_tag; // @[tracegen.scala:30:16] reg [4:0] rob_13_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_13_data; // @[tracegen.scala:30:16] reg [33:0] rob_14_addr; // @[tracegen.scala:30:16] reg [5:0] rob_14_tag; // @[tracegen.scala:30:16] reg [4:0] rob_14_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_14_data; // @[tracegen.scala:30:16] reg [33:0] rob_15_addr; // @[tracegen.scala:30:16] reg [5:0] rob_15_tag; // @[tracegen.scala:30:16] reg [4:0] rob_15_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_15_data; // @[tracegen.scala:30:16] reg [33:0] rob_16_addr; // @[tracegen.scala:30:16] reg [5:0] rob_16_tag; // @[tracegen.scala:30:16] reg [4:0] rob_16_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_16_data; // @[tracegen.scala:30:16] reg [33:0] rob_17_addr; // @[tracegen.scala:30:16] reg [5:0] rob_17_tag; // @[tracegen.scala:30:16] reg [4:0] rob_17_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_17_data; // @[tracegen.scala:30:16] reg [33:0] rob_18_addr; // @[tracegen.scala:30:16] reg [5:0] rob_18_tag; // @[tracegen.scala:30:16] reg [4:0] rob_18_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_18_data; // @[tracegen.scala:30:16] reg [33:0] rob_19_addr; // @[tracegen.scala:30:16] reg [5:0] rob_19_tag; // @[tracegen.scala:30:16] reg [4:0] rob_19_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_19_data; // @[tracegen.scala:30:16] reg [33:0] rob_20_addr; // @[tracegen.scala:30:16] reg [5:0] rob_20_tag; // @[tracegen.scala:30:16] reg [4:0] rob_20_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_20_data; // @[tracegen.scala:30:16] reg [33:0] rob_21_addr; // @[tracegen.scala:30:16] reg [5:0] rob_21_tag; // @[tracegen.scala:30:16] reg [4:0] rob_21_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_21_data; // @[tracegen.scala:30:16] reg [33:0] rob_22_addr; // @[tracegen.scala:30:16] reg [5:0] rob_22_tag; // @[tracegen.scala:30:16] reg [4:0] rob_22_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_22_data; // @[tracegen.scala:30:16] reg [33:0] rob_23_addr; // @[tracegen.scala:30:16] reg [5:0] rob_23_tag; // @[tracegen.scala:30:16] reg [4:0] rob_23_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_23_data; // @[tracegen.scala:30:16] reg [33:0] rob_24_addr; // @[tracegen.scala:30:16] reg [5:0] rob_24_tag; // @[tracegen.scala:30:16] reg [4:0] rob_24_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_24_data; // @[tracegen.scala:30:16] reg [33:0] rob_25_addr; // @[tracegen.scala:30:16] reg [5:0] rob_25_tag; // @[tracegen.scala:30:16] reg [4:0] rob_25_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_25_data; // @[tracegen.scala:30:16] reg [33:0] rob_26_addr; // @[tracegen.scala:30:16] reg [5:0] rob_26_tag; // @[tracegen.scala:30:16] reg [4:0] rob_26_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_26_data; // @[tracegen.scala:30:16] reg [33:0] rob_27_addr; // @[tracegen.scala:30:16] reg [5:0] rob_27_tag; // @[tracegen.scala:30:16] reg [4:0] rob_27_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_27_data; // @[tracegen.scala:30:16] reg [33:0] rob_28_addr; // @[tracegen.scala:30:16] reg [5:0] rob_28_tag; // @[tracegen.scala:30:16] reg [4:0] rob_28_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_28_data; // @[tracegen.scala:30:16] reg [33:0] rob_29_addr; // @[tracegen.scala:30:16] reg [5:0] rob_29_tag; // @[tracegen.scala:30:16] reg [4:0] rob_29_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_29_data; // @[tracegen.scala:30:16] reg [33:0] rob_30_addr; // @[tracegen.scala:30:16] reg [5:0] rob_30_tag; // @[tracegen.scala:30:16] reg [4:0] rob_30_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_30_data; // @[tracegen.scala:30:16] reg [33:0] rob_31_addr; // @[tracegen.scala:30:16] reg [5:0] rob_31_tag; // @[tracegen.scala:30:16] reg [4:0] rob_31_cmd; // @[tracegen.scala:30:16] reg [63:0] rob_31_data; // @[tracegen.scala:30:16] reg rob_respd_0; // @[tracegen.scala:31:26] reg rob_respd_1; // @[tracegen.scala:31:26] reg rob_respd_2; // @[tracegen.scala:31:26] reg rob_respd_3; // @[tracegen.scala:31:26] reg rob_respd_4; // @[tracegen.scala:31:26] reg rob_respd_5; // @[tracegen.scala:31:26] reg rob_respd_6; // @[tracegen.scala:31:26] reg rob_respd_7; // @[tracegen.scala:31:26] reg rob_respd_8; // @[tracegen.scala:31:26] reg rob_respd_9; // @[tracegen.scala:31:26] reg rob_respd_10; // @[tracegen.scala:31:26] reg rob_respd_11; // @[tracegen.scala:31:26] reg rob_respd_12; // @[tracegen.scala:31:26] reg rob_respd_13; // @[tracegen.scala:31:26] reg rob_respd_14; // @[tracegen.scala:31:26] reg rob_respd_15; // @[tracegen.scala:31:26] reg rob_respd_16; // @[tracegen.scala:31:26] reg rob_respd_17; // @[tracegen.scala:31:26] reg rob_respd_18; // @[tracegen.scala:31:26] reg rob_respd_19; // @[tracegen.scala:31:26] reg rob_respd_20; // @[tracegen.scala:31:26] reg rob_respd_21; // @[tracegen.scala:31:26] reg rob_respd_22; // @[tracegen.scala:31:26] reg rob_respd_23; // @[tracegen.scala:31:26] reg rob_respd_24; // @[tracegen.scala:31:26] reg rob_respd_25; // @[tracegen.scala:31:26] reg rob_respd_26; // @[tracegen.scala:31:26] reg rob_respd_27; // @[tracegen.scala:31:26] reg rob_respd_28; // @[tracegen.scala:31:26] reg rob_respd_29; // @[tracegen.scala:31:26] reg rob_respd_30; // @[tracegen.scala:31:26] reg rob_respd_31; // @[tracegen.scala:31:26] reg [31:0] rob_uop_0_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_0_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_0_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_0_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_0_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_0_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_0_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_0_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_1_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_1_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_1_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_1_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_1_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_1_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_1_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_1_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_2_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_2_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_2_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_2_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_2_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_2_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_2_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_2_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_3_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_3_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_3_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_3_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_3_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_3_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_3_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_3_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_4_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_4_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_4_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_4_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_4_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_4_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_4_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_4_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_5_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_5_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_5_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_5_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_5_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_5_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_5_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_5_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_6_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_6_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_6_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_6_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_6_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_6_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_6_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_6_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_7_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_7_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_7_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_7_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_7_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_7_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_7_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_7_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_8_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_8_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_8_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_8_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_8_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_8_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_8_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_8_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_9_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_9_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_9_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_9_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_9_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_9_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_9_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_9_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_10_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_10_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_10_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_10_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_10_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_10_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_10_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_10_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_11_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_11_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_11_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_11_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_11_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_11_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_11_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_11_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_12_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_12_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_12_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_12_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_12_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_12_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_12_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_12_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_13_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_13_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_13_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_13_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_13_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_13_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_13_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_13_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_14_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_14_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_14_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_14_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_14_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_14_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_14_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_14_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_15_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_15_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_15_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_15_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_15_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_15_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_15_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_15_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_16_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_16_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_16_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_16_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_16_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_16_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_16_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_16_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_17_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_17_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_17_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_17_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_17_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_17_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_17_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_17_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_18_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_18_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_18_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_18_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_18_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_18_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_18_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_18_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_19_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_19_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_19_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_19_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_19_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_19_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_19_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_19_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_20_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_20_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_20_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_20_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_20_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_20_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_20_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_20_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_21_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_21_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_21_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_21_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_21_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_21_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_21_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_21_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_22_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_22_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_22_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_22_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_22_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_22_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_22_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_22_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_23_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_23_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_23_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_23_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_23_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_23_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_23_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_23_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_24_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_24_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_24_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_24_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_24_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_24_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_24_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_24_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_25_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_25_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_25_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_25_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_25_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_25_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_25_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_25_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_26_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_26_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_26_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_26_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_26_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_26_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_26_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_26_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_27_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_27_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_27_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_27_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_27_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_27_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_27_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_27_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_28_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_28_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_28_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_28_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_28_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_28_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_28_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_28_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_29_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_29_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_29_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_29_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_29_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_29_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_29_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_29_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_30_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_30_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_30_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_30_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_30_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_30_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_30_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_30_uses_stq; // @[tracegen.scala:32:20] reg [31:0] rob_uop_31_debug_inst; // @[tracegen.scala:32:20] reg rob_uop_31_is_amo; // @[tracegen.scala:32:20] reg [4:0] rob_uop_31_rob_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_31_ldq_idx; // @[tracegen.scala:32:20] reg [3:0] rob_uop_31_stq_idx; // @[tracegen.scala:32:20] reg [4:0] rob_uop_31_mem_cmd; // @[tracegen.scala:32:20] reg rob_uop_31_uses_ldq; // @[tracegen.scala:32:20] reg rob_uop_31_uses_stq; // @[tracegen.scala:32:20] reg rob_bsy_0; // @[tracegen.scala:33:25] reg rob_bsy_1; // @[tracegen.scala:33:25] reg rob_bsy_2; // @[tracegen.scala:33:25] reg rob_bsy_3; // @[tracegen.scala:33:25] reg rob_bsy_4; // @[tracegen.scala:33:25] reg rob_bsy_5; // @[tracegen.scala:33:25] reg rob_bsy_6; // @[tracegen.scala:33:25] reg rob_bsy_7; // @[tracegen.scala:33:25] reg rob_bsy_8; // @[tracegen.scala:33:25] reg rob_bsy_9; // @[tracegen.scala:33:25] reg rob_bsy_10; // @[tracegen.scala:33:25] reg rob_bsy_11; // @[tracegen.scala:33:25] reg rob_bsy_12; // @[tracegen.scala:33:25] reg rob_bsy_13; // @[tracegen.scala:33:25] reg rob_bsy_14; // @[tracegen.scala:33:25] reg rob_bsy_15; // @[tracegen.scala:33:25] reg rob_bsy_16; // @[tracegen.scala:33:25] reg rob_bsy_17; // @[tracegen.scala:33:25] reg rob_bsy_18; // @[tracegen.scala:33:25] reg rob_bsy_19; // @[tracegen.scala:33:25] reg rob_bsy_20; // @[tracegen.scala:33:25] reg rob_bsy_21; // @[tracegen.scala:33:25] reg rob_bsy_22; // @[tracegen.scala:33:25] reg rob_bsy_23; // @[tracegen.scala:33:25] reg rob_bsy_24; // @[tracegen.scala:33:25] reg rob_bsy_25; // @[tracegen.scala:33:25] reg rob_bsy_26; // @[tracegen.scala:33:25] reg rob_bsy_27; // @[tracegen.scala:33:25] reg rob_bsy_28; // @[tracegen.scala:33:25] reg rob_bsy_29; // @[tracegen.scala:33:25] reg rob_bsy_30; // @[tracegen.scala:33:25] reg rob_bsy_31; // @[tracegen.scala:33:25] reg [4:0] rob_head; // @[tracegen.scala:34:25] assign io_lsu_rob_head_idx_0 = rob_head; // @[tracegen.scala:19:7, :34:25] reg [4:0] rob_tail; // @[tracegen.scala:35:25] assign io_lsu_rob_pnr_idx_0 = rob_tail; // @[tracegen.scala:19:7, :35:25] assign tracegen_uop_rob_idx = rob_tail; // @[tracegen.scala:35:25, :55:30] reg rob_wait_till_empty; // @[tracegen.scala:36:36] wire _ready_for_amo_T = rob_tail == rob_head; // @[tracegen.scala:34:25, :35:25, :37:32] wire ready_for_amo = _ready_for_amo_T & io_lsu_fencei_rdy_0; // @[tracegen.scala:19:7, :37:{32,45}] wire [31:0] _GEN = {{rob_bsy_31}, {rob_bsy_30}, {rob_bsy_29}, {rob_bsy_28}, {rob_bsy_27}, {rob_bsy_26}, {rob_bsy_25}, {rob_bsy_24}, {rob_bsy_23}, {rob_bsy_22}, {rob_bsy_21}, {rob_bsy_20}, {rob_bsy_19}, {rob_bsy_18}, {rob_bsy_17}, {rob_bsy_16}, {rob_bsy_15}, {rob_bsy_14}, {rob_bsy_13}, {rob_bsy_12}, {rob_bsy_11}, {rob_bsy_10}, {rob_bsy_9}, {rob_bsy_8}, {rob_bsy_7}, {rob_bsy_6}, {rob_bsy_5}, {rob_bsy_4}, {rob_bsy_3}, {rob_bsy_2}, {rob_bsy_1}, {rob_bsy_0}}; // @[tracegen.scala:33:25, :47:29] wire _io_tracegen_req_ready_T = ~_GEN[rob_tail]; // @[tracegen.scala:35:25, :47:29] wire _io_tracegen_req_ready_T_1 = ~rob_wait_till_empty; // @[tracegen.scala:36:36, :48:5] wire _io_tracegen_req_ready_T_2 = _io_tracegen_req_ready_T & _io_tracegen_req_ready_T_1; // @[tracegen.scala:47:{29,48}, :48:5] wire _T_1 = io_tracegen_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_3; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_3 = _T_1; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_40; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_40 = _T_1; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_66; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_66 = _T_1; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_7; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_7 = _T_1; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_30; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_30 = _T_1; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_5; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_5 = _T_1; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T = _T_1; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_57; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_57 = _T_1; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_80; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_80 = _T_1; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_28; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_28 = _T_1; // @[package.scala:16:47] wire _T_2 = io_tracegen_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_4; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_4 = _T_2; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_41; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_41 = _T_2; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_67; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_67 = _T_2; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_8; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_8 = _T_2; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_31; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_31 = _T_2; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_6; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_6 = _T_2; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_1; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_1 = _T_2; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_58; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_58 = _T_2; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_81; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_81 = _T_2; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_29; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_29 = _T_2; // @[package.scala:16:47] wire _T_3 = io_tracegen_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_5; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_5 = _T_3; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_42; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_42 = _T_3; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_68; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_68 = _T_3; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_9; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_9 = _T_3; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_32; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_32 = _T_3; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_7; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_7 = _T_3; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_2; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_2 = _T_3; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_59; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_59 = _T_3; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_82; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_82 = _T_3; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_30; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_30 = _T_3; // @[package.scala:16:47] wire _T_4 = io_tracegen_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_6; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_6 = _T_4; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_43; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_43 = _T_4; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_69; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_69 = _T_4; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_10; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_10 = _T_4; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_33; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_33 = _T_4; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_8; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_8 = _T_4; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_3; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_3 = _T_4; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_60; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_60 = _T_4; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_83; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_83 = _T_4; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_31; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_31 = _T_4; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_7 = _io_tracegen_req_ready_T_3 \| _io_tracegen_req_ready_T_4; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_8 = _io_tracegen_req_ready_T_7 \| _io_tracegen_req_ready_T_5; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_9 = _io_tracegen_req_ready_T_8 \| _io_tracegen_req_ready_T_6; // @[package.scala:16:47, :81:59] wire _T_8 = io_tracegen_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_10; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_10 = _T_8; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_47; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_47 = _T_8; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_73; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_73 = _T_8; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_14; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_14 = _T_8; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_37; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_37 = _T_8; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_12; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_12 = _T_8; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_7; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_7 = _T_8; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_64; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_64 = _T_8; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_87; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_87 = _T_8; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_35; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_35 = _T_8; // @[package.scala:16:47] wire _T_9 = io_tracegen_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_11; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_11 = _T_9; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_48; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_48 = _T_9; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_74; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_74 = _T_9; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_15; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_15 = _T_9; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_38; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_38 = _T_9; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_13; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_13 = _T_9; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_8; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_8 = _T_9; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_65; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_65 = _T_9; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_88; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_88 = _T_9; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_36; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_36 = _T_9; // @[package.scala:16:47] wire _T_10 = io_tracegen_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_12; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_12 = _T_10; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_49; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_49 = _T_10; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_75; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_75 = _T_10; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_16; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_16 = _T_10; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_39; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_39 = _T_10; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_14; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_14 = _T_10; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_9; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_9 = _T_10; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_66; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_66 = _T_10; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_89; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_89 = _T_10; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_37; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_37 = _T_10; // @[package.scala:16:47] wire _T_11 = io_tracegen_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_13; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_13 = _T_11; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_50; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_50 = _T_11; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_76; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_76 = _T_11; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_17; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_17 = _T_11; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_40; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_40 = _T_11; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_15; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_15 = _T_11; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_10; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_10 = _T_11; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_67; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_67 = _T_11; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_90; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_90 = _T_11; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_38; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_38 = _T_11; // @[package.scala:16:47] wire _T_12 = io_tracegen_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_14; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_14 = _T_12; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_51; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_51 = _T_12; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_77; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_77 = _T_12; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_18; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_18 = _T_12; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_41; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_41 = _T_12; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_16; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_16 = _T_12; // @[package.scala:16:47] wire _tracegen_uop_is_amo_T_11; // @[package.scala:16:47] assign _tracegen_uop_is_amo_T_11 = _T_12; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_68; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_68 = _T_12; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_91; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_91 = _T_12; // @[package.scala:16:47] wire _tracegen_uop_uses_stq_T_39; // @[package.scala:16:47] assign _tracegen_uop_uses_stq_T_39 = _T_12; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_15 = _io_tracegen_req_ready_T_10 \| _io_tracegen_req_ready_T_11; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_16 = _io_tracegen_req_ready_T_15 \| _io_tracegen_req_ready_T_12; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_17 = _io_tracegen_req_ready_T_16 \| _io_tracegen_req_ready_T_13; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_18 = _io_tracegen_req_ready_T_17 \| _io_tracegen_req_ready_T_14; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_19 = _io_tracegen_req_ready_T_9 \| _io_tracegen_req_ready_T_18; // @[package.scala:81:59] wire _T_18 = io_tracegen_req_bits_cmd_0 == 5'h6; // @[tracegen.scala:19:7, :49:85] wire _io_tracegen_req_ready_T_20; // @[tracegen.scala:49:85] assign _io_tracegen_req_ready_T_20 = _T_18; // @[tracegen.scala:49:85] wire _io_tracegen_req_ready_T_35; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_35 = _T_18; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_2; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_2 = _T_18; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_52; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_52 = _T_18; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_21 = _io_tracegen_req_ready_T_19 \| _io_tracegen_req_ready_T_20; // @[Consts.scala:87:44] wire _T_20 = io_tracegen_req_bits_cmd_0 == 5'h7; // @[tracegen.scala:19:7, :49:123] wire _io_tracegen_req_ready_T_22; // @[tracegen.scala:49:123] assign _io_tracegen_req_ready_T_22 = _T_20; // @[tracegen.scala:49:123] wire _io_tracegen_req_ready_T_36; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_36 = _T_20; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_64; // @[Consts.scala:90:66] assign _io_tracegen_req_ready_T_64 = _T_20; // @[Consts.scala:90:66] wire _tracegen_uop_uses_ldq_T_3; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_3 = _T_20; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_28; // @[Consts.scala:90:66] assign _tracegen_uop_uses_ldq_T_28 = _T_20; // @[Consts.scala:90:66] wire _tracegen_uop_uses_stq_T_3; // @[Consts.scala:90:66] assign _tracegen_uop_uses_stq_T_3 = _T_20; // @[Consts.scala:90:66] wire _tracegen_uop_is_amo_T_17; // @[tracegen.scala:65:92] assign _tracegen_uop_is_amo_T_17 = _T_20; // @[tracegen.scala:49:123, :65:92] wire _tracegen_uop_uses_ldq_T_53; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_53 = _T_20; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_78; // @[Consts.scala:90:66] assign _tracegen_uop_uses_ldq_T_78 = _T_20; // @[Consts.scala:90:66] wire _tracegen_uop_uses_stq_T_26; // @[Consts.scala:90:66] assign _tracegen_uop_uses_stq_T_26 = _T_20; // @[Consts.scala:90:66] wire _io_tracegen_req_ready_T_23 = _io_tracegen_req_ready_T_21 \| _io_tracegen_req_ready_T_22; // @[tracegen.scala:49:{57,95,123}] wire _io_tracegen_req_ready_T_24 = ~_io_tracegen_req_ready_T_23; // @[tracegen.scala:49:{23,95}] wire _io_tracegen_req_ready_T_25 = ready_for_amo \| _io_tracegen_req_ready_T_24; // @[tracegen.scala:37:45, :49:{20,23}] wire _io_tracegen_req_ready_T_26 = _io_tracegen_req_ready_T_2 & _io_tracegen_req_ready_T_25; // @[tracegen.scala:47:48, :48:26, :49:20] wire _io_tracegen_req_ready_T_27 = &rob_tail; // @[tracegen.scala:35:25, :43:13] wire [5:0] _GEN_0 = {1'h0, rob_tail} + 6'h1; // @[tracegen.scala:35:25, :43:37] wire [5:0] _io_tracegen_req_ready_T_28; // @[tracegen.scala:43:37] assign _io_tracegen_req_ready_T_28 = _GEN_0; // @[tracegen.scala:43:37] wire [5:0] _rob_tail_T_1; // @[tracegen.scala:43:37] assign _rob_tail_T_1 = _GEN_0; // @[tracegen.scala:43:37] wire [4:0] _io_tracegen_req_ready_T_29 = _io_tracegen_req_ready_T_28[4:0]; // @[tracegen.scala:43:37] wire [4:0] _io_tracegen_req_ready_T_30 = _io_tracegen_req_ready_T_27 ? 5'h0 : _io_tracegen_req_ready_T_29; // @[tracegen.scala:43:{8,13,37}] wire _io_tracegen_req_ready_T_31 = _io_tracegen_req_ready_T_30 != rob_head; // @[tracegen.scala:34:25, :43:8, :50:32] wire _io_tracegen_req_ready_T_32 = _io_tracegen_req_ready_T_26 & _io_tracegen_req_ready_T_31; // @[tracegen.scala:48:26, :49:135, :50:32] wire _GEN_1 = io_tracegen_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_33; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_33 = _GEN_1; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T = _GEN_1; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_50; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_50 = _GEN_1; // @[package.scala:16:47] wire _GEN_2 = io_tracegen_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_34; // @[package.scala:16:47] assign _io_tracegen_req_ready_T_34 = _GEN_2; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_1; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_1 = _GEN_2; // @[package.scala:16:47] wire _tracegen_uop_uses_ldq_T_51; // @[package.scala:16:47] assign _tracegen_uop_uses_ldq_T_51 = _GEN_2; // @[package.scala:16:47] wire _io_tracegen_req_ready_T_37 = _io_tracegen_req_ready_T_33 \| _io_tracegen_req_ready_T_34; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_38 = _io_tracegen_req_ready_T_37 \| _io_tracegen_req_ready_T_35; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_39 = _io_tracegen_req_ready_T_38 \| _io_tracegen_req_ready_T_36; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_44 = _io_tracegen_req_ready_T_40 \| _io_tracegen_req_ready_T_41; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_45 = _io_tracegen_req_ready_T_44 \| _io_tracegen_req_ready_T_42; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_46 = _io_tracegen_req_ready_T_45 \| _io_tracegen_req_ready_T_43; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_52 = _io_tracegen_req_ready_T_47 \| _io_tracegen_req_ready_T_48; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_53 = _io_tracegen_req_ready_T_52 \| _io_tracegen_req_ready_T_49; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_54 = _io_tracegen_req_ready_T_53 \| _io_tracegen_req_ready_T_50; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_55 = _io_tracegen_req_ready_T_54 \| _io_tracegen_req_ready_T_51; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_56 = _io_tracegen_req_ready_T_46 \| _io_tracegen_req_ready_T_55; // @[package.scala:81:59] wire _io_tracegen_req_ready_T_57 = _io_tracegen_req_ready_T_39 \| _io_tracegen_req_ready_T_56; // @[package.scala:81:59] wire _io_tracegen_req_ready_T_58 = io_lsu_ldq_full_0_0 & _io_tracegen_req_ready_T_57; // @[Consts.scala:89:68] wire _io_tracegen_req_ready_T_59 = ~_io_tracegen_req_ready_T_58; // @[tracegen.scala:51:{5,26}] wire _io_tracegen_req_ready_T_60 = _io_tracegen_req_ready_T_32 & _io_tracegen_req_ready_T_59; // @[tracegen.scala:49:135, :50:46, :51:5] wire _GEN_3 = io_tracegen_req_bits_cmd_0 == 5'h1; // @[Consts.scala:90:32] wire _io_tracegen_req_ready_T_61; // @[Consts.scala:90:32] assign _io_tracegen_req_ready_T_61 = _GEN_3; // @[Consts.scala:90:32] wire _tracegen_uop_uses_ldq_T_25; // @[Consts.scala:90:32] assign _tracegen_uop_uses_ldq_T_25 = _GEN_3; // @[Consts.scala:90:32] wire _tracegen_uop_uses_stq_T; // @[Consts.scala:90:32] assign _tracegen_uop_uses_stq_T = _GEN_3; // @[Consts.scala:90:32] wire _tracegen_uop_uses_ldq_T_75; // @[Consts.scala:90:32] assign _tracegen_uop_uses_ldq_T_75 = _GEN_3; // @[Consts.scala:90:32] wire _tracegen_uop_uses_stq_T_23; // @[Consts.scala:90:32] assign _tracegen_uop_uses_stq_T_23 = _GEN_3; // @[Consts.scala:90:32] wire _GEN_4 = io_tracegen_req_bits_cmd_0 == 5'h11; // @[Consts.scala:90:49] wire _io_tracegen_req_ready_T_62; // @[Consts.scala:90:49] assign _io_tracegen_req_ready_T_62 = _GEN_4; // @[Consts.scala:90:49] wire _tracegen_uop_uses_ldq_T_26; // @[Consts.scala:90:49] assign _tracegen_uop_uses_ldq_T_26 = _GEN_4; // @[Consts.scala:90:49] wire _tracegen_uop_uses_stq_T_1; // @[Consts.scala:90:49] assign _tracegen_uop_uses_stq_T_1 = _GEN_4; // @[Consts.scala:90:49] wire _tracegen_uop_uses_ldq_T_76; // @[Consts.scala:90:49] assign _tracegen_uop_uses_ldq_T_76 = _GEN_4; // @[Consts.scala:90:49] wire _tracegen_uop_uses_stq_T_24; // @[Consts.scala:90:49] assign _tracegen_uop_uses_stq_T_24 = _GEN_4; // @[Consts.scala:90:49] wire _io_tracegen_req_ready_T_63 = _io_tracegen_req_ready_T_61 \| _io_tracegen_req_ready_T_62; // @[Consts.scala:90:{32,42,49}] wire _io_tracegen_req_ready_T_65 = _io_tracegen_req_ready_T_63 \| _io_tracegen_req_ready_T_64; // @[Consts.scala:90:{42,59,66}] wire _io_tracegen_req_ready_T_70 = _io_tracegen_req_ready_T_66 \| _io_tracegen_req_ready_T_67; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_71 = _io_tracegen_req_ready_T_70 \| _io_tracegen_req_ready_T_68; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_72 = _io_tracegen_req_ready_T_71 \| _io_tracegen_req_ready_T_69; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_78 = _io_tracegen_req_ready_T_73 \| _io_tracegen_req_ready_T_74; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_79 = _io_tracegen_req_ready_T_78 \| _io_tracegen_req_ready_T_75; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_80 = _io_tracegen_req_ready_T_79 \| _io_tracegen_req_ready_T_76; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_81 = _io_tracegen_req_ready_T_80 \| _io_tracegen_req_ready_T_77; // @[package.scala:16:47, :81:59] wire _io_tracegen_req_ready_T_82 = _io_tracegen_req_ready_T_72 \| _io_tracegen_req_ready_T_81; // @[package.scala:81:59] wire _io_tracegen_req_ready_T_83 = _io_tracegen_req_ready_T_65 \| _io_tracegen_req_ready_T_82; // @[Consts.scala:87:44, :90:{59,76}] wire _io_tracegen_req_ready_T_84 = io_lsu_stq_full_0_0 & _io_tracegen_req_ready_T_83; // @[Consts.scala:90:76] wire _io_tracegen_req_ready_T_85 = ~_io_tracegen_req_ready_T_84; // @[tracegen.scala:52:{5,26}] assign _io_tracegen_req_ready_T_86 = _io_tracegen_req_ready_T_60 & _io_tracegen_req_ready_T_85; // @[tracegen.scala:50:46, :51:63, :52:5] assign io_tracegen_req_ready_0 = _io_tracegen_req_ready_T_86; // @[tracegen.scala:19:7, :51:63] assign io_lsu_dis_uops_0_bits_debug_inst_0 = tracegen_uop_debug_inst; // @[tracegen.scala:19:7, :55:30] wire _tracegen_uop_is_amo_T_18; // @[tracegen.scala:65:64] assign io_lsu_dis_uops_0_bits_is_amo_0 = tracegen_uop_is_amo; // @[tracegen.scala:19:7, :55:30] assign io_lsu_dis_uops_0_bits_rob_idx_0 = tracegen_uop_rob_idx; // @[tracegen.scala:19:7, :55:30] assign io_lsu_dis_uops_0_bits_ldq_idx_0 = tracegen_uop_ldq_idx; // @[tracegen.scala:19:7, :55:30] assign io_lsu_dis_uops_0_bits_stq_idx_0 = tracegen_uop_stq_idx; // @[tracegen.scala:19:7, :55:30] assign io_lsu_dis_uops_0_bits_mem_cmd_0 = tracegen_uop_mem_cmd; // @[tracegen.scala:19:7, :55:30] wire _tracegen_uop_uses_ldq_T_99; // @[tracegen.scala:66:65] assign io_lsu_dis_uops_0_bits_uses_ldq_0 = tracegen_uop_uses_ldq; // @[tracegen.scala:19:7, :55:30] wire _tracegen_uop_uses_stq_T_45; // @[Consts.scala:90:76] assign io_lsu_dis_uops_0_bits_uses_stq_0 = tracegen_uop_uses_stq; // @[tracegen.scala:19:7, :55:30] wire _tracegen_uop_uses_ldq_T_4 = _tracegen_uop_uses_ldq_T \| _tracegen_uop_uses_ldq_T_1; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_5 = _tracegen_uop_uses_ldq_T_4 \| _tracegen_uop_uses_ldq_T_2; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_6 = _tracegen_uop_uses_ldq_T_5 \| _tracegen_uop_uses_ldq_T_3; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_11 = _tracegen_uop_uses_ldq_T_7 \| _tracegen_uop_uses_ldq_T_8; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_12 = _tracegen_uop_uses_ldq_T_11 \| _tracegen_uop_uses_ldq_T_9; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_13 = _tracegen_uop_uses_ldq_T_12 \| _tracegen_uop_uses_ldq_T_10; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_19 = _tracegen_uop_uses_ldq_T_14 \| _tracegen_uop_uses_ldq_T_15; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_20 = _tracegen_uop_uses_ldq_T_19 \| _tracegen_uop_uses_ldq_T_16; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_21 = _tracegen_uop_uses_ldq_T_20 \| _tracegen_uop_uses_ldq_T_17; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_22 = _tracegen_uop_uses_ldq_T_21 \| _tracegen_uop_uses_ldq_T_18; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_23 = _tracegen_uop_uses_ldq_T_13 \| _tracegen_uop_uses_ldq_T_22; // @[package.scala:81:59] wire _tracegen_uop_uses_ldq_T_24 = _tracegen_uop_uses_ldq_T_6 \| _tracegen_uop_uses_ldq_T_23; // @[package.scala:81:59] wire _tracegen_uop_uses_ldq_T_27 = _tracegen_uop_uses_ldq_T_25 \| _tracegen_uop_uses_ldq_T_26; // @[Consts.scala:90:{32,42,49}] wire _tracegen_uop_uses_ldq_T_29 = _tracegen_uop_uses_ldq_T_27 \| _tracegen_uop_uses_ldq_T_28; // @[Consts.scala:90:{42,59,66}] wire _tracegen_uop_uses_ldq_T_34 = _tracegen_uop_uses_ldq_T_30 \| _tracegen_uop_uses_ldq_T_31; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_35 = _tracegen_uop_uses_ldq_T_34 \| _tracegen_uop_uses_ldq_T_32; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_36 = _tracegen_uop_uses_ldq_T_35 \| _tracegen_uop_uses_ldq_T_33; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_42 = _tracegen_uop_uses_ldq_T_37 \| _tracegen_uop_uses_ldq_T_38; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_43 = _tracegen_uop_uses_ldq_T_42 \| _tracegen_uop_uses_ldq_T_39; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_44 = _tracegen_uop_uses_ldq_T_43 \| _tracegen_uop_uses_ldq_T_40; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_45 = _tracegen_uop_uses_ldq_T_44 \| _tracegen_uop_uses_ldq_T_41; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_46 = _tracegen_uop_uses_ldq_T_36 \| _tracegen_uop_uses_ldq_T_45; // @[package.scala:81:59] wire _tracegen_uop_uses_ldq_T_47 = _tracegen_uop_uses_ldq_T_29 \| _tracegen_uop_uses_ldq_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _tracegen_uop_uses_ldq_T_48 = ~_tracegen_uop_uses_ldq_T_47; // @[Consts.scala:90:76] wire _tracegen_uop_uses_ldq_T_49 = _tracegen_uop_uses_ldq_T_24 & _tracegen_uop_uses_ldq_T_48; // @[Consts.scala:89:68] wire _tracegen_uop_uses_stq_T_2 = _tracegen_uop_uses_stq_T \| _tracegen_uop_uses_stq_T_1; // @[Consts.scala:90:{32,42,49}] wire _tracegen_uop_uses_stq_T_4 = _tracegen_uop_uses_stq_T_2 \| _tracegen_uop_uses_stq_T_3; // @[Consts.scala:90:{42,59,66}] wire _tracegen_uop_uses_stq_T_9 = _tracegen_uop_uses_stq_T_5 \| _tracegen_uop_uses_stq_T_6; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_10 = _tracegen_uop_uses_stq_T_9 \| _tracegen_uop_uses_stq_T_7; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_11 = _tracegen_uop_uses_stq_T_10 \| _tracegen_uop_uses_stq_T_8; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_17 = _tracegen_uop_uses_stq_T_12 \| _tracegen_uop_uses_stq_T_13; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_18 = _tracegen_uop_uses_stq_T_17 \| _tracegen_uop_uses_stq_T_14; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_19 = _tracegen_uop_uses_stq_T_18 \| _tracegen_uop_uses_stq_T_15; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_20 = _tracegen_uop_uses_stq_T_19 \| _tracegen_uop_uses_stq_T_16; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_21 = _tracegen_uop_uses_stq_T_11 \| _tracegen_uop_uses_stq_T_20; // @[package.scala:81:59] wire _tracegen_uop_uses_stq_T_22 = _tracegen_uop_uses_stq_T_4 \| _tracegen_uop_uses_stq_T_21; // @[Consts.scala:87:44, :90:{59,76}] assign tracegen_uop_debug_inst = {26'h0, io_tracegen_req_bits_tag_0}; // @[tracegen.scala:19:7, :55:30, :59:29] wire _tracegen_uop_is_amo_T_4 = _tracegen_uop_is_amo_T \| _tracegen_uop_is_amo_T_1; // @[package.scala:16:47, :81:59] wire _tracegen_uop_is_amo_T_5 = _tracegen_uop_is_amo_T_4 \| _tracegen_uop_is_amo_T_2; // @[package.scala:16:47, :81:59] wire _tracegen_uop_is_amo_T_6 = _tracegen_uop_is_amo_T_5 \| _tracegen_uop_is_amo_T_3; // @[package.scala:16:47, :81:59] wire _tracegen_uop_is_amo_T_12 = _tracegen_uop_is_amo_T_7 \| _tracegen_uop_is_amo_T_8; // @[package.scala:16:47, :81:59] wire _tracegen_uop_is_amo_T_13 = _tracegen_uop_is_amo_T_12 \| _tracegen_uop_is_amo_T_9; // @[package.scala:16:47, :81:59] wire _tracegen_uop_is_amo_T_14 = _tracegen_uop_is_amo_T_13 \| _tracegen_uop_is_amo_T_10; // @[package.scala:16:47, :81:59] wire _tracegen_uop_is_amo_T_15 = _tracegen_uop_is_amo_T_14 \| _tracegen_uop_is_amo_T_11; // @[package.scala:16:47, :81:59] wire _tracegen_uop_is_amo_T_16 = _tracegen_uop_is_amo_T_6 \| _tracegen_uop_is_amo_T_15; // @[package.scala:81:59] assign _tracegen_uop_is_amo_T_18 = _tracegen_uop_is_amo_T_16 \| _tracegen_uop_is_amo_T_17; // @[Consts.scala:87:44] assign tracegen_uop_is_amo = _tracegen_uop_is_amo_T_18; // @[tracegen.scala:55:30, :65:64] wire _tracegen_uop_uses_ldq_T_54 = _tracegen_uop_uses_ldq_T_50 \| _tracegen_uop_uses_ldq_T_51; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_55 = _tracegen_uop_uses_ldq_T_54 \| _tracegen_uop_uses_ldq_T_52; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_56 = _tracegen_uop_uses_ldq_T_55 \| _tracegen_uop_uses_ldq_T_53; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_61 = _tracegen_uop_uses_ldq_T_57 \| _tracegen_uop_uses_ldq_T_58; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_62 = _tracegen_uop_uses_ldq_T_61 \| _tracegen_uop_uses_ldq_T_59; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_63 = _tracegen_uop_uses_ldq_T_62 \| _tracegen_uop_uses_ldq_T_60; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_69 = _tracegen_uop_uses_ldq_T_64 \| _tracegen_uop_uses_ldq_T_65; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_70 = _tracegen_uop_uses_ldq_T_69 \| _tracegen_uop_uses_ldq_T_66; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_71 = _tracegen_uop_uses_ldq_T_70 \| _tracegen_uop_uses_ldq_T_67; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_72 = _tracegen_uop_uses_ldq_T_71 \| _tracegen_uop_uses_ldq_T_68; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_73 = _tracegen_uop_uses_ldq_T_63 \| _tracegen_uop_uses_ldq_T_72; // @[package.scala:81:59] wire _tracegen_uop_uses_ldq_T_74 = _tracegen_uop_uses_ldq_T_56 \| _tracegen_uop_uses_ldq_T_73; // @[package.scala:81:59] wire _tracegen_uop_uses_ldq_T_77 = _tracegen_uop_uses_ldq_T_75 \| _tracegen_uop_uses_ldq_T_76; // @[Consts.scala:90:{32,42,49}] wire _tracegen_uop_uses_ldq_T_79 = _tracegen_uop_uses_ldq_T_77 \| _tracegen_uop_uses_ldq_T_78; // @[Consts.scala:90:{42,59,66}] wire _tracegen_uop_uses_ldq_T_84 = _tracegen_uop_uses_ldq_T_80 \| _tracegen_uop_uses_ldq_T_81; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_85 = _tracegen_uop_uses_ldq_T_84 \| _tracegen_uop_uses_ldq_T_82; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_86 = _tracegen_uop_uses_ldq_T_85 \| _tracegen_uop_uses_ldq_T_83; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_92 = _tracegen_uop_uses_ldq_T_87 \| _tracegen_uop_uses_ldq_T_88; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_93 = _tracegen_uop_uses_ldq_T_92 \| _tracegen_uop_uses_ldq_T_89; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_94 = _tracegen_uop_uses_ldq_T_93 \| _tracegen_uop_uses_ldq_T_90; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_95 = _tracegen_uop_uses_ldq_T_94 \| _tracegen_uop_uses_ldq_T_91; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_ldq_T_96 = _tracegen_uop_uses_ldq_T_86 \| _tracegen_uop_uses_ldq_T_95; // @[package.scala:81:59] wire _tracegen_uop_uses_ldq_T_97 = _tracegen_uop_uses_ldq_T_79 \| _tracegen_uop_uses_ldq_T_96; // @[Consts.scala:87:44, :90:{59,76}] wire _tracegen_uop_uses_ldq_T_98 = ~_tracegen_uop_uses_ldq_T_97; // @[Consts.scala:90:76] assign _tracegen_uop_uses_ldq_T_99 = _tracegen_uop_uses_ldq_T_74 & _tracegen_uop_uses_ldq_T_98; // @[Consts.scala:89:68] assign tracegen_uop_uses_ldq = _tracegen_uop_uses_ldq_T_99; // @[tracegen.scala:55:30, :66:65] wire _tracegen_uop_uses_stq_T_25 = _tracegen_uop_uses_stq_T_23 \| _tracegen_uop_uses_stq_T_24; // @[Consts.scala:90:{32,42,49}] wire _tracegen_uop_uses_stq_T_27 = _tracegen_uop_uses_stq_T_25 \| _tracegen_uop_uses_stq_T_26; // @[Consts.scala:90:{42,59,66}] wire _tracegen_uop_uses_stq_T_32 = _tracegen_uop_uses_stq_T_28 \| _tracegen_uop_uses_stq_T_29; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_33 = _tracegen_uop_uses_stq_T_32 \| _tracegen_uop_uses_stq_T_30; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_34 = _tracegen_uop_uses_stq_T_33 \| _tracegen_uop_uses_stq_T_31; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_40 = _tracegen_uop_uses_stq_T_35 \| _tracegen_uop_uses_stq_T_36; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_41 = _tracegen_uop_uses_stq_T_40 \| _tracegen_uop_uses_stq_T_37; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_42 = _tracegen_uop_uses_stq_T_41 \| _tracegen_uop_uses_stq_T_38; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_43 = _tracegen_uop_uses_stq_T_42 \| _tracegen_uop_uses_stq_T_39; // @[package.scala:16:47, :81:59] wire _tracegen_uop_uses_stq_T_44 = _tracegen_uop_uses_stq_T_34 \| _tracegen_uop_uses_stq_T_43; // @[package.scala:81:59] assign _tracegen_uop_uses_stq_T_45 = _tracegen_uop_uses_stq_T_27 \| _tracegen_uop_uses_stq_T_44; // @[Consts.scala:87:44, :90:{59,76}] assign tracegen_uop_uses_stq = _tracegen_uop_uses_stq_T_45; // @[Consts.scala:90:76] wire _T = io_tracegen_req_ready_0 & io_tracegen_req_valid_0; // @[Decoupled.scala:51:35] assign _io_lsu_dis_uops_0_valid_T = _T; // @[Decoupled.scala:51:35] wire _io_lsu_agen_0_valid_T; // @[Decoupled.scala:51:35] assign _io_lsu_agen_0_valid_T = _T; // @[Decoupled.scala:51:35] wire _io_lsu_dgen_0_valid_T; // @[Decoupled.scala:51:35] assign _io_lsu_dgen_0_valid_T = _T; // @[Decoupled.scala:51:35] assign io_lsu_dis_uops_0_valid_0 = _io_lsu_dis_uops_0_valid_T; // @[Decoupled.scala:51:35] wire _rob_tail_T = &rob_tail; // @[tracegen.scala:35:25, :43:13] wire [4:0] _rob_tail_T_2 = _rob_tail_T_1[4:0]; // @[tracegen.scala:43:37] wire [4:0] _rob_tail_T_3 = _rob_tail_T ? 5'h0 : _rob_tail_T_2; // @[tracegen.scala:43:{8,13,37}] wire _io_lsu_commit_valids_0_T = ~_GEN[rob_head]; // @[tracegen.scala:34:25, :47:29, :92:31] wire _io_lsu_commit_valids_0_T_1 = rob_head != rob_tail; // @[tracegen.scala:34:25, :35:25, :92:62] wire _io_lsu_commit_valids_0_T_2 = _io_lsu_commit_valids_0_T & _io_lsu_commit_valids_0_T_1; // @[tracegen.scala:92:{31,50,62}] wire [31:0] _GEN_5 = {{rob_respd_31}, {rob_respd_30}, {rob_respd_29}, {rob_respd_28}, {rob_respd_27}, {rob_respd_26}, {rob_respd_25}, {rob_respd_24}, {rob_respd_23}, {rob_respd_22}, {rob_respd_21}, {rob_respd_20}, {rob_respd_19}, {rob_respd_18}, {rob_respd_17}, {rob_respd_16}, {rob_respd_15}, {rob_respd_14}, {rob_respd_13}, {rob_respd_12}, {rob_respd_11}, {rob_respd_10}, {rob_respd_9}, {rob_respd_8}, {rob_respd_7}, {rob_respd_6}, {rob_respd_5}, {rob_respd_4}, {rob_respd_3}, {rob_respd_2}, {rob_respd_1}, {rob_respd_0}}; // @[tracegen.scala:31:26, :92:75] assign _io_lsu_commit_valids_0_T_3 = _io_lsu_commit_valids_0_T_2 & _GEN_5[rob_head]; // @[tracegen.scala:34:25, :92:{50,75}] assign io_lsu_commit_valids_0_0 = _io_lsu_commit_valids_0_T_3; // @[tracegen.scala:19:7, :92:75] wire [31:0][31:0] _GEN_6 = {{rob_uop_31_debug_inst}, {rob_uop_30_debug_inst}, {rob_uop_29_debug_inst}, {rob_uop_28_debug_inst}, {rob_uop_27_debug_inst}, {rob_uop_26_debug_inst}, {rob_uop_25_debug_inst}, {rob_uop_24_debug_inst}, {rob_uop_23_debug_inst}, {rob_uop_22_debug_inst}, {rob_uop_21_debug_inst}, {rob_uop_20_debug_inst}, {rob_uop_19_debug_inst}, {rob_uop_18_debug_inst}, {rob_uop_17_debug_inst}, {rob_uop_16_debug_inst}, {rob_uop_15_debug_inst}, {rob_uop_14_debug_inst}, {rob_uop_13_debug_inst}, {rob_uop_12_debug_inst}, {rob_uop_11_debug_inst}, {rob_uop_10_debug_inst}, {rob_uop_9_debug_inst}, {rob_uop_8_debug_inst}, {rob_uop_7_debug_inst}, {rob_uop_6_debug_inst}, {rob_uop_5_debug_inst}, {rob_uop_4_debug_inst}, {rob_uop_3_debug_inst}, {rob_uop_2_debug_inst}, {rob_uop_1_debug_inst}, {rob_uop_0_debug_inst}}; // @[tracegen.scala:32:20, :93:27] assign io_lsu_commit_uops_0_debug_inst_0 = _GEN_6[rob_head]; // @[tracegen.scala:19:7, :34:25, :93:27] wire [31:0] _GEN_7 = {{rob_uop_31_is_amo}, {rob_uop_30_is_amo}, {rob_uop_29_is_amo}, {rob_uop_28_is_amo}, {rob_uop_27_is_amo}, {rob_uop_26_is_amo}, {rob_uop_25_is_amo}, {rob_uop_24_is_amo}, {rob_uop_23_is_amo}, {rob_uop_22_is_amo}, {rob_uop_21_is_amo}, {rob_uop_20_is_amo}, {rob_uop_19_is_amo}, {rob_uop_18_is_amo}, {rob_uop_17_is_amo}, {rob_uop_16_is_amo}, {rob_uop_15_is_amo}, {rob_uop_14_is_amo}, {rob_uop_13_is_amo}, {rob_uop_12_is_amo}, {rob_uop_11_is_amo}, {rob_uop_10_is_amo}, {rob_uop_9_is_amo}, {rob_uop_8_is_amo}, {rob_uop_7_is_amo}, {rob_uop_6_is_amo}, {rob_uop_5_is_amo}, {rob_uop_4_is_amo}, {rob_uop_3_is_amo}, {rob_uop_2_is_amo}, {rob_uop_1_is_amo}, {rob_uop_0_is_amo}}; // @[tracegen.scala:32:20, :93:27] assign io_lsu_commit_uops_0_is_amo_0 = _GEN_7[rob_head]; // @[tracegen.scala:19:7, :34:25, :93:27] wire [31:0][4:0] _GEN_8 = {{rob_uop_31_rob_idx}, {rob_uop_30_rob_idx}, {rob_uop_29_rob_idx}, {rob_uop_28_rob_idx}, {rob_uop_27_rob_idx}, {rob_uop_26_rob_idx}, {rob_uop_25_rob_idx}, {rob_uop_24_rob_idx}, {rob_uop_23_rob_idx}, {rob_uop_22_rob_idx}, {rob_uop_21_rob_idx}, {rob_uop_20_rob_idx}, {rob_uop_19_rob_idx}, {rob_uop_18_rob_idx}, {rob_uop_17_rob_idx}, {rob_uop_16_rob_idx}, {rob_uop_15_rob_idx}, {rob_uop_14_rob_idx}, {rob_uop_13_rob_idx}, {rob_uop_12_rob_idx}, {rob_uop_11_rob_idx}, {rob_uop_10_rob_idx}, {rob_uop_9_rob_idx}, {rob_uop_8_rob_idx}, {rob_uop_7_rob_idx}, {rob_uop_6_rob_idx}, {rob_uop_5_rob_idx}, {rob_uop_4_rob_idx}, {rob_uop_3_rob_idx}, {rob_uop_2_rob_idx}, {rob_uop_1_rob_idx}, {rob_uop_0_rob_idx}}; // @[tracegen.scala:32:20, :93:27] assign io_lsu_commit_uops_0_rob_idx_0 = _GEN_8[rob_head]; // @[tracegen.scala:19:7, :34:25, :93:27] wire [31:0][3:0] _GEN_9 = {{rob_uop_31_ldq_idx}, {rob_uop_30_ldq_idx}, {rob_uop_29_ldq_idx}, {rob_uop_28_ldq_idx}, {rob_uop_27_ldq_idx}, {rob_uop_26_ldq_idx}, {rob_uop_25_ldq_idx}, {rob_uop_24_ldq_idx}, {rob_uop_23_ldq_idx}, {rob_uop_22_ldq_idx}, {rob_uop_21_ldq_idx}, {rob_uop_20_ldq_idx}, {rob_uop_19_ldq_idx}, {rob_uop_18_ldq_idx}, {rob_uop_17_ldq_idx}, {rob_uop_16_ldq_idx}, {rob_uop_15_ldq_idx}, {rob_uop_14_ldq_idx}, {rob_uop_13_ldq_idx}, {rob_uop_12_ldq_idx}, {rob_uop_11_ldq_idx}, {rob_uop_10_ldq_idx}, {rob_uop_9_ldq_idx}, {rob_uop_8_ldq_idx}, {rob_uop_7_ldq_idx}, {rob_uop_6_ldq_idx}, {rob_uop_5_ldq_idx}, {rob_uop_4_ldq_idx}, {rob_uop_3_ldq_idx}, {rob_uop_2_ldq_idx}, {rob_uop_1_ldq_idx}, {rob_uop_0_ldq_idx}}; // @[tracegen.scala:32:20, :93:27] assign io_lsu_commit_uops_0_ldq_idx_0 = _GEN_9[rob_head]; // @[tracegen.scala:19:7, :34:25, :93:27] wire [31:0][3:0] _GEN_10 = {{rob_uop_31_stq_idx}, {rob_uop_30_stq_idx}, {rob_uop_29_stq_idx}, {rob_uop_28_stq_idx}, {rob_uop_27_stq_idx}, {rob_uop_26_stq_idx}, {rob_uop_25_stq_idx}, {rob_uop_24_stq_idx}, {rob_uop_23_stq_idx}, {rob_uop_22_stq_idx}, {rob_uop_21_stq_idx}, {rob_uop_20_stq_idx}, {rob_uop_19_stq_idx}, {rob_uop_18_stq_idx}, {rob_uop_17_stq_idx}, {rob_uop_16_stq_idx}, {rob_uop_15_stq_idx}, {rob_uop_14_stq_idx}, {rob_uop_13_stq_idx}, {rob_uop_12_stq_idx}, {rob_uop_11_stq_idx}, {rob_uop_10_stq_idx}, {rob_uop_9_stq_idx}, {rob_uop_8_stq_idx}, {rob_uop_7_stq_idx}, {rob_uop_6_stq_idx}, {rob_uop_5_stq_idx}, {rob_uop_4_stq_idx}, {rob_uop_3_stq_idx}, {rob_uop_2_stq_idx}, {rob_uop_1_stq_idx}, {rob_uop_0_stq_idx}}; // @[tracegen.scala:32:20, :93:27] assign io_lsu_commit_uops_0_stq_idx_0 = _GEN_10[rob_head]; // @[tracegen.scala:19:7, :34:25, :93:27] wire [31:0][4:0] _GEN_11 = {{rob_uop_31_mem_cmd}, {rob_uop_30_mem_cmd}, {rob_uop_29_mem_cmd}, {rob_uop_28_mem_cmd}, {rob_uop_27_mem_cmd}, {rob_uop_26_mem_cmd}, {rob_uop_25_mem_cmd}, {rob_uop_24_mem_cmd}, {rob_uop_23_mem_cmd}, {rob_uop_22_mem_cmd}, {rob_uop_21_mem_cmd}, {rob_uop_20_mem_cmd}, {rob_uop_19_mem_cmd}, {rob_uop_18_mem_cmd}, {rob_uop_17_mem_cmd}, {rob_uop_16_mem_cmd}, {rob_uop_15_mem_cmd}, {rob_uop_14_mem_cmd}, {rob_uop_13_mem_cmd}, {rob_uop_12_mem_cmd}, {rob_uop_11_mem_cmd}, {rob_uop_10_mem_cmd}, {rob_uop_9_mem_cmd}, {rob_uop_8_mem_cmd}, {rob_uop_7_mem_cmd}, {rob_uop_6_mem_cmd}, {rob_uop_5_mem_cmd}, {rob_uop_4_mem_cmd}, {rob_uop_3_mem_cmd}, {rob_uop_2_mem_cmd}, {rob_uop_1_mem_cmd}, {rob_uop_0_mem_cmd}}; // @[tracegen.scala:32:20, :93:27] assign io_lsu_commit_uops_0_mem_cmd_0 = _GEN_11[rob_head]; // @[tracegen.scala:19:7, :34:25, :93:27] wire [31:0] _GEN_12 = {{rob_uop_31_uses_ldq}, {rob_uop_30_uses_ldq}, {rob_uop_29_uses_ldq}, {rob_uop_28_uses_ldq}, {rob_uop_27_uses_ldq}, {rob_uop_26_uses_ldq}, {rob_uop_25_uses_ldq}, {rob_uop_24_uses_ldq}, {rob_uop_23_uses_ldq}, {rob_uop_22_uses_ldq}, {rob_uop_21_uses_ldq}, {rob_uop_20_uses_ldq}, {rob_uop_19_uses_ldq}, {rob_uop_18_uses_ldq}, {rob_uop_17_uses_ldq}, {rob_uop_16_uses_ldq}, {rob_uop_15_uses_ldq}, {rob_uop_14_uses_ldq}, {rob_uop_13_uses_ldq}, {rob_uop_12_uses_ldq}, {rob_uop_11_uses_ldq}, {rob_uop_10_uses_ldq}, {rob_uop_9_uses_ldq}, {rob_uop_8_uses_ldq}, {rob_uop_7_uses_ldq}, {rob_uop_6_uses_ldq}, {rob_uop_5_uses_ldq}, {rob_uop_4_uses_ldq}, {rob_uop_3_uses_ldq}, {rob_uop_2_uses_ldq}, {rob_uop_1_uses_ldq}, {rob_uop_0_uses_ldq}}; // @[tracegen.scala:32:20, :93:27] assign io_lsu_commit_uops_0_uses_ldq_0 = _GEN_12[rob_head]; // @[tracegen.scala:19:7, :34:25, :93:27] wire [31:0] _GEN_13 = {{rob_uop_31_uses_stq}, {rob_uop_30_uses_stq}, {rob_uop_29_uses_stq}, {rob_uop_28_uses_stq}, {rob_uop_27_uses_stq}, {rob_uop_26_uses_stq}, {rob_uop_25_uses_stq}, {rob_uop_24_uses_stq}, {rob_uop_23_uses_stq}, {rob_uop_22_uses_stq}, {rob_uop_21_uses_stq}, {rob_uop_20_uses_stq}, {rob_uop_19_uses_stq}, {rob_uop_18_uses_stq}, {rob_uop_17_uses_stq}, {rob_uop_16_uses_stq}, {rob_uop_15_uses_stq}, {rob_uop_14_uses_stq}, {rob_uop_13_uses_stq}, {rob_uop_12_uses_stq}, {rob_uop_11_uses_stq}, {rob_uop_10_uses_stq}, {rob_uop_9_uses_stq}, {rob_uop_8_uses_stq}, {rob_uop_7_uses_stq}, {rob_uop_6_uses_stq}, {rob_uop_5_uses_stq}, {rob_uop_4_uses_stq}, {rob_uop_3_uses_stq}, {rob_uop_2_uses_stq}, {rob_uop_1_uses_stq}, {rob_uop_0_uses_stq}}; // @[tracegen.scala:32:20, :93:27] assign io_lsu_commit_uops_0_uses_stq_0 = _GEN_13[rob_head]; // @[tracegen.scala:19:7, :34:25, :93:27] wire _rob_head_T = &rob_head; // @[tracegen.scala:34:25, :43:13] wire [5:0] _rob_head_T_1 = {1'h0, rob_head} + 6'h1; // @[tracegen.scala:34:25, :43:37] wire [4:0] _rob_head_T_2 = _rob_head_T_1[4:0]; // @[tracegen.scala:43:37] wire [4:0] _rob_head_T_3 = _rob_head_T ? 5'h0 : _rob_head_T_2; // @[tracegen.scala:43:{8,13,37}] wire [31:0][4:0] _GEN_14 = {{rob_31_cmd}, {rob_30_cmd}, {rob_29_cmd}, {rob_28_cmd}, {rob_27_cmd}, {rob_26_cmd}, {rob_25_cmd}, {rob_24_cmd}, {rob_23_cmd}, {rob_22_cmd}, {rob_21_cmd}, {rob_20_cmd}, {rob_19_cmd}, {rob_18_cmd}, {rob_17_cmd}, {rob_16_cmd}, {rob_15_cmd}, {rob_14_cmd}, {rob_13_cmd}, {rob_12_cmd}, {rob_11_cmd}, {rob_10_cmd}, {rob_9_cmd}, {rob_8_cmd}, {rob_7_cmd}, {rob_6_cmd}, {rob_5_cmd}, {rob_4_cmd}, {rob_3_cmd}, {rob_2_cmd}, {rob_1_cmd}, {rob_0_cmd}}; // @[tracegen.scala:30:16, :102:74]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation */ def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag }	module OptimizationBarrier_TLBEntryData_303( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to the following Chisel files. File RecFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import consts._ class RecFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val in = Input(Bits((inExpWidth + inSigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in); if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- io.out := io.in<<(outSigWidth - inSigWidth) io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W) } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( inExpWidth, inSigWidth, outExpWidth, outSigWidth, flRoundOpt_sigMSBitAlwaysZero )) roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn) roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := rawIn roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } } File rawFloatFromRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ /---------------------------------------------------------------------------- \| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be \| set. ----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }	module RecFNToRecFN_187( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_62( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_90 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File HasChipyardPRCI.scala: package chipyard.clocking import chisel3._ import scala.collection.mutable.{ArrayBuffer} import org.chipsalliance.cde.config.{Parameters, Field, Config} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.regmapper._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import freechips.rocketchip.prci._ import testchipip.boot.{TLTileResetCtrl} import testchipip.clocking.{ClockGroupFakeResetSynchronizer} case class ChipyardPRCIControlParams( slaveWhere: TLBusWrapperLocation = CBUS, baseAddress: BigInt = 0x100000, enableTileClockGating: Boolean = true, enableTileResetSetting: Boolean = true, enableResetSynchronizers: Boolean = true // this should only be disabled to work around verilator async-reset initialization problems ) { def generatePRCIXBar = enableTileClockGating \|\| enableTileResetSetting } case object ChipyardPRCIControlKey extends Field[ChipyardPRCIControlParams](ChipyardPRCIControlParams()) trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElements => require(!p(SubsystemDriveClockGroupsFromIO), "Subsystem allClockGroups cannot be driven from implicit clocks") val prciParams = p(ChipyardPRCIControlKey) // Set up clock domain private val tlbus = locateTLBusWrapper(prciParams.slaveWhere) val prci_ctrl_domain = tlbus.generateSynchronousDomain("ChipyardPRCICtrl") .suggestName("chipyard_prcictrl_domain") val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar(nameSuffix = Some("prcibus")) } } prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar := TLFIFOFixer(TLFIFOFixer.all) := TLBuffer() := _) }) // Aggregate all the clock groups into a single node val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node // The diplomatic clocks in the subsystem are routed to this allClockGroupsNode val clockNamePrefixer = ClockGroupNamePrefixer() (allClockGroupsNode := clockNamePrefixer := aggregator) // Once all the clocks are gathered in the aggregator node, several steps remain // 1. Assign frequencies to any clock groups which did not specify a frequency. // 2. Combine duplicated clock groups (clock groups which physically should be in the same clock domain) // 3. Synchronize reset to each clock group // 4. Clock gate the clock groups corresponding to Tiles (if desired). // 5. Add reset control registers to the tiles (if desired) // The final clock group here contains physically distinct clock domains, which some PRCI node in a // diplomatic IOBinder should drive val frequencySpecifier = ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey)) val clockGroupCombiner = ClockGroupCombiner() val resetSynchronizer = prci_ctrl_domain { if (prciParams.enableResetSynchronizers) ClockGroupResetSynchronizer() else ClockGroupFakeResetSynchronizer() } val tileClockGater = Option.when(prciParams.enableTileClockGating) { prci_ctrl_domain { val clock_gater = LazyModule(new TileClockGater(prciParams.baseAddress + 0x00000, tlbus.beatBytes)) clock_gater.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileClockGater")) := prci_ctrl_bus.get clock_gater } } val tileResetSetter = Option.when(prciParams.enableTileResetSetting) { prci_ctrl_domain { val reset_setter = LazyModule(new TileResetSetter(prciParams.baseAddress + 0x10000, tlbus.beatBytes, tile_prci_domains.map(_._2.tile_reset_domain.clockNode.portParams(0).name.get).toSeq, Nil)) reset_setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileResetSetter")) := prci_ctrl_bus.get reset_setter } } if (!prciParams.enableResetSynchronizers) { println(Console.RED + s""" !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! WARNING: DISABLING THE RESET SYNCHRONIZERS RESULTS IN A BROKEN DESIGN THAT WILL NOT BEHAVE PROPERLY AS ASIC OR FPGA. THESE SHOULD ONLY BE DISABLED TO WORK AROUND LIMITATIONS IN ASYNC RESET INITIALIZATION IN RTL SIMULATORS, NAMELY VERILATOR. !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! """ + Console.RESET) } // The chiptopClockGroupsNode shouuld be what ClockBinders attach to val chiptopClockGroupsNode = ClockGroupEphemeralNode() (aggregator := frequencySpecifier := clockGroupCombiner := resetSynchronizer := tileClockGater.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp"))) := tileResetSetter.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp"))) := chiptopClockGroupsNode) } File Fragmenter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes} import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1} import scala.math.min import freechips.rocketchip.util.DataToAugmentedData object EarlyAck { sealed trait T case object AllPuts extends T case object PutFulls extends T case object None extends T } // minSize: minimum size of transfers supported by all outward managers // maxSize: maximum size of transfers supported after the Fragmenter is applied // alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager) // earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat // holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst // nameSuffix: appends a suffix to the module name // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize") require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize") require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize") val fragmentBits = log2Ceil(maxSize / minSize) val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0 val toggleBits = 1 val addedBits = fragmentBits + toggleBits + fullBits def expandTransfer(x: TransferSizes, op: String) = if (!x) x else { // validate that we can apply the fragmenter correctly require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})") TransferSizes(x.min, maxSize) } private def noChangeRequired = minSize == maxSize private def shrinkTransfer(x: TransferSizes) = if (!alwaysMin) x else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max)) else TransferSizes.none private def mapManager(m: TLSlaveParameters) = m.v1copy( supportsArithmetic = shrinkTransfer(m.supportsArithmetic), supportsLogical = shrinkTransfer(m.supportsLogical), supportsGet = expandTransfer(m.supportsGet, "Get"), supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"), supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"), supportsHint = expandTransfer(m.supportsHint, "Hint")) val node = new TLAdapterNode( // We require that all the responses are mutually FIFO // Thus we need to compact all of the masters into one big master clientFn = { c => (if (noChangeRequired) c else c.v2copy( masters = Seq(TLMasterParameters.v2( name = "TLFragmenter", sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) ))}, managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) } ) { override def circuitIdentity = noChangeRequired } lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => if (noChangeRequired) { out <> in } else { // All managers must share a common FIFO domain (responses might end up interleaved) val manager = edgeOut.manager val managers = manager.managers val beatBytes = manager.beatBytes val fifoId = managers(0).fifoId require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _)) require (!manager.anySupportAcquireB \|\| !edgeOut.client.anySupportProbe, s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region") require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses") // We can't support devices which are cached on both sides of us require (!edgeOut.manager.anySupportAcquireB \|\| !edgeIn.client.anySupportProbe) // We can't support denied because we reassemble fragments require (!edgeOut.manager.mayDenyGet \|\| holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true") require (!edgeOut.manager.mayDenyPut \|\| earlyAck == EarlyAck.None) /* The Fragmenter is a bit tricky, because there are 5 sizes in play: * max size -- the maximum transfer size possible * orig size -- the original pre-fragmenter size * frag size -- the modified post-fragmenter size * min size -- the threshold below which frag=orig * beat size -- the amount transfered on any given beat * * The relationships are as follows: * max >= orig >= frag * max > min >= beat * It IS possible that orig <= min (then frag=orig; ie: no fragmentation) * * The fragment# (sent via TL.source) is measured in multiples of min size. * Meanwhile, to track the progress, counters measure in multiples of beat size. * * Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16. * * in.A out.A (frag#) out.D (frag#) in.D gen# ack# * get64 get16 6 ackD16 6 ackD64 12 15 * ackD16 6 ackD64 14 * ackD16 6 ackD64 13 * ackD16 6 ackD64 12 * get16 4 ackD16 4 ackD64 8 11 * ackD16 4 ackD64 10 * ackD16 4 ackD64 9 * ackD16 4 ackD64 8 * get16 2 ackD16 2 ackD64 4 7 * ackD16 2 ackD64 6 * ackD16 2 ackD64 5 * ackD16 2 ackD64 4 * get16 0 ackD16 0 ackD64 0 3 * ackD16 0 ackD64 2 * ackD16 0 ackD64 1 * ackD16 0 ackD64 0 * * get8 get8 0 ackD8 0 ackD8 0 1 * ackD8 0 ackD8 0 * * get4 get4 0 ackD4 0 ackD4 0 0 * get1 get1 0 ackD1 0 ackD1 0 0 * * put64 put16 6 15 * put64 put16 6 14 * put64 put16 6 13 * put64 put16 6 ack16 6 12 12 * put64 put16 4 11 * put64 put16 4 10 * put64 put16 4 9 * put64 put16 4 ack16 4 8 8 * put64 put16 2 7 * put64 put16 2 6 * put64 put16 2 5 * put64 put16 2 ack16 2 4 4 * put64 put16 0 3 * put64 put16 0 2 * put64 put16 0 1 * put64 put16 0 ack16 0 ack64 0 0 * * put8 put8 0 1 * put8 put8 0 ack8 0 ack8 0 0 * * put4 put4 0 ack4 0 ack4 0 0 * put1 put1 0 ack1 0 ack1 0 0 / val counterBits = log2Up(maxSize/beatBytes) val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize) // Consider the following waveform for two 4-beat bursts: // ---A----A------------ // -------D-----DDD-DDDD // Under TL rules, the second A can use the same source as the first A, // because the source is released for reuse on the first response beat. // // However, if we fragment the requests, it looks like this: // ---3210-3210--------- // -------3-----210-3210 // ... now we've broken the rules because 210 are twice inflight. // // This phenomenon means we can have essentially 2maxSize/minSize-1 // fragmented transactions in flight per original transaction source. // // To keep the source unique, we encode the beat counter in the low // bits of the source. To solve the overlap, we use a toggle bit. // Whatever toggle bit the D is reassembling, A will use the opposite. // First, handle the return path val acknum = RegInit(0.U(counterBits.W)) val dOrig = Reg(UInt()) val dToggle = RegInit(false.B) val dFragnum = out.d.bits.source(fragmentBits-1, 0) val dFirst = acknum === 0.U val dLast = dFragnum === 0.U // only for AccessAck (!Data) val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1) val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize)) val dHasData = edgeOut.hasData(out.d.bits) // calculate new acknum val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes) val acknum_size = dsizeOH1 >> log2Ceil(beatBytes) assert (!out.d.valid \|\| (acknum_fragment & acknum_size) === 0.U) val dFirst_acknum = acknum_fragment \| Mux(dHasData, acknum_size, 0.U) val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes)) // calculate the original size val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) \| dsizeOH1) when (out.d.fire) { acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement) when (dFirst) { dOrig := dFirst_size dToggle := out.d.bits.source(fragmentBits) } } // Swallow up non-data ack fragments val doEarlyAck = earlyAck match { case EarlyAck.AllPuts => true.B case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1) case EarlyAck.None => false.B } val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast) out.d.ready := in.d.ready \|\| drop in.d.valid := out.d.valid && !drop in.d.bits := out.d.bits // pass most stuff unchanged in.d.bits.source := out.d.bits.source >> addedBits in.d.bits.size := Mux(dFirst, dFirst_size, dOrig) if (edgeOut.manager.mayDenyPut) { val r_denied = Reg(Bool()) val d_denied = (!dFirst && r_denied) \|\| out.d.bits.denied when (out.d.fire) { r_denied := d_denied } in.d.bits.denied := d_denied } if (edgeOut.manager.mayDenyGet) { // Take denied only from the first beat and hold that value val d_denied = out.d.bits.denied holdUnless dFirst when (dHasData) { in.d.bits.denied := d_denied in.d.bits.corrupt := d_denied \|\| out.d.bits.corrupt } } // What maximum transfer sizes do downstream devices support? val maxArithmetics = managers.map(_.supportsArithmetic.max) val maxLogicals = managers.map(_.supportsLogical.max) val maxGets = managers.map(_.supportsGet.max) val maxPutFulls = managers.map(_.supportsPutFull.max) val maxPutPartials = managers.map(_.supportsPutPartial.max) val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0) // We assume that the request is valid => size 0 is impossible val lgMinSize = log2Ceil(minSize).U val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U) val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U) // Make the request repeatable val repeater = Module(new Repeater(in.a.bits)) repeater.io.enq <> in.a val in_a = repeater.io.deq // If this is infront of a single manager, these become constants val find = manager.findFast(edgeIn.address(in_a.bits)) val maxLgArithmetic = Mux1H(find, maxLgArithmetics) val maxLgLogical = Mux1H(find, maxLgLogicals) val maxLgGet = Mux1H(find, maxLgGets) val maxLgPutFull = Mux1H(find, maxLgPutFulls) val maxLgPutPartial = Mux1H(find, maxLgPutPartials) val maxLgHint = Mux1H(find, maxLgHints) val limit = if (alwaysMin) lgMinSize else MuxLookup(in_a.bits.opcode, lgMinSize)(Array( TLMessages.PutFullData -> maxLgPutFull, TLMessages.PutPartialData -> maxLgPutPartial, TLMessages.ArithmeticData -> maxLgArithmetic, TLMessages.LogicalData -> maxLgLogical, TLMessages.Get -> maxLgGet, TLMessages.Hint -> maxLgHint)) val aOrig = in_a.bits.size val aFrag = Mux(aOrig > limit, limit, aOrig) val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize)) val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize)) val aHasData = edgeIn.hasData(in_a.bits) val aMask = Mux(aHasData, 0.U, aFragOH1) val gennum = RegInit(0.U(counterBits.W)) val aFirst = gennum === 0.U val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U) val new_gennum = ~(~old_gennum1 \| (aMask >> log2Ceil(beatBytes))) // ~(~x\|y) is width safe val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) \| (aFragOH1 >> log2Ceil(minSize))) val aLast = aFragnum === 0.U val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst)) val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None when (out.a.fire) { gennum := new_gennum } repeater.io.repeat := !aHasData && aFragnum =/= 0.U out.a <> in_a out.a.bits.address := in_a.bits.address \| ~(old_gennum1 << log2Ceil(beatBytes) \| ~aOrigOH1 \| aFragOH1 \| (minSize-1).U) out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum)) out.a.bits.size := aFrag // Optimize away some of the Repeater's registers assert (!repeater.io.full \|\| !aHasData) out.a.bits.data := in.a.bits.data val fullMask = ((BigInt(1) << beatBytes) - 1).U assert (!repeater.io.full \|\| in_a.bits.mask === fullMask) out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask) out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData) // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLFragmenter { def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { if (minSize <= maxSize) { val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix)) fragmenter.node } else { TLEphemeralNode()(ValName("no_fragmenter")) } } def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix) def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None) } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) (ram.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.1) := TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLFragmenter(ramBeatBytes, maxSize/2) := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := model.node := fuzz.node) lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module) io.finished := dut.io.finished dut.io.start := io.start } File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File ResetSynchronizer.scala: // See LICENSE for license details. package freechips.rocketchip.prci import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.ResetCatchAndSync /** * Synchronizes the reset of a diplomatic clock-reset pair to its accompanying clock. / class ResetSynchronizer(implicit p: Parameters) extends LazyModule { val node = ClockAdapterNode() lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { (node.out zip node.in).map { case ((o, _), (i, _)) => o.clock := i.clock o.reset := ResetCatchAndSync(i.clock, i.reset.asBool) } } } object ResetSynchronizer { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ResetSynchronizer()).node } /* * Instantiates a reset synchronizer on all clock-reset pairs in a clock group. / class ClockGroupResetSynchronizer(implicit p: Parameters) extends LazyModule { val node = ClockGroupAdapterNode() lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { (node.out zip node.in).map { case ((oG, _), (iG, _)) => (oG.member.data zip iG.member.data).foreach { case (o, i) => o.clock := i.clock o.reset := ResetCatchAndSync(i.clock, i.reset.asBool) } } } } object ClockGroupResetSynchronizer { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupResetSynchronizer()).node } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size node.out.size) > (832)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source \| r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source \| r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink \| r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ \|\| _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) \|\| o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) \|\| o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) \|\| (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }	module ChipyardPRCICtrlClockSinkDomain( // @[ClockDomain.scala:14:9] input auto_reset_setter_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_reset_setter_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_resetSynchronizer_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] output auto_resetSynchronizer_out_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_xbar_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_xbar_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_xbar_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_xbar_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_xbar_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_xbar_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_xbar_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_xbar_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_xbar_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_xbar_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_xbar_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_xbar_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_xbar_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_xbar_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_xbar_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_xbar_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_in_reset // @[LazyModuleImp.scala:107:25] ); wire _fragmenter_1_auto_anon_out_a_valid; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_1_auto_anon_out_a_bits_opcode; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_1_auto_anon_out_a_bits_param; // @[Fragmenter.scala:345:34] wire [1:0] _fragmenter_1_auto_anon_out_a_bits_size; // @[Fragmenter.scala:345:34] wire [10:0] _fragmenter_1_auto_anon_out_a_bits_source; // @[Fragmenter.scala:345:34] wire [20:0] _fragmenter_1_auto_anon_out_a_bits_address; // @[Fragmenter.scala:345:34] wire [7:0] _fragmenter_1_auto_anon_out_a_bits_mask; // @[Fragmenter.scala:345:34] wire [63:0] _fragmenter_1_auto_anon_out_a_bits_data; // @[Fragmenter.scala:345:34] wire _fragmenter_1_auto_anon_out_a_bits_corrupt; // @[Fragmenter.scala:345:34] wire _fragmenter_1_auto_anon_out_d_ready; // @[Fragmenter.scala:345:34] wire _reset_setter_auto_clock_out_member_allClocks_uncore_clock; // @[HasChipyardPRCI.scala:78:34] wire _reset_setter_auto_clock_out_member_allClocks_uncore_reset; // @[HasChipyardPRCI.scala:78:34] wire _fragmenter_auto_anon_in_a_ready; // @[Fragmenter.scala:345:34] wire _fragmenter_auto_anon_in_d_valid; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_auto_anon_in_d_bits_opcode; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_auto_anon_in_d_bits_size; // @[Fragmenter.scala:345:34] wire [6:0] _fragmenter_auto_anon_in_d_bits_source; // @[Fragmenter.scala:345:34] wire [63:0] _fragmenter_auto_anon_in_d_bits_data; // @[Fragmenter.scala:345:34] wire _fragmenter_auto_anon_out_a_valid; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_auto_anon_out_a_bits_opcode; // @[Fragmenter.scala:345:34] wire [2:0] _fragmenter_auto_anon_out_a_bits_param; // @[Fragmenter.scala:345:34] wire [1:0] _fragmenter_auto_anon_out_a_bits_size; // @[Fragmenter.scala:345:34] wire [10:0] _fragmenter_auto_anon_out_a_bits_source; // @[Fragmenter.scala:345:34] wire [20:0] _fragmenter_auto_anon_out_a_bits_address; // @[Fragmenter.scala:345:34] wire [7:0] _fragmenter_auto_anon_out_a_bits_mask; // @[Fragmenter.scala:345:34] wire [63:0] _fragmenter_auto_anon_out_a_bits_data; // @[Fragmenter.scala:345:34] wire _fragmenter_auto_anon_out_a_bits_corrupt; // @[Fragmenter.scala:345:34] wire _fragmenter_auto_anon_out_d_ready; // @[Fragmenter.scala:345:34] wire _clock_gater_auto_clock_gater_in_1_a_ready; // @[HasChipyardPRCI.scala:73:33] wire _clock_gater_auto_clock_gater_in_1_d_valid; // @[HasChipyardPRCI.scala:73:33] wire [2:0] _clock_gater_auto_clock_gater_in_1_d_bits_opcode; // @[HasChipyardPRCI.scala:73:33] wire [1:0] _clock_gater_auto_clock_gater_in_1_d_bits_size; // @[HasChipyardPRCI.scala:73:33] wire [10:0] _clock_gater_auto_clock_gater_in_1_d_bits_source; // @[HasChipyardPRCI.scala:73:33] wire [63:0] _clock_gater_auto_clock_gater_in_1_d_bits_data; // @[HasChipyardPRCI.scala:73:33] wire _clock_gater_auto_clock_gater_out_member_allClocks_uncore_clock; // @[HasChipyardPRCI.scala:73:33] wire _clock_gater_auto_clock_gater_out_member_allClocks_uncore_reset; // @[HasChipyardPRCI.scala:73:33] wire _xbar_auto_anon_out_1_a_valid; // @[Xbar.scala:346:26] wire [2:0] _xbar_auto_anon_out_1_a_bits_opcode; // @[Xbar.scala:346:26] wire [2:0] _xbar_auto_anon_out_1_a_bits_param; // @[Xbar.scala:346:26] wire [2:0] _xbar_auto_anon_out_1_a_bits_size; // @[Xbar.scala:346:26] wire [6:0] _xbar_auto_anon_out_1_a_bits_source; // @[Xbar.scala:346:26] wire [20:0] _xbar_auto_anon_out_1_a_bits_address; // @[Xbar.scala:346:26] wire [7:0] _xbar_auto_anon_out_1_a_bits_mask; // @[Xbar.scala:346:26] wire [63:0] _xbar_auto_anon_out_1_a_bits_data; // @[Xbar.scala:346:26] wire _xbar_auto_anon_out_1_a_bits_corrupt; // @[Xbar.scala:346:26] wire _xbar_auto_anon_out_1_d_ready; // @[Xbar.scala:346:26] wire _xbar_auto_anon_out_0_a_valid; // @[Xbar.scala:346:26] wire [2:0] _xbar_auto_anon_out_0_a_bits_opcode; // @[Xbar.scala:346:26] wire [2:0] _xbar_auto_anon_out_0_a_bits_param; // @[Xbar.scala:346:26] wire [2:0] _xbar_auto_anon_out_0_a_bits_size; // @[Xbar.scala:346:26] wire [6:0] _xbar_auto_anon_out_0_a_bits_source; // @[Xbar.scala:346:26] wire [20:0] _xbar_auto_anon_out_0_a_bits_address; // @[Xbar.scala:346:26] wire [7:0] _xbar_auto_anon_out_0_a_bits_mask; // @[Xbar.scala:346:26] wire [63:0] _xbar_auto_anon_out_0_a_bits_data; // @[Xbar.scala:346:26] wire _xbar_auto_anon_out_0_a_bits_corrupt; // @[Xbar.scala:346:26] wire _xbar_auto_anon_out_0_d_ready; // @[Xbar.scala:346:26] wire auto_reset_setter_clock_in_member_allClocks_uncore_clock_0 = auto_reset_setter_clock_in_member_allClocks_uncore_clock; // @[ClockDomain.scala:14:9] wire auto_reset_setter_clock_in_member_allClocks_uncore_reset_0 = auto_reset_setter_clock_in_member_allClocks_uncore_reset; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_a_valid_0 = auto_xbar_anon_in_a_valid; // @[ClockDomain.scala:14:9] wire [2:0] auto_xbar_anon_in_a_bits_opcode_0 = auto_xbar_anon_in_a_bits_opcode; // @[ClockDomain.scala:14:9] wire [2:0] auto_xbar_anon_in_a_bits_param_0 = auto_xbar_anon_in_a_bits_param; // @[ClockDomain.scala:14:9] wire [2:0] auto_xbar_anon_in_a_bits_size_0 = auto_xbar_anon_in_a_bits_size; // @[ClockDomain.scala:14:9] wire [6:0] auto_xbar_anon_in_a_bits_source_0 = auto_xbar_anon_in_a_bits_source; // @[ClockDomain.scala:14:9] wire [20:0] auto_xbar_anon_in_a_bits_address_0 = auto_xbar_anon_in_a_bits_address; // @[ClockDomain.scala:14:9] wire [7:0] auto_xbar_anon_in_a_bits_mask_0 = auto_xbar_anon_in_a_bits_mask; // @[ClockDomain.scala:14:9] wire [63:0] auto_xbar_anon_in_a_bits_data_0 = auto_xbar_anon_in_a_bits_data; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_a_bits_corrupt_0 = auto_xbar_anon_in_a_bits_corrupt; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_d_ready_0 = auto_xbar_anon_in_d_ready; // @[ClockDomain.scala:14:9] wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9] wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9] wire [1:0] auto_xbar_anon_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9] wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9] wire auto_resetSynchronizer_out_member_allClocks_uncore_clock_0; // @[ClockDomain.scala:14:9] wire auto_resetSynchronizer_out_member_allClocks_uncore_reset_0; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_xbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] wire [2:0] auto_xbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9] wire [6:0] auto_xbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9] wire [63:0] auto_xbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9] wire auto_xbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9] wire childClock; // @[LazyModuleImp.scala:155:31] wire childReset; // @[LazyModuleImp.scala:158:31] assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17] assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17] TLXbar_prcibus_i1_o2_a21d64s7k1z3u xbar ( // @[Xbar.scala:346:26] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_a_ready (auto_xbar_anon_in_a_ready_0), .auto_anon_in_a_valid (auto_xbar_anon_in_a_valid_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_opcode (auto_xbar_anon_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_param (auto_xbar_anon_in_a_bits_param_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_size (auto_xbar_anon_in_a_bits_size_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_source (auto_xbar_anon_in_a_bits_source_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_address (auto_xbar_anon_in_a_bits_address_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_mask (auto_xbar_anon_in_a_bits_mask_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_data (auto_xbar_anon_in_a_bits_data_0), // @[ClockDomain.scala:14:9] .auto_anon_in_a_bits_corrupt (auto_xbar_anon_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9] .auto_anon_in_d_ready (auto_xbar_anon_in_d_ready_0), // @[ClockDomain.scala:14:9] .auto_anon_in_d_valid (auto_xbar_anon_in_d_valid_0), .auto_anon_in_d_bits_opcode (auto_xbar_anon_in_d_bits_opcode_0), .auto_anon_in_d_bits_size (auto_xbar_anon_in_d_bits_size_0), .auto_anon_in_d_bits_source (auto_xbar_anon_in_d_bits_source_0), .auto_anon_in_d_bits_data (auto_xbar_anon_in_d_bits_data_0), .auto_anon_out_1_a_valid (_xbar_auto_anon_out_1_a_valid), .auto_anon_out_1_a_bits_opcode (_xbar_auto_anon_out_1_a_bits_opcode), .auto_anon_out_1_a_bits_param (_xbar_auto_anon_out_1_a_bits_param), .auto_anon_out_1_a_bits_size (_xbar_auto_anon_out_1_a_bits_size), .auto_anon_out_1_a_bits_source (_xbar_auto_anon_out_1_a_bits_source), .auto_anon_out_1_a_bits_address (_xbar_auto_anon_out_1_a_bits_address), .auto_anon_out_1_a_bits_mask (_xbar_auto_anon_out_1_a_bits_mask), .auto_anon_out_1_a_bits_data (_xbar_auto_anon_out_1_a_bits_data), .auto_anon_out_1_a_bits_corrupt (_xbar_auto_anon_out_1_a_bits_corrupt), .auto_anon_out_1_d_ready (_xbar_auto_anon_out_1_d_ready), .auto_anon_out_0_a_ready (_fragmenter_auto_anon_in_a_ready), // @[Fragmenter.scala:345:34] .auto_anon_out_0_a_valid (_xbar_auto_anon_out_0_a_valid), .auto_anon_out_0_a_bits_opcode (_xbar_auto_anon_out_0_a_bits_opcode), .auto_anon_out_0_a_bits_param (_xbar_auto_anon_out_0_a_bits_param), .auto_anon_out_0_a_bits_size (_xbar_auto_anon_out_0_a_bits_size), .auto_anon_out_0_a_bits_source (_xbar_auto_anon_out_0_a_bits_source), .auto_anon_out_0_a_bits_address (_xbar_auto_anon_out_0_a_bits_address), .auto_anon_out_0_a_bits_mask (_xbar_auto_anon_out_0_a_bits_mask), .auto_anon_out_0_a_bits_data (_xbar_auto_anon_out_0_a_bits_data), .auto_anon_out_0_a_bits_corrupt (_xbar_auto_anon_out_0_a_bits_corrupt), .auto_anon_out_0_d_ready (_xbar_auto_anon_out_0_d_ready), .auto_anon_out_0_d_valid (_fragmenter_auto_anon_in_d_valid), // @[Fragmenter.scala:345:34] .auto_anon_out_0_d_bits_opcode (_fragmenter_auto_anon_in_d_bits_opcode), // @[Fragmenter.scala:345:34] .auto_anon_out_0_d_bits_size (_fragmenter_auto_anon_in_d_bits_size), // @[Fragmenter.scala:345:34] .auto_anon_out_0_d_bits_source (_fragmenter_auto_anon_in_d_bits_source), // @[Fragmenter.scala:345:34] .auto_anon_out_0_d_bits_data (_fragmenter_auto_anon_in_d_bits_data) // @[Fragmenter.scala:345:34] ); // @[Xbar.scala:346:26] ClockGroupResetSynchronizer resetSynchronizer ( // @[ResetSynchronizer.scala:46:69] .auto_in_member_allClocks_uncore_clock (_clock_gater_auto_clock_gater_out_member_allClocks_uncore_clock), // @[HasChipyardPRCI.scala:73:33] .auto_in_member_allClocks_uncore_reset (_clock_gater_auto_clock_gater_out_member_allClocks_uncore_reset), // @[HasChipyardPRCI.scala:73:33] .auto_out_member_allClocks_uncore_clock (auto_resetSynchronizer_out_member_allClocks_uncore_clock_0), .auto_out_member_allClocks_uncore_reset (auto_resetSynchronizer_out_member_allClocks_uncore_reset_0) ); // @[ResetSynchronizer.scala:46:69] TileClockGater clock_gater ( // @[HasChipyardPRCI.scala:73:33] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_clock_gater_in_1_a_ready (_clock_gater_auto_clock_gater_in_1_a_ready), .auto_clock_gater_in_1_a_valid (_fragmenter_auto_anon_out_a_valid), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_param (_fragmenter_auto_anon_out_a_bits_param), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_size (_fragmenter_auto_anon_out_a_bits_size), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_source (_fragmenter_auto_anon_out_a_bits_source), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_address (_fragmenter_auto_anon_out_a_bits_address), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_data (_fragmenter_auto_anon_out_a_bits_data), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_d_ready (_fragmenter_auto_anon_out_d_ready), // @[Fragmenter.scala:345:34] .auto_clock_gater_in_1_d_valid (_clock_gater_auto_clock_gater_in_1_d_valid), .auto_clock_gater_in_1_d_bits_opcode (_clock_gater_auto_clock_gater_in_1_d_bits_opcode), .auto_clock_gater_in_1_d_bits_size (_clock_gater_auto_clock_gater_in_1_d_bits_size), .auto_clock_gater_in_1_d_bits_source (_clock_gater_auto_clock_gater_in_1_d_bits_source), .auto_clock_gater_in_1_d_bits_data (_clock_gater_auto_clock_gater_in_1_d_bits_data), .auto_clock_gater_in_0_member_allClocks_uncore_clock (_reset_setter_auto_clock_out_member_allClocks_uncore_clock), // @[HasChipyardPRCI.scala:78:34] .auto_clock_gater_in_0_member_allClocks_uncore_reset (_reset_setter_auto_clock_out_member_allClocks_uncore_reset), // @[HasChipyardPRCI.scala:78:34] .auto_clock_gater_out_member_allClocks_uncore_clock (_clock_gater_auto_clock_gater_out_member_allClocks_uncore_clock), .auto_clock_gater_out_member_allClocks_uncore_reset (_clock_gater_auto_clock_gater_out_member_allClocks_uncore_reset) ); // @[HasChipyardPRCI.scala:73:33] TLFragmenter_TileClockGater fragmenter ( // @[Fragmenter.scala:345:34] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_a_ready (_fragmenter_auto_anon_in_a_ready), .auto_anon_in_a_valid (_xbar_auto_anon_out_0_a_valid), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_opcode (_xbar_auto_anon_out_0_a_bits_opcode), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_param (_xbar_auto_anon_out_0_a_bits_param), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_size (_xbar_auto_anon_out_0_a_bits_size), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_source (_xbar_auto_anon_out_0_a_bits_source), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_address (_xbar_auto_anon_out_0_a_bits_address), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_mask (_xbar_auto_anon_out_0_a_bits_mask), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_data (_xbar_auto_anon_out_0_a_bits_data), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_corrupt (_xbar_auto_anon_out_0_a_bits_corrupt), // @[Xbar.scala:346:26] .auto_anon_in_d_ready (_xbar_auto_anon_out_0_d_ready), // @[Xbar.scala:346:26] .auto_anon_in_d_valid (_fragmenter_auto_anon_in_d_valid), .auto_anon_in_d_bits_opcode (_fragmenter_auto_anon_in_d_bits_opcode), .auto_anon_in_d_bits_size (_fragmenter_auto_anon_in_d_bits_size), .auto_anon_in_d_bits_source (_fragmenter_auto_anon_in_d_bits_source), .auto_anon_in_d_bits_data (_fragmenter_auto_anon_in_d_bits_data), .auto_anon_out_a_ready (_clock_gater_auto_clock_gater_in_1_a_ready), // @[HasChipyardPRCI.scala:73:33] .auto_anon_out_a_valid (_fragmenter_auto_anon_out_a_valid), .auto_anon_out_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (_fragmenter_auto_anon_out_a_bits_param), .auto_anon_out_a_bits_size (_fragmenter_auto_anon_out_a_bits_size), .auto_anon_out_a_bits_source (_fragmenter_auto_anon_out_a_bits_source), .auto_anon_out_a_bits_address (_fragmenter_auto_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (_fragmenter_auto_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (_fragmenter_auto_anon_out_d_ready), .auto_anon_out_d_valid (_clock_gater_auto_clock_gater_in_1_d_valid), // @[HasChipyardPRCI.scala:73:33] .auto_anon_out_d_bits_opcode (_clock_gater_auto_clock_gater_in_1_d_bits_opcode), // @[HasChipyardPRCI.scala:73:33] .auto_anon_out_d_bits_size (_clock_gater_auto_clock_gater_in_1_d_bits_size), // @[HasChipyardPRCI.scala:73:33] .auto_anon_out_d_bits_source (_clock_gater_auto_clock_gater_in_1_d_bits_source), // @[HasChipyardPRCI.scala:73:33] .auto_anon_out_d_bits_data (_clock_gater_auto_clock_gater_in_1_d_bits_data) // @[HasChipyardPRCI.scala:73:33] ); // @[Fragmenter.scala:345:34] TileResetSetter reset_setter ( // @[HasChipyardPRCI.scala:78:34] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_clock_in_member_allClocks_uncore_clock (auto_reset_setter_clock_in_member_allClocks_uncore_clock_0), // @[ClockDomain.scala:14:9] .auto_clock_in_member_allClocks_uncore_reset (auto_reset_setter_clock_in_member_allClocks_uncore_reset_0), // @[ClockDomain.scala:14:9] .auto_clock_out_member_allClocks_uncore_clock (_reset_setter_auto_clock_out_member_allClocks_uncore_clock), .auto_clock_out_member_allClocks_uncore_reset (_reset_setter_auto_clock_out_member_allClocks_uncore_reset), .auto_tl_in_a_valid (_fragmenter_1_auto_anon_out_a_valid), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_opcode (_fragmenter_1_auto_anon_out_a_bits_opcode), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_param (_fragmenter_1_auto_anon_out_a_bits_param), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_size (_fragmenter_1_auto_anon_out_a_bits_size), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_source (_fragmenter_1_auto_anon_out_a_bits_source), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_address (_fragmenter_1_auto_anon_out_a_bits_address), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_mask (_fragmenter_1_auto_anon_out_a_bits_mask), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_data (_fragmenter_1_auto_anon_out_a_bits_data), // @[Fragmenter.scala:345:34] .auto_tl_in_a_bits_corrupt (_fragmenter_1_auto_anon_out_a_bits_corrupt), // @[Fragmenter.scala:345:34] .auto_tl_in_d_ready (_fragmenter_1_auto_anon_out_d_ready) // @[Fragmenter.scala:345:34] ); // @[HasChipyardPRCI.scala:78:34] TLFragmenter_TileResetSetter fragmenter_1 ( // @[Fragmenter.scala:345:34] .clock (childClock), // @[LazyModuleImp.scala:155:31] .reset (childReset), // @[LazyModuleImp.scala:158:31] .auto_anon_in_a_valid (_xbar_auto_anon_out_1_a_valid), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_opcode (_xbar_auto_anon_out_1_a_bits_opcode), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_param (_xbar_auto_anon_out_1_a_bits_param), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_size (_xbar_auto_anon_out_1_a_bits_size), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_source (_xbar_auto_anon_out_1_a_bits_source), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_address (_xbar_auto_anon_out_1_a_bits_address), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_mask (_xbar_auto_anon_out_1_a_bits_mask), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_data (_xbar_auto_anon_out_1_a_bits_data), // @[Xbar.scala:346:26] .auto_anon_in_a_bits_corrupt (_xbar_auto_anon_out_1_a_bits_corrupt), // @[Xbar.scala:346:26] .auto_anon_in_d_ready (_xbar_auto_anon_out_1_d_ready), // @[Xbar.scala:346:26] .auto_anon_out_a_valid (_fragmenter_1_auto_anon_out_a_valid), .auto_anon_out_a_bits_opcode (_fragmenter_1_auto_anon_out_a_bits_opcode), .auto_anon_out_a_bits_param (_fragmenter_1_auto_anon_out_a_bits_param), .auto_anon_out_a_bits_size (_fragmenter_1_auto_anon_out_a_bits_size), .auto_anon_out_a_bits_source (_fragmenter_1_auto_anon_out_a_bits_source), .auto_anon_out_a_bits_address (_fragmenter_1_auto_anon_out_a_bits_address), .auto_anon_out_a_bits_mask (_fragmenter_1_auto_anon_out_a_bits_mask), .auto_anon_out_a_bits_data (_fragmenter_1_auto_anon_out_a_bits_data), .auto_anon_out_a_bits_corrupt (_fragmenter_1_auto_anon_out_a_bits_corrupt), .auto_anon_out_d_ready (_fragmenter_1_auto_anon_out_d_ready) ); // @[Fragmenter.scala:345:34] assign auto_resetSynchronizer_out_member_allClocks_uncore_clock = auto_resetSynchronizer_out_member_allClocks_uncore_clock_0; // @[ClockDomain.scala:14:9] assign auto_resetSynchronizer_out_member_allClocks_uncore_reset = auto_resetSynchronizer_out_member_allClocks_uncore_reset_0; // @[ClockDomain.scala:14:9] assign auto_xbar_anon_in_a_ready = auto_xbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9] assign auto_xbar_anon_in_d_valid = auto_xbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9] assign auto_xbar_anon_in_d_bits_opcode = auto_xbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9] assign auto_xbar_anon_in_d_bits_size = auto_xbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9] assign auto_xbar_anon_in_d_bits_source = auto_xbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9] assign auto_xbar_anon_in_d_bits_data = auto_xbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Rounding.scala: package saturn.exu import chisel3._ import chisel3.util._ object RoundingIncrement { def apply(vxrm: UInt, v_d: Bool, v_d1: Bool, v_d20: Option[UInt]): Bool = MuxLookup(vxrm(1,0), false.B)(Seq( (0.U -> (v_d1)), (1.U -> (v_d1 && (v_d20.map(_ =/= 0.U).getOrElse(false.B) \|\| v_d))), (2.U -> (false.B)), (3.U -> (!v_d && Cat(v_d1, v_d20.getOrElse(false.B)) =/= 0.U)) )) def apply(vxrm: UInt, bits: UInt): UInt = { val w = bits.getWidth val d = w - 1 require(w >= 2) apply(vxrm, bits(d), bits(d-1), if (w > 2) Some(bits(d-2,0)) else None) } } File IntegerPipe.scala: package saturn.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import freechips.rocketchip.rocket._ import freechips.rocketchip.util._ import freechips.rocketchip.tile._ import saturn.common._ import saturn.insns._ class AdderArray(dLenB: Int) extends Module { val io = IO(new Bundle { val in1 = Input(Vec(dLenB, UInt(8.W))) val in2 = Input(Vec(dLenB, UInt(8.W))) val incr = Input(Vec(dLenB, Bool())) val mask_carry = Input(UInt(dLenB.W)) val signed = Input(Bool()) val eew = Input(UInt(2.W)) val avg = Input(Bool()) val rm = Input(UInt(2.W)) val sub = Input(Bool()) val cmask = Input(Bool()) val out = Output(Vec(dLenB, UInt(8.W))) val carry = Output(Vec(dLenB, Bool())) }) val use_carry = VecInit.tabulate(4)({ eew => Fill(dLenB >> eew, ~(1.U((1 << eew).W))) })(io.eew) val carry_clear = Mux(io.avg, use_carry.asBools.map(Cat(~(0.U(8.W)), _)).asUInt, ~(0.U(73.W))) val carry_restore = Mux(io.avg, use_carry.asBools.map(Cat(0.U(8.W), _)).asUInt, 0.U(73.W)) val avg_in1 = VecInit.tabulate(4) { eew => VecInit(io.in1.asTypeOf(Vec(dLenB >> eew, UInt((8 << eew).W))).map(e => Cat(io.signed && e((8<<eew)-1), e) >> 1)).asUInt }(io.eew).asTypeOf(Vec(dLenB, UInt(8.W))) val avg_in2 = VecInit.tabulate(4) { eew => VecInit(io.in2.asTypeOf(Vec(dLenB >> eew, UInt((8 << eew).W))).map(e => Cat(io.signed && e((8<<eew)-1), e) >> 1)).asUInt }(io.eew).asTypeOf(Vec(dLenB, UInt(8.W))) val in1 = Mux(io.avg, avg_in1, io.in1) val in2 = Mux(io.avg, avg_in2, io.in2) for (i <- 0 until (dLenB >> 3)) { val h = (i+1)8-1 val l = i8 val io_in1_slice = io.in1.slice(l,h+1) val io_in2_slice = io.in2.slice(l,h+1) val in1_slice = in1.slice(l,h+1) val in2_slice = in2.slice(l,h+1) val use_carry_slice = use_carry(h,l).asBools val mask_carry_slice = io.mask_carry(h,l).asBools val incr_slice = io.incr.slice(l,h+1) val in1_dummy_bits = (io_in1_slice .zip(io_in2_slice) .zip(use_carry_slice) .zip(mask_carry_slice).map { case(((i1, i2), carry), mask_bit) => { val avg_bit = ((io.sub ^ i1(0)) & i2(0)) \| (((io.sub ^ i1(0)) ^ i2(0)) & io.sub) val bit = (!io.cmask & io.sub) \| (io.cmask & (io.sub ^ mask_bit)) Mux(carry, 1.U(1.W), Mux(io.avg, avg_bit, bit)) }}) val in2_dummy_bits = (io_in1_slice .zip(io_in2_slice) .zip(use_carry_slice) .zip(mask_carry_slice).map { case(((i1, i2), carry), mask_bit) => { val avg_bit = ((io.sub ^ i1(0)) & i2(0)) \| (((io.sub ^ i1(0)) ^ i2(0)) & io.sub) val bit = (!io.cmask & io.sub) \| (io.cmask & (io.sub ^ mask_bit)) Mux(carry, 0.U(1.W), Mux(io.avg, avg_bit, bit)) }}) val round_incrs = (io_in1_slice .zip(io_in2_slice) .zipWithIndex.map { case((l, r), i) => { val sum = r(1,0) +& ((l(1,0) ^ Fill(2, io.sub)) +& io.sub) Cat(0.U(7.W), Cat(Mux(io.avg, RoundingIncrement(io.rm, sum(1), sum(0), None) & !use_carry_slice(i), 0.U), 0.U(1.W))) }} .asUInt) val in1_constructed = in1_slice.zip(in1_dummy_bits).map { case(i1, dummy_bit) => (i1 ^ Fill(8, io.sub)) ## dummy_bit }.asUInt val in2_constructed = in2_slice.zip(in2_dummy_bits).map { case(i2, dummy_bit) => i2 ## dummy_bit }.asUInt val incr_constructed = incr_slice.zip(use_carry_slice).map { case(incr, masking) => Cat(0.U(7.W), Cat(Mux(!masking, incr, 0.U(1.W)), 0.U(1.W))) }.asUInt val sum = (((in1_constructed +& in2_constructed) & carry_clear) \| carry_restore) +& round_incrs +& incr_constructed for (j <- 0 until 8) { io.out((i8) + j) := sum(((j+1)9)-1, (j9) + 1) io.carry((i8) + j) := sum((j+1)9) } } } class CompareArray(dLenB: Int) extends Module { val io = IO(new Bundle { val in1 = Input(Vec(dLenB, UInt(8.W))) val in2 = Input(Vec(dLenB, UInt(8.W))) val eew = Input(UInt(2.W)) val signed = Input(Bool()) val less = Input(Bool()) val sle = Input(Bool()) val inv = Input(Bool()) val minmax = Output(UInt(dLenB.W)) val result = Output(UInt(dLenB.W)) }) val eq = io.in2.zip(io.in1).map { x => x._1 === x._2 } val lt = io.in2.zip(io.in1).map { x => x._1 < x._2 } val minmax_bits = Wire(Vec(4, UInt(dLenB.W))) val result_bits = Wire(Vec(4, UInt(dLenB.W))) io.minmax := minmax_bits(io.eew) io.result := result_bits(io.eew) for (eew <- 0 until 4) { val lts = lt.grouped(1 << eew) val eqs = eq.grouped(1 << eew) val bits = VecInit(lts.zip(eqs).zipWithIndex.map { case ((e_lts, e_eqs), i) => val eq = e_eqs.andR val in1_hi = io.in1((i+1)(1<<eew)-1)(7) val in2_hi = io.in2((i+1)(1<<eew)-1)(7) val hi_lt = Mux(io.signed, in2_hi & !in1_hi, !in2_hi & in1_hi) val hi_eq = in1_hi === in2_hi val lt = (e_lts :+ hi_lt).zip(e_eqs :+ hi_eq).foldLeft(false.B) { case (p, (l, e)) => l \|\| (e && p) } Mux(io.less, lt \|\| (io.sle && eq), io.inv ^ eq) }.toSeq).asUInt minmax_bits(eew) := FillInterleaved(1 << eew, bits) result_bits(eew) := Fill(1 << eew, bits) } } class SaturatedSumArray(dLenB: Int) extends Module { val dLen = dLenB 8 val io = IO(new Bundle { val sum = Input(Vec(dLenB, UInt(8.W))) val carry = Input(Vec(dLenB, Bool())) val in1_sign = Input(Vec(dLenB, Bool())) val in2_sign = Input(Vec(dLenB, Bool())) val sub = Input(Bool()) val eew = Input(UInt(2.W)) val signed = Input(Bool()) val set_vxsat = Output(UInt(dLenB.W)) val out = Output(Vec(dLenB, UInt(8.W))) }) val unsigned_mask = VecInit.tabulate(4)({ eew => FillInterleaved(1 << eew, VecInit.tabulate(dLenB >> eew)(i => io.sub ^ io.carry(((i+1) << eew)-1)).asUInt) })(io.eew) val unsigned_clip = Mux(io.sub, 0.U(dLen.W), ~(0.U(dLen.W))).asTypeOf(Vec(dLenB, UInt(8.W))) val (signed_masks, signed_clips): (Seq[UInt], Seq[UInt]) = Seq.tabulate(4)({ eew => val out_sign = VecInit.tabulate(dLenB >> eew)(i => io.sum(((i+1)<<eew)-1)(7)).asUInt val vs2_sign = VecInit.tabulate(dLenB >> eew)(i => io.in2_sign(((i+1)<<eew)-1) ).asUInt val vs1_sign = VecInit.tabulate(dLenB >> eew)(i => io.in1_sign(((i+1)<<eew)-1) ).asUInt val input_xor = vs2_sign ^ vs1_sign val may_clip = Mux(io.sub, input_xor, ~input_xor) // add clips when signs match, sub clips when signs mismatch val clip = (vs2_sign ^ out_sign) & may_clip // clips if the output sign doesn't match the input sign val clip_neg = Cat(1.U, 0.U(((8 << eew)-1).W)) val clip_pos = ~clip_neg val clip_value = VecInit(vs2_sign.asBools.map(sign => Mux(sign, clip_neg, clip_pos))).asUInt (FillInterleaved((1 << eew), clip), clip_value) }).unzip val signed_mask = VecInit(signed_masks)(io.eew) val signed_clip = VecInit(signed_clips)(io.eew).asTypeOf(Vec(dLenB, UInt(8.W))) val mask = Mux(io.signed, signed_mask, unsigned_mask) val clip = Mux(io.signed, signed_clip, unsigned_clip) io.out := io.sum.zipWithIndex.map { case (o,i) => Mux(mask(i), clip(i), o) } io.set_vxsat := mask } case object IntegerPipeFactory extends FunctionalUnitFactory { def insns = Seq( ADD.VV, ADD.VX, ADD.VI, SUB.VV, SUB.VX, RSUB.VX, RSUB.VI, WADDU.VV, WADDU.VX, WADD.VV, WADD.VX, WSUBU.VV, WSUBU.VX, WSUB.VV, WSUB.VX, WADDUW.VV, WADDUW.VX, WADDW.VV, WADDW.VX, WSUBUW.VV, WSUBUW.VX, WSUBW.VV, WSUBW.VX, ADC.VV, ADC.VX, ADC.VI, MADC.VV, MADC.VX, MADC.VI, SBC.VV, SBC.VX, MSBC.VV, MSBC.VX, NEXT.VV, MSEQ.VV, MSEQ.VX, MSEQ.VI, MSNE.VV, MSNE.VX, MSNE.VI, MSLTU.VV, MSLTU.VX, MSLT.VV, MSLT.VX, MSLEU.VV, MSLEU.VX, MSLEU.VI, MSLE.VV, MSLE.VX, MSLE.VI, MSGTU.VX, MSGTU.VI, MSGT.VX, MSGT.VI, MINU.VV, MINU.VX, MIN.VV, MIN.VX, MAXU.VV, MAXU.VX, MAX.VV, MAX.VX, MERGE.VV, MERGE.VX, MERGE.VI, SADDU.VV, SADDU.VX, SADDU.VI, SADD.VV, SADD.VX, SADD.VI, SSUBU.VV, SSUBU.VX, SSUB.VV, SSUB.VX, AADDU.VV, AADDU.VX, AADD.VV, AADD.VX, ASUBU.VV, ASUBU.VX, ASUB.VV, ASUB.VX, REDSUM.VV, WREDSUM.VV, WREDSUMU.VV, REDMINU.VV, REDMIN.VV, REDMAXU.VV, REDMAX.VV, FMERGE.VF, // zvbb BREV8.VV, BREV.VV, REV8.VV, CLZ.VV, CTZ.VV, CPOP.VV ) def generate(implicit p: Parameters) = new IntegerPipe()(p) } class IntegerPipe(implicit p: Parameters) extends PipelinedFunctionalUnit(1)(p) { val supported_insns = IntegerPipeFactory.insns val rvs1_eew = io.pipe(0).bits.rvs1_eew val rvs2_eew = io.pipe(0).bits.rvs2_eew val vd_eew = io.pipe(0).bits.vd_eew val ctrl = new VectorDecoder( io.pipe(0).bits.funct3, io.pipe(0).bits.funct6, io.pipe(0).bits.rs1, io.pipe(0).bits.rs2, supported_insns, Seq(UsesCmp, UsesNarrowingSext, UsesMinMax, UsesMerge, UsesSat, DoSub, WideningSext, Averaging, CarryIn, AlwaysCarryIn, CmpLess, Swap12, WritesAsMask, UsesBitSwap, UsesCountZeros)) io.iss.ready := new VectorDecoder(io.iss.op.funct3, io.iss.op.funct6, 0.U, 0.U, supported_insns, Nil).matched val carry_in = ctrl.bool(CarryIn) && (!io.pipe(0).bits.vm \|\| ctrl.bool(AlwaysCarryIn)) val sat_signed = io.pipe(0).bits.funct6(0) val sat_addu = io.pipe(0).bits.funct6(1,0) === 0.U val sat_subu = io.pipe(0).bits.funct6(1,0) === 2.U val rvs1_bytes = io.pipe(0).bits.rvs1_data.asTypeOf(Vec(dLenB, UInt(8.W))) val rvs2_bytes = io.pipe(0).bits.rvs2_data.asTypeOf(Vec(dLenB, UInt(8.W))) val in1_bytes = Mux(ctrl.bool(Swap12), rvs2_bytes, rvs1_bytes) val in2_bytes = Mux(ctrl.bool(Swap12), rvs1_bytes, rvs2_bytes) val narrow_vs1 = narrow2_expand(rvs1_bytes, rvs1_eew, (io.pipe(0).bits.eidx >> (dLenOffBits.U - vd_eew))(0), ctrl.bool(WideningSext)) val narrow_vs2 = narrow2_expand(rvs2_bytes, rvs2_eew, (io.pipe(0).bits.eidx >> (dLenOffBits.U - vd_eew))(0), ctrl.bool(WideningSext)) val add_mask_carry = VecInit.tabulate(4)({ eew => VecInit((0 until dLenB >> eew).map { i => io.pipe(0).bits.rmask(i) \| 0.U((1 << eew).W) }).asUInt })(rvs2_eew) val add_carry = Wire(Vec(dLenB, UInt(1.W))) val add_out = Wire(Vec(dLenB, UInt(8.W))) val merge_mask = VecInit.tabulate(4)({eew => FillInterleaved(1 << eew, io.pipe(0).bits.rmask((dLenB >> eew)-1,0))})(rvs2_eew) val merge_out = VecInit((0 until dLenB).map { i => Mux(merge_mask(i), rvs1_bytes(i), rvs2_bytes(i)) }).asUInt val carryborrow_res = VecInit.tabulate(4)({ eew => Fill(1 << eew, VecInit(add_carry.grouped(1 << eew).map(_.last).toSeq).asUInt) })(rvs1_eew) val adder_arr = Module(new AdderArray(dLenB)) adder_arr.io.in1 := Mux(rvs1_eew < vd_eew, narrow_vs1, in1_bytes) adder_arr.io.in2 := Mux(rvs2_eew < vd_eew, narrow_vs2, in2_bytes) adder_arr.io.incr.foreach(_ := false.B) adder_arr.io.avg := ctrl.bool(Averaging) adder_arr.io.eew := vd_eew adder_arr.io.rm := io.pipe(0).bits.vxrm adder_arr.io.mask_carry := add_mask_carry adder_arr.io.sub := ctrl.bool(DoSub) adder_arr.io.cmask := carry_in adder_arr.io.signed := io.pipe(0).bits.funct6(0) add_out := adder_arr.io.out add_carry := adder_arr.io.carry val cmp_arr = Module(new CompareArray(dLenB)) cmp_arr.io.in1 := in1_bytes cmp_arr.io.in2 := in2_bytes cmp_arr.io.eew := rvs1_eew cmp_arr.io.signed := io.pipe(0).bits.funct6(0) cmp_arr.io.less := ctrl.bool(CmpLess) cmp_arr.io.sle := io.pipe(0).bits.funct6(2,1) === 2.U cmp_arr.io.inv := io.pipe(0).bits.funct6(0) val minmax_out = VecInit(rvs1_bytes.zip(rvs2_bytes).zip(cmp_arr.io.minmax.asBools).map { case ((v1, v2), s) => Mux(s, v2, v1) }).asUInt val mask_out = Fill(8, Mux(ctrl.bool(UsesCmp), cmp_arr.io.result, carryborrow_res ^ Fill(dLenB, ctrl.bool(DoSub)))) val sat_arr = Module(new SaturatedSumArray(dLenB)) sat_arr.io.sum := add_out sat_arr.io.carry := add_carry sat_arr.io.in1_sign := rvs1_bytes.map(_(7)) sat_arr.io.in2_sign := rvs2_bytes.map(_(7)) sat_arr.io.sub := ctrl.bool(DoSub) sat_arr.io.eew := vd_eew sat_arr.io.signed := io.pipe(0).bits.funct6(0) val sat_out = sat_arr.io.out.asUInt val narrowing_ext_eew_mul = io.pipe(0).bits.vd_eew - rvs2_eew val narrowing_ext_in = (1 until 4).map { m => val w = dLen >> m val in = Wire(UInt(w.W)) val in_mul = io.pipe(0).bits.rvs2_data.asTypeOf(Vec(1 << m, UInt(w.W))) val sel = (io.pipe(0).bits.eidx >> (dLenOffBits.U - vd_eew))(m-1,0) in := in_mul(sel) in } val narrowing_ext_out = Mux1H((1 until 4).map { eew => (0 until eew).map { vs2_eew => (vd_eew === eew.U && rvs2_eew === vs2_eew.U) -> { val mul = eew - vs2_eew val in = narrowing_ext_in(mul-1).asTypeOf(Vec(dLenB >> eew, UInt((8 << vs2_eew).W))) val out = Wire(Vec(dLenB >> eew, UInt((8 << eew).W))) out.zip(in).foreach { case (l, r) => l := Cat( Fill((8 << eew) - (8 << vs2_eew), io.pipe(0).bits.rs1(0) && r((8 << vs2_eew)-1)), r) } out.asUInt } }}.flatten) val brev_bytes = VecInit(in2_bytes.map(b => Reverse(b))).asUInt val brev_elements = VecInit((0 until 4).map { eew => VecInit(in2_bytes.asTypeOf(Vec(dLenB >> eew, UInt((8 << eew).W))).map(b => Reverse(b))).asUInt })(vd_eew) val rev8_elements = VecInit((0 until 4).map { eew => VecInit(in2_bytes.asTypeOf(Vec(dLenB >> eew, Vec(1 << eew, UInt(8.W)))).map(b => VecInit(b.reverse))).asUInt })(vd_eew) val swap_out = Mux1H(Seq( (io.pipe(0).bits.rs1(1,0) === 0.U) -> brev_bytes, (io.pipe(0).bits.rs1(1,0) === 1.U) -> rev8_elements, (io.pipe(0).bits.rs1(1,0) === 2.U) -> brev_elements )) val tz_in = Mux(io.pipe(0).bits.rs1(0), in2_bytes, brev_elements.asTypeOf(Vec(dLenB, UInt(8.W)))) val tz_8b = tz_in.map(b => (b === 0.U, (PriorityEncoderOH(1.U ## b) - 1.U)(7,0))) val tz_16b = tz_8b.grouped(2).toSeq.map(t => (t.map(_._1).andR, Mux(t(0)._1, t(1)._2 ## ~(0.U(8.W)), t(0)._2)) ) val tz_32b = tz_16b.grouped(2).toSeq.map(t => (t.map(_._1).andR, Mux(t(0)._1, t(1)._2 ## ~(0.U(16.W)), t(0)._2)) ) val tz_64b = tz_32b.grouped(2).toSeq.map(t => (t.map(_._1).andR, Mux(t(0)._1, t(1)._2 ## ~(0.U(32.W)), t(0)._2)) ) val tz_out = WireInit(VecInit( VecInit(tz_8b.map(_._2)).asUInt, VecInit(tz_16b.map(_._2)).asUInt, VecInit(tz_32b.map(_._2)).asUInt, VecInit(tz_64b.map(_._2)).asUInt )(vd_eew).asTypeOf(Vec(dLenB, UInt(8.W)))) val cpop_in = Mux(io.pipe(0).bits.rs1(1), in2_bytes, tz_out) val cpop_8b = cpop_in.map(b => PopCount(b)) val cpop_16b = cpop_8b.grouped(2).toSeq.map(_.reduce(_ +& _)) val cpop_32b = cpop_16b.grouped(2).toSeq.map(_.reduce(_ +& _)) val cpop_64b = cpop_32b.grouped(2).toSeq.map(_.reduce(_ +& _)) val cpops = Seq(cpop_8b, cpop_16b, cpop_32b, cpop_64b) val count_out = WireInit(VecInit((0 until 4).map { eew => val out = Wire(Vec(dLenB >> eew, UInt((8 << eew).W))) out := VecInit(cpops(eew)) out.asUInt })(vd_eew)) val outs = Seq( (ctrl.bool(UsesNarrowingSext) , narrowing_ext_out), (ctrl.bool(WritesAsMask) , mask_out), (ctrl.bool(UsesMinMax) , minmax_out), (ctrl.bool(UsesMerge) , merge_out), (ctrl.bool(UsesSat) , sat_out), (ctrl.bool(UsesBitSwap) , swap_out), (ctrl.bool(UsesCountZeros) , count_out) ) val out = Mux(outs.map(_._1).orR, Mux1H(outs), add_out.asUInt) val mask_write_offset = VecInit.tabulate(4)({ eew => Cat(io.pipe(0).bits.eidx(log2Ceil(dLen)-1, dLenOffBits-eew), 0.U((dLenOffBits-eew).W)) })(rvs1_eew) val mask_write_mask = (VecInit.tabulate(4)({ eew => VecInit(io.pipe(0).bits.wmask.asBools.grouped(1 << eew).map(_.head).toSeq).asUInt })(rvs1_eew) << mask_write_offset)(dLen-1,0) io.pipe0_stall := false.B io.write.valid := io.pipe(0).valid io.write.bits.eg := io.pipe(0).bits.wvd_eg io.write.bits.mask := Mux(ctrl.bool(WritesAsMask), mask_write_mask, FillInterleaved(8, io.pipe(0).bits.wmask)) io.write.bits.data := out val sat_vxsat = Mux(ctrl.bool(UsesSat) , sat_arr.io.set_vxsat , 0.U) & io.pipe(0).bits.wmask io.set_vxsat := io.pipe(0).valid && (sat_vxsat =/= 0.U) io.set_fflags.valid := false.B io.set_fflags.bits := DontCare io.scalar_write.valid := false.B io.scalar_write.bits := DontCare }	module AdderArray( // @[IntegerPipe.scala:12:7] input [7:0] io_in1_0, // @[IntegerPipe.scala:13:14] input [7:0] io_in1_1, // @[IntegerPipe.scala:13:14] input [7:0] io_in1_2, // @[IntegerPipe.scala:13:14] input [7:0] io_in1_3, // @[IntegerPipe.scala:13:14] input [7:0] io_in1_4, // @[IntegerPipe.scala:13:14] input [7:0] io_in1_5, // @[IntegerPipe.scala:13:14] input [7:0] io_in1_6, // @[IntegerPipe.scala:13:14] input [7:0] io_in1_7, // @[IntegerPipe.scala:13:14] input [7:0] io_in1_8, // @[IntegerPipe.scala:13:14] input [7:0] io_in1_9, // @[IntegerPipe.scala:13:14] input [7:0] io_in1_10, // @[IntegerPipe.scala:13:14] input [7:0] io_in1_11, // @[IntegerPipe.scala:13:14] input [7:0] io_in1_12, // @[IntegerPipe.scala:13:14] input [7:0] io_in1_13, // @[IntegerPipe.scala:13:14] input [7:0] io_in1_14, // @[IntegerPipe.scala:13:14] input [7:0] io_in1_15, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_0, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_1, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_2, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_3, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_4, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_5, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_6, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_7, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_8, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_9, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_10, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_11, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_12, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_13, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_14, // @[IntegerPipe.scala:13:14] input [7:0] io_in2_15, // @[IntegerPipe.scala:13:14] input io_incr_0, // @[IntegerPipe.scala:13:14] input io_incr_1, // @[IntegerPipe.scala:13:14] input io_incr_2, // @[IntegerPipe.scala:13:14] input io_incr_3, // @[IntegerPipe.scala:13:14] input io_incr_4, // @[IntegerPipe.scala:13:14] input io_incr_5, // @[IntegerPipe.scala:13:14] input io_incr_6, // @[IntegerPipe.scala:13:14] input io_incr_7, // @[IntegerPipe.scala:13:14] input io_incr_8, // @[IntegerPipe.scala:13:14] input io_incr_9, // @[IntegerPipe.scala:13:14] input io_incr_10, // @[IntegerPipe.scala:13:14] input io_incr_11, // @[IntegerPipe.scala:13:14] input io_incr_12, // @[IntegerPipe.scala:13:14] input io_incr_13, // @[IntegerPipe.scala:13:14] input io_incr_14, // @[IntegerPipe.scala:13:14] input io_incr_15, // @[IntegerPipe.scala:13:14] input [15:0] io_mask_carry, // @[IntegerPipe.scala:13:14] input io_signed, // @[IntegerPipe.scala:13:14] input [1:0] io_eew, // @[IntegerPipe.scala:13:14] input io_avg, // @[IntegerPipe.scala:13:14] input [1:0] io_rm, // @[IntegerPipe.scala:13:14] input io_sub, // @[IntegerPipe.scala:13:14] input io_cmask, // @[IntegerPipe.scala:13:14] output [7:0] io_out_0, // @[IntegerPipe.scala:13:14] output [7:0] io_out_1, // @[IntegerPipe.scala:13:14] output [7:0] io_out_2, // @[IntegerPipe.scala:13:14] output [7:0] io_out_3, // @[IntegerPipe.scala:13:14] output [7:0] io_out_4, // @[IntegerPipe.scala:13:14] output [7:0] io_out_5, // @[IntegerPipe.scala:13:14] output [7:0] io_out_6, // @[IntegerPipe.scala:13:14] output [7:0] io_out_7, // @[IntegerPipe.scala:13:14] output [7:0] io_out_8, // @[IntegerPipe.scala:13:14] output [7:0] io_out_9, // @[IntegerPipe.scala:13:14] output [7:0] io_out_10, // @[IntegerPipe.scala:13:14] output [7:0] io_out_11, // @[IntegerPipe.scala:13:14] output [7:0] io_out_12, // @[IntegerPipe.scala:13:14] output [7:0] io_out_13, // @[IntegerPipe.scala:13:14] output [7:0] io_out_14, // @[IntegerPipe.scala:13:14] output [7:0] io_out_15, // @[IntegerPipe.scala:13:14] output io_carry_0, // @[IntegerPipe.scala:13:14] output io_carry_1, // @[IntegerPipe.scala:13:14] output io_carry_2, // @[IntegerPipe.scala:13:14] output io_carry_3, // @[IntegerPipe.scala:13:14] output io_carry_4, // @[IntegerPipe.scala:13:14] output io_carry_5, // @[IntegerPipe.scala:13:14] output io_carry_6, // @[IntegerPipe.scala:13:14] output io_carry_7, // @[IntegerPipe.scala:13:14] output io_carry_8, // @[IntegerPipe.scala:13:14] output io_carry_9, // @[IntegerPipe.scala:13:14] output io_carry_10, // @[IntegerPipe.scala:13:14] output io_carry_11, // @[IntegerPipe.scala:13:14] output io_carry_12, // @[IntegerPipe.scala:13:14] output io_carry_13, // @[IntegerPipe.scala:13:14] output io_carry_14, // @[IntegerPipe.scala:13:14] output io_carry_15 // @[IntegerPipe.scala:13:14] ); wire [3:0][15:0] _GEN = '{16'hFEFE, 16'hEEEE, 16'hAAAA, 16'h0}; // @[IntegerPipe.scala:33:43] wire [72:0] carry_clear = io_avg ? {_GEN[io_eew][8], 8'hFF, _GEN[io_eew][7], 8'hFF, _GEN[io_eew][6], 8'hFF, _GEN[io_eew][5], 8'hFF, _GEN[io_eew][4], 8'hFF, _GEN[io_eew][3], 8'hFF, _GEN[io_eew][2], 8'hFF, _GEN[io_eew][1], 8'hFF, _GEN[io_eew][0]} : 73'h1FFFFFFFFFFFFFFFFFF; // @[IntegerPipe.scala:33:{24,43}] wire [72:0] carry_restore = io_avg ? {_GEN[io_eew][8], 8'h0, _GEN[io_eew][7], 8'h0, _GEN[io_eew][6], 8'h0, _GEN[io_eew][5], 8'h0, _GEN[io_eew][4], 8'h0, _GEN[io_eew][3], 8'h0, _GEN[io_eew][2], 8'h0, _GEN[io_eew][1], 8'h0, _GEN[io_eew][0]} : 73'h0; // @[IntegerPipe.scala:33:43, :34:26] wire [3:0][127:0] _GEN_0 = {{{io_signed & io_in1_15[7], io_in1_15, io_in1_14, io_in1_13, io_in1_12, io_in1_11, io_in1_10, io_in1_9, io_in1_8[7:1], io_signed & io_in1_7[7], io_in1_7, io_in1_6, io_in1_5, io_in1_4, io_in1_3, io_in1_2, io_in1_1, io_in1_0[7:1]}}, {{io_signed & io_in1_15[7], io_in1_15, io_in1_14, io_in1_13, io_in1_12[7:1], io_signed & io_in1_11[7], io_in1_11, io_in1_10, io_in1_9, io_in1_8[7:1], io_signed & io_in1_7[7], io_in1_7, io_in1_6, io_in1_5, io_in1_4[7:1], io_signed & io_in1_3[7], io_in1_3, io_in1_2, io_in1_1, io_in1_0[7:1]}}, {{io_signed & io_in1_15[7], io_in1_15, io_in1_14[7:1], io_signed & io_in1_13[7], io_in1_13, io_in1_12[7:1], io_signed & io_in1_11[7], io_in1_11, io_in1_10[7:1], io_signed & io_in1_9[7], io_in1_9, io_in1_8[7:1], io_signed & io_in1_7[7], io_in1_7, io_in1_6[7:1], io_signed & io_in1_5[7], io_in1_5, io_in1_4[7:1], io_signed & io_in1_3[7], io_in1_3, io_in1_2[7:1], io_signed & io_in1_1[7], io_in1_1, io_in1_0[7:1]}}, {{io_signed & io_in1_15[7], io_in1_15[7:1], io_signed & io_in1_14[7], io_in1_14[7:1], io_signed & io_in1_13[7], io_in1_13[7:1], io_signed & io_in1_12[7], io_in1_12[7:1], io_signed & io_in1_11[7], io_in1_11[7:1], io_signed & io_in1_10[7], io_in1_10[7:1], io_signed & io_in1_9[7], io_in1_9[7:1], io_signed & io_in1_8[7], io_in1_8[7:1], io_signed & io_in1_7[7], io_in1_7[7:1], io_signed & io_in1_6[7], io_in1_6[7:1], io_signed & io_in1_5[7], io_in1_5[7:1], io_signed & io_in1_4[7], io_in1_4[7:1], io_signed & io_in1_3[7], io_in1_3[7:1], io_signed & io_in1_2[7], io_in1_2[7:1], io_signed & io_in1_1[7], io_in1_1[7:1], io_signed & io_in1_0[7], io_in1_0[7:1]}}}; // @[IntegerPipe.scala:37:{91,95,112,119}, :38:21] wire [3:0][127:0] _GEN_1 = {{{io_signed & io_in2_15[7], io_in2_15, io_in2_14, io_in2_13, io_in2_12, io_in2_11, io_in2_10, io_in2_9, io_in2_8[7:1], io_signed & io_in2_7[7], io_in2_7, io_in2_6, io_in2_5, io_in2_4, io_in2_3, io_in2_2, io_in2_1, io_in2_0[7:1]}}, {{io_signed & io_in2_15[7], io_in2_15, io_in2_14, io_in2_13, io_in2_12[7:1], io_signed & io_in2_11[7], io_in2_11, io_in2_10, io_in2_9, io_in2_8[7:1], io_signed & io_in2_7[7], io_in2_7, io_in2_6, io_in2_5, io_in2_4[7:1], io_signed & io_in2_3[7], io_in2_3, io_in2_2, io_in2_1, io_in2_0[7:1]}}, {{io_signed & io_in2_15[7], io_in2_15, io_in2_14[7:1], io_signed & io_in2_13[7], io_in2_13, io_in2_12[7:1], io_signed & io_in2_11[7], io_in2_11, io_in2_10[7:1], io_signed & io_in2_9[7], io_in2_9, io_in2_8[7:1], io_signed & io_in2_7[7], io_in2_7, io_in2_6[7:1], io_signed & io_in2_5[7], io_in2_5, io_in2_4[7:1], io_signed & io_in2_3[7], io_in2_3, io_in2_2[7:1], io_signed & io_in2_1[7], io_in2_1, io_in2_0[7:1]}}, {{io_signed & io_in2_15[7], io_in2_15[7:1], io_signed & io_in2_14[7], io_in2_14[7:1], io_signed & io_in2_13[7], io_in2_13[7:1], io_signed & io_in2_12[7], io_in2_12[7:1], io_signed & io_in2_11[7], io_in2_11[7:1], io_signed & io_in2_10[7], io_in2_10[7:1], io_signed & io_in2_9[7], io_in2_9[7:1], io_signed & io_in2_8[7], io_in2_8[7:1], io_signed & io_in2_7[7], io_in2_7[7:1], io_signed & io_in2_6[7], io_in2_6[7:1], io_signed & io_in2_5[7], io_in2_5[7:1], io_signed & io_in2_4[7], io_in2_4[7:1], io_signed & io_in2_3[7], io_in2_3[7:1], io_signed & io_in2_2[7], io_in2_2[7:1], io_signed & io_in2_1[7], io_in2_1[7:1], io_signed & io_in2_0[7], io_in2_0[7:1]}}}; // @[IntegerPipe.scala:40:{91,95,112,119}, :41:21] wire _in2_dummy_bits_bit_T_2 = io_sub ^ io_mask_carry[0]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire _in2_dummy_bits_bit_T_6 = io_sub ^ io_mask_carry[1]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire _in2_dummy_bits_bit_T_10 = io_sub ^ io_mask_carry[2]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire _in2_dummy_bits_bit_T_14 = io_sub ^ io_mask_carry[3]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire _in2_dummy_bits_bit_T_18 = io_sub ^ io_mask_carry[4]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire _in2_dummy_bits_bit_T_22 = io_sub ^ io_mask_carry[5]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire _in2_dummy_bits_bit_T_26 = io_sub ^ io_mask_carry[6]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire _in2_dummy_bits_bit_T_30 = io_sub ^ io_mask_carry[7]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire [1:0] _round_incrs_sum_T_77 = {2{io_sub}}; // @[IntegerPipe.scala:76:44] wire [1:0] _GEN_2 = {1'h0, io_sub}; // @[IntegerPipe.scala:76:57] wire [1:0] round_incrs_sum = io_in2_0[1:0] + (io_in1_0[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire _GEN_3 = io_rm != 2'h2; // @[Rounding.scala:8:106] wire [1:0] round_incrs_sum_1 = io_in2_1[1:0] + (io_in1_1[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire [1:0] round_incrs_sum_2 = io_in2_2[1:0] + (io_in1_2[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire [1:0] round_incrs_sum_3 = io_in2_3[1:0] + (io_in1_3[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire [1:0] round_incrs_sum_4 = io_in2_4[1:0] + (io_in1_4[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire [1:0] round_incrs_sum_5 = io_in2_5[1:0] + (io_in1_5[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire [1:0] round_incrs_sum_6 = io_in2_6[1:0] + (io_in1_6[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire [1:0] round_incrs_sum_7 = io_in2_7[1:0] + (io_in1_7[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire [7:0] _in1_constructed_T_45 = {8{io_sub}}; // @[IntegerPipe.scala:82:96] wire [72:0] _sum_T = {1'h0, (io_avg ? _GEN_0[io_eew][63:56] : io_in1_7) ^ _in1_constructed_T_45, _GEN[io_eew][7] \| (io_avg ? (io_sub ^ io_in1_7[0]) & io_in2_7[0] \| (io_sub ^ io_in1_7[0] ^ io_in2_7[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_30), (io_avg ? _GEN_0[io_eew][55:48] : io_in1_6) ^ _in1_constructed_T_45, _GEN[io_eew][6] \| (io_avg ? (io_sub ^ io_in1_6[0]) & io_in2_6[0] \| (io_sub ^ io_in1_6[0] ^ io_in2_6[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_26), (io_avg ? _GEN_0[io_eew][47:40] : io_in1_5) ^ _in1_constructed_T_45, _GEN[io_eew][5] \| (io_avg ? (io_sub ^ io_in1_5[0]) & io_in2_5[0] \| (io_sub ^ io_in1_5[0] ^ io_in2_5[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_22), (io_avg ? _GEN_0[io_eew][39:32] : io_in1_4) ^ _in1_constructed_T_45, _GEN[io_eew][4] \| (io_avg ? (io_sub ^ io_in1_4[0]) & io_in2_4[0] \| (io_sub ^ io_in1_4[0] ^ io_in2_4[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_18), (io_avg ? _GEN_0[io_eew][31:24] : io_in1_3) ^ _in1_constructed_T_45, _GEN[io_eew][3] \| (io_avg ? (io_sub ^ io_in1_3[0]) & io_in2_3[0] \| (io_sub ^ io_in1_3[0] ^ io_in2_3[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_14), (io_avg ? _GEN_0[io_eew][23:16] : io_in1_2) ^ _in1_constructed_T_45, _GEN[io_eew][2] \| (io_avg ? (io_sub ^ io_in1_2[0]) & io_in2_2[0] \| (io_sub ^ io_in1_2[0] ^ io_in2_2[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_10), (io_avg ? _GEN_0[io_eew][15:8] : io_in1_1) ^ _in1_constructed_T_45, _GEN[io_eew][1] \| (io_avg ? (io_sub ^ io_in1_1[0]) & io_in2_1[0] \| (io_sub ^ io_in1_1[0] ^ io_in2_1[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_6), (io_avg ? _GEN_0[io_eew][7:0] : io_in1_0) ^ _in1_constructed_T_45, _GEN[io_eew][0] \| (io_avg ? (io_sub ^ io_in1_0[0]) & io_in2_0[0] \| (io_sub ^ io_in1_0[0] ^ io_in2_0[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_2)} + {1'h0, io_avg ? _GEN_1[io_eew][63:56] : io_in2_7, ~(_GEN[io_eew][7]) & (io_avg ? (io_sub ^ io_in1_7[0]) & io_in2_7[0] \| (io_sub ^ io_in1_7[0] ^ io_in2_7[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_30), io_avg ? _GEN_1[io_eew][55:48] : io_in2_6, ~(_GEN[io_eew][6]) & (io_avg ? (io_sub ^ io_in1_6[0]) & io_in2_6[0] \| (io_sub ^ io_in1_6[0] ^ io_in2_6[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_26), io_avg ? _GEN_1[io_eew][47:40] : io_in2_5, ~(_GEN[io_eew][5]) & (io_avg ? (io_sub ^ io_in1_5[0]) & io_in2_5[0] \| (io_sub ^ io_in1_5[0] ^ io_in2_5[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_22), io_avg ? _GEN_1[io_eew][39:32] : io_in2_4, ~(_GEN[io_eew][4]) & (io_avg ? (io_sub ^ io_in1_4[0]) & io_in2_4[0] \| (io_sub ^ io_in1_4[0] ^ io_in2_4[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_18), io_avg ? _GEN_1[io_eew][31:24] : io_in2_3, ~(_GEN[io_eew][3]) & (io_avg ? (io_sub ^ io_in1_3[0]) & io_in2_3[0] \| (io_sub ^ io_in1_3[0] ^ io_in2_3[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_14), io_avg ? _GEN_1[io_eew][23:16] : io_in2_2, ~(_GEN[io_eew][2]) & (io_avg ? (io_sub ^ io_in1_2[0]) & io_in2_2[0] \| (io_sub ^ io_in1_2[0] ^ io_in2_2[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_10), io_avg ? _GEN_1[io_eew][15:8] : io_in2_1, ~(_GEN[io_eew][1]) & (io_avg ? (io_sub ^ io_in1_1[0]) & io_in2_1[0] \| (io_sub ^ io_in1_1[0] ^ io_in2_1[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_6), io_avg ? _GEN_1[io_eew][7:0] : io_in2_0, ~(_GEN[io_eew][0]) & (io_avg ? (io_sub ^ io_in1_0[0]) & io_in2_0[0] \| (io_sub ^ io_in1_0[0] ^ io_in2_0[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_2)}; // @[IntegerPipe.scala:33:43, :38:21, :41:21, :43:16, :44:16, :53:{36,42}, :61:{32,36,41,45,50,62,71,80}, :62:{20,30,40,52,62}, :63:{12,33}, :69:{32,41,50,62,71,80}, :70:{30,40,52}, :71:{12,33}, :82:{90,96}, :87:34] wire [72:0] sum = (carry_clear & _sum_T \| carry_restore) + {8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum_7[1]) & round_incrs_sum_7[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum_7) : round_incrs_sum_7[0])) & ~(_GEN[io_eew][7]), 8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum_6[1]) & round_incrs_sum_6[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum_6) : round_incrs_sum_6[0])) & ~(_GEN[io_eew][6]), 8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum_5[1]) & round_incrs_sum_5[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum_5) : round_incrs_sum_5[0])) & ~(_GEN[io_eew][5]), 8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum_4[1]) & round_incrs_sum_4[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum_4) : round_incrs_sum_4[0])) & ~(_GEN[io_eew][4]), 8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum_3[1]) & round_incrs_sum_3[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum_3) : round_incrs_sum_3[0])) & ~(_GEN[io_eew][3]), 8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum_2[1]) & round_incrs_sum_2[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum_2) : round_incrs_sum_2[0])) & ~(_GEN[io_eew][2]), 8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum_1[1]) & round_incrs_sum_1[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum_1) : round_incrs_sum_1[0])) & ~(_GEN[io_eew][1]), 8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum[1]) & round_incrs_sum[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum) : round_incrs_sum[0])) & ~(_GEN[io_eew][0]), 1'h0} + {8'h0, ~(_GEN[io_eew][7]) & io_incr_7, 8'h0, ~(_GEN[io_eew][6]) & io_incr_6, 8'h0, ~(_GEN[io_eew][5]) & io_incr_5, 8'h0, ~(_GEN[io_eew][4]) & io_incr_4, 8'h0, ~(_GEN[io_eew][3]) & io_incr_3, 8'h0, ~(_GEN[io_eew][2]) & io_incr_2, 8'h0, ~(_GEN[io_eew][1]) & io_incr_1, 8'h0, ~(_GEN[io_eew][0]) & io_incr_0, 1'h0}; // @[IntegerPipe.scala:33:{24,43}, :34:26, :53:{36,42}, :76:{26,57}, :77:{30,67,75,86,88}, :85:110, :87:{34,54,69,86,101}] wire _in2_dummy_bits_bit_T_34 = io_sub ^ io_mask_carry[8]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire _in2_dummy_bits_bit_T_38 = io_sub ^ io_mask_carry[9]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire _in2_dummy_bits_bit_T_42 = io_sub ^ io_mask_carry[10]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire _in2_dummy_bits_bit_T_46 = io_sub ^ io_mask_carry[11]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire _in2_dummy_bits_bit_T_50 = io_sub ^ io_mask_carry[12]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire _in2_dummy_bits_bit_T_54 = io_sub ^ io_mask_carry[13]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire _in2_dummy_bits_bit_T_58 = io_sub ^ io_mask_carry[14]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire _in2_dummy_bits_bit_T_62 = io_sub ^ io_mask_carry[15]; // @[IntegerPipe.scala:54:{41,47}, :62:62] wire [1:0] round_incrs_sum_8 = io_in2_8[1:0] + (io_in1_8[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire [1:0] round_incrs_sum_9 = io_in2_9[1:0] + (io_in1_9[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire [1:0] round_incrs_sum_10 = io_in2_10[1:0] + (io_in1_10[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire [1:0] round_incrs_sum_11 = io_in2_11[1:0] + (io_in1_11[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire [1:0] round_incrs_sum_12 = io_in2_12[1:0] + (io_in1_12[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire [1:0] round_incrs_sum_13 = io_in2_13[1:0] + (io_in1_13[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire [1:0] round_incrs_sum_14 = io_in2_14[1:0] + (io_in1_14[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire [1:0] round_incrs_sum_15 = io_in2_15[1:0] + (io_in1_15[1:0] ^ _round_incrs_sum_T_77) + _GEN_2; // @[IntegerPipe.scala:76:{20,26,32,38,44,57}] wire [72:0] _sum_T_4 = {1'h0, (io_avg ? _GEN_0[io_eew][127:120] : io_in1_15) ^ _in1_constructed_T_45, _GEN[io_eew][15] \| (io_avg ? (io_sub ^ io_in1_15[0]) & io_in2_15[0] \| (io_sub ^ io_in1_15[0] ^ io_in2_15[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_62), (io_avg ? _GEN_0[io_eew][119:112] : io_in1_14) ^ _in1_constructed_T_45, _GEN[io_eew][14] \| (io_avg ? (io_sub ^ io_in1_14[0]) & io_in2_14[0] \| (io_sub ^ io_in1_14[0] ^ io_in2_14[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_58), (io_avg ? _GEN_0[io_eew][111:104] : io_in1_13) ^ _in1_constructed_T_45, _GEN[io_eew][13] \| (io_avg ? (io_sub ^ io_in1_13[0]) & io_in2_13[0] \| (io_sub ^ io_in1_13[0] ^ io_in2_13[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_54), (io_avg ? _GEN_0[io_eew][103:96] : io_in1_12) ^ _in1_constructed_T_45, _GEN[io_eew][12] \| (io_avg ? (io_sub ^ io_in1_12[0]) & io_in2_12[0] \| (io_sub ^ io_in1_12[0] ^ io_in2_12[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_50), (io_avg ? _GEN_0[io_eew][95:88] : io_in1_11) ^ _in1_constructed_T_45, _GEN[io_eew][11] \| (io_avg ? (io_sub ^ io_in1_11[0]) & io_in2_11[0] \| (io_sub ^ io_in1_11[0] ^ io_in2_11[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_46), (io_avg ? _GEN_0[io_eew][87:80] : io_in1_10) ^ _in1_constructed_T_45, _GEN[io_eew][10] \| (io_avg ? (io_sub ^ io_in1_10[0]) & io_in2_10[0] \| (io_sub ^ io_in1_10[0] ^ io_in2_10[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_42), (io_avg ? _GEN_0[io_eew][79:72] : io_in1_9) ^ _in1_constructed_T_45, _GEN[io_eew][9] \| (io_avg ? (io_sub ^ io_in1_9[0]) & io_in2_9[0] \| (io_sub ^ io_in1_9[0] ^ io_in2_9[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_38), (io_avg ? _GEN_0[io_eew][71:64] : io_in1_8) ^ _in1_constructed_T_45, _GEN[io_eew][8] \| (io_avg ? (io_sub ^ io_in1_8[0]) & io_in2_8[0] \| (io_sub ^ io_in1_8[0] ^ io_in2_8[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_34)} + {1'h0, io_avg ? _GEN_1[io_eew][127:120] : io_in2_15, ~(_GEN[io_eew][15]) & (io_avg ? (io_sub ^ io_in1_15[0]) & io_in2_15[0] \| (io_sub ^ io_in1_15[0] ^ io_in2_15[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_62), io_avg ? _GEN_1[io_eew][119:112] : io_in2_14, ~(_GEN[io_eew][14]) & (io_avg ? (io_sub ^ io_in1_14[0]) & io_in2_14[0] \| (io_sub ^ io_in1_14[0] ^ io_in2_14[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_58), io_avg ? _GEN_1[io_eew][111:104] : io_in2_13, ~(_GEN[io_eew][13]) & (io_avg ? (io_sub ^ io_in1_13[0]) & io_in2_13[0] \| (io_sub ^ io_in1_13[0] ^ io_in2_13[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_54), io_avg ? _GEN_1[io_eew][103:96] : io_in2_12, ~(_GEN[io_eew][12]) & (io_avg ? (io_sub ^ io_in1_12[0]) & io_in2_12[0] \| (io_sub ^ io_in1_12[0] ^ io_in2_12[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_50), io_avg ? _GEN_1[io_eew][95:88] : io_in2_11, ~(_GEN[io_eew][11]) & (io_avg ? (io_sub ^ io_in1_11[0]) & io_in2_11[0] \| (io_sub ^ io_in1_11[0] ^ io_in2_11[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_46), io_avg ? _GEN_1[io_eew][87:80] : io_in2_10, ~(_GEN[io_eew][10]) & (io_avg ? (io_sub ^ io_in1_10[0]) & io_in2_10[0] \| (io_sub ^ io_in1_10[0] ^ io_in2_10[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_42), io_avg ? _GEN_1[io_eew][79:72] : io_in2_9, ~(_GEN[io_eew][9]) & (io_avg ? (io_sub ^ io_in1_9[0]) & io_in2_9[0] \| (io_sub ^ io_in1_9[0] ^ io_in2_9[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_38), io_avg ? _GEN_1[io_eew][71:64] : io_in2_8, ~(_GEN[io_eew][8]) & (io_avg ? (io_sub ^ io_in1_8[0]) & io_in2_8[0] \| (io_sub ^ io_in1_8[0] ^ io_in2_8[0]) & io_sub : ~io_cmask & io_sub \| io_cmask & _in2_dummy_bits_bit_T_34)}; // @[IntegerPipe.scala:33:43, :38:21, :41:21, :43:16, :44:16, :53:{36,42}, :61:{32,36,41,45,50,62,71,80}, :62:{20,30,40,52,62}, :63:{12,33}, :69:{32,41,50,62,71,80}, :70:{30,40,52}, :71:{12,33}, :82:{90,96}, :87:34] wire [72:0] sum_1 = (carry_clear & _sum_T_4 \| carry_restore) + {8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum_15[1]) & round_incrs_sum_15[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum_15) : round_incrs_sum_15[0])) & ~(_GEN[io_eew][15]), 8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum_14[1]) & round_incrs_sum_14[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum_14) : round_incrs_sum_14[0])) & ~(_GEN[io_eew][14]), 8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum_13[1]) & round_incrs_sum_13[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum_13) : round_incrs_sum_13[0])) & ~(_GEN[io_eew][13]), 8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum_12[1]) & round_incrs_sum_12[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum_12) : round_incrs_sum_12[0])) & ~(_GEN[io_eew][12]), 8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum_11[1]) & round_incrs_sum_11[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum_11) : round_incrs_sum_11[0])) & ~(_GEN[io_eew][11]), 8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum_10[1]) & round_incrs_sum_10[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum_10) : round_incrs_sum_10[0])) & ~(_GEN[io_eew][10]), 8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum_9[1]) & round_incrs_sum_9[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum_9) : round_incrs_sum_9[0])) & ~(_GEN[io_eew][9]), 8'h0, io_avg & ((&io_rm) ? ~(round_incrs_sum_8[1]) & round_incrs_sum_8[0] : _GEN_3 & (io_rm == 2'h1 ? (&round_incrs_sum_8) : round_incrs_sum_8[0])) & ~(_GEN[io_eew][8]), 1'h0} + {8'h0, ~(_GEN[io_eew][15]) & io_incr_15, 8'h0, ~(_GEN[io_eew][14]) & io_incr_14, 8'h0, ~(_GEN[io_eew][13]) & io_incr_13, 8'h0, ~(_GEN[io_eew][12]) & io_incr_12, 8'h0, ~(_GEN[io_eew][11]) & io_incr_11, 8'h0, ~(_GEN[io_eew][10]) & io_incr_10, 8'h0, ~(_GEN[io_eew][9]) & io_incr_9, 8'h0, ~(_GEN[io_eew][8]) & io_incr_8, 1'h0}; // @[IntegerPipe.scala:33:{24,43}, :34:26, :53:{36,42}, :76:{26,57}, :77:{30,67,75,86,88}, :85:110, :87:{34,54,69,86,101}] assign io_out_0 = sum[8:1]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_out_1 = sum[17:10]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_out_2 = sum[26:19]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_out_3 = sum[35:28]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_out_4 = sum[44:37]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_out_5 = sum[53:46]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_out_6 = sum[62:55]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_out_7 = sum[71:64]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_out_8 = sum_1[8:1]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_out_9 = sum_1[17:10]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_out_10 = sum_1[26:19]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_out_11 = sum_1[35:28]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_out_12 = sum_1[44:37]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_out_13 = sum_1[53:46]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_out_14 = sum_1[62:55]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_out_15 = sum_1[71:64]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :90:31] assign io_carry_0 = sum[9]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] assign io_carry_1 = sum[18]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] assign io_carry_2 = sum[27]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] assign io_carry_3 = sum[36]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] assign io_carry_4 = sum[45]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] assign io_carry_5 = sum[54]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] assign io_carry_6 = sum[63]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] assign io_carry_7 = sum[72]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] assign io_carry_8 = sum_1[9]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] assign io_carry_9 = sum_1[18]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] assign io_carry_10 = sum_1[27]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] assign io_carry_11 = sum_1[36]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] assign io_carry_12 = sum_1[45]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] assign io_carry_13 = sum_1[54]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] assign io_carry_14 = sum_1[63]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] assign io_carry_15 = sum_1[72]; // @[IntegerPipe.scala:12:7, :87:{86,101}, :91:33] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Crossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.interrupts import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg} @deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2") class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val intnode = IntAdapterNode() lazy val module = new Impl class Impl extends LazyModuleImp(this) { (intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) => out := SynchronizerShiftReg(in, sync) } } } object IntSyncCrossingSource { def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = { val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered)) intsource.node } } class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule { val node = IntSyncSourceNode(alreadyRegistered) lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl) class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := AsyncResetReg(Cat(in.reverse)).asBools } } class ImplRegistered extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0) override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.sync := in } } } object IntSyncCrossingSink { @deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2") def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := SynchronizerShiftReg(in.sync, sync) } } } object IntSyncAsyncCrossingSink { def apply(sync: Int = 3)(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync)) intsink.node } } class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(0) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := in.sync } } } object IntSyncSyncCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncSyncCrossingSink()) intsink.node } } class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule { val node = IntSyncSinkNode(1) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def outSize = node.out.headOption.map(_._1.size).getOrElse(0) override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}" (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out := RegNext(in.sync) } } } object IntSyncRationalCrossingSink { def apply()(implicit p: Parameters) = { val intsink = LazyModule(new IntSyncRationalCrossingSink()) intsink.node } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph */ def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } }	module IntSyncSyncCrossingSink_n1x1_3( // @[Crossing.scala:96:9] input auto_in_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_0 // @[LazyModuleImp.scala:107:25] ); wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:96:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:96:9] wire nodeOut_0; // @[MixedNode.scala:542:17] wire auto_out_0_0; // @[Crossing.scala:96:9] assign nodeOut_0 = nodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17] assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:96:9] assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:96:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async } File AsyncCrossing.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, NodeHandle} import freechips.rocketchip.prci.{AsynchronousCrossing} import freechips.rocketchip.subsystem.CrossingWrapper import freechips.rocketchip.util.{AsyncQueueParams, ToAsyncBundle, FromAsyncBundle, Pow2ClockDivider, property} class TLAsyncCrossingSource(sync: Option[Int])(implicit p: Parameters) extends LazyModule { def this(x: Int)(implicit p: Parameters) = this(Some(x)) def this()(implicit p: Parameters) = this(None) val node = TLAsyncSourceNode(sync) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLAsyncCrossingSource") ++ node.in.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val bce = edgeIn.manager.anySupportAcquireB && edgeIn.client.anySupportProbe val psync = sync.getOrElse(edgeOut.manager.async.sync) val params = edgeOut.manager.async.copy(sync = psync) out.a <> ToAsyncBundle(in.a, params) in.d <> FromAsyncBundle(out.d, psync) property.cover(in.a, "TL_ASYNC_CROSSING_SOURCE_A", "MemorySystem;;TLAsyncCrossingSource Channel A") property.cover(in.d, "TL_ASYNC_CROSSING_SOURCE_D", "MemorySystem;;TLAsyncCrossingSource Channel D") if (bce) { in.b <> FromAsyncBundle(out.b, psync) out.c <> ToAsyncBundle(in.c, params) out.e <> ToAsyncBundle(in.e, params) property.cover(in.b, "TL_ASYNC_CROSSING_SOURCE_B", "MemorySystem;;TLAsyncCrossingSource Channel B") property.cover(in.c, "TL_ASYNC_CROSSING_SOURCE_C", "MemorySystem;;TLAsyncCrossingSource Channel C") property.cover(in.e, "TL_ASYNC_CROSSING_SOURCE_E", "MemorySystem;;TLAsyncCrossingSource Channel E") } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ridx := 0.U out.c.widx := 0.U out.e.widx := 0.U } } } } class TLAsyncCrossingSink(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) extends LazyModule { val node = TLAsyncSinkNode(params) lazy val module = new Impl class Impl extends LazyModuleImp(this) { override def desiredName = (Seq("TLAsyncCrossingSink") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val bce = edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe out.a <> FromAsyncBundle(in.a, params.sync) in.d <> ToAsyncBundle(out.d, params) property.cover(out.a, "TL_ASYNC_CROSSING_SINK_A", "MemorySystem;;TLAsyncCrossingSink Channel A") property.cover(out.d, "TL_ASYNC_CROSSING_SINK_D", "MemorySystem;;TLAsyncCrossingSink Channel D") if (bce) { in.b <> ToAsyncBundle(out.b, params) out.c <> FromAsyncBundle(in.c, params.sync) out.e <> FromAsyncBundle(in.e, params.sync) property.cover(out.b, "TL_ASYNC_CROSSING_SINK_B", "MemorySystem;;TLAsyncCrossingSinkChannel B") property.cover(out.c, "TL_ASYNC_CROSSING_SINK_C", "MemorySystem;;TLAsyncCrossingSink Channel C") property.cover(out.e, "TL_ASYNC_CROSSING_SINK_E", "MemorySystem;;TLAsyncCrossingSink Channel E") } else { in.b.widx := 0.U in.c.ridx := 0.U in.e.ridx := 0.U out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLAsyncCrossingSource { def apply()(implicit p: Parameters): TLAsyncSourceNode = apply(None) def apply(sync: Int)(implicit p: Parameters): TLAsyncSourceNode = apply(Some(sync)) def apply(sync: Option[Int])(implicit p: Parameters): TLAsyncSourceNode = { val asource = LazyModule(new TLAsyncCrossingSource(sync)) asource.node } } object TLAsyncCrossingSink { def apply(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) = { val asink = LazyModule(new TLAsyncCrossingSink(params)) asink.node } } @deprecated("TLAsyncCrossing is fragile. Use TLAsyncCrossingSource and TLAsyncCrossingSink", "rocket-chip 1.2") class TLAsyncCrossing(params: AsyncQueueParams = AsyncQueueParams())(implicit p: Parameters) extends LazyModule { val source = LazyModule(new TLAsyncCrossingSource()) val sink = LazyModule(new TLAsyncCrossingSink(params)) val node = NodeHandle(source.node, sink.node) sink.node := source.node lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val in_clock = Input(Clock()) val in_reset = Input(Bool()) val out_clock = Input(Clock()) val out_reset = Input(Bool()) }) source.module.clock := io.in_clock source.module.reset := io.in_reset sink.module.clock := io.out_clock sink.module.reset := io.out_reset } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMAsyncCrossing(txns: Int, params: AsynchronousCrossing = AsynchronousCrossing())(implicit p: Parameters) extends LazyModule { val model = LazyModule(new TLRAMModel("AsyncCrossing")) val fuzz = LazyModule(new TLFuzzer(txns)) val island = LazyModule(new CrossingWrapper(params)) val ram = island { LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) } island.crossTLIn(ram.node) := TLFragmenter(4, 256) := TLDelayer(0.1) := model.node := fuzz.node lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished // Shove the RAM into another clock domain val clocks = Module(new Pow2ClockDivider(2)) island.module.clock := clocks.io.clock_out } } class TLRAMAsyncCrossingTest(txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut_wide = Module(LazyModule(new TLRAMAsyncCrossing(txns)).module) val dut_narrow = Module(LazyModule(new TLRAMAsyncCrossing(txns, AsynchronousCrossing(safe = false, narrow = true))).module) io.finished := dut_wide.io.finished && dut_narrow.io.finished dut_wide.io.start := io.start dut_narrow.io.start := io.start } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. */ val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } }	module TLAsyncCrossingSource_a9d32s1k1z2u( // @[AsyncCrossing.scala:23:9] input clock, // @[AsyncCrossing.scala:23:9] input reset, // @[AsyncCrossing.scala:23:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_a_mem_0_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_mem_0_data, // @[LazyModuleImp.scala:107:25] input auto_out_a_ridx, // @[LazyModuleImp.scala:107:25] output auto_out_a_widx, // @[LazyModuleImp.scala:107:25] input auto_out_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] output auto_out_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25] output auto_out_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] input auto_out_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_mem_0_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_mem_0_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_d_mem_0_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ridx, // @[LazyModuleImp.scala:107:25] input auto_out_d_widx, // @[LazyModuleImp.scala:107:25] output auto_out_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] input auto_out_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25] input auto_out_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] output auto_out_d_safe_sink_reset_n // @[LazyModuleImp.scala:107:25] ); wire _nodeIn_d_sink_io_deq_valid; // @[AsyncQueue.scala:211:22] wire [2:0] _nodeIn_d_sink_io_deq_bits_opcode; // @[AsyncQueue.scala:211:22] wire [1:0] _nodeIn_d_sink_io_deq_bits_param; // @[AsyncQueue.scala:211:22] wire [1:0] _nodeIn_d_sink_io_deq_bits_size; // @[AsyncQueue.scala:211:22] wire _nodeIn_d_sink_io_deq_bits_source; // @[AsyncQueue.scala:211:22] wire _nodeIn_d_sink_io_deq_bits_sink; // @[AsyncQueue.scala:211:22] wire _nodeIn_d_sink_io_deq_bits_denied; // @[AsyncQueue.scala:211:22] wire _nodeIn_d_sink_io_deq_bits_corrupt; // @[AsyncQueue.scala:211:22] wire _nodeOut_a_source_io_enq_ready; // @[AsyncQueue.scala:220:24] TLMonitor_74 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_nodeOut_a_source_io_enq_ready), // @[AsyncQueue.scala:220:24] .io_in_a_valid (auto_in_a_valid), .io_in_a_bits_opcode (auto_in_a_bits_opcode), .io_in_a_bits_address (auto_in_a_bits_address), .io_in_d_ready (auto_in_d_ready), .io_in_d_valid (_nodeIn_d_sink_io_deq_valid), // @[AsyncQueue.scala:211:22] .io_in_d_bits_opcode (_nodeIn_d_sink_io_deq_bits_opcode), // @[AsyncQueue.scala:211:22] .io_in_d_bits_param (_nodeIn_d_sink_io_deq_bits_param), // @[AsyncQueue.scala:211:22] .io_in_d_bits_size (_nodeIn_d_sink_io_deq_bits_size), // @[AsyncQueue.scala:211:22] .io_in_d_bits_source (_nodeIn_d_sink_io_deq_bits_source), // @[AsyncQueue.scala:211:22] .io_in_d_bits_sink (_nodeIn_d_sink_io_deq_bits_sink), // @[AsyncQueue.scala:211:22] .io_in_d_bits_denied (_nodeIn_d_sink_io_deq_bits_denied), // @[AsyncQueue.scala:211:22] .io_in_d_bits_corrupt (_nodeIn_d_sink_io_deq_bits_corrupt) // @[AsyncQueue.scala:211:22] ); // @[Nodes.scala:27:25] AsyncQueueSource_TLBundleA_a9d32s1k1z2u nodeOut_a_source ( // @[AsyncQueue.scala:220:24] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_a_source_io_enq_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_opcode (auto_in_a_bits_opcode), .io_enq_bits_address (auto_in_a_bits_address), .io_enq_bits_data (auto_in_a_bits_data), .io_async_mem_0_opcode (auto_out_a_mem_0_opcode), .io_async_mem_0_address (auto_out_a_mem_0_address), .io_async_mem_0_data (auto_out_a_mem_0_data), .io_async_ridx (auto_out_a_ridx), .io_async_widx (auto_out_a_widx), .io_async_safe_ridx_valid (auto_out_a_safe_ridx_valid), .io_async_safe_widx_valid (auto_out_a_safe_widx_valid), .io_async_safe_source_reset_n (auto_out_a_safe_source_reset_n), .io_async_safe_sink_reset_n (auto_out_a_safe_sink_reset_n) ); // @[AsyncQueue.scala:220:24] AsyncQueueSink_TLBundleD_a9d32s1k1z2u nodeIn_d_sink ( // @[AsyncQueue.scala:211:22] .clock (clock), .reset (reset), .io_deq_ready (auto_in_d_ready), .io_deq_valid (_nodeIn_d_sink_io_deq_valid), .io_deq_bits_opcode (_nodeIn_d_sink_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_d_sink_io_deq_bits_param), .io_deq_bits_size (_nodeIn_d_sink_io_deq_bits_size), .io_deq_bits_source (_nodeIn_d_sink_io_deq_bits_source), .io_deq_bits_sink (_nodeIn_d_sink_io_deq_bits_sink), .io_deq_bits_denied (_nodeIn_d_sink_io_deq_bits_denied), .io_deq_bits_data (auto_in_d_bits_data), .io_deq_bits_corrupt (_nodeIn_d_sink_io_deq_bits_corrupt), .io_async_mem_0_opcode (auto_out_d_mem_0_opcode), .io_async_mem_0_size (auto_out_d_mem_0_size), .io_async_mem_0_source (auto_out_d_mem_0_source), .io_async_mem_0_data (auto_out_d_mem_0_data), .io_async_ridx (auto_out_d_ridx), .io_async_widx (auto_out_d_widx), .io_async_safe_ridx_valid (auto_out_d_safe_ridx_valid), .io_async_safe_widx_valid (auto_out_d_safe_widx_valid), .io_async_safe_source_reset_n (auto_out_d_safe_source_reset_n), .io_async_safe_sink_reset_n (auto_out_d_safe_sink_reset_n) ); // @[AsyncQueue.scala:211:22] assign auto_in_a_ready = _nodeOut_a_source_io_enq_ready; // @[AsyncQueue.scala:220:24] assign auto_in_d_valid = _nodeIn_d_sink_io_deq_valid; // @[AsyncQueue.scala:211:22] assign auto_in_d_bits_opcode = _nodeIn_d_sink_io_deq_bits_opcode; // @[AsyncQueue.scala:211:22] assign auto_in_d_bits_param = _nodeIn_d_sink_io_deq_bits_param; // @[AsyncQueue.scala:211:22] assign auto_in_d_bits_size = _nodeIn_d_sink_io_deq_bits_size; // @[AsyncQueue.scala:211:22] assign auto_in_d_bits_source = _nodeIn_d_sink_io_deq_bits_source; // @[AsyncQueue.scala:211:22] assign auto_in_d_bits_sink = _nodeIn_d_sink_io_deq_bits_sink; // @[AsyncQueue.scala:211:22] assign auto_in_d_bits_denied = _nodeIn_d_sink_io_deq_bits_denied; // @[AsyncQueue.scala:211:22] assign auto_in_d_bits_corrupt = _nodeIn_d_sink_io_deq_bits_corrupt; // @[AsyncQueue.scala:211:22] endmodule
Generate the Verilog code corresponding to the following Chisel files. File TilelinkAdapters.scala: package constellation.protocol import chisel3._ import chisel3.util._ import constellation.channel._ import constellation.noc._ import constellation.soc.{CanAttachToGlobalNoC} import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ import freechips.rocketchip.tilelink._ import scala.collection.immutable.{ListMap} abstract class TLChannelToNoC[T <: TLChannel](gen: => T, edge: TLEdge, idToEgress: Int => Int)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Flipped(Decoupled(gen)) val flit = Decoupled(new IngressFlit(flitWidth)) }) def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B // convert decoupled to irrevocable val q = Module(new Queue(gen, 1, pipe=true, flow=true)) val protocol = q.io.deq val has_body = Wire(Bool()) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val head = edge.first(protocol.bits, protocol.fire) val tail = edge.last(protocol.bits, protocol.fire) def requestOH: Seq[Bool] val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt)) val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt)) val is_body = RegInit(false.B) io.flit.valid := protocol.valid protocol.ready := io.flit.ready && (is_body \|\| !has_body) io.flit.bits.head := head && !is_body io.flit.bits.tail := tail && (is_body \|\| !has_body) io.flit.bits.egress_id := Mux1H(requestOH.zipWithIndex.map { case (r, i) => r -> idToEgress(i).U }) io.flit.bits.payload := Mux(is_body, body, const) when (io.flit.fire && io.flit.bits.head) { is_body := true.B } when (io.flit.fire && io.flit.bits.tail) { is_body := false.B } } abstract class TLChannelFromNoC[T <: TLChannel](gen: => T)(implicit val p: Parameters) extends Module with TLFieldHelper { val flitWidth = minTLPayloadWidth(gen) val io = IO(new Bundle { val protocol = Decoupled(gen) val flit = Flipped(Decoupled(new EgressFlit(flitWidth))) }) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) val protocol = Wire(Decoupled(gen)) val body_fields = getBodyFields(protocol.bits) val const_fields = getConstFields(protocol.bits) val is_const = RegInit(true.B) val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W)) val const = Mux(io.flit.bits.head, io.flit.bits.payload, const_reg) io.flit.ready := (is_const && !io.flit.bits.tail) \|\| protocol.ready protocol.valid := (!is_const \|\| io.flit.bits.tail) && io.flit.valid def assign(i: UInt, sigs: Seq[Data]) = { var t = i for (s <- sigs.reverse) { s := t.asTypeOf(s.cloneType) t = t >> s.getWidth } } assign(const, const_fields) assign(io.flit.bits.payload, body_fields) when (io.flit.fire && io.flit.bits.head) { is_const := false.B; const_reg := io.flit.bits.payload } when (io.flit.fire && io.flit.bits.tail) { is_const := true.B } } trait HasAddressDecoder { // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) val edgeIn: TLEdge val edgesOut: Seq[TLEdge] lazy val reacheableIO = edgesOut.map { mp => edgeIn.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma) }} }} }.toVector lazy val releaseIO = (edgesOut zip reacheableIO).map { case (mp, reachable) => reachable && edgeIn.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector def outputPortFn(connectIO: Seq[Boolean]) = { val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectIO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_\|\|_)) } } class TLAToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToAEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleA(bundle), edgeIn, slaveToAEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) \|\| (~protocol.bits.mask =/= 0.U) lazy val connectAIO = reacheableIO lazy val requestOH = outputPortFn(connectAIO).zipWithIndex.map { case (o, j) => connectAIO(j).B && (unique(connectAIO) \|\| o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source \| sourceStart.U } class TLAFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleA(bundle))(p) { io.protocol <> protocol when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLBToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToBIngress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleB(bundle), edgeOut, masterToBIngress)(p) { has_body := edgeOut.hasData(protocol.bits) \|\| (~protocol.bits.mask =/= 0.U) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol } class TLBFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleB(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) when (io.flit.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) } } class TLCToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToCEgress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleC(bundle), edgeIn, slaveToCEgress)(p) with HasAddressDecoder { has_body := edgeIn.hasData(protocol.bits) lazy val connectCIO = releaseIO lazy val requestOH = outputPortFn(connectCIO).zipWithIndex.map { case (o, j) => connectCIO(j).B && (unique(connectCIO) \|\| o(protocol.bits.address)) } q.io.enq <> io.protocol q.io.enq.bits.source := io.protocol.bits.source \| sourceStart.U } class TLCFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleC(bundle))(p) { io.protocol <> protocol } class TLDToNoC( edgeOut: TLEdge, edgesIn: Seq[TLEdge], bundle: TLBundleParameters, masterToDIngress: Int => Int, sourceStart: Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleD(bundle), edgeOut, masterToDIngress)(p) { has_body := edgeOut.hasData(protocol.bits) lazy val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) lazy val requestOH = inputIdRanges.map { i => i.contains(protocol.bits.source) } q.io.enq <> io.protocol q.io.enq.bits.sink := io.protocol.bits.sink \| sourceStart.U } class TLDFromNoC(edgeIn: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleD(bundle))(p) { io.protocol <> protocol io.protocol.bits.source := trim(protocol.bits.source, sourceSize) } class TLEToNoC( val edgeIn: TLEdge, val edgesOut: Seq[TLEdge], bundle: TLBundleParameters, slaveToEEgress: Int => Int )(implicit p: Parameters) extends TLChannelToNoC(new TLBundleE(bundle), edgeIn, slaveToEEgress)(p) { has_body := edgeIn.hasData(protocol.bits) lazy val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) lazy val requestOH = outputIdRanges.map { o => o.contains(protocol.bits.sink) } q.io.enq <> io.protocol } class TLEFromNoC(edgeOut: TLEdge, bundle: TLBundleParameters, sourceSize: Int)(implicit p: Parameters) extends TLChannelFromNoC(new TLBundleE(bundle))(p) { io.protocol <> protocol io.protocol.bits.sink := trim(protocol.bits.sink, sourceSize) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLCToNoC_11( // @[TilelinkAdapters.scala:151:7] input clock, // @[TilelinkAdapters.scala:151:7] input reset, // @[TilelinkAdapters.scala:151:7] output io_protocol_ready, // @[TilelinkAdapters.scala:19:14] input io_protocol_valid, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14] input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14] input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14] input [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14] input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14] input [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14] input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14] input io_flit_ready, // @[TilelinkAdapters.scala:19:14] output io_flit_valid, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14] output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14] output [64:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14] output [5:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14] ); wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17] wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17] wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17] wire [5:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17] wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17] wire [63:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17] wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17] wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71] reg [8:0] head_counter; // @[Edges.scala:229:27] wire head = head_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire [8:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:3]) : 9'h0; // @[package.scala:243:{46,71,76}] reg [8:0] tail_counter; // @[Edges.scala:229:27] reg is_body; // @[TilelinkAdapters.scala:39:24] wire q_io_deq_ready = io_flit_ready & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36] wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25] wire io_flit_bits_tail_0 = (tail_counter == 9'h1 \| tail_beats1 == 9'h0) & (is_body \| ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36, :221:14, :229:27, :232:{25,33,43}] wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:151:7] if (reset) begin // @[TilelinkAdapters.scala:151:7] head_counter <= 9'h0; // @[Edges.scala:229:27] tail_counter <= 9'h0; // @[Edges.scala:229:27] is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :151:7] end else begin // @[TilelinkAdapters.scala:151:7] if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35] head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:3]) : 9'h0) : head_counter - 9'h1; // @[package.scala:243:{46,71,76}] tail_counter <= tail_counter == 9'h0 ? tail_beats1 : tail_counter - 9'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21] end is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 \| is_body); // @[Decoupled.scala:51:35] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_333( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File SourceB.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class SourceBRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val param = UInt(3.W) val tag = UInt(params.tagBits.W) val set = UInt(params.setBits.W) val clients = UInt(params.clientBits.W) } class SourceB(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val req = Flipped(Decoupled(new SourceBRequest(params))) val b = Decoupled(new TLBundleB(params.inner.bundle)) }) if (params.firstLevel) { // Tie off unused ports io.req.ready := true.B io.b.valid := false.B io.b.bits := DontCare } else { val remain = RegInit(0.U(params.clientBits.W)) val remain_set = WireInit(init = 0.U(params.clientBits.W)) val remain_clr = WireInit(init = 0.U(params.clientBits.W)) remain := (remain \| remain_set) & ~remain_clr val busy = remain.orR val todo = Mux(busy, remain, io.req.bits.clients) val next = ~(leftOR(todo) << 1) & todo if (params.clientBits > 1) { params.ccover(PopCount(remain) > 1.U, "SOURCEB_MULTI_PROBE", "Had to probe more than one client") } assert (!io.req.valid \|\| io.req.bits.clients =/= 0.U) io.req.ready := !busy when (io.req.fire) { remain_set := io.req.bits.clients } // No restrictions on the type of buffer used here val b = Wire(chiselTypeOf(io.b)) io.b <> params.micro.innerBuf.b(b) b.valid := busy \|\| io.req.valid when (b.fire) { remain_clr := next } params.ccover(b.valid && !b.ready, "SOURCEB_STALL", "Backpressured when issuing a probe") val tag = Mux(!busy, io.req.bits.tag, RegEnable(io.req.bits.tag, io.req.fire)) val set = Mux(!busy, io.req.bits.set, RegEnable(io.req.bits.set, io.req.fire)) val param = Mux(!busy, io.req.bits.param, RegEnable(io.req.bits.param, io.req.fire)) b.bits.opcode := TLMessages.Probe b.bits.param := param b.bits.size := params.offsetBits .U b.bits.source := params.clientSource(next) b.bits.address := params.expandAddress(tag, set, 0.U) b.bits.mask := ~0.U(params.inner.manager.beatBytes.W) b.bits.data := 0.U b.bits.corrupt := false.B } } File Parameters.scala: / * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relListscache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_\|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x \| 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ \|\| _) (matches, bits.U) } expanded \| Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) \|\| (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) \|\| ((opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm \|\| opcode === TLMessages.Get \|\| (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN \|\| param === TLPermissions.BtoN \|\| param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB \|\| param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle	module SourceB_1( // @[SourceB.scala:33:7] input clock, // @[SourceB.scala:33:7] input reset, // @[SourceB.scala:33:7] output io_req_ready, // @[SourceB.scala:35:14] input io_req_valid, // @[SourceB.scala:35:14] input [2:0] io_req_bits_param, // @[SourceB.scala:35:14] input [8:0] io_req_bits_tag, // @[SourceB.scala:35:14] input [10:0] io_req_bits_set, // @[SourceB.scala:35:14] input io_req_bits_clients, // @[SourceB.scala:35:14] input io_b_ready, // @[SourceB.scala:35:14] output io_b_valid, // @[SourceB.scala:35:14] output [1:0] io_b_bits_param, // @[SourceB.scala:35:14] output [31:0] io_b_bits_address // @[SourceB.scala:35:14] ); wire io_req_valid_0 = io_req_valid; // @[SourceB.scala:33:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceB.scala:33:7] wire [8:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceB.scala:33:7] wire [10:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceB.scala:33:7] wire io_req_bits_clients_0 = io_req_bits_clients; // @[SourceB.scala:33:7] wire io_b_ready_0 = io_b_ready; // @[SourceB.scala:33:7] wire _b_bits_address_base_T_2 = reset; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_8 = reset; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_14 = reset; // @[Parameters.scala:222:12] wire [2:0] io_b_bits_opcode = 3'h6; // @[SourceB.scala:33:7] wire [2:0] io_b_bits_size = 3'h6; // @[SourceB.scala:33:7] wire [2:0] b_bits_opcode = 3'h6; // @[SourceB.scala:65:17] wire [2:0] b_bits_size = 3'h6; // @[SourceB.scala:65:17] wire [5:0] io_b_bits_source = 6'h28; // @[SourceB.scala:33:7] wire [5:0] b_bits_source = 6'h28; // @[SourceB.scala:65:17] wire [15:0] io_b_bits_mask = 16'hFFFF; // @[SourceB.scala:33:7] wire [15:0] b_bits_mask = 16'hFFFF; // @[SourceB.scala:65:17] wire [15:0] _b_bits_mask_T = 16'hFFFF; // @[SourceB.scala:81:23] wire [127:0] io_b_bits_data = 128'h0; // @[SourceB.scala:33:7] wire [127:0] b_bits_data = 128'h0; // @[SourceB.scala:65:17] wire io_b_bits_corrupt = 1'h0; // @[SourceB.scala:33:7] wire b_bits_corrupt = 1'h0; // @[SourceB.scala:65:17] wire _b_bits_address_base_T = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_4 = 1'h0; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_6 = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_10 = 1'h0; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_12 = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_16 = 1'h0; // @[Parameters.scala:222:12] wire [1:0] b_bits_address_lo_lo_hi_hi = 2'h0; // @[Parameters.scala:230:8] wire [1:0] b_bits_address_hi_hi_hi_lo = 2'h0; // @[Parameters.scala:230:8] wire [5:0] b_bits_address_base_y_2 = 6'h0; // @[Parameters.scala:221:15] wire [5:0] _b_bits_address_base_T_17 = 6'h0; // @[Parameters.scala:223:6] wire _b_bits_address_base_T_1 = 1'h1; // @[Parameters.scala:222:24] wire _b_bits_address_base_T_7 = 1'h1; // @[Parameters.scala:222:24] wire _b_bits_address_base_T_13 = 1'h1; // @[Parameters.scala:222:24] wire _io_req_ready_T; // @[SourceB.scala:61:21] wire b_ready = io_b_ready_0; // @[SourceB.scala:33:7, :65:17] wire b_valid; // @[SourceB.scala:65:17] wire [1:0] b_bits_param; // @[SourceB.scala:65:17] wire [31:0] b_bits_address; // @[SourceB.scala:65:17] wire io_req_ready_0; // @[SourceB.scala:33:7] wire [1:0] io_b_bits_param_0; // @[SourceB.scala:33:7] wire [31:0] io_b_bits_address_0; // @[SourceB.scala:33:7] wire io_b_valid_0; // @[SourceB.scala:33:7] reg remain; // @[SourceB.scala:46:25] wire busy = remain; // @[SourceB.scala:46:25, :51:23] wire remain_set; // @[SourceB.scala:47:30] wire remain_clr; // @[SourceB.scala:48:30] wire _remain_T = remain \| remain_set; // @[SourceB.scala:46:25, :47:30, :49:23] wire _remain_T_1 = ~remain_clr; // @[SourceB.scala:48:30, :49:39] wire _remain_T_2 = _remain_T & _remain_T_1; // @[SourceB.scala:49:{23,37,39}] wire todo = busy ? remain : io_req_bits_clients_0; // @[SourceB.scala:33:7, :46:25, :51:23, :52:19] wire _next_T = todo; // @[package.scala:254:17] wire [1:0] _next_T_1 = {_next_T, 1'h0}; // @[package.scala:254:17] wire [1:0] _next_T_2 = ~_next_T_1; // @[SourceB.scala:53:{16,31}] wire [1:0] next = {1'h0, _next_T_2[0] & todo}; // @[SourceB.scala:52:19, :53:{16,37}]
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_148( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_252 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_1( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); AsyncResetSynchronizerPrimitiveShiftReg_d3_i0 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_d), .io_q (io_q) ); // @[ShiftReg.scala:45:23] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Transposer.scala: package gemmini import chisel3._ import chisel3.util._ import Util._ trait Transposer[T <: Data] extends Module { def dim: Int def dataType: T val io = IO(new Bundle { val inRow = Flipped(Decoupled(Vec(dim, dataType))) val outCol = Decoupled(Vec(dim, dataType)) }) } class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose val sMoveUp :: sMoveLeft :: Nil = Enum(2) val state = RegInit(sMoveUp) val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1) val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1) io.outCol.valid := 0.U io.inRow.ready := 0.U switch(state) { is(sMoveUp) { io.inRow.ready := upCounter <= dim.U io.outCol.valid := leftCounter > 0.U when(io.inRow.fire) { upCounter := upCounter + 1.U } when(upCounter === (dim-1).U) { state := sMoveLeft leftCounter := 0.U } when(io.outCol.fire) { leftCounter := leftCounter - 1.U } } is(sMoveLeft) { io.inRow.ready := leftCounter <= dim.U // TODO: this is naive io.outCol.valid := upCounter > 0.U when(leftCounter === (dim-1).U) { state := sMoveUp } when(io.inRow.fire) { leftCounter := leftCounter + 1.U upCounter := 0.U } when(io.outCol.fire) { upCounter := upCounter - 1.U } } } // Propagate input from bottom row to top row systolically in the move up phase // TODO: need to iterate over columns to connect Chisel values of type T // Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?) for (colIdx <- 0 until dim) { regArray.foldRight(io.inRow.bits(colIdx)) { case (regRow, prevReg) => when (state === sMoveUp) { regRow(colIdx) := prevReg } regRow(colIdx) } } // Propagate input from right side to left side systolically in the move left phase for (rowIdx <- 0 until dim) { regArrayT.foldRight(io.inRow.bits(rowIdx)) { case (regCol, prevReg) => when (state === sMoveLeft) { regCol(rowIdx) := prevReg } regCol(rowIdx) } } // Pull from the left side or the top side based on the state for (idx <- 0 until dim) { when (state === sMoveUp) { io.outCol.bits(idx) := regArray(0)(idx) }.elsewhen(state === sMoveLeft) { io.outCol.bits(idx) := regArrayT(0)(idx) }.otherwise { io.outCol.bits(idx) := DontCare } } } class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { require(isPow2(dim)) val LEFT_DIR = 0.U(1.W) val UP_DIR = 1.U(1.W) class PE extends Module { val io = IO(new Bundle { val inR = Input(dataType) val inD = Input(dataType) val outL = Output(dataType) val outU = Output(dataType) val dir = Input(UInt(1.W)) val en = Input(Bool()) }) val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en) io.outU := reg io.outL := reg } val pes = Seq.fill(dim,dim)(Module(new PE)) val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter val dir = RegInit(LEFT_DIR) // Wire up horizontal signals for (row <- 0 until dim; col <- 0 until dim) { val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL pes(row)(col).io.inR := right_in } // Wire up vertical signals for (row <- 0 until dim; col <- 0 until dim) { val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU pes(row)(col).io.inD := down_in } // Wire up global signals pes.flatten.foreach(_.io.dir := dir) pes.flatten.foreach(_.io.en := io.inRow.fire) io.outCol.valid := true.B io.inRow.ready := true.B val left_out = VecInit(pes.transpose.head.map(_.io.outL)) val up_out = VecInit(pes.head.map(_.io.outU)) io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out) when (io.inRow.fire) { counter := wrappingAdd(counter, 1.U, dim) } when (counter === (dim-1).U && io.inRow.fire) { dir := ~dir } } class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] { val regArray = Seq.fill(dim, dim)(Reg(dataType)) val regArrayT = regArray.transpose // state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise val state = RegInit(0.U(1.W)) val countInc = io.inRow.fire \|\| io.outCol.fire val (countValue, countWrap) = Counter(countInc, dim) io.inRow.ready := state === 0.U io.outCol.valid := state === 1.U for (i <- 0 until dim) { for (j <- 0 until dim) { when(countValue === i.U && io.inRow.fire) { regArray(i)(j) := io.inRow.bits(j) } } } for (i <- 0 until dim) { io.outCol.bits(i) := 0.U for (j <- 0 until dim) { when(countValue === j.U) { io.outCol.bits(i) := regArrayT(j)(i) } } } when (io.inRow.fire && countWrap) { state := 1.U } when (io.outCol.fire && countWrap) { state := 0.U } assert(!(state === 0.U) \|\| !io.outCol.fire) assert(!(state === 1.U) \|\| !io.inRow.fire) }	module PE_210( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.diplomacy.{ AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry, IdRange, RegionType, TransferSizes } import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions} import freechips.rocketchip.util.{ AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase, CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct } import scala.math.max //These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel case class TLMasterToSlaveTransferSizes( // Supports both Acquire+Release of the following two sizes: acquireT: TransferSizes = TransferSizes.none, acquireB: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none) extends TLCommonTransferSizes { def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .intersect(rhs.acquireT), acquireB = acquireB .intersect(rhs.acquireB), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( acquireT = acquireT .mincover(rhs.acquireT), acquireB = acquireB .mincover(rhs.acquireB), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(acquireT, "T"), str(acquireB, "B"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""acquireT = ${acquireT} \|acquireB = ${acquireB} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLMasterToSlaveTransferSizes { def unknownEmits = TLMasterToSlaveTransferSizes( acquireT = TransferSizes(1, 4096), acquireB = TransferSizes(1, 4096), arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096)) def unknownSupports = TLMasterToSlaveTransferSizes() } //These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel case class TLSlaveToMasterTransferSizes( probe: TransferSizes = TransferSizes.none, arithmetic: TransferSizes = TransferSizes.none, logical: TransferSizes = TransferSizes.none, get: TransferSizes = TransferSizes.none, putFull: TransferSizes = TransferSizes.none, putPartial: TransferSizes = TransferSizes.none, hint: TransferSizes = TransferSizes.none ) extends TLCommonTransferSizes { def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .intersect(rhs.probe), arithmetic = arithmetic.intersect(rhs.arithmetic), logical = logical .intersect(rhs.logical), get = get .intersect(rhs.get), putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( probe = probe .mincover(rhs.probe), arithmetic = arithmetic.mincover(rhs.arithmetic), logical = logical .mincover(rhs.logical), get = get .mincover(rhs.get), putFull = putFull .mincover(rhs.putFull), putPartial = putPartial.mincover(rhs.putPartial), hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag def flags = Vector( str(probe, "P"), str(arithmetic, "A"), str(logical, "L"), str(get, "G"), str(putFull, "F"), str(putPartial, "P"), str(hint, "H")) flags.mkString } // Prints out the actual information in a user readable way def infoString = { s"""probe = ${probe} \|arithmetic = ${arithmetic} \|logical = ${logical} \|get = ${get} \|putFull = ${putFull} \|putPartial = ${putPartial} \|hint = ${hint} \| \|""".stripMargin } } object TLSlaveToMasterTransferSizes { def unknownEmits = TLSlaveToMasterTransferSizes( arithmetic = TransferSizes(1, 4096), logical = TransferSizes(1, 4096), get = TransferSizes(1, 4096), putFull = TransferSizes(1, 4096), putPartial = TransferSizes(1, 4096), hint = TransferSizes(1, 4096), probe = TransferSizes(1, 4096)) def unknownSupports = TLSlaveToMasterTransferSizes() } trait TLCommonTransferSizes { def arithmetic: TransferSizes def logical: TransferSizes def get: TransferSizes def putFull: TransferSizes def putPartial: TransferSizes def hint: TransferSizes } class TLSlaveParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], setName: Option[String], val address: Seq[AddressSet], val regionType: RegionType.T, val executable: Boolean, val fifoId: Option[Int], val supports: TLMasterToSlaveTransferSizes, val emits: TLSlaveToMasterTransferSizes, // By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation) val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData // If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order // Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck // ReleaseAck may NEVER be denied extends SimpleProduct { def sortedAddress = address.sorted override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters] override def productPrefix = "TLSlaveParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 11 def productElement(n: Int): Any = n match { case 0 => name case 1 => address case 2 => resources case 3 => regionType case 4 => executable case 5 => fifoId case 6 => supports case 7 => emits case 8 => alwaysGrantsT case 9 => mayDenyGet case 10 => mayDenyPut case _ => throw new IndexOutOfBoundsException(n.toString) } def supportsAcquireT: TransferSizes = supports.acquireT def supportsAcquireB: TransferSizes = supports.acquireB def supportsArithmetic: TransferSizes = supports.arithmetic def supportsLogical: TransferSizes = supports.logical def supportsGet: TransferSizes = supports.get def supportsPutFull: TransferSizes = supports.putFull def supportsPutPartial: TransferSizes = supports.putPartial def supportsHint: TransferSizes = supports.hint require (!address.isEmpty, "Address cannot be empty") address.foreach { a => require (a.finite, "Address must be finite") } address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)") require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)") require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)") require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)") require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)") require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)") require (!alwaysGrantsT \|\| supportsAcquireT, s"Must supportAcquireT if promising to always grantT") // Make sure that the regionType agrees with the capabilities require (!supportsAcquireB \|\| regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached require (regionType <= RegionType.UNCACHED \|\| supportsAcquireB) // tracked, cached -> acquire require (regionType != RegionType.UNCACHED \|\| supportsGet) // uncached -> supportsGet val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected") val maxTransfer = List( // Largest supported transfer of all types supportsAcquireT.max, supportsAcquireB.max, supportsArithmetic.max, supportsLogical.max, supportsGet.max, supportsPutFull.max, supportsPutPartial.max).max val maxAddress = address.map(_.max).max val minAlignment = address.map(_.alignment).min // The device had better not support a transfer larger than its alignment require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)") def toResource: ResourceAddress = { ResourceAddress(address, ResourcePermissions( r = supportsAcquireB \|\| supportsGet, w = supportsAcquireT \|\| supportsPutFull, x = executable, c = supportsAcquireB, a = supportsArithmetic && supportsLogical)) } def findTreeViolation() = nodePath.find { case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false case _: SinkNode[_, _, _, _, _] => false case node => node.inputs.size != 1 } def isTree = findTreeViolation() == None def infoString = { s"""Slave Name = ${name} \|Slave Address = ${address} \|supports = ${supports.infoString} \| \|""".stripMargin } def v1copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { new TLSlaveParameters( setName = setName, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = emits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, fifoId: Option[Int] = fifoId, supports: TLMasterToSlaveTransferSizes = supports, emits: TLSlaveToMasterTransferSizes = emits, alwaysGrantsT: Boolean = alwaysGrantsT, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } @deprecated("Use v1copy instead of copy","") def copy( address: Seq[AddressSet] = address, resources: Seq[Resource] = resources, regionType: RegionType.T = regionType, executable: Boolean = executable, nodePath: Seq[BaseNode] = nodePath, supportsAcquireT: TransferSizes = supports.acquireT, supportsAcquireB: TransferSizes = supports.acquireB, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint, mayDenyGet: Boolean = mayDenyGet, mayDenyPut: Boolean = mayDenyPut, alwaysGrantsT: Boolean = alwaysGrantsT, fifoId: Option[Int] = fifoId) = { v1copy( address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supportsAcquireT = supportsAcquireT, supportsAcquireB = supportsAcquireB, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } } object TLSlaveParameters { def v1( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = { new TLSlaveParameters( setName = None, address = address, resources = resources, regionType = regionType, executable = executable, nodePath = nodePath, supports = TLMasterToSlaveTransferSizes( acquireT = supportsAcquireT, acquireB = supportsAcquireB, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLSlaveToMasterTransferSizes.unknownEmits, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut, alwaysGrantsT = alwaysGrantsT, fifoId = fifoId) } def v2( address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports, emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits, alwaysGrantsT: Boolean = false, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false) = { new TLSlaveParameters( nodePath = nodePath, resources = resources, setName = name, address = address, regionType = regionType, executable = executable, fifoId = fifoId, supports = supports, emits = emits, alwaysGrantsT = alwaysGrantsT, mayDenyGet = mayDenyGet, mayDenyPut = mayDenyPut) } } object TLManagerParameters { @deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","") def apply( address: Seq[AddressSet], resources: Seq[Resource] = Seq(), regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, nodePath: Seq[BaseNode] = Seq(), supportsAcquireT: TransferSizes = TransferSizes.none, supportsAcquireB: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none, mayDenyGet: Boolean = false, mayDenyPut: Boolean = false, alwaysGrantsT: Boolean = false, fifoId: Option[Int] = None) = TLSlaveParameters.v1( address, resources, regionType, executable, nodePath, supportsAcquireT, supportsAcquireB, supportsArithmetic, supportsLogical, supportsGet, supportsPutFull, supportsPutPartial, supportsHint, mayDenyGet, mayDenyPut, alwaysGrantsT, fifoId, ) } case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int]) { def members = Seq(a, b, c, d) members.collect { case Some(beatBytes) => require (isPow2(beatBytes), "Data channel width must be a power of 2") } } object TLChannelBeatBytes{ def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes( Some(beatBytes), Some(beatBytes), Some(beatBytes), Some(beatBytes)) def apply(): TLChannelBeatBytes = TLChannelBeatBytes( None, None, None, None) } class TLSlavePortParameters private( val slaves: Seq[TLSlaveParameters], val channelBytes: TLChannelBeatBytes, val endSinkId: Int, val minLatency: Int, val responseFields: Seq[BundleFieldBase], val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct { def sortedSlaves = slaves.sortBy(_.sortedAddress.head) override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters] override def productPrefix = "TLSlavePortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => slaves case 1 => channelBytes case 2 => endSinkId case 3 => minLatency case 4 => responseFields case 5 => requestKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!slaves.isEmpty, "Slave ports must have slaves") require (endSinkId >= 0, "Sink ids cannot be negative") require (minLatency >= 0, "Minimum required latency cannot be negative") // Using this API implies you cannot handle mixed-width busses def beatBytes = { channelBytes.members.foreach { width => require (width.isDefined && width == channelBytes.a) } channelBytes.a.get } // TODO this should be deprecated def managers = slaves def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = { val relevant = slaves.filter(m => policy(m)) relevant.foreach { m => require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ") } } // Bounds on required sizes def maxAddress = slaves.map(_.maxAddress).max def maxTransfer = slaves.map(_.maxTransfer).max def mayDenyGet = slaves.exists(_.mayDenyGet) def mayDenyPut = slaves.exists(_.mayDenyPut) // Diplomatically determined operation sizes emitted by all outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _) // Operation Emitted by at least one outward Slaves // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _) val allSupportAcquireT = allSupportClaims.acquireT val allSupportAcquireB = allSupportClaims.acquireB val allSupportArithmetic = allSupportClaims.arithmetic val allSupportLogical = allSupportClaims.logical val allSupportGet = allSupportClaims.get val allSupportPutFull = allSupportClaims.putFull val allSupportPutPartial = allSupportClaims.putPartial val allSupportHint = allSupportClaims.hint // Operation supported by at least one outward Slaves // as opposed to supports* which generate circuitry to check which specific addresses val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupportClaims.acquireT.none val anySupportAcquireB = !anySupportClaims.acquireB.none val anySupportArithmetic = !anySupportClaims.arithmetic.none val anySupportLogical = !anySupportClaims.logical.none val anySupportGet = !anySupportClaims.get.none val anySupportPutFull = !anySupportClaims.putFull.none val anySupportPutPartial = !anySupportClaims.putPartial.none val anySupportHint = !anySupportClaims.hint.none // Supporting Acquire means being routable for GrantAck require ((endSinkId == 0) == !anySupportAcquireB) // These return Option[TLSlaveParameters] for your convenience def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address))) // The safe version will check the entire address def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ \|\| _))) // The fast version assumes the address is valid (you probably want fastProperty instead of this function) def findFast(address: UInt) = { val routingMask = AddressDecoder(slaves.map(_.address)) VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ \|\| _))) } // Compute the simplest AddressSets that decide a key def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = { val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) => k -> vs.flatMap(_._2) } val reductionMask = AddressDecoder(groups.map(_._2)) groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) } } // Select a property def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D = Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_\|\|_), d(v)) }) // Note: returns the actual fifoId + 1 or 0 if None def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U) def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B) // Does this Port manage this ID/address? def containsSafe(address: UInt) = findSafe(address).reduce(_ \|\| _) private def addressHelper( // setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity safe: Boolean, // member filters out the sizes being checked based on the opcode being emitted or supported member: TLSlaveParameters => TransferSizes, address: UInt, lgSize: UInt, // range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity range: Option[TransferSizes]): Bool = { // trim reduces circuit complexity by intersecting checked sizes with the range argument def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x) // groupBy returns an unordered map, convert back to Seq and sort the result for determinism // groupByIntoSeq is turning slaves into trimmed membership sizes // We are grouping all the slaves by their transfer size where // if they support the trimmed size then // member is the type of transfer that you are looking for (What you are trying to filter on) // When you consider membership, you are trimming the sizes to only the ones that you care about // you are filtering the slaves based on both whether they support a particular opcode and the size // Grouping the slaves based on the actual transfer size range they support // intersecting the range and checking their membership // FOR SUPPORTCASES instead of returning the list of slaves, // you are returning a map from transfer size to the set of // address sets that are supported for that transfer size // find all the slaves that support a certain type of operation and then group their addresses by the supported size // for every size there could be multiple address ranges // safety is a trade off between checking between all possible addresses vs only the addresses // that are known to have supported sizes // the trade off is 'checking all addresses is a more expensive circuit but will always give you // the right answer even if you give it an illegal address' // the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer // fast presumes address legality // This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies. // In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size. val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) => k -> vs.flatMap(_.address) } // safe produces a circuit that compares against all possible addresses, // whereas fast presumes that the address is legal but uses an efficient address decoder val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2)) // Simplified creates the most concise possible representation of each cases' address sets based on the mask. val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) } simplified.map { case (s, a) => // s is a size, you are checking for this size either the size of the operation is in s // We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire. ((Some(s) == range).B \|\| s.containsLg(lgSize)) && a.map(_.contains(address)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range) def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range) def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range) def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range) def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range) def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range) def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range) def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range) def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range) def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range) def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range) def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range) def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range) def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range) def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range) def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range) def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range) def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range) def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range) def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range) def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range) def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range) def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range) def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption def isTree = !slaves.exists(!_.isTree) def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString def v1copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = managers, channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } def v2copy( slaves: Seq[TLSlaveParameters] = slaves, channelBytes: TLChannelBeatBytes = channelBytes, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { new TLSlavePortParameters( slaves = slaves, channelBytes = channelBytes, endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } @deprecated("Use v1copy instead of copy","") def copy( managers: Seq[TLSlaveParameters] = slaves, beatBytes: Int = -1, endSinkId: Int = endSinkId, minLatency: Int = minLatency, responseFields: Seq[BundleFieldBase] = responseFields, requestKeys: Seq[BundleKeyBase] = requestKeys) = { v1copy( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } object TLSlavePortParameters { def v1( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { new TLSlavePortParameters( slaves = managers, channelBytes = TLChannelBeatBytes(beatBytes), endSinkId = endSinkId, minLatency = minLatency, responseFields = responseFields, requestKeys = requestKeys) } } object TLManagerPortParameters { @deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","") def apply( managers: Seq[TLSlaveParameters], beatBytes: Int, endSinkId: Int = 0, minLatency: Int = 0, responseFields: Seq[BundleFieldBase] = Nil, requestKeys: Seq[BundleKeyBase] = Nil) = { TLSlavePortParameters.v1( managers, beatBytes, endSinkId, minLatency, responseFields, requestKeys) } } class TLMasterParameters private( val nodePath: Seq[BaseNode], val resources: Seq[Resource], val name: String, val visibility: Seq[AddressSet], val unusedRegionTypes: Set[RegionType.T], val executesOnly: Boolean, val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C. val supports: TLSlaveToMasterTransferSizes, val emits: TLMasterToSlaveTransferSizes, val neverReleasesData: Boolean, val sourceId: IdRange) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters] override def productPrefix = "TLMasterParameters" // We intentionally omit nodePath for equality testing / formatting def productArity: Int = 10 def productElement(n: Int): Any = n match { case 0 => name case 1 => sourceId case 2 => resources case 3 => visibility case 4 => unusedRegionTypes case 5 => executesOnly case 6 => requestFifo case 7 => supports case 8 => emits case 9 => neverReleasesData case _ => throw new IndexOutOfBoundsException(n.toString) } require (!sourceId.isEmpty) require (!visibility.isEmpty) require (supports.putFull.contains(supports.putPartial)) // We only support these operations if we support Probe (ie: we're a cache) require (supports.probe.contains(supports.arithmetic)) require (supports.probe.contains(supports.logical)) require (supports.probe.contains(supports.get)) require (supports.probe.contains(supports.putFull)) require (supports.probe.contains(supports.putPartial)) require (supports.probe.contains(supports.hint)) visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") } val maxTransfer = List( supports.probe.max, supports.arithmetic.max, supports.logical.max, supports.get.max, supports.putFull.max, supports.putPartial.max).max def infoString = { s"""Master Name = ${name} \|visibility = ${visibility} \|emits = ${emits.infoString} \|sourceId = ${sourceId} \| \|""".stripMargin } def v1copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { new TLMasterParameters( nodePath = nodePath, resources = this.resources, name = name, visibility = visibility, unusedRegionTypes = this.unusedRegionTypes, executesOnly = this.executesOnly, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = this.emits, neverReleasesData = this.neverReleasesData, sourceId = sourceId) } def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, name: String = name, visibility: Seq[AddressSet] = visibility, unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes, executesOnly: Boolean = executesOnly, requestFifo: Boolean = requestFifo, supports: TLSlaveToMasterTransferSizes = supports, emits: TLMasterToSlaveTransferSizes = emits, neverReleasesData: Boolean = neverReleasesData, sourceId: IdRange = sourceId) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } @deprecated("Use v1copy instead of copy","") def copy( name: String = name, sourceId: IdRange = sourceId, nodePath: Seq[BaseNode] = nodePath, requestFifo: Boolean = requestFifo, visibility: Seq[AddressSet] = visibility, supportsProbe: TransferSizes = supports.probe, supportsArithmetic: TransferSizes = supports.arithmetic, supportsLogical: TransferSizes = supports.logical, supportsGet: TransferSizes = supports.get, supportsPutFull: TransferSizes = supports.putFull, supportsPutPartial: TransferSizes = supports.putPartial, supportsHint: TransferSizes = supports.hint) = { v1copy( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } object TLMasterParameters { def v1( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { new TLMasterParameters( nodePath = nodePath, resources = Nil, name = name, visibility = visibility, unusedRegionTypes = Set(), executesOnly = false, requestFifo = requestFifo, supports = TLSlaveToMasterTransferSizes( probe = supportsProbe, arithmetic = supportsArithmetic, logical = supportsLogical, get = supportsGet, putFull = supportsPutFull, putPartial = supportsPutPartial, hint = supportsHint), emits = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData = false, sourceId = sourceId) } def v2( nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Nil, name: String, visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)), unusedRegionTypes: Set[RegionType.T] = Set(), executesOnly: Boolean = false, requestFifo: Boolean = false, supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports, emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits, neverReleasesData: Boolean = false, sourceId: IdRange = IdRange(0,1)) = { new TLMasterParameters( nodePath = nodePath, resources = resources, name = name, visibility = visibility, unusedRegionTypes = unusedRegionTypes, executesOnly = executesOnly, requestFifo = requestFifo, supports = supports, emits = emits, neverReleasesData = neverReleasesData, sourceId = sourceId) } } object TLClientParameters { @deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","") def apply( name: String, sourceId: IdRange = IdRange(0,1), nodePath: Seq[BaseNode] = Seq(), requestFifo: Boolean = false, visibility: Seq[AddressSet] = Seq(AddressSet.everything), supportsProbe: TransferSizes = TransferSizes.none, supportsArithmetic: TransferSizes = TransferSizes.none, supportsLogical: TransferSizes = TransferSizes.none, supportsGet: TransferSizes = TransferSizes.none, supportsPutFull: TransferSizes = TransferSizes.none, supportsPutPartial: TransferSizes = TransferSizes.none, supportsHint: TransferSizes = TransferSizes.none) = { TLMasterParameters.v1( name = name, sourceId = sourceId, nodePath = nodePath, requestFifo = requestFifo, visibility = visibility, supportsProbe = supportsProbe, supportsArithmetic = supportsArithmetic, supportsLogical = supportsLogical, supportsGet = supportsGet, supportsPutFull = supportsPutFull, supportsPutPartial = supportsPutPartial, supportsHint = supportsHint) } } class TLMasterPortParameters private( val masters: Seq[TLMasterParameters], val channelBytes: TLChannelBeatBytes, val minLatency: Int, val echoFields: Seq[BundleFieldBase], val requestFields: Seq[BundleFieldBase], val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct { override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters] override def productPrefix = "TLMasterPortParameters" def productArity: Int = 6 def productElement(n: Int): Any = n match { case 0 => masters case 1 => channelBytes case 2 => minLatency case 3 => echoFields case 4 => requestFields case 5 => responseKeys case _ => throw new IndexOutOfBoundsException(n.toString) } require (!masters.isEmpty) require (minLatency >= 0) def clients = masters // Require disjoint ranges for Ids IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) => require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}") } // Bounds on required sizes def endSourceId = masters.map(_.sourceId.end).max def maxTransfer = masters.map(_.maxTransfer).max // The unused sources < endSourceId def unusedSources: Seq[Int] = { val usedSources = masters.map(_.sourceId).sortBy(_.start) ((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) => end until start } } // Diplomatically determined operation sizes emitted by all inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val allEmitClaims = masters.map(_.emits).reduce( _ intersect _) // Diplomatically determined operation sizes Emitted by at least one inward Masters // as opposed to emits* which generate circuitry to check which specific addresses val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _) // Diplomatically determined operation sizes supported by all inward Masters // as opposed to supports* which generate circuitry to check which specific addresses val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _) val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _) val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _) val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _) val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _) val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _) val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _) // Diplomatically determined operation sizes supported by at least one master // as opposed to supports* which generate circuitry to check which specific addresses val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ \|\| _) val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ \|\| _) val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ \|\| _) val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ \|\| _) val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ \|\| _) val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ \|\| _) val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ \|\| _) // These return Option[TLMasterParameters] for your convenience def find(id: Int) = masters.find(_.sourceId.contains(id)) // Synthesizable lookup methods def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id))) def contains(id: UInt) = find(id).reduce(_ \|\| _) def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B)) // Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = { val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _) // this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version; // the case where there is only one group. if (allSame) member(masters(0)).containsLg(lgSize) else { // Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize Mux1H(find(id), masters.map(member(_).containsLg(lgSize))) } } // Check for support of a given operation at a specific id val supportsProbe = sourceIdHelper(_.supports.probe) _ val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _ val supportsLogical = sourceIdHelper(_.supports.logical) _ val supportsGet = sourceIdHelper(_.supports.get) _ val supportsPutFull = sourceIdHelper(_.supports.putFull) _ val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _ val supportsHint = sourceIdHelper(_.supports.hint) _ // TODO: Merge sourceIdHelper2 with sourceIdHelper private def sourceIdHelper2( member: TLMasterParameters => TransferSizes, sourceId: UInt, lgSize: UInt): Bool = { // Because sourceIds are uniquely owned by each master, we use them to group the // cases that have to be checked. val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) => k -> vs.map(_.sourceId) } emitCases.map { case (s, a) => (s.containsLg(lgSize)) && a.map(_.contains(sourceId)).reduce(_\|\|_) }.foldLeft(false.B)(_\|\|_) } // Check for emit of a given operation at a specific id def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize) def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize) def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize) def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize) def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize) def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize) def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize) def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize) def infoString = masters.map(_.infoString).mkString def v1copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = clients, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2copy( masters: Seq[TLMasterParameters] = masters, channelBytes: TLChannelBeatBytes = channelBytes, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } @deprecated("Use v1copy instead of copy","") def copy( clients: Seq[TLMasterParameters] = masters, minLatency: Int = minLatency, echoFields: Seq[BundleFieldBase] = echoFields, requestFields: Seq[BundleFieldBase] = requestFields, responseKeys: Seq[BundleKeyBase] = responseKeys) = { v1copy( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLClientPortParameters { @deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","") def apply( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { TLMasterPortParameters.v1( clients, minLatency, echoFields, requestFields, responseKeys) } } object TLMasterPortParameters { def v1( clients: Seq[TLMasterParameters], minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = clients, channelBytes = TLChannelBeatBytes(), minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } def v2( masters: Seq[TLMasterParameters], channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(), minLatency: Int = 0, echoFields: Seq[BundleFieldBase] = Nil, requestFields: Seq[BundleFieldBase] = Nil, responseKeys: Seq[BundleKeyBase] = Nil) = { new TLMasterPortParameters( masters = masters, channelBytes = channelBytes, minLatency = minLatency, echoFields = echoFields, requestFields = requestFields, responseKeys = responseKeys) } } case class TLBundleParameters( addressBits: Int, dataBits: Int, sourceBits: Int, sinkBits: Int, sizeBits: Int, echoFields: Seq[BundleFieldBase], requestFields: Seq[BundleFieldBase], responseFields: Seq[BundleFieldBase], hasBCE: Boolean) { // Chisel has issues with 0-width wires require (addressBits >= 1) require (dataBits >= 8) require (sourceBits >= 1) require (sinkBits >= 1) require (sizeBits >= 1) require (isPow2(dataBits)) echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") } val addrLoBits = log2Up(dataBits/8) // Used to uniquify bus IP names def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u") def union(x: TLBundleParameters) = TLBundleParameters( max(addressBits, x.addressBits), max(dataBits, x.dataBits), max(sourceBits, x.sourceBits), max(sinkBits, x.sinkBits), max(sizeBits, x.sizeBits), echoFields = BundleField.union(echoFields ++ x.echoFields), requestFields = BundleField.union(requestFields ++ x.requestFields), responseFields = BundleField.union(responseFields ++ x.responseFields), hasBCE \|\| x.hasBCE) } object TLBundleParameters { val emptyBundleParams = TLBundleParameters( addressBits = 1, dataBits = 8, sourceBits = 1, sinkBits = 1, sizeBits = 1, echoFields = Nil, requestFields = Nil, responseFields = Nil, hasBCE = false) def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y)) def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) = new TLBundleParameters( addressBits = log2Up(slave.maxAddress + 1), dataBits = slave.beatBytes * 8, sourceBits = log2Up(master.endSourceId), sinkBits = log2Up(slave.endSinkId), sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1), echoFields = master.echoFields, requestFields = BundleField.accept(master.requestFields, slave.requestKeys), responseFields = BundleField.accept(slave.responseFields, master.responseKeys), hasBCE = master.anySupportProbe && slave.anySupportAcquireB) } case class TLEdgeParameters( master: TLMasterPortParameters, slave: TLSlavePortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { // legacy names: def manager = slave def client = master val maxTransfer = max(master.maxTransfer, slave.maxTransfer) val maxLgSize = log2Ceil(maxTransfer) // Sanity check the link... require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})") def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims) val bundle = TLBundleParameters(master, slave) def formatEdge = master.infoString + "\n" + slave.infoString } case class TLCreditedDelay( a: CreditedDelay, b: CreditedDelay, c: CreditedDelay, d: CreditedDelay, e: CreditedDelay) { def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay( a = a + that.a, b = b + that.b, c = c + that.c, d = d + that.d, e = e + that.e) override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})" } object TLCreditedDelay { def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay) } case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString} case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val delay = client.delay + manager.delay val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters) case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base)) def formatEdge = client.infoString + "\n" + manager.infoString } case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString} case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString} case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge { val bundle = TLBundleParameters(client.base, manager.base) def formatEdge = client.infoString + "\n" + manager.infoString } // To be unified, devices must agree on all of these terms case class ManagerUnificationKey( resources: Seq[Resource], regionType: RegionType.T, executable: Boolean, supportsAcquireT: TransferSizes, supportsAcquireB: TransferSizes, supportsArithmetic: TransferSizes, supportsLogical: TransferSizes, supportsGet: TransferSizes, supportsPutFull: TransferSizes, supportsPutPartial: TransferSizes, supportsHint: TransferSizes) object ManagerUnificationKey { def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey( resources = x.resources, regionType = x.regionType, executable = x.executable, supportsAcquireT = x.supportsAcquireT, supportsAcquireB = x.supportsAcquireB, supportsArithmetic = x.supportsArithmetic, supportsLogical = x.supportsLogical, supportsGet = x.supportsGet, supportsPutFull = x.supportsPutFull, supportsPutPartial = x.supportsPutPartial, supportsHint = x.supportsHint) } object ManagerUnification { def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = { slaves.groupBy(ManagerUnificationKey.apply).values.map { seq => val agree = seq.forall(_.fifoId == seq.head.fifoId) seq(0).v1copy( address = AddressSet.unify(seq.flatMap(_.address)), fifoId = if (agree) seq(0).fifoId else None) }.toList } } case class TLBufferParams( a: BufferParams = BufferParams.none, b: BufferParams = BufferParams.none, c: BufferParams = BufferParams.none, d: BufferParams = BufferParams.none, e: BufferParams = BufferParams.none ) extends DirectedBuffers[TLBufferParams] { def copyIn(x: BufferParams) = this.copy(b = x, d = x) def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x) def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x) } /** Pretty printing of TL source id maps / class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] { private val tlDigits = String.valueOf(tl.endSourceId-1).length() protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s" private val sorted = tl.masters.sortBy(_.sourceId) val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c => TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo) } } case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = tlId val maxTransactionsInFlight = Some(tlId.size) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_78( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46] wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7] wire [3:0] mask = 4'hF; // @[Misc.scala:222:10] wire [31:0] io_in_d_bits_data = 32'h0; // @[Monitor.scala:36:7] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_wo_ready_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [127:0] _is_aligned_T = {126'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 128'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire _T_607 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_607; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_607; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [127:0] address; // @[Monitor.scala:391:22] wire _T_675 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_675; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_675; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_675; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_537 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_537; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_537; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_607 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_586 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_586 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_675 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] wire [3:0] _GEN_1 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_opcodes_clr = _GEN_1; // @[Monitor.scala:668:33, :678:89, :680:21] assign d_sizes_clr = _GEN_1; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] \| a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes \| a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes \| a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_651 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_651 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_675 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] wire [3:0] _GEN_2 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_opcodes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :788:88, :790:21] assign d_sizes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File SwitchAllocator.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ class SwitchAllocReq(val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams]) (implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val tail = Bool() } class SwitchArbiter(inN: Int, outN: Int, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Module { val io = IO(new Bundle { val in = Flipped(Vec(inN, Decoupled(new SwitchAllocReq(outParams, egressParams)))) val out = Vec(outN, Decoupled(new SwitchAllocReq(outParams, egressParams))) val chosen_oh = Vec(outN, Output(UInt(inN.W))) }) val lock = Seq.fill(outN) { RegInit(0.U(inN.W)) } val unassigned = Cat(io.in.map(_.valid).reverse) & ~(lock.reduce(_\|_)) val mask = RegInit(0.U(inN.W)) val choices = Wire(Vec(outN, UInt(inN.W))) var sel = PriorityEncoderOH(Cat(unassigned, unassigned & ~mask)) for (i <- 0 until outN) { choices(i) := sel \| (sel >> inN) sel = PriorityEncoderOH(unassigned & ~choices(i)) } io.in.foreach(_.ready := false.B) var chosens = 0.U(inN.W) val in_tails = Cat(io.in.map(_.bits.tail).reverse) for (i <- 0 until outN) { val in_valids = Cat((0 until inN).map { j => io.in(j).valid && !chosens(j) }.reverse) val chosen = Mux((in_valids & lock(i) & ~chosens).orR, lock(i), choices(i)) io.chosen_oh(i) := chosen io.out(i).valid := (in_valids & chosen).orR io.out(i).bits := Mux1H(chosen, io.in.map(_.bits)) for (j <- 0 until inN) { when (chosen(j) && io.out(i).ready) { io.in(j).ready := true.B } } chosens = chosens \| chosen when (io.out(i).fire) { lock(i) := chosen & ~in_tails } } when (io.out(0).fire) { mask := (0 until inN).map { i => (io.chosen_oh(0) >> i) }.reduce(_\|_) } .otherwise { mask := Mux(~mask === 0.U, 0.U, (mask << 1) \| 1.U(1.W)) } } class SwitchAllocator( val routerParams: RouterParams, val inParams: Seq[ChannelParams], val outParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterParams with HasRouterInputParams with HasRouterOutputParams { val io = IO(new Bundle { val req = MixedVec(allInParams.map(u => Vec(u.destSpeedup, Flipped(Decoupled(new SwitchAllocReq(outParams, egressParams)))))) val credit_alloc = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Output(new OutputCreditAlloc))}) val switch_sel = MixedVec(allOutParams.map { o => Vec(o.srcSpeedup, MixedVec(allInParams.map { i => Vec(i.destSpeedup, Output(Bool())) })) }) }) val nInputChannels = allInParams.map(_.nVirtualChannels).sum val arbs = allOutParams.map { oP => Module(new SwitchArbiter( allInParams.map(_.destSpeedup).reduce(_+_), oP.srcSpeedup, outParams, egressParams ))} arbs.foreach(_.io.out.foreach(_.ready := true.B)) var idx = 0 io.req.foreach(_.foreach { o => val fires = Wire(Vec(arbs.size, Bool())) arbs.zipWithIndex.foreach { case (a,i) => a.io.in(idx).valid := o.valid && o.bits.vc_sel(i).reduce(_\|\|_) a.io.in(idx).bits := o.bits fires(i) := a.io.in(idx).fire } o.ready := fires.reduce(_\|\|_) idx += 1 }) for (i <- 0 until nAllOutputs) { for (j <- 0 until allOutParams(i).srcSpeedup) { idx = 0 for (m <- 0 until nAllInputs) { for (n <- 0 until allInParams(m).destSpeedup) { io.switch_sel(i)(j)(m)(n) := arbs(i).io.in(idx).valid && arbs(i).io.chosen_oh(j)(idx) && arbs(i).io.out(j).valid idx += 1 } } } } io.credit_alloc.foreach(_.foreach(_.alloc := false.B)) io.credit_alloc.foreach(_.foreach(_.tail := false.B)) (arbs zip io.credit_alloc).zipWithIndex.map { case ((a,i),t) => for (j <- 0 until i.size) { for (k <- 0 until a.io.out.size) { when (a.io.out(k).valid && a.io.out(k).bits.vc_sel(t)(j)) { i(j).alloc := true.B i(j).tail := a.io.out(k).bits.tail } } } } }	module SwitchArbiter_330( // @[SwitchAllocator.scala:17:7] input clock, // @[SwitchAllocator.scala:17:7] input reset, // @[SwitchAllocator.scala:17:7] output io_in_0_ready, // @[SwitchAllocator.scala:18:14] input io_in_0_valid, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_8, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_9, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_8, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_9, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_1_ready, // @[SwitchAllocator.scala:18:14] input io_in_1_valid, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_8, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_9, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_8, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_9, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_tail, // @[SwitchAllocator.scala:18:14] output io_out_0_valid, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_8, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_9, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_8, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_9, // @[SwitchAllocator.scala:18:14] output [1:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14] ); reg [1:0] lock_0; // @[SwitchAllocator.scala:24:38] wire [1:0] unassigned = {io_in_1_valid, io_in_0_valid} & ~lock_0; // @[SwitchAllocator.scala:24:38, :25:{23,52,54}] reg [1:0] mask; // @[SwitchAllocator.scala:27:21] wire [1:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}] wire [3:0] sel = _sel_T_1[0] ? 4'h1 : _sel_T_1[1] ? 4'h2 : unassigned[0] ? 4'h4 : {unassigned[1], 3'h0}; // @[OneHot.scala:85:71] wire [1:0] in_valids = {io_in_1_valid, io_in_0_valid}; // @[SwitchAllocator.scala:41:24] wire [1:0] chosen = (\|(in_valids & lock_0)) ? lock_0 : sel[1:0] \| sel[3:2]; // @[Mux.scala:50:70] wire [1:0] _io_out_0_valid_T = in_valids & chosen; // @[SwitchAllocator.scala:41:24, :42:21, :44:35] always @(posedge clock) begin // @[SwitchAllocator.scala:17:7] if (reset) begin // @[SwitchAllocator.scala:17:7] lock_0 <= 2'h0; // @[SwitchAllocator.scala:24:38] mask <= 2'h0; // @[SwitchAllocator.scala:27:21] end else begin // @[SwitchAllocator.scala:17:7] if (\|_io_out_0_valid_T) // @[SwitchAllocator.scala:44:{35,45}] lock_0 <= chosen & ~{io_in_1_bits_tail, io_in_0_bits_tail}; // @[SwitchAllocator.scala:24:38, :39:21, :42:21, :53:{25,27}] mask <= (\|_io_out_0_valid_T) ? {chosen[1], \|chosen} : (&mask) ? 2'h0 : {mask[0], 1'h1}; // @[SwitchAllocator.scala:17:7, :27:21, :42:21, :44:{35,45}, :57:25, :58:{10,71}, :60:{10,16,23,49}] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File MulAddRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ import consts._ //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN_interIo(expWidth: Int, sigWidth: Int) extends Bundle { //*** ENCODE SOME OF THESE CASES IN FEWER BITS?: val isSigNaNAny = Bool() val isNaNAOrB = Bool() val isInfA = Bool() val isZeroA = Bool() val isInfB = Bool() val isZeroB = Bool() val signProd = Bool() val isNaNC = Bool() val isInfC = Bool() val isZeroC = Bool() val sExpSum = SInt((expWidth + 2).W) val doSubMags = Bool() val CIsDominant = Bool() val CDom_CAlignDist = UInt(log2Ceil(sigWidth + 1).W) val highAlignedSigC = UInt((sigWidth + 2).W) val bit0AlignedSigC = UInt(1.W) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_preMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_preMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val mulAddA = Output(UInt(sigWidth.W)) val mulAddB = Output(UInt(sigWidth.W)) val mulAddC = Output(UInt((sigWidth * 2).W)) val toPostMul = Output(new MulAddRecFN_interIo(expWidth, sigWidth)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ //* POSSIBLE TO REDUCE THIS BY 1 OR 2 BITS? (CURRENTLY 2 BITS BETWEEN //* UNSHIFTED C AND PRODUCT): val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawA = rawFloatFromRecFN(expWidth, sigWidth, io.a) val rawB = rawFloatFromRecFN(expWidth, sigWidth, io.b) val rawC = rawFloatFromRecFN(expWidth, sigWidth, io.c) val signProd = rawA.sign ^ rawB.sign ^ io.op(1) //* REVIEW THE BIAS FOR 'sExpAlignedProd': val sExpAlignedProd = rawA.sExp +& rawB.sExp + (-(BigInt(1)<<expWidth) + sigWidth + 3).S val doSubMags = signProd ^ rawC.sign ^ io.op(0) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sNatCAlignDist = sExpAlignedProd - rawC.sExp val posNatCAlignDist = sNatCAlignDist(expWidth + 1, 0) val isMinCAlign = rawA.isZero \|\| rawB.isZero \|\| (sNatCAlignDist < 0.S) val CIsDominant = ! rawC.isZero && (isMinCAlign \|\| (posNatCAlignDist <= sigWidth.U)) val CAlignDist = Mux(isMinCAlign, 0.U, Mux(posNatCAlignDist < (sigSumWidth - 1).U, posNatCAlignDist(log2Ceil(sigSumWidth) - 1, 0), (sigSumWidth - 1).U ) ) val mainAlignedSigC = (Mux(doSubMags, ~rawC.sig, rawC.sig) ## Fill(sigSumWidth - sigWidth + 2, doSubMags)).asSInt>>CAlignDist val reduced4CExtra = (orReduceBy4(rawC.sig<<((sigSumWidth - sigWidth - 1) & 3)) & lowMask( CAlignDist>>2, //* NOT NEEDED?: // (sigSumWidth + 2)>>2, (sigSumWidth - 1)>>2, (sigSumWidth - sigWidth - 1)>>2 ) ).orR val alignedSigC = Cat(mainAlignedSigC>>3, Mux(doSubMags, mainAlignedSigC(2, 0).andR && ! reduced4CExtra, mainAlignedSigC(2, 0).orR \|\| reduced4CExtra ) ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ io.mulAddA := rawA.sig io.mulAddB := rawB.sig io.mulAddC := alignedSigC(sigWidth * 2, 1) io.toPostMul.isSigNaNAny := isSigNaNRawFloat(rawA) \|\| isSigNaNRawFloat(rawB) \|\| isSigNaNRawFloat(rawC) io.toPostMul.isNaNAOrB := rawA.isNaN \|\| rawB.isNaN io.toPostMul.isInfA := rawA.isInf io.toPostMul.isZeroA := rawA.isZero io.toPostMul.isInfB := rawB.isInf io.toPostMul.isZeroB := rawB.isZero io.toPostMul.signProd := signProd io.toPostMul.isNaNC := rawC.isNaN io.toPostMul.isInfC := rawC.isInf io.toPostMul.isZeroC := rawC.isZero io.toPostMul.sExpSum := Mux(CIsDominant, rawC.sExp, sExpAlignedProd - sigWidth.S) io.toPostMul.doSubMags := doSubMags io.toPostMul.CIsDominant := CIsDominant io.toPostMul.CDom_CAlignDist := CAlignDist(log2Ceil(sigWidth + 1) - 1, 0) io.toPostMul.highAlignedSigC := alignedSigC(sigSumWidth - 1, sigWidth * 2 + 1) io.toPostMul.bit0AlignedSigC := alignedSigC(0) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFNToRaw_postMul(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFNToRaw_postMul_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val fromPreMul = Input(new MulAddRecFN_interIo(expWidth, sigWidth)) val mulAddResult = Input(UInt((sigWidth * 2 + 1).W)) val roundingMode = Input(UInt(3.W)) val invalidExc = Output(Bool()) val rawOut = Output(new RawFloat(expWidth, sigWidth + 2)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val sigSumWidth = sigWidth * 3 + 3 //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundingMode_min = (io.roundingMode === round_min) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val opSignC = io.fromPreMul.signProd ^ io.fromPreMul.doSubMags val sigSum = Cat(Mux(io.mulAddResult(sigWidth * 2), io.fromPreMul.highAlignedSigC + 1.U, io.fromPreMul.highAlignedSigC ), io.mulAddResult(sigWidth * 2 - 1, 0), io.fromPreMul.bit0AlignedSigC ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val CDom_sign = opSignC val CDom_sExp = io.fromPreMul.sExpSum - io.fromPreMul.doSubMags.zext val CDom_absSigSum = Mux(io.fromPreMul.doSubMags, ~sigSum(sigSumWidth - 1, sigWidth + 1), 0.U(1.W) ## //*** IF GAP IS REDUCED TO 1 BIT, MUST REDUCE THIS COMPONENT TO 1 BIT TOO: io.fromPreMul.highAlignedSigC(sigWidth + 1, sigWidth) ## sigSum(sigSumWidth - 3, sigWidth + 2) ) val CDom_absSigSumExtra = Mux(io.fromPreMul.doSubMags, (~sigSum(sigWidth, 1)).orR, sigSum(sigWidth + 1, 1).orR ) val CDom_mainSig = (CDom_absSigSum<<io.fromPreMul.CDom_CAlignDist)( sigWidth * 2 + 1, sigWidth - 3) val CDom_reduced4SigExtra = (orReduceBy4(CDom_absSigSum(sigWidth - 1, 0)<<(~sigWidth & 3)) & lowMask(io.fromPreMul.CDom_CAlignDist>>2, 0, sigWidth>>2)).orR val CDom_sig = Cat(CDom_mainSig>>3, CDom_mainSig(2, 0).orR \|\| CDom_reduced4SigExtra \|\| CDom_absSigSumExtra ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notCDom_signSigSum = sigSum(sigWidth * 2 + 3) val notCDom_absSigSum = Mux(notCDom_signSigSum, ~sigSum(sigWidth * 2 + 2, 0), sigSum(sigWidth * 2 + 2, 0) + io.fromPreMul.doSubMags ) val notCDom_reduced2AbsSigSum = orReduceBy2(notCDom_absSigSum) val notCDom_normDistReduced2 = countLeadingZeros(notCDom_reduced2AbsSigSum) val notCDom_nearNormDist = notCDom_normDistReduced2<<1 val notCDom_sExp = io.fromPreMul.sExpSum - notCDom_nearNormDist.asUInt.zext val notCDom_mainSig = (notCDom_absSigSum<<notCDom_nearNormDist)( sigWidth * 2 + 3, sigWidth - 1) val notCDom_reduced4SigExtra = (orReduceBy2( notCDom_reduced2AbsSigSum(sigWidth>>1, 0)<<((sigWidth>>1) & 1)) & lowMask(notCDom_normDistReduced2>>1, 0, (sigWidth + 2)>>2) ).orR val notCDom_sig = Cat(notCDom_mainSig>>3, notCDom_mainSig(2, 0).orR \|\| notCDom_reduced4SigExtra ) val notCDom_completeCancellation = (notCDom_sig(sigWidth + 2, sigWidth + 1) === 0.U) val notCDom_sign = Mux(notCDom_completeCancellation, roundingMode_min, io.fromPreMul.signProd ^ notCDom_signSigSum ) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val notNaN_isInfProd = io.fromPreMul.isInfA \|\| io.fromPreMul.isInfB val notNaN_isInfOut = notNaN_isInfProd \|\| io.fromPreMul.isInfC val notNaN_addZeros = (io.fromPreMul.isZeroA \|\| io.fromPreMul.isZeroB) && io.fromPreMul.isZeroC io.invalidExc := io.fromPreMul.isSigNaNAny \|\| (io.fromPreMul.isInfA && io.fromPreMul.isZeroB) \|\| (io.fromPreMul.isZeroA && io.fromPreMul.isInfB) \|\| (! io.fromPreMul.isNaNAOrB && (io.fromPreMul.isInfA \|\| io.fromPreMul.isInfB) && io.fromPreMul.isInfC && io.fromPreMul.doSubMags) io.rawOut.isNaN := io.fromPreMul.isNaNAOrB \|\| io.fromPreMul.isNaNC io.rawOut.isInf := notNaN_isInfOut //*** IMPROVE?: io.rawOut.isZero := notNaN_addZeros \|\| (! io.fromPreMul.CIsDominant && notCDom_completeCancellation) io.rawOut.sign := (notNaN_isInfProd && io.fromPreMul.signProd) \|\| (io.fromPreMul.isInfC && opSignC) \|\| (notNaN_addZeros && ! roundingMode_min && io.fromPreMul.signProd && opSignC) \|\| (notNaN_addZeros && roundingMode_min && (io.fromPreMul.signProd \|\| opSignC)) \|\| (! notNaN_isInfOut && ! notNaN_addZeros && Mux(io.fromPreMul.CIsDominant, CDom_sign, notCDom_sign)) io.rawOut.sExp := Mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) io.rawOut.sig := Mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) } //---------------------------------------------------------------------------- //---------------------------------------------------------------------------- class MulAddRecFN(expWidth: Int, sigWidth: Int) extends RawModule { override def desiredName = s"MulAddRecFN_e${expWidth}_s${sigWidth}" val io = IO(new Bundle { val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC mulAddRecFNToRaw_postMul.io.fromPreMul := mulAddRecFNToRaw_preMul.io.toPostMul mulAddRecFNToRaw_postMul.io.mulAddResult := mulAddResult mulAddRecFNToRaw_postMul.io.roundingMode := io.roundingMode //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0)) roundRawFNToRecFN.io.invalidExc := mulAddRecFNToRaw_postMul.io.invalidExc roundRawFNToRecFN.io.infiniteExc := false.B roundRawFNToRecFN.io.in := mulAddRecFNToRaw_postMul.io.rawOut roundRawFNToRecFN.io.roundingMode := io.roundingMode roundRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags }	module MulAddRecFN_e8_s24_28( // @[MulAddRecFN.scala:300:7] input [32:0] io_a, // @[MulAddRecFN.scala:303:16] input [32:0] io_c, // @[MulAddRecFN.scala:303:16] output [32:0] io_out // @[MulAddRecFN.scala:303:16] ); wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15] wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15] wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15] wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15] wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[MulAddRecFN.scala:317:15] wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[MulAddRecFN.scala:317:15] wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15] wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15] wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7] wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:300:7] wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :339:15] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15] wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7] wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7] wire [47:0] _mulAddResult_T = {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddA, 23'h0}; // @[MulAddRecFN.scala:317:15, :327:45] wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50] MulAddRecFNToRaw_preMul_e8_s24_28 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15] .io_a (io_a_0), // @[MulAddRecFN.scala:300:7] .io_c (io_c_0), // @[MulAddRecFN.scala:300:7] .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA), .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) ); // @[MulAddRecFN.scala:317:15] MulAddRecFNToRaw_postMul_e8_s24_28 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15] .io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15] .io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) ); // @[MulAddRecFN.scala:319:15] RoundRawFNToRecFN_e8_s24_43 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15] .io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15] .io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15] .io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15] .io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15] .io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15] .io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulAddRecFN.scala:339:15] assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_23( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [10:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [10:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1039:0] inflight; // @[Monitor.scala:614:27] reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire [2047:0] _GEN = {2037'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_0 = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [2047:0] _GEN_2 = {2037'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1039:0] inflight_1; // @[Monitor.scala:726:35] reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to the following Chisel files. File RecFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import consts._ class RecFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val in = Input(Bits((inExpWidth + inSigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in); if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- io.out := io.in<<(outSigWidth - inSigWidth) io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W) } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( inExpWidth, inSigWidth, outExpWidth, outSigWidth, flRoundOpt_sigMSBitAlwaysZero )) roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn) roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := rawIn roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } } File rawFloatFromRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ /---------------------------------------------------------------------------- \| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be \| set. ----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }	module RecFNToRecFN_145( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File tage.scala: package boom.v3.ifu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import boom.v3.common._ import boom.v3.util.{BoomCoreStringPrefix, MaskLower, WrapInc} import scala.math.min class TageResp extends Bundle { val ctr = UInt(3.W) val u = UInt(2.W) } class TageTable(val nRows: Int, val tagSz: Int, val histLength: Int, val uBitPeriod: Int) (implicit p: Parameters) extends BoomModule()(p) with HasBoomFrontendParameters { require(histLength <= globalHistoryLength) val nWrBypassEntries = 2 val io = IO( new Bundle { val f1_req_valid = Input(Bool()) val f1_req_pc = Input(UInt(vaddrBitsExtended.W)) val f1_req_ghist = Input(UInt(globalHistoryLength.W)) val f3_resp = Output(Vec(bankWidth, Valid(new TageResp))) val update_mask = Input(Vec(bankWidth, Bool())) val update_taken = Input(Vec(bankWidth, Bool())) val update_alloc = Input(Vec(bankWidth, Bool())) val update_old_ctr = Input(Vec(bankWidth, UInt(3.W))) val update_pc = Input(UInt()) val update_hist = Input(UInt()) val update_u_mask = Input(Vec(bankWidth, Bool())) val update_u = Input(Vec(bankWidth, UInt(2.W))) }) def compute_folded_hist(hist: UInt, l: Int) = { val nChunks = (histLength + l - 1) / l val hist_chunks = (0 until nChunks) map {i => hist(min((i+1)l, histLength)-1, il) } hist_chunks.reduce(_^_) } def compute_tag_and_hash(unhashed_idx: UInt, hist: UInt) = { val idx_history = compute_folded_hist(hist, log2Ceil(nRows)) val idx = (unhashed_idx ^ idx_history)(log2Ceil(nRows)-1,0) val tag_history = compute_folded_hist(hist, tagSz) val tag = ((unhashed_idx >> log2Ceil(nRows)) ^ tag_history)(tagSz-1,0) (idx, tag) } def inc_ctr(ctr: UInt, taken: Bool): UInt = { Mux(!taken, Mux(ctr === 0.U, 0.U, ctr - 1.U), Mux(ctr === 7.U, 7.U, ctr + 1.U)) } val doing_reset = RegInit(true.B) val reset_idx = RegInit(0.U(log2Ceil(nRows).W)) reset_idx := reset_idx + doing_reset when (reset_idx === (nRows-1).U) { doing_reset := false.B } class TageEntry extends Bundle { val valid = Bool() // TODO: Remove this valid bit val tag = UInt(tagSz.W) val ctr = UInt(3.W) } val tageEntrySz = 1 + tagSz + 3 val (s1_hashed_idx, s1_tag) = compute_tag_and_hash(fetchIdx(io.f1_req_pc), io.f1_req_ghist) val hi_us = SyncReadMem(nRows, Vec(bankWidth, Bool())) val lo_us = SyncReadMem(nRows, Vec(bankWidth, Bool())) val table = SyncReadMem(nRows, Vec(bankWidth, UInt(tageEntrySz.W))) val mems = Seq((f"tage_l$histLength", nRows, bankWidth * tageEntrySz)) val s2_tag = RegNext(s1_tag) val s2_req_rtage = VecInit(table.read(s1_hashed_idx, io.f1_req_valid).map(_.asTypeOf(new TageEntry))) val s2_req_rhius = hi_us.read(s1_hashed_idx, io.f1_req_valid) val s2_req_rlous = lo_us.read(s1_hashed_idx, io.f1_req_valid) val s2_req_rhits = VecInit(s2_req_rtage.map(e => e.valid && e.tag === s2_tag && !doing_reset)) for (w <- 0 until bankWidth) { // This bit indicates the TAGE table matched here io.f3_resp(w).valid := RegNext(s2_req_rhits(w)) io.f3_resp(w).bits.u := RegNext(Cat(s2_req_rhius(w), s2_req_rlous(w))) io.f3_resp(w).bits.ctr := RegNext(s2_req_rtage(w).ctr) } val clear_u_ctr = RegInit(0.U((log2Ceil(uBitPeriod) + log2Ceil(nRows) + 1).W)) when (doing_reset) { clear_u_ctr := 1.U } .otherwise { clear_u_ctr := clear_u_ctr + 1.U } val doing_clear_u = clear_u_ctr(log2Ceil(uBitPeriod)-1,0) === 0.U val doing_clear_u_hi = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 1.U val doing_clear_u_lo = doing_clear_u && clear_u_ctr(log2Ceil(uBitPeriod) + log2Ceil(nRows)) === 0.U val clear_u_idx = clear_u_ctr >> log2Ceil(uBitPeriod) val (update_idx, update_tag) = compute_tag_and_hash(fetchIdx(io.update_pc), io.update_hist) val update_wdata = Wire(Vec(bankWidth, new TageEntry)) table.write( Mux(doing_reset, reset_idx , update_idx), Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(tageEntrySz.W) }), VecInit(update_wdata.map(_.asUInt))), Mux(doing_reset, ~(0.U(bankWidth.W)) , io.update_mask.asUInt).asBools ) val update_hi_wdata = Wire(Vec(bankWidth, Bool())) hi_us.write( Mux(doing_reset, reset_idx, Mux(doing_clear_u_hi, clear_u_idx, update_idx)), Mux(doing_reset \|\| doing_clear_u_hi, VecInit((0.U(bankWidth.W)).asBools), update_hi_wdata), Mux(doing_reset \|\| doing_clear_u_hi, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools ) val update_lo_wdata = Wire(Vec(bankWidth, Bool())) lo_us.write( Mux(doing_reset, reset_idx, Mux(doing_clear_u_lo, clear_u_idx, update_idx)), Mux(doing_reset \|\| doing_clear_u_lo, VecInit((0.U(bankWidth.W)).asBools), update_lo_wdata), Mux(doing_reset \|\| doing_clear_u_lo, ~(0.U(bankWidth.W)), io.update_u_mask.asUInt).asBools ) val wrbypass_tags = Reg(Vec(nWrBypassEntries, UInt(tagSz.W))) val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nRows).W))) val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(3.W)))) val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W)) val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i => !doing_reset && wrbypass_tags(i) === update_tag && wrbypass_idxs(i) === update_idx }) val wrbypass_hit = wrbypass_hits.reduce(_\|\|_) val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits) for (w <- 0 until bankWidth) { update_wdata(w).ctr := Mux(io.update_alloc(w), Mux(io.update_taken(w), 4.U, 3.U ), Mux(wrbypass_hit, inc_ctr(wrbypass(wrbypass_hit_idx)(w), io.update_taken(w)), inc_ctr(io.update_old_ctr(w), io.update_taken(w)) ) ) update_wdata(w).valid := true.B update_wdata(w).tag := update_tag update_hi_wdata(w) := io.update_u(w)(1) update_lo_wdata(w) := io.update_u(w)(0) } when (io.update_mask.reduce(_\|\|_)) { when (wrbypass_hits.reduce(_\|\|_)) { wrbypass(wrbypass_hit_idx) := VecInit(update_wdata.map(_.ctr)) } .otherwise { wrbypass (wrbypass_enq_idx) := VecInit(update_wdata.map(_.ctr)) wrbypass_tags(wrbypass_enq_idx) := update_tag wrbypass_idxs(wrbypass_enq_idx) := update_idx wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries) } } } case class BoomTageParams( // nSets, histLen, tagSz tableInfo: Seq[Tuple3[Int, Int, Int]] = Seq(( 128, 2, 7), ( 128, 4, 7), ( 256, 8, 8), ( 256, 16, 8), ( 128, 32, 9), ( 128, 64, 9)), uBitPeriod: Int = 2048 ) class TageBranchPredictorBank(params: BoomTageParams = BoomTageParams())(implicit p: Parameters) extends BranchPredictorBank()(p) { val tageUBitPeriod = params.uBitPeriod val tageNTables = params.tableInfo.size class TageMeta extends Bundle { val provider = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W))) val alt_differs = Vec(bankWidth, Output(Bool())) val provider_u = Vec(bankWidth, Output(UInt(2.W))) val provider_ctr = Vec(bankWidth, Output(UInt(3.W))) val allocate = Vec(bankWidth, Valid(UInt(log2Ceil(tageNTables).W))) } val f3_meta = Wire(new TageMeta) override val metaSz = f3_meta.asUInt.getWidth require(metaSz <= bpdMaxMetaLength) def inc_u(u: UInt, alt_differs: Bool, mispredict: Bool): UInt = { Mux(!alt_differs, u, Mux(mispredict, Mux(u === 0.U, 0.U, u - 1.U), Mux(u === 3.U, 3.U, u + 1.U))) } val tt = params.tableInfo map { case (n, l, s) => { val t = Module(new TageTable(n, s, l, params.uBitPeriod)) t.io.f1_req_valid := RegNext(io.f0_valid) t.io.f1_req_pc := RegNext(io.f0_pc) t.io.f1_req_ghist := io.f1_ghist (t, t.mems) } } val tables = tt.map(_._1) val mems = tt.map(_._2).flatten val f3_resps = VecInit(tables.map(_.io.f3_resp)) val s1_update_meta = s1_update.bits.meta.asTypeOf(new TageMeta) val s1_update_mispredict_mask = UIntToOH(s1_update.bits.cfi_idx.bits) & Fill(bankWidth, s1_update.bits.cfi_mispredicted) val s1_update_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, Bool())))) val s1_update_u_mask = WireInit((0.U).asTypeOf(Vec(tageNTables, Vec(bankWidth, UInt(1.W))))) val s1_update_taken = Wire(Vec(tageNTables, Vec(bankWidth, Bool()))) val s1_update_old_ctr = Wire(Vec(tageNTables, Vec(bankWidth, UInt(3.W)))) val s1_update_alloc = Wire(Vec(tageNTables, Vec(bankWidth, Bool()))) val s1_update_u = Wire(Vec(tageNTables, Vec(bankWidth, UInt(2.W)))) s1_update_taken := DontCare s1_update_old_ctr := DontCare s1_update_alloc := DontCare s1_update_u := DontCare for (w <- 0 until bankWidth) { var altpred = io.resp_in(0).f3(w).taken val final_altpred = WireInit(io.resp_in(0).f3(w).taken) var provided = false.B var provider = 0.U io.resp.f3(w).taken := io.resp_in(0).f3(w).taken for (i <- 0 until tageNTables) { val hit = f3_resps(i)(w).valid val ctr = f3_resps(i)(w).bits.ctr when (hit) { io.resp.f3(w).taken := Mux(ctr === 3.U \|\| ctr === 4.U, altpred, ctr(2)) final_altpred := altpred } provided = provided \|\| hit provider = Mux(hit, i.U, provider) altpred = Mux(hit, f3_resps(i)(w).bits.ctr(2), altpred) } f3_meta.provider(w).valid := provided f3_meta.provider(w).bits := provider f3_meta.alt_differs(w) := final_altpred =/= io.resp.f3(w).taken f3_meta.provider_u(w) := f3_resps(provider)(w).bits.u f3_meta.provider_ctr(w) := f3_resps(provider)(w).bits.ctr // Create a mask of tables which did not hit our query, and also contain useless entries // and also uses a longer history than the provider val allocatable_slots = ( VecInit(f3_resps.map(r => !r(w).valid && r(w).bits.u === 0.U)).asUInt & ~(MaskLower(UIntToOH(provider)) & Fill(tageNTables, provided)) ) val alloc_lfsr = random.LFSR(tageNTables max 2) val first_entry = PriorityEncoder(allocatable_slots) val masked_entry = PriorityEncoder(allocatable_slots & alloc_lfsr) val alloc_entry = Mux(allocatable_slots(masked_entry), masked_entry, first_entry) f3_meta.allocate(w).valid := allocatable_slots =/= 0.U f3_meta.allocate(w).bits := alloc_entry val update_was_taken = (s1_update.bits.cfi_idx.valid && (s1_update.bits.cfi_idx.bits === w.U) && s1_update.bits.cfi_taken) when (s1_update.bits.br_mask(w) && s1_update.valid && s1_update.bits.is_commit_update) { when (s1_update_meta.provider(w).valid) { val provider = s1_update_meta.provider(w).bits s1_update_mask(provider)(w) := true.B s1_update_u_mask(provider)(w) := true.B val new_u = inc_u(s1_update_meta.provider_u(w), s1_update_meta.alt_differs(w), s1_update_mispredict_mask(w)) s1_update_u (provider)(w) := new_u s1_update_taken (provider)(w) := update_was_taken s1_update_old_ctr(provider)(w) := s1_update_meta.provider_ctr(w) s1_update_alloc (provider)(w) := false.B } } } when (s1_update.valid && s1_update.bits.is_commit_update && s1_update.bits.cfi_mispredicted && s1_update.bits.cfi_idx.valid) { val idx = s1_update.bits.cfi_idx.bits val allocate = s1_update_meta.allocate(idx) when (allocate.valid) { s1_update_mask (allocate.bits)(idx) := true.B s1_update_taken(allocate.bits)(idx) := s1_update.bits.cfi_taken s1_update_alloc(allocate.bits)(idx) := true.B s1_update_u_mask(allocate.bits)(idx) := true.B s1_update_u (allocate.bits)(idx) := 0.U } .otherwise { val provider = s1_update_meta.provider(idx) val decr_mask = Mux(provider.valid, ~MaskLower(UIntToOH(provider.bits)), 0.U) for (i <- 0 until tageNTables) { when (decr_mask(i)) { s1_update_u_mask(i)(idx) := true.B s1_update_u (i)(idx) := 0.U } } } } for (i <- 0 until tageNTables) { for (w <- 0 until bankWidth) { tables(i).io.update_mask(w) := RegNext(s1_update_mask(i)(w)) tables(i).io.update_taken(w) := RegNext(s1_update_taken(i)(w)) tables(i).io.update_alloc(w) := RegNext(s1_update_alloc(i)(w)) tables(i).io.update_old_ctr(w) := RegNext(s1_update_old_ctr(i)(w)) tables(i).io.update_u_mask(w) := RegNext(s1_update_u_mask(i)(w)) tables(i).io.update_u(w) := RegNext(s1_update_u(i)(w)) } tables(i).io.update_pc := RegNext(s1_update.bits.pc) tables(i).io.update_hist := RegNext(s1_update.bits.ghist) } //io.f3_meta := Cat(f3_meta.asUInt, micro.io.f3_meta(micro.metaSz-1,0), base.io.f3_meta(base.metaSz-1, 0)) io.f3_meta := f3_meta.asUInt }	module hi_us( // @[tage.scala:89:27] input [6:0] R0_addr, input R0_en, input R0_clk, output [3:0] R0_data, input [6:0] W0_addr, input W0_clk, input [3:0] W0_data, input [3:0] W0_mask ); hi_us_ext hi_us_ext ( // @[tage.scala:89:27] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (1'h1), // @[tage.scala:89:27] .W0_clk (W0_clk), .W0_data (W0_data), .W0_mask (W0_mask) ); // @[tage.scala:89:27] endmodule
Generate the Verilog code corresponding to the following Chisel files. File FPU.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util._ import chisel3.{DontCare, WireInit, withClock, withReset} import chisel3.experimental.SourceInfo import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property case class FPUParams( minFLen: Int = 32, fLen: Int = 64, divSqrt: Boolean = true, sfmaLatency: Int = 3, dfmaLatency: Int = 4, fpmuLatency: Int = 2, ifpuLatency: Int = 2 ) object FPConstants { val RM_SZ = 3 val FLAGS_SZ = 5 } trait HasFPUCtrlSigs { val ldst = Bool() val wen = Bool() val ren1 = Bool() val ren2 = Bool() val ren3 = Bool() val swap12 = Bool() val swap23 = Bool() val typeTagIn = UInt(2.W) val typeTagOut = UInt(2.W) val fromint = Bool() val toint = Bool() val fastpipe = Bool() val fma = Bool() val div = Bool() val sqrt = Bool() val wflags = Bool() val vec = Bool() } class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new Bundle { val inst = Input(Bits(32.W)) val sigs = Output(new FPUCtrlSigs()) }) private val X2 = BitPat.dontCare(2) val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N) val h: Array[(BitPat, List[BitPat])] = Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N), FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N), FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N), FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N), FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N), FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N), FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N), FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N), FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N)) val f: Array[(BitPat, List[BitPat])] = Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N), FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N), FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N), FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N), FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N), FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N), FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N)) val d: Array[(BitPat, List[BitPat])] = Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N), FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N), FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N), FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N), FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N), FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N), FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N), FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N), FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N)) val fcvt_hd: Array[(BitPat, List[BitPat])] = Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N), FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N)) val vfmv_f_s: Array[(BitPat, List[BitPat])] = Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y)) val insns = ((minFLen, fLen) match { case (32, 32) => f case (16, 32) => h ++ f case (32, 64) => f ++ d case (16, 64) => h ++ f ++ d ++ fcvt_hd case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration") }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]()) val decoder = DecodeLogic(io.inst, default, insns) val s = io.sigs val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec) sigs zip decoder map {case(s,d) => s := d} } class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val time = Input(UInt(xLen.W)) val inst = Input(Bits(32.W)) val fromint_data = Input(Bits(xLen.W)) val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W)) val v_sew = Input(UInt(3.W)) val store_data = Output(Bits(fLen.W)) val toint_data = Output(Bits(xLen.W)) val ll_resp_val = Input(Bool()) val ll_resp_type = Input(Bits(3.W)) val ll_resp_tag = Input(UInt(5.W)) val ll_resp_data = Input(Bits(fLen.W)) val valid = Input(Bool()) val fcsr_rdy = Output(Bool()) val nack_mem = Output(Bool()) val illegal_rm = Output(Bool()) val killx = Input(Bool()) val killm = Input(Bool()) val dec = Output(new FPUCtrlSigs()) val sboard_set = Output(Bool()) val sboard_clr = Output(Bool()) val sboard_clra = Output(UInt(5.W)) val keep_clock_enabled = Input(Bool()) } class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) { val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs val cp_resp = Decoupled(new FPResult()) } class FPResult(implicit p: Parameters) extends CoreBundle()(p) { val data = Bits((fLen+1).W) val exc = Bits(FPConstants.FLAGS_SZ.W) } class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val typ = Bits(2.W) val in1 = Bits(xLen.W) } class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val fmaCmd = Bits(2.W) val typ = Bits(2.W) val fmt = Bits(2.W) val in1 = Bits((fLen+1).W) val in2 = Bits((fLen+1).W) val in3 = Bits((fLen+1).W) } case class FType(exp: Int, sig: Int) { def ieeeWidth = exp + sig def recodedWidth = ieeeWidth + 1 def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W) def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W) def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2) def classify(x: UInt) = { val sign = x(sig + exp) val code = x(exp + sig - 1, exp + sig - 3) val codeHi = code(2, 1) val isSpecial = codeHi === 3.U val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U val isSubnormal = code === 1.U \|\| codeHi === 1.U && isHighSubnormalIn val isNormal = codeHi === 1.U && !isHighSubnormalIn \|\| codeHi === 2.U val isZero = code === 0.U val isInf = isSpecial && !code(0) val isNaN = code.andR val isSNaN = isNaN && !x(sig-2) val isQNaN = isNaN && x(sig-2) Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign, isSubnormal && !sign, isZero && !sign, isZero && sign, isSubnormal && sign, isNormal && sign, isInf && sign) } // convert between formats, ignoring rounding, range, NaN def unsafeConvert(x: UInt, to: FType) = if (this == to) x else { val sign = x(sig + exp) val fractIn = x(sig - 2, 0) val expIn = x(sig + exp - 1, sig - 1) val fractOut = fractIn << to.sig >> sig val expOut = { val expCode = expIn(exp, exp - 2) val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U Mux(expCode === 0.U \|\| expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0)) } Cat(sign, expOut, fractOut) } private def ieeeBundle = { val expWidth = exp class IEEEBundle extends Bundle { val sign = Bool() val exp = UInt(expWidth.W) val sig = UInt((ieeeWidth-expWidth-1).W) } new IEEEBundle } def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle) def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x) def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x) } object FType { val H = new FType(5, 11) val S = new FType(8, 24) val D = new FType(11, 53) val all = List(H, S, D) } trait HasFPUParameters { require(fLen == 0 \|\| FType.all.exists(_.ieeeWidth == fLen)) val minFLen: Int val fLen: Int def xLen: Int val minXLen = 32 val nIntTypes = log2Ceil(xLen/minXLen) + 1 def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen) def minType = floatTypes.head def maxType = floatTypes.last def prevType(t: FType) = floatTypes(typeTag(t) - 1) def maxExpWidth = maxType.exp def maxSigWidth = maxType.sig def typeTag(t: FType) = floatTypes.indexOf(t) def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U // typeTag def H = typeTagGroup(FType.H) def S = typeTagGroup(FType.S) def D = typeTagGroup(FType.D) def I = typeTag(maxType).U private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = { require(xt.ieeeWidth == 2 * yt.ieeeWidth) val swizzledNaN = Cat( x(xt.sig + xt.exp, xt.sig + xt.exp - 3), x(xt.sig - 2, yt.recodedWidth - 1).andR, x(xt.sig + xt.exp - 5, xt.sig), y(yt.recodedWidth - 2), x(xt.sig - 2, yt.recodedWidth - 1), y(yt.recodedWidth - 1), y(yt.recodedWidth - 3, 0)) Mux(xt.isNaN(x), swizzledNaN, x) } // implement NaN unboxing for FU inputs def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = { val outType = exactType.getOrElse(maxType) def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = { val prev = if (t == minType) { Seq() } else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prev = helper(unswizzled, prevT) val isbox = isBox(x, t) prev.map(p => (isbox && p._1, p._2)) } prev :+ (true.B, t.unsafeConvert(x, outType)) } val (oks, floats) = helper(x, maxType).unzip if (exactType.isEmpty \|\| floatTypes.size == 1) { Mux(oks(tag), floats(tag), maxType.qNaN) } else { val t = exactType.get floats(typeTag(t)) \| Mux(oks(typeTag(t)), 0.U, t.qNaN) } } // make sure that the redundant bits in the NaN-boxed encoding are consistent def consistent(x: UInt): Bool = { def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prevOK = !isBox(x, t) \|\| helper(unswizzled, prevT) val curOK = !t.isNaN(x) \|\| x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR prevOK && curOK } helper(x, maxType) } // generate a NaN box from an FU result def box(x: UInt, t: FType): UInt = { if (t == maxType) { x } else { val nt = floatTypes(typeTag(t) + 1) val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t) bigger \| ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U } } // generate a NaN box from an FU result def box(x: UInt, tag: UInt): UInt = { val opts = floatTypes.map(t => box(x, t)) opts(tag) } // zap bits that hardfloat thinks are don't-cares, but we do care about def sanitizeNaN(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { x } else { val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) \| (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W) Mux(t.isNaN(x), maskedNaN, x) } } // implement NaN boxing and recoding for FL/fmv..x def recode(x: UInt, tag: UInt): UInt = { def helper(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { t.recode(x) } else { val prevT = prevType(t) box(t.recode(x), t, helper(x, prevT), prevT) } } // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U) helper(boxes(tag) \| x, maxType) } // implement NaN unboxing and un-recoding for FS/fmv.x. def ieee(x: UInt, t: FType = maxType): UInt = { if (typeTag(t) == 0) { t.ieee(x) } else { val unrecoded = t.ieee(x) val prevT = prevType(t) val prevRecoded = Cat( x(prevT.recodedWidth-2), x(t.sig-1), x(prevT.recodedWidth-3, 0)) val prevUnrecoded = ieee(prevRecoded, prevT) Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0))) } } } abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { class Output extends Bundle { val in = new FPInput val lt = Bool() val store = Bits(fLen.W) val toint = Bits(xLen.W) val exc = Bits(FPConstants.FLAGS_SZ.W) } val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new Output) }) val in = RegEnable(io.in.bits, io.in.valid) val valid = RegNext(io.in.valid) val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth)) dcmp.io.a := in.in1 dcmp.io.b := in.in2 dcmp.io.signaling := !in.rm(1) val tag = in.typeTagOut val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen)) else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) val toint = WireDefault(toint_ieee) val intType = WireDefault(in.fmt(0)) io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType) io.out.bits.exc := 0.U when (in.rm(0)) { val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag) toint := classify_out \| (toint_ieee >> minXLen << minXLen) intType := false.B } when (in.wflags) { // feq/flt/fle, fcvt toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR \| (toint_ieee >> minXLen << minXLen) io.out.bits.exc := dcmp.io.exceptionFlags intType := false.B when (!in.ren2) { // fcvt val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1) intType := cvtType val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen)) conv.io.in := in.in1 conv.io.roundingMode := in.rm conv.io.signedOut := ~in.typ(0) toint := conv.io.out io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0)) for (i <- 0 until nIntTypes-1) { val w = minXLen << i when (cvtType === i.U) { val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w)) narrow.io.in := in.in1 narrow.io.roundingMode := in.rm narrow.io.signedOut := ~in.typ(0) val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1) val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign)) val invalid = conv.io.intExceptionFlags(2) \|\| narrow.io.intExceptionFlags(1) when (invalid) { toint := Cat(conv.io.out >> w, excOut) } io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0)) } } } } io.out.valid := valid io.out.bits.lt := dcmp.io.lt \|\| (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S) io.out.bits.in := in } class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new IntToFPInput)) val out = Valid(new FPResult) }) val in = Pipe(io.in) val tag = in.bits.typeTagIn val mux = Wire(new FPResult) mux.exc := 0.U mux.data := recode(in.bits.in1, tag) val intValue = { val res = WireDefault(in.bits.in1.asSInt) for (i <- 0 until nIntTypes-1) { val smallInt = in.bits.in1((minXLen << i) - 1, 0) when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) { res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt) } } res.asUInt } when (in.bits.wflags) { // fcvt // could be improved for RVD/RVQ with a single variable-position rounding // unit, rather than N fixed-position ones val i2fResults = for (t <- floatTypes) yield { val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig)) i2f.io.signedIn := ~in.bits.typ(0) i2f.io.in := intValue i2f.io.roundingMode := in.bits.rm i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags) } val (data, exc) = i2fResults.unzip val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last mux.data := dataPadded(tag) mux.exc := exc(tag) } io.out <> Pipe(in.valid, mux, latency-1) } class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) val lt = Input(Bool()) // from FPToInt }) val in = Pipe(io.in) val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2)) val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0)) val fsgnjMux = Wire(new FPResult) fsgnjMux.exc := 0.U fsgnjMux.data := fsgnj when (in.bits.wflags) { // fmin/fmax val isnan1 = maxType.isNaN(in.bits.in1) val isnan2 = maxType.isNaN(in.bits.in2) val isInvalid = maxType.isSNaN(in.bits.in1) \|\| maxType.isSNaN(in.bits.in2) val isNaNOut = isnan1 && isnan2 val isLHS = isnan2 \|\| in.bits.rm(0) =/= io.lt && !isnan1 fsgnjMux.exc := isInvalid << 4 fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2)) } val inTag = in.bits.typeTagIn val outTag = in.bits.typeTagOut val mux = WireDefault(fsgnjMux) for (t <- floatTypes.init) { when (outTag === typeTag(t).U) { mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t)) } } when (in.bits.wflags && !in.bits.ren2) { // fcvt if (floatTypes.size > 1) { // widening conversions simply canonicalize NaN operands val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1) fsgnjMux.data := widened fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4 // narrowing conversions require rounding (for RVQ, this could be // optimized to use a single variable-position rounding unit, rather // than two fixed-position ones) for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B \|\| outTag < inTag)) { val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig)) narrower.io.in := in.bits.in1 narrower.io.roundingMode := in.bits.rm narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding val narrowed = sanitizeNaN(narrower.io.out, outType) mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed) mux.exc := narrower.io.exceptionFlags } } } io.out <> Pipe(in.valid, mux, latency-1) } class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module { override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}" require(latency<=2) val io = IO(new Bundle { val validin = Input(Bool()) val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) val validout = Output(Bool()) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC val valid_stage0 = Wire(Bool()) val roundingMode_stage0 = Wire(UInt(3.W)) val detectTininess_stage0 = Wire(UInt(1.W)) val postmul_regs = if(latency>0) 1 else 0 mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0)) val round_regs = if(latency==2) 1 else 0 roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits io.validout := Pipe(valid_stage0, false.B, round_regs).valid roundRawFNToRecFN.io.infiniteExc := false.B io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } class FPUFMAPipe(val latency: Int, val t: FType) (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}" require(latency>0) val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) }) val valid = RegNext(io.in.valid) val in = Reg(new FPInput) when (io.in.valid) { val one = 1.U << (t.sig + t.exp - 1) val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp)) val cmd_fma = io.in.bits.ren3 val cmd_addsub = io.in.bits.swap23 in := io.in.bits when (cmd_addsub) { in.in2 := one } when (!(cmd_fma \|\| cmd_addsub)) { in.in3 := zero } } val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig)) fma.io.validin := valid fma.io.op := in.fmaCmd fma.io.roundingMode := in.rm fma.io.detectTininess := hardfloat.consts.tininess_afterRounding fma.io.a := in.in1 fma.io.b := in.in2 fma.io.c := in.in3 val res = Wire(new FPResult) res.data := sanitizeNaN(fma.io.out, t) res.exc := fma.io.exceptionFlags io.out := Pipe(fma.io.validout, res, (latency-3) max 0) } class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new FPUIO) val (useClockGating, useDebugROB) = coreParams match { case r: RocketCoreParams => val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1 (r.clockGate, sz < 1) case _ => (false, false) } val clock_en_reg = Reg(Bool()) val clock_en = clock_en_reg \|\| io.cp_req.valid val gated_clock = if (!useClockGating) clock else ClockGate(clock, clock_en, "fpu_clock_gate") val fp_decoder = Module(new FPUDecoder) fp_decoder.io.inst := io.inst val id_ctrl = WireInit(fp_decoder.io.sigs) coreParams match { case r: RocketCoreParams => r.vector.map(v => { val v_decode = v.decoder(p) // Only need to get ren1 v_decode.io.inst := io.inst v_decode.io.vconfig := DontCare // core deals with this when (v_decode.io.legal && v_decode.io.read_frs1) { id_ctrl.ren1 := true.B id_ctrl.swap12 := false.B id_ctrl.toint := true.B id_ctrl.typeTagIn := I id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S) } when (v_decode.io.write_frd) { id_ctrl.wen := true.B } })} val ex_reg_valid = RegNext(io.valid, false.B) val ex_reg_inst = RegEnable(io.inst, io.valid) val ex_reg_ctrl = RegEnable(id_ctrl, io.valid) val ex_ra = List.fill(3)(Reg(UInt())) // load/vector response val load_wb = RegNext(io.ll_resp_val) val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val) val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val) val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val) class FPUImpl { // entering gated-clock domain val req_valid = ex_reg_valid \|\| io.cp_req.valid val ex_cp_valid = io.cp_req.fire val mem_cp_valid = RegNext(ex_cp_valid, false.B) val wb_cp_valid = RegNext(mem_cp_valid, false.B) val mem_reg_valid = RegInit(false.B) val killm = (io.killm \|\| io.nack_mem) && !mem_cp_valid // Kill X-stage instruction if M-stage is killed. This prevents it from // speculatively being sent to the div-sqrt unit, which can cause priority // inversion for two back-to-back divides, the first of which is killed. val killx = io.killx \|\| mem_reg_valid && killm mem_reg_valid := ex_reg_valid && !killx \|\| ex_cp_valid val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid) val wb_reg_valid = RegNext(mem_reg_valid && (!killm \|\| mem_cp_valid), false.B) val cp_ctrl = Wire(new FPUCtrlSigs) cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs) io.cp_resp.valid := false.B io.cp_resp.bits.data := 0.U io.cp_resp.bits.exc := DontCare val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl) val mem_ctrl = RegEnable(ex_ctrl, req_valid) val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid) // CoreMonitorBundle to monitor fp register file writes val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare)) frfWriteBundle.foreach { i => i.clock := clock i.reset := reset i.hartid := io.hartid i.timer := io.time(31,0) i.valid := false.B i.wrenx := false.B i.wrenf := false.B i.excpt := false.B } // regfile val regfile = Mem(32, Bits((fLen+1).W)) when (load_wb) { val wdata = recode(load_wb_data, load_wb_typeTag) regfile(load_wb_tag) := wdata assert(consistent(wdata)) if (enableCommitLog) printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata)) if (useDebugROB) DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata)) frfWriteBundle(0).wrdst := load_wb_tag frfWriteBundle(0).wrenf := true.B frfWriteBundle(0).wrdata := ieee(wdata) } val ex_rs = ex_ra.map(a => regfile(a)) when (io.valid) { when (id_ctrl.ren1) { when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) } when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) } } when (id_ctrl.ren2) { when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) } when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) } when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) } } when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) } } val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12)) def fuInput(minT: Option[FType]): FPInput = { val req = Wire(new FPInput) val tag = ex_ctrl.typeTagIn req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs) req.rm := ex_rm req.in1 := unbox(ex_rs(0), tag, minT) req.in2 := unbox(ex_rs(1), tag, minT) req.in3 := unbox(ex_rs(2), tag, minT) req.typ := ex_reg_inst(21,20) req.fmt := ex_reg_inst(26,25) req.fmaCmd := ex_reg_inst(3,2) \| (!ex_ctrl.ren3 && ex_reg_inst(27)) when (ex_cp_valid) { req := io.cp_req.bits when (io.cp_req.bits.swap12) { req.in1 := io.cp_req.bits.in2 req.in2 := io.cp_req.bits.in1 } when (io.cp_req.bits.swap23) { req.in2 := io.cp_req.bits.in3 req.in3 := io.cp_req.bits.in2 } } req } val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S)) sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S sfma.io.in.bits := fuInput(Some(sfma.t)) val fpiu = Module(new FPToInt) fpiu.io.in.valid := req_valid && (ex_ctrl.toint \|\| ex_ctrl.div \|\| ex_ctrl.sqrt \|\| (ex_ctrl.fastpipe && ex_ctrl.wflags)) fpiu.io.in.bits := fuInput(None) io.store_data := fpiu.io.out.bits.store io.toint_data := fpiu.io.out.bits.toint when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){ io.cp_resp.bits.data := fpiu.io.out.bits.toint io.cp_resp.valid := true.B } val ifpu = Module(new IntToFP(cfg.ifpuLatency)) ifpu.io.in.valid := req_valid && ex_ctrl.fromint ifpu.io.in.bits := fpiu.io.in.bits ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) val fpmu = Module(new FPToFP(cfg.fpmuLatency)) fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe fpmu.io.in.bits := fpiu.io.in.bits fpmu.io.lt := fpiu.io.out.bits.lt val divSqrt_wen = WireDefault(false.B) val divSqrt_inFlight = WireDefault(false.B) val divSqrt_waddr = Reg(UInt(5.W)) val divSqrt_cp = Reg(Bool()) val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W)) val divSqrt_wdata = Wire(UInt((fLen+1).W)) val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W)) divSqrt_typeTag := DontCare divSqrt_wdata := DontCare divSqrt_flags := DontCare // writeback arbitration case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult) val pipes = List( Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits), Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits), Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++ (fLen > 32).option({ val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D)) dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D dfma.io.in.bits := fuInput(Some(dfma.t)) Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits) }) ++ (minFLen == 16).option({ val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H)) hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H hfma.io.in.bits := fuInput(Some(hfma.t)) Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits) }) def latencyMask(c: FPUCtrlSigs, offset: Int) = { require(pipes.forall(_.lat >= offset)) pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_\|_) } def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_\|_) val maxLatency = pipes.map(_.lat).max val memLatencyMask = latencyMask(mem_ctrl, 2) class WBInfo extends Bundle { val rd = UInt(5.W) val typeTag = UInt(log2Up(floatTypes.size).W) val cp = Bool() val pipeid = UInt(log2Ceil(pipes.size).W) } val wen = RegInit(0.U((maxLatency-1).W)) val wbInfo = Reg(Vec(maxLatency-1, new WBInfo)) val mem_wen = mem_reg_valid && (mem_ctrl.fma \|\| mem_ctrl.fastpipe \|\| mem_ctrl.fromint) val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR \|\| (wen & latencyMask(ex_ctrl, 0)).orR, req_valid) ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback") for (i <- 0 until maxLatency-2) { when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) } } wen := wen >> 1 when (mem_wen) { when (!killm) { wen := wen >> 1 \| memLatencyMask } for (i <- 0 until maxLatency-1) { when (!write_port_busy && memLatencyMask(i)) { wbInfo(i).cp := mem_cp_valid wbInfo(i).typeTag := mem_ctrl.typeTagOut wbInfo(i).pipeid := pipeid(mem_ctrl) wbInfo(i).rd := mem_reg_inst(11,7) } } } val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd) val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp) val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag) val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag) val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid) when ((!wbInfo(0).cp && wen(0)) \|\| divSqrt_wen) { assert(consistent(wdata)) regfile(waddr) := wdata if (enableCommitLog) { printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata)) } frfWriteBundle(1).wrdst := waddr frfWriteBundle(1).wrenf := true.B frfWriteBundle(1).wrdata := ieee(wdata) } if (useDebugROB) { DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) \|\| divSqrt_wen, waddr + 32.U, ieee(wdata)) } when (wb_cp && (wen(0) \|\| divSqrt_wen)) { io.cp_resp.bits.data := wdata io.cp_resp.valid := true.B } assert(!io.cp_req.valid \|\| pipes.forall(_.lat == pipes.head.lat).B, s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}") // Avoid structural hazards and nacking of external requests // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight val wb_toint_valid = wb_reg_valid && wb_ctrl.toint val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint) io.fcsr_flags.valid := wb_toint_valid \|\| divSqrt_wen \|\| wen(0) io.fcsr_flags.bits := Mux(wb_toint_valid, wb_toint_exc, 0.U) \| Mux(divSqrt_wen, divSqrt_flags, 0.U) \| Mux(wen(0), wexc, 0.U) val divSqrt_write_port_busy = (mem_ctrl.div \|\| mem_ctrl.sqrt) && wen.orR io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags \|\| mem_reg_valid && mem_ctrl.wflags \|\| wb_reg_valid && wb_ctrl.toint \|\| wen.orR \|\| divSqrt_inFlight) io.nack_mem := (write_port_busy \|\| divSqrt_write_port_busy \|\| divSqrt_inFlight) && !mem_cp_valid io.dec <> id_ctrl def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_\|\|_) io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) \|\| mem_ctrl.div \|\| mem_ctrl.sqrt \|\| mem_ctrl.vec) io.sboard_clr := !wb_cp_valid && (divSqrt_wen \|\| (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U))) io.sboard_clra := waddr ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle") // we don't currently support round-max-magnitude (rm=4) io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) \|\| io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U if (cfg.divSqrt) { val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div \|\| mem_ctrl.sqrt) && !divSqrt_inFlight val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B) when (divSqrt_inValid) { divSqrt_waddr := mem_reg_inst(11,7) divSqrt_cp := mem_cp_valid } ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider") ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div \|\| mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard") ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback") for (t <- floatTypes) { val tag = mem_ctrl.typeTagOut val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) } divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U divSqrt.io.sqrtOp := mem_ctrl.sqrt divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t) divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t) divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight when (divSqrt.io.outValid_div \|\| divSqrt.io.outValid_sqrt) { divSqrt_wen := !divSqrt_killed divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t) divSqrt_flags := divSqrt.io.exceptionFlags divSqrt_typeTag := typeTag(t).U } } when (divSqrt_killed) { divSqrt_inFlight := false.B } } else { when (id_ctrl.div \|\| id_ctrl.sqrt) { io.illegal_rm := true.B } } // gate the clock clock_en_reg := !useClockGating.B \|\| io.keep_clock_enabled \|\| // chicken bit io.valid \|\| // ID stage req_valid \|\| // EX stage mem_reg_valid \|\| mem_cp_valid \|\| // MEM stage wb_reg_valid \|\| wb_cp_valid \|\| // WB stage wen.orR \|\| divSqrt_inFlight \|\| // post-WB stage io.ll_resp_val // load writeback } // leaving gated-clock domain val fpuImpl = withClock (gated_clock) { new FPUImpl } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"FPU_$label", "Core;;" + desc) }	module FPToFP( // @[FPU.scala:573:7] input clock, // @[FPU.scala:573:7] input reset, // @[FPU.scala:573:7] input io_in_valid, // @[FPU.scala:574:14] input io_in_bits_ren2, // @[FPU.scala:574:14] input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:574:14] input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:574:14] input io_in_bits_wflags, // @[FPU.scala:574:14] input [2:0] io_in_bits_rm, // @[FPU.scala:574:14] input [64:0] io_in_bits_in1, // @[FPU.scala:574:14] input [64:0] io_in_bits_in2, // @[FPU.scala:574:14] output [64:0] io_out_bits_data, // @[FPU.scala:574:14] output [4:0] io_out_bits_exc, // @[FPU.scala:574:14] input io_lt // @[FPU.scala:574:14] ); wire [32:0] _narrower_1_io_out; // @[FPU.scala:619:30] wire [4:0] _narrower_1_io_exceptionFlags; // @[FPU.scala:619:30] wire [16:0] _narrower_io_out; // @[FPU.scala:619:30] wire [4:0] _narrower_io_exceptionFlags; // @[FPU.scala:619:30] reg in_pipe_v; // @[Valid.scala:141:24] reg in_pipe_b_ren2; // @[Valid.scala:142:26] reg [1:0] in_pipe_b_typeTagIn; // @[Valid.scala:142:26] reg [1:0] in_pipe_b_typeTagOut; // @[Valid.scala:142:26] reg in_pipe_b_wflags; // @[Valid.scala:142:26] reg [2:0] in_pipe_b_rm; // @[Valid.scala:142:26] reg [64:0] in_pipe_b_in1; // @[Valid.scala:142:26] reg [64:0] in_pipe_b_in2; // @[Valid.scala:142:26] wire _GEN = in_pipe_b_wflags & ~in_pipe_b_ren2; // @[Valid.scala:142:26] wire [64:0] fsgnjMux_data = _GEN ? ((&(in_pipe_b_in1[63:61])) ? 65'hE008000000000000 : in_pipe_b_in1) : in_pipe_b_wflags ? ((&(in_pipe_b_in1[63:61])) & (&(in_pipe_b_in2[63:61])) ? 65'hE008000000000000 : (&(in_pipe_b_in2[63:61])) \| in_pipe_b_rm[0] != io_lt & ~(&(in_pipe_b_in1[63:61])) ? in_pipe_b_in1 : in_pipe_b_in2) : {in_pipe_b_rm[1] ? in_pipe_b_in1[64] ^ in_pipe_b_in2[64] : in_pipe_b_rm[0] ^ in_pipe_b_in2[64], in_pipe_b_in1[63:0]}; // @[Valid.scala:142:26] reg [64:0] io_out_pipe_b_data; // @[Valid.scala:142:26] reg [4:0] io_out_pipe_b_exc; // @[Valid.scala:142:26] wire [4:0] _GEN_0 = in_pipe_b_wflags ? {(&(in_pipe_b_in1[63:61])) & ~(in_pipe_b_in1[51]) \| (&(in_pipe_b_in2[63:61])) & ~(in_pipe_b_in2[51]), 4'h0} : 5'h0; // @[Valid.scala:142:26] wire _GEN_1 = in_pipe_b_typeTagOut == 2'h0; // @[Valid.scala:142:26] wire [5:0] _mux_data_expOut_commonCase_T = fsgnjMux_data[57:52] - 6'h20; // @[FPU.scala:276:18, :280:31, :589:25, :608:42, :612:21] wire _GEN_2 = in_pipe_b_typeTagOut == 2'h1; // @[Valid.scala:142:26] wire [8:0] _mux_data_expOut_commonCase_T_3 = fsgnjMux_data[60:52] - 9'h100; // @[FPU.scala:276:18, :280:31, :589:25, :608:42, :612:21] wire [64:0] _mux_data_T_5 = {fsgnjMux_data[64:33], fsgnjMux_data[64], fsgnjMux_data[63:61] == 3'h0 \| fsgnjMux_data[63:61] > 3'h5 ? {fsgnjMux_data[63:61], _mux_data_expOut_commonCase_T_3[5:0]} : _mux_data_expOut_commonCase_T_3, fsgnjMux_data[51:29]}; // @[FPU.scala:274:17, :276:18, :277:38, :279:26, :280:{31,50}, :281:{10,19,27,38,49,69}, :589:25, :604:{22,37}, :608:42, :612:21] wire _GEN_3 = _GEN_2 & in_pipe_b_typeTagOut < in_pipe_b_typeTagIn; // @[Valid.scala:142:26] always @(posedge clock) begin // @[FPU.scala:573:7] if (reset) // @[FPU.scala:573:7] in_pipe_v <= 1'h0; // @[Valid.scala:141:24] else // @[FPU.scala:573:7] in_pipe_v <= io_in_valid; // @[Valid.scala:141:24] if (io_in_valid) begin // @[FPU.scala:574:14] in_pipe_b_ren2 <= io_in_bits_ren2; // @[Valid.scala:142:26] in_pipe_b_typeTagIn <= io_in_bits_typeTagIn; // @[Valid.scala:142:26] in_pipe_b_typeTagOut <= io_in_bits_typeTagOut; // @[Valid.scala:142:26] in_pipe_b_wflags <= io_in_bits_wflags; // @[Valid.scala:142:26] in_pipe_b_rm <= io_in_bits_rm; // @[Valid.scala:142:26] in_pipe_b_in1 <= io_in_bits_in1; // @[Valid.scala:142:26] in_pipe_b_in2 <= io_in_bits_in2; // @[Valid.scala:142:26] end if (in_pipe_v) begin // @[Valid.scala:141:24] io_out_pipe_b_data <= _GEN ? (_GEN_3 ? {fsgnjMux_data[64:33], ({33{_narrower_1_io_out[31:29] != 3'h7}} \| 33'h1EF7FFFFF) & _narrower_1_io_out} : _GEN_1 ? {fsgnjMux_data[64:17], _narrower_io_out} : _GEN_2 ? _mux_data_T_5 : fsgnjMux_data) : _GEN_2 ? _mux_data_T_5 : _GEN_1 ? {fsgnjMux_data[64:17], fsgnjMux_data[64], fsgnjMux_data[63:61] == 3'h0 \| fsgnjMux_data[63:61] > 3'h5 ? {fsgnjMux_data[63:61], _mux_data_expOut_commonCase_T[2:0]} : _mux_data_expOut_commonCase_T, fsgnjMux_data[51:42]} : fsgnjMux_data; // @[Valid.scala:142:26] io_out_pipe_b_exc <= _GEN ? (_GEN_3 ? _narrower_1_io_exceptionFlags : _GEN_1 ? _narrower_io_exceptionFlags : _GEN ? {(&(in_pipe_b_in1[63:61])) & ~(in_pipe_b_in1[51]), 4'h0} : _GEN_0) : _GEN_0; // @[Valid.scala:142:26] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications */ abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File AsyncQueue.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ case class AsyncQueueParams( depth: Int = 8, sync: Int = 3, safe: Boolean = true, // If safe is true, then effort is made to resynchronize the crossing indices when either side is reset. // This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty. narrow: Boolean = false) // If narrow is true then the read mux is moved to the source side of the crossing. // This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing, // at the expense of a combinational path from the sink to the source and back to the sink. { require (depth > 0 && isPow2(depth)) require (sync >= 2) val bits = log2Ceil(depth) val wires = if (narrow) 1 else depth } object AsyncQueueParams { // When there is only one entry, we don't need narrow. def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false) } class AsyncBundleSafety extends Bundle { val ridx_valid = Input (Bool()) val widx_valid = Output(Bool()) val source_reset_n = Output(Bool()) val sink_reset_n = Input (Bool()) } class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle { // Data-path synchronization val mem = Output(Vec(params.wires, gen)) val ridx = Input (UInt((params.bits+1).W)) val widx = Output(UInt((params.bits+1).W)) val index = params.narrow.option(Input(UInt(params.bits.W))) // Signals used to self-stabilize a safe AsyncQueue val safe = params.safe.option(new AsyncBundleSafety) } object GrayCounter { def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = { val incremented = Wire(UInt(bits.W)) val binary = RegNext(next=incremented, init=0.U).suggestName(name) incremented := Mux(clear, 0.U, binary + increment.asUInt) incremented ^ (incremented >> 1) } } class AsyncValidSync(sync: Int, desc: String) extends RawModule { val io = IO(new Bundle { val in = Input(Bool()) val out = Output(Bool()) }) val clock = IO(Input(Clock())) val reset = IO(Input(AsyncReset())) withClockAndReset(clock, reset){ io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc)) } } class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSource_${gen.typeName}" val io = IO(new Bundle { // These come from the source domain val enq = Flipped(Decoupled(gen)) // These cross to the sink clock domain val async = new AsyncBundle(gen, params) }) val bits = params.bits val sink_ready = WireInit(true.B) val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all. val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin")) val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray")) val ready = sink_ready && widx =/= (ridx ^ (params.depth \| params.depth >> 1).U) val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1)) when (io.enq.fire) { mem(index) := io.enq.bits } val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg")) io.enq.ready := ready_reg && sink_ready val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray")) io.async.widx := widx_reg io.async.index match { case Some(index) => io.async.mem(0) := mem(index) case None => io.async.mem := mem } io.async.safe.foreach { sio => val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0")) val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1")) val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend")) val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid")) source_valid_0.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset source_valid_1.reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_extend .reset := (reset.asBool \|\| !sio.sink_reset_n).asAsyncReset sink_valid .reset := reset.asAsyncReset source_valid_0.clock := clock source_valid_1.clock := clock sink_extend .clock := clock sink_valid .clock := clock source_valid_0.io.in := true.B source_valid_1.io.in := source_valid_0.io.out sio.widx_valid := source_valid_1.io.out sink_extend.io.in := sio.ridx_valid sink_valid.io.in := sink_extend.io.out sink_ready := sink_valid.io.out sio.source_reset_n := !reset.asBool // Assert that if there is stuff in the queue, then reset cannot happen // Impossible to write because dequeue can occur on the receiving side, // then reset allowed to happen, but write side cannot know that dequeue // occurred. // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // assert (!(reset \|\| !sio.sink_reset_n) \|\| !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected") // assert (!reset_rise \|\| prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty") } } class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module { override def desiredName = s"AsyncQueueSink_${gen.typeName}" val io = IO(new Bundle { // These come from the sink domain val deq = Decoupled(gen) // These cross to the source clock domain val async = Flipped(new AsyncBundle(gen, params)) }) val bits = params.bits val source_ready = WireInit(true.B) val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin")) val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray")) val valid = source_ready && ridx =/= widx // The mux is safe because timing analysis ensures ridx has reached the register // On an ASIC, changes to the unread location cannot affect the selected value // On an FPGA, only one input changes at a time => mem updates don't cause glitches // The register only latches when the selected valued is not being written val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1)) io.async.index.foreach { _ := index } // This register does not NEED to be reset, as its contents will not // be considered unless the asynchronously reset deq valid register is set. // It is possible that bits latches when the source domain is reset / has power cut // This is safe, because isolation gates brought mem low before the zeroed widx reached us val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index) io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg")) val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg")) io.deq.valid := valid_reg && source_ready val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray")) io.async.ridx := ridx_reg io.async.safe.foreach { sio => val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0")) val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1")) val source_extend = Module(new AsyncValidSync(params.sync, "source_extend")) val source_valid = Module(new AsyncValidSync(params.sync, "source_valid")) sink_valid_0 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset sink_valid_1 .reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_extend.reset := (reset.asBool \|\| !sio.source_reset_n).asAsyncReset source_valid .reset := reset.asAsyncReset sink_valid_0 .clock := clock sink_valid_1 .clock := clock source_extend.clock := clock source_valid .clock := clock sink_valid_0.io.in := true.B sink_valid_1.io.in := sink_valid_0.io.out sio.ridx_valid := sink_valid_1.io.out source_extend.io.in := sio.widx_valid source_valid.io.in := source_extend.io.out source_ready := source_valid.io.out sio.sink_reset_n := !reset.asBool // TODO: write some sort of sanity check assertion for users // that denote don't reset when there is activity // // val reset_and_extend = !source_ready \|\| !sio.source_reset_n \|\| reset.asBool // val reset_and_extend_prev = RegNext(reset_and_extend, true.B) // val reset_rise = !reset_and_extend_prev && reset_and_extend // val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0) // assert (!reset_rise \|\| prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty") } } object FromAsyncBundle { // Sometimes it makes sense for the sink to have different sync than the source def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync) def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = { val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync))) sink.io.async <> x sink.io.deq } } object ToAsyncBundle { def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = { val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params)) source.io.enq <> x source.io.async } } class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] { val io = IO(new CrossingIO(gen)) val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) } val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) } source.io.enq <> io.enq io.deq <> sink.io.deq sink.io.async <> source.io.async }	module AsyncValidSync_246( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_263 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File BusBypass.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.devices.tilelink import chisel3._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ abstract class TLBusBypassBase(beatBytes: Int, deadlock: Boolean = false, bufferError: Boolean = true, maxAtomic: Int = 16, maxTransfer: Int = 4096) (implicit p: Parameters) extends LazyModule { protected val nodeIn = TLIdentityNode() protected val nodeOut = TLIdentityNode() val node = NodeHandle(nodeIn, nodeOut) protected val bar = LazyModule(new TLBusBypassBar(dFn = { mp => mp.v1copy(managers = mp.managers.map { m => m.v1copy( mayDenyPut = m.mayDenyPut \|\| !deadlock, mayDenyGet = m.mayDenyGet \|\| !deadlock) }) })) protected val everything = Seq(AddressSet(0, BigInt("ffffffffffffffffffffffffffffffff", 16))) // 128-bit protected val params = DevNullParams(everything, maxAtomic, maxTransfer, region=RegionType.TRACKED) protected val error = if (deadlock) LazyModule(new TLDeadlock(params, beatBytes)) else LazyModule(new TLError(params, bufferError, beatBytes)) // order matters because the parameters and bypass // assume that the non-bypassed connection is // the last connection to the bar, so keep nodeOut last. bar.node := nodeIn error.node := bar.node nodeOut := bar.node } class TLBusBypass(beatBytes: Int, bufferError: Boolean = false, maxAtomic: Int = 16, maxTransfer: Int = 4096)(implicit p: Parameters) extends TLBusBypassBase(beatBytes, deadlock = false, bufferError = bufferError, maxAtomic = maxAtomic, maxTransfer = maxTransfer) { lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val bypass = Input(Bool()) }) bar.module.io.bypass := io.bypass } } class TLBypassNode(dFn: TLSlavePortParameters => TLSlavePortParameters)(implicit valName: ValName) extends TLCustomNode { def resolveStar(iKnown: Int, oKnown: Int, iStars: Int, oStars: Int): (Int, Int) = { require (iStars == 0 && oStars == 0, "TLBypass node does not support := or :=") require (iKnown == 1, "TLBypass node expects exactly one input") require (oKnown == 2, "TLBypass node expects exactly two outputs") (0, 0) } def mapParamsD(n: Int, p: Seq[TLMasterPortParameters]): Seq[TLMasterPortParameters] = { p ++ p } def mapParamsU(n: Int, p: Seq[TLSlavePortParameters]): Seq[TLSlavePortParameters] = { Seq(dFn(p.last).v1copy(minLatency = p.map(_.minLatency).min))} } class TLBusBypassBar(dFn: TLSlavePortParameters => TLSlavePortParameters)(implicit p: Parameters) extends LazyModule { val node = new TLBypassNode(dFn) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val io = IO(new Bundle { val bypass = Input(Bool()) val pending = Output(Bool()) }) val (in, edgeIn) = node.in(0) val Seq((out0, edgeOut0), (out1, edgeOut1)) = node.out require (edgeOut0.manager.beatBytes == edgeOut1.manager.beatBytes, s"BusBypass slave device widths mismatch (${edgeOut0.manager.managers.map(_.name)} has ${edgeOut0.manager.beatBytes}B vs ${edgeOut1.manager.managers.map(_.name)} has ${edgeOut1.manager.beatBytes}B)") // We need to be locked to the given bypass direction until all transactions stop val in_reset = RegNext(false.B, init = true.B) val bypass_reg = Reg(Bool()) val bypass = Mux(in_reset, io.bypass, bypass_reg) val (flight, next_flight) = edgeIn.inFlight(in) io.pending := (flight > 0.U) when (in_reset \|\| (next_flight === 0.U)) { bypass_reg := io.bypass } val stall = (bypass =/= io.bypass) && edgeIn.first(in.a) out0.a.valid := !stall && in.a.valid && bypass out1.a.valid := !stall && in.a.valid && !bypass in.a.ready := !stall && Mux(bypass, out0.a.ready, out1.a.ready) out0.a.bits := in.a.bits out1.a.bits := in.a.bits out0.d.ready := in.d.ready && bypass out1.d.ready := in.d.ready && !bypass in.d.valid := Mux(bypass, out0.d.valid, out1.d.valid) def cast(x: TLBundleD) = { val out = WireDefault(in.d.bits); out <> x; out } in.d.bits := Mux(bypass, cast(out0.d.bits), cast(out1.d.bits)) if (edgeIn.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) { out0.b.ready := in.b.ready && bypass out1.b.ready := in.b.ready && !bypass in.b.valid := Mux(bypass, out0.b.valid, out1.b.valid) def cast(x: TLBundleB) = { val out = Wire(in.b.bits); out <> x; out } in.b.bits := Mux(bypass, cast(out0.b.bits), cast(out1.b.bits)) out0.c.valid := in.c.valid && bypass out1.c.valid := in.c.valid && !bypass in.c.ready := Mux(bypass, out0.c.ready, out1.c.ready) out0.c.bits := in.c.bits out1.c.bits := in.c.bits out0.e.valid := in.e.valid && bypass out1.e.valid := in.e.valid && !bypass in.e.ready := Mux(bypass, out0.e.ready, out1.e.ready) out0.e.bits := in.e.bits out1.e.bits := in.e.bits } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out0.b.ready := true.B out0.c.valid := false.B out0.e.valid := false.B out1.b.ready := true.B out1.c.valid := false.B out1.e.valid := false.B } } } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLBusBypassBar( // @[BusBypass.scala:66:9] input clock, // @[BusBypass.scala:66:9] input reset, // @[BusBypass.scala:66:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [127:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_bypass // @[BusBypass.scala:67:16] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BusBypass.scala:66:9] wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BusBypass.scala:66:9] wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BusBypass.scala:66:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[BusBypass.scala:66:9] wire auto_out_1_a_ready_0 = auto_out_1_a_ready; // @[BusBypass.scala:66:9] wire auto_out_1_d_valid_0 = auto_out_1_d_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_d_bits_opcode_0 = auto_out_1_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] auto_out_1_d_bits_param_0 = auto_out_1_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] auto_out_1_d_bits_size_0 = auto_out_1_d_bits_size; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_source_0 = auto_out_1_d_bits_source; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_sink_0 = auto_out_1_d_bits_sink; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_denied_0 = auto_out_1_d_bits_denied; // @[BusBypass.scala:66:9] wire [31:0] auto_out_1_d_bits_data_0 = auto_out_1_d_bits_data; // @[BusBypass.scala:66:9] wire auto_out_1_d_bits_corrupt_0 = auto_out_1_d_bits_corrupt; // @[BusBypass.scala:66:9] wire auto_out_0_a_ready_0 = auto_out_0_a_ready; // @[BusBypass.scala:66:9] wire auto_out_0_d_valid_0 = auto_out_0_d_valid; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_d_bits_opcode_0 = auto_out_0_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] auto_out_0_d_bits_param_0 = auto_out_0_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] auto_out_0_d_bits_size_0 = auto_out_0_d_bits_size; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_denied_0 = auto_out_0_d_bits_denied; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_corrupt_0 = auto_out_0_d_bits_corrupt; // @[BusBypass.scala:66:9] wire io_bypass_0 = io_bypass; // @[BusBypass.scala:66:9] wire [4:0] _r_beats1_decode_T_3 = 5'h3; // @[package.scala:243:71] wire [4:0] _r_beats1_decode_T_6 = 5'h3; // @[package.scala:243:71] wire [3:0] _b_inc_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _b_inc_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _b_dec_WIRE_bits_mask = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _b_dec_WIRE_1_bits_mask = 4'h0; // @[Bundles.scala:264:61] wire [8:0] _b_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74] wire [8:0] _b_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61] wire [8:0] _c_inc_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_inc_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _b_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:264:74] wire [8:0] _b_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:264:61] wire [8:0] _c_dec_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_dec_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [4:0] _r_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _stall_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [1:0] _r_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _r_beats1_decode_T_5 = 2'h0; // @[package.scala:243:46] wire [1:0] _r_beats1_decode_T_8 = 2'h0; // @[package.scala:243:46] wire [1:0] _b_inc_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_inc_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _b_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _c_inc_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_inc_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _b_dec_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _b_dec_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _b_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _c_dec_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_dec_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _stall_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [31:0] auto_out_0_d_bits_data = 32'h0; // @[BusBypass.scala:66:9] wire [31:0] nodeOut_d_bits_data = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] _b_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _b_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _c_inc_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_inc_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _b_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _b_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _c_dec_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_dec_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] nodeIn_d_bits_out_data = 32'h0; // @[BusBypass.scala:97:53] wire [3:0] auto_in_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] auto_out_1_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] auto_out_0_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] nodeIn_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [3:0] x1_nodeOut_a_bits_mask = 4'hF; // @[Nodes.scala:27:25] wire [1:0] auto_in_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] auto_out_1_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] auto_out_0_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] nodeIn_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [1:0] x1_nodeOut_a_bits_size = 2'h2; // @[Nodes.scala:27:25] wire [2:0] auto_in_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_a_bits_param = 3'h0; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] _b_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _b_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _c_inc_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_inc_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_inc_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_inc_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _b_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _b_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _c_dec_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_dec_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_dec_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_dec_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [1:0] _r_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _r_beats1_decode_T_4 = 2'h3; // @[package.scala:243:76] wire [1:0] _r_counter1_T_1 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _r_beats1_decode_T_7 = 2'h3; // @[package.scala:243:76] wire [1:0] _r_counter1_T_2 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _r_counter1_T_4 = 2'h3; // @[Edges.scala:230:28] wire [1:0] _stall_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire _r_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_last = 1'h1; // @[Edges.scala:232:33] wire r_beats1_opdata_1 = 1'h1; // @[Edges.scala:97:28] wire r_counter1_1 = 1'h1; // @[Edges.scala:230:28] wire b_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire b_last = 1'h1; // @[Edges.scala:232:33] wire r_counter1_2 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire c_last = 1'h1; // @[Edges.scala:232:33] wire _r_last_T_7 = 1'h1; // @[Edges.scala:232:43] wire d_last = 1'h1; // @[Edges.scala:232:33] wire r_counter1_4 = 1'h1; // @[Edges.scala:230:28] wire e_first = 1'h1; // @[Edges.scala:231:25] wire _r_last_T_9 = 1'h1; // @[Edges.scala:232:43] wire e_last = 1'h1; // @[Edges.scala:232:33] wire c_response = 1'h1; // @[Edges.scala:82:41] wire _stall_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire stall_last = 1'h1; // @[Edges.scala:232:33] wire auto_in_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_in_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_1_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_1_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_a_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_a_bits_corrupt = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_source = 1'h0; // @[BusBypass.scala:66:9] wire auto_out_0_d_bits_sink = 1'h0; // @[BusBypass.scala:66:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire r_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire r_beats1 = 1'h0; // @[Edges.scala:221:14] wire r_4 = 1'h0; // @[Edges.scala:234:25] wire r_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire _r_beats1_opdata_T_1 = 1'h0; // @[Edges.scala:97:37] wire r_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire _r_last_T_2 = 1'h0; // @[Edges.scala:232:25] wire r_3_1 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_1 = 1'h0; // @[Edges.scala:234:27] wire r_4_1 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_1 = 1'h0; // @[Edges.scala:236:21] wire r_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire r_beats1_opdata_2 = 1'h0; // @[Edges.scala:102:36] wire r_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire _r_last_T_4 = 1'h0; // @[Edges.scala:232:25] wire r_3_2 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_2 = 1'h0; // @[Edges.scala:234:27] wire r_4_2 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_2 = 1'h0; // @[Edges.scala:236:21] wire r_beats1_decode_3 = 1'h0; // @[Edges.scala:220:59] wire r_beats1_3 = 1'h0; // @[Edges.scala:221:14] wire r_4_3 = 1'h0; // @[Edges.scala:234:25] wire _r_last_T_8 = 1'h0; // @[Edges.scala:232:25] wire r_3_4 = 1'h0; // @[Edges.scala:233:22] wire _r_count_T_4 = 1'h0; // @[Edges.scala:234:27] wire r_4_4 = 1'h0; // @[Edges.scala:234:25] wire _r_counter_T_4 = 1'h0; // @[Edges.scala:236:21] wire c_request = 1'h0; // @[Edges.scala:68:40] wire _b_inc_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _b_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _b_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _b_inc_T_1 = 1'h0; // @[Edges.scala:311:26] wire b_inc = 1'h0; // @[Edges.scala:311:37] wire _c_inc_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _c_inc_T_1 = 1'h0; // @[Edges.scala:312:26] wire c_inc = 1'h0; // @[Edges.scala:312:37] wire _e_inc_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _e_inc_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _e_inc_T = 1'h0; // @[Decoupled.scala:51:35] wire _e_inc_T_1 = 1'h0; // @[Edges.scala:314:26] wire e_inc = 1'h0; // @[Edges.scala:314:37] wire a_dec = 1'h0; // @[Edges.scala:317:36] wire _b_dec_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _b_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _b_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _b_dec_T_1 = 1'h0; // @[Edges.scala:318:26] wire b_dec = 1'h0; // @[Edges.scala:318:36] wire _c_dec_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _c_dec_T_1 = 1'h0; // @[Edges.scala:319:26] wire c_dec = 1'h0; // @[Edges.scala:319:36] wire _e_dec_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _e_dec_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _e_dec_T = 1'h0; // @[Decoupled.scala:51:35] wire _e_dec_T_1 = 1'h0; // @[Edges.scala:321:26] wire e_dec = 1'h0; // @[Edges.scala:321:36] wire stall_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire stall_beats1 = 1'h0; // @[Edges.scala:221:14] wire stall_count = 1'h0; // @[Edges.scala:234:25] wire nodeIn_d_bits_out_source = 1'h0; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_sink = 1'h0; // @[BusBypass.scala:97:53] wire nodeIn_a_valid = auto_in_a_valid_0; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BusBypass.scala:66:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[BusBypass.scala:66:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire x1_nodeOut_a_ready = auto_out_1_a_ready_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [8:0] x1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_valid = auto_out_1_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] x1_nodeOut_d_bits_opcode = auto_out_1_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] x1_nodeOut_d_bits_param = auto_out_1_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] x1_nodeOut_d_bits_size = auto_out_1_d_bits_size_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_source = auto_out_1_d_bits_source_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_sink = auto_out_1_d_bits_sink_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_denied = auto_out_1_d_bits_denied_0; // @[BusBypass.scala:66:9] wire [31:0] x1_nodeOut_d_bits_data = auto_out_1_d_bits_data_0; // @[BusBypass.scala:66:9] wire x1_nodeOut_d_bits_corrupt = auto_out_1_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire nodeOut_a_ready = auto_out_0_a_ready_0; // @[BusBypass.scala:66:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [127:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_0_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_0_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] nodeOut_d_bits_param = auto_out_0_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] nodeOut_d_bits_size = auto_out_0_d_bits_size_0; // @[BusBypass.scala:66:9] wire nodeOut_d_bits_denied = auto_out_0_d_bits_denied_0; // @[BusBypass.scala:66:9] wire nodeOut_d_bits_corrupt = auto_out_0_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire _io_pending_T; // @[BusBypass.scala:84:27] wire auto_in_a_ready_0; // @[BusBypass.scala:66:9] wire [2:0] auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9] wire [1:0] auto_in_d_bits_param_0; // @[BusBypass.scala:66:9] wire [1:0] auto_in_d_bits_size_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_source_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9] wire [31:0] auto_in_d_bits_data_0; // @[BusBypass.scala:66:9] wire auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9] wire auto_in_d_valid_0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [8:0] auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9] wire auto_out_1_a_valid_0; // @[BusBypass.scala:66:9] wire auto_out_1_d_ready_0; // @[BusBypass.scala:66:9] wire [2:0] auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9] wire [127:0] auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9] wire [31:0] auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9] wire auto_out_0_a_valid_0; // @[BusBypass.scala:66:9] wire auto_out_0_d_ready_0; // @[BusBypass.scala:66:9] wire io_pending; // @[BusBypass.scala:66:9] wire _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BusBypass.scala:66:9] assign nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_opcode = nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_address = nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] assign nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_a_bits_data = nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17] wire _nodeIn_d_valid_T; // @[BusBypass.scala:96:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BusBypass.scala:66:9] wire [2:0] _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[BusBypass.scala:66:9] wire [1:0] _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[BusBypass.scala:66:9] wire [1:0] _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[BusBypass.scala:66:9] wire [31:0] _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BusBypass.scala:66:9] wire _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[BusBypass.scala:66:9] wire _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42] assign auto_out_0_a_valid_0 = nodeOut_a_valid; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_address_0 = nodeOut_a_bits_address; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_data_0 = nodeOut_a_bits_data; // @[BusBypass.scala:66:9] wire _nodeOut_d_ready_T; // @[BusBypass.scala:94:32] assign auto_out_0_d_ready_0 = nodeOut_d_ready; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_d_bits_out_opcode = nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_param = nodeOut_d_bits_param; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_size = nodeOut_d_bits_size; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_denied = nodeOut_d_bits_denied; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_corrupt = nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53] wire _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42] assign auto_out_1_a_valid_0 = x1_nodeOut_a_valid; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_opcode_0 = x1_nodeOut_a_bits_opcode; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_address_0 = x1_nodeOut_a_bits_address; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_data_0 = x1_nodeOut_a_bits_data; // @[BusBypass.scala:66:9] wire _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32] assign auto_out_1_d_ready_0 = x1_nodeOut_d_ready; // @[BusBypass.scala:66:9] wire [2:0] nodeIn_d_bits_out_1_opcode = x1_nodeOut_d_bits_opcode; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_1_param = x1_nodeOut_d_bits_param; // @[BusBypass.scala:97:53] wire [1:0] nodeIn_d_bits_out_1_size = x1_nodeOut_d_bits_size; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_source = x1_nodeOut_d_bits_source; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_sink = x1_nodeOut_d_bits_sink; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_denied = x1_nodeOut_d_bits_denied; // @[BusBypass.scala:97:53] wire [31:0] nodeIn_d_bits_out_1_data = x1_nodeOut_d_bits_data; // @[BusBypass.scala:97:53] wire nodeIn_d_bits_out_1_corrupt = x1_nodeOut_d_bits_corrupt; // @[BusBypass.scala:97:53] reg in_reset; // @[BusBypass.scala:79:27] reg bypass_reg; // @[BusBypass.scala:80:25] wire bypass = in_reset ? io_bypass_0 : bypass_reg; // @[BusBypass.scala:66:9, :79:27, :80:25, :81:21] reg [1:0] flight; // @[Edges.scala:295:25] wire _T = nodeIn_a_ready & nodeIn_a_valid; // @[Decoupled.scala:51:35] wire r_3; // @[Edges.scala:233:22] assign r_3 = _T; // @[Decoupled.scala:51:35] wire _a_inc_T; // @[Decoupled.scala:51:35] assign _a_inc_T = _T; // @[Decoupled.scala:51:35] wire _a_dec_T; // @[Decoupled.scala:51:35] assign _a_dec_T = _T; // @[Decoupled.scala:51:35] wire _stall_T_1; // @[Decoupled.scala:51:35] assign _stall_T_1 = _T; // @[Decoupled.scala:51:35] wire _r_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire _stall_beats1_opdata_T = nodeIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire r_beats1_opdata = ~_r_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg r_counter; // @[Edges.scala:229:27] wire _r_last_T = r_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _r_counter1_T = {1'h0, r_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire r_counter1 = _r_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~r_counter; // @[Edges.scala:229:27, :231:25] wire _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire _r_counter_T = ~a_first & r_counter1; // @[Edges.scala:230:28, :231:25, :236:21] wire _T_3 = nodeIn_d_ready & nodeIn_d_valid; // @[Decoupled.scala:51:35] wire r_3_3; // @[Edges.scala:233:22] assign r_3_3 = _T_3; // @[Decoupled.scala:51:35] wire _d_inc_T; // @[Decoupled.scala:51:35] assign _d_inc_T = _T_3; // @[Decoupled.scala:51:35] wire _d_dec_T; // @[Decoupled.scala:51:35] assign _d_dec_T = _T_3; // @[Decoupled.scala:51:35] wire [4:0] _r_beats1_decode_T_9 = 5'h3 << nodeIn_d_bits_size; // @[package.scala:243:71] wire [1:0] _r_beats1_decode_T_10 = _r_beats1_decode_T_9[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _r_beats1_decode_T_11 = ~_r_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire r_beats1_opdata_3 = nodeIn_d_bits_opcode[0]; // @[Edges.scala:106:36] reg r_counter_3; // @[Edges.scala:229:27] wire _r_last_T_6 = r_counter_3; // @[Edges.scala:229:27, :232:25] wire [1:0] _r_counter1_T_3 = {1'h0, r_counter_3} - 2'h1; // @[Edges.scala:229:27, :230:28] wire r_counter1_3 = _r_counter1_T_3[0]; // @[Edges.scala:230:28] wire d_first = ~r_counter_3; // @[Edges.scala:229:27, :231:25] wire _r_count_T_3 = ~r_counter1_3; // @[Edges.scala:230:28, :234:27] wire _r_counter_T_3 = ~d_first & r_counter1_3; // @[Edges.scala:230:28, :231:25, :236:21] wire d_request = nodeIn_d_bits_opcode[2] & ~(nodeIn_d_bits_opcode[1]); // @[Edges.scala:71:{36,40,43,52}] wire _a_inc_T_1 = _a_inc_T & a_first; // @[Decoupled.scala:51:35] wire a_inc = _a_inc_T_1; // @[Edges.scala:310:{26,37}] wire _d_inc_T_1 = _d_inc_T & d_first; // @[Decoupled.scala:51:35] wire d_inc = _d_inc_T_1 & d_request; // @[Edges.scala:71:40, :313:{26,37}] wire [1:0] inc = {a_inc, d_inc}; // @[Edges.scala:310:37, :313:37, :315:18] wire _a_dec_T_1 = _a_dec_T; // @[Decoupled.scala:51:35] wire _d_dec_T_1 = _d_dec_T; // @[Decoupled.scala:51:35] wire d_dec = _d_dec_T_1; // @[Edges.scala:320:{26,36}] wire [1:0] dec = {1'h0, d_dec}; // @[Edges.scala:320:36, :322:18] wire _next_flight_T = inc[0]; // @[Edges.scala:315:18, :324:40] wire _next_flight_T_1 = inc[1]; // @[Edges.scala:315:18, :324:40] wire [1:0] _next_flight_T_2 = {1'h0, _next_flight_T} + {1'h0, _next_flight_T_1}; // @[Edges.scala:324:40] wire [1:0] _next_flight_T_3 = _next_flight_T_2; // @[Edges.scala:324:40] wire [2:0] _next_flight_T_4 = {1'h0, flight} + {1'h0, _next_flight_T_3}; // @[Edges.scala:295:25, :324:{30,40}] wire [1:0] _next_flight_T_5 = _next_flight_T_4[1:0]; // @[Edges.scala:324:30] wire _next_flight_T_6 = dec[0]; // @[Edges.scala:322:18, :324:56] wire _next_flight_T_7 = dec[1]; // @[Edges.scala:322:18, :324:56] wire [1:0] _next_flight_T_8 = {1'h0, _next_flight_T_6} + {1'h0, _next_flight_T_7}; // @[Edges.scala:324:56] wire [1:0] _next_flight_T_9 = _next_flight_T_8; // @[Edges.scala:324:56] wire [2:0] _next_flight_T_10 = {1'h0, _next_flight_T_5} - {1'h0, _next_flight_T_9}; // @[Edges.scala:324:{30,46,56}] wire [1:0] next_flight = _next_flight_T_10[1:0]; // @[Edges.scala:324:46] assign _io_pending_T = \|flight; // @[Edges.scala:295:25] assign io_pending = _io_pending_T; // @[BusBypass.scala:66:9, :84:27] wire _stall_T = bypass != io_bypass_0; // @[BusBypass.scala:66:9, :81:21, :86:25] wire stall_done = _stall_T_1; // @[Decoupled.scala:51:35] wire stall_beats1_opdata = ~_stall_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg stall_counter; // @[Edges.scala:229:27] wire _stall_last_T = stall_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _stall_counter1_T = {1'h0, stall_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire stall_counter1 = _stall_counter1_T[0]; // @[Edges.scala:230:28] wire stall_first = ~stall_counter; // @[Edges.scala:229:27, :231:25] wire _stall_count_T = ~stall_counter1; // @[Edges.scala:230:28, :234:27] wire _stall_counter_T = ~stall_first & stall_counter1; // @[Edges.scala:230:28, :231:25, :236:21] wire stall = _stall_T & stall_first; // @[Edges.scala:231:25] wire _nodeOut_a_valid_T = ~stall; // @[BusBypass.scala:86:40, :88:21] wire _nodeOut_a_valid_T_1 = _nodeOut_a_valid_T & nodeIn_a_valid; // @[BusBypass.scala:88:{21,28}] assign _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T_1 & bypass; // @[BusBypass.scala:81:21, :88:{28,42}] assign nodeOut_a_valid = _nodeOut_a_valid_T_2; // @[BusBypass.scala:88:42] wire _nodeOut_a_valid_T_3 = ~stall; // @[BusBypass.scala:86:40, :88:21, :89:21] wire _nodeOut_a_valid_T_4 = _nodeOut_a_valid_T_3 & nodeIn_a_valid; // @[BusBypass.scala:89:{21,28}] wire _nodeOut_a_valid_T_5 = ~bypass; // @[BusBypass.scala:81:21, :89:45] assign _nodeOut_a_valid_T_6 = _nodeOut_a_valid_T_4 & _nodeOut_a_valid_T_5; // @[BusBypass.scala:89:{28,42,45}] assign x1_nodeOut_a_valid = _nodeOut_a_valid_T_6; // @[BusBypass.scala:89:42] wire _nodeIn_a_ready_T = ~stall; // @[BusBypass.scala:86:40, :88:21, :90:21] wire _nodeIn_a_ready_T_1 = bypass ? nodeOut_a_ready : x1_nodeOut_a_ready; // @[BusBypass.scala:81:21, :90:34] assign _nodeIn_a_ready_T_2 = _nodeIn_a_ready_T & _nodeIn_a_ready_T_1; // @[BusBypass.scala:90:{21,28,34}] assign nodeIn_a_ready = _nodeIn_a_ready_T_2; // @[BusBypass.scala:90:28] assign nodeOut_a_bits_address = {119'h0, nodeIn_a_bits_address}; // @[BusBypass.scala:91:18] assign _nodeOut_d_ready_T = nodeIn_d_ready & bypass; // @[BusBypass.scala:81:21, :94:32] assign nodeOut_d_ready = _nodeOut_d_ready_T; // @[BusBypass.scala:94:32] wire _nodeOut_d_ready_T_1 = ~bypass; // @[BusBypass.scala:81:21, :89:45, :95:35] assign _nodeOut_d_ready_T_2 = nodeIn_d_ready & _nodeOut_d_ready_T_1; // @[BusBypass.scala:95:{32,35}] assign x1_nodeOut_d_ready = _nodeOut_d_ready_T_2; // @[BusBypass.scala:95:32] assign _nodeIn_d_valid_T = bypass ? nodeOut_d_valid : x1_nodeOut_d_valid; // @[BusBypass.scala:81:21, :96:24] assign nodeIn_d_valid = _nodeIn_d_valid_T; // @[BusBypass.scala:96:24] assign _nodeIn_d_bits_T_opcode = bypass ? nodeIn_d_bits_out_opcode : nodeIn_d_bits_out_1_opcode; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_param = bypass ? nodeIn_d_bits_out_param : nodeIn_d_bits_out_1_param; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_size = bypass ? nodeIn_d_bits_out_size : nodeIn_d_bits_out_1_size; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_source = ~bypass & nodeIn_d_bits_out_1_source; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_sink = ~bypass & nodeIn_d_bits_out_1_sink; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_denied = bypass ? nodeIn_d_bits_out_denied : nodeIn_d_bits_out_1_denied; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_data = bypass ? 32'h0 : nodeIn_d_bits_out_1_data; // @[BusBypass.scala:81:21, :97:53, :98:21] assign _nodeIn_d_bits_T_corrupt = bypass ? nodeIn_d_bits_out_corrupt : nodeIn_d_bits_out_1_corrupt; // @[BusBypass.scala:81:21, :97:53, :98:21] assign nodeIn_d_bits_opcode = _nodeIn_d_bits_T_opcode; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_param = _nodeIn_d_bits_T_param; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_size = _nodeIn_d_bits_T_size; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_source = _nodeIn_d_bits_T_source; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_sink = _nodeIn_d_bits_T_sink; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_denied = _nodeIn_d_bits_T_denied; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_data = _nodeIn_d_bits_T_data; // @[BusBypass.scala:98:21] assign nodeIn_d_bits_corrupt = _nodeIn_d_bits_T_corrupt; // @[BusBypass.scala:98:21] always @(posedge clock) begin // @[BusBypass.scala:66:9] if (reset) begin // @[BusBypass.scala:66:9] in_reset <= 1'h1; // @[BusBypass.scala:79:27] flight <= 2'h0; // @[Edges.scala:295:25] r_counter <= 1'h0; // @[Edges.scala:229:27] r_counter_3 <= 1'h0; // @[Edges.scala:229:27] stall_counter <= 1'h0; // @[Edges.scala:229:27] end else begin // @[BusBypass.scala:66:9] in_reset <= 1'h0; // @[BusBypass.scala:79:27] flight <= next_flight; // @[Edges.scala:295:25, :324:46] if (_T) // @[Decoupled.scala:51:35] r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21] if (_T_3) // @[Decoupled.scala:51:35] r_counter_3 <= _r_counter_T_3; // @[Edges.scala:229:27, :236:21] if (_stall_T_1) // @[Decoupled.scala:51:35] stall_counter <= _stall_counter_T; // @[Edges.scala:229:27, :236:21] end if (in_reset \| next_flight == 2'h0) // @[Edges.scala:324:46] bypass_reg <= io_bypass_0; // @[BusBypass.scala:66:9, :80:25] always @(posedge) TLMonitor_59 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_in_a_ready = auto_in_a_ready_0; // @[BusBypass.scala:66:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BusBypass.scala:66:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_valid = auto_out_1_a_valid_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_opcode = auto_out_1_a_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_address = auto_out_1_a_bits_address_0; // @[BusBypass.scala:66:9] assign auto_out_1_a_bits_data = auto_out_1_a_bits_data_0; // @[BusBypass.scala:66:9] assign auto_out_1_d_ready = auto_out_1_d_ready_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_valid = auto_out_0_a_valid_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_opcode = auto_out_0_a_bits_opcode_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_address = auto_out_0_a_bits_address_0; // @[BusBypass.scala:66:9] assign auto_out_0_a_bits_data = auto_out_0_a_bits_data_0; // @[BusBypass.scala:66:9] assign auto_out_0_d_ready = auto_out_0_d_ready_0; // @[BusBypass.scala:66:9] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Metadata.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import freechips.rocketchip.rocket.constants.MemoryOpConstants import freechips.rocketchip.util._ object ClientStates { val width = 2 def Nothing = 0.U(width.W) def Branch = 1.U(width.W) def Trunk = 2.U(width.W) def Dirty = 3.U(width.W) def hasReadPermission(state: UInt): Bool = state > Nothing def hasWritePermission(state: UInt): Bool = state > Branch } object MemoryOpCategories extends MemoryOpConstants { def wr = Cat(true.B, true.B) // Op actually writes def wi = Cat(false.B, true.B) // Future op will write def rd = Cat(false.B, false.B) // Op only reads def categorize(cmd: UInt): UInt = { val cat = Cat(isWrite(cmd), isWriteIntent(cmd)) //assert(cat.isOneOf(wr,wi,rd), "Could not categorize command.") cat } } /* Stores the client-side coherence information, * such as permissions on the data and whether the data is dirty. * Its API can be used to make TileLink messages in response to * memory operations, cache control oeprations, or Probe messages. / class ClientMetadata extends Bundle { /* Actual state information stored in this bundle / val state = UInt(ClientStates.width.W) /* Metadata equality / def ===(rhs: UInt): Bool = state === rhs def ===(rhs: ClientMetadata): Bool = state === rhs.state def =/=(rhs: ClientMetadata): Bool = !this.===(rhs) /* Is the block's data present in this cache / def isValid(dummy: Int = 0): Bool = state > ClientStates.Nothing /* Determine whether this cmd misses, and the new state (on hit) or param to be sent (on miss) / private def growStarter(cmd: UInt): (Bool, UInt) = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) MuxTLookup(Cat(c, state), (false.B, 0.U), Seq( //(effect, am now) -> (was a hit, next) Cat(rd, Dirty) -> (true.B, Dirty), Cat(rd, Trunk) -> (true.B, Trunk), Cat(rd, Branch) -> (true.B, Branch), Cat(wi, Dirty) -> (true.B, Dirty), Cat(wi, Trunk) -> (true.B, Trunk), Cat(wr, Dirty) -> (true.B, Dirty), Cat(wr, Trunk) -> (true.B, Dirty), //(effect, am now) -> (was a miss, param) Cat(rd, Nothing) -> (false.B, NtoB), Cat(wi, Branch) -> (false.B, BtoT), Cat(wi, Nothing) -> (false.B, NtoT), Cat(wr, Branch) -> (false.B, BtoT), Cat(wr, Nothing) -> (false.B, NtoT))) } /* Determine what state to go to after miss based on Grant param * For now, doesn't depend on state (which may have been Probed). / private def growFinisher(cmd: UInt, param: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ import ClientStates._ val c = categorize(cmd) //assert(c === rd \|\| param === toT, "Client was expecting trunk permissions.") MuxLookup(Cat(c, param), Nothing)(Seq( //(effect param) -> (next) Cat(rd, toB) -> Branch, Cat(rd, toT) -> Trunk, Cat(wi, toT) -> Trunk, Cat(wr, toT) -> Dirty)) } /* Does this cache have permissions on this block sufficient to perform op, * and what to do next (Acquire message param or updated metadata). / def onAccess(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = growStarter(cmd) (r._1, r._2, ClientMetadata(r._2)) } /* Does a secondary miss on the block require another Acquire message / def onSecondaryAccess(first_cmd: UInt, second_cmd: UInt): (Bool, Bool, UInt, ClientMetadata, UInt) = { import MemoryOpCategories._ val r1 = growStarter(first_cmd) val r2 = growStarter(second_cmd) val needs_second_acq = isWriteIntent(second_cmd) && !isWriteIntent(first_cmd) val hit_again = r1._1 && r2._1 val dirties = categorize(second_cmd) === wr val biggest_grow_param = Mux(dirties, r2._2, r1._2) val dirtiest_state = ClientMetadata(biggest_grow_param) val dirtiest_cmd = Mux(dirties, second_cmd, first_cmd) (needs_second_acq, hit_again, biggest_grow_param, dirtiest_state, dirtiest_cmd) } /* Metadata change on a returned Grant / def onGrant(cmd: UInt, param: UInt): ClientMetadata = ClientMetadata(growFinisher(cmd, param)) /* Determine what state to go to based on Probe param / private def shrinkHelper(param: UInt): (Bool, UInt, UInt) = { import ClientStates._ import TLPermissions._ MuxTLookup(Cat(param, state), (false.B, 0.U, 0.U), Seq( //(wanted, am now) -> (hasDirtyData resp, next) Cat(toT, Dirty) -> (true.B, TtoT, Trunk), Cat(toT, Trunk) -> (false.B, TtoT, Trunk), Cat(toT, Branch) -> (false.B, BtoB, Branch), Cat(toT, Nothing) -> (false.B, NtoN, Nothing), Cat(toB, Dirty) -> (true.B, TtoB, Branch), Cat(toB, Trunk) -> (false.B, TtoB, Branch), // Policy: Don't notify on clean downgrade Cat(toB, Branch) -> (false.B, BtoB, Branch), Cat(toB, Nothing) -> (false.B, NtoN, Nothing), Cat(toN, Dirty) -> (true.B, TtoN, Nothing), Cat(toN, Trunk) -> (false.B, TtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Branch) -> (false.B, BtoN, Nothing), // Policy: Don't notify on clean downgrade Cat(toN, Nothing) -> (false.B, NtoN, Nothing))) } /* Translate cache control cmds into Probe param / private def cmdToPermCap(cmd: UInt): UInt = { import MemoryOpCategories._ import TLPermissions._ MuxLookup(cmd, toN)(Seq( M_FLUSH -> toN, M_PRODUCE -> toB, M_CLEAN -> toT)) } def onCacheControl(cmd: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(cmdToPermCap(cmd)) (r._1, r._2, ClientMetadata(r._3)) } def onProbe(param: UInt): (Bool, UInt, ClientMetadata) = { val r = shrinkHelper(param) (r._1, r._2, ClientMetadata(r._3)) } } /* Factories for ClientMetadata, including on reset / object ClientMetadata { def apply(perm: UInt) = { val meta = Wire(new ClientMetadata) meta.state := perm meta } def onReset = ClientMetadata(ClientStates.Nothing) def maximum = ClientMetadata(ClientStates.Dirty) } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) \|\| isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR \|\| cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) \|\| isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR \|\| cmd === M_PWR \|\| cmd === M_XSC \|\| isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) \|\| cmd === M_PFW \|\| cmd === M_XLR } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File mshrs.scala: //***************************************************************************** // Ported from Rocket-Chip // See LICENSE.Berkeley and LICENSE.SiFive in Rocket-Chip for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v3.lsu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.rocket._ import boom.v3.common._ import boom.v3.exu.BrUpdateInfo import boom.v3.util.{IsKilledByBranch, GetNewBrMask, BranchKillableQueue, IsOlder, UpdateBrMask, AgePriorityEncoder, WrapInc} class BoomDCacheReqInternal(implicit p: Parameters) extends BoomDCacheReq()(p) with HasL1HellaCacheParameters { // miss info val tag_match = Bool() val old_meta = new L1Metadata val way_en = UInt(nWays.W) // Used in the MSHRs val sdq_id = UInt(log2Ceil(cfg.nSDQ).W) } class BoomMSHR(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p) with HasL1HellaCacheParameters { val io = IO(new Bundle { val id = Input(UInt()) val req_pri_val = Input(Bool()) val req_pri_rdy = Output(Bool()) val req_sec_val = Input(Bool()) val req_sec_rdy = Output(Bool()) val clear_prefetch = Input(Bool()) val brupdate = Input(new BrUpdateInfo) val exception = Input(Bool()) val rob_pnr_idx = Input(UInt(robAddrSz.W)) val rob_head_idx = Input(UInt(robAddrSz.W)) val req = Input(new BoomDCacheReqInternal) val req_is_probe = Input(Bool()) val idx = Output(Valid(UInt())) val way = Output(Valid(UInt())) val tag = Output(Valid(UInt())) val mem_acquire = Decoupled(new TLBundleA(edge.bundle)) val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle))) val mem_finish = Decoupled(new TLBundleE(edge.bundle)) val prober_state = Input(Valid(UInt(coreMaxAddrBits.W))) val refill = Decoupled(new L1DataWriteReq) val meta_write = Decoupled(new L1MetaWriteReq) val meta_read = Decoupled(new L1MetaReadReq) val meta_resp = Input(Valid(new L1Metadata)) val wb_req = Decoupled(new WritebackReq(edge.bundle)) // To inform the prefetcher when we are commiting the fetch of this line val commit_val = Output(Bool()) val commit_addr = Output(UInt(coreMaxAddrBits.W)) val commit_coh = Output(new ClientMetadata) // Reading from the line buffer val lb_read = Decoupled(new LineBufferReadReq) val lb_resp = Input(UInt(encRowBits.W)) val lb_write = Decoupled(new LineBufferWriteReq) // Replays go through the cache pipeline again val replay = Decoupled(new BoomDCacheReqInternal) // Resp go straight out to the core val resp = Decoupled(new BoomDCacheResp) // Writeback unit tells us when it is done processing our wb val wb_resp = Input(Bool()) val probe_rdy = Output(Bool()) }) // TODO: Optimize this. We don't want to mess with cache during speculation // s_refill_req : Make a request for a new cache line // s_refill_resp : Store the refill response into our buffer // s_drain_rpq_loads : Drain out loads from the rpq // : If miss was misspeculated, go to s_invalid // s_wb_req : Write back the evicted cache line // s_wb_resp : Finish writing back the evicted cache line // s_meta_write_req : Write the metadata for new cache lne // s_meta_write_resp : val s_invalid :: s_refill_req :: s_refill_resp :: s_drain_rpq_loads :: s_meta_read :: s_meta_resp_1 :: s_meta_resp_2 :: s_meta_clear :: s_wb_meta_read :: s_wb_req :: s_wb_resp :: s_commit_line :: s_drain_rpq :: s_meta_write_req :: s_mem_finish_1 :: s_mem_finish_2 :: s_prefetched :: s_prefetch :: Nil = Enum(18) val state = RegInit(s_invalid) val req = Reg(new BoomDCacheReqInternal) val req_idx = req.addr(untagBits-1, blockOffBits) val req_tag = req.addr >> untagBits val req_block_addr = (req.addr >> blockOffBits) << blockOffBits val req_needs_wb = RegInit(false.B) val new_coh = RegInit(ClientMetadata.onReset) val (_, shrink_param, coh_on_clear) = req.old_meta.coh.onCacheControl(M_FLUSH) val grow_param = new_coh.onAccess(req.uop.mem_cmd)._2 val coh_on_grant = new_coh.onGrant(req.uop.mem_cmd, io.mem_grant.bits.param) // We only accept secondary misses if the original request had sufficient permissions val (cmd_requires_second_acquire, is_hit_again, _, dirtier_coh, dirtier_cmd) = new_coh.onSecondaryAccess(req.uop.mem_cmd, io.req.uop.mem_cmd) val (_, _, refill_done, refill_address_inc) = edge.addr_inc(io.mem_grant) val sec_rdy = (!cmd_requires_second_acquire && !io.req_is_probe && !state.isOneOf(s_invalid, s_meta_write_req, s_mem_finish_1, s_mem_finish_2))// Always accept secondary misses val rpq = Module(new BranchKillableQueue(new BoomDCacheReqInternal, cfg.nRPQ, u => u.uses_ldq, false)) rpq.io.brupdate := io.brupdate rpq.io.flush := io.exception assert(!(state === s_invalid && !rpq.io.empty)) rpq.io.enq.valid := ((io.req_pri_val && io.req_pri_rdy) \|\| (io.req_sec_val && io.req_sec_rdy)) && !isPrefetch(io.req.uop.mem_cmd) rpq.io.enq.bits := io.req rpq.io.deq.ready := false.B val grantack = Reg(Valid(new TLBundleE(edge.bundle))) val refill_ctr = Reg(UInt(log2Ceil(cacheDataBeats).W)) val commit_line = Reg(Bool()) val grant_had_data = Reg(Bool()) val finish_to_prefetch = Reg(Bool()) // Block probes if a tag write we started is still in the pipeline val meta_hazard = RegInit(0.U(2.W)) when (meta_hazard =/= 0.U) { meta_hazard := meta_hazard + 1.U } when (io.meta_write.fire) { meta_hazard := 1.U } io.probe_rdy := (meta_hazard === 0.U && (state.isOneOf(s_invalid, s_refill_req, s_refill_resp, s_drain_rpq_loads) \|\| (state === s_meta_read && grantack.valid))) io.idx.valid := state =/= s_invalid io.tag.valid := state =/= s_invalid io.way.valid := !state.isOneOf(s_invalid, s_prefetch) io.idx.bits := req_idx io.tag.bits := req_tag io.way.bits := req.way_en io.meta_write.valid := false.B io.meta_write.bits := DontCare io.req_pri_rdy := false.B io.req_sec_rdy := sec_rdy && rpq.io.enq.ready io.mem_acquire.valid := false.B io.mem_acquire.bits := DontCare io.refill.valid := false.B io.refill.bits := DontCare io.replay.valid := false.B io.replay.bits := DontCare io.wb_req.valid := false.B io.wb_req.bits := DontCare io.resp.valid := false.B io.resp.bits := DontCare io.commit_val := false.B io.commit_addr := req.addr io.commit_coh := coh_on_grant io.meta_read.valid := false.B io.meta_read.bits := DontCare io.mem_finish.valid := false.B io.mem_finish.bits := DontCare io.lb_write.valid := false.B io.lb_write.bits := DontCare io.lb_read.valid := false.B io.lb_read.bits := DontCare io.mem_grant.ready := false.B when (io.req_sec_val && io.req_sec_rdy) { req.uop.mem_cmd := dirtier_cmd when (is_hit_again) { new_coh := dirtier_coh } } def handle_pri_req(old_state: UInt): UInt = { val new_state = WireInit(old_state) grantack.valid := false.B refill_ctr := 0.U assert(rpq.io.enq.ready) req := io.req val old_coh = io.req.old_meta.coh req_needs_wb := old_coh.onCacheControl(M_FLUSH)._1 // does the line we are evicting need to be written back when (io.req.tag_match) { val (is_hit, _, coh_on_hit) = old_coh.onAccess(io.req.uop.mem_cmd) when (is_hit) { // set dirty bit assert(isWrite(io.req.uop.mem_cmd)) new_coh := coh_on_hit new_state := s_drain_rpq } .otherwise { // upgrade permissions new_coh := old_coh new_state := s_refill_req } } .otherwise { // refill and writeback if necessary new_coh := ClientMetadata.onReset new_state := s_refill_req } new_state } when (state === s_invalid) { io.req_pri_rdy := true.B grant_had_data := false.B when (io.req_pri_val && io.req_pri_rdy) { state := handle_pri_req(state) } } .elsewhen (state === s_refill_req) { io.mem_acquire.valid := true.B // TODO: Use AcquirePerm if just doing permissions acquire io.mem_acquire.bits := edge.AcquireBlock( fromSource = io.id, toAddress = Cat(req_tag, req_idx) << blockOffBits, lgSize = lgCacheBlockBytes.U, growPermissions = grow_param)._2 when (io.mem_acquire.fire) { state := s_refill_resp } } .elsewhen (state === s_refill_resp) { when (edge.hasData(io.mem_grant.bits)) { io.mem_grant.ready := io.lb_write.ready io.lb_write.valid := io.mem_grant.valid io.lb_write.bits.id := io.id io.lb_write.bits.offset := refill_address_inc >> rowOffBits io.lb_write.bits.data := io.mem_grant.bits.data } .otherwise { io.mem_grant.ready := true.B } when (io.mem_grant.fire) { grant_had_data := edge.hasData(io.mem_grant.bits) } when (refill_done) { grantack.valid := edge.isRequest(io.mem_grant.bits) grantack.bits := edge.GrantAck(io.mem_grant.bits) state := Mux(grant_had_data, s_drain_rpq_loads, s_drain_rpq) assert(!(!grant_had_data && req_needs_wb)) commit_line := false.B new_coh := coh_on_grant } } .elsewhen (state === s_drain_rpq_loads) { val drain_load = (isRead(rpq.io.deq.bits.uop.mem_cmd) && !isWrite(rpq.io.deq.bits.uop.mem_cmd) && (rpq.io.deq.bits.uop.mem_cmd =/= M_XLR)) // LR should go through replay // drain all loads for now val rp_addr = Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)) val word_idx = if (rowWords == 1) 0.U else rp_addr(log2Up(rowWordscoreDataBytes)-1, log2Up(wordBytes)) val data = io.lb_resp val data_word = data >> Cat(word_idx, 0.U(log2Up(coreDataBits).W)) val loadgen = new LoadGen(rpq.io.deq.bits.uop.mem_size, rpq.io.deq.bits.uop.mem_signed, Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)), data_word, false.B, wordBytes) rpq.io.deq.ready := io.resp.ready && io.lb_read.ready && drain_load io.lb_read.valid := rpq.io.deq.valid && drain_load io.lb_read.bits.id := io.id io.lb_read.bits.offset := rpq.io.deq.bits.addr >> rowOffBits io.resp.valid := rpq.io.deq.valid && io.lb_read.fire && drain_load io.resp.bits.uop := rpq.io.deq.bits.uop io.resp.bits.data := loadgen.data io.resp.bits.is_hella := rpq.io.deq.bits.is_hella when (rpq.io.deq.fire) { commit_line := true.B } .elsewhen (rpq.io.empty && !commit_line) { when (!rpq.io.enq.fire) { state := s_mem_finish_1 finish_to_prefetch := enablePrefetching.B } } .elsewhen (rpq.io.empty \|\| (rpq.io.deq.valid && !drain_load)) { // io.commit_val is for the prefetcher. it tells the prefetcher that this line was correctly acquired // The prefetcher should consider fetching the next line io.commit_val := true.B state := s_meta_read } } .elsewhen (state === s_meta_read) { io.meta_read.valid := !io.prober_state.valid \|\| !grantack.valid \|\| (io.prober_state.bits(untagBits-1,blockOffBits) =/= req_idx) io.meta_read.bits.idx := req_idx io.meta_read.bits.tag := req_tag io.meta_read.bits.way_en := req.way_en when (io.meta_read.fire) { state := s_meta_resp_1 } } .elsewhen (state === s_meta_resp_1) { state := s_meta_resp_2 } .elsewhen (state === s_meta_resp_2) { val needs_wb = io.meta_resp.bits.coh.onCacheControl(M_FLUSH)._1 state := Mux(!io.meta_resp.valid, s_meta_read, // Prober could have nack'd this read Mux(needs_wb, s_meta_clear, s_commit_line)) } .elsewhen (state === s_meta_clear) { io.meta_write.valid := true.B io.meta_write.bits.idx := req_idx io.meta_write.bits.data.coh := coh_on_clear io.meta_write.bits.data.tag := req_tag io.meta_write.bits.way_en := req.way_en when (io.meta_write.fire) { state := s_wb_req } } .elsewhen (state === s_wb_req) { io.wb_req.valid := true.B io.wb_req.bits.tag := req.old_meta.tag io.wb_req.bits.idx := req_idx io.wb_req.bits.param := shrink_param io.wb_req.bits.way_en := req.way_en io.wb_req.bits.source := io.id io.wb_req.bits.voluntary := true.B when (io.wb_req.fire) { state := s_wb_resp } } .elsewhen (state === s_wb_resp) { when (io.wb_resp) { state := s_commit_line } } .elsewhen (state === s_commit_line) { io.lb_read.valid := true.B io.lb_read.bits.id := io.id io.lb_read.bits.offset := refill_ctr io.refill.valid := io.lb_read.fire io.refill.bits.addr := req_block_addr \| (refill_ctr << rowOffBits) io.refill.bits.way_en := req.way_en io.refill.bits.wmask := ~(0.U(rowWords.W)) io.refill.bits.data := io.lb_resp when (io.refill.fire) { refill_ctr := refill_ctr + 1.U when (refill_ctr === (cacheDataBeats - 1).U) { state := s_drain_rpq } } } .elsewhen (state === s_drain_rpq) { io.replay <> rpq.io.deq io.replay.bits.way_en := req.way_en io.replay.bits.addr := Cat(req_tag, req_idx, rpq.io.deq.bits.addr(blockOffBits-1,0)) when (io.replay.fire && isWrite(rpq.io.deq.bits.uop.mem_cmd)) { // Set dirty bit val (is_hit, _, coh_on_hit) = new_coh.onAccess(rpq.io.deq.bits.uop.mem_cmd) assert(is_hit, "We still don't have permissions for this store") new_coh := coh_on_hit } when (rpq.io.empty && !rpq.io.enq.valid) { state := s_meta_write_req } } .elsewhen (state === s_meta_write_req) { io.meta_write.valid := true.B io.meta_write.bits.idx := req_idx io.meta_write.bits.data.coh := new_coh io.meta_write.bits.data.tag := req_tag io.meta_write.bits.way_en := req.way_en when (io.meta_write.fire) { state := s_mem_finish_1 finish_to_prefetch := false.B } } .elsewhen (state === s_mem_finish_1) { io.mem_finish.valid := grantack.valid io.mem_finish.bits := grantack.bits when (io.mem_finish.fire \|\| !grantack.valid) { grantack.valid := false.B state := s_mem_finish_2 } } .elsewhen (state === s_mem_finish_2) { state := Mux(finish_to_prefetch, s_prefetch, s_invalid) } .elsewhen (state === s_prefetch) { io.req_pri_rdy := true.B when ((io.req_sec_val && !io.req_sec_rdy) \|\| io.clear_prefetch) { state := s_invalid } .elsewhen (io.req_sec_val && io.req_sec_rdy) { val (is_hit, _, coh_on_hit) = new_coh.onAccess(io.req.uop.mem_cmd) when (is_hit) { // Proceed with refill new_coh := coh_on_hit state := s_meta_read } .otherwise { // Reacquire this line new_coh := ClientMetadata.onReset state := s_refill_req } } .elsewhen (io.req_pri_val && io.req_pri_rdy) { grant_had_data := false.B state := handle_pri_req(state) } } } class BoomIOMSHR(id: Int)(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p) with HasL1HellaCacheParameters { val io = IO(new Bundle { val req = Flipped(Decoupled(new BoomDCacheReq)) val resp = Decoupled(new BoomDCacheResp) val mem_access = Decoupled(new TLBundleA(edge.bundle)) val mem_ack = Flipped(Valid(new TLBundleD(edge.bundle))) // We don't need brupdate in here because uncacheable operations are guaranteed non-speculative }) def beatOffset(addr: UInt) = addr.extract(beatOffBits-1, wordOffBits) def wordFromBeat(addr: UInt, dat: UInt) = { val shift = Cat(beatOffset(addr), 0.U((wordOffBits+log2Ceil(wordBytes)).W)) (dat >> shift)(wordBits-1, 0) } val req = Reg(new BoomDCacheReq) val grant_word = Reg(UInt(wordBits.W)) val s_idle :: s_mem_access :: s_mem_ack :: s_resp :: Nil = Enum(4) val state = RegInit(s_idle) io.req.ready := state === s_idle val loadgen = new LoadGen(req.uop.mem_size, req.uop.mem_signed, req.addr, grant_word, false.B, wordBytes) val a_source = id.U val a_address = req.addr val a_size = req.uop.mem_size val a_data = Fill(beatWords, req.data) val get = edge.Get(a_source, a_address, a_size)._2 val put = edge.Put(a_source, a_address, a_size, a_data)._2 val atomics = if (edge.manager.anySupportLogical) { MuxLookup(req.uop.mem_cmd, (0.U).asTypeOf(new TLBundleA(edge.bundle)))(Array( M_XA_SWAP -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.SWAP)._2, M_XA_XOR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.XOR) ._2, M_XA_OR -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.OR) ._2, M_XA_AND -> edge.Logical(a_source, a_address, a_size, a_data, TLAtomics.AND) ._2, M_XA_ADD -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.ADD)._2, M_XA_MIN -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MIN)._2, M_XA_MAX -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAX)._2, M_XA_MINU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MINU)._2, M_XA_MAXU -> edge.Arithmetic(a_source, a_address, a_size, a_data, TLAtomics.MAXU)._2)) } else { // If no managers support atomics, assert fail if processor asks for them assert(state === s_idle \|\| !isAMO(req.uop.mem_cmd)) (0.U).asTypeOf(new TLBundleA(edge.bundle)) } assert(state === s_idle \|\| req.uop.mem_cmd =/= M_XSC) io.mem_access.valid := state === s_mem_access io.mem_access.bits := Mux(isAMO(req.uop.mem_cmd), atomics, Mux(isRead(req.uop.mem_cmd), get, put)) val send_resp = isRead(req.uop.mem_cmd) io.resp.valid := (state === s_resp) && send_resp io.resp.bits.is_hella := req.is_hella io.resp.bits.uop := req.uop io.resp.bits.data := loadgen.data when (io.req.fire) { req := io.req.bits state := s_mem_access } when (io.mem_access.fire) { state := s_mem_ack } when (state === s_mem_ack && io.mem_ack.valid) { state := s_resp when (isRead(req.uop.mem_cmd)) { grant_word := wordFromBeat(req.addr, io.mem_ack.bits.data) } } when (state === s_resp) { when (!send_resp \|\| io.resp.fire) { state := s_idle } } } class LineBufferReadReq(implicit p: Parameters) extends BoomBundle()(p) with HasL1HellaCacheParameters { val id = UInt(log2Ceil(nLBEntries).W) val offset = UInt(log2Ceil(cacheDataBeats).W) def lb_addr = Cat(id, offset) } class LineBufferWriteReq(implicit p: Parameters) extends LineBufferReadReq()(p) { val data = UInt(encRowBits.W) } class LineBufferMetaWriteReq(implicit p: Parameters) extends BoomBundle()(p) { val id = UInt(log2Ceil(nLBEntries).W) val coh = new ClientMetadata val addr = UInt(coreMaxAddrBits.W) } class LineBufferMeta(implicit p: Parameters) extends BoomBundle()(p) with HasL1HellaCacheParameters { val coh = new ClientMetadata val addr = UInt(coreMaxAddrBits.W) } class BoomMSHRFile(implicit edge: TLEdgeOut, p: Parameters) extends BoomModule()(p) with HasL1HellaCacheParameters { val io = IO(new Bundle { val req = Flipped(Vec(memWidth, Decoupled(new BoomDCacheReqInternal))) // Req from s2 of DCache pipe val req_is_probe = Input(Vec(memWidth, Bool())) val resp = Decoupled(new BoomDCacheResp) val secondary_miss = Output(Vec(memWidth, Bool())) val block_hit = Output(Vec(memWidth, Bool())) val brupdate = Input(new BrUpdateInfo) val exception = Input(Bool()) val rob_pnr_idx = Input(UInt(robAddrSz.W)) val rob_head_idx = Input(UInt(robAddrSz.W)) val mem_acquire = Decoupled(new TLBundleA(edge.bundle)) val mem_grant = Flipped(Decoupled(new TLBundleD(edge.bundle))) val mem_finish = Decoupled(new TLBundleE(edge.bundle)) val refill = Decoupled(new L1DataWriteReq) val meta_write = Decoupled(new L1MetaWriteReq) val meta_read = Decoupled(new L1MetaReadReq) val meta_resp = Input(Valid(new L1Metadata)) val replay = Decoupled(new BoomDCacheReqInternal) val prefetch = Decoupled(new BoomDCacheReq) val wb_req = Decoupled(new WritebackReq(edge.bundle)) val prober_state = Input(Valid(UInt(coreMaxAddrBits.W))) val clear_all = Input(Bool()) // Clears all uncommitted MSHRs to prepare for fence val wb_resp = Input(Bool()) val fence_rdy = Output(Bool()) val probe_rdy = Output(Bool()) }) val req_idx = OHToUInt(io.req.map(_.valid)) val req = io.req(req_idx) val req_is_probe = io.req_is_probe(0) for (w <- 0 until memWidth) io.req(w).ready := false.B val prefetcher: DataPrefetcher = if (enablePrefetching) Module(new NLPrefetcher) else Module(new NullPrefetcher) io.prefetch <> prefetcher.io.prefetch val cacheable = edge.manager.supportsAcquireBFast(req.bits.addr, lgCacheBlockBytes.U) // -------------------- // The MSHR SDQ val sdq_val = RegInit(0.U(cfg.nSDQ.W)) val sdq_alloc_id = PriorityEncoder(~sdq_val(cfg.nSDQ-1,0)) val sdq_rdy = !sdq_val.andR val sdq_enq = req.fire && cacheable && isWrite(req.bits.uop.mem_cmd) val sdq = Mem(cfg.nSDQ, UInt(coreDataBits.W)) when (sdq_enq) { sdq(sdq_alloc_id) := req.bits.data } // -------------------- // The LineBuffer Data // Holds refilling lines, prefetched lines val lb = Mem(nLBEntries cacheDataBeats, UInt(encRowBits.W)) val lb_read_arb = Module(new Arbiter(new LineBufferReadReq, cfg.nMSHRs)) val lb_write_arb = Module(new Arbiter(new LineBufferWriteReq, cfg.nMSHRs)) lb_read_arb.io.out.ready := false.B lb_write_arb.io.out.ready := true.B val lb_read_data = WireInit(0.U(encRowBits.W)) when (lb_write_arb.io.out.fire) { lb.write(lb_write_arb.io.out.bits.lb_addr, lb_write_arb.io.out.bits.data) } .otherwise { lb_read_arb.io.out.ready := true.B when (lb_read_arb.io.out.fire) { lb_read_data := lb.read(lb_read_arb.io.out.bits.lb_addr) } } def widthMap[T <: Data](f: Int => T) = VecInit((0 until memWidth).map(f)) val idx_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool()))) val tag_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool()))) val way_matches = Wire(Vec(memWidth, Vec(cfg.nMSHRs, Bool()))) val tag_match = widthMap(w => Mux1H(idx_matches(w), tag_matches(w))) val idx_match = widthMap(w => idx_matches(w).reduce(_\|\|_)) val way_match = widthMap(w => Mux1H(idx_matches(w), way_matches(w))) val wb_tag_list = Wire(Vec(cfg.nMSHRs, UInt(tagBits.W))) val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq , cfg.nMSHRs)) val meta_read_arb = Module(new Arbiter(new L1MetaReadReq , cfg.nMSHRs)) val wb_req_arb = Module(new Arbiter(new WritebackReq(edge.bundle), cfg.nMSHRs)) val replay_arb = Module(new Arbiter(new BoomDCacheReqInternal , cfg.nMSHRs)) val resp_arb = Module(new Arbiter(new BoomDCacheResp , cfg.nMSHRs + nIOMSHRs)) val refill_arb = Module(new Arbiter(new L1DataWriteReq , cfg.nMSHRs)) val commit_vals = Wire(Vec(cfg.nMSHRs, Bool())) val commit_addrs = Wire(Vec(cfg.nMSHRs, UInt(coreMaxAddrBits.W))) val commit_cohs = Wire(Vec(cfg.nMSHRs, new ClientMetadata)) var sec_rdy = false.B io.fence_rdy := true.B io.probe_rdy := true.B io.mem_grant.ready := false.B val mshr_alloc_idx = Wire(UInt()) val pri_rdy = WireInit(false.B) val pri_val = req.valid && sdq_rdy && cacheable && !idx_match(req_idx) val mshrs = (0 until cfg.nMSHRs) map { i => val mshr = Module(new BoomMSHR) mshr.io.id := i.U(log2Ceil(cfg.nMSHRs).W) for (w <- 0 until memWidth) { idx_matches(w)(i) := mshr.io.idx.valid && mshr.io.idx.bits === io.req(w).bits.addr(untagBits-1,blockOffBits) tag_matches(w)(i) := mshr.io.tag.valid && mshr.io.tag.bits === io.req(w).bits.addr >> untagBits way_matches(w)(i) := mshr.io.way.valid && mshr.io.way.bits === io.req(w).bits.way_en } wb_tag_list(i) := mshr.io.wb_req.bits.tag mshr.io.req_pri_val := (i.U === mshr_alloc_idx) && pri_val when (i.U === mshr_alloc_idx) { pri_rdy := mshr.io.req_pri_rdy } mshr.io.req_sec_val := req.valid && sdq_rdy && tag_match(req_idx) && idx_matches(req_idx)(i) && cacheable mshr.io.req := req.bits mshr.io.req_is_probe := req_is_probe mshr.io.req.sdq_id := sdq_alloc_id // Clear because of a FENCE, a request to the same idx as a prefetched line, // a probe to that prefetched line, all mshrs are in use mshr.io.clear_prefetch := ((io.clear_all && !req.valid)\|\| (req.valid && idx_matches(req_idx)(i) && cacheable && !tag_match(req_idx)) \|\| (req_is_probe && idx_matches(req_idx)(i))) mshr.io.brupdate := io.brupdate mshr.io.exception := io.exception mshr.io.rob_pnr_idx := io.rob_pnr_idx mshr.io.rob_head_idx := io.rob_head_idx mshr.io.prober_state := io.prober_state mshr.io.wb_resp := io.wb_resp meta_write_arb.io.in(i) <> mshr.io.meta_write meta_read_arb.io.in(i) <> mshr.io.meta_read mshr.io.meta_resp := io.meta_resp wb_req_arb.io.in(i) <> mshr.io.wb_req replay_arb.io.in(i) <> mshr.io.replay refill_arb.io.in(i) <> mshr.io.refill lb_read_arb.io.in(i) <> mshr.io.lb_read mshr.io.lb_resp := lb_read_data lb_write_arb.io.in(i) <> mshr.io.lb_write commit_vals(i) := mshr.io.commit_val commit_addrs(i) := mshr.io.commit_addr commit_cohs(i) := mshr.io.commit_coh mshr.io.mem_grant.valid := false.B mshr.io.mem_grant.bits := DontCare when (io.mem_grant.bits.source === i.U) { mshr.io.mem_grant <> io.mem_grant } sec_rdy = sec_rdy \|\| (mshr.io.req_sec_rdy && mshr.io.req_sec_val) resp_arb.io.in(i) <> mshr.io.resp when (!mshr.io.req_pri_rdy) { io.fence_rdy := false.B } for (w <- 0 until memWidth) { when (!mshr.io.probe_rdy && idx_matches(w)(i) && io.req_is_probe(w)) { io.probe_rdy := false.B } } mshr } // Try to round-robin the MSHRs val mshr_head = RegInit(0.U(log2Ceil(cfg.nMSHRs).W)) mshr_alloc_idx := RegNext(AgePriorityEncoder(mshrs.map(m=>m.io.req_pri_rdy), mshr_head)) when (pri_rdy && pri_val) { mshr_head := WrapInc(mshr_head, cfg.nMSHRs) } io.meta_write <> meta_write_arb.io.out io.meta_read <> meta_read_arb.io.out io.wb_req <> wb_req_arb.io.out val mmio_alloc_arb = Module(new Arbiter(Bool(), nIOMSHRs)) var mmio_rdy = false.B val mmios = (0 until nIOMSHRs) map { i => val id = cfg.nMSHRs + 1 + i // +1 for wb unit val mshr = Module(new BoomIOMSHR(id)) mmio_alloc_arb.io.in(i).valid := mshr.io.req.ready mmio_alloc_arb.io.in(i).bits := DontCare mshr.io.req.valid := mmio_alloc_arb.io.in(i).ready mshr.io.req.bits := req.bits mmio_rdy = mmio_rdy \|\| mshr.io.req.ready mshr.io.mem_ack.bits := io.mem_grant.bits mshr.io.mem_ack.valid := io.mem_grant.valid && io.mem_grant.bits.source === id.U when (io.mem_grant.bits.source === id.U) { io.mem_grant.ready := true.B } resp_arb.io.in(cfg.nMSHRs + i) <> mshr.io.resp when (!mshr.io.req.ready) { io.fence_rdy := false.B } mshr } mmio_alloc_arb.io.out.ready := req.valid && !cacheable TLArbiter.lowestFromSeq(edge, io.mem_acquire, mshrs.map(_.io.mem_acquire) ++ mmios.map(_.io.mem_access)) TLArbiter.lowestFromSeq(edge, io.mem_finish, mshrs.map(_.io.mem_finish)) val respq = Module(new BranchKillableQueue(new BoomDCacheResp, 4, u => u.uses_ldq, flow = false)) respq.io.brupdate := io.brupdate respq.io.flush := io.exception respq.io.enq <> resp_arb.io.out io.resp <> respq.io.deq for (w <- 0 until memWidth) { io.req(w).ready := (w.U === req_idx) && Mux(!cacheable, mmio_rdy, sdq_rdy && Mux(idx_match(w), tag_match(w) && sec_rdy, pri_rdy)) io.secondary_miss(w) := idx_match(w) && way_match(w) && !tag_match(w) io.block_hit(w) := idx_match(w) && tag_match(w) } io.refill <> refill_arb.io.out val free_sdq = io.replay.fire && isWrite(io.replay.bits.uop.mem_cmd) io.replay <> replay_arb.io.out io.replay.bits.data := sdq(replay_arb.io.out.bits.sdq_id) when (io.replay.valid \|\| sdq_enq) { sdq_val := sdq_val & ~(UIntToOH(replay_arb.io.out.bits.sdq_id) & Fill(cfg.nSDQ, free_sdq)) \| PriorityEncoderOH(~sdq_val(cfg.nSDQ-1,0)) & Fill(cfg.nSDQ, sdq_enq) } prefetcher.io.mshr_avail := RegNext(pri_rdy) prefetcher.io.req_val := RegNext(commit_vals.reduce(_\|\|_)) prefetcher.io.req_addr := RegNext(Mux1H(commit_vals, commit_addrs)) prefetcher.io.req_coh := RegNext(Mux1H(commit_vals, commit_cohs)) } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File AMOALU.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) { val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W)) size := typ val dat_padded = dat.pad(maxSize8) def misaligned: Bool = (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR def mask = { var res = 1.U for (i <- 0 until log2Up(maxSize)) { val upper = Mux(addr(i), res, 0.U) \| Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U) val lower = Mux(addr(i), 0.U, res) res = Cat(upper, lower) } res } protected def genData(i: Int): UInt = if (i >= log2Up(maxSize)) dat_padded else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1)) def data = genData(0) def wordData = genData(2) } class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { private val size = new StoreGen(typ, addr, dat, maxSize).size private def genData(logMinSize: Int): UInt = { var res = dat for (i <- log2Up(maxSize)-1 to logMinSize by -1) { val pos = 8 << i val shifted = Mux(addr(i), res(2pos-1,pos), res(pos-1,0)) val doZero = (i == 0).B && zero val zeroed = Mux(doZero, 0.U, shifted) res = Cat(Mux(size === i.U \|\| doZero, Fill(8maxSize-pos, signed && zeroed(pos-1)), res(8*maxSize-1,pos)), zeroed) } res } def wordData = genData(2) def data = genData(0) } class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module { val minXLen = 32 val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _) val io = IO(new Bundle { val mask = Input(UInt((operandBits / 8).W)) val cmd = Input(UInt(M_SZ.W)) val lhs = Input(UInt(operandBits.W)) val rhs = Input(UInt(operandBits.W)) val out = Output(UInt(operandBits.W)) val out_unmasked = Output(UInt(operandBits.W)) }) val max = io.cmd === M_XA_MAX \|\| io.cmd === M_XA_MAXU val min = io.cmd === M_XA_MIN \|\| io.cmd === M_XA_MINU val add = io.cmd === M_XA_ADD val logic_and = io.cmd === M_XA_OR \|\| io.cmd === M_XA_AND val logic_xor = io.cmd === M_XA_XOR \|\| io.cmd === M_XA_OR val adder_out = { // partition the carry chain to support sub-xLen addition val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_\|_) (io.lhs & mask) + (io.rhs & mask) } val less = { // break up the comparator so the lower parts will be CSE'd def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = { if (n == minXLen) x(n-1, 0) < y(n-1, 0) else x(n-1, n/2) < y(n-1, n/2) \|\| x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2) } def isLess(x: UInt, y: UInt, n: Int): Bool = { val signed = { val mask = M_XA_MIN ^ M_XA_MINU (io.cmd & mask) === (M_XA_MIN & mask) } Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1))) } PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w)))) } val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs) val logic = Mux(logic_and, io.lhs & io.rhs, 0.U) \| Mux(logic_xor, io.lhs ^ io.rhs, 0.U) val out = Mux(add, adder_out, Mux(logic_and \|\| logic_xor, logic, minmax)) val wmask = FillInterleaved(8, io.mask) io.out := wmask & out \| ~wmask & io.lhs io.out_unmasked := out }	module BoomMSHR_9( // @[mshrs.scala:36:7] input clock, // @[mshrs.scala:36:7] input reset, // @[mshrs.scala:36:7] input io_req_pri_val, // @[mshrs.scala:39:14] output io_req_pri_rdy, // @[mshrs.scala:39:14] input io_req_sec_val, // @[mshrs.scala:39:14] output io_req_sec_rdy, // @[mshrs.scala:39:14] input io_clear_prefetch, // @[mshrs.scala:39:14] input [5:0] io_rob_pnr_idx, // @[mshrs.scala:39:14] input [5:0] io_rob_head_idx, // @[mshrs.scala:39:14] input [6:0] io_req_uop_uopc, // @[mshrs.scala:39:14] input [31:0] io_req_uop_inst, // @[mshrs.scala:39:14] input [31:0] io_req_uop_debug_inst, // @[mshrs.scala:39:14] input io_req_uop_is_rvc, // @[mshrs.scala:39:14] input [33:0] io_req_uop_debug_pc, // @[mshrs.scala:39:14] input [2:0] io_req_uop_iq_type, // @[mshrs.scala:39:14] input [9:0] io_req_uop_fu_code, // @[mshrs.scala:39:14] input [3:0] io_req_uop_ctrl_br_type, // @[mshrs.scala:39:14] input [1:0] io_req_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] input [2:0] io_req_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] input [2:0] io_req_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] input [4:0] io_req_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] input io_req_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] input [2:0] io_req_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] input io_req_uop_ctrl_is_load, // @[mshrs.scala:39:14] input io_req_uop_ctrl_is_sta, // @[mshrs.scala:39:14] input io_req_uop_ctrl_is_std, // @[mshrs.scala:39:14] input [1:0] io_req_uop_iw_state, // @[mshrs.scala:39:14] input io_req_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] input io_req_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] input io_req_uop_is_br, // @[mshrs.scala:39:14] input io_req_uop_is_jalr, // @[mshrs.scala:39:14] input io_req_uop_is_jal, // @[mshrs.scala:39:14] input io_req_uop_is_sfb, // @[mshrs.scala:39:14] input [3:0] io_req_uop_br_mask, // @[mshrs.scala:39:14] input [1:0] io_req_uop_br_tag, // @[mshrs.scala:39:14] input [3:0] io_req_uop_ftq_idx, // @[mshrs.scala:39:14] input io_req_uop_edge_inst, // @[mshrs.scala:39:14] input [5:0] io_req_uop_pc_lob, // @[mshrs.scala:39:14] input io_req_uop_taken, // @[mshrs.scala:39:14] input [19:0] io_req_uop_imm_packed, // @[mshrs.scala:39:14] input [11:0] io_req_uop_csr_addr, // @[mshrs.scala:39:14] input [5:0] io_req_uop_rob_idx, // @[mshrs.scala:39:14] input [3:0] io_req_uop_ldq_idx, // @[mshrs.scala:39:14] input [3:0] io_req_uop_stq_idx, // @[mshrs.scala:39:14] input [1:0] io_req_uop_rxq_idx, // @[mshrs.scala:39:14] input [6:0] io_req_uop_pdst, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs1, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs2, // @[mshrs.scala:39:14] input [6:0] io_req_uop_prs3, // @[mshrs.scala:39:14] input [3:0] io_req_uop_ppred, // @[mshrs.scala:39:14] input io_req_uop_prs1_busy, // @[mshrs.scala:39:14] input io_req_uop_prs2_busy, // @[mshrs.scala:39:14] input io_req_uop_prs3_busy, // @[mshrs.scala:39:14] input io_req_uop_ppred_busy, // @[mshrs.scala:39:14] input [6:0] io_req_uop_stale_pdst, // @[mshrs.scala:39:14] input io_req_uop_exception, // @[mshrs.scala:39:14] input [63:0] io_req_uop_exc_cause, // @[mshrs.scala:39:14] input io_req_uop_bypassable, // @[mshrs.scala:39:14] input [4:0] io_req_uop_mem_cmd, // @[mshrs.scala:39:14] input [1:0] io_req_uop_mem_size, // @[mshrs.scala:39:14] input io_req_uop_mem_signed, // @[mshrs.scala:39:14] input io_req_uop_is_fence, // @[mshrs.scala:39:14] input io_req_uop_is_fencei, // @[mshrs.scala:39:14] input io_req_uop_is_amo, // @[mshrs.scala:39:14] input io_req_uop_uses_ldq, // @[mshrs.scala:39:14] input io_req_uop_uses_stq, // @[mshrs.scala:39:14] input io_req_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] input io_req_uop_is_unique, // @[mshrs.scala:39:14] input io_req_uop_flush_on_commit, // @[mshrs.scala:39:14] input io_req_uop_ldst_is_rs1, // @[mshrs.scala:39:14] input [5:0] io_req_uop_ldst, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs1, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs2, // @[mshrs.scala:39:14] input [5:0] io_req_uop_lrs3, // @[mshrs.scala:39:14] input io_req_uop_ldst_val, // @[mshrs.scala:39:14] input [1:0] io_req_uop_dst_rtype, // @[mshrs.scala:39:14] input [1:0] io_req_uop_lrs1_rtype, // @[mshrs.scala:39:14] input [1:0] io_req_uop_lrs2_rtype, // @[mshrs.scala:39:14] input io_req_uop_frs3_en, // @[mshrs.scala:39:14] input io_req_uop_fp_val, // @[mshrs.scala:39:14] input io_req_uop_fp_single, // @[mshrs.scala:39:14] input io_req_uop_xcpt_pf_if, // @[mshrs.scala:39:14] input io_req_uop_xcpt_ae_if, // @[mshrs.scala:39:14] input io_req_uop_xcpt_ma_if, // @[mshrs.scala:39:14] input io_req_uop_bp_debug_if, // @[mshrs.scala:39:14] input io_req_uop_bp_xcpt_if, // @[mshrs.scala:39:14] input [1:0] io_req_uop_debug_fsrc, // @[mshrs.scala:39:14] input [1:0] io_req_uop_debug_tsrc, // @[mshrs.scala:39:14] input [33:0] io_req_addr, // @[mshrs.scala:39:14] input [63:0] io_req_data, // @[mshrs.scala:39:14] input io_req_is_hella, // @[mshrs.scala:39:14] input io_req_tag_match, // @[mshrs.scala:39:14] input [1:0] io_req_old_meta_coh_state, // @[mshrs.scala:39:14] input [21:0] io_req_old_meta_tag, // @[mshrs.scala:39:14] input [1:0] io_req_way_en, // @[mshrs.scala:39:14] input [4:0] io_req_sdq_id, // @[mshrs.scala:39:14] input io_req_is_probe, // @[mshrs.scala:39:14] output io_idx_valid, // @[mshrs.scala:39:14] output [3:0] io_idx_bits, // @[mshrs.scala:39:14] output io_way_valid, // @[mshrs.scala:39:14] output [1:0] io_way_bits, // @[mshrs.scala:39:14] output io_tag_valid, // @[mshrs.scala:39:14] output [23:0] io_tag_bits, // @[mshrs.scala:39:14] input io_mem_acquire_ready, // @[mshrs.scala:39:14] output io_mem_acquire_valid, // @[mshrs.scala:39:14] output [2:0] io_mem_acquire_bits_param, // @[mshrs.scala:39:14] output [31:0] io_mem_acquire_bits_address, // @[mshrs.scala:39:14] output io_mem_grant_ready, // @[mshrs.scala:39:14] input io_mem_grant_valid, // @[mshrs.scala:39:14] input [2:0] io_mem_grant_bits_opcode, // @[mshrs.scala:39:14] input [1:0] io_mem_grant_bits_param, // @[mshrs.scala:39:14] input [3:0] io_mem_grant_bits_size, // @[mshrs.scala:39:14] input [3:0] io_mem_grant_bits_source, // @[mshrs.scala:39:14] input [2:0] io_mem_grant_bits_sink, // @[mshrs.scala:39:14] input io_mem_grant_bits_denied, // @[mshrs.scala:39:14] input [63:0] io_mem_grant_bits_data, // @[mshrs.scala:39:14] input io_mem_grant_bits_corrupt, // @[mshrs.scala:39:14] input io_mem_finish_ready, // @[mshrs.scala:39:14] output io_mem_finish_valid, // @[mshrs.scala:39:14] output [2:0] io_mem_finish_bits_sink, // @[mshrs.scala:39:14] input io_prober_state_valid, // @[mshrs.scala:39:14] input [33:0] io_prober_state_bits, // @[mshrs.scala:39:14] input io_refill_ready, // @[mshrs.scala:39:14] output io_refill_valid, // @[mshrs.scala:39:14] output [1:0] io_refill_bits_way_en, // @[mshrs.scala:39:14] output [9:0] io_refill_bits_addr, // @[mshrs.scala:39:14] output [63:0] io_refill_bits_data, // @[mshrs.scala:39:14] input io_meta_write_ready, // @[mshrs.scala:39:14] output io_meta_write_valid, // @[mshrs.scala:39:14] output [3:0] io_meta_write_bits_idx, // @[mshrs.scala:39:14] output [1:0] io_meta_write_bits_way_en, // @[mshrs.scala:39:14] output [1:0] io_meta_write_bits_data_coh_state, // @[mshrs.scala:39:14] output [21:0] io_meta_write_bits_data_tag, // @[mshrs.scala:39:14] input io_meta_read_ready, // @[mshrs.scala:39:14] output io_meta_read_valid, // @[mshrs.scala:39:14] output [3:0] io_meta_read_bits_idx, // @[mshrs.scala:39:14] output [1:0] io_meta_read_bits_way_en, // @[mshrs.scala:39:14] output [21:0] io_meta_read_bits_tag, // @[mshrs.scala:39:14] input io_meta_resp_valid, // @[mshrs.scala:39:14] input [1:0] io_meta_resp_bits_coh_state, // @[mshrs.scala:39:14] input [21:0] io_meta_resp_bits_tag, // @[mshrs.scala:39:14] input io_wb_req_ready, // @[mshrs.scala:39:14] output io_wb_req_valid, // @[mshrs.scala:39:14] output [21:0] io_wb_req_bits_tag, // @[mshrs.scala:39:14] output [3:0] io_wb_req_bits_idx, // @[mshrs.scala:39:14] output [2:0] io_wb_req_bits_param, // @[mshrs.scala:39:14] output [1:0] io_wb_req_bits_way_en, // @[mshrs.scala:39:14] output io_commit_val, // @[mshrs.scala:39:14] output [33:0] io_commit_addr, // @[mshrs.scala:39:14] output [1:0] io_commit_coh_state, // @[mshrs.scala:39:14] input io_lb_read_ready, // @[mshrs.scala:39:14] output io_lb_read_valid, // @[mshrs.scala:39:14] output [2:0] io_lb_read_bits_offset, // @[mshrs.scala:39:14] input [63:0] io_lb_resp, // @[mshrs.scala:39:14] input io_lb_write_ready, // @[mshrs.scala:39:14] output io_lb_write_valid, // @[mshrs.scala:39:14] output [2:0] io_lb_write_bits_offset, // @[mshrs.scala:39:14] output [63:0] io_lb_write_bits_data, // @[mshrs.scala:39:14] input io_replay_ready, // @[mshrs.scala:39:14] output io_replay_valid, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_uopc, // @[mshrs.scala:39:14] output [31:0] io_replay_bits_uop_inst, // @[mshrs.scala:39:14] output [31:0] io_replay_bits_uop_debug_inst, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_rvc, // @[mshrs.scala:39:14] output [33:0] io_replay_bits_uop_debug_pc, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_iq_type, // @[mshrs.scala:39:14] output [9:0] io_replay_bits_uop_fu_code, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] output [2:0] io_replay_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14] output io_replay_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_iw_state, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] output io_replay_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_br, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_jalr, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_jal, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_sfb, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_br_mask, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_br_tag, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_ftq_idx, // @[mshrs.scala:39:14] output io_replay_bits_uop_edge_inst, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_pc_lob, // @[mshrs.scala:39:14] output io_replay_bits_uop_taken, // @[mshrs.scala:39:14] output [19:0] io_replay_bits_uop_imm_packed, // @[mshrs.scala:39:14] output [11:0] io_replay_bits_uop_csr_addr, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_rob_idx, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_ldq_idx, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_stq_idx, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_rxq_idx, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_pdst, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs1, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs2, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_prs3, // @[mshrs.scala:39:14] output [3:0] io_replay_bits_uop_ppred, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs1_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs2_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_prs3_busy, // @[mshrs.scala:39:14] output io_replay_bits_uop_ppred_busy, // @[mshrs.scala:39:14] output [6:0] io_replay_bits_uop_stale_pdst, // @[mshrs.scala:39:14] output io_replay_bits_uop_exception, // @[mshrs.scala:39:14] output [63:0] io_replay_bits_uop_exc_cause, // @[mshrs.scala:39:14] output io_replay_bits_uop_bypassable, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_uop_mem_cmd, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_mem_size, // @[mshrs.scala:39:14] output io_replay_bits_uop_mem_signed, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_fence, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_fencei, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_amo, // @[mshrs.scala:39:14] output io_replay_bits_uop_uses_ldq, // @[mshrs.scala:39:14] output io_replay_bits_uop_uses_stq, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] output io_replay_bits_uop_is_unique, // @[mshrs.scala:39:14] output io_replay_bits_uop_flush_on_commit, // @[mshrs.scala:39:14] output io_replay_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_ldst, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs1, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs2, // @[mshrs.scala:39:14] output [5:0] io_replay_bits_uop_lrs3, // @[mshrs.scala:39:14] output io_replay_bits_uop_ldst_val, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_dst_rtype, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14] output io_replay_bits_uop_frs3_en, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_val, // @[mshrs.scala:39:14] output io_replay_bits_uop_fp_single, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_bp_debug_if, // @[mshrs.scala:39:14] output io_replay_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_debug_fsrc, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_uop_debug_tsrc, // @[mshrs.scala:39:14] output [33:0] io_replay_bits_addr, // @[mshrs.scala:39:14] output [63:0] io_replay_bits_data, // @[mshrs.scala:39:14] output io_replay_bits_is_hella, // @[mshrs.scala:39:14] output io_replay_bits_tag_match, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_old_meta_coh_state, // @[mshrs.scala:39:14] output [21:0] io_replay_bits_old_meta_tag, // @[mshrs.scala:39:14] output [1:0] io_replay_bits_way_en, // @[mshrs.scala:39:14] output [4:0] io_replay_bits_sdq_id, // @[mshrs.scala:39:14] input io_resp_ready, // @[mshrs.scala:39:14] output io_resp_valid, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_uopc, // @[mshrs.scala:39:14] output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:39:14] output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_rvc, // @[mshrs.scala:39:14] output [33:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_iq_type, // @[mshrs.scala:39:14] output [9:0] io_resp_bits_uop_fu_code, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14] output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14] output io_resp_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_iw_state, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14] output io_resp_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_br, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_jalr, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_jal, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_sfb, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:39:14] output io_resp_bits_uop_edge_inst, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:39:14] output io_resp_bits_uop_taken, // @[mshrs.scala:39:14] output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:39:14] output [11:0] io_resp_bits_uop_csr_addr, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_pdst, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs1, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs2, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_prs3, // @[mshrs.scala:39:14] output [3:0] io_resp_bits_uop_ppred, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:39:14] output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:39:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:39:14] output io_resp_bits_uop_exception, // @[mshrs.scala:39:14] output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:39:14] output io_resp_bits_uop_bypassable, // @[mshrs.scala:39:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:39:14] output io_resp_bits_uop_mem_signed, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_fence, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_fencei, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_amo, // @[mshrs.scala:39:14] output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:39:14] output io_resp_bits_uop_uses_stq, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14] output io_resp_bits_uop_is_unique, // @[mshrs.scala:39:14] output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:39:14] output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:39:14] output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:39:14] output io_resp_bits_uop_ldst_val, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14] output io_resp_bits_uop_frs3_en, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_val, // @[mshrs.scala:39:14] output io_resp_bits_uop_fp_single, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:39:14] output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:39:14] output [1:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:39:14] output [63:0] io_resp_bits_data, // @[mshrs.scala:39:14] output io_resp_bits_is_hella, // @[mshrs.scala:39:14] input io_wb_resp, // @[mshrs.scala:39:14] output io_probe_rdy // @[mshrs.scala:39:14] ); wire rpq_io_deq_ready; // @[mshrs.scala:135:20, :215:30, :222:40, :233:41, :256:45] wire _rpq_io_enq_ready; // @[mshrs.scala:128:19] wire _rpq_io_deq_valid; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_uopc; // @[mshrs.scala:128:19] wire [31:0] _rpq_io_deq_bits_uop_inst; // @[mshrs.scala:128:19] wire [31:0] _rpq_io_deq_bits_uop_debug_inst; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_rvc; // @[mshrs.scala:128:19] wire [33:0] _rpq_io_deq_bits_uop_debug_pc; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_iq_type; // @[mshrs.scala:128:19] wire [9:0] _rpq_io_deq_bits_uop_fu_code; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_ctrl_br_type; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_ctrl_op1_sel; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_ctrl_op2_sel; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_ctrl_imm_sel; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_ctrl_op_fcn; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_fcn_dw; // @[mshrs.scala:128:19] wire [2:0] _rpq_io_deq_bits_uop_ctrl_csr_cmd; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_is_load; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_is_sta; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ctrl_is_std; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_iw_state; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_p1_poisoned; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_iw_p2_poisoned; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_br; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_jalr; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_jal; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_sfb; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_br_mask; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_br_tag; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_ftq_idx; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_edge_inst; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_pc_lob; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_taken; // @[mshrs.scala:128:19] wire [19:0] _rpq_io_deq_bits_uop_imm_packed; // @[mshrs.scala:128:19] wire [11:0] _rpq_io_deq_bits_uop_csr_addr; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_rob_idx; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_ldq_idx; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_stq_idx; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_rxq_idx; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_pdst; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs1; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs2; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_prs3; // @[mshrs.scala:128:19] wire [3:0] _rpq_io_deq_bits_uop_ppred; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs1_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs2_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_prs3_busy; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ppred_busy; // @[mshrs.scala:128:19] wire [6:0] _rpq_io_deq_bits_uop_stale_pdst; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_exception; // @[mshrs.scala:128:19] wire [63:0] _rpq_io_deq_bits_uop_exc_cause; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bypassable; // @[mshrs.scala:128:19] wire [4:0] _rpq_io_deq_bits_uop_mem_cmd; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_mem_size; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_mem_signed; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_fence; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_fencei; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_amo; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_uses_ldq; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_uses_stq; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_sys_pc2epc; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_is_unique; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_flush_on_commit; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ldst_is_rs1; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_ldst; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs1; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs2; // @[mshrs.scala:128:19] wire [5:0] _rpq_io_deq_bits_uop_lrs3; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_ldst_val; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_dst_rtype; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_lrs1_rtype; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_lrs2_rtype; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_frs3_en; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_val; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_fp_single; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_pf_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_ae_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_xcpt_ma_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bp_debug_if; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_uop_bp_xcpt_if; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_debug_fsrc; // @[mshrs.scala:128:19] wire [1:0] _rpq_io_deq_bits_uop_debug_tsrc; // @[mshrs.scala:128:19] wire [33:0] _rpq_io_deq_bits_addr; // @[mshrs.scala:128:19] wire _rpq_io_deq_bits_is_hella; // @[mshrs.scala:128:19] wire _rpq_io_empty; // @[mshrs.scala:128:19] wire io_req_pri_val_0 = io_req_pri_val; // @[mshrs.scala:36:7] wire io_req_sec_val_0 = io_req_sec_val; // @[mshrs.scala:36:7] wire io_clear_prefetch_0 = io_clear_prefetch; // @[mshrs.scala:36:7] wire [5:0] io_rob_pnr_idx_0 = io_rob_pnr_idx; // @[mshrs.scala:36:7] wire [5:0] io_rob_head_idx_0 = io_rob_head_idx; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_uopc_0 = io_req_uop_uopc; // @[mshrs.scala:36:7] wire [31:0] io_req_uop_inst_0 = io_req_uop_inst; // @[mshrs.scala:36:7] wire [31:0] io_req_uop_debug_inst_0 = io_req_uop_debug_inst; // @[mshrs.scala:36:7] wire io_req_uop_is_rvc_0 = io_req_uop_is_rvc; // @[mshrs.scala:36:7] wire [33:0] io_req_uop_debug_pc_0 = io_req_uop_debug_pc; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_iq_type_0 = io_req_uop_iq_type; // @[mshrs.scala:36:7] wire [9:0] io_req_uop_fu_code_0 = io_req_uop_fu_code; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_ctrl_br_type_0 = io_req_uop_ctrl_br_type; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_ctrl_op1_sel_0 = io_req_uop_ctrl_op1_sel; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_ctrl_op2_sel_0 = io_req_uop_ctrl_op2_sel; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_ctrl_imm_sel_0 = io_req_uop_ctrl_imm_sel; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_ctrl_op_fcn_0 = io_req_uop_ctrl_op_fcn; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_fcn_dw_0 = io_req_uop_ctrl_fcn_dw; // @[mshrs.scala:36:7] wire [2:0] io_req_uop_ctrl_csr_cmd_0 = io_req_uop_ctrl_csr_cmd; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_is_load_0 = io_req_uop_ctrl_is_load; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_is_sta_0 = io_req_uop_ctrl_is_sta; // @[mshrs.scala:36:7] wire io_req_uop_ctrl_is_std_0 = io_req_uop_ctrl_is_std; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_iw_state_0 = io_req_uop_iw_state; // @[mshrs.scala:36:7] wire io_req_uop_iw_p1_poisoned_0 = io_req_uop_iw_p1_poisoned; // @[mshrs.scala:36:7] wire io_req_uop_iw_p2_poisoned_0 = io_req_uop_iw_p2_poisoned; // @[mshrs.scala:36:7] wire io_req_uop_is_br_0 = io_req_uop_is_br; // @[mshrs.scala:36:7] wire io_req_uop_is_jalr_0 = io_req_uop_is_jalr; // @[mshrs.scala:36:7] wire io_req_uop_is_jal_0 = io_req_uop_is_jal; // @[mshrs.scala:36:7] wire io_req_uop_is_sfb_0 = io_req_uop_is_sfb; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_br_mask_0 = io_req_uop_br_mask; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_br_tag_0 = io_req_uop_br_tag; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_ftq_idx_0 = io_req_uop_ftq_idx; // @[mshrs.scala:36:7] wire io_req_uop_edge_inst_0 = io_req_uop_edge_inst; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_pc_lob_0 = io_req_uop_pc_lob; // @[mshrs.scala:36:7] wire io_req_uop_taken_0 = io_req_uop_taken; // @[mshrs.scala:36:7] wire [19:0] io_req_uop_imm_packed_0 = io_req_uop_imm_packed; // @[mshrs.scala:36:7] wire [11:0] io_req_uop_csr_addr_0 = io_req_uop_csr_addr; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_rob_idx_0 = io_req_uop_rob_idx; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_ldq_idx_0 = io_req_uop_ldq_idx; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_stq_idx_0 = io_req_uop_stq_idx; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_rxq_idx_0 = io_req_uop_rxq_idx; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_pdst_0 = io_req_uop_pdst; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs1_0 = io_req_uop_prs1; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs2_0 = io_req_uop_prs2; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_prs3_0 = io_req_uop_prs3; // @[mshrs.scala:36:7] wire [3:0] io_req_uop_ppred_0 = io_req_uop_ppred; // @[mshrs.scala:36:7] wire io_req_uop_prs1_busy_0 = io_req_uop_prs1_busy; // @[mshrs.scala:36:7] wire io_req_uop_prs2_busy_0 = io_req_uop_prs2_busy; // @[mshrs.scala:36:7] wire io_req_uop_prs3_busy_0 = io_req_uop_prs3_busy; // @[mshrs.scala:36:7] wire io_req_uop_ppred_busy_0 = io_req_uop_ppred_busy; // @[mshrs.scala:36:7] wire [6:0] io_req_uop_stale_pdst_0 = io_req_uop_stale_pdst; // @[mshrs.scala:36:7] wire io_req_uop_exception_0 = io_req_uop_exception; // @[mshrs.scala:36:7] wire [63:0] io_req_uop_exc_cause_0 = io_req_uop_exc_cause; // @[mshrs.scala:36:7] wire io_req_uop_bypassable_0 = io_req_uop_bypassable; // @[mshrs.scala:36:7] wire [4:0] io_req_uop_mem_cmd_0 = io_req_uop_mem_cmd; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_mem_size_0 = io_req_uop_mem_size; // @[mshrs.scala:36:7] wire io_req_uop_mem_signed_0 = io_req_uop_mem_signed; // @[mshrs.scala:36:7] wire io_req_uop_is_fence_0 = io_req_uop_is_fence; // @[mshrs.scala:36:7] wire io_req_uop_is_fencei_0 = io_req_uop_is_fencei; // @[mshrs.scala:36:7] wire io_req_uop_is_amo_0 = io_req_uop_is_amo; // @[mshrs.scala:36:7] wire io_req_uop_uses_ldq_0 = io_req_uop_uses_ldq; // @[mshrs.scala:36:7] wire io_req_uop_uses_stq_0 = io_req_uop_uses_stq; // @[mshrs.scala:36:7] wire io_req_uop_is_sys_pc2epc_0 = io_req_uop_is_sys_pc2epc; // @[mshrs.scala:36:7] wire io_req_uop_is_unique_0 = io_req_uop_is_unique; // @[mshrs.scala:36:7] wire io_req_uop_flush_on_commit_0 = io_req_uop_flush_on_commit; // @[mshrs.scala:36:7] wire io_req_uop_ldst_is_rs1_0 = io_req_uop_ldst_is_rs1; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_ldst_0 = io_req_uop_ldst; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs1_0 = io_req_uop_lrs1; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs2_0 = io_req_uop_lrs2; // @[mshrs.scala:36:7] wire [5:0] io_req_uop_lrs3_0 = io_req_uop_lrs3; // @[mshrs.scala:36:7] wire io_req_uop_ldst_val_0 = io_req_uop_ldst_val; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_dst_rtype_0 = io_req_uop_dst_rtype; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_lrs1_rtype_0 = io_req_uop_lrs1_rtype; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_lrs2_rtype_0 = io_req_uop_lrs2_rtype; // @[mshrs.scala:36:7] wire io_req_uop_frs3_en_0 = io_req_uop_frs3_en; // @[mshrs.scala:36:7] wire io_req_uop_fp_val_0 = io_req_uop_fp_val; // @[mshrs.scala:36:7] wire io_req_uop_fp_single_0 = io_req_uop_fp_single; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_pf_if_0 = io_req_uop_xcpt_pf_if; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_ae_if_0 = io_req_uop_xcpt_ae_if; // @[mshrs.scala:36:7] wire io_req_uop_xcpt_ma_if_0 = io_req_uop_xcpt_ma_if; // @[mshrs.scala:36:7] wire io_req_uop_bp_debug_if_0 = io_req_uop_bp_debug_if; // @[mshrs.scala:36:7] wire io_req_uop_bp_xcpt_if_0 = io_req_uop_bp_xcpt_if; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_debug_fsrc_0 = io_req_uop_debug_fsrc; // @[mshrs.scala:36:7] wire [1:0] io_req_uop_debug_tsrc_0 = io_req_uop_debug_tsrc; // @[mshrs.scala:36:7] wire [33:0] io_req_addr_0 = io_req_addr; // @[mshrs.scala:36:7] wire [63:0] io_req_data_0 = io_req_data; // @[mshrs.scala:36:7] wire io_req_is_hella_0 = io_req_is_hella; // @[mshrs.scala:36:7] wire io_req_tag_match_0 = io_req_tag_match; // @[mshrs.scala:36:7] wire [1:0] io_req_old_meta_coh_state_0 = io_req_old_meta_coh_state; // @[mshrs.scala:36:7] wire [21:0] io_req_old_meta_tag_0 = io_req_old_meta_tag; // @[mshrs.scala:36:7] wire [1:0] io_req_way_en_0 = io_req_way_en; // @[mshrs.scala:36:7] wire [4:0] io_req_sdq_id_0 = io_req_sdq_id; // @[mshrs.scala:36:7] wire io_req_is_probe_0 = io_req_is_probe; // @[mshrs.scala:36:7] wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[mshrs.scala:36:7] wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[mshrs.scala:36:7] wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[mshrs.scala:36:7] wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[mshrs.scala:36:7] wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[mshrs.scala:36:7] wire [3:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[mshrs.scala:36:7] wire [2:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[mshrs.scala:36:7] wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[mshrs.scala:36:7] wire [63:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[mshrs.scala:36:7] wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[mshrs.scala:36:7] wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[mshrs.scala:36:7] wire io_prober_state_valid_0 = io_prober_state_valid; // @[mshrs.scala:36:7] wire [33:0] io_prober_state_bits_0 = io_prober_state_bits; // @[mshrs.scala:36:7] wire io_refill_ready_0 = io_refill_ready; // @[mshrs.scala:36:7] wire io_meta_write_ready_0 = io_meta_write_ready; // @[mshrs.scala:36:7] wire io_meta_read_ready_0 = io_meta_read_ready; // @[mshrs.scala:36:7] wire io_meta_resp_valid_0 = io_meta_resp_valid; // @[mshrs.scala:36:7] wire [1:0] io_meta_resp_bits_coh_state_0 = io_meta_resp_bits_coh_state; // @[mshrs.scala:36:7] wire [21:0] io_meta_resp_bits_tag_0 = io_meta_resp_bits_tag; // @[mshrs.scala:36:7] wire io_wb_req_ready_0 = io_wb_req_ready; // @[mshrs.scala:36:7] wire io_lb_read_ready_0 = io_lb_read_ready; // @[mshrs.scala:36:7] wire [63:0] io_lb_resp_0 = io_lb_resp; // @[mshrs.scala:36:7] wire io_lb_write_ready_0 = io_lb_write_ready; // @[mshrs.scala:36:7] wire io_replay_ready_0 = io_replay_ready; // @[mshrs.scala:36:7] wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:36:7] wire io_wb_resp_0 = io_wb_resp; // @[mshrs.scala:36:7] wire _state_T = reset; // @[mshrs.scala:194:11] wire _state_T_26 = reset; // @[mshrs.scala:201:15] wire _state_T_34 = reset; // @[mshrs.scala:194:11] wire _state_T_60 = reset; // @[mshrs.scala:201:15] wire [2:0] io_id = 3'h1; // @[mshrs.scala:36:7] wire [2:0] io_lb_read_bits_id = 3'h1; // @[mshrs.scala:36:7] wire [2:0] io_lb_write_bits_id = 3'h1; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[mshrs.scala:36:7] wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[mshrs.scala:36:7] wire [3:0] _r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _grow_param_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _coh_on_grant_T_4 = 4'h0; // @[Metadata.scala:87:10] wire [3:0] _r1_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r2_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _state_req_needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _state_r_T_16 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _r_T_80 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _r_T_139 = 4'h0; // @[Metadata.scala:68:10] wire [3:0] _state_req_needs_wb_r_T_74 = 4'h0; // @[Metadata.scala:125:10] wire [3:0] _state_r_T_75 = 4'h0; // @[Metadata.scala:68:10] wire [6:0] io_brupdate_b2_uop_uopc = 7'h0; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_pdst = 7'h0; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs1 = 7'h0; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs2 = 7'h0; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_prs3 = 7'h0; // @[mshrs.scala:36:7] wire [6:0] io_brupdate_b2_uop_stale_pdst = 7'h0; // @[mshrs.scala:36:7] wire [6:0] _data_word_T = 7'h0; // @[mshrs.scala:264:32] wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[mshrs.scala:36:7] wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_fcn_dw = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_is_load = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_is_sta = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ctrl_is_std = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_p1_poisoned = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_iw_p2_poisoned = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_br = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_jalr = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_jal = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_taken = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_exception = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bypassable = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_fence = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_amo = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_is_unique = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_ldst_val = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_val = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_fp_single = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_valid = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_mispredict = 1'h0; // @[mshrs.scala:36:7] wire io_brupdate_b2_taken = 1'h0; // @[mshrs.scala:36:7] wire io_exception = 1'h0; // @[mshrs.scala:36:7] wire io_mem_acquire_bits_corrupt = 1'h0; // @[mshrs.scala:36:7] wire _r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _grow_param_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _grow_param_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r1_T_38 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_26 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_29 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_32 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_35 = 1'h0; // @[Misc.scala:35:9] wire _r2_T_38 = 1'h0; // @[Misc.scala:35:9] wire _state_req_needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _state_r_T_26 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_29 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_32 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_35 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_38 = 1'h0; // @[Misc.scala:35:9] wire _io_mem_acquire_bits_legal_T = 1'h0; // @[Parameters.scala:684:29] wire _io_mem_acquire_bits_legal_T_6 = 1'h0; // @[Parameters.scala:684:54] wire _io_mem_acquire_bits_legal_T_15 = 1'h0; // @[Parameters.scala:686:26] wire io_mem_acquire_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17] wire io_mem_acquire_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _io_mem_acquire_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _io_mem_acquire_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31] wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31] wire _needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24] wire _needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9] wire _needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9] wire _r_T_90 = 1'h0; // @[Misc.scala:35:9] wire _r_T_93 = 1'h0; // @[Misc.scala:35:9] wire _r_T_96 = 1'h0; // @[Misc.scala:35:9] wire _r_T_99 = 1'h0; // @[Misc.scala:35:9] wire _r_T_102 = 1'h0; // @[Misc.scala:35:9] wire _r_T_149 = 1'h0; // @[Misc.scala:35:9] wire _r_T_152 = 1'h0; // @[Misc.scala:35:9] wire _r_T_155 = 1'h0; // @[Misc.scala:35:9] wire _r_T_158 = 1'h0; // @[Misc.scala:35:9] wire _r_T_161 = 1'h0; // @[Misc.scala:35:9] wire _state_req_needs_wb_r_T_66 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_68 = 1'h0; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T_84 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_88 = 1'h0; // @[Misc.scala:38:9] wire _state_req_needs_wb_r_T_92 = 1'h0; // @[Misc.scala:38:9] wire _state_r_T_85 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_88 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_91 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_94 = 1'h0; // @[Misc.scala:35:9] wire _state_r_T_97 = 1'h0; // @[Misc.scala:35:9] wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[mshrs.scala:36:7] wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_iq_type = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd = 3'h0; // @[mshrs.scala:36:7] wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[mshrs.scala:36:7] wire [9:0] io_brupdate_b2_uop_fu_code = 10'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_iw_state = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[mshrs.scala:36:7] wire [1:0] io_brupdate_b2_target_offset = 2'h0; // @[mshrs.scala:36:7] wire [1:0] new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _grow_param_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _grow_param_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _coh_on_grant_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r1_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r2_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_req_needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_r_T_1 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_3 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_5 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_15 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] state_new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _r_T_65 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_67 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_69 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_79 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_124 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_126 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_128 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _r_T_138 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] _state_req_needs_wb_r_T_86 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_90 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_94 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_98 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_req_needs_wb_r_T_102 = 2'h0; // @[Misc.scala:38:63] wire [1:0] _state_r_T_60 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_62 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_64 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] _state_r_T_74 = 2'h0; // @[Metadata.scala:26:15] wire [1:0] state_new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn = 5'h0; // @[mshrs.scala:36:7] wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_rob_idx = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[mshrs.scala:36:7] wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[mshrs.scala:36:7] wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[mshrs.scala:36:7] wire [11:0] io_brupdate_b2_uop_csr_addr = 12'h0; // @[mshrs.scala:36:7] wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[mshrs.scala:36:7] wire [63:0] io_mem_acquire_bits_data = 64'h0; // @[mshrs.scala:36:7] wire [63:0] io_mem_acquire_bits_a_data = 64'h0; // @[Edges.scala:346:17] wire [2:0] io_mem_acquire_bits_opcode = 3'h6; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_a_opcode = 3'h6; // @[Edges.scala:346:17] wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34] wire [3:0] io_mem_acquire_bits_size = 4'h6; // @[mshrs.scala:36:7] wire [3:0] _r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _grow_param_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r1_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r2_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _state_req_needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _state_r_T_10 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] io_mem_acquire_bits_a_size = 4'h6; // @[Edges.scala:346:17] wire [3:0] _needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _r_T_74 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _r_T_133 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] _state_req_needs_wb_r_T_76 = 4'h6; // @[Metadata.scala:127:10] wire [3:0] _state_r_T_69 = 4'h6; // @[Metadata.scala:64:10] wire [3:0] io_mem_acquire_bits_source = 4'h1; // @[mshrs.scala:36:7] wire [3:0] io_wb_req_bits_source = 4'h1; // @[mshrs.scala:36:7] wire [3:0] _r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _grow_param_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _coh_on_grant_T_2 = 4'h1; // @[Metadata.scala:86:10] wire [3:0] _r1_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r2_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _state_req_needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _state_r_T_6 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] io_mem_acquire_bits_a_source = 4'h1; // @[Edges.scala:346:17] wire [3:0] _needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _r_T_70 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _r_T_129 = 4'h1; // @[Metadata.scala:62:10] wire [3:0] _state_req_needs_wb_r_T_73 = 4'h1; // @[Metadata.scala:124:10] wire [3:0] _state_r_T_65 = 4'h1; // @[Metadata.scala:62:10] wire [7:0] io_mem_acquire_bits_mask = 8'hFF; // @[mshrs.scala:36:7] wire [7:0] io_mem_acquire_bits_a_mask = 8'hFF; // @[Edges.scala:346:17] wire [7:0] _io_mem_acquire_bits_a_mask_T = 8'hFF; // @[Misc.scala:222:10] wire io_refill_bits_wmask = 1'h1; // @[mshrs.scala:36:7] wire io_wb_req_bits_voluntary = 1'h1; // @[mshrs.scala:36:7] wire _r_T = 1'h1; // @[Metadata.scala:140:24] wire _state_req_needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _io_mem_acquire_bits_legal_T_7 = 1'h1; // @[Parameters.scala:91:44] wire _io_mem_acquire_bits_legal_T_8 = 1'h1; // @[Parameters.scala:684:29] wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire io_mem_acquire_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26] wire io_mem_acquire_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire io_mem_acquire_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire _needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24] wire _io_refill_bits_wmask_T = 1'h1; // @[mshrs.scala:342:30] wire _state_req_needs_wb_r_T_64 = 1'h1; // @[Metadata.scala:140:24] wire [21:0] io_meta_write_bits_tag = 22'h0; // @[mshrs.scala:36:7] wire [3:0] _grow_param_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _coh_on_grant_T_8 = 4'hC; // @[Metadata.scala:89:10] wire [3:0] _r1_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r2_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _state_r_T_24 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_88 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _r_T_147 = 4'hC; // @[Metadata.scala:72:10] wire [3:0] _state_r_T_83 = 4'hC; // @[Metadata.scala:72:10] wire [1:0] _grow_param_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _grow_param_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _coh_on_grant_T_7 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r1_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r2_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _dirties_T = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_11 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_13 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_21 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_23 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] io_mem_acquire_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] io_mem_acquire_bits_a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _r_T_75 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_77 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_85 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_87 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_134 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_136 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_144 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _r_T_146 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_70 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_72 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_80 = 2'h3; // @[Metadata.scala:24:15] wire [1:0] _state_r_T_82 = 2'h3; // @[Metadata.scala:24:15] wire [3:0] _grow_param_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r1_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r2_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _state_r_T_22 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_86 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_145 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _state_r_T_81 = 4'hD; // @[Metadata.scala:71:10] wire [3:0] _r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _grow_param_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _coh_on_grant_T_6 = 4'h4; // @[Metadata.scala:88:10] wire [3:0] _r1_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r2_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _state_req_needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _state_r_T_20 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _r_T_84 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r_T_143 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _state_req_needs_wb_r_T_78 = 4'h4; // @[Metadata.scala:129:10] wire [3:0] _state_r_T_79 = 4'h4; // @[Metadata.scala:70:10] wire [3:0] _r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _grow_param_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r1_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r2_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _state_req_needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _state_r_T_18 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _r_T_82 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _r_T_141 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _state_req_needs_wb_r_T_77 = 4'h5; // @[Metadata.scala:128:10] wire [3:0] _state_r_T_77 = 4'h5; // @[Metadata.scala:69:10] wire [3:0] _grow_param_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r1_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r2_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _state_r_T_14 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_78 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _r_T_137 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _state_r_T_73 = 4'hE; // @[Metadata.scala:66:10] wire [3:0] _grow_param_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r1_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r2_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _state_r_T_12 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] io_mem_acquire_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] io_mem_acquire_bits_a_mask_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] _r_T_76 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_135 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _state_r_T_71 = 4'hF; // @[Metadata.scala:65:10] wire [3:0] _r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _grow_param_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r1_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r2_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _state_req_needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _state_r_T_8 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _r_T_72 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r_T_131 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _state_req_needs_wb_r_T_75 = 4'h7; // @[Metadata.scala:126:10] wire [3:0] _state_r_T_67 = 4'h7; // @[Metadata.scala:63:10] wire [3:0] _r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _grow_param_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r1_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r2_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _state_req_needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _state_r_T_4 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _r_T_68 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_127 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _state_req_needs_wb_r_T_72 = 4'h2; // @[Metadata.scala:123:10] wire [3:0] _state_r_T_63 = 4'h2; // @[Metadata.scala:61:10] wire [3:0] _r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _grow_param_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r1_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r2_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _state_req_needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _state_r_T_2 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _r_T_66 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_125 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _state_req_needs_wb_r_T_71 = 4'h3; // @[Metadata.scala:122:10] wire [3:0] _state_r_T_61 = 4'h3; // @[Metadata.scala:60:10] wire [3:0] _r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _state_req_needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _state_req_needs_wb_r_T_82 = 4'h8; // @[Metadata.scala:133:10] wire [3:0] _r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _state_req_needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _state_req_needs_wb_r_T_81 = 4'h9; // @[Metadata.scala:132:10] wire [3:0] _r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _state_req_needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _state_req_needs_wb_r_T_80 = 4'hA; // @[Metadata.scala:131:10] wire [3:0] _r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _state_req_needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10] wire [3:0] _state_req_needs_wb_r_T_79 = 4'hB; // @[Metadata.scala:130:10] wire [1:0] _r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire [1:0] _needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_65 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_67 = 2'h2; // @[Metadata.scala:140:24] wire [1:0] _state_req_needs_wb_r_T_69 = 2'h2; // @[Metadata.scala:140:24] wire [2:0] io_mem_acquire_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81] wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27] wire [1:0] _grow_param_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _grow_param_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _coh_on_grant_T_5 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r1_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r2_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_7 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_9 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_17 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_19 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_71 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_73 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_81 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_83 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_130 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_132 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_140 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _r_T_142 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_66 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_68 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_76 = 2'h1; // @[Metadata.scala:25:15] wire [1:0] _state_r_T_78 = 2'h1; // @[Metadata.scala:25:15] wire _io_req_sec_rdy_T; // @[mshrs.scala:159:37] wire _io_idx_valid_T; // @[mshrs.scala:149:25] wire [3:0] req_idx; // @[mshrs.scala:110:25] wire _io_way_valid_T_3; // @[mshrs.scala:151:19] wire _io_tag_valid_T; // @[mshrs.scala:150:25] wire [23:0] req_tag; // @[mshrs.scala:111:26] wire [2:0] io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] wire [31:0] io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] wire [2:0] grantack_bits_e_sink = io_mem_grant_bits_sink_0; // @[Edges.scala:451:17] wire [63:0] io_lb_write_bits_data_0 = io_mem_grant_bits_data_0; // @[mshrs.scala:36:7] wire [2:0] shrink_param; // @[Misc.scala:38:36] wire [1:0] coh_on_grant_state; // @[Metadata.scala:160:20] wire [63:0] io_refill_bits_data_0 = io_lb_resp_0; // @[mshrs.scala:36:7] wire [63:0] data_word = io_lb_resp_0; // @[mshrs.scala:36:7, :264:26] wire [33:0] _io_replay_bits_addr_T_1; // @[mshrs.scala:353:31] wire [63:0] _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16] wire _io_probe_rdy_T_11; // @[mshrs.scala:148:42] wire io_idx_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_idx_bits_0; // @[mshrs.scala:36:7] wire io_way_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_way_bits_0; // @[mshrs.scala:36:7] wire io_tag_valid_0; // @[mshrs.scala:36:7] wire [23:0] io_tag_bits_0; // @[mshrs.scala:36:7] wire [2:0] io_mem_acquire_bits_param_0; // @[mshrs.scala:36:7] wire [31:0] io_mem_acquire_bits_address_0; // @[mshrs.scala:36:7] wire io_mem_acquire_valid_0; // @[mshrs.scala:36:7] wire io_mem_grant_ready_0; // @[mshrs.scala:36:7] wire [2:0] io_mem_finish_bits_sink_0; // @[mshrs.scala:36:7] wire io_mem_finish_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_refill_bits_way_en_0; // @[mshrs.scala:36:7] wire [9:0] io_refill_bits_addr_0; // @[mshrs.scala:36:7] wire io_refill_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_meta_write_bits_data_coh_state_0; // @[mshrs.scala:36:7] wire [21:0] io_meta_write_bits_data_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_meta_write_bits_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_meta_write_bits_way_en_0; // @[mshrs.scala:36:7] wire io_meta_write_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_meta_read_bits_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_meta_read_bits_way_en_0; // @[mshrs.scala:36:7] wire [21:0] io_meta_read_bits_tag_0; // @[mshrs.scala:36:7] wire io_meta_read_valid_0; // @[mshrs.scala:36:7] wire [21:0] io_wb_req_bits_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_wb_req_bits_idx_0; // @[mshrs.scala:36:7] wire [2:0] io_wb_req_bits_param_0; // @[mshrs.scala:36:7] wire [1:0] io_wb_req_bits_way_en_0; // @[mshrs.scala:36:7] wire io_wb_req_valid_0; // @[mshrs.scala:36:7] wire [1:0] io_commit_coh_state_0; // @[mshrs.scala:36:7] wire [2:0] io_lb_read_bits_offset_0; // @[mshrs.scala:36:7] wire io_lb_read_valid_0; // @[mshrs.scala:36:7] wire [2:0] io_lb_write_bits_offset_0; // @[mshrs.scala:36:7] wire io_lb_write_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_uopc_0; // @[mshrs.scala:36:7] wire [31:0] io_replay_bits_uop_inst_0; // @[mshrs.scala:36:7] wire [31:0] io_replay_bits_uop_debug_inst_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_rvc_0; // @[mshrs.scala:36:7] wire [33:0] io_replay_bits_uop_debug_pc_0; // @[mshrs.scala:36:7] wire [2:0] io_replay_bits_uop_iq_type_0; // @[mshrs.scala:36:7] wire [9:0] io_replay_bits_uop_fu_code_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_iw_state_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_br_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_jalr_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_jal_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_sfb_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_br_mask_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_br_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_edge_inst_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_pc_lob_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_taken_0; // @[mshrs.scala:36:7] wire [19:0] io_replay_bits_uop_imm_packed_0; // @[mshrs.scala:36:7] wire [11:0] io_replay_bits_uop_csr_addr_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_rob_idx_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_stq_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_pdst_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs1_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs2_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_prs3_0; // @[mshrs.scala:36:7] wire [3:0] io_replay_bits_uop_ppred_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7] wire [6:0] io_replay_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_exception_0; // @[mshrs.scala:36:7] wire [63:0] io_replay_bits_uop_exc_cause_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bypassable_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_mem_size_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_mem_signed_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_fence_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_fencei_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_amo_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_uses_stq_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_is_unique_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_ldst_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs1_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs2_0; // @[mshrs.scala:36:7] wire [5:0] io_replay_bits_uop_lrs3_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_ldst_val_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_frs3_en_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_val_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_fp_single_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7] wire io_replay_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_old_meta_coh_state_0; // @[mshrs.scala:36:7] wire [21:0] io_replay_bits_old_meta_tag_0; // @[mshrs.scala:36:7] wire [33:0] io_replay_bits_addr_0; // @[mshrs.scala:36:7] wire [63:0] io_replay_bits_data_0; // @[mshrs.scala:36:7] wire io_replay_bits_is_hella_0; // @[mshrs.scala:36:7] wire io_replay_bits_tag_match_0; // @[mshrs.scala:36:7] wire [1:0] io_replay_bits_way_en_0; // @[mshrs.scala:36:7] wire [4:0] io_replay_bits_sdq_id_0; // @[mshrs.scala:36:7] wire io_replay_valid_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_uopc_0; // @[mshrs.scala:36:7] wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:36:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:36:7] wire [33:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:36:7] wire [2:0] io_resp_bits_uop_iq_type_0; // @[mshrs.scala:36:7] wire [9:0] io_resp_bits_uop_fu_code_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_iw_state_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_br_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_jalr_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_jal_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_taken_0; // @[mshrs.scala:36:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:36:7] wire [11:0] io_resp_bits_uop_csr_addr_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:36:7] wire [3:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7] wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_exception_0; // @[mshrs.scala:36:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bypassable_0; // @[mshrs.scala:36:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:36:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_ldst_val_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_fp_single_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7] wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7] wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:36:7] wire io_resp_bits_is_hella_0; // @[mshrs.scala:36:7] wire io_resp_valid_0; // @[mshrs.scala:36:7] wire io_req_pri_rdy_0; // @[mshrs.scala:36:7] wire io_req_sec_rdy_0; // @[mshrs.scala:36:7] wire io_commit_val_0; // @[mshrs.scala:36:7] wire [33:0] io_commit_addr_0; // @[mshrs.scala:36:7] wire io_probe_rdy_0; // @[mshrs.scala:36:7] reg [4:0] state; // @[mshrs.scala:107:22] reg [6:0] req_uop_uopc; // @[mshrs.scala:109:20] reg [31:0] req_uop_inst; // @[mshrs.scala:109:20] reg [31:0] req_uop_debug_inst; // @[mshrs.scala:109:20] reg req_uop_is_rvc; // @[mshrs.scala:109:20] reg [33:0] req_uop_debug_pc; // @[mshrs.scala:109:20] reg [2:0] req_uop_iq_type; // @[mshrs.scala:109:20] reg [9:0] req_uop_fu_code; // @[mshrs.scala:109:20] reg [3:0] req_uop_ctrl_br_type; // @[mshrs.scala:109:20] reg [1:0] req_uop_ctrl_op1_sel; // @[mshrs.scala:109:20] reg [2:0] req_uop_ctrl_op2_sel; // @[mshrs.scala:109:20] reg [2:0] req_uop_ctrl_imm_sel; // @[mshrs.scala:109:20] reg [4:0] req_uop_ctrl_op_fcn; // @[mshrs.scala:109:20] reg req_uop_ctrl_fcn_dw; // @[mshrs.scala:109:20] reg [2:0] req_uop_ctrl_csr_cmd; // @[mshrs.scala:109:20] reg req_uop_ctrl_is_load; // @[mshrs.scala:109:20] reg req_uop_ctrl_is_sta; // @[mshrs.scala:109:20] reg req_uop_ctrl_is_std; // @[mshrs.scala:109:20] reg [1:0] req_uop_iw_state; // @[mshrs.scala:109:20] reg req_uop_iw_p1_poisoned; // @[mshrs.scala:109:20] reg req_uop_iw_p2_poisoned; // @[mshrs.scala:109:20] reg req_uop_is_br; // @[mshrs.scala:109:20] reg req_uop_is_jalr; // @[mshrs.scala:109:20] reg req_uop_is_jal; // @[mshrs.scala:109:20] reg req_uop_is_sfb; // @[mshrs.scala:109:20] reg [3:0] req_uop_br_mask; // @[mshrs.scala:109:20] reg [1:0] req_uop_br_tag; // @[mshrs.scala:109:20] reg [3:0] req_uop_ftq_idx; // @[mshrs.scala:109:20] reg req_uop_edge_inst; // @[mshrs.scala:109:20] reg [5:0] req_uop_pc_lob; // @[mshrs.scala:109:20] reg req_uop_taken; // @[mshrs.scala:109:20] reg [19:0] req_uop_imm_packed; // @[mshrs.scala:109:20] reg [11:0] req_uop_csr_addr; // @[mshrs.scala:109:20] reg [5:0] req_uop_rob_idx; // @[mshrs.scala:109:20] reg [3:0] req_uop_ldq_idx; // @[mshrs.scala:109:20] reg [3:0] req_uop_stq_idx; // @[mshrs.scala:109:20] reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:109:20] reg [6:0] req_uop_pdst; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs1; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs2; // @[mshrs.scala:109:20] reg [6:0] req_uop_prs3; // @[mshrs.scala:109:20] reg [3:0] req_uop_ppred; // @[mshrs.scala:109:20] reg req_uop_prs1_busy; // @[mshrs.scala:109:20] reg req_uop_prs2_busy; // @[mshrs.scala:109:20] reg req_uop_prs3_busy; // @[mshrs.scala:109:20] reg req_uop_ppred_busy; // @[mshrs.scala:109:20] reg [6:0] req_uop_stale_pdst; // @[mshrs.scala:109:20] reg req_uop_exception; // @[mshrs.scala:109:20] reg [63:0] req_uop_exc_cause; // @[mshrs.scala:109:20] reg req_uop_bypassable; // @[mshrs.scala:109:20] reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:109:20] reg [1:0] req_uop_mem_size; // @[mshrs.scala:109:20] reg req_uop_mem_signed; // @[mshrs.scala:109:20] reg req_uop_is_fence; // @[mshrs.scala:109:20] reg req_uop_is_fencei; // @[mshrs.scala:109:20] reg req_uop_is_amo; // @[mshrs.scala:109:20] reg req_uop_uses_ldq; // @[mshrs.scala:109:20] reg req_uop_uses_stq; // @[mshrs.scala:109:20] reg req_uop_is_sys_pc2epc; // @[mshrs.scala:109:20] reg req_uop_is_unique; // @[mshrs.scala:109:20] reg req_uop_flush_on_commit; // @[mshrs.scala:109:20] reg req_uop_ldst_is_rs1; // @[mshrs.scala:109:20] reg [5:0] req_uop_ldst; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs1; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs2; // @[mshrs.scala:109:20] reg [5:0] req_uop_lrs3; // @[mshrs.scala:109:20] reg req_uop_ldst_val; // @[mshrs.scala:109:20] reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:109:20] reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:109:20] reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:109:20] reg req_uop_frs3_en; // @[mshrs.scala:109:20] reg req_uop_fp_val; // @[mshrs.scala:109:20] reg req_uop_fp_single; // @[mshrs.scala:109:20] reg req_uop_xcpt_pf_if; // @[mshrs.scala:109:20] reg req_uop_xcpt_ae_if; // @[mshrs.scala:109:20] reg req_uop_xcpt_ma_if; // @[mshrs.scala:109:20] reg req_uop_bp_debug_if; // @[mshrs.scala:109:20] reg req_uop_bp_xcpt_if; // @[mshrs.scala:109:20] reg [1:0] req_uop_debug_fsrc; // @[mshrs.scala:109:20] reg [1:0] req_uop_debug_tsrc; // @[mshrs.scala:109:20] reg [33:0] req_addr; // @[mshrs.scala:109:20] assign io_commit_addr_0 = req_addr; // @[mshrs.scala:36:7, :109:20] reg [63:0] req_data; // @[mshrs.scala:109:20] reg req_is_hella; // @[mshrs.scala:109:20] reg req_tag_match; // @[mshrs.scala:109:20] reg [1:0] req_old_meta_coh_state; // @[mshrs.scala:109:20] reg [21:0] req_old_meta_tag; // @[mshrs.scala:109:20] assign io_wb_req_bits_tag_0 = req_old_meta_tag; // @[mshrs.scala:36:7, :109:20] reg [1:0] req_way_en; // @[mshrs.scala:109:20] assign io_way_bits_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_refill_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_meta_write_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_meta_read_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_wb_req_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] assign io_replay_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20] reg [4:0] req_sdq_id; // @[mshrs.scala:109:20] assign req_idx = req_addr[9:6]; // @[mshrs.scala:109:20, :110:25] assign io_idx_bits_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_meta_write_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_meta_read_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign io_wb_req_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25] assign req_tag = req_addr[33:10]; // @[mshrs.scala:109:20, :111:26] assign io_tag_bits_0 = req_tag; // @[mshrs.scala:36:7, :111:26] wire [27:0] _req_block_addr_T = req_addr[33:6]; // @[mshrs.scala:109:20, :112:34] wire [33:0] req_block_addr = {_req_block_addr_T, 6'h0}; // @[mshrs.scala:112:{34,51}] reg req_needs_wb; // @[mshrs.scala:113:29] reg [1:0] new_coh_state; // @[mshrs.scala:115:24] wire [3:0] _r_T_6 = {2'h2, req_old_meta_coh_state}; // @[Metadata.scala:120:19] wire _r_T_19 = _r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _r_T_21 = _r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _r_T_23 = _r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _r_T_25 = _r_T_23 ? 3'h2 : _r_T_21; // @[Misc.scala:38:36, :56:20] wire _r_T_27 = _r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _r_T_29 = _r_T_27 ? 3'h1 : _r_T_25; // @[Misc.scala:38:36, :56:20] wire _r_T_31 = _r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _r_T_32 = _r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_33 = _r_T_31 ? 3'h1 : _r_T_29; // @[Misc.scala:38:36, :56:20] wire _r_T_35 = _r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _r_T_36 = ~_r_T_35 & _r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_37 = _r_T_35 ? 3'h5 : _r_T_33; // @[Misc.scala:38:36, :56:20] wire _r_T_39 = _r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _r_T_40 = ~_r_T_39 & _r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_41 = _r_T_39 ? 3'h4 : _r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_42 = {1'h0, _r_T_39}; // @[Misc.scala:38:63, :56:20] wire _r_T_43 = _r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _r_T_44 = ~_r_T_43 & _r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_45 = _r_T_43 ? 3'h0 : _r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_46 = _r_T_43 ? 2'h1 : _r_T_42; // @[Misc.scala:38:63, :56:20] wire _r_T_47 = _r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _r_T_48 = _r_T_47 \| _r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_49 = _r_T_47 ? 3'h0 : _r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_50 = _r_T_47 ? 2'h1 : _r_T_46; // @[Misc.scala:38:63, :56:20] wire _r_T_51 = _r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _r_T_52 = ~_r_T_51 & _r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_53 = _r_T_51 ? 3'h5 : _r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_54 = _r_T_51 ? 2'h0 : _r_T_50; // @[Misc.scala:38:63, :56:20] wire _r_T_55 = _r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _r_T_56 = ~_r_T_55 & _r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_57 = _r_T_55 ? 3'h4 : _r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_58 = _r_T_55 ? 2'h1 : _r_T_54; // @[Misc.scala:38:63, :56:20] wire _r_T_59 = _r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _r_T_60 = ~_r_T_59 & _r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _r_T_61 = _r_T_59 ? 3'h3 : _r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _r_T_62 = _r_T_59 ? 2'h2 : _r_T_58; // @[Misc.scala:38:63, :56:20] wire _r_T_63 = _r_T_6 == 4'h3; // @[Misc.scala:56:20] wire r_1 = _r_T_63 \| _r_T_60; // @[Misc.scala:38:9, :56:20] assign shrink_param = _r_T_63 ? 3'h3 : _r_T_61; // @[Misc.scala:38:36, :56:20] assign io_wb_req_bits_param_0 = shrink_param; // @[Misc.scala:38:36] wire [1:0] r_3 = _r_T_63 ? 2'h2 : _r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] coh_on_clear_state = r_3; // @[Misc.scala:38:63] wire _GEN = req_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _grow_param_r_c_cat_T_23; // @[Consts.scala:90:32] assign _grow_param_r_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _coh_on_grant_c_cat_T_23; // @[Consts.scala:90:32] assign _coh_on_grant_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T; // @[Consts.scala:90:32] assign _r1_c_cat_T = _GEN; // @[Consts.scala:90:32] wire _r1_c_cat_T_23; // @[Consts.scala:90:32] assign _r1_c_cat_T_23 = _GEN; // @[Consts.scala:90:32] wire _needs_second_acq_T_27; // @[Consts.scala:90:32] assign _needs_second_acq_T_27 = _GEN; // @[Consts.scala:90:32] wire _GEN_0 = req_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_1; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_24; // @[Consts.scala:90:49] assign _grow_param_r_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:49] assign _coh_on_grant_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_1; // @[Consts.scala:90:49] assign _r1_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49] wire _r1_c_cat_T_24; // @[Consts.scala:90:49] assign _r1_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49] wire _needs_second_acq_T_28; // @[Consts.scala:90:49] assign _needs_second_acq_T_28 = _GEN_0; // @[Consts.scala:90:49] wire _grow_param_r_c_cat_T_2 = _grow_param_r_c_cat_T \| _grow_param_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_1 = req_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_3; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_26; // @[Consts.scala:90:66] assign _grow_param_r_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:66] assign _coh_on_grant_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_3; // @[Consts.scala:90:66] assign _r1_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66] wire _r1_c_cat_T_26; // @[Consts.scala:90:66] assign _r1_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66] wire _needs_second_acq_T_30; // @[Consts.scala:90:66] assign _needs_second_acq_T_30 = _GEN_1; // @[Consts.scala:90:66] wire _grow_param_r_c_cat_T_4 = _grow_param_r_c_cat_T_2 \| _grow_param_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_2 = req_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_5; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_28; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_5; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_28; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_5; // @[package.scala:16:47] assign _r1_c_cat_T_5 = _GEN_2; // @[package.scala:16:47] wire _r1_c_cat_T_28; // @[package.scala:16:47] assign _r1_c_cat_T_28 = _GEN_2; // @[package.scala:16:47] wire _needs_second_acq_T_32; // @[package.scala:16:47] assign _needs_second_acq_T_32 = _GEN_2; // @[package.scala:16:47] wire _GEN_3 = req_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_6; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_29; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_6; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_29; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_6; // @[package.scala:16:47] assign _r1_c_cat_T_6 = _GEN_3; // @[package.scala:16:47] wire _r1_c_cat_T_29; // @[package.scala:16:47] assign _r1_c_cat_T_29 = _GEN_3; // @[package.scala:16:47] wire _needs_second_acq_T_33; // @[package.scala:16:47] assign _needs_second_acq_T_33 = _GEN_3; // @[package.scala:16:47] wire _GEN_4 = req_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_7; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_30; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_7; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_30; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_7; // @[package.scala:16:47] assign _r1_c_cat_T_7 = _GEN_4; // @[package.scala:16:47] wire _r1_c_cat_T_30; // @[package.scala:16:47] assign _r1_c_cat_T_30 = _GEN_4; // @[package.scala:16:47] wire _needs_second_acq_T_34; // @[package.scala:16:47] assign _needs_second_acq_T_34 = _GEN_4; // @[package.scala:16:47] wire _GEN_5 = req_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_8; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_31; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_8; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_31; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_8; // @[package.scala:16:47] assign _r1_c_cat_T_8 = _GEN_5; // @[package.scala:16:47] wire _r1_c_cat_T_31; // @[package.scala:16:47] assign _r1_c_cat_T_31 = _GEN_5; // @[package.scala:16:47] wire _needs_second_acq_T_35; // @[package.scala:16:47] assign _needs_second_acq_T_35 = _GEN_5; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_9 = _grow_param_r_c_cat_T_5 \| _grow_param_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_10 = _grow_param_r_c_cat_T_9 \| _grow_param_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_11 = _grow_param_r_c_cat_T_10 \| _grow_param_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_6 = req_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_12; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_35; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_12; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_35; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_12; // @[package.scala:16:47] assign _r1_c_cat_T_12 = _GEN_6; // @[package.scala:16:47] wire _r1_c_cat_T_35; // @[package.scala:16:47] assign _r1_c_cat_T_35 = _GEN_6; // @[package.scala:16:47] wire _needs_second_acq_T_39; // @[package.scala:16:47] assign _needs_second_acq_T_39 = _GEN_6; // @[package.scala:16:47] wire _GEN_7 = req_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_13; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_36; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_13; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_36; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_13; // @[package.scala:16:47] assign _r1_c_cat_T_13 = _GEN_7; // @[package.scala:16:47] wire _r1_c_cat_T_36; // @[package.scala:16:47] assign _r1_c_cat_T_36 = _GEN_7; // @[package.scala:16:47] wire _needs_second_acq_T_40; // @[package.scala:16:47] assign _needs_second_acq_T_40 = _GEN_7; // @[package.scala:16:47] wire _GEN_8 = req_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_14; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_37; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_14; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_37; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_14; // @[package.scala:16:47] assign _r1_c_cat_T_14 = _GEN_8; // @[package.scala:16:47] wire _r1_c_cat_T_37; // @[package.scala:16:47] assign _r1_c_cat_T_37 = _GEN_8; // @[package.scala:16:47] wire _needs_second_acq_T_41; // @[package.scala:16:47] assign _needs_second_acq_T_41 = _GEN_8; // @[package.scala:16:47] wire _GEN_9 = req_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_15; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_38; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_15; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_38; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_15; // @[package.scala:16:47] assign _r1_c_cat_T_15 = _GEN_9; // @[package.scala:16:47] wire _r1_c_cat_T_38; // @[package.scala:16:47] assign _r1_c_cat_T_38 = _GEN_9; // @[package.scala:16:47] wire _needs_second_acq_T_42; // @[package.scala:16:47] assign _needs_second_acq_T_42 = _GEN_9; // @[package.scala:16:47] wire _GEN_10 = req_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_16; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_39; // @[package.scala:16:47] assign _grow_param_r_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_16; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _coh_on_grant_c_cat_T_39; // @[package.scala:16:47] assign _coh_on_grant_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_16; // @[package.scala:16:47] assign _r1_c_cat_T_16 = _GEN_10; // @[package.scala:16:47] wire _r1_c_cat_T_39; // @[package.scala:16:47] assign _r1_c_cat_T_39 = _GEN_10; // @[package.scala:16:47] wire _needs_second_acq_T_43; // @[package.scala:16:47] assign _needs_second_acq_T_43 = _GEN_10; // @[package.scala:16:47] wire _grow_param_r_c_cat_T_17 = _grow_param_r_c_cat_T_12 \| _grow_param_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_18 = _grow_param_r_c_cat_T_17 \| _grow_param_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_19 = _grow_param_r_c_cat_T_18 \| _grow_param_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_20 = _grow_param_r_c_cat_T_19 \| _grow_param_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_21 = _grow_param_r_c_cat_T_11 \| _grow_param_r_c_cat_T_20; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_22 = _grow_param_r_c_cat_T_4 \| _grow_param_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _grow_param_r_c_cat_T_25 = _grow_param_r_c_cat_T_23 \| _grow_param_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _grow_param_r_c_cat_T_27 = _grow_param_r_c_cat_T_25 \| _grow_param_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _grow_param_r_c_cat_T_32 = _grow_param_r_c_cat_T_28 \| _grow_param_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_33 = _grow_param_r_c_cat_T_32 \| _grow_param_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_34 = _grow_param_r_c_cat_T_33 \| _grow_param_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_40 = _grow_param_r_c_cat_T_35 \| _grow_param_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_41 = _grow_param_r_c_cat_T_40 \| _grow_param_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_42 = _grow_param_r_c_cat_T_41 \| _grow_param_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_43 = _grow_param_r_c_cat_T_42 \| _grow_param_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _grow_param_r_c_cat_T_44 = _grow_param_r_c_cat_T_34 \| _grow_param_r_c_cat_T_43; // @[package.scala:81:59] wire _grow_param_r_c_cat_T_45 = _grow_param_r_c_cat_T_27 \| _grow_param_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_11 = req_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_46; // @[Consts.scala:91:54] assign _grow_param_r_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _coh_on_grant_c_cat_T_46; // @[Consts.scala:91:54] assign _coh_on_grant_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _r1_c_cat_T_46; // @[Consts.scala:91:54] assign _r1_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54] wire _needs_second_acq_T_50; // @[Consts.scala:91:54] assign _needs_second_acq_T_50 = _GEN_11; // @[Consts.scala:91:54] wire _grow_param_r_c_cat_T_47 = _grow_param_r_c_cat_T_45 \| _grow_param_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_12 = req_uop_mem_cmd == 5'h6; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_48; // @[Consts.scala:91:71] assign _grow_param_r_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:71] assign _coh_on_grant_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _r1_c_cat_T_48; // @[Consts.scala:91:71] assign _r1_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71] wire _needs_second_acq_T_52; // @[Consts.scala:91:71] assign _needs_second_acq_T_52 = _GEN_12; // @[Consts.scala:91:71] wire _grow_param_r_c_cat_T_49 = _grow_param_r_c_cat_T_47 \| _grow_param_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] grow_param_r_c = {_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _grow_param_r_T = {grow_param_r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _grow_param_r_T_25 = _grow_param_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_27 = {1'h0, _grow_param_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_28 = _grow_param_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_30 = _grow_param_r_T_28 ? 2'h2 : _grow_param_r_T_27; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_31 = _grow_param_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_33 = _grow_param_r_T_31 ? 2'h1 : _grow_param_r_T_30; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_34 = _grow_param_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_36 = _grow_param_r_T_34 ? 2'h2 : _grow_param_r_T_33; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_37 = _grow_param_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _grow_param_r_T_39 = _grow_param_r_T_37 ? 2'h0 : _grow_param_r_T_36; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_40 = _grow_param_r_T == 4'hE; // @[Misc.scala:49:20] wire _grow_param_r_T_41 = _grow_param_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_42 = _grow_param_r_T_40 ? 2'h3 : _grow_param_r_T_39; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_43 = &_grow_param_r_T; // @[Misc.scala:49:20] wire _grow_param_r_T_44 = _grow_param_r_T_43 \| _grow_param_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_45 = _grow_param_r_T_43 ? 2'h3 : _grow_param_r_T_42; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_46 = _grow_param_r_T == 4'h6; // @[Misc.scala:49:20] wire _grow_param_r_T_47 = _grow_param_r_T_46 \| _grow_param_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_48 = _grow_param_r_T_46 ? 2'h2 : _grow_param_r_T_45; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_49 = _grow_param_r_T == 4'h7; // @[Misc.scala:49:20] wire _grow_param_r_T_50 = _grow_param_r_T_49 \| _grow_param_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_51 = _grow_param_r_T_49 ? 2'h3 : _grow_param_r_T_48; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_52 = _grow_param_r_T == 4'h1; // @[Misc.scala:49:20] wire _grow_param_r_T_53 = _grow_param_r_T_52 \| _grow_param_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_54 = _grow_param_r_T_52 ? 2'h1 : _grow_param_r_T_51; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_55 = _grow_param_r_T == 4'h2; // @[Misc.scala:49:20] wire _grow_param_r_T_56 = _grow_param_r_T_55 \| _grow_param_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _grow_param_r_T_57 = _grow_param_r_T_55 ? 2'h2 : _grow_param_r_T_54; // @[Misc.scala:35:36, :49:20] wire _grow_param_r_T_58 = _grow_param_r_T == 4'h3; // @[Misc.scala:49:20] wire grow_param_r_1 = _grow_param_r_T_58 \| _grow_param_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] grow_param = _grow_param_r_T_58 ? 2'h3 : _grow_param_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] grow_param_meta_state = grow_param; // @[Misc.scala:35:36] wire _coh_on_grant_c_cat_T_2 = _coh_on_grant_c_cat_T \| _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_4 = _coh_on_grant_c_cat_T_2 \| _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_9 = _coh_on_grant_c_cat_T_5 \| _coh_on_grant_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_10 = _coh_on_grant_c_cat_T_9 \| _coh_on_grant_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_11 = _coh_on_grant_c_cat_T_10 \| _coh_on_grant_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_17 = _coh_on_grant_c_cat_T_12 \| _coh_on_grant_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_18 = _coh_on_grant_c_cat_T_17 \| _coh_on_grant_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_19 = _coh_on_grant_c_cat_T_18 \| _coh_on_grant_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_20 = _coh_on_grant_c_cat_T_19 \| _coh_on_grant_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_21 = _coh_on_grant_c_cat_T_11 \| _coh_on_grant_c_cat_T_20; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_22 = _coh_on_grant_c_cat_T_4 \| _coh_on_grant_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_25 = _coh_on_grant_c_cat_T_23 \| _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _coh_on_grant_c_cat_T_27 = _coh_on_grant_c_cat_T_25 \| _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _coh_on_grant_c_cat_T_32 = _coh_on_grant_c_cat_T_28 \| _coh_on_grant_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_33 = _coh_on_grant_c_cat_T_32 \| _coh_on_grant_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_34 = _coh_on_grant_c_cat_T_33 \| _coh_on_grant_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_40 = _coh_on_grant_c_cat_T_35 \| _coh_on_grant_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_41 = _coh_on_grant_c_cat_T_40 \| _coh_on_grant_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_42 = _coh_on_grant_c_cat_T_41 \| _coh_on_grant_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_43 = _coh_on_grant_c_cat_T_42 \| _coh_on_grant_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _coh_on_grant_c_cat_T_44 = _coh_on_grant_c_cat_T_34 \| _coh_on_grant_c_cat_T_43; // @[package.scala:81:59] wire _coh_on_grant_c_cat_T_45 = _coh_on_grant_c_cat_T_27 \| _coh_on_grant_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _coh_on_grant_c_cat_T_47 = _coh_on_grant_c_cat_T_45 \| _coh_on_grant_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _coh_on_grant_c_cat_T_49 = _coh_on_grant_c_cat_T_47 \| _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] coh_on_grant_c = {_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _coh_on_grant_T = {coh_on_grant_c, io_mem_grant_bits_param_0}; // @[Metadata.scala:29:18, :84:18] wire _coh_on_grant_T_9 = _coh_on_grant_T == 4'h1; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_10 = {1'h0, _coh_on_grant_T_9}; // @[Metadata.scala:84:38] wire _coh_on_grant_T_11 = _coh_on_grant_T == 4'h0; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_12 = _coh_on_grant_T_11 ? 2'h2 : _coh_on_grant_T_10; // @[Metadata.scala:84:38] wire _coh_on_grant_T_13 = _coh_on_grant_T == 4'h4; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_14 = _coh_on_grant_T_13 ? 2'h2 : _coh_on_grant_T_12; // @[Metadata.scala:84:38] wire _coh_on_grant_T_15 = _coh_on_grant_T == 4'hC; // @[Metadata.scala:84:{18,38}] wire [1:0] _coh_on_grant_T_16 = _coh_on_grant_T_15 ? 2'h3 : _coh_on_grant_T_14; // @[Metadata.scala:84:38] assign coh_on_grant_state = _coh_on_grant_T_16; // @[Metadata.scala:84:38, :160:20] assign io_commit_coh_state_0 = coh_on_grant_state; // @[Metadata.scala:160:20] wire _r1_c_cat_T_2 = _r1_c_cat_T \| _r1_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_4 = _r1_c_cat_T_2 \| _r1_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_9 = _r1_c_cat_T_5 \| _r1_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_10 = _r1_c_cat_T_9 \| _r1_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_11 = _r1_c_cat_T_10 \| _r1_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_17 = _r1_c_cat_T_12 \| _r1_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_18 = _r1_c_cat_T_17 \| _r1_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_19 = _r1_c_cat_T_18 \| _r1_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_20 = _r1_c_cat_T_19 \| _r1_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_21 = _r1_c_cat_T_11 \| _r1_c_cat_T_20; // @[package.scala:81:59] wire _r1_c_cat_T_22 = _r1_c_cat_T_4 \| _r1_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_25 = _r1_c_cat_T_23 \| _r1_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r1_c_cat_T_27 = _r1_c_cat_T_25 \| _r1_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r1_c_cat_T_32 = _r1_c_cat_T_28 \| _r1_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_33 = _r1_c_cat_T_32 \| _r1_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_34 = _r1_c_cat_T_33 \| _r1_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_40 = _r1_c_cat_T_35 \| _r1_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_41 = _r1_c_cat_T_40 \| _r1_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_42 = _r1_c_cat_T_41 \| _r1_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_43 = _r1_c_cat_T_42 \| _r1_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r1_c_cat_T_44 = _r1_c_cat_T_34 \| _r1_c_cat_T_43; // @[package.scala:81:59] wire _r1_c_cat_T_45 = _r1_c_cat_T_27 \| _r1_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r1_c_cat_T_47 = _r1_c_cat_T_45 \| _r1_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r1_c_cat_T_49 = _r1_c_cat_T_47 \| _r1_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r1_c = {_r1_c_cat_T_22, _r1_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r1_T = {r1_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r1_T_25 = _r1_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r1_T_27 = {1'h0, _r1_T_25}; // @[Misc.scala:35:36, :49:20] wire _r1_T_28 = _r1_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r1_T_30 = _r1_T_28 ? 2'h2 : _r1_T_27; // @[Misc.scala:35:36, :49:20] wire _r1_T_31 = _r1_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r1_T_33 = _r1_T_31 ? 2'h1 : _r1_T_30; // @[Misc.scala:35:36, :49:20] wire _r1_T_34 = _r1_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r1_T_36 = _r1_T_34 ? 2'h2 : _r1_T_33; // @[Misc.scala:35:36, :49:20] wire _r1_T_37 = _r1_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r1_T_39 = _r1_T_37 ? 2'h0 : _r1_T_36; // @[Misc.scala:35:36, :49:20] wire _r1_T_40 = _r1_T == 4'hE; // @[Misc.scala:49:20] wire _r1_T_41 = _r1_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_42 = _r1_T_40 ? 2'h3 : _r1_T_39; // @[Misc.scala:35:36, :49:20] wire _r1_T_43 = &_r1_T; // @[Misc.scala:49:20] wire _r1_T_44 = _r1_T_43 \| _r1_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_45 = _r1_T_43 ? 2'h3 : _r1_T_42; // @[Misc.scala:35:36, :49:20] wire _r1_T_46 = _r1_T == 4'h6; // @[Misc.scala:49:20] wire _r1_T_47 = _r1_T_46 \| _r1_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_48 = _r1_T_46 ? 2'h2 : _r1_T_45; // @[Misc.scala:35:36, :49:20] wire _r1_T_49 = _r1_T == 4'h7; // @[Misc.scala:49:20] wire _r1_T_50 = _r1_T_49 \| _r1_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_51 = _r1_T_49 ? 2'h3 : _r1_T_48; // @[Misc.scala:35:36, :49:20] wire _r1_T_52 = _r1_T == 4'h1; // @[Misc.scala:49:20] wire _r1_T_53 = _r1_T_52 \| _r1_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_54 = _r1_T_52 ? 2'h1 : _r1_T_51; // @[Misc.scala:35:36, :49:20] wire _r1_T_55 = _r1_T == 4'h2; // @[Misc.scala:49:20] wire _r1_T_56 = _r1_T_55 \| _r1_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r1_T_57 = _r1_T_55 ? 2'h2 : _r1_T_54; // @[Misc.scala:35:36, :49:20] wire _r1_T_58 = _r1_T == 4'h3; // @[Misc.scala:49:20] wire r1_1 = _r1_T_58 \| _r1_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r1_2 = _r1_T_58 ? 2'h3 : _r1_T_57; // @[Misc.scala:35:36, :49:20] wire _GEN_13 = io_req_uop_mem_cmd_0 == 5'h1; // @[Consts.scala:90:32] wire _r2_c_cat_T; // @[Consts.scala:90:32] assign _r2_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _r2_c_cat_T_23; // @[Consts.scala:90:32] assign _r2_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _needs_second_acq_T; // @[Consts.scala:90:32] assign _needs_second_acq_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T; // @[Consts.scala:90:32] assign _dirties_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _dirties_cat_T_23; // @[Consts.scala:90:32] assign _dirties_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T; // @[Consts.scala:90:32] assign _state_r_c_cat_T = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_23; // @[Consts.scala:90:32] assign _state_r_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32] wire _state_T_3; // @[Consts.scala:90:32] assign _state_T_3 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_50; // @[Consts.scala:90:32] assign _r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32] wire _r_c_cat_T_73; // @[Consts.scala:90:32] assign _r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_50; // @[Consts.scala:90:32] assign _state_r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32] wire _state_r_c_cat_T_73; // @[Consts.scala:90:32] assign _state_r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32] wire _state_T_37; // @[Consts.scala:90:32] assign _state_T_37 = _GEN_13; // @[Consts.scala:90:32] wire _GEN_14 = io_req_uop_mem_cmd_0 == 5'h11; // @[Consts.scala:90:49] wire _r2_c_cat_T_1; // @[Consts.scala:90:49] assign _r2_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_24; // @[Consts.scala:90:49] assign _r2_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _needs_second_acq_T_1; // @[Consts.scala:90:49] assign _needs_second_acq_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_1; // @[Consts.scala:90:49] assign _dirties_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _dirties_cat_T_24; // @[Consts.scala:90:49] assign _dirties_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_1; // @[Consts.scala:90:49] assign _state_r_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_24; // @[Consts.scala:90:49] assign _state_r_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49] wire _state_T_4; // @[Consts.scala:90:49] assign _state_T_4 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_51; // @[Consts.scala:90:49] assign _r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49] wire _r_c_cat_T_74; // @[Consts.scala:90:49] assign _r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_51; // @[Consts.scala:90:49] assign _state_r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49] wire _state_r_c_cat_T_74; // @[Consts.scala:90:49] assign _state_r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49] wire _state_T_38; // @[Consts.scala:90:49] assign _state_T_38 = _GEN_14; // @[Consts.scala:90:49] wire _r2_c_cat_T_2 = _r2_c_cat_T \| _r2_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _GEN_15 = io_req_uop_mem_cmd_0 == 5'h7; // @[Consts.scala:90:66] wire _r2_c_cat_T_3; // @[Consts.scala:90:66] assign _r2_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_26; // @[Consts.scala:90:66] assign _r2_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _needs_second_acq_T_3; // @[Consts.scala:90:66] assign _needs_second_acq_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_3; // @[Consts.scala:90:66] assign _dirties_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _dirties_cat_T_26; // @[Consts.scala:90:66] assign _dirties_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_3; // @[Consts.scala:90:66] assign _state_r_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_26; // @[Consts.scala:90:66] assign _state_r_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66] wire _state_T_6; // @[Consts.scala:90:66] assign _state_T_6 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_53; // @[Consts.scala:90:66] assign _r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66] wire _r_c_cat_T_76; // @[Consts.scala:90:66] assign _r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_53; // @[Consts.scala:90:66] assign _state_r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66] wire _state_r_c_cat_T_76; // @[Consts.scala:90:66] assign _state_r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66] wire _state_T_40; // @[Consts.scala:90:66] assign _state_T_40 = _GEN_15; // @[Consts.scala:90:66] wire _r2_c_cat_T_4 = _r2_c_cat_T_2 \| _r2_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _GEN_16 = io_req_uop_mem_cmd_0 == 5'h4; // @[package.scala:16:47] wire _r2_c_cat_T_5; // @[package.scala:16:47] assign _r2_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _r2_c_cat_T_28; // @[package.scala:16:47] assign _r2_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _needs_second_acq_T_5; // @[package.scala:16:47] assign _needs_second_acq_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_5; // @[package.scala:16:47] assign _dirties_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _dirties_cat_T_28; // @[package.scala:16:47] assign _dirties_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_5; // @[package.scala:16:47] assign _state_r_c_cat_T_5 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_28; // @[package.scala:16:47] assign _state_r_c_cat_T_28 = _GEN_16; // @[package.scala:16:47] wire _state_T_8; // @[package.scala:16:47] assign _state_T_8 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_55; // @[package.scala:16:47] assign _r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47] wire _r_c_cat_T_78; // @[package.scala:16:47] assign _r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_55; // @[package.scala:16:47] assign _state_r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47] wire _state_r_c_cat_T_78; // @[package.scala:16:47] assign _state_r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47] wire _state_T_42; // @[package.scala:16:47] assign _state_T_42 = _GEN_16; // @[package.scala:16:47] wire _GEN_17 = io_req_uop_mem_cmd_0 == 5'h9; // @[package.scala:16:47] wire _r2_c_cat_T_6; // @[package.scala:16:47] assign _r2_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _r2_c_cat_T_29; // @[package.scala:16:47] assign _r2_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _needs_second_acq_T_6; // @[package.scala:16:47] assign _needs_second_acq_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_6; // @[package.scala:16:47] assign _dirties_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _dirties_cat_T_29; // @[package.scala:16:47] assign _dirties_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_6; // @[package.scala:16:47] assign _state_r_c_cat_T_6 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_29; // @[package.scala:16:47] assign _state_r_c_cat_T_29 = _GEN_17; // @[package.scala:16:47] wire _state_T_9; // @[package.scala:16:47] assign _state_T_9 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_56; // @[package.scala:16:47] assign _r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47] wire _r_c_cat_T_79; // @[package.scala:16:47] assign _r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_56; // @[package.scala:16:47] assign _state_r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47] wire _state_r_c_cat_T_79; // @[package.scala:16:47] assign _state_r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47] wire _state_T_43; // @[package.scala:16:47] assign _state_T_43 = _GEN_17; // @[package.scala:16:47] wire _GEN_18 = io_req_uop_mem_cmd_0 == 5'hA; // @[package.scala:16:47] wire _r2_c_cat_T_7; // @[package.scala:16:47] assign _r2_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _r2_c_cat_T_30; // @[package.scala:16:47] assign _r2_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _needs_second_acq_T_7; // @[package.scala:16:47] assign _needs_second_acq_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_7; // @[package.scala:16:47] assign _dirties_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _dirties_cat_T_30; // @[package.scala:16:47] assign _dirties_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_7; // @[package.scala:16:47] assign _state_r_c_cat_T_7 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_30; // @[package.scala:16:47] assign _state_r_c_cat_T_30 = _GEN_18; // @[package.scala:16:47] wire _state_T_10; // @[package.scala:16:47] assign _state_T_10 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_57; // @[package.scala:16:47] assign _r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47] wire _r_c_cat_T_80; // @[package.scala:16:47] assign _r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_57; // @[package.scala:16:47] assign _state_r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47] wire _state_r_c_cat_T_80; // @[package.scala:16:47] assign _state_r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47] wire _state_T_44; // @[package.scala:16:47] assign _state_T_44 = _GEN_18; // @[package.scala:16:47] wire _GEN_19 = io_req_uop_mem_cmd_0 == 5'hB; // @[package.scala:16:47] wire _r2_c_cat_T_8; // @[package.scala:16:47] assign _r2_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_31; // @[package.scala:16:47] assign _r2_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _needs_second_acq_T_8; // @[package.scala:16:47] assign _needs_second_acq_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_8; // @[package.scala:16:47] assign _dirties_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _dirties_cat_T_31; // @[package.scala:16:47] assign _dirties_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_8; // @[package.scala:16:47] assign _state_r_c_cat_T_8 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_31; // @[package.scala:16:47] assign _state_r_c_cat_T_31 = _GEN_19; // @[package.scala:16:47] wire _state_T_11; // @[package.scala:16:47] assign _state_T_11 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_58; // @[package.scala:16:47] assign _r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47] wire _r_c_cat_T_81; // @[package.scala:16:47] assign _r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_58; // @[package.scala:16:47] assign _state_r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47] wire _state_r_c_cat_T_81; // @[package.scala:16:47] assign _state_r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47] wire _state_T_45; // @[package.scala:16:47] assign _state_T_45 = _GEN_19; // @[package.scala:16:47] wire _r2_c_cat_T_9 = _r2_c_cat_T_5 \| _r2_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_10 = _r2_c_cat_T_9 \| _r2_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_11 = _r2_c_cat_T_10 \| _r2_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _GEN_20 = io_req_uop_mem_cmd_0 == 5'h8; // @[package.scala:16:47] wire _r2_c_cat_T_12; // @[package.scala:16:47] assign _r2_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _r2_c_cat_T_35; // @[package.scala:16:47] assign _r2_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _needs_second_acq_T_12; // @[package.scala:16:47] assign _needs_second_acq_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_12; // @[package.scala:16:47] assign _dirties_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _dirties_cat_T_35; // @[package.scala:16:47] assign _dirties_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_12; // @[package.scala:16:47] assign _state_r_c_cat_T_12 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_35; // @[package.scala:16:47] assign _state_r_c_cat_T_35 = _GEN_20; // @[package.scala:16:47] wire _state_T_15; // @[package.scala:16:47] assign _state_T_15 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_62; // @[package.scala:16:47] assign _r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47] wire _r_c_cat_T_85; // @[package.scala:16:47] assign _r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_62; // @[package.scala:16:47] assign _state_r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47] wire _state_r_c_cat_T_85; // @[package.scala:16:47] assign _state_r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47] wire _state_T_49; // @[package.scala:16:47] assign _state_T_49 = _GEN_20; // @[package.scala:16:47] wire _GEN_21 = io_req_uop_mem_cmd_0 == 5'hC; // @[package.scala:16:47] wire _r2_c_cat_T_13; // @[package.scala:16:47] assign _r2_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _r2_c_cat_T_36; // @[package.scala:16:47] assign _r2_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _needs_second_acq_T_13; // @[package.scala:16:47] assign _needs_second_acq_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_13; // @[package.scala:16:47] assign _dirties_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _dirties_cat_T_36; // @[package.scala:16:47] assign _dirties_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_13; // @[package.scala:16:47] assign _state_r_c_cat_T_13 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_36; // @[package.scala:16:47] assign _state_r_c_cat_T_36 = _GEN_21; // @[package.scala:16:47] wire _state_T_16; // @[package.scala:16:47] assign _state_T_16 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_63; // @[package.scala:16:47] assign _r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47] wire _r_c_cat_T_86; // @[package.scala:16:47] assign _r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_63; // @[package.scala:16:47] assign _state_r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47] wire _state_r_c_cat_T_86; // @[package.scala:16:47] assign _state_r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47] wire _state_T_50; // @[package.scala:16:47] assign _state_T_50 = _GEN_21; // @[package.scala:16:47] wire _GEN_22 = io_req_uop_mem_cmd_0 == 5'hD; // @[package.scala:16:47] wire _r2_c_cat_T_14; // @[package.scala:16:47] assign _r2_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _r2_c_cat_T_37; // @[package.scala:16:47] assign _r2_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _needs_second_acq_T_14; // @[package.scala:16:47] assign _needs_second_acq_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_14; // @[package.scala:16:47] assign _dirties_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _dirties_cat_T_37; // @[package.scala:16:47] assign _dirties_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_14; // @[package.scala:16:47] assign _state_r_c_cat_T_14 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_37; // @[package.scala:16:47] assign _state_r_c_cat_T_37 = _GEN_22; // @[package.scala:16:47] wire _state_T_17; // @[package.scala:16:47] assign _state_T_17 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_64; // @[package.scala:16:47] assign _r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47] wire _r_c_cat_T_87; // @[package.scala:16:47] assign _r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_64; // @[package.scala:16:47] assign _state_r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47] wire _state_r_c_cat_T_87; // @[package.scala:16:47] assign _state_r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47] wire _state_T_51; // @[package.scala:16:47] assign _state_T_51 = _GEN_22; // @[package.scala:16:47] wire _GEN_23 = io_req_uop_mem_cmd_0 == 5'hE; // @[package.scala:16:47] wire _r2_c_cat_T_15; // @[package.scala:16:47] assign _r2_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _r2_c_cat_T_38; // @[package.scala:16:47] assign _r2_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _needs_second_acq_T_15; // @[package.scala:16:47] assign _needs_second_acq_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_15; // @[package.scala:16:47] assign _dirties_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _dirties_cat_T_38; // @[package.scala:16:47] assign _dirties_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_15; // @[package.scala:16:47] assign _state_r_c_cat_T_15 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_38; // @[package.scala:16:47] assign _state_r_c_cat_T_38 = _GEN_23; // @[package.scala:16:47] wire _state_T_18; // @[package.scala:16:47] assign _state_T_18 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_65; // @[package.scala:16:47] assign _r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47] wire _r_c_cat_T_88; // @[package.scala:16:47] assign _r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_65; // @[package.scala:16:47] assign _state_r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47] wire _state_r_c_cat_T_88; // @[package.scala:16:47] assign _state_r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47] wire _state_T_52; // @[package.scala:16:47] assign _state_T_52 = _GEN_23; // @[package.scala:16:47] wire _GEN_24 = io_req_uop_mem_cmd_0 == 5'hF; // @[package.scala:16:47] wire _r2_c_cat_T_16; // @[package.scala:16:47] assign _r2_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_39; // @[package.scala:16:47] assign _r2_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _needs_second_acq_T_16; // @[package.scala:16:47] assign _needs_second_acq_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_16; // @[package.scala:16:47] assign _dirties_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _dirties_cat_T_39; // @[package.scala:16:47] assign _dirties_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_16; // @[package.scala:16:47] assign _state_r_c_cat_T_16 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_39; // @[package.scala:16:47] assign _state_r_c_cat_T_39 = _GEN_24; // @[package.scala:16:47] wire _state_T_19; // @[package.scala:16:47] assign _state_T_19 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_66; // @[package.scala:16:47] assign _r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47] wire _r_c_cat_T_89; // @[package.scala:16:47] assign _r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_66; // @[package.scala:16:47] assign _state_r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47] wire _state_r_c_cat_T_89; // @[package.scala:16:47] assign _state_r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47] wire _state_T_53; // @[package.scala:16:47] assign _state_T_53 = _GEN_24; // @[package.scala:16:47] wire _r2_c_cat_T_17 = _r2_c_cat_T_12 \| _r2_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_18 = _r2_c_cat_T_17 \| _r2_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_19 = _r2_c_cat_T_18 \| _r2_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_20 = _r2_c_cat_T_19 \| _r2_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_21 = _r2_c_cat_T_11 \| _r2_c_cat_T_20; // @[package.scala:81:59] wire _r2_c_cat_T_22 = _r2_c_cat_T_4 \| _r2_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r2_c_cat_T_25 = _r2_c_cat_T_23 \| _r2_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r2_c_cat_T_27 = _r2_c_cat_T_25 \| _r2_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r2_c_cat_T_32 = _r2_c_cat_T_28 \| _r2_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_33 = _r2_c_cat_T_32 \| _r2_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_34 = _r2_c_cat_T_33 \| _r2_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_40 = _r2_c_cat_T_35 \| _r2_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_41 = _r2_c_cat_T_40 \| _r2_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_42 = _r2_c_cat_T_41 \| _r2_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_43 = _r2_c_cat_T_42 \| _r2_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r2_c_cat_T_44 = _r2_c_cat_T_34 \| _r2_c_cat_T_43; // @[package.scala:81:59] wire _r2_c_cat_T_45 = _r2_c_cat_T_27 \| _r2_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _GEN_25 = io_req_uop_mem_cmd_0 == 5'h3; // @[Consts.scala:91:54] wire _r2_c_cat_T_46; // @[Consts.scala:91:54] assign _r2_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _needs_second_acq_T_23; // @[Consts.scala:91:54] assign _needs_second_acq_T_23 = _GEN_25; // @[Consts.scala:91:54] wire _dirties_cat_T_46; // @[Consts.scala:91:54] assign _dirties_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _rpq_io_enq_valid_T_4; // @[Consts.scala:88:52] assign _rpq_io_enq_valid_T_4 = _GEN_25; // @[Consts.scala:88:52, :91:54] wire _state_r_c_cat_T_46; // @[Consts.scala:91:54] assign _state_r_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54] wire _r_c_cat_T_96; // @[Consts.scala:91:54] assign _r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54] wire _state_r_c_cat_T_96; // @[Consts.scala:91:54] assign _state_r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54] wire _r2_c_cat_T_47 = _r2_c_cat_T_45 \| _r2_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _GEN_26 = io_req_uop_mem_cmd_0 == 5'h6; // @[Consts.scala:91:71] wire _r2_c_cat_T_48; // @[Consts.scala:91:71] assign _r2_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _needs_second_acq_T_25; // @[Consts.scala:91:71] assign _needs_second_acq_T_25 = _GEN_26; // @[Consts.scala:91:71] wire _dirties_cat_T_48; // @[Consts.scala:91:71] assign _dirties_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _state_r_c_cat_T_48; // @[Consts.scala:91:71] assign _state_r_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71] wire _r_c_cat_T_98; // @[Consts.scala:91:71] assign _r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71] wire _state_r_c_cat_T_98; // @[Consts.scala:91:71] assign _state_r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71] wire _r2_c_cat_T_49 = _r2_c_cat_T_47 \| _r2_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r2_c = {_r2_c_cat_T_22, _r2_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r2_T = {r2_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r2_T_25 = _r2_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r2_T_27 = {1'h0, _r2_T_25}; // @[Misc.scala:35:36, :49:20] wire _r2_T_28 = _r2_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r2_T_30 = _r2_T_28 ? 2'h2 : _r2_T_27; // @[Misc.scala:35:36, :49:20] wire _r2_T_31 = _r2_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r2_T_33 = _r2_T_31 ? 2'h1 : _r2_T_30; // @[Misc.scala:35:36, :49:20] wire _r2_T_34 = _r2_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r2_T_36 = _r2_T_34 ? 2'h2 : _r2_T_33; // @[Misc.scala:35:36, :49:20] wire _r2_T_37 = _r2_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r2_T_39 = _r2_T_37 ? 2'h0 : _r2_T_36; // @[Misc.scala:35:36, :49:20] wire _r2_T_40 = _r2_T == 4'hE; // @[Misc.scala:49:20] wire _r2_T_41 = _r2_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_42 = _r2_T_40 ? 2'h3 : _r2_T_39; // @[Misc.scala:35:36, :49:20] wire _r2_T_43 = &_r2_T; // @[Misc.scala:49:20] wire _r2_T_44 = _r2_T_43 \| _r2_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_45 = _r2_T_43 ? 2'h3 : _r2_T_42; // @[Misc.scala:35:36, :49:20] wire _r2_T_46 = _r2_T == 4'h6; // @[Misc.scala:49:20] wire _r2_T_47 = _r2_T_46 \| _r2_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_48 = _r2_T_46 ? 2'h2 : _r2_T_45; // @[Misc.scala:35:36, :49:20] wire _r2_T_49 = _r2_T == 4'h7; // @[Misc.scala:49:20] wire _r2_T_50 = _r2_T_49 \| _r2_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_51 = _r2_T_49 ? 2'h3 : _r2_T_48; // @[Misc.scala:35:36, :49:20] wire _r2_T_52 = _r2_T == 4'h1; // @[Misc.scala:49:20] wire _r2_T_53 = _r2_T_52 \| _r2_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_54 = _r2_T_52 ? 2'h1 : _r2_T_51; // @[Misc.scala:35:36, :49:20] wire _r2_T_55 = _r2_T == 4'h2; // @[Misc.scala:49:20] wire _r2_T_56 = _r2_T_55 \| _r2_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _r2_T_57 = _r2_T_55 ? 2'h2 : _r2_T_54; // @[Misc.scala:35:36, :49:20] wire _r2_T_58 = _r2_T == 4'h3; // @[Misc.scala:49:20] wire r2_1 = _r2_T_58 \| _r2_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] r2_2 = _r2_T_58 ? 2'h3 : _r2_T_57; // @[Misc.scala:35:36, :49:20] wire _needs_second_acq_T_2 = _needs_second_acq_T \| _needs_second_acq_T_1; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_4 = _needs_second_acq_T_2 \| _needs_second_acq_T_3; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_9 = _needs_second_acq_T_5 \| _needs_second_acq_T_6; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_10 = _needs_second_acq_T_9 \| _needs_second_acq_T_7; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_11 = _needs_second_acq_T_10 \| _needs_second_acq_T_8; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_17 = _needs_second_acq_T_12 \| _needs_second_acq_T_13; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_18 = _needs_second_acq_T_17 \| _needs_second_acq_T_14; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_19 = _needs_second_acq_T_18 \| _needs_second_acq_T_15; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_20 = _needs_second_acq_T_19 \| _needs_second_acq_T_16; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_21 = _needs_second_acq_T_11 \| _needs_second_acq_T_20; // @[package.scala:81:59] wire _needs_second_acq_T_22 = _needs_second_acq_T_4 \| _needs_second_acq_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_24 = _needs_second_acq_T_22 \| _needs_second_acq_T_23; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_26 = _needs_second_acq_T_24 \| _needs_second_acq_T_25; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_29 = _needs_second_acq_T_27 \| _needs_second_acq_T_28; // @[Consts.scala:90:{32,42,49}] wire _needs_second_acq_T_31 = _needs_second_acq_T_29 \| _needs_second_acq_T_30; // @[Consts.scala:90:{42,59,66}] wire _needs_second_acq_T_36 = _needs_second_acq_T_32 \| _needs_second_acq_T_33; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_37 = _needs_second_acq_T_36 \| _needs_second_acq_T_34; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_38 = _needs_second_acq_T_37 \| _needs_second_acq_T_35; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_44 = _needs_second_acq_T_39 \| _needs_second_acq_T_40; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_45 = _needs_second_acq_T_44 \| _needs_second_acq_T_41; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_46 = _needs_second_acq_T_45 \| _needs_second_acq_T_42; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_47 = _needs_second_acq_T_46 \| _needs_second_acq_T_43; // @[package.scala:16:47, :81:59] wire _needs_second_acq_T_48 = _needs_second_acq_T_38 \| _needs_second_acq_T_47; // @[package.scala:81:59] wire _needs_second_acq_T_49 = _needs_second_acq_T_31 \| _needs_second_acq_T_48; // @[Consts.scala:87:44, :90:{59,76}] wire _needs_second_acq_T_51 = _needs_second_acq_T_49 \| _needs_second_acq_T_50; // @[Consts.scala:90:76, :91:{47,54}] wire _needs_second_acq_T_53 = _needs_second_acq_T_51 \| _needs_second_acq_T_52; // @[Consts.scala:91:{47,64,71}] wire _needs_second_acq_T_54 = ~_needs_second_acq_T_53; // @[Metadata.scala:104:57] wire cmd_requires_second_acquire = _needs_second_acq_T_26 & _needs_second_acq_T_54; // @[Metadata.scala:104:{54,57}] wire is_hit_again = r1_1 & r2_1; // @[Misc.scala:35:9] wire _dirties_cat_T_2 = _dirties_cat_T \| _dirties_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_4 = _dirties_cat_T_2 \| _dirties_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_9 = _dirties_cat_T_5 \| _dirties_cat_T_6; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_10 = _dirties_cat_T_9 \| _dirties_cat_T_7; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_11 = _dirties_cat_T_10 \| _dirties_cat_T_8; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_17 = _dirties_cat_T_12 \| _dirties_cat_T_13; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_18 = _dirties_cat_T_17 \| _dirties_cat_T_14; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_19 = _dirties_cat_T_18 \| _dirties_cat_T_15; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_20 = _dirties_cat_T_19 \| _dirties_cat_T_16; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_21 = _dirties_cat_T_11 \| _dirties_cat_T_20; // @[package.scala:81:59] wire _dirties_cat_T_22 = _dirties_cat_T_4 \| _dirties_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_25 = _dirties_cat_T_23 \| _dirties_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _dirties_cat_T_27 = _dirties_cat_T_25 \| _dirties_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _dirties_cat_T_32 = _dirties_cat_T_28 \| _dirties_cat_T_29; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_33 = _dirties_cat_T_32 \| _dirties_cat_T_30; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_34 = _dirties_cat_T_33 \| _dirties_cat_T_31; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_40 = _dirties_cat_T_35 \| _dirties_cat_T_36; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_41 = _dirties_cat_T_40 \| _dirties_cat_T_37; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_42 = _dirties_cat_T_41 \| _dirties_cat_T_38; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_43 = _dirties_cat_T_42 \| _dirties_cat_T_39; // @[package.scala:16:47, :81:59] wire _dirties_cat_T_44 = _dirties_cat_T_34 \| _dirties_cat_T_43; // @[package.scala:81:59] wire _dirties_cat_T_45 = _dirties_cat_T_27 \| _dirties_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _dirties_cat_T_47 = _dirties_cat_T_45 \| _dirties_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _dirties_cat_T_49 = _dirties_cat_T_47 \| _dirties_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] dirties_cat = {_dirties_cat_T_22, _dirties_cat_T_49}; // @[Metadata.scala:29:18] wire dirties = &dirties_cat; // @[Metadata.scala:29:18, :106:42] wire [1:0] biggest_grow_param = dirties ? r2_2 : r1_2; // @[Misc.scala:35:36] wire [1:0] dirtier_coh_state = biggest_grow_param; // @[Metadata.scala:107:33, :160:20] wire [4:0] dirtier_cmd = dirties ? io_req_uop_mem_cmd_0 : req_uop_mem_cmd; // @[Metadata.scala:106:42, :109:27] wire _T_16 = io_mem_grant_ready_0 & io_mem_grant_valid_0; // @[Decoupled.scala:51:35] wire [26:0] _r_beats1_decode_T = 27'hFFF << io_mem_grant_bits_size_0; // @[package.scala:243:71] wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire r_beats1_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire grant_had_data_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36] wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] r_counter; // @[Edges.scala:229:27] wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28] wire r_1_1 = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire r_2 = _r_last_T \| _r_last_T_1; // @[Edges.scala:232:{25,33,43}] wire refill_done = r_2 & _T_16; // @[Decoupled.scala:51:35] wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _r_counter_T = r_1_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] refill_address_inc = {r_4, 3'h0}; // @[Edges.scala:234:25, :269:29] wire _sec_rdy_T = ~cmd_requires_second_acquire; // @[Metadata.scala:104:54] wire _sec_rdy_T_1 = ~io_req_is_probe_0; // @[mshrs.scala:36:7, :125:50] wire _sec_rdy_T_2 = _sec_rdy_T & _sec_rdy_T_1; // @[mshrs.scala:125:{18,47,50}] wire _sec_rdy_T_3 = ~(\|state); // @[package.scala:16:47] wire _sec_rdy_T_4 = state == 5'hD; // @[package.scala:16:47] wire _sec_rdy_T_5 = state == 5'hE; // @[package.scala:16:47] wire _sec_rdy_T_6 = state == 5'hF; // @[package.scala:16:47] wire _sec_rdy_T_7 = _sec_rdy_T_3 \| _sec_rdy_T_4; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_8 = _sec_rdy_T_7 \| _sec_rdy_T_5; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_9 = _sec_rdy_T_8 \| _sec_rdy_T_6; // @[package.scala:16:47, :81:59] wire _sec_rdy_T_10 = ~_sec_rdy_T_9; // @[package.scala:81:59] wire sec_rdy = _sec_rdy_T_2 & _sec_rdy_T_10; // @[mshrs.scala:125:{47,67}, :126:18] wire _rpq_io_enq_valid_T = io_req_pri_val_0 & io_req_pri_rdy_0; // @[mshrs.scala:36:7, :133:40] wire _rpq_io_enq_valid_T_1 = io_req_sec_val_0 & io_req_sec_rdy_0; // @[mshrs.scala:36:7, :133:78] wire _rpq_io_enq_valid_T_2 = _rpq_io_enq_valid_T \| _rpq_io_enq_valid_T_1; // @[mshrs.scala:133:{40,59,78}] wire _rpq_io_enq_valid_T_3 = io_req_uop_mem_cmd_0 == 5'h2; // @[Consts.scala:88:35] wire _rpq_io_enq_valid_T_5 = _rpq_io_enq_valid_T_3 \| _rpq_io_enq_valid_T_4; // @[Consts.scala:88:{35,45,52}] wire _rpq_io_enq_valid_T_6 = ~_rpq_io_enq_valid_T_5; // @[Consts.scala:88:45] wire _rpq_io_enq_valid_T_7 = _rpq_io_enq_valid_T_2 & _rpq_io_enq_valid_T_6; // @[mshrs.scala:133:{59,98,101}] reg grantack_valid; // @[mshrs.scala:138:21] reg [2:0] grantack_bits_sink; // @[mshrs.scala:138:21] assign io_mem_finish_bits_sink_0 = grantack_bits_sink; // @[mshrs.scala:36:7, :138:21] reg [2:0] refill_ctr; // @[mshrs.scala:139:24] reg commit_line; // @[mshrs.scala:140:24] reg grant_had_data; // @[mshrs.scala:141:27] reg finish_to_prefetch; // @[mshrs.scala:142:31] reg [1:0] meta_hazard; // @[mshrs.scala:145:28] wire [2:0] _meta_hazard_T = {1'h0, meta_hazard} + 3'h1; // @[mshrs.scala:145:28, :146:59] wire [1:0] _meta_hazard_T_1 = _meta_hazard_T[1:0]; // @[mshrs.scala:146:59] wire _io_probe_rdy_T = meta_hazard == 2'h0; // @[mshrs.scala:145:28, :148:34] wire _io_probe_rdy_T_1 = ~(\|state); // @[package.scala:16:47] wire _io_probe_rdy_T_2 = state == 5'h1; // @[package.scala:16:47] wire _io_probe_rdy_T_3 = state == 5'h2; // @[package.scala:16:47] wire _io_probe_rdy_T_4 = state == 5'h3; // @[package.scala:16:47] wire _io_probe_rdy_T_5 = _io_probe_rdy_T_1 \| _io_probe_rdy_T_2; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_6 = _io_probe_rdy_T_5 \| _io_probe_rdy_T_3; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_7 = _io_probe_rdy_T_6 \| _io_probe_rdy_T_4; // @[package.scala:16:47, :81:59] wire _io_probe_rdy_T_8 = state == 5'h4; // @[mshrs.scala:107:22, :148:129] wire _io_probe_rdy_T_9 = _io_probe_rdy_T_8 & grantack_valid; // @[mshrs.scala:138:21, :148:{129,145}] wire _io_probe_rdy_T_10 = _io_probe_rdy_T_7 \| _io_probe_rdy_T_9; // @[package.scala:81:59] assign _io_probe_rdy_T_11 = _io_probe_rdy_T & _io_probe_rdy_T_10; // @[mshrs.scala:148:{34,42,119}] assign io_probe_rdy_0 = _io_probe_rdy_T_11; // @[mshrs.scala:36:7, :148:42] assign _io_idx_valid_T = \|state; // @[package.scala:16:47] assign io_idx_valid_0 = _io_idx_valid_T; // @[mshrs.scala:36:7, :149:25] assign _io_tag_valid_T = \|state; // @[package.scala:16:47] assign io_tag_valid_0 = _io_tag_valid_T; // @[mshrs.scala:36:7, :150:25] wire _io_way_valid_T = ~(\|state); // @[package.scala:16:47] wire _io_way_valid_T_1 = state == 5'h11; // @[package.scala:16:47] wire _io_way_valid_T_2 = _io_way_valid_T \| _io_way_valid_T_1; // @[package.scala:16:47, :81:59] assign _io_way_valid_T_3 = ~_io_way_valid_T_2; // @[package.scala:81:59] assign io_way_valid_0 = _io_way_valid_T_3; // @[mshrs.scala:36:7, :151:19] assign _io_req_sec_rdy_T = sec_rdy & _rpq_io_enq_ready; // @[mshrs.scala:125:67, :128:19, :159:37] assign io_req_sec_rdy_0 = _io_req_sec_rdy_T; // @[mshrs.scala:36:7, :159:37] wire [4:0] state_new_state; // @[mshrs.scala:191:29] wire _state_T_1 = ~_state_T; // @[mshrs.scala:194:11] wire _state_T_2 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11] wire [3:0] _GEN_27 = {2'h2, io_req_old_meta_coh_state_0}; // @[Metadata.scala:120:19] wire [3:0] _state_req_needs_wb_r_T_6; // @[Metadata.scala:120:19] assign _state_req_needs_wb_r_T_6 = _GEN_27; // @[Metadata.scala:120:19] wire [3:0] _state_req_needs_wb_r_T_70; // @[Metadata.scala:120:19] assign _state_req_needs_wb_r_T_70 = _GEN_27; // @[Metadata.scala:120:19] wire _state_req_needs_wb_r_T_19 = _state_req_needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_21 = _state_req_needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_23 = _state_req_needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_25 = _state_req_needs_wb_r_T_23 ? 3'h2 : _state_req_needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_27 = _state_req_needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_29 = _state_req_needs_wb_r_T_27 ? 3'h1 : _state_req_needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_31 = _state_req_needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_32 = _state_req_needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_33 = _state_req_needs_wb_r_T_31 ? 3'h1 : _state_req_needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_35 = _state_req_needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_36 = ~_state_req_needs_wb_r_T_35 & _state_req_needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_37 = _state_req_needs_wb_r_T_35 ? 3'h5 : _state_req_needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_39 = _state_req_needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_40 = ~_state_req_needs_wb_r_T_39 & _state_req_needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_41 = _state_req_needs_wb_r_T_39 ? 3'h4 : _state_req_needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_42 = {1'h0, _state_req_needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_43 = _state_req_needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_44 = ~_state_req_needs_wb_r_T_43 & _state_req_needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_45 = _state_req_needs_wb_r_T_43 ? 3'h0 : _state_req_needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_46 = _state_req_needs_wb_r_T_43 ? 2'h1 : _state_req_needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_47 = _state_req_needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_48 = _state_req_needs_wb_r_T_47 \| _state_req_needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_49 = _state_req_needs_wb_r_T_47 ? 3'h0 : _state_req_needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_50 = _state_req_needs_wb_r_T_47 ? 2'h1 : _state_req_needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_51 = _state_req_needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_52 = ~_state_req_needs_wb_r_T_51 & _state_req_needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_53 = _state_req_needs_wb_r_T_51 ? 3'h5 : _state_req_needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_54 = _state_req_needs_wb_r_T_51 ? 2'h0 : _state_req_needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_55 = _state_req_needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_56 = ~_state_req_needs_wb_r_T_55 & _state_req_needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_57 = _state_req_needs_wb_r_T_55 ? 3'h4 : _state_req_needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_58 = _state_req_needs_wb_r_T_55 ? 2'h1 : _state_req_needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_59 = _state_req_needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_60 = ~_state_req_needs_wb_r_T_59 & _state_req_needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_61 = _state_req_needs_wb_r_T_59 ? 3'h3 : _state_req_needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_62 = _state_req_needs_wb_r_T_59 ? 2'h2 : _state_req_needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_63 = _state_req_needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire state_req_needs_wb_r_1 = _state_req_needs_wb_r_T_63 \| _state_req_needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] state_req_needs_wb_r_2 = _state_req_needs_wb_r_T_63 ? 3'h3 : _state_req_needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] state_req_needs_wb_r_3 = _state_req_needs_wb_r_T_63 ? 2'h2 : _state_req_needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] state_req_needs_wb_meta_state = state_req_needs_wb_r_3; // @[Misc.scala:38:63] wire _state_r_c_cat_T_2 = _state_r_c_cat_T \| _state_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_4 = _state_r_c_cat_T_2 \| _state_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_9 = _state_r_c_cat_T_5 \| _state_r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_10 = _state_r_c_cat_T_9 \| _state_r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_11 = _state_r_c_cat_T_10 \| _state_r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_17 = _state_r_c_cat_T_12 \| _state_r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_18 = _state_r_c_cat_T_17 \| _state_r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_19 = _state_r_c_cat_T_18 \| _state_r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_20 = _state_r_c_cat_T_19 \| _state_r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_21 = _state_r_c_cat_T_11 \| _state_r_c_cat_T_20; // @[package.scala:81:59] wire _state_r_c_cat_T_22 = _state_r_c_cat_T_4 \| _state_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_25 = _state_r_c_cat_T_23 \| _state_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_27 = _state_r_c_cat_T_25 \| _state_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_32 = _state_r_c_cat_T_28 \| _state_r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_33 = _state_r_c_cat_T_32 \| _state_r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_34 = _state_r_c_cat_T_33 \| _state_r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_40 = _state_r_c_cat_T_35 \| _state_r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_41 = _state_r_c_cat_T_40 \| _state_r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_42 = _state_r_c_cat_T_41 \| _state_r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_43 = _state_r_c_cat_T_42 \| _state_r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_44 = _state_r_c_cat_T_34 \| _state_r_c_cat_T_43; // @[package.scala:81:59] wire _state_r_c_cat_T_45 = _state_r_c_cat_T_27 \| _state_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_47 = _state_r_c_cat_T_45 \| _state_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _state_r_c_cat_T_49 = _state_r_c_cat_T_47 \| _state_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] state_r_c = {_state_r_c_cat_T_22, _state_r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _state_r_T = {state_r_c, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19] wire _state_r_T_25 = _state_r_T == 4'hC; // @[Misc.scala:49:20] wire [1:0] _state_r_T_27 = {1'h0, _state_r_T_25}; // @[Misc.scala:35:36, :49:20] wire _state_r_T_28 = _state_r_T == 4'hD; // @[Misc.scala:49:20] wire [1:0] _state_r_T_30 = _state_r_T_28 ? 2'h2 : _state_r_T_27; // @[Misc.scala:35:36, :49:20] wire _state_r_T_31 = _state_r_T == 4'h4; // @[Misc.scala:49:20] wire [1:0] _state_r_T_33 = _state_r_T_31 ? 2'h1 : _state_r_T_30; // @[Misc.scala:35:36, :49:20] wire _state_r_T_34 = _state_r_T == 4'h5; // @[Misc.scala:49:20] wire [1:0] _state_r_T_36 = _state_r_T_34 ? 2'h2 : _state_r_T_33; // @[Misc.scala:35:36, :49:20] wire _state_r_T_37 = _state_r_T == 4'h0; // @[Misc.scala:49:20] wire [1:0] _state_r_T_39 = _state_r_T_37 ? 2'h0 : _state_r_T_36; // @[Misc.scala:35:36, :49:20] wire _state_r_T_40 = _state_r_T == 4'hE; // @[Misc.scala:49:20] wire _state_r_T_41 = _state_r_T_40; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_42 = _state_r_T_40 ? 2'h3 : _state_r_T_39; // @[Misc.scala:35:36, :49:20] wire _state_r_T_43 = &_state_r_T; // @[Misc.scala:49:20] wire _state_r_T_44 = _state_r_T_43 \| _state_r_T_41; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_45 = _state_r_T_43 ? 2'h3 : _state_r_T_42; // @[Misc.scala:35:36, :49:20] wire _state_r_T_46 = _state_r_T == 4'h6; // @[Misc.scala:49:20] wire _state_r_T_47 = _state_r_T_46 \| _state_r_T_44; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_48 = _state_r_T_46 ? 2'h2 : _state_r_T_45; // @[Misc.scala:35:36, :49:20] wire _state_r_T_49 = _state_r_T == 4'h7; // @[Misc.scala:49:20] wire _state_r_T_50 = _state_r_T_49 \| _state_r_T_47; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_51 = _state_r_T_49 ? 2'h3 : _state_r_T_48; // @[Misc.scala:35:36, :49:20] wire _state_r_T_52 = _state_r_T == 4'h1; // @[Misc.scala:49:20] wire _state_r_T_53 = _state_r_T_52 \| _state_r_T_50; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_54 = _state_r_T_52 ? 2'h1 : _state_r_T_51; // @[Misc.scala:35:36, :49:20] wire _state_r_T_55 = _state_r_T == 4'h2; // @[Misc.scala:49:20] wire _state_r_T_56 = _state_r_T_55 \| _state_r_T_53; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_57 = _state_r_T_55 ? 2'h2 : _state_r_T_54; // @[Misc.scala:35:36, :49:20] wire _state_r_T_58 = _state_r_T == 4'h3; // @[Misc.scala:49:20] wire state_is_hit = _state_r_T_58 \| _state_r_T_56; // @[Misc.scala:35:9, :49:20] wire [1:0] state_r_2 = _state_r_T_58 ? 2'h3 : _state_r_T_57; // @[Misc.scala:35:36, :49:20] wire [1:0] state_coh_on_hit_state = state_r_2; // @[Misc.scala:35:36] wire _state_T_5 = _state_T_3 \| _state_T_4; // @[Consts.scala:90:{32,42,49}] wire _state_T_7 = _state_T_5 \| _state_T_6; // @[Consts.scala:90:{42,59,66}] wire _state_T_12 = _state_T_8 \| _state_T_9; // @[package.scala:16:47, :81:59] wire _state_T_13 = _state_T_12 \| _state_T_10; // @[package.scala:16:47, :81:59] wire _state_T_14 = _state_T_13 \| _state_T_11; // @[package.scala:16:47, :81:59] wire _state_T_20 = _state_T_15 \| _state_T_16; // @[package.scala:16:47, :81:59] wire _state_T_21 = _state_T_20 \| _state_T_17; // @[package.scala:16:47, :81:59] wire _state_T_22 = _state_T_21 \| _state_T_18; // @[package.scala:16:47, :81:59] wire _state_T_23 = _state_T_22 \| _state_T_19; // @[package.scala:16:47, :81:59] wire _state_T_24 = _state_T_14 \| _state_T_23; // @[package.scala:81:59] wire _state_T_25 = _state_T_7 \| _state_T_24; // @[Consts.scala:87:44, :90:{59,76}] wire _state_T_27 = ~_state_T_26; // @[mshrs.scala:201:15] wire _state_T_28 = ~_state_T_25; // @[Consts.scala:90:76] assign state_new_state = io_req_tag_match_0 & state_is_hit ? 5'hC : 5'h1; // @[Misc.scala:35:9] assign io_mem_acquire_valid_0 = (\|state) & _io_probe_rdy_T_2; // @[package.scala:16:47] wire [27:0] _GEN_28 = {req_tag, req_idx}; // @[mshrs.scala:110:25, :111:26, :227:28] wire [27:0] _io_mem_acquire_bits_T; // @[mshrs.scala:227:28] assign _io_mem_acquire_bits_T = _GEN_28; // @[mshrs.scala:227:28] wire [27:0] rp_addr_hi; // @[mshrs.scala:261:22] assign rp_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :261:22] wire [27:0] hi; // @[mshrs.scala:266:10] assign hi = _GEN_28; // @[mshrs.scala:227:28, :266:10] wire [27:0] io_replay_bits_addr_hi; // @[mshrs.scala:353:31] assign io_replay_bits_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :353:31] wire [33:0] _io_mem_acquire_bits_T_1 = {_io_mem_acquire_bits_T, 6'h0}; // @[mshrs.scala:227:{28,47}] wire [33:0] _io_mem_acquire_bits_legal_T_1 = _io_mem_acquire_bits_T_1; // @[Parameters.scala:137:31] wire [34:0] _io_mem_acquire_bits_legal_T_2 = {1'h0, _io_mem_acquire_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_mem_acquire_bits_legal_T_3 = _io_mem_acquire_bits_legal_T_2 & 35'h80000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_mem_acquire_bits_legal_T_4 = _io_mem_acquire_bits_legal_T_3; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_5 = _io_mem_acquire_bits_legal_T_4 == 35'h0; // @[Parameters.scala:137:{46,59}] assign io_mem_acquire_bits_a_address = _io_mem_acquire_bits_T_1[31:0]; // @[Edges.scala:346:17] wire [33:0] _io_mem_acquire_bits_legal_T_9 = {_io_mem_acquire_bits_T_1[33:32], io_mem_acquire_bits_a_address ^ 32'h80000000}; // @[Edges.scala:346:17] wire [34:0] _io_mem_acquire_bits_legal_T_10 = {1'h0, _io_mem_acquire_bits_legal_T_9}; // @[Parameters.scala:137:{31,41}] wire [34:0] _io_mem_acquire_bits_legal_T_11 = _io_mem_acquire_bits_legal_T_10 & 35'h80000000; // @[Parameters.scala:137:{41,46}] wire [34:0] _io_mem_acquire_bits_legal_T_12 = _io_mem_acquire_bits_legal_T_11; // @[Parameters.scala:137:46] wire _io_mem_acquire_bits_legal_T_13 = _io_mem_acquire_bits_legal_T_12 == 35'h0; // @[Parameters.scala:137:{46,59}] wire _io_mem_acquire_bits_legal_T_14 = _io_mem_acquire_bits_legal_T_13; // @[Parameters.scala:684:54] wire io_mem_acquire_bits_legal = _io_mem_acquire_bits_legal_T_14; // @[Parameters.scala:684:54, :686:26] assign io_mem_acquire_bits_param_0 = io_mem_acquire_bits_a_param; // @[Edges.scala:346:17] assign io_mem_acquire_bits_address_0 = io_mem_acquire_bits_a_address; // @[Edges.scala:346:17] assign io_mem_acquire_bits_a_param = {1'h0, grow_param}; // @[Misc.scala:35:36] wire io_mem_acquire_bits_a_mask_sub_sub_bit = _io_mem_acquire_bits_T_1[2]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T = io_mem_acquire_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = io_mem_acquire_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_sub_bit = _io_mem_acquire_bits_T_1[1]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire io_mem_acquire_bits_a_mask_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire io_mem_acquire_bits_a_mask_bit = _io_mem_acquire_bits_T_1[0]; // @[Misc.scala:210:26] wire io_mem_acquire_bits_a_mask_nbit = ~io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20] wire io_mem_acquire_bits_a_mask_eq = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T = io_mem_acquire_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_1 = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_1 = io_mem_acquire_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_2 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_2 = io_mem_acquire_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_3 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_3 = io_mem_acquire_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_4 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_4 = io_mem_acquire_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_5 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_5 = io_mem_acquire_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_6 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_6 = io_mem_acquire_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38] wire io_mem_acquire_bits_a_mask_eq_7 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27] wire _io_mem_acquire_bits_a_mask_acc_T_7 = io_mem_acquire_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38] wire _GEN_29 = ~(\|state) \| _io_probe_rdy_T_2; // @[package.scala:16:47] assign io_lb_write_valid_0 = ~_GEN_29 & _io_probe_rdy_T_3 & opdata & io_mem_grant_valid_0; // @[package.scala:16:47] wire [8:0] _io_lb_write_bits_offset_T = refill_address_inc[11:3]; // @[Edges.scala:269:29] assign io_lb_write_bits_offset_0 = _io_lb_write_bits_offset_T[2:0]; // @[mshrs.scala:36:7, :238:{31,53}] assign io_mem_grant_ready_0 = ~_GEN_29 & _io_probe_rdy_T_3 & (~opdata \| io_lb_write_ready_0); // @[package.scala:16:47] wire _grantack_valid_T = io_mem_grant_bits_opcode_0[2]; // @[Edges.scala:71:36] wire _grantack_valid_T_1 = io_mem_grant_bits_opcode_0[1]; // @[Edges.scala:71:52] wire _grantack_valid_T_2 = ~_grantack_valid_T_1; // @[Edges.scala:71:{43,52}] wire _grantack_valid_T_3 = _grantack_valid_T & _grantack_valid_T_2; // @[Edges.scala:71:{36,40,43}] wire [4:0] _state_T_29 = grant_had_data ? 5'h3 : 5'hC; // @[mshrs.scala:141:27, :250:19] wire _drain_load_T = _rpq_io_deq_bits_uop_mem_cmd == 5'h0; // @[package.scala:16:47] wire _drain_load_T_1 = _rpq_io_deq_bits_uop_mem_cmd == 5'h10; // @[package.scala:16:47] wire _GEN_30 = _rpq_io_deq_bits_uop_mem_cmd == 5'h6; // @[package.scala:16:47] wire _drain_load_T_2; // @[package.scala:16:47] assign _drain_load_T_2 = _GEN_30; // @[package.scala:16:47] wire _r_c_cat_T_48; // @[Consts.scala:91:71] assign _r_c_cat_T_48 = _GEN_30; // @[package.scala:16:47] wire _GEN_31 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[package.scala:16:47] wire _drain_load_T_3; // @[package.scala:16:47] assign _drain_load_T_3 = _GEN_31; // @[package.scala:16:47] wire _drain_load_T_28; // @[Consts.scala:90:66] assign _drain_load_T_28 = _GEN_31; // @[package.scala:16:47] wire _drain_load_T_4 = _drain_load_T \| _drain_load_T_1; // @[package.scala:16:47, :81:59] wire _drain_load_T_5 = _drain_load_T_4 \| _drain_load_T_2; // @[package.scala:16:47, :81:59] wire _drain_load_T_6 = _drain_load_T_5 \| _drain_load_T_3; // @[package.scala:16:47, :81:59] wire _GEN_32 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _drain_load_T_7; // @[package.scala:16:47] assign _drain_load_T_7 = _GEN_32; // @[package.scala:16:47] wire _drain_load_T_30; // @[package.scala:16:47] assign _drain_load_T_30 = _GEN_32; // @[package.scala:16:47] wire _GEN_33 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _drain_load_T_8; // @[package.scala:16:47] assign _drain_load_T_8 = _GEN_33; // @[package.scala:16:47] wire _drain_load_T_31; // @[package.scala:16:47] assign _drain_load_T_31 = _GEN_33; // @[package.scala:16:47] wire _GEN_34 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _drain_load_T_9; // @[package.scala:16:47] assign _drain_load_T_9 = _GEN_34; // @[package.scala:16:47] wire _drain_load_T_32; // @[package.scala:16:47] assign _drain_load_T_32 = _GEN_34; // @[package.scala:16:47] wire _GEN_35 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _drain_load_T_10; // @[package.scala:16:47] assign _drain_load_T_10 = _GEN_35; // @[package.scala:16:47] wire _drain_load_T_33; // @[package.scala:16:47] assign _drain_load_T_33 = _GEN_35; // @[package.scala:16:47] wire _drain_load_T_11 = _drain_load_T_7 \| _drain_load_T_8; // @[package.scala:16:47, :81:59] wire _drain_load_T_12 = _drain_load_T_11 \| _drain_load_T_9; // @[package.scala:16:47, :81:59] wire _drain_load_T_13 = _drain_load_T_12 \| _drain_load_T_10; // @[package.scala:16:47, :81:59] wire _GEN_36 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _drain_load_T_14; // @[package.scala:16:47] assign _drain_load_T_14 = _GEN_36; // @[package.scala:16:47] wire _drain_load_T_37; // @[package.scala:16:47] assign _drain_load_T_37 = _GEN_36; // @[package.scala:16:47] wire _GEN_37 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _drain_load_T_15; // @[package.scala:16:47] assign _drain_load_T_15 = _GEN_37; // @[package.scala:16:47] wire _drain_load_T_38; // @[package.scala:16:47] assign _drain_load_T_38 = _GEN_37; // @[package.scala:16:47] wire _GEN_38 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _drain_load_T_16; // @[package.scala:16:47] assign _drain_load_T_16 = _GEN_38; // @[package.scala:16:47] wire _drain_load_T_39; // @[package.scala:16:47] assign _drain_load_T_39 = _GEN_38; // @[package.scala:16:47] wire _GEN_39 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _drain_load_T_17; // @[package.scala:16:47] assign _drain_load_T_17 = _GEN_39; // @[package.scala:16:47] wire _drain_load_T_40; // @[package.scala:16:47] assign _drain_load_T_40 = _GEN_39; // @[package.scala:16:47] wire _GEN_40 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _drain_load_T_18; // @[package.scala:16:47] assign _drain_load_T_18 = _GEN_40; // @[package.scala:16:47] wire _drain_load_T_41; // @[package.scala:16:47] assign _drain_load_T_41 = _GEN_40; // @[package.scala:16:47] wire _drain_load_T_19 = _drain_load_T_14 \| _drain_load_T_15; // @[package.scala:16:47, :81:59] wire _drain_load_T_20 = _drain_load_T_19 \| _drain_load_T_16; // @[package.scala:16:47, :81:59] wire _drain_load_T_21 = _drain_load_T_20 \| _drain_load_T_17; // @[package.scala:16:47, :81:59] wire _drain_load_T_22 = _drain_load_T_21 \| _drain_load_T_18; // @[package.scala:16:47, :81:59] wire _drain_load_T_23 = _drain_load_T_13 \| _drain_load_T_22; // @[package.scala:81:59] wire _drain_load_T_24 = _drain_load_T_6 \| _drain_load_T_23; // @[package.scala:81:59] wire _drain_load_T_25 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _drain_load_T_26 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _drain_load_T_27 = _drain_load_T_25 \| _drain_load_T_26; // @[Consts.scala:90:{32,42,49}] wire _drain_load_T_29 = _drain_load_T_27 \| _drain_load_T_28; // @[Consts.scala:90:{42,59,66}] wire _drain_load_T_34 = _drain_load_T_30 \| _drain_load_T_31; // @[package.scala:16:47, :81:59] wire _drain_load_T_35 = _drain_load_T_34 \| _drain_load_T_32; // @[package.scala:16:47, :81:59] wire _drain_load_T_36 = _drain_load_T_35 \| _drain_load_T_33; // @[package.scala:16:47, :81:59] wire _drain_load_T_42 = _drain_load_T_37 \| _drain_load_T_38; // @[package.scala:16:47, :81:59] wire _drain_load_T_43 = _drain_load_T_42 \| _drain_load_T_39; // @[package.scala:16:47, :81:59] wire _drain_load_T_44 = _drain_load_T_43 \| _drain_load_T_40; // @[package.scala:16:47, :81:59] wire _drain_load_T_45 = _drain_load_T_44 \| _drain_load_T_41; // @[package.scala:16:47, :81:59] wire _drain_load_T_46 = _drain_load_T_36 \| _drain_load_T_45; // @[package.scala:81:59] wire _drain_load_T_47 = _drain_load_T_29 \| _drain_load_T_46; // @[Consts.scala:87:44, :90:{59,76}] wire _drain_load_T_48 = ~_drain_load_T_47; // @[Consts.scala:90:76] wire _drain_load_T_49 = _drain_load_T_24 & _drain_load_T_48; // @[Consts.scala:89:68] wire _drain_load_T_50 = _rpq_io_deq_bits_uop_mem_cmd != 5'h6; // @[mshrs.scala:128:19, :259:51] wire drain_load = _drain_load_T_49 & _drain_load_T_50; // @[mshrs.scala:257:59, :258:60, :259:51] wire [5:0] _rp_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :261:61] wire [33:0] rp_addr = {rp_addr_hi, _rp_addr_T}; // @[mshrs.scala:261:{22,61}] wire [1:0] size; // @[AMOALU.scala:11:18] wire _rpq_io_deq_ready_T = io_resp_ready_0 & io_lb_read_ready_0; // @[mshrs.scala:36:7, :270:45] wire _rpq_io_deq_ready_T_1 = _rpq_io_deq_ready_T & drain_load; // @[mshrs.scala:258:60, :270:{45,65}] wire _io_lb_read_valid_T = _rpq_io_deq_valid & drain_load; // @[mshrs.scala:128:19, :258:60, :271:48] wire [30:0] _io_lb_read_bits_offset_T = _rpq_io_deq_bits_addr[33:3]; // @[mshrs.scala:128:19, :273:52] wire _GEN_41 = io_lb_read_ready_0 & io_lb_read_valid_0; // @[Decoupled.scala:51:35] wire _io_resp_valid_T; // @[Decoupled.scala:51:35] assign _io_resp_valid_T = _GEN_41; // @[Decoupled.scala:51:35] wire _io_refill_valid_T; // @[Decoupled.scala:51:35] assign _io_refill_valid_T = _GEN_41; // @[Decoupled.scala:51:35] wire _io_resp_valid_T_1 = _rpq_io_deq_valid & _io_resp_valid_T; // @[Decoupled.scala:51:35] wire _io_resp_valid_T_2 = _io_resp_valid_T_1 & drain_load; // @[mshrs.scala:258:60, :275:{43,62}] wire _GEN_42 = ~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3; // @[package.scala:16:47] assign io_resp_valid_0 = ~_GEN_42 & _io_probe_rdy_T_4 & _io_resp_valid_T_2; // @[package.scala:16:47] wire _io_resp_bits_data_shifted_T = _rpq_io_deq_bits_addr[2]; // @[AMOALU.scala:42:29] wire [31:0] _io_resp_bits_data_shifted_T_1 = data_word[63:32]; // @[AMOALU.scala:42:37] wire [31:0] _io_resp_bits_data_T_5 = data_word[63:32]; // @[AMOALU.scala:42:37, :45:94] wire [31:0] _io_resp_bits_data_shifted_T_2 = data_word[31:0]; // @[AMOALU.scala:42:55] wire [31:0] io_resp_bits_data_shifted = _io_resp_bits_data_shifted_T ? _io_resp_bits_data_shifted_T_1 : _io_resp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}] wire [31:0] io_resp_bits_data_zeroed = io_resp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T = size == 2'h2; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_1 = _io_resp_bits_data_T; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_2 = io_resp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_3 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_2; // @[AMOALU.scala:45:{72,81}] wire [31:0] _io_resp_bits_data_T_4 = {32{_io_resp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}] wire [31:0] _io_resp_bits_data_T_6 = _io_resp_bits_data_T_1 ? _io_resp_bits_data_T_4 : _io_resp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_resp_bits_data_T_7 = {_io_resp_bits_data_T_6, io_resp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_resp_bits_data_shifted_T_3 = _rpq_io_deq_bits_addr[1]; // @[AMOALU.scala:42:29] wire [15:0] _io_resp_bits_data_shifted_T_4 = _io_resp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16] wire [15:0] _io_resp_bits_data_shifted_T_5 = _io_resp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16] wire [15:0] io_resp_bits_data_shifted_1 = _io_resp_bits_data_shifted_T_3 ? _io_resp_bits_data_shifted_T_4 : _io_resp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}] wire [15:0] io_resp_bits_data_zeroed_1 = io_resp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T_8 = size == 2'h1; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_9 = _io_resp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_10 = io_resp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_11 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_10; // @[AMOALU.scala:45:{72,81}] wire [47:0] _io_resp_bits_data_T_12 = {48{_io_resp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}] wire [47:0] _io_resp_bits_data_T_13 = _io_resp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}] wire [47:0] _io_resp_bits_data_T_14 = _io_resp_bits_data_T_9 ? _io_resp_bits_data_T_12 : _io_resp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}] wire [63:0] _io_resp_bits_data_T_15 = {_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}] wire _io_resp_bits_data_shifted_T_6 = _rpq_io_deq_bits_addr[0]; // @[AMOALU.scala:42:29] wire [7:0] _io_resp_bits_data_shifted_T_7 = _io_resp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16] wire [7:0] _io_resp_bits_data_shifted_T_8 = _io_resp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16] wire [7:0] io_resp_bits_data_shifted_2 = _io_resp_bits_data_shifted_T_6 ? _io_resp_bits_data_shifted_T_7 : _io_resp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}] wire [7:0] io_resp_bits_data_zeroed_2 = io_resp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23] wire _io_resp_bits_data_T_16 = size == 2'h0; // @[AMOALU.scala:11:18, :45:26] wire _io_resp_bits_data_T_17 = _io_resp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}] wire _io_resp_bits_data_T_18 = io_resp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81] wire _io_resp_bits_data_T_19 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_18; // @[AMOALU.scala:45:{72,81}] wire [55:0] _io_resp_bits_data_T_20 = {56{_io_resp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}] wire [55:0] _io_resp_bits_data_T_21 = _io_resp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}] wire [55:0] _io_resp_bits_data_T_22 = _io_resp_bits_data_T_17 ? _io_resp_bits_data_T_20 : _io_resp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}] assign _io_resp_bits_data_T_23 = {_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}] assign io_resp_bits_data_0 = _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16] wire _T_26 = rpq_io_deq_ready & _rpq_io_deq_valid; // @[Decoupled.scala:51:35] wire _T_28 = _rpq_io_empty & ~commit_line; // @[mshrs.scala:128:19, :140:24, :282:{31,34}] wire _T_33 = _rpq_io_empty \| _rpq_io_deq_valid & ~drain_load; // @[mshrs.scala:128:19, :258:60, :288:{31,52,55}] assign io_commit_val_0 = ~_GEN_42 & _io_probe_rdy_T_4 & ~(_T_26 \| _T_28) & _T_33; // @[Decoupled.scala:51:35] wire _io_meta_read_valid_T = ~io_prober_state_valid_0; // @[mshrs.scala:36:7, :295:27] wire _io_meta_read_valid_T_1 = ~grantack_valid; // @[mshrs.scala:138:21, :295:53] wire _io_meta_read_valid_T_2 = _io_meta_read_valid_T \| _io_meta_read_valid_T_1; // @[mshrs.scala:295:{27,50,53}] wire [3:0] _io_meta_read_valid_T_3 = io_prober_state_bits_0[9:6]; // @[mshrs.scala:36:7, :295:93] wire _io_meta_read_valid_T_4 = _io_meta_read_valid_T_3 != req_idx; // @[mshrs.scala:110:25, :295:{93,120}] wire _io_meta_read_valid_T_5 = _io_meta_read_valid_T_2 \| _io_meta_read_valid_T_4; // @[mshrs.scala:295:{50,69,120}] assign io_meta_read_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4) & _io_probe_rdy_T_8 & _io_meta_read_valid_T_5; // @[package.scala:16:47] assign io_meta_write_bits_data_tag_0 = req_tag[21:0]; // @[mshrs.scala:36:7, :111:26, :297:27] assign io_meta_read_bits_tag_0 = req_tag[21:0]; // @[mshrs.scala:36:7, :111:26, :297:27] wire _T_36 = state == 5'h5; // @[mshrs.scala:107:22, :302:22] wire _T_37 = state == 5'h6; // @[mshrs.scala:107:22, :304:22] wire [3:0] _needs_wb_r_T_6 = {2'h2, io_meta_resp_bits_coh_state_0}; // @[Metadata.scala:120:19] wire _needs_wb_r_T_19 = _needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_21 = _needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_23 = _needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_25 = _needs_wb_r_T_23 ? 3'h2 : _needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_27 = _needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _needs_wb_r_T_29 = _needs_wb_r_T_27 ? 3'h1 : _needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_31 = _needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20] wire _needs_wb_r_T_32 = _needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_33 = _needs_wb_r_T_31 ? 3'h1 : _needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_35 = _needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20] wire _needs_wb_r_T_36 = ~_needs_wb_r_T_35 & _needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_37 = _needs_wb_r_T_35 ? 3'h5 : _needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20] wire _needs_wb_r_T_39 = _needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20] wire _needs_wb_r_T_40 = ~_needs_wb_r_T_39 & _needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_41 = _needs_wb_r_T_39 ? 3'h4 : _needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_42 = {1'h0, _needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_43 = _needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20] wire _needs_wb_r_T_44 = ~_needs_wb_r_T_43 & _needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_45 = _needs_wb_r_T_43 ? 3'h0 : _needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_46 = _needs_wb_r_T_43 ? 2'h1 : _needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_47 = _needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20] wire _needs_wb_r_T_48 = _needs_wb_r_T_47 \| _needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_49 = _needs_wb_r_T_47 ? 3'h0 : _needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_50 = _needs_wb_r_T_47 ? 2'h1 : _needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_51 = _needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20] wire _needs_wb_r_T_52 = ~_needs_wb_r_T_51 & _needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_53 = _needs_wb_r_T_51 ? 3'h5 : _needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_54 = _needs_wb_r_T_51 ? 2'h0 : _needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_55 = _needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20] wire _needs_wb_r_T_56 = ~_needs_wb_r_T_55 & _needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_57 = _needs_wb_r_T_55 ? 3'h4 : _needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_58 = _needs_wb_r_T_55 ? 2'h1 : _needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_59 = _needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20] wire _needs_wb_r_T_60 = ~_needs_wb_r_T_59 & _needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20] wire [2:0] _needs_wb_r_T_61 = _needs_wb_r_T_59 ? 3'h3 : _needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20] wire [1:0] _needs_wb_r_T_62 = _needs_wb_r_T_59 ? 2'h2 : _needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20] wire _needs_wb_r_T_63 = _needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20] wire needs_wb = _needs_wb_r_T_63 \| _needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20] wire [2:0] needs_wb_r_2 = _needs_wb_r_T_63 ? 3'h3 : _needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20] wire [1:0] needs_wb_r_3 = _needs_wb_r_T_63 ? 2'h2 : _needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20] wire [1:0] needs_wb_meta_state = needs_wb_r_3; // @[Misc.scala:38:63] wire _state_T_30 = ~io_meta_resp_valid_0; // @[mshrs.scala:36:7, :306:18] wire [4:0] _state_T_31 = needs_wb ? 5'h7 : 5'hB; // @[Misc.scala:38:9] wire [4:0] _state_T_32 = _state_T_30 ? 5'h4 : _state_T_31; // @[mshrs.scala:306:{17,18}, :307:17] wire _T_38 = state == 5'h7; // @[mshrs.scala:107:22, :308:22] wire _T_40 = state == 5'h9; // @[mshrs.scala:107:22, :318:22] assign io_wb_req_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38) & _T_40; // @[package.scala:16:47] wire _T_42 = state == 5'hA; // @[mshrs.scala:107:22, :330:22] wire _T_43 = state == 5'hB; // @[mshrs.scala:107:22, :334:22] wire _GEN_43 = _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42; // @[mshrs.scala:148:129, :179:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:41] assign io_lb_read_valid_0 = ~_GEN_42 & (_io_probe_rdy_T_4 ? _io_lb_read_valid_T : ~_GEN_43 & _T_43); // @[package.scala:16:47] assign io_lb_read_bits_offset_0 = _io_probe_rdy_T_4 ? _io_lb_read_bits_offset_T[2:0] : refill_ctr; // @[package.scala:16:47] wire _GEN_44 = _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4 \| _GEN_43; // @[package.scala:16:47] assign io_refill_valid_0 = ~(~(\|state) \| _GEN_44) & _T_43 & _io_refill_valid_T; // @[Decoupled.scala:51:35] wire [5:0] _io_refill_bits_addr_T = {refill_ctr, 3'h0}; // @[mshrs.scala:139:24, :340:59] wire [33:0] _io_refill_bits_addr_T_1 = {req_block_addr[33:6], req_block_addr[5:0] \| _io_refill_bits_addr_T}; // @[mshrs.scala:112:51, :340:{45,59}] assign io_refill_bits_addr_0 = _io_refill_bits_addr_T_1[9:0]; // @[mshrs.scala:36:7, :340:{27,45}] wire [3:0] _refill_ctr_T = {1'h0, refill_ctr} + 4'h1; // @[mshrs.scala:139:24, :345:32] wire [2:0] _refill_ctr_T_1 = _refill_ctr_T[2:0]; // @[mshrs.scala:345:32] wire _T_46 = state == 5'hC; // @[mshrs.scala:107:22, :350:22] wire _GEN_45 = _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42 \| _T_43; // @[mshrs.scala:148:129, :164:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:39] wire _GEN_46 = _io_probe_rdy_T_4 \| _GEN_45; // @[package.scala:16:47] assign io_replay_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _GEN_46) & _T_46 & _rpq_io_deq_valid; // @[package.scala:16:47] assign rpq_io_deq_ready = ~_GEN_42 & (_io_probe_rdy_T_4 ? _rpq_io_deq_ready_T_1 : ~_GEN_45 & _T_46 & io_replay_ready_0); // @[package.scala:16:47] wire [5:0] _io_replay_bits_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :353:70] assign _io_replay_bits_addr_T_1 = {io_replay_bits_addr_hi, _io_replay_bits_addr_T}; // @[mshrs.scala:353:{31,70}] assign io_replay_bits_addr_0 = _io_replay_bits_addr_T_1; // @[mshrs.scala:36:7, :353:31] wire _T_48 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32] wire _r_c_cat_T; // @[Consts.scala:90:32] assign _r_c_cat_T = _T_48; // @[Consts.scala:90:32] wire _r_c_cat_T_23; // @[Consts.scala:90:32] assign _r_c_cat_T_23 = _T_48; // @[Consts.scala:90:32] wire _T_49 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49] wire _r_c_cat_T_1; // @[Consts.scala:90:49] assign _r_c_cat_T_1 = _T_49; // @[Consts.scala:90:49] wire _r_c_cat_T_24; // @[Consts.scala:90:49] assign _r_c_cat_T_24 = _T_49; // @[Consts.scala:90:49] wire _T_51 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66] wire _r_c_cat_T_3; // @[Consts.scala:90:66] assign _r_c_cat_T_3 = _T_51; // @[Consts.scala:90:66] wire _r_c_cat_T_26; // @[Consts.scala:90:66] assign _r_c_cat_T_26 = _T_51; // @[Consts.scala:90:66] wire _T_53 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47] wire _r_c_cat_T_5; // @[package.scala:16:47] assign _r_c_cat_T_5 = _T_53; // @[package.scala:16:47] wire _r_c_cat_T_28; // @[package.scala:16:47] assign _r_c_cat_T_28 = _T_53; // @[package.scala:16:47] wire _T_54 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47] wire _r_c_cat_T_6; // @[package.scala:16:47] assign _r_c_cat_T_6 = _T_54; // @[package.scala:16:47] wire _r_c_cat_T_29; // @[package.scala:16:47] assign _r_c_cat_T_29 = _T_54; // @[package.scala:16:47] wire _T_55 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47] wire _r_c_cat_T_7; // @[package.scala:16:47] assign _r_c_cat_T_7 = _T_55; // @[package.scala:16:47] wire _r_c_cat_T_30; // @[package.scala:16:47] assign _r_c_cat_T_30 = _T_55; // @[package.scala:16:47] wire _T_56 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47] wire _r_c_cat_T_8; // @[package.scala:16:47] assign _r_c_cat_T_8 = _T_56; // @[package.scala:16:47] wire _r_c_cat_T_31; // @[package.scala:16:47] assign _r_c_cat_T_31 = _T_56; // @[package.scala:16:47] wire _T_60 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47] wire _r_c_cat_T_12; // @[package.scala:16:47] assign _r_c_cat_T_12 = _T_60; // @[package.scala:16:47] wire _r_c_cat_T_35; // @[package.scala:16:47] assign _r_c_cat_T_35 = _T_60; // @[package.scala:16:47] wire _T_61 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47] wire _r_c_cat_T_13; // @[package.scala:16:47] assign _r_c_cat_T_13 = _T_61; // @[package.scala:16:47] wire _r_c_cat_T_36; // @[package.scala:16:47] assign _r_c_cat_T_36 = _T_61; // @[package.scala:16:47] wire _T_62 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47] wire _r_c_cat_T_14; // @[package.scala:16:47] assign _r_c_cat_T_14 = _T_62; // @[package.scala:16:47] wire _r_c_cat_T_37; // @[package.scala:16:47] assign _r_c_cat_T_37 = _T_62; // @[package.scala:16:47] wire _T_63 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47] wire _r_c_cat_T_15; // @[package.scala:16:47] assign _r_c_cat_T_15 = _T_63; // @[package.scala:16:47] wire _r_c_cat_T_38; // @[package.scala:16:47] assign _r_c_cat_T_38 = _T_63; // @[package.scala:16:47] wire _T_64 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47] wire _r_c_cat_T_16; // @[package.scala:16:47] assign _r_c_cat_T_16 = _T_64; // @[package.scala:16:47] wire _r_c_cat_T_39; // @[package.scala:16:47] assign _r_c_cat_T_39 = _T_64; // @[package.scala:16:47] wire _T_71 = io_replay_ready_0 & io_replay_valid_0 & (_T_48 \| _T_49 \| _T_51 \| _T_53 \| _T_54 \| _T_55 \| _T_56 \| _T_60 \| _T_61 \| _T_62 \| _T_63 \| _T_64); // @[Decoupled.scala:51:35] wire _r_c_cat_T_2 = _r_c_cat_T \| _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_4 = _r_c_cat_T_2 \| _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_9 = _r_c_cat_T_5 \| _r_c_cat_T_6; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_10 = _r_c_cat_T_9 \| _r_c_cat_T_7; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_11 = _r_c_cat_T_10 \| _r_c_cat_T_8; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_17 = _r_c_cat_T_12 \| _r_c_cat_T_13; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_18 = _r_c_cat_T_17 \| _r_c_cat_T_14; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_19 = _r_c_cat_T_18 \| _r_c_cat_T_15; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_20 = _r_c_cat_T_19 \| _r_c_cat_T_16; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_21 = _r_c_cat_T_11 \| _r_c_cat_T_20; // @[package.scala:81:59] wire _r_c_cat_T_22 = _r_c_cat_T_4 \| _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_25 = _r_c_cat_T_23 \| _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_27 = _r_c_cat_T_25 \| _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_32 = _r_c_cat_T_28 \| _r_c_cat_T_29; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_33 = _r_c_cat_T_32 \| _r_c_cat_T_30; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_34 = _r_c_cat_T_33 \| _r_c_cat_T_31; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_40 = _r_c_cat_T_35 \| _r_c_cat_T_36; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_41 = _r_c_cat_T_40 \| _r_c_cat_T_37; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_42 = _r_c_cat_T_41 \| _r_c_cat_T_38; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_43 = _r_c_cat_T_42 \| _r_c_cat_T_39; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_44 = _r_c_cat_T_34 \| _r_c_cat_T_43; // @[package.scala:81:59] wire _r_c_cat_T_45 = _r_c_cat_T_27 \| _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_46 = _rpq_io_deq_bits_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54] wire _r_c_cat_T_47 = _r_c_cat_T_45 \| _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_49 = _r_c_cat_T_47 \| _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18] wire [3:0] _r_T_64 = {r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_89 = _r_T_64 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_91 = {1'h0, _r_T_89}; // @[Misc.scala:35:36, :49:20] wire _r_T_92 = _r_T_64 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_94 = _r_T_92 ? 2'h2 : _r_T_91; // @[Misc.scala:35:36, :49:20] wire _r_T_95 = _r_T_64 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_97 = _r_T_95 ? 2'h1 : _r_T_94; // @[Misc.scala:35:36, :49:20] wire _r_T_98 = _r_T_64 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_100 = _r_T_98 ? 2'h2 : _r_T_97; // @[Misc.scala:35:36, :49:20] wire _r_T_101 = _r_T_64 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_103 = _r_T_101 ? 2'h0 : _r_T_100; // @[Misc.scala:35:36, :49:20] wire _r_T_104 = _r_T_64 == 4'hE; // @[Misc.scala:49:20] wire _r_T_105 = _r_T_104; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_106 = _r_T_104 ? 2'h3 : _r_T_103; // @[Misc.scala:35:36, :49:20] wire _r_T_107 = &_r_T_64; // @[Misc.scala:49:20] wire _r_T_108 = _r_T_107 \| _r_T_105; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_109 = _r_T_107 ? 2'h3 : _r_T_106; // @[Misc.scala:35:36, :49:20] wire _r_T_110 = _r_T_64 == 4'h6; // @[Misc.scala:49:20] wire _r_T_111 = _r_T_110 \| _r_T_108; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_112 = _r_T_110 ? 2'h2 : _r_T_109; // @[Misc.scala:35:36, :49:20] wire _r_T_113 = _r_T_64 == 4'h7; // @[Misc.scala:49:20] wire _r_T_114 = _r_T_113 \| _r_T_111; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_115 = _r_T_113 ? 2'h3 : _r_T_112; // @[Misc.scala:35:36, :49:20] wire _r_T_116 = _r_T_64 == 4'h1; // @[Misc.scala:49:20] wire _r_T_117 = _r_T_116 \| _r_T_114; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_118 = _r_T_116 ? 2'h1 : _r_T_115; // @[Misc.scala:35:36, :49:20] wire _r_T_119 = _r_T_64 == 4'h2; // @[Misc.scala:49:20] wire _r_T_120 = _r_T_119 \| _r_T_117; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_121 = _r_T_119 ? 2'h2 : _r_T_118; // @[Misc.scala:35:36, :49:20] wire _r_T_122 = _r_T_64 == 4'h3; // @[Misc.scala:49:20] wire is_hit = _r_T_122 \| _r_T_120; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_1 = _r_T_122 ? 2'h3 : _r_T_121; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_state = r_2_1; // @[Misc.scala:35:36] wire _GEN_47 = _T_40 \| _T_42 \| _T_43 \| _T_46; // @[mshrs.scala:156:26, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:{22,39}, :363:44] assign io_meta_write_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37) & (_T_38 \| ~_GEN_47 & _sec_rdy_T_4); // @[package.scala:16:47] assign io_meta_write_bits_data_coh_state_0 = _T_38 ? coh_on_clear_state : new_coh_state; // @[Metadata.scala:160:20] wire _GEN_48 = _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42 \| _T_43 \| _T_46 \| _sec_rdy_T_4; // @[package.scala:16:47] assign io_mem_finish_valid_0 = ~(~(\|state) \| _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _GEN_48) & _sec_rdy_T_5 & grantack_valid; // @[package.scala:16:47] wire [4:0] _state_T_33 = finish_to_prefetch ? 5'h11 : 5'h0; // @[mshrs.scala:142:31, :381:17] wire _GEN_49 = _sec_rdy_T_4 \| _sec_rdy_T_5 \| _sec_rdy_T_6; // @[package.scala:16:47] wire _GEN_50 = _T_46 \| _GEN_49; // @[mshrs.scala:158:26, :350:{22,39}, :363:44, :373:42, :380:42, :382:38] wire _GEN_51 = _io_probe_rdy_T_4 \| _io_probe_rdy_T_8 \| _T_36 \| _T_37 \| _T_38 \| _T_40 \| _T_42 \| _T_43 \| _GEN_50; // @[package.scala:16:47] wire _GEN_52 = _io_probe_rdy_T_2 \| _io_probe_rdy_T_3 \| _GEN_51; // @[package.scala:16:47] assign io_req_pri_rdy_0 = ~(\|state) \| ~_GEN_52 & _io_way_valid_T_1; // @[package.scala:16:47] wire _T_87 = io_req_sec_val_0 & ~io_req_sec_rdy_0 \| io_clear_prefetch_0; // @[mshrs.scala:36:7, :384:{27,30,47}] wire _r_c_cat_T_52 = _r_c_cat_T_50 \| _r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_54 = _r_c_cat_T_52 \| _r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_59 = _r_c_cat_T_55 \| _r_c_cat_T_56; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_60 = _r_c_cat_T_59 \| _r_c_cat_T_57; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_61 = _r_c_cat_T_60 \| _r_c_cat_T_58; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_67 = _r_c_cat_T_62 \| _r_c_cat_T_63; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_68 = _r_c_cat_T_67 \| _r_c_cat_T_64; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_69 = _r_c_cat_T_68 \| _r_c_cat_T_65; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_70 = _r_c_cat_T_69 \| _r_c_cat_T_66; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_71 = _r_c_cat_T_61 \| _r_c_cat_T_70; // @[package.scala:81:59] wire _r_c_cat_T_72 = _r_c_cat_T_54 \| _r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_75 = _r_c_cat_T_73 \| _r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}] wire _r_c_cat_T_77 = _r_c_cat_T_75 \| _r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}] wire _r_c_cat_T_82 = _r_c_cat_T_78 \| _r_c_cat_T_79; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_83 = _r_c_cat_T_82 \| _r_c_cat_T_80; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_84 = _r_c_cat_T_83 \| _r_c_cat_T_81; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_90 = _r_c_cat_T_85 \| _r_c_cat_T_86; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_91 = _r_c_cat_T_90 \| _r_c_cat_T_87; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_92 = _r_c_cat_T_91 \| _r_c_cat_T_88; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_93 = _r_c_cat_T_92 \| _r_c_cat_T_89; // @[package.scala:16:47, :81:59] wire _r_c_cat_T_94 = _r_c_cat_T_84 \| _r_c_cat_T_93; // @[package.scala:81:59] wire _r_c_cat_T_95 = _r_c_cat_T_77 \| _r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}] wire _r_c_cat_T_97 = _r_c_cat_T_95 \| _r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}] wire _r_c_cat_T_99 = _r_c_cat_T_97 \| _r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}] wire [1:0] r_c_1 = {_r_c_cat_T_72, _r_c_cat_T_99}; // @[Metadata.scala:29:18] wire [3:0] _r_T_123 = {r_c_1, new_coh_state}; // @[Metadata.scala:29:18, :58:19] wire _r_T_148 = _r_T_123 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _r_T_150 = {1'h0, _r_T_148}; // @[Misc.scala:35:36, :49:20] wire _r_T_151 = _r_T_123 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _r_T_153 = _r_T_151 ? 2'h2 : _r_T_150; // @[Misc.scala:35:36, :49:20] wire _r_T_154 = _r_T_123 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _r_T_156 = _r_T_154 ? 2'h1 : _r_T_153; // @[Misc.scala:35:36, :49:20] wire _r_T_157 = _r_T_123 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _r_T_159 = _r_T_157 ? 2'h2 : _r_T_156; // @[Misc.scala:35:36, :49:20] wire _r_T_160 = _r_T_123 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _r_T_162 = _r_T_160 ? 2'h0 : _r_T_159; // @[Misc.scala:35:36, :49:20] wire _r_T_163 = _r_T_123 == 4'hE; // @[Misc.scala:49:20] wire _r_T_164 = _r_T_163; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_165 = _r_T_163 ? 2'h3 : _r_T_162; // @[Misc.scala:35:36, :49:20] wire _r_T_166 = &_r_T_123; // @[Misc.scala:49:20] wire _r_T_167 = _r_T_166 \| _r_T_164; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_168 = _r_T_166 ? 2'h3 : _r_T_165; // @[Misc.scala:35:36, :49:20] wire _r_T_169 = _r_T_123 == 4'h6; // @[Misc.scala:49:20] wire _r_T_170 = _r_T_169 \| _r_T_167; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_171 = _r_T_169 ? 2'h2 : _r_T_168; // @[Misc.scala:35:36, :49:20] wire _r_T_172 = _r_T_123 == 4'h7; // @[Misc.scala:49:20] wire _r_T_173 = _r_T_172 \| _r_T_170; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_174 = _r_T_172 ? 2'h3 : _r_T_171; // @[Misc.scala:35:36, :49:20] wire _r_T_175 = _r_T_123 == 4'h1; // @[Misc.scala:49:20] wire _r_T_176 = _r_T_175 \| _r_T_173; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_177 = _r_T_175 ? 2'h1 : _r_T_174; // @[Misc.scala:35:36, :49:20] wire _r_T_178 = _r_T_123 == 4'h2; // @[Misc.scala:49:20] wire _r_T_179 = _r_T_178 \| _r_T_176; // @[Misc.scala:35:9, :49:20] wire [1:0] _r_T_180 = _r_T_178 ? 2'h2 : _r_T_177; // @[Misc.scala:35:36, :49:20] wire _r_T_181 = _r_T_123 == 4'h3; // @[Misc.scala:49:20] wire is_hit_1 = _r_T_181 \| _r_T_179; // @[Misc.scala:35:9, :49:20] wire [1:0] r_2_2 = _r_T_181 ? 2'h3 : _r_T_180; // @[Misc.scala:35:36, :49:20] wire [1:0] coh_on_hit_1_state = r_2_2; // @[Misc.scala:35:36] wire [4:0] state_new_state_1; // @[mshrs.scala:191:29] wire _state_T_35 = ~_state_T_34; // @[mshrs.scala:194:11] wire _state_T_36 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11] wire _state_req_needs_wb_r_T_83 = _state_req_needs_wb_r_T_70 == 4'h8; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_85 = _state_req_needs_wb_r_T_83 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_87 = _state_req_needs_wb_r_T_70 == 4'h9; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_89 = _state_req_needs_wb_r_T_87 ? 3'h2 : _state_req_needs_wb_r_T_85; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_91 = _state_req_needs_wb_r_T_70 == 4'hA; // @[Misc.scala:56:20] wire [2:0] _state_req_needs_wb_r_T_93 = _state_req_needs_wb_r_T_91 ? 3'h1 : _state_req_needs_wb_r_T_89; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_95 = _state_req_needs_wb_r_T_70 == 4'hB; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_96 = _state_req_needs_wb_r_T_95; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_97 = _state_req_needs_wb_r_T_95 ? 3'h1 : _state_req_needs_wb_r_T_93; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_99 = _state_req_needs_wb_r_T_70 == 4'h4; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_100 = ~_state_req_needs_wb_r_T_99 & _state_req_needs_wb_r_T_96; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_101 = _state_req_needs_wb_r_T_99 ? 3'h5 : _state_req_needs_wb_r_T_97; // @[Misc.scala:38:36, :56:20] wire _state_req_needs_wb_r_T_103 = _state_req_needs_wb_r_T_70 == 4'h5; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_104 = ~_state_req_needs_wb_r_T_103 & _state_req_needs_wb_r_T_100; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_105 = _state_req_needs_wb_r_T_103 ? 3'h4 : _state_req_needs_wb_r_T_101; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_106 = {1'h0, _state_req_needs_wb_r_T_103}; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_107 = _state_req_needs_wb_r_T_70 == 4'h6; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_108 = ~_state_req_needs_wb_r_T_107 & _state_req_needs_wb_r_T_104; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_109 = _state_req_needs_wb_r_T_107 ? 3'h0 : _state_req_needs_wb_r_T_105; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_110 = _state_req_needs_wb_r_T_107 ? 2'h1 : _state_req_needs_wb_r_T_106; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_111 = _state_req_needs_wb_r_T_70 == 4'h7; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_112 = _state_req_needs_wb_r_T_111 \| _state_req_needs_wb_r_T_108; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_113 = _state_req_needs_wb_r_T_111 ? 3'h0 : _state_req_needs_wb_r_T_109; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_114 = _state_req_needs_wb_r_T_111 ? 2'h1 : _state_req_needs_wb_r_T_110; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_115 = _state_req_needs_wb_r_T_70 == 4'h0; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_116 = ~_state_req_needs_wb_r_T_115 & _state_req_needs_wb_r_T_112; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_117 = _state_req_needs_wb_r_T_115 ? 3'h5 : _state_req_needs_wb_r_T_113; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_118 = _state_req_needs_wb_r_T_115 ? 2'h0 : _state_req_needs_wb_r_T_114; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_119 = _state_req_needs_wb_r_T_70 == 4'h1; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_120 = ~_state_req_needs_wb_r_T_119 & _state_req_needs_wb_r_T_116; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_121 = _state_req_needs_wb_r_T_119 ? 3'h4 : _state_req_needs_wb_r_T_117; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_122 = _state_req_needs_wb_r_T_119 ? 2'h1 : _state_req_needs_wb_r_T_118; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_123 = _state_req_needs_wb_r_T_70 == 4'h2; // @[Misc.scala:56:20] wire _state_req_needs_wb_r_T_124 = ~_state_req_needs_wb_r_T_123 & _state_req_needs_wb_r_T_120; // @[Misc.scala:38:9, :56:20] wire [2:0] _state_req_needs_wb_r_T_125 = _state_req_needs_wb_r_T_123 ? 3'h3 : _state_req_needs_wb_r_T_121; // @[Misc.scala:38:36, :56:20] wire [1:0] _state_req_needs_wb_r_T_126 = _state_req_needs_wb_r_T_123 ? 2'h2 : _state_req_needs_wb_r_T_122; // @[Misc.scala:38:63, :56:20] wire _state_req_needs_wb_r_T_127 = _state_req_needs_wb_r_T_70 == 4'h3; // @[Misc.scala:56:20] wire state_req_needs_wb_r_1_1 = _state_req_needs_wb_r_T_127 \| _state_req_needs_wb_r_T_124; // @[Misc.scala:38:9, :56:20] wire [2:0] state_req_needs_wb_r_2_1 = _state_req_needs_wb_r_T_127 ? 3'h3 : _state_req_needs_wb_r_T_125; // @[Misc.scala:38:36, :56:20] wire [1:0] state_req_needs_wb_r_3_1 = _state_req_needs_wb_r_T_127 ? 2'h2 : _state_req_needs_wb_r_T_126; // @[Misc.scala:38:63, :56:20] wire [1:0] state_req_needs_wb_meta_1_state = state_req_needs_wb_r_3_1; // @[Misc.scala:38:63] wire _state_r_c_cat_T_52 = _state_r_c_cat_T_50 \| _state_r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_54 = _state_r_c_cat_T_52 \| _state_r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_59 = _state_r_c_cat_T_55 \| _state_r_c_cat_T_56; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_60 = _state_r_c_cat_T_59 \| _state_r_c_cat_T_57; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_61 = _state_r_c_cat_T_60 \| _state_r_c_cat_T_58; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_67 = _state_r_c_cat_T_62 \| _state_r_c_cat_T_63; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_68 = _state_r_c_cat_T_67 \| _state_r_c_cat_T_64; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_69 = _state_r_c_cat_T_68 \| _state_r_c_cat_T_65; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_70 = _state_r_c_cat_T_69 \| _state_r_c_cat_T_66; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_71 = _state_r_c_cat_T_61 \| _state_r_c_cat_T_70; // @[package.scala:81:59] wire _state_r_c_cat_T_72 = _state_r_c_cat_T_54 \| _state_r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_75 = _state_r_c_cat_T_73 \| _state_r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}] wire _state_r_c_cat_T_77 = _state_r_c_cat_T_75 \| _state_r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}] wire _state_r_c_cat_T_82 = _state_r_c_cat_T_78 \| _state_r_c_cat_T_79; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_83 = _state_r_c_cat_T_82 \| _state_r_c_cat_T_80; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_84 = _state_r_c_cat_T_83 \| _state_r_c_cat_T_81; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_90 = _state_r_c_cat_T_85 \| _state_r_c_cat_T_86; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_91 = _state_r_c_cat_T_90 \| _state_r_c_cat_T_87; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_92 = _state_r_c_cat_T_91 \| _state_r_c_cat_T_88; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_93 = _state_r_c_cat_T_92 \| _state_r_c_cat_T_89; // @[package.scala:16:47, :81:59] wire _state_r_c_cat_T_94 = _state_r_c_cat_T_84 \| _state_r_c_cat_T_93; // @[package.scala:81:59] wire _state_r_c_cat_T_95 = _state_r_c_cat_T_77 \| _state_r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}] wire _state_r_c_cat_T_97 = _state_r_c_cat_T_95 \| _state_r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}] wire _state_r_c_cat_T_99 = _state_r_c_cat_T_97 \| _state_r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}] wire [1:0] state_r_c_1 = {_state_r_c_cat_T_72, _state_r_c_cat_T_99}; // @[Metadata.scala:29:18] wire [3:0] _state_r_T_59 = {state_r_c_1, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19] wire _state_r_T_84 = _state_r_T_59 == 4'hC; // @[Misc.scala:49:20] wire [1:0] _state_r_T_86 = {1'h0, _state_r_T_84}; // @[Misc.scala:35:36, :49:20] wire _state_r_T_87 = _state_r_T_59 == 4'hD; // @[Misc.scala:49:20] wire [1:0] _state_r_T_89 = _state_r_T_87 ? 2'h2 : _state_r_T_86; // @[Misc.scala:35:36, :49:20] wire _state_r_T_90 = _state_r_T_59 == 4'h4; // @[Misc.scala:49:20] wire [1:0] _state_r_T_92 = _state_r_T_90 ? 2'h1 : _state_r_T_89; // @[Misc.scala:35:36, :49:20] wire _state_r_T_93 = _state_r_T_59 == 4'h5; // @[Misc.scala:49:20] wire [1:0] _state_r_T_95 = _state_r_T_93 ? 2'h2 : _state_r_T_92; // @[Misc.scala:35:36, :49:20] wire _state_r_T_96 = _state_r_T_59 == 4'h0; // @[Misc.scala:49:20] wire [1:0] _state_r_T_98 = _state_r_T_96 ? 2'h0 : _state_r_T_95; // @[Misc.scala:35:36, :49:20] wire _state_r_T_99 = _state_r_T_59 == 4'hE; // @[Misc.scala:49:20] wire _state_r_T_100 = _state_r_T_99; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_101 = _state_r_T_99 ? 2'h3 : _state_r_T_98; // @[Misc.scala:35:36, :49:20] wire _state_r_T_102 = &_state_r_T_59; // @[Misc.scala:49:20] wire _state_r_T_103 = _state_r_T_102 \| _state_r_T_100; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_104 = _state_r_T_102 ? 2'h3 : _state_r_T_101; // @[Misc.scala:35:36, :49:20] wire _state_r_T_105 = _state_r_T_59 == 4'h6; // @[Misc.scala:49:20] wire _state_r_T_106 = _state_r_T_105 \| _state_r_T_103; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_107 = _state_r_T_105 ? 2'h2 : _state_r_T_104; // @[Misc.scala:35:36, :49:20] wire _state_r_T_108 = _state_r_T_59 == 4'h7; // @[Misc.scala:49:20] wire _state_r_T_109 = _state_r_T_108 \| _state_r_T_106; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_110 = _state_r_T_108 ? 2'h3 : _state_r_T_107; // @[Misc.scala:35:36, :49:20] wire _state_r_T_111 = _state_r_T_59 == 4'h1; // @[Misc.scala:49:20] wire _state_r_T_112 = _state_r_T_111 \| _state_r_T_109; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_113 = _state_r_T_111 ? 2'h1 : _state_r_T_110; // @[Misc.scala:35:36, :49:20] wire _state_r_T_114 = _state_r_T_59 == 4'h2; // @[Misc.scala:49:20] wire _state_r_T_115 = _state_r_T_114 \| _state_r_T_112; // @[Misc.scala:35:9, :49:20] wire [1:0] _state_r_T_116 = _state_r_T_114 ? 2'h2 : _state_r_T_113; // @[Misc.scala:35:36, :49:20] wire _state_r_T_117 = _state_r_T_59 == 4'h3; // @[Misc.scala:49:20] wire state_is_hit_1 = _state_r_T_117 \| _state_r_T_115; // @[Misc.scala:35:9, :49:20] wire [1:0] state_r_2_1 = _state_r_T_117 ? 2'h3 : _state_r_T_116; // @[Misc.scala:35:36, :49:20] wire [1:0] state_coh_on_hit_1_state = state_r_2_1; // @[Misc.scala:35:36] wire _state_T_39 = _state_T_37 \| _state_T_38; // @[Consts.scala:90:{32,42,49}] wire _state_T_41 = _state_T_39 \| _state_T_40; // @[Consts.scala:90:{42,59,66}] wire _state_T_46 = _state_T_42 \| _state_T_43; // @[package.scala:16:47, :81:59] wire _state_T_47 = _state_T_46 \| _state_T_44; // @[package.scala:16:47, :81:59] wire _state_T_48 = _state_T_47 \| _state_T_45; // @[package.scala:16:47, :81:59] wire _state_T_54 = _state_T_49 \| _state_T_50; // @[package.scala:16:47, :81:59] wire _state_T_55 = _state_T_54 \| _state_T_51; // @[package.scala:16:47, :81:59] wire _state_T_56 = _state_T_55 \| _state_T_52; // @[package.scala:16:47, :81:59] wire _state_T_57 = _state_T_56 \| _state_T_53; // @[package.scala:16:47, :81:59] wire _state_T_58 = _state_T_48 \| _state_T_57; // @[package.scala:81:59] wire _state_T_59 = _state_T_41 \| _state_T_58; // @[Consts.scala:87:44, :90:{59,76}] wire _state_T_61 = ~_state_T_60; // @[mshrs.scala:201:15] wire _state_T_62 = ~_state_T_59; // @[Consts.scala:90:76]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File Bundles.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import freechips.rocketchip.util._ import scala.collection.immutable.ListMap import chisel3.util.Decoupled import chisel3.util.DecoupledIO import chisel3.reflect.DataMirror abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle // common combos in lazy policy: // Put + Acquire // Release + AccessAck object TLMessages { // A B C D E def PutFullData = 0.U // . . => AccessAck def PutPartialData = 1.U // . . => AccessAck def ArithmeticData = 2.U // . . => AccessAckData def LogicalData = 3.U // . . => AccessAckData def Get = 4.U // . . => AccessAckData def Hint = 5.U // . . => HintAck def AcquireBlock = 6.U // . => Grant[Data] def AcquirePerm = 7.U // . => Grant[Data] def Probe = 6.U // . => ProbeAck[Data] def AccessAck = 0.U // . . def AccessAckData = 1.U // . . def HintAck = 2.U // . . def ProbeAck = 4.U // . def ProbeAckData = 5.U // . def Release = 6.U // . => ReleaseAck def ReleaseData = 7.U // . => ReleaseAck def Grant = 4.U // . => GrantAck def GrantData = 5.U // . => GrantAck def ReleaseAck = 6.U // . def GrantAck = 0.U // . def isA(x: UInt) = x <= AcquirePerm def isB(x: UInt) = x <= Probe def isC(x: UInt) = x <= ReleaseData def isD(x: UInt) = x <= ReleaseAck def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant) def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck) def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("AcquireBlock",TLPermissions.PermMsgGrow), ("AcquirePerm",TLPermissions.PermMsgGrow)) def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved), ("PutPartialData",TLPermissions.PermMsgReserved), ("ArithmeticData",TLAtomics.ArithMsg), ("LogicalData",TLAtomics.LogicMsg), ("Get",TLPermissions.PermMsgReserved), ("Hint",TLHints.HintsMsg), ("Probe",TLPermissions.PermMsgCap)) def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("ProbeAck",TLPermissions.PermMsgReport), ("ProbeAckData",TLPermissions.PermMsgReport), ("Release",TLPermissions.PermMsgReport), ("ReleaseData",TLPermissions.PermMsgReport)) def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved), ("AccessAckData",TLPermissions.PermMsgReserved), ("HintAck",TLPermissions.PermMsgReserved), ("Invalid Opcode",TLPermissions.PermMsgReserved), ("Grant",TLPermissions.PermMsgCap), ("GrantData",TLPermissions.PermMsgCap), ("ReleaseAck",TLPermissions.PermMsgReserved)) } /* * The three primary TileLink permissions are: * (T)runk: the agent is (or is on inwards path to) the global point of serialization. * (B)ranch: the agent is on an outwards path to * (N)one: * These permissions are permuted by transfer operations in various ways. * Operations can cap permissions, request for them to be grown or shrunk, * or for a report on their current status. / object TLPermissions { val aWidth = 2 val bdWidth = 2 val cWidth = 3 // Cap types (Grant = new permissions, Probe = permisions <= target) def toT = 0.U(bdWidth.W) def toB = 1.U(bdWidth.W) def toN = 2.U(bdWidth.W) def isCap(x: UInt) = x <= toN // Grow types (Acquire = permissions >= target) def NtoB = 0.U(aWidth.W) def NtoT = 1.U(aWidth.W) def BtoT = 2.U(aWidth.W) def isGrow(x: UInt) = x <= BtoT // Shrink types (ProbeAck, Release) def TtoB = 0.U(cWidth.W) def TtoN = 1.U(cWidth.W) def BtoN = 2.U(cWidth.W) def isShrink(x: UInt) = x <= BtoN // Report types (ProbeAck, Release) def TtoT = 3.U(cWidth.W) def BtoB = 4.U(cWidth.W) def NtoN = 5.U(cWidth.W) def isReport(x: UInt) = x <= NtoN def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT") def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN") def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN") def PermMsgReserved:Seq[String] = Seq("Reserved") } object TLAtomics { val width = 3 // Arithmetic types def MIN = 0.U(width.W) def MAX = 1.U(width.W) def MINU = 2.U(width.W) def MAXU = 3.U(width.W) def ADD = 4.U(width.W) def isArithmetic(x: UInt) = x <= ADD // Logical types def XOR = 0.U(width.W) def OR = 1.U(width.W) def AND = 2.U(width.W) def SWAP = 3.U(width.W) def isLogical(x: UInt) = x <= SWAP def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD") def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP") } object TLHints { val width = 1 def PREFETCH_READ = 0.U(width.W) def PREFETCH_WRITE = 1.U(width.W) def isHints(x: UInt) = x <= PREFETCH_WRITE def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite") } sealed trait TLChannel extends TLBundleBase { val channelName: String } sealed trait TLDataChannel extends TLChannel sealed trait TLAddrChannel extends TLDataChannel final class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleA_${params.shortName}" val channelName = "'A' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode \|\| grow perms \|\| hint val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleB_${params.shortName}" val channelName = "'B' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val address = UInt(params.addressBits.W) // from // variable fields during multibeat: val mask = UInt((params.dataBits/8).W) val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params) with TLAddrChannel { override def typeName = s"TLBundleC_${params.shortName}" val channelName = "'C' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.cWidth.W) // shrink or report perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // from val address = UInt(params.addressBits.W) // to val user = BundleMap(params.requestFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params) with TLDataChannel { override def typeName = s"TLBundleD_${params.shortName}" val channelName = "'D' channel" // fixed fields during multibeat: val opcode = UInt(3.W) val param = UInt(TLPermissions.bdWidth.W) // cap perms val size = UInt(params.sizeBits.W) val source = UInt(params.sourceBits.W) // to val sink = UInt(params.sinkBits.W) // from val denied = Bool() // implies corrupt iff Data val user = BundleMap(params.responseFields) val echo = BundleMap(params.echoFields) // variable fields during multibeat: val data = UInt(params.dataBits.W) val corrupt = Bool() // only applies to Data messages } final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { override def typeName = s"TLBundleE_${params.shortName}" val channelName = "'E' channel" val sink = UInt(params.sinkBits.W) // to } class TLBundle(val params: TLBundleParameters) extends Record { // Emulate a Bundle with elements abcde or ad depending on params.hasBCE private val optA = Some (Decoupled(new TLBundleA(params))) private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params)))) private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params))) private val optD = Some (Flipped(Decoupled(new TLBundleD(params)))) private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params))) def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params))))) def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params))))) def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params))))) def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params))))) def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params))))) val elements = if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a) else ListMap("d" -> d, "a" -> a) def tieoff(): Unit = { DataMirror.specifiedDirectionOf(a.ready) match { case SpecifiedDirection.Input => a.ready := false.B c.ready := false.B e.ready := false.B b.valid := false.B d.valid := false.B case SpecifiedDirection.Output => a.valid := false.B c.valid := false.B e.valid := false.B b.ready := false.B d.ready := false.B case _ => } } } object TLBundle { def apply(params: TLBundleParameters) = new TLBundle(params) } class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params) { val a = new AsyncBundle(new TLBundleA(params.base), params.async) val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async)) val c = new AsyncBundle(new TLBundleC(params.base), params.async) val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async)) val e = new AsyncBundle(new TLBundleE(params.base), params.async) } class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = RationalIO(new TLBundleA(params)) val b = Flipped(RationalIO(new TLBundleB(params))) val c = RationalIO(new TLBundleC(params)) val d = Flipped(RationalIO(new TLBundleD(params))) val e = RationalIO(new TLBundleE(params)) } class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params) { val a = CreditedIO(new TLBundleA(params)) val b = Flipped(CreditedIO(new TLBundleB(params))) val c = CreditedIO(new TLBundleC(params)) val d = Flipped(CreditedIO(new TLBundleD(params))) val e = CreditedIO(new TLBundleE(params)) } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File MixedNode.scala: package org.chipsalliance.diplomacy.nodes import chisel3.{Data, DontCare, Wire} import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.{Field, Parameters} import org.chipsalliance.diplomacy.ValName import org.chipsalliance.diplomacy.sourceLine /* One side metadata of a [[Dangle]]. * * Describes one side of an edge going into or out of a [[BaseNode]]. * * @param serial * the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to. * @param index * the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to. / case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] { import scala.math.Ordered.orderingToOrdered def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that)) } /* [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]] * connects. * * [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] , * [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]]. * * @param source * the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within * that [[BaseNode]]. * @param sink * sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that * [[BaseNode]]. * @param flipped * flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to * `danglesIn`. * @param dataOpt * actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module / case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) { def data = dataOpt.get } /* [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often * derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually * implement the protocol. / case class Edges[EI, EO](in: Seq[EI], out: Seq[EO]) /* A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. / case object MonitorsEnabled extends Field[Boolean](true) /* When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented. * * For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but * [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink * nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the * [[LazyModule]]. / case object RenderFlipped extends Field[Boolean](false) /* The sealed node class in the package, all node are derived from it. * * @param inner * Sink interface implementation. * @param outer * Source interface implementation. * @param valName * val name of this node. * @tparam DI * Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters * describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected * [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port * parameters. * @tparam UI * Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing * the protocol parameters of a sink. For an [[InwardNode]], it is determined itself. * @tparam EI * Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers * specified for a sink according to protocol. * @tparam BI * Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface. * It should extends from [[chisel3.Data]], which represents the real hardware. * @tparam DO * Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters * describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself. * @tparam UO * Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing * the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]]. * Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters. * @tparam EO * Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers * specified for a source according to protocol. * @tparam BO * Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source * interface. It should extends from [[chisel3.Data]], which represents the real hardware. * * @note * Call Graph of [[MixedNode]] * - line `─`: source is process by a function and generate pass to others * - Arrow `→`: target of arrow is generated by source * * {{{ * (from the other node) * ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐ * ↓ │ * (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │ * [[InwardNode.accPI]] │ │ │ * │ │ (based on protocol) │ * │ │ [[MixedNode.inner.edgeI]] │ * │ │ ↓ │ * ↓ │ │ │ * (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │ * [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │ * │ │ ↑ │ │ │ * │ │ │ [[OutwardNode.doParams]] │ │ * │ │ │ (from the other node) │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * │ │ │ └────────┬──────────────┤ │ * │ │ │ │ │ │ * │ │ │ │ (based on protocol) │ * │ │ │ │ [[MixedNode.inner.edgeI]] │ * │ │ │ │ │ │ * │ │ (from the other node) │ ↓ │ * │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │ * │ ↑ ↑ │ │ ↓ │ * │ │ │ │ │ [[MixedNode.in]] │ * │ │ │ │ ↓ ↑ │ * │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │ * ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │ * │ │ │ [[MixedNode.bundleOut]]─┐ │ │ * │ │ │ ↑ ↓ │ │ * │ │ │ │ [[MixedNode.out]] │ │ * │ ↓ ↓ │ ↑ │ │ * │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │ * │ │ (from the other node) ↑ │ │ * │ │ │ │ │ │ * │ │ │ [[MixedNode.outer.edgeO]] │ │ * │ │ │ (based on protocol) │ │ * │ │ │ │ │ │ * │ │ │ ┌────────────────────────────────────────┤ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * │ │ │ │ │ │ │ * (immobilize after elaboration)│ ↓ │ │ │ │ * [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │ * ↑ (inward port from [[OutwardNode]]) │ │ │ │ * │ ┌─────────────────────────────────────────┤ │ │ │ * │ │ │ │ │ │ * │ │ │ │ │ │ * [[OutwardNode.accPO]] │ ↓ │ │ │ * (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │ * │ ↑ │ │ * │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │ * └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘ * }}} / abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data]( val inner: InwardNodeImp[DI, UI, EI, BI], val outer: OutwardNodeImp[DO, UO, EO, BO] )( implicit valName: ValName) extends BaseNode with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO] with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO] { // Generate a [[NodeHandle]] with inward and outward node are both this node. val inward = this val outward = this /* Debug info of nodes binding. / def bindingInfo: String = s"""$iBindingInfo \|$oBindingInfo \|""".stripMargin /* Debug info of ports connecting. / def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}] \|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}] \|""".stripMargin /* Debug info of parameters propagations. / def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}] \|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}] \|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}] \|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}] \|""".stripMargin /* For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and * [[MixedNode.iPortMapping]]. * * Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward * stars and outward stars. * * This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type * of node. * * @param iKnown * Number of known-size ([[BIND_ONCE]]) input bindings. * @param oKnown * Number of known-size ([[BIND_ONCE]]) output bindings. * @param iStar * Number of unknown size ([[BIND_STAR]]) input bindings. * @param oStar * Number of unknown size ([[BIND_STAR]]) output bindings. * @return * A Tuple of the resolved number of input and output connections. / protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int) /* Function to generate downward-flowing outward params from the downward-flowing input params and the current output * ports. * * @param n * The size of the output sequence to generate. * @param p * Sequence of downward-flowing input parameters of this node. * @return * A `n`-sized sequence of downward-flowing output edge parameters. / protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO] /* Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]]. * * @param n * Size of the output sequence. * @param p * Upward-flowing output edge parameters. * @return * A n-sized sequence of upward-flowing input edge parameters. / protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI] /* @return * The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with * [[BIND_STAR]]. / protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR) /* @return * The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of * output bindings bound with [[BIND_STAR]]. / protected[diplomacy] lazy val sourceCard: Int = iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR) /* @return list of nodes involved in flex bindings with this node. / protected[diplomacy] lazy val flexes: Seq[BaseNode] = oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2) /* Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin * greedily taking up the remaining connections. * * @return * A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return * value is not relevant. / protected[diplomacy] lazy val flexOffset: Int = { /* Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex * operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a * connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of * each node in the current set and decide whether they should be added to the set or not. * * @return * the mapping of [[BaseNode]] indexed by their serial numbers. / def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = { if (visited.contains(v.serial) \|\| !v.flexibleArityDirection) { visited } else { v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum)) } } /* Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node. * * @example * {{{ * a := b := c * d := b * e := f * }}} * * `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)` / val flexSet = DFS(this, Map()).values /* The total number of := operators where we're on the left. / val allSink = flexSet.map(_.sinkCard).sum /** The total number of :=* operators used when we're on the right. / val allSource = flexSet.map(_.sourceCard).sum require( allSink == 0 \|\| allSource == 0, s"The nodes ${flexSet.map(_.name)} which are inter-connected by :=* have ${allSink} := operators and ${allSource} := operators connected to them, making it impossible to determine cardinality inference direction." ) allSink - allSource } /** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. / protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = { if (flexibleArityDirection) flexOffset else if (n.flexibleArityDirection) n.flexOffset else 0 } /* For a node which is connected between two nodes, select the one that will influence the direction of the flex * resolution. / protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = { val dir = edgeArityDirection(n) if (dir < 0) l else if (dir > 0) r else 1 } /* Ensure that the same node is not visited twice in resolving `:=`, etc operators. / private var starCycleGuard = false /** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star" * connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also * need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct * edge parameters and later build up correct bundle connections. * * [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding * operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort * (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N := foo` or `N :=* foo := bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo := N` / protected[diplomacy] lazy val ( oPortMapping: Seq[(Int, Int)], iPortMapping: Seq[(Int, Int)], oStar: Int, iStar: Int ) = { try { if (starCycleGuard) throw StarCycleException() starCycleGuard = true // For a given node N... // Number of foo := N // + Number of bar :=* foo := N val oStars = oBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) < 0) } // Number of N := foo // + Number of N :=* foo := bar val iStars = iBindings.count { case (_, n, b, _, _) => b == BIND_STAR \|\| (b == BIND_FLEX && edgeArityDirection(n) > 0) } // 1 for foo := N // + bar.iStar for bar := foo := N // + foo.iStar for foo := N // + 0 for foo := N val oKnown = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, 0, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => 0 } }.sum // 1 for N := foo // + bar.oStar for N := foo :=* bar // + foo.oStar for N :=* foo // + 0 for N := foo val iKnown = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, 0) case BIND_QUERY => n.oStar case BIND_STAR => 0 } }.sum // Resolve star depends on the node subclass to implement the algorithm for this. val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars) // Cumulative list of resolved outward binding range starting points val oSum = oBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar) case BIND_QUERY => n.iStar case BIND_STAR => oStar } }.scanLeft(0)(_ + _) // Cumulative list of resolved inward binding range starting points val iSum = iBindings.map { case (_, n, b, _, _) => b match { case BIND_ONCE => 1 case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar) case BIND_QUERY => n.oStar case BIND_STAR => iStar } }.scanLeft(0)(_ + _) // Create ranges for each binding based on the running sums and return // those along with resolved values for the star operations. (oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar) } catch { case c: StarCycleException => throw c.copy(loop = context +: c.loop) } } /* Sequence of inward ports. * * This should be called after all star bindings are resolved. * * Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. * `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this * connection was made in the source code. / protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oBindings.flatMap { case (i, n, _, p, s) => // for each binding operator in this node, look at what it connects to val (start, end) = n.iPortMapping(i) (start until end).map { j => (j, n, p, s) } } /* Sequence of outward ports. * * This should be called after all star bindings are resolved. * * `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of * outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection * was made in the source code. / protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iBindings.flatMap { case (i, n, _, p, s) => // query this port index range of this node in the other side of node. val (start, end) = n.oPortMapping(i) (start until end).map { j => (j, n, p, s) } } // Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree // Thus, there must exist an Eulerian path and the below algorithms terminate @scala.annotation.tailrec private def oTrace( tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) ): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.iForward(i) match { case None => (i, n, p, s) case Some((j, m)) => oTrace((j, m, p, s)) } } @scala.annotation.tailrec private def iTrace( tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) ): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match { case (i, n, p, s) => n.oForward(i) match { case None => (i, n, p, s) case Some((j, m)) => iTrace((j, m, p, s)) } } /* Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - Numeric index of this binding in the [[InwardNode]] on the other end. * - [[InwardNode]] on the other end of this binding. * - A view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace) /* Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved. * * Each Port is a tuple of: * - numeric index of this binding in [[OutwardNode]] on the other end. * - [[OutwardNode]] on the other end of this binding. * - a view of [[Parameters]] where the binding occurred. * - [[SourceInfo]] for source-level error reporting. / lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace) private var oParamsCycleGuard = false protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) } protected[diplomacy] lazy val doParams: Seq[DO] = { try { if (oParamsCycleGuard) throw DownwardCycleException() oParamsCycleGuard = true val o = mapParamsD(oPorts.size, diParams) require( o.size == oPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of outward ports should equal the number of produced outward parameters. \|$context \|$connectedPortsInfo \|Downstreamed inward parameters: [${diParams.mkString(",")}] \|Produced outward parameters: [${o.mkString(",")}] \|""".stripMargin ) o.map(outer.mixO(_, this)) } catch { case c: DownwardCycleException => throw c.copy(loop = context +: c.loop) } } private var iParamsCycleGuard = false protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) } protected[diplomacy] lazy val uiParams: Seq[UI] = { try { if (iParamsCycleGuard) throw UpwardCycleException() iParamsCycleGuard = true val i = mapParamsU(iPorts.size, uoParams) require( i.size == iPorts.size, s"""Diplomacy has detected a problem with your graph: \|At the following node, the number of inward ports should equal the number of produced inward parameters. \|$context \|$connectedPortsInfo \|Upstreamed outward parameters: [${uoParams.mkString(",")}] \|Produced inward parameters: [${i.mkString(",")}] \|""".stripMargin ) i.map(inner.mixI(_, this)) } catch { case c: UpwardCycleException => throw c.copy(loop = context +: c.loop) } } /* Outward edge parameters. / protected[diplomacy] lazy val edgesOut: Seq[EO] = (oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) } /* Inward edge parameters. / protected[diplomacy] lazy val edgesIn: Seq[EI] = (iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) } /* A tuple of the input edge parameters and output edge parameters for the edges bound to this node. * * If you need to access to the edges of a foreign Node, use this method (in/out create bundles). / lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut) /* Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. / protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e => val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } /* Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. / protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e => val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In") // TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue, // In the future, we should add an option to decide whether allowing unconnected in the LazyModule x := DontCare x } private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(serial, i), sink = HalfEdge(n.serial, j), flipped = false, name = wirePrefix + "out", dataOpt = None ) } private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) => Dangle( source = HalfEdge(n.serial, j), sink = HalfEdge(serial, i), flipped = true, name = wirePrefix + "in", dataOpt = None ) } /* Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. / protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleOut(i))) } /* Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. / protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) => d.copy(dataOpt = Some(bundleIn(i))) } private[diplomacy] var instantiated = false /* Gather Bundle and edge parameters of outward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def out: Seq[(BO, EO)] = { require( instantiated, s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleOut.zip(edgesOut) } /* Gather Bundle and edge parameters of inward ports. * * Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within * [[LazyModuleImp]] code or after its instantiation has completed. / def in: Seq[(BI, EI)] = { require( instantiated, s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun" ) bundleIn.zip(edgesIn) } /* Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires, * instantiate monitors on all input ports if appropriate, and return all the dangles of this node. / protected[diplomacy] def instantiate(): Seq[Dangle] = { instantiated = true if (!circuitIdentity) { (iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) } } danglesOut ++ danglesIn } protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn /* Connects the outward part of a node with the inward part of this node. / protected[diplomacy] def bind( h: OutwardNode[DI, UI, BI], binding: NodeBinding )( implicit p: Parameters, sourceInfo: SourceInfo ): Unit = { val x = this // x := y val y = h sourceLine(sourceInfo, " at ", "") val i = x.iPushed val o = y.oPushed y.oPush( i, x, binding match { case BIND_ONCE => BIND_ONCE case BIND_FLEX => BIND_FLEX case BIND_STAR => BIND_QUERY case BIND_QUERY => BIND_STAR } ) x.iPush(o, y, binding) } / Metadata for printing the node graph. / def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) => val re = inner.render(e) (n, re.copy(flipped = re.flipped != p(RenderFlipped))) } /* Metadata for printing the node graph / def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } } File Arbiter.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ object TLArbiter { // (valids, select) => readys type Policy = (Integer, UInt, Bool) => UInt val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0) val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width)) val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else { val valid = valids(width-1, 0) assert (valid === valids) val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0)) val filter = Cat(valid & ~mask, valid) val unready = (rightOR(filter, width2, width) >> 1) \| (mask << width) val readys = ~((unready >> width) & unready(width-1, 0)) when (select && valid.orR) { mask := leftOR(readys & valid, width) } readys(width-1, 0) } def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = { apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_) } def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]): Unit = { apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_) } def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])): Unit = { if (sources.isEmpty) { sink.bits := DontCare } else if (sources.size == 1) { sink :<>= sources.head._2 } else { val pairs = sources.toList val beatsIn = pairs.map(_._1) val sourcesIn = pairs.map(_._2) // The number of beats which remain to be sent val beatsLeft = RegInit(0.U) val idle = beatsLeft === 0.U val latch = idle && sink.ready // winner (if any) claims sink // Who wants access to the sink? val valids = sourcesIn.map(_.valid) // Arbitrate amongst the requests val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools) // Which request wins arbitration? val winner = VecInit((readys zip valids) map { case (r,v) => r&&v }) // Confirm the policy works properly require (readys.size == valids.size) // Never two winners val prefixOR = winner.scanLeft(false.B)(_\|\|_).init assert((prefixOR zip winner) map { case (p,w) => !p \|\| !w } reduce {_ && _}) // If there was any request, there is a winner assert (!valids.reduce(_\|\|_) \|\| winner.reduce(_\|\|_)) // Track remaining beats val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) } val initBeats = maskedBeats.reduce(_ \| _) // no winner => 0 beats beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire) // The one-hot source granted access in the previous cycle val state = RegInit(VecInit(Seq.fill(sources.size)(false.B))) val muxState = Mux(idle, winner, state) state := muxState val allowed = Mux(idle, readys, state) (sourcesIn zip allowed) foreach { case (s, r) => s.ready := sink.ready && r } sink.valid := Mux(idle, valids.reduce(_\|\|_), Mux1H(state, valids)) sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits)) } } } // Synthesizable unit tests import freechips.rocketchip.unittest._ abstract class DecoupledArbiterTest( policy: TLArbiter.Policy, txns: Int, timeout: Int, val numSources: Int, beatsLeftFromIdx: Int => UInt) (implicit p: Parameters) extends UnitTest(timeout) { val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W)))) dontTouch(sources.suggestName("sources")) val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W))) dontTouch(sink.suggestName("sink")) val count = RegInit(0.U(log2Ceil(txns).W)) val lfsr = LFSR(16, true.B) sources.zipWithIndex.map { case (z, i) => z.bits := i.U } TLArbiter(policy)(sink, sources.zipWithIndex.map { case (z, i) => (beatsLeftFromIdx(i), z) }:_) count := count + 1.U io.finished := count >= txns.U } /** This tests that when a specific pattern of source valids are driven, * a new index from amongst that pattern is always selected, * unless one of those sources takes multiple beats, * in which case the same index should be selected until the arbiter goes idle. / class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false) (implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U) { val lastWinner = RegInit((numSources+1).U) val beatsLeft = RegInit(0.U(log2Ceil(numSources).W)) val first = lastWinner > numSources.U val valid = lfsr(0) val ready = lfsr(15) sink.ready := ready sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid) } when (sink.fire) { if (print) { printf("TestRobin: %d\n", sink.bits) } when (beatsLeft === 0.U) { assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.") lastWinner := sink.bits beatsLeft := sink.bits } .otherwise { assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats") beatsLeft := beatsLeft - 1.U } } if (print) { when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) } } } /* This tests that the lowest index is always selected across random single cycle transactions. / class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertLowest(id: Int): Unit = { when (sources(id).valid) { assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) } } /* This tests that the highest index is always selected across random single cycle transactions. / class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters) extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U) { def assertHighest(id: Int): Unit = { when (sources(id).valid) { assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.") } } sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) } sink.ready := lfsr(15) when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) } } File Xbar.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue} import freechips.rocketchip.util.BundleField // Trades off slave port proximity against routing resource cost object ForceFanout { def apply[T]( a: TriStateValue = TriStateValue.unset, b: TriStateValue = TriStateValue.unset, c: TriStateValue = TriStateValue.unset, d: TriStateValue = TriStateValue.unset, e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) = { body(p.alterPartial { case ForceFanoutKey => p(ForceFanoutKey) match { case ForceFanoutParams(pa, pb, pc, pd, pe) => ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe)) } }) } } private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean) private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false)) class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule { val node = new TLNexusNode( clientFn = { seq => seq(0).v1copy( echoFields = BundleField.union(seq.flatMap(_.echoFields)), requestFields = BundleField.union(seq.flatMap(_.requestFields)), responseKeys = seq.flatMap(_.responseKeys).distinct, minLatency = seq.map(_.minLatency).min, clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) => port.clients map { client => client.v1copy( sourceId = client.sourceId.shift(range.start) )} } ) }, managerFn = { seq => val fifoIdFactory = TLXbar.relabeler() seq(0).v1copy( responseFields = BundleField.union(seq.flatMap(_.responseFields)), requestKeys = seq.flatMap(_.requestKeys).distinct, minLatency = seq.map(_.minLatency).min, endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max, managers = seq.flatMap { port => require (port.beatBytes == seq(0).beatBytes, s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B") val fifoIdMapper = fifoIdFactory() port.managers map { manager => manager.v1copy( fifoId = manager.fifoId.map(fifoIdMapper(_)) )} } ) } ){ override def circuitIdentity = outputs.size == 1 && inputs.size == 1 } lazy val module = new Impl class Impl extends LazyModuleImp(this) { if ((node.in.size node.out.size) > (832)) { println (s"!!! WARNING !!!") println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.") println (s"!!! WARNING !!!") } val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle)) override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_") TLXbar.circuit(policy, node.in, node.out) } } object TLXbar { def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId)) def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId)) def assignRanges(sizes: Seq[Int]) = { val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) } val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions val ranges = (tuples zip starts) map { case ((sz, i), st) => (if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i) } ranges.sortBy(_._2).map(_._1) // Restore orignal order } def relabeler() = { var idFactory = 0 () => { val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int] (x: Int) => { if (fifoMap.contains(x)) fifoMap(x) else { val out = idFactory idFactory = idFactory + 1 fifoMap += (x -> out) out } } } } def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) { val (io_in, edgesIn) = seqIn.unzip val (io_out, edgesOut) = seqOut.unzip // Not every master need connect to every slave on every channel; determine which connections are necessary val reachableIO = edgesIn.map { cp => edgesOut.map { mp => cp.client.clients.exists { c => mp.manager.managers.exists { m => c.visibility.exists { ca => m.address.exists { ma => ca.overlaps(ma)}}}} }.toVector}.toVector val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED) }.toVector}.toVector val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) => (edgesOut zip reachableO).map { case (mp, reachable) => reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB }.toVector}.toVector val connectAIO = reachableIO val connectBIO = probeIO val connectCIO = releaseIO val connectDIO = reachableIO val connectEIO = releaseIO def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } } val connectAOI = transpose(connectAIO) val connectBOI = transpose(connectBIO) val connectCOI = transpose(connectCIO) val connectDOI = transpose(connectDIO) val connectEOI = transpose(connectEIO) // Grab the port ID mapping val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client)) val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager)) // We need an intermediate size of bundle with the widest possible identifiers val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params)) // Handle size = 1 gracefully (Chisel3 empty range is broken) def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0) // Transform input bundle sources (sinks use global namespace on both sides) val in = Wire(Vec(io_in.size, TLBundle(wide_bundle))) for (i <- 0 until in.size) { val r = inputIdRanges(i) if (connectAIO(i).exists(x=>x)) { in(i).a.bits.user := DontCare in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll in(i).a.bits.source := io_in(i).a.bits.source \| r.start.U } else { in(i).a := DontCare io_in(i).a := DontCare in(i).a.valid := false.B io_in(i).a.ready := true.B } if (connectBIO(i).exists(x=>x)) { io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size) } else { in(i).b := DontCare io_in(i).b := DontCare in(i).b.ready := true.B io_in(i).b.valid := false.B } if (connectCIO(i).exists(x=>x)) { in(i).c.bits.user := DontCare in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll in(i).c.bits.source := io_in(i).c.bits.source \| r.start.U } else { in(i).c := DontCare io_in(i).c := DontCare in(i).c.valid := false.B io_in(i).c.ready := true.B } if (connectDIO(i).exists(x=>x)) { io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size) } else { in(i).d := DontCare io_in(i).d := DontCare in(i).d.ready := true.B io_in(i).d.valid := false.B } if (connectEIO(i).exists(x=>x)) { in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll } else { in(i).e := DontCare io_in(i).e := DontCare in(i).e.valid := false.B io_in(i).e.ready := true.B } } // Transform output bundle sinks (sources use global namespace on both sides) val out = Wire(Vec(io_out.size, TLBundle(wide_bundle))) for (o <- 0 until out.size) { val r = outputIdRanges(o) if (connectAOI(o).exists(x=>x)) { out(o).a.bits.user := DontCare io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll } else { out(o).a := DontCare io_out(o).a := DontCare out(o).a.ready := true.B io_out(o).a.valid := false.B } if (connectBOI(o).exists(x=>x)) { out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll } else { out(o).b := DontCare io_out(o).b := DontCare out(o).b.valid := false.B io_out(o).b.ready := true.B } if (connectCOI(o).exists(x=>x)) { out(o).c.bits.user := DontCare io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll } else { out(o).c := DontCare io_out(o).c := DontCare out(o).c.ready := true.B io_out(o).c.valid := false.B } if (connectDOI(o).exists(x=>x)) { out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll out(o).d.bits.sink := io_out(o).d.bits.sink \| r.start.U } else { out(o).d := DontCare io_out(o).d := DontCare out(o).d.valid := false.B io_out(o).d.ready := true.B } if (connectEOI(o).exists(x=>x)) { io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size) } else { out(o).e := DontCare io_out(o).e := DontCare out(o).e.ready := true.B io_out(o).e.valid := false.B } } // Filter a list to only those elements selected def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1) // Based on input=>output connectivity, create per-input minimal address decode circuits val requiredAC = (connectAIO ++ connectCIO).distinct val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO => val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address)) val routingMask = AddressDecoder(filter(port_addrs, connectO)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) // Print the address mapping if (false) { println("Xbar mapping:") route_addrs.foreach { p => print(" ") p.foreach { a => print(s" ${a}") } println("") } println("--") } (connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ \|\| _))) }.toMap // Print the ID mapping if (false) { println(s"XBar mapping:") (edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) => println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}") } println("") } val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) } val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) } def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) \|\| o(i) } } val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) \|\| o(i) } } val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } } val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } } val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } } val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) } val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) } val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) } val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) } val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) } // Fanout the input sources to the output sinks val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) }) val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) }) val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) }) val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) }) val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) }) // Arbitrate amongst the sources for (o <- 0 until out.size) { TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_) TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_) TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_) filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B } filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B } } for (i <- 0 until in.size) { TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_) TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_) filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B } filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B } } } def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode = { val xbar = LazyModule(new TLXbar(policy, nameSuffix)) xbar.node } // Replicate an input port to each output port def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = { val filtered = Wire(Vec(select.size, chiselTypeOf(input))) for (i <- 0 until select.size) { filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits) filtered(i).valid := input.valid && (select(i) \|\| (select.size == 1).B) } input.ready := Mux1H(select, filtered.map(_.ready)) filtered } } // Synthesizable unit tests import freechips.rocketchip.unittest._ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished } } class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module) dut.io.start := io.start io.finished := dut.io.finished } class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400n, 0x3ff))) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new Impl class Impl extends LazyModuleImp(this) with UnitTestModule { io.finished := fuzzers.last.module.io.finished } } class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) { val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module) dut.io.start := io.start io.finished := dut.io.finished }	module TLXbar_mbus_i1_o2_a32d64s3k1z3u( // @[Xbar.scala:74:9] input clock, // @[Xbar.scala:74:9] input reset, // @[Xbar.scala:74:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire out_1_d_bits_sink; // @[Xbar.scala:216:19] wire [2:0] in_0_d_bits_source; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_source; // @[Xbar.scala:159:18] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[Xbar.scala:74:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_ready_0 = auto_anon_out_1_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_valid_0 = auto_anon_out_1_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_opcode_0 = auto_anon_out_1_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] auto_anon_out_1_d_bits_param_0 = auto_anon_out_1_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_size_0 = auto_anon_out_1_d_bits_size; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_d_bits_source_0 = auto_anon_out_1_d_bits_source; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_sink_0 = auto_anon_out_1_d_bits_sink; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_denied_0 = auto_anon_out_1_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_1_d_bits_data_0 = auto_anon_out_1_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_bits_corrupt_0 = auto_anon_out_1_d_bits_corrupt; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_ready_0 = auto_anon_out_0_a_ready; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_valid_0 = auto_anon_out_0_d_valid; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_opcode_0 = auto_anon_out_0_d_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_size_0 = auto_anon_out_0_d_bits_size; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_d_bits_source_0 = auto_anon_out_0_d_bits_source; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_denied_0 = auto_anon_out_0_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_0_d_bits_data_0 = auto_anon_out_0_d_bits_data; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_bits_corrupt_0 = auto_anon_out_0_d_bits_corrupt; // @[Xbar.scala:74:9] wire _readys_T_2 = reset; // @[Arbiter.scala:22:12] wire [1:0] auto_anon_out_0_d_bits_param = 2'h0; // @[Xbar.scala:74:9] wire [1:0] anonOut_d_bits_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] out_0_d_bits_param = 2'h0; // @[Xbar.scala:216:19] wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _beatsBO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _beatsBO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _portsBIO_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] _portsBIO_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [1:0] portsBIO_filtered_1_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] portsDIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24] wire [1:0] _in_0_d_bits_T_18 = 2'h0; // @[Mux.scala:30:73] wire auto_anon_out_0_d_bits_sink = 1'h0; // @[Xbar.scala:74:9] wire anonOut_d_bits_sink = 1'h0; // @[MixedNode.scala:542:17] wire out_0_d_bits_sink = 1'h0; // @[Xbar.scala:216:19] wire _out_0_d_bits_sink_T = 1'h0; // @[Xbar.scala:251:53] wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _requestBOI_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T = 1'h0; // @[Parameters.scala:54:10] wire _requestDOI_T_5 = 1'h0; // @[Parameters.scala:54:10] wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_2_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61] wire _requestEIO_WIRE_3_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37] wire _beatsBO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _beatsBO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _beatsBO_opdata_T_1 = 1'h0; // @[Edges.scala:97:37] wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36] wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _beatsEI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsBIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire _portsBIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61] wire _portsBIO_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire portsBIO_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsBIO_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsBIO_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsCOI_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24] wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsCOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsCOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire portsDIO_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74] wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61] wire _portsEOI_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61] wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_0_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24] wire portsEOI_filtered_1_bits_sink = 1'h0; // @[Xbar.scala:352:24] wire _portsEOI_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_filtered_1_valid_T = 1'h0; // @[Xbar.scala:355:54] wire _portsEOI_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40] wire _portsEOI_T = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_1 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_T_2 = 1'h0; // @[Mux.scala:30:73] wire _portsEOI_WIRE_2 = 1'h0; // @[Mux.scala:30:73] wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34] wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34] wire _in_0_d_bits_T_9 = 1'h0; // @[Mux.scala:30:73] wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107] wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59] wire requestCIO_0_1 = 1'h1; // @[Xbar.scala:308:107] wire _requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestBOI_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestBOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestBOI_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestBOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestBOI_1_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48] wire _requestDOI_T_6 = 1'h1; // @[Parameters.scala:54:32] wire _requestDOI_T_7 = 1'h1; // @[Parameters.scala:56:32] wire _requestDOI_T_8 = 1'h1; // @[Parameters.scala:54:67] wire _requestDOI_T_9 = 1'h1; // @[Parameters.scala:57:20] wire requestDOI_1_0 = 1'h1; // @[Parameters.scala:56:48] wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28] wire beatsBO_opdata_1 = 1'h1; // @[Edges.scala:97:28] wire _portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsBIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsCOI_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54] wire _portsDIO_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54] wire [63:0] _addressC_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _addressC_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _requestBOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _requestBOI_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _requestBOI_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsBO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _beatsBO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _beatsCI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _beatsCI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _portsBIO_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsBIO_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] _portsBIO_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] portsBIO_filtered_1_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] _portsCOI_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _portsCOI_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] portsCOI_filtered_0_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [63:0] portsCOI_filtered_1_bits_data = 64'h0; // @[Xbar.scala:352:24] wire [31:0] _addressC_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _addressC_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _requestCIO_T = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31] wire [31:0] _requestBOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _requestBOI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _requestBOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsBO_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _beatsBO_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _beatsCI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _beatsCI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _portsBIO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] portsBIO_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsBIO_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] _portsBIO_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] portsBIO_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] _portsCOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _portsCOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] portsCOI_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [31:0] portsCOI_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24] wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_bits_source = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _addressC_WIRE_1_bits_source = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_bits_source = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_1_bits_source = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_uncommonBits_T = 3'h0; // @[Parameters.scala:52:29] wire [2:0] requestBOI_uncommonBits = 3'h0; // @[Parameters.scala:52:56] wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_2_bits_source = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_WIRE_3_bits_source = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _requestBOI_uncommonBits_T_1 = 3'h0; // @[Parameters.scala:52:29] wire [2:0] requestBOI_uncommonBits_1 = 3'h0; // @[Parameters.scala:52:56] wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_bits_source = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_1_bits_source = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsBO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_2_bits_source = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _beatsBO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _beatsBO_WIRE_3_bits_source = 3'h0; // @[Bundles.scala:264:61] wire [2:0] beatsBO_decode_1 = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsBO_1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_bits_source = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _beatsCI_WIRE_1_bits_source = 3'h0; // @[Bundles.scala:265:61] wire [2:0] beatsCI_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] beatsCI_0 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_bits_source = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _portsBIO_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _portsBIO_WIRE_1_bits_source = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_0_bits_source = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsBIO_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_2_bits_source = 3'h0; // @[Bundles.scala:264:74] wire [2:0] _portsBIO_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _portsBIO_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _portsBIO_WIRE_3_bits_source = 3'h0; // @[Bundles.scala:264:61] wire [2:0] portsBIO_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsBIO_filtered_1_0_bits_source = 3'h0; // @[Xbar.scala:352:24] wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_bits_source = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _portsCOI_WIRE_1_bits_source = 3'h0; // @[Bundles.scala:265:61] wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_0_bits_source = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_param = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_size = 3'h0; // @[Xbar.scala:352:24] wire [2:0] portsCOI_filtered_1_bits_source = 3'h0; // @[Xbar.scala:352:24] wire [7:0] _requestBOI_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _requestBOI_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _requestBOI_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _beatsBO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _beatsBO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] _portsBIO_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [7:0] _portsBIO_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] _portsBIO_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [7:0] portsBIO_filtered_1_0_bits_mask = 8'h0; // @[Xbar.scala:352:24] wire [5:0] _beatsBO_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsBO_decode_T_5 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsCI_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _beatsBO_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsBO_decode_T_4 = 6'h3F; // @[package.scala:243:76] wire [5:0] _beatsCI_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _beatsBO_decode_T = 13'h3F; // @[package.scala:243:71] wire [12:0] _beatsBO_decode_T_3 = 13'h3F; // @[package.scala:243:71] wire [12:0] _beatsCI_decode_T = 13'h3F; // @[package.scala:243:71] wire [32:0] _requestCIO_T_1 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41] wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46] wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[Xbar.scala:74:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[Xbar.scala:74:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire x1_anonOut_a_ready = auto_anon_out_1_a_ready_0; // @[Xbar.scala:74:9] wire x1_anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] x1_anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [27:0] x1_anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_anonOut_d_ready; // @[MixedNode.scala:542:17] wire x1_anonOut_d_valid = auto_anon_out_1_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_opcode = auto_anon_out_1_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] x1_anonOut_d_bits_param = auto_anon_out_1_d_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_size = auto_anon_out_1_d_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] x1_anonOut_d_bits_source = auto_anon_out_1_d_bits_source_0; // @[Xbar.scala:74:9] wire x1_anonOut_d_bits_sink = auto_anon_out_1_d_bits_sink_0; // @[Xbar.scala:74:9] wire x1_anonOut_d_bits_denied = auto_anon_out_1_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] x1_anonOut_d_bits_data = auto_anon_out_1_d_bits_data_0; // @[Xbar.scala:74:9] wire x1_anonOut_d_bits_corrupt = auto_anon_out_1_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire anonOut_a_ready = auto_anon_out_0_a_ready_0; // @[Xbar.scala:74:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_0_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_0_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_size = auto_anon_out_0_d_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] anonOut_d_bits_source = auto_anon_out_0_d_bits_source_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_denied = auto_anon_out_0_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] anonOut_d_bits_data = auto_anon_out_0_d_bits_data_0; // @[Xbar.scala:74:9] wire anonOut_d_bits_corrupt = auto_anon_out_0_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_a_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[Xbar.scala:74:9] wire [1:0] auto_anon_in_d_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_d_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_in_d_bits_source_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_sink_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_denied_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_in_d_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_in_d_valid_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_1_a_bits_source_0; // @[Xbar.scala:74:9] wire [27:0] auto_anon_out_1_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_1_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_1_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_1_d_ready_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_opcode_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_param_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_size_0; // @[Xbar.scala:74:9] wire [2:0] auto_anon_out_0_a_bits_source_0; // @[Xbar.scala:74:9] wire [31:0] auto_anon_out_0_a_bits_address_0; // @[Xbar.scala:74:9] wire [7:0] auto_anon_out_0_a_bits_mask_0; // @[Xbar.scala:74:9] wire [63:0] auto_anon_out_0_a_bits_data_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_bits_corrupt_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_a_valid_0; // @[Xbar.scala:74:9] wire auto_anon_out_0_d_ready_0; // @[Xbar.scala:74:9] wire in_0_a_ready; // @[Xbar.scala:159:18] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9] wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18] wire [2:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18] wire [2:0] _in_0_a_bits_source_T = anonIn_a_bits_source; // @[Xbar.scala:166:55] wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18] wire [7:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18] wire [63:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18] wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18] wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18] wire in_0_d_valid; // @[Xbar.scala:159:18] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9] wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9] wire [2:0] in_0_d_bits_size; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9] wire [2:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9] wire in_0_d_bits_sink; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9] wire in_0_d_bits_denied; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9] wire [63:0] in_0_d_bits_data; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9] wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19] wire out_0_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [2:0] out_0_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9] wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_0_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_0_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_0_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_0_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_0_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9] wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [2:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19] wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire out_1_a_ready = x1_anonOut_a_ready; // @[Xbar.scala:216:19] wire out_1_a_valid; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_valid_0 = x1_anonOut_a_valid; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_opcode_0 = x1_anonOut_a_bits_opcode; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_param; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_param_0 = x1_anonOut_a_bits_param; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_size; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_size_0 = x1_anonOut_a_bits_size; // @[Xbar.scala:74:9] wire [2:0] out_1_a_bits_source; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_source_0 = x1_anonOut_a_bits_source; // @[Xbar.scala:74:9] assign auto_anon_out_1_a_bits_address_0 = x1_anonOut_a_bits_address; // @[Xbar.scala:74:9] wire [7:0] out_1_a_bits_mask; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_mask_0 = x1_anonOut_a_bits_mask; // @[Xbar.scala:74:9] wire [63:0] out_1_a_bits_data; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_data_0 = x1_anonOut_a_bits_data; // @[Xbar.scala:74:9] wire out_1_a_bits_corrupt; // @[Xbar.scala:216:19] assign auto_anon_out_1_a_bits_corrupt_0 = x1_anonOut_a_bits_corrupt; // @[Xbar.scala:74:9] wire out_1_d_ready; // @[Xbar.scala:216:19] assign auto_anon_out_1_d_ready_0 = x1_anonOut_d_ready; // @[Xbar.scala:74:9] wire out_1_d_valid = x1_anonOut_d_valid; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_opcode = x1_anonOut_d_bits_opcode; // @[Xbar.scala:216:19] wire [1:0] out_1_d_bits_param = x1_anonOut_d_bits_param; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_size = x1_anonOut_d_bits_size; // @[Xbar.scala:216:19] wire [2:0] out_1_d_bits_source = x1_anonOut_d_bits_source; // @[Xbar.scala:216:19] wire _out_1_d_bits_sink_T = x1_anonOut_d_bits_sink; // @[Xbar.scala:251:53] wire out_1_d_bits_denied = x1_anonOut_d_bits_denied; // @[Xbar.scala:216:19] wire [63:0] out_1_d_bits_data = x1_anonOut_d_bits_data; // @[Xbar.scala:216:19] wire out_1_d_bits_corrupt = x1_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19] wire _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18] wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [2:0] portsAOI_filtered_1_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24] wire [31:0] _requestAIO_T_5 = in_0_a_bits_address; // @[Xbar.scala:159:18] wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [31:0] portsAOI_filtered_1_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [7:0] portsAOI_filtered_1_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire [63:0] portsAOI_filtered_1_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire portsAOI_filtered_1_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24] wire _in_0_d_valid_T_4; // @[Arbiter.scala:96:24] assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_opcode; // @[Mux.scala:30:73] assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18] wire [1:0] _in_0_d_bits_WIRE_param; // @[Mux.scala:30:73] assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_size; // @[Mux.scala:30:73] assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18] wire [2:0] _in_0_d_bits_WIRE_source; // @[Mux.scala:30:73] assign _anonIn_d_bits_source_T = in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18] wire _in_0_d_bits_WIRE_sink; // @[Mux.scala:30:73] assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18] wire _in_0_d_bits_WIRE_denied; // @[Mux.scala:30:73] assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18] wire [63:0] _in_0_d_bits_WIRE_data; // @[Mux.scala:30:73] assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18] wire _in_0_d_bits_WIRE_corrupt; // @[Mux.scala:30:73] assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18] assign in_0_a_bits_source = _in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55] assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69] wire portsAOI_filtered_0_ready = out_0_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24] assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19] assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19] assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19] assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19] assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19] assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19] assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19] assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19] assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_0_ready; // @[Xbar.scala:352:24] assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_1 = out_0_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [2:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19] wire [2:0] portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_1_ready = out_1_a_ready; // @[Xbar.scala:216:19, :352:24] wire portsAOI_filtered_1_valid; // @[Xbar.scala:352:24] assign x1_anonOut_a_valid = out_1_a_valid; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_opcode = out_1_a_bits_opcode; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_param = out_1_a_bits_param; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_size = out_1_a_bits_size; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_source = out_1_a_bits_source; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_mask = out_1_a_bits_mask; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_data = out_1_a_bits_data; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_corrupt = out_1_a_bits_corrupt; // @[Xbar.scala:216:19] wire portsDIO_filtered_1_0_ready; // @[Xbar.scala:352:24] assign x1_anonOut_d_ready = out_1_d_ready; // @[Xbar.scala:216:19] wire _portsDIO_filtered_0_valid_T_3 = out_1_d_valid; // @[Xbar.scala:216:19, :355:40] wire [2:0] portsDIO_filtered_1_0_bits_opcode = out_1_d_bits_opcode; // @[Xbar.scala:216:19, :352:24] wire [1:0] portsDIO_filtered_1_0_bits_param = out_1_d_bits_param; // @[Xbar.scala:216:19, :352:24] wire [2:0] portsDIO_filtered_1_0_bits_size = out_1_d_bits_size; // @[Xbar.scala:216:19, :352:24] wire [2:0] _requestDOI_uncommonBits_T_1 = out_1_d_bits_source; // @[Xbar.scala:216:19] wire [2:0] portsDIO_filtered_1_0_bits_source = out_1_d_bits_source; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_bits_sink = out_1_d_bits_sink; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_bits_denied = out_1_d_bits_denied; // @[Xbar.scala:216:19, :352:24] wire [63:0] portsDIO_filtered_1_0_bits_data = out_1_d_bits_data; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_bits_corrupt = out_1_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire [31:0] out_1_a_bits_address; // @[Xbar.scala:216:19] assign x1_anonOut_a_bits_address = out_1_a_bits_address[27:0]; // @[Xbar.scala:216:19, :222:41] assign out_1_d_bits_sink = _out_1_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53] wire [31:0] _requestAIO_T = in_0_a_bits_address ^ 32'h80000000; // @[Xbar.scala:159:18] wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_2 = _requestAIO_T_1 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_3 = _requestAIO_T_2; // @[Parameters.scala:137:46] wire _requestAIO_T_4 = _requestAIO_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_0 = _requestAIO_T_4; // @[Xbar.scala:307:107] wire _portsAOI_filtered_0_valid_T = requestAIO_0_0; // @[Xbar.scala:307:107, :355:54] wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _requestAIO_T_7 = _requestAIO_T_6 & 33'h80000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _requestAIO_T_8 = _requestAIO_T_7; // @[Parameters.scala:137:46] wire _requestAIO_T_9 = _requestAIO_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire requestAIO_0_1 = _requestAIO_T_9; // @[Xbar.scala:307:107] wire _portsAOI_filtered_1_valid_T = requestAIO_0_1; // @[Xbar.scala:307:107, :355:54] wire [2:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [2:0] requestDOI_uncommonBits_1 = _requestDOI_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [12:0] _beatsAI_decode_T = 13'h3F << in_0_a_bits_size; // @[package.scala:243:71] wire [5:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] beatsAI_decode = _beatsAI_decode_T_2[5:3]; // @[package.scala:243:46] wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18] wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] wire [12:0] _beatsDO_decode_T = 13'h3F << out_0_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode = _beatsDO_decode_T_2[5:3]; // @[package.scala:243:46] wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire [12:0] _beatsDO_decode_T_3 = 13'h3F << out_1_d_bits_size; // @[package.scala:243:71] wire [5:0] _beatsDO_decode_T_4 = _beatsDO_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _beatsDO_decode_T_5 = ~_beatsDO_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] beatsDO_decode_1 = _beatsDO_decode_T_5[5:3]; // @[package.scala:243:46] wire beatsDO_opdata_1 = out_1_d_bits_opcode[0]; // @[Xbar.scala:216:19] wire [2:0] beatsDO_1 = beatsDO_opdata_1 ? beatsDO_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] wire _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:355:40] assign out_0_a_valid = portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_opcode = portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_param = portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_size = portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_source = portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_address = portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_mask = portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_data = portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_0_a_bits_corrupt = portsAOI_filtered_0_bits_corrupt; // @[Xbar.scala:216:19, :352:24] wire _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:355:40] assign out_1_a_valid = portsAOI_filtered_1_valid; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_opcode = portsAOI_filtered_1_bits_opcode; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_param = portsAOI_filtered_1_bits_param; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_size = portsAOI_filtered_1_bits_size; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_source = portsAOI_filtered_1_bits_source; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_address = portsAOI_filtered_1_bits_address; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_mask = portsAOI_filtered_1_bits_mask; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_data = portsAOI_filtered_1_bits_data; // @[Xbar.scala:216:19, :352:24] assign out_1_a_bits_corrupt = portsAOI_filtered_1_bits_corrupt; // @[Xbar.scala:216:19, :352:24] assign _portsAOI_filtered_0_valid_T_1 = in_0_a_valid & _portsAOI_filtered_0_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] assign _portsAOI_filtered_1_valid_T_1 = in_0_a_valid & _portsAOI_filtered_1_valid_T; // @[Xbar.scala:159:18, :355:{40,54}] assign portsAOI_filtered_1_valid = _portsAOI_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _portsAOI_in_0_a_ready_T = requestAIO_0_0 & portsAOI_filtered_0_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_1 = requestAIO_0_1 & portsAOI_filtered_1_ready; // @[Mux.scala:30:73] wire _portsAOI_in_0_a_ready_T_2 = _portsAOI_in_0_a_ready_T \| _portsAOI_in_0_a_ready_T_1; // @[Mux.scala:30:73] assign _portsAOI_in_0_a_ready_WIRE = _portsAOI_in_0_a_ready_T_2; // @[Mux.scala:30:73] assign in_0_a_ready = _portsAOI_in_0_a_ready_WIRE; // @[Mux.scala:30:73] wire _filtered_0_ready_T; // @[Arbiter.scala:94:31] assign out_0_d_ready = portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40] wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31] assign out_1_d_ready = portsDIO_filtered_1_0_ready; // @[Xbar.scala:216:19, :352:24] wire portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] assign portsDIO_filtered_1_0_valid = _portsDIO_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40] reg [2:0] beatsLeft; // @[Arbiter.scala:60:30] wire idle = beatsLeft == 3'h0; // @[Arbiter.scala:60:30, :61:28] wire latch = idle & in_0_d_ready; // @[Xbar.scala:159:18] wire [1:0] _readys_T = {portsDIO_filtered_1_0_valid, portsDIO_filtered_0_valid}; // @[Xbar.scala:352:24] wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51] wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51] wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12] wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}] reg [1:0] readys_mask; // @[Arbiter.scala:23:23] wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30] wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}] wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}] wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48] wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] \| _readys_unready_T}; // @[package.scala:262:{43,48}] wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17] wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17] wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66] wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} \| _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}] wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29] wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48] wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}] wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}] wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11] wire _readys_T_5 = \|readys_valid; // @[Arbiter.scala:21:23, :27:27] wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24] wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29] wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48] wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}] wire [1:0] _readys_mask_T_3 = _readys_mask_T \| _readys_mask_T_2; // @[package.scala:253:{43,53}] wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17] wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76] wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}] wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76] wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}] wire _winner_T = readys_0 & portsDIO_filtered_0_valid; // @[Xbar.scala:352:24] wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}] wire _winner_T_1 = readys_1 & portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24] wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}] wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48] wire _prefixOR_T = prefixOR_1 \| winner_1; // @[Arbiter.scala:71:27, :76:48] wire _in_0_d_valid_T = portsDIO_filtered_0_valid \| portsDIO_filtered_1_0_valid; // @[Xbar.scala:352:24]
Generate the Verilog code corresponding to the following Chisel files. File MSHR.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import freechips.rocketchip.tilelink._ import TLPermissions._ import TLMessages._ import MetaData._ import chisel3.PrintableHelper import chisel3.experimental.dataview._ class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val a = Valid(new SourceARequest(params)) val b = Valid(new SourceBRequest(params)) val c = Valid(new SourceCRequest(params)) val d = Valid(new SourceDRequest(params)) val e = Valid(new SourceERequest(params)) val x = Valid(new SourceXRequest(params)) val dir = Valid(new DirectoryWrite(params)) val reload = Bool() // get next request via allocate (if any) } class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val way = UInt(params.wayBits.W) val blockB = Bool() val nestB = Bool() val blockC = Bool() val nestC = Bool() } class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val b_toN = Bool() // nested Probes may unhit us val b_toB = Bool() // nested Probes may demote us val b_clr_dirty = Bool() // nested Probes clear dirty val c_set_dirty = Bool() // nested Releases MAY set dirty } sealed trait CacheState { val code = CacheState.index.U CacheState.index = CacheState.index + 1 } object CacheState { var index = 0 } case object S_INVALID extends CacheState case object S_BRANCH extends CacheState case object S_BRANCH_C extends CacheState case object S_TIP extends CacheState case object S_TIP_C extends CacheState case object S_TIP_CD extends CacheState case object S_TIP_D extends CacheState case object S_TRUNK_C extends CacheState case object S_TRUNK_CD extends CacheState class MSHR(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup val status = Valid(new MSHRStatus(params)) val schedule = Decoupled(new ScheduleRequest(params)) val sinkc = Flipped(Valid(new SinkCResponse(params))) val sinkd = Flipped(Valid(new SinkDResponse(params))) val sinke = Flipped(Valid(new SinkEResponse(params))) val nestedwb = Flipped(new NestedWriteback(params)) }) val request_valid = RegInit(false.B) val request = Reg(new FullRequest(params)) val meta_valid = RegInit(false.B) val meta = Reg(new DirectoryResult(params)) // Define which states are valid when (meta_valid) { when (meta.state === INVALID) { assert (!meta.clients.orR) assert (!meta.dirty) } when (meta.state === BRANCH) { assert (!meta.dirty) } when (meta.state === TRUNK) { assert (meta.clients.orR) assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one } when (meta.state === TIP) { // noop } } // Completed transitions (s_ = scheduled), (w_ = waiting) val s_rprobe = RegInit(true.B) // B val w_rprobeackfirst = RegInit(true.B) val w_rprobeacklast = RegInit(true.B) val s_release = RegInit(true.B) // CW w_rprobeackfirst val w_releaseack = RegInit(true.B) val s_pprobe = RegInit(true.B) // B val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1] val s_flush = RegInit(true.B) // X w_releaseack val w_grantfirst = RegInit(true.B) val w_grantlast = RegInit(true.B) val w_grant = RegInit(true.B) // first \| last depending on wormhole val w_pprobeackfirst = RegInit(true.B) val w_pprobeacklast = RegInit(true.B) val w_pprobeack = RegInit(true.B) // first \| last depending on wormhole val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_) val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD val s_execute = RegInit(true.B) // D w_pprobeack, w_grant val w_grantack = RegInit(true.B) val s_writeback = RegInit(true.B) // W w_* // [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall) // However, inB and outC are higher priority than outB, so s_release and s_pprobe // may be safely issued while blockB. Thus we must NOT try to schedule the // potentially stuck s_acquire with either of them (scheduler is all or none). // Meta-data that we discover underway val sink = Reg(UInt(params.outer.bundle.sinkBits.W)) val gotT = Reg(Bool()) val bad_grant = Reg(Bool()) val probes_done = Reg(UInt(params.clientBits.W)) val probes_toN = Reg(UInt(params.clientBits.W)) val probes_noT = Reg(Bool()) // When a nested transaction completes, update our meta data when (meta_valid && meta.state =/= INVALID && io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) { when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B } when (io.nestedwb.c_set_dirty) { meta.dirty := true.B } when (io.nestedwb.b_toB) { meta.state := BRANCH } when (io.nestedwb.b_toN) { meta.hit := false.B } } // Scheduler status io.status.valid := request_valid io.status.bits.set := request.set io.status.bits.tag := request.tag io.status.bits.way := meta.way io.status.bits.blockB := !meta_valid \|\| ((!w_releaseack \|\| !w_rprobeacklast \|\| !w_pprobeacklast) && !w_grantfirst) io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst // The above rules ensure we will block and not nest an outer probe while still doing our // own inner probes. Thus every probe wakes exactly one MSHR. io.status.bits.blockC := !meta_valid io.status.bits.nestC := meta_valid && (!w_rprobeackfirst \|\| !w_pprobeackfirst \|\| !w_grantfirst) // The w_grantfirst in nestC is necessary to deal with: // acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock // ... this is possible because the release+probe can be for same set, but different tag // We can only demand: block, nest, or queue assert (!io.status.bits.nestB \|\| !io.status.bits.blockB) assert (!io.status.bits.nestC \|\| !io.status.bits.blockC) // Scheduler requests val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe io.schedule.bits.b.valid := !s_rprobe \|\| !s_pprobe io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) \|\| (!s_probeack && w_pprobeackfirst) io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant io.schedule.bits.e.valid := !s_grantack && w_grantfirst io.schedule.bits.x.valid := !s_flush && w_releaseack io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) \|\| (!s_writeback && no_wait) io.schedule.bits.reload := no_wait io.schedule.valid := io.schedule.bits.a.valid \|\| io.schedule.bits.b.valid \|\| io.schedule.bits.c.valid \|\| io.schedule.bits.d.valid \|\| io.schedule.bits.e.valid \|\| io.schedule.bits.x.valid \|\| io.schedule.bits.dir.valid // Schedule completions when (io.schedule.ready) { s_rprobe := true.B when (w_rprobeackfirst) { s_release := true.B } s_pprobe := true.B when (s_release && s_pprobe) { s_acquire := true.B } when (w_releaseack) { s_flush := true.B } when (w_pprobeackfirst) { s_probeack := true.B } when (w_grantfirst) { s_grantack := true.B } when (w_pprobeack && w_grant) { s_execute := true.B } when (no_wait) { s_writeback := true.B } // Await the next operation when (no_wait) { request_valid := false.B meta_valid := false.B } } // Resulting meta-data val final_meta_writeback = WireInit(meta) val req_clientBit = params.clientBit(request.source) val req_needT = needT(request.opcode, request.param) val req_acquire = request.opcode === AcquireBlock \|\| request.opcode === AcquirePerm val meta_no_clients = !meta.clients.orR val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT) when (request.prio(2) && (!params.firstLevel).B) { // always a hit final_meta_writeback.dirty := meta.dirty \|\| request.opcode(0) final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state) final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U) final_meta_writeback.hit := true.B // chained requests are hits } .elsewhen (request.control && params.control.B) { // request.prio(0) when (meta.hit) { final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := meta.clients & ~probes_toN } final_meta_writeback.hit := false.B } .otherwise { final_meta_writeback.dirty := (meta.hit && meta.dirty) \|\| !request.opcode(2) final_meta_writeback.state := Mux(req_needT, Mux(req_acquire, TRUNK, TIP), Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH), MuxLookup(meta.state, 0.U(2.W))(Seq( INVALID -> BRANCH, BRANCH -> BRANCH, TRUNK -> TIP, TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP))))) final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) \| Mux(req_acquire, req_clientBit, 0.U) final_meta_writeback.tag := request.tag final_meta_writeback.hit := true.B } when (bad_grant) { when (meta.hit) { // upgrade failed (B -> T) assert (!meta_valid \|\| meta.state === BRANCH) final_meta_writeback.hit := true.B final_meta_writeback.dirty := false.B final_meta_writeback.state := BRANCH final_meta_writeback.clients := meta.clients & ~probes_toN } .otherwise { // failed N -> (T or B) final_meta_writeback.hit := false.B final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := 0.U } } val invalid = Wire(new DirectoryEntry(params)) invalid.dirty := false.B invalid.state := INVALID invalid.clients := 0.U invalid.tag := 0.U // Just because a client says BtoT, by the time we process the request he may be N. // Therefore, we must consult our own meta-data state to confirm he owns the line still. val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR // The client asking us to act is proof they don't have permissions. val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U) io.schedule.bits.a.bits.tag := request.tag io.schedule.bits.a.bits.set := request.set io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB) io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U \|\| !(request.opcode === PutFullData \|\| request.opcode === AcquirePerm) io.schedule.bits.a.bits.source := 0.U io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB))) io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag) io.schedule.bits.b.bits.set := request.set io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release) io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN) io.schedule.bits.c.bits.source := 0.U io.schedule.bits.c.bits.tag := meta.tag io.schedule.bits.c.bits.set := request.set io.schedule.bits.c.bits.way := meta.way io.schedule.bits.c.bits.dirty := meta.dirty io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param, MuxLookup(request.param, request.param)(Seq( NtoB -> Mux(req_promoteT, NtoT, NtoB), BtoT -> Mux(honour_BtoT, BtoT, NtoT), NtoT -> NtoT))) io.schedule.bits.d.bits.sink := 0.U io.schedule.bits.d.bits.way := meta.way io.schedule.bits.d.bits.bad := bad_grant io.schedule.bits.e.bits.sink := sink io.schedule.bits.x.bits.fail := false.B io.schedule.bits.dir.bits.set := request.set io.schedule.bits.dir.bits.way := meta.way io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback)) // Coverage of state transitions def cacheState(entry: DirectoryEntry, hit: Bool) = { val out = WireDefault(0.U) val c = entry.clients.orR val d = entry.dirty switch (entry.state) { is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) } is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) } is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) } is (INVALID) { out := S_INVALID.code } } when (!hit) { out := S_INVALID.code } out } val p = !params.lastLevel // can be probed val c = !params.firstLevel // can be acquired val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read) val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist val f = params.control // flush control register exists val cfg = (p, c, m, r, f) val b = r \|\| p // can reach branch state (via probe downgrade or read-only device) // The cache must be used for something or we would not be here require(c \|\| m) val evict = cacheState(meta, !meta.hit) val before = cacheState(meta, meta.hit) val after = cacheState(final_meta_writeback, true.B) def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}") } else { assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}") } if (cover && f) { params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}") } else { assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}") } } def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}") } else { assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}") } } when ((!s_release && w_rprobeackfirst) && io.schedule.ready) { eviction(S_BRANCH, b) // MMIO read to read-only device eviction(S_BRANCH_C, b && c) // you need children to become C eviction(S_TIP, true) // MMIO read \|\| clean release can lead to this state eviction(S_TIP_C, c) // needs two clients \|\| client + mmio \|\| downgrading client eviction(S_TIP_CD, c) // needs two clients \|\| client + mmio \|\| downgrading client eviction(S_TIP_D, true) // MMIO write \|\| dirty release lead here eviction(S_TRUNK_C, c) // acquire for write eviction(S_TRUNK_CD, c) // dirty release then reacquire } when ((!s_writeback && no_wait) && io.schedule.ready) { transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches transition(S_INVALID, S_TIP, m) // MMIO read transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_INVALID, S_TIP_D, m) // MMIO write transition(S_INVALID, S_TRUNK_C, c) // acquire transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions) transition(S_BRANCH, S_BRANCH_C, b && c) // acquire transition(S_BRANCH, S_TIP, b && m) // prefetch write transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_TIP_D, b && m) // MMIO write transition(S_BRANCH, S_TRUNK_C, b && c) // acquire transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH_C, S_INVALID, b && c && p) transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional) transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_TIP, S_INVALID, p) transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately transition(S_TIP, S_TRUNK_C, c) // acquire transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately transition(S_TIP_C, S_INVALID, c && p) transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_TIP, c) // probed while MMIO read \|\| clean release (optional) transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_TIP_C, S_TRUNK_C, c) // acquire transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty transition(S_TIP_D, S_INVALID, p) transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared transition(S_TIP_D, S_TIP, p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired transition(S_TIP_D, S_TRUNK_CD, c) // acquire transition(S_TIP_CD, S_INVALID, c && p) transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_CD, S_TIP_D, c) // MMIO write \|\| clean release (optional) transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire transition(S_TIP_CD, S_TRUNK_CD, c) // acquire transition(S_TRUNK_C, S_INVALID, c && p) transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_TIP, c) // MMIO read \|\| clean release (optional) transition(S_TRUNK_C, S_TIP_C, c) // bounce shared transition(S_TRUNK_C, S_TIP_D, c) // dirty release transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce transition(S_TRUNK_CD, S_INVALID, c && p) transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TRUNK_CD, S_TIP_D, c) // dirty release transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire } // Handle response messages val probe_bit = params.clientBit(io.sinkc.bits.source) val last_probe = (probes_done \| probe_bit) === (meta.clients & ~excluded_client) val probe_toN = isToN(io.sinkc.bits.param) if (!params.firstLevel) when (io.sinkc.valid) { params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B") params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B") // Caution: the probe matches us only in set. // We would never allow an outer probe to nest until both w_[rp]probeack complete, so // it is safe to just unguardedly update the probe FSM. probes_done := probes_done \| probe_bit probes_toN := probes_toN \| Mux(probe_toN, probe_bit, 0.U) probes_noT := probes_noT \|\| io.sinkc.bits.param =/= TtoT w_rprobeackfirst := w_rprobeackfirst \|\| last_probe w_rprobeacklast := w_rprobeacklast \|\| (last_probe && io.sinkc.bits.last) w_pprobeackfirst := w_pprobeackfirst \|\| last_probe w_pprobeacklast := w_pprobeacklast \|\| (last_probe && io.sinkc.bits.last) // Allow wormhole routing from sinkC if the first request beat has offset 0 val set_pprobeack = last_probe && (io.sinkc.bits.last \|\| request.offset === 0.U) w_pprobeack := w_pprobeack \|\| set_pprobeack params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data") params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data") // However, meta-data updates need to be done more cautiously when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!! } when (io.sinkd.valid) { when (io.sinkd.bits.opcode === Grant \|\| io.sinkd.bits.opcode === GrantData) { sink := io.sinkd.bits.sink w_grantfirst := true.B w_grantlast := io.sinkd.bits.last // Record if we need to prevent taking ownership bad_grant := io.sinkd.bits.denied // Allow wormhole routing for requests whose first beat has offset 0 w_grant := request.offset === 0.U \|\| io.sinkd.bits.last params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data") params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data") gotT := io.sinkd.bits.param === toT } .elsewhen (io.sinkd.bits.opcode === ReleaseAck) { w_releaseack := true.B } } when (io.sinke.valid) { w_grantack := true.B } // Bootstrap new requests val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits) val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits) val new_request = Mux(io.allocate.valid, allocate_as_full, request) val new_needT = needT(new_request.opcode, new_request.param) val new_clientBit = params.clientBit(new_request.source) val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U) val prior = cacheState(final_meta_writeback, true.B) def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}") } else { assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}") } } when (io.allocate.valid && io.allocate.bits.repeat) { bypass(S_INVALID, f \|\| p) // Can lose permissions (probe/flush) bypass(S_BRANCH, b) // MMIO read to read-only device bypass(S_BRANCH_C, b && c) // you need children to become C bypass(S_TIP, true) // MMIO read \|\| clean release can lead to this state bypass(S_TIP_C, c) // needs two clients \|\| client + mmio \|\| downgrading client bypass(S_TIP_CD, c) // needs two clients \|\| client + mmio \|\| downgrading client bypass(S_TIP_D, true) // MMIO write \|\| dirty release lead here bypass(S_TRUNK_C, c) // acquire for write bypass(S_TRUNK_CD, c) // dirty release then reacquire } when (io.allocate.valid) { assert (!request_valid \|\| (no_wait && io.schedule.fire)) request_valid := true.B request := io.allocate.bits } // Create execution plan when (io.directory.valid \|\| (io.allocate.valid && io.allocate.bits.repeat)) { meta_valid := true.B meta := new_meta probes_done := 0.U probes_toN := 0.U probes_noT := false.B gotT := false.B bad_grant := false.B // These should already be either true or turning true // We clear them here explicitly to simplify the mux tree s_rprobe := true.B w_rprobeackfirst := true.B w_rprobeacklast := true.B s_release := true.B w_releaseack := true.B s_pprobe := true.B s_acquire := true.B s_flush := true.B w_grantfirst := true.B w_grantlast := true.B w_grant := true.B w_pprobeackfirst := true.B w_pprobeacklast := true.B w_pprobeack := true.B s_probeack := true.B s_grantack := true.B s_execute := true.B w_grantack := true.B s_writeback := true.B // For C channel requests (ie: Release[Data]) when (new_request.prio(2) && (!params.firstLevel).B) { s_execute := false.B // Do we need to go dirty? when (new_request.opcode(0) && !new_meta.dirty) { s_writeback := false.B } // Does our state change? when (isToB(new_request.param) && new_meta.state === TRUNK) { s_writeback := false.B } // Do our clients change? when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) { s_writeback := false.B } assert (new_meta.hit) } // For X channel requests (ie: flush) .elsewhen (new_request.control && params.control.B) { // new_request.prio(0) s_flush := false.B // Do we need to actually do something? when (new_meta.hit) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } } // For A channel requests .otherwise { // new_request.prio(0) && !new_request.control s_execute := false.B // Do we need an eviction? when (!new_meta.hit && new_meta.state =/= INVALID) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } // Do we need an acquire? when (!new_meta.hit \|\| (new_meta.state === BRANCH && new_needT)) { s_acquire := false.B w_grantfirst := false.B w_grantlast := false.B w_grant := false.B s_grantack := false.B s_writeback := false.B } // Do we need a probe? when ((!params.firstLevel).B && (new_meta.hit && (new_needT \|\| new_meta.state === TRUNK) && (new_meta.clients & ~new_skipProbe) =/= 0.U)) { s_pprobe := false.B w_pprobeackfirst := false.B w_pprobeacklast := false.B w_pprobeack := false.B s_writeback := false.B } // Do we need a grantack? when (new_request.opcode === AcquireBlock \|\| new_request.opcode === AcquirePerm) { w_grantack := false.B s_writeback := false.B } // Becomes dirty? when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) { s_writeback := false.B } } } } File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relListscache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_\|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x \| 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ \|\| _) (matches, bits.U) } expanded \| Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) \|\| (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) \|\| ((opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm \|\| opcode === TLMessages.Get \|\| (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN \|\| param === TLPermissions.BtoN \|\| param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB \|\| param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle	module MSHR_4( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input [5:0] io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire [5:0] final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire [5:0] io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [5:0] invalid_clients = 6'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire [5:0] _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire [5:0] _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg [5:0] meta_clients; // @[MSHR.scala:100:17] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg [5:0] probes_done; // @[MSHR.scala:150:24] reg [5:0] probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire [5:0] _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire _req_clientBit_T = request_source == 6'h24; // @[Parameters.scala:46:9] wire _req_clientBit_T_1 = request_source == 6'h2E; // @[Parameters.scala:46:9] wire _req_clientBit_T_2 = request_source == 6'h2C; // @[Parameters.scala:46:9] wire _req_clientBit_T_3 = request_source == 6'h2A; // @[Parameters.scala:46:9] wire _req_clientBit_T_4 = request_source == 6'h28; // @[Parameters.scala:46:9] wire _req_clientBit_T_5 = request_source == 6'h20; // @[Parameters.scala:46:9] wire [1:0] req_clientBit_lo_hi = {_req_clientBit_T_2, _req_clientBit_T_1}; // @[Parameters.scala:46:9] wire [2:0] req_clientBit_lo = {req_clientBit_lo_hi, _req_clientBit_T}; // @[Parameters.scala:46:9] wire [1:0] req_clientBit_hi_hi = {_req_clientBit_T_5, _req_clientBit_T_4}; // @[Parameters.scala:46:9] wire [2:0] req_clientBit_hi = {req_clientBit_hi_hi, _req_clientBit_T_3}; // @[Parameters.scala:46:9] wire [5:0] req_clientBit = {req_clientBit_hi, req_clientBit_lo}; // @[Parameters.scala:201:10] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire _meta_no_clients_T = \|meta_clients; // @[MSHR.scala:100:17, :220:39] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire [5:0] _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 ? req_clientBit : 6'h0; // @[Parameters.scala:201:10, :282:66] wire [5:0] _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire [5:0] _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire [5:0] _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire [5:0] _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire [5:0] _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire [5:0] _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire [5:0] _final_meta_writeback_clients_T_12 = meta_hit ? _final_meta_writeback_clients_T_11 : 6'h0; // @[MSHR.scala:100:17, :245:{40,64}] wire [5:0] _final_meta_writeback_clients_T_13 = req_acquire ? req_clientBit : 6'h0; // @[Parameters.scala:201:10] wire [5:0] _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire [5:0] _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire [5:0] _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? (meta_hit ? _final_meta_writeback_clients_T_16 : 6'h0) : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire [5:0] _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:201:10] wire _honour_BtoT_T_1 = \|_honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire [5:0] excluded_client = _excluded_client_T_9 ? req_clientBit : 6'h0; // @[Parameters.scala:201:10] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire [5:0] _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = _io_schedule_bits_dir_bits_data_T ? 6'h0 : _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire evict_c = \|meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire before_c = \|meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire after_c = \|final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _probe_bit_T = io_sinkc_bits_source_0 == 6'h24; // @[Parameters.scala:46:9] wire _probe_bit_T_1 = io_sinkc_bits_source_0 == 6'h2E; // @[Parameters.scala:46:9] wire _probe_bit_T_2 = io_sinkc_bits_source_0 == 6'h2C; // @[Parameters.scala:46:9] wire _probe_bit_T_3 = io_sinkc_bits_source_0 == 6'h2A; // @[Parameters.scala:46:9] wire _probe_bit_T_4 = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9] wire _probe_bit_T_5 = io_sinkc_bits_source_0 == 6'h20; // @[Parameters.scala:46:9] wire [1:0] probe_bit_lo_hi = {_probe_bit_T_2, _probe_bit_T_1}; // @[Parameters.scala:46:9] wire [2:0] probe_bit_lo = {probe_bit_lo_hi, _probe_bit_T}; // @[Parameters.scala:46:9] wire [1:0] probe_bit_hi_hi = {_probe_bit_T_5, _probe_bit_T_4}; // @[Parameters.scala:46:9] wire [2:0] probe_bit_hi = {probe_bit_hi_hi, _probe_bit_T_3}; // @[Parameters.scala:46:9] wire [5:0] probe_bit = {probe_bit_hi, probe_bit_lo}; // @[Parameters.scala:201:10] wire [5:0] _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:201:10] wire [5:0] _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire [5:0] _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire [5:0] _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire [5:0] _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire [5:0] _probes_toN_T = probe_toN ? probe_bit : 6'h0; // @[Parameters.scala:201:10, :282:66] wire [5:0] _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [5:0] new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _new_clientBit_T = new_request_source == 6'h24; // @[Parameters.scala:46:9] wire _new_clientBit_T_1 = new_request_source == 6'h2E; // @[Parameters.scala:46:9] wire _new_clientBit_T_2 = new_request_source == 6'h2C; // @[Parameters.scala:46:9] wire _new_clientBit_T_3 = new_request_source == 6'h2A; // @[Parameters.scala:46:9] wire _new_clientBit_T_4 = new_request_source == 6'h28; // @[Parameters.scala:46:9] wire _new_clientBit_T_5 = new_request_source == 6'h20; // @[Parameters.scala:46:9] wire [1:0] new_clientBit_lo_hi = {_new_clientBit_T_2, _new_clientBit_T_1}; // @[Parameters.scala:46:9] wire [2:0] new_clientBit_lo = {new_clientBit_lo_hi, _new_clientBit_T}; // @[Parameters.scala:46:9] wire [1:0] new_clientBit_hi_hi = {_new_clientBit_T_5, _new_clientBit_T_4}; // @[Parameters.scala:46:9] wire [2:0] new_clientBit_hi = {new_clientBit_hi_hi, _new_clientBit_T_3}; // @[Parameters.scala:46:9] wire [5:0] new_clientBit = {new_clientBit_hi, new_clientBit_lo}; // @[Parameters.scala:201:10] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire [5:0] new_skipProbe = _new_skipProbe_T_7 ? new_clientBit : 6'h0; // @[Parameters.scala:201:10, :279:106] wire [3:0] prior; // @[MSHR.scala:314:26] wire prior_c = \|final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry / case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic / val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U \| in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } / Write request logic / // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) \| usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U \| in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) / Read/write response logic / val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied \|\| out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B / Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. / def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } / ReservableListBuffer logic, and associated classes. / class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /* Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. / abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /* A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index / class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) \| validSet used := (used & ~usedClr) \| usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) \| dataIsPresentSet / Reservation logic signals / val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) / Response logic signals / val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) / Reservation logic / reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } / Response logic / // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } / Response unwind logic / // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent \|\| isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind \|\| (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind \|\| (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready \|\| !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire \|\| unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /* Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) \| usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }	module dataMems_97( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File MSHR.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import freechips.rocketchip.tilelink._ import TLPermissions._ import TLMessages._ import MetaData._ import chisel3.PrintableHelper import chisel3.experimental.dataview._ class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val a = Valid(new SourceARequest(params)) val b = Valid(new SourceBRequest(params)) val c = Valid(new SourceCRequest(params)) val d = Valid(new SourceDRequest(params)) val e = Valid(new SourceERequest(params)) val x = Valid(new SourceXRequest(params)) val dir = Valid(new DirectoryWrite(params)) val reload = Bool() // get next request via allocate (if any) } class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val way = UInt(params.wayBits.W) val blockB = Bool() val nestB = Bool() val blockC = Bool() val nestC = Bool() } class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val b_toN = Bool() // nested Probes may unhit us val b_toB = Bool() // nested Probes may demote us val b_clr_dirty = Bool() // nested Probes clear dirty val c_set_dirty = Bool() // nested Releases MAY set dirty } sealed trait CacheState { val code = CacheState.index.U CacheState.index = CacheState.index + 1 } object CacheState { var index = 0 } case object S_INVALID extends CacheState case object S_BRANCH extends CacheState case object S_BRANCH_C extends CacheState case object S_TIP extends CacheState case object S_TIP_C extends CacheState case object S_TIP_CD extends CacheState case object S_TIP_D extends CacheState case object S_TRUNK_C extends CacheState case object S_TRUNK_CD extends CacheState class MSHR(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup val status = Valid(new MSHRStatus(params)) val schedule = Decoupled(new ScheduleRequest(params)) val sinkc = Flipped(Valid(new SinkCResponse(params))) val sinkd = Flipped(Valid(new SinkDResponse(params))) val sinke = Flipped(Valid(new SinkEResponse(params))) val nestedwb = Flipped(new NestedWriteback(params)) }) val request_valid = RegInit(false.B) val request = Reg(new FullRequest(params)) val meta_valid = RegInit(false.B) val meta = Reg(new DirectoryResult(params)) // Define which states are valid when (meta_valid) { when (meta.state === INVALID) { assert (!meta.clients.orR) assert (!meta.dirty) } when (meta.state === BRANCH) { assert (!meta.dirty) } when (meta.state === TRUNK) { assert (meta.clients.orR) assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one } when (meta.state === TIP) { // noop } } // Completed transitions (s_ = scheduled), (w_ = waiting) val s_rprobe = RegInit(true.B) // B val w_rprobeackfirst = RegInit(true.B) val w_rprobeacklast = RegInit(true.B) val s_release = RegInit(true.B) // CW w_rprobeackfirst val w_releaseack = RegInit(true.B) val s_pprobe = RegInit(true.B) // B val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1] val s_flush = RegInit(true.B) // X w_releaseack val w_grantfirst = RegInit(true.B) val w_grantlast = RegInit(true.B) val w_grant = RegInit(true.B) // first \| last depending on wormhole val w_pprobeackfirst = RegInit(true.B) val w_pprobeacklast = RegInit(true.B) val w_pprobeack = RegInit(true.B) // first \| last depending on wormhole val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_) val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD val s_execute = RegInit(true.B) // D w_pprobeack, w_grant val w_grantack = RegInit(true.B) val s_writeback = RegInit(true.B) // W w_* // [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall) // However, inB and outC are higher priority than outB, so s_release and s_pprobe // may be safely issued while blockB. Thus we must NOT try to schedule the // potentially stuck s_acquire with either of them (scheduler is all or none). // Meta-data that we discover underway val sink = Reg(UInt(params.outer.bundle.sinkBits.W)) val gotT = Reg(Bool()) val bad_grant = Reg(Bool()) val probes_done = Reg(UInt(params.clientBits.W)) val probes_toN = Reg(UInt(params.clientBits.W)) val probes_noT = Reg(Bool()) // When a nested transaction completes, update our meta data when (meta_valid && meta.state =/= INVALID && io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) { when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B } when (io.nestedwb.c_set_dirty) { meta.dirty := true.B } when (io.nestedwb.b_toB) { meta.state := BRANCH } when (io.nestedwb.b_toN) { meta.hit := false.B } } // Scheduler status io.status.valid := request_valid io.status.bits.set := request.set io.status.bits.tag := request.tag io.status.bits.way := meta.way io.status.bits.blockB := !meta_valid \|\| ((!w_releaseack \|\| !w_rprobeacklast \|\| !w_pprobeacklast) && !w_grantfirst) io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst // The above rules ensure we will block and not nest an outer probe while still doing our // own inner probes. Thus every probe wakes exactly one MSHR. io.status.bits.blockC := !meta_valid io.status.bits.nestC := meta_valid && (!w_rprobeackfirst \|\| !w_pprobeackfirst \|\| !w_grantfirst) // The w_grantfirst in nestC is necessary to deal with: // acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock // ... this is possible because the release+probe can be for same set, but different tag // We can only demand: block, nest, or queue assert (!io.status.bits.nestB \|\| !io.status.bits.blockB) assert (!io.status.bits.nestC \|\| !io.status.bits.blockC) // Scheduler requests val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe io.schedule.bits.b.valid := !s_rprobe \|\| !s_pprobe io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) \|\| (!s_probeack && w_pprobeackfirst) io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant io.schedule.bits.e.valid := !s_grantack && w_grantfirst io.schedule.bits.x.valid := !s_flush && w_releaseack io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) \|\| (!s_writeback && no_wait) io.schedule.bits.reload := no_wait io.schedule.valid := io.schedule.bits.a.valid \|\| io.schedule.bits.b.valid \|\| io.schedule.bits.c.valid \|\| io.schedule.bits.d.valid \|\| io.schedule.bits.e.valid \|\| io.schedule.bits.x.valid \|\| io.schedule.bits.dir.valid // Schedule completions when (io.schedule.ready) { s_rprobe := true.B when (w_rprobeackfirst) { s_release := true.B } s_pprobe := true.B when (s_release && s_pprobe) { s_acquire := true.B } when (w_releaseack) { s_flush := true.B } when (w_pprobeackfirst) { s_probeack := true.B } when (w_grantfirst) { s_grantack := true.B } when (w_pprobeack && w_grant) { s_execute := true.B } when (no_wait) { s_writeback := true.B } // Await the next operation when (no_wait) { request_valid := false.B meta_valid := false.B } } // Resulting meta-data val final_meta_writeback = WireInit(meta) val req_clientBit = params.clientBit(request.source) val req_needT = needT(request.opcode, request.param) val req_acquire = request.opcode === AcquireBlock \|\| request.opcode === AcquirePerm val meta_no_clients = !meta.clients.orR val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT) when (request.prio(2) && (!params.firstLevel).B) { // always a hit final_meta_writeback.dirty := meta.dirty \|\| request.opcode(0) final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state) final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U) final_meta_writeback.hit := true.B // chained requests are hits } .elsewhen (request.control && params.control.B) { // request.prio(0) when (meta.hit) { final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := meta.clients & ~probes_toN } final_meta_writeback.hit := false.B } .otherwise { final_meta_writeback.dirty := (meta.hit && meta.dirty) \|\| !request.opcode(2) final_meta_writeback.state := Mux(req_needT, Mux(req_acquire, TRUNK, TIP), Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH), MuxLookup(meta.state, 0.U(2.W))(Seq( INVALID -> BRANCH, BRANCH -> BRANCH, TRUNK -> TIP, TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP))))) final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) \| Mux(req_acquire, req_clientBit, 0.U) final_meta_writeback.tag := request.tag final_meta_writeback.hit := true.B } when (bad_grant) { when (meta.hit) { // upgrade failed (B -> T) assert (!meta_valid \|\| meta.state === BRANCH) final_meta_writeback.hit := true.B final_meta_writeback.dirty := false.B final_meta_writeback.state := BRANCH final_meta_writeback.clients := meta.clients & ~probes_toN } .otherwise { // failed N -> (T or B) final_meta_writeback.hit := false.B final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := 0.U } } val invalid = Wire(new DirectoryEntry(params)) invalid.dirty := false.B invalid.state := INVALID invalid.clients := 0.U invalid.tag := 0.U // Just because a client says BtoT, by the time we process the request he may be N. // Therefore, we must consult our own meta-data state to confirm he owns the line still. val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR // The client asking us to act is proof they don't have permissions. val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U) io.schedule.bits.a.bits.tag := request.tag io.schedule.bits.a.bits.set := request.set io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB) io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U \|\| !(request.opcode === PutFullData \|\| request.opcode === AcquirePerm) io.schedule.bits.a.bits.source := 0.U io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB))) io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag) io.schedule.bits.b.bits.set := request.set io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release) io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN) io.schedule.bits.c.bits.source := 0.U io.schedule.bits.c.bits.tag := meta.tag io.schedule.bits.c.bits.set := request.set io.schedule.bits.c.bits.way := meta.way io.schedule.bits.c.bits.dirty := meta.dirty io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param, MuxLookup(request.param, request.param)(Seq( NtoB -> Mux(req_promoteT, NtoT, NtoB), BtoT -> Mux(honour_BtoT, BtoT, NtoT), NtoT -> NtoT))) io.schedule.bits.d.bits.sink := 0.U io.schedule.bits.d.bits.way := meta.way io.schedule.bits.d.bits.bad := bad_grant io.schedule.bits.e.bits.sink := sink io.schedule.bits.x.bits.fail := false.B io.schedule.bits.dir.bits.set := request.set io.schedule.bits.dir.bits.way := meta.way io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback)) // Coverage of state transitions def cacheState(entry: DirectoryEntry, hit: Bool) = { val out = WireDefault(0.U) val c = entry.clients.orR val d = entry.dirty switch (entry.state) { is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) } is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) } is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) } is (INVALID) { out := S_INVALID.code } } when (!hit) { out := S_INVALID.code } out } val p = !params.lastLevel // can be probed val c = !params.firstLevel // can be acquired val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read) val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist val f = params.control // flush control register exists val cfg = (p, c, m, r, f) val b = r \|\| p // can reach branch state (via probe downgrade or read-only device) // The cache must be used for something or we would not be here require(c \|\| m) val evict = cacheState(meta, !meta.hit) val before = cacheState(meta, meta.hit) val after = cacheState(final_meta_writeback, true.B) def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}") } else { assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}") } if (cover && f) { params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}") } else { assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}") } } def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}") } else { assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}") } } when ((!s_release && w_rprobeackfirst) && io.schedule.ready) { eviction(S_BRANCH, b) // MMIO read to read-only device eviction(S_BRANCH_C, b && c) // you need children to become C eviction(S_TIP, true) // MMIO read \|\| clean release can lead to this state eviction(S_TIP_C, c) // needs two clients \|\| client + mmio \|\| downgrading client eviction(S_TIP_CD, c) // needs two clients \|\| client + mmio \|\| downgrading client eviction(S_TIP_D, true) // MMIO write \|\| dirty release lead here eviction(S_TRUNK_C, c) // acquire for write eviction(S_TRUNK_CD, c) // dirty release then reacquire } when ((!s_writeback && no_wait) && io.schedule.ready) { transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches transition(S_INVALID, S_TIP, m) // MMIO read transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_INVALID, S_TIP_D, m) // MMIO write transition(S_INVALID, S_TRUNK_C, c) // acquire transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions) transition(S_BRANCH, S_BRANCH_C, b && c) // acquire transition(S_BRANCH, S_TIP, b && m) // prefetch write transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_TIP_D, b && m) // MMIO write transition(S_BRANCH, S_TRUNK_C, b && c) // acquire transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH_C, S_INVALID, b && c && p) transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional) transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_TIP, S_INVALID, p) transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately transition(S_TIP, S_TRUNK_C, c) // acquire transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately transition(S_TIP_C, S_INVALID, c && p) transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_TIP, c) // probed while MMIO read \|\| clean release (optional) transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_TIP_C, S_TRUNK_C, c) // acquire transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty transition(S_TIP_D, S_INVALID, p) transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared transition(S_TIP_D, S_TIP, p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired transition(S_TIP_D, S_TRUNK_CD, c) // acquire transition(S_TIP_CD, S_INVALID, c && p) transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_CD, S_TIP_D, c) // MMIO write \|\| clean release (optional) transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire transition(S_TIP_CD, S_TRUNK_CD, c) // acquire transition(S_TRUNK_C, S_INVALID, c && p) transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_TIP, c) // MMIO read \|\| clean release (optional) transition(S_TRUNK_C, S_TIP_C, c) // bounce shared transition(S_TRUNK_C, S_TIP_D, c) // dirty release transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce transition(S_TRUNK_CD, S_INVALID, c && p) transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TRUNK_CD, S_TIP_D, c) // dirty release transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire } // Handle response messages val probe_bit = params.clientBit(io.sinkc.bits.source) val last_probe = (probes_done \| probe_bit) === (meta.clients & ~excluded_client) val probe_toN = isToN(io.sinkc.bits.param) if (!params.firstLevel) when (io.sinkc.valid) { params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B") params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B") // Caution: the probe matches us only in set. // We would never allow an outer probe to nest until both w_[rp]probeack complete, so // it is safe to just unguardedly update the probe FSM. probes_done := probes_done \| probe_bit probes_toN := probes_toN \| Mux(probe_toN, probe_bit, 0.U) probes_noT := probes_noT \|\| io.sinkc.bits.param =/= TtoT w_rprobeackfirst := w_rprobeackfirst \|\| last_probe w_rprobeacklast := w_rprobeacklast \|\| (last_probe && io.sinkc.bits.last) w_pprobeackfirst := w_pprobeackfirst \|\| last_probe w_pprobeacklast := w_pprobeacklast \|\| (last_probe && io.sinkc.bits.last) // Allow wormhole routing from sinkC if the first request beat has offset 0 val set_pprobeack = last_probe && (io.sinkc.bits.last \|\| request.offset === 0.U) w_pprobeack := w_pprobeack \|\| set_pprobeack params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data") params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data") // However, meta-data updates need to be done more cautiously when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!! } when (io.sinkd.valid) { when (io.sinkd.bits.opcode === Grant \|\| io.sinkd.bits.opcode === GrantData) { sink := io.sinkd.bits.sink w_grantfirst := true.B w_grantlast := io.sinkd.bits.last // Record if we need to prevent taking ownership bad_grant := io.sinkd.bits.denied // Allow wormhole routing for requests whose first beat has offset 0 w_grant := request.offset === 0.U \|\| io.sinkd.bits.last params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data") params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data") gotT := io.sinkd.bits.param === toT } .elsewhen (io.sinkd.bits.opcode === ReleaseAck) { w_releaseack := true.B } } when (io.sinke.valid) { w_grantack := true.B } // Bootstrap new requests val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits) val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits) val new_request = Mux(io.allocate.valid, allocate_as_full, request) val new_needT = needT(new_request.opcode, new_request.param) val new_clientBit = params.clientBit(new_request.source) val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U) val prior = cacheState(final_meta_writeback, true.B) def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}") } else { assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}") } } when (io.allocate.valid && io.allocate.bits.repeat) { bypass(S_INVALID, f \|\| p) // Can lose permissions (probe/flush) bypass(S_BRANCH, b) // MMIO read to read-only device bypass(S_BRANCH_C, b && c) // you need children to become C bypass(S_TIP, true) // MMIO read \|\| clean release can lead to this state bypass(S_TIP_C, c) // needs two clients \|\| client + mmio \|\| downgrading client bypass(S_TIP_CD, c) // needs two clients \|\| client + mmio \|\| downgrading client bypass(S_TIP_D, true) // MMIO write \|\| dirty release lead here bypass(S_TRUNK_C, c) // acquire for write bypass(S_TRUNK_CD, c) // dirty release then reacquire } when (io.allocate.valid) { assert (!request_valid \|\| (no_wait && io.schedule.fire)) request_valid := true.B request := io.allocate.bits } // Create execution plan when (io.directory.valid \|\| (io.allocate.valid && io.allocate.bits.repeat)) { meta_valid := true.B meta := new_meta probes_done := 0.U probes_toN := 0.U probes_noT := false.B gotT := false.B bad_grant := false.B // These should already be either true or turning true // We clear them here explicitly to simplify the mux tree s_rprobe := true.B w_rprobeackfirst := true.B w_rprobeacklast := true.B s_release := true.B w_releaseack := true.B s_pprobe := true.B s_acquire := true.B s_flush := true.B w_grantfirst := true.B w_grantlast := true.B w_grant := true.B w_pprobeackfirst := true.B w_pprobeacklast := true.B w_pprobeack := true.B s_probeack := true.B s_grantack := true.B s_execute := true.B w_grantack := true.B s_writeback := true.B // For C channel requests (ie: Release[Data]) when (new_request.prio(2) && (!params.firstLevel).B) { s_execute := false.B // Do we need to go dirty? when (new_request.opcode(0) && !new_meta.dirty) { s_writeback := false.B } // Does our state change? when (isToB(new_request.param) && new_meta.state === TRUNK) { s_writeback := false.B } // Do our clients change? when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) { s_writeback := false.B } assert (new_meta.hit) } // For X channel requests (ie: flush) .elsewhen (new_request.control && params.control.B) { // new_request.prio(0) s_flush := false.B // Do we need to actually do something? when (new_meta.hit) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } } // For A channel requests .otherwise { // new_request.prio(0) && !new_request.control s_execute := false.B // Do we need an eviction? when (!new_meta.hit && new_meta.state =/= INVALID) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } // Do we need an acquire? when (!new_meta.hit \|\| (new_meta.state === BRANCH && new_needT)) { s_acquire := false.B w_grantfirst := false.B w_grantlast := false.B w_grant := false.B s_grantack := false.B s_writeback := false.B } // Do we need a probe? when ((!params.firstLevel).B && (new_meta.hit && (new_needT \|\| new_meta.state === TRUNK) && (new_meta.clients & ~new_skipProbe) =/= 0.U)) { s_pprobe := false.B w_pprobeackfirst := false.B w_pprobeacklast := false.B w_pprobeack := false.B s_writeback := false.B } // Do we need a grantack? when (new_request.opcode === AcquireBlock \|\| new_request.opcode === AcquirePerm) { w_grantack := false.B s_writeback := false.B } // Becomes dirty? when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) { s_writeback := false.B } } } } File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relListscache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_\|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x \| 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ \|\| _) (matches, bits.U) } expanded \| Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) \|\| (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) \|\| ((opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm \|\| opcode === TLMessages.Get \|\| (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN \|\| param === TLPermissions.BtoN \|\| param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB \|\| param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle	module MSHR_4( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input [7:0] io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output [7:0] io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output [7:0] io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire [7:0] final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire [7:0] io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [7:0] invalid_clients = 8'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire [7:0] _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire [7:0] _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire [7:0] io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire [7:0] io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg [7:0] meta_clients; // @[MSHR.scala:100:17] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg [7:0] probes_done; // @[MSHR.scala:150:24] reg [7:0] probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire [7:0] _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire _req_clientBit_T = request_source == 6'h3C; // @[Parameters.scala:46:9] wire _req_clientBit_T_1 = request_source == 6'h38; // @[Parameters.scala:46:9] wire _req_clientBit_T_2 = request_source == 6'h34; // @[Parameters.scala:46:9] wire _req_clientBit_T_3 = request_source == 6'h30; // @[Parameters.scala:46:9] wire _req_clientBit_T_4 = request_source == 6'h2C; // @[Parameters.scala:46:9] wire _req_clientBit_T_5 = request_source == 6'h28; // @[Parameters.scala:46:9] wire _req_clientBit_T_6 = request_source == 6'h24; // @[Parameters.scala:46:9] wire _req_clientBit_T_7 = request_source == 6'h20; // @[Parameters.scala:46:9] wire [1:0] req_clientBit_lo_lo = {_req_clientBit_T_1, _req_clientBit_T}; // @[Parameters.scala:46:9] wire [1:0] req_clientBit_lo_hi = {_req_clientBit_T_3, _req_clientBit_T_2}; // @[Parameters.scala:46:9] wire [3:0] req_clientBit_lo = {req_clientBit_lo_hi, req_clientBit_lo_lo}; // @[Parameters.scala:201:10] wire [1:0] req_clientBit_hi_lo = {_req_clientBit_T_5, _req_clientBit_T_4}; // @[Parameters.scala:46:9] wire [1:0] req_clientBit_hi_hi = {_req_clientBit_T_7, _req_clientBit_T_6}; // @[Parameters.scala:46:9] wire [3:0] req_clientBit_hi = {req_clientBit_hi_hi, req_clientBit_hi_lo}; // @[Parameters.scala:201:10] wire [7:0] req_clientBit = {req_clientBit_hi, req_clientBit_lo}; // @[Parameters.scala:201:10] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire _meta_no_clients_T = \|meta_clients; // @[MSHR.scala:100:17, :220:39] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire [7:0] _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 ? req_clientBit : 8'h0; // @[Parameters.scala:201:10, :282:66] wire [7:0] _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire [7:0] _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire [7:0] _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire [7:0] _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire [7:0] _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire [7:0] _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire [7:0] _final_meta_writeback_clients_T_12 = meta_hit ? _final_meta_writeback_clients_T_11 : 8'h0; // @[MSHR.scala:100:17, :245:{40,64}] wire [7:0] _final_meta_writeback_clients_T_13 = req_acquire ? req_clientBit : 8'h0; // @[Parameters.scala:201:10] wire [7:0] _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire [7:0] _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire [7:0] _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? (meta_hit ? _final_meta_writeback_clients_T_16 : 8'h0) : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire [7:0] _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:201:10] wire _honour_BtoT_T_1 = \|_honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire [7:0] excluded_client = _excluded_client_T_9 ? req_clientBit : 8'h0; // @[Parameters.scala:201:10] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire [7:0] _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = _io_schedule_bits_dir_bits_data_T ? 8'h0 : _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire evict_c = \|meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire before_c = \|meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire after_c = \|final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _probe_bit_T = io_sinkc_bits_source_0 == 6'h3C; // @[Parameters.scala:46:9] wire _probe_bit_T_1 = io_sinkc_bits_source_0 == 6'h38; // @[Parameters.scala:46:9] wire _probe_bit_T_2 = io_sinkc_bits_source_0 == 6'h34; // @[Parameters.scala:46:9] wire _probe_bit_T_3 = io_sinkc_bits_source_0 == 6'h30; // @[Parameters.scala:46:9] wire _probe_bit_T_4 = io_sinkc_bits_source_0 == 6'h2C; // @[Parameters.scala:46:9] wire _probe_bit_T_5 = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9] wire _probe_bit_T_6 = io_sinkc_bits_source_0 == 6'h24; // @[Parameters.scala:46:9] wire _probe_bit_T_7 = io_sinkc_bits_source_0 == 6'h20; // @[Parameters.scala:46:9] wire [1:0] probe_bit_lo_lo = {_probe_bit_T_1, _probe_bit_T}; // @[Parameters.scala:46:9] wire [1:0] probe_bit_lo_hi = {_probe_bit_T_3, _probe_bit_T_2}; // @[Parameters.scala:46:9] wire [3:0] probe_bit_lo = {probe_bit_lo_hi, probe_bit_lo_lo}; // @[Parameters.scala:201:10] wire [1:0] probe_bit_hi_lo = {_probe_bit_T_5, _probe_bit_T_4}; // @[Parameters.scala:46:9] wire [1:0] probe_bit_hi_hi = {_probe_bit_T_7, _probe_bit_T_6}; // @[Parameters.scala:46:9] wire [3:0] probe_bit_hi = {probe_bit_hi_hi, probe_bit_hi_lo}; // @[Parameters.scala:201:10] wire [7:0] probe_bit = {probe_bit_hi, probe_bit_lo}; // @[Parameters.scala:201:10] wire [7:0] _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:201:10] wire [7:0] _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire [7:0] _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire [7:0] _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire [7:0] _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire [7:0] _probes_toN_T = probe_toN ? probe_bit : 8'h0; // @[Parameters.scala:201:10, :282:66] wire [7:0] _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [7:0] new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _new_clientBit_T = new_request_source == 6'h3C; // @[Parameters.scala:46:9] wire _new_clientBit_T_1 = new_request_source == 6'h38; // @[Parameters.scala:46:9] wire _new_clientBit_T_2 = new_request_source == 6'h34; // @[Parameters.scala:46:9] wire _new_clientBit_T_3 = new_request_source == 6'h30; // @[Parameters.scala:46:9] wire _new_clientBit_T_4 = new_request_source == 6'h2C; // @[Parameters.scala:46:9] wire _new_clientBit_T_5 = new_request_source == 6'h28; // @[Parameters.scala:46:9] wire _new_clientBit_T_6 = new_request_source == 6'h24; // @[Parameters.scala:46:9] wire _new_clientBit_T_7 = new_request_source == 6'h20; // @[Parameters.scala:46:9] wire [1:0] new_clientBit_lo_lo = {_new_clientBit_T_1, _new_clientBit_T}; // @[Parameters.scala:46:9] wire [1:0] new_clientBit_lo_hi = {_new_clientBit_T_3, _new_clientBit_T_2}; // @[Parameters.scala:46:9] wire [3:0] new_clientBit_lo = {new_clientBit_lo_hi, new_clientBit_lo_lo}; // @[Parameters.scala:201:10] wire [1:0] new_clientBit_hi_lo = {_new_clientBit_T_5, _new_clientBit_T_4}; // @[Parameters.scala:46:9] wire [1:0] new_clientBit_hi_hi = {_new_clientBit_T_7, _new_clientBit_T_6}; // @[Parameters.scala:46:9] wire [3:0] new_clientBit_hi = {new_clientBit_hi_hi, new_clientBit_hi_lo}; // @[Parameters.scala:201:10] wire [7:0] new_clientBit = {new_clientBit_hi, new_clientBit_lo}; // @[Parameters.scala:201:10] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire [7:0] new_skipProbe = _new_skipProbe_T_7 ? new_clientBit : 8'h0; // @[Parameters.scala:201:10, :279:106] wire [3:0] prior; // @[MSHR.scala:314:26] wire prior_c = \|final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_45( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire [26:0] _GEN_0 = {23'h0, io_in_c_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [7:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [2:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35] reg [7:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [2:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [7:0] b_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg [2:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35] reg [7:0] c_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [2:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [4:0] inflight; // @[Monitor.scala:614:27] reg [19:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire [7:0] _GEN_1 = {5'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [7:0] _GEN_4 = {5'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [4:0] inflight_1; // @[Monitor.scala:726:35] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [7:0] c_first_counter_1; // @[Edges.scala:229:27] wire c_first_1 = c_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}] wire [7:0] _GEN_6 = {5'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35] wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] reg [15:0] inflight_2; // @[Monitor.scala:828:27] reg [7:0] d_first_counter_3; // @[Edges.scala:229:27] wire d_first_3 = d_first_counter_3 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35] wire [15:0] _GEN_9 = {12'h0, io_in_d_bits_sink}; // @[OneHot.scala:58:35] wire [15:0] d_set = _GEN_8 ? 16'h1 << _GEN_9 : 16'h0; // @[OneHot.scala:58:35] wire _GEN_10 = io_in_e_ready & io_in_e_valid; // @[Decoupled.scala:51:35] wire [15:0] _GEN_11 = {12'h0, io_in_e_bits_sink}; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to the following Chisel files. File issue-unit-age-ordered.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Logic //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.Str import boom.v4.common._ class IssueUnitCollapsing( params: IssueParams, numWakeupPorts: Int) (implicit p: Parameters) extends IssueUnit(params, numWakeupPorts) { //------------------------------------------------------------- // Set up the dispatch uops // special case "storing" 2 uops within one issue slot. val dis_uops = Array.fill(dispatchWidth) {Wire(new MicroOp())} for (w <- 0 until dispatchWidth) { dis_uops(w) := io.dis_uops(w).bits dis_uops(w).iw_issued := false.B dis_uops(w).iw_issued_partial_agen := false.B dis_uops(w).iw_issued_partial_dgen := false.B dis_uops(w).iw_p1_bypass_hint := false.B dis_uops(w).iw_p2_bypass_hint := false.B dis_uops(w).iw_p3_bypass_hint := false.B // Handle wakeups on dispatch val prs1_matches = io.wakeup_ports.map { wu => wu.bits.uop.pdst === io.dis_uops(w).bits.prs1 } val prs2_matches = io.wakeup_ports.map { wu => wu.bits.uop.pdst === io.dis_uops(w).bits.prs2 } val prs3_matches = io.wakeup_ports.map { wu => wu.bits.uop.pdst === io.dis_uops(w).bits.prs3 } val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (wu,m) => wu.valid && m } val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (wu,m) => wu.valid && m } val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (wu,m) => wu.valid && m } val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (wu,m) => wu.bits.rebusy && m } val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (wu,m) => wu.bits.rebusy && m } val bypassables = io.wakeup_ports.map { wu => wu.bits.bypassable } val speculative_masks = io.wakeup_ports.map { wu => wu.bits.speculative_mask } when (prs1_wakeups.reduce(_\|\|_)) { dis_uops(w).prs1_busy := false.B dis_uops(w).iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks) dis_uops(w).iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables) } when (prs1_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & io.dis_uops(w).bits.iw_p1_speculative_child) =/= 0.U)) { dis_uops(w).prs1_busy := io.dis_uops(w).bits.lrs1_rtype === RT_FIX } when (prs2_wakeups.reduce(_\|\|_)) { dis_uops(w).prs2_busy := false.B dis_uops(w).iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks) dis_uops(w).iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables) } when (prs2_rebusys.reduce(_\|\|_) \|\| ((io.child_rebusys & io.dis_uops(w).bits.iw_p2_speculative_child) =/= 0.U)) { dis_uops(w).prs2_busy := io.dis_uops(w).bits.lrs2_rtype === RT_FIX } when (prs3_wakeups.reduce(_\|\|_)) { dis_uops(w).prs3_busy := false.B dis_uops(w).iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables) } when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === io.dis_uops(w).bits.ppred) { dis_uops(w).ppred_busy := false.B } if (iqType == IQ_UNQ) { when (io.dis_uops(w).bits.fu_code(FC_I2F)) { dis_uops(w).prs2 := Cat(io.dis_uops(w).bits.fp_rm, io.dis_uops(w).bits.fp_typ) } when (io.dis_uops(w).bits.is_sfence) { dis_uops(w).pimm := io.dis_uops(w).bits.mem_size } } if (iqType == IQ_MEM) { // For store addr gen for FP, rs2 is the FP register, and we don't wait for that here when (io.dis_uops(w).bits.uses_stq && io.dis_uops(w).bits.lrs2_rtype === RT_FLT) { dis_uops(w).lrs2_rtype := RT_X dis_uops(w).prs2_busy := false.B } dis_uops(w).prs3_busy := false.B } else if (iqType == IQ_FP) { // FP "StoreAddrGen" is really storeDataGen, and rs1 is the integer address register when (io.dis_uops(w).bits.uses_stq) { dis_uops(w).lrs1_rtype := RT_X dis_uops(w).prs1_busy := false.B } } if (iqType != IQ_ALU) { assert(!(io.dis_uops(w).bits.ppred_busy && io.dis_uops(w).valid)) dis_uops(w).ppred_busy := false.B } } //------------------------------------------------------------- // Issue Table val slots = (0 until numIssueSlots) map { w => Module(new IssueSlot(numWakeupPorts, iqType == IQ_MEM, iqType == IQ_FP)) } val issue_slots = VecInit(slots.map(_.io)) for (i <- 0 until numIssueSlots) { issue_slots(i).wakeup_ports := io.wakeup_ports issue_slots(i).pred_wakeup_port := io.pred_wakeup_port issue_slots(i).child_rebusys := io.child_rebusys issue_slots(i).squash_grant := io.squash_grant issue_slots(i).brupdate := io.brupdate issue_slots(i).kill := io.flush_pipeline } for (w <- 0 until issueWidth) { io.iss_uops(w).valid := false.B } //------------------------------------------------------------- assert (PopCount(issue_slots.map(s => s.grant)) <= issueWidth.U, "[issue] window giving out too many grants.") //------------------------------------------------------------- // Figure out how much to shift entries by // Slow slots only shift 1 per cycle, these reduce critical path val nSlowSlots = params.numSlowEntries // Fast slots can shift up to dispatchWidth per cycle, so they can handle full dispatch throughput val nFastSlots = numIssueSlots - nSlowSlots require (nFastSlots >= dispatchWidth) require (nFastSlots <= numIssueSlots) val vacants = issue_slots.map(s => !(s.valid)) ++ io.dis_uops.map(_.valid).map(!_.asBool) val shamts_oh = Wire(Vec(numIssueSlots+dispatchWidth, UInt(width=dispatchWidth.W))) // track how many to shift up this entry by by counting previous vacant spots def SaturatingCounterOH(count_oh:UInt, inc: Bool, max: Int): UInt = { val next = Wire(UInt(width=max.W)) next := count_oh when (count_oh === 0.U && inc) { next := 1.U } .elsewhen (!count_oh(max-1) && inc) { next := (count_oh << 1.U) } next } shamts_oh(0) := 0.U for (i <- 1 until numIssueSlots + dispatchWidth) { val shift = if (i < nSlowSlots) (dispatchWidth min 1 + (i * (dispatchWidth-1)/nSlowSlots).toInt) else dispatchWidth if (dispatchWidth == 1 \|\| shift == 1) { shamts_oh(i) := vacants.take(i).reduce(_\|\|_) } else { shamts_oh(i) := SaturatingCounterOH(shamts_oh(i-1), vacants(i-1), shift) } } //------------------------------------------------------------- // which entries' uops will still be next cycle? (not being issued and vacated) val will_be_valid = (0 until numIssueSlots).map(i => issue_slots(i).will_be_valid) ++ (0 until dispatchWidth).map(i => io.dis_uops(i).valid && !dis_uops(i).exception && !dis_uops(i).is_fence && !dis_uops(i).is_fencei) val uops = issue_slots.map(s=>s.out_uop) ++ dis_uops.map(s=>s) for (i <- 0 until numIssueSlots) { issue_slots(i).in_uop.valid := false.B issue_slots(i).in_uop.bits := uops(i+1) for (j <- 1 to dispatchWidth by 1) { when (shamts_oh(i+j) === (1 << (j-1)).U) { issue_slots(i).in_uop.valid := will_be_valid(i+j) issue_slots(i).in_uop.bits := uops(i+j) } } issue_slots(i).clear := shamts_oh(i) =/= 0.U } //------------------------------------------------------------- // Dispatch/Entry Logic // did we find a spot to slide the new dispatched uops into? // Only look at the fast slots to determine readiness to dispatch. // Slow slot do not compact fast enough to make this calculation valid val is_available = Reg(Vec(nFastSlots, Bool())) is_available := VecInit((nSlowSlots until numIssueSlots).map(i => (!issue_slots(i).will_be_valid \|\| issue_slots(i).clear) && !(issue_slots(i).in_uop.valid))) for (w <- 0 until dispatchWidth) { io.dis_uops(w).ready := RegNext(PopCount(is_available) > w.U(log2Ceil(nFastSlots).W) + PopCount(io.dis_uops.map(_.fire))) // io.dis_uops(w).ready := RegNext(PopCount(will_be_available) > w.U) assert (!io.dis_uops(w).ready \|\| (shamts_oh(w+numIssueSlots) >> w) =/= 0.U) } //------------------------------------------------------------- // Issue Select Logic val requests = issue_slots.map(s => s.request) val port_issued = Array.fill(issueWidth){Bool()} for (w <- 0 until issueWidth) { port_issued(w) = false.B } val iss_select_mask = Array.ofDim[Boolean](issueWidth, numIssueSlots) if (params.useFullIssueSel) { for (w <- 0 until issueWidth) { for (i <- 0 until numIssueSlots) { iss_select_mask(w)(i) = true } } } else { for (w <- 0 until issueWidth) { for (i <- 0 until numIssueSlots) { iss_select_mask(w)(i) = (w % 2) == (i % 2) } iss_select_mask(w)(0) = true } } val iss_uops = Wire(Vec(issueWidth, Valid(new MicroOp))) for (w <- 0 until issueWidth) { iss_uops(w).valid := false.B iss_uops(w).bits := DontCare } for (i <- 0 until numIssueSlots) { issue_slots(i).grant := false.B var uop_issued = false.B for (w <- 0 until issueWidth) { val fu_code_match = (issue_slots(i).iss_uop.fu_code zip io.fu_types(w)).map { case (r,c) => r && c } .reduce(_\|\|_) val can_allocate = fu_code_match && iss_select_mask(w)(i).B when (requests(i) && !uop_issued && can_allocate && !port_issued(w)) { issue_slots(i).grant := true.B iss_uops(w).valid := true.B iss_uops(w).bits := issue_slots(i).iss_uop } val was_port_issued_yet = port_issued(w) port_issued(w) = (requests(i) && !uop_issued && can_allocate) \| port_issued(w) uop_issued = (requests(i) && can_allocate && !was_port_issued_yet) \| uop_issued } } io.iss_uops := iss_uops when (io.squash_grant) { io.iss_uops.map { u => u.valid := false.B } } } File issue-unit.scala: //****************************************************************************** // Copyright (c) 2015 - 2018, The Regents of the University of California (Regents). // All Rights Reserved. See LICENSE and LICENSE.SiFive for license details. //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // RISCV Processor Issue Logic //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ package boom.v4.exu import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util.{Str} import boom.v4.common._ import boom.v4.util.{BoolToChar} case class IssueParams( dispatchWidth: Int = 1, issueWidth: Int = 1, numEntries: Int = 8, useFullIssueSel: Boolean = true, numSlowEntries: Int = 0, iqType: Int ) abstract class IssueUnit( val params: IssueParams, val numWakeupPorts: Int )(implicit p: Parameters) extends BoomModule { val numIssueSlots = params.numEntries val issueWidth = params.issueWidth val iqType = params.iqType val dispatchWidth = params.dispatchWidth val io = IO(new Bundle { val dis_uops = Vec(dispatchWidth, Flipped(Decoupled(new MicroOp))) val iss_uops = Output(Vec(issueWidth, Valid(new MicroOp()))) val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup))) val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W))) val child_rebusys = Input(UInt(aluWidth.W)) // tell the issue unit what each execution pipeline has in terms of functional units val fu_types = Input(Vec(issueWidth, Vec(FC_SZ, Bool()))) val brupdate = Input(new BrUpdateInfo()) val flush_pipeline = Input(Bool()) val squash_grant = Input(Bool()) val tsc_reg = Input(UInt(xLen.W)) }) //------------------------------------------------------------- def getType: String = if (iqType == IQ_ALU) "alu" else if (iqType == IQ_MEM) "mem" else if (iqType == IQ_FP) " fp" else if (iqType == IQ_UNQ) "unique" else "unknown" } object IssueUnit { def apply(params: IssueParams, numWakeupPorts: Int, useColumnIssueUnit: Boolean, useSingleWideDispatch: Boolean)(implicit p: Parameters): IssueUnit = { if (useColumnIssueUnit) Module(new IssueUnitBanked(params, numWakeupPorts, useSingleWideDispatch)) else Module(new IssueUnitCollapsing(params, numWakeupPorts)) } }	module IssueUnitCollapsing( // @[issue-unit-age-ordered.scala:22:7] input clock, // @[issue-unit-age-ordered.scala:22:7] input reset, // @[issue-unit-age-ordered.scala:22:7] output io_dis_uops_0_ready, // @[issue-unit.scala:44:14] input io_dis_uops_0_valid, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_0_bits_inst, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_0_bits_debug_inst, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_dis_uops_0_bits_debug_pc, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iq_type_0, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iq_type_1, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iq_type_2, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iq_type_3, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_0, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_1, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_2, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_3, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_4, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_5, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_6, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_7, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_8, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fu_code_9, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_issued, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_dis_uops_0_bits_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_0_bits_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_0_bits_br_type, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_sfb, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_fence, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_fencei, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_sfence, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_amo, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_eret, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_rocc, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_ftq_idx, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_pc_lob, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_taken, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_pimm, // @[issue-unit.scala:44:14] input [19:0] io_dis_uops_0_bits_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_op2_sel, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_pdst, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_prs1, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_prs2, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_prs3, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_ppred, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_prs1_busy, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_prs2_busy, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_prs3_busy, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_0_bits_stale_pdst, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_exception, // @[issue-unit.scala:44:14] input [63:0] io_dis_uops_0_bits_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_mem_size, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_mem_signed, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_uses_ldq, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_uses_stq, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_is_unique, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_csr_cmd, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_ldst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_0_bits_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_lrs2_rtype, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_frs3_en, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_0_bits_fcn_op, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_0_bits_fp_typ, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_bp_debug_if, // @[issue-unit.scala:44:14] input io_dis_uops_0_bits_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_0_bits_debug_tsrc, // @[issue-unit.scala:44:14] output io_dis_uops_1_ready, // @[issue-unit.scala:44:14] input io_dis_uops_1_valid, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_1_bits_inst, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_1_bits_debug_inst, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_dis_uops_1_bits_debug_pc, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iq_type_0, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iq_type_1, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iq_type_2, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iq_type_3, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_0, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_1, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_2, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_3, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_4, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_5, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_6, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_7, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_8, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fu_code_9, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_issued, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_dis_uops_1_bits_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_1_bits_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_1_bits_br_type, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_sfb, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_fence, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_fencei, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_sfence, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_amo, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_eret, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_rocc, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_ftq_idx, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_pc_lob, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_taken, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_pimm, // @[issue-unit.scala:44:14] input [19:0] io_dis_uops_1_bits_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_op2_sel, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_pdst, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_prs1, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_prs2, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_prs3, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_ppred, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_prs1_busy, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_prs2_busy, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_prs3_busy, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_1_bits_stale_pdst, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_exception, // @[issue-unit.scala:44:14] input [63:0] io_dis_uops_1_bits_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_mem_size, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_mem_signed, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_uses_ldq, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_uses_stq, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_is_unique, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_csr_cmd, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_ldst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_1_bits_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_lrs2_rtype, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_frs3_en, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_1_bits_fcn_op, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_1_bits_fp_typ, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_bp_debug_if, // @[issue-unit.scala:44:14] input io_dis_uops_1_bits_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_1_bits_debug_tsrc, // @[issue-unit.scala:44:14] output io_dis_uops_2_ready, // @[issue-unit.scala:44:14] input io_dis_uops_2_valid, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_2_bits_inst, // @[issue-unit.scala:44:14] input [31:0] io_dis_uops_2_bits_debug_inst, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_dis_uops_2_bits_debug_pc, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iq_type_0, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iq_type_1, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iq_type_2, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iq_type_3, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_0, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_1, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_2, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_3, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_4, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_5, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_6, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_7, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_8, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fu_code_9, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iw_issued, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_dis_uops_2_bits_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_2_bits_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_dis_uops_2_bits_br_type, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_sfb, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_fence, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_fencei, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_sfence, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_amo, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_eret, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_rocc, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_ftq_idx, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_2_bits_pc_lob, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_taken, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_pimm, // @[issue-unit.scala:44:14] input [19:0] io_dis_uops_2_bits_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_op2_sel, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_2_bits_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_2_bits_pdst, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_2_bits_prs1, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_2_bits_prs2, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_2_bits_prs3, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_ppred, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_prs1_busy, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_prs2_busy, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_prs3_busy, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_dis_uops_2_bits_stale_pdst, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_exception, // @[issue-unit.scala:44:14] input [63:0] io_dis_uops_2_bits_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_mem_size, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_mem_signed, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_uses_ldq, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_uses_stq, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_is_unique, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_csr_cmd, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_2_bits_ldst, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_2_bits_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_2_bits_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_dis_uops_2_bits_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_lrs2_rtype, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_frs3_en, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_dis_uops_2_bits_fcn_op, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_dis_uops_2_bits_fp_typ, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_bp_debug_if, // @[issue-unit.scala:44:14] input io_dis_uops_2_bits_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_dis_uops_2_bits_debug_tsrc, // @[issue-unit.scala:44:14] output io_iss_uops_0_valid, // @[issue-unit.scala:44:14] output [31:0] io_iss_uops_0_bits_inst, // @[issue-unit.scala:44:14] output [31:0] io_iss_uops_0_bits_debug_inst, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_rvc, // @[issue-unit.scala:44:14] output [39:0] io_iss_uops_0_bits_debug_pc, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iq_type_0, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iq_type_1, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iq_type_2, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iq_type_3, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_0, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_1, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_2, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_3, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_4, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_5, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_6, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_7, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_8, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fu_code_9, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iw_issued, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_iw_p1_speculative_child, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_iw_p2_speculative_child, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_dis_col_sel, // @[issue-unit.scala:44:14] output [15:0] io_iss_uops_0_bits_br_mask, // @[issue-unit.scala:44:14] output [3:0] io_iss_uops_0_bits_br_tag, // @[issue-unit.scala:44:14] output [3:0] io_iss_uops_0_bits_br_type, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_sfb, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_fence, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_fencei, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_sfence, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_amo, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_eret, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_sys_pc2epc, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_rocc, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_mov, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_ftq_idx, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_edge_inst, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_pc_lob, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_taken, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_imm_rename, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_imm_sel, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_pimm, // @[issue-unit.scala:44:14] output [19:0] io_iss_uops_0_bits_imm_packed, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_op1_sel, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_op2_sel, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_ldst, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_wen, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_ren1, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_ren2, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_ren3, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_swap12, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_swap23, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_fromint, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_toint, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_fma, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_div, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_wflags, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_ctrl_vec, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_rob_idx, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_ldq_idx, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_stq_idx, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_rxq_idx, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_pdst, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_prs1, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_prs2, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_prs3, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_ppred, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_prs1_busy, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_prs2_busy, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_prs3_busy, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_ppred_busy, // @[issue-unit.scala:44:14] output [6:0] io_iss_uops_0_bits_stale_pdst, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_exception, // @[issue-unit.scala:44:14] output [63:0] io_iss_uops_0_bits_exc_cause, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_mem_cmd, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_mem_size, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_mem_signed, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_uses_ldq, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_uses_stq, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_is_unique, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_flush_on_commit, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_csr_cmd, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_ldst_is_rs1, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_ldst, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_lrs1, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_lrs2, // @[issue-unit.scala:44:14] output [5:0] io_iss_uops_0_bits_lrs3, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_dst_rtype, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_lrs1_rtype, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_lrs2_rtype, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_frs3_en, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fcn_dw, // @[issue-unit.scala:44:14] output [4:0] io_iss_uops_0_bits_fcn_op, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_fp_val, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_fp_rm, // @[issue-unit.scala:44:14] output [1:0] io_iss_uops_0_bits_fp_typ, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_xcpt_pf_if, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_xcpt_ae_if, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_xcpt_ma_if, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_bp_debug_if, // @[issue-unit.scala:44:14] output io_iss_uops_0_bits_bp_xcpt_if, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_debug_fsrc, // @[issue-unit.scala:44:14] output [2:0] io_iss_uops_0_bits_debug_tsrc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_valid, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_taken, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_valid, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_taken, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-unit.scala:44:14] input io_fu_types_0_7, // @[issue-unit.scala:44:14] input io_fu_types_0_9, // @[issue-unit.scala:44:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-unit.scala:44:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-unit.scala:44:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-unit.scala:44:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_rvc, // @[issue-unit.scala:44:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iq_type_0, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iq_type_1, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iq_type_2, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iq_type_3, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_0, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_1, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_2, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_3, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_4, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_5, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_6, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_7, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_8, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fu_code_9, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_issued, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-unit.scala:44:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-unit.scala:44:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-unit.scala:44:14] input [3:0] io_brupdate_b2_uop_br_type, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_sfb, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_fence, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_fencei, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_sfence, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_amo, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_eret, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_rocc, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_mov, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_edge_inst, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_taken, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_imm_rename, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_pimm, // @[issue-unit.scala:44:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-unit.scala:44:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_exception, // @[issue-unit.scala:44:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_mem_signed, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_uses_stq, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_is_unique, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-unit.scala:44:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_frs3_en, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fcn_dw, // @[issue-unit.scala:44:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_fp_val, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-unit.scala:44:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-unit.scala:44:14] input io_brupdate_b2_mispredict, // @[issue-unit.scala:44:14] input io_brupdate_b2_taken, // @[issue-unit.scala:44:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-unit.scala:44:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-unit.scala:44:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-unit.scala:44:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-unit.scala:44:14] input io_flush_pipeline, // @[issue-unit.scala:44:14] input io_squash_grant, // @[issue-unit.scala:44:14] input [63:0] io_tsc_reg // @[issue-unit.scala:44:14] ); wire issue_slots_23_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire io_dis_uops_0_valid_0 = io_dis_uops_0_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_0_bits_inst_0 = io_dis_uops_0_bits_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_0_bits_debug_inst_0 = io_dis_uops_0_bits_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_rvc_0 = io_dis_uops_0_bits_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_dis_uops_0_bits_debug_pc_0 = io_dis_uops_0_bits_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iq_type_0_0 = io_dis_uops_0_bits_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iq_type_1_0 = io_dis_uops_0_bits_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iq_type_2_0 = io_dis_uops_0_bits_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iq_type_3_0 = io_dis_uops_0_bits_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_0_0 = io_dis_uops_0_bits_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_1_0 = io_dis_uops_0_bits_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_2_0 = io_dis_uops_0_bits_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_3_0 = io_dis_uops_0_bits_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_4_0 = io_dis_uops_0_bits_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_5_0 = io_dis_uops_0_bits_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_6_0 = io_dis_uops_0_bits_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_7_0 = io_dis_uops_0_bits_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_8_0 = io_dis_uops_0_bits_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fu_code_9_0 = io_dis_uops_0_bits_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_issued_0 = io_dis_uops_0_bits_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_issued_partial_agen_0 = io_dis_uops_0_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_issued_partial_dgen_0 = io_dis_uops_0_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_iw_p1_speculative_child_0 = io_dis_uops_0_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_iw_p2_speculative_child_0 = io_dis_uops_0_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_p1_bypass_hint_0 = io_dis_uops_0_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_p2_bypass_hint_0 = io_dis_uops_0_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_iw_p3_bypass_hint_0 = io_dis_uops_0_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_dis_col_sel_0 = io_dis_uops_0_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_dis_uops_0_bits_br_mask_0 = io_dis_uops_0_bits_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_0_bits_br_tag_0 = io_dis_uops_0_bits_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_0_bits_br_type_0 = io_dis_uops_0_bits_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_sfb_0 = io_dis_uops_0_bits_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_fence_0 = io_dis_uops_0_bits_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_fencei_0 = io_dis_uops_0_bits_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_sfence_0 = io_dis_uops_0_bits_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_amo_0 = io_dis_uops_0_bits_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_eret_0 = io_dis_uops_0_bits_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_sys_pc2epc_0 = io_dis_uops_0_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_rocc_0 = io_dis_uops_0_bits_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_mov_0 = io_dis_uops_0_bits_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_ftq_idx_0 = io_dis_uops_0_bits_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_edge_inst_0 = io_dis_uops_0_bits_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_pc_lob_0 = io_dis_uops_0_bits_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_taken_0 = io_dis_uops_0_bits_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_imm_rename_0 = io_dis_uops_0_bits_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_imm_sel_0 = io_dis_uops_0_bits_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_pimm_0 = io_dis_uops_0_bits_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_dis_uops_0_bits_imm_packed_0 = io_dis_uops_0_bits_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_op1_sel_0 = io_dis_uops_0_bits_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_op2_sel_0 = io_dis_uops_0_bits_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_ldst_0 = io_dis_uops_0_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_wen_0 = io_dis_uops_0_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_ren1_0 = io_dis_uops_0_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_ren2_0 = io_dis_uops_0_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_ren3_0 = io_dis_uops_0_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_swap12_0 = io_dis_uops_0_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_swap23_0 = io_dis_uops_0_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagIn_0 = io_dis_uops_0_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_fp_ctrl_typeTagOut_0 = io_dis_uops_0_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_fromint_0 = io_dis_uops_0_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_toint_0 = io_dis_uops_0_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_fastpipe_0 = io_dis_uops_0_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_fma_0 = io_dis_uops_0_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_div_0 = io_dis_uops_0_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_sqrt_0 = io_dis_uops_0_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_wflags_0 = io_dis_uops_0_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_ctrl_vec_0 = io_dis_uops_0_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_rob_idx_0 = io_dis_uops_0_bits_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_ldq_idx_0 = io_dis_uops_0_bits_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_stq_idx_0 = io_dis_uops_0_bits_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_rxq_idx_0 = io_dis_uops_0_bits_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_pdst_0 = io_dis_uops_0_bits_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_prs1_0 = io_dis_uops_0_bits_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_prs2_0 = io_dis_uops_0_bits_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_prs3_0 = io_dis_uops_0_bits_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_ppred_0 = io_dis_uops_0_bits_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_prs1_busy_0 = io_dis_uops_0_bits_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_prs2_busy_0 = io_dis_uops_0_bits_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_prs3_busy_0 = io_dis_uops_0_bits_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_ppred_busy_0 = io_dis_uops_0_bits_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_0_bits_stale_pdst_0 = io_dis_uops_0_bits_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_exception_0 = io_dis_uops_0_bits_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_dis_uops_0_bits_exc_cause_0 = io_dis_uops_0_bits_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_mem_cmd_0 = io_dis_uops_0_bits_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_mem_size_0 = io_dis_uops_0_bits_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_mem_signed_0 = io_dis_uops_0_bits_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_uses_ldq_0 = io_dis_uops_0_bits_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_uses_stq_0 = io_dis_uops_0_bits_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_is_unique_0 = io_dis_uops_0_bits_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_flush_on_commit_0 = io_dis_uops_0_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_csr_cmd_0 = io_dis_uops_0_bits_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_ldst_is_rs1_0 = io_dis_uops_0_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_ldst_0 = io_dis_uops_0_bits_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_lrs1_0 = io_dis_uops_0_bits_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_lrs2_0 = io_dis_uops_0_bits_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_0_bits_lrs3_0 = io_dis_uops_0_bits_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_dst_rtype_0 = io_dis_uops_0_bits_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_lrs1_rtype_0 = io_dis_uops_0_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_lrs2_rtype_0 = io_dis_uops_0_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_frs3_en_0 = io_dis_uops_0_bits_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fcn_dw_0 = io_dis_uops_0_bits_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_0_bits_fcn_op_0 = io_dis_uops_0_bits_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_fp_val_0 = io_dis_uops_0_bits_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_fp_rm_0 = io_dis_uops_0_bits_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_0_bits_fp_typ_0 = io_dis_uops_0_bits_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_xcpt_pf_if_0 = io_dis_uops_0_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_xcpt_ae_if_0 = io_dis_uops_0_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_xcpt_ma_if_0 = io_dis_uops_0_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_bp_debug_if_0 = io_dis_uops_0_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_0_bits_bp_xcpt_if_0 = io_dis_uops_0_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_debug_fsrc_0 = io_dis_uops_0_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_0_bits_debug_tsrc_0 = io_dis_uops_0_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_valid_0 = io_dis_uops_1_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_1_bits_inst_0 = io_dis_uops_1_bits_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_1_bits_debug_inst_0 = io_dis_uops_1_bits_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_rvc_0 = io_dis_uops_1_bits_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_dis_uops_1_bits_debug_pc_0 = io_dis_uops_1_bits_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iq_type_0_0 = io_dis_uops_1_bits_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iq_type_1_0 = io_dis_uops_1_bits_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iq_type_2_0 = io_dis_uops_1_bits_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iq_type_3_0 = io_dis_uops_1_bits_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_0_0 = io_dis_uops_1_bits_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_1_0 = io_dis_uops_1_bits_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_2_0 = io_dis_uops_1_bits_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_3_0 = io_dis_uops_1_bits_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_4_0 = io_dis_uops_1_bits_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_5_0 = io_dis_uops_1_bits_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_6_0 = io_dis_uops_1_bits_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_7_0 = io_dis_uops_1_bits_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_8_0 = io_dis_uops_1_bits_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fu_code_9_0 = io_dis_uops_1_bits_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_issued_0 = io_dis_uops_1_bits_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_issued_partial_agen_0 = io_dis_uops_1_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_issued_partial_dgen_0 = io_dis_uops_1_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_iw_p1_speculative_child_0 = io_dis_uops_1_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_iw_p2_speculative_child_0 = io_dis_uops_1_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_p1_bypass_hint_0 = io_dis_uops_1_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_p2_bypass_hint_0 = io_dis_uops_1_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_iw_p3_bypass_hint_0 = io_dis_uops_1_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_dis_col_sel_0 = io_dis_uops_1_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_dis_uops_1_bits_br_mask_0 = io_dis_uops_1_bits_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_1_bits_br_tag_0 = io_dis_uops_1_bits_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_1_bits_br_type_0 = io_dis_uops_1_bits_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_sfb_0 = io_dis_uops_1_bits_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_fence_0 = io_dis_uops_1_bits_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_fencei_0 = io_dis_uops_1_bits_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_sfence_0 = io_dis_uops_1_bits_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_amo_0 = io_dis_uops_1_bits_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_eret_0 = io_dis_uops_1_bits_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_sys_pc2epc_0 = io_dis_uops_1_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_rocc_0 = io_dis_uops_1_bits_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_mov_0 = io_dis_uops_1_bits_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_ftq_idx_0 = io_dis_uops_1_bits_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_edge_inst_0 = io_dis_uops_1_bits_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_pc_lob_0 = io_dis_uops_1_bits_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_taken_0 = io_dis_uops_1_bits_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_imm_rename_0 = io_dis_uops_1_bits_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_imm_sel_0 = io_dis_uops_1_bits_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_pimm_0 = io_dis_uops_1_bits_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_dis_uops_1_bits_imm_packed_0 = io_dis_uops_1_bits_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_op1_sel_0 = io_dis_uops_1_bits_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_op2_sel_0 = io_dis_uops_1_bits_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_ldst_0 = io_dis_uops_1_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_wen_0 = io_dis_uops_1_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_ren1_0 = io_dis_uops_1_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_ren2_0 = io_dis_uops_1_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_ren3_0 = io_dis_uops_1_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_swap12_0 = io_dis_uops_1_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_swap23_0 = io_dis_uops_1_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagIn_0 = io_dis_uops_1_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_fp_ctrl_typeTagOut_0 = io_dis_uops_1_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_fromint_0 = io_dis_uops_1_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_toint_0 = io_dis_uops_1_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_fastpipe_0 = io_dis_uops_1_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_fma_0 = io_dis_uops_1_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_div_0 = io_dis_uops_1_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_sqrt_0 = io_dis_uops_1_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_wflags_0 = io_dis_uops_1_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_ctrl_vec_0 = io_dis_uops_1_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_rob_idx_0 = io_dis_uops_1_bits_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_ldq_idx_0 = io_dis_uops_1_bits_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_stq_idx_0 = io_dis_uops_1_bits_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_rxq_idx_0 = io_dis_uops_1_bits_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_pdst_0 = io_dis_uops_1_bits_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_prs1_0 = io_dis_uops_1_bits_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_prs2_0 = io_dis_uops_1_bits_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_prs3_0 = io_dis_uops_1_bits_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_ppred_0 = io_dis_uops_1_bits_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_prs1_busy_0 = io_dis_uops_1_bits_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_prs2_busy_0 = io_dis_uops_1_bits_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_prs3_busy_0 = io_dis_uops_1_bits_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_ppred_busy_0 = io_dis_uops_1_bits_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_1_bits_stale_pdst_0 = io_dis_uops_1_bits_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_exception_0 = io_dis_uops_1_bits_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_dis_uops_1_bits_exc_cause_0 = io_dis_uops_1_bits_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_mem_cmd_0 = io_dis_uops_1_bits_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_mem_size_0 = io_dis_uops_1_bits_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_mem_signed_0 = io_dis_uops_1_bits_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_uses_ldq_0 = io_dis_uops_1_bits_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_uses_stq_0 = io_dis_uops_1_bits_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_is_unique_0 = io_dis_uops_1_bits_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_flush_on_commit_0 = io_dis_uops_1_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_csr_cmd_0 = io_dis_uops_1_bits_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_ldst_is_rs1_0 = io_dis_uops_1_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_ldst_0 = io_dis_uops_1_bits_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_lrs1_0 = io_dis_uops_1_bits_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_lrs2_0 = io_dis_uops_1_bits_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_1_bits_lrs3_0 = io_dis_uops_1_bits_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_dst_rtype_0 = io_dis_uops_1_bits_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_lrs1_rtype_0 = io_dis_uops_1_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_lrs2_rtype_0 = io_dis_uops_1_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_frs3_en_0 = io_dis_uops_1_bits_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fcn_dw_0 = io_dis_uops_1_bits_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_1_bits_fcn_op_0 = io_dis_uops_1_bits_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_fp_val_0 = io_dis_uops_1_bits_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_fp_rm_0 = io_dis_uops_1_bits_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_1_bits_fp_typ_0 = io_dis_uops_1_bits_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_xcpt_pf_if_0 = io_dis_uops_1_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_xcpt_ae_if_0 = io_dis_uops_1_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_xcpt_ma_if_0 = io_dis_uops_1_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_bp_debug_if_0 = io_dis_uops_1_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_bits_bp_xcpt_if_0 = io_dis_uops_1_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_debug_fsrc_0 = io_dis_uops_1_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_1_bits_debug_tsrc_0 = io_dis_uops_1_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_valid_0 = io_dis_uops_2_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_2_bits_inst_0 = io_dis_uops_2_bits_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_dis_uops_2_bits_debug_inst_0 = io_dis_uops_2_bits_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_rvc_0 = io_dis_uops_2_bits_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_dis_uops_2_bits_debug_pc_0 = io_dis_uops_2_bits_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iq_type_0_0 = io_dis_uops_2_bits_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iq_type_1_0 = io_dis_uops_2_bits_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iq_type_2_0 = io_dis_uops_2_bits_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iq_type_3_0 = io_dis_uops_2_bits_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_0_0 = io_dis_uops_2_bits_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_1_0 = io_dis_uops_2_bits_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_2_0 = io_dis_uops_2_bits_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_3_0 = io_dis_uops_2_bits_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_4_0 = io_dis_uops_2_bits_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_5_0 = io_dis_uops_2_bits_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_6_0 = io_dis_uops_2_bits_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_7_0 = io_dis_uops_2_bits_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_8_0 = io_dis_uops_2_bits_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fu_code_9_0 = io_dis_uops_2_bits_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iw_issued_0 = io_dis_uops_2_bits_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iw_issued_partial_agen_0 = io_dis_uops_2_bits_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iw_issued_partial_dgen_0 = io_dis_uops_2_bits_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_iw_p1_speculative_child_0 = io_dis_uops_2_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_iw_p2_speculative_child_0 = io_dis_uops_2_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iw_p1_bypass_hint_0 = io_dis_uops_2_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iw_p2_bypass_hint_0 = io_dis_uops_2_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_iw_p3_bypass_hint_0 = io_dis_uops_2_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_dis_col_sel_0 = io_dis_uops_2_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_dis_uops_2_bits_br_mask_0 = io_dis_uops_2_bits_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_2_bits_br_tag_0 = io_dis_uops_2_bits_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_dis_uops_2_bits_br_type_0 = io_dis_uops_2_bits_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_sfb_0 = io_dis_uops_2_bits_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_fence_0 = io_dis_uops_2_bits_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_fencei_0 = io_dis_uops_2_bits_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_sfence_0 = io_dis_uops_2_bits_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_amo_0 = io_dis_uops_2_bits_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_eret_0 = io_dis_uops_2_bits_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_sys_pc2epc_0 = io_dis_uops_2_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_rocc_0 = io_dis_uops_2_bits_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_mov_0 = io_dis_uops_2_bits_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_ftq_idx_0 = io_dis_uops_2_bits_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_edge_inst_0 = io_dis_uops_2_bits_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_2_bits_pc_lob_0 = io_dis_uops_2_bits_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_taken_0 = io_dis_uops_2_bits_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_imm_rename_0 = io_dis_uops_2_bits_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_imm_sel_0 = io_dis_uops_2_bits_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_pimm_0 = io_dis_uops_2_bits_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_dis_uops_2_bits_imm_packed_0 = io_dis_uops_2_bits_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_op1_sel_0 = io_dis_uops_2_bits_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_op2_sel_0 = io_dis_uops_2_bits_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_ldst_0 = io_dis_uops_2_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_wen_0 = io_dis_uops_2_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_ren1_0 = io_dis_uops_2_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_ren2_0 = io_dis_uops_2_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_ren3_0 = io_dis_uops_2_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_swap12_0 = io_dis_uops_2_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_swap23_0 = io_dis_uops_2_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_fp_ctrl_typeTagIn_0 = io_dis_uops_2_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_fp_ctrl_typeTagOut_0 = io_dis_uops_2_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_fromint_0 = io_dis_uops_2_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_toint_0 = io_dis_uops_2_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_fastpipe_0 = io_dis_uops_2_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_fma_0 = io_dis_uops_2_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_div_0 = io_dis_uops_2_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_sqrt_0 = io_dis_uops_2_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_wflags_0 = io_dis_uops_2_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_ctrl_vec_0 = io_dis_uops_2_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_2_bits_rob_idx_0 = io_dis_uops_2_bits_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_ldq_idx_0 = io_dis_uops_2_bits_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_stq_idx_0 = io_dis_uops_2_bits_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_rxq_idx_0 = io_dis_uops_2_bits_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_2_bits_pdst_0 = io_dis_uops_2_bits_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_2_bits_prs1_0 = io_dis_uops_2_bits_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_2_bits_prs2_0 = io_dis_uops_2_bits_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_2_bits_prs3_0 = io_dis_uops_2_bits_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_ppred_0 = io_dis_uops_2_bits_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_prs1_busy_0 = io_dis_uops_2_bits_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_prs2_busy_0 = io_dis_uops_2_bits_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_prs3_busy_0 = io_dis_uops_2_bits_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_ppred_busy_0 = io_dis_uops_2_bits_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_dis_uops_2_bits_stale_pdst_0 = io_dis_uops_2_bits_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_exception_0 = io_dis_uops_2_bits_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_dis_uops_2_bits_exc_cause_0 = io_dis_uops_2_bits_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_mem_cmd_0 = io_dis_uops_2_bits_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_mem_size_0 = io_dis_uops_2_bits_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_mem_signed_0 = io_dis_uops_2_bits_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_uses_ldq_0 = io_dis_uops_2_bits_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_uses_stq_0 = io_dis_uops_2_bits_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_is_unique_0 = io_dis_uops_2_bits_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_flush_on_commit_0 = io_dis_uops_2_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_csr_cmd_0 = io_dis_uops_2_bits_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_ldst_is_rs1_0 = io_dis_uops_2_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_2_bits_ldst_0 = io_dis_uops_2_bits_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_2_bits_lrs1_0 = io_dis_uops_2_bits_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_2_bits_lrs2_0 = io_dis_uops_2_bits_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_dis_uops_2_bits_lrs3_0 = io_dis_uops_2_bits_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_dst_rtype_0 = io_dis_uops_2_bits_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_lrs1_rtype_0 = io_dis_uops_2_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_lrs2_rtype_0 = io_dis_uops_2_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_frs3_en_0 = io_dis_uops_2_bits_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fcn_dw_0 = io_dis_uops_2_bits_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_dis_uops_2_bits_fcn_op_0 = io_dis_uops_2_bits_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_fp_val_0 = io_dis_uops_2_bits_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_fp_rm_0 = io_dis_uops_2_bits_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_dis_uops_2_bits_fp_typ_0 = io_dis_uops_2_bits_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_xcpt_pf_if_0 = io_dis_uops_2_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_xcpt_ae_if_0 = io_dis_uops_2_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_xcpt_ma_if_0 = io_dis_uops_2_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_bp_debug_if_0 = io_dis_uops_2_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_bits_bp_xcpt_if_0 = io_dis_uops_2_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_debug_fsrc_0 = io_dis_uops_2_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_dis_uops_2_bits_debug_tsrc_0 = io_dis_uops_2_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_7_0 = io_fu_types_0_7; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_9_0 = io_fu_types_0_9; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-unit-age-ordered.scala:22:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-unit-age-ordered.scala:22:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-unit-age-ordered.scala:22:7] wire io_flush_pipeline_0 = io_flush_pipeline; // @[issue-unit-age-ordered.scala:22:7] wire io_squash_grant_0 = io_squash_grant; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_tsc_reg_0 = io_tsc_reg; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_0 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_1 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_2 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_3 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_4 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_5 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_8 = 1'h0; // @[issue-unit-age-ordered.scala:22:7] wire prs1_rebusys_0 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs2_rebusys_0 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs1_rebusys_0_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_1_1 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs2_rebusys_0_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_1_1 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs1_rebusys_0_2 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs1_rebusys_1_2 = 1'h0; // @[issue-unit-age-ordered.scala:50:95] wire prs2_rebusys_0_2 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire prs2_rebusys_1_2 = 1'h0; // @[issue-unit-age-ordered.scala:51:95] wire issue_slots_0_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_clear = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_iw_issued = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_ppred_busy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_pred_wakeup_port_valid = 1'h0; // @[issue-unit-age-ordered.scala:122:28] wire _issue_slots_0_clear_T = 1'h0; // @[issue-unit-age-ordered.scala:199:49] wire iss_uops_0_bits_iw_issued_partial_agen = 1'h0; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_issued_partial_dgen = 1'h0; // @[issue-unit-age-ordered.scala:241:22] wire _fu_code_match_T = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_1 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_2 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_3 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_4 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_5 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_8 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_10 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_11 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_12 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_13 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_14 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_18 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_19 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_20 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_21 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_22 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_23 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_26 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_28 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_29 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_30 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_31 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_32 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_36 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_37 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_38 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_39 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_40 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_41 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_44 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_46 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_47 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_48 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_49 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_50 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_54 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_55 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_56 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_57 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_58 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_59 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_62 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_64 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_65 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_66 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_67 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_68 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_72 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_73 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_74 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_75 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_76 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_77 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_80 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_82 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_83 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_84 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_85 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_86 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_90 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_91 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_92 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_93 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_94 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_95 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_98 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_100 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_101 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_102 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_103 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_104 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_108 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_109 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_110 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_111 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_112 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_113 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_116 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_118 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_119 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_120 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_121 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_122 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_126 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_127 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_128 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_129 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_130 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_131 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_134 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_136 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_137 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_138 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_139 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_140 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_144 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_145 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_146 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_147 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_148 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_149 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_152 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_154 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_155 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_156 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_157 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_158 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_162 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_163 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_164 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_165 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_166 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_167 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_170 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_172 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_173 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_174 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_175 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_176 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_180 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_181 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_182 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_183 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_184 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_185 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_188 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_190 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_191 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_192 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_193 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_194 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_198 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_199 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_200 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_201 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_202 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_203 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_206 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_208 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_209 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_210 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_211 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_212 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_216 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_217 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_218 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_219 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_220 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_221 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_224 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_226 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_227 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_228 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_229 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_230 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_234 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_235 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_236 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_237 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_238 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_239 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_242 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_244 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_245 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_246 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_247 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_248 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_252 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_253 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_254 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_255 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_256 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_257 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_260 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_262 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_263 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_264 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_265 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_266 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_270 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_271 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_272 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_273 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_274 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_275 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_278 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_280 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_281 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_282 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_283 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_284 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_288 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_289 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_290 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_291 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_292 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_293 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_296 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_298 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_299 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_300 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_301 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_302 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_306 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_307 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_308 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_309 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_310 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_311 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_314 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_316 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_317 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_318 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_319 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_320 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_324 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_325 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_326 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_327 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_328 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_329 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_332 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_334 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_335 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_336 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_337 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_338 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_342 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_343 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_344 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_345 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_346 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_347 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_350 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_352 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_353 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_354 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_355 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_356 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_360 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_361 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_362 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_363 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_364 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_365 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_368 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_370 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_371 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_372 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_373 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_374 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_378 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_379 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_380 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_381 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_382 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_383 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_386 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_388 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_389 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_390 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_391 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_392 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_396 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_397 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_398 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_399 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_400 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_401 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_404 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_406 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_407 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_408 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_409 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_410 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_414 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_415 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_416 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_417 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_418 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_419 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_422 = 1'h0; // @[issue-unit-age-ordered.scala:253:25] wire _fu_code_match_T_424 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_425 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_426 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_427 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire _fu_code_match_T_428 = 1'h0; // @[issue-unit-age-ordered.scala:254:18] wire io_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:22:7] wire io_fu_types_0_6 = 1'h1; // @[issue-unit-age-ordered.scala:22:7] wire issue_slots_0_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] io_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] issue_slots_0_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_in_uop_bits_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_in_uop_bits_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_out_uop_iw_p1_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_out_uop_iw_p2_speculative_child = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_wakeup_ports_0_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_child_rebusys = 3'h0; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] shamts_oh_0 = 3'h0; // @[issue-unit-age-ordered.scala:158:23] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] issue_slots_0_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_pred_wakeup_port_bits = 5'h0; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] iss_uops_0_bits_inst; // @[issue-unit-age-ordered.scala:241:22] wire [31:0] iss_uops_0_bits_debug_inst; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_rvc; // @[issue-unit-age-ordered.scala:241:22] wire [39:0] iss_uops_0_bits_debug_pc; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iq_type_0; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iq_type_1; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iq_type_2; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iq_type_3; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_0; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_1; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_2; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_3; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_4; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_5; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_6; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_7; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_8; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fu_code_9; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_issued; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:241:22] wire [15:0] iss_uops_0_bits_br_mask; // @[issue-unit-age-ordered.scala:241:22] wire [3:0] iss_uops_0_bits_br_tag; // @[issue-unit-age-ordered.scala:241:22] wire [3:0] iss_uops_0_bits_br_type; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_sfb; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_fence; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_fencei; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_sfence; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_amo; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_eret; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_rocc; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_mov; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_ftq_idx; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_edge_inst; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_pc_lob; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_taken; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_imm_rename; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_imm_sel; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_pimm; // @[issue-unit-age-ordered.scala:241:22] wire [19:0] iss_uops_0_bits_imm_packed; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_op1_sel; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_op2_sel; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_rob_idx; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_ldq_idx; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_stq_idx; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_rxq_idx; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_pdst; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_prs1; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_prs2; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_prs3; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_ppred; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_prs1_busy; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_prs2_busy; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_prs3_busy; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_ppred_busy; // @[issue-unit-age-ordered.scala:241:22] wire [6:0] iss_uops_0_bits_stale_pdst; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_exception; // @[issue-unit-age-ordered.scala:241:22] wire [63:0] iss_uops_0_bits_exc_cause; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_mem_cmd; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_mem_size; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_mem_signed; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_uses_ldq; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_uses_stq; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_is_unique; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_csr_cmd; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_ldst; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_lrs1; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_lrs2; // @[issue-unit-age-ordered.scala:241:22] wire [5:0] iss_uops_0_bits_lrs3; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_dst_rtype; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_frs3_en; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fcn_dw; // @[issue-unit-age-ordered.scala:241:22] wire [4:0] iss_uops_0_bits_fcn_op; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_fp_val; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_fp_rm; // @[issue-unit-age-ordered.scala:241:22] wire [1:0] iss_uops_0_bits_fp_typ; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:241:22] wire iss_uops_0_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:241:22] wire [2:0] iss_uops_0_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:241:22] wire issue_slots_0_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_valid = io_wakeup_ports_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_16_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_17_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_18_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_19_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_20_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_21_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_22_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_23_wakeup_ports_0_bits_uop_inst = io_wakeup_ports_0_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_16_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_17_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_18_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_19_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_20_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_21_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_22_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_23_wakeup_ports_0_bits_uop_debug_inst = io_wakeup_ports_0_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_is_rvc = io_wakeup_ports_0_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_12_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_13_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_14_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_15_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_16_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_17_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_18_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_19_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_20_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_21_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_22_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_23_wakeup_ports_0_bits_uop_debug_pc = io_wakeup_ports_0_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_iq_type_0 = io_wakeup_ports_0_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_iq_type_1 = io_wakeup_ports_0_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_iq_type_2 = io_wakeup_ports_0_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_iq_type_3 = io_wakeup_ports_0_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fu_code_0 = io_wakeup_ports_0_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fu_code_1 = io_wakeup_ports_0_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fu_code_2 = io_wakeup_ports_0_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fu_code_3 = io_wakeup_ports_0_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fu_code_4 = io_wakeup_ports_0_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fu_code_5 = io_wakeup_ports_0_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fu_code_6 = io_wakeup_ports_0_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fu_code_7 = io_wakeup_ports_0_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fu_code_8 = io_wakeup_ports_0_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fu_code_9 = io_wakeup_ports_0_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_iw_issued = io_wakeup_ports_0_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_iw_issued_partial_agen = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_0_bits_uop_iw_p1_speculative_child = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_0_bits_uop_iw_p2_speculative_child = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_0_bits_uop_dis_col_sel = io_wakeup_ports_0_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_16_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_17_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_18_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_19_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_20_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_21_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_22_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_23_wakeup_ports_0_bits_uop_br_mask = io_wakeup_ports_0_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_16_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_17_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_18_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_19_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_20_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_21_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_22_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_23_wakeup_ports_0_bits_uop_br_tag = io_wakeup_ports_0_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_16_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_17_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_18_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_19_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_20_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_21_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_22_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_23_wakeup_ports_0_bits_uop_br_type = io_wakeup_ports_0_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_is_sfb = io_wakeup_ports_0_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_is_fence = io_wakeup_ports_0_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_is_fencei = io_wakeup_ports_0_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_is_sfence = io_wakeup_ports_0_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_is_amo = io_wakeup_ports_0_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_is_eret = io_wakeup_ports_0_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_is_sys_pc2epc = io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_is_rocc = io_wakeup_ports_0_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_is_mov = io_wakeup_ports_0_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_wakeup_ports_0_bits_uop_ftq_idx = io_wakeup_ports_0_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_edge_inst = io_wakeup_ports_0_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_16_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_17_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_18_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_19_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_20_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_21_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_22_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_23_wakeup_ports_0_bits_uop_pc_lob = io_wakeup_ports_0_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_taken = io_wakeup_ports_0_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_imm_rename = io_wakeup_ports_0_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_0_bits_uop_imm_sel = io_wakeup_ports_0_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_wakeup_ports_0_bits_uop_pimm = io_wakeup_ports_0_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_12_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_13_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_14_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_15_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_16_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_17_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_18_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_19_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_20_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_21_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_22_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_23_wakeup_ports_0_bits_uop_imm_packed = io_wakeup_ports_0_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_0_bits_uop_op1_sel = io_wakeup_ports_0_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_0_bits_uop_op2_sel = io_wakeup_ports_0_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_ldst = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_wen = io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_fromint = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_toint = io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_fma = io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_div = io_wakeup_ports_0_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_wflags = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_ctrl_vec = io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_wakeup_ports_0_bits_uop_rob_idx = io_wakeup_ports_0_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_wakeup_ports_0_bits_uop_ldq_idx = io_wakeup_ports_0_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_wakeup_ports_0_bits_uop_stq_idx = io_wakeup_ports_0_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_0_bits_uop_rxq_idx = io_wakeup_ports_0_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_wakeup_ports_0_bits_uop_pdst = io_wakeup_ports_0_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_wakeup_ports_0_bits_uop_prs1 = io_wakeup_ports_0_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_wakeup_ports_0_bits_uop_prs2 = io_wakeup_ports_0_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_wakeup_ports_0_bits_uop_prs3 = io_wakeup_ports_0_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_wakeup_ports_0_bits_uop_ppred = io_wakeup_ports_0_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_prs1_busy = io_wakeup_ports_0_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_prs2_busy = io_wakeup_ports_0_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_prs3_busy = io_wakeup_ports_0_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_ppred_busy = io_wakeup_ports_0_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_wakeup_ports_0_bits_uop_stale_pdst = io_wakeup_ports_0_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_exception = io_wakeup_ports_0_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_12_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_13_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_14_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_15_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_16_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_17_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_18_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_19_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_20_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_21_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_22_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_23_wakeup_ports_0_bits_uop_exc_cause = io_wakeup_ports_0_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_wakeup_ports_0_bits_uop_mem_cmd = io_wakeup_ports_0_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_0_bits_uop_mem_size = io_wakeup_ports_0_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_mem_signed = io_wakeup_ports_0_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_uses_ldq = io_wakeup_ports_0_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_uses_stq = io_wakeup_ports_0_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_is_unique = io_wakeup_ports_0_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_flush_on_commit = io_wakeup_ports_0_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_0_bits_uop_csr_cmd = io_wakeup_ports_0_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_ldst_is_rs1 = io_wakeup_ports_0_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_16_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_17_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_18_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_19_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_20_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_21_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_22_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_23_wakeup_ports_0_bits_uop_ldst = io_wakeup_ports_0_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_16_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_17_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_18_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_19_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_20_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_21_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_22_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_23_wakeup_ports_0_bits_uop_lrs1 = io_wakeup_ports_0_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_16_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_17_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_18_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_19_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_20_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_21_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_22_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_23_wakeup_ports_0_bits_uop_lrs2 = io_wakeup_ports_0_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_16_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_17_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_18_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_19_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_20_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_21_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_22_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_23_wakeup_ports_0_bits_uop_lrs3 = io_wakeup_ports_0_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_0_bits_uop_dst_rtype = io_wakeup_ports_0_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_0_bits_uop_lrs1_rtype = io_wakeup_ports_0_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_0_bits_uop_lrs2_rtype = io_wakeup_ports_0_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_frs3_en = io_wakeup_ports_0_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fcn_dw = io_wakeup_ports_0_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_wakeup_ports_0_bits_uop_fcn_op = io_wakeup_ports_0_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_fp_val = io_wakeup_ports_0_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_0_bits_uop_fp_rm = io_wakeup_ports_0_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_0_bits_uop_fp_typ = io_wakeup_ports_0_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_xcpt_pf_if = io_wakeup_ports_0_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_xcpt_ae_if = io_wakeup_ports_0_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_xcpt_ma_if = io_wakeup_ports_0_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_bp_debug_if = io_wakeup_ports_0_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_0_bits_uop_bp_xcpt_if = io_wakeup_ports_0_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_0_bits_uop_debug_fsrc = io_wakeup_ports_0_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_0_bits_uop_debug_tsrc = io_wakeup_ports_0_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_valid = io_wakeup_ports_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_16_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_17_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_18_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_19_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_20_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_21_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_22_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_23_wakeup_ports_1_bits_uop_inst = io_wakeup_ports_1_bits_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_16_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_17_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_18_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_19_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_20_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_21_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_22_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_23_wakeup_ports_1_bits_uop_debug_inst = io_wakeup_ports_1_bits_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_is_rvc = io_wakeup_ports_1_bits_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_12_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_13_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_14_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_15_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_16_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_17_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_18_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_19_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_20_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_21_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_22_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_23_wakeup_ports_1_bits_uop_debug_pc = io_wakeup_ports_1_bits_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_iq_type_0 = io_wakeup_ports_1_bits_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_iq_type_1 = io_wakeup_ports_1_bits_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_iq_type_2 = io_wakeup_ports_1_bits_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_iq_type_3 = io_wakeup_ports_1_bits_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fu_code_0 = io_wakeup_ports_1_bits_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fu_code_1 = io_wakeup_ports_1_bits_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fu_code_2 = io_wakeup_ports_1_bits_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fu_code_3 = io_wakeup_ports_1_bits_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fu_code_4 = io_wakeup_ports_1_bits_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fu_code_5 = io_wakeup_ports_1_bits_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fu_code_6 = io_wakeup_ports_1_bits_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fu_code_7 = io_wakeup_ports_1_bits_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fu_code_8 = io_wakeup_ports_1_bits_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fu_code_9 = io_wakeup_ports_1_bits_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_iw_issued = io_wakeup_ports_1_bits_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_iw_issued_partial_agen = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_iw_issued_partial_dgen = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_1_bits_uop_iw_p1_speculative_child = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_1_bits_uop_iw_p2_speculative_child = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_iw_p1_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_iw_p2_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_iw_p3_bypass_hint = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_1_bits_uop_dis_col_sel = io_wakeup_ports_1_bits_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_16_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_17_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_18_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_19_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_20_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_21_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_22_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_23_wakeup_ports_1_bits_uop_br_mask = io_wakeup_ports_1_bits_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_16_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_17_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_18_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_19_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_20_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_21_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_22_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_23_wakeup_ports_1_bits_uop_br_tag = io_wakeup_ports_1_bits_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_16_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_17_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_18_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_19_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_20_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_21_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_22_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_23_wakeup_ports_1_bits_uop_br_type = io_wakeup_ports_1_bits_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_is_sfb = io_wakeup_ports_1_bits_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_is_fence = io_wakeup_ports_1_bits_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_is_fencei = io_wakeup_ports_1_bits_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_is_sfence = io_wakeup_ports_1_bits_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_is_amo = io_wakeup_ports_1_bits_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_is_eret = io_wakeup_ports_1_bits_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_is_sys_pc2epc = io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_is_rocc = io_wakeup_ports_1_bits_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_is_mov = io_wakeup_ports_1_bits_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_wakeup_ports_1_bits_uop_ftq_idx = io_wakeup_ports_1_bits_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_edge_inst = io_wakeup_ports_1_bits_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_16_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_17_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_18_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_19_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_20_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_21_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_22_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_23_wakeup_ports_1_bits_uop_pc_lob = io_wakeup_ports_1_bits_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_taken = io_wakeup_ports_1_bits_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_imm_rename = io_wakeup_ports_1_bits_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_1_bits_uop_imm_sel = io_wakeup_ports_1_bits_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_wakeup_ports_1_bits_uop_pimm = io_wakeup_ports_1_bits_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_12_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_13_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_14_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_15_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_16_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_17_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_18_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_19_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_20_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_21_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_22_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_23_wakeup_ports_1_bits_uop_imm_packed = io_wakeup_ports_1_bits_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_1_bits_uop_op1_sel = io_wakeup_ports_1_bits_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_1_bits_uop_op2_sel = io_wakeup_ports_1_bits_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_ldst = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_wen = io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_ren1 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_ren2 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_ren3 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_swap12 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_swap23 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_fromint = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_toint = io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_fma = io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_div = io_wakeup_ports_1_bits_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_sqrt = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_wflags = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_ctrl_vec = io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_wakeup_ports_1_bits_uop_rob_idx = io_wakeup_ports_1_bits_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_wakeup_ports_1_bits_uop_ldq_idx = io_wakeup_ports_1_bits_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_wakeup_ports_1_bits_uop_stq_idx = io_wakeup_ports_1_bits_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_1_bits_uop_rxq_idx = io_wakeup_ports_1_bits_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_wakeup_ports_1_bits_uop_pdst = io_wakeup_ports_1_bits_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_wakeup_ports_1_bits_uop_prs1 = io_wakeup_ports_1_bits_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_wakeup_ports_1_bits_uop_prs2 = io_wakeup_ports_1_bits_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_wakeup_ports_1_bits_uop_prs3 = io_wakeup_ports_1_bits_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_wakeup_ports_1_bits_uop_ppred = io_wakeup_ports_1_bits_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_prs1_busy = io_wakeup_ports_1_bits_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_prs2_busy = io_wakeup_ports_1_bits_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_prs3_busy = io_wakeup_ports_1_bits_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_ppred_busy = io_wakeup_ports_1_bits_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_wakeup_ports_1_bits_uop_stale_pdst = io_wakeup_ports_1_bits_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_exception = io_wakeup_ports_1_bits_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_12_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_13_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_14_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_15_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_16_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_17_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_18_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_19_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_20_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_21_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_22_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_23_wakeup_ports_1_bits_uop_exc_cause = io_wakeup_ports_1_bits_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_wakeup_ports_1_bits_uop_mem_cmd = io_wakeup_ports_1_bits_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_1_bits_uop_mem_size = io_wakeup_ports_1_bits_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_mem_signed = io_wakeup_ports_1_bits_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_uses_ldq = io_wakeup_ports_1_bits_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_uses_stq = io_wakeup_ports_1_bits_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_is_unique = io_wakeup_ports_1_bits_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_flush_on_commit = io_wakeup_ports_1_bits_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_1_bits_uop_csr_cmd = io_wakeup_ports_1_bits_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_ldst_is_rs1 = io_wakeup_ports_1_bits_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_16_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_17_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_18_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_19_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_20_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_21_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_22_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_23_wakeup_ports_1_bits_uop_ldst = io_wakeup_ports_1_bits_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_16_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_17_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_18_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_19_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_20_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_21_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_22_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_23_wakeup_ports_1_bits_uop_lrs1 = io_wakeup_ports_1_bits_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_16_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_17_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_18_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_19_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_20_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_21_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_22_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_23_wakeup_ports_1_bits_uop_lrs2 = io_wakeup_ports_1_bits_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_16_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_17_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_18_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_19_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_20_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_21_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_22_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_23_wakeup_ports_1_bits_uop_lrs3 = io_wakeup_ports_1_bits_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_1_bits_uop_dst_rtype = io_wakeup_ports_1_bits_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_1_bits_uop_lrs1_rtype = io_wakeup_ports_1_bits_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_1_bits_uop_lrs2_rtype = io_wakeup_ports_1_bits_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_frs3_en = io_wakeup_ports_1_bits_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fcn_dw = io_wakeup_ports_1_bits_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_wakeup_ports_1_bits_uop_fcn_op = io_wakeup_ports_1_bits_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_fp_val = io_wakeup_ports_1_bits_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_1_bits_uop_fp_rm = io_wakeup_ports_1_bits_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_wakeup_ports_1_bits_uop_fp_typ = io_wakeup_ports_1_bits_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_xcpt_pf_if = io_wakeup_ports_1_bits_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_xcpt_ae_if = io_wakeup_ports_1_bits_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_xcpt_ma_if = io_wakeup_ports_1_bits_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_bp_debug_if = io_wakeup_ports_1_bits_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_wakeup_ports_1_bits_uop_bp_xcpt_if = io_wakeup_ports_1_bits_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_1_bits_uop_debug_fsrc = io_wakeup_ports_1_bits_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_wakeup_ports_1_bits_uop_debug_tsrc = io_wakeup_ports_1_bits_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_16_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_17_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_18_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_19_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_20_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_21_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_22_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_23_brupdate_b1_resolve_mask = io_brupdate_b1_resolve_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_16_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_17_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_18_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_19_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_20_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_21_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_22_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_23_brupdate_b1_mispredict_mask = io_brupdate_b1_mispredict_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_16_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_17_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_18_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_19_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_20_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_21_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_22_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_23_brupdate_b2_uop_inst = io_brupdate_b2_uop_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_0_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_1_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_2_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_3_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_4_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_5_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_6_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_7_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_8_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_9_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_10_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_11_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_12_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_13_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_14_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_15_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_16_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_17_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_18_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_19_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_20_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_21_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_22_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [31:0] issue_slots_23_brupdate_b2_uop_debug_inst = io_brupdate_b2_uop_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_is_rvc = io_brupdate_b2_uop_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_12_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_13_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_14_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_15_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_16_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_17_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_18_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_19_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_20_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_21_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_22_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_23_brupdate_b2_uop_debug_pc = io_brupdate_b2_uop_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_iq_type_1 = io_brupdate_b2_uop_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_iq_type_2 = io_brupdate_b2_uop_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_iq_type_3 = io_brupdate_b2_uop_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fu_code_1 = io_brupdate_b2_uop_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fu_code_2 = io_brupdate_b2_uop_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fu_code_3 = io_brupdate_b2_uop_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fu_code_4 = io_brupdate_b2_uop_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fu_code_5 = io_brupdate_b2_uop_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fu_code_6 = io_brupdate_b2_uop_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fu_code_7 = io_brupdate_b2_uop_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fu_code_8 = io_brupdate_b2_uop_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fu_code_9 = io_brupdate_b2_uop_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_iw_issued = io_brupdate_b2_uop_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_iw_issued_partial_agen = io_brupdate_b2_uop_iw_issued_partial_agen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_iw_issued_partial_dgen = io_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_brupdate_b2_uop_iw_p1_speculative_child = io_brupdate_b2_uop_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_brupdate_b2_uop_iw_p2_speculative_child = io_brupdate_b2_uop_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_iw_p1_bypass_hint = io_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_iw_p2_bypass_hint = io_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_iw_p3_bypass_hint = io_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_brupdate_b2_uop_dis_col_sel = io_brupdate_b2_uop_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_0_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_1_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_2_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_3_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_4_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_5_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_6_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_7_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_8_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_9_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_10_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_11_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_12_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_13_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_14_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_15_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_16_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_17_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_18_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_19_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_20_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_21_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_22_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [15:0] issue_slots_23_brupdate_b2_uop_br_mask = io_brupdate_b2_uop_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_16_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_17_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_18_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_19_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_20_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_21_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_22_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_23_brupdate_b2_uop_br_tag = io_brupdate_b2_uop_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_0_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_1_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_2_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_3_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_4_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_5_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_6_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_7_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_8_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_9_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_10_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_11_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_12_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_13_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_14_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_15_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_16_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_17_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_18_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_19_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_20_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_21_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_22_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [3:0] issue_slots_23_brupdate_b2_uop_br_type = io_brupdate_b2_uop_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_is_sfb = io_brupdate_b2_uop_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_is_fence = io_brupdate_b2_uop_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_is_fencei = io_brupdate_b2_uop_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_is_sfence = io_brupdate_b2_uop_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_is_amo = io_brupdate_b2_uop_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_is_eret = io_brupdate_b2_uop_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_is_sys_pc2epc = io_brupdate_b2_uop_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_is_rocc = io_brupdate_b2_uop_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_is_mov = io_brupdate_b2_uop_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_brupdate_b2_uop_ftq_idx = io_brupdate_b2_uop_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_edge_inst = io_brupdate_b2_uop_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_16_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_17_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_18_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_19_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_20_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_21_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_22_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_23_brupdate_b2_uop_pc_lob = io_brupdate_b2_uop_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_taken = io_brupdate_b2_uop_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_imm_rename = io_brupdate_b2_uop_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_brupdate_b2_uop_imm_sel = io_brupdate_b2_uop_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_brupdate_b2_uop_pimm = io_brupdate_b2_uop_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_0_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_1_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_2_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_3_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_4_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_5_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_6_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_7_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_8_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_9_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_10_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_11_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_12_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_13_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_14_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_15_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_16_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_17_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_18_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_19_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_20_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_21_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_22_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [19:0] issue_slots_23_brupdate_b2_uop_imm_packed = io_brupdate_b2_uop_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_brupdate_b2_uop_op1_sel = io_brupdate_b2_uop_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_brupdate_b2_uop_op2_sel = io_brupdate_b2_uop_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_ctrl_ldst = io_brupdate_b2_uop_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_ctrl_wen = io_brupdate_b2_uop_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_ctrl_ren1 = io_brupdate_b2_uop_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_ctrl_ren2 = io_brupdate_b2_uop_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_ctrl_ren3 = io_brupdate_b2_uop_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_ctrl_swap12 = io_brupdate_b2_uop_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_ctrl_swap23 = io_brupdate_b2_uop_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_brupdate_b2_uop_fp_ctrl_typeTagIn = io_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_brupdate_b2_uop_fp_ctrl_typeTagOut = io_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_ctrl_fromint = io_brupdate_b2_uop_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_ctrl_toint = io_brupdate_b2_uop_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_ctrl_fastpipe = io_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_ctrl_fma = io_brupdate_b2_uop_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_ctrl_div = io_brupdate_b2_uop_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_ctrl_sqrt = io_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_ctrl_wflags = io_brupdate_b2_uop_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_ctrl_vec = io_brupdate_b2_uop_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_brupdate_b2_uop_rob_idx = io_brupdate_b2_uop_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_brupdate_b2_uop_ldq_idx = io_brupdate_b2_uop_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_brupdate_b2_uop_stq_idx = io_brupdate_b2_uop_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_brupdate_b2_uop_rxq_idx = io_brupdate_b2_uop_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_brupdate_b2_uop_pdst = io_brupdate_b2_uop_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_brupdate_b2_uop_prs1 = io_brupdate_b2_uop_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_brupdate_b2_uop_prs2 = io_brupdate_b2_uop_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_brupdate_b2_uop_prs3 = io_brupdate_b2_uop_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_brupdate_b2_uop_ppred = io_brupdate_b2_uop_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_prs1_busy = io_brupdate_b2_uop_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_prs2_busy = io_brupdate_b2_uop_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_prs3_busy = io_brupdate_b2_uop_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_ppred_busy = io_brupdate_b2_uop_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_0_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_1_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_2_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_3_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_4_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_5_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_6_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_7_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_8_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_9_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_10_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_11_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_12_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_13_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_14_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_15_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_16_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_17_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_18_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_19_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_20_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_21_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_22_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [6:0] issue_slots_23_brupdate_b2_uop_stale_pdst = io_brupdate_b2_uop_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_exception = io_brupdate_b2_uop_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_0_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_1_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_2_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_3_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_4_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_5_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_6_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_7_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_8_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_9_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_10_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_11_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_12_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_13_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_14_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_15_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_16_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_17_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_18_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_19_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_20_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_21_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_22_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [63:0] issue_slots_23_brupdate_b2_uop_exc_cause = io_brupdate_b2_uop_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_brupdate_b2_uop_mem_cmd = io_brupdate_b2_uop_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_brupdate_b2_uop_mem_size = io_brupdate_b2_uop_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_mem_signed = io_brupdate_b2_uop_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_uses_ldq = io_brupdate_b2_uop_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_uses_stq = io_brupdate_b2_uop_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_is_unique = io_brupdate_b2_uop_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_flush_on_commit = io_brupdate_b2_uop_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_brupdate_b2_uop_csr_cmd = io_brupdate_b2_uop_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_ldst_is_rs1 = io_brupdate_b2_uop_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_16_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_17_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_18_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_19_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_20_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_21_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_22_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_23_brupdate_b2_uop_ldst = io_brupdate_b2_uop_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_16_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_17_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_18_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_19_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_20_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_21_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_22_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_23_brupdate_b2_uop_lrs1 = io_brupdate_b2_uop_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_16_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_17_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_18_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_19_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_20_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_21_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_22_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_23_brupdate_b2_uop_lrs2 = io_brupdate_b2_uop_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_0_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_1_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_2_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_3_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_4_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_5_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_6_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_7_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_8_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_9_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_10_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_11_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_12_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_13_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_14_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_15_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_16_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_17_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_18_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_19_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_20_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_21_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_22_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [5:0] issue_slots_23_brupdate_b2_uop_lrs3 = io_brupdate_b2_uop_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_brupdate_b2_uop_dst_rtype = io_brupdate_b2_uop_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_brupdate_b2_uop_lrs1_rtype = io_brupdate_b2_uop_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_brupdate_b2_uop_lrs2_rtype = io_brupdate_b2_uop_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_frs3_en = io_brupdate_b2_uop_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fcn_dw = io_brupdate_b2_uop_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_0_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_1_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_2_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_3_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_4_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_5_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_6_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_7_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_8_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_9_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_10_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_11_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_12_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_13_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_14_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_15_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_16_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_17_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_18_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_19_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_20_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_21_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_22_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [4:0] issue_slots_23_brupdate_b2_uop_fcn_op = io_brupdate_b2_uop_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_fp_val = io_brupdate_b2_uop_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_brupdate_b2_uop_fp_rm = io_brupdate_b2_uop_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_brupdate_b2_uop_fp_typ = io_brupdate_b2_uop_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_xcpt_pf_if = io_brupdate_b2_uop_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_xcpt_ae_if = io_brupdate_b2_uop_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_xcpt_ma_if = io_brupdate_b2_uop_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_bp_debug_if = io_brupdate_b2_uop_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_uop_bp_xcpt_if = io_brupdate_b2_uop_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_brupdate_b2_uop_debug_fsrc = io_brupdate_b2_uop_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_brupdate_b2_uop_debug_tsrc = io_brupdate_b2_uop_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_mispredict = io_brupdate_b2_mispredict_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_brupdate_b2_taken = io_brupdate_b2_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_0_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_1_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_2_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_3_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_4_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_5_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_6_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_7_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_8_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_9_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_10_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_11_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_12_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_13_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_14_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_15_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_16_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_17_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_18_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_19_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_20_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_21_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_22_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [2:0] issue_slots_23_brupdate_b2_cfi_type = io_brupdate_b2_cfi_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_0_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_1_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_2_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_3_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_4_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_5_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_6_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_7_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_8_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_9_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_10_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_11_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_12_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_13_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_14_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_15_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_16_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_17_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_18_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_19_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_20_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_21_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_22_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [1:0] issue_slots_23_brupdate_b2_pc_sel = io_brupdate_b2_pc_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_0_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_1_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_2_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_3_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_4_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_5_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_6_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_7_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_8_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_9_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_10_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_11_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_12_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_13_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_14_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_15_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_16_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_17_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_18_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_19_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_20_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_21_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_22_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [39:0] issue_slots_23_brupdate_b2_jalr_target = io_brupdate_b2_jalr_target_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_0_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_1_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_2_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_3_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_4_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_5_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_6_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_7_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_8_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_9_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_10_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_11_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_12_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_13_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_14_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_15_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_16_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_17_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_18_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_19_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_20_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_21_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_22_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire [20:0] issue_slots_23_brupdate_b2_target_offset = io_brupdate_b2_target_offset_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_kill = io_flush_pipeline_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_0_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_1_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_2_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_3_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_4_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_5_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_6_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_7_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_8_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_9_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_10_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_11_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_12_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_13_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_14_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_15_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_16_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_17_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_18_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_19_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_20_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_21_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_22_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire issue_slots_23_squash_grant = io_squash_grant_0; // @[issue-unit-age-ordered.scala:22:7, :122:28] wire io_dis_uops_0_ready_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_1_ready_0; // @[issue-unit-age-ordered.scala:22:7] wire io_dis_uops_2_ready_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_iss_uops_0_bits_inst_0; // @[issue-unit-age-ordered.scala:22:7] wire [31:0] io_iss_uops_0_bits_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7] wire [39:0] io_iss_uops_0_bits_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_issued_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_p1_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_p2_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_iw_p3_bypass_hint_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [15:0] io_iss_uops_0_bits_br_mask_0; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_iss_uops_0_bits_br_tag_0; // @[issue-unit-age-ordered.scala:22:7] wire [3:0] io_iss_uops_0_bits_br_type_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_amo_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_eret_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_mov_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_taken_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_pimm_0; // @[issue-unit-age-ordered.scala:22:7] wire [19:0] io_iss_uops_0_bits_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_pdst_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_ppred_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_ppred_busy_0; // @[issue-unit-age-ordered.scala:22:7] wire [6:0] io_iss_uops_0_bits_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7] wire [63:0] io_iss_uops_0_bits_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_mem_size_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_is_unique_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_ldst_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_lrs1_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_lrs2_0; // @[issue-unit-age-ordered.scala:22:7] wire [5:0] io_iss_uops_0_bits_lrs3_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7] wire [4:0] io_iss_uops_0_bits_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_fp_val_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7] wire [1:0] io_iss_uops_0_bits_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_bits_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7] wire [2:0] io_iss_uops_0_bits_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7] wire io_iss_uops_0_valid_0; // @[issue-unit-age-ordered.scala:22:7] wire prs1_matches_0 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs2_matches_0 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs3_matches_0 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs1_wakeups_0 = io_wakeup_ports_0_valid_0 & prs1_matches_0; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_1 = io_wakeup_ports_1_valid_0 & prs1_matches_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs2_wakeups_0 = io_wakeup_ports_0_valid_0 & prs2_matches_0; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_1 = io_wakeup_ports_1_valid_0 & prs2_matches_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs3_wakeups_0 = io_wakeup_ports_0_valid_0 & prs3_matches_0; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_1 = io_wakeup_ports_1_valid_0 & prs3_matches_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire _T = prs1_wakeups_0 \| prs1_wakeups_1; // @[issue-unit-age-ordered.scala:47:89, :57:32] wire _WIRE_iw_p1_bypass_hint = _T & prs1_wakeups_0; // @[issue-unit-age-ordered.scala:39:35, :47:89, :57:{32,38}, :60:37] wire _T_12 = prs2_wakeups_0 \| prs2_wakeups_1; // @[issue-unit-age-ordered.scala:48:89, :65:32] wire _WIRE_prs2_busy = ~_T_12 & io_dis_uops_0_bits_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :65:{32,38}, :66:29] wire _WIRE_iw_p2_bypass_hint = _T_12 & prs2_wakeups_0; // @[issue-unit-age-ordered.scala:40:35, :48:89, :65:{32,38}, :68:37] wire _T_24 = prs3_wakeups_0 \| prs3_wakeups_1; // @[issue-unit-age-ordered.scala:49:89, :76:32] wire _WIRE_prs3_busy = ~_T_24 & io_dis_uops_0_bits_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :76:{32,38}, :77:29] wire _WIRE_iw_p3_bypass_hint = _T_24 & prs3_wakeups_0; // @[issue-unit-age-ordered.scala:41:35, :49:89, :76:{32,38}, :78:37] wire [1:0] _WIRE_lrs1_rtype = io_dis_uops_0_bits_uses_stq_0 ? 2'h2 : io_dis_uops_0_bits_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :103:43, :104:32] wire _WIRE_prs1_busy = ~io_dis_uops_0_bits_uses_stq_0 & ~_T & io_dis_uops_0_bits_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :57:{32,38}, :58:29, :62:116, :103:43, :105:32] wire prs1_matches_0_1 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_1_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_1_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs2_matches_0_1 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_1_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_1_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs3_matches_0_1 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_1_1 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_1_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs1_wakeups_0_1 = io_wakeup_ports_0_valid_0 & prs1_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_1_1 = io_wakeup_ports_1_valid_0 & prs1_matches_1_1; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs2_wakeups_0_1 = io_wakeup_ports_0_valid_0 & prs2_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_1_1 = io_wakeup_ports_1_valid_0 & prs2_matches_1_1; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs3_wakeups_0_1 = io_wakeup_ports_0_valid_0 & prs3_matches_0_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_1_1 = io_wakeup_ports_1_valid_0 & prs3_matches_1_1; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire _T_35 = prs1_wakeups_0_1 \| prs1_wakeups_1_1; // @[issue-unit-age-ordered.scala:47:89, :57:32] wire [2:0] _WIRE_1_iw_p1_speculative_child = _T_35 ? 3'h0 : io_dis_uops_1_bits_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :57:{32,38}, :59:43] wire _WIRE_1_iw_p1_bypass_hint = _T_35 & prs1_wakeups_0_1; // @[issue-unit-age-ordered.scala:39:35, :47:89, :57:{32,38}, :60:37] wire _T_47 = prs2_wakeups_0_1 \| prs2_wakeups_1_1; // @[issue-unit-age-ordered.scala:48:89, :65:32] wire _WIRE_1_prs2_busy = ~_T_47 & io_dis_uops_1_bits_prs2_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :65:{32,38}, :66:29] wire [2:0] _WIRE_1_iw_p2_speculative_child = _T_47 ? 3'h0 : io_dis_uops_1_bits_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :65:{32,38}, :67:43] wire _WIRE_1_iw_p2_bypass_hint = _T_47 & prs2_wakeups_0_1; // @[issue-unit-age-ordered.scala:40:35, :48:89, :65:{32,38}, :68:37] wire _T_59 = prs3_wakeups_0_1 \| prs3_wakeups_1_1; // @[issue-unit-age-ordered.scala:49:89, :76:32] wire _WIRE_1_prs3_busy = ~_T_59 & io_dis_uops_1_bits_prs3_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :76:{32,38}, :77:29] wire _WIRE_1_iw_p3_bypass_hint = _T_59 & prs3_wakeups_0_1; // @[issue-unit-age-ordered.scala:41:35, :49:89, :76:{32,38}, :78:37] wire [1:0] _WIRE_1_lrs1_rtype = io_dis_uops_1_bits_uses_stq_0 ? 2'h2 : io_dis_uops_1_bits_lrs1_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :103:43, :104:32] wire _WIRE_1_prs1_busy = ~io_dis_uops_1_bits_uses_stq_0 & ~_T_35 & io_dis_uops_1_bits_prs1_busy_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :57:{32,38}, :58:29, :62:116, :103:43, :105:32] wire prs1_matches_0_2 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_2_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs1_matches_1_2 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_2_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :44:69] wire prs2_matches_0_2 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_2_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs2_matches_1_2 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_2_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :45:69] wire prs3_matches_0_2 = io_wakeup_ports_0_bits_uop_pdst_0 == io_dis_uops_2_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs3_matches_1_2 = io_wakeup_ports_1_bits_uop_pdst_0 == io_dis_uops_2_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :46:69] wire prs1_wakeups_0_2 = io_wakeup_ports_0_valid_0 & prs1_matches_0_2; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs1_wakeups_1_2 = io_wakeup_ports_1_valid_0 & prs1_matches_1_2; // @[issue-unit-age-ordered.scala:22:7, :44:69, :47:89] wire prs2_wakeups_0_2 = io_wakeup_ports_0_valid_0 & prs2_matches_0_2; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs2_wakeups_1_2 = io_wakeup_ports_1_valid_0 & prs2_matches_1_2; // @[issue-unit-age-ordered.scala:22:7, :45:69, :48:89] wire prs3_wakeups_0_2 = io_wakeup_ports_0_valid_0 & prs3_matches_0_2; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire prs3_wakeups_1_2 = io_wakeup_ports_1_valid_0 & prs3_matches_1_2; // @[issue-unit-age-ordered.scala:22:7, :46:69, :49:89] wire _T_70 = prs1_wakeups_0_2 \| prs1_wakeups_1_2; // @[issue-unit-age-ordered.scala:47:89, :57:32] wire _T_82 = prs2_wakeups_0_2 \| prs2_wakeups_1_2; // @[issue-unit-age-ordered.scala:48:89, :65:32] wire _T_94 = prs3_wakeups_0_2 \| prs3_wakeups_1_2; // @[issue-unit-age-ordered.scala:49:89, :76:32] wire _fu_code_match_T_6 = issue_slots_0_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _fu_code_match_T_24 = issue_slots_1_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_1_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_42 = issue_slots_2_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_2_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_60 = issue_slots_3_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_3_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_78 = issue_slots_4_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_4_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_96 = issue_slots_5_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_5_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_114 = issue_slots_6_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_6_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_132 = issue_slots_7_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_7_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_150 = issue_slots_8_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_8_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_168 = issue_slots_9_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_9_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_186 = issue_slots_10_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_10_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_204 = issue_slots_11_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_11_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_222 = issue_slots_12_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_12_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_240 = issue_slots_13_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_13_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_258 = issue_slots_14_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_14_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_276 = issue_slots_15_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_15_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_294 = issue_slots_16_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_16_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_312 = issue_slots_17_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_17_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_330 = issue_slots_18_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_18_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_348 = issue_slots_19_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_19_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_366 = issue_slots_20_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_20_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_384 = issue_slots_21_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_21_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_402 = issue_slots_22_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_22_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire _fu_code_match_T_420 = issue_slots_23_iss_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :253:25] wire _issue_slots_23_clear_T; // @[issue-unit-age-ordered.scala:199:49] wire issue_slots_0_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_0_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_0_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_0_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_0_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_0_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_0_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_0_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_0_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_0_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_0_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_0_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_0_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_0_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_0_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_0_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_0_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_0_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_0_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_0_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_0_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_1_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_1_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_1_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_1_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_1_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_1_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_1_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_1_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_1_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_1_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_1_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_1_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_1_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_1_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_1_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_1_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_1_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_1_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_1_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_1_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_2_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_2_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_2_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_2_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_2_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_2_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_2_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_2_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_2_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_2_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_2_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_2_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_2_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_2_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_2_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_2_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_2_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_2_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_2_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_2_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_3_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_3_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_3_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_3_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_3_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_3_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_3_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_3_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_3_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_3_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_3_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_3_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_3_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_3_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_3_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_3_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_3_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_3_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_3_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_3_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_4_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_4_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_4_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_4_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_4_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_4_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_4_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_4_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_4_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_4_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_4_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_4_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_4_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_4_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_4_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_4_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_4_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_4_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_4_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_4_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_5_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_5_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_5_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_5_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_5_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_5_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_5_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_5_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_5_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_5_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_5_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_5_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_5_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_5_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_5_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_5_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_5_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_5_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_5_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_5_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_6_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_6_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_6_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_6_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_6_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_6_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_6_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_6_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_6_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_6_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_6_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_6_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_6_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_6_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_6_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_6_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_6_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_6_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_6_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_6_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_7_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_7_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_7_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_7_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_7_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_7_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_7_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_7_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_7_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_7_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_7_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_7_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_7_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_7_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_7_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_7_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_7_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_7_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_7_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_7_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_8_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_8_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_8_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_8_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_8_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_8_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_8_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_8_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_8_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_8_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_8_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_8_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_8_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_8_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_8_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_8_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_8_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_8_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_8_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_8_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_9_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_9_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_9_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_9_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_9_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_9_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_9_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_9_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_9_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_9_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_9_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_9_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_9_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_9_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_9_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_9_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_9_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_9_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_9_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_9_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_10_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_10_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_10_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_10_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_10_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_10_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_10_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_10_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_10_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_10_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_10_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_10_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_10_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_10_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_10_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_10_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_10_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_10_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_10_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_10_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_11_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_11_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_11_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_11_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_11_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_11_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_11_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_11_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_11_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_11_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_11_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_11_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_11_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_11_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_11_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_11_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_11_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_11_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_11_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_11_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_12_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_12_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_12_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_12_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_12_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_12_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_12_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_12_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_12_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_12_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_12_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_12_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_12_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_12_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_12_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_12_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_12_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_12_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_12_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_12_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_12_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_12_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_12_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_12_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_12_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_12_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_12_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_12_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_12_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_12_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_13_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_13_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_13_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_13_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_13_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_13_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_13_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_13_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_13_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_13_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_13_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_13_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_13_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_13_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_13_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_13_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_13_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_13_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_13_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_13_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_13_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_13_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_13_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_13_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_13_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_13_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_13_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_13_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_13_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_13_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_14_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_14_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_14_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_14_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_14_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_14_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_14_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_14_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_14_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_14_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_14_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_14_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_14_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_14_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_14_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_14_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_14_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_14_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_14_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_14_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_14_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_14_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_14_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_14_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_14_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_14_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_14_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_14_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_14_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_14_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_15_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_15_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_15_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_15_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_15_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_15_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_15_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_15_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_15_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_15_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_15_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_15_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_15_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_15_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_15_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_15_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_15_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_15_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_15_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_15_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_15_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_15_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_15_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_15_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_15_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_15_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_15_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_15_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_15_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_15_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_16_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_16_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_16_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_16_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_16_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_16_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_16_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_16_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_16_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_16_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_16_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_16_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_16_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_16_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_16_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_16_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_16_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_16_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_16_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_16_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_16_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_16_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_16_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_16_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_16_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_16_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_16_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_16_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_16_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_16_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_16_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_16_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_16_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_16_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_16_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_16_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_16_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_16_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_16_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_16_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_16_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_16_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_16_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_16_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_17_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_17_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_17_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_17_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_17_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_17_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_17_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_17_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_17_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_17_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_17_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_17_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_17_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_17_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_17_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_17_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_17_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_17_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_17_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_17_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_17_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_17_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_17_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_17_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_17_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_17_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_17_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_17_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_17_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_17_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_17_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_17_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_17_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_17_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_17_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_17_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_17_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_17_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_17_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_17_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_17_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_17_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_17_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_17_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_18_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_18_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_18_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_18_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_18_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_18_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_18_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_18_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_18_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_18_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_18_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_18_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_18_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_18_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_18_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_18_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_18_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_18_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_18_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_18_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_18_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_18_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_18_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_18_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_18_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_18_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_18_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_18_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_18_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_18_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_18_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_18_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_18_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_18_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_18_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_18_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_18_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_18_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_18_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_18_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_18_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_18_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_18_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_18_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_19_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_19_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_19_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_19_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_19_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_19_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_19_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_19_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_19_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_19_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_19_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_19_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_19_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_19_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_19_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_19_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_19_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_19_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_19_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_19_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_19_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_19_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_19_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_19_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_19_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_19_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_19_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_19_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_19_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_19_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_19_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_19_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_19_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_19_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_19_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_19_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_19_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_19_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_19_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_19_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_19_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_19_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_19_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_19_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_20_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_20_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_20_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_20_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_20_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_20_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_20_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_20_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_20_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_20_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_20_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_20_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_20_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_20_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_20_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_20_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_20_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_20_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_20_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_20_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_20_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_20_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_20_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_20_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_20_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_20_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_20_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_20_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_20_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_20_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_20_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_20_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_20_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_20_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_20_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_20_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_20_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_20_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_20_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_20_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_20_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_20_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_20_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_20_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_21_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_21_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_21_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_21_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_21_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_21_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_21_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_21_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_21_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_21_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_21_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_21_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_21_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_21_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_21_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_21_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_21_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_21_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_21_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_21_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_21_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_21_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_21_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_21_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_21_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_21_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_21_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_21_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_21_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_21_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_21_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_21_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_21_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_21_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_21_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_21_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_21_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_21_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_21_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_21_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_21_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_21_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_21_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_21_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_22_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_22_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_22_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_22_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_22_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_22_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_22_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_22_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_22_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_22_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_22_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_22_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_22_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_22_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_22_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_22_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_22_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_22_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_22_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_22_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_22_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_22_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_22_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_22_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_22_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_22_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_22_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_22_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_22_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_22_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_22_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_22_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_22_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_22_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_22_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_22_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_22_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_22_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_22_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_22_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_22_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_22_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_22_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_22_clear; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_iss_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_iss_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_23_iss_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_23_iss_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_23_iss_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_iss_uop_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_iss_uop_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_iss_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_23_iss_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_23_iss_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_23_iss_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_iss_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_23_iss_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_iss_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_iss_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_23_iss_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_iss_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_iss_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_iss_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_iss_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_iss_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_iss_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_iss_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_iss_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_iss_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_iss_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_iss_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_iss_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_23_iss_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_iss_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_iss_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_iss_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_23_iss_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_23_iss_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_23_iss_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_23_iss_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_iss_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_iss_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_iss_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_iss_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_iss_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_iss_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_iss_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_iss_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_iss_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_23_in_uop_bits_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_23_in_uop_bits_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_23_in_uop_bits_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_in_uop_bits_iw_p1_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_in_uop_bits_iw_p2_speculative_child; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_in_uop_bits_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_23_in_uop_bits_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_23_in_uop_bits_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_23_in_uop_bits_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_in_uop_bits_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_23_in_uop_bits_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_in_uop_bits_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_in_uop_bits_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_23_in_uop_bits_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_in_uop_bits_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_in_uop_bits_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_in_uop_bits_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_in_uop_bits_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_in_uop_bits_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_in_uop_bits_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_in_uop_bits_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_in_uop_bits_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_in_uop_bits_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_in_uop_bits_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_in_uop_bits_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_in_uop_bits_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_23_in_uop_bits_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_in_uop_bits_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_in_uop_bits_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_in_uop_bits_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_23_in_uop_bits_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_23_in_uop_bits_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_23_in_uop_bits_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_23_in_uop_bits_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_in_uop_bits_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_in_uop_bits_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_in_uop_bits_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_in_uop_bits_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_in_uop_bits_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_in_uop_bits_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_bits_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_in_uop_bits_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_in_uop_bits_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_in_uop_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_23_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28] wire [31:0] issue_slots_23_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28] wire [39:0] issue_slots_23_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28] wire [15:0] issue_slots_23_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_23_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28] wire [3:0] issue_slots_23_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_23_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28] wire [19:0] issue_slots_23_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28] wire [6:0] issue_slots_23_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28] wire [63:0] issue_slots_23_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_23_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_23_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_23_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28] wire [5:0] issue_slots_23_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28] wire [4:0] issue_slots_23_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28] wire [1:0] issue_slots_23_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28] wire [2:0] issue_slots_23_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_will_be_valid; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_request; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_grant; // @[issue-unit-age-ordered.scala:122:28] wire issue_slots_23_clear; // @[issue-unit-age-ordered.scala:122:28] wire vacants_0 = ~issue_slots_0_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_1 = ~issue_slots_1_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_2 = ~issue_slots_2_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_3 = ~issue_slots_3_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_4 = ~issue_slots_4_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_5 = ~issue_slots_5_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_6 = ~issue_slots_6_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_7 = ~issue_slots_7_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_8 = ~issue_slots_8_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_9 = ~issue_slots_9_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_10 = ~issue_slots_10_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_11 = ~issue_slots_11_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_12 = ~issue_slots_12_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_13 = ~issue_slots_13_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_14 = ~issue_slots_14_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_15 = ~issue_slots_15_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_16 = ~issue_slots_16_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_17 = ~issue_slots_17_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_18 = ~issue_slots_18_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_19 = ~issue_slots_19_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_20 = ~issue_slots_20_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_21 = ~issue_slots_21_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_22 = ~issue_slots_22_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_23 = ~issue_slots_23_valid; // @[issue-unit-age-ordered.scala:122:28, :157:38] wire vacants_24 = ~io_dis_uops_0_valid_0; // @[issue-unit-age-ordered.scala:22:7, :157:82] wire vacants_25 = ~io_dis_uops_1_valid_0; // @[issue-unit-age-ordered.scala:22:7, :157:82] wire vacants_26 = ~io_dis_uops_2_valid_0; // @[issue-unit-age-ordered.scala:22:7, :157:82] wire [2:0] shamts_oh_12_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_13_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_14_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_15_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_16_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_17_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_18_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_19_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_20_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_21_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_22_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_23_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_24_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_25_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_26_next; // @[issue-unit-age-ordered.scala:161:21] wire [2:0] shamts_oh_1; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_2; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_3; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_4; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_5; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_6; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_7; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_8; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_9; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_10; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_11; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_12; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_13; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_14; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_15; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_16; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_17; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_18; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_19; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_20; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_21; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_22; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_23; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_24; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_25; // @[issue-unit-age-ordered.scala:158:23] wire [2:0] shamts_oh_26; // @[issue-unit-age-ordered.scala:158:23] assign shamts_oh_1 = {2'h0, vacants_0}; // @[issue-unit-age-ordered.scala:141:19, :157:38, :158:23, :174:20] wire _GEN = vacants_0 \| vacants_1; // @[issue-unit-age-ordered.scala:157:38, :174:47] wire _shamts_oh_2_T; // @[issue-unit-age-ordered.scala:174:47] assign _shamts_oh_2_T = _GEN; // @[issue-unit-age-ordered.scala:174:47] wire _shamts_oh_3_T; // @[issue-unit-age-ordered.scala:174:47] assign _shamts_oh_3_T = _GEN; // @[issue-unit-age-ordered.scala:174:47] wire _shamts_oh_4_T; // @[issue-unit-age-ordered.scala:174:47] assign _shamts_oh_4_T = _GEN; // @[issue-unit-age-ordered.scala:174:47] wire _shamts_oh_5_T; // @[issue-unit-age-ordered.scala:174:47] assign _shamts_oh_5_T = _GEN; // @[issue-unit-age-ordered.scala:174:47] assign shamts_oh_2 = {2'h0, _shamts_oh_2_T}; // @[issue-unit-age-ordered.scala:141:19, :158:23, :174:{20,47}] wire _shamts_oh_3_T_1 = _shamts_oh_3_T \| vacants_2; // @[issue-unit-age-ordered.scala:157:38, :174:47] assign shamts_oh_3 = {2'h0, _shamts_oh_3_T_1}; // @[issue-unit-age-ordered.scala:141:19, :158:23, :174:{20,47}] wire _shamts_oh_4_T_1 = _shamts_oh_4_T \| vacants_2; // @[issue-unit-age-ordered.scala:157:38, :174:47] wire _shamts_oh_4_T_2 = _shamts_oh_4_T_1 \| vacants_3; // @[issue-unit-age-ordered.scala:157:38, :174:47] assign shamts_oh_4 = {2'h0, _shamts_oh_4_T_2}; // @[issue-unit-age-ordered.scala:141:19, :158:23, :174:{20,47}] wire _shamts_oh_5_T_1 = _shamts_oh_5_T \| vacants_2; // @[issue-unit-age-ordered.scala:157:38, :174:47] wire _shamts_oh_5_T_2 = _shamts_oh_5_T_1 \| vacants_3; // @[issue-unit-age-ordered.scala:157:38, :174:47] wire _shamts_oh_5_T_3 = _shamts_oh_5_T_2 \| vacants_4; // @[issue-unit-age-ordered.scala:157:38, :174:47] assign shamts_oh_5 = {2'h0, _shamts_oh_5_T_3}; // @[issue-unit-age-ordered.scala:141:19, :158:23, :174:{20,47}] wire [1:0] shamts_oh_6_next; // @[issue-unit-age-ordered.scala:161:21] wire _shamts_oh_6_T = ~(\|shamts_oh_5); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_6_T_1 = _shamts_oh_6_T & vacants_5; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_6_T_2 = shamts_oh_5[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_6_T_3 = ~_shamts_oh_6_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_6_T_4 = _shamts_oh_6_T_3 & vacants_5; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_6_next_T = {shamts_oh_5, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_6_next = _shamts_oh_6_T_1 ? 2'h1 : _shamts_oh_6_T_4 ? _shamts_oh_6_next_T[1:0] : shamts_oh_5[1:0]; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_6 = {1'h0, shamts_oh_6_next}; // @[issue-unit-age-ordered.scala:158:23, :161:21, :176:20] wire [1:0] shamts_oh_7_next; // @[issue-unit-age-ordered.scala:161:21] wire _shamts_oh_7_T = ~(\|shamts_oh_6); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_7_T_1 = _shamts_oh_7_T & vacants_6; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_7_T_2 = shamts_oh_6[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_7_T_3 = ~_shamts_oh_7_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_7_T_4 = _shamts_oh_7_T_3 & vacants_6; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_7_next_T = {shamts_oh_6, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_7_next = _shamts_oh_7_T_1 ? 2'h1 : _shamts_oh_7_T_4 ? _shamts_oh_7_next_T[1:0] : shamts_oh_6[1:0]; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_7 = {1'h0, shamts_oh_7_next}; // @[issue-unit-age-ordered.scala:158:23, :161:21, :176:20] wire [1:0] shamts_oh_8_next; // @[issue-unit-age-ordered.scala:161:21] wire _shamts_oh_8_T = ~(\|shamts_oh_7); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_8_T_1 = _shamts_oh_8_T & vacants_7; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_8_T_2 = shamts_oh_7[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_8_T_3 = ~_shamts_oh_8_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_8_T_4 = _shamts_oh_8_T_3 & vacants_7; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_8_next_T = {shamts_oh_7, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_8_next = _shamts_oh_8_T_1 ? 2'h1 : _shamts_oh_8_T_4 ? _shamts_oh_8_next_T[1:0] : shamts_oh_7[1:0]; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_8 = {1'h0, shamts_oh_8_next}; // @[issue-unit-age-ordered.scala:158:23, :161:21, :176:20] wire [1:0] shamts_oh_9_next; // @[issue-unit-age-ordered.scala:161:21] wire _shamts_oh_9_T = ~(\|shamts_oh_8); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_9_T_1 = _shamts_oh_9_T & vacants_8; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_9_T_2 = shamts_oh_8[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_9_T_3 = ~_shamts_oh_9_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_9_T_4 = _shamts_oh_9_T_3 & vacants_8; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_9_next_T = {shamts_oh_8, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_9_next = _shamts_oh_9_T_1 ? 2'h1 : _shamts_oh_9_T_4 ? _shamts_oh_9_next_T[1:0] : shamts_oh_8[1:0]; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_9 = {1'h0, shamts_oh_9_next}; // @[issue-unit-age-ordered.scala:158:23, :161:21, :176:20] wire [1:0] shamts_oh_10_next; // @[issue-unit-age-ordered.scala:161:21] wire _shamts_oh_10_T = ~(\|shamts_oh_9); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_10_T_1 = _shamts_oh_10_T & vacants_9; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_10_T_2 = shamts_oh_9[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_10_T_3 = ~_shamts_oh_10_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_10_T_4 = _shamts_oh_10_T_3 & vacants_9; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_10_next_T = {shamts_oh_9, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_10_next = _shamts_oh_10_T_1 ? 2'h1 : _shamts_oh_10_T_4 ? _shamts_oh_10_next_T[1:0] : shamts_oh_9[1:0]; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_10 = {1'h0, shamts_oh_10_next}; // @[issue-unit-age-ordered.scala:158:23, :161:21, :176:20] wire [1:0] shamts_oh_11_next; // @[issue-unit-age-ordered.scala:161:21] wire _shamts_oh_11_T = ~(\|shamts_oh_10); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_11_T_1 = _shamts_oh_11_T & vacants_10; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_11_T_2 = shamts_oh_10[1]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_11_T_3 = ~_shamts_oh_11_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_11_T_4 = _shamts_oh_11_T_3 & vacants_10; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_11_next_T = {shamts_oh_10, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_11_next = _shamts_oh_11_T_1 ? 2'h1 : _shamts_oh_11_T_4 ? _shamts_oh_11_next_T[1:0] : shamts_oh_10[1:0]; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_11 = {1'h0, shamts_oh_11_next}; // @[issue-unit-age-ordered.scala:158:23, :161:21, :176:20] assign shamts_oh_12 = shamts_oh_12_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_12_T = ~(\|shamts_oh_11); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_12_T_1 = _shamts_oh_12_T & vacants_11; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_12_T_2 = shamts_oh_11[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_12_T_3 = ~_shamts_oh_12_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_12_T_4 = _shamts_oh_12_T_3 & vacants_11; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_12_next_T = {shamts_oh_11, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_12_next = _shamts_oh_12_T_1 ? 3'h1 : _shamts_oh_12_T_4 ? _shamts_oh_12_next_T[2:0] : shamts_oh_11; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_13 = shamts_oh_13_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_13_T = ~(\|shamts_oh_12); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_13_T_1 = _shamts_oh_13_T & vacants_12; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_13_T_2 = shamts_oh_12[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_13_T_3 = ~_shamts_oh_13_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_13_T_4 = _shamts_oh_13_T_3 & vacants_12; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_13_next_T = {shamts_oh_12, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_13_next = _shamts_oh_13_T_1 ? 3'h1 : _shamts_oh_13_T_4 ? _shamts_oh_13_next_T[2:0] : shamts_oh_12; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_14 = shamts_oh_14_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_14_T = ~(\|shamts_oh_13); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_14_T_1 = _shamts_oh_14_T & vacants_13; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_14_T_2 = shamts_oh_13[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_14_T_3 = ~_shamts_oh_14_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_14_T_4 = _shamts_oh_14_T_3 & vacants_13; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_14_next_T = {shamts_oh_13, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_14_next = _shamts_oh_14_T_1 ? 3'h1 : _shamts_oh_14_T_4 ? _shamts_oh_14_next_T[2:0] : shamts_oh_13; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_15 = shamts_oh_15_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_15_T = ~(\|shamts_oh_14); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_15_T_1 = _shamts_oh_15_T & vacants_14; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_15_T_2 = shamts_oh_14[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_15_T_3 = ~_shamts_oh_15_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_15_T_4 = _shamts_oh_15_T_3 & vacants_14; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_15_next_T = {shamts_oh_14, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_15_next = _shamts_oh_15_T_1 ? 3'h1 : _shamts_oh_15_T_4 ? _shamts_oh_15_next_T[2:0] : shamts_oh_14; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_16 = shamts_oh_16_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_16_T = ~(\|shamts_oh_15); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_16_T_1 = _shamts_oh_16_T & vacants_15; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_16_T_2 = shamts_oh_15[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_16_T_3 = ~_shamts_oh_16_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_16_T_4 = _shamts_oh_16_T_3 & vacants_15; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_16_next_T = {shamts_oh_15, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_16_next = _shamts_oh_16_T_1 ? 3'h1 : _shamts_oh_16_T_4 ? _shamts_oh_16_next_T[2:0] : shamts_oh_15; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_17 = shamts_oh_17_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_17_T = ~(\|shamts_oh_16); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_17_T_1 = _shamts_oh_17_T & vacants_16; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_17_T_2 = shamts_oh_16[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_17_T_3 = ~_shamts_oh_17_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_17_T_4 = _shamts_oh_17_T_3 & vacants_16; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_17_next_T = {shamts_oh_16, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_17_next = _shamts_oh_17_T_1 ? 3'h1 : _shamts_oh_17_T_4 ? _shamts_oh_17_next_T[2:0] : shamts_oh_16; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_18 = shamts_oh_18_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_18_T = ~(\|shamts_oh_17); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_18_T_1 = _shamts_oh_18_T & vacants_17; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_18_T_2 = shamts_oh_17[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_18_T_3 = ~_shamts_oh_18_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_18_T_4 = _shamts_oh_18_T_3 & vacants_17; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_18_next_T = {shamts_oh_17, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_18_next = _shamts_oh_18_T_1 ? 3'h1 : _shamts_oh_18_T_4 ? _shamts_oh_18_next_T[2:0] : shamts_oh_17; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_19 = shamts_oh_19_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_19_T = ~(\|shamts_oh_18); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_19_T_1 = _shamts_oh_19_T & vacants_18; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_19_T_2 = shamts_oh_18[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_19_T_3 = ~_shamts_oh_19_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_19_T_4 = _shamts_oh_19_T_3 & vacants_18; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_19_next_T = {shamts_oh_18, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_19_next = _shamts_oh_19_T_1 ? 3'h1 : _shamts_oh_19_T_4 ? _shamts_oh_19_next_T[2:0] : shamts_oh_18; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_20 = shamts_oh_20_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_20_T = ~(\|shamts_oh_19); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_20_T_1 = _shamts_oh_20_T & vacants_19; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_20_T_2 = shamts_oh_19[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_20_T_3 = ~_shamts_oh_20_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_20_T_4 = _shamts_oh_20_T_3 & vacants_19; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_20_next_T = {shamts_oh_19, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_20_next = _shamts_oh_20_T_1 ? 3'h1 : _shamts_oh_20_T_4 ? _shamts_oh_20_next_T[2:0] : shamts_oh_19; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_21 = shamts_oh_21_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_21_T = ~(\|shamts_oh_20); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_21_T_1 = _shamts_oh_21_T & vacants_20; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_21_T_2 = shamts_oh_20[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_21_T_3 = ~_shamts_oh_21_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_21_T_4 = _shamts_oh_21_T_3 & vacants_20; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_21_next_T = {shamts_oh_20, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_21_next = _shamts_oh_21_T_1 ? 3'h1 : _shamts_oh_21_T_4 ? _shamts_oh_21_next_T[2:0] : shamts_oh_20; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_22 = shamts_oh_22_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_22_T = ~(\|shamts_oh_21); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_22_T_1 = _shamts_oh_22_T & vacants_21; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_22_T_2 = shamts_oh_21[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_22_T_3 = ~_shamts_oh_22_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_22_T_4 = _shamts_oh_22_T_3 & vacants_21; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_22_next_T = {shamts_oh_21, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_22_next = _shamts_oh_22_T_1 ? 3'h1 : _shamts_oh_22_T_4 ? _shamts_oh_22_next_T[2:0] : shamts_oh_21; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_23 = shamts_oh_23_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_23_T = ~(\|shamts_oh_22); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_23_T_1 = _shamts_oh_23_T & vacants_22; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_23_T_2 = shamts_oh_22[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_23_T_3 = ~_shamts_oh_23_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_23_T_4 = _shamts_oh_23_T_3 & vacants_22; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_23_next_T = {shamts_oh_22, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_23_next = _shamts_oh_23_T_1 ? 3'h1 : _shamts_oh_23_T_4 ? _shamts_oh_23_next_T[2:0] : shamts_oh_22; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_24 = shamts_oh_24_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_24_T = ~(\|shamts_oh_23); // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_24_T_1 = _shamts_oh_24_T & vacants_23; // @[issue-unit-age-ordered.scala:157:38, :163:{21,29}] wire _shamts_oh_24_T_2 = shamts_oh_23[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_24_T_3 = ~_shamts_oh_24_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_24_T_4 = _shamts_oh_24_T_3 & vacants_23; // @[issue-unit-age-ordered.scala:157:38, :165:{19,36}] wire [3:0] _shamts_oh_24_next_T = {shamts_oh_23, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_24_next = _shamts_oh_24_T_1 ? 3'h1 : _shamts_oh_24_T_4 ? _shamts_oh_24_next_T[2:0] : shamts_oh_23; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_25 = shamts_oh_25_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_25_T = shamts_oh_24 == 3'h0; // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_25_T_1 = _shamts_oh_25_T & vacants_24; // @[issue-unit-age-ordered.scala:157:82, :163:{21,29}] wire _shamts_oh_25_T_2 = shamts_oh_24[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_25_T_3 = ~_shamts_oh_25_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_25_T_4 = _shamts_oh_25_T_3 & vacants_24; // @[issue-unit-age-ordered.scala:157:82, :165:{19,36}] wire [3:0] _shamts_oh_25_next_T = {shamts_oh_24, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_25_next = _shamts_oh_25_T_1 ? 3'h1 : _shamts_oh_25_T_4 ? _shamts_oh_25_next_T[2:0] : shamts_oh_24; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] assign shamts_oh_26 = shamts_oh_26_next; // @[issue-unit-age-ordered.scala:158:23, :161:21] wire _shamts_oh_26_T = shamts_oh_25 == 3'h0; // @[issue-unit-age-ordered.scala:158:23, :163:21] wire _shamts_oh_26_T_1 = _shamts_oh_26_T & vacants_25; // @[issue-unit-age-ordered.scala:157:82, :163:{21,29}] wire _shamts_oh_26_T_2 = shamts_oh_25[2]; // @[issue-unit-age-ordered.scala:158:23, :165:28] wire _shamts_oh_26_T_3 = ~_shamts_oh_26_T_2; // @[issue-unit-age-ordered.scala:165:{19,28}] wire _shamts_oh_26_T_4 = _shamts_oh_26_T_3 & vacants_25; // @[issue-unit-age-ordered.scala:157:82, :165:{19,36}] wire [3:0] _shamts_oh_26_next_T = {shamts_oh_25, 1'h0}; // @[issue-unit-age-ordered.scala:158:23, :166:26] assign shamts_oh_26_next = _shamts_oh_26_T_1 ? 3'h1 : _shamts_oh_26_T_4 ? _shamts_oh_26_next_T[2:0] : shamts_oh_25; // @[issue-unit-age-ordered.scala:158:23, :161:21, :162:11, :163:{29,37}, :164:13, :165:{36,44}, :166:{13,26}] wire _will_be_valid_T = ~io_dis_uops_0_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7, :185:57] wire _will_be_valid_T_1 = io_dis_uops_0_valid_0 & _will_be_valid_T; // @[issue-unit-age-ordered.scala:22:7, :184:77, :185:57] wire _will_be_valid_T_2 = ~io_dis_uops_0_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :186:57] wire _will_be_valid_T_3 = _will_be_valid_T_1 & _will_be_valid_T_2; // @[issue-unit-age-ordered.scala:184:77, :185:80, :186:57] wire _will_be_valid_T_4 = ~io_dis_uops_0_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :187:57] wire will_be_valid_24 = _will_be_valid_T_3 & _will_be_valid_T_4; // @[issue-unit-age-ordered.scala:185:80, :186:79, :187:57] wire _will_be_valid_T_5 = ~io_dis_uops_1_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7, :185:57] wire _will_be_valid_T_6 = io_dis_uops_1_valid_0 & _will_be_valid_T_5; // @[issue-unit-age-ordered.scala:22:7, :184:77, :185:57] wire _will_be_valid_T_7 = ~io_dis_uops_1_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :186:57] wire _will_be_valid_T_8 = _will_be_valid_T_6 & _will_be_valid_T_7; // @[issue-unit-age-ordered.scala:184:77, :185:80, :186:57] wire _will_be_valid_T_9 = ~io_dis_uops_1_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :187:57] wire will_be_valid_25 = _will_be_valid_T_8 & _will_be_valid_T_9; // @[issue-unit-age-ordered.scala:185:80, :186:79, :187:57] wire _will_be_valid_T_10 = ~io_dis_uops_2_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7, :185:57] wire _will_be_valid_T_11 = io_dis_uops_2_valid_0 & _will_be_valid_T_10; // @[issue-unit-age-ordered.scala:22:7, :184:77, :185:57] wire _will_be_valid_T_12 = ~io_dis_uops_2_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :186:57] wire _will_be_valid_T_13 = _will_be_valid_T_11 & _will_be_valid_T_12; // @[issue-unit-age-ordered.scala:184:77, :185:80, :186:57] wire _will_be_valid_T_14 = ~io_dis_uops_2_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :187:57] wire will_be_valid_26 = _will_be_valid_T_13 & _will_be_valid_T_14; // @[issue-unit-age-ordered.scala:185:80, :186:79, :187:57] wire _T_156 = shamts_oh_2 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_157 = shamts_oh_3 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_0_in_uop_valid = _T_157 ? issue_slots_3_will_be_valid : _T_156 ? issue_slots_2_will_be_valid : shamts_oh_1 == 3'h1 & issue_slots_1_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_0_in_uop_bits_debug_tsrc = _T_157 ? issue_slots_3_out_uop_debug_tsrc : _T_156 ? issue_slots_2_out_uop_debug_tsrc : issue_slots_1_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_debug_fsrc = _T_157 ? issue_slots_3_out_uop_debug_fsrc : _T_156 ? issue_slots_2_out_uop_debug_fsrc : issue_slots_1_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_bp_xcpt_if = _T_157 ? issue_slots_3_out_uop_bp_xcpt_if : _T_156 ? issue_slots_2_out_uop_bp_xcpt_if : issue_slots_1_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_bp_debug_if = _T_157 ? issue_slots_3_out_uop_bp_debug_if : _T_156 ? issue_slots_2_out_uop_bp_debug_if : issue_slots_1_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_xcpt_ma_if = _T_157 ? issue_slots_3_out_uop_xcpt_ma_if : _T_156 ? issue_slots_2_out_uop_xcpt_ma_if : issue_slots_1_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_xcpt_ae_if = _T_157 ? issue_slots_3_out_uop_xcpt_ae_if : _T_156 ? issue_slots_2_out_uop_xcpt_ae_if : issue_slots_1_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_xcpt_pf_if = _T_157 ? issue_slots_3_out_uop_xcpt_pf_if : _T_156 ? issue_slots_2_out_uop_xcpt_pf_if : issue_slots_1_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_typ = _T_157 ? issue_slots_3_out_uop_fp_typ : _T_156 ? issue_slots_2_out_uop_fp_typ : issue_slots_1_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_rm = _T_157 ? issue_slots_3_out_uop_fp_rm : _T_156 ? issue_slots_2_out_uop_fp_rm : issue_slots_1_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_val = _T_157 ? issue_slots_3_out_uop_fp_val : _T_156 ? issue_slots_2_out_uop_fp_val : issue_slots_1_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fcn_op = _T_157 ? issue_slots_3_out_uop_fcn_op : _T_156 ? issue_slots_2_out_uop_fcn_op : issue_slots_1_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fcn_dw = _T_157 ? issue_slots_3_out_uop_fcn_dw : _T_156 ? issue_slots_2_out_uop_fcn_dw : issue_slots_1_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_frs3_en = _T_157 ? issue_slots_3_out_uop_frs3_en : _T_156 ? issue_slots_2_out_uop_frs3_en : issue_slots_1_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs2_rtype = _T_157 ? issue_slots_3_out_uop_lrs2_rtype : _T_156 ? issue_slots_2_out_uop_lrs2_rtype : issue_slots_1_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs1_rtype = _T_157 ? issue_slots_3_out_uop_lrs1_rtype : _T_156 ? issue_slots_2_out_uop_lrs1_rtype : issue_slots_1_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_dst_rtype = _T_157 ? issue_slots_3_out_uop_dst_rtype : _T_156 ? issue_slots_2_out_uop_dst_rtype : issue_slots_1_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs3 = _T_157 ? issue_slots_3_out_uop_lrs3 : _T_156 ? issue_slots_2_out_uop_lrs3 : issue_slots_1_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs2 = _T_157 ? issue_slots_3_out_uop_lrs2 : _T_156 ? issue_slots_2_out_uop_lrs2 : issue_slots_1_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_lrs1 = _T_157 ? issue_slots_3_out_uop_lrs1 : _T_156 ? issue_slots_2_out_uop_lrs1 : issue_slots_1_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ldst = _T_157 ? issue_slots_3_out_uop_ldst : _T_156 ? issue_slots_2_out_uop_ldst : issue_slots_1_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ldst_is_rs1 = _T_157 ? issue_slots_3_out_uop_ldst_is_rs1 : _T_156 ? issue_slots_2_out_uop_ldst_is_rs1 : issue_slots_1_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_csr_cmd = _T_157 ? issue_slots_3_out_uop_csr_cmd : _T_156 ? issue_slots_2_out_uop_csr_cmd : issue_slots_1_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_flush_on_commit = _T_157 ? issue_slots_3_out_uop_flush_on_commit : _T_156 ? issue_slots_2_out_uop_flush_on_commit : issue_slots_1_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_unique = _T_157 ? issue_slots_3_out_uop_is_unique : _T_156 ? issue_slots_2_out_uop_is_unique : issue_slots_1_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_uses_stq = _T_157 ? issue_slots_3_out_uop_uses_stq : _T_156 ? issue_slots_2_out_uop_uses_stq : issue_slots_1_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_uses_ldq = _T_157 ? issue_slots_3_out_uop_uses_ldq : _T_156 ? issue_slots_2_out_uop_uses_ldq : issue_slots_1_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_mem_signed = _T_157 ? issue_slots_3_out_uop_mem_signed : _T_156 ? issue_slots_2_out_uop_mem_signed : issue_slots_1_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_mem_size = _T_157 ? issue_slots_3_out_uop_mem_size : _T_156 ? issue_slots_2_out_uop_mem_size : issue_slots_1_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_mem_cmd = _T_157 ? issue_slots_3_out_uop_mem_cmd : _T_156 ? issue_slots_2_out_uop_mem_cmd : issue_slots_1_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_exc_cause = _T_157 ? issue_slots_3_out_uop_exc_cause : _T_156 ? issue_slots_2_out_uop_exc_cause : issue_slots_1_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_exception = _T_157 ? issue_slots_3_out_uop_exception : _T_156 ? issue_slots_2_out_uop_exception : issue_slots_1_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_stale_pdst = _T_157 ? issue_slots_3_out_uop_stale_pdst : _T_156 ? issue_slots_2_out_uop_stale_pdst : issue_slots_1_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ppred_busy = _T_157 ? issue_slots_3_out_uop_ppred_busy : _T_156 ? issue_slots_2_out_uop_ppred_busy : issue_slots_1_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs3_busy = _T_157 ? issue_slots_3_out_uop_prs3_busy : _T_156 ? issue_slots_2_out_uop_prs3_busy : issue_slots_1_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs2_busy = _T_157 ? issue_slots_3_out_uop_prs2_busy : _T_156 ? issue_slots_2_out_uop_prs2_busy : issue_slots_1_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs1_busy = _T_157 ? issue_slots_3_out_uop_prs1_busy : _T_156 ? issue_slots_2_out_uop_prs1_busy : issue_slots_1_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ppred = _T_157 ? issue_slots_3_out_uop_ppred : _T_156 ? issue_slots_2_out_uop_ppred : issue_slots_1_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs3 = _T_157 ? issue_slots_3_out_uop_prs3 : _T_156 ? issue_slots_2_out_uop_prs3 : issue_slots_1_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs2 = _T_157 ? issue_slots_3_out_uop_prs2 : _T_156 ? issue_slots_2_out_uop_prs2 : issue_slots_1_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_prs1 = _T_157 ? issue_slots_3_out_uop_prs1 : _T_156 ? issue_slots_2_out_uop_prs1 : issue_slots_1_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_pdst = _T_157 ? issue_slots_3_out_uop_pdst : _T_156 ? issue_slots_2_out_uop_pdst : issue_slots_1_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_rxq_idx = _T_157 ? issue_slots_3_out_uop_rxq_idx : _T_156 ? issue_slots_2_out_uop_rxq_idx : issue_slots_1_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_stq_idx = _T_157 ? issue_slots_3_out_uop_stq_idx : _T_156 ? issue_slots_2_out_uop_stq_idx : issue_slots_1_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ldq_idx = _T_157 ? issue_slots_3_out_uop_ldq_idx : _T_156 ? issue_slots_2_out_uop_ldq_idx : issue_slots_1_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_rob_idx = _T_157 ? issue_slots_3_out_uop_rob_idx : _T_156 ? issue_slots_2_out_uop_rob_idx : issue_slots_1_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_vec = _T_157 ? issue_slots_3_out_uop_fp_ctrl_vec : _T_156 ? issue_slots_2_out_uop_fp_ctrl_vec : issue_slots_1_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_wflags = _T_157 ? issue_slots_3_out_uop_fp_ctrl_wflags : _T_156 ? issue_slots_2_out_uop_fp_ctrl_wflags : issue_slots_1_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_sqrt = _T_157 ? issue_slots_3_out_uop_fp_ctrl_sqrt : _T_156 ? issue_slots_2_out_uop_fp_ctrl_sqrt : issue_slots_1_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_div = _T_157 ? issue_slots_3_out_uop_fp_ctrl_div : _T_156 ? issue_slots_2_out_uop_fp_ctrl_div : issue_slots_1_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_fma = _T_157 ? issue_slots_3_out_uop_fp_ctrl_fma : _T_156 ? issue_slots_2_out_uop_fp_ctrl_fma : issue_slots_1_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_fastpipe = _T_157 ? issue_slots_3_out_uop_fp_ctrl_fastpipe : _T_156 ? issue_slots_2_out_uop_fp_ctrl_fastpipe : issue_slots_1_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_toint = _T_157 ? issue_slots_3_out_uop_fp_ctrl_toint : _T_156 ? issue_slots_2_out_uop_fp_ctrl_toint : issue_slots_1_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_fromint = _T_157 ? issue_slots_3_out_uop_fp_ctrl_fromint : _T_156 ? issue_slots_2_out_uop_fp_ctrl_fromint : issue_slots_1_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_typeTagOut = _T_157 ? issue_slots_3_out_uop_fp_ctrl_typeTagOut : _T_156 ? issue_slots_2_out_uop_fp_ctrl_typeTagOut : issue_slots_1_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_typeTagIn = _T_157 ? issue_slots_3_out_uop_fp_ctrl_typeTagIn : _T_156 ? issue_slots_2_out_uop_fp_ctrl_typeTagIn : issue_slots_1_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_swap23 = _T_157 ? issue_slots_3_out_uop_fp_ctrl_swap23 : _T_156 ? issue_slots_2_out_uop_fp_ctrl_swap23 : issue_slots_1_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_swap12 = _T_157 ? issue_slots_3_out_uop_fp_ctrl_swap12 : _T_156 ? issue_slots_2_out_uop_fp_ctrl_swap12 : issue_slots_1_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_ren3 = _T_157 ? issue_slots_3_out_uop_fp_ctrl_ren3 : _T_156 ? issue_slots_2_out_uop_fp_ctrl_ren3 : issue_slots_1_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_ren2 = _T_157 ? issue_slots_3_out_uop_fp_ctrl_ren2 : _T_156 ? issue_slots_2_out_uop_fp_ctrl_ren2 : issue_slots_1_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_ren1 = _T_157 ? issue_slots_3_out_uop_fp_ctrl_ren1 : _T_156 ? issue_slots_2_out_uop_fp_ctrl_ren1 : issue_slots_1_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_wen = _T_157 ? issue_slots_3_out_uop_fp_ctrl_wen : _T_156 ? issue_slots_2_out_uop_fp_ctrl_wen : issue_slots_1_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fp_ctrl_ldst = _T_157 ? issue_slots_3_out_uop_fp_ctrl_ldst : _T_156 ? issue_slots_2_out_uop_fp_ctrl_ldst : issue_slots_1_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_op2_sel = _T_157 ? issue_slots_3_out_uop_op2_sel : _T_156 ? issue_slots_2_out_uop_op2_sel : issue_slots_1_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_op1_sel = _T_157 ? issue_slots_3_out_uop_op1_sel : _T_156 ? issue_slots_2_out_uop_op1_sel : issue_slots_1_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_imm_packed = _T_157 ? issue_slots_3_out_uop_imm_packed : _T_156 ? issue_slots_2_out_uop_imm_packed : issue_slots_1_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_pimm = _T_157 ? issue_slots_3_out_uop_pimm : _T_156 ? issue_slots_2_out_uop_pimm : issue_slots_1_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_imm_sel = _T_157 ? issue_slots_3_out_uop_imm_sel : _T_156 ? issue_slots_2_out_uop_imm_sel : issue_slots_1_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_imm_rename = _T_157 ? issue_slots_3_out_uop_imm_rename : _T_156 ? issue_slots_2_out_uop_imm_rename : issue_slots_1_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_taken = _T_157 ? issue_slots_3_out_uop_taken : _T_156 ? issue_slots_2_out_uop_taken : issue_slots_1_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_pc_lob = _T_157 ? issue_slots_3_out_uop_pc_lob : _T_156 ? issue_slots_2_out_uop_pc_lob : issue_slots_1_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_edge_inst = _T_157 ? issue_slots_3_out_uop_edge_inst : _T_156 ? issue_slots_2_out_uop_edge_inst : issue_slots_1_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_ftq_idx = _T_157 ? issue_slots_3_out_uop_ftq_idx : _T_156 ? issue_slots_2_out_uop_ftq_idx : issue_slots_1_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_mov = _T_157 ? issue_slots_3_out_uop_is_mov : _T_156 ? issue_slots_2_out_uop_is_mov : issue_slots_1_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_rocc = _T_157 ? issue_slots_3_out_uop_is_rocc : _T_156 ? issue_slots_2_out_uop_is_rocc : issue_slots_1_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_sys_pc2epc = _T_157 ? issue_slots_3_out_uop_is_sys_pc2epc : _T_156 ? issue_slots_2_out_uop_is_sys_pc2epc : issue_slots_1_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_eret = _T_157 ? issue_slots_3_out_uop_is_eret : _T_156 ? issue_slots_2_out_uop_is_eret : issue_slots_1_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_amo = _T_157 ? issue_slots_3_out_uop_is_amo : _T_156 ? issue_slots_2_out_uop_is_amo : issue_slots_1_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_sfence = _T_157 ? issue_slots_3_out_uop_is_sfence : _T_156 ? issue_slots_2_out_uop_is_sfence : issue_slots_1_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_fencei = _T_157 ? issue_slots_3_out_uop_is_fencei : _T_156 ? issue_slots_2_out_uop_is_fencei : issue_slots_1_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_fence = _T_157 ? issue_slots_3_out_uop_is_fence : _T_156 ? issue_slots_2_out_uop_is_fence : issue_slots_1_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_sfb = _T_157 ? issue_slots_3_out_uop_is_sfb : _T_156 ? issue_slots_2_out_uop_is_sfb : issue_slots_1_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_br_type = _T_157 ? issue_slots_3_out_uop_br_type : _T_156 ? issue_slots_2_out_uop_br_type : issue_slots_1_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_br_tag = _T_157 ? issue_slots_3_out_uop_br_tag : _T_156 ? issue_slots_2_out_uop_br_tag : issue_slots_1_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_br_mask = _T_157 ? issue_slots_3_out_uop_br_mask : _T_156 ? issue_slots_2_out_uop_br_mask : issue_slots_1_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_dis_col_sel = _T_157 ? issue_slots_3_out_uop_dis_col_sel : _T_156 ? issue_slots_2_out_uop_dis_col_sel : issue_slots_1_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_p3_bypass_hint = _T_157 ? issue_slots_3_out_uop_iw_p3_bypass_hint : _T_156 ? issue_slots_2_out_uop_iw_p3_bypass_hint : issue_slots_1_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_p2_bypass_hint = _T_157 ? issue_slots_3_out_uop_iw_p2_bypass_hint : _T_156 ? issue_slots_2_out_uop_iw_p2_bypass_hint : issue_slots_1_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_p1_bypass_hint = _T_157 ? issue_slots_3_out_uop_iw_p1_bypass_hint : _T_156 ? issue_slots_2_out_uop_iw_p1_bypass_hint : issue_slots_1_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iw_issued = _T_157 ? issue_slots_3_out_uop_iw_issued : _T_156 ? issue_slots_2_out_uop_iw_issued : issue_slots_1_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_0 = _T_157 ? issue_slots_3_out_uop_fu_code_0 : _T_156 ? issue_slots_2_out_uop_fu_code_0 : issue_slots_1_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_1 = _T_157 ? issue_slots_3_out_uop_fu_code_1 : _T_156 ? issue_slots_2_out_uop_fu_code_1 : issue_slots_1_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_2 = _T_157 ? issue_slots_3_out_uop_fu_code_2 : _T_156 ? issue_slots_2_out_uop_fu_code_2 : issue_slots_1_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_3 = _T_157 ? issue_slots_3_out_uop_fu_code_3 : _T_156 ? issue_slots_2_out_uop_fu_code_3 : issue_slots_1_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_4 = _T_157 ? issue_slots_3_out_uop_fu_code_4 : _T_156 ? issue_slots_2_out_uop_fu_code_4 : issue_slots_1_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_5 = _T_157 ? issue_slots_3_out_uop_fu_code_5 : _T_156 ? issue_slots_2_out_uop_fu_code_5 : issue_slots_1_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_6 = _T_157 ? issue_slots_3_out_uop_fu_code_6 : _T_156 ? issue_slots_2_out_uop_fu_code_6 : issue_slots_1_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_7 = _T_157 ? issue_slots_3_out_uop_fu_code_7 : _T_156 ? issue_slots_2_out_uop_fu_code_7 : issue_slots_1_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_8 = _T_157 ? issue_slots_3_out_uop_fu_code_8 : _T_156 ? issue_slots_2_out_uop_fu_code_8 : issue_slots_1_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_fu_code_9 = _T_157 ? issue_slots_3_out_uop_fu_code_9 : _T_156 ? issue_slots_2_out_uop_fu_code_9 : issue_slots_1_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iq_type_0 = _T_157 ? issue_slots_3_out_uop_iq_type_0 : _T_156 ? issue_slots_2_out_uop_iq_type_0 : issue_slots_1_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iq_type_1 = _T_157 ? issue_slots_3_out_uop_iq_type_1 : _T_156 ? issue_slots_2_out_uop_iq_type_1 : issue_slots_1_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iq_type_2 = _T_157 ? issue_slots_3_out_uop_iq_type_2 : _T_156 ? issue_slots_2_out_uop_iq_type_2 : issue_slots_1_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_iq_type_3 = _T_157 ? issue_slots_3_out_uop_iq_type_3 : _T_156 ? issue_slots_2_out_uop_iq_type_3 : issue_slots_1_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_debug_pc = _T_157 ? issue_slots_3_out_uop_debug_pc : _T_156 ? issue_slots_2_out_uop_debug_pc : issue_slots_1_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_is_rvc = _T_157 ? issue_slots_3_out_uop_is_rvc : _T_156 ? issue_slots_2_out_uop_is_rvc : issue_slots_1_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_debug_inst = _T_157 ? issue_slots_3_out_uop_debug_inst : _T_156 ? issue_slots_2_out_uop_debug_inst : issue_slots_1_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_0_in_uop_bits_inst = _T_157 ? issue_slots_3_out_uop_inst : _T_156 ? issue_slots_2_out_uop_inst : issue_slots_1_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] wire _T_159 = shamts_oh_3 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_160 = shamts_oh_4 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_1_in_uop_valid = _T_160 ? issue_slots_4_will_be_valid : _T_159 ? issue_slots_3_will_be_valid : shamts_oh_2 == 3'h1 & issue_slots_2_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_1_in_uop_bits_debug_tsrc = _T_160 ? issue_slots_4_out_uop_debug_tsrc : _T_159 ? issue_slots_3_out_uop_debug_tsrc : issue_slots_2_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_debug_fsrc = _T_160 ? issue_slots_4_out_uop_debug_fsrc : _T_159 ? issue_slots_3_out_uop_debug_fsrc : issue_slots_2_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_bp_xcpt_if = _T_160 ? issue_slots_4_out_uop_bp_xcpt_if : _T_159 ? issue_slots_3_out_uop_bp_xcpt_if : issue_slots_2_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_bp_debug_if = _T_160 ? issue_slots_4_out_uop_bp_debug_if : _T_159 ? issue_slots_3_out_uop_bp_debug_if : issue_slots_2_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_xcpt_ma_if = _T_160 ? issue_slots_4_out_uop_xcpt_ma_if : _T_159 ? issue_slots_3_out_uop_xcpt_ma_if : issue_slots_2_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_xcpt_ae_if = _T_160 ? issue_slots_4_out_uop_xcpt_ae_if : _T_159 ? issue_slots_3_out_uop_xcpt_ae_if : issue_slots_2_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_xcpt_pf_if = _T_160 ? issue_slots_4_out_uop_xcpt_pf_if : _T_159 ? issue_slots_3_out_uop_xcpt_pf_if : issue_slots_2_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_typ = _T_160 ? issue_slots_4_out_uop_fp_typ : _T_159 ? issue_slots_3_out_uop_fp_typ : issue_slots_2_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_rm = _T_160 ? issue_slots_4_out_uop_fp_rm : _T_159 ? issue_slots_3_out_uop_fp_rm : issue_slots_2_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_val = _T_160 ? issue_slots_4_out_uop_fp_val : _T_159 ? issue_slots_3_out_uop_fp_val : issue_slots_2_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fcn_op = _T_160 ? issue_slots_4_out_uop_fcn_op : _T_159 ? issue_slots_3_out_uop_fcn_op : issue_slots_2_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fcn_dw = _T_160 ? issue_slots_4_out_uop_fcn_dw : _T_159 ? issue_slots_3_out_uop_fcn_dw : issue_slots_2_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_frs3_en = _T_160 ? issue_slots_4_out_uop_frs3_en : _T_159 ? issue_slots_3_out_uop_frs3_en : issue_slots_2_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs2_rtype = _T_160 ? issue_slots_4_out_uop_lrs2_rtype : _T_159 ? issue_slots_3_out_uop_lrs2_rtype : issue_slots_2_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs1_rtype = _T_160 ? issue_slots_4_out_uop_lrs1_rtype : _T_159 ? issue_slots_3_out_uop_lrs1_rtype : issue_slots_2_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_dst_rtype = _T_160 ? issue_slots_4_out_uop_dst_rtype : _T_159 ? issue_slots_3_out_uop_dst_rtype : issue_slots_2_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs3 = _T_160 ? issue_slots_4_out_uop_lrs3 : _T_159 ? issue_slots_3_out_uop_lrs3 : issue_slots_2_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs2 = _T_160 ? issue_slots_4_out_uop_lrs2 : _T_159 ? issue_slots_3_out_uop_lrs2 : issue_slots_2_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_lrs1 = _T_160 ? issue_slots_4_out_uop_lrs1 : _T_159 ? issue_slots_3_out_uop_lrs1 : issue_slots_2_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ldst = _T_160 ? issue_slots_4_out_uop_ldst : _T_159 ? issue_slots_3_out_uop_ldst : issue_slots_2_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ldst_is_rs1 = _T_160 ? issue_slots_4_out_uop_ldst_is_rs1 : _T_159 ? issue_slots_3_out_uop_ldst_is_rs1 : issue_slots_2_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_csr_cmd = _T_160 ? issue_slots_4_out_uop_csr_cmd : _T_159 ? issue_slots_3_out_uop_csr_cmd : issue_slots_2_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_flush_on_commit = _T_160 ? issue_slots_4_out_uop_flush_on_commit : _T_159 ? issue_slots_3_out_uop_flush_on_commit : issue_slots_2_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_unique = _T_160 ? issue_slots_4_out_uop_is_unique : _T_159 ? issue_slots_3_out_uop_is_unique : issue_slots_2_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_uses_stq = _T_160 ? issue_slots_4_out_uop_uses_stq : _T_159 ? issue_slots_3_out_uop_uses_stq : issue_slots_2_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_uses_ldq = _T_160 ? issue_slots_4_out_uop_uses_ldq : _T_159 ? issue_slots_3_out_uop_uses_ldq : issue_slots_2_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_mem_signed = _T_160 ? issue_slots_4_out_uop_mem_signed : _T_159 ? issue_slots_3_out_uop_mem_signed : issue_slots_2_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_mem_size = _T_160 ? issue_slots_4_out_uop_mem_size : _T_159 ? issue_slots_3_out_uop_mem_size : issue_slots_2_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_mem_cmd = _T_160 ? issue_slots_4_out_uop_mem_cmd : _T_159 ? issue_slots_3_out_uop_mem_cmd : issue_slots_2_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_exc_cause = _T_160 ? issue_slots_4_out_uop_exc_cause : _T_159 ? issue_slots_3_out_uop_exc_cause : issue_slots_2_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_exception = _T_160 ? issue_slots_4_out_uop_exception : _T_159 ? issue_slots_3_out_uop_exception : issue_slots_2_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_stale_pdst = _T_160 ? issue_slots_4_out_uop_stale_pdst : _T_159 ? issue_slots_3_out_uop_stale_pdst : issue_slots_2_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ppred_busy = _T_160 ? issue_slots_4_out_uop_ppred_busy : _T_159 ? issue_slots_3_out_uop_ppred_busy : issue_slots_2_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs3_busy = _T_160 ? issue_slots_4_out_uop_prs3_busy : _T_159 ? issue_slots_3_out_uop_prs3_busy : issue_slots_2_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs2_busy = _T_160 ? issue_slots_4_out_uop_prs2_busy : _T_159 ? issue_slots_3_out_uop_prs2_busy : issue_slots_2_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs1_busy = _T_160 ? issue_slots_4_out_uop_prs1_busy : _T_159 ? issue_slots_3_out_uop_prs1_busy : issue_slots_2_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ppred = _T_160 ? issue_slots_4_out_uop_ppred : _T_159 ? issue_slots_3_out_uop_ppred : issue_slots_2_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs3 = _T_160 ? issue_slots_4_out_uop_prs3 : _T_159 ? issue_slots_3_out_uop_prs3 : issue_slots_2_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs2 = _T_160 ? issue_slots_4_out_uop_prs2 : _T_159 ? issue_slots_3_out_uop_prs2 : issue_slots_2_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_prs1 = _T_160 ? issue_slots_4_out_uop_prs1 : _T_159 ? issue_slots_3_out_uop_prs1 : issue_slots_2_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_pdst = _T_160 ? issue_slots_4_out_uop_pdst : _T_159 ? issue_slots_3_out_uop_pdst : issue_slots_2_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_rxq_idx = _T_160 ? issue_slots_4_out_uop_rxq_idx : _T_159 ? issue_slots_3_out_uop_rxq_idx : issue_slots_2_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_stq_idx = _T_160 ? issue_slots_4_out_uop_stq_idx : _T_159 ? issue_slots_3_out_uop_stq_idx : issue_slots_2_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ldq_idx = _T_160 ? issue_slots_4_out_uop_ldq_idx : _T_159 ? issue_slots_3_out_uop_ldq_idx : issue_slots_2_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_rob_idx = _T_160 ? issue_slots_4_out_uop_rob_idx : _T_159 ? issue_slots_3_out_uop_rob_idx : issue_slots_2_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_vec = _T_160 ? issue_slots_4_out_uop_fp_ctrl_vec : _T_159 ? issue_slots_3_out_uop_fp_ctrl_vec : issue_slots_2_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_wflags = _T_160 ? issue_slots_4_out_uop_fp_ctrl_wflags : _T_159 ? issue_slots_3_out_uop_fp_ctrl_wflags : issue_slots_2_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_sqrt = _T_160 ? issue_slots_4_out_uop_fp_ctrl_sqrt : _T_159 ? issue_slots_3_out_uop_fp_ctrl_sqrt : issue_slots_2_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_div = _T_160 ? issue_slots_4_out_uop_fp_ctrl_div : _T_159 ? issue_slots_3_out_uop_fp_ctrl_div : issue_slots_2_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_fma = _T_160 ? issue_slots_4_out_uop_fp_ctrl_fma : _T_159 ? issue_slots_3_out_uop_fp_ctrl_fma : issue_slots_2_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_fastpipe = _T_160 ? issue_slots_4_out_uop_fp_ctrl_fastpipe : _T_159 ? issue_slots_3_out_uop_fp_ctrl_fastpipe : issue_slots_2_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_toint = _T_160 ? issue_slots_4_out_uop_fp_ctrl_toint : _T_159 ? issue_slots_3_out_uop_fp_ctrl_toint : issue_slots_2_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_fromint = _T_160 ? issue_slots_4_out_uop_fp_ctrl_fromint : _T_159 ? issue_slots_3_out_uop_fp_ctrl_fromint : issue_slots_2_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_typeTagOut = _T_160 ? issue_slots_4_out_uop_fp_ctrl_typeTagOut : _T_159 ? issue_slots_3_out_uop_fp_ctrl_typeTagOut : issue_slots_2_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_typeTagIn = _T_160 ? issue_slots_4_out_uop_fp_ctrl_typeTagIn : _T_159 ? issue_slots_3_out_uop_fp_ctrl_typeTagIn : issue_slots_2_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_swap23 = _T_160 ? issue_slots_4_out_uop_fp_ctrl_swap23 : _T_159 ? issue_slots_3_out_uop_fp_ctrl_swap23 : issue_slots_2_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_swap12 = _T_160 ? issue_slots_4_out_uop_fp_ctrl_swap12 : _T_159 ? issue_slots_3_out_uop_fp_ctrl_swap12 : issue_slots_2_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_ren3 = _T_160 ? issue_slots_4_out_uop_fp_ctrl_ren3 : _T_159 ? issue_slots_3_out_uop_fp_ctrl_ren3 : issue_slots_2_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_ren2 = _T_160 ? issue_slots_4_out_uop_fp_ctrl_ren2 : _T_159 ? issue_slots_3_out_uop_fp_ctrl_ren2 : issue_slots_2_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_ren1 = _T_160 ? issue_slots_4_out_uop_fp_ctrl_ren1 : _T_159 ? issue_slots_3_out_uop_fp_ctrl_ren1 : issue_slots_2_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_wen = _T_160 ? issue_slots_4_out_uop_fp_ctrl_wen : _T_159 ? issue_slots_3_out_uop_fp_ctrl_wen : issue_slots_2_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fp_ctrl_ldst = _T_160 ? issue_slots_4_out_uop_fp_ctrl_ldst : _T_159 ? issue_slots_3_out_uop_fp_ctrl_ldst : issue_slots_2_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_op2_sel = _T_160 ? issue_slots_4_out_uop_op2_sel : _T_159 ? issue_slots_3_out_uop_op2_sel : issue_slots_2_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_op1_sel = _T_160 ? issue_slots_4_out_uop_op1_sel : _T_159 ? issue_slots_3_out_uop_op1_sel : issue_slots_2_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_imm_packed = _T_160 ? issue_slots_4_out_uop_imm_packed : _T_159 ? issue_slots_3_out_uop_imm_packed : issue_slots_2_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_pimm = _T_160 ? issue_slots_4_out_uop_pimm : _T_159 ? issue_slots_3_out_uop_pimm : issue_slots_2_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_imm_sel = _T_160 ? issue_slots_4_out_uop_imm_sel : _T_159 ? issue_slots_3_out_uop_imm_sel : issue_slots_2_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_imm_rename = _T_160 ? issue_slots_4_out_uop_imm_rename : _T_159 ? issue_slots_3_out_uop_imm_rename : issue_slots_2_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_taken = _T_160 ? issue_slots_4_out_uop_taken : _T_159 ? issue_slots_3_out_uop_taken : issue_slots_2_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_pc_lob = _T_160 ? issue_slots_4_out_uop_pc_lob : _T_159 ? issue_slots_3_out_uop_pc_lob : issue_slots_2_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_edge_inst = _T_160 ? issue_slots_4_out_uop_edge_inst : _T_159 ? issue_slots_3_out_uop_edge_inst : issue_slots_2_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_ftq_idx = _T_160 ? issue_slots_4_out_uop_ftq_idx : _T_159 ? issue_slots_3_out_uop_ftq_idx : issue_slots_2_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_mov = _T_160 ? issue_slots_4_out_uop_is_mov : _T_159 ? issue_slots_3_out_uop_is_mov : issue_slots_2_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_rocc = _T_160 ? issue_slots_4_out_uop_is_rocc : _T_159 ? issue_slots_3_out_uop_is_rocc : issue_slots_2_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_sys_pc2epc = _T_160 ? issue_slots_4_out_uop_is_sys_pc2epc : _T_159 ? issue_slots_3_out_uop_is_sys_pc2epc : issue_slots_2_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_eret = _T_160 ? issue_slots_4_out_uop_is_eret : _T_159 ? issue_slots_3_out_uop_is_eret : issue_slots_2_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_amo = _T_160 ? issue_slots_4_out_uop_is_amo : _T_159 ? issue_slots_3_out_uop_is_amo : issue_slots_2_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_sfence = _T_160 ? issue_slots_4_out_uop_is_sfence : _T_159 ? issue_slots_3_out_uop_is_sfence : issue_slots_2_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_fencei = _T_160 ? issue_slots_4_out_uop_is_fencei : _T_159 ? issue_slots_3_out_uop_is_fencei : issue_slots_2_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_fence = _T_160 ? issue_slots_4_out_uop_is_fence : _T_159 ? issue_slots_3_out_uop_is_fence : issue_slots_2_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_sfb = _T_160 ? issue_slots_4_out_uop_is_sfb : _T_159 ? issue_slots_3_out_uop_is_sfb : issue_slots_2_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_br_type = _T_160 ? issue_slots_4_out_uop_br_type : _T_159 ? issue_slots_3_out_uop_br_type : issue_slots_2_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_br_tag = _T_160 ? issue_slots_4_out_uop_br_tag : _T_159 ? issue_slots_3_out_uop_br_tag : issue_slots_2_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_br_mask = _T_160 ? issue_slots_4_out_uop_br_mask : _T_159 ? issue_slots_3_out_uop_br_mask : issue_slots_2_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_dis_col_sel = _T_160 ? issue_slots_4_out_uop_dis_col_sel : _T_159 ? issue_slots_3_out_uop_dis_col_sel : issue_slots_2_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_p3_bypass_hint = _T_160 ? issue_slots_4_out_uop_iw_p3_bypass_hint : _T_159 ? issue_slots_3_out_uop_iw_p3_bypass_hint : issue_slots_2_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_p2_bypass_hint = _T_160 ? issue_slots_4_out_uop_iw_p2_bypass_hint : _T_159 ? issue_slots_3_out_uop_iw_p2_bypass_hint : issue_slots_2_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_p1_bypass_hint = _T_160 ? issue_slots_4_out_uop_iw_p1_bypass_hint : _T_159 ? issue_slots_3_out_uop_iw_p1_bypass_hint : issue_slots_2_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iw_issued = _T_160 ? issue_slots_4_out_uop_iw_issued : _T_159 ? issue_slots_3_out_uop_iw_issued : issue_slots_2_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_0 = _T_160 ? issue_slots_4_out_uop_fu_code_0 : _T_159 ? issue_slots_3_out_uop_fu_code_0 : issue_slots_2_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_1 = _T_160 ? issue_slots_4_out_uop_fu_code_1 : _T_159 ? issue_slots_3_out_uop_fu_code_1 : issue_slots_2_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_2 = _T_160 ? issue_slots_4_out_uop_fu_code_2 : _T_159 ? issue_slots_3_out_uop_fu_code_2 : issue_slots_2_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_3 = _T_160 ? issue_slots_4_out_uop_fu_code_3 : _T_159 ? issue_slots_3_out_uop_fu_code_3 : issue_slots_2_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_4 = _T_160 ? issue_slots_4_out_uop_fu_code_4 : _T_159 ? issue_slots_3_out_uop_fu_code_4 : issue_slots_2_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_5 = _T_160 ? issue_slots_4_out_uop_fu_code_5 : _T_159 ? issue_slots_3_out_uop_fu_code_5 : issue_slots_2_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_6 = _T_160 ? issue_slots_4_out_uop_fu_code_6 : _T_159 ? issue_slots_3_out_uop_fu_code_6 : issue_slots_2_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_7 = _T_160 ? issue_slots_4_out_uop_fu_code_7 : _T_159 ? issue_slots_3_out_uop_fu_code_7 : issue_slots_2_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_8 = _T_160 ? issue_slots_4_out_uop_fu_code_8 : _T_159 ? issue_slots_3_out_uop_fu_code_8 : issue_slots_2_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_fu_code_9 = _T_160 ? issue_slots_4_out_uop_fu_code_9 : _T_159 ? issue_slots_3_out_uop_fu_code_9 : issue_slots_2_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iq_type_0 = _T_160 ? issue_slots_4_out_uop_iq_type_0 : _T_159 ? issue_slots_3_out_uop_iq_type_0 : issue_slots_2_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iq_type_1 = _T_160 ? issue_slots_4_out_uop_iq_type_1 : _T_159 ? issue_slots_3_out_uop_iq_type_1 : issue_slots_2_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iq_type_2 = _T_160 ? issue_slots_4_out_uop_iq_type_2 : _T_159 ? issue_slots_3_out_uop_iq_type_2 : issue_slots_2_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_iq_type_3 = _T_160 ? issue_slots_4_out_uop_iq_type_3 : _T_159 ? issue_slots_3_out_uop_iq_type_3 : issue_slots_2_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_debug_pc = _T_160 ? issue_slots_4_out_uop_debug_pc : _T_159 ? issue_slots_3_out_uop_debug_pc : issue_slots_2_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_is_rvc = _T_160 ? issue_slots_4_out_uop_is_rvc : _T_159 ? issue_slots_3_out_uop_is_rvc : issue_slots_2_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_debug_inst = _T_160 ? issue_slots_4_out_uop_debug_inst : _T_159 ? issue_slots_3_out_uop_debug_inst : issue_slots_2_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_1_in_uop_bits_inst = _T_160 ? issue_slots_4_out_uop_inst : _T_159 ? issue_slots_3_out_uop_inst : issue_slots_2_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_1_clear_T = \|shamts_oh_1; // @[issue-unit-age-ordered.scala:158:23, :199:49] assign issue_slots_1_clear = _issue_slots_1_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_162 = shamts_oh_4 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_163 = shamts_oh_5 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_2_in_uop_valid = _T_163 ? issue_slots_5_will_be_valid : _T_162 ? issue_slots_4_will_be_valid : shamts_oh_3 == 3'h1 & issue_slots_3_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_2_in_uop_bits_debug_tsrc = _T_163 ? issue_slots_5_out_uop_debug_tsrc : _T_162 ? issue_slots_4_out_uop_debug_tsrc : issue_slots_3_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_debug_fsrc = _T_163 ? issue_slots_5_out_uop_debug_fsrc : _T_162 ? issue_slots_4_out_uop_debug_fsrc : issue_slots_3_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_bp_xcpt_if = _T_163 ? issue_slots_5_out_uop_bp_xcpt_if : _T_162 ? issue_slots_4_out_uop_bp_xcpt_if : issue_slots_3_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_bp_debug_if = _T_163 ? issue_slots_5_out_uop_bp_debug_if : _T_162 ? issue_slots_4_out_uop_bp_debug_if : issue_slots_3_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_xcpt_ma_if = _T_163 ? issue_slots_5_out_uop_xcpt_ma_if : _T_162 ? issue_slots_4_out_uop_xcpt_ma_if : issue_slots_3_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_xcpt_ae_if = _T_163 ? issue_slots_5_out_uop_xcpt_ae_if : _T_162 ? issue_slots_4_out_uop_xcpt_ae_if : issue_slots_3_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_xcpt_pf_if = _T_163 ? issue_slots_5_out_uop_xcpt_pf_if : _T_162 ? issue_slots_4_out_uop_xcpt_pf_if : issue_slots_3_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_typ = _T_163 ? issue_slots_5_out_uop_fp_typ : _T_162 ? issue_slots_4_out_uop_fp_typ : issue_slots_3_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_rm = _T_163 ? issue_slots_5_out_uop_fp_rm : _T_162 ? issue_slots_4_out_uop_fp_rm : issue_slots_3_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_val = _T_163 ? issue_slots_5_out_uop_fp_val : _T_162 ? issue_slots_4_out_uop_fp_val : issue_slots_3_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fcn_op = _T_163 ? issue_slots_5_out_uop_fcn_op : _T_162 ? issue_slots_4_out_uop_fcn_op : issue_slots_3_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fcn_dw = _T_163 ? issue_slots_5_out_uop_fcn_dw : _T_162 ? issue_slots_4_out_uop_fcn_dw : issue_slots_3_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_frs3_en = _T_163 ? issue_slots_5_out_uop_frs3_en : _T_162 ? issue_slots_4_out_uop_frs3_en : issue_slots_3_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs2_rtype = _T_163 ? issue_slots_5_out_uop_lrs2_rtype : _T_162 ? issue_slots_4_out_uop_lrs2_rtype : issue_slots_3_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs1_rtype = _T_163 ? issue_slots_5_out_uop_lrs1_rtype : _T_162 ? issue_slots_4_out_uop_lrs1_rtype : issue_slots_3_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_dst_rtype = _T_163 ? issue_slots_5_out_uop_dst_rtype : _T_162 ? issue_slots_4_out_uop_dst_rtype : issue_slots_3_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs3 = _T_163 ? issue_slots_5_out_uop_lrs3 : _T_162 ? issue_slots_4_out_uop_lrs3 : issue_slots_3_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs2 = _T_163 ? issue_slots_5_out_uop_lrs2 : _T_162 ? issue_slots_4_out_uop_lrs2 : issue_slots_3_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_lrs1 = _T_163 ? issue_slots_5_out_uop_lrs1 : _T_162 ? issue_slots_4_out_uop_lrs1 : issue_slots_3_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ldst = _T_163 ? issue_slots_5_out_uop_ldst : _T_162 ? issue_slots_4_out_uop_ldst : issue_slots_3_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ldst_is_rs1 = _T_163 ? issue_slots_5_out_uop_ldst_is_rs1 : _T_162 ? issue_slots_4_out_uop_ldst_is_rs1 : issue_slots_3_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_csr_cmd = _T_163 ? issue_slots_5_out_uop_csr_cmd : _T_162 ? issue_slots_4_out_uop_csr_cmd : issue_slots_3_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_flush_on_commit = _T_163 ? issue_slots_5_out_uop_flush_on_commit : _T_162 ? issue_slots_4_out_uop_flush_on_commit : issue_slots_3_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_unique = _T_163 ? issue_slots_5_out_uop_is_unique : _T_162 ? issue_slots_4_out_uop_is_unique : issue_slots_3_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_uses_stq = _T_163 ? issue_slots_5_out_uop_uses_stq : _T_162 ? issue_slots_4_out_uop_uses_stq : issue_slots_3_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_uses_ldq = _T_163 ? issue_slots_5_out_uop_uses_ldq : _T_162 ? issue_slots_4_out_uop_uses_ldq : issue_slots_3_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_mem_signed = _T_163 ? issue_slots_5_out_uop_mem_signed : _T_162 ? issue_slots_4_out_uop_mem_signed : issue_slots_3_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_mem_size = _T_163 ? issue_slots_5_out_uop_mem_size : _T_162 ? issue_slots_4_out_uop_mem_size : issue_slots_3_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_mem_cmd = _T_163 ? issue_slots_5_out_uop_mem_cmd : _T_162 ? issue_slots_4_out_uop_mem_cmd : issue_slots_3_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_exc_cause = _T_163 ? issue_slots_5_out_uop_exc_cause : _T_162 ? issue_slots_4_out_uop_exc_cause : issue_slots_3_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_exception = _T_163 ? issue_slots_5_out_uop_exception : _T_162 ? issue_slots_4_out_uop_exception : issue_slots_3_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_stale_pdst = _T_163 ? issue_slots_5_out_uop_stale_pdst : _T_162 ? issue_slots_4_out_uop_stale_pdst : issue_slots_3_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ppred_busy = _T_163 ? issue_slots_5_out_uop_ppred_busy : _T_162 ? issue_slots_4_out_uop_ppred_busy : issue_slots_3_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs3_busy = _T_163 ? issue_slots_5_out_uop_prs3_busy : _T_162 ? issue_slots_4_out_uop_prs3_busy : issue_slots_3_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs2_busy = _T_163 ? issue_slots_5_out_uop_prs2_busy : _T_162 ? issue_slots_4_out_uop_prs2_busy : issue_slots_3_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs1_busy = _T_163 ? issue_slots_5_out_uop_prs1_busy : _T_162 ? issue_slots_4_out_uop_prs1_busy : issue_slots_3_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ppred = _T_163 ? issue_slots_5_out_uop_ppred : _T_162 ? issue_slots_4_out_uop_ppred : issue_slots_3_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs3 = _T_163 ? issue_slots_5_out_uop_prs3 : _T_162 ? issue_slots_4_out_uop_prs3 : issue_slots_3_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs2 = _T_163 ? issue_slots_5_out_uop_prs2 : _T_162 ? issue_slots_4_out_uop_prs2 : issue_slots_3_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_prs1 = _T_163 ? issue_slots_5_out_uop_prs1 : _T_162 ? issue_slots_4_out_uop_prs1 : issue_slots_3_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_pdst = _T_163 ? issue_slots_5_out_uop_pdst : _T_162 ? issue_slots_4_out_uop_pdst : issue_slots_3_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_rxq_idx = _T_163 ? issue_slots_5_out_uop_rxq_idx : _T_162 ? issue_slots_4_out_uop_rxq_idx : issue_slots_3_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_stq_idx = _T_163 ? issue_slots_5_out_uop_stq_idx : _T_162 ? issue_slots_4_out_uop_stq_idx : issue_slots_3_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ldq_idx = _T_163 ? issue_slots_5_out_uop_ldq_idx : _T_162 ? issue_slots_4_out_uop_ldq_idx : issue_slots_3_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_rob_idx = _T_163 ? issue_slots_5_out_uop_rob_idx : _T_162 ? issue_slots_4_out_uop_rob_idx : issue_slots_3_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_vec = _T_163 ? issue_slots_5_out_uop_fp_ctrl_vec : _T_162 ? issue_slots_4_out_uop_fp_ctrl_vec : issue_slots_3_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_wflags = _T_163 ? issue_slots_5_out_uop_fp_ctrl_wflags : _T_162 ? issue_slots_4_out_uop_fp_ctrl_wflags : issue_slots_3_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_sqrt = _T_163 ? issue_slots_5_out_uop_fp_ctrl_sqrt : _T_162 ? issue_slots_4_out_uop_fp_ctrl_sqrt : issue_slots_3_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_div = _T_163 ? issue_slots_5_out_uop_fp_ctrl_div : _T_162 ? issue_slots_4_out_uop_fp_ctrl_div : issue_slots_3_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_fma = _T_163 ? issue_slots_5_out_uop_fp_ctrl_fma : _T_162 ? issue_slots_4_out_uop_fp_ctrl_fma : issue_slots_3_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_fastpipe = _T_163 ? issue_slots_5_out_uop_fp_ctrl_fastpipe : _T_162 ? issue_slots_4_out_uop_fp_ctrl_fastpipe : issue_slots_3_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_toint = _T_163 ? issue_slots_5_out_uop_fp_ctrl_toint : _T_162 ? issue_slots_4_out_uop_fp_ctrl_toint : issue_slots_3_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_fromint = _T_163 ? issue_slots_5_out_uop_fp_ctrl_fromint : _T_162 ? issue_slots_4_out_uop_fp_ctrl_fromint : issue_slots_3_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_typeTagOut = _T_163 ? issue_slots_5_out_uop_fp_ctrl_typeTagOut : _T_162 ? issue_slots_4_out_uop_fp_ctrl_typeTagOut : issue_slots_3_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_typeTagIn = _T_163 ? issue_slots_5_out_uop_fp_ctrl_typeTagIn : _T_162 ? issue_slots_4_out_uop_fp_ctrl_typeTagIn : issue_slots_3_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_swap23 = _T_163 ? issue_slots_5_out_uop_fp_ctrl_swap23 : _T_162 ? issue_slots_4_out_uop_fp_ctrl_swap23 : issue_slots_3_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_swap12 = _T_163 ? issue_slots_5_out_uop_fp_ctrl_swap12 : _T_162 ? issue_slots_4_out_uop_fp_ctrl_swap12 : issue_slots_3_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_ren3 = _T_163 ? issue_slots_5_out_uop_fp_ctrl_ren3 : _T_162 ? issue_slots_4_out_uop_fp_ctrl_ren3 : issue_slots_3_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_ren2 = _T_163 ? issue_slots_5_out_uop_fp_ctrl_ren2 : _T_162 ? issue_slots_4_out_uop_fp_ctrl_ren2 : issue_slots_3_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_ren1 = _T_163 ? issue_slots_5_out_uop_fp_ctrl_ren1 : _T_162 ? issue_slots_4_out_uop_fp_ctrl_ren1 : issue_slots_3_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_wen = _T_163 ? issue_slots_5_out_uop_fp_ctrl_wen : _T_162 ? issue_slots_4_out_uop_fp_ctrl_wen : issue_slots_3_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fp_ctrl_ldst = _T_163 ? issue_slots_5_out_uop_fp_ctrl_ldst : _T_162 ? issue_slots_4_out_uop_fp_ctrl_ldst : issue_slots_3_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_op2_sel = _T_163 ? issue_slots_5_out_uop_op2_sel : _T_162 ? issue_slots_4_out_uop_op2_sel : issue_slots_3_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_op1_sel = _T_163 ? issue_slots_5_out_uop_op1_sel : _T_162 ? issue_slots_4_out_uop_op1_sel : issue_slots_3_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_imm_packed = _T_163 ? issue_slots_5_out_uop_imm_packed : _T_162 ? issue_slots_4_out_uop_imm_packed : issue_slots_3_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_pimm = _T_163 ? issue_slots_5_out_uop_pimm : _T_162 ? issue_slots_4_out_uop_pimm : issue_slots_3_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_imm_sel = _T_163 ? issue_slots_5_out_uop_imm_sel : _T_162 ? issue_slots_4_out_uop_imm_sel : issue_slots_3_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_imm_rename = _T_163 ? issue_slots_5_out_uop_imm_rename : _T_162 ? issue_slots_4_out_uop_imm_rename : issue_slots_3_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_taken = _T_163 ? issue_slots_5_out_uop_taken : _T_162 ? issue_slots_4_out_uop_taken : issue_slots_3_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_pc_lob = _T_163 ? issue_slots_5_out_uop_pc_lob : _T_162 ? issue_slots_4_out_uop_pc_lob : issue_slots_3_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_edge_inst = _T_163 ? issue_slots_5_out_uop_edge_inst : _T_162 ? issue_slots_4_out_uop_edge_inst : issue_slots_3_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_ftq_idx = _T_163 ? issue_slots_5_out_uop_ftq_idx : _T_162 ? issue_slots_4_out_uop_ftq_idx : issue_slots_3_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_mov = _T_163 ? issue_slots_5_out_uop_is_mov : _T_162 ? issue_slots_4_out_uop_is_mov : issue_slots_3_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_rocc = _T_163 ? issue_slots_5_out_uop_is_rocc : _T_162 ? issue_slots_4_out_uop_is_rocc : issue_slots_3_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_sys_pc2epc = _T_163 ? issue_slots_5_out_uop_is_sys_pc2epc : _T_162 ? issue_slots_4_out_uop_is_sys_pc2epc : issue_slots_3_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_eret = _T_163 ? issue_slots_5_out_uop_is_eret : _T_162 ? issue_slots_4_out_uop_is_eret : issue_slots_3_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_amo = _T_163 ? issue_slots_5_out_uop_is_amo : _T_162 ? issue_slots_4_out_uop_is_amo : issue_slots_3_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_sfence = _T_163 ? issue_slots_5_out_uop_is_sfence : _T_162 ? issue_slots_4_out_uop_is_sfence : issue_slots_3_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_fencei = _T_163 ? issue_slots_5_out_uop_is_fencei : _T_162 ? issue_slots_4_out_uop_is_fencei : issue_slots_3_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_fence = _T_163 ? issue_slots_5_out_uop_is_fence : _T_162 ? issue_slots_4_out_uop_is_fence : issue_slots_3_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_sfb = _T_163 ? issue_slots_5_out_uop_is_sfb : _T_162 ? issue_slots_4_out_uop_is_sfb : issue_slots_3_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_br_type = _T_163 ? issue_slots_5_out_uop_br_type : _T_162 ? issue_slots_4_out_uop_br_type : issue_slots_3_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_br_tag = _T_163 ? issue_slots_5_out_uop_br_tag : _T_162 ? issue_slots_4_out_uop_br_tag : issue_slots_3_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_br_mask = _T_163 ? issue_slots_5_out_uop_br_mask : _T_162 ? issue_slots_4_out_uop_br_mask : issue_slots_3_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_dis_col_sel = _T_163 ? issue_slots_5_out_uop_dis_col_sel : _T_162 ? issue_slots_4_out_uop_dis_col_sel : issue_slots_3_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_p3_bypass_hint = _T_163 ? issue_slots_5_out_uop_iw_p3_bypass_hint : _T_162 ? issue_slots_4_out_uop_iw_p3_bypass_hint : issue_slots_3_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_p2_bypass_hint = _T_163 ? issue_slots_5_out_uop_iw_p2_bypass_hint : _T_162 ? issue_slots_4_out_uop_iw_p2_bypass_hint : issue_slots_3_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_p1_bypass_hint = _T_163 ? issue_slots_5_out_uop_iw_p1_bypass_hint : _T_162 ? issue_slots_4_out_uop_iw_p1_bypass_hint : issue_slots_3_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iw_issued = _T_163 ? issue_slots_5_out_uop_iw_issued : _T_162 ? issue_slots_4_out_uop_iw_issued : issue_slots_3_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_0 = _T_163 ? issue_slots_5_out_uop_fu_code_0 : _T_162 ? issue_slots_4_out_uop_fu_code_0 : issue_slots_3_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_1 = _T_163 ? issue_slots_5_out_uop_fu_code_1 : _T_162 ? issue_slots_4_out_uop_fu_code_1 : issue_slots_3_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_2 = _T_163 ? issue_slots_5_out_uop_fu_code_2 : _T_162 ? issue_slots_4_out_uop_fu_code_2 : issue_slots_3_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_3 = _T_163 ? issue_slots_5_out_uop_fu_code_3 : _T_162 ? issue_slots_4_out_uop_fu_code_3 : issue_slots_3_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_4 = _T_163 ? issue_slots_5_out_uop_fu_code_4 : _T_162 ? issue_slots_4_out_uop_fu_code_4 : issue_slots_3_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_5 = _T_163 ? issue_slots_5_out_uop_fu_code_5 : _T_162 ? issue_slots_4_out_uop_fu_code_5 : issue_slots_3_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_6 = _T_163 ? issue_slots_5_out_uop_fu_code_6 : _T_162 ? issue_slots_4_out_uop_fu_code_6 : issue_slots_3_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_7 = _T_163 ? issue_slots_5_out_uop_fu_code_7 : _T_162 ? issue_slots_4_out_uop_fu_code_7 : issue_slots_3_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_8 = _T_163 ? issue_slots_5_out_uop_fu_code_8 : _T_162 ? issue_slots_4_out_uop_fu_code_8 : issue_slots_3_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_fu_code_9 = _T_163 ? issue_slots_5_out_uop_fu_code_9 : _T_162 ? issue_slots_4_out_uop_fu_code_9 : issue_slots_3_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iq_type_0 = _T_163 ? issue_slots_5_out_uop_iq_type_0 : _T_162 ? issue_slots_4_out_uop_iq_type_0 : issue_slots_3_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iq_type_1 = _T_163 ? issue_slots_5_out_uop_iq_type_1 : _T_162 ? issue_slots_4_out_uop_iq_type_1 : issue_slots_3_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iq_type_2 = _T_163 ? issue_slots_5_out_uop_iq_type_2 : _T_162 ? issue_slots_4_out_uop_iq_type_2 : issue_slots_3_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_iq_type_3 = _T_163 ? issue_slots_5_out_uop_iq_type_3 : _T_162 ? issue_slots_4_out_uop_iq_type_3 : issue_slots_3_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_debug_pc = _T_163 ? issue_slots_5_out_uop_debug_pc : _T_162 ? issue_slots_4_out_uop_debug_pc : issue_slots_3_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_is_rvc = _T_163 ? issue_slots_5_out_uop_is_rvc : _T_162 ? issue_slots_4_out_uop_is_rvc : issue_slots_3_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_debug_inst = _T_163 ? issue_slots_5_out_uop_debug_inst : _T_162 ? issue_slots_4_out_uop_debug_inst : issue_slots_3_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_2_in_uop_bits_inst = _T_163 ? issue_slots_5_out_uop_inst : _T_162 ? issue_slots_4_out_uop_inst : issue_slots_3_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_2_clear_T = \|shamts_oh_2; // @[issue-unit-age-ordered.scala:158:23, :199:49] assign issue_slots_2_clear = _issue_slots_2_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_165 = shamts_oh_5 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_166 = shamts_oh_6 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_3_in_uop_valid = _T_166 ? issue_slots_6_will_be_valid : _T_165 ? issue_slots_5_will_be_valid : shamts_oh_4 == 3'h1 & issue_slots_4_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_3_in_uop_bits_debug_tsrc = _T_166 ? issue_slots_6_out_uop_debug_tsrc : _T_165 ? issue_slots_5_out_uop_debug_tsrc : issue_slots_4_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_debug_fsrc = _T_166 ? issue_slots_6_out_uop_debug_fsrc : _T_165 ? issue_slots_5_out_uop_debug_fsrc : issue_slots_4_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_bp_xcpt_if = _T_166 ? issue_slots_6_out_uop_bp_xcpt_if : _T_165 ? issue_slots_5_out_uop_bp_xcpt_if : issue_slots_4_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_bp_debug_if = _T_166 ? issue_slots_6_out_uop_bp_debug_if : _T_165 ? issue_slots_5_out_uop_bp_debug_if : issue_slots_4_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_xcpt_ma_if = _T_166 ? issue_slots_6_out_uop_xcpt_ma_if : _T_165 ? issue_slots_5_out_uop_xcpt_ma_if : issue_slots_4_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_xcpt_ae_if = _T_166 ? issue_slots_6_out_uop_xcpt_ae_if : _T_165 ? issue_slots_5_out_uop_xcpt_ae_if : issue_slots_4_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_xcpt_pf_if = _T_166 ? issue_slots_6_out_uop_xcpt_pf_if : _T_165 ? issue_slots_5_out_uop_xcpt_pf_if : issue_slots_4_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_typ = _T_166 ? issue_slots_6_out_uop_fp_typ : _T_165 ? issue_slots_5_out_uop_fp_typ : issue_slots_4_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_rm = _T_166 ? issue_slots_6_out_uop_fp_rm : _T_165 ? issue_slots_5_out_uop_fp_rm : issue_slots_4_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_val = _T_166 ? issue_slots_6_out_uop_fp_val : _T_165 ? issue_slots_5_out_uop_fp_val : issue_slots_4_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fcn_op = _T_166 ? issue_slots_6_out_uop_fcn_op : _T_165 ? issue_slots_5_out_uop_fcn_op : issue_slots_4_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fcn_dw = _T_166 ? issue_slots_6_out_uop_fcn_dw : _T_165 ? issue_slots_5_out_uop_fcn_dw : issue_slots_4_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_frs3_en = _T_166 ? issue_slots_6_out_uop_frs3_en : _T_165 ? issue_slots_5_out_uop_frs3_en : issue_slots_4_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs2_rtype = _T_166 ? issue_slots_6_out_uop_lrs2_rtype : _T_165 ? issue_slots_5_out_uop_lrs2_rtype : issue_slots_4_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs1_rtype = _T_166 ? issue_slots_6_out_uop_lrs1_rtype : _T_165 ? issue_slots_5_out_uop_lrs1_rtype : issue_slots_4_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_dst_rtype = _T_166 ? issue_slots_6_out_uop_dst_rtype : _T_165 ? issue_slots_5_out_uop_dst_rtype : issue_slots_4_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs3 = _T_166 ? issue_slots_6_out_uop_lrs3 : _T_165 ? issue_slots_5_out_uop_lrs3 : issue_slots_4_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs2 = _T_166 ? issue_slots_6_out_uop_lrs2 : _T_165 ? issue_slots_5_out_uop_lrs2 : issue_slots_4_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_lrs1 = _T_166 ? issue_slots_6_out_uop_lrs1 : _T_165 ? issue_slots_5_out_uop_lrs1 : issue_slots_4_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ldst = _T_166 ? issue_slots_6_out_uop_ldst : _T_165 ? issue_slots_5_out_uop_ldst : issue_slots_4_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ldst_is_rs1 = _T_166 ? issue_slots_6_out_uop_ldst_is_rs1 : _T_165 ? issue_slots_5_out_uop_ldst_is_rs1 : issue_slots_4_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_csr_cmd = _T_166 ? issue_slots_6_out_uop_csr_cmd : _T_165 ? issue_slots_5_out_uop_csr_cmd : issue_slots_4_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_flush_on_commit = _T_166 ? issue_slots_6_out_uop_flush_on_commit : _T_165 ? issue_slots_5_out_uop_flush_on_commit : issue_slots_4_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_unique = _T_166 ? issue_slots_6_out_uop_is_unique : _T_165 ? issue_slots_5_out_uop_is_unique : issue_slots_4_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_uses_stq = _T_166 ? issue_slots_6_out_uop_uses_stq : _T_165 ? issue_slots_5_out_uop_uses_stq : issue_slots_4_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_uses_ldq = _T_166 ? issue_slots_6_out_uop_uses_ldq : _T_165 ? issue_slots_5_out_uop_uses_ldq : issue_slots_4_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_mem_signed = _T_166 ? issue_slots_6_out_uop_mem_signed : _T_165 ? issue_slots_5_out_uop_mem_signed : issue_slots_4_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_mem_size = _T_166 ? issue_slots_6_out_uop_mem_size : _T_165 ? issue_slots_5_out_uop_mem_size : issue_slots_4_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_mem_cmd = _T_166 ? issue_slots_6_out_uop_mem_cmd : _T_165 ? issue_slots_5_out_uop_mem_cmd : issue_slots_4_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_exc_cause = _T_166 ? issue_slots_6_out_uop_exc_cause : _T_165 ? issue_slots_5_out_uop_exc_cause : issue_slots_4_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_exception = _T_166 ? issue_slots_6_out_uop_exception : _T_165 ? issue_slots_5_out_uop_exception : issue_slots_4_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_stale_pdst = _T_166 ? issue_slots_6_out_uop_stale_pdst : _T_165 ? issue_slots_5_out_uop_stale_pdst : issue_slots_4_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ppred_busy = _T_166 ? issue_slots_6_out_uop_ppred_busy : _T_165 ? issue_slots_5_out_uop_ppred_busy : issue_slots_4_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs3_busy = _T_166 ? issue_slots_6_out_uop_prs3_busy : _T_165 ? issue_slots_5_out_uop_prs3_busy : issue_slots_4_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs2_busy = _T_166 ? issue_slots_6_out_uop_prs2_busy : _T_165 ? issue_slots_5_out_uop_prs2_busy : issue_slots_4_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs1_busy = _T_166 ? issue_slots_6_out_uop_prs1_busy : _T_165 ? issue_slots_5_out_uop_prs1_busy : issue_slots_4_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ppred = _T_166 ? issue_slots_6_out_uop_ppred : _T_165 ? issue_slots_5_out_uop_ppred : issue_slots_4_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs3 = _T_166 ? issue_slots_6_out_uop_prs3 : _T_165 ? issue_slots_5_out_uop_prs3 : issue_slots_4_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs2 = _T_166 ? issue_slots_6_out_uop_prs2 : _T_165 ? issue_slots_5_out_uop_prs2 : issue_slots_4_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_prs1 = _T_166 ? issue_slots_6_out_uop_prs1 : _T_165 ? issue_slots_5_out_uop_prs1 : issue_slots_4_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_pdst = _T_166 ? issue_slots_6_out_uop_pdst : _T_165 ? issue_slots_5_out_uop_pdst : issue_slots_4_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_rxq_idx = _T_166 ? issue_slots_6_out_uop_rxq_idx : _T_165 ? issue_slots_5_out_uop_rxq_idx : issue_slots_4_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_stq_idx = _T_166 ? issue_slots_6_out_uop_stq_idx : _T_165 ? issue_slots_5_out_uop_stq_idx : issue_slots_4_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ldq_idx = _T_166 ? issue_slots_6_out_uop_ldq_idx : _T_165 ? issue_slots_5_out_uop_ldq_idx : issue_slots_4_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_rob_idx = _T_166 ? issue_slots_6_out_uop_rob_idx : _T_165 ? issue_slots_5_out_uop_rob_idx : issue_slots_4_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_vec = _T_166 ? issue_slots_6_out_uop_fp_ctrl_vec : _T_165 ? issue_slots_5_out_uop_fp_ctrl_vec : issue_slots_4_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_wflags = _T_166 ? issue_slots_6_out_uop_fp_ctrl_wflags : _T_165 ? issue_slots_5_out_uop_fp_ctrl_wflags : issue_slots_4_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_sqrt = _T_166 ? issue_slots_6_out_uop_fp_ctrl_sqrt : _T_165 ? issue_slots_5_out_uop_fp_ctrl_sqrt : issue_slots_4_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_div = _T_166 ? issue_slots_6_out_uop_fp_ctrl_div : _T_165 ? issue_slots_5_out_uop_fp_ctrl_div : issue_slots_4_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_fma = _T_166 ? issue_slots_6_out_uop_fp_ctrl_fma : _T_165 ? issue_slots_5_out_uop_fp_ctrl_fma : issue_slots_4_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_fastpipe = _T_166 ? issue_slots_6_out_uop_fp_ctrl_fastpipe : _T_165 ? issue_slots_5_out_uop_fp_ctrl_fastpipe : issue_slots_4_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_toint = _T_166 ? issue_slots_6_out_uop_fp_ctrl_toint : _T_165 ? issue_slots_5_out_uop_fp_ctrl_toint : issue_slots_4_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_fromint = _T_166 ? issue_slots_6_out_uop_fp_ctrl_fromint : _T_165 ? issue_slots_5_out_uop_fp_ctrl_fromint : issue_slots_4_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_typeTagOut = _T_166 ? issue_slots_6_out_uop_fp_ctrl_typeTagOut : _T_165 ? issue_slots_5_out_uop_fp_ctrl_typeTagOut : issue_slots_4_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_typeTagIn = _T_166 ? issue_slots_6_out_uop_fp_ctrl_typeTagIn : _T_165 ? issue_slots_5_out_uop_fp_ctrl_typeTagIn : issue_slots_4_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_swap23 = _T_166 ? issue_slots_6_out_uop_fp_ctrl_swap23 : _T_165 ? issue_slots_5_out_uop_fp_ctrl_swap23 : issue_slots_4_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_swap12 = _T_166 ? issue_slots_6_out_uop_fp_ctrl_swap12 : _T_165 ? issue_slots_5_out_uop_fp_ctrl_swap12 : issue_slots_4_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_ren3 = _T_166 ? issue_slots_6_out_uop_fp_ctrl_ren3 : _T_165 ? issue_slots_5_out_uop_fp_ctrl_ren3 : issue_slots_4_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_ren2 = _T_166 ? issue_slots_6_out_uop_fp_ctrl_ren2 : _T_165 ? issue_slots_5_out_uop_fp_ctrl_ren2 : issue_slots_4_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_ren1 = _T_166 ? issue_slots_6_out_uop_fp_ctrl_ren1 : _T_165 ? issue_slots_5_out_uop_fp_ctrl_ren1 : issue_slots_4_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_wen = _T_166 ? issue_slots_6_out_uop_fp_ctrl_wen : _T_165 ? issue_slots_5_out_uop_fp_ctrl_wen : issue_slots_4_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fp_ctrl_ldst = _T_166 ? issue_slots_6_out_uop_fp_ctrl_ldst : _T_165 ? issue_slots_5_out_uop_fp_ctrl_ldst : issue_slots_4_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_op2_sel = _T_166 ? issue_slots_6_out_uop_op2_sel : _T_165 ? issue_slots_5_out_uop_op2_sel : issue_slots_4_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_op1_sel = _T_166 ? issue_slots_6_out_uop_op1_sel : _T_165 ? issue_slots_5_out_uop_op1_sel : issue_slots_4_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_imm_packed = _T_166 ? issue_slots_6_out_uop_imm_packed : _T_165 ? issue_slots_5_out_uop_imm_packed : issue_slots_4_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_pimm = _T_166 ? issue_slots_6_out_uop_pimm : _T_165 ? issue_slots_5_out_uop_pimm : issue_slots_4_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_imm_sel = _T_166 ? issue_slots_6_out_uop_imm_sel : _T_165 ? issue_slots_5_out_uop_imm_sel : issue_slots_4_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_imm_rename = _T_166 ? issue_slots_6_out_uop_imm_rename : _T_165 ? issue_slots_5_out_uop_imm_rename : issue_slots_4_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_taken = _T_166 ? issue_slots_6_out_uop_taken : _T_165 ? issue_slots_5_out_uop_taken : issue_slots_4_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_pc_lob = _T_166 ? issue_slots_6_out_uop_pc_lob : _T_165 ? issue_slots_5_out_uop_pc_lob : issue_slots_4_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_edge_inst = _T_166 ? issue_slots_6_out_uop_edge_inst : _T_165 ? issue_slots_5_out_uop_edge_inst : issue_slots_4_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_ftq_idx = _T_166 ? issue_slots_6_out_uop_ftq_idx : _T_165 ? issue_slots_5_out_uop_ftq_idx : issue_slots_4_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_mov = _T_166 ? issue_slots_6_out_uop_is_mov : _T_165 ? issue_slots_5_out_uop_is_mov : issue_slots_4_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_rocc = _T_166 ? issue_slots_6_out_uop_is_rocc : _T_165 ? issue_slots_5_out_uop_is_rocc : issue_slots_4_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_sys_pc2epc = _T_166 ? issue_slots_6_out_uop_is_sys_pc2epc : _T_165 ? issue_slots_5_out_uop_is_sys_pc2epc : issue_slots_4_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_eret = _T_166 ? issue_slots_6_out_uop_is_eret : _T_165 ? issue_slots_5_out_uop_is_eret : issue_slots_4_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_amo = _T_166 ? issue_slots_6_out_uop_is_amo : _T_165 ? issue_slots_5_out_uop_is_amo : issue_slots_4_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_sfence = _T_166 ? issue_slots_6_out_uop_is_sfence : _T_165 ? issue_slots_5_out_uop_is_sfence : issue_slots_4_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_fencei = _T_166 ? issue_slots_6_out_uop_is_fencei : _T_165 ? issue_slots_5_out_uop_is_fencei : issue_slots_4_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_fence = _T_166 ? issue_slots_6_out_uop_is_fence : _T_165 ? issue_slots_5_out_uop_is_fence : issue_slots_4_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_sfb = _T_166 ? issue_slots_6_out_uop_is_sfb : _T_165 ? issue_slots_5_out_uop_is_sfb : issue_slots_4_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_br_type = _T_166 ? issue_slots_6_out_uop_br_type : _T_165 ? issue_slots_5_out_uop_br_type : issue_slots_4_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_br_tag = _T_166 ? issue_slots_6_out_uop_br_tag : _T_165 ? issue_slots_5_out_uop_br_tag : issue_slots_4_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_br_mask = _T_166 ? issue_slots_6_out_uop_br_mask : _T_165 ? issue_slots_5_out_uop_br_mask : issue_slots_4_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_dis_col_sel = _T_166 ? issue_slots_6_out_uop_dis_col_sel : _T_165 ? issue_slots_5_out_uop_dis_col_sel : issue_slots_4_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_p3_bypass_hint = _T_166 ? issue_slots_6_out_uop_iw_p3_bypass_hint : _T_165 ? issue_slots_5_out_uop_iw_p3_bypass_hint : issue_slots_4_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_p2_bypass_hint = _T_166 ? issue_slots_6_out_uop_iw_p2_bypass_hint : _T_165 ? issue_slots_5_out_uop_iw_p2_bypass_hint : issue_slots_4_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_p1_bypass_hint = _T_166 ? issue_slots_6_out_uop_iw_p1_bypass_hint : _T_165 ? issue_slots_5_out_uop_iw_p1_bypass_hint : issue_slots_4_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iw_issued = _T_166 ? issue_slots_6_out_uop_iw_issued : _T_165 ? issue_slots_5_out_uop_iw_issued : issue_slots_4_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_0 = _T_166 ? issue_slots_6_out_uop_fu_code_0 : _T_165 ? issue_slots_5_out_uop_fu_code_0 : issue_slots_4_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_1 = _T_166 ? issue_slots_6_out_uop_fu_code_1 : _T_165 ? issue_slots_5_out_uop_fu_code_1 : issue_slots_4_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_2 = _T_166 ? issue_slots_6_out_uop_fu_code_2 : _T_165 ? issue_slots_5_out_uop_fu_code_2 : issue_slots_4_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_3 = _T_166 ? issue_slots_6_out_uop_fu_code_3 : _T_165 ? issue_slots_5_out_uop_fu_code_3 : issue_slots_4_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_4 = _T_166 ? issue_slots_6_out_uop_fu_code_4 : _T_165 ? issue_slots_5_out_uop_fu_code_4 : issue_slots_4_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_5 = _T_166 ? issue_slots_6_out_uop_fu_code_5 : _T_165 ? issue_slots_5_out_uop_fu_code_5 : issue_slots_4_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_6 = _T_166 ? issue_slots_6_out_uop_fu_code_6 : _T_165 ? issue_slots_5_out_uop_fu_code_6 : issue_slots_4_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_7 = _T_166 ? issue_slots_6_out_uop_fu_code_7 : _T_165 ? issue_slots_5_out_uop_fu_code_7 : issue_slots_4_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_8 = _T_166 ? issue_slots_6_out_uop_fu_code_8 : _T_165 ? issue_slots_5_out_uop_fu_code_8 : issue_slots_4_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_fu_code_9 = _T_166 ? issue_slots_6_out_uop_fu_code_9 : _T_165 ? issue_slots_5_out_uop_fu_code_9 : issue_slots_4_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iq_type_0 = _T_166 ? issue_slots_6_out_uop_iq_type_0 : _T_165 ? issue_slots_5_out_uop_iq_type_0 : issue_slots_4_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iq_type_1 = _T_166 ? issue_slots_6_out_uop_iq_type_1 : _T_165 ? issue_slots_5_out_uop_iq_type_1 : issue_slots_4_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iq_type_2 = _T_166 ? issue_slots_6_out_uop_iq_type_2 : _T_165 ? issue_slots_5_out_uop_iq_type_2 : issue_slots_4_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_iq_type_3 = _T_166 ? issue_slots_6_out_uop_iq_type_3 : _T_165 ? issue_slots_5_out_uop_iq_type_3 : issue_slots_4_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_debug_pc = _T_166 ? issue_slots_6_out_uop_debug_pc : _T_165 ? issue_slots_5_out_uop_debug_pc : issue_slots_4_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_is_rvc = _T_166 ? issue_slots_6_out_uop_is_rvc : _T_165 ? issue_slots_5_out_uop_is_rvc : issue_slots_4_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_debug_inst = _T_166 ? issue_slots_6_out_uop_debug_inst : _T_165 ? issue_slots_5_out_uop_debug_inst : issue_slots_4_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_3_in_uop_bits_inst = _T_166 ? issue_slots_6_out_uop_inst : _T_165 ? issue_slots_5_out_uop_inst : issue_slots_4_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_3_clear_T = \|shamts_oh_3; // @[issue-unit-age-ordered.scala:158:23, :199:49] assign issue_slots_3_clear = _issue_slots_3_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_168 = shamts_oh_6 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_169 = shamts_oh_7 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_4_in_uop_valid = _T_169 ? issue_slots_7_will_be_valid : _T_168 ? issue_slots_6_will_be_valid : shamts_oh_5 == 3'h1 & issue_slots_5_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_4_in_uop_bits_debug_tsrc = _T_169 ? issue_slots_7_out_uop_debug_tsrc : _T_168 ? issue_slots_6_out_uop_debug_tsrc : issue_slots_5_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_debug_fsrc = _T_169 ? issue_slots_7_out_uop_debug_fsrc : _T_168 ? issue_slots_6_out_uop_debug_fsrc : issue_slots_5_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_bp_xcpt_if = _T_169 ? issue_slots_7_out_uop_bp_xcpt_if : _T_168 ? issue_slots_6_out_uop_bp_xcpt_if : issue_slots_5_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_bp_debug_if = _T_169 ? issue_slots_7_out_uop_bp_debug_if : _T_168 ? issue_slots_6_out_uop_bp_debug_if : issue_slots_5_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_xcpt_ma_if = _T_169 ? issue_slots_7_out_uop_xcpt_ma_if : _T_168 ? issue_slots_6_out_uop_xcpt_ma_if : issue_slots_5_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_xcpt_ae_if = _T_169 ? issue_slots_7_out_uop_xcpt_ae_if : _T_168 ? issue_slots_6_out_uop_xcpt_ae_if : issue_slots_5_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_xcpt_pf_if = _T_169 ? issue_slots_7_out_uop_xcpt_pf_if : _T_168 ? issue_slots_6_out_uop_xcpt_pf_if : issue_slots_5_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_typ = _T_169 ? issue_slots_7_out_uop_fp_typ : _T_168 ? issue_slots_6_out_uop_fp_typ : issue_slots_5_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_rm = _T_169 ? issue_slots_7_out_uop_fp_rm : _T_168 ? issue_slots_6_out_uop_fp_rm : issue_slots_5_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_val = _T_169 ? issue_slots_7_out_uop_fp_val : _T_168 ? issue_slots_6_out_uop_fp_val : issue_slots_5_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fcn_op = _T_169 ? issue_slots_7_out_uop_fcn_op : _T_168 ? issue_slots_6_out_uop_fcn_op : issue_slots_5_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fcn_dw = _T_169 ? issue_slots_7_out_uop_fcn_dw : _T_168 ? issue_slots_6_out_uop_fcn_dw : issue_slots_5_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_frs3_en = _T_169 ? issue_slots_7_out_uop_frs3_en : _T_168 ? issue_slots_6_out_uop_frs3_en : issue_slots_5_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs2_rtype = _T_169 ? issue_slots_7_out_uop_lrs2_rtype : _T_168 ? issue_slots_6_out_uop_lrs2_rtype : issue_slots_5_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs1_rtype = _T_169 ? issue_slots_7_out_uop_lrs1_rtype : _T_168 ? issue_slots_6_out_uop_lrs1_rtype : issue_slots_5_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_dst_rtype = _T_169 ? issue_slots_7_out_uop_dst_rtype : _T_168 ? issue_slots_6_out_uop_dst_rtype : issue_slots_5_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs3 = _T_169 ? issue_slots_7_out_uop_lrs3 : _T_168 ? issue_slots_6_out_uop_lrs3 : issue_slots_5_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs2 = _T_169 ? issue_slots_7_out_uop_lrs2 : _T_168 ? issue_slots_6_out_uop_lrs2 : issue_slots_5_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_lrs1 = _T_169 ? issue_slots_7_out_uop_lrs1 : _T_168 ? issue_slots_6_out_uop_lrs1 : issue_slots_5_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ldst = _T_169 ? issue_slots_7_out_uop_ldst : _T_168 ? issue_slots_6_out_uop_ldst : issue_slots_5_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ldst_is_rs1 = _T_169 ? issue_slots_7_out_uop_ldst_is_rs1 : _T_168 ? issue_slots_6_out_uop_ldst_is_rs1 : issue_slots_5_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_csr_cmd = _T_169 ? issue_slots_7_out_uop_csr_cmd : _T_168 ? issue_slots_6_out_uop_csr_cmd : issue_slots_5_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_flush_on_commit = _T_169 ? issue_slots_7_out_uop_flush_on_commit : _T_168 ? issue_slots_6_out_uop_flush_on_commit : issue_slots_5_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_unique = _T_169 ? issue_slots_7_out_uop_is_unique : _T_168 ? issue_slots_6_out_uop_is_unique : issue_slots_5_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_uses_stq = _T_169 ? issue_slots_7_out_uop_uses_stq : _T_168 ? issue_slots_6_out_uop_uses_stq : issue_slots_5_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_uses_ldq = _T_169 ? issue_slots_7_out_uop_uses_ldq : _T_168 ? issue_slots_6_out_uop_uses_ldq : issue_slots_5_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_mem_signed = _T_169 ? issue_slots_7_out_uop_mem_signed : _T_168 ? issue_slots_6_out_uop_mem_signed : issue_slots_5_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_mem_size = _T_169 ? issue_slots_7_out_uop_mem_size : _T_168 ? issue_slots_6_out_uop_mem_size : issue_slots_5_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_mem_cmd = _T_169 ? issue_slots_7_out_uop_mem_cmd : _T_168 ? issue_slots_6_out_uop_mem_cmd : issue_slots_5_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_exc_cause = _T_169 ? issue_slots_7_out_uop_exc_cause : _T_168 ? issue_slots_6_out_uop_exc_cause : issue_slots_5_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_exception = _T_169 ? issue_slots_7_out_uop_exception : _T_168 ? issue_slots_6_out_uop_exception : issue_slots_5_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_stale_pdst = _T_169 ? issue_slots_7_out_uop_stale_pdst : _T_168 ? issue_slots_6_out_uop_stale_pdst : issue_slots_5_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ppred_busy = _T_169 ? issue_slots_7_out_uop_ppred_busy : _T_168 ? issue_slots_6_out_uop_ppred_busy : issue_slots_5_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs3_busy = _T_169 ? issue_slots_7_out_uop_prs3_busy : _T_168 ? issue_slots_6_out_uop_prs3_busy : issue_slots_5_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs2_busy = _T_169 ? issue_slots_7_out_uop_prs2_busy : _T_168 ? issue_slots_6_out_uop_prs2_busy : issue_slots_5_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs1_busy = _T_169 ? issue_slots_7_out_uop_prs1_busy : _T_168 ? issue_slots_6_out_uop_prs1_busy : issue_slots_5_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ppred = _T_169 ? issue_slots_7_out_uop_ppred : _T_168 ? issue_slots_6_out_uop_ppred : issue_slots_5_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs3 = _T_169 ? issue_slots_7_out_uop_prs3 : _T_168 ? issue_slots_6_out_uop_prs3 : issue_slots_5_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs2 = _T_169 ? issue_slots_7_out_uop_prs2 : _T_168 ? issue_slots_6_out_uop_prs2 : issue_slots_5_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_prs1 = _T_169 ? issue_slots_7_out_uop_prs1 : _T_168 ? issue_slots_6_out_uop_prs1 : issue_slots_5_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_pdst = _T_169 ? issue_slots_7_out_uop_pdst : _T_168 ? issue_slots_6_out_uop_pdst : issue_slots_5_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_rxq_idx = _T_169 ? issue_slots_7_out_uop_rxq_idx : _T_168 ? issue_slots_6_out_uop_rxq_idx : issue_slots_5_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_stq_idx = _T_169 ? issue_slots_7_out_uop_stq_idx : _T_168 ? issue_slots_6_out_uop_stq_idx : issue_slots_5_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ldq_idx = _T_169 ? issue_slots_7_out_uop_ldq_idx : _T_168 ? issue_slots_6_out_uop_ldq_idx : issue_slots_5_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_rob_idx = _T_169 ? issue_slots_7_out_uop_rob_idx : _T_168 ? issue_slots_6_out_uop_rob_idx : issue_slots_5_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_vec = _T_169 ? issue_slots_7_out_uop_fp_ctrl_vec : _T_168 ? issue_slots_6_out_uop_fp_ctrl_vec : issue_slots_5_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_wflags = _T_169 ? issue_slots_7_out_uop_fp_ctrl_wflags : _T_168 ? issue_slots_6_out_uop_fp_ctrl_wflags : issue_slots_5_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_sqrt = _T_169 ? issue_slots_7_out_uop_fp_ctrl_sqrt : _T_168 ? issue_slots_6_out_uop_fp_ctrl_sqrt : issue_slots_5_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_div = _T_169 ? issue_slots_7_out_uop_fp_ctrl_div : _T_168 ? issue_slots_6_out_uop_fp_ctrl_div : issue_slots_5_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_fma = _T_169 ? issue_slots_7_out_uop_fp_ctrl_fma : _T_168 ? issue_slots_6_out_uop_fp_ctrl_fma : issue_slots_5_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_fastpipe = _T_169 ? issue_slots_7_out_uop_fp_ctrl_fastpipe : _T_168 ? issue_slots_6_out_uop_fp_ctrl_fastpipe : issue_slots_5_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_toint = _T_169 ? issue_slots_7_out_uop_fp_ctrl_toint : _T_168 ? issue_slots_6_out_uop_fp_ctrl_toint : issue_slots_5_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_fromint = _T_169 ? issue_slots_7_out_uop_fp_ctrl_fromint : _T_168 ? issue_slots_6_out_uop_fp_ctrl_fromint : issue_slots_5_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_typeTagOut = _T_169 ? issue_slots_7_out_uop_fp_ctrl_typeTagOut : _T_168 ? issue_slots_6_out_uop_fp_ctrl_typeTagOut : issue_slots_5_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_typeTagIn = _T_169 ? issue_slots_7_out_uop_fp_ctrl_typeTagIn : _T_168 ? issue_slots_6_out_uop_fp_ctrl_typeTagIn : issue_slots_5_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_swap23 = _T_169 ? issue_slots_7_out_uop_fp_ctrl_swap23 : _T_168 ? issue_slots_6_out_uop_fp_ctrl_swap23 : issue_slots_5_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_swap12 = _T_169 ? issue_slots_7_out_uop_fp_ctrl_swap12 : _T_168 ? issue_slots_6_out_uop_fp_ctrl_swap12 : issue_slots_5_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_ren3 = _T_169 ? issue_slots_7_out_uop_fp_ctrl_ren3 : _T_168 ? issue_slots_6_out_uop_fp_ctrl_ren3 : issue_slots_5_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_ren2 = _T_169 ? issue_slots_7_out_uop_fp_ctrl_ren2 : _T_168 ? issue_slots_6_out_uop_fp_ctrl_ren2 : issue_slots_5_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_ren1 = _T_169 ? issue_slots_7_out_uop_fp_ctrl_ren1 : _T_168 ? issue_slots_6_out_uop_fp_ctrl_ren1 : issue_slots_5_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_wen = _T_169 ? issue_slots_7_out_uop_fp_ctrl_wen : _T_168 ? issue_slots_6_out_uop_fp_ctrl_wen : issue_slots_5_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fp_ctrl_ldst = _T_169 ? issue_slots_7_out_uop_fp_ctrl_ldst : _T_168 ? issue_slots_6_out_uop_fp_ctrl_ldst : issue_slots_5_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_op2_sel = _T_169 ? issue_slots_7_out_uop_op2_sel : _T_168 ? issue_slots_6_out_uop_op2_sel : issue_slots_5_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_op1_sel = _T_169 ? issue_slots_7_out_uop_op1_sel : _T_168 ? issue_slots_6_out_uop_op1_sel : issue_slots_5_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_imm_packed = _T_169 ? issue_slots_7_out_uop_imm_packed : _T_168 ? issue_slots_6_out_uop_imm_packed : issue_slots_5_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_pimm = _T_169 ? issue_slots_7_out_uop_pimm : _T_168 ? issue_slots_6_out_uop_pimm : issue_slots_5_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_imm_sel = _T_169 ? issue_slots_7_out_uop_imm_sel : _T_168 ? issue_slots_6_out_uop_imm_sel : issue_slots_5_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_imm_rename = _T_169 ? issue_slots_7_out_uop_imm_rename : _T_168 ? issue_slots_6_out_uop_imm_rename : issue_slots_5_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_taken = _T_169 ? issue_slots_7_out_uop_taken : _T_168 ? issue_slots_6_out_uop_taken : issue_slots_5_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_pc_lob = _T_169 ? issue_slots_7_out_uop_pc_lob : _T_168 ? issue_slots_6_out_uop_pc_lob : issue_slots_5_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_edge_inst = _T_169 ? issue_slots_7_out_uop_edge_inst : _T_168 ? issue_slots_6_out_uop_edge_inst : issue_slots_5_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_ftq_idx = _T_169 ? issue_slots_7_out_uop_ftq_idx : _T_168 ? issue_slots_6_out_uop_ftq_idx : issue_slots_5_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_mov = _T_169 ? issue_slots_7_out_uop_is_mov : _T_168 ? issue_slots_6_out_uop_is_mov : issue_slots_5_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_rocc = _T_169 ? issue_slots_7_out_uop_is_rocc : _T_168 ? issue_slots_6_out_uop_is_rocc : issue_slots_5_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_sys_pc2epc = _T_169 ? issue_slots_7_out_uop_is_sys_pc2epc : _T_168 ? issue_slots_6_out_uop_is_sys_pc2epc : issue_slots_5_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_eret = _T_169 ? issue_slots_7_out_uop_is_eret : _T_168 ? issue_slots_6_out_uop_is_eret : issue_slots_5_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_amo = _T_169 ? issue_slots_7_out_uop_is_amo : _T_168 ? issue_slots_6_out_uop_is_amo : issue_slots_5_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_sfence = _T_169 ? issue_slots_7_out_uop_is_sfence : _T_168 ? issue_slots_6_out_uop_is_sfence : issue_slots_5_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_fencei = _T_169 ? issue_slots_7_out_uop_is_fencei : _T_168 ? issue_slots_6_out_uop_is_fencei : issue_slots_5_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_fence = _T_169 ? issue_slots_7_out_uop_is_fence : _T_168 ? issue_slots_6_out_uop_is_fence : issue_slots_5_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_sfb = _T_169 ? issue_slots_7_out_uop_is_sfb : _T_168 ? issue_slots_6_out_uop_is_sfb : issue_slots_5_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_br_type = _T_169 ? issue_slots_7_out_uop_br_type : _T_168 ? issue_slots_6_out_uop_br_type : issue_slots_5_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_br_tag = _T_169 ? issue_slots_7_out_uop_br_tag : _T_168 ? issue_slots_6_out_uop_br_tag : issue_slots_5_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_br_mask = _T_169 ? issue_slots_7_out_uop_br_mask : _T_168 ? issue_slots_6_out_uop_br_mask : issue_slots_5_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_dis_col_sel = _T_169 ? issue_slots_7_out_uop_dis_col_sel : _T_168 ? issue_slots_6_out_uop_dis_col_sel : issue_slots_5_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_p3_bypass_hint = _T_169 ? issue_slots_7_out_uop_iw_p3_bypass_hint : _T_168 ? issue_slots_6_out_uop_iw_p3_bypass_hint : issue_slots_5_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_p2_bypass_hint = _T_169 ? issue_slots_7_out_uop_iw_p2_bypass_hint : _T_168 ? issue_slots_6_out_uop_iw_p2_bypass_hint : issue_slots_5_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_p1_bypass_hint = _T_169 ? issue_slots_7_out_uop_iw_p1_bypass_hint : _T_168 ? issue_slots_6_out_uop_iw_p1_bypass_hint : issue_slots_5_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iw_issued = _T_169 ? issue_slots_7_out_uop_iw_issued : _T_168 ? issue_slots_6_out_uop_iw_issued : issue_slots_5_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_0 = _T_169 ? issue_slots_7_out_uop_fu_code_0 : _T_168 ? issue_slots_6_out_uop_fu_code_0 : issue_slots_5_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_1 = _T_169 ? issue_slots_7_out_uop_fu_code_1 : _T_168 ? issue_slots_6_out_uop_fu_code_1 : issue_slots_5_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_2 = _T_169 ? issue_slots_7_out_uop_fu_code_2 : _T_168 ? issue_slots_6_out_uop_fu_code_2 : issue_slots_5_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_3 = _T_169 ? issue_slots_7_out_uop_fu_code_3 : _T_168 ? issue_slots_6_out_uop_fu_code_3 : issue_slots_5_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_4 = _T_169 ? issue_slots_7_out_uop_fu_code_4 : _T_168 ? issue_slots_6_out_uop_fu_code_4 : issue_slots_5_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_5 = _T_169 ? issue_slots_7_out_uop_fu_code_5 : _T_168 ? issue_slots_6_out_uop_fu_code_5 : issue_slots_5_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_6 = _T_169 ? issue_slots_7_out_uop_fu_code_6 : _T_168 ? issue_slots_6_out_uop_fu_code_6 : issue_slots_5_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_7 = _T_169 ? issue_slots_7_out_uop_fu_code_7 : _T_168 ? issue_slots_6_out_uop_fu_code_7 : issue_slots_5_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_8 = _T_169 ? issue_slots_7_out_uop_fu_code_8 : _T_168 ? issue_slots_6_out_uop_fu_code_8 : issue_slots_5_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_fu_code_9 = _T_169 ? issue_slots_7_out_uop_fu_code_9 : _T_168 ? issue_slots_6_out_uop_fu_code_9 : issue_slots_5_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iq_type_0 = _T_169 ? issue_slots_7_out_uop_iq_type_0 : _T_168 ? issue_slots_6_out_uop_iq_type_0 : issue_slots_5_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iq_type_1 = _T_169 ? issue_slots_7_out_uop_iq_type_1 : _T_168 ? issue_slots_6_out_uop_iq_type_1 : issue_slots_5_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iq_type_2 = _T_169 ? issue_slots_7_out_uop_iq_type_2 : _T_168 ? issue_slots_6_out_uop_iq_type_2 : issue_slots_5_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_iq_type_3 = _T_169 ? issue_slots_7_out_uop_iq_type_3 : _T_168 ? issue_slots_6_out_uop_iq_type_3 : issue_slots_5_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_debug_pc = _T_169 ? issue_slots_7_out_uop_debug_pc : _T_168 ? issue_slots_6_out_uop_debug_pc : issue_slots_5_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_is_rvc = _T_169 ? issue_slots_7_out_uop_is_rvc : _T_168 ? issue_slots_6_out_uop_is_rvc : issue_slots_5_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_debug_inst = _T_169 ? issue_slots_7_out_uop_debug_inst : _T_168 ? issue_slots_6_out_uop_debug_inst : issue_slots_5_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_4_in_uop_bits_inst = _T_169 ? issue_slots_7_out_uop_inst : _T_168 ? issue_slots_6_out_uop_inst : issue_slots_5_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_4_clear_T = \|shamts_oh_4; // @[issue-unit-age-ordered.scala:158:23, :199:49] assign issue_slots_4_clear = _issue_slots_4_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_171 = shamts_oh_7 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_172 = shamts_oh_8 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_5_in_uop_valid = _T_172 ? issue_slots_8_will_be_valid : _T_171 ? issue_slots_7_will_be_valid : shamts_oh_6 == 3'h1 & issue_slots_6_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_5_in_uop_bits_debug_tsrc = _T_172 ? issue_slots_8_out_uop_debug_tsrc : _T_171 ? issue_slots_7_out_uop_debug_tsrc : issue_slots_6_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_debug_fsrc = _T_172 ? issue_slots_8_out_uop_debug_fsrc : _T_171 ? issue_slots_7_out_uop_debug_fsrc : issue_slots_6_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_bp_xcpt_if = _T_172 ? issue_slots_8_out_uop_bp_xcpt_if : _T_171 ? issue_slots_7_out_uop_bp_xcpt_if : issue_slots_6_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_bp_debug_if = _T_172 ? issue_slots_8_out_uop_bp_debug_if : _T_171 ? issue_slots_7_out_uop_bp_debug_if : issue_slots_6_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_xcpt_ma_if = _T_172 ? issue_slots_8_out_uop_xcpt_ma_if : _T_171 ? issue_slots_7_out_uop_xcpt_ma_if : issue_slots_6_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_xcpt_ae_if = _T_172 ? issue_slots_8_out_uop_xcpt_ae_if : _T_171 ? issue_slots_7_out_uop_xcpt_ae_if : issue_slots_6_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_xcpt_pf_if = _T_172 ? issue_slots_8_out_uop_xcpt_pf_if : _T_171 ? issue_slots_7_out_uop_xcpt_pf_if : issue_slots_6_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_typ = _T_172 ? issue_slots_8_out_uop_fp_typ : _T_171 ? issue_slots_7_out_uop_fp_typ : issue_slots_6_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_rm = _T_172 ? issue_slots_8_out_uop_fp_rm : _T_171 ? issue_slots_7_out_uop_fp_rm : issue_slots_6_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_val = _T_172 ? issue_slots_8_out_uop_fp_val : _T_171 ? issue_slots_7_out_uop_fp_val : issue_slots_6_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fcn_op = _T_172 ? issue_slots_8_out_uop_fcn_op : _T_171 ? issue_slots_7_out_uop_fcn_op : issue_slots_6_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fcn_dw = _T_172 ? issue_slots_8_out_uop_fcn_dw : _T_171 ? issue_slots_7_out_uop_fcn_dw : issue_slots_6_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_frs3_en = _T_172 ? issue_slots_8_out_uop_frs3_en : _T_171 ? issue_slots_7_out_uop_frs3_en : issue_slots_6_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs2_rtype = _T_172 ? issue_slots_8_out_uop_lrs2_rtype : _T_171 ? issue_slots_7_out_uop_lrs2_rtype : issue_slots_6_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs1_rtype = _T_172 ? issue_slots_8_out_uop_lrs1_rtype : _T_171 ? issue_slots_7_out_uop_lrs1_rtype : issue_slots_6_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_dst_rtype = _T_172 ? issue_slots_8_out_uop_dst_rtype : _T_171 ? issue_slots_7_out_uop_dst_rtype : issue_slots_6_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs3 = _T_172 ? issue_slots_8_out_uop_lrs3 : _T_171 ? issue_slots_7_out_uop_lrs3 : issue_slots_6_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs2 = _T_172 ? issue_slots_8_out_uop_lrs2 : _T_171 ? issue_slots_7_out_uop_lrs2 : issue_slots_6_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_lrs1 = _T_172 ? issue_slots_8_out_uop_lrs1 : _T_171 ? issue_slots_7_out_uop_lrs1 : issue_slots_6_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ldst = _T_172 ? issue_slots_8_out_uop_ldst : _T_171 ? issue_slots_7_out_uop_ldst : issue_slots_6_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ldst_is_rs1 = _T_172 ? issue_slots_8_out_uop_ldst_is_rs1 : _T_171 ? issue_slots_7_out_uop_ldst_is_rs1 : issue_slots_6_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_csr_cmd = _T_172 ? issue_slots_8_out_uop_csr_cmd : _T_171 ? issue_slots_7_out_uop_csr_cmd : issue_slots_6_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_flush_on_commit = _T_172 ? issue_slots_8_out_uop_flush_on_commit : _T_171 ? issue_slots_7_out_uop_flush_on_commit : issue_slots_6_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_unique = _T_172 ? issue_slots_8_out_uop_is_unique : _T_171 ? issue_slots_7_out_uop_is_unique : issue_slots_6_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_uses_stq = _T_172 ? issue_slots_8_out_uop_uses_stq : _T_171 ? issue_slots_7_out_uop_uses_stq : issue_slots_6_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_uses_ldq = _T_172 ? issue_slots_8_out_uop_uses_ldq : _T_171 ? issue_slots_7_out_uop_uses_ldq : issue_slots_6_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_mem_signed = _T_172 ? issue_slots_8_out_uop_mem_signed : _T_171 ? issue_slots_7_out_uop_mem_signed : issue_slots_6_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_mem_size = _T_172 ? issue_slots_8_out_uop_mem_size : _T_171 ? issue_slots_7_out_uop_mem_size : issue_slots_6_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_mem_cmd = _T_172 ? issue_slots_8_out_uop_mem_cmd : _T_171 ? issue_slots_7_out_uop_mem_cmd : issue_slots_6_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_exc_cause = _T_172 ? issue_slots_8_out_uop_exc_cause : _T_171 ? issue_slots_7_out_uop_exc_cause : issue_slots_6_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_exception = _T_172 ? issue_slots_8_out_uop_exception : _T_171 ? issue_slots_7_out_uop_exception : issue_slots_6_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_stale_pdst = _T_172 ? issue_slots_8_out_uop_stale_pdst : _T_171 ? issue_slots_7_out_uop_stale_pdst : issue_slots_6_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ppred_busy = _T_172 ? issue_slots_8_out_uop_ppred_busy : _T_171 ? issue_slots_7_out_uop_ppred_busy : issue_slots_6_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs3_busy = _T_172 ? issue_slots_8_out_uop_prs3_busy : _T_171 ? issue_slots_7_out_uop_prs3_busy : issue_slots_6_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs2_busy = _T_172 ? issue_slots_8_out_uop_prs2_busy : _T_171 ? issue_slots_7_out_uop_prs2_busy : issue_slots_6_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs1_busy = _T_172 ? issue_slots_8_out_uop_prs1_busy : _T_171 ? issue_slots_7_out_uop_prs1_busy : issue_slots_6_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ppred = _T_172 ? issue_slots_8_out_uop_ppred : _T_171 ? issue_slots_7_out_uop_ppred : issue_slots_6_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs3 = _T_172 ? issue_slots_8_out_uop_prs3 : _T_171 ? issue_slots_7_out_uop_prs3 : issue_slots_6_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs2 = _T_172 ? issue_slots_8_out_uop_prs2 : _T_171 ? issue_slots_7_out_uop_prs2 : issue_slots_6_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_prs1 = _T_172 ? issue_slots_8_out_uop_prs1 : _T_171 ? issue_slots_7_out_uop_prs1 : issue_slots_6_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_pdst = _T_172 ? issue_slots_8_out_uop_pdst : _T_171 ? issue_slots_7_out_uop_pdst : issue_slots_6_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_rxq_idx = _T_172 ? issue_slots_8_out_uop_rxq_idx : _T_171 ? issue_slots_7_out_uop_rxq_idx : issue_slots_6_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_stq_idx = _T_172 ? issue_slots_8_out_uop_stq_idx : _T_171 ? issue_slots_7_out_uop_stq_idx : issue_slots_6_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ldq_idx = _T_172 ? issue_slots_8_out_uop_ldq_idx : _T_171 ? issue_slots_7_out_uop_ldq_idx : issue_slots_6_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_rob_idx = _T_172 ? issue_slots_8_out_uop_rob_idx : _T_171 ? issue_slots_7_out_uop_rob_idx : issue_slots_6_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_vec = _T_172 ? issue_slots_8_out_uop_fp_ctrl_vec : _T_171 ? issue_slots_7_out_uop_fp_ctrl_vec : issue_slots_6_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_wflags = _T_172 ? issue_slots_8_out_uop_fp_ctrl_wflags : _T_171 ? issue_slots_7_out_uop_fp_ctrl_wflags : issue_slots_6_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_sqrt = _T_172 ? issue_slots_8_out_uop_fp_ctrl_sqrt : _T_171 ? issue_slots_7_out_uop_fp_ctrl_sqrt : issue_slots_6_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_div = _T_172 ? issue_slots_8_out_uop_fp_ctrl_div : _T_171 ? issue_slots_7_out_uop_fp_ctrl_div : issue_slots_6_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_fma = _T_172 ? issue_slots_8_out_uop_fp_ctrl_fma : _T_171 ? issue_slots_7_out_uop_fp_ctrl_fma : issue_slots_6_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_fastpipe = _T_172 ? issue_slots_8_out_uop_fp_ctrl_fastpipe : _T_171 ? issue_slots_7_out_uop_fp_ctrl_fastpipe : issue_slots_6_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_toint = _T_172 ? issue_slots_8_out_uop_fp_ctrl_toint : _T_171 ? issue_slots_7_out_uop_fp_ctrl_toint : issue_slots_6_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_fromint = _T_172 ? issue_slots_8_out_uop_fp_ctrl_fromint : _T_171 ? issue_slots_7_out_uop_fp_ctrl_fromint : issue_slots_6_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_typeTagOut = _T_172 ? issue_slots_8_out_uop_fp_ctrl_typeTagOut : _T_171 ? issue_slots_7_out_uop_fp_ctrl_typeTagOut : issue_slots_6_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_typeTagIn = _T_172 ? issue_slots_8_out_uop_fp_ctrl_typeTagIn : _T_171 ? issue_slots_7_out_uop_fp_ctrl_typeTagIn : issue_slots_6_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_swap23 = _T_172 ? issue_slots_8_out_uop_fp_ctrl_swap23 : _T_171 ? issue_slots_7_out_uop_fp_ctrl_swap23 : issue_slots_6_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_swap12 = _T_172 ? issue_slots_8_out_uop_fp_ctrl_swap12 : _T_171 ? issue_slots_7_out_uop_fp_ctrl_swap12 : issue_slots_6_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_ren3 = _T_172 ? issue_slots_8_out_uop_fp_ctrl_ren3 : _T_171 ? issue_slots_7_out_uop_fp_ctrl_ren3 : issue_slots_6_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_ren2 = _T_172 ? issue_slots_8_out_uop_fp_ctrl_ren2 : _T_171 ? issue_slots_7_out_uop_fp_ctrl_ren2 : issue_slots_6_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_ren1 = _T_172 ? issue_slots_8_out_uop_fp_ctrl_ren1 : _T_171 ? issue_slots_7_out_uop_fp_ctrl_ren1 : issue_slots_6_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_wen = _T_172 ? issue_slots_8_out_uop_fp_ctrl_wen : _T_171 ? issue_slots_7_out_uop_fp_ctrl_wen : issue_slots_6_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fp_ctrl_ldst = _T_172 ? issue_slots_8_out_uop_fp_ctrl_ldst : _T_171 ? issue_slots_7_out_uop_fp_ctrl_ldst : issue_slots_6_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_op2_sel = _T_172 ? issue_slots_8_out_uop_op2_sel : _T_171 ? issue_slots_7_out_uop_op2_sel : issue_slots_6_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_op1_sel = _T_172 ? issue_slots_8_out_uop_op1_sel : _T_171 ? issue_slots_7_out_uop_op1_sel : issue_slots_6_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_imm_packed = _T_172 ? issue_slots_8_out_uop_imm_packed : _T_171 ? issue_slots_7_out_uop_imm_packed : issue_slots_6_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_pimm = _T_172 ? issue_slots_8_out_uop_pimm : _T_171 ? issue_slots_7_out_uop_pimm : issue_slots_6_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_imm_sel = _T_172 ? issue_slots_8_out_uop_imm_sel : _T_171 ? issue_slots_7_out_uop_imm_sel : issue_slots_6_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_imm_rename = _T_172 ? issue_slots_8_out_uop_imm_rename : _T_171 ? issue_slots_7_out_uop_imm_rename : issue_slots_6_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_taken = _T_172 ? issue_slots_8_out_uop_taken : _T_171 ? issue_slots_7_out_uop_taken : issue_slots_6_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_pc_lob = _T_172 ? issue_slots_8_out_uop_pc_lob : _T_171 ? issue_slots_7_out_uop_pc_lob : issue_slots_6_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_edge_inst = _T_172 ? issue_slots_8_out_uop_edge_inst : _T_171 ? issue_slots_7_out_uop_edge_inst : issue_slots_6_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_ftq_idx = _T_172 ? issue_slots_8_out_uop_ftq_idx : _T_171 ? issue_slots_7_out_uop_ftq_idx : issue_slots_6_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_mov = _T_172 ? issue_slots_8_out_uop_is_mov : _T_171 ? issue_slots_7_out_uop_is_mov : issue_slots_6_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_rocc = _T_172 ? issue_slots_8_out_uop_is_rocc : _T_171 ? issue_slots_7_out_uop_is_rocc : issue_slots_6_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_sys_pc2epc = _T_172 ? issue_slots_8_out_uop_is_sys_pc2epc : _T_171 ? issue_slots_7_out_uop_is_sys_pc2epc : issue_slots_6_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_eret = _T_172 ? issue_slots_8_out_uop_is_eret : _T_171 ? issue_slots_7_out_uop_is_eret : issue_slots_6_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_amo = _T_172 ? issue_slots_8_out_uop_is_amo : _T_171 ? issue_slots_7_out_uop_is_amo : issue_slots_6_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_sfence = _T_172 ? issue_slots_8_out_uop_is_sfence : _T_171 ? issue_slots_7_out_uop_is_sfence : issue_slots_6_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_fencei = _T_172 ? issue_slots_8_out_uop_is_fencei : _T_171 ? issue_slots_7_out_uop_is_fencei : issue_slots_6_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_fence = _T_172 ? issue_slots_8_out_uop_is_fence : _T_171 ? issue_slots_7_out_uop_is_fence : issue_slots_6_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_sfb = _T_172 ? issue_slots_8_out_uop_is_sfb : _T_171 ? issue_slots_7_out_uop_is_sfb : issue_slots_6_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_br_type = _T_172 ? issue_slots_8_out_uop_br_type : _T_171 ? issue_slots_7_out_uop_br_type : issue_slots_6_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_br_tag = _T_172 ? issue_slots_8_out_uop_br_tag : _T_171 ? issue_slots_7_out_uop_br_tag : issue_slots_6_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_br_mask = _T_172 ? issue_slots_8_out_uop_br_mask : _T_171 ? issue_slots_7_out_uop_br_mask : issue_slots_6_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_dis_col_sel = _T_172 ? issue_slots_8_out_uop_dis_col_sel : _T_171 ? issue_slots_7_out_uop_dis_col_sel : issue_slots_6_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_p3_bypass_hint = _T_172 ? issue_slots_8_out_uop_iw_p3_bypass_hint : _T_171 ? issue_slots_7_out_uop_iw_p3_bypass_hint : issue_slots_6_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_p2_bypass_hint = _T_172 ? issue_slots_8_out_uop_iw_p2_bypass_hint : _T_171 ? issue_slots_7_out_uop_iw_p2_bypass_hint : issue_slots_6_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_p1_bypass_hint = _T_172 ? issue_slots_8_out_uop_iw_p1_bypass_hint : _T_171 ? issue_slots_7_out_uop_iw_p1_bypass_hint : issue_slots_6_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iw_issued = _T_172 ? issue_slots_8_out_uop_iw_issued : _T_171 ? issue_slots_7_out_uop_iw_issued : issue_slots_6_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_0 = _T_172 ? issue_slots_8_out_uop_fu_code_0 : _T_171 ? issue_slots_7_out_uop_fu_code_0 : issue_slots_6_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_1 = _T_172 ? issue_slots_8_out_uop_fu_code_1 : _T_171 ? issue_slots_7_out_uop_fu_code_1 : issue_slots_6_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_2 = _T_172 ? issue_slots_8_out_uop_fu_code_2 : _T_171 ? issue_slots_7_out_uop_fu_code_2 : issue_slots_6_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_3 = _T_172 ? issue_slots_8_out_uop_fu_code_3 : _T_171 ? issue_slots_7_out_uop_fu_code_3 : issue_slots_6_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_4 = _T_172 ? issue_slots_8_out_uop_fu_code_4 : _T_171 ? issue_slots_7_out_uop_fu_code_4 : issue_slots_6_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_5 = _T_172 ? issue_slots_8_out_uop_fu_code_5 : _T_171 ? issue_slots_7_out_uop_fu_code_5 : issue_slots_6_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_6 = _T_172 ? issue_slots_8_out_uop_fu_code_6 : _T_171 ? issue_slots_7_out_uop_fu_code_6 : issue_slots_6_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_7 = _T_172 ? issue_slots_8_out_uop_fu_code_7 : _T_171 ? issue_slots_7_out_uop_fu_code_7 : issue_slots_6_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_8 = _T_172 ? issue_slots_8_out_uop_fu_code_8 : _T_171 ? issue_slots_7_out_uop_fu_code_8 : issue_slots_6_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_fu_code_9 = _T_172 ? issue_slots_8_out_uop_fu_code_9 : _T_171 ? issue_slots_7_out_uop_fu_code_9 : issue_slots_6_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iq_type_0 = _T_172 ? issue_slots_8_out_uop_iq_type_0 : _T_171 ? issue_slots_7_out_uop_iq_type_0 : issue_slots_6_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iq_type_1 = _T_172 ? issue_slots_8_out_uop_iq_type_1 : _T_171 ? issue_slots_7_out_uop_iq_type_1 : issue_slots_6_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iq_type_2 = _T_172 ? issue_slots_8_out_uop_iq_type_2 : _T_171 ? issue_slots_7_out_uop_iq_type_2 : issue_slots_6_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_iq_type_3 = _T_172 ? issue_slots_8_out_uop_iq_type_3 : _T_171 ? issue_slots_7_out_uop_iq_type_3 : issue_slots_6_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_debug_pc = _T_172 ? issue_slots_8_out_uop_debug_pc : _T_171 ? issue_slots_7_out_uop_debug_pc : issue_slots_6_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_is_rvc = _T_172 ? issue_slots_8_out_uop_is_rvc : _T_171 ? issue_slots_7_out_uop_is_rvc : issue_slots_6_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_debug_inst = _T_172 ? issue_slots_8_out_uop_debug_inst : _T_171 ? issue_slots_7_out_uop_debug_inst : issue_slots_6_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_5_in_uop_bits_inst = _T_172 ? issue_slots_8_out_uop_inst : _T_171 ? issue_slots_7_out_uop_inst : issue_slots_6_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_5_clear_T = \|shamts_oh_5; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_5_clear = _issue_slots_5_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_174 = shamts_oh_8 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_175 = shamts_oh_9 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_6_in_uop_valid = _T_175 ? issue_slots_9_will_be_valid : _T_174 ? issue_slots_8_will_be_valid : shamts_oh_7 == 3'h1 & issue_slots_7_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_6_in_uop_bits_debug_tsrc = _T_175 ? issue_slots_9_out_uop_debug_tsrc : _T_174 ? issue_slots_8_out_uop_debug_tsrc : issue_slots_7_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_debug_fsrc = _T_175 ? issue_slots_9_out_uop_debug_fsrc : _T_174 ? issue_slots_8_out_uop_debug_fsrc : issue_slots_7_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_bp_xcpt_if = _T_175 ? issue_slots_9_out_uop_bp_xcpt_if : _T_174 ? issue_slots_8_out_uop_bp_xcpt_if : issue_slots_7_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_bp_debug_if = _T_175 ? issue_slots_9_out_uop_bp_debug_if : _T_174 ? issue_slots_8_out_uop_bp_debug_if : issue_slots_7_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_xcpt_ma_if = _T_175 ? issue_slots_9_out_uop_xcpt_ma_if : _T_174 ? issue_slots_8_out_uop_xcpt_ma_if : issue_slots_7_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_xcpt_ae_if = _T_175 ? issue_slots_9_out_uop_xcpt_ae_if : _T_174 ? issue_slots_8_out_uop_xcpt_ae_if : issue_slots_7_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_xcpt_pf_if = _T_175 ? issue_slots_9_out_uop_xcpt_pf_if : _T_174 ? issue_slots_8_out_uop_xcpt_pf_if : issue_slots_7_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_typ = _T_175 ? issue_slots_9_out_uop_fp_typ : _T_174 ? issue_slots_8_out_uop_fp_typ : issue_slots_7_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_rm = _T_175 ? issue_slots_9_out_uop_fp_rm : _T_174 ? issue_slots_8_out_uop_fp_rm : issue_slots_7_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_val = _T_175 ? issue_slots_9_out_uop_fp_val : _T_174 ? issue_slots_8_out_uop_fp_val : issue_slots_7_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fcn_op = _T_175 ? issue_slots_9_out_uop_fcn_op : _T_174 ? issue_slots_8_out_uop_fcn_op : issue_slots_7_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fcn_dw = _T_175 ? issue_slots_9_out_uop_fcn_dw : _T_174 ? issue_slots_8_out_uop_fcn_dw : issue_slots_7_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_frs3_en = _T_175 ? issue_slots_9_out_uop_frs3_en : _T_174 ? issue_slots_8_out_uop_frs3_en : issue_slots_7_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs2_rtype = _T_175 ? issue_slots_9_out_uop_lrs2_rtype : _T_174 ? issue_slots_8_out_uop_lrs2_rtype : issue_slots_7_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs1_rtype = _T_175 ? issue_slots_9_out_uop_lrs1_rtype : _T_174 ? issue_slots_8_out_uop_lrs1_rtype : issue_slots_7_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_dst_rtype = _T_175 ? issue_slots_9_out_uop_dst_rtype : _T_174 ? issue_slots_8_out_uop_dst_rtype : issue_slots_7_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs3 = _T_175 ? issue_slots_9_out_uop_lrs3 : _T_174 ? issue_slots_8_out_uop_lrs3 : issue_slots_7_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs2 = _T_175 ? issue_slots_9_out_uop_lrs2 : _T_174 ? issue_slots_8_out_uop_lrs2 : issue_slots_7_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_lrs1 = _T_175 ? issue_slots_9_out_uop_lrs1 : _T_174 ? issue_slots_8_out_uop_lrs1 : issue_slots_7_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ldst = _T_175 ? issue_slots_9_out_uop_ldst : _T_174 ? issue_slots_8_out_uop_ldst : issue_slots_7_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ldst_is_rs1 = _T_175 ? issue_slots_9_out_uop_ldst_is_rs1 : _T_174 ? issue_slots_8_out_uop_ldst_is_rs1 : issue_slots_7_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_csr_cmd = _T_175 ? issue_slots_9_out_uop_csr_cmd : _T_174 ? issue_slots_8_out_uop_csr_cmd : issue_slots_7_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_flush_on_commit = _T_175 ? issue_slots_9_out_uop_flush_on_commit : _T_174 ? issue_slots_8_out_uop_flush_on_commit : issue_slots_7_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_unique = _T_175 ? issue_slots_9_out_uop_is_unique : _T_174 ? issue_slots_8_out_uop_is_unique : issue_slots_7_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_uses_stq = _T_175 ? issue_slots_9_out_uop_uses_stq : _T_174 ? issue_slots_8_out_uop_uses_stq : issue_slots_7_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_uses_ldq = _T_175 ? issue_slots_9_out_uop_uses_ldq : _T_174 ? issue_slots_8_out_uop_uses_ldq : issue_slots_7_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_mem_signed = _T_175 ? issue_slots_9_out_uop_mem_signed : _T_174 ? issue_slots_8_out_uop_mem_signed : issue_slots_7_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_mem_size = _T_175 ? issue_slots_9_out_uop_mem_size : _T_174 ? issue_slots_8_out_uop_mem_size : issue_slots_7_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_mem_cmd = _T_175 ? issue_slots_9_out_uop_mem_cmd : _T_174 ? issue_slots_8_out_uop_mem_cmd : issue_slots_7_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_exc_cause = _T_175 ? issue_slots_9_out_uop_exc_cause : _T_174 ? issue_slots_8_out_uop_exc_cause : issue_slots_7_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_exception = _T_175 ? issue_slots_9_out_uop_exception : _T_174 ? issue_slots_8_out_uop_exception : issue_slots_7_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_stale_pdst = _T_175 ? issue_slots_9_out_uop_stale_pdst : _T_174 ? issue_slots_8_out_uop_stale_pdst : issue_slots_7_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ppred_busy = _T_175 ? issue_slots_9_out_uop_ppred_busy : _T_174 ? issue_slots_8_out_uop_ppred_busy : issue_slots_7_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs3_busy = _T_175 ? issue_slots_9_out_uop_prs3_busy : _T_174 ? issue_slots_8_out_uop_prs3_busy : issue_slots_7_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs2_busy = _T_175 ? issue_slots_9_out_uop_prs2_busy : _T_174 ? issue_slots_8_out_uop_prs2_busy : issue_slots_7_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs1_busy = _T_175 ? issue_slots_9_out_uop_prs1_busy : _T_174 ? issue_slots_8_out_uop_prs1_busy : issue_slots_7_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ppred = _T_175 ? issue_slots_9_out_uop_ppred : _T_174 ? issue_slots_8_out_uop_ppred : issue_slots_7_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs3 = _T_175 ? issue_slots_9_out_uop_prs3 : _T_174 ? issue_slots_8_out_uop_prs3 : issue_slots_7_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs2 = _T_175 ? issue_slots_9_out_uop_prs2 : _T_174 ? issue_slots_8_out_uop_prs2 : issue_slots_7_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_prs1 = _T_175 ? issue_slots_9_out_uop_prs1 : _T_174 ? issue_slots_8_out_uop_prs1 : issue_slots_7_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_pdst = _T_175 ? issue_slots_9_out_uop_pdst : _T_174 ? issue_slots_8_out_uop_pdst : issue_slots_7_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_rxq_idx = _T_175 ? issue_slots_9_out_uop_rxq_idx : _T_174 ? issue_slots_8_out_uop_rxq_idx : issue_slots_7_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_stq_idx = _T_175 ? issue_slots_9_out_uop_stq_idx : _T_174 ? issue_slots_8_out_uop_stq_idx : issue_slots_7_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ldq_idx = _T_175 ? issue_slots_9_out_uop_ldq_idx : _T_174 ? issue_slots_8_out_uop_ldq_idx : issue_slots_7_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_rob_idx = _T_175 ? issue_slots_9_out_uop_rob_idx : _T_174 ? issue_slots_8_out_uop_rob_idx : issue_slots_7_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_vec = _T_175 ? issue_slots_9_out_uop_fp_ctrl_vec : _T_174 ? issue_slots_8_out_uop_fp_ctrl_vec : issue_slots_7_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_wflags = _T_175 ? issue_slots_9_out_uop_fp_ctrl_wflags : _T_174 ? issue_slots_8_out_uop_fp_ctrl_wflags : issue_slots_7_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_sqrt = _T_175 ? issue_slots_9_out_uop_fp_ctrl_sqrt : _T_174 ? issue_slots_8_out_uop_fp_ctrl_sqrt : issue_slots_7_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_div = _T_175 ? issue_slots_9_out_uop_fp_ctrl_div : _T_174 ? issue_slots_8_out_uop_fp_ctrl_div : issue_slots_7_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_fma = _T_175 ? issue_slots_9_out_uop_fp_ctrl_fma : _T_174 ? issue_slots_8_out_uop_fp_ctrl_fma : issue_slots_7_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_fastpipe = _T_175 ? issue_slots_9_out_uop_fp_ctrl_fastpipe : _T_174 ? issue_slots_8_out_uop_fp_ctrl_fastpipe : issue_slots_7_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_toint = _T_175 ? issue_slots_9_out_uop_fp_ctrl_toint : _T_174 ? issue_slots_8_out_uop_fp_ctrl_toint : issue_slots_7_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_fromint = _T_175 ? issue_slots_9_out_uop_fp_ctrl_fromint : _T_174 ? issue_slots_8_out_uop_fp_ctrl_fromint : issue_slots_7_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_typeTagOut = _T_175 ? issue_slots_9_out_uop_fp_ctrl_typeTagOut : _T_174 ? issue_slots_8_out_uop_fp_ctrl_typeTagOut : issue_slots_7_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_typeTagIn = _T_175 ? issue_slots_9_out_uop_fp_ctrl_typeTagIn : _T_174 ? issue_slots_8_out_uop_fp_ctrl_typeTagIn : issue_slots_7_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_swap23 = _T_175 ? issue_slots_9_out_uop_fp_ctrl_swap23 : _T_174 ? issue_slots_8_out_uop_fp_ctrl_swap23 : issue_slots_7_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_swap12 = _T_175 ? issue_slots_9_out_uop_fp_ctrl_swap12 : _T_174 ? issue_slots_8_out_uop_fp_ctrl_swap12 : issue_slots_7_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_ren3 = _T_175 ? issue_slots_9_out_uop_fp_ctrl_ren3 : _T_174 ? issue_slots_8_out_uop_fp_ctrl_ren3 : issue_slots_7_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_ren2 = _T_175 ? issue_slots_9_out_uop_fp_ctrl_ren2 : _T_174 ? issue_slots_8_out_uop_fp_ctrl_ren2 : issue_slots_7_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_ren1 = _T_175 ? issue_slots_9_out_uop_fp_ctrl_ren1 : _T_174 ? issue_slots_8_out_uop_fp_ctrl_ren1 : issue_slots_7_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_wen = _T_175 ? issue_slots_9_out_uop_fp_ctrl_wen : _T_174 ? issue_slots_8_out_uop_fp_ctrl_wen : issue_slots_7_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fp_ctrl_ldst = _T_175 ? issue_slots_9_out_uop_fp_ctrl_ldst : _T_174 ? issue_slots_8_out_uop_fp_ctrl_ldst : issue_slots_7_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_op2_sel = _T_175 ? issue_slots_9_out_uop_op2_sel : _T_174 ? issue_slots_8_out_uop_op2_sel : issue_slots_7_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_op1_sel = _T_175 ? issue_slots_9_out_uop_op1_sel : _T_174 ? issue_slots_8_out_uop_op1_sel : issue_slots_7_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_imm_packed = _T_175 ? issue_slots_9_out_uop_imm_packed : _T_174 ? issue_slots_8_out_uop_imm_packed : issue_slots_7_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_pimm = _T_175 ? issue_slots_9_out_uop_pimm : _T_174 ? issue_slots_8_out_uop_pimm : issue_slots_7_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_imm_sel = _T_175 ? issue_slots_9_out_uop_imm_sel : _T_174 ? issue_slots_8_out_uop_imm_sel : issue_slots_7_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_imm_rename = _T_175 ? issue_slots_9_out_uop_imm_rename : _T_174 ? issue_slots_8_out_uop_imm_rename : issue_slots_7_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_taken = _T_175 ? issue_slots_9_out_uop_taken : _T_174 ? issue_slots_8_out_uop_taken : issue_slots_7_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_pc_lob = _T_175 ? issue_slots_9_out_uop_pc_lob : _T_174 ? issue_slots_8_out_uop_pc_lob : issue_slots_7_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_edge_inst = _T_175 ? issue_slots_9_out_uop_edge_inst : _T_174 ? issue_slots_8_out_uop_edge_inst : issue_slots_7_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_ftq_idx = _T_175 ? issue_slots_9_out_uop_ftq_idx : _T_174 ? issue_slots_8_out_uop_ftq_idx : issue_slots_7_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_mov = _T_175 ? issue_slots_9_out_uop_is_mov : _T_174 ? issue_slots_8_out_uop_is_mov : issue_slots_7_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_rocc = _T_175 ? issue_slots_9_out_uop_is_rocc : _T_174 ? issue_slots_8_out_uop_is_rocc : issue_slots_7_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_sys_pc2epc = _T_175 ? issue_slots_9_out_uop_is_sys_pc2epc : _T_174 ? issue_slots_8_out_uop_is_sys_pc2epc : issue_slots_7_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_eret = _T_175 ? issue_slots_9_out_uop_is_eret : _T_174 ? issue_slots_8_out_uop_is_eret : issue_slots_7_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_amo = _T_175 ? issue_slots_9_out_uop_is_amo : _T_174 ? issue_slots_8_out_uop_is_amo : issue_slots_7_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_sfence = _T_175 ? issue_slots_9_out_uop_is_sfence : _T_174 ? issue_slots_8_out_uop_is_sfence : issue_slots_7_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_fencei = _T_175 ? issue_slots_9_out_uop_is_fencei : _T_174 ? issue_slots_8_out_uop_is_fencei : issue_slots_7_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_fence = _T_175 ? issue_slots_9_out_uop_is_fence : _T_174 ? issue_slots_8_out_uop_is_fence : issue_slots_7_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_sfb = _T_175 ? issue_slots_9_out_uop_is_sfb : _T_174 ? issue_slots_8_out_uop_is_sfb : issue_slots_7_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_br_type = _T_175 ? issue_slots_9_out_uop_br_type : _T_174 ? issue_slots_8_out_uop_br_type : issue_slots_7_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_br_tag = _T_175 ? issue_slots_9_out_uop_br_tag : _T_174 ? issue_slots_8_out_uop_br_tag : issue_slots_7_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_br_mask = _T_175 ? issue_slots_9_out_uop_br_mask : _T_174 ? issue_slots_8_out_uop_br_mask : issue_slots_7_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_dis_col_sel = _T_175 ? issue_slots_9_out_uop_dis_col_sel : _T_174 ? issue_slots_8_out_uop_dis_col_sel : issue_slots_7_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_p3_bypass_hint = _T_175 ? issue_slots_9_out_uop_iw_p3_bypass_hint : _T_174 ? issue_slots_8_out_uop_iw_p3_bypass_hint : issue_slots_7_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_p2_bypass_hint = _T_175 ? issue_slots_9_out_uop_iw_p2_bypass_hint : _T_174 ? issue_slots_8_out_uop_iw_p2_bypass_hint : issue_slots_7_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_p1_bypass_hint = _T_175 ? issue_slots_9_out_uop_iw_p1_bypass_hint : _T_174 ? issue_slots_8_out_uop_iw_p1_bypass_hint : issue_slots_7_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iw_issued = _T_175 ? issue_slots_9_out_uop_iw_issued : _T_174 ? issue_slots_8_out_uop_iw_issued : issue_slots_7_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_0 = _T_175 ? issue_slots_9_out_uop_fu_code_0 : _T_174 ? issue_slots_8_out_uop_fu_code_0 : issue_slots_7_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_1 = _T_175 ? issue_slots_9_out_uop_fu_code_1 : _T_174 ? issue_slots_8_out_uop_fu_code_1 : issue_slots_7_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_2 = _T_175 ? issue_slots_9_out_uop_fu_code_2 : _T_174 ? issue_slots_8_out_uop_fu_code_2 : issue_slots_7_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_3 = _T_175 ? issue_slots_9_out_uop_fu_code_3 : _T_174 ? issue_slots_8_out_uop_fu_code_3 : issue_slots_7_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_4 = _T_175 ? issue_slots_9_out_uop_fu_code_4 : _T_174 ? issue_slots_8_out_uop_fu_code_4 : issue_slots_7_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_5 = _T_175 ? issue_slots_9_out_uop_fu_code_5 : _T_174 ? issue_slots_8_out_uop_fu_code_5 : issue_slots_7_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_6 = _T_175 ? issue_slots_9_out_uop_fu_code_6 : _T_174 ? issue_slots_8_out_uop_fu_code_6 : issue_slots_7_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_7 = _T_175 ? issue_slots_9_out_uop_fu_code_7 : _T_174 ? issue_slots_8_out_uop_fu_code_7 : issue_slots_7_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_8 = _T_175 ? issue_slots_9_out_uop_fu_code_8 : _T_174 ? issue_slots_8_out_uop_fu_code_8 : issue_slots_7_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_fu_code_9 = _T_175 ? issue_slots_9_out_uop_fu_code_9 : _T_174 ? issue_slots_8_out_uop_fu_code_9 : issue_slots_7_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iq_type_0 = _T_175 ? issue_slots_9_out_uop_iq_type_0 : _T_174 ? issue_slots_8_out_uop_iq_type_0 : issue_slots_7_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iq_type_1 = _T_175 ? issue_slots_9_out_uop_iq_type_1 : _T_174 ? issue_slots_8_out_uop_iq_type_1 : issue_slots_7_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iq_type_2 = _T_175 ? issue_slots_9_out_uop_iq_type_2 : _T_174 ? issue_slots_8_out_uop_iq_type_2 : issue_slots_7_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_iq_type_3 = _T_175 ? issue_slots_9_out_uop_iq_type_3 : _T_174 ? issue_slots_8_out_uop_iq_type_3 : issue_slots_7_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_debug_pc = _T_175 ? issue_slots_9_out_uop_debug_pc : _T_174 ? issue_slots_8_out_uop_debug_pc : issue_slots_7_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_is_rvc = _T_175 ? issue_slots_9_out_uop_is_rvc : _T_174 ? issue_slots_8_out_uop_is_rvc : issue_slots_7_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_debug_inst = _T_175 ? issue_slots_9_out_uop_debug_inst : _T_174 ? issue_slots_8_out_uop_debug_inst : issue_slots_7_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_6_in_uop_bits_inst = _T_175 ? issue_slots_9_out_uop_inst : _T_174 ? issue_slots_8_out_uop_inst : issue_slots_7_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_6_clear_T = \|shamts_oh_6; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_6_clear = _issue_slots_6_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_177 = shamts_oh_9 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_178 = shamts_oh_10 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_7_in_uop_valid = _T_178 ? issue_slots_10_will_be_valid : _T_177 ? issue_slots_9_will_be_valid : shamts_oh_8 == 3'h1 & issue_slots_8_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_7_in_uop_bits_debug_tsrc = _T_178 ? issue_slots_10_out_uop_debug_tsrc : _T_177 ? issue_slots_9_out_uop_debug_tsrc : issue_slots_8_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_debug_fsrc = _T_178 ? issue_slots_10_out_uop_debug_fsrc : _T_177 ? issue_slots_9_out_uop_debug_fsrc : issue_slots_8_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_bp_xcpt_if = _T_178 ? issue_slots_10_out_uop_bp_xcpt_if : _T_177 ? issue_slots_9_out_uop_bp_xcpt_if : issue_slots_8_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_bp_debug_if = _T_178 ? issue_slots_10_out_uop_bp_debug_if : _T_177 ? issue_slots_9_out_uop_bp_debug_if : issue_slots_8_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_xcpt_ma_if = _T_178 ? issue_slots_10_out_uop_xcpt_ma_if : _T_177 ? issue_slots_9_out_uop_xcpt_ma_if : issue_slots_8_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_xcpt_ae_if = _T_178 ? issue_slots_10_out_uop_xcpt_ae_if : _T_177 ? issue_slots_9_out_uop_xcpt_ae_if : issue_slots_8_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_xcpt_pf_if = _T_178 ? issue_slots_10_out_uop_xcpt_pf_if : _T_177 ? issue_slots_9_out_uop_xcpt_pf_if : issue_slots_8_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_typ = _T_178 ? issue_slots_10_out_uop_fp_typ : _T_177 ? issue_slots_9_out_uop_fp_typ : issue_slots_8_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_rm = _T_178 ? issue_slots_10_out_uop_fp_rm : _T_177 ? issue_slots_9_out_uop_fp_rm : issue_slots_8_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_val = _T_178 ? issue_slots_10_out_uop_fp_val : _T_177 ? issue_slots_9_out_uop_fp_val : issue_slots_8_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fcn_op = _T_178 ? issue_slots_10_out_uop_fcn_op : _T_177 ? issue_slots_9_out_uop_fcn_op : issue_slots_8_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fcn_dw = _T_178 ? issue_slots_10_out_uop_fcn_dw : _T_177 ? issue_slots_9_out_uop_fcn_dw : issue_slots_8_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_frs3_en = _T_178 ? issue_slots_10_out_uop_frs3_en : _T_177 ? issue_slots_9_out_uop_frs3_en : issue_slots_8_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs2_rtype = _T_178 ? issue_slots_10_out_uop_lrs2_rtype : _T_177 ? issue_slots_9_out_uop_lrs2_rtype : issue_slots_8_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs1_rtype = _T_178 ? issue_slots_10_out_uop_lrs1_rtype : _T_177 ? issue_slots_9_out_uop_lrs1_rtype : issue_slots_8_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_dst_rtype = _T_178 ? issue_slots_10_out_uop_dst_rtype : _T_177 ? issue_slots_9_out_uop_dst_rtype : issue_slots_8_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs3 = _T_178 ? issue_slots_10_out_uop_lrs3 : _T_177 ? issue_slots_9_out_uop_lrs3 : issue_slots_8_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs2 = _T_178 ? issue_slots_10_out_uop_lrs2 : _T_177 ? issue_slots_9_out_uop_lrs2 : issue_slots_8_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_lrs1 = _T_178 ? issue_slots_10_out_uop_lrs1 : _T_177 ? issue_slots_9_out_uop_lrs1 : issue_slots_8_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ldst = _T_178 ? issue_slots_10_out_uop_ldst : _T_177 ? issue_slots_9_out_uop_ldst : issue_slots_8_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ldst_is_rs1 = _T_178 ? issue_slots_10_out_uop_ldst_is_rs1 : _T_177 ? issue_slots_9_out_uop_ldst_is_rs1 : issue_slots_8_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_csr_cmd = _T_178 ? issue_slots_10_out_uop_csr_cmd : _T_177 ? issue_slots_9_out_uop_csr_cmd : issue_slots_8_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_flush_on_commit = _T_178 ? issue_slots_10_out_uop_flush_on_commit : _T_177 ? issue_slots_9_out_uop_flush_on_commit : issue_slots_8_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_unique = _T_178 ? issue_slots_10_out_uop_is_unique : _T_177 ? issue_slots_9_out_uop_is_unique : issue_slots_8_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_uses_stq = _T_178 ? issue_slots_10_out_uop_uses_stq : _T_177 ? issue_slots_9_out_uop_uses_stq : issue_slots_8_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_uses_ldq = _T_178 ? issue_slots_10_out_uop_uses_ldq : _T_177 ? issue_slots_9_out_uop_uses_ldq : issue_slots_8_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_mem_signed = _T_178 ? issue_slots_10_out_uop_mem_signed : _T_177 ? issue_slots_9_out_uop_mem_signed : issue_slots_8_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_mem_size = _T_178 ? issue_slots_10_out_uop_mem_size : _T_177 ? issue_slots_9_out_uop_mem_size : issue_slots_8_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_mem_cmd = _T_178 ? issue_slots_10_out_uop_mem_cmd : _T_177 ? issue_slots_9_out_uop_mem_cmd : issue_slots_8_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_exc_cause = _T_178 ? issue_slots_10_out_uop_exc_cause : _T_177 ? issue_slots_9_out_uop_exc_cause : issue_slots_8_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_exception = _T_178 ? issue_slots_10_out_uop_exception : _T_177 ? issue_slots_9_out_uop_exception : issue_slots_8_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_stale_pdst = _T_178 ? issue_slots_10_out_uop_stale_pdst : _T_177 ? issue_slots_9_out_uop_stale_pdst : issue_slots_8_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ppred_busy = _T_178 ? issue_slots_10_out_uop_ppred_busy : _T_177 ? issue_slots_9_out_uop_ppred_busy : issue_slots_8_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs3_busy = _T_178 ? issue_slots_10_out_uop_prs3_busy : _T_177 ? issue_slots_9_out_uop_prs3_busy : issue_slots_8_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs2_busy = _T_178 ? issue_slots_10_out_uop_prs2_busy : _T_177 ? issue_slots_9_out_uop_prs2_busy : issue_slots_8_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs1_busy = _T_178 ? issue_slots_10_out_uop_prs1_busy : _T_177 ? issue_slots_9_out_uop_prs1_busy : issue_slots_8_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ppred = _T_178 ? issue_slots_10_out_uop_ppred : _T_177 ? issue_slots_9_out_uop_ppred : issue_slots_8_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs3 = _T_178 ? issue_slots_10_out_uop_prs3 : _T_177 ? issue_slots_9_out_uop_prs3 : issue_slots_8_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs2 = _T_178 ? issue_slots_10_out_uop_prs2 : _T_177 ? issue_slots_9_out_uop_prs2 : issue_slots_8_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_prs1 = _T_178 ? issue_slots_10_out_uop_prs1 : _T_177 ? issue_slots_9_out_uop_prs1 : issue_slots_8_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_pdst = _T_178 ? issue_slots_10_out_uop_pdst : _T_177 ? issue_slots_9_out_uop_pdst : issue_slots_8_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_rxq_idx = _T_178 ? issue_slots_10_out_uop_rxq_idx : _T_177 ? issue_slots_9_out_uop_rxq_idx : issue_slots_8_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_stq_idx = _T_178 ? issue_slots_10_out_uop_stq_idx : _T_177 ? issue_slots_9_out_uop_stq_idx : issue_slots_8_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ldq_idx = _T_178 ? issue_slots_10_out_uop_ldq_idx : _T_177 ? issue_slots_9_out_uop_ldq_idx : issue_slots_8_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_rob_idx = _T_178 ? issue_slots_10_out_uop_rob_idx : _T_177 ? issue_slots_9_out_uop_rob_idx : issue_slots_8_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_vec = _T_178 ? issue_slots_10_out_uop_fp_ctrl_vec : _T_177 ? issue_slots_9_out_uop_fp_ctrl_vec : issue_slots_8_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_wflags = _T_178 ? issue_slots_10_out_uop_fp_ctrl_wflags : _T_177 ? issue_slots_9_out_uop_fp_ctrl_wflags : issue_slots_8_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_sqrt = _T_178 ? issue_slots_10_out_uop_fp_ctrl_sqrt : _T_177 ? issue_slots_9_out_uop_fp_ctrl_sqrt : issue_slots_8_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_div = _T_178 ? issue_slots_10_out_uop_fp_ctrl_div : _T_177 ? issue_slots_9_out_uop_fp_ctrl_div : issue_slots_8_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_fma = _T_178 ? issue_slots_10_out_uop_fp_ctrl_fma : _T_177 ? issue_slots_9_out_uop_fp_ctrl_fma : issue_slots_8_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_fastpipe = _T_178 ? issue_slots_10_out_uop_fp_ctrl_fastpipe : _T_177 ? issue_slots_9_out_uop_fp_ctrl_fastpipe : issue_slots_8_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_toint = _T_178 ? issue_slots_10_out_uop_fp_ctrl_toint : _T_177 ? issue_slots_9_out_uop_fp_ctrl_toint : issue_slots_8_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_fromint = _T_178 ? issue_slots_10_out_uop_fp_ctrl_fromint : _T_177 ? issue_slots_9_out_uop_fp_ctrl_fromint : issue_slots_8_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_typeTagOut = _T_178 ? issue_slots_10_out_uop_fp_ctrl_typeTagOut : _T_177 ? issue_slots_9_out_uop_fp_ctrl_typeTagOut : issue_slots_8_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_typeTagIn = _T_178 ? issue_slots_10_out_uop_fp_ctrl_typeTagIn : _T_177 ? issue_slots_9_out_uop_fp_ctrl_typeTagIn : issue_slots_8_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_swap23 = _T_178 ? issue_slots_10_out_uop_fp_ctrl_swap23 : _T_177 ? issue_slots_9_out_uop_fp_ctrl_swap23 : issue_slots_8_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_swap12 = _T_178 ? issue_slots_10_out_uop_fp_ctrl_swap12 : _T_177 ? issue_slots_9_out_uop_fp_ctrl_swap12 : issue_slots_8_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_ren3 = _T_178 ? issue_slots_10_out_uop_fp_ctrl_ren3 : _T_177 ? issue_slots_9_out_uop_fp_ctrl_ren3 : issue_slots_8_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_ren2 = _T_178 ? issue_slots_10_out_uop_fp_ctrl_ren2 : _T_177 ? issue_slots_9_out_uop_fp_ctrl_ren2 : issue_slots_8_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_ren1 = _T_178 ? issue_slots_10_out_uop_fp_ctrl_ren1 : _T_177 ? issue_slots_9_out_uop_fp_ctrl_ren1 : issue_slots_8_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_wen = _T_178 ? issue_slots_10_out_uop_fp_ctrl_wen : _T_177 ? issue_slots_9_out_uop_fp_ctrl_wen : issue_slots_8_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fp_ctrl_ldst = _T_178 ? issue_slots_10_out_uop_fp_ctrl_ldst : _T_177 ? issue_slots_9_out_uop_fp_ctrl_ldst : issue_slots_8_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_op2_sel = _T_178 ? issue_slots_10_out_uop_op2_sel : _T_177 ? issue_slots_9_out_uop_op2_sel : issue_slots_8_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_op1_sel = _T_178 ? issue_slots_10_out_uop_op1_sel : _T_177 ? issue_slots_9_out_uop_op1_sel : issue_slots_8_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_imm_packed = _T_178 ? issue_slots_10_out_uop_imm_packed : _T_177 ? issue_slots_9_out_uop_imm_packed : issue_slots_8_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_pimm = _T_178 ? issue_slots_10_out_uop_pimm : _T_177 ? issue_slots_9_out_uop_pimm : issue_slots_8_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_imm_sel = _T_178 ? issue_slots_10_out_uop_imm_sel : _T_177 ? issue_slots_9_out_uop_imm_sel : issue_slots_8_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_imm_rename = _T_178 ? issue_slots_10_out_uop_imm_rename : _T_177 ? issue_slots_9_out_uop_imm_rename : issue_slots_8_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_taken = _T_178 ? issue_slots_10_out_uop_taken : _T_177 ? issue_slots_9_out_uop_taken : issue_slots_8_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_pc_lob = _T_178 ? issue_slots_10_out_uop_pc_lob : _T_177 ? issue_slots_9_out_uop_pc_lob : issue_slots_8_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_edge_inst = _T_178 ? issue_slots_10_out_uop_edge_inst : _T_177 ? issue_slots_9_out_uop_edge_inst : issue_slots_8_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_ftq_idx = _T_178 ? issue_slots_10_out_uop_ftq_idx : _T_177 ? issue_slots_9_out_uop_ftq_idx : issue_slots_8_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_mov = _T_178 ? issue_slots_10_out_uop_is_mov : _T_177 ? issue_slots_9_out_uop_is_mov : issue_slots_8_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_rocc = _T_178 ? issue_slots_10_out_uop_is_rocc : _T_177 ? issue_slots_9_out_uop_is_rocc : issue_slots_8_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_sys_pc2epc = _T_178 ? issue_slots_10_out_uop_is_sys_pc2epc : _T_177 ? issue_slots_9_out_uop_is_sys_pc2epc : issue_slots_8_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_eret = _T_178 ? issue_slots_10_out_uop_is_eret : _T_177 ? issue_slots_9_out_uop_is_eret : issue_slots_8_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_amo = _T_178 ? issue_slots_10_out_uop_is_amo : _T_177 ? issue_slots_9_out_uop_is_amo : issue_slots_8_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_sfence = _T_178 ? issue_slots_10_out_uop_is_sfence : _T_177 ? issue_slots_9_out_uop_is_sfence : issue_slots_8_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_fencei = _T_178 ? issue_slots_10_out_uop_is_fencei : _T_177 ? issue_slots_9_out_uop_is_fencei : issue_slots_8_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_fence = _T_178 ? issue_slots_10_out_uop_is_fence : _T_177 ? issue_slots_9_out_uop_is_fence : issue_slots_8_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_sfb = _T_178 ? issue_slots_10_out_uop_is_sfb : _T_177 ? issue_slots_9_out_uop_is_sfb : issue_slots_8_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_br_type = _T_178 ? issue_slots_10_out_uop_br_type : _T_177 ? issue_slots_9_out_uop_br_type : issue_slots_8_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_br_tag = _T_178 ? issue_slots_10_out_uop_br_tag : _T_177 ? issue_slots_9_out_uop_br_tag : issue_slots_8_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_br_mask = _T_178 ? issue_slots_10_out_uop_br_mask : _T_177 ? issue_slots_9_out_uop_br_mask : issue_slots_8_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_dis_col_sel = _T_178 ? issue_slots_10_out_uop_dis_col_sel : _T_177 ? issue_slots_9_out_uop_dis_col_sel : issue_slots_8_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_p3_bypass_hint = _T_178 ? issue_slots_10_out_uop_iw_p3_bypass_hint : _T_177 ? issue_slots_9_out_uop_iw_p3_bypass_hint : issue_slots_8_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_p2_bypass_hint = _T_178 ? issue_slots_10_out_uop_iw_p2_bypass_hint : _T_177 ? issue_slots_9_out_uop_iw_p2_bypass_hint : issue_slots_8_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_p1_bypass_hint = _T_178 ? issue_slots_10_out_uop_iw_p1_bypass_hint : _T_177 ? issue_slots_9_out_uop_iw_p1_bypass_hint : issue_slots_8_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iw_issued = _T_178 ? issue_slots_10_out_uop_iw_issued : _T_177 ? issue_slots_9_out_uop_iw_issued : issue_slots_8_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_0 = _T_178 ? issue_slots_10_out_uop_fu_code_0 : _T_177 ? issue_slots_9_out_uop_fu_code_0 : issue_slots_8_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_1 = _T_178 ? issue_slots_10_out_uop_fu_code_1 : _T_177 ? issue_slots_9_out_uop_fu_code_1 : issue_slots_8_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_2 = _T_178 ? issue_slots_10_out_uop_fu_code_2 : _T_177 ? issue_slots_9_out_uop_fu_code_2 : issue_slots_8_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_3 = _T_178 ? issue_slots_10_out_uop_fu_code_3 : _T_177 ? issue_slots_9_out_uop_fu_code_3 : issue_slots_8_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_4 = _T_178 ? issue_slots_10_out_uop_fu_code_4 : _T_177 ? issue_slots_9_out_uop_fu_code_4 : issue_slots_8_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_5 = _T_178 ? issue_slots_10_out_uop_fu_code_5 : _T_177 ? issue_slots_9_out_uop_fu_code_5 : issue_slots_8_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_6 = _T_178 ? issue_slots_10_out_uop_fu_code_6 : _T_177 ? issue_slots_9_out_uop_fu_code_6 : issue_slots_8_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_7 = _T_178 ? issue_slots_10_out_uop_fu_code_7 : _T_177 ? issue_slots_9_out_uop_fu_code_7 : issue_slots_8_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_8 = _T_178 ? issue_slots_10_out_uop_fu_code_8 : _T_177 ? issue_slots_9_out_uop_fu_code_8 : issue_slots_8_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_fu_code_9 = _T_178 ? issue_slots_10_out_uop_fu_code_9 : _T_177 ? issue_slots_9_out_uop_fu_code_9 : issue_slots_8_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iq_type_0 = _T_178 ? issue_slots_10_out_uop_iq_type_0 : _T_177 ? issue_slots_9_out_uop_iq_type_0 : issue_slots_8_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iq_type_1 = _T_178 ? issue_slots_10_out_uop_iq_type_1 : _T_177 ? issue_slots_9_out_uop_iq_type_1 : issue_slots_8_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iq_type_2 = _T_178 ? issue_slots_10_out_uop_iq_type_2 : _T_177 ? issue_slots_9_out_uop_iq_type_2 : issue_slots_8_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_iq_type_3 = _T_178 ? issue_slots_10_out_uop_iq_type_3 : _T_177 ? issue_slots_9_out_uop_iq_type_3 : issue_slots_8_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_debug_pc = _T_178 ? issue_slots_10_out_uop_debug_pc : _T_177 ? issue_slots_9_out_uop_debug_pc : issue_slots_8_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_is_rvc = _T_178 ? issue_slots_10_out_uop_is_rvc : _T_177 ? issue_slots_9_out_uop_is_rvc : issue_slots_8_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_debug_inst = _T_178 ? issue_slots_10_out_uop_debug_inst : _T_177 ? issue_slots_9_out_uop_debug_inst : issue_slots_8_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_7_in_uop_bits_inst = _T_178 ? issue_slots_10_out_uop_inst : _T_177 ? issue_slots_9_out_uop_inst : issue_slots_8_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_7_clear_T = \|shamts_oh_7; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_7_clear = _issue_slots_7_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_180 = shamts_oh_10 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_181 = shamts_oh_11 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_8_in_uop_valid = _T_181 ? issue_slots_11_will_be_valid : _T_180 ? issue_slots_10_will_be_valid : shamts_oh_9 == 3'h1 & issue_slots_9_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_8_in_uop_bits_debug_tsrc = _T_181 ? issue_slots_11_out_uop_debug_tsrc : _T_180 ? issue_slots_10_out_uop_debug_tsrc : issue_slots_9_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_debug_fsrc = _T_181 ? issue_slots_11_out_uop_debug_fsrc : _T_180 ? issue_slots_10_out_uop_debug_fsrc : issue_slots_9_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_bp_xcpt_if = _T_181 ? issue_slots_11_out_uop_bp_xcpt_if : _T_180 ? issue_slots_10_out_uop_bp_xcpt_if : issue_slots_9_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_bp_debug_if = _T_181 ? issue_slots_11_out_uop_bp_debug_if : _T_180 ? issue_slots_10_out_uop_bp_debug_if : issue_slots_9_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_xcpt_ma_if = _T_181 ? issue_slots_11_out_uop_xcpt_ma_if : _T_180 ? issue_slots_10_out_uop_xcpt_ma_if : issue_slots_9_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_xcpt_ae_if = _T_181 ? issue_slots_11_out_uop_xcpt_ae_if : _T_180 ? issue_slots_10_out_uop_xcpt_ae_if : issue_slots_9_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_xcpt_pf_if = _T_181 ? issue_slots_11_out_uop_xcpt_pf_if : _T_180 ? issue_slots_10_out_uop_xcpt_pf_if : issue_slots_9_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_typ = _T_181 ? issue_slots_11_out_uop_fp_typ : _T_180 ? issue_slots_10_out_uop_fp_typ : issue_slots_9_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_rm = _T_181 ? issue_slots_11_out_uop_fp_rm : _T_180 ? issue_slots_10_out_uop_fp_rm : issue_slots_9_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_val = _T_181 ? issue_slots_11_out_uop_fp_val : _T_180 ? issue_slots_10_out_uop_fp_val : issue_slots_9_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fcn_op = _T_181 ? issue_slots_11_out_uop_fcn_op : _T_180 ? issue_slots_10_out_uop_fcn_op : issue_slots_9_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fcn_dw = _T_181 ? issue_slots_11_out_uop_fcn_dw : _T_180 ? issue_slots_10_out_uop_fcn_dw : issue_slots_9_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_frs3_en = _T_181 ? issue_slots_11_out_uop_frs3_en : _T_180 ? issue_slots_10_out_uop_frs3_en : issue_slots_9_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs2_rtype = _T_181 ? issue_slots_11_out_uop_lrs2_rtype : _T_180 ? issue_slots_10_out_uop_lrs2_rtype : issue_slots_9_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs1_rtype = _T_181 ? issue_slots_11_out_uop_lrs1_rtype : _T_180 ? issue_slots_10_out_uop_lrs1_rtype : issue_slots_9_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_dst_rtype = _T_181 ? issue_slots_11_out_uop_dst_rtype : _T_180 ? issue_slots_10_out_uop_dst_rtype : issue_slots_9_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs3 = _T_181 ? issue_slots_11_out_uop_lrs3 : _T_180 ? issue_slots_10_out_uop_lrs3 : issue_slots_9_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs2 = _T_181 ? issue_slots_11_out_uop_lrs2 : _T_180 ? issue_slots_10_out_uop_lrs2 : issue_slots_9_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_lrs1 = _T_181 ? issue_slots_11_out_uop_lrs1 : _T_180 ? issue_slots_10_out_uop_lrs1 : issue_slots_9_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ldst = _T_181 ? issue_slots_11_out_uop_ldst : _T_180 ? issue_slots_10_out_uop_ldst : issue_slots_9_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ldst_is_rs1 = _T_181 ? issue_slots_11_out_uop_ldst_is_rs1 : _T_180 ? issue_slots_10_out_uop_ldst_is_rs1 : issue_slots_9_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_csr_cmd = _T_181 ? issue_slots_11_out_uop_csr_cmd : _T_180 ? issue_slots_10_out_uop_csr_cmd : issue_slots_9_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_flush_on_commit = _T_181 ? issue_slots_11_out_uop_flush_on_commit : _T_180 ? issue_slots_10_out_uop_flush_on_commit : issue_slots_9_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_unique = _T_181 ? issue_slots_11_out_uop_is_unique : _T_180 ? issue_slots_10_out_uop_is_unique : issue_slots_9_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_uses_stq = _T_181 ? issue_slots_11_out_uop_uses_stq : _T_180 ? issue_slots_10_out_uop_uses_stq : issue_slots_9_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_uses_ldq = _T_181 ? issue_slots_11_out_uop_uses_ldq : _T_180 ? issue_slots_10_out_uop_uses_ldq : issue_slots_9_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_mem_signed = _T_181 ? issue_slots_11_out_uop_mem_signed : _T_180 ? issue_slots_10_out_uop_mem_signed : issue_slots_9_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_mem_size = _T_181 ? issue_slots_11_out_uop_mem_size : _T_180 ? issue_slots_10_out_uop_mem_size : issue_slots_9_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_mem_cmd = _T_181 ? issue_slots_11_out_uop_mem_cmd : _T_180 ? issue_slots_10_out_uop_mem_cmd : issue_slots_9_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_exc_cause = _T_181 ? issue_slots_11_out_uop_exc_cause : _T_180 ? issue_slots_10_out_uop_exc_cause : issue_slots_9_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_exception = _T_181 ? issue_slots_11_out_uop_exception : _T_180 ? issue_slots_10_out_uop_exception : issue_slots_9_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_stale_pdst = _T_181 ? issue_slots_11_out_uop_stale_pdst : _T_180 ? issue_slots_10_out_uop_stale_pdst : issue_slots_9_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ppred_busy = _T_181 ? issue_slots_11_out_uop_ppred_busy : _T_180 ? issue_slots_10_out_uop_ppred_busy : issue_slots_9_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs3_busy = _T_181 ? issue_slots_11_out_uop_prs3_busy : _T_180 ? issue_slots_10_out_uop_prs3_busy : issue_slots_9_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs2_busy = _T_181 ? issue_slots_11_out_uop_prs2_busy : _T_180 ? issue_slots_10_out_uop_prs2_busy : issue_slots_9_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs1_busy = _T_181 ? issue_slots_11_out_uop_prs1_busy : _T_180 ? issue_slots_10_out_uop_prs1_busy : issue_slots_9_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ppred = _T_181 ? issue_slots_11_out_uop_ppred : _T_180 ? issue_slots_10_out_uop_ppred : issue_slots_9_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs3 = _T_181 ? issue_slots_11_out_uop_prs3 : _T_180 ? issue_slots_10_out_uop_prs3 : issue_slots_9_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs2 = _T_181 ? issue_slots_11_out_uop_prs2 : _T_180 ? issue_slots_10_out_uop_prs2 : issue_slots_9_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_prs1 = _T_181 ? issue_slots_11_out_uop_prs1 : _T_180 ? issue_slots_10_out_uop_prs1 : issue_slots_9_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_pdst = _T_181 ? issue_slots_11_out_uop_pdst : _T_180 ? issue_slots_10_out_uop_pdst : issue_slots_9_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_rxq_idx = _T_181 ? issue_slots_11_out_uop_rxq_idx : _T_180 ? issue_slots_10_out_uop_rxq_idx : issue_slots_9_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_stq_idx = _T_181 ? issue_slots_11_out_uop_stq_idx : _T_180 ? issue_slots_10_out_uop_stq_idx : issue_slots_9_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ldq_idx = _T_181 ? issue_slots_11_out_uop_ldq_idx : _T_180 ? issue_slots_10_out_uop_ldq_idx : issue_slots_9_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_rob_idx = _T_181 ? issue_slots_11_out_uop_rob_idx : _T_180 ? issue_slots_10_out_uop_rob_idx : issue_slots_9_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_vec = _T_181 ? issue_slots_11_out_uop_fp_ctrl_vec : _T_180 ? issue_slots_10_out_uop_fp_ctrl_vec : issue_slots_9_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_wflags = _T_181 ? issue_slots_11_out_uop_fp_ctrl_wflags : _T_180 ? issue_slots_10_out_uop_fp_ctrl_wflags : issue_slots_9_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_sqrt = _T_181 ? issue_slots_11_out_uop_fp_ctrl_sqrt : _T_180 ? issue_slots_10_out_uop_fp_ctrl_sqrt : issue_slots_9_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_div = _T_181 ? issue_slots_11_out_uop_fp_ctrl_div : _T_180 ? issue_slots_10_out_uop_fp_ctrl_div : issue_slots_9_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_fma = _T_181 ? issue_slots_11_out_uop_fp_ctrl_fma : _T_180 ? issue_slots_10_out_uop_fp_ctrl_fma : issue_slots_9_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_fastpipe = _T_181 ? issue_slots_11_out_uop_fp_ctrl_fastpipe : _T_180 ? issue_slots_10_out_uop_fp_ctrl_fastpipe : issue_slots_9_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_toint = _T_181 ? issue_slots_11_out_uop_fp_ctrl_toint : _T_180 ? issue_slots_10_out_uop_fp_ctrl_toint : issue_slots_9_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_fromint = _T_181 ? issue_slots_11_out_uop_fp_ctrl_fromint : _T_180 ? issue_slots_10_out_uop_fp_ctrl_fromint : issue_slots_9_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_typeTagOut = _T_181 ? issue_slots_11_out_uop_fp_ctrl_typeTagOut : _T_180 ? issue_slots_10_out_uop_fp_ctrl_typeTagOut : issue_slots_9_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_typeTagIn = _T_181 ? issue_slots_11_out_uop_fp_ctrl_typeTagIn : _T_180 ? issue_slots_10_out_uop_fp_ctrl_typeTagIn : issue_slots_9_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_swap23 = _T_181 ? issue_slots_11_out_uop_fp_ctrl_swap23 : _T_180 ? issue_slots_10_out_uop_fp_ctrl_swap23 : issue_slots_9_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_swap12 = _T_181 ? issue_slots_11_out_uop_fp_ctrl_swap12 : _T_180 ? issue_slots_10_out_uop_fp_ctrl_swap12 : issue_slots_9_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_ren3 = _T_181 ? issue_slots_11_out_uop_fp_ctrl_ren3 : _T_180 ? issue_slots_10_out_uop_fp_ctrl_ren3 : issue_slots_9_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_ren2 = _T_181 ? issue_slots_11_out_uop_fp_ctrl_ren2 : _T_180 ? issue_slots_10_out_uop_fp_ctrl_ren2 : issue_slots_9_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_ren1 = _T_181 ? issue_slots_11_out_uop_fp_ctrl_ren1 : _T_180 ? issue_slots_10_out_uop_fp_ctrl_ren1 : issue_slots_9_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_wen = _T_181 ? issue_slots_11_out_uop_fp_ctrl_wen : _T_180 ? issue_slots_10_out_uop_fp_ctrl_wen : issue_slots_9_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fp_ctrl_ldst = _T_181 ? issue_slots_11_out_uop_fp_ctrl_ldst : _T_180 ? issue_slots_10_out_uop_fp_ctrl_ldst : issue_slots_9_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_op2_sel = _T_181 ? issue_slots_11_out_uop_op2_sel : _T_180 ? issue_slots_10_out_uop_op2_sel : issue_slots_9_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_op1_sel = _T_181 ? issue_slots_11_out_uop_op1_sel : _T_180 ? issue_slots_10_out_uop_op1_sel : issue_slots_9_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_imm_packed = _T_181 ? issue_slots_11_out_uop_imm_packed : _T_180 ? issue_slots_10_out_uop_imm_packed : issue_slots_9_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_pimm = _T_181 ? issue_slots_11_out_uop_pimm : _T_180 ? issue_slots_10_out_uop_pimm : issue_slots_9_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_imm_sel = _T_181 ? issue_slots_11_out_uop_imm_sel : _T_180 ? issue_slots_10_out_uop_imm_sel : issue_slots_9_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_imm_rename = _T_181 ? issue_slots_11_out_uop_imm_rename : _T_180 ? issue_slots_10_out_uop_imm_rename : issue_slots_9_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_taken = _T_181 ? issue_slots_11_out_uop_taken : _T_180 ? issue_slots_10_out_uop_taken : issue_slots_9_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_pc_lob = _T_181 ? issue_slots_11_out_uop_pc_lob : _T_180 ? issue_slots_10_out_uop_pc_lob : issue_slots_9_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_edge_inst = _T_181 ? issue_slots_11_out_uop_edge_inst : _T_180 ? issue_slots_10_out_uop_edge_inst : issue_slots_9_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_ftq_idx = _T_181 ? issue_slots_11_out_uop_ftq_idx : _T_180 ? issue_slots_10_out_uop_ftq_idx : issue_slots_9_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_mov = _T_181 ? issue_slots_11_out_uop_is_mov : _T_180 ? issue_slots_10_out_uop_is_mov : issue_slots_9_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_rocc = _T_181 ? issue_slots_11_out_uop_is_rocc : _T_180 ? issue_slots_10_out_uop_is_rocc : issue_slots_9_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_sys_pc2epc = _T_181 ? issue_slots_11_out_uop_is_sys_pc2epc : _T_180 ? issue_slots_10_out_uop_is_sys_pc2epc : issue_slots_9_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_eret = _T_181 ? issue_slots_11_out_uop_is_eret : _T_180 ? issue_slots_10_out_uop_is_eret : issue_slots_9_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_amo = _T_181 ? issue_slots_11_out_uop_is_amo : _T_180 ? issue_slots_10_out_uop_is_amo : issue_slots_9_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_sfence = _T_181 ? issue_slots_11_out_uop_is_sfence : _T_180 ? issue_slots_10_out_uop_is_sfence : issue_slots_9_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_fencei = _T_181 ? issue_slots_11_out_uop_is_fencei : _T_180 ? issue_slots_10_out_uop_is_fencei : issue_slots_9_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_fence = _T_181 ? issue_slots_11_out_uop_is_fence : _T_180 ? issue_slots_10_out_uop_is_fence : issue_slots_9_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_sfb = _T_181 ? issue_slots_11_out_uop_is_sfb : _T_180 ? issue_slots_10_out_uop_is_sfb : issue_slots_9_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_br_type = _T_181 ? issue_slots_11_out_uop_br_type : _T_180 ? issue_slots_10_out_uop_br_type : issue_slots_9_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_br_tag = _T_181 ? issue_slots_11_out_uop_br_tag : _T_180 ? issue_slots_10_out_uop_br_tag : issue_slots_9_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_br_mask = _T_181 ? issue_slots_11_out_uop_br_mask : _T_180 ? issue_slots_10_out_uop_br_mask : issue_slots_9_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_dis_col_sel = _T_181 ? issue_slots_11_out_uop_dis_col_sel : _T_180 ? issue_slots_10_out_uop_dis_col_sel : issue_slots_9_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_p3_bypass_hint = _T_181 ? issue_slots_11_out_uop_iw_p3_bypass_hint : _T_180 ? issue_slots_10_out_uop_iw_p3_bypass_hint : issue_slots_9_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_p2_bypass_hint = _T_181 ? issue_slots_11_out_uop_iw_p2_bypass_hint : _T_180 ? issue_slots_10_out_uop_iw_p2_bypass_hint : issue_slots_9_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_p1_bypass_hint = _T_181 ? issue_slots_11_out_uop_iw_p1_bypass_hint : _T_180 ? issue_slots_10_out_uop_iw_p1_bypass_hint : issue_slots_9_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iw_issued = _T_181 ? issue_slots_11_out_uop_iw_issued : _T_180 ? issue_slots_10_out_uop_iw_issued : issue_slots_9_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_0 = _T_181 ? issue_slots_11_out_uop_fu_code_0 : _T_180 ? issue_slots_10_out_uop_fu_code_0 : issue_slots_9_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_1 = _T_181 ? issue_slots_11_out_uop_fu_code_1 : _T_180 ? issue_slots_10_out_uop_fu_code_1 : issue_slots_9_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_2 = _T_181 ? issue_slots_11_out_uop_fu_code_2 : _T_180 ? issue_slots_10_out_uop_fu_code_2 : issue_slots_9_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_3 = _T_181 ? issue_slots_11_out_uop_fu_code_3 : _T_180 ? issue_slots_10_out_uop_fu_code_3 : issue_slots_9_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_4 = _T_181 ? issue_slots_11_out_uop_fu_code_4 : _T_180 ? issue_slots_10_out_uop_fu_code_4 : issue_slots_9_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_5 = _T_181 ? issue_slots_11_out_uop_fu_code_5 : _T_180 ? issue_slots_10_out_uop_fu_code_5 : issue_slots_9_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_6 = _T_181 ? issue_slots_11_out_uop_fu_code_6 : _T_180 ? issue_slots_10_out_uop_fu_code_6 : issue_slots_9_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_7 = _T_181 ? issue_slots_11_out_uop_fu_code_7 : _T_180 ? issue_slots_10_out_uop_fu_code_7 : issue_slots_9_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_8 = _T_181 ? issue_slots_11_out_uop_fu_code_8 : _T_180 ? issue_slots_10_out_uop_fu_code_8 : issue_slots_9_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_fu_code_9 = _T_181 ? issue_slots_11_out_uop_fu_code_9 : _T_180 ? issue_slots_10_out_uop_fu_code_9 : issue_slots_9_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iq_type_0 = _T_181 ? issue_slots_11_out_uop_iq_type_0 : _T_180 ? issue_slots_10_out_uop_iq_type_0 : issue_slots_9_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iq_type_1 = _T_181 ? issue_slots_11_out_uop_iq_type_1 : _T_180 ? issue_slots_10_out_uop_iq_type_1 : issue_slots_9_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iq_type_2 = _T_181 ? issue_slots_11_out_uop_iq_type_2 : _T_180 ? issue_slots_10_out_uop_iq_type_2 : issue_slots_9_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_iq_type_3 = _T_181 ? issue_slots_11_out_uop_iq_type_3 : _T_180 ? issue_slots_10_out_uop_iq_type_3 : issue_slots_9_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_debug_pc = _T_181 ? issue_slots_11_out_uop_debug_pc : _T_180 ? issue_slots_10_out_uop_debug_pc : issue_slots_9_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_is_rvc = _T_181 ? issue_slots_11_out_uop_is_rvc : _T_180 ? issue_slots_10_out_uop_is_rvc : issue_slots_9_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_debug_inst = _T_181 ? issue_slots_11_out_uop_debug_inst : _T_180 ? issue_slots_10_out_uop_debug_inst : issue_slots_9_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_8_in_uop_bits_inst = _T_181 ? issue_slots_11_out_uop_inst : _T_180 ? issue_slots_10_out_uop_inst : issue_slots_9_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_8_clear_T = \|shamts_oh_8; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_8_clear = _issue_slots_8_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_183 = shamts_oh_11 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_184 = shamts_oh_12 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_9_in_uop_valid = _T_184 ? issue_slots_12_will_be_valid : _T_183 ? issue_slots_11_will_be_valid : shamts_oh_10 == 3'h1 & issue_slots_10_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_9_in_uop_bits_debug_tsrc = _T_184 ? issue_slots_12_out_uop_debug_tsrc : _T_183 ? issue_slots_11_out_uop_debug_tsrc : issue_slots_10_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_debug_fsrc = _T_184 ? issue_slots_12_out_uop_debug_fsrc : _T_183 ? issue_slots_11_out_uop_debug_fsrc : issue_slots_10_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_bp_xcpt_if = _T_184 ? issue_slots_12_out_uop_bp_xcpt_if : _T_183 ? issue_slots_11_out_uop_bp_xcpt_if : issue_slots_10_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_bp_debug_if = _T_184 ? issue_slots_12_out_uop_bp_debug_if : _T_183 ? issue_slots_11_out_uop_bp_debug_if : issue_slots_10_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_xcpt_ma_if = _T_184 ? issue_slots_12_out_uop_xcpt_ma_if : _T_183 ? issue_slots_11_out_uop_xcpt_ma_if : issue_slots_10_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_xcpt_ae_if = _T_184 ? issue_slots_12_out_uop_xcpt_ae_if : _T_183 ? issue_slots_11_out_uop_xcpt_ae_if : issue_slots_10_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_xcpt_pf_if = _T_184 ? issue_slots_12_out_uop_xcpt_pf_if : _T_183 ? issue_slots_11_out_uop_xcpt_pf_if : issue_slots_10_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_typ = _T_184 ? issue_slots_12_out_uop_fp_typ : _T_183 ? issue_slots_11_out_uop_fp_typ : issue_slots_10_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_rm = _T_184 ? issue_slots_12_out_uop_fp_rm : _T_183 ? issue_slots_11_out_uop_fp_rm : issue_slots_10_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_val = _T_184 ? issue_slots_12_out_uop_fp_val : _T_183 ? issue_slots_11_out_uop_fp_val : issue_slots_10_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fcn_op = _T_184 ? issue_slots_12_out_uop_fcn_op : _T_183 ? issue_slots_11_out_uop_fcn_op : issue_slots_10_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fcn_dw = _T_184 ? issue_slots_12_out_uop_fcn_dw : _T_183 ? issue_slots_11_out_uop_fcn_dw : issue_slots_10_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_frs3_en = _T_184 ? issue_slots_12_out_uop_frs3_en : _T_183 ? issue_slots_11_out_uop_frs3_en : issue_slots_10_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs2_rtype = _T_184 ? issue_slots_12_out_uop_lrs2_rtype : _T_183 ? issue_slots_11_out_uop_lrs2_rtype : issue_slots_10_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs1_rtype = _T_184 ? issue_slots_12_out_uop_lrs1_rtype : _T_183 ? issue_slots_11_out_uop_lrs1_rtype : issue_slots_10_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_dst_rtype = _T_184 ? issue_slots_12_out_uop_dst_rtype : _T_183 ? issue_slots_11_out_uop_dst_rtype : issue_slots_10_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs3 = _T_184 ? issue_slots_12_out_uop_lrs3 : _T_183 ? issue_slots_11_out_uop_lrs3 : issue_slots_10_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs2 = _T_184 ? issue_slots_12_out_uop_lrs2 : _T_183 ? issue_slots_11_out_uop_lrs2 : issue_slots_10_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_lrs1 = _T_184 ? issue_slots_12_out_uop_lrs1 : _T_183 ? issue_slots_11_out_uop_lrs1 : issue_slots_10_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ldst = _T_184 ? issue_slots_12_out_uop_ldst : _T_183 ? issue_slots_11_out_uop_ldst : issue_slots_10_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ldst_is_rs1 = _T_184 ? issue_slots_12_out_uop_ldst_is_rs1 : _T_183 ? issue_slots_11_out_uop_ldst_is_rs1 : issue_slots_10_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_csr_cmd = _T_184 ? issue_slots_12_out_uop_csr_cmd : _T_183 ? issue_slots_11_out_uop_csr_cmd : issue_slots_10_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_flush_on_commit = _T_184 ? issue_slots_12_out_uop_flush_on_commit : _T_183 ? issue_slots_11_out_uop_flush_on_commit : issue_slots_10_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_unique = _T_184 ? issue_slots_12_out_uop_is_unique : _T_183 ? issue_slots_11_out_uop_is_unique : issue_slots_10_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_uses_stq = _T_184 ? issue_slots_12_out_uop_uses_stq : _T_183 ? issue_slots_11_out_uop_uses_stq : issue_slots_10_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_uses_ldq = _T_184 ? issue_slots_12_out_uop_uses_ldq : _T_183 ? issue_slots_11_out_uop_uses_ldq : issue_slots_10_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_mem_signed = _T_184 ? issue_slots_12_out_uop_mem_signed : _T_183 ? issue_slots_11_out_uop_mem_signed : issue_slots_10_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_mem_size = _T_184 ? issue_slots_12_out_uop_mem_size : _T_183 ? issue_slots_11_out_uop_mem_size : issue_slots_10_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_mem_cmd = _T_184 ? issue_slots_12_out_uop_mem_cmd : _T_183 ? issue_slots_11_out_uop_mem_cmd : issue_slots_10_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_exc_cause = _T_184 ? issue_slots_12_out_uop_exc_cause : _T_183 ? issue_slots_11_out_uop_exc_cause : issue_slots_10_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_exception = _T_184 ? issue_slots_12_out_uop_exception : _T_183 ? issue_slots_11_out_uop_exception : issue_slots_10_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_stale_pdst = _T_184 ? issue_slots_12_out_uop_stale_pdst : _T_183 ? issue_slots_11_out_uop_stale_pdst : issue_slots_10_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ppred_busy = _T_184 ? issue_slots_12_out_uop_ppred_busy : _T_183 ? issue_slots_11_out_uop_ppred_busy : issue_slots_10_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs3_busy = _T_184 ? issue_slots_12_out_uop_prs3_busy : _T_183 ? issue_slots_11_out_uop_prs3_busy : issue_slots_10_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs2_busy = _T_184 ? issue_slots_12_out_uop_prs2_busy : _T_183 ? issue_slots_11_out_uop_prs2_busy : issue_slots_10_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs1_busy = _T_184 ? issue_slots_12_out_uop_prs1_busy : _T_183 ? issue_slots_11_out_uop_prs1_busy : issue_slots_10_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ppred = _T_184 ? issue_slots_12_out_uop_ppred : _T_183 ? issue_slots_11_out_uop_ppred : issue_slots_10_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs3 = _T_184 ? issue_slots_12_out_uop_prs3 : _T_183 ? issue_slots_11_out_uop_prs3 : issue_slots_10_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs2 = _T_184 ? issue_slots_12_out_uop_prs2 : _T_183 ? issue_slots_11_out_uop_prs2 : issue_slots_10_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_prs1 = _T_184 ? issue_slots_12_out_uop_prs1 : _T_183 ? issue_slots_11_out_uop_prs1 : issue_slots_10_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_pdst = _T_184 ? issue_slots_12_out_uop_pdst : _T_183 ? issue_slots_11_out_uop_pdst : issue_slots_10_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_rxq_idx = _T_184 ? issue_slots_12_out_uop_rxq_idx : _T_183 ? issue_slots_11_out_uop_rxq_idx : issue_slots_10_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_stq_idx = _T_184 ? issue_slots_12_out_uop_stq_idx : _T_183 ? issue_slots_11_out_uop_stq_idx : issue_slots_10_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ldq_idx = _T_184 ? issue_slots_12_out_uop_ldq_idx : _T_183 ? issue_slots_11_out_uop_ldq_idx : issue_slots_10_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_rob_idx = _T_184 ? issue_slots_12_out_uop_rob_idx : _T_183 ? issue_slots_11_out_uop_rob_idx : issue_slots_10_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_vec = _T_184 ? issue_slots_12_out_uop_fp_ctrl_vec : _T_183 ? issue_slots_11_out_uop_fp_ctrl_vec : issue_slots_10_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_wflags = _T_184 ? issue_slots_12_out_uop_fp_ctrl_wflags : _T_183 ? issue_slots_11_out_uop_fp_ctrl_wflags : issue_slots_10_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_sqrt = _T_184 ? issue_slots_12_out_uop_fp_ctrl_sqrt : _T_183 ? issue_slots_11_out_uop_fp_ctrl_sqrt : issue_slots_10_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_div = _T_184 ? issue_slots_12_out_uop_fp_ctrl_div : _T_183 ? issue_slots_11_out_uop_fp_ctrl_div : issue_slots_10_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_fma = _T_184 ? issue_slots_12_out_uop_fp_ctrl_fma : _T_183 ? issue_slots_11_out_uop_fp_ctrl_fma : issue_slots_10_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_fastpipe = _T_184 ? issue_slots_12_out_uop_fp_ctrl_fastpipe : _T_183 ? issue_slots_11_out_uop_fp_ctrl_fastpipe : issue_slots_10_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_toint = _T_184 ? issue_slots_12_out_uop_fp_ctrl_toint : _T_183 ? issue_slots_11_out_uop_fp_ctrl_toint : issue_slots_10_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_fromint = _T_184 ? issue_slots_12_out_uop_fp_ctrl_fromint : _T_183 ? issue_slots_11_out_uop_fp_ctrl_fromint : issue_slots_10_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_typeTagOut = _T_184 ? issue_slots_12_out_uop_fp_ctrl_typeTagOut : _T_183 ? issue_slots_11_out_uop_fp_ctrl_typeTagOut : issue_slots_10_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_typeTagIn = _T_184 ? issue_slots_12_out_uop_fp_ctrl_typeTagIn : _T_183 ? issue_slots_11_out_uop_fp_ctrl_typeTagIn : issue_slots_10_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_swap23 = _T_184 ? issue_slots_12_out_uop_fp_ctrl_swap23 : _T_183 ? issue_slots_11_out_uop_fp_ctrl_swap23 : issue_slots_10_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_swap12 = _T_184 ? issue_slots_12_out_uop_fp_ctrl_swap12 : _T_183 ? issue_slots_11_out_uop_fp_ctrl_swap12 : issue_slots_10_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_ren3 = _T_184 ? issue_slots_12_out_uop_fp_ctrl_ren3 : _T_183 ? issue_slots_11_out_uop_fp_ctrl_ren3 : issue_slots_10_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_ren2 = _T_184 ? issue_slots_12_out_uop_fp_ctrl_ren2 : _T_183 ? issue_slots_11_out_uop_fp_ctrl_ren2 : issue_slots_10_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_ren1 = _T_184 ? issue_slots_12_out_uop_fp_ctrl_ren1 : _T_183 ? issue_slots_11_out_uop_fp_ctrl_ren1 : issue_slots_10_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_wen = _T_184 ? issue_slots_12_out_uop_fp_ctrl_wen : _T_183 ? issue_slots_11_out_uop_fp_ctrl_wen : issue_slots_10_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fp_ctrl_ldst = _T_184 ? issue_slots_12_out_uop_fp_ctrl_ldst : _T_183 ? issue_slots_11_out_uop_fp_ctrl_ldst : issue_slots_10_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_op2_sel = _T_184 ? issue_slots_12_out_uop_op2_sel : _T_183 ? issue_slots_11_out_uop_op2_sel : issue_slots_10_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_op1_sel = _T_184 ? issue_slots_12_out_uop_op1_sel : _T_183 ? issue_slots_11_out_uop_op1_sel : issue_slots_10_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_imm_packed = _T_184 ? issue_slots_12_out_uop_imm_packed : _T_183 ? issue_slots_11_out_uop_imm_packed : issue_slots_10_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_pimm = _T_184 ? issue_slots_12_out_uop_pimm : _T_183 ? issue_slots_11_out_uop_pimm : issue_slots_10_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_imm_sel = _T_184 ? issue_slots_12_out_uop_imm_sel : _T_183 ? issue_slots_11_out_uop_imm_sel : issue_slots_10_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_imm_rename = _T_184 ? issue_slots_12_out_uop_imm_rename : _T_183 ? issue_slots_11_out_uop_imm_rename : issue_slots_10_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_taken = _T_184 ? issue_slots_12_out_uop_taken : _T_183 ? issue_slots_11_out_uop_taken : issue_slots_10_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_pc_lob = _T_184 ? issue_slots_12_out_uop_pc_lob : _T_183 ? issue_slots_11_out_uop_pc_lob : issue_slots_10_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_edge_inst = _T_184 ? issue_slots_12_out_uop_edge_inst : _T_183 ? issue_slots_11_out_uop_edge_inst : issue_slots_10_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_ftq_idx = _T_184 ? issue_slots_12_out_uop_ftq_idx : _T_183 ? issue_slots_11_out_uop_ftq_idx : issue_slots_10_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_mov = _T_184 ? issue_slots_12_out_uop_is_mov : _T_183 ? issue_slots_11_out_uop_is_mov : issue_slots_10_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_rocc = _T_184 ? issue_slots_12_out_uop_is_rocc : _T_183 ? issue_slots_11_out_uop_is_rocc : issue_slots_10_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_sys_pc2epc = _T_184 ? issue_slots_12_out_uop_is_sys_pc2epc : _T_183 ? issue_slots_11_out_uop_is_sys_pc2epc : issue_slots_10_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_eret = _T_184 ? issue_slots_12_out_uop_is_eret : _T_183 ? issue_slots_11_out_uop_is_eret : issue_slots_10_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_amo = _T_184 ? issue_slots_12_out_uop_is_amo : _T_183 ? issue_slots_11_out_uop_is_amo : issue_slots_10_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_sfence = _T_184 ? issue_slots_12_out_uop_is_sfence : _T_183 ? issue_slots_11_out_uop_is_sfence : issue_slots_10_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_fencei = _T_184 ? issue_slots_12_out_uop_is_fencei : _T_183 ? issue_slots_11_out_uop_is_fencei : issue_slots_10_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_fence = _T_184 ? issue_slots_12_out_uop_is_fence : _T_183 ? issue_slots_11_out_uop_is_fence : issue_slots_10_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_sfb = _T_184 ? issue_slots_12_out_uop_is_sfb : _T_183 ? issue_slots_11_out_uop_is_sfb : issue_slots_10_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_br_type = _T_184 ? issue_slots_12_out_uop_br_type : _T_183 ? issue_slots_11_out_uop_br_type : issue_slots_10_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_br_tag = _T_184 ? issue_slots_12_out_uop_br_tag : _T_183 ? issue_slots_11_out_uop_br_tag : issue_slots_10_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_br_mask = _T_184 ? issue_slots_12_out_uop_br_mask : _T_183 ? issue_slots_11_out_uop_br_mask : issue_slots_10_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_dis_col_sel = _T_184 ? issue_slots_12_out_uop_dis_col_sel : _T_183 ? issue_slots_11_out_uop_dis_col_sel : issue_slots_10_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_p3_bypass_hint = _T_184 ? issue_slots_12_out_uop_iw_p3_bypass_hint : _T_183 ? issue_slots_11_out_uop_iw_p3_bypass_hint : issue_slots_10_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_p2_bypass_hint = _T_184 ? issue_slots_12_out_uop_iw_p2_bypass_hint : _T_183 ? issue_slots_11_out_uop_iw_p2_bypass_hint : issue_slots_10_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_p1_bypass_hint = _T_184 ? issue_slots_12_out_uop_iw_p1_bypass_hint : _T_183 ? issue_slots_11_out_uop_iw_p1_bypass_hint : issue_slots_10_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iw_issued = _T_184 ? issue_slots_12_out_uop_iw_issued : _T_183 ? issue_slots_11_out_uop_iw_issued : issue_slots_10_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_0 = _T_184 ? issue_slots_12_out_uop_fu_code_0 : _T_183 ? issue_slots_11_out_uop_fu_code_0 : issue_slots_10_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_1 = _T_184 ? issue_slots_12_out_uop_fu_code_1 : _T_183 ? issue_slots_11_out_uop_fu_code_1 : issue_slots_10_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_2 = _T_184 ? issue_slots_12_out_uop_fu_code_2 : _T_183 ? issue_slots_11_out_uop_fu_code_2 : issue_slots_10_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_3 = _T_184 ? issue_slots_12_out_uop_fu_code_3 : _T_183 ? issue_slots_11_out_uop_fu_code_3 : issue_slots_10_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_4 = _T_184 ? issue_slots_12_out_uop_fu_code_4 : _T_183 ? issue_slots_11_out_uop_fu_code_4 : issue_slots_10_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_5 = _T_184 ? issue_slots_12_out_uop_fu_code_5 : _T_183 ? issue_slots_11_out_uop_fu_code_5 : issue_slots_10_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_6 = _T_184 ? issue_slots_12_out_uop_fu_code_6 : _T_183 ? issue_slots_11_out_uop_fu_code_6 : issue_slots_10_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_7 = _T_184 ? issue_slots_12_out_uop_fu_code_7 : _T_183 ? issue_slots_11_out_uop_fu_code_7 : issue_slots_10_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_8 = _T_184 ? issue_slots_12_out_uop_fu_code_8 : _T_183 ? issue_slots_11_out_uop_fu_code_8 : issue_slots_10_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_fu_code_9 = _T_184 ? issue_slots_12_out_uop_fu_code_9 : _T_183 ? issue_slots_11_out_uop_fu_code_9 : issue_slots_10_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iq_type_0 = _T_184 ? issue_slots_12_out_uop_iq_type_0 : _T_183 ? issue_slots_11_out_uop_iq_type_0 : issue_slots_10_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iq_type_1 = _T_184 ? issue_slots_12_out_uop_iq_type_1 : _T_183 ? issue_slots_11_out_uop_iq_type_1 : issue_slots_10_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iq_type_2 = _T_184 ? issue_slots_12_out_uop_iq_type_2 : _T_183 ? issue_slots_11_out_uop_iq_type_2 : issue_slots_10_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_iq_type_3 = _T_184 ? issue_slots_12_out_uop_iq_type_3 : _T_183 ? issue_slots_11_out_uop_iq_type_3 : issue_slots_10_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_debug_pc = _T_184 ? issue_slots_12_out_uop_debug_pc : _T_183 ? issue_slots_11_out_uop_debug_pc : issue_slots_10_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_is_rvc = _T_184 ? issue_slots_12_out_uop_is_rvc : _T_183 ? issue_slots_11_out_uop_is_rvc : issue_slots_10_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_debug_inst = _T_184 ? issue_slots_12_out_uop_debug_inst : _T_183 ? issue_slots_11_out_uop_debug_inst : issue_slots_10_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_9_in_uop_bits_inst = _T_184 ? issue_slots_12_out_uop_inst : _T_183 ? issue_slots_11_out_uop_inst : issue_slots_10_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_9_clear_T = \|shamts_oh_9; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_9_clear = _issue_slots_9_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_186 = shamts_oh_12 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_187 = shamts_oh_13 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_10_in_uop_valid = _T_187 ? issue_slots_13_will_be_valid : _T_186 ? issue_slots_12_will_be_valid : shamts_oh_11 == 3'h1 & issue_slots_11_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_10_in_uop_bits_debug_tsrc = _T_187 ? issue_slots_13_out_uop_debug_tsrc : _T_186 ? issue_slots_12_out_uop_debug_tsrc : issue_slots_11_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_debug_fsrc = _T_187 ? issue_slots_13_out_uop_debug_fsrc : _T_186 ? issue_slots_12_out_uop_debug_fsrc : issue_slots_11_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_bp_xcpt_if = _T_187 ? issue_slots_13_out_uop_bp_xcpt_if : _T_186 ? issue_slots_12_out_uop_bp_xcpt_if : issue_slots_11_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_bp_debug_if = _T_187 ? issue_slots_13_out_uop_bp_debug_if : _T_186 ? issue_slots_12_out_uop_bp_debug_if : issue_slots_11_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_xcpt_ma_if = _T_187 ? issue_slots_13_out_uop_xcpt_ma_if : _T_186 ? issue_slots_12_out_uop_xcpt_ma_if : issue_slots_11_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_xcpt_ae_if = _T_187 ? issue_slots_13_out_uop_xcpt_ae_if : _T_186 ? issue_slots_12_out_uop_xcpt_ae_if : issue_slots_11_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_xcpt_pf_if = _T_187 ? issue_slots_13_out_uop_xcpt_pf_if : _T_186 ? issue_slots_12_out_uop_xcpt_pf_if : issue_slots_11_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_typ = _T_187 ? issue_slots_13_out_uop_fp_typ : _T_186 ? issue_slots_12_out_uop_fp_typ : issue_slots_11_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_rm = _T_187 ? issue_slots_13_out_uop_fp_rm : _T_186 ? issue_slots_12_out_uop_fp_rm : issue_slots_11_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_val = _T_187 ? issue_slots_13_out_uop_fp_val : _T_186 ? issue_slots_12_out_uop_fp_val : issue_slots_11_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fcn_op = _T_187 ? issue_slots_13_out_uop_fcn_op : _T_186 ? issue_slots_12_out_uop_fcn_op : issue_slots_11_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fcn_dw = _T_187 ? issue_slots_13_out_uop_fcn_dw : _T_186 ? issue_slots_12_out_uop_fcn_dw : issue_slots_11_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_frs3_en = _T_187 ? issue_slots_13_out_uop_frs3_en : _T_186 ? issue_slots_12_out_uop_frs3_en : issue_slots_11_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs2_rtype = _T_187 ? issue_slots_13_out_uop_lrs2_rtype : _T_186 ? issue_slots_12_out_uop_lrs2_rtype : issue_slots_11_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs1_rtype = _T_187 ? issue_slots_13_out_uop_lrs1_rtype : _T_186 ? issue_slots_12_out_uop_lrs1_rtype : issue_slots_11_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_dst_rtype = _T_187 ? issue_slots_13_out_uop_dst_rtype : _T_186 ? issue_slots_12_out_uop_dst_rtype : issue_slots_11_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs3 = _T_187 ? issue_slots_13_out_uop_lrs3 : _T_186 ? issue_slots_12_out_uop_lrs3 : issue_slots_11_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs2 = _T_187 ? issue_slots_13_out_uop_lrs2 : _T_186 ? issue_slots_12_out_uop_lrs2 : issue_slots_11_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_lrs1 = _T_187 ? issue_slots_13_out_uop_lrs1 : _T_186 ? issue_slots_12_out_uop_lrs1 : issue_slots_11_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ldst = _T_187 ? issue_slots_13_out_uop_ldst : _T_186 ? issue_slots_12_out_uop_ldst : issue_slots_11_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ldst_is_rs1 = _T_187 ? issue_slots_13_out_uop_ldst_is_rs1 : _T_186 ? issue_slots_12_out_uop_ldst_is_rs1 : issue_slots_11_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_csr_cmd = _T_187 ? issue_slots_13_out_uop_csr_cmd : _T_186 ? issue_slots_12_out_uop_csr_cmd : issue_slots_11_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_flush_on_commit = _T_187 ? issue_slots_13_out_uop_flush_on_commit : _T_186 ? issue_slots_12_out_uop_flush_on_commit : issue_slots_11_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_unique = _T_187 ? issue_slots_13_out_uop_is_unique : _T_186 ? issue_slots_12_out_uop_is_unique : issue_slots_11_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_uses_stq = _T_187 ? issue_slots_13_out_uop_uses_stq : _T_186 ? issue_slots_12_out_uop_uses_stq : issue_slots_11_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_uses_ldq = _T_187 ? issue_slots_13_out_uop_uses_ldq : _T_186 ? issue_slots_12_out_uop_uses_ldq : issue_slots_11_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_mem_signed = _T_187 ? issue_slots_13_out_uop_mem_signed : _T_186 ? issue_slots_12_out_uop_mem_signed : issue_slots_11_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_mem_size = _T_187 ? issue_slots_13_out_uop_mem_size : _T_186 ? issue_slots_12_out_uop_mem_size : issue_slots_11_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_mem_cmd = _T_187 ? issue_slots_13_out_uop_mem_cmd : _T_186 ? issue_slots_12_out_uop_mem_cmd : issue_slots_11_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_exc_cause = _T_187 ? issue_slots_13_out_uop_exc_cause : _T_186 ? issue_slots_12_out_uop_exc_cause : issue_slots_11_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_exception = _T_187 ? issue_slots_13_out_uop_exception : _T_186 ? issue_slots_12_out_uop_exception : issue_slots_11_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_stale_pdst = _T_187 ? issue_slots_13_out_uop_stale_pdst : _T_186 ? issue_slots_12_out_uop_stale_pdst : issue_slots_11_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ppred_busy = _T_187 ? issue_slots_13_out_uop_ppred_busy : _T_186 ? issue_slots_12_out_uop_ppred_busy : issue_slots_11_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs3_busy = _T_187 ? issue_slots_13_out_uop_prs3_busy : _T_186 ? issue_slots_12_out_uop_prs3_busy : issue_slots_11_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs2_busy = _T_187 ? issue_slots_13_out_uop_prs2_busy : _T_186 ? issue_slots_12_out_uop_prs2_busy : issue_slots_11_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs1_busy = _T_187 ? issue_slots_13_out_uop_prs1_busy : _T_186 ? issue_slots_12_out_uop_prs1_busy : issue_slots_11_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ppred = _T_187 ? issue_slots_13_out_uop_ppred : _T_186 ? issue_slots_12_out_uop_ppred : issue_slots_11_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs3 = _T_187 ? issue_slots_13_out_uop_prs3 : _T_186 ? issue_slots_12_out_uop_prs3 : issue_slots_11_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs2 = _T_187 ? issue_slots_13_out_uop_prs2 : _T_186 ? issue_slots_12_out_uop_prs2 : issue_slots_11_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_prs1 = _T_187 ? issue_slots_13_out_uop_prs1 : _T_186 ? issue_slots_12_out_uop_prs1 : issue_slots_11_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_pdst = _T_187 ? issue_slots_13_out_uop_pdst : _T_186 ? issue_slots_12_out_uop_pdst : issue_slots_11_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_rxq_idx = _T_187 ? issue_slots_13_out_uop_rxq_idx : _T_186 ? issue_slots_12_out_uop_rxq_idx : issue_slots_11_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_stq_idx = _T_187 ? issue_slots_13_out_uop_stq_idx : _T_186 ? issue_slots_12_out_uop_stq_idx : issue_slots_11_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ldq_idx = _T_187 ? issue_slots_13_out_uop_ldq_idx : _T_186 ? issue_slots_12_out_uop_ldq_idx : issue_slots_11_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_rob_idx = _T_187 ? issue_slots_13_out_uop_rob_idx : _T_186 ? issue_slots_12_out_uop_rob_idx : issue_slots_11_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_vec = _T_187 ? issue_slots_13_out_uop_fp_ctrl_vec : _T_186 ? issue_slots_12_out_uop_fp_ctrl_vec : issue_slots_11_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_wflags = _T_187 ? issue_slots_13_out_uop_fp_ctrl_wflags : _T_186 ? issue_slots_12_out_uop_fp_ctrl_wflags : issue_slots_11_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_sqrt = _T_187 ? issue_slots_13_out_uop_fp_ctrl_sqrt : _T_186 ? issue_slots_12_out_uop_fp_ctrl_sqrt : issue_slots_11_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_div = _T_187 ? issue_slots_13_out_uop_fp_ctrl_div : _T_186 ? issue_slots_12_out_uop_fp_ctrl_div : issue_slots_11_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_fma = _T_187 ? issue_slots_13_out_uop_fp_ctrl_fma : _T_186 ? issue_slots_12_out_uop_fp_ctrl_fma : issue_slots_11_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_fastpipe = _T_187 ? issue_slots_13_out_uop_fp_ctrl_fastpipe : _T_186 ? issue_slots_12_out_uop_fp_ctrl_fastpipe : issue_slots_11_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_toint = _T_187 ? issue_slots_13_out_uop_fp_ctrl_toint : _T_186 ? issue_slots_12_out_uop_fp_ctrl_toint : issue_slots_11_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_fromint = _T_187 ? issue_slots_13_out_uop_fp_ctrl_fromint : _T_186 ? issue_slots_12_out_uop_fp_ctrl_fromint : issue_slots_11_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_typeTagOut = _T_187 ? issue_slots_13_out_uop_fp_ctrl_typeTagOut : _T_186 ? issue_slots_12_out_uop_fp_ctrl_typeTagOut : issue_slots_11_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_typeTagIn = _T_187 ? issue_slots_13_out_uop_fp_ctrl_typeTagIn : _T_186 ? issue_slots_12_out_uop_fp_ctrl_typeTagIn : issue_slots_11_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_swap23 = _T_187 ? issue_slots_13_out_uop_fp_ctrl_swap23 : _T_186 ? issue_slots_12_out_uop_fp_ctrl_swap23 : issue_slots_11_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_swap12 = _T_187 ? issue_slots_13_out_uop_fp_ctrl_swap12 : _T_186 ? issue_slots_12_out_uop_fp_ctrl_swap12 : issue_slots_11_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_ren3 = _T_187 ? issue_slots_13_out_uop_fp_ctrl_ren3 : _T_186 ? issue_slots_12_out_uop_fp_ctrl_ren3 : issue_slots_11_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_ren2 = _T_187 ? issue_slots_13_out_uop_fp_ctrl_ren2 : _T_186 ? issue_slots_12_out_uop_fp_ctrl_ren2 : issue_slots_11_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_ren1 = _T_187 ? issue_slots_13_out_uop_fp_ctrl_ren1 : _T_186 ? issue_slots_12_out_uop_fp_ctrl_ren1 : issue_slots_11_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_wen = _T_187 ? issue_slots_13_out_uop_fp_ctrl_wen : _T_186 ? issue_slots_12_out_uop_fp_ctrl_wen : issue_slots_11_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fp_ctrl_ldst = _T_187 ? issue_slots_13_out_uop_fp_ctrl_ldst : _T_186 ? issue_slots_12_out_uop_fp_ctrl_ldst : issue_slots_11_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_op2_sel = _T_187 ? issue_slots_13_out_uop_op2_sel : _T_186 ? issue_slots_12_out_uop_op2_sel : issue_slots_11_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_op1_sel = _T_187 ? issue_slots_13_out_uop_op1_sel : _T_186 ? issue_slots_12_out_uop_op1_sel : issue_slots_11_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_imm_packed = _T_187 ? issue_slots_13_out_uop_imm_packed : _T_186 ? issue_slots_12_out_uop_imm_packed : issue_slots_11_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_pimm = _T_187 ? issue_slots_13_out_uop_pimm : _T_186 ? issue_slots_12_out_uop_pimm : issue_slots_11_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_imm_sel = _T_187 ? issue_slots_13_out_uop_imm_sel : _T_186 ? issue_slots_12_out_uop_imm_sel : issue_slots_11_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_imm_rename = _T_187 ? issue_slots_13_out_uop_imm_rename : _T_186 ? issue_slots_12_out_uop_imm_rename : issue_slots_11_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_taken = _T_187 ? issue_slots_13_out_uop_taken : _T_186 ? issue_slots_12_out_uop_taken : issue_slots_11_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_pc_lob = _T_187 ? issue_slots_13_out_uop_pc_lob : _T_186 ? issue_slots_12_out_uop_pc_lob : issue_slots_11_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_edge_inst = _T_187 ? issue_slots_13_out_uop_edge_inst : _T_186 ? issue_slots_12_out_uop_edge_inst : issue_slots_11_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_ftq_idx = _T_187 ? issue_slots_13_out_uop_ftq_idx : _T_186 ? issue_slots_12_out_uop_ftq_idx : issue_slots_11_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_mov = _T_187 ? issue_slots_13_out_uop_is_mov : _T_186 ? issue_slots_12_out_uop_is_mov : issue_slots_11_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_rocc = _T_187 ? issue_slots_13_out_uop_is_rocc : _T_186 ? issue_slots_12_out_uop_is_rocc : issue_slots_11_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_sys_pc2epc = _T_187 ? issue_slots_13_out_uop_is_sys_pc2epc : _T_186 ? issue_slots_12_out_uop_is_sys_pc2epc : issue_slots_11_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_eret = _T_187 ? issue_slots_13_out_uop_is_eret : _T_186 ? issue_slots_12_out_uop_is_eret : issue_slots_11_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_amo = _T_187 ? issue_slots_13_out_uop_is_amo : _T_186 ? issue_slots_12_out_uop_is_amo : issue_slots_11_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_sfence = _T_187 ? issue_slots_13_out_uop_is_sfence : _T_186 ? issue_slots_12_out_uop_is_sfence : issue_slots_11_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_fencei = _T_187 ? issue_slots_13_out_uop_is_fencei : _T_186 ? issue_slots_12_out_uop_is_fencei : issue_slots_11_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_fence = _T_187 ? issue_slots_13_out_uop_is_fence : _T_186 ? issue_slots_12_out_uop_is_fence : issue_slots_11_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_sfb = _T_187 ? issue_slots_13_out_uop_is_sfb : _T_186 ? issue_slots_12_out_uop_is_sfb : issue_slots_11_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_br_type = _T_187 ? issue_slots_13_out_uop_br_type : _T_186 ? issue_slots_12_out_uop_br_type : issue_slots_11_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_br_tag = _T_187 ? issue_slots_13_out_uop_br_tag : _T_186 ? issue_slots_12_out_uop_br_tag : issue_slots_11_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_br_mask = _T_187 ? issue_slots_13_out_uop_br_mask : _T_186 ? issue_slots_12_out_uop_br_mask : issue_slots_11_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_dis_col_sel = _T_187 ? issue_slots_13_out_uop_dis_col_sel : _T_186 ? issue_slots_12_out_uop_dis_col_sel : issue_slots_11_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_p3_bypass_hint = _T_187 ? issue_slots_13_out_uop_iw_p3_bypass_hint : _T_186 ? issue_slots_12_out_uop_iw_p3_bypass_hint : issue_slots_11_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_p2_bypass_hint = _T_187 ? issue_slots_13_out_uop_iw_p2_bypass_hint : _T_186 ? issue_slots_12_out_uop_iw_p2_bypass_hint : issue_slots_11_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_p1_bypass_hint = _T_187 ? issue_slots_13_out_uop_iw_p1_bypass_hint : _T_186 ? issue_slots_12_out_uop_iw_p1_bypass_hint : issue_slots_11_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iw_issued = _T_187 ? issue_slots_13_out_uop_iw_issued : _T_186 ? issue_slots_12_out_uop_iw_issued : issue_slots_11_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_0 = _T_187 ? issue_slots_13_out_uop_fu_code_0 : _T_186 ? issue_slots_12_out_uop_fu_code_0 : issue_slots_11_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_1 = _T_187 ? issue_slots_13_out_uop_fu_code_1 : _T_186 ? issue_slots_12_out_uop_fu_code_1 : issue_slots_11_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_2 = _T_187 ? issue_slots_13_out_uop_fu_code_2 : _T_186 ? issue_slots_12_out_uop_fu_code_2 : issue_slots_11_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_3 = _T_187 ? issue_slots_13_out_uop_fu_code_3 : _T_186 ? issue_slots_12_out_uop_fu_code_3 : issue_slots_11_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_4 = _T_187 ? issue_slots_13_out_uop_fu_code_4 : _T_186 ? issue_slots_12_out_uop_fu_code_4 : issue_slots_11_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_5 = _T_187 ? issue_slots_13_out_uop_fu_code_5 : _T_186 ? issue_slots_12_out_uop_fu_code_5 : issue_slots_11_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_6 = _T_187 ? issue_slots_13_out_uop_fu_code_6 : _T_186 ? issue_slots_12_out_uop_fu_code_6 : issue_slots_11_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_7 = _T_187 ? issue_slots_13_out_uop_fu_code_7 : _T_186 ? issue_slots_12_out_uop_fu_code_7 : issue_slots_11_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_8 = _T_187 ? issue_slots_13_out_uop_fu_code_8 : _T_186 ? issue_slots_12_out_uop_fu_code_8 : issue_slots_11_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_fu_code_9 = _T_187 ? issue_slots_13_out_uop_fu_code_9 : _T_186 ? issue_slots_12_out_uop_fu_code_9 : issue_slots_11_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iq_type_0 = _T_187 ? issue_slots_13_out_uop_iq_type_0 : _T_186 ? issue_slots_12_out_uop_iq_type_0 : issue_slots_11_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iq_type_1 = _T_187 ? issue_slots_13_out_uop_iq_type_1 : _T_186 ? issue_slots_12_out_uop_iq_type_1 : issue_slots_11_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iq_type_2 = _T_187 ? issue_slots_13_out_uop_iq_type_2 : _T_186 ? issue_slots_12_out_uop_iq_type_2 : issue_slots_11_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_iq_type_3 = _T_187 ? issue_slots_13_out_uop_iq_type_3 : _T_186 ? issue_slots_12_out_uop_iq_type_3 : issue_slots_11_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_debug_pc = _T_187 ? issue_slots_13_out_uop_debug_pc : _T_186 ? issue_slots_12_out_uop_debug_pc : issue_slots_11_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_is_rvc = _T_187 ? issue_slots_13_out_uop_is_rvc : _T_186 ? issue_slots_12_out_uop_is_rvc : issue_slots_11_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_debug_inst = _T_187 ? issue_slots_13_out_uop_debug_inst : _T_186 ? issue_slots_12_out_uop_debug_inst : issue_slots_11_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_10_in_uop_bits_inst = _T_187 ? issue_slots_13_out_uop_inst : _T_186 ? issue_slots_12_out_uop_inst : issue_slots_11_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_10_clear_T = \|shamts_oh_10; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_10_clear = _issue_slots_10_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_189 = shamts_oh_13 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_190 = shamts_oh_14 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_11_in_uop_valid = _T_190 ? issue_slots_14_will_be_valid : _T_189 ? issue_slots_13_will_be_valid : shamts_oh_12 == 3'h1 & issue_slots_12_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_11_in_uop_bits_debug_tsrc = _T_190 ? issue_slots_14_out_uop_debug_tsrc : _T_189 ? issue_slots_13_out_uop_debug_tsrc : issue_slots_12_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_debug_fsrc = _T_190 ? issue_slots_14_out_uop_debug_fsrc : _T_189 ? issue_slots_13_out_uop_debug_fsrc : issue_slots_12_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_bp_xcpt_if = _T_190 ? issue_slots_14_out_uop_bp_xcpt_if : _T_189 ? issue_slots_13_out_uop_bp_xcpt_if : issue_slots_12_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_bp_debug_if = _T_190 ? issue_slots_14_out_uop_bp_debug_if : _T_189 ? issue_slots_13_out_uop_bp_debug_if : issue_slots_12_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_xcpt_ma_if = _T_190 ? issue_slots_14_out_uop_xcpt_ma_if : _T_189 ? issue_slots_13_out_uop_xcpt_ma_if : issue_slots_12_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_xcpt_ae_if = _T_190 ? issue_slots_14_out_uop_xcpt_ae_if : _T_189 ? issue_slots_13_out_uop_xcpt_ae_if : issue_slots_12_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_xcpt_pf_if = _T_190 ? issue_slots_14_out_uop_xcpt_pf_if : _T_189 ? issue_slots_13_out_uop_xcpt_pf_if : issue_slots_12_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_typ = _T_190 ? issue_slots_14_out_uop_fp_typ : _T_189 ? issue_slots_13_out_uop_fp_typ : issue_slots_12_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_rm = _T_190 ? issue_slots_14_out_uop_fp_rm : _T_189 ? issue_slots_13_out_uop_fp_rm : issue_slots_12_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_val = _T_190 ? issue_slots_14_out_uop_fp_val : _T_189 ? issue_slots_13_out_uop_fp_val : issue_slots_12_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fcn_op = _T_190 ? issue_slots_14_out_uop_fcn_op : _T_189 ? issue_slots_13_out_uop_fcn_op : issue_slots_12_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fcn_dw = _T_190 ? issue_slots_14_out_uop_fcn_dw : _T_189 ? issue_slots_13_out_uop_fcn_dw : issue_slots_12_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_frs3_en = _T_190 ? issue_slots_14_out_uop_frs3_en : _T_189 ? issue_slots_13_out_uop_frs3_en : issue_slots_12_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs2_rtype = _T_190 ? issue_slots_14_out_uop_lrs2_rtype : _T_189 ? issue_slots_13_out_uop_lrs2_rtype : issue_slots_12_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs1_rtype = _T_190 ? issue_slots_14_out_uop_lrs1_rtype : _T_189 ? issue_slots_13_out_uop_lrs1_rtype : issue_slots_12_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_dst_rtype = _T_190 ? issue_slots_14_out_uop_dst_rtype : _T_189 ? issue_slots_13_out_uop_dst_rtype : issue_slots_12_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs3 = _T_190 ? issue_slots_14_out_uop_lrs3 : _T_189 ? issue_slots_13_out_uop_lrs3 : issue_slots_12_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs2 = _T_190 ? issue_slots_14_out_uop_lrs2 : _T_189 ? issue_slots_13_out_uop_lrs2 : issue_slots_12_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_lrs1 = _T_190 ? issue_slots_14_out_uop_lrs1 : _T_189 ? issue_slots_13_out_uop_lrs1 : issue_slots_12_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ldst = _T_190 ? issue_slots_14_out_uop_ldst : _T_189 ? issue_slots_13_out_uop_ldst : issue_slots_12_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ldst_is_rs1 = _T_190 ? issue_slots_14_out_uop_ldst_is_rs1 : _T_189 ? issue_slots_13_out_uop_ldst_is_rs1 : issue_slots_12_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_csr_cmd = _T_190 ? issue_slots_14_out_uop_csr_cmd : _T_189 ? issue_slots_13_out_uop_csr_cmd : issue_slots_12_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_flush_on_commit = _T_190 ? issue_slots_14_out_uop_flush_on_commit : _T_189 ? issue_slots_13_out_uop_flush_on_commit : issue_slots_12_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_unique = _T_190 ? issue_slots_14_out_uop_is_unique : _T_189 ? issue_slots_13_out_uop_is_unique : issue_slots_12_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_uses_stq = _T_190 ? issue_slots_14_out_uop_uses_stq : _T_189 ? issue_slots_13_out_uop_uses_stq : issue_slots_12_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_uses_ldq = _T_190 ? issue_slots_14_out_uop_uses_ldq : _T_189 ? issue_slots_13_out_uop_uses_ldq : issue_slots_12_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_mem_signed = _T_190 ? issue_slots_14_out_uop_mem_signed : _T_189 ? issue_slots_13_out_uop_mem_signed : issue_slots_12_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_mem_size = _T_190 ? issue_slots_14_out_uop_mem_size : _T_189 ? issue_slots_13_out_uop_mem_size : issue_slots_12_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_mem_cmd = _T_190 ? issue_slots_14_out_uop_mem_cmd : _T_189 ? issue_slots_13_out_uop_mem_cmd : issue_slots_12_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_exc_cause = _T_190 ? issue_slots_14_out_uop_exc_cause : _T_189 ? issue_slots_13_out_uop_exc_cause : issue_slots_12_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_exception = _T_190 ? issue_slots_14_out_uop_exception : _T_189 ? issue_slots_13_out_uop_exception : issue_slots_12_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_stale_pdst = _T_190 ? issue_slots_14_out_uop_stale_pdst : _T_189 ? issue_slots_13_out_uop_stale_pdst : issue_slots_12_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ppred_busy = _T_190 ? issue_slots_14_out_uop_ppred_busy : _T_189 ? issue_slots_13_out_uop_ppred_busy : issue_slots_12_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs3_busy = _T_190 ? issue_slots_14_out_uop_prs3_busy : _T_189 ? issue_slots_13_out_uop_prs3_busy : issue_slots_12_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs2_busy = _T_190 ? issue_slots_14_out_uop_prs2_busy : _T_189 ? issue_slots_13_out_uop_prs2_busy : issue_slots_12_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs1_busy = _T_190 ? issue_slots_14_out_uop_prs1_busy : _T_189 ? issue_slots_13_out_uop_prs1_busy : issue_slots_12_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ppred = _T_190 ? issue_slots_14_out_uop_ppred : _T_189 ? issue_slots_13_out_uop_ppred : issue_slots_12_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs3 = _T_190 ? issue_slots_14_out_uop_prs3 : _T_189 ? issue_slots_13_out_uop_prs3 : issue_slots_12_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs2 = _T_190 ? issue_slots_14_out_uop_prs2 : _T_189 ? issue_slots_13_out_uop_prs2 : issue_slots_12_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_prs1 = _T_190 ? issue_slots_14_out_uop_prs1 : _T_189 ? issue_slots_13_out_uop_prs1 : issue_slots_12_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_pdst = _T_190 ? issue_slots_14_out_uop_pdst : _T_189 ? issue_slots_13_out_uop_pdst : issue_slots_12_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_rxq_idx = _T_190 ? issue_slots_14_out_uop_rxq_idx : _T_189 ? issue_slots_13_out_uop_rxq_idx : issue_slots_12_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_stq_idx = _T_190 ? issue_slots_14_out_uop_stq_idx : _T_189 ? issue_slots_13_out_uop_stq_idx : issue_slots_12_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ldq_idx = _T_190 ? issue_slots_14_out_uop_ldq_idx : _T_189 ? issue_slots_13_out_uop_ldq_idx : issue_slots_12_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_rob_idx = _T_190 ? issue_slots_14_out_uop_rob_idx : _T_189 ? issue_slots_13_out_uop_rob_idx : issue_slots_12_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_vec = _T_190 ? issue_slots_14_out_uop_fp_ctrl_vec : _T_189 ? issue_slots_13_out_uop_fp_ctrl_vec : issue_slots_12_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_wflags = _T_190 ? issue_slots_14_out_uop_fp_ctrl_wflags : _T_189 ? issue_slots_13_out_uop_fp_ctrl_wflags : issue_slots_12_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_sqrt = _T_190 ? issue_slots_14_out_uop_fp_ctrl_sqrt : _T_189 ? issue_slots_13_out_uop_fp_ctrl_sqrt : issue_slots_12_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_div = _T_190 ? issue_slots_14_out_uop_fp_ctrl_div : _T_189 ? issue_slots_13_out_uop_fp_ctrl_div : issue_slots_12_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_fma = _T_190 ? issue_slots_14_out_uop_fp_ctrl_fma : _T_189 ? issue_slots_13_out_uop_fp_ctrl_fma : issue_slots_12_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_fastpipe = _T_190 ? issue_slots_14_out_uop_fp_ctrl_fastpipe : _T_189 ? issue_slots_13_out_uop_fp_ctrl_fastpipe : issue_slots_12_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_toint = _T_190 ? issue_slots_14_out_uop_fp_ctrl_toint : _T_189 ? issue_slots_13_out_uop_fp_ctrl_toint : issue_slots_12_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_fromint = _T_190 ? issue_slots_14_out_uop_fp_ctrl_fromint : _T_189 ? issue_slots_13_out_uop_fp_ctrl_fromint : issue_slots_12_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_typeTagOut = _T_190 ? issue_slots_14_out_uop_fp_ctrl_typeTagOut : _T_189 ? issue_slots_13_out_uop_fp_ctrl_typeTagOut : issue_slots_12_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_typeTagIn = _T_190 ? issue_slots_14_out_uop_fp_ctrl_typeTagIn : _T_189 ? issue_slots_13_out_uop_fp_ctrl_typeTagIn : issue_slots_12_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_swap23 = _T_190 ? issue_slots_14_out_uop_fp_ctrl_swap23 : _T_189 ? issue_slots_13_out_uop_fp_ctrl_swap23 : issue_slots_12_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_swap12 = _T_190 ? issue_slots_14_out_uop_fp_ctrl_swap12 : _T_189 ? issue_slots_13_out_uop_fp_ctrl_swap12 : issue_slots_12_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_ren3 = _T_190 ? issue_slots_14_out_uop_fp_ctrl_ren3 : _T_189 ? issue_slots_13_out_uop_fp_ctrl_ren3 : issue_slots_12_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_ren2 = _T_190 ? issue_slots_14_out_uop_fp_ctrl_ren2 : _T_189 ? issue_slots_13_out_uop_fp_ctrl_ren2 : issue_slots_12_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_ren1 = _T_190 ? issue_slots_14_out_uop_fp_ctrl_ren1 : _T_189 ? issue_slots_13_out_uop_fp_ctrl_ren1 : issue_slots_12_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_wen = _T_190 ? issue_slots_14_out_uop_fp_ctrl_wen : _T_189 ? issue_slots_13_out_uop_fp_ctrl_wen : issue_slots_12_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fp_ctrl_ldst = _T_190 ? issue_slots_14_out_uop_fp_ctrl_ldst : _T_189 ? issue_slots_13_out_uop_fp_ctrl_ldst : issue_slots_12_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_op2_sel = _T_190 ? issue_slots_14_out_uop_op2_sel : _T_189 ? issue_slots_13_out_uop_op2_sel : issue_slots_12_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_op1_sel = _T_190 ? issue_slots_14_out_uop_op1_sel : _T_189 ? issue_slots_13_out_uop_op1_sel : issue_slots_12_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_imm_packed = _T_190 ? issue_slots_14_out_uop_imm_packed : _T_189 ? issue_slots_13_out_uop_imm_packed : issue_slots_12_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_pimm = _T_190 ? issue_slots_14_out_uop_pimm : _T_189 ? issue_slots_13_out_uop_pimm : issue_slots_12_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_imm_sel = _T_190 ? issue_slots_14_out_uop_imm_sel : _T_189 ? issue_slots_13_out_uop_imm_sel : issue_slots_12_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_imm_rename = _T_190 ? issue_slots_14_out_uop_imm_rename : _T_189 ? issue_slots_13_out_uop_imm_rename : issue_slots_12_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_taken = _T_190 ? issue_slots_14_out_uop_taken : _T_189 ? issue_slots_13_out_uop_taken : issue_slots_12_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_pc_lob = _T_190 ? issue_slots_14_out_uop_pc_lob : _T_189 ? issue_slots_13_out_uop_pc_lob : issue_slots_12_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_edge_inst = _T_190 ? issue_slots_14_out_uop_edge_inst : _T_189 ? issue_slots_13_out_uop_edge_inst : issue_slots_12_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_ftq_idx = _T_190 ? issue_slots_14_out_uop_ftq_idx : _T_189 ? issue_slots_13_out_uop_ftq_idx : issue_slots_12_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_mov = _T_190 ? issue_slots_14_out_uop_is_mov : _T_189 ? issue_slots_13_out_uop_is_mov : issue_slots_12_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_rocc = _T_190 ? issue_slots_14_out_uop_is_rocc : _T_189 ? issue_slots_13_out_uop_is_rocc : issue_slots_12_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_sys_pc2epc = _T_190 ? issue_slots_14_out_uop_is_sys_pc2epc : _T_189 ? issue_slots_13_out_uop_is_sys_pc2epc : issue_slots_12_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_eret = _T_190 ? issue_slots_14_out_uop_is_eret : _T_189 ? issue_slots_13_out_uop_is_eret : issue_slots_12_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_amo = _T_190 ? issue_slots_14_out_uop_is_amo : _T_189 ? issue_slots_13_out_uop_is_amo : issue_slots_12_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_sfence = _T_190 ? issue_slots_14_out_uop_is_sfence : _T_189 ? issue_slots_13_out_uop_is_sfence : issue_slots_12_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_fencei = _T_190 ? issue_slots_14_out_uop_is_fencei : _T_189 ? issue_slots_13_out_uop_is_fencei : issue_slots_12_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_fence = _T_190 ? issue_slots_14_out_uop_is_fence : _T_189 ? issue_slots_13_out_uop_is_fence : issue_slots_12_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_sfb = _T_190 ? issue_slots_14_out_uop_is_sfb : _T_189 ? issue_slots_13_out_uop_is_sfb : issue_slots_12_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_br_type = _T_190 ? issue_slots_14_out_uop_br_type : _T_189 ? issue_slots_13_out_uop_br_type : issue_slots_12_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_br_tag = _T_190 ? issue_slots_14_out_uop_br_tag : _T_189 ? issue_slots_13_out_uop_br_tag : issue_slots_12_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_br_mask = _T_190 ? issue_slots_14_out_uop_br_mask : _T_189 ? issue_slots_13_out_uop_br_mask : issue_slots_12_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_dis_col_sel = _T_190 ? issue_slots_14_out_uop_dis_col_sel : _T_189 ? issue_slots_13_out_uop_dis_col_sel : issue_slots_12_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_p3_bypass_hint = _T_190 ? issue_slots_14_out_uop_iw_p3_bypass_hint : _T_189 ? issue_slots_13_out_uop_iw_p3_bypass_hint : issue_slots_12_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_p2_bypass_hint = _T_190 ? issue_slots_14_out_uop_iw_p2_bypass_hint : _T_189 ? issue_slots_13_out_uop_iw_p2_bypass_hint : issue_slots_12_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_p1_bypass_hint = _T_190 ? issue_slots_14_out_uop_iw_p1_bypass_hint : _T_189 ? issue_slots_13_out_uop_iw_p1_bypass_hint : issue_slots_12_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iw_issued = _T_190 ? issue_slots_14_out_uop_iw_issued : _T_189 ? issue_slots_13_out_uop_iw_issued : issue_slots_12_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_0 = _T_190 ? issue_slots_14_out_uop_fu_code_0 : _T_189 ? issue_slots_13_out_uop_fu_code_0 : issue_slots_12_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_1 = _T_190 ? issue_slots_14_out_uop_fu_code_1 : _T_189 ? issue_slots_13_out_uop_fu_code_1 : issue_slots_12_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_2 = _T_190 ? issue_slots_14_out_uop_fu_code_2 : _T_189 ? issue_slots_13_out_uop_fu_code_2 : issue_slots_12_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_3 = _T_190 ? issue_slots_14_out_uop_fu_code_3 : _T_189 ? issue_slots_13_out_uop_fu_code_3 : issue_slots_12_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_4 = _T_190 ? issue_slots_14_out_uop_fu_code_4 : _T_189 ? issue_slots_13_out_uop_fu_code_4 : issue_slots_12_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_5 = _T_190 ? issue_slots_14_out_uop_fu_code_5 : _T_189 ? issue_slots_13_out_uop_fu_code_5 : issue_slots_12_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_6 = _T_190 ? issue_slots_14_out_uop_fu_code_6 : _T_189 ? issue_slots_13_out_uop_fu_code_6 : issue_slots_12_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_7 = _T_190 ? issue_slots_14_out_uop_fu_code_7 : _T_189 ? issue_slots_13_out_uop_fu_code_7 : issue_slots_12_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_8 = _T_190 ? issue_slots_14_out_uop_fu_code_8 : _T_189 ? issue_slots_13_out_uop_fu_code_8 : issue_slots_12_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_fu_code_9 = _T_190 ? issue_slots_14_out_uop_fu_code_9 : _T_189 ? issue_slots_13_out_uop_fu_code_9 : issue_slots_12_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iq_type_0 = _T_190 ? issue_slots_14_out_uop_iq_type_0 : _T_189 ? issue_slots_13_out_uop_iq_type_0 : issue_slots_12_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iq_type_1 = _T_190 ? issue_slots_14_out_uop_iq_type_1 : _T_189 ? issue_slots_13_out_uop_iq_type_1 : issue_slots_12_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iq_type_2 = _T_190 ? issue_slots_14_out_uop_iq_type_2 : _T_189 ? issue_slots_13_out_uop_iq_type_2 : issue_slots_12_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_iq_type_3 = _T_190 ? issue_slots_14_out_uop_iq_type_3 : _T_189 ? issue_slots_13_out_uop_iq_type_3 : issue_slots_12_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_debug_pc = _T_190 ? issue_slots_14_out_uop_debug_pc : _T_189 ? issue_slots_13_out_uop_debug_pc : issue_slots_12_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_is_rvc = _T_190 ? issue_slots_14_out_uop_is_rvc : _T_189 ? issue_slots_13_out_uop_is_rvc : issue_slots_12_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_debug_inst = _T_190 ? issue_slots_14_out_uop_debug_inst : _T_189 ? issue_slots_13_out_uop_debug_inst : issue_slots_12_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_11_in_uop_bits_inst = _T_190 ? issue_slots_14_out_uop_inst : _T_189 ? issue_slots_13_out_uop_inst : issue_slots_12_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_11_clear_T = \|shamts_oh_11; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_11_clear = _issue_slots_11_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_192 = shamts_oh_14 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_193 = shamts_oh_15 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_12_in_uop_valid = _T_193 ? issue_slots_15_will_be_valid : _T_192 ? issue_slots_14_will_be_valid : shamts_oh_13 == 3'h1 & issue_slots_13_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_12_in_uop_bits_debug_tsrc = _T_193 ? issue_slots_15_out_uop_debug_tsrc : _T_192 ? issue_slots_14_out_uop_debug_tsrc : issue_slots_13_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_debug_fsrc = _T_193 ? issue_slots_15_out_uop_debug_fsrc : _T_192 ? issue_slots_14_out_uop_debug_fsrc : issue_slots_13_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_bp_xcpt_if = _T_193 ? issue_slots_15_out_uop_bp_xcpt_if : _T_192 ? issue_slots_14_out_uop_bp_xcpt_if : issue_slots_13_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_bp_debug_if = _T_193 ? issue_slots_15_out_uop_bp_debug_if : _T_192 ? issue_slots_14_out_uop_bp_debug_if : issue_slots_13_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_xcpt_ma_if = _T_193 ? issue_slots_15_out_uop_xcpt_ma_if : _T_192 ? issue_slots_14_out_uop_xcpt_ma_if : issue_slots_13_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_xcpt_ae_if = _T_193 ? issue_slots_15_out_uop_xcpt_ae_if : _T_192 ? issue_slots_14_out_uop_xcpt_ae_if : issue_slots_13_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_xcpt_pf_if = _T_193 ? issue_slots_15_out_uop_xcpt_pf_if : _T_192 ? issue_slots_14_out_uop_xcpt_pf_if : issue_slots_13_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_typ = _T_193 ? issue_slots_15_out_uop_fp_typ : _T_192 ? issue_slots_14_out_uop_fp_typ : issue_slots_13_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_rm = _T_193 ? issue_slots_15_out_uop_fp_rm : _T_192 ? issue_slots_14_out_uop_fp_rm : issue_slots_13_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_val = _T_193 ? issue_slots_15_out_uop_fp_val : _T_192 ? issue_slots_14_out_uop_fp_val : issue_slots_13_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fcn_op = _T_193 ? issue_slots_15_out_uop_fcn_op : _T_192 ? issue_slots_14_out_uop_fcn_op : issue_slots_13_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fcn_dw = _T_193 ? issue_slots_15_out_uop_fcn_dw : _T_192 ? issue_slots_14_out_uop_fcn_dw : issue_slots_13_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_frs3_en = _T_193 ? issue_slots_15_out_uop_frs3_en : _T_192 ? issue_slots_14_out_uop_frs3_en : issue_slots_13_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_lrs2_rtype = _T_193 ? issue_slots_15_out_uop_lrs2_rtype : _T_192 ? issue_slots_14_out_uop_lrs2_rtype : issue_slots_13_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_lrs1_rtype = _T_193 ? issue_slots_15_out_uop_lrs1_rtype : _T_192 ? issue_slots_14_out_uop_lrs1_rtype : issue_slots_13_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_dst_rtype = _T_193 ? issue_slots_15_out_uop_dst_rtype : _T_192 ? issue_slots_14_out_uop_dst_rtype : issue_slots_13_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_lrs3 = _T_193 ? issue_slots_15_out_uop_lrs3 : _T_192 ? issue_slots_14_out_uop_lrs3 : issue_slots_13_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_lrs2 = _T_193 ? issue_slots_15_out_uop_lrs2 : _T_192 ? issue_slots_14_out_uop_lrs2 : issue_slots_13_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_lrs1 = _T_193 ? issue_slots_15_out_uop_lrs1 : _T_192 ? issue_slots_14_out_uop_lrs1 : issue_slots_13_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_ldst = _T_193 ? issue_slots_15_out_uop_ldst : _T_192 ? issue_slots_14_out_uop_ldst : issue_slots_13_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_ldst_is_rs1 = _T_193 ? issue_slots_15_out_uop_ldst_is_rs1 : _T_192 ? issue_slots_14_out_uop_ldst_is_rs1 : issue_slots_13_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_csr_cmd = _T_193 ? issue_slots_15_out_uop_csr_cmd : _T_192 ? issue_slots_14_out_uop_csr_cmd : issue_slots_13_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_flush_on_commit = _T_193 ? issue_slots_15_out_uop_flush_on_commit : _T_192 ? issue_slots_14_out_uop_flush_on_commit : issue_slots_13_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_unique = _T_193 ? issue_slots_15_out_uop_is_unique : _T_192 ? issue_slots_14_out_uop_is_unique : issue_slots_13_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_uses_stq = _T_193 ? issue_slots_15_out_uop_uses_stq : _T_192 ? issue_slots_14_out_uop_uses_stq : issue_slots_13_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_uses_ldq = _T_193 ? issue_slots_15_out_uop_uses_ldq : _T_192 ? issue_slots_14_out_uop_uses_ldq : issue_slots_13_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_mem_signed = _T_193 ? issue_slots_15_out_uop_mem_signed : _T_192 ? issue_slots_14_out_uop_mem_signed : issue_slots_13_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_mem_size = _T_193 ? issue_slots_15_out_uop_mem_size : _T_192 ? issue_slots_14_out_uop_mem_size : issue_slots_13_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_mem_cmd = _T_193 ? issue_slots_15_out_uop_mem_cmd : _T_192 ? issue_slots_14_out_uop_mem_cmd : issue_slots_13_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_exc_cause = _T_193 ? issue_slots_15_out_uop_exc_cause : _T_192 ? issue_slots_14_out_uop_exc_cause : issue_slots_13_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_exception = _T_193 ? issue_slots_15_out_uop_exception : _T_192 ? issue_slots_14_out_uop_exception : issue_slots_13_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_stale_pdst = _T_193 ? issue_slots_15_out_uop_stale_pdst : _T_192 ? issue_slots_14_out_uop_stale_pdst : issue_slots_13_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_ppred_busy = _T_193 ? issue_slots_15_out_uop_ppred_busy : _T_192 ? issue_slots_14_out_uop_ppred_busy : issue_slots_13_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_prs3_busy = _T_193 ? issue_slots_15_out_uop_prs3_busy : _T_192 ? issue_slots_14_out_uop_prs3_busy : issue_slots_13_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_prs2_busy = _T_193 ? issue_slots_15_out_uop_prs2_busy : _T_192 ? issue_slots_14_out_uop_prs2_busy : issue_slots_13_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_prs1_busy = _T_193 ? issue_slots_15_out_uop_prs1_busy : _T_192 ? issue_slots_14_out_uop_prs1_busy : issue_slots_13_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_ppred = _T_193 ? issue_slots_15_out_uop_ppred : _T_192 ? issue_slots_14_out_uop_ppred : issue_slots_13_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_prs3 = _T_193 ? issue_slots_15_out_uop_prs3 : _T_192 ? issue_slots_14_out_uop_prs3 : issue_slots_13_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_prs2 = _T_193 ? issue_slots_15_out_uop_prs2 : _T_192 ? issue_slots_14_out_uop_prs2 : issue_slots_13_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_prs1 = _T_193 ? issue_slots_15_out_uop_prs1 : _T_192 ? issue_slots_14_out_uop_prs1 : issue_slots_13_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_pdst = _T_193 ? issue_slots_15_out_uop_pdst : _T_192 ? issue_slots_14_out_uop_pdst : issue_slots_13_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_rxq_idx = _T_193 ? issue_slots_15_out_uop_rxq_idx : _T_192 ? issue_slots_14_out_uop_rxq_idx : issue_slots_13_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_stq_idx = _T_193 ? issue_slots_15_out_uop_stq_idx : _T_192 ? issue_slots_14_out_uop_stq_idx : issue_slots_13_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_ldq_idx = _T_193 ? issue_slots_15_out_uop_ldq_idx : _T_192 ? issue_slots_14_out_uop_ldq_idx : issue_slots_13_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_rob_idx = _T_193 ? issue_slots_15_out_uop_rob_idx : _T_192 ? issue_slots_14_out_uop_rob_idx : issue_slots_13_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_vec = _T_193 ? issue_slots_15_out_uop_fp_ctrl_vec : _T_192 ? issue_slots_14_out_uop_fp_ctrl_vec : issue_slots_13_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_wflags = _T_193 ? issue_slots_15_out_uop_fp_ctrl_wflags : _T_192 ? issue_slots_14_out_uop_fp_ctrl_wflags : issue_slots_13_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_sqrt = _T_193 ? issue_slots_15_out_uop_fp_ctrl_sqrt : _T_192 ? issue_slots_14_out_uop_fp_ctrl_sqrt : issue_slots_13_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_div = _T_193 ? issue_slots_15_out_uop_fp_ctrl_div : _T_192 ? issue_slots_14_out_uop_fp_ctrl_div : issue_slots_13_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_fma = _T_193 ? issue_slots_15_out_uop_fp_ctrl_fma : _T_192 ? issue_slots_14_out_uop_fp_ctrl_fma : issue_slots_13_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_fastpipe = _T_193 ? issue_slots_15_out_uop_fp_ctrl_fastpipe : _T_192 ? issue_slots_14_out_uop_fp_ctrl_fastpipe : issue_slots_13_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_toint = _T_193 ? issue_slots_15_out_uop_fp_ctrl_toint : _T_192 ? issue_slots_14_out_uop_fp_ctrl_toint : issue_slots_13_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_fromint = _T_193 ? issue_slots_15_out_uop_fp_ctrl_fromint : _T_192 ? issue_slots_14_out_uop_fp_ctrl_fromint : issue_slots_13_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_typeTagOut = _T_193 ? issue_slots_15_out_uop_fp_ctrl_typeTagOut : _T_192 ? issue_slots_14_out_uop_fp_ctrl_typeTagOut : issue_slots_13_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_typeTagIn = _T_193 ? issue_slots_15_out_uop_fp_ctrl_typeTagIn : _T_192 ? issue_slots_14_out_uop_fp_ctrl_typeTagIn : issue_slots_13_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_swap23 = _T_193 ? issue_slots_15_out_uop_fp_ctrl_swap23 : _T_192 ? issue_slots_14_out_uop_fp_ctrl_swap23 : issue_slots_13_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_swap12 = _T_193 ? issue_slots_15_out_uop_fp_ctrl_swap12 : _T_192 ? issue_slots_14_out_uop_fp_ctrl_swap12 : issue_slots_13_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_ren3 = _T_193 ? issue_slots_15_out_uop_fp_ctrl_ren3 : _T_192 ? issue_slots_14_out_uop_fp_ctrl_ren3 : issue_slots_13_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_ren2 = _T_193 ? issue_slots_15_out_uop_fp_ctrl_ren2 : _T_192 ? issue_slots_14_out_uop_fp_ctrl_ren2 : issue_slots_13_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_ren1 = _T_193 ? issue_slots_15_out_uop_fp_ctrl_ren1 : _T_192 ? issue_slots_14_out_uop_fp_ctrl_ren1 : issue_slots_13_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_wen = _T_193 ? issue_slots_15_out_uop_fp_ctrl_wen : _T_192 ? issue_slots_14_out_uop_fp_ctrl_wen : issue_slots_13_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fp_ctrl_ldst = _T_193 ? issue_slots_15_out_uop_fp_ctrl_ldst : _T_192 ? issue_slots_14_out_uop_fp_ctrl_ldst : issue_slots_13_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_op2_sel = _T_193 ? issue_slots_15_out_uop_op2_sel : _T_192 ? issue_slots_14_out_uop_op2_sel : issue_slots_13_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_op1_sel = _T_193 ? issue_slots_15_out_uop_op1_sel : _T_192 ? issue_slots_14_out_uop_op1_sel : issue_slots_13_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_imm_packed = _T_193 ? issue_slots_15_out_uop_imm_packed : _T_192 ? issue_slots_14_out_uop_imm_packed : issue_slots_13_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_pimm = _T_193 ? issue_slots_15_out_uop_pimm : _T_192 ? issue_slots_14_out_uop_pimm : issue_slots_13_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_imm_sel = _T_193 ? issue_slots_15_out_uop_imm_sel : _T_192 ? issue_slots_14_out_uop_imm_sel : issue_slots_13_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_imm_rename = _T_193 ? issue_slots_15_out_uop_imm_rename : _T_192 ? issue_slots_14_out_uop_imm_rename : issue_slots_13_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_taken = _T_193 ? issue_slots_15_out_uop_taken : _T_192 ? issue_slots_14_out_uop_taken : issue_slots_13_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_pc_lob = _T_193 ? issue_slots_15_out_uop_pc_lob : _T_192 ? issue_slots_14_out_uop_pc_lob : issue_slots_13_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_edge_inst = _T_193 ? issue_slots_15_out_uop_edge_inst : _T_192 ? issue_slots_14_out_uop_edge_inst : issue_slots_13_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_ftq_idx = _T_193 ? issue_slots_15_out_uop_ftq_idx : _T_192 ? issue_slots_14_out_uop_ftq_idx : issue_slots_13_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_mov = _T_193 ? issue_slots_15_out_uop_is_mov : _T_192 ? issue_slots_14_out_uop_is_mov : issue_slots_13_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_rocc = _T_193 ? issue_slots_15_out_uop_is_rocc : _T_192 ? issue_slots_14_out_uop_is_rocc : issue_slots_13_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_sys_pc2epc = _T_193 ? issue_slots_15_out_uop_is_sys_pc2epc : _T_192 ? issue_slots_14_out_uop_is_sys_pc2epc : issue_slots_13_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_eret = _T_193 ? issue_slots_15_out_uop_is_eret : _T_192 ? issue_slots_14_out_uop_is_eret : issue_slots_13_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_amo = _T_193 ? issue_slots_15_out_uop_is_amo : _T_192 ? issue_slots_14_out_uop_is_amo : issue_slots_13_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_sfence = _T_193 ? issue_slots_15_out_uop_is_sfence : _T_192 ? issue_slots_14_out_uop_is_sfence : issue_slots_13_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_fencei = _T_193 ? issue_slots_15_out_uop_is_fencei : _T_192 ? issue_slots_14_out_uop_is_fencei : issue_slots_13_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_fence = _T_193 ? issue_slots_15_out_uop_is_fence : _T_192 ? issue_slots_14_out_uop_is_fence : issue_slots_13_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_sfb = _T_193 ? issue_slots_15_out_uop_is_sfb : _T_192 ? issue_slots_14_out_uop_is_sfb : issue_slots_13_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_br_type = _T_193 ? issue_slots_15_out_uop_br_type : _T_192 ? issue_slots_14_out_uop_br_type : issue_slots_13_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_br_tag = _T_193 ? issue_slots_15_out_uop_br_tag : _T_192 ? issue_slots_14_out_uop_br_tag : issue_slots_13_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_br_mask = _T_193 ? issue_slots_15_out_uop_br_mask : _T_192 ? issue_slots_14_out_uop_br_mask : issue_slots_13_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_dis_col_sel = _T_193 ? issue_slots_15_out_uop_dis_col_sel : _T_192 ? issue_slots_14_out_uop_dis_col_sel : issue_slots_13_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iw_p3_bypass_hint = _T_193 ? issue_slots_15_out_uop_iw_p3_bypass_hint : _T_192 ? issue_slots_14_out_uop_iw_p3_bypass_hint : issue_slots_13_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iw_p2_bypass_hint = _T_193 ? issue_slots_15_out_uop_iw_p2_bypass_hint : _T_192 ? issue_slots_14_out_uop_iw_p2_bypass_hint : issue_slots_13_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iw_p1_bypass_hint = _T_193 ? issue_slots_15_out_uop_iw_p1_bypass_hint : _T_192 ? issue_slots_14_out_uop_iw_p1_bypass_hint : issue_slots_13_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iw_issued = _T_193 ? issue_slots_15_out_uop_iw_issued : _T_192 ? issue_slots_14_out_uop_iw_issued : issue_slots_13_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_0 = _T_193 ? issue_slots_15_out_uop_fu_code_0 : _T_192 ? issue_slots_14_out_uop_fu_code_0 : issue_slots_13_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_1 = _T_193 ? issue_slots_15_out_uop_fu_code_1 : _T_192 ? issue_slots_14_out_uop_fu_code_1 : issue_slots_13_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_2 = _T_193 ? issue_slots_15_out_uop_fu_code_2 : _T_192 ? issue_slots_14_out_uop_fu_code_2 : issue_slots_13_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_3 = _T_193 ? issue_slots_15_out_uop_fu_code_3 : _T_192 ? issue_slots_14_out_uop_fu_code_3 : issue_slots_13_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_4 = _T_193 ? issue_slots_15_out_uop_fu_code_4 : _T_192 ? issue_slots_14_out_uop_fu_code_4 : issue_slots_13_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_5 = _T_193 ? issue_slots_15_out_uop_fu_code_5 : _T_192 ? issue_slots_14_out_uop_fu_code_5 : issue_slots_13_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_6 = _T_193 ? issue_slots_15_out_uop_fu_code_6 : _T_192 ? issue_slots_14_out_uop_fu_code_6 : issue_slots_13_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_7 = _T_193 ? issue_slots_15_out_uop_fu_code_7 : _T_192 ? issue_slots_14_out_uop_fu_code_7 : issue_slots_13_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_8 = _T_193 ? issue_slots_15_out_uop_fu_code_8 : _T_192 ? issue_slots_14_out_uop_fu_code_8 : issue_slots_13_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_fu_code_9 = _T_193 ? issue_slots_15_out_uop_fu_code_9 : _T_192 ? issue_slots_14_out_uop_fu_code_9 : issue_slots_13_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iq_type_0 = _T_193 ? issue_slots_15_out_uop_iq_type_0 : _T_192 ? issue_slots_14_out_uop_iq_type_0 : issue_slots_13_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iq_type_1 = _T_193 ? issue_slots_15_out_uop_iq_type_1 : _T_192 ? issue_slots_14_out_uop_iq_type_1 : issue_slots_13_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iq_type_2 = _T_193 ? issue_slots_15_out_uop_iq_type_2 : _T_192 ? issue_slots_14_out_uop_iq_type_2 : issue_slots_13_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_iq_type_3 = _T_193 ? issue_slots_15_out_uop_iq_type_3 : _T_192 ? issue_slots_14_out_uop_iq_type_3 : issue_slots_13_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_debug_pc = _T_193 ? issue_slots_15_out_uop_debug_pc : _T_192 ? issue_slots_14_out_uop_debug_pc : issue_slots_13_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_is_rvc = _T_193 ? issue_slots_15_out_uop_is_rvc : _T_192 ? issue_slots_14_out_uop_is_rvc : issue_slots_13_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_debug_inst = _T_193 ? issue_slots_15_out_uop_debug_inst : _T_192 ? issue_slots_14_out_uop_debug_inst : issue_slots_13_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_12_in_uop_bits_inst = _T_193 ? issue_slots_15_out_uop_inst : _T_192 ? issue_slots_14_out_uop_inst : issue_slots_13_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_12_clear_T = \|shamts_oh_12; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_12_clear = _issue_slots_12_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_195 = shamts_oh_15 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_196 = shamts_oh_16 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_13_in_uop_valid = _T_196 ? issue_slots_16_will_be_valid : _T_195 ? issue_slots_15_will_be_valid : shamts_oh_14 == 3'h1 & issue_slots_14_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_13_in_uop_bits_debug_tsrc = _T_196 ? issue_slots_16_out_uop_debug_tsrc : _T_195 ? issue_slots_15_out_uop_debug_tsrc : issue_slots_14_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_debug_fsrc = _T_196 ? issue_slots_16_out_uop_debug_fsrc : _T_195 ? issue_slots_15_out_uop_debug_fsrc : issue_slots_14_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_bp_xcpt_if = _T_196 ? issue_slots_16_out_uop_bp_xcpt_if : _T_195 ? issue_slots_15_out_uop_bp_xcpt_if : issue_slots_14_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_bp_debug_if = _T_196 ? issue_slots_16_out_uop_bp_debug_if : _T_195 ? issue_slots_15_out_uop_bp_debug_if : issue_slots_14_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_xcpt_ma_if = _T_196 ? issue_slots_16_out_uop_xcpt_ma_if : _T_195 ? issue_slots_15_out_uop_xcpt_ma_if : issue_slots_14_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_xcpt_ae_if = _T_196 ? issue_slots_16_out_uop_xcpt_ae_if : _T_195 ? issue_slots_15_out_uop_xcpt_ae_if : issue_slots_14_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_xcpt_pf_if = _T_196 ? issue_slots_16_out_uop_xcpt_pf_if : _T_195 ? issue_slots_15_out_uop_xcpt_pf_if : issue_slots_14_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_typ = _T_196 ? issue_slots_16_out_uop_fp_typ : _T_195 ? issue_slots_15_out_uop_fp_typ : issue_slots_14_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_rm = _T_196 ? issue_slots_16_out_uop_fp_rm : _T_195 ? issue_slots_15_out_uop_fp_rm : issue_slots_14_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_val = _T_196 ? issue_slots_16_out_uop_fp_val : _T_195 ? issue_slots_15_out_uop_fp_val : issue_slots_14_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fcn_op = _T_196 ? issue_slots_16_out_uop_fcn_op : _T_195 ? issue_slots_15_out_uop_fcn_op : issue_slots_14_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fcn_dw = _T_196 ? issue_slots_16_out_uop_fcn_dw : _T_195 ? issue_slots_15_out_uop_fcn_dw : issue_slots_14_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_frs3_en = _T_196 ? issue_slots_16_out_uop_frs3_en : _T_195 ? issue_slots_15_out_uop_frs3_en : issue_slots_14_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_lrs2_rtype = _T_196 ? issue_slots_16_out_uop_lrs2_rtype : _T_195 ? issue_slots_15_out_uop_lrs2_rtype : issue_slots_14_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_lrs1_rtype = _T_196 ? issue_slots_16_out_uop_lrs1_rtype : _T_195 ? issue_slots_15_out_uop_lrs1_rtype : issue_slots_14_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_dst_rtype = _T_196 ? issue_slots_16_out_uop_dst_rtype : _T_195 ? issue_slots_15_out_uop_dst_rtype : issue_slots_14_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_lrs3 = _T_196 ? issue_slots_16_out_uop_lrs3 : _T_195 ? issue_slots_15_out_uop_lrs3 : issue_slots_14_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_lrs2 = _T_196 ? issue_slots_16_out_uop_lrs2 : _T_195 ? issue_slots_15_out_uop_lrs2 : issue_slots_14_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_lrs1 = _T_196 ? issue_slots_16_out_uop_lrs1 : _T_195 ? issue_slots_15_out_uop_lrs1 : issue_slots_14_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_ldst = _T_196 ? issue_slots_16_out_uop_ldst : _T_195 ? issue_slots_15_out_uop_ldst : issue_slots_14_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_ldst_is_rs1 = _T_196 ? issue_slots_16_out_uop_ldst_is_rs1 : _T_195 ? issue_slots_15_out_uop_ldst_is_rs1 : issue_slots_14_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_csr_cmd = _T_196 ? issue_slots_16_out_uop_csr_cmd : _T_195 ? issue_slots_15_out_uop_csr_cmd : issue_slots_14_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_flush_on_commit = _T_196 ? issue_slots_16_out_uop_flush_on_commit : _T_195 ? issue_slots_15_out_uop_flush_on_commit : issue_slots_14_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_unique = _T_196 ? issue_slots_16_out_uop_is_unique : _T_195 ? issue_slots_15_out_uop_is_unique : issue_slots_14_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_uses_stq = _T_196 ? issue_slots_16_out_uop_uses_stq : _T_195 ? issue_slots_15_out_uop_uses_stq : issue_slots_14_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_uses_ldq = _T_196 ? issue_slots_16_out_uop_uses_ldq : _T_195 ? issue_slots_15_out_uop_uses_ldq : issue_slots_14_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_mem_signed = _T_196 ? issue_slots_16_out_uop_mem_signed : _T_195 ? issue_slots_15_out_uop_mem_signed : issue_slots_14_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_mem_size = _T_196 ? issue_slots_16_out_uop_mem_size : _T_195 ? issue_slots_15_out_uop_mem_size : issue_slots_14_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_mem_cmd = _T_196 ? issue_slots_16_out_uop_mem_cmd : _T_195 ? issue_slots_15_out_uop_mem_cmd : issue_slots_14_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_exc_cause = _T_196 ? issue_slots_16_out_uop_exc_cause : _T_195 ? issue_slots_15_out_uop_exc_cause : issue_slots_14_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_exception = _T_196 ? issue_slots_16_out_uop_exception : _T_195 ? issue_slots_15_out_uop_exception : issue_slots_14_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_stale_pdst = _T_196 ? issue_slots_16_out_uop_stale_pdst : _T_195 ? issue_slots_15_out_uop_stale_pdst : issue_slots_14_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_ppred_busy = _T_196 ? issue_slots_16_out_uop_ppred_busy : _T_195 ? issue_slots_15_out_uop_ppred_busy : issue_slots_14_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_prs3_busy = _T_196 ? issue_slots_16_out_uop_prs3_busy : _T_195 ? issue_slots_15_out_uop_prs3_busy : issue_slots_14_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_prs2_busy = _T_196 ? issue_slots_16_out_uop_prs2_busy : _T_195 ? issue_slots_15_out_uop_prs2_busy : issue_slots_14_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_prs1_busy = _T_196 ? issue_slots_16_out_uop_prs1_busy : _T_195 ? issue_slots_15_out_uop_prs1_busy : issue_slots_14_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_ppred = _T_196 ? issue_slots_16_out_uop_ppred : _T_195 ? issue_slots_15_out_uop_ppred : issue_slots_14_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_prs3 = _T_196 ? issue_slots_16_out_uop_prs3 : _T_195 ? issue_slots_15_out_uop_prs3 : issue_slots_14_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_prs2 = _T_196 ? issue_slots_16_out_uop_prs2 : _T_195 ? issue_slots_15_out_uop_prs2 : issue_slots_14_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_prs1 = _T_196 ? issue_slots_16_out_uop_prs1 : _T_195 ? issue_slots_15_out_uop_prs1 : issue_slots_14_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_pdst = _T_196 ? issue_slots_16_out_uop_pdst : _T_195 ? issue_slots_15_out_uop_pdst : issue_slots_14_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_rxq_idx = _T_196 ? issue_slots_16_out_uop_rxq_idx : _T_195 ? issue_slots_15_out_uop_rxq_idx : issue_slots_14_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_stq_idx = _T_196 ? issue_slots_16_out_uop_stq_idx : _T_195 ? issue_slots_15_out_uop_stq_idx : issue_slots_14_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_ldq_idx = _T_196 ? issue_slots_16_out_uop_ldq_idx : _T_195 ? issue_slots_15_out_uop_ldq_idx : issue_slots_14_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_rob_idx = _T_196 ? issue_slots_16_out_uop_rob_idx : _T_195 ? issue_slots_15_out_uop_rob_idx : issue_slots_14_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_vec = _T_196 ? issue_slots_16_out_uop_fp_ctrl_vec : _T_195 ? issue_slots_15_out_uop_fp_ctrl_vec : issue_slots_14_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_wflags = _T_196 ? issue_slots_16_out_uop_fp_ctrl_wflags : _T_195 ? issue_slots_15_out_uop_fp_ctrl_wflags : issue_slots_14_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_sqrt = _T_196 ? issue_slots_16_out_uop_fp_ctrl_sqrt : _T_195 ? issue_slots_15_out_uop_fp_ctrl_sqrt : issue_slots_14_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_div = _T_196 ? issue_slots_16_out_uop_fp_ctrl_div : _T_195 ? issue_slots_15_out_uop_fp_ctrl_div : issue_slots_14_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_fma = _T_196 ? issue_slots_16_out_uop_fp_ctrl_fma : _T_195 ? issue_slots_15_out_uop_fp_ctrl_fma : issue_slots_14_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_fastpipe = _T_196 ? issue_slots_16_out_uop_fp_ctrl_fastpipe : _T_195 ? issue_slots_15_out_uop_fp_ctrl_fastpipe : issue_slots_14_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_toint = _T_196 ? issue_slots_16_out_uop_fp_ctrl_toint : _T_195 ? issue_slots_15_out_uop_fp_ctrl_toint : issue_slots_14_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_fromint = _T_196 ? issue_slots_16_out_uop_fp_ctrl_fromint : _T_195 ? issue_slots_15_out_uop_fp_ctrl_fromint : issue_slots_14_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_typeTagOut = _T_196 ? issue_slots_16_out_uop_fp_ctrl_typeTagOut : _T_195 ? issue_slots_15_out_uop_fp_ctrl_typeTagOut : issue_slots_14_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_typeTagIn = _T_196 ? issue_slots_16_out_uop_fp_ctrl_typeTagIn : _T_195 ? issue_slots_15_out_uop_fp_ctrl_typeTagIn : issue_slots_14_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_swap23 = _T_196 ? issue_slots_16_out_uop_fp_ctrl_swap23 : _T_195 ? issue_slots_15_out_uop_fp_ctrl_swap23 : issue_slots_14_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_swap12 = _T_196 ? issue_slots_16_out_uop_fp_ctrl_swap12 : _T_195 ? issue_slots_15_out_uop_fp_ctrl_swap12 : issue_slots_14_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_ren3 = _T_196 ? issue_slots_16_out_uop_fp_ctrl_ren3 : _T_195 ? issue_slots_15_out_uop_fp_ctrl_ren3 : issue_slots_14_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_ren2 = _T_196 ? issue_slots_16_out_uop_fp_ctrl_ren2 : _T_195 ? issue_slots_15_out_uop_fp_ctrl_ren2 : issue_slots_14_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_ren1 = _T_196 ? issue_slots_16_out_uop_fp_ctrl_ren1 : _T_195 ? issue_slots_15_out_uop_fp_ctrl_ren1 : issue_slots_14_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_wen = _T_196 ? issue_slots_16_out_uop_fp_ctrl_wen : _T_195 ? issue_slots_15_out_uop_fp_ctrl_wen : issue_slots_14_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fp_ctrl_ldst = _T_196 ? issue_slots_16_out_uop_fp_ctrl_ldst : _T_195 ? issue_slots_15_out_uop_fp_ctrl_ldst : issue_slots_14_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_op2_sel = _T_196 ? issue_slots_16_out_uop_op2_sel : _T_195 ? issue_slots_15_out_uop_op2_sel : issue_slots_14_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_op1_sel = _T_196 ? issue_slots_16_out_uop_op1_sel : _T_195 ? issue_slots_15_out_uop_op1_sel : issue_slots_14_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_imm_packed = _T_196 ? issue_slots_16_out_uop_imm_packed : _T_195 ? issue_slots_15_out_uop_imm_packed : issue_slots_14_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_pimm = _T_196 ? issue_slots_16_out_uop_pimm : _T_195 ? issue_slots_15_out_uop_pimm : issue_slots_14_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_imm_sel = _T_196 ? issue_slots_16_out_uop_imm_sel : _T_195 ? issue_slots_15_out_uop_imm_sel : issue_slots_14_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_imm_rename = _T_196 ? issue_slots_16_out_uop_imm_rename : _T_195 ? issue_slots_15_out_uop_imm_rename : issue_slots_14_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_taken = _T_196 ? issue_slots_16_out_uop_taken : _T_195 ? issue_slots_15_out_uop_taken : issue_slots_14_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_pc_lob = _T_196 ? issue_slots_16_out_uop_pc_lob : _T_195 ? issue_slots_15_out_uop_pc_lob : issue_slots_14_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_edge_inst = _T_196 ? issue_slots_16_out_uop_edge_inst : _T_195 ? issue_slots_15_out_uop_edge_inst : issue_slots_14_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_ftq_idx = _T_196 ? issue_slots_16_out_uop_ftq_idx : _T_195 ? issue_slots_15_out_uop_ftq_idx : issue_slots_14_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_mov = _T_196 ? issue_slots_16_out_uop_is_mov : _T_195 ? issue_slots_15_out_uop_is_mov : issue_slots_14_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_rocc = _T_196 ? issue_slots_16_out_uop_is_rocc : _T_195 ? issue_slots_15_out_uop_is_rocc : issue_slots_14_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_sys_pc2epc = _T_196 ? issue_slots_16_out_uop_is_sys_pc2epc : _T_195 ? issue_slots_15_out_uop_is_sys_pc2epc : issue_slots_14_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_eret = _T_196 ? issue_slots_16_out_uop_is_eret : _T_195 ? issue_slots_15_out_uop_is_eret : issue_slots_14_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_amo = _T_196 ? issue_slots_16_out_uop_is_amo : _T_195 ? issue_slots_15_out_uop_is_amo : issue_slots_14_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_sfence = _T_196 ? issue_slots_16_out_uop_is_sfence : _T_195 ? issue_slots_15_out_uop_is_sfence : issue_slots_14_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_fencei = _T_196 ? issue_slots_16_out_uop_is_fencei : _T_195 ? issue_slots_15_out_uop_is_fencei : issue_slots_14_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_fence = _T_196 ? issue_slots_16_out_uop_is_fence : _T_195 ? issue_slots_15_out_uop_is_fence : issue_slots_14_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_sfb = _T_196 ? issue_slots_16_out_uop_is_sfb : _T_195 ? issue_slots_15_out_uop_is_sfb : issue_slots_14_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_br_type = _T_196 ? issue_slots_16_out_uop_br_type : _T_195 ? issue_slots_15_out_uop_br_type : issue_slots_14_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_br_tag = _T_196 ? issue_slots_16_out_uop_br_tag : _T_195 ? issue_slots_15_out_uop_br_tag : issue_slots_14_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_br_mask = _T_196 ? issue_slots_16_out_uop_br_mask : _T_195 ? issue_slots_15_out_uop_br_mask : issue_slots_14_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_dis_col_sel = _T_196 ? issue_slots_16_out_uop_dis_col_sel : _T_195 ? issue_slots_15_out_uop_dis_col_sel : issue_slots_14_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iw_p3_bypass_hint = _T_196 ? issue_slots_16_out_uop_iw_p3_bypass_hint : _T_195 ? issue_slots_15_out_uop_iw_p3_bypass_hint : issue_slots_14_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iw_p2_bypass_hint = _T_196 ? issue_slots_16_out_uop_iw_p2_bypass_hint : _T_195 ? issue_slots_15_out_uop_iw_p2_bypass_hint : issue_slots_14_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iw_p1_bypass_hint = _T_196 ? issue_slots_16_out_uop_iw_p1_bypass_hint : _T_195 ? issue_slots_15_out_uop_iw_p1_bypass_hint : issue_slots_14_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iw_issued = _T_196 ? issue_slots_16_out_uop_iw_issued : _T_195 ? issue_slots_15_out_uop_iw_issued : issue_slots_14_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_0 = _T_196 ? issue_slots_16_out_uop_fu_code_0 : _T_195 ? issue_slots_15_out_uop_fu_code_0 : issue_slots_14_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_1 = _T_196 ? issue_slots_16_out_uop_fu_code_1 : _T_195 ? issue_slots_15_out_uop_fu_code_1 : issue_slots_14_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_2 = _T_196 ? issue_slots_16_out_uop_fu_code_2 : _T_195 ? issue_slots_15_out_uop_fu_code_2 : issue_slots_14_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_3 = _T_196 ? issue_slots_16_out_uop_fu_code_3 : _T_195 ? issue_slots_15_out_uop_fu_code_3 : issue_slots_14_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_4 = _T_196 ? issue_slots_16_out_uop_fu_code_4 : _T_195 ? issue_slots_15_out_uop_fu_code_4 : issue_slots_14_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_5 = _T_196 ? issue_slots_16_out_uop_fu_code_5 : _T_195 ? issue_slots_15_out_uop_fu_code_5 : issue_slots_14_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_6 = _T_196 ? issue_slots_16_out_uop_fu_code_6 : _T_195 ? issue_slots_15_out_uop_fu_code_6 : issue_slots_14_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_7 = _T_196 ? issue_slots_16_out_uop_fu_code_7 : _T_195 ? issue_slots_15_out_uop_fu_code_7 : issue_slots_14_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_8 = _T_196 ? issue_slots_16_out_uop_fu_code_8 : _T_195 ? issue_slots_15_out_uop_fu_code_8 : issue_slots_14_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_fu_code_9 = _T_196 ? issue_slots_16_out_uop_fu_code_9 : _T_195 ? issue_slots_15_out_uop_fu_code_9 : issue_slots_14_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iq_type_0 = _T_196 ? issue_slots_16_out_uop_iq_type_0 : _T_195 ? issue_slots_15_out_uop_iq_type_0 : issue_slots_14_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iq_type_1 = _T_196 ? issue_slots_16_out_uop_iq_type_1 : _T_195 ? issue_slots_15_out_uop_iq_type_1 : issue_slots_14_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iq_type_2 = _T_196 ? issue_slots_16_out_uop_iq_type_2 : _T_195 ? issue_slots_15_out_uop_iq_type_2 : issue_slots_14_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_iq_type_3 = _T_196 ? issue_slots_16_out_uop_iq_type_3 : _T_195 ? issue_slots_15_out_uop_iq_type_3 : issue_slots_14_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_debug_pc = _T_196 ? issue_slots_16_out_uop_debug_pc : _T_195 ? issue_slots_15_out_uop_debug_pc : issue_slots_14_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_is_rvc = _T_196 ? issue_slots_16_out_uop_is_rvc : _T_195 ? issue_slots_15_out_uop_is_rvc : issue_slots_14_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_debug_inst = _T_196 ? issue_slots_16_out_uop_debug_inst : _T_195 ? issue_slots_15_out_uop_debug_inst : issue_slots_14_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_13_in_uop_bits_inst = _T_196 ? issue_slots_16_out_uop_inst : _T_195 ? issue_slots_15_out_uop_inst : issue_slots_14_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_13_clear_T = \|shamts_oh_13; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_13_clear = _issue_slots_13_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_198 = shamts_oh_16 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_199 = shamts_oh_17 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_14_in_uop_valid = _T_199 ? issue_slots_17_will_be_valid : _T_198 ? issue_slots_16_will_be_valid : shamts_oh_15 == 3'h1 & issue_slots_15_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_14_in_uop_bits_debug_tsrc = _T_199 ? issue_slots_17_out_uop_debug_tsrc : _T_198 ? issue_slots_16_out_uop_debug_tsrc : issue_slots_15_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_debug_fsrc = _T_199 ? issue_slots_17_out_uop_debug_fsrc : _T_198 ? issue_slots_16_out_uop_debug_fsrc : issue_slots_15_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_bp_xcpt_if = _T_199 ? issue_slots_17_out_uop_bp_xcpt_if : _T_198 ? issue_slots_16_out_uop_bp_xcpt_if : issue_slots_15_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_bp_debug_if = _T_199 ? issue_slots_17_out_uop_bp_debug_if : _T_198 ? issue_slots_16_out_uop_bp_debug_if : issue_slots_15_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_xcpt_ma_if = _T_199 ? issue_slots_17_out_uop_xcpt_ma_if : _T_198 ? issue_slots_16_out_uop_xcpt_ma_if : issue_slots_15_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_xcpt_ae_if = _T_199 ? issue_slots_17_out_uop_xcpt_ae_if : _T_198 ? issue_slots_16_out_uop_xcpt_ae_if : issue_slots_15_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_xcpt_pf_if = _T_199 ? issue_slots_17_out_uop_xcpt_pf_if : _T_198 ? issue_slots_16_out_uop_xcpt_pf_if : issue_slots_15_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_typ = _T_199 ? issue_slots_17_out_uop_fp_typ : _T_198 ? issue_slots_16_out_uop_fp_typ : issue_slots_15_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_rm = _T_199 ? issue_slots_17_out_uop_fp_rm : _T_198 ? issue_slots_16_out_uop_fp_rm : issue_slots_15_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_val = _T_199 ? issue_slots_17_out_uop_fp_val : _T_198 ? issue_slots_16_out_uop_fp_val : issue_slots_15_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fcn_op = _T_199 ? issue_slots_17_out_uop_fcn_op : _T_198 ? issue_slots_16_out_uop_fcn_op : issue_slots_15_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fcn_dw = _T_199 ? issue_slots_17_out_uop_fcn_dw : _T_198 ? issue_slots_16_out_uop_fcn_dw : issue_slots_15_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_frs3_en = _T_199 ? issue_slots_17_out_uop_frs3_en : _T_198 ? issue_slots_16_out_uop_frs3_en : issue_slots_15_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_lrs2_rtype = _T_199 ? issue_slots_17_out_uop_lrs2_rtype : _T_198 ? issue_slots_16_out_uop_lrs2_rtype : issue_slots_15_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_lrs1_rtype = _T_199 ? issue_slots_17_out_uop_lrs1_rtype : _T_198 ? issue_slots_16_out_uop_lrs1_rtype : issue_slots_15_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_dst_rtype = _T_199 ? issue_slots_17_out_uop_dst_rtype : _T_198 ? issue_slots_16_out_uop_dst_rtype : issue_slots_15_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_lrs3 = _T_199 ? issue_slots_17_out_uop_lrs3 : _T_198 ? issue_slots_16_out_uop_lrs3 : issue_slots_15_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_lrs2 = _T_199 ? issue_slots_17_out_uop_lrs2 : _T_198 ? issue_slots_16_out_uop_lrs2 : issue_slots_15_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_lrs1 = _T_199 ? issue_slots_17_out_uop_lrs1 : _T_198 ? issue_slots_16_out_uop_lrs1 : issue_slots_15_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_ldst = _T_199 ? issue_slots_17_out_uop_ldst : _T_198 ? issue_slots_16_out_uop_ldst : issue_slots_15_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_ldst_is_rs1 = _T_199 ? issue_slots_17_out_uop_ldst_is_rs1 : _T_198 ? issue_slots_16_out_uop_ldst_is_rs1 : issue_slots_15_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_csr_cmd = _T_199 ? issue_slots_17_out_uop_csr_cmd : _T_198 ? issue_slots_16_out_uop_csr_cmd : issue_slots_15_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_flush_on_commit = _T_199 ? issue_slots_17_out_uop_flush_on_commit : _T_198 ? issue_slots_16_out_uop_flush_on_commit : issue_slots_15_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_unique = _T_199 ? issue_slots_17_out_uop_is_unique : _T_198 ? issue_slots_16_out_uop_is_unique : issue_slots_15_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_uses_stq = _T_199 ? issue_slots_17_out_uop_uses_stq : _T_198 ? issue_slots_16_out_uop_uses_stq : issue_slots_15_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_uses_ldq = _T_199 ? issue_slots_17_out_uop_uses_ldq : _T_198 ? issue_slots_16_out_uop_uses_ldq : issue_slots_15_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_mem_signed = _T_199 ? issue_slots_17_out_uop_mem_signed : _T_198 ? issue_slots_16_out_uop_mem_signed : issue_slots_15_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_mem_size = _T_199 ? issue_slots_17_out_uop_mem_size : _T_198 ? issue_slots_16_out_uop_mem_size : issue_slots_15_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_mem_cmd = _T_199 ? issue_slots_17_out_uop_mem_cmd : _T_198 ? issue_slots_16_out_uop_mem_cmd : issue_slots_15_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_exc_cause = _T_199 ? issue_slots_17_out_uop_exc_cause : _T_198 ? issue_slots_16_out_uop_exc_cause : issue_slots_15_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_exception = _T_199 ? issue_slots_17_out_uop_exception : _T_198 ? issue_slots_16_out_uop_exception : issue_slots_15_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_stale_pdst = _T_199 ? issue_slots_17_out_uop_stale_pdst : _T_198 ? issue_slots_16_out_uop_stale_pdst : issue_slots_15_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_ppred_busy = _T_199 ? issue_slots_17_out_uop_ppred_busy : _T_198 ? issue_slots_16_out_uop_ppred_busy : issue_slots_15_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_prs3_busy = _T_199 ? issue_slots_17_out_uop_prs3_busy : _T_198 ? issue_slots_16_out_uop_prs3_busy : issue_slots_15_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_prs2_busy = _T_199 ? issue_slots_17_out_uop_prs2_busy : _T_198 ? issue_slots_16_out_uop_prs2_busy : issue_slots_15_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_prs1_busy = _T_199 ? issue_slots_17_out_uop_prs1_busy : _T_198 ? issue_slots_16_out_uop_prs1_busy : issue_slots_15_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_ppred = _T_199 ? issue_slots_17_out_uop_ppred : _T_198 ? issue_slots_16_out_uop_ppred : issue_slots_15_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_prs3 = _T_199 ? issue_slots_17_out_uop_prs3 : _T_198 ? issue_slots_16_out_uop_prs3 : issue_slots_15_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_prs2 = _T_199 ? issue_slots_17_out_uop_prs2 : _T_198 ? issue_slots_16_out_uop_prs2 : issue_slots_15_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_prs1 = _T_199 ? issue_slots_17_out_uop_prs1 : _T_198 ? issue_slots_16_out_uop_prs1 : issue_slots_15_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_pdst = _T_199 ? issue_slots_17_out_uop_pdst : _T_198 ? issue_slots_16_out_uop_pdst : issue_slots_15_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_rxq_idx = _T_199 ? issue_slots_17_out_uop_rxq_idx : _T_198 ? issue_slots_16_out_uop_rxq_idx : issue_slots_15_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_stq_idx = _T_199 ? issue_slots_17_out_uop_stq_idx : _T_198 ? issue_slots_16_out_uop_stq_idx : issue_slots_15_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_ldq_idx = _T_199 ? issue_slots_17_out_uop_ldq_idx : _T_198 ? issue_slots_16_out_uop_ldq_idx : issue_slots_15_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_rob_idx = _T_199 ? issue_slots_17_out_uop_rob_idx : _T_198 ? issue_slots_16_out_uop_rob_idx : issue_slots_15_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_vec = _T_199 ? issue_slots_17_out_uop_fp_ctrl_vec : _T_198 ? issue_slots_16_out_uop_fp_ctrl_vec : issue_slots_15_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_wflags = _T_199 ? issue_slots_17_out_uop_fp_ctrl_wflags : _T_198 ? issue_slots_16_out_uop_fp_ctrl_wflags : issue_slots_15_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_sqrt = _T_199 ? issue_slots_17_out_uop_fp_ctrl_sqrt : _T_198 ? issue_slots_16_out_uop_fp_ctrl_sqrt : issue_slots_15_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_div = _T_199 ? issue_slots_17_out_uop_fp_ctrl_div : _T_198 ? issue_slots_16_out_uop_fp_ctrl_div : issue_slots_15_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_fma = _T_199 ? issue_slots_17_out_uop_fp_ctrl_fma : _T_198 ? issue_slots_16_out_uop_fp_ctrl_fma : issue_slots_15_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_fastpipe = _T_199 ? issue_slots_17_out_uop_fp_ctrl_fastpipe : _T_198 ? issue_slots_16_out_uop_fp_ctrl_fastpipe : issue_slots_15_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_toint = _T_199 ? issue_slots_17_out_uop_fp_ctrl_toint : _T_198 ? issue_slots_16_out_uop_fp_ctrl_toint : issue_slots_15_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_fromint = _T_199 ? issue_slots_17_out_uop_fp_ctrl_fromint : _T_198 ? issue_slots_16_out_uop_fp_ctrl_fromint : issue_slots_15_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_typeTagOut = _T_199 ? issue_slots_17_out_uop_fp_ctrl_typeTagOut : _T_198 ? issue_slots_16_out_uop_fp_ctrl_typeTagOut : issue_slots_15_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_typeTagIn = _T_199 ? issue_slots_17_out_uop_fp_ctrl_typeTagIn : _T_198 ? issue_slots_16_out_uop_fp_ctrl_typeTagIn : issue_slots_15_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_swap23 = _T_199 ? issue_slots_17_out_uop_fp_ctrl_swap23 : _T_198 ? issue_slots_16_out_uop_fp_ctrl_swap23 : issue_slots_15_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_swap12 = _T_199 ? issue_slots_17_out_uop_fp_ctrl_swap12 : _T_198 ? issue_slots_16_out_uop_fp_ctrl_swap12 : issue_slots_15_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_ren3 = _T_199 ? issue_slots_17_out_uop_fp_ctrl_ren3 : _T_198 ? issue_slots_16_out_uop_fp_ctrl_ren3 : issue_slots_15_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_ren2 = _T_199 ? issue_slots_17_out_uop_fp_ctrl_ren2 : _T_198 ? issue_slots_16_out_uop_fp_ctrl_ren2 : issue_slots_15_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_ren1 = _T_199 ? issue_slots_17_out_uop_fp_ctrl_ren1 : _T_198 ? issue_slots_16_out_uop_fp_ctrl_ren1 : issue_slots_15_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_wen = _T_199 ? issue_slots_17_out_uop_fp_ctrl_wen : _T_198 ? issue_slots_16_out_uop_fp_ctrl_wen : issue_slots_15_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fp_ctrl_ldst = _T_199 ? issue_slots_17_out_uop_fp_ctrl_ldst : _T_198 ? issue_slots_16_out_uop_fp_ctrl_ldst : issue_slots_15_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_op2_sel = _T_199 ? issue_slots_17_out_uop_op2_sel : _T_198 ? issue_slots_16_out_uop_op2_sel : issue_slots_15_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_op1_sel = _T_199 ? issue_slots_17_out_uop_op1_sel : _T_198 ? issue_slots_16_out_uop_op1_sel : issue_slots_15_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_imm_packed = _T_199 ? issue_slots_17_out_uop_imm_packed : _T_198 ? issue_slots_16_out_uop_imm_packed : issue_slots_15_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_pimm = _T_199 ? issue_slots_17_out_uop_pimm : _T_198 ? issue_slots_16_out_uop_pimm : issue_slots_15_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_imm_sel = _T_199 ? issue_slots_17_out_uop_imm_sel : _T_198 ? issue_slots_16_out_uop_imm_sel : issue_slots_15_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_imm_rename = _T_199 ? issue_slots_17_out_uop_imm_rename : _T_198 ? issue_slots_16_out_uop_imm_rename : issue_slots_15_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_taken = _T_199 ? issue_slots_17_out_uop_taken : _T_198 ? issue_slots_16_out_uop_taken : issue_slots_15_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_pc_lob = _T_199 ? issue_slots_17_out_uop_pc_lob : _T_198 ? issue_slots_16_out_uop_pc_lob : issue_slots_15_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_edge_inst = _T_199 ? issue_slots_17_out_uop_edge_inst : _T_198 ? issue_slots_16_out_uop_edge_inst : issue_slots_15_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_ftq_idx = _T_199 ? issue_slots_17_out_uop_ftq_idx : _T_198 ? issue_slots_16_out_uop_ftq_idx : issue_slots_15_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_mov = _T_199 ? issue_slots_17_out_uop_is_mov : _T_198 ? issue_slots_16_out_uop_is_mov : issue_slots_15_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_rocc = _T_199 ? issue_slots_17_out_uop_is_rocc : _T_198 ? issue_slots_16_out_uop_is_rocc : issue_slots_15_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_sys_pc2epc = _T_199 ? issue_slots_17_out_uop_is_sys_pc2epc : _T_198 ? issue_slots_16_out_uop_is_sys_pc2epc : issue_slots_15_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_eret = _T_199 ? issue_slots_17_out_uop_is_eret : _T_198 ? issue_slots_16_out_uop_is_eret : issue_slots_15_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_amo = _T_199 ? issue_slots_17_out_uop_is_amo : _T_198 ? issue_slots_16_out_uop_is_amo : issue_slots_15_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_sfence = _T_199 ? issue_slots_17_out_uop_is_sfence : _T_198 ? issue_slots_16_out_uop_is_sfence : issue_slots_15_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_fencei = _T_199 ? issue_slots_17_out_uop_is_fencei : _T_198 ? issue_slots_16_out_uop_is_fencei : issue_slots_15_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_fence = _T_199 ? issue_slots_17_out_uop_is_fence : _T_198 ? issue_slots_16_out_uop_is_fence : issue_slots_15_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_sfb = _T_199 ? issue_slots_17_out_uop_is_sfb : _T_198 ? issue_slots_16_out_uop_is_sfb : issue_slots_15_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_br_type = _T_199 ? issue_slots_17_out_uop_br_type : _T_198 ? issue_slots_16_out_uop_br_type : issue_slots_15_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_br_tag = _T_199 ? issue_slots_17_out_uop_br_tag : _T_198 ? issue_slots_16_out_uop_br_tag : issue_slots_15_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_br_mask = _T_199 ? issue_slots_17_out_uop_br_mask : _T_198 ? issue_slots_16_out_uop_br_mask : issue_slots_15_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_dis_col_sel = _T_199 ? issue_slots_17_out_uop_dis_col_sel : _T_198 ? issue_slots_16_out_uop_dis_col_sel : issue_slots_15_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iw_p3_bypass_hint = _T_199 ? issue_slots_17_out_uop_iw_p3_bypass_hint : _T_198 ? issue_slots_16_out_uop_iw_p3_bypass_hint : issue_slots_15_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iw_p2_bypass_hint = _T_199 ? issue_slots_17_out_uop_iw_p2_bypass_hint : _T_198 ? issue_slots_16_out_uop_iw_p2_bypass_hint : issue_slots_15_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iw_p1_bypass_hint = _T_199 ? issue_slots_17_out_uop_iw_p1_bypass_hint : _T_198 ? issue_slots_16_out_uop_iw_p1_bypass_hint : issue_slots_15_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iw_issued = _T_199 ? issue_slots_17_out_uop_iw_issued : _T_198 ? issue_slots_16_out_uop_iw_issued : issue_slots_15_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_0 = _T_199 ? issue_slots_17_out_uop_fu_code_0 : _T_198 ? issue_slots_16_out_uop_fu_code_0 : issue_slots_15_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_1 = _T_199 ? issue_slots_17_out_uop_fu_code_1 : _T_198 ? issue_slots_16_out_uop_fu_code_1 : issue_slots_15_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_2 = _T_199 ? issue_slots_17_out_uop_fu_code_2 : _T_198 ? issue_slots_16_out_uop_fu_code_2 : issue_slots_15_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_3 = _T_199 ? issue_slots_17_out_uop_fu_code_3 : _T_198 ? issue_slots_16_out_uop_fu_code_3 : issue_slots_15_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_4 = _T_199 ? issue_slots_17_out_uop_fu_code_4 : _T_198 ? issue_slots_16_out_uop_fu_code_4 : issue_slots_15_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_5 = _T_199 ? issue_slots_17_out_uop_fu_code_5 : _T_198 ? issue_slots_16_out_uop_fu_code_5 : issue_slots_15_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_6 = _T_199 ? issue_slots_17_out_uop_fu_code_6 : _T_198 ? issue_slots_16_out_uop_fu_code_6 : issue_slots_15_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_7 = _T_199 ? issue_slots_17_out_uop_fu_code_7 : _T_198 ? issue_slots_16_out_uop_fu_code_7 : issue_slots_15_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_8 = _T_199 ? issue_slots_17_out_uop_fu_code_8 : _T_198 ? issue_slots_16_out_uop_fu_code_8 : issue_slots_15_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_fu_code_9 = _T_199 ? issue_slots_17_out_uop_fu_code_9 : _T_198 ? issue_slots_16_out_uop_fu_code_9 : issue_slots_15_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iq_type_0 = _T_199 ? issue_slots_17_out_uop_iq_type_0 : _T_198 ? issue_slots_16_out_uop_iq_type_0 : issue_slots_15_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iq_type_1 = _T_199 ? issue_slots_17_out_uop_iq_type_1 : _T_198 ? issue_slots_16_out_uop_iq_type_1 : issue_slots_15_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iq_type_2 = _T_199 ? issue_slots_17_out_uop_iq_type_2 : _T_198 ? issue_slots_16_out_uop_iq_type_2 : issue_slots_15_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_iq_type_3 = _T_199 ? issue_slots_17_out_uop_iq_type_3 : _T_198 ? issue_slots_16_out_uop_iq_type_3 : issue_slots_15_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_debug_pc = _T_199 ? issue_slots_17_out_uop_debug_pc : _T_198 ? issue_slots_16_out_uop_debug_pc : issue_slots_15_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_is_rvc = _T_199 ? issue_slots_17_out_uop_is_rvc : _T_198 ? issue_slots_16_out_uop_is_rvc : issue_slots_15_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_debug_inst = _T_199 ? issue_slots_17_out_uop_debug_inst : _T_198 ? issue_slots_16_out_uop_debug_inst : issue_slots_15_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_14_in_uop_bits_inst = _T_199 ? issue_slots_17_out_uop_inst : _T_198 ? issue_slots_16_out_uop_inst : issue_slots_15_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_14_clear_T = \|shamts_oh_14; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_14_clear = _issue_slots_14_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_201 = shamts_oh_17 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_202 = shamts_oh_18 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_15_in_uop_valid = _T_202 ? issue_slots_18_will_be_valid : _T_201 ? issue_slots_17_will_be_valid : shamts_oh_16 == 3'h1 & issue_slots_16_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_15_in_uop_bits_debug_tsrc = _T_202 ? issue_slots_18_out_uop_debug_tsrc : _T_201 ? issue_slots_17_out_uop_debug_tsrc : issue_slots_16_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_debug_fsrc = _T_202 ? issue_slots_18_out_uop_debug_fsrc : _T_201 ? issue_slots_17_out_uop_debug_fsrc : issue_slots_16_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_bp_xcpt_if = _T_202 ? issue_slots_18_out_uop_bp_xcpt_if : _T_201 ? issue_slots_17_out_uop_bp_xcpt_if : issue_slots_16_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_bp_debug_if = _T_202 ? issue_slots_18_out_uop_bp_debug_if : _T_201 ? issue_slots_17_out_uop_bp_debug_if : issue_slots_16_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_xcpt_ma_if = _T_202 ? issue_slots_18_out_uop_xcpt_ma_if : _T_201 ? issue_slots_17_out_uop_xcpt_ma_if : issue_slots_16_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_xcpt_ae_if = _T_202 ? issue_slots_18_out_uop_xcpt_ae_if : _T_201 ? issue_slots_17_out_uop_xcpt_ae_if : issue_slots_16_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_xcpt_pf_if = _T_202 ? issue_slots_18_out_uop_xcpt_pf_if : _T_201 ? issue_slots_17_out_uop_xcpt_pf_if : issue_slots_16_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_typ = _T_202 ? issue_slots_18_out_uop_fp_typ : _T_201 ? issue_slots_17_out_uop_fp_typ : issue_slots_16_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_rm = _T_202 ? issue_slots_18_out_uop_fp_rm : _T_201 ? issue_slots_17_out_uop_fp_rm : issue_slots_16_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_val = _T_202 ? issue_slots_18_out_uop_fp_val : _T_201 ? issue_slots_17_out_uop_fp_val : issue_slots_16_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fcn_op = _T_202 ? issue_slots_18_out_uop_fcn_op : _T_201 ? issue_slots_17_out_uop_fcn_op : issue_slots_16_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fcn_dw = _T_202 ? issue_slots_18_out_uop_fcn_dw : _T_201 ? issue_slots_17_out_uop_fcn_dw : issue_slots_16_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_frs3_en = _T_202 ? issue_slots_18_out_uop_frs3_en : _T_201 ? issue_slots_17_out_uop_frs3_en : issue_slots_16_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_lrs2_rtype = _T_202 ? issue_slots_18_out_uop_lrs2_rtype : _T_201 ? issue_slots_17_out_uop_lrs2_rtype : issue_slots_16_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_lrs1_rtype = _T_202 ? issue_slots_18_out_uop_lrs1_rtype : _T_201 ? issue_slots_17_out_uop_lrs1_rtype : issue_slots_16_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_dst_rtype = _T_202 ? issue_slots_18_out_uop_dst_rtype : _T_201 ? issue_slots_17_out_uop_dst_rtype : issue_slots_16_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_lrs3 = _T_202 ? issue_slots_18_out_uop_lrs3 : _T_201 ? issue_slots_17_out_uop_lrs3 : issue_slots_16_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_lrs2 = _T_202 ? issue_slots_18_out_uop_lrs2 : _T_201 ? issue_slots_17_out_uop_lrs2 : issue_slots_16_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_lrs1 = _T_202 ? issue_slots_18_out_uop_lrs1 : _T_201 ? issue_slots_17_out_uop_lrs1 : issue_slots_16_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_ldst = _T_202 ? issue_slots_18_out_uop_ldst : _T_201 ? issue_slots_17_out_uop_ldst : issue_slots_16_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_ldst_is_rs1 = _T_202 ? issue_slots_18_out_uop_ldst_is_rs1 : _T_201 ? issue_slots_17_out_uop_ldst_is_rs1 : issue_slots_16_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_csr_cmd = _T_202 ? issue_slots_18_out_uop_csr_cmd : _T_201 ? issue_slots_17_out_uop_csr_cmd : issue_slots_16_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_flush_on_commit = _T_202 ? issue_slots_18_out_uop_flush_on_commit : _T_201 ? issue_slots_17_out_uop_flush_on_commit : issue_slots_16_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_unique = _T_202 ? issue_slots_18_out_uop_is_unique : _T_201 ? issue_slots_17_out_uop_is_unique : issue_slots_16_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_uses_stq = _T_202 ? issue_slots_18_out_uop_uses_stq : _T_201 ? issue_slots_17_out_uop_uses_stq : issue_slots_16_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_uses_ldq = _T_202 ? issue_slots_18_out_uop_uses_ldq : _T_201 ? issue_slots_17_out_uop_uses_ldq : issue_slots_16_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_mem_signed = _T_202 ? issue_slots_18_out_uop_mem_signed : _T_201 ? issue_slots_17_out_uop_mem_signed : issue_slots_16_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_mem_size = _T_202 ? issue_slots_18_out_uop_mem_size : _T_201 ? issue_slots_17_out_uop_mem_size : issue_slots_16_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_mem_cmd = _T_202 ? issue_slots_18_out_uop_mem_cmd : _T_201 ? issue_slots_17_out_uop_mem_cmd : issue_slots_16_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_exc_cause = _T_202 ? issue_slots_18_out_uop_exc_cause : _T_201 ? issue_slots_17_out_uop_exc_cause : issue_slots_16_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_exception = _T_202 ? issue_slots_18_out_uop_exception : _T_201 ? issue_slots_17_out_uop_exception : issue_slots_16_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_stale_pdst = _T_202 ? issue_slots_18_out_uop_stale_pdst : _T_201 ? issue_slots_17_out_uop_stale_pdst : issue_slots_16_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_ppred_busy = _T_202 ? issue_slots_18_out_uop_ppred_busy : _T_201 ? issue_slots_17_out_uop_ppred_busy : issue_slots_16_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_prs3_busy = _T_202 ? issue_slots_18_out_uop_prs3_busy : _T_201 ? issue_slots_17_out_uop_prs3_busy : issue_slots_16_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_prs2_busy = _T_202 ? issue_slots_18_out_uop_prs2_busy : _T_201 ? issue_slots_17_out_uop_prs2_busy : issue_slots_16_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_prs1_busy = _T_202 ? issue_slots_18_out_uop_prs1_busy : _T_201 ? issue_slots_17_out_uop_prs1_busy : issue_slots_16_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_ppred = _T_202 ? issue_slots_18_out_uop_ppred : _T_201 ? issue_slots_17_out_uop_ppred : issue_slots_16_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_prs3 = _T_202 ? issue_slots_18_out_uop_prs3 : _T_201 ? issue_slots_17_out_uop_prs3 : issue_slots_16_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_prs2 = _T_202 ? issue_slots_18_out_uop_prs2 : _T_201 ? issue_slots_17_out_uop_prs2 : issue_slots_16_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_prs1 = _T_202 ? issue_slots_18_out_uop_prs1 : _T_201 ? issue_slots_17_out_uop_prs1 : issue_slots_16_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_pdst = _T_202 ? issue_slots_18_out_uop_pdst : _T_201 ? issue_slots_17_out_uop_pdst : issue_slots_16_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_rxq_idx = _T_202 ? issue_slots_18_out_uop_rxq_idx : _T_201 ? issue_slots_17_out_uop_rxq_idx : issue_slots_16_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_stq_idx = _T_202 ? issue_slots_18_out_uop_stq_idx : _T_201 ? issue_slots_17_out_uop_stq_idx : issue_slots_16_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_ldq_idx = _T_202 ? issue_slots_18_out_uop_ldq_idx : _T_201 ? issue_slots_17_out_uop_ldq_idx : issue_slots_16_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_rob_idx = _T_202 ? issue_slots_18_out_uop_rob_idx : _T_201 ? issue_slots_17_out_uop_rob_idx : issue_slots_16_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_vec = _T_202 ? issue_slots_18_out_uop_fp_ctrl_vec : _T_201 ? issue_slots_17_out_uop_fp_ctrl_vec : issue_slots_16_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_wflags = _T_202 ? issue_slots_18_out_uop_fp_ctrl_wflags : _T_201 ? issue_slots_17_out_uop_fp_ctrl_wflags : issue_slots_16_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_sqrt = _T_202 ? issue_slots_18_out_uop_fp_ctrl_sqrt : _T_201 ? issue_slots_17_out_uop_fp_ctrl_sqrt : issue_slots_16_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_div = _T_202 ? issue_slots_18_out_uop_fp_ctrl_div : _T_201 ? issue_slots_17_out_uop_fp_ctrl_div : issue_slots_16_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_fma = _T_202 ? issue_slots_18_out_uop_fp_ctrl_fma : _T_201 ? issue_slots_17_out_uop_fp_ctrl_fma : issue_slots_16_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_fastpipe = _T_202 ? issue_slots_18_out_uop_fp_ctrl_fastpipe : _T_201 ? issue_slots_17_out_uop_fp_ctrl_fastpipe : issue_slots_16_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_toint = _T_202 ? issue_slots_18_out_uop_fp_ctrl_toint : _T_201 ? issue_slots_17_out_uop_fp_ctrl_toint : issue_slots_16_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_fromint = _T_202 ? issue_slots_18_out_uop_fp_ctrl_fromint : _T_201 ? issue_slots_17_out_uop_fp_ctrl_fromint : issue_slots_16_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_typeTagOut = _T_202 ? issue_slots_18_out_uop_fp_ctrl_typeTagOut : _T_201 ? issue_slots_17_out_uop_fp_ctrl_typeTagOut : issue_slots_16_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_typeTagIn = _T_202 ? issue_slots_18_out_uop_fp_ctrl_typeTagIn : _T_201 ? issue_slots_17_out_uop_fp_ctrl_typeTagIn : issue_slots_16_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_swap23 = _T_202 ? issue_slots_18_out_uop_fp_ctrl_swap23 : _T_201 ? issue_slots_17_out_uop_fp_ctrl_swap23 : issue_slots_16_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_swap12 = _T_202 ? issue_slots_18_out_uop_fp_ctrl_swap12 : _T_201 ? issue_slots_17_out_uop_fp_ctrl_swap12 : issue_slots_16_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_ren3 = _T_202 ? issue_slots_18_out_uop_fp_ctrl_ren3 : _T_201 ? issue_slots_17_out_uop_fp_ctrl_ren3 : issue_slots_16_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_ren2 = _T_202 ? issue_slots_18_out_uop_fp_ctrl_ren2 : _T_201 ? issue_slots_17_out_uop_fp_ctrl_ren2 : issue_slots_16_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_ren1 = _T_202 ? issue_slots_18_out_uop_fp_ctrl_ren1 : _T_201 ? issue_slots_17_out_uop_fp_ctrl_ren1 : issue_slots_16_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_wen = _T_202 ? issue_slots_18_out_uop_fp_ctrl_wen : _T_201 ? issue_slots_17_out_uop_fp_ctrl_wen : issue_slots_16_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fp_ctrl_ldst = _T_202 ? issue_slots_18_out_uop_fp_ctrl_ldst : _T_201 ? issue_slots_17_out_uop_fp_ctrl_ldst : issue_slots_16_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_op2_sel = _T_202 ? issue_slots_18_out_uop_op2_sel : _T_201 ? issue_slots_17_out_uop_op2_sel : issue_slots_16_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_op1_sel = _T_202 ? issue_slots_18_out_uop_op1_sel : _T_201 ? issue_slots_17_out_uop_op1_sel : issue_slots_16_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_imm_packed = _T_202 ? issue_slots_18_out_uop_imm_packed : _T_201 ? issue_slots_17_out_uop_imm_packed : issue_slots_16_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_pimm = _T_202 ? issue_slots_18_out_uop_pimm : _T_201 ? issue_slots_17_out_uop_pimm : issue_slots_16_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_imm_sel = _T_202 ? issue_slots_18_out_uop_imm_sel : _T_201 ? issue_slots_17_out_uop_imm_sel : issue_slots_16_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_imm_rename = _T_202 ? issue_slots_18_out_uop_imm_rename : _T_201 ? issue_slots_17_out_uop_imm_rename : issue_slots_16_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_taken = _T_202 ? issue_slots_18_out_uop_taken : _T_201 ? issue_slots_17_out_uop_taken : issue_slots_16_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_pc_lob = _T_202 ? issue_slots_18_out_uop_pc_lob : _T_201 ? issue_slots_17_out_uop_pc_lob : issue_slots_16_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_edge_inst = _T_202 ? issue_slots_18_out_uop_edge_inst : _T_201 ? issue_slots_17_out_uop_edge_inst : issue_slots_16_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_ftq_idx = _T_202 ? issue_slots_18_out_uop_ftq_idx : _T_201 ? issue_slots_17_out_uop_ftq_idx : issue_slots_16_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_mov = _T_202 ? issue_slots_18_out_uop_is_mov : _T_201 ? issue_slots_17_out_uop_is_mov : issue_slots_16_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_rocc = _T_202 ? issue_slots_18_out_uop_is_rocc : _T_201 ? issue_slots_17_out_uop_is_rocc : issue_slots_16_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_sys_pc2epc = _T_202 ? issue_slots_18_out_uop_is_sys_pc2epc : _T_201 ? issue_slots_17_out_uop_is_sys_pc2epc : issue_slots_16_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_eret = _T_202 ? issue_slots_18_out_uop_is_eret : _T_201 ? issue_slots_17_out_uop_is_eret : issue_slots_16_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_amo = _T_202 ? issue_slots_18_out_uop_is_amo : _T_201 ? issue_slots_17_out_uop_is_amo : issue_slots_16_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_sfence = _T_202 ? issue_slots_18_out_uop_is_sfence : _T_201 ? issue_slots_17_out_uop_is_sfence : issue_slots_16_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_fencei = _T_202 ? issue_slots_18_out_uop_is_fencei : _T_201 ? issue_slots_17_out_uop_is_fencei : issue_slots_16_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_fence = _T_202 ? issue_slots_18_out_uop_is_fence : _T_201 ? issue_slots_17_out_uop_is_fence : issue_slots_16_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_sfb = _T_202 ? issue_slots_18_out_uop_is_sfb : _T_201 ? issue_slots_17_out_uop_is_sfb : issue_slots_16_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_br_type = _T_202 ? issue_slots_18_out_uop_br_type : _T_201 ? issue_slots_17_out_uop_br_type : issue_slots_16_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_br_tag = _T_202 ? issue_slots_18_out_uop_br_tag : _T_201 ? issue_slots_17_out_uop_br_tag : issue_slots_16_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_br_mask = _T_202 ? issue_slots_18_out_uop_br_mask : _T_201 ? issue_slots_17_out_uop_br_mask : issue_slots_16_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_dis_col_sel = _T_202 ? issue_slots_18_out_uop_dis_col_sel : _T_201 ? issue_slots_17_out_uop_dis_col_sel : issue_slots_16_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_iw_p3_bypass_hint = _T_202 ? issue_slots_18_out_uop_iw_p3_bypass_hint : _T_201 ? issue_slots_17_out_uop_iw_p3_bypass_hint : issue_slots_16_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_iw_p2_bypass_hint = _T_202 ? issue_slots_18_out_uop_iw_p2_bypass_hint : _T_201 ? issue_slots_17_out_uop_iw_p2_bypass_hint : issue_slots_16_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_iw_p1_bypass_hint = _T_202 ? issue_slots_18_out_uop_iw_p1_bypass_hint : _T_201 ? issue_slots_17_out_uop_iw_p1_bypass_hint : issue_slots_16_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_iw_issued = _T_202 ? issue_slots_18_out_uop_iw_issued : _T_201 ? issue_slots_17_out_uop_iw_issued : issue_slots_16_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_0 = _T_202 ? issue_slots_18_out_uop_fu_code_0 : _T_201 ? issue_slots_17_out_uop_fu_code_0 : issue_slots_16_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_1 = _T_202 ? issue_slots_18_out_uop_fu_code_1 : _T_201 ? issue_slots_17_out_uop_fu_code_1 : issue_slots_16_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_2 = _T_202 ? issue_slots_18_out_uop_fu_code_2 : _T_201 ? issue_slots_17_out_uop_fu_code_2 : issue_slots_16_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_3 = _T_202 ? issue_slots_18_out_uop_fu_code_3 : _T_201 ? issue_slots_17_out_uop_fu_code_3 : issue_slots_16_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_4 = _T_202 ? issue_slots_18_out_uop_fu_code_4 : _T_201 ? issue_slots_17_out_uop_fu_code_4 : issue_slots_16_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_5 = _T_202 ? issue_slots_18_out_uop_fu_code_5 : _T_201 ? issue_slots_17_out_uop_fu_code_5 : issue_slots_16_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_6 = _T_202 ? issue_slots_18_out_uop_fu_code_6 : _T_201 ? issue_slots_17_out_uop_fu_code_6 : issue_slots_16_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_7 = _T_202 ? issue_slots_18_out_uop_fu_code_7 : _T_201 ? issue_slots_17_out_uop_fu_code_7 : issue_slots_16_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_8 = _T_202 ? issue_slots_18_out_uop_fu_code_8 : _T_201 ? issue_slots_17_out_uop_fu_code_8 : issue_slots_16_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_fu_code_9 = _T_202 ? issue_slots_18_out_uop_fu_code_9 : _T_201 ? issue_slots_17_out_uop_fu_code_9 : issue_slots_16_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_iq_type_0 = _T_202 ? issue_slots_18_out_uop_iq_type_0 : _T_201 ? issue_slots_17_out_uop_iq_type_0 : issue_slots_16_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_iq_type_1 = _T_202 ? issue_slots_18_out_uop_iq_type_1 : _T_201 ? issue_slots_17_out_uop_iq_type_1 : issue_slots_16_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_iq_type_2 = _T_202 ? issue_slots_18_out_uop_iq_type_2 : _T_201 ? issue_slots_17_out_uop_iq_type_2 : issue_slots_16_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_iq_type_3 = _T_202 ? issue_slots_18_out_uop_iq_type_3 : _T_201 ? issue_slots_17_out_uop_iq_type_3 : issue_slots_16_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_debug_pc = _T_202 ? issue_slots_18_out_uop_debug_pc : _T_201 ? issue_slots_17_out_uop_debug_pc : issue_slots_16_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_is_rvc = _T_202 ? issue_slots_18_out_uop_is_rvc : _T_201 ? issue_slots_17_out_uop_is_rvc : issue_slots_16_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_debug_inst = _T_202 ? issue_slots_18_out_uop_debug_inst : _T_201 ? issue_slots_17_out_uop_debug_inst : issue_slots_16_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_15_in_uop_bits_inst = _T_202 ? issue_slots_18_out_uop_inst : _T_201 ? issue_slots_17_out_uop_inst : issue_slots_16_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_15_clear_T = \|shamts_oh_15; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_15_clear = _issue_slots_15_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_204 = shamts_oh_18 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_205 = shamts_oh_19 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_16_in_uop_valid = _T_205 ? issue_slots_19_will_be_valid : _T_204 ? issue_slots_18_will_be_valid : shamts_oh_17 == 3'h1 & issue_slots_17_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_16_in_uop_bits_debug_tsrc = _T_205 ? issue_slots_19_out_uop_debug_tsrc : _T_204 ? issue_slots_18_out_uop_debug_tsrc : issue_slots_17_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_debug_fsrc = _T_205 ? issue_slots_19_out_uop_debug_fsrc : _T_204 ? issue_slots_18_out_uop_debug_fsrc : issue_slots_17_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_bp_xcpt_if = _T_205 ? issue_slots_19_out_uop_bp_xcpt_if : _T_204 ? issue_slots_18_out_uop_bp_xcpt_if : issue_slots_17_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_bp_debug_if = _T_205 ? issue_slots_19_out_uop_bp_debug_if : _T_204 ? issue_slots_18_out_uop_bp_debug_if : issue_slots_17_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_xcpt_ma_if = _T_205 ? issue_slots_19_out_uop_xcpt_ma_if : _T_204 ? issue_slots_18_out_uop_xcpt_ma_if : issue_slots_17_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_xcpt_ae_if = _T_205 ? issue_slots_19_out_uop_xcpt_ae_if : _T_204 ? issue_slots_18_out_uop_xcpt_ae_if : issue_slots_17_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_xcpt_pf_if = _T_205 ? issue_slots_19_out_uop_xcpt_pf_if : _T_204 ? issue_slots_18_out_uop_xcpt_pf_if : issue_slots_17_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_typ = _T_205 ? issue_slots_19_out_uop_fp_typ : _T_204 ? issue_slots_18_out_uop_fp_typ : issue_slots_17_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_rm = _T_205 ? issue_slots_19_out_uop_fp_rm : _T_204 ? issue_slots_18_out_uop_fp_rm : issue_slots_17_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_val = _T_205 ? issue_slots_19_out_uop_fp_val : _T_204 ? issue_slots_18_out_uop_fp_val : issue_slots_17_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fcn_op = _T_205 ? issue_slots_19_out_uop_fcn_op : _T_204 ? issue_slots_18_out_uop_fcn_op : issue_slots_17_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fcn_dw = _T_205 ? issue_slots_19_out_uop_fcn_dw : _T_204 ? issue_slots_18_out_uop_fcn_dw : issue_slots_17_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_frs3_en = _T_205 ? issue_slots_19_out_uop_frs3_en : _T_204 ? issue_slots_18_out_uop_frs3_en : issue_slots_17_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_lrs2_rtype = _T_205 ? issue_slots_19_out_uop_lrs2_rtype : _T_204 ? issue_slots_18_out_uop_lrs2_rtype : issue_slots_17_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_lrs1_rtype = _T_205 ? issue_slots_19_out_uop_lrs1_rtype : _T_204 ? issue_slots_18_out_uop_lrs1_rtype : issue_slots_17_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_dst_rtype = _T_205 ? issue_slots_19_out_uop_dst_rtype : _T_204 ? issue_slots_18_out_uop_dst_rtype : issue_slots_17_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_lrs3 = _T_205 ? issue_slots_19_out_uop_lrs3 : _T_204 ? issue_slots_18_out_uop_lrs3 : issue_slots_17_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_lrs2 = _T_205 ? issue_slots_19_out_uop_lrs2 : _T_204 ? issue_slots_18_out_uop_lrs2 : issue_slots_17_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_lrs1 = _T_205 ? issue_slots_19_out_uop_lrs1 : _T_204 ? issue_slots_18_out_uop_lrs1 : issue_slots_17_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_ldst = _T_205 ? issue_slots_19_out_uop_ldst : _T_204 ? issue_slots_18_out_uop_ldst : issue_slots_17_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_ldst_is_rs1 = _T_205 ? issue_slots_19_out_uop_ldst_is_rs1 : _T_204 ? issue_slots_18_out_uop_ldst_is_rs1 : issue_slots_17_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_csr_cmd = _T_205 ? issue_slots_19_out_uop_csr_cmd : _T_204 ? issue_slots_18_out_uop_csr_cmd : issue_slots_17_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_flush_on_commit = _T_205 ? issue_slots_19_out_uop_flush_on_commit : _T_204 ? issue_slots_18_out_uop_flush_on_commit : issue_slots_17_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_is_unique = _T_205 ? issue_slots_19_out_uop_is_unique : _T_204 ? issue_slots_18_out_uop_is_unique : issue_slots_17_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_uses_stq = _T_205 ? issue_slots_19_out_uop_uses_stq : _T_204 ? issue_slots_18_out_uop_uses_stq : issue_slots_17_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_uses_ldq = _T_205 ? issue_slots_19_out_uop_uses_ldq : _T_204 ? issue_slots_18_out_uop_uses_ldq : issue_slots_17_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_mem_signed = _T_205 ? issue_slots_19_out_uop_mem_signed : _T_204 ? issue_slots_18_out_uop_mem_signed : issue_slots_17_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_mem_size = _T_205 ? issue_slots_19_out_uop_mem_size : _T_204 ? issue_slots_18_out_uop_mem_size : issue_slots_17_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_mem_cmd = _T_205 ? issue_slots_19_out_uop_mem_cmd : _T_204 ? issue_slots_18_out_uop_mem_cmd : issue_slots_17_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_exc_cause = _T_205 ? issue_slots_19_out_uop_exc_cause : _T_204 ? issue_slots_18_out_uop_exc_cause : issue_slots_17_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_exception = _T_205 ? issue_slots_19_out_uop_exception : _T_204 ? issue_slots_18_out_uop_exception : issue_slots_17_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_stale_pdst = _T_205 ? issue_slots_19_out_uop_stale_pdst : _T_204 ? issue_slots_18_out_uop_stale_pdst : issue_slots_17_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_ppred_busy = _T_205 ? issue_slots_19_out_uop_ppred_busy : _T_204 ? issue_slots_18_out_uop_ppred_busy : issue_slots_17_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_prs3_busy = _T_205 ? issue_slots_19_out_uop_prs3_busy : _T_204 ? issue_slots_18_out_uop_prs3_busy : issue_slots_17_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_prs2_busy = _T_205 ? issue_slots_19_out_uop_prs2_busy : _T_204 ? issue_slots_18_out_uop_prs2_busy : issue_slots_17_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_prs1_busy = _T_205 ? issue_slots_19_out_uop_prs1_busy : _T_204 ? issue_slots_18_out_uop_prs1_busy : issue_slots_17_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_ppred = _T_205 ? issue_slots_19_out_uop_ppred : _T_204 ? issue_slots_18_out_uop_ppred : issue_slots_17_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_prs3 = _T_205 ? issue_slots_19_out_uop_prs3 : _T_204 ? issue_slots_18_out_uop_prs3 : issue_slots_17_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_prs2 = _T_205 ? issue_slots_19_out_uop_prs2 : _T_204 ? issue_slots_18_out_uop_prs2 : issue_slots_17_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_prs1 = _T_205 ? issue_slots_19_out_uop_prs1 : _T_204 ? issue_slots_18_out_uop_prs1 : issue_slots_17_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_pdst = _T_205 ? issue_slots_19_out_uop_pdst : _T_204 ? issue_slots_18_out_uop_pdst : issue_slots_17_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_rxq_idx = _T_205 ? issue_slots_19_out_uop_rxq_idx : _T_204 ? issue_slots_18_out_uop_rxq_idx : issue_slots_17_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_stq_idx = _T_205 ? issue_slots_19_out_uop_stq_idx : _T_204 ? issue_slots_18_out_uop_stq_idx : issue_slots_17_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_ldq_idx = _T_205 ? issue_slots_19_out_uop_ldq_idx : _T_204 ? issue_slots_18_out_uop_ldq_idx : issue_slots_17_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_rob_idx = _T_205 ? issue_slots_19_out_uop_rob_idx : _T_204 ? issue_slots_18_out_uop_rob_idx : issue_slots_17_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_vec = _T_205 ? issue_slots_19_out_uop_fp_ctrl_vec : _T_204 ? issue_slots_18_out_uop_fp_ctrl_vec : issue_slots_17_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_wflags = _T_205 ? issue_slots_19_out_uop_fp_ctrl_wflags : _T_204 ? issue_slots_18_out_uop_fp_ctrl_wflags : issue_slots_17_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_sqrt = _T_205 ? issue_slots_19_out_uop_fp_ctrl_sqrt : _T_204 ? issue_slots_18_out_uop_fp_ctrl_sqrt : issue_slots_17_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_div = _T_205 ? issue_slots_19_out_uop_fp_ctrl_div : _T_204 ? issue_slots_18_out_uop_fp_ctrl_div : issue_slots_17_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_fma = _T_205 ? issue_slots_19_out_uop_fp_ctrl_fma : _T_204 ? issue_slots_18_out_uop_fp_ctrl_fma : issue_slots_17_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_fastpipe = _T_205 ? issue_slots_19_out_uop_fp_ctrl_fastpipe : _T_204 ? issue_slots_18_out_uop_fp_ctrl_fastpipe : issue_slots_17_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_toint = _T_205 ? issue_slots_19_out_uop_fp_ctrl_toint : _T_204 ? issue_slots_18_out_uop_fp_ctrl_toint : issue_slots_17_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_fromint = _T_205 ? issue_slots_19_out_uop_fp_ctrl_fromint : _T_204 ? issue_slots_18_out_uop_fp_ctrl_fromint : issue_slots_17_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_typeTagOut = _T_205 ? issue_slots_19_out_uop_fp_ctrl_typeTagOut : _T_204 ? issue_slots_18_out_uop_fp_ctrl_typeTagOut : issue_slots_17_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_typeTagIn = _T_205 ? issue_slots_19_out_uop_fp_ctrl_typeTagIn : _T_204 ? issue_slots_18_out_uop_fp_ctrl_typeTagIn : issue_slots_17_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_swap23 = _T_205 ? issue_slots_19_out_uop_fp_ctrl_swap23 : _T_204 ? issue_slots_18_out_uop_fp_ctrl_swap23 : issue_slots_17_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_swap12 = _T_205 ? issue_slots_19_out_uop_fp_ctrl_swap12 : _T_204 ? issue_slots_18_out_uop_fp_ctrl_swap12 : issue_slots_17_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_ren3 = _T_205 ? issue_slots_19_out_uop_fp_ctrl_ren3 : _T_204 ? issue_slots_18_out_uop_fp_ctrl_ren3 : issue_slots_17_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_ren2 = _T_205 ? issue_slots_19_out_uop_fp_ctrl_ren2 : _T_204 ? issue_slots_18_out_uop_fp_ctrl_ren2 : issue_slots_17_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_ren1 = _T_205 ? issue_slots_19_out_uop_fp_ctrl_ren1 : _T_204 ? issue_slots_18_out_uop_fp_ctrl_ren1 : issue_slots_17_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_wen = _T_205 ? issue_slots_19_out_uop_fp_ctrl_wen : _T_204 ? issue_slots_18_out_uop_fp_ctrl_wen : issue_slots_17_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fp_ctrl_ldst = _T_205 ? issue_slots_19_out_uop_fp_ctrl_ldst : _T_204 ? issue_slots_18_out_uop_fp_ctrl_ldst : issue_slots_17_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_op2_sel = _T_205 ? issue_slots_19_out_uop_op2_sel : _T_204 ? issue_slots_18_out_uop_op2_sel : issue_slots_17_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_op1_sel = _T_205 ? issue_slots_19_out_uop_op1_sel : _T_204 ? issue_slots_18_out_uop_op1_sel : issue_slots_17_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_imm_packed = _T_205 ? issue_slots_19_out_uop_imm_packed : _T_204 ? issue_slots_18_out_uop_imm_packed : issue_slots_17_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_pimm = _T_205 ? issue_slots_19_out_uop_pimm : _T_204 ? issue_slots_18_out_uop_pimm : issue_slots_17_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_imm_sel = _T_205 ? issue_slots_19_out_uop_imm_sel : _T_204 ? issue_slots_18_out_uop_imm_sel : issue_slots_17_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_imm_rename = _T_205 ? issue_slots_19_out_uop_imm_rename : _T_204 ? issue_slots_18_out_uop_imm_rename : issue_slots_17_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_taken = _T_205 ? issue_slots_19_out_uop_taken : _T_204 ? issue_slots_18_out_uop_taken : issue_slots_17_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_pc_lob = _T_205 ? issue_slots_19_out_uop_pc_lob : _T_204 ? issue_slots_18_out_uop_pc_lob : issue_slots_17_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_edge_inst = _T_205 ? issue_slots_19_out_uop_edge_inst : _T_204 ? issue_slots_18_out_uop_edge_inst : issue_slots_17_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_ftq_idx = _T_205 ? issue_slots_19_out_uop_ftq_idx : _T_204 ? issue_slots_18_out_uop_ftq_idx : issue_slots_17_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_is_mov = _T_205 ? issue_slots_19_out_uop_is_mov : _T_204 ? issue_slots_18_out_uop_is_mov : issue_slots_17_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_is_rocc = _T_205 ? issue_slots_19_out_uop_is_rocc : _T_204 ? issue_slots_18_out_uop_is_rocc : issue_slots_17_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_is_sys_pc2epc = _T_205 ? issue_slots_19_out_uop_is_sys_pc2epc : _T_204 ? issue_slots_18_out_uop_is_sys_pc2epc : issue_slots_17_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_is_eret = _T_205 ? issue_slots_19_out_uop_is_eret : _T_204 ? issue_slots_18_out_uop_is_eret : issue_slots_17_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_is_amo = _T_205 ? issue_slots_19_out_uop_is_amo : _T_204 ? issue_slots_18_out_uop_is_amo : issue_slots_17_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_is_sfence = _T_205 ? issue_slots_19_out_uop_is_sfence : _T_204 ? issue_slots_18_out_uop_is_sfence : issue_slots_17_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_is_fencei = _T_205 ? issue_slots_19_out_uop_is_fencei : _T_204 ? issue_slots_18_out_uop_is_fencei : issue_slots_17_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_is_fence = _T_205 ? issue_slots_19_out_uop_is_fence : _T_204 ? issue_slots_18_out_uop_is_fence : issue_slots_17_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_is_sfb = _T_205 ? issue_slots_19_out_uop_is_sfb : _T_204 ? issue_slots_18_out_uop_is_sfb : issue_slots_17_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_br_type = _T_205 ? issue_slots_19_out_uop_br_type : _T_204 ? issue_slots_18_out_uop_br_type : issue_slots_17_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_br_tag = _T_205 ? issue_slots_19_out_uop_br_tag : _T_204 ? issue_slots_18_out_uop_br_tag : issue_slots_17_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_br_mask = _T_205 ? issue_slots_19_out_uop_br_mask : _T_204 ? issue_slots_18_out_uop_br_mask : issue_slots_17_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_dis_col_sel = _T_205 ? issue_slots_19_out_uop_dis_col_sel : _T_204 ? issue_slots_18_out_uop_dis_col_sel : issue_slots_17_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_iw_p3_bypass_hint = _T_205 ? issue_slots_19_out_uop_iw_p3_bypass_hint : _T_204 ? issue_slots_18_out_uop_iw_p3_bypass_hint : issue_slots_17_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_iw_p2_bypass_hint = _T_205 ? issue_slots_19_out_uop_iw_p2_bypass_hint : _T_204 ? issue_slots_18_out_uop_iw_p2_bypass_hint : issue_slots_17_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_iw_p1_bypass_hint = _T_205 ? issue_slots_19_out_uop_iw_p1_bypass_hint : _T_204 ? issue_slots_18_out_uop_iw_p1_bypass_hint : issue_slots_17_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_iw_issued = _T_205 ? issue_slots_19_out_uop_iw_issued : _T_204 ? issue_slots_18_out_uop_iw_issued : issue_slots_17_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fu_code_0 = _T_205 ? issue_slots_19_out_uop_fu_code_0 : _T_204 ? issue_slots_18_out_uop_fu_code_0 : issue_slots_17_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fu_code_1 = _T_205 ? issue_slots_19_out_uop_fu_code_1 : _T_204 ? issue_slots_18_out_uop_fu_code_1 : issue_slots_17_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fu_code_2 = _T_205 ? issue_slots_19_out_uop_fu_code_2 : _T_204 ? issue_slots_18_out_uop_fu_code_2 : issue_slots_17_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fu_code_3 = _T_205 ? issue_slots_19_out_uop_fu_code_3 : _T_204 ? issue_slots_18_out_uop_fu_code_3 : issue_slots_17_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fu_code_4 = _T_205 ? issue_slots_19_out_uop_fu_code_4 : _T_204 ? issue_slots_18_out_uop_fu_code_4 : issue_slots_17_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fu_code_5 = _T_205 ? issue_slots_19_out_uop_fu_code_5 : _T_204 ? issue_slots_18_out_uop_fu_code_5 : issue_slots_17_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fu_code_6 = _T_205 ? issue_slots_19_out_uop_fu_code_6 : _T_204 ? issue_slots_18_out_uop_fu_code_6 : issue_slots_17_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fu_code_7 = _T_205 ? issue_slots_19_out_uop_fu_code_7 : _T_204 ? issue_slots_18_out_uop_fu_code_7 : issue_slots_17_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fu_code_8 = _T_205 ? issue_slots_19_out_uop_fu_code_8 : _T_204 ? issue_slots_18_out_uop_fu_code_8 : issue_slots_17_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_fu_code_9 = _T_205 ? issue_slots_19_out_uop_fu_code_9 : _T_204 ? issue_slots_18_out_uop_fu_code_9 : issue_slots_17_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_iq_type_0 = _T_205 ? issue_slots_19_out_uop_iq_type_0 : _T_204 ? issue_slots_18_out_uop_iq_type_0 : issue_slots_17_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_iq_type_1 = _T_205 ? issue_slots_19_out_uop_iq_type_1 : _T_204 ? issue_slots_18_out_uop_iq_type_1 : issue_slots_17_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_iq_type_2 = _T_205 ? issue_slots_19_out_uop_iq_type_2 : _T_204 ? issue_slots_18_out_uop_iq_type_2 : issue_slots_17_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_iq_type_3 = _T_205 ? issue_slots_19_out_uop_iq_type_3 : _T_204 ? issue_slots_18_out_uop_iq_type_3 : issue_slots_17_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_debug_pc = _T_205 ? issue_slots_19_out_uop_debug_pc : _T_204 ? issue_slots_18_out_uop_debug_pc : issue_slots_17_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_is_rvc = _T_205 ? issue_slots_19_out_uop_is_rvc : _T_204 ? issue_slots_18_out_uop_is_rvc : issue_slots_17_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_debug_inst = _T_205 ? issue_slots_19_out_uop_debug_inst : _T_204 ? issue_slots_18_out_uop_debug_inst : issue_slots_17_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_16_in_uop_bits_inst = _T_205 ? issue_slots_19_out_uop_inst : _T_204 ? issue_slots_18_out_uop_inst : issue_slots_17_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_16_clear_T = \|shamts_oh_16; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_16_clear = _issue_slots_16_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_207 = shamts_oh_19 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_208 = shamts_oh_20 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_17_in_uop_valid = _T_208 ? issue_slots_20_will_be_valid : _T_207 ? issue_slots_19_will_be_valid : shamts_oh_18 == 3'h1 & issue_slots_18_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_17_in_uop_bits_debug_tsrc = _T_208 ? issue_slots_20_out_uop_debug_tsrc : _T_207 ? issue_slots_19_out_uop_debug_tsrc : issue_slots_18_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_debug_fsrc = _T_208 ? issue_slots_20_out_uop_debug_fsrc : _T_207 ? issue_slots_19_out_uop_debug_fsrc : issue_slots_18_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_bp_xcpt_if = _T_208 ? issue_slots_20_out_uop_bp_xcpt_if : _T_207 ? issue_slots_19_out_uop_bp_xcpt_if : issue_slots_18_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_bp_debug_if = _T_208 ? issue_slots_20_out_uop_bp_debug_if : _T_207 ? issue_slots_19_out_uop_bp_debug_if : issue_slots_18_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_xcpt_ma_if = _T_208 ? issue_slots_20_out_uop_xcpt_ma_if : _T_207 ? issue_slots_19_out_uop_xcpt_ma_if : issue_slots_18_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_xcpt_ae_if = _T_208 ? issue_slots_20_out_uop_xcpt_ae_if : _T_207 ? issue_slots_19_out_uop_xcpt_ae_if : issue_slots_18_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_xcpt_pf_if = _T_208 ? issue_slots_20_out_uop_xcpt_pf_if : _T_207 ? issue_slots_19_out_uop_xcpt_pf_if : issue_slots_18_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_typ = _T_208 ? issue_slots_20_out_uop_fp_typ : _T_207 ? issue_slots_19_out_uop_fp_typ : issue_slots_18_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_rm = _T_208 ? issue_slots_20_out_uop_fp_rm : _T_207 ? issue_slots_19_out_uop_fp_rm : issue_slots_18_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_val = _T_208 ? issue_slots_20_out_uop_fp_val : _T_207 ? issue_slots_19_out_uop_fp_val : issue_slots_18_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fcn_op = _T_208 ? issue_slots_20_out_uop_fcn_op : _T_207 ? issue_slots_19_out_uop_fcn_op : issue_slots_18_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fcn_dw = _T_208 ? issue_slots_20_out_uop_fcn_dw : _T_207 ? issue_slots_19_out_uop_fcn_dw : issue_slots_18_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_frs3_en = _T_208 ? issue_slots_20_out_uop_frs3_en : _T_207 ? issue_slots_19_out_uop_frs3_en : issue_slots_18_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_lrs2_rtype = _T_208 ? issue_slots_20_out_uop_lrs2_rtype : _T_207 ? issue_slots_19_out_uop_lrs2_rtype : issue_slots_18_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_lrs1_rtype = _T_208 ? issue_slots_20_out_uop_lrs1_rtype : _T_207 ? issue_slots_19_out_uop_lrs1_rtype : issue_slots_18_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_dst_rtype = _T_208 ? issue_slots_20_out_uop_dst_rtype : _T_207 ? issue_slots_19_out_uop_dst_rtype : issue_slots_18_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_lrs3 = _T_208 ? issue_slots_20_out_uop_lrs3 : _T_207 ? issue_slots_19_out_uop_lrs3 : issue_slots_18_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_lrs2 = _T_208 ? issue_slots_20_out_uop_lrs2 : _T_207 ? issue_slots_19_out_uop_lrs2 : issue_slots_18_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_lrs1 = _T_208 ? issue_slots_20_out_uop_lrs1 : _T_207 ? issue_slots_19_out_uop_lrs1 : issue_slots_18_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_ldst = _T_208 ? issue_slots_20_out_uop_ldst : _T_207 ? issue_slots_19_out_uop_ldst : issue_slots_18_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_ldst_is_rs1 = _T_208 ? issue_slots_20_out_uop_ldst_is_rs1 : _T_207 ? issue_slots_19_out_uop_ldst_is_rs1 : issue_slots_18_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_csr_cmd = _T_208 ? issue_slots_20_out_uop_csr_cmd : _T_207 ? issue_slots_19_out_uop_csr_cmd : issue_slots_18_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_flush_on_commit = _T_208 ? issue_slots_20_out_uop_flush_on_commit : _T_207 ? issue_slots_19_out_uop_flush_on_commit : issue_slots_18_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_is_unique = _T_208 ? issue_slots_20_out_uop_is_unique : _T_207 ? issue_slots_19_out_uop_is_unique : issue_slots_18_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_uses_stq = _T_208 ? issue_slots_20_out_uop_uses_stq : _T_207 ? issue_slots_19_out_uop_uses_stq : issue_slots_18_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_uses_ldq = _T_208 ? issue_slots_20_out_uop_uses_ldq : _T_207 ? issue_slots_19_out_uop_uses_ldq : issue_slots_18_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_mem_signed = _T_208 ? issue_slots_20_out_uop_mem_signed : _T_207 ? issue_slots_19_out_uop_mem_signed : issue_slots_18_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_mem_size = _T_208 ? issue_slots_20_out_uop_mem_size : _T_207 ? issue_slots_19_out_uop_mem_size : issue_slots_18_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_mem_cmd = _T_208 ? issue_slots_20_out_uop_mem_cmd : _T_207 ? issue_slots_19_out_uop_mem_cmd : issue_slots_18_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_exc_cause = _T_208 ? issue_slots_20_out_uop_exc_cause : _T_207 ? issue_slots_19_out_uop_exc_cause : issue_slots_18_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_exception = _T_208 ? issue_slots_20_out_uop_exception : _T_207 ? issue_slots_19_out_uop_exception : issue_slots_18_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_stale_pdst = _T_208 ? issue_slots_20_out_uop_stale_pdst : _T_207 ? issue_slots_19_out_uop_stale_pdst : issue_slots_18_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_ppred_busy = _T_208 ? issue_slots_20_out_uop_ppred_busy : _T_207 ? issue_slots_19_out_uop_ppred_busy : issue_slots_18_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_prs3_busy = _T_208 ? issue_slots_20_out_uop_prs3_busy : _T_207 ? issue_slots_19_out_uop_prs3_busy : issue_slots_18_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_prs2_busy = _T_208 ? issue_slots_20_out_uop_prs2_busy : _T_207 ? issue_slots_19_out_uop_prs2_busy : issue_slots_18_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_prs1_busy = _T_208 ? issue_slots_20_out_uop_prs1_busy : _T_207 ? issue_slots_19_out_uop_prs1_busy : issue_slots_18_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_ppred = _T_208 ? issue_slots_20_out_uop_ppred : _T_207 ? issue_slots_19_out_uop_ppred : issue_slots_18_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_prs3 = _T_208 ? issue_slots_20_out_uop_prs3 : _T_207 ? issue_slots_19_out_uop_prs3 : issue_slots_18_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_prs2 = _T_208 ? issue_slots_20_out_uop_prs2 : _T_207 ? issue_slots_19_out_uop_prs2 : issue_slots_18_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_prs1 = _T_208 ? issue_slots_20_out_uop_prs1 : _T_207 ? issue_slots_19_out_uop_prs1 : issue_slots_18_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_pdst = _T_208 ? issue_slots_20_out_uop_pdst : _T_207 ? issue_slots_19_out_uop_pdst : issue_slots_18_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_rxq_idx = _T_208 ? issue_slots_20_out_uop_rxq_idx : _T_207 ? issue_slots_19_out_uop_rxq_idx : issue_slots_18_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_stq_idx = _T_208 ? issue_slots_20_out_uop_stq_idx : _T_207 ? issue_slots_19_out_uop_stq_idx : issue_slots_18_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_ldq_idx = _T_208 ? issue_slots_20_out_uop_ldq_idx : _T_207 ? issue_slots_19_out_uop_ldq_idx : issue_slots_18_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_rob_idx = _T_208 ? issue_slots_20_out_uop_rob_idx : _T_207 ? issue_slots_19_out_uop_rob_idx : issue_slots_18_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_vec = _T_208 ? issue_slots_20_out_uop_fp_ctrl_vec : _T_207 ? issue_slots_19_out_uop_fp_ctrl_vec : issue_slots_18_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_wflags = _T_208 ? issue_slots_20_out_uop_fp_ctrl_wflags : _T_207 ? issue_slots_19_out_uop_fp_ctrl_wflags : issue_slots_18_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_sqrt = _T_208 ? issue_slots_20_out_uop_fp_ctrl_sqrt : _T_207 ? issue_slots_19_out_uop_fp_ctrl_sqrt : issue_slots_18_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_div = _T_208 ? issue_slots_20_out_uop_fp_ctrl_div : _T_207 ? issue_slots_19_out_uop_fp_ctrl_div : issue_slots_18_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_fma = _T_208 ? issue_slots_20_out_uop_fp_ctrl_fma : _T_207 ? issue_slots_19_out_uop_fp_ctrl_fma : issue_slots_18_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_fastpipe = _T_208 ? issue_slots_20_out_uop_fp_ctrl_fastpipe : _T_207 ? issue_slots_19_out_uop_fp_ctrl_fastpipe : issue_slots_18_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_toint = _T_208 ? issue_slots_20_out_uop_fp_ctrl_toint : _T_207 ? issue_slots_19_out_uop_fp_ctrl_toint : issue_slots_18_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_fromint = _T_208 ? issue_slots_20_out_uop_fp_ctrl_fromint : _T_207 ? issue_slots_19_out_uop_fp_ctrl_fromint : issue_slots_18_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_typeTagOut = _T_208 ? issue_slots_20_out_uop_fp_ctrl_typeTagOut : _T_207 ? issue_slots_19_out_uop_fp_ctrl_typeTagOut : issue_slots_18_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_typeTagIn = _T_208 ? issue_slots_20_out_uop_fp_ctrl_typeTagIn : _T_207 ? issue_slots_19_out_uop_fp_ctrl_typeTagIn : issue_slots_18_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_swap23 = _T_208 ? issue_slots_20_out_uop_fp_ctrl_swap23 : _T_207 ? issue_slots_19_out_uop_fp_ctrl_swap23 : issue_slots_18_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_swap12 = _T_208 ? issue_slots_20_out_uop_fp_ctrl_swap12 : _T_207 ? issue_slots_19_out_uop_fp_ctrl_swap12 : issue_slots_18_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_ren3 = _T_208 ? issue_slots_20_out_uop_fp_ctrl_ren3 : _T_207 ? issue_slots_19_out_uop_fp_ctrl_ren3 : issue_slots_18_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_ren2 = _T_208 ? issue_slots_20_out_uop_fp_ctrl_ren2 : _T_207 ? issue_slots_19_out_uop_fp_ctrl_ren2 : issue_slots_18_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_ren1 = _T_208 ? issue_slots_20_out_uop_fp_ctrl_ren1 : _T_207 ? issue_slots_19_out_uop_fp_ctrl_ren1 : issue_slots_18_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_wen = _T_208 ? issue_slots_20_out_uop_fp_ctrl_wen : _T_207 ? issue_slots_19_out_uop_fp_ctrl_wen : issue_slots_18_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fp_ctrl_ldst = _T_208 ? issue_slots_20_out_uop_fp_ctrl_ldst : _T_207 ? issue_slots_19_out_uop_fp_ctrl_ldst : issue_slots_18_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_op2_sel = _T_208 ? issue_slots_20_out_uop_op2_sel : _T_207 ? issue_slots_19_out_uop_op2_sel : issue_slots_18_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_op1_sel = _T_208 ? issue_slots_20_out_uop_op1_sel : _T_207 ? issue_slots_19_out_uop_op1_sel : issue_slots_18_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_imm_packed = _T_208 ? issue_slots_20_out_uop_imm_packed : _T_207 ? issue_slots_19_out_uop_imm_packed : issue_slots_18_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_pimm = _T_208 ? issue_slots_20_out_uop_pimm : _T_207 ? issue_slots_19_out_uop_pimm : issue_slots_18_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_imm_sel = _T_208 ? issue_slots_20_out_uop_imm_sel : _T_207 ? issue_slots_19_out_uop_imm_sel : issue_slots_18_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_imm_rename = _T_208 ? issue_slots_20_out_uop_imm_rename : _T_207 ? issue_slots_19_out_uop_imm_rename : issue_slots_18_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_taken = _T_208 ? issue_slots_20_out_uop_taken : _T_207 ? issue_slots_19_out_uop_taken : issue_slots_18_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_pc_lob = _T_208 ? issue_slots_20_out_uop_pc_lob : _T_207 ? issue_slots_19_out_uop_pc_lob : issue_slots_18_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_edge_inst = _T_208 ? issue_slots_20_out_uop_edge_inst : _T_207 ? issue_slots_19_out_uop_edge_inst : issue_slots_18_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_ftq_idx = _T_208 ? issue_slots_20_out_uop_ftq_idx : _T_207 ? issue_slots_19_out_uop_ftq_idx : issue_slots_18_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_is_mov = _T_208 ? issue_slots_20_out_uop_is_mov : _T_207 ? issue_slots_19_out_uop_is_mov : issue_slots_18_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_is_rocc = _T_208 ? issue_slots_20_out_uop_is_rocc : _T_207 ? issue_slots_19_out_uop_is_rocc : issue_slots_18_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_is_sys_pc2epc = _T_208 ? issue_slots_20_out_uop_is_sys_pc2epc : _T_207 ? issue_slots_19_out_uop_is_sys_pc2epc : issue_slots_18_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_is_eret = _T_208 ? issue_slots_20_out_uop_is_eret : _T_207 ? issue_slots_19_out_uop_is_eret : issue_slots_18_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_is_amo = _T_208 ? issue_slots_20_out_uop_is_amo : _T_207 ? issue_slots_19_out_uop_is_amo : issue_slots_18_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_is_sfence = _T_208 ? issue_slots_20_out_uop_is_sfence : _T_207 ? issue_slots_19_out_uop_is_sfence : issue_slots_18_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_is_fencei = _T_208 ? issue_slots_20_out_uop_is_fencei : _T_207 ? issue_slots_19_out_uop_is_fencei : issue_slots_18_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_is_fence = _T_208 ? issue_slots_20_out_uop_is_fence : _T_207 ? issue_slots_19_out_uop_is_fence : issue_slots_18_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_is_sfb = _T_208 ? issue_slots_20_out_uop_is_sfb : _T_207 ? issue_slots_19_out_uop_is_sfb : issue_slots_18_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_br_type = _T_208 ? issue_slots_20_out_uop_br_type : _T_207 ? issue_slots_19_out_uop_br_type : issue_slots_18_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_br_tag = _T_208 ? issue_slots_20_out_uop_br_tag : _T_207 ? issue_slots_19_out_uop_br_tag : issue_slots_18_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_br_mask = _T_208 ? issue_slots_20_out_uop_br_mask : _T_207 ? issue_slots_19_out_uop_br_mask : issue_slots_18_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_dis_col_sel = _T_208 ? issue_slots_20_out_uop_dis_col_sel : _T_207 ? issue_slots_19_out_uop_dis_col_sel : issue_slots_18_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_iw_p3_bypass_hint = _T_208 ? issue_slots_20_out_uop_iw_p3_bypass_hint : _T_207 ? issue_slots_19_out_uop_iw_p3_bypass_hint : issue_slots_18_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_iw_p2_bypass_hint = _T_208 ? issue_slots_20_out_uop_iw_p2_bypass_hint : _T_207 ? issue_slots_19_out_uop_iw_p2_bypass_hint : issue_slots_18_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_iw_p1_bypass_hint = _T_208 ? issue_slots_20_out_uop_iw_p1_bypass_hint : _T_207 ? issue_slots_19_out_uop_iw_p1_bypass_hint : issue_slots_18_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_iw_issued = _T_208 ? issue_slots_20_out_uop_iw_issued : _T_207 ? issue_slots_19_out_uop_iw_issued : issue_slots_18_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fu_code_0 = _T_208 ? issue_slots_20_out_uop_fu_code_0 : _T_207 ? issue_slots_19_out_uop_fu_code_0 : issue_slots_18_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fu_code_1 = _T_208 ? issue_slots_20_out_uop_fu_code_1 : _T_207 ? issue_slots_19_out_uop_fu_code_1 : issue_slots_18_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fu_code_2 = _T_208 ? issue_slots_20_out_uop_fu_code_2 : _T_207 ? issue_slots_19_out_uop_fu_code_2 : issue_slots_18_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fu_code_3 = _T_208 ? issue_slots_20_out_uop_fu_code_3 : _T_207 ? issue_slots_19_out_uop_fu_code_3 : issue_slots_18_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fu_code_4 = _T_208 ? issue_slots_20_out_uop_fu_code_4 : _T_207 ? issue_slots_19_out_uop_fu_code_4 : issue_slots_18_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fu_code_5 = _T_208 ? issue_slots_20_out_uop_fu_code_5 : _T_207 ? issue_slots_19_out_uop_fu_code_5 : issue_slots_18_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fu_code_6 = _T_208 ? issue_slots_20_out_uop_fu_code_6 : _T_207 ? issue_slots_19_out_uop_fu_code_6 : issue_slots_18_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fu_code_7 = _T_208 ? issue_slots_20_out_uop_fu_code_7 : _T_207 ? issue_slots_19_out_uop_fu_code_7 : issue_slots_18_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fu_code_8 = _T_208 ? issue_slots_20_out_uop_fu_code_8 : _T_207 ? issue_slots_19_out_uop_fu_code_8 : issue_slots_18_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_fu_code_9 = _T_208 ? issue_slots_20_out_uop_fu_code_9 : _T_207 ? issue_slots_19_out_uop_fu_code_9 : issue_slots_18_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_iq_type_0 = _T_208 ? issue_slots_20_out_uop_iq_type_0 : _T_207 ? issue_slots_19_out_uop_iq_type_0 : issue_slots_18_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_iq_type_1 = _T_208 ? issue_slots_20_out_uop_iq_type_1 : _T_207 ? issue_slots_19_out_uop_iq_type_1 : issue_slots_18_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_iq_type_2 = _T_208 ? issue_slots_20_out_uop_iq_type_2 : _T_207 ? issue_slots_19_out_uop_iq_type_2 : issue_slots_18_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_iq_type_3 = _T_208 ? issue_slots_20_out_uop_iq_type_3 : _T_207 ? issue_slots_19_out_uop_iq_type_3 : issue_slots_18_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_debug_pc = _T_208 ? issue_slots_20_out_uop_debug_pc : _T_207 ? issue_slots_19_out_uop_debug_pc : issue_slots_18_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_is_rvc = _T_208 ? issue_slots_20_out_uop_is_rvc : _T_207 ? issue_slots_19_out_uop_is_rvc : issue_slots_18_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_debug_inst = _T_208 ? issue_slots_20_out_uop_debug_inst : _T_207 ? issue_slots_19_out_uop_debug_inst : issue_slots_18_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_17_in_uop_bits_inst = _T_208 ? issue_slots_20_out_uop_inst : _T_207 ? issue_slots_19_out_uop_inst : issue_slots_18_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_17_clear_T = \|shamts_oh_17; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_17_clear = _issue_slots_17_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_210 = shamts_oh_20 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_211 = shamts_oh_21 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_18_in_uop_valid = _T_211 ? issue_slots_21_will_be_valid : _T_210 ? issue_slots_20_will_be_valid : shamts_oh_19 == 3'h1 & issue_slots_19_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_18_in_uop_bits_debug_tsrc = _T_211 ? issue_slots_21_out_uop_debug_tsrc : _T_210 ? issue_slots_20_out_uop_debug_tsrc : issue_slots_19_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_debug_fsrc = _T_211 ? issue_slots_21_out_uop_debug_fsrc : _T_210 ? issue_slots_20_out_uop_debug_fsrc : issue_slots_19_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_bp_xcpt_if = _T_211 ? issue_slots_21_out_uop_bp_xcpt_if : _T_210 ? issue_slots_20_out_uop_bp_xcpt_if : issue_slots_19_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_bp_debug_if = _T_211 ? issue_slots_21_out_uop_bp_debug_if : _T_210 ? issue_slots_20_out_uop_bp_debug_if : issue_slots_19_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_xcpt_ma_if = _T_211 ? issue_slots_21_out_uop_xcpt_ma_if : _T_210 ? issue_slots_20_out_uop_xcpt_ma_if : issue_slots_19_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_xcpt_ae_if = _T_211 ? issue_slots_21_out_uop_xcpt_ae_if : _T_210 ? issue_slots_20_out_uop_xcpt_ae_if : issue_slots_19_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_xcpt_pf_if = _T_211 ? issue_slots_21_out_uop_xcpt_pf_if : _T_210 ? issue_slots_20_out_uop_xcpt_pf_if : issue_slots_19_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_typ = _T_211 ? issue_slots_21_out_uop_fp_typ : _T_210 ? issue_slots_20_out_uop_fp_typ : issue_slots_19_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_rm = _T_211 ? issue_slots_21_out_uop_fp_rm : _T_210 ? issue_slots_20_out_uop_fp_rm : issue_slots_19_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_val = _T_211 ? issue_slots_21_out_uop_fp_val : _T_210 ? issue_slots_20_out_uop_fp_val : issue_slots_19_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fcn_op = _T_211 ? issue_slots_21_out_uop_fcn_op : _T_210 ? issue_slots_20_out_uop_fcn_op : issue_slots_19_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fcn_dw = _T_211 ? issue_slots_21_out_uop_fcn_dw : _T_210 ? issue_slots_20_out_uop_fcn_dw : issue_slots_19_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_frs3_en = _T_211 ? issue_slots_21_out_uop_frs3_en : _T_210 ? issue_slots_20_out_uop_frs3_en : issue_slots_19_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_lrs2_rtype = _T_211 ? issue_slots_21_out_uop_lrs2_rtype : _T_210 ? issue_slots_20_out_uop_lrs2_rtype : issue_slots_19_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_lrs1_rtype = _T_211 ? issue_slots_21_out_uop_lrs1_rtype : _T_210 ? issue_slots_20_out_uop_lrs1_rtype : issue_slots_19_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_dst_rtype = _T_211 ? issue_slots_21_out_uop_dst_rtype : _T_210 ? issue_slots_20_out_uop_dst_rtype : issue_slots_19_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_lrs3 = _T_211 ? issue_slots_21_out_uop_lrs3 : _T_210 ? issue_slots_20_out_uop_lrs3 : issue_slots_19_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_lrs2 = _T_211 ? issue_slots_21_out_uop_lrs2 : _T_210 ? issue_slots_20_out_uop_lrs2 : issue_slots_19_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_lrs1 = _T_211 ? issue_slots_21_out_uop_lrs1 : _T_210 ? issue_slots_20_out_uop_lrs1 : issue_slots_19_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_ldst = _T_211 ? issue_slots_21_out_uop_ldst : _T_210 ? issue_slots_20_out_uop_ldst : issue_slots_19_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_ldst_is_rs1 = _T_211 ? issue_slots_21_out_uop_ldst_is_rs1 : _T_210 ? issue_slots_20_out_uop_ldst_is_rs1 : issue_slots_19_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_csr_cmd = _T_211 ? issue_slots_21_out_uop_csr_cmd : _T_210 ? issue_slots_20_out_uop_csr_cmd : issue_slots_19_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_flush_on_commit = _T_211 ? issue_slots_21_out_uop_flush_on_commit : _T_210 ? issue_slots_20_out_uop_flush_on_commit : issue_slots_19_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_is_unique = _T_211 ? issue_slots_21_out_uop_is_unique : _T_210 ? issue_slots_20_out_uop_is_unique : issue_slots_19_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_uses_stq = _T_211 ? issue_slots_21_out_uop_uses_stq : _T_210 ? issue_slots_20_out_uop_uses_stq : issue_slots_19_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_uses_ldq = _T_211 ? issue_slots_21_out_uop_uses_ldq : _T_210 ? issue_slots_20_out_uop_uses_ldq : issue_slots_19_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_mem_signed = _T_211 ? issue_slots_21_out_uop_mem_signed : _T_210 ? issue_slots_20_out_uop_mem_signed : issue_slots_19_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_mem_size = _T_211 ? issue_slots_21_out_uop_mem_size : _T_210 ? issue_slots_20_out_uop_mem_size : issue_slots_19_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_mem_cmd = _T_211 ? issue_slots_21_out_uop_mem_cmd : _T_210 ? issue_slots_20_out_uop_mem_cmd : issue_slots_19_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_exc_cause = _T_211 ? issue_slots_21_out_uop_exc_cause : _T_210 ? issue_slots_20_out_uop_exc_cause : issue_slots_19_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_exception = _T_211 ? issue_slots_21_out_uop_exception : _T_210 ? issue_slots_20_out_uop_exception : issue_slots_19_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_stale_pdst = _T_211 ? issue_slots_21_out_uop_stale_pdst : _T_210 ? issue_slots_20_out_uop_stale_pdst : issue_slots_19_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_ppred_busy = _T_211 ? issue_slots_21_out_uop_ppred_busy : _T_210 ? issue_slots_20_out_uop_ppred_busy : issue_slots_19_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_prs3_busy = _T_211 ? issue_slots_21_out_uop_prs3_busy : _T_210 ? issue_slots_20_out_uop_prs3_busy : issue_slots_19_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_prs2_busy = _T_211 ? issue_slots_21_out_uop_prs2_busy : _T_210 ? issue_slots_20_out_uop_prs2_busy : issue_slots_19_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_prs1_busy = _T_211 ? issue_slots_21_out_uop_prs1_busy : _T_210 ? issue_slots_20_out_uop_prs1_busy : issue_slots_19_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_ppred = _T_211 ? issue_slots_21_out_uop_ppred : _T_210 ? issue_slots_20_out_uop_ppred : issue_slots_19_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_prs3 = _T_211 ? issue_slots_21_out_uop_prs3 : _T_210 ? issue_slots_20_out_uop_prs3 : issue_slots_19_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_prs2 = _T_211 ? issue_slots_21_out_uop_prs2 : _T_210 ? issue_slots_20_out_uop_prs2 : issue_slots_19_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_prs1 = _T_211 ? issue_slots_21_out_uop_prs1 : _T_210 ? issue_slots_20_out_uop_prs1 : issue_slots_19_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_pdst = _T_211 ? issue_slots_21_out_uop_pdst : _T_210 ? issue_slots_20_out_uop_pdst : issue_slots_19_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_rxq_idx = _T_211 ? issue_slots_21_out_uop_rxq_idx : _T_210 ? issue_slots_20_out_uop_rxq_idx : issue_slots_19_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_stq_idx = _T_211 ? issue_slots_21_out_uop_stq_idx : _T_210 ? issue_slots_20_out_uop_stq_idx : issue_slots_19_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_ldq_idx = _T_211 ? issue_slots_21_out_uop_ldq_idx : _T_210 ? issue_slots_20_out_uop_ldq_idx : issue_slots_19_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_rob_idx = _T_211 ? issue_slots_21_out_uop_rob_idx : _T_210 ? issue_slots_20_out_uop_rob_idx : issue_slots_19_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_vec = _T_211 ? issue_slots_21_out_uop_fp_ctrl_vec : _T_210 ? issue_slots_20_out_uop_fp_ctrl_vec : issue_slots_19_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_wflags = _T_211 ? issue_slots_21_out_uop_fp_ctrl_wflags : _T_210 ? issue_slots_20_out_uop_fp_ctrl_wflags : issue_slots_19_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_sqrt = _T_211 ? issue_slots_21_out_uop_fp_ctrl_sqrt : _T_210 ? issue_slots_20_out_uop_fp_ctrl_sqrt : issue_slots_19_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_div = _T_211 ? issue_slots_21_out_uop_fp_ctrl_div : _T_210 ? issue_slots_20_out_uop_fp_ctrl_div : issue_slots_19_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_fma = _T_211 ? issue_slots_21_out_uop_fp_ctrl_fma : _T_210 ? issue_slots_20_out_uop_fp_ctrl_fma : issue_slots_19_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_fastpipe = _T_211 ? issue_slots_21_out_uop_fp_ctrl_fastpipe : _T_210 ? issue_slots_20_out_uop_fp_ctrl_fastpipe : issue_slots_19_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_toint = _T_211 ? issue_slots_21_out_uop_fp_ctrl_toint : _T_210 ? issue_slots_20_out_uop_fp_ctrl_toint : issue_slots_19_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_fromint = _T_211 ? issue_slots_21_out_uop_fp_ctrl_fromint : _T_210 ? issue_slots_20_out_uop_fp_ctrl_fromint : issue_slots_19_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_typeTagOut = _T_211 ? issue_slots_21_out_uop_fp_ctrl_typeTagOut : _T_210 ? issue_slots_20_out_uop_fp_ctrl_typeTagOut : issue_slots_19_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_typeTagIn = _T_211 ? issue_slots_21_out_uop_fp_ctrl_typeTagIn : _T_210 ? issue_slots_20_out_uop_fp_ctrl_typeTagIn : issue_slots_19_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_swap23 = _T_211 ? issue_slots_21_out_uop_fp_ctrl_swap23 : _T_210 ? issue_slots_20_out_uop_fp_ctrl_swap23 : issue_slots_19_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_swap12 = _T_211 ? issue_slots_21_out_uop_fp_ctrl_swap12 : _T_210 ? issue_slots_20_out_uop_fp_ctrl_swap12 : issue_slots_19_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_ren3 = _T_211 ? issue_slots_21_out_uop_fp_ctrl_ren3 : _T_210 ? issue_slots_20_out_uop_fp_ctrl_ren3 : issue_slots_19_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_ren2 = _T_211 ? issue_slots_21_out_uop_fp_ctrl_ren2 : _T_210 ? issue_slots_20_out_uop_fp_ctrl_ren2 : issue_slots_19_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_ren1 = _T_211 ? issue_slots_21_out_uop_fp_ctrl_ren1 : _T_210 ? issue_slots_20_out_uop_fp_ctrl_ren1 : issue_slots_19_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_wen = _T_211 ? issue_slots_21_out_uop_fp_ctrl_wen : _T_210 ? issue_slots_20_out_uop_fp_ctrl_wen : issue_slots_19_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fp_ctrl_ldst = _T_211 ? issue_slots_21_out_uop_fp_ctrl_ldst : _T_210 ? issue_slots_20_out_uop_fp_ctrl_ldst : issue_slots_19_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_op2_sel = _T_211 ? issue_slots_21_out_uop_op2_sel : _T_210 ? issue_slots_20_out_uop_op2_sel : issue_slots_19_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_op1_sel = _T_211 ? issue_slots_21_out_uop_op1_sel : _T_210 ? issue_slots_20_out_uop_op1_sel : issue_slots_19_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_imm_packed = _T_211 ? issue_slots_21_out_uop_imm_packed : _T_210 ? issue_slots_20_out_uop_imm_packed : issue_slots_19_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_pimm = _T_211 ? issue_slots_21_out_uop_pimm : _T_210 ? issue_slots_20_out_uop_pimm : issue_slots_19_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_imm_sel = _T_211 ? issue_slots_21_out_uop_imm_sel : _T_210 ? issue_slots_20_out_uop_imm_sel : issue_slots_19_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_imm_rename = _T_211 ? issue_slots_21_out_uop_imm_rename : _T_210 ? issue_slots_20_out_uop_imm_rename : issue_slots_19_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_taken = _T_211 ? issue_slots_21_out_uop_taken : _T_210 ? issue_slots_20_out_uop_taken : issue_slots_19_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_pc_lob = _T_211 ? issue_slots_21_out_uop_pc_lob : _T_210 ? issue_slots_20_out_uop_pc_lob : issue_slots_19_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_edge_inst = _T_211 ? issue_slots_21_out_uop_edge_inst : _T_210 ? issue_slots_20_out_uop_edge_inst : issue_slots_19_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_ftq_idx = _T_211 ? issue_slots_21_out_uop_ftq_idx : _T_210 ? issue_slots_20_out_uop_ftq_idx : issue_slots_19_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_is_mov = _T_211 ? issue_slots_21_out_uop_is_mov : _T_210 ? issue_slots_20_out_uop_is_mov : issue_slots_19_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_is_rocc = _T_211 ? issue_slots_21_out_uop_is_rocc : _T_210 ? issue_slots_20_out_uop_is_rocc : issue_slots_19_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_is_sys_pc2epc = _T_211 ? issue_slots_21_out_uop_is_sys_pc2epc : _T_210 ? issue_slots_20_out_uop_is_sys_pc2epc : issue_slots_19_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_is_eret = _T_211 ? issue_slots_21_out_uop_is_eret : _T_210 ? issue_slots_20_out_uop_is_eret : issue_slots_19_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_is_amo = _T_211 ? issue_slots_21_out_uop_is_amo : _T_210 ? issue_slots_20_out_uop_is_amo : issue_slots_19_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_is_sfence = _T_211 ? issue_slots_21_out_uop_is_sfence : _T_210 ? issue_slots_20_out_uop_is_sfence : issue_slots_19_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_is_fencei = _T_211 ? issue_slots_21_out_uop_is_fencei : _T_210 ? issue_slots_20_out_uop_is_fencei : issue_slots_19_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_is_fence = _T_211 ? issue_slots_21_out_uop_is_fence : _T_210 ? issue_slots_20_out_uop_is_fence : issue_slots_19_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_is_sfb = _T_211 ? issue_slots_21_out_uop_is_sfb : _T_210 ? issue_slots_20_out_uop_is_sfb : issue_slots_19_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_br_type = _T_211 ? issue_slots_21_out_uop_br_type : _T_210 ? issue_slots_20_out_uop_br_type : issue_slots_19_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_br_tag = _T_211 ? issue_slots_21_out_uop_br_tag : _T_210 ? issue_slots_20_out_uop_br_tag : issue_slots_19_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_br_mask = _T_211 ? issue_slots_21_out_uop_br_mask : _T_210 ? issue_slots_20_out_uop_br_mask : issue_slots_19_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_dis_col_sel = _T_211 ? issue_slots_21_out_uop_dis_col_sel : _T_210 ? issue_slots_20_out_uop_dis_col_sel : issue_slots_19_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_iw_p3_bypass_hint = _T_211 ? issue_slots_21_out_uop_iw_p3_bypass_hint : _T_210 ? issue_slots_20_out_uop_iw_p3_bypass_hint : issue_slots_19_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_iw_p2_bypass_hint = _T_211 ? issue_slots_21_out_uop_iw_p2_bypass_hint : _T_210 ? issue_slots_20_out_uop_iw_p2_bypass_hint : issue_slots_19_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_iw_p1_bypass_hint = _T_211 ? issue_slots_21_out_uop_iw_p1_bypass_hint : _T_210 ? issue_slots_20_out_uop_iw_p1_bypass_hint : issue_slots_19_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_iw_issued = _T_211 ? issue_slots_21_out_uop_iw_issued : _T_210 ? issue_slots_20_out_uop_iw_issued : issue_slots_19_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fu_code_0 = _T_211 ? issue_slots_21_out_uop_fu_code_0 : _T_210 ? issue_slots_20_out_uop_fu_code_0 : issue_slots_19_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fu_code_1 = _T_211 ? issue_slots_21_out_uop_fu_code_1 : _T_210 ? issue_slots_20_out_uop_fu_code_1 : issue_slots_19_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fu_code_2 = _T_211 ? issue_slots_21_out_uop_fu_code_2 : _T_210 ? issue_slots_20_out_uop_fu_code_2 : issue_slots_19_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fu_code_3 = _T_211 ? issue_slots_21_out_uop_fu_code_3 : _T_210 ? issue_slots_20_out_uop_fu_code_3 : issue_slots_19_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fu_code_4 = _T_211 ? issue_slots_21_out_uop_fu_code_4 : _T_210 ? issue_slots_20_out_uop_fu_code_4 : issue_slots_19_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fu_code_5 = _T_211 ? issue_slots_21_out_uop_fu_code_5 : _T_210 ? issue_slots_20_out_uop_fu_code_5 : issue_slots_19_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fu_code_6 = _T_211 ? issue_slots_21_out_uop_fu_code_6 : _T_210 ? issue_slots_20_out_uop_fu_code_6 : issue_slots_19_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fu_code_7 = _T_211 ? issue_slots_21_out_uop_fu_code_7 : _T_210 ? issue_slots_20_out_uop_fu_code_7 : issue_slots_19_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fu_code_8 = _T_211 ? issue_slots_21_out_uop_fu_code_8 : _T_210 ? issue_slots_20_out_uop_fu_code_8 : issue_slots_19_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_fu_code_9 = _T_211 ? issue_slots_21_out_uop_fu_code_9 : _T_210 ? issue_slots_20_out_uop_fu_code_9 : issue_slots_19_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_iq_type_0 = _T_211 ? issue_slots_21_out_uop_iq_type_0 : _T_210 ? issue_slots_20_out_uop_iq_type_0 : issue_slots_19_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_iq_type_1 = _T_211 ? issue_slots_21_out_uop_iq_type_1 : _T_210 ? issue_slots_20_out_uop_iq_type_1 : issue_slots_19_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_iq_type_2 = _T_211 ? issue_slots_21_out_uop_iq_type_2 : _T_210 ? issue_slots_20_out_uop_iq_type_2 : issue_slots_19_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_iq_type_3 = _T_211 ? issue_slots_21_out_uop_iq_type_3 : _T_210 ? issue_slots_20_out_uop_iq_type_3 : issue_slots_19_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_debug_pc = _T_211 ? issue_slots_21_out_uop_debug_pc : _T_210 ? issue_slots_20_out_uop_debug_pc : issue_slots_19_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_is_rvc = _T_211 ? issue_slots_21_out_uop_is_rvc : _T_210 ? issue_slots_20_out_uop_is_rvc : issue_slots_19_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_debug_inst = _T_211 ? issue_slots_21_out_uop_debug_inst : _T_210 ? issue_slots_20_out_uop_debug_inst : issue_slots_19_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_18_in_uop_bits_inst = _T_211 ? issue_slots_21_out_uop_inst : _T_210 ? issue_slots_20_out_uop_inst : issue_slots_19_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_18_clear_T = \|shamts_oh_18; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_18_clear = _issue_slots_18_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_213 = shamts_oh_21 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_214 = shamts_oh_22 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_19_in_uop_valid = _T_214 ? issue_slots_22_will_be_valid : _T_213 ? issue_slots_21_will_be_valid : shamts_oh_20 == 3'h1 & issue_slots_20_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_19_in_uop_bits_debug_tsrc = _T_214 ? issue_slots_22_out_uop_debug_tsrc : _T_213 ? issue_slots_21_out_uop_debug_tsrc : issue_slots_20_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_debug_fsrc = _T_214 ? issue_slots_22_out_uop_debug_fsrc : _T_213 ? issue_slots_21_out_uop_debug_fsrc : issue_slots_20_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_bp_xcpt_if = _T_214 ? issue_slots_22_out_uop_bp_xcpt_if : _T_213 ? issue_slots_21_out_uop_bp_xcpt_if : issue_slots_20_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_bp_debug_if = _T_214 ? issue_slots_22_out_uop_bp_debug_if : _T_213 ? issue_slots_21_out_uop_bp_debug_if : issue_slots_20_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_xcpt_ma_if = _T_214 ? issue_slots_22_out_uop_xcpt_ma_if : _T_213 ? issue_slots_21_out_uop_xcpt_ma_if : issue_slots_20_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_xcpt_ae_if = _T_214 ? issue_slots_22_out_uop_xcpt_ae_if : _T_213 ? issue_slots_21_out_uop_xcpt_ae_if : issue_slots_20_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_xcpt_pf_if = _T_214 ? issue_slots_22_out_uop_xcpt_pf_if : _T_213 ? issue_slots_21_out_uop_xcpt_pf_if : issue_slots_20_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_typ = _T_214 ? issue_slots_22_out_uop_fp_typ : _T_213 ? issue_slots_21_out_uop_fp_typ : issue_slots_20_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_rm = _T_214 ? issue_slots_22_out_uop_fp_rm : _T_213 ? issue_slots_21_out_uop_fp_rm : issue_slots_20_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_val = _T_214 ? issue_slots_22_out_uop_fp_val : _T_213 ? issue_slots_21_out_uop_fp_val : issue_slots_20_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fcn_op = _T_214 ? issue_slots_22_out_uop_fcn_op : _T_213 ? issue_slots_21_out_uop_fcn_op : issue_slots_20_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fcn_dw = _T_214 ? issue_slots_22_out_uop_fcn_dw : _T_213 ? issue_slots_21_out_uop_fcn_dw : issue_slots_20_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_frs3_en = _T_214 ? issue_slots_22_out_uop_frs3_en : _T_213 ? issue_slots_21_out_uop_frs3_en : issue_slots_20_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_lrs2_rtype = _T_214 ? issue_slots_22_out_uop_lrs2_rtype : _T_213 ? issue_slots_21_out_uop_lrs2_rtype : issue_slots_20_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_lrs1_rtype = _T_214 ? issue_slots_22_out_uop_lrs1_rtype : _T_213 ? issue_slots_21_out_uop_lrs1_rtype : issue_slots_20_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_dst_rtype = _T_214 ? issue_slots_22_out_uop_dst_rtype : _T_213 ? issue_slots_21_out_uop_dst_rtype : issue_slots_20_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_lrs3 = _T_214 ? issue_slots_22_out_uop_lrs3 : _T_213 ? issue_slots_21_out_uop_lrs3 : issue_slots_20_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_lrs2 = _T_214 ? issue_slots_22_out_uop_lrs2 : _T_213 ? issue_slots_21_out_uop_lrs2 : issue_slots_20_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_lrs1 = _T_214 ? issue_slots_22_out_uop_lrs1 : _T_213 ? issue_slots_21_out_uop_lrs1 : issue_slots_20_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_ldst = _T_214 ? issue_slots_22_out_uop_ldst : _T_213 ? issue_slots_21_out_uop_ldst : issue_slots_20_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_ldst_is_rs1 = _T_214 ? issue_slots_22_out_uop_ldst_is_rs1 : _T_213 ? issue_slots_21_out_uop_ldst_is_rs1 : issue_slots_20_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_csr_cmd = _T_214 ? issue_slots_22_out_uop_csr_cmd : _T_213 ? issue_slots_21_out_uop_csr_cmd : issue_slots_20_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_flush_on_commit = _T_214 ? issue_slots_22_out_uop_flush_on_commit : _T_213 ? issue_slots_21_out_uop_flush_on_commit : issue_slots_20_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_is_unique = _T_214 ? issue_slots_22_out_uop_is_unique : _T_213 ? issue_slots_21_out_uop_is_unique : issue_slots_20_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_uses_stq = _T_214 ? issue_slots_22_out_uop_uses_stq : _T_213 ? issue_slots_21_out_uop_uses_stq : issue_slots_20_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_uses_ldq = _T_214 ? issue_slots_22_out_uop_uses_ldq : _T_213 ? issue_slots_21_out_uop_uses_ldq : issue_slots_20_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_mem_signed = _T_214 ? issue_slots_22_out_uop_mem_signed : _T_213 ? issue_slots_21_out_uop_mem_signed : issue_slots_20_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_mem_size = _T_214 ? issue_slots_22_out_uop_mem_size : _T_213 ? issue_slots_21_out_uop_mem_size : issue_slots_20_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_mem_cmd = _T_214 ? issue_slots_22_out_uop_mem_cmd : _T_213 ? issue_slots_21_out_uop_mem_cmd : issue_slots_20_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_exc_cause = _T_214 ? issue_slots_22_out_uop_exc_cause : _T_213 ? issue_slots_21_out_uop_exc_cause : issue_slots_20_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_exception = _T_214 ? issue_slots_22_out_uop_exception : _T_213 ? issue_slots_21_out_uop_exception : issue_slots_20_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_stale_pdst = _T_214 ? issue_slots_22_out_uop_stale_pdst : _T_213 ? issue_slots_21_out_uop_stale_pdst : issue_slots_20_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_ppred_busy = _T_214 ? issue_slots_22_out_uop_ppred_busy : _T_213 ? issue_slots_21_out_uop_ppred_busy : issue_slots_20_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_prs3_busy = _T_214 ? issue_slots_22_out_uop_prs3_busy : _T_213 ? issue_slots_21_out_uop_prs3_busy : issue_slots_20_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_prs2_busy = _T_214 ? issue_slots_22_out_uop_prs2_busy : _T_213 ? issue_slots_21_out_uop_prs2_busy : issue_slots_20_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_prs1_busy = _T_214 ? issue_slots_22_out_uop_prs1_busy : _T_213 ? issue_slots_21_out_uop_prs1_busy : issue_slots_20_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_ppred = _T_214 ? issue_slots_22_out_uop_ppred : _T_213 ? issue_slots_21_out_uop_ppred : issue_slots_20_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_prs3 = _T_214 ? issue_slots_22_out_uop_prs3 : _T_213 ? issue_slots_21_out_uop_prs3 : issue_slots_20_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_prs2 = _T_214 ? issue_slots_22_out_uop_prs2 : _T_213 ? issue_slots_21_out_uop_prs2 : issue_slots_20_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_prs1 = _T_214 ? issue_slots_22_out_uop_prs1 : _T_213 ? issue_slots_21_out_uop_prs1 : issue_slots_20_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_pdst = _T_214 ? issue_slots_22_out_uop_pdst : _T_213 ? issue_slots_21_out_uop_pdst : issue_slots_20_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_rxq_idx = _T_214 ? issue_slots_22_out_uop_rxq_idx : _T_213 ? issue_slots_21_out_uop_rxq_idx : issue_slots_20_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_stq_idx = _T_214 ? issue_slots_22_out_uop_stq_idx : _T_213 ? issue_slots_21_out_uop_stq_idx : issue_slots_20_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_ldq_idx = _T_214 ? issue_slots_22_out_uop_ldq_idx : _T_213 ? issue_slots_21_out_uop_ldq_idx : issue_slots_20_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_rob_idx = _T_214 ? issue_slots_22_out_uop_rob_idx : _T_213 ? issue_slots_21_out_uop_rob_idx : issue_slots_20_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_vec = _T_214 ? issue_slots_22_out_uop_fp_ctrl_vec : _T_213 ? issue_slots_21_out_uop_fp_ctrl_vec : issue_slots_20_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_wflags = _T_214 ? issue_slots_22_out_uop_fp_ctrl_wflags : _T_213 ? issue_slots_21_out_uop_fp_ctrl_wflags : issue_slots_20_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_sqrt = _T_214 ? issue_slots_22_out_uop_fp_ctrl_sqrt : _T_213 ? issue_slots_21_out_uop_fp_ctrl_sqrt : issue_slots_20_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_div = _T_214 ? issue_slots_22_out_uop_fp_ctrl_div : _T_213 ? issue_slots_21_out_uop_fp_ctrl_div : issue_slots_20_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_fma = _T_214 ? issue_slots_22_out_uop_fp_ctrl_fma : _T_213 ? issue_slots_21_out_uop_fp_ctrl_fma : issue_slots_20_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_fastpipe = _T_214 ? issue_slots_22_out_uop_fp_ctrl_fastpipe : _T_213 ? issue_slots_21_out_uop_fp_ctrl_fastpipe : issue_slots_20_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_toint = _T_214 ? issue_slots_22_out_uop_fp_ctrl_toint : _T_213 ? issue_slots_21_out_uop_fp_ctrl_toint : issue_slots_20_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_fromint = _T_214 ? issue_slots_22_out_uop_fp_ctrl_fromint : _T_213 ? issue_slots_21_out_uop_fp_ctrl_fromint : issue_slots_20_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_typeTagOut = _T_214 ? issue_slots_22_out_uop_fp_ctrl_typeTagOut : _T_213 ? issue_slots_21_out_uop_fp_ctrl_typeTagOut : issue_slots_20_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_typeTagIn = _T_214 ? issue_slots_22_out_uop_fp_ctrl_typeTagIn : _T_213 ? issue_slots_21_out_uop_fp_ctrl_typeTagIn : issue_slots_20_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_swap23 = _T_214 ? issue_slots_22_out_uop_fp_ctrl_swap23 : _T_213 ? issue_slots_21_out_uop_fp_ctrl_swap23 : issue_slots_20_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_swap12 = _T_214 ? issue_slots_22_out_uop_fp_ctrl_swap12 : _T_213 ? issue_slots_21_out_uop_fp_ctrl_swap12 : issue_slots_20_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_ren3 = _T_214 ? issue_slots_22_out_uop_fp_ctrl_ren3 : _T_213 ? issue_slots_21_out_uop_fp_ctrl_ren3 : issue_slots_20_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_ren2 = _T_214 ? issue_slots_22_out_uop_fp_ctrl_ren2 : _T_213 ? issue_slots_21_out_uop_fp_ctrl_ren2 : issue_slots_20_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_ren1 = _T_214 ? issue_slots_22_out_uop_fp_ctrl_ren1 : _T_213 ? issue_slots_21_out_uop_fp_ctrl_ren1 : issue_slots_20_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_wen = _T_214 ? issue_slots_22_out_uop_fp_ctrl_wen : _T_213 ? issue_slots_21_out_uop_fp_ctrl_wen : issue_slots_20_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fp_ctrl_ldst = _T_214 ? issue_slots_22_out_uop_fp_ctrl_ldst : _T_213 ? issue_slots_21_out_uop_fp_ctrl_ldst : issue_slots_20_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_op2_sel = _T_214 ? issue_slots_22_out_uop_op2_sel : _T_213 ? issue_slots_21_out_uop_op2_sel : issue_slots_20_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_op1_sel = _T_214 ? issue_slots_22_out_uop_op1_sel : _T_213 ? issue_slots_21_out_uop_op1_sel : issue_slots_20_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_imm_packed = _T_214 ? issue_slots_22_out_uop_imm_packed : _T_213 ? issue_slots_21_out_uop_imm_packed : issue_slots_20_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_pimm = _T_214 ? issue_slots_22_out_uop_pimm : _T_213 ? issue_slots_21_out_uop_pimm : issue_slots_20_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_imm_sel = _T_214 ? issue_slots_22_out_uop_imm_sel : _T_213 ? issue_slots_21_out_uop_imm_sel : issue_slots_20_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_imm_rename = _T_214 ? issue_slots_22_out_uop_imm_rename : _T_213 ? issue_slots_21_out_uop_imm_rename : issue_slots_20_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_taken = _T_214 ? issue_slots_22_out_uop_taken : _T_213 ? issue_slots_21_out_uop_taken : issue_slots_20_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_pc_lob = _T_214 ? issue_slots_22_out_uop_pc_lob : _T_213 ? issue_slots_21_out_uop_pc_lob : issue_slots_20_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_edge_inst = _T_214 ? issue_slots_22_out_uop_edge_inst : _T_213 ? issue_slots_21_out_uop_edge_inst : issue_slots_20_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_ftq_idx = _T_214 ? issue_slots_22_out_uop_ftq_idx : _T_213 ? issue_slots_21_out_uop_ftq_idx : issue_slots_20_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_is_mov = _T_214 ? issue_slots_22_out_uop_is_mov : _T_213 ? issue_slots_21_out_uop_is_mov : issue_slots_20_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_is_rocc = _T_214 ? issue_slots_22_out_uop_is_rocc : _T_213 ? issue_slots_21_out_uop_is_rocc : issue_slots_20_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_is_sys_pc2epc = _T_214 ? issue_slots_22_out_uop_is_sys_pc2epc : _T_213 ? issue_slots_21_out_uop_is_sys_pc2epc : issue_slots_20_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_is_eret = _T_214 ? issue_slots_22_out_uop_is_eret : _T_213 ? issue_slots_21_out_uop_is_eret : issue_slots_20_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_is_amo = _T_214 ? issue_slots_22_out_uop_is_amo : _T_213 ? issue_slots_21_out_uop_is_amo : issue_slots_20_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_is_sfence = _T_214 ? issue_slots_22_out_uop_is_sfence : _T_213 ? issue_slots_21_out_uop_is_sfence : issue_slots_20_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_is_fencei = _T_214 ? issue_slots_22_out_uop_is_fencei : _T_213 ? issue_slots_21_out_uop_is_fencei : issue_slots_20_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_is_fence = _T_214 ? issue_slots_22_out_uop_is_fence : _T_213 ? issue_slots_21_out_uop_is_fence : issue_slots_20_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_is_sfb = _T_214 ? issue_slots_22_out_uop_is_sfb : _T_213 ? issue_slots_21_out_uop_is_sfb : issue_slots_20_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_br_type = _T_214 ? issue_slots_22_out_uop_br_type : _T_213 ? issue_slots_21_out_uop_br_type : issue_slots_20_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_br_tag = _T_214 ? issue_slots_22_out_uop_br_tag : _T_213 ? issue_slots_21_out_uop_br_tag : issue_slots_20_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_br_mask = _T_214 ? issue_slots_22_out_uop_br_mask : _T_213 ? issue_slots_21_out_uop_br_mask : issue_slots_20_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_dis_col_sel = _T_214 ? issue_slots_22_out_uop_dis_col_sel : _T_213 ? issue_slots_21_out_uop_dis_col_sel : issue_slots_20_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_iw_p3_bypass_hint = _T_214 ? issue_slots_22_out_uop_iw_p3_bypass_hint : _T_213 ? issue_slots_21_out_uop_iw_p3_bypass_hint : issue_slots_20_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_iw_p2_bypass_hint = _T_214 ? issue_slots_22_out_uop_iw_p2_bypass_hint : _T_213 ? issue_slots_21_out_uop_iw_p2_bypass_hint : issue_slots_20_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_iw_p1_bypass_hint = _T_214 ? issue_slots_22_out_uop_iw_p1_bypass_hint : _T_213 ? issue_slots_21_out_uop_iw_p1_bypass_hint : issue_slots_20_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_iw_issued = _T_214 ? issue_slots_22_out_uop_iw_issued : _T_213 ? issue_slots_21_out_uop_iw_issued : issue_slots_20_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fu_code_0 = _T_214 ? issue_slots_22_out_uop_fu_code_0 : _T_213 ? issue_slots_21_out_uop_fu_code_0 : issue_slots_20_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fu_code_1 = _T_214 ? issue_slots_22_out_uop_fu_code_1 : _T_213 ? issue_slots_21_out_uop_fu_code_1 : issue_slots_20_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fu_code_2 = _T_214 ? issue_slots_22_out_uop_fu_code_2 : _T_213 ? issue_slots_21_out_uop_fu_code_2 : issue_slots_20_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fu_code_3 = _T_214 ? issue_slots_22_out_uop_fu_code_3 : _T_213 ? issue_slots_21_out_uop_fu_code_3 : issue_slots_20_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fu_code_4 = _T_214 ? issue_slots_22_out_uop_fu_code_4 : _T_213 ? issue_slots_21_out_uop_fu_code_4 : issue_slots_20_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fu_code_5 = _T_214 ? issue_slots_22_out_uop_fu_code_5 : _T_213 ? issue_slots_21_out_uop_fu_code_5 : issue_slots_20_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fu_code_6 = _T_214 ? issue_slots_22_out_uop_fu_code_6 : _T_213 ? issue_slots_21_out_uop_fu_code_6 : issue_slots_20_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fu_code_7 = _T_214 ? issue_slots_22_out_uop_fu_code_7 : _T_213 ? issue_slots_21_out_uop_fu_code_7 : issue_slots_20_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fu_code_8 = _T_214 ? issue_slots_22_out_uop_fu_code_8 : _T_213 ? issue_slots_21_out_uop_fu_code_8 : issue_slots_20_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_fu_code_9 = _T_214 ? issue_slots_22_out_uop_fu_code_9 : _T_213 ? issue_slots_21_out_uop_fu_code_9 : issue_slots_20_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_iq_type_0 = _T_214 ? issue_slots_22_out_uop_iq_type_0 : _T_213 ? issue_slots_21_out_uop_iq_type_0 : issue_slots_20_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_iq_type_1 = _T_214 ? issue_slots_22_out_uop_iq_type_1 : _T_213 ? issue_slots_21_out_uop_iq_type_1 : issue_slots_20_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_iq_type_2 = _T_214 ? issue_slots_22_out_uop_iq_type_2 : _T_213 ? issue_slots_21_out_uop_iq_type_2 : issue_slots_20_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_iq_type_3 = _T_214 ? issue_slots_22_out_uop_iq_type_3 : _T_213 ? issue_slots_21_out_uop_iq_type_3 : issue_slots_20_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_debug_pc = _T_214 ? issue_slots_22_out_uop_debug_pc : _T_213 ? issue_slots_21_out_uop_debug_pc : issue_slots_20_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_is_rvc = _T_214 ? issue_slots_22_out_uop_is_rvc : _T_213 ? issue_slots_21_out_uop_is_rvc : issue_slots_20_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_debug_inst = _T_214 ? issue_slots_22_out_uop_debug_inst : _T_213 ? issue_slots_21_out_uop_debug_inst : issue_slots_20_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_19_in_uop_bits_inst = _T_214 ? issue_slots_22_out_uop_inst : _T_213 ? issue_slots_21_out_uop_inst : issue_slots_20_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_19_clear_T = \|shamts_oh_19; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_19_clear = _issue_slots_19_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_216 = shamts_oh_22 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_217 = shamts_oh_23 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_20_in_uop_valid = _T_217 ? issue_slots_23_will_be_valid : _T_216 ? issue_slots_22_will_be_valid : shamts_oh_21 == 3'h1 & issue_slots_21_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :191:33, :194:{28,48}, :195:37] assign issue_slots_20_in_uop_bits_debug_tsrc = _T_217 ? issue_slots_23_out_uop_debug_tsrc : _T_216 ? issue_slots_22_out_uop_debug_tsrc : issue_slots_21_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_debug_fsrc = _T_217 ? issue_slots_23_out_uop_debug_fsrc : _T_216 ? issue_slots_22_out_uop_debug_fsrc : issue_slots_21_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_bp_xcpt_if = _T_217 ? issue_slots_23_out_uop_bp_xcpt_if : _T_216 ? issue_slots_22_out_uop_bp_xcpt_if : issue_slots_21_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_bp_debug_if = _T_217 ? issue_slots_23_out_uop_bp_debug_if : _T_216 ? issue_slots_22_out_uop_bp_debug_if : issue_slots_21_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_xcpt_ma_if = _T_217 ? issue_slots_23_out_uop_xcpt_ma_if : _T_216 ? issue_slots_22_out_uop_xcpt_ma_if : issue_slots_21_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_xcpt_ae_if = _T_217 ? issue_slots_23_out_uop_xcpt_ae_if : _T_216 ? issue_slots_22_out_uop_xcpt_ae_if : issue_slots_21_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_xcpt_pf_if = _T_217 ? issue_slots_23_out_uop_xcpt_pf_if : _T_216 ? issue_slots_22_out_uop_xcpt_pf_if : issue_slots_21_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_typ = _T_217 ? issue_slots_23_out_uop_fp_typ : _T_216 ? issue_slots_22_out_uop_fp_typ : issue_slots_21_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_rm = _T_217 ? issue_slots_23_out_uop_fp_rm : _T_216 ? issue_slots_22_out_uop_fp_rm : issue_slots_21_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_val = _T_217 ? issue_slots_23_out_uop_fp_val : _T_216 ? issue_slots_22_out_uop_fp_val : issue_slots_21_out_uop_fp_val; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fcn_op = _T_217 ? issue_slots_23_out_uop_fcn_op : _T_216 ? issue_slots_22_out_uop_fcn_op : issue_slots_21_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fcn_dw = _T_217 ? issue_slots_23_out_uop_fcn_dw : _T_216 ? issue_slots_22_out_uop_fcn_dw : issue_slots_21_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_frs3_en = _T_217 ? issue_slots_23_out_uop_frs3_en : _T_216 ? issue_slots_22_out_uop_frs3_en : issue_slots_21_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_lrs2_rtype = _T_217 ? issue_slots_23_out_uop_lrs2_rtype : _T_216 ? issue_slots_22_out_uop_lrs2_rtype : issue_slots_21_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_lrs1_rtype = _T_217 ? issue_slots_23_out_uop_lrs1_rtype : _T_216 ? issue_slots_22_out_uop_lrs1_rtype : issue_slots_21_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_dst_rtype = _T_217 ? issue_slots_23_out_uop_dst_rtype : _T_216 ? issue_slots_22_out_uop_dst_rtype : issue_slots_21_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_lrs3 = _T_217 ? issue_slots_23_out_uop_lrs3 : _T_216 ? issue_slots_22_out_uop_lrs3 : issue_slots_21_out_uop_lrs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_lrs2 = _T_217 ? issue_slots_23_out_uop_lrs2 : _T_216 ? issue_slots_22_out_uop_lrs2 : issue_slots_21_out_uop_lrs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_lrs1 = _T_217 ? issue_slots_23_out_uop_lrs1 : _T_216 ? issue_slots_22_out_uop_lrs1 : issue_slots_21_out_uop_lrs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_ldst = _T_217 ? issue_slots_23_out_uop_ldst : _T_216 ? issue_slots_22_out_uop_ldst : issue_slots_21_out_uop_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_ldst_is_rs1 = _T_217 ? issue_slots_23_out_uop_ldst_is_rs1 : _T_216 ? issue_slots_22_out_uop_ldst_is_rs1 : issue_slots_21_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_csr_cmd = _T_217 ? issue_slots_23_out_uop_csr_cmd : _T_216 ? issue_slots_22_out_uop_csr_cmd : issue_slots_21_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_flush_on_commit = _T_217 ? issue_slots_23_out_uop_flush_on_commit : _T_216 ? issue_slots_22_out_uop_flush_on_commit : issue_slots_21_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_is_unique = _T_217 ? issue_slots_23_out_uop_is_unique : _T_216 ? issue_slots_22_out_uop_is_unique : issue_slots_21_out_uop_is_unique; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_uses_stq = _T_217 ? issue_slots_23_out_uop_uses_stq : _T_216 ? issue_slots_22_out_uop_uses_stq : issue_slots_21_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_uses_ldq = _T_217 ? issue_slots_23_out_uop_uses_ldq : _T_216 ? issue_slots_22_out_uop_uses_ldq : issue_slots_21_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_mem_signed = _T_217 ? issue_slots_23_out_uop_mem_signed : _T_216 ? issue_slots_22_out_uop_mem_signed : issue_slots_21_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_mem_size = _T_217 ? issue_slots_23_out_uop_mem_size : _T_216 ? issue_slots_22_out_uop_mem_size : issue_slots_21_out_uop_mem_size; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_mem_cmd = _T_217 ? issue_slots_23_out_uop_mem_cmd : _T_216 ? issue_slots_22_out_uop_mem_cmd : issue_slots_21_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_exc_cause = _T_217 ? issue_slots_23_out_uop_exc_cause : _T_216 ? issue_slots_22_out_uop_exc_cause : issue_slots_21_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_exception = _T_217 ? issue_slots_23_out_uop_exception : _T_216 ? issue_slots_22_out_uop_exception : issue_slots_21_out_uop_exception; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_stale_pdst = _T_217 ? issue_slots_23_out_uop_stale_pdst : _T_216 ? issue_slots_22_out_uop_stale_pdst : issue_slots_21_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_ppred_busy = _T_217 ? issue_slots_23_out_uop_ppred_busy : _T_216 ? issue_slots_22_out_uop_ppred_busy : issue_slots_21_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_prs3_busy = _T_217 ? issue_slots_23_out_uop_prs3_busy : _T_216 ? issue_slots_22_out_uop_prs3_busy : issue_slots_21_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_prs2_busy = _T_217 ? issue_slots_23_out_uop_prs2_busy : _T_216 ? issue_slots_22_out_uop_prs2_busy : issue_slots_21_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_prs1_busy = _T_217 ? issue_slots_23_out_uop_prs1_busy : _T_216 ? issue_slots_22_out_uop_prs1_busy : issue_slots_21_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_ppred = _T_217 ? issue_slots_23_out_uop_ppred : _T_216 ? issue_slots_22_out_uop_ppred : issue_slots_21_out_uop_ppred; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_prs3 = _T_217 ? issue_slots_23_out_uop_prs3 : _T_216 ? issue_slots_22_out_uop_prs3 : issue_slots_21_out_uop_prs3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_prs2 = _T_217 ? issue_slots_23_out_uop_prs2 : _T_216 ? issue_slots_22_out_uop_prs2 : issue_slots_21_out_uop_prs2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_prs1 = _T_217 ? issue_slots_23_out_uop_prs1 : _T_216 ? issue_slots_22_out_uop_prs1 : issue_slots_21_out_uop_prs1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_pdst = _T_217 ? issue_slots_23_out_uop_pdst : _T_216 ? issue_slots_22_out_uop_pdst : issue_slots_21_out_uop_pdst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_rxq_idx = _T_217 ? issue_slots_23_out_uop_rxq_idx : _T_216 ? issue_slots_22_out_uop_rxq_idx : issue_slots_21_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_stq_idx = _T_217 ? issue_slots_23_out_uop_stq_idx : _T_216 ? issue_slots_22_out_uop_stq_idx : issue_slots_21_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_ldq_idx = _T_217 ? issue_slots_23_out_uop_ldq_idx : _T_216 ? issue_slots_22_out_uop_ldq_idx : issue_slots_21_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_rob_idx = _T_217 ? issue_slots_23_out_uop_rob_idx : _T_216 ? issue_slots_22_out_uop_rob_idx : issue_slots_21_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_vec = _T_217 ? issue_slots_23_out_uop_fp_ctrl_vec : _T_216 ? issue_slots_22_out_uop_fp_ctrl_vec : issue_slots_21_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_wflags = _T_217 ? issue_slots_23_out_uop_fp_ctrl_wflags : _T_216 ? issue_slots_22_out_uop_fp_ctrl_wflags : issue_slots_21_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_sqrt = _T_217 ? issue_slots_23_out_uop_fp_ctrl_sqrt : _T_216 ? issue_slots_22_out_uop_fp_ctrl_sqrt : issue_slots_21_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_div = _T_217 ? issue_slots_23_out_uop_fp_ctrl_div : _T_216 ? issue_slots_22_out_uop_fp_ctrl_div : issue_slots_21_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_fma = _T_217 ? issue_slots_23_out_uop_fp_ctrl_fma : _T_216 ? issue_slots_22_out_uop_fp_ctrl_fma : issue_slots_21_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_fastpipe = _T_217 ? issue_slots_23_out_uop_fp_ctrl_fastpipe : _T_216 ? issue_slots_22_out_uop_fp_ctrl_fastpipe : issue_slots_21_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_toint = _T_217 ? issue_slots_23_out_uop_fp_ctrl_toint : _T_216 ? issue_slots_22_out_uop_fp_ctrl_toint : issue_slots_21_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_fromint = _T_217 ? issue_slots_23_out_uop_fp_ctrl_fromint : _T_216 ? issue_slots_22_out_uop_fp_ctrl_fromint : issue_slots_21_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_typeTagOut = _T_217 ? issue_slots_23_out_uop_fp_ctrl_typeTagOut : _T_216 ? issue_slots_22_out_uop_fp_ctrl_typeTagOut : issue_slots_21_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_typeTagIn = _T_217 ? issue_slots_23_out_uop_fp_ctrl_typeTagIn : _T_216 ? issue_slots_22_out_uop_fp_ctrl_typeTagIn : issue_slots_21_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_swap23 = _T_217 ? issue_slots_23_out_uop_fp_ctrl_swap23 : _T_216 ? issue_slots_22_out_uop_fp_ctrl_swap23 : issue_slots_21_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_swap12 = _T_217 ? issue_slots_23_out_uop_fp_ctrl_swap12 : _T_216 ? issue_slots_22_out_uop_fp_ctrl_swap12 : issue_slots_21_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_ren3 = _T_217 ? issue_slots_23_out_uop_fp_ctrl_ren3 : _T_216 ? issue_slots_22_out_uop_fp_ctrl_ren3 : issue_slots_21_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_ren2 = _T_217 ? issue_slots_23_out_uop_fp_ctrl_ren2 : _T_216 ? issue_slots_22_out_uop_fp_ctrl_ren2 : issue_slots_21_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_ren1 = _T_217 ? issue_slots_23_out_uop_fp_ctrl_ren1 : _T_216 ? issue_slots_22_out_uop_fp_ctrl_ren1 : issue_slots_21_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_wen = _T_217 ? issue_slots_23_out_uop_fp_ctrl_wen : _T_216 ? issue_slots_22_out_uop_fp_ctrl_wen : issue_slots_21_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fp_ctrl_ldst = _T_217 ? issue_slots_23_out_uop_fp_ctrl_ldst : _T_216 ? issue_slots_22_out_uop_fp_ctrl_ldst : issue_slots_21_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_op2_sel = _T_217 ? issue_slots_23_out_uop_op2_sel : _T_216 ? issue_slots_22_out_uop_op2_sel : issue_slots_21_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_op1_sel = _T_217 ? issue_slots_23_out_uop_op1_sel : _T_216 ? issue_slots_22_out_uop_op1_sel : issue_slots_21_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_imm_packed = _T_217 ? issue_slots_23_out_uop_imm_packed : _T_216 ? issue_slots_22_out_uop_imm_packed : issue_slots_21_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_pimm = _T_217 ? issue_slots_23_out_uop_pimm : _T_216 ? issue_slots_22_out_uop_pimm : issue_slots_21_out_uop_pimm; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_imm_sel = _T_217 ? issue_slots_23_out_uop_imm_sel : _T_216 ? issue_slots_22_out_uop_imm_sel : issue_slots_21_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_imm_rename = _T_217 ? issue_slots_23_out_uop_imm_rename : _T_216 ? issue_slots_22_out_uop_imm_rename : issue_slots_21_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_taken = _T_217 ? issue_slots_23_out_uop_taken : _T_216 ? issue_slots_22_out_uop_taken : issue_slots_21_out_uop_taken; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_pc_lob = _T_217 ? issue_slots_23_out_uop_pc_lob : _T_216 ? issue_slots_22_out_uop_pc_lob : issue_slots_21_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_edge_inst = _T_217 ? issue_slots_23_out_uop_edge_inst : _T_216 ? issue_slots_22_out_uop_edge_inst : issue_slots_21_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_ftq_idx = _T_217 ? issue_slots_23_out_uop_ftq_idx : _T_216 ? issue_slots_22_out_uop_ftq_idx : issue_slots_21_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_is_mov = _T_217 ? issue_slots_23_out_uop_is_mov : _T_216 ? issue_slots_22_out_uop_is_mov : issue_slots_21_out_uop_is_mov; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_is_rocc = _T_217 ? issue_slots_23_out_uop_is_rocc : _T_216 ? issue_slots_22_out_uop_is_rocc : issue_slots_21_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_is_sys_pc2epc = _T_217 ? issue_slots_23_out_uop_is_sys_pc2epc : _T_216 ? issue_slots_22_out_uop_is_sys_pc2epc : issue_slots_21_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_is_eret = _T_217 ? issue_slots_23_out_uop_is_eret : _T_216 ? issue_slots_22_out_uop_is_eret : issue_slots_21_out_uop_is_eret; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_is_amo = _T_217 ? issue_slots_23_out_uop_is_amo : _T_216 ? issue_slots_22_out_uop_is_amo : issue_slots_21_out_uop_is_amo; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_is_sfence = _T_217 ? issue_slots_23_out_uop_is_sfence : _T_216 ? issue_slots_22_out_uop_is_sfence : issue_slots_21_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_is_fencei = _T_217 ? issue_slots_23_out_uop_is_fencei : _T_216 ? issue_slots_22_out_uop_is_fencei : issue_slots_21_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_is_fence = _T_217 ? issue_slots_23_out_uop_is_fence : _T_216 ? issue_slots_22_out_uop_is_fence : issue_slots_21_out_uop_is_fence; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_is_sfb = _T_217 ? issue_slots_23_out_uop_is_sfb : _T_216 ? issue_slots_22_out_uop_is_sfb : issue_slots_21_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_br_type = _T_217 ? issue_slots_23_out_uop_br_type : _T_216 ? issue_slots_22_out_uop_br_type : issue_slots_21_out_uop_br_type; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_br_tag = _T_217 ? issue_slots_23_out_uop_br_tag : _T_216 ? issue_slots_22_out_uop_br_tag : issue_slots_21_out_uop_br_tag; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_br_mask = _T_217 ? issue_slots_23_out_uop_br_mask : _T_216 ? issue_slots_22_out_uop_br_mask : issue_slots_21_out_uop_br_mask; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_dis_col_sel = _T_217 ? issue_slots_23_out_uop_dis_col_sel : _T_216 ? issue_slots_22_out_uop_dis_col_sel : issue_slots_21_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_iw_p3_bypass_hint = _T_217 ? issue_slots_23_out_uop_iw_p3_bypass_hint : _T_216 ? issue_slots_22_out_uop_iw_p3_bypass_hint : issue_slots_21_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_iw_p2_bypass_hint = _T_217 ? issue_slots_23_out_uop_iw_p2_bypass_hint : _T_216 ? issue_slots_22_out_uop_iw_p2_bypass_hint : issue_slots_21_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_iw_p1_bypass_hint = _T_217 ? issue_slots_23_out_uop_iw_p1_bypass_hint : _T_216 ? issue_slots_22_out_uop_iw_p1_bypass_hint : issue_slots_21_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_iw_issued = _T_217 ? issue_slots_23_out_uop_iw_issued : _T_216 ? issue_slots_22_out_uop_iw_issued : issue_slots_21_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fu_code_0 = _T_217 ? issue_slots_23_out_uop_fu_code_0 : _T_216 ? issue_slots_22_out_uop_fu_code_0 : issue_slots_21_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fu_code_1 = _T_217 ? issue_slots_23_out_uop_fu_code_1 : _T_216 ? issue_slots_22_out_uop_fu_code_1 : issue_slots_21_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fu_code_2 = _T_217 ? issue_slots_23_out_uop_fu_code_2 : _T_216 ? issue_slots_22_out_uop_fu_code_2 : issue_slots_21_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fu_code_3 = _T_217 ? issue_slots_23_out_uop_fu_code_3 : _T_216 ? issue_slots_22_out_uop_fu_code_3 : issue_slots_21_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fu_code_4 = _T_217 ? issue_slots_23_out_uop_fu_code_4 : _T_216 ? issue_slots_22_out_uop_fu_code_4 : issue_slots_21_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fu_code_5 = _T_217 ? issue_slots_23_out_uop_fu_code_5 : _T_216 ? issue_slots_22_out_uop_fu_code_5 : issue_slots_21_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fu_code_6 = _T_217 ? issue_slots_23_out_uop_fu_code_6 : _T_216 ? issue_slots_22_out_uop_fu_code_6 : issue_slots_21_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fu_code_7 = _T_217 ? issue_slots_23_out_uop_fu_code_7 : _T_216 ? issue_slots_22_out_uop_fu_code_7 : issue_slots_21_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fu_code_8 = _T_217 ? issue_slots_23_out_uop_fu_code_8 : _T_216 ? issue_slots_22_out_uop_fu_code_8 : issue_slots_21_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_fu_code_9 = _T_217 ? issue_slots_23_out_uop_fu_code_9 : _T_216 ? issue_slots_22_out_uop_fu_code_9 : issue_slots_21_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_iq_type_0 = _T_217 ? issue_slots_23_out_uop_iq_type_0 : _T_216 ? issue_slots_22_out_uop_iq_type_0 : issue_slots_21_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_iq_type_1 = _T_217 ? issue_slots_23_out_uop_iq_type_1 : _T_216 ? issue_slots_22_out_uop_iq_type_1 : issue_slots_21_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_iq_type_2 = _T_217 ? issue_slots_23_out_uop_iq_type_2 : _T_216 ? issue_slots_22_out_uop_iq_type_2 : issue_slots_21_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_iq_type_3 = _T_217 ? issue_slots_23_out_uop_iq_type_3 : _T_216 ? issue_slots_22_out_uop_iq_type_3 : issue_slots_21_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_debug_pc = _T_217 ? issue_slots_23_out_uop_debug_pc : _T_216 ? issue_slots_22_out_uop_debug_pc : issue_slots_21_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_is_rvc = _T_217 ? issue_slots_23_out_uop_is_rvc : _T_216 ? issue_slots_22_out_uop_is_rvc : issue_slots_21_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_debug_inst = _T_217 ? issue_slots_23_out_uop_debug_inst : _T_216 ? issue_slots_22_out_uop_debug_inst : issue_slots_21_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_20_in_uop_bits_inst = _T_217 ? issue_slots_23_out_uop_inst : _T_216 ? issue_slots_22_out_uop_inst : issue_slots_21_out_uop_inst; // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign _issue_slots_20_clear_T = \|shamts_oh_20; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_20_clear = _issue_slots_20_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_219 = shamts_oh_23 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_220 = shamts_oh_24 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_21_in_uop_valid = _T_220 ? will_be_valid_24 : _T_219 ? issue_slots_23_will_be_valid : shamts_oh_22 == 3'h1 & issue_slots_22_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :186:79, :191:33, :194:{28,48}, :195:37] assign issue_slots_21_in_uop_bits_debug_tsrc = _T_220 ? io_dis_uops_0_bits_debug_tsrc_0 : _T_219 ? issue_slots_23_out_uop_debug_tsrc : issue_slots_22_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_debug_fsrc = _T_220 ? io_dis_uops_0_bits_debug_fsrc_0 : _T_219 ? issue_slots_23_out_uop_debug_fsrc : issue_slots_22_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_bp_xcpt_if = _T_220 ? io_dis_uops_0_bits_bp_xcpt_if_0 : _T_219 ? issue_slots_23_out_uop_bp_xcpt_if : issue_slots_22_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_bp_debug_if = _T_220 ? io_dis_uops_0_bits_bp_debug_if_0 : _T_219 ? issue_slots_23_out_uop_bp_debug_if : issue_slots_22_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_xcpt_ma_if = _T_220 ? io_dis_uops_0_bits_xcpt_ma_if_0 : _T_219 ? issue_slots_23_out_uop_xcpt_ma_if : issue_slots_22_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_xcpt_ae_if = _T_220 ? io_dis_uops_0_bits_xcpt_ae_if_0 : _T_219 ? issue_slots_23_out_uop_xcpt_ae_if : issue_slots_22_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_xcpt_pf_if = _T_220 ? io_dis_uops_0_bits_xcpt_pf_if_0 : _T_219 ? issue_slots_23_out_uop_xcpt_pf_if : issue_slots_22_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_typ = _T_220 ? io_dis_uops_0_bits_fp_typ_0 : _T_219 ? issue_slots_23_out_uop_fp_typ : issue_slots_22_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_rm = _T_220 ? io_dis_uops_0_bits_fp_rm_0 : _T_219 ? issue_slots_23_out_uop_fp_rm : issue_slots_22_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_val = _T_220 ? io_dis_uops_0_bits_fp_val_0 : _T_219 ? issue_slots_23_out_uop_fp_val : issue_slots_22_out_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fcn_op = _T_220 ? io_dis_uops_0_bits_fcn_op_0 : _T_219 ? issue_slots_23_out_uop_fcn_op : issue_slots_22_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fcn_dw = _T_220 ? io_dis_uops_0_bits_fcn_dw_0 : _T_219 ? issue_slots_23_out_uop_fcn_dw : issue_slots_22_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_frs3_en = _T_220 ? io_dis_uops_0_bits_frs3_en_0 : _T_219 ? issue_slots_23_out_uop_frs3_en : issue_slots_22_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_lrs2_rtype = _T_220 ? io_dis_uops_0_bits_lrs2_rtype_0 : _T_219 ? issue_slots_23_out_uop_lrs2_rtype : issue_slots_22_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_lrs1_rtype = _T_220 ? _WIRE_lrs1_rtype : _T_219 ? issue_slots_23_out_uop_lrs1_rtype : issue_slots_22_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:35:17, :103:43, :104:32, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_dst_rtype = _T_220 ? io_dis_uops_0_bits_dst_rtype_0 : _T_219 ? issue_slots_23_out_uop_dst_rtype : issue_slots_22_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_lrs3 = _T_220 ? io_dis_uops_0_bits_lrs3_0 : _T_219 ? issue_slots_23_out_uop_lrs3 : issue_slots_22_out_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_lrs2 = _T_220 ? io_dis_uops_0_bits_lrs2_0 : _T_219 ? issue_slots_23_out_uop_lrs2 : issue_slots_22_out_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_lrs1 = _T_220 ? io_dis_uops_0_bits_lrs1_0 : _T_219 ? issue_slots_23_out_uop_lrs1 : issue_slots_22_out_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_ldst = _T_220 ? io_dis_uops_0_bits_ldst_0 : _T_219 ? issue_slots_23_out_uop_ldst : issue_slots_22_out_uop_ldst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_ldst_is_rs1 = _T_220 ? io_dis_uops_0_bits_ldst_is_rs1_0 : _T_219 ? issue_slots_23_out_uop_ldst_is_rs1 : issue_slots_22_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_csr_cmd = _T_220 ? io_dis_uops_0_bits_csr_cmd_0 : _T_219 ? issue_slots_23_out_uop_csr_cmd : issue_slots_22_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_flush_on_commit = _T_220 ? io_dis_uops_0_bits_flush_on_commit_0 : _T_219 ? issue_slots_23_out_uop_flush_on_commit : issue_slots_22_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_is_unique = _T_220 ? io_dis_uops_0_bits_is_unique_0 : _T_219 ? issue_slots_23_out_uop_is_unique : issue_slots_22_out_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_uses_stq = _T_220 ? io_dis_uops_0_bits_uses_stq_0 : _T_219 ? issue_slots_23_out_uop_uses_stq : issue_slots_22_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_uses_ldq = _T_220 ? io_dis_uops_0_bits_uses_ldq_0 : _T_219 ? issue_slots_23_out_uop_uses_ldq : issue_slots_22_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_mem_signed = _T_220 ? io_dis_uops_0_bits_mem_signed_0 : _T_219 ? issue_slots_23_out_uop_mem_signed : issue_slots_22_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_mem_size = _T_220 ? io_dis_uops_0_bits_mem_size_0 : _T_219 ? issue_slots_23_out_uop_mem_size : issue_slots_22_out_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_mem_cmd = _T_220 ? io_dis_uops_0_bits_mem_cmd_0 : _T_219 ? issue_slots_23_out_uop_mem_cmd : issue_slots_22_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_exc_cause = _T_220 ? io_dis_uops_0_bits_exc_cause_0 : _T_219 ? issue_slots_23_out_uop_exc_cause : issue_slots_22_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_exception = _T_220 ? io_dis_uops_0_bits_exception_0 : _T_219 ? issue_slots_23_out_uop_exception : issue_slots_22_out_uop_exception; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_stale_pdst = _T_220 ? io_dis_uops_0_bits_stale_pdst_0 : _T_219 ? issue_slots_23_out_uop_stale_pdst : issue_slots_22_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_ppred_busy = ~_T_220 & (_T_219 ? issue_slots_23_out_uop_ppred_busy : issue_slots_22_out_uop_ppred_busy); // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_prs3_busy = _T_220 ? _WIRE_prs3_busy : _T_219 ? issue_slots_23_out_uop_prs3_busy : issue_slots_22_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:35:17, :76:38, :77:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_prs2_busy = _T_220 ? _WIRE_prs2_busy : _T_219 ? issue_slots_23_out_uop_prs2_busy : issue_slots_22_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:35:17, :65:38, :66:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_prs1_busy = _T_220 ? _WIRE_prs1_busy : _T_219 ? issue_slots_23_out_uop_prs1_busy : issue_slots_22_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:35:17, :57:38, :58:29, :62:116, :103:43, :105:32, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_ppred = _T_220 ? io_dis_uops_0_bits_ppred_0 : _T_219 ? issue_slots_23_out_uop_ppred : issue_slots_22_out_uop_ppred; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_prs3 = _T_220 ? io_dis_uops_0_bits_prs3_0 : _T_219 ? issue_slots_23_out_uop_prs3 : issue_slots_22_out_uop_prs3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_prs2 = _T_220 ? io_dis_uops_0_bits_prs2_0 : _T_219 ? issue_slots_23_out_uop_prs2 : issue_slots_22_out_uop_prs2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_prs1 = _T_220 ? io_dis_uops_0_bits_prs1_0 : _T_219 ? issue_slots_23_out_uop_prs1 : issue_slots_22_out_uop_prs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_pdst = _T_220 ? io_dis_uops_0_bits_pdst_0 : _T_219 ? issue_slots_23_out_uop_pdst : issue_slots_22_out_uop_pdst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_rxq_idx = _T_220 ? io_dis_uops_0_bits_rxq_idx_0 : _T_219 ? issue_slots_23_out_uop_rxq_idx : issue_slots_22_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_stq_idx = _T_220 ? io_dis_uops_0_bits_stq_idx_0 : _T_219 ? issue_slots_23_out_uop_stq_idx : issue_slots_22_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_ldq_idx = _T_220 ? io_dis_uops_0_bits_ldq_idx_0 : _T_219 ? issue_slots_23_out_uop_ldq_idx : issue_slots_22_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_rob_idx = _T_220 ? io_dis_uops_0_bits_rob_idx_0 : _T_219 ? issue_slots_23_out_uop_rob_idx : issue_slots_22_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_vec = _T_220 ? io_dis_uops_0_bits_fp_ctrl_vec_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_vec : issue_slots_22_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_wflags = _T_220 ? io_dis_uops_0_bits_fp_ctrl_wflags_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_wflags : issue_slots_22_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_sqrt = _T_220 ? io_dis_uops_0_bits_fp_ctrl_sqrt_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_sqrt : issue_slots_22_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_div = _T_220 ? io_dis_uops_0_bits_fp_ctrl_div_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_div : issue_slots_22_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_fma = _T_220 ? io_dis_uops_0_bits_fp_ctrl_fma_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_fma : issue_slots_22_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_fastpipe = _T_220 ? io_dis_uops_0_bits_fp_ctrl_fastpipe_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_fastpipe : issue_slots_22_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_toint = _T_220 ? io_dis_uops_0_bits_fp_ctrl_toint_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_toint : issue_slots_22_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_fromint = _T_220 ? io_dis_uops_0_bits_fp_ctrl_fromint_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_fromint : issue_slots_22_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_typeTagOut = _T_220 ? io_dis_uops_0_bits_fp_ctrl_typeTagOut_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_typeTagOut : issue_slots_22_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_typeTagIn = _T_220 ? io_dis_uops_0_bits_fp_ctrl_typeTagIn_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_typeTagIn : issue_slots_22_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_swap23 = _T_220 ? io_dis_uops_0_bits_fp_ctrl_swap23_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_swap23 : issue_slots_22_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_swap12 = _T_220 ? io_dis_uops_0_bits_fp_ctrl_swap12_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_swap12 : issue_slots_22_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_ren3 = _T_220 ? io_dis_uops_0_bits_fp_ctrl_ren3_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_ren3 : issue_slots_22_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_ren2 = _T_220 ? io_dis_uops_0_bits_fp_ctrl_ren2_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_ren2 : issue_slots_22_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_ren1 = _T_220 ? io_dis_uops_0_bits_fp_ctrl_ren1_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_ren1 : issue_slots_22_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_wen = _T_220 ? io_dis_uops_0_bits_fp_ctrl_wen_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_wen : issue_slots_22_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fp_ctrl_ldst = _T_220 ? io_dis_uops_0_bits_fp_ctrl_ldst_0 : _T_219 ? issue_slots_23_out_uop_fp_ctrl_ldst : issue_slots_22_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_op2_sel = _T_220 ? io_dis_uops_0_bits_op2_sel_0 : _T_219 ? issue_slots_23_out_uop_op2_sel : issue_slots_22_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_op1_sel = _T_220 ? io_dis_uops_0_bits_op1_sel_0 : _T_219 ? issue_slots_23_out_uop_op1_sel : issue_slots_22_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_imm_packed = _T_220 ? io_dis_uops_0_bits_imm_packed_0 : _T_219 ? issue_slots_23_out_uop_imm_packed : issue_slots_22_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_pimm = _T_220 ? io_dis_uops_0_bits_pimm_0 : _T_219 ? issue_slots_23_out_uop_pimm : issue_slots_22_out_uop_pimm; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_imm_sel = _T_220 ? io_dis_uops_0_bits_imm_sel_0 : _T_219 ? issue_slots_23_out_uop_imm_sel : issue_slots_22_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_imm_rename = _T_220 ? io_dis_uops_0_bits_imm_rename_0 : _T_219 ? issue_slots_23_out_uop_imm_rename : issue_slots_22_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_taken = _T_220 ? io_dis_uops_0_bits_taken_0 : _T_219 ? issue_slots_23_out_uop_taken : issue_slots_22_out_uop_taken; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_pc_lob = _T_220 ? io_dis_uops_0_bits_pc_lob_0 : _T_219 ? issue_slots_23_out_uop_pc_lob : issue_slots_22_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_edge_inst = _T_220 ? io_dis_uops_0_bits_edge_inst_0 : _T_219 ? issue_slots_23_out_uop_edge_inst : issue_slots_22_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_ftq_idx = _T_220 ? io_dis_uops_0_bits_ftq_idx_0 : _T_219 ? issue_slots_23_out_uop_ftq_idx : issue_slots_22_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_is_mov = _T_220 ? io_dis_uops_0_bits_is_mov_0 : _T_219 ? issue_slots_23_out_uop_is_mov : issue_slots_22_out_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_is_rocc = _T_220 ? io_dis_uops_0_bits_is_rocc_0 : _T_219 ? issue_slots_23_out_uop_is_rocc : issue_slots_22_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_is_sys_pc2epc = _T_220 ? io_dis_uops_0_bits_is_sys_pc2epc_0 : _T_219 ? issue_slots_23_out_uop_is_sys_pc2epc : issue_slots_22_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_is_eret = _T_220 ? io_dis_uops_0_bits_is_eret_0 : _T_219 ? issue_slots_23_out_uop_is_eret : issue_slots_22_out_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_is_amo = _T_220 ? io_dis_uops_0_bits_is_amo_0 : _T_219 ? issue_slots_23_out_uop_is_amo : issue_slots_22_out_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_is_sfence = _T_220 ? io_dis_uops_0_bits_is_sfence_0 : _T_219 ? issue_slots_23_out_uop_is_sfence : issue_slots_22_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_is_fencei = _T_220 ? io_dis_uops_0_bits_is_fencei_0 : _T_219 ? issue_slots_23_out_uop_is_fencei : issue_slots_22_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_is_fence = _T_220 ? io_dis_uops_0_bits_is_fence_0 : _T_219 ? issue_slots_23_out_uop_is_fence : issue_slots_22_out_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_is_sfb = _T_220 ? io_dis_uops_0_bits_is_sfb_0 : _T_219 ? issue_slots_23_out_uop_is_sfb : issue_slots_22_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_br_type = _T_220 ? io_dis_uops_0_bits_br_type_0 : _T_219 ? issue_slots_23_out_uop_br_type : issue_slots_22_out_uop_br_type; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_br_tag = _T_220 ? io_dis_uops_0_bits_br_tag_0 : _T_219 ? issue_slots_23_out_uop_br_tag : issue_slots_22_out_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_br_mask = _T_220 ? io_dis_uops_0_bits_br_mask_0 : _T_219 ? issue_slots_23_out_uop_br_mask : issue_slots_22_out_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_dis_col_sel = _T_220 ? io_dis_uops_0_bits_dis_col_sel_0 : _T_219 ? issue_slots_23_out_uop_dis_col_sel : issue_slots_22_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_iw_p3_bypass_hint = _T_220 ? _WIRE_iw_p3_bypass_hint : _T_219 ? issue_slots_23_out_uop_iw_p3_bypass_hint : issue_slots_22_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:41:35, :76:38, :78:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_iw_p2_bypass_hint = _T_220 ? _WIRE_iw_p2_bypass_hint : _T_219 ? issue_slots_23_out_uop_iw_p2_bypass_hint : issue_slots_22_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:40:35, :65:38, :68:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_iw_p1_bypass_hint = _T_220 ? _WIRE_iw_p1_bypass_hint : _T_219 ? issue_slots_23_out_uop_iw_p1_bypass_hint : issue_slots_22_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:39:35, :57:38, :60:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_iw_p2_speculative_child = ~_T_220 \| _T_12 ? 3'h0 : io_dis_uops_0_bits_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :65:32, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_iw_p1_speculative_child = ~_T_220 \| _T ? 3'h0 : io_dis_uops_0_bits_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :57:32, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_iw_issued = ~_T_220 & (_T_219 ? issue_slots_23_out_uop_iw_issued : issue_slots_22_out_uop_iw_issued); // @[issue-unit-age-ordered.scala:122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fu_code_0 = _T_220 ? io_dis_uops_0_bits_fu_code_0_0 : _T_219 ? issue_slots_23_out_uop_fu_code_0 : issue_slots_22_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fu_code_1 = _T_220 ? io_dis_uops_0_bits_fu_code_1_0 : _T_219 ? issue_slots_23_out_uop_fu_code_1 : issue_slots_22_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fu_code_2 = _T_220 ? io_dis_uops_0_bits_fu_code_2_0 : _T_219 ? issue_slots_23_out_uop_fu_code_2 : issue_slots_22_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fu_code_3 = _T_220 ? io_dis_uops_0_bits_fu_code_3_0 : _T_219 ? issue_slots_23_out_uop_fu_code_3 : issue_slots_22_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fu_code_4 = _T_220 ? io_dis_uops_0_bits_fu_code_4_0 : _T_219 ? issue_slots_23_out_uop_fu_code_4 : issue_slots_22_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fu_code_5 = _T_220 ? io_dis_uops_0_bits_fu_code_5_0 : _T_219 ? issue_slots_23_out_uop_fu_code_5 : issue_slots_22_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fu_code_6 = _T_220 ? io_dis_uops_0_bits_fu_code_6_0 : _T_219 ? issue_slots_23_out_uop_fu_code_6 : issue_slots_22_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fu_code_7 = _T_220 ? io_dis_uops_0_bits_fu_code_7_0 : _T_219 ? issue_slots_23_out_uop_fu_code_7 : issue_slots_22_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fu_code_8 = _T_220 ? io_dis_uops_0_bits_fu_code_8_0 : _T_219 ? issue_slots_23_out_uop_fu_code_8 : issue_slots_22_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_fu_code_9 = _T_220 ? io_dis_uops_0_bits_fu_code_9_0 : _T_219 ? issue_slots_23_out_uop_fu_code_9 : issue_slots_22_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_iq_type_0 = _T_220 ? io_dis_uops_0_bits_iq_type_0_0 : _T_219 ? issue_slots_23_out_uop_iq_type_0 : issue_slots_22_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_iq_type_1 = _T_220 ? io_dis_uops_0_bits_iq_type_1_0 : _T_219 ? issue_slots_23_out_uop_iq_type_1 : issue_slots_22_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_iq_type_2 = _T_220 ? io_dis_uops_0_bits_iq_type_2_0 : _T_219 ? issue_slots_23_out_uop_iq_type_2 : issue_slots_22_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_iq_type_3 = _T_220 ? io_dis_uops_0_bits_iq_type_3_0 : _T_219 ? issue_slots_23_out_uop_iq_type_3 : issue_slots_22_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_debug_pc = _T_220 ? io_dis_uops_0_bits_debug_pc_0 : _T_219 ? issue_slots_23_out_uop_debug_pc : issue_slots_22_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_is_rvc = _T_220 ? io_dis_uops_0_bits_is_rvc_0 : _T_219 ? issue_slots_23_out_uop_is_rvc : issue_slots_22_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_debug_inst = _T_220 ? io_dis_uops_0_bits_debug_inst_0 : _T_219 ? issue_slots_23_out_uop_debug_inst : issue_slots_22_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_21_in_uop_bits_inst = _T_220 ? io_dis_uops_0_bits_inst_0 : _T_219 ? issue_slots_23_out_uop_inst : issue_slots_22_out_uop_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign _issue_slots_21_clear_T = \|shamts_oh_21; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_21_clear = _issue_slots_21_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_222 = shamts_oh_24 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_223 = shamts_oh_25 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_22_in_uop_valid = _T_223 ? will_be_valid_25 : _T_222 ? will_be_valid_24 : shamts_oh_23 == 3'h1 & issue_slots_23_will_be_valid; // @[issue-unit-age-ordered.scala:122:28, :158:23, :186:79, :191:33, :194:{28,48}, :195:37] assign issue_slots_22_in_uop_bits_debug_tsrc = _T_223 ? io_dis_uops_1_bits_debug_tsrc_0 : _T_222 ? io_dis_uops_0_bits_debug_tsrc_0 : issue_slots_23_out_uop_debug_tsrc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_debug_fsrc = _T_223 ? io_dis_uops_1_bits_debug_fsrc_0 : _T_222 ? io_dis_uops_0_bits_debug_fsrc_0 : issue_slots_23_out_uop_debug_fsrc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_bp_xcpt_if = _T_223 ? io_dis_uops_1_bits_bp_xcpt_if_0 : _T_222 ? io_dis_uops_0_bits_bp_xcpt_if_0 : issue_slots_23_out_uop_bp_xcpt_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_bp_debug_if = _T_223 ? io_dis_uops_1_bits_bp_debug_if_0 : _T_222 ? io_dis_uops_0_bits_bp_debug_if_0 : issue_slots_23_out_uop_bp_debug_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_xcpt_ma_if = _T_223 ? io_dis_uops_1_bits_xcpt_ma_if_0 : _T_222 ? io_dis_uops_0_bits_xcpt_ma_if_0 : issue_slots_23_out_uop_xcpt_ma_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_xcpt_ae_if = _T_223 ? io_dis_uops_1_bits_xcpt_ae_if_0 : _T_222 ? io_dis_uops_0_bits_xcpt_ae_if_0 : issue_slots_23_out_uop_xcpt_ae_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_xcpt_pf_if = _T_223 ? io_dis_uops_1_bits_xcpt_pf_if_0 : _T_222 ? io_dis_uops_0_bits_xcpt_pf_if_0 : issue_slots_23_out_uop_xcpt_pf_if; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_typ = _T_223 ? io_dis_uops_1_bits_fp_typ_0 : _T_222 ? io_dis_uops_0_bits_fp_typ_0 : issue_slots_23_out_uop_fp_typ; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_rm = _T_223 ? io_dis_uops_1_bits_fp_rm_0 : _T_222 ? io_dis_uops_0_bits_fp_rm_0 : issue_slots_23_out_uop_fp_rm; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_val = _T_223 ? io_dis_uops_1_bits_fp_val_0 : _T_222 ? io_dis_uops_0_bits_fp_val_0 : issue_slots_23_out_uop_fp_val; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fcn_op = _T_223 ? io_dis_uops_1_bits_fcn_op_0 : _T_222 ? io_dis_uops_0_bits_fcn_op_0 : issue_slots_23_out_uop_fcn_op; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fcn_dw = _T_223 ? io_dis_uops_1_bits_fcn_dw_0 : _T_222 ? io_dis_uops_0_bits_fcn_dw_0 : issue_slots_23_out_uop_fcn_dw; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_frs3_en = _T_223 ? io_dis_uops_1_bits_frs3_en_0 : _T_222 ? io_dis_uops_0_bits_frs3_en_0 : issue_slots_23_out_uop_frs3_en; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_lrs2_rtype = _T_223 ? io_dis_uops_1_bits_lrs2_rtype_0 : _T_222 ? io_dis_uops_0_bits_lrs2_rtype_0 : issue_slots_23_out_uop_lrs2_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_lrs1_rtype = _T_223 ? _WIRE_1_lrs1_rtype : _T_222 ? _WIRE_lrs1_rtype : issue_slots_23_out_uop_lrs1_rtype; // @[issue-unit-age-ordered.scala:35:17, :103:43, :104:32, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_dst_rtype = _T_223 ? io_dis_uops_1_bits_dst_rtype_0 : _T_222 ? io_dis_uops_0_bits_dst_rtype_0 : issue_slots_23_out_uop_dst_rtype; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_lrs3 = _T_223 ? io_dis_uops_1_bits_lrs3_0 : _T_222 ? io_dis_uops_0_bits_lrs3_0 : issue_slots_23_out_uop_lrs3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_lrs2 = _T_223 ? io_dis_uops_1_bits_lrs2_0 : _T_222 ? io_dis_uops_0_bits_lrs2_0 : issue_slots_23_out_uop_lrs2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_lrs1 = _T_223 ? io_dis_uops_1_bits_lrs1_0 : _T_222 ? io_dis_uops_0_bits_lrs1_0 : issue_slots_23_out_uop_lrs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_ldst = _T_223 ? io_dis_uops_1_bits_ldst_0 : _T_222 ? io_dis_uops_0_bits_ldst_0 : issue_slots_23_out_uop_ldst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_ldst_is_rs1 = _T_223 ? io_dis_uops_1_bits_ldst_is_rs1_0 : _T_222 ? io_dis_uops_0_bits_ldst_is_rs1_0 : issue_slots_23_out_uop_ldst_is_rs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_csr_cmd = _T_223 ? io_dis_uops_1_bits_csr_cmd_0 : _T_222 ? io_dis_uops_0_bits_csr_cmd_0 : issue_slots_23_out_uop_csr_cmd; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_flush_on_commit = _T_223 ? io_dis_uops_1_bits_flush_on_commit_0 : _T_222 ? io_dis_uops_0_bits_flush_on_commit_0 : issue_slots_23_out_uop_flush_on_commit; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_is_unique = _T_223 ? io_dis_uops_1_bits_is_unique_0 : _T_222 ? io_dis_uops_0_bits_is_unique_0 : issue_slots_23_out_uop_is_unique; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_uses_stq = _T_223 ? io_dis_uops_1_bits_uses_stq_0 : _T_222 ? io_dis_uops_0_bits_uses_stq_0 : issue_slots_23_out_uop_uses_stq; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_uses_ldq = _T_223 ? io_dis_uops_1_bits_uses_ldq_0 : _T_222 ? io_dis_uops_0_bits_uses_ldq_0 : issue_slots_23_out_uop_uses_ldq; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_mem_signed = _T_223 ? io_dis_uops_1_bits_mem_signed_0 : _T_222 ? io_dis_uops_0_bits_mem_signed_0 : issue_slots_23_out_uop_mem_signed; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_mem_size = _T_223 ? io_dis_uops_1_bits_mem_size_0 : _T_222 ? io_dis_uops_0_bits_mem_size_0 : issue_slots_23_out_uop_mem_size; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_mem_cmd = _T_223 ? io_dis_uops_1_bits_mem_cmd_0 : _T_222 ? io_dis_uops_0_bits_mem_cmd_0 : issue_slots_23_out_uop_mem_cmd; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_exc_cause = _T_223 ? io_dis_uops_1_bits_exc_cause_0 : _T_222 ? io_dis_uops_0_bits_exc_cause_0 : issue_slots_23_out_uop_exc_cause; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_exception = _T_223 ? io_dis_uops_1_bits_exception_0 : _T_222 ? io_dis_uops_0_bits_exception_0 : issue_slots_23_out_uop_exception; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_stale_pdst = _T_223 ? io_dis_uops_1_bits_stale_pdst_0 : _T_222 ? io_dis_uops_0_bits_stale_pdst_0 : issue_slots_23_out_uop_stale_pdst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] wire _GEN_0 = _T_223 \| _T_222; // @[issue-unit-age-ordered.scala:194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_ppred_busy = ~_GEN_0 & issue_slots_23_out_uop_ppred_busy; // @[issue-unit-age-ordered.scala:122:28, :194:48, :196:37] assign issue_slots_22_in_uop_bits_prs3_busy = _T_223 ? _WIRE_1_prs3_busy : _T_222 ? _WIRE_prs3_busy : issue_slots_23_out_uop_prs3_busy; // @[issue-unit-age-ordered.scala:35:17, :76:38, :77:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_prs2_busy = _T_223 ? _WIRE_1_prs2_busy : _T_222 ? _WIRE_prs2_busy : issue_slots_23_out_uop_prs2_busy; // @[issue-unit-age-ordered.scala:35:17, :65:38, :66:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_prs1_busy = _T_223 ? _WIRE_1_prs1_busy : _T_222 ? _WIRE_prs1_busy : issue_slots_23_out_uop_prs1_busy; // @[issue-unit-age-ordered.scala:35:17, :57:38, :58:29, :62:116, :103:43, :105:32, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_ppred = _T_223 ? io_dis_uops_1_bits_ppred_0 : _T_222 ? io_dis_uops_0_bits_ppred_0 : issue_slots_23_out_uop_ppred; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_prs3 = _T_223 ? io_dis_uops_1_bits_prs3_0 : _T_222 ? io_dis_uops_0_bits_prs3_0 : issue_slots_23_out_uop_prs3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_prs2 = _T_223 ? io_dis_uops_1_bits_prs2_0 : _T_222 ? io_dis_uops_0_bits_prs2_0 : issue_slots_23_out_uop_prs2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_prs1 = _T_223 ? io_dis_uops_1_bits_prs1_0 : _T_222 ? io_dis_uops_0_bits_prs1_0 : issue_slots_23_out_uop_prs1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_pdst = _T_223 ? io_dis_uops_1_bits_pdst_0 : _T_222 ? io_dis_uops_0_bits_pdst_0 : issue_slots_23_out_uop_pdst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_rxq_idx = _T_223 ? io_dis_uops_1_bits_rxq_idx_0 : _T_222 ? io_dis_uops_0_bits_rxq_idx_0 : issue_slots_23_out_uop_rxq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_stq_idx = _T_223 ? io_dis_uops_1_bits_stq_idx_0 : _T_222 ? io_dis_uops_0_bits_stq_idx_0 : issue_slots_23_out_uop_stq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_ldq_idx = _T_223 ? io_dis_uops_1_bits_ldq_idx_0 : _T_222 ? io_dis_uops_0_bits_ldq_idx_0 : issue_slots_23_out_uop_ldq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_rob_idx = _T_223 ? io_dis_uops_1_bits_rob_idx_0 : _T_222 ? io_dis_uops_0_bits_rob_idx_0 : issue_slots_23_out_uop_rob_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_vec = _T_223 ? io_dis_uops_1_bits_fp_ctrl_vec_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_vec_0 : issue_slots_23_out_uop_fp_ctrl_vec; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_wflags = _T_223 ? io_dis_uops_1_bits_fp_ctrl_wflags_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_wflags_0 : issue_slots_23_out_uop_fp_ctrl_wflags; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_sqrt = _T_223 ? io_dis_uops_1_bits_fp_ctrl_sqrt_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_sqrt_0 : issue_slots_23_out_uop_fp_ctrl_sqrt; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_div = _T_223 ? io_dis_uops_1_bits_fp_ctrl_div_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_div_0 : issue_slots_23_out_uop_fp_ctrl_div; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_fma = _T_223 ? io_dis_uops_1_bits_fp_ctrl_fma_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_fma_0 : issue_slots_23_out_uop_fp_ctrl_fma; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_fastpipe = _T_223 ? io_dis_uops_1_bits_fp_ctrl_fastpipe_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_fastpipe_0 : issue_slots_23_out_uop_fp_ctrl_fastpipe; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_toint = _T_223 ? io_dis_uops_1_bits_fp_ctrl_toint_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_toint_0 : issue_slots_23_out_uop_fp_ctrl_toint; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_fromint = _T_223 ? io_dis_uops_1_bits_fp_ctrl_fromint_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_fromint_0 : issue_slots_23_out_uop_fp_ctrl_fromint; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_typeTagOut = _T_223 ? io_dis_uops_1_bits_fp_ctrl_typeTagOut_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_typeTagOut_0 : issue_slots_23_out_uop_fp_ctrl_typeTagOut; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_typeTagIn = _T_223 ? io_dis_uops_1_bits_fp_ctrl_typeTagIn_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_typeTagIn_0 : issue_slots_23_out_uop_fp_ctrl_typeTagIn; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_swap23 = _T_223 ? io_dis_uops_1_bits_fp_ctrl_swap23_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_swap23_0 : issue_slots_23_out_uop_fp_ctrl_swap23; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_swap12 = _T_223 ? io_dis_uops_1_bits_fp_ctrl_swap12_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_swap12_0 : issue_slots_23_out_uop_fp_ctrl_swap12; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_ren3 = _T_223 ? io_dis_uops_1_bits_fp_ctrl_ren3_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_ren3_0 : issue_slots_23_out_uop_fp_ctrl_ren3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_ren2 = _T_223 ? io_dis_uops_1_bits_fp_ctrl_ren2_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_ren2_0 : issue_slots_23_out_uop_fp_ctrl_ren2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_ren1 = _T_223 ? io_dis_uops_1_bits_fp_ctrl_ren1_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_ren1_0 : issue_slots_23_out_uop_fp_ctrl_ren1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_wen = _T_223 ? io_dis_uops_1_bits_fp_ctrl_wen_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_wen_0 : issue_slots_23_out_uop_fp_ctrl_wen; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fp_ctrl_ldst = _T_223 ? io_dis_uops_1_bits_fp_ctrl_ldst_0 : _T_222 ? io_dis_uops_0_bits_fp_ctrl_ldst_0 : issue_slots_23_out_uop_fp_ctrl_ldst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_op2_sel = _T_223 ? io_dis_uops_1_bits_op2_sel_0 : _T_222 ? io_dis_uops_0_bits_op2_sel_0 : issue_slots_23_out_uop_op2_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_op1_sel = _T_223 ? io_dis_uops_1_bits_op1_sel_0 : _T_222 ? io_dis_uops_0_bits_op1_sel_0 : issue_slots_23_out_uop_op1_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_imm_packed = _T_223 ? io_dis_uops_1_bits_imm_packed_0 : _T_222 ? io_dis_uops_0_bits_imm_packed_0 : issue_slots_23_out_uop_imm_packed; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_pimm = _T_223 ? io_dis_uops_1_bits_pimm_0 : _T_222 ? io_dis_uops_0_bits_pimm_0 : issue_slots_23_out_uop_pimm; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_imm_sel = _T_223 ? io_dis_uops_1_bits_imm_sel_0 : _T_222 ? io_dis_uops_0_bits_imm_sel_0 : issue_slots_23_out_uop_imm_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_imm_rename = _T_223 ? io_dis_uops_1_bits_imm_rename_0 : _T_222 ? io_dis_uops_0_bits_imm_rename_0 : issue_slots_23_out_uop_imm_rename; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_taken = _T_223 ? io_dis_uops_1_bits_taken_0 : _T_222 ? io_dis_uops_0_bits_taken_0 : issue_slots_23_out_uop_taken; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_pc_lob = _T_223 ? io_dis_uops_1_bits_pc_lob_0 : _T_222 ? io_dis_uops_0_bits_pc_lob_0 : issue_slots_23_out_uop_pc_lob; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_edge_inst = _T_223 ? io_dis_uops_1_bits_edge_inst_0 : _T_222 ? io_dis_uops_0_bits_edge_inst_0 : issue_slots_23_out_uop_edge_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_ftq_idx = _T_223 ? io_dis_uops_1_bits_ftq_idx_0 : _T_222 ? io_dis_uops_0_bits_ftq_idx_0 : issue_slots_23_out_uop_ftq_idx; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_is_mov = _T_223 ? io_dis_uops_1_bits_is_mov_0 : _T_222 ? io_dis_uops_0_bits_is_mov_0 : issue_slots_23_out_uop_is_mov; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_is_rocc = _T_223 ? io_dis_uops_1_bits_is_rocc_0 : _T_222 ? io_dis_uops_0_bits_is_rocc_0 : issue_slots_23_out_uop_is_rocc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_is_sys_pc2epc = _T_223 ? io_dis_uops_1_bits_is_sys_pc2epc_0 : _T_222 ? io_dis_uops_0_bits_is_sys_pc2epc_0 : issue_slots_23_out_uop_is_sys_pc2epc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_is_eret = _T_223 ? io_dis_uops_1_bits_is_eret_0 : _T_222 ? io_dis_uops_0_bits_is_eret_0 : issue_slots_23_out_uop_is_eret; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_is_amo = _T_223 ? io_dis_uops_1_bits_is_amo_0 : _T_222 ? io_dis_uops_0_bits_is_amo_0 : issue_slots_23_out_uop_is_amo; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_is_sfence = _T_223 ? io_dis_uops_1_bits_is_sfence_0 : _T_222 ? io_dis_uops_0_bits_is_sfence_0 : issue_slots_23_out_uop_is_sfence; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_is_fencei = _T_223 ? io_dis_uops_1_bits_is_fencei_0 : _T_222 ? io_dis_uops_0_bits_is_fencei_0 : issue_slots_23_out_uop_is_fencei; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_is_fence = _T_223 ? io_dis_uops_1_bits_is_fence_0 : _T_222 ? io_dis_uops_0_bits_is_fence_0 : issue_slots_23_out_uop_is_fence; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_is_sfb = _T_223 ? io_dis_uops_1_bits_is_sfb_0 : _T_222 ? io_dis_uops_0_bits_is_sfb_0 : issue_slots_23_out_uop_is_sfb; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_br_type = _T_223 ? io_dis_uops_1_bits_br_type_0 : _T_222 ? io_dis_uops_0_bits_br_type_0 : issue_slots_23_out_uop_br_type; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_br_tag = _T_223 ? io_dis_uops_1_bits_br_tag_0 : _T_222 ? io_dis_uops_0_bits_br_tag_0 : issue_slots_23_out_uop_br_tag; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_br_mask = _T_223 ? io_dis_uops_1_bits_br_mask_0 : _T_222 ? io_dis_uops_0_bits_br_mask_0 : issue_slots_23_out_uop_br_mask; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_dis_col_sel = _T_223 ? io_dis_uops_1_bits_dis_col_sel_0 : _T_222 ? io_dis_uops_0_bits_dis_col_sel_0 : issue_slots_23_out_uop_dis_col_sel; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_iw_p3_bypass_hint = _T_223 ? _WIRE_1_iw_p3_bypass_hint : _T_222 ? _WIRE_iw_p3_bypass_hint : issue_slots_23_out_uop_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:41:35, :76:38, :78:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_iw_p2_bypass_hint = _T_223 ? _WIRE_1_iw_p2_bypass_hint : _T_222 ? _WIRE_iw_p2_bypass_hint : issue_slots_23_out_uop_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:40:35, :65:38, :68:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_iw_p1_bypass_hint = _T_223 ? _WIRE_1_iw_p1_bypass_hint : _T_222 ? _WIRE_iw_p1_bypass_hint : issue_slots_23_out_uop_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:39:35, :57:38, :60:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_iw_p2_speculative_child = _T_223 ? _WIRE_1_iw_p2_speculative_child : ~_T_222 \| _T_12 ? 3'h0 : io_dis_uops_0_bits_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :65:{32,38}, :67:43, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_iw_p1_speculative_child = _T_223 ? _WIRE_1_iw_p1_speculative_child : ~_T_222 \| _T ? 3'h0 : io_dis_uops_0_bits_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :57:{32,38}, :59:43, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_iw_issued = ~_GEN_0 & issue_slots_23_out_uop_iw_issued; // @[issue-unit-age-ordered.scala:122:28, :194:48, :196:37] assign issue_slots_22_in_uop_bits_fu_code_0 = _T_223 ? io_dis_uops_1_bits_fu_code_0_0 : _T_222 ? io_dis_uops_0_bits_fu_code_0_0 : issue_slots_23_out_uop_fu_code_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fu_code_1 = _T_223 ? io_dis_uops_1_bits_fu_code_1_0 : _T_222 ? io_dis_uops_0_bits_fu_code_1_0 : issue_slots_23_out_uop_fu_code_1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fu_code_2 = _T_223 ? io_dis_uops_1_bits_fu_code_2_0 : _T_222 ? io_dis_uops_0_bits_fu_code_2_0 : issue_slots_23_out_uop_fu_code_2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fu_code_3 = _T_223 ? io_dis_uops_1_bits_fu_code_3_0 : _T_222 ? io_dis_uops_0_bits_fu_code_3_0 : issue_slots_23_out_uop_fu_code_3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fu_code_4 = _T_223 ? io_dis_uops_1_bits_fu_code_4_0 : _T_222 ? io_dis_uops_0_bits_fu_code_4_0 : issue_slots_23_out_uop_fu_code_4; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fu_code_5 = _T_223 ? io_dis_uops_1_bits_fu_code_5_0 : _T_222 ? io_dis_uops_0_bits_fu_code_5_0 : issue_slots_23_out_uop_fu_code_5; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fu_code_6 = _T_223 ? io_dis_uops_1_bits_fu_code_6_0 : _T_222 ? io_dis_uops_0_bits_fu_code_6_0 : issue_slots_23_out_uop_fu_code_6; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fu_code_7 = _T_223 ? io_dis_uops_1_bits_fu_code_7_0 : _T_222 ? io_dis_uops_0_bits_fu_code_7_0 : issue_slots_23_out_uop_fu_code_7; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fu_code_8 = _T_223 ? io_dis_uops_1_bits_fu_code_8_0 : _T_222 ? io_dis_uops_0_bits_fu_code_8_0 : issue_slots_23_out_uop_fu_code_8; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_fu_code_9 = _T_223 ? io_dis_uops_1_bits_fu_code_9_0 : _T_222 ? io_dis_uops_0_bits_fu_code_9_0 : issue_slots_23_out_uop_fu_code_9; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_iq_type_0 = _T_223 ? io_dis_uops_1_bits_iq_type_0_0 : _T_222 ? io_dis_uops_0_bits_iq_type_0_0 : issue_slots_23_out_uop_iq_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_iq_type_1 = _T_223 ? io_dis_uops_1_bits_iq_type_1_0 : _T_222 ? io_dis_uops_0_bits_iq_type_1_0 : issue_slots_23_out_uop_iq_type_1; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_iq_type_2 = _T_223 ? io_dis_uops_1_bits_iq_type_2_0 : _T_222 ? io_dis_uops_0_bits_iq_type_2_0 : issue_slots_23_out_uop_iq_type_2; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_iq_type_3 = _T_223 ? io_dis_uops_1_bits_iq_type_3_0 : _T_222 ? io_dis_uops_0_bits_iq_type_3_0 : issue_slots_23_out_uop_iq_type_3; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_debug_pc = _T_223 ? io_dis_uops_1_bits_debug_pc_0 : _T_222 ? io_dis_uops_0_bits_debug_pc_0 : issue_slots_23_out_uop_debug_pc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_is_rvc = _T_223 ? io_dis_uops_1_bits_is_rvc_0 : _T_222 ? io_dis_uops_0_bits_is_rvc_0 : issue_slots_23_out_uop_is_rvc; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_debug_inst = _T_223 ? io_dis_uops_1_bits_debug_inst_0 : _T_222 ? io_dis_uops_0_bits_debug_inst_0 : issue_slots_23_out_uop_debug_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_22_in_uop_bits_inst = _T_223 ? io_dis_uops_1_bits_inst_0 : _T_222 ? io_dis_uops_0_bits_inst_0 : issue_slots_23_out_uop_inst; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign _issue_slots_22_clear_T = \|shamts_oh_22; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_22_clear = _issue_slots_22_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] wire _T_225 = shamts_oh_25 == 3'h2; // @[issue-unit-age-ordered.scala:158:23, :194:28] wire _T_226 = shamts_oh_26 == 3'h4; // @[issue-unit-age-ordered.scala:158:23, :194:28] assign issue_slots_23_in_uop_valid = _T_226 ? will_be_valid_26 : _T_225 ? will_be_valid_25 : shamts_oh_24 == 3'h1 & will_be_valid_24; // @[issue-unit-age-ordered.scala:122:28, :158:23, :186:79, :191:33, :194:{28,48}, :195:37] assign issue_slots_23_in_uop_bits_debug_tsrc = _T_226 ? io_dis_uops_2_bits_debug_tsrc_0 : _T_225 ? io_dis_uops_1_bits_debug_tsrc_0 : io_dis_uops_0_bits_debug_tsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_debug_fsrc = _T_226 ? io_dis_uops_2_bits_debug_fsrc_0 : _T_225 ? io_dis_uops_1_bits_debug_fsrc_0 : io_dis_uops_0_bits_debug_fsrc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_bp_xcpt_if = _T_226 ? io_dis_uops_2_bits_bp_xcpt_if_0 : _T_225 ? io_dis_uops_1_bits_bp_xcpt_if_0 : io_dis_uops_0_bits_bp_xcpt_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_bp_debug_if = _T_226 ? io_dis_uops_2_bits_bp_debug_if_0 : _T_225 ? io_dis_uops_1_bits_bp_debug_if_0 : io_dis_uops_0_bits_bp_debug_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_xcpt_ma_if = _T_226 ? io_dis_uops_2_bits_xcpt_ma_if_0 : _T_225 ? io_dis_uops_1_bits_xcpt_ma_if_0 : io_dis_uops_0_bits_xcpt_ma_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_xcpt_ae_if = _T_226 ? io_dis_uops_2_bits_xcpt_ae_if_0 : _T_225 ? io_dis_uops_1_bits_xcpt_ae_if_0 : io_dis_uops_0_bits_xcpt_ae_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_xcpt_pf_if = _T_226 ? io_dis_uops_2_bits_xcpt_pf_if_0 : _T_225 ? io_dis_uops_1_bits_xcpt_pf_if_0 : io_dis_uops_0_bits_xcpt_pf_if_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_typ = _T_226 ? io_dis_uops_2_bits_fp_typ_0 : _T_225 ? io_dis_uops_1_bits_fp_typ_0 : io_dis_uops_0_bits_fp_typ_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_rm = _T_226 ? io_dis_uops_2_bits_fp_rm_0 : _T_225 ? io_dis_uops_1_bits_fp_rm_0 : io_dis_uops_0_bits_fp_rm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_val = _T_226 ? io_dis_uops_2_bits_fp_val_0 : _T_225 ? io_dis_uops_1_bits_fp_val_0 : io_dis_uops_0_bits_fp_val_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fcn_op = _T_226 ? io_dis_uops_2_bits_fcn_op_0 : _T_225 ? io_dis_uops_1_bits_fcn_op_0 : io_dis_uops_0_bits_fcn_op_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fcn_dw = _T_226 ? io_dis_uops_2_bits_fcn_dw_0 : _T_225 ? io_dis_uops_1_bits_fcn_dw_0 : io_dis_uops_0_bits_fcn_dw_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_frs3_en = _T_226 ? io_dis_uops_2_bits_frs3_en_0 : _T_225 ? io_dis_uops_1_bits_frs3_en_0 : io_dis_uops_0_bits_frs3_en_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_lrs2_rtype = _T_226 ? io_dis_uops_2_bits_lrs2_rtype_0 : _T_225 ? io_dis_uops_1_bits_lrs2_rtype_0 : io_dis_uops_0_bits_lrs2_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_lrs1_rtype = _T_226 ? (io_dis_uops_2_bits_uses_stq_0 ? 2'h2 : io_dis_uops_2_bits_lrs1_rtype_0) : _T_225 ? _WIRE_1_lrs1_rtype : _WIRE_lrs1_rtype; // @[issue-unit-age-ordered.scala:22:7, :35:17, :103:43, :104:32, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_dst_rtype = _T_226 ? io_dis_uops_2_bits_dst_rtype_0 : _T_225 ? io_dis_uops_1_bits_dst_rtype_0 : io_dis_uops_0_bits_dst_rtype_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_lrs3 = _T_226 ? io_dis_uops_2_bits_lrs3_0 : _T_225 ? io_dis_uops_1_bits_lrs3_0 : io_dis_uops_0_bits_lrs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_lrs2 = _T_226 ? io_dis_uops_2_bits_lrs2_0 : _T_225 ? io_dis_uops_1_bits_lrs2_0 : io_dis_uops_0_bits_lrs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_lrs1 = _T_226 ? io_dis_uops_2_bits_lrs1_0 : _T_225 ? io_dis_uops_1_bits_lrs1_0 : io_dis_uops_0_bits_lrs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_ldst = _T_226 ? io_dis_uops_2_bits_ldst_0 : _T_225 ? io_dis_uops_1_bits_ldst_0 : io_dis_uops_0_bits_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_ldst_is_rs1 = _T_226 ? io_dis_uops_2_bits_ldst_is_rs1_0 : _T_225 ? io_dis_uops_1_bits_ldst_is_rs1_0 : io_dis_uops_0_bits_ldst_is_rs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_csr_cmd = _T_226 ? io_dis_uops_2_bits_csr_cmd_0 : _T_225 ? io_dis_uops_1_bits_csr_cmd_0 : io_dis_uops_0_bits_csr_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_flush_on_commit = _T_226 ? io_dis_uops_2_bits_flush_on_commit_0 : _T_225 ? io_dis_uops_1_bits_flush_on_commit_0 : io_dis_uops_0_bits_flush_on_commit_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_is_unique = _T_226 ? io_dis_uops_2_bits_is_unique_0 : _T_225 ? io_dis_uops_1_bits_is_unique_0 : io_dis_uops_0_bits_is_unique_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_uses_stq = _T_226 ? io_dis_uops_2_bits_uses_stq_0 : _T_225 ? io_dis_uops_1_bits_uses_stq_0 : io_dis_uops_0_bits_uses_stq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_uses_ldq = _T_226 ? io_dis_uops_2_bits_uses_ldq_0 : _T_225 ? io_dis_uops_1_bits_uses_ldq_0 : io_dis_uops_0_bits_uses_ldq_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_mem_signed = _T_226 ? io_dis_uops_2_bits_mem_signed_0 : _T_225 ? io_dis_uops_1_bits_mem_signed_0 : io_dis_uops_0_bits_mem_signed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_mem_size = _T_226 ? io_dis_uops_2_bits_mem_size_0 : _T_225 ? io_dis_uops_1_bits_mem_size_0 : io_dis_uops_0_bits_mem_size_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_mem_cmd = _T_226 ? io_dis_uops_2_bits_mem_cmd_0 : _T_225 ? io_dis_uops_1_bits_mem_cmd_0 : io_dis_uops_0_bits_mem_cmd_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_exc_cause = _T_226 ? io_dis_uops_2_bits_exc_cause_0 : _T_225 ? io_dis_uops_1_bits_exc_cause_0 : io_dis_uops_0_bits_exc_cause_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_exception = _T_226 ? io_dis_uops_2_bits_exception_0 : _T_225 ? io_dis_uops_1_bits_exception_0 : io_dis_uops_0_bits_exception_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_stale_pdst = _T_226 ? io_dis_uops_2_bits_stale_pdst_0 : _T_225 ? io_dis_uops_1_bits_stale_pdst_0 : io_dis_uops_0_bits_stale_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_prs3_busy = _T_226 ? ~_T_94 & io_dis_uops_2_bits_prs3_busy_0 : _T_225 ? _WIRE_1_prs3_busy : _WIRE_prs3_busy; // @[issue-unit-age-ordered.scala:22:7, :35:17, :76:{32,38}, :77:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_prs2_busy = _T_226 ? ~_T_82 & io_dis_uops_2_bits_prs2_busy_0 : _T_225 ? _WIRE_1_prs2_busy : _WIRE_prs2_busy; // @[issue-unit-age-ordered.scala:22:7, :35:17, :65:{32,38}, :66:29, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_prs1_busy = _T_226 ? ~io_dis_uops_2_bits_uses_stq_0 & ~_T_70 & io_dis_uops_2_bits_prs1_busy_0 : _T_225 ? _WIRE_1_prs1_busy : _WIRE_prs1_busy; // @[issue-unit-age-ordered.scala:22:7, :35:17, :57:{32,38}, :58:29, :62:116, :103:43, :105:32, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_ppred = _T_226 ? io_dis_uops_2_bits_ppred_0 : _T_225 ? io_dis_uops_1_bits_ppred_0 : io_dis_uops_0_bits_ppred_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_prs3 = _T_226 ? io_dis_uops_2_bits_prs3_0 : _T_225 ? io_dis_uops_1_bits_prs3_0 : io_dis_uops_0_bits_prs3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_prs2 = _T_226 ? io_dis_uops_2_bits_prs2_0 : _T_225 ? io_dis_uops_1_bits_prs2_0 : io_dis_uops_0_bits_prs2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_prs1 = _T_226 ? io_dis_uops_2_bits_prs1_0 : _T_225 ? io_dis_uops_1_bits_prs1_0 : io_dis_uops_0_bits_prs1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_pdst = _T_226 ? io_dis_uops_2_bits_pdst_0 : _T_225 ? io_dis_uops_1_bits_pdst_0 : io_dis_uops_0_bits_pdst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_rxq_idx = _T_226 ? io_dis_uops_2_bits_rxq_idx_0 : _T_225 ? io_dis_uops_1_bits_rxq_idx_0 : io_dis_uops_0_bits_rxq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_stq_idx = _T_226 ? io_dis_uops_2_bits_stq_idx_0 : _T_225 ? io_dis_uops_1_bits_stq_idx_0 : io_dis_uops_0_bits_stq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_ldq_idx = _T_226 ? io_dis_uops_2_bits_ldq_idx_0 : _T_225 ? io_dis_uops_1_bits_ldq_idx_0 : io_dis_uops_0_bits_ldq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_rob_idx = _T_226 ? io_dis_uops_2_bits_rob_idx_0 : _T_225 ? io_dis_uops_1_bits_rob_idx_0 : io_dis_uops_0_bits_rob_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_vec = _T_226 ? io_dis_uops_2_bits_fp_ctrl_vec_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_vec_0 : io_dis_uops_0_bits_fp_ctrl_vec_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_wflags = _T_226 ? io_dis_uops_2_bits_fp_ctrl_wflags_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_wflags_0 : io_dis_uops_0_bits_fp_ctrl_wflags_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_sqrt = _T_226 ? io_dis_uops_2_bits_fp_ctrl_sqrt_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_sqrt_0 : io_dis_uops_0_bits_fp_ctrl_sqrt_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_div = _T_226 ? io_dis_uops_2_bits_fp_ctrl_div_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_div_0 : io_dis_uops_0_bits_fp_ctrl_div_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_fma = _T_226 ? io_dis_uops_2_bits_fp_ctrl_fma_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_fma_0 : io_dis_uops_0_bits_fp_ctrl_fma_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_fastpipe = _T_226 ? io_dis_uops_2_bits_fp_ctrl_fastpipe_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_fastpipe_0 : io_dis_uops_0_bits_fp_ctrl_fastpipe_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_toint = _T_226 ? io_dis_uops_2_bits_fp_ctrl_toint_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_toint_0 : io_dis_uops_0_bits_fp_ctrl_toint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_fromint = _T_226 ? io_dis_uops_2_bits_fp_ctrl_fromint_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_fromint_0 : io_dis_uops_0_bits_fp_ctrl_fromint_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_typeTagOut = _T_226 ? io_dis_uops_2_bits_fp_ctrl_typeTagOut_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_typeTagOut_0 : io_dis_uops_0_bits_fp_ctrl_typeTagOut_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_typeTagIn = _T_226 ? io_dis_uops_2_bits_fp_ctrl_typeTagIn_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_typeTagIn_0 : io_dis_uops_0_bits_fp_ctrl_typeTagIn_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_swap23 = _T_226 ? io_dis_uops_2_bits_fp_ctrl_swap23_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_swap23_0 : io_dis_uops_0_bits_fp_ctrl_swap23_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_swap12 = _T_226 ? io_dis_uops_2_bits_fp_ctrl_swap12_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_swap12_0 : io_dis_uops_0_bits_fp_ctrl_swap12_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_ren3 = _T_226 ? io_dis_uops_2_bits_fp_ctrl_ren3_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_ren3_0 : io_dis_uops_0_bits_fp_ctrl_ren3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_ren2 = _T_226 ? io_dis_uops_2_bits_fp_ctrl_ren2_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_ren2_0 : io_dis_uops_0_bits_fp_ctrl_ren2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_ren1 = _T_226 ? io_dis_uops_2_bits_fp_ctrl_ren1_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_ren1_0 : io_dis_uops_0_bits_fp_ctrl_ren1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_wen = _T_226 ? io_dis_uops_2_bits_fp_ctrl_wen_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_wen_0 : io_dis_uops_0_bits_fp_ctrl_wen_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fp_ctrl_ldst = _T_226 ? io_dis_uops_2_bits_fp_ctrl_ldst_0 : _T_225 ? io_dis_uops_1_bits_fp_ctrl_ldst_0 : io_dis_uops_0_bits_fp_ctrl_ldst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_op2_sel = _T_226 ? io_dis_uops_2_bits_op2_sel_0 : _T_225 ? io_dis_uops_1_bits_op2_sel_0 : io_dis_uops_0_bits_op2_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_op1_sel = _T_226 ? io_dis_uops_2_bits_op1_sel_0 : _T_225 ? io_dis_uops_1_bits_op1_sel_0 : io_dis_uops_0_bits_op1_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_imm_packed = _T_226 ? io_dis_uops_2_bits_imm_packed_0 : _T_225 ? io_dis_uops_1_bits_imm_packed_0 : io_dis_uops_0_bits_imm_packed_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_pimm = _T_226 ? io_dis_uops_2_bits_pimm_0 : _T_225 ? io_dis_uops_1_bits_pimm_0 : io_dis_uops_0_bits_pimm_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_imm_sel = _T_226 ? io_dis_uops_2_bits_imm_sel_0 : _T_225 ? io_dis_uops_1_bits_imm_sel_0 : io_dis_uops_0_bits_imm_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_imm_rename = _T_226 ? io_dis_uops_2_bits_imm_rename_0 : _T_225 ? io_dis_uops_1_bits_imm_rename_0 : io_dis_uops_0_bits_imm_rename_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_taken = _T_226 ? io_dis_uops_2_bits_taken_0 : _T_225 ? io_dis_uops_1_bits_taken_0 : io_dis_uops_0_bits_taken_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_pc_lob = _T_226 ? io_dis_uops_2_bits_pc_lob_0 : _T_225 ? io_dis_uops_1_bits_pc_lob_0 : io_dis_uops_0_bits_pc_lob_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_edge_inst = _T_226 ? io_dis_uops_2_bits_edge_inst_0 : _T_225 ? io_dis_uops_1_bits_edge_inst_0 : io_dis_uops_0_bits_edge_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_ftq_idx = _T_226 ? io_dis_uops_2_bits_ftq_idx_0 : _T_225 ? io_dis_uops_1_bits_ftq_idx_0 : io_dis_uops_0_bits_ftq_idx_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_is_mov = _T_226 ? io_dis_uops_2_bits_is_mov_0 : _T_225 ? io_dis_uops_1_bits_is_mov_0 : io_dis_uops_0_bits_is_mov_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_is_rocc = _T_226 ? io_dis_uops_2_bits_is_rocc_0 : _T_225 ? io_dis_uops_1_bits_is_rocc_0 : io_dis_uops_0_bits_is_rocc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_is_sys_pc2epc = _T_226 ? io_dis_uops_2_bits_is_sys_pc2epc_0 : _T_225 ? io_dis_uops_1_bits_is_sys_pc2epc_0 : io_dis_uops_0_bits_is_sys_pc2epc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_is_eret = _T_226 ? io_dis_uops_2_bits_is_eret_0 : _T_225 ? io_dis_uops_1_bits_is_eret_0 : io_dis_uops_0_bits_is_eret_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_is_amo = _T_226 ? io_dis_uops_2_bits_is_amo_0 : _T_225 ? io_dis_uops_1_bits_is_amo_0 : io_dis_uops_0_bits_is_amo_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_is_sfence = _T_226 ? io_dis_uops_2_bits_is_sfence_0 : _T_225 ? io_dis_uops_1_bits_is_sfence_0 : io_dis_uops_0_bits_is_sfence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_is_fencei = _T_226 ? io_dis_uops_2_bits_is_fencei_0 : _T_225 ? io_dis_uops_1_bits_is_fencei_0 : io_dis_uops_0_bits_is_fencei_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_is_fence = _T_226 ? io_dis_uops_2_bits_is_fence_0 : _T_225 ? io_dis_uops_1_bits_is_fence_0 : io_dis_uops_0_bits_is_fence_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_is_sfb = _T_226 ? io_dis_uops_2_bits_is_sfb_0 : _T_225 ? io_dis_uops_1_bits_is_sfb_0 : io_dis_uops_0_bits_is_sfb_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_br_type = _T_226 ? io_dis_uops_2_bits_br_type_0 : _T_225 ? io_dis_uops_1_bits_br_type_0 : io_dis_uops_0_bits_br_type_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_br_tag = _T_226 ? io_dis_uops_2_bits_br_tag_0 : _T_225 ? io_dis_uops_1_bits_br_tag_0 : io_dis_uops_0_bits_br_tag_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_br_mask = _T_226 ? io_dis_uops_2_bits_br_mask_0 : _T_225 ? io_dis_uops_1_bits_br_mask_0 : io_dis_uops_0_bits_br_mask_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_dis_col_sel = _T_226 ? io_dis_uops_2_bits_dis_col_sel_0 : _T_225 ? io_dis_uops_1_bits_dis_col_sel_0 : io_dis_uops_0_bits_dis_col_sel_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_iw_p3_bypass_hint = _T_226 ? _T_94 & prs3_wakeups_0_2 : _T_225 ? _WIRE_1_iw_p3_bypass_hint : _WIRE_iw_p3_bypass_hint; // @[issue-unit-age-ordered.scala:41:35, :49:89, :76:{32,38}, :78:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_iw_p2_bypass_hint = _T_226 ? _T_82 & prs2_wakeups_0_2 : _T_225 ? _WIRE_1_iw_p2_bypass_hint : _WIRE_iw_p2_bypass_hint; // @[issue-unit-age-ordered.scala:40:35, :48:89, :65:{32,38}, :68:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_iw_p1_bypass_hint = _T_226 ? _T_70 & prs1_wakeups_0_2 : _T_225 ? _WIRE_1_iw_p1_bypass_hint : _WIRE_iw_p1_bypass_hint; // @[issue-unit-age-ordered.scala:39:35, :47:89, :57:{32,38}, :60:37, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_iw_p2_speculative_child = _T_226 ? (_T_82 ? 3'h0 : io_dis_uops_2_bits_iw_p2_speculative_child_0) : _T_225 ? _WIRE_1_iw_p2_speculative_child : _T_12 ? 3'h0 : io_dis_uops_0_bits_iw_p2_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :65:{32,38}, :67:43, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_iw_p1_speculative_child = _T_226 ? (_T_70 ? 3'h0 : io_dis_uops_2_bits_iw_p1_speculative_child_0) : _T_225 ? _WIRE_1_iw_p1_speculative_child : _T ? 3'h0 : io_dis_uops_0_bits_iw_p1_speculative_child_0; // @[issue-unit-age-ordered.scala:22:7, :35:17, :57:{32,38}, :59:43, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fu_code_0 = _T_226 ? io_dis_uops_2_bits_fu_code_0_0 : _T_225 ? io_dis_uops_1_bits_fu_code_0_0 : io_dis_uops_0_bits_fu_code_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fu_code_1 = _T_226 ? io_dis_uops_2_bits_fu_code_1_0 : _T_225 ? io_dis_uops_1_bits_fu_code_1_0 : io_dis_uops_0_bits_fu_code_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fu_code_2 = _T_226 ? io_dis_uops_2_bits_fu_code_2_0 : _T_225 ? io_dis_uops_1_bits_fu_code_2_0 : io_dis_uops_0_bits_fu_code_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fu_code_3 = _T_226 ? io_dis_uops_2_bits_fu_code_3_0 : _T_225 ? io_dis_uops_1_bits_fu_code_3_0 : io_dis_uops_0_bits_fu_code_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fu_code_4 = _T_226 ? io_dis_uops_2_bits_fu_code_4_0 : _T_225 ? io_dis_uops_1_bits_fu_code_4_0 : io_dis_uops_0_bits_fu_code_4_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fu_code_5 = _T_226 ? io_dis_uops_2_bits_fu_code_5_0 : _T_225 ? io_dis_uops_1_bits_fu_code_5_0 : io_dis_uops_0_bits_fu_code_5_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fu_code_6 = _T_226 ? io_dis_uops_2_bits_fu_code_6_0 : _T_225 ? io_dis_uops_1_bits_fu_code_6_0 : io_dis_uops_0_bits_fu_code_6_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fu_code_7 = _T_226 ? io_dis_uops_2_bits_fu_code_7_0 : _T_225 ? io_dis_uops_1_bits_fu_code_7_0 : io_dis_uops_0_bits_fu_code_7_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fu_code_8 = _T_226 ? io_dis_uops_2_bits_fu_code_8_0 : _T_225 ? io_dis_uops_1_bits_fu_code_8_0 : io_dis_uops_0_bits_fu_code_8_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_fu_code_9 = _T_226 ? io_dis_uops_2_bits_fu_code_9_0 : _T_225 ? io_dis_uops_1_bits_fu_code_9_0 : io_dis_uops_0_bits_fu_code_9_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_iq_type_0 = _T_226 ? io_dis_uops_2_bits_iq_type_0_0 : _T_225 ? io_dis_uops_1_bits_iq_type_0_0 : io_dis_uops_0_bits_iq_type_0_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_iq_type_1 = _T_226 ? io_dis_uops_2_bits_iq_type_1_0 : _T_225 ? io_dis_uops_1_bits_iq_type_1_0 : io_dis_uops_0_bits_iq_type_1_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_iq_type_2 = _T_226 ? io_dis_uops_2_bits_iq_type_2_0 : _T_225 ? io_dis_uops_1_bits_iq_type_2_0 : io_dis_uops_0_bits_iq_type_2_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_iq_type_3 = _T_226 ? io_dis_uops_2_bits_iq_type_3_0 : _T_225 ? io_dis_uops_1_bits_iq_type_3_0 : io_dis_uops_0_bits_iq_type_3_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_debug_pc = _T_226 ? io_dis_uops_2_bits_debug_pc_0 : _T_225 ? io_dis_uops_1_bits_debug_pc_0 : io_dis_uops_0_bits_debug_pc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_is_rvc = _T_226 ? io_dis_uops_2_bits_is_rvc_0 : _T_225 ? io_dis_uops_1_bits_is_rvc_0 : io_dis_uops_0_bits_is_rvc_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_debug_inst = _T_226 ? io_dis_uops_2_bits_debug_inst_0 : _T_225 ? io_dis_uops_1_bits_debug_inst_0 : io_dis_uops_0_bits_debug_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign issue_slots_23_in_uop_bits_inst = _T_226 ? io_dis_uops_2_bits_inst_0 : _T_225 ? io_dis_uops_1_bits_inst_0 : io_dis_uops_0_bits_inst_0; // @[issue-unit-age-ordered.scala:22:7, :122:28, :194:{28,48}, :196:37] assign _issue_slots_23_clear_T = \|shamts_oh_23; // @[issue-unit-age-ordered.scala:158:23, :163:21, :199:49] assign issue_slots_23_clear = _issue_slots_23_clear_T; // @[issue-unit-age-ordered.scala:122:28, :199:49] reg is_available_0; // @[issue-unit-age-ordered.scala:208:25] reg is_available_1; // @[issue-unit-age-ordered.scala:208:25] reg is_available_2; // @[issue-unit-age-ordered.scala:208:25] reg is_available_3; // @[issue-unit-age-ordered.scala:208:25] reg is_available_4; // @[issue-unit-age-ordered.scala:208:25] reg is_available_5; // @[issue-unit-age-ordered.scala:208:25] reg is_available_6; // @[issue-unit-age-ordered.scala:208:25] reg is_available_7; // @[issue-unit-age-ordered.scala:208:25] reg is_available_8; // @[issue-unit-age-ordered.scala:208:25] reg is_available_9; // @[issue-unit-age-ordered.scala:208:25] reg is_available_10; // @[issue-unit-age-ordered.scala:208:25] reg is_available_11; // @[issue-unit-age-ordered.scala:208:25] wire [1:0] _GEN_1 = {1'h0, is_available_1} + {1'h0, is_available_2}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T = _GEN_1; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T = _GEN_1; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_2_ready_T = _GEN_1; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_1 = _io_dis_uops_0_ready_T; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _GEN_2 = {2'h0, is_available_0}; // @[issue-unit-age-ordered.scala:141:19, :208:25, :212:45] wire [2:0] _io_dis_uops_0_ready_T_2 = _GEN_2 + {1'h0, _io_dis_uops_0_ready_T_1}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_3 = _io_dis_uops_0_ready_T_2[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _GEN_3 = {1'h0, is_available_4} + {1'h0, is_available_5}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T_4; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T_4 = _GEN_3; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_4; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T_4 = _GEN_3; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_4; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_2_ready_T_4 = _GEN_3; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_5 = _io_dis_uops_0_ready_T_4; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _GEN_4 = {2'h0, is_available_3}; // @[issue-unit-age-ordered.scala:141:19, :208:25, :212:45] wire [2:0] _io_dis_uops_0_ready_T_6 = _GEN_4 + {1'h0, _io_dis_uops_0_ready_T_5}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_7 = _io_dis_uops_0_ready_T_6[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_8 = {1'h0, _io_dis_uops_0_ready_T_3} + {1'h0, _io_dis_uops_0_ready_T_7}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_9 = _io_dis_uops_0_ready_T_8; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _GEN_5 = {1'h0, is_available_7} + {1'h0, is_available_8}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T_10; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T_10 = _GEN_5; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_10; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T_10 = _GEN_5; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_10; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_2_ready_T_10 = _GEN_5; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_11 = _io_dis_uops_0_ready_T_10; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _GEN_6 = {2'h0, is_available_6}; // @[issue-unit-age-ordered.scala:141:19, :208:25, :212:45] wire [2:0] _io_dis_uops_0_ready_T_12 = _GEN_6 + {1'h0, _io_dis_uops_0_ready_T_11}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_13 = _io_dis_uops_0_ready_T_12[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _GEN_7 = {1'h0, is_available_10} + {1'h0, is_available_11}; // @[issue-unit-age-ordered.scala:208:25, :212:45] wire [1:0] _io_dis_uops_0_ready_T_14; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_0_ready_T_14 = _GEN_7; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_14; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_1_ready_T_14 = _GEN_7; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_14; // @[issue-unit-age-ordered.scala:212:45] assign _io_dis_uops_2_ready_T_14 = _GEN_7; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_15 = _io_dis_uops_0_ready_T_14; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _GEN_8 = {2'h0, is_available_9}; // @[issue-unit-age-ordered.scala:141:19, :208:25, :212:45] wire [2:0] _io_dis_uops_0_ready_T_16 = _GEN_8 + {1'h0, _io_dis_uops_0_ready_T_15}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_0_ready_T_17 = _io_dis_uops_0_ready_T_16[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_18 = {1'h0, _io_dis_uops_0_ready_T_13} + {1'h0, _io_dis_uops_0_ready_T_17}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_0_ready_T_19 = _io_dis_uops_0_ready_T_18; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_0_ready_T_20 = {1'h0, _io_dis_uops_0_ready_T_9} + {1'h0, _io_dis_uops_0_ready_T_19}; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_0_ready_T_21 = _io_dis_uops_0_ready_T_20; // @[issue-unit-age-ordered.scala:212:45] wire _GEN_9 = io_dis_uops_0_ready_0 & io_dis_uops_0_valid_0; // @[Decoupled.scala:51:35] wire _io_dis_uops_0_ready_T_22; // @[Decoupled.scala:51:35] assign _io_dis_uops_0_ready_T_22 = _GEN_9; // @[Decoupled.scala:51:35] wire _io_dis_uops_1_ready_T_22; // @[Decoupled.scala:51:35] assign _io_dis_uops_1_ready_T_22 = _GEN_9; // @[Decoupled.scala:51:35] wire _io_dis_uops_2_ready_T_22; // @[Decoupled.scala:51:35] assign _io_dis_uops_2_ready_T_22 = _GEN_9; // @[Decoupled.scala:51:35] wire _GEN_10 = io_dis_uops_1_ready_0 & io_dis_uops_1_valid_0; // @[Decoupled.scala:51:35] wire _io_dis_uops_0_ready_T_23; // @[Decoupled.scala:51:35] assign _io_dis_uops_0_ready_T_23 = _GEN_10; // @[Decoupled.scala:51:35] wire _io_dis_uops_1_ready_T_23; // @[Decoupled.scala:51:35] assign _io_dis_uops_1_ready_T_23 = _GEN_10; // @[Decoupled.scala:51:35] wire _io_dis_uops_2_ready_T_23; // @[Decoupled.scala:51:35] assign _io_dis_uops_2_ready_T_23 = _GEN_10; // @[Decoupled.scala:51:35] wire _GEN_11 = io_dis_uops_2_ready_0 & io_dis_uops_2_valid_0; // @[Decoupled.scala:51:35] wire _io_dis_uops_0_ready_T_24; // @[Decoupled.scala:51:35] assign _io_dis_uops_0_ready_T_24 = _GEN_11; // @[Decoupled.scala:51:35] wire _io_dis_uops_1_ready_T_24; // @[Decoupled.scala:51:35] assign _io_dis_uops_1_ready_T_24 = _GEN_11; // @[Decoupled.scala:51:35] wire _io_dis_uops_2_ready_T_24; // @[Decoupled.scala:51:35] assign _io_dis_uops_2_ready_T_24 = _GEN_11; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_0_ready_T_25 = {1'h0, _io_dis_uops_0_ready_T_23} + {1'h0, _io_dis_uops_0_ready_T_24}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_0_ready_T_26 = _io_dis_uops_0_ready_T_25; // @[issue-unit-age-ordered.scala:212:100] wire [2:0] _io_dis_uops_0_ready_T_27 = {2'h0, _io_dis_uops_0_ready_T_22} + {1'h0, _io_dis_uops_0_ready_T_26}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_0_ready_T_28 = _io_dis_uops_0_ready_T_27[1:0]; // @[issue-unit-age-ordered.scala:212:100] wire [4:0] _io_dis_uops_0_ready_T_29 = {3'h0, _io_dis_uops_0_ready_T_28}; // @[issue-unit-age-ordered.scala:212:{90,100}] wire [3:0] _io_dis_uops_0_ready_T_30 = _io_dis_uops_0_ready_T_29[3:0]; // @[issue-unit-age-ordered.scala:212:90] wire _io_dis_uops_0_ready_T_31 = _io_dis_uops_0_ready_T_21 > _io_dis_uops_0_ready_T_30; // @[issue-unit-age-ordered.scala:212:{45,60,90}] reg io_dis_uops_0_ready_REG; // @[issue-unit-age-ordered.scala:212:36] assign io_dis_uops_0_ready_0 = io_dis_uops_0_ready_REG; // @[issue-unit-age-ordered.scala:22:7, :212:36] wire [1:0] _io_dis_uops_1_ready_T_1 = _io_dis_uops_1_ready_T; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_2 = _GEN_2 + {1'h0, _io_dis_uops_1_ready_T_1}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_3 = _io_dis_uops_1_ready_T_2[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_5 = _io_dis_uops_1_ready_T_4; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_6 = _GEN_4 + {1'h0, _io_dis_uops_1_ready_T_5}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_7 = _io_dis_uops_1_ready_T_6[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_8 = {1'h0, _io_dis_uops_1_ready_T_3} + {1'h0, _io_dis_uops_1_ready_T_7}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_9 = _io_dis_uops_1_ready_T_8; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_11 = _io_dis_uops_1_ready_T_10; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_12 = _GEN_6 + {1'h0, _io_dis_uops_1_ready_T_11}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_13 = _io_dis_uops_1_ready_T_12[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_15 = _io_dis_uops_1_ready_T_14; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_16 = _GEN_8 + {1'h0, _io_dis_uops_1_ready_T_15}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_17 = _io_dis_uops_1_ready_T_16[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_18 = {1'h0, _io_dis_uops_1_ready_T_13} + {1'h0, _io_dis_uops_1_ready_T_17}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_1_ready_T_19 = _io_dis_uops_1_ready_T_18; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_1_ready_T_20 = {1'h0, _io_dis_uops_1_ready_T_9} + {1'h0, _io_dis_uops_1_ready_T_19}; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_1_ready_T_21 = _io_dis_uops_1_ready_T_20; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_1_ready_T_25 = {1'h0, _io_dis_uops_1_ready_T_23} + {1'h0, _io_dis_uops_1_ready_T_24}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_1_ready_T_26 = _io_dis_uops_1_ready_T_25; // @[issue-unit-age-ordered.scala:212:100] wire [2:0] _io_dis_uops_1_ready_T_27 = {2'h0, _io_dis_uops_1_ready_T_22} + {1'h0, _io_dis_uops_1_ready_T_26}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_1_ready_T_28 = _io_dis_uops_1_ready_T_27[1:0]; // @[issue-unit-age-ordered.scala:212:100] wire [4:0] _io_dis_uops_1_ready_T_29 = {3'h0, _io_dis_uops_1_ready_T_28} + 5'h1; // @[issue-unit-age-ordered.scala:212:{90,100}] wire [3:0] _io_dis_uops_1_ready_T_30 = _io_dis_uops_1_ready_T_29[3:0]; // @[issue-unit-age-ordered.scala:212:90] wire _io_dis_uops_1_ready_T_31 = _io_dis_uops_1_ready_T_21 > _io_dis_uops_1_ready_T_30; // @[issue-unit-age-ordered.scala:212:{45,60,90}] reg io_dis_uops_1_ready_REG; // @[issue-unit-age-ordered.scala:212:36] assign io_dis_uops_1_ready_0 = io_dis_uops_1_ready_REG; // @[issue-unit-age-ordered.scala:22:7, :212:36] wire [1:0] _io_dis_uops_2_ready_T_1 = _io_dis_uops_2_ready_T; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_2 = _GEN_2 + {1'h0, _io_dis_uops_2_ready_T_1}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_3 = _io_dis_uops_2_ready_T_2[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_5 = _io_dis_uops_2_ready_T_4; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_6 = _GEN_4 + {1'h0, _io_dis_uops_2_ready_T_5}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_7 = _io_dis_uops_2_ready_T_6[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_8 = {1'h0, _io_dis_uops_2_ready_T_3} + {1'h0, _io_dis_uops_2_ready_T_7}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_9 = _io_dis_uops_2_ready_T_8; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_11 = _io_dis_uops_2_ready_T_10; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_12 = _GEN_6 + {1'h0, _io_dis_uops_2_ready_T_11}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_13 = _io_dis_uops_2_ready_T_12[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_15 = _io_dis_uops_2_ready_T_14; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_16 = _GEN_8 + {1'h0, _io_dis_uops_2_ready_T_15}; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_17 = _io_dis_uops_2_ready_T_16[1:0]; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_18 = {1'h0, _io_dis_uops_2_ready_T_13} + {1'h0, _io_dis_uops_2_ready_T_17}; // @[issue-unit-age-ordered.scala:212:45] wire [2:0] _io_dis_uops_2_ready_T_19 = _io_dis_uops_2_ready_T_18; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_2_ready_T_20 = {1'h0, _io_dis_uops_2_ready_T_9} + {1'h0, _io_dis_uops_2_ready_T_19}; // @[issue-unit-age-ordered.scala:212:45] wire [3:0] _io_dis_uops_2_ready_T_21 = _io_dis_uops_2_ready_T_20; // @[issue-unit-age-ordered.scala:212:45] wire [1:0] _io_dis_uops_2_ready_T_25 = {1'h0, _io_dis_uops_2_ready_T_23} + {1'h0, _io_dis_uops_2_ready_T_24}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_2_ready_T_26 = _io_dis_uops_2_ready_T_25; // @[issue-unit-age-ordered.scala:212:100] wire [2:0] _io_dis_uops_2_ready_T_27 = {2'h0, _io_dis_uops_2_ready_T_22} + {1'h0, _io_dis_uops_2_ready_T_26}; // @[Decoupled.scala:51:35] wire [1:0] _io_dis_uops_2_ready_T_28 = _io_dis_uops_2_ready_T_27[1:0]; // @[issue-unit-age-ordered.scala:212:100] wire [4:0] _io_dis_uops_2_ready_T_29 = {3'h0, _io_dis_uops_2_ready_T_28} + 5'h2; // @[issue-unit-age-ordered.scala:212:{90,100}] wire [3:0] _io_dis_uops_2_ready_T_30 = _io_dis_uops_2_ready_T_29[3:0]; // @[issue-unit-age-ordered.scala:212:90] wire _io_dis_uops_2_ready_T_31 = _io_dis_uops_2_ready_T_21 > _io_dis_uops_2_ready_T_30; // @[issue-unit-age-ordered.scala:212:{45,60,90}] reg io_dis_uops_2_ready_REG; // @[issue-unit-age-ordered.scala:212:36] assign io_dis_uops_2_ready_0 = io_dis_uops_2_ready_REG; // @[issue-unit-age-ordered.scala:22:7, :212:36]
Generate the Verilog code corresponding to the following Chisel files. File SourceB.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class SourceBRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val param = UInt(3.W) val tag = UInt(params.tagBits.W) val set = UInt(params.setBits.W) val clients = UInt(params.clientBits.W) } class SourceB(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val req = Flipped(Decoupled(new SourceBRequest(params))) val b = Decoupled(new TLBundleB(params.inner.bundle)) }) if (params.firstLevel) { // Tie off unused ports io.req.ready := true.B io.b.valid := false.B io.b.bits := DontCare } else { val remain = RegInit(0.U(params.clientBits.W)) val remain_set = WireInit(init = 0.U(params.clientBits.W)) val remain_clr = WireInit(init = 0.U(params.clientBits.W)) remain := (remain \| remain_set) & ~remain_clr val busy = remain.orR val todo = Mux(busy, remain, io.req.bits.clients) val next = ~(leftOR(todo) << 1) & todo if (params.clientBits > 1) { params.ccover(PopCount(remain) > 1.U, "SOURCEB_MULTI_PROBE", "Had to probe more than one client") } assert (!io.req.valid \|\| io.req.bits.clients =/= 0.U) io.req.ready := !busy when (io.req.fire) { remain_set := io.req.bits.clients } // No restrictions on the type of buffer used here val b = Wire(chiselTypeOf(io.b)) io.b <> params.micro.innerBuf.b(b) b.valid := busy \|\| io.req.valid when (b.fire) { remain_clr := next } params.ccover(b.valid && !b.ready, "SOURCEB_STALL", "Backpressured when issuing a probe") val tag = Mux(!busy, io.req.bits.tag, RegEnable(io.req.bits.tag, io.req.fire)) val set = Mux(!busy, io.req.bits.set, RegEnable(io.req.bits.set, io.req.fire)) val param = Mux(!busy, io.req.bits.param, RegEnable(io.req.bits.param, io.req.fire)) b.bits.opcode := TLMessages.Probe b.bits.param := param b.bits.size := params.offsetBits .U b.bits.source := params.clientSource(next) b.bits.address := params.expandAddress(tag, set, 0.U) b.bits.mask := ~0.U(params.inner.manager.beatBytes.W) b.bits.data := 0.U b.bits.corrupt := false.B } } File Parameters.scala: / * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relListscache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_\|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x \| 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ \|\| _) (matches, bits.U) } expanded \| Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) \|\| (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) \|\| ((opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm \|\| opcode === TLMessages.Get \|\| (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN \|\| param === TLPermissions.BtoN \|\| param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB \|\| param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle	module SourceB( // @[SourceB.scala:33:7] input clock, // @[SourceB.scala:33:7] input reset, // @[SourceB.scala:33:7] output io_req_ready, // @[SourceB.scala:35:14] input io_req_valid, // @[SourceB.scala:35:14] input [2:0] io_req_bits_param, // @[SourceB.scala:35:14] input [12:0] io_req_bits_tag, // @[SourceB.scala:35:14] input [9:0] io_req_bits_set, // @[SourceB.scala:35:14] input io_req_bits_clients, // @[SourceB.scala:35:14] input io_b_ready, // @[SourceB.scala:35:14] output io_b_valid, // @[SourceB.scala:35:14] output [1:0] io_b_bits_param, // @[SourceB.scala:35:14] output [31:0] io_b_bits_address // @[SourceB.scala:35:14] ); wire io_req_valid_0 = io_req_valid; // @[SourceB.scala:33:7] wire [2:0] io_req_bits_param_0 = io_req_bits_param; // @[SourceB.scala:33:7] wire [12:0] io_req_bits_tag_0 = io_req_bits_tag; // @[SourceB.scala:33:7] wire [9:0] io_req_bits_set_0 = io_req_bits_set; // @[SourceB.scala:33:7] wire io_req_bits_clients_0 = io_req_bits_clients; // @[SourceB.scala:33:7] wire io_b_ready_0 = io_b_ready; // @[SourceB.scala:33:7] wire _b_bits_address_base_T_2 = reset; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_8 = reset; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_14 = reset; // @[Parameters.scala:222:12] wire [2:0] io_b_bits_opcode = 3'h6; // @[SourceB.scala:33:7] wire [2:0] io_b_bits_size = 3'h6; // @[SourceB.scala:33:7] wire [2:0] b_bits_opcode = 3'h6; // @[SourceB.scala:65:17] wire [2:0] b_bits_size = 3'h6; // @[SourceB.scala:65:17] wire [7:0] io_b_bits_source = 8'hA0; // @[SourceB.scala:33:7] wire [7:0] b_bits_source = 8'hA0; // @[SourceB.scala:65:17] wire [15:0] io_b_bits_mask = 16'hFFFF; // @[SourceB.scala:33:7] wire [15:0] b_bits_mask = 16'hFFFF; // @[SourceB.scala:65:17] wire [15:0] _b_bits_mask_T = 16'hFFFF; // @[SourceB.scala:81:23] wire [127:0] io_b_bits_data = 128'h0; // @[SourceB.scala:33:7] wire [127:0] b_bits_data = 128'h0; // @[SourceB.scala:65:17] wire io_b_bits_corrupt = 1'h0; // @[SourceB.scala:33:7] wire b_bits_corrupt = 1'h0; // @[SourceB.scala:65:17] wire _b_bits_address_base_T = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_4 = 1'h0; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_6 = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_10 = 1'h0; // @[Parameters.scala:222:12] wire _b_bits_address_base_T_12 = 1'h0; // @[Parameters.scala:222:15] wire _b_bits_address_base_T_16 = 1'h0; // @[Parameters.scala:222:12] wire [1:0] b_bits_address_hi_hi_hi_lo = 2'h0; // @[Parameters.scala:230:8] wire [5:0] b_bits_address_base_y_2 = 6'h0; // @[Parameters.scala:221:15] wire [5:0] _b_bits_address_base_T_17 = 6'h0; // @[Parameters.scala:223:6] wire _b_bits_address_base_T_1 = 1'h1; // @[Parameters.scala:222:24] wire _b_bits_address_base_T_7 = 1'h1; // @[Parameters.scala:222:24] wire _b_bits_address_base_T_13 = 1'h1; // @[Parameters.scala:222:24] wire _io_req_ready_T; // @[SourceB.scala:61:21] wire b_ready = io_b_ready_0; // @[SourceB.scala:33:7, :65:17] wire b_valid; // @[SourceB.scala:65:17] wire [1:0] b_bits_param; // @[SourceB.scala:65:17] wire [31:0] b_bits_address; // @[SourceB.scala:65:17] wire io_req_ready_0; // @[SourceB.scala:33:7] wire [1:0] io_b_bits_param_0; // @[SourceB.scala:33:7] wire [31:0] io_b_bits_address_0; // @[SourceB.scala:33:7] wire io_b_valid_0; // @[SourceB.scala:33:7] reg remain; // @[SourceB.scala:46:25] wire busy = remain; // @[SourceB.scala:46:25, :51:23] wire remain_set; // @[SourceB.scala:47:30] wire remain_clr; // @[SourceB.scala:48:30] wire _remain_T = remain \| remain_set; // @[SourceB.scala:46:25, :47:30, :49:23] wire _remain_T_1 = ~remain_clr; // @[SourceB.scala:48:30, :49:39] wire _remain_T_2 = _remain_T & _remain_T_1; // @[SourceB.scala:49:{23,37,39}] wire todo = busy ? remain : io_req_bits_clients_0; // @[SourceB.scala:33:7, :46:25, :51:23, :52:19] wire _next_T = todo; // @[package.scala:254:17] wire [1:0] _next_T_1 = {_next_T, 1'h0}; // @[package.scala:254:17] wire [1:0] _next_T_2 = ~_next_T_1; // @[SourceB.scala:53:{16,31}] wire [1:0] next = {1'h0, _next_T_2[0] & todo}; // @[SourceB.scala:52:19, :53:{16,37}]
Generate the Verilog code corresponding to the following Chisel files. File SwitchAllocator.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ class SwitchAllocReq(val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams]) (implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val tail = Bool() } class SwitchArbiter(inN: Int, outN: Int, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Module { val io = IO(new Bundle { val in = Flipped(Vec(inN, Decoupled(new SwitchAllocReq(outParams, egressParams)))) val out = Vec(outN, Decoupled(new SwitchAllocReq(outParams, egressParams))) val chosen_oh = Vec(outN, Output(UInt(inN.W))) }) val lock = Seq.fill(outN) { RegInit(0.U(inN.W)) } val unassigned = Cat(io.in.map(_.valid).reverse) & ~(lock.reduce(_\|_)) val mask = RegInit(0.U(inN.W)) val choices = Wire(Vec(outN, UInt(inN.W))) var sel = PriorityEncoderOH(Cat(unassigned, unassigned & ~mask)) for (i <- 0 until outN) { choices(i) := sel \| (sel >> inN) sel = PriorityEncoderOH(unassigned & ~choices(i)) } io.in.foreach(_.ready := false.B) var chosens = 0.U(inN.W) val in_tails = Cat(io.in.map(_.bits.tail).reverse) for (i <- 0 until outN) { val in_valids = Cat((0 until inN).map { j => io.in(j).valid && !chosens(j) }.reverse) val chosen = Mux((in_valids & lock(i) & ~chosens).orR, lock(i), choices(i)) io.chosen_oh(i) := chosen io.out(i).valid := (in_valids & chosen).orR io.out(i).bits := Mux1H(chosen, io.in.map(_.bits)) for (j <- 0 until inN) { when (chosen(j) && io.out(i).ready) { io.in(j).ready := true.B } } chosens = chosens \| chosen when (io.out(i).fire) { lock(i) := chosen & ~in_tails } } when (io.out(0).fire) { mask := (0 until inN).map { i => (io.chosen_oh(0) >> i) }.reduce(_\|_) } .otherwise { mask := Mux(~mask === 0.U, 0.U, (mask << 1) \| 1.U(1.W)) } } class SwitchAllocator( val routerParams: RouterParams, val inParams: Seq[ChannelParams], val outParams: Seq[ChannelParams], val ingressParams: Seq[IngressChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterParams with HasRouterInputParams with HasRouterOutputParams { val io = IO(new Bundle { val req = MixedVec(allInParams.map(u => Vec(u.destSpeedup, Flipped(Decoupled(new SwitchAllocReq(outParams, egressParams)))))) val credit_alloc = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Output(new OutputCreditAlloc))}) val switch_sel = MixedVec(allOutParams.map { o => Vec(o.srcSpeedup, MixedVec(allInParams.map { i => Vec(i.destSpeedup, Output(Bool())) })) }) }) val nInputChannels = allInParams.map(_.nVirtualChannels).sum val arbs = allOutParams.map { oP => Module(new SwitchArbiter( allInParams.map(_.destSpeedup).reduce(_+_), oP.srcSpeedup, outParams, egressParams ))} arbs.foreach(_.io.out.foreach(_.ready := true.B)) var idx = 0 io.req.foreach(_.foreach { o => val fires = Wire(Vec(arbs.size, Bool())) arbs.zipWithIndex.foreach { case (a,i) => a.io.in(idx).valid := o.valid && o.bits.vc_sel(i).reduce(_\|\|_) a.io.in(idx).bits := o.bits fires(i) := a.io.in(idx).fire } o.ready := fires.reduce(_\|\|_) idx += 1 }) for (i <- 0 until nAllOutputs) { for (j <- 0 until allOutParams(i).srcSpeedup) { idx = 0 for (m <- 0 until nAllInputs) { for (n <- 0 until allInParams(m).destSpeedup) { io.switch_sel(i)(j)(m)(n) := arbs(i).io.in(idx).valid && arbs(i).io.chosen_oh(j)(idx) && arbs(i).io.out(j).valid idx += 1 } } } } io.credit_alloc.foreach(_.foreach(_.alloc := false.B)) io.credit_alloc.foreach(_.foreach(_.tail := false.B)) (arbs zip io.credit_alloc).zipWithIndex.map { case ((a,i),t) => for (j <- 0 until i.size) { for (k <- 0 until a.io.out.size) { when (a.io.out(k).valid && a.io.out(k).bits.vc_sel(t)(j)) { i(j).alloc := true.B i(j).tail := a.io.out(k).bits.tail } } } } }	module SwitchArbiter_313( // @[SwitchAllocator.scala:17:7] input clock, // @[SwitchAllocator.scala:17:7] input reset, // @[SwitchAllocator.scala:17:7] output io_in_0_ready, // @[SwitchAllocator.scala:18:14] input io_in_0_valid, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_3, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_4, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_5, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_6, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_7, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_8, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_2_9, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_8, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_1_9, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_8, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_vc_sel_0_9, // @[SwitchAllocator.scala:18:14] input io_in_0_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_1_ready, // @[SwitchAllocator.scala:18:14] input io_in_1_valid, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_3, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_4, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_5, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_6, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_7, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_8, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_2_9, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_8, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_1_9, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_8, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_vc_sel_0_9, // @[SwitchAllocator.scala:18:14] input io_in_1_bits_tail, // @[SwitchAllocator.scala:18:14] output io_in_2_ready, // @[SwitchAllocator.scala:18:14] input io_in_2_valid, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_3, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_4, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_5, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_6, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_7, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_8, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_2_9, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_8, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_1_9, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_8, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_vc_sel_0_9, // @[SwitchAllocator.scala:18:14] input io_in_2_bits_tail, // @[SwitchAllocator.scala:18:14] output io_out_0_valid, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_2, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_3, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_4, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_5, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_6, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_7, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_8, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_2_9, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_2, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_3, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_4, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_5, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_6, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_7, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_8, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_1_9, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_2, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_3, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_4, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_5, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_6, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_7, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_8, // @[SwitchAllocator.scala:18:14] output io_out_0_bits_vc_sel_0_9, // @[SwitchAllocator.scala:18:14] output [2:0] io_chosen_oh_0 // @[SwitchAllocator.scala:18:14] ); reg [2:0] lock_0; // @[SwitchAllocator.scala:24:38] wire [2:0] unassigned = {io_in_2_valid, io_in_1_valid, io_in_0_valid} & ~lock_0; // @[SwitchAllocator.scala:24:38, :25:{23,52,54}] reg [2:0] mask; // @[SwitchAllocator.scala:27:21] wire [2:0] _sel_T_1 = unassigned & ~mask; // @[SwitchAllocator.scala:25:52, :27:21, :30:{58,60}] wire [5:0] sel = _sel_T_1[0] ? 6'h1 : _sel_T_1[1] ? 6'h2 : _sel_T_1[2] ? 6'h4 : unassigned[0] ? 6'h8 : unassigned[1] ? 6'h10 : {unassigned[2], 5'h0}; // @[OneHot.scala:85:71] wire [2:0] in_valids = {io_in_2_valid, io_in_1_valid, io_in_0_valid}; // @[SwitchAllocator.scala:41:24] wire [2:0] chosen = (\|(in_valids & lock_0)) ? lock_0 : sel[2:0] \| sel[5:3]; // @[Mux.scala:50:70] wire [2:0] _io_out_0_valid_T = in_valids & chosen; // @[SwitchAllocator.scala:41:24, :42:21, :44:35] wire [1:0] _GEN = chosen[1:0] \| chosen[2:1]; // @[SwitchAllocator.scala:42:21, :58:{55,71}] always @(posedge clock) begin // @[SwitchAllocator.scala:17:7] if (reset) begin // @[SwitchAllocator.scala:17:7] lock_0 <= 3'h0; // @[SwitchAllocator.scala:24:38] mask <= 3'h0; // @[SwitchAllocator.scala:27:21] end else begin // @[SwitchAllocator.scala:17:7] if (\|_io_out_0_valid_T) // @[SwitchAllocator.scala:44:{35,45}] lock_0 <= chosen & ~{io_in_2_bits_tail, io_in_1_bits_tail, io_in_0_bits_tail}; // @[SwitchAllocator.scala:24:38, :39:21, :42:21, :53:{25,27}] mask <= (\|_io_out_0_valid_T) ? {chosen[2], _GEN[1], _GEN[0] \| chosen[2]} : (&mask) ? 3'h0 : {mask[1:0], 1'h1}; // @[SwitchAllocator.scala:17:7, :27:21, :42:21, :44:{35,45}, :57:25, :58:{10,55,71}, :60:{10,16,23,49}] end always @(posedge)
Generate the Verilog code corresponding to the following Chisel files. File Tile.scala: // See README.md for license details. package gemmini import chisel3._ import chisel3.util._ import Util._ /** * A Tile is a purely combinational 2D array of passThrough PEs. * a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs * @param width The data width of each PE in bits * @param rows Number of PEs on each row * @param columns Number of PEs on each column */ class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module { val io = IO(new Bundle { val in_a = Input(Vec(rows, inputType)) val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it val in_d = Input(Vec(columns, outputType)) val in_control = Input(Vec(columns, new PEControl(accType))) val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val in_last = Input(Vec(columns, Bool())) val out_a = Output(Vec(rows, inputType)) val out_c = Output(Vec(columns, outputType)) val out_b = Output(Vec(columns, outputType)) val out_control = Output(Vec(columns, new PEControl(accType))) val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W))) val out_last = Output(Vec(columns, Bool())) val in_valid = Input(Vec(columns, Bool())) val out_valid = Output(Vec(columns, Bool())) val bad_dataflow = Output(Bool()) }) import ev._ val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls))) val tileT = tile.transpose // TODO: abstract hori/vert broadcast, all these connections look the same // Broadcast 'a' horizontally across the Tile for (r <- 0 until rows) { tile(r).foldLeft(io.in_a(r)) { case (in_a, pe) => pe.io.in_a := in_a pe.io.out_a } } // Broadcast 'b' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_b(c)) { case (in_b, pe) => pe.io.in_b := (if (tree_reduction) in_b.zero else in_b) pe.io.out_b } } // Broadcast 'd' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_d(c)) { case (in_d, pe) => pe.io.in_d := in_d pe.io.out_c } } // Broadcast 'control' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_control(c)) { case (in_ctrl, pe) => pe.io.in_control := in_ctrl pe.io.out_control } } // Broadcast 'garbage' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_valid(c)) { case (v, pe) => pe.io.in_valid := v pe.io.out_valid } } // Broadcast 'id' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_id(c)) { case (id, pe) => pe.io.in_id := id pe.io.out_id } } // Broadcast 'last' vertically across the Tile for (c <- 0 until columns) { tileT(c).foldLeft(io.in_last(c)) { case (last, pe) => pe.io.in_last := last pe.io.out_last } } // Drive the Tile's bottom IO for (c <- 0 until columns) { io.out_c(c) := tile(rows-1)(c).io.out_c io.out_control(c) := tile(rows-1)(c).io.out_control io.out_id(c) := tile(rows-1)(c).io.out_id io.out_last(c) := tile(rows-1)(c).io.out_last io.out_valid(c) := tile(rows-1)(c).io.out_valid io.out_b(c) := { if (tree_reduction) { val prods = tileT(c).map(_.io.out_b) accumulateTree(prods :+ io.in_b(c)) } else { tile(rows - 1)(c).io.out_b } } } io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_\|\|_)).reduce(_\|\|_) // Drive the Tile's right IO for (r <- 0 until rows) { io.out_a(r) := tile(r)(columns-1).io.out_a } }	module Tile_71( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_327 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File UnsafeAXI4ToTL.scala: package ara import chisel3._ import chisel3.util._ import freechips.rocketchip.amba._ import freechips.rocketchip.amba.axi4._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle { val data = UInt(dataWidth.W) val resp = UInt(respWidth.W) val last = Bool() val user = BundleMap(userFields) } /** Parameters for [[BaseReservableListBuffer]] and all child classes. * * @param numEntries Total number of elements that can be stored in the 'data' RAM * @param numLists Maximum number of linked lists * @param numBeats Maximum number of beats per entry / case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) { // Avoid zero-width wires when we call 'log2Ceil' val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries) val listBits = if (numLists == 1) 1 else log2Ceil(numLists) val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats) } case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName) extends MixedAdapterNode(AXI4Imp, TLImp)( dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.zipWithIndex.map { case (m, i) => // Support 'numTlTxns' read requests and 'numTlTxns' write requests at once. val numSourceIds = numTlTxns 2 TLMasterParameters.v2( name = m.name, sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds), nodePath = m.nodePath ) }, echoFields = mp.echoFields, requestFields = AMBAProtField() +: mp.requestFields, responseKeys = mp.responseKeys ) }, uFn = { mp => AXI4SlavePortParameters( slaves = mp.managers.map { m => val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits)) AXI4SlaveParameters( address = m.address, resources = m.resources, regionType = m.regionType, executable = m.executable, nodePath = m.nodePath, supportsWrite = m.supportsPutPartial.intersect(maxXfer), supportsRead = m.supportsGet.intersect(maxXfer), interleavedId = Some(0) // TL2 never interleaves D beats ) }, beatBytes = mp.beatBytes, minLatency = mp.minLatency, responseFields = mp.responseFields, requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt) ) } ) class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule { require(numTlTxns >= 1) require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2") val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt) lazy val module = new LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => edgeIn.master.masters.foreach { m => require(m.aligned, "AXI4ToTL requires aligned requests") } val numIds = edgeIn.master.endId val beatBytes = edgeOut.slave.beatBytes val maxTransfer = edgeOut.slave.maxTransfer val maxBeats = maxTransfer / beatBytes // Look for an Error device to redirect bad requests val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError") require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.") val errorDev = errorDevs.maxBy(_.maxTransfer) val errorDevAddr = errorDev.address.head.base require( errorDev.supportsPutPartial.contains(maxTransfer), s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer" ) require( errorDev.supportsGet.contains(maxTransfer), s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer" ) // All of the read-response reordering logic. val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields) val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats) val listBuffer = if (numTlTxns > 1) { Module(new ReservableListBuffer(listBufData, listBufParams)) } else { Module(new PassthroughListBuffer(listBufData, listBufParams)) } // To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to // 0 for read requests and 1 for write requests. val isReadSourceBit = 0.U(1.W) val isWriteSourceBit = 1.U(1.W) /* Read request logic / val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val rBytes1 = in.ar.bits.bytes1() val rSize = OH1ToUInt(rBytes1) val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize) val rId = if (numTlTxns > 1) { Cat(isReadSourceBit, listBuffer.ioReservedIndex) } else { isReadSourceBit } val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U \| in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Indicates if there are still valid TileLink source IDs left to use. val canIssueR = listBuffer.ioReserve.ready listBuffer.ioReserve.bits := in.ar.bits.id listBuffer.ioReserve.valid := in.ar.valid && rOut.ready in.ar.ready := rOut.ready && canIssueR rOut.valid := in.ar.valid && canIssueR rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2 rOut.bits.user :<= in.ar.bits.user rOut.bits.user.lift(AMBAProt).foreach { rProt => rProt.privileged := in.ar.bits.prot(0) rProt.secure := !in.ar.bits.prot(1) rProt.fetch := in.ar.bits.prot(2) rProt.bufferable := in.ar.bits.cache(0) rProt.modifiable := in.ar.bits.cache(1) rProt.readalloc := in.ar.bits.cache(2) rProt.writealloc := in.ar.bits.cache(3) } / Write request logic / // Strip off the MSB, which identifies the transaction as read vs write. val strippedResponseSourceId = if (numTlTxns > 1) { out.d.bits.source((out.d.bits.source).getWidth - 2, 0) } else { // When there's only 1 TileLink transaction allowed for read/write, then this field is always 0. 0.U(1.W) } // Track when a write request burst is in progress. val writeBurstBusy = RegInit(false.B) when(in.w.fire) { writeBurstBusy := !in.w.bits.last } val usedWriteIds = RegInit(0.U(numTlTxns.W)) val canIssueW = !usedWriteIds.andR val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W)) val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W)) usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) \| usedWriteIdsSet // Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't // change mid-burst. val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W)) val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy val freeWriteIdIndex = OHToUInt(freeWriteIdOH) freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle))) val wBytes1 = in.aw.bits.bytes1() val wSize = OH1ToUInt(wBytes1) val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize) val wId = if (numTlTxns > 1) { Cat(isWriteSourceBit, freeWriteIdIndex) } else { isWriteSourceBit } val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U \| in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0)) // Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain // asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but // the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb // bits during a W-channel burst. in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW in.w.ready := wOut.ready && in.aw.valid && canIssueW wOut.valid := in.aw.valid && in.w.valid && canIssueW wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2 in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ } wOut.bits.user :<= in.aw.bits.user wOut.bits.user.lift(AMBAProt).foreach { wProt => wProt.privileged := in.aw.bits.prot(0) wProt.secure := !in.aw.bits.prot(1) wProt.fetch := in.aw.bits.prot(2) wProt.bufferable := in.aw.bits.cache(0) wProt.modifiable := in.aw.bits.cache(1) wProt.readalloc := in.aw.bits.cache(2) wProt.writealloc := in.aw.bits.cache(3) } // Merge the AXI4 read/write requests into the TL-A channel. TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut)) / Read/write response logic / val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle))) val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle))) val dResp = Mux(out.d.bits.denied \|\| out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY) val dHasData = edgeOut.hasData(out.d.bits) val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d) val dNumBeats1 = edgeOut.numBeats1(out.d.bits) // Handle cases where writeack arrives before write is done val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck) listBuffer.ioDataOut.ready := okR.ready okR.valid := listBuffer.ioDataOut.valid okB.valid := out.d.valid && !dHasData && !writeEarlyAck listBuffer.ioResponse.valid := out.d.valid && dHasData listBuffer.ioResponse.bits.index := strippedResponseSourceId listBuffer.ioResponse.bits.data.data := out.d.bits.data listBuffer.ioResponse.bits.data.resp := dResp listBuffer.ioResponse.bits.data.last := dLast listBuffer.ioResponse.bits.data.user :<= out.d.bits.user listBuffer.ioResponse.bits.count := dCount listBuffer.ioResponse.bits.numBeats1 := dNumBeats1 okR.bits.id := listBuffer.ioDataOut.bits.listIndex okR.bits.data := listBuffer.ioDataOut.bits.payload.data okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp okR.bits.last := listBuffer.ioDataOut.bits.payload.last okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user // Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write // response, mark the write transaction as complete. val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W)) val writeResponseId = writeIdMap.read(strippedResponseSourceId) when(wOut.fire) { writeIdMap.write(freeWriteIdIndex, in.aw.bits.id) } when(edgeOut.done(wOut)) { usedWriteIdsSet := freeWriteIdOH } when(okB.fire) { usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns) } okB.bits.id := writeResponseId okB.bits.resp := dResp okB.bits.user :<= out.d.bits.user // AXI4 needs irrevocable behaviour in.r <> Queue.irrevocable(okR, 1, flow = true) in.b <> Queue.irrevocable(okB, 1, flow = true) // Unused channels out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B / Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. / def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = { val lReqType = reqType.toLowerCase when(a.valid) { assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U) // Narrow transfers and FIXED bursts must be single-beat bursts. when(a.bits.len =/= 0.U) { assert( a.bits.size === log2Ceil(beatBytes).U, s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)", 1.U << a.bits.size, a.bits.len + 1.U ) assert( a.bits.burst =/= AXI4Parameters.BURST_FIXED, s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)", a.bits.len + 1.U ) } // Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in // particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink // Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts. } } checkRequest(in.ar, "Read") checkRequest(in.aw, "Write") } } } object UnsafeAXI4ToTL { def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = { val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt)) axi42tl.node } } / ReservableListBuffer logic, and associated classes. / class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle { val index = UInt(params.entryBits.W) val count = UInt(params.beatBits.W) val numBeats1 = UInt(params.beatBits.W) } class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle { val listIndex = UInt(params.listBits.W) } /* Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. / abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends Module { require(params.numEntries > 0) require(params.numLists > 0) val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W)))) val ioReservedIndex = IO(Output(UInt(params.entryBits.W))) val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params)))) val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params))) } /* A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve * linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the * 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a * given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order. * * ==Constructor== * @param gen Chisel type of linked list data element * @param params Other parameters * * ==Module IO== * @param ioReserve Index of list to reserve a new element in * @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire' * @param ioResponse Payload containing response data and linked-list-entry index * @param ioDataOut Payload containing data read from response linked list and linked list index / class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { val valid = RegInit(0.U(params.numLists.W)) val head = Mem(params.numLists, UInt(params.entryBits.W)) val tail = Mem(params.numLists, UInt(params.entryBits.W)) val used = RegInit(0.U(params.numEntries.W)) val next = Mem(params.numEntries, UInt(params.entryBits.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) } val dataIsPresent = RegInit(0.U(params.numEntries.W)) val beats = Mem(params.numEntries, UInt(params.beatBits.W)) // The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower. val dataMemReadEnable = WireDefault(false.B) val dataMemWriteEnable = WireDefault(false.B) assert(!(dataMemReadEnable && dataMemWriteEnable)) // 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the // lowest-index entry in the 'data' RAM which is free. val freeOH = Wire(UInt(params.numEntries.W)) val freeIndex = OHToUInt(freeOH) freeOH := ~(leftOR(~used) << 1) & ~used ioReservedIndex := freeIndex val validSet = WireDefault(0.U(params.numLists.W)) val validClr = WireDefault(0.U(params.numLists.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) val dataIsPresentSet = WireDefault(0.U(params.numEntries.W)) val dataIsPresentClr = WireDefault(0.U(params.numEntries.W)) valid := (valid & ~validClr) \| validSet used := (used & ~usedClr) \| usedSet dataIsPresent := (dataIsPresent & ~dataIsPresentClr) \| dataIsPresentSet / Reservation logic signals / val reserveTail = Wire(UInt(params.entryBits.W)) val reserveIsValid = Wire(Bool()) / Response logic signals / val responseIndex = Wire(UInt(params.entryBits.W)) val responseListIndex = Wire(UInt(params.listBits.W)) val responseHead = Wire(UInt(params.entryBits.W)) val responseTail = Wire(UInt(params.entryBits.W)) val nextResponseHead = Wire(UInt(params.entryBits.W)) val nextDataIsPresent = Wire(Bool()) val isResponseInOrder = Wire(Bool()) val isEndOfList = Wire(Bool()) val isLastBeat = Wire(Bool()) val isLastResponseBeat = Wire(Bool()) val isLastUnwindBeat = Wire(Bool()) / Reservation logic / reserveTail := tail.read(ioReserve.bits) reserveIsValid := valid(ioReserve.bits) ioReserve.ready := !used.andR // When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we // actually start a new list, rather than appending to a list that's about to disappear. val reserveResponseSameList = ioReserve.bits === responseListIndex val appendToAndDestroyList = ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat when(ioReserve.fire) { validSet := UIntToOH(ioReserve.bits, params.numLists) usedSet := freeOH when(reserveIsValid && !appendToAndDestroyList) { next.write(reserveTail, freeIndex) }.otherwise { head.write(ioReserve.bits, freeIndex) } tail.write(ioReserve.bits, freeIndex) map.write(freeIndex, ioReserve.bits) } / Response logic / // The majority of the response logic (reading from and writing to the various RAMs) is common between the // response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid). // The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the // 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and // response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after // two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker. responseHead := head.read(responseListIndex) responseTail := tail.read(responseListIndex) nextResponseHead := next.read(responseIndex) nextDataIsPresent := dataIsPresent(nextResponseHead) // Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since // there isn't a next element in the linked list. isResponseInOrder := responseHead === responseIndex isEndOfList := responseHead === responseTail isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1 // When a response's last beat is sent to the output channel, mark it as completed. This can happen in two // situations: // 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM // reservation was never needed. // 2. An entry is read out of the 'data' SRAM (within the unwind FSM). when(ioDataOut.fire && isLastBeat) { // Mark the reservation as no-longer-used. usedClr := UIntToOH(responseIndex, params.numEntries) // If the response is in-order, then we're popping an element from this linked list. when(isEndOfList) { // Once we pop the last element from a linked list, mark it as no-longer-present. validClr := UIntToOH(responseListIndex, params.numLists) }.otherwise { // Move the linked list's head pointer to the new head pointer. head.write(responseListIndex, nextResponseHead) } } // If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding. when(ioResponse.fire && !isResponseInOrder) { dataMemWriteEnable := true.B when(isLastResponseBeat) { dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries) beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1) } } // Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to. val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats) (responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) => when(select && dataMemWriteEnable) { seqMem.write(ioResponse.bits.index, ioResponse.bits.data) } } / Response unwind logic / // Unwind FSM state definitions val sIdle :: sUnwinding :: Nil = Enum(2) val unwindState = RegInit(sIdle) val busyUnwinding = unwindState === sUnwinding val startUnwind = Wire(Bool()) val stopUnwind = Wire(Bool()) when(startUnwind) { unwindState := sUnwinding }.elsewhen(stopUnwind) { unwindState := sIdle } assert(!(startUnwind && stopUnwind)) // Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to // become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is // invalid. // // Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to // worry about overwriting the 'data' SRAM's output when we start the unwind FSM. startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent // Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of // two things happens: // 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent) // 2. There are no more outstanding responses in this list (isEndOfList) // // Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are // passing from 'ioResponse' to 'ioDataOut'. stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent \|\| isEndOfList) val isUnwindBurstOver = Wire(Bool()) val startNewBurst = startUnwind \|\| (isUnwindBurstOver && dataMemReadEnable) // Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of // beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we // increment 'beatCounter' until it reaches 'unwindBeats1'. val unwindBeats1 = Reg(UInt(params.beatBits.W)) val nextBeatCounter = Wire(UInt(params.beatBits.W)) val beatCounter = RegNext(nextBeatCounter) isUnwindBurstOver := beatCounter === unwindBeats1 when(startNewBurst) { unwindBeats1 := beats.read(nextResponseHead) nextBeatCounter := 0.U }.elsewhen(dataMemReadEnable) { nextBeatCounter := beatCounter + 1.U }.otherwise { nextBeatCounter := beatCounter } // When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next // entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which // happens at the start of reading a new stored burst). val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst) responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index) // Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the // SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead // holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'. val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex) // The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid // until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle). val unwindDataIsValid = RegInit(false.B) when(dataMemReadEnable) { unwindDataIsValid := true.B }.elsewhen(ioDataOut.fire) { unwindDataIsValid := false.B } isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid // Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats. isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat) // Select which SRAM to read from based on the beat counter. val dataOutputVec = Wire(Vec(params.numBeats, gen)) val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats) (nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) => dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable) } // Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured // by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading // from. val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable) // Mark 'data' burst entries as no-longer-present as they get read out of the SRAM. when(dataMemReadEnable) { dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries) } // As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue // a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know // we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be // consumed by the output channel). val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready dataMemReadEnable := startUnwind \|\| (busyUnwinding && !stopUnwind && !dontReadFromDataMem) // While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need // 'responseListIndex' to be coherent for the entire unwind process. val rawResponseListIndex = map.read(responseIndex) val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst) responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex) // Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are // just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that // could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be // single-ported. ioResponse.ready := (ioDataOut.ready \|\| !isResponseInOrder) && !busyUnwinding // Either pass an in-order response to the output channel, or data read from the unwind FSM. ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder) ioDataOut.bits.listIndex := responseListIndex ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data) // It's an error to get a response that isn't associated with a valid linked list. when(ioResponse.fire \|\| unwindDataIsValid) { assert( valid(responseListIndex), "No linked list exists at index %d, mapped from %d", responseListIndex, responseIndex ) } when(busyUnwinding && dataMemReadEnable) { assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order") } } /* Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1. * * Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to * reorder any responses, or store any linked lists. */ class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters) extends BaseReservableListBuffer(gen, params) { require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1") val used = RegInit(0.U(params.numEntries.W)) val map = Mem(params.numEntries, UInt(params.listBits.W)) val usedSet = WireDefault(0.U(params.numEntries.W)) val usedClr = WireDefault(0.U(params.numEntries.W)) used := (used & ~usedClr) \| usedSet ioReserve.ready := used === 0.U // Store which list index was reserved, we need to return this value when we get a response. when(ioReserve.fire) { usedSet := 1.U map.write(0.U, ioReserve.bits) } // There's only one valid linked list entry, which is at index 0. ioReservedIndex := 0.U val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1 // Mark the linked list as empty when we get the last beat in a response. // Note that 'ioResponse.fire === ioDataOut.fire'. when(ioResponse.fire && isLastResponseBeat) { usedClr := 1.U } // Always pass the response data straight through, since we never need to reorder the response data. ioDataOut.bits.listIndex := map.read(0.U) ioDataOut.bits.payload := ioResponse.bits.data ioDataOut.valid := ioResponse.valid ioResponse.ready := ioDataOut.ready }	module dataMems_399( // @[UnsafeAXI4ToTL.scala:365:62] input [4:0] R0_addr, input R0_en, input R0_clk, output [66:0] R0_data, input [4:0] W0_addr, input W0_en, input W0_clk, input [66:0] W0_data ); dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62] .R0_addr (R0_addr), .R0_en (R0_en), .R0_clk (R0_clk), .R0_data (R0_data), .W0_addr (W0_addr), .W0_en (W0_en), .W0_clk (W0_clk), .W0_data (W0_data) ); // @[UnsafeAXI4ToTL.scala:365:62] endmodule
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Nodes.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection} case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args)) object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle] { def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo) def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo) def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle) def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle) def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" / black /, label = (ei.manager.beatBytes 8).toString) override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = { val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge))) monitor.io.in := bundle } override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters = pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }) override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters = pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }) } trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut] case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode case class TLAdapterNode( clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s }, managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLJunctionNode( clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters], managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])( implicit valName: ValName) extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode object TLNameNode { def apply(name: ValName) = TLIdentityNode()(name) def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLIdentityNode = apply(Some(name)) } case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)() object TLTempNode { def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp")) } case class TLNexusNode( clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters, managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)( implicit valName: ValName) extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode abstract class TLCustomNode(implicit valName: ValName) extends CustomNode(TLImp) with TLFormatNode // Asynchronous crossings trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters] object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle] { def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle) def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red /, label = e.manager.async.depth.toString) override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLAsyncAdapterNode( clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s }, managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode object TLAsyncNameNode { def apply(name: ValName) = TLAsyncIdentityNode()(name) def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLAsyncIdentityNode = apply(Some(name)) } case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLAsyncImp)( dFn = { p => TLAsyncClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName) extends MixedAdapterNode(TLAsyncImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) }, uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut] // Rationally related crossings trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters] object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle] { def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle) def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" / green /) override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLRationalAdapterNode( clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s }, managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode object TLRationalNameNode { def apply(name: ValName) = TLRationalIdentityNode()(name) def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLRationalIdentityNode = apply(Some(name)) } case class TLRationalSourceNode()(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLRationalImp)( dFn = { p => TLRationalClientPortParameters(p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName) extends MixedAdapterNode(TLRationalImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut] // Credited version of TileLink channels trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters] object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle] { def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo) def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle) def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" / yellow /, e.delay.toString) override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters = pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })) override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters = pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })) } case class TLCreditedAdapterNode( clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s }, managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })( implicit valName: ValName) extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode object TLCreditedNameNode { def apply(name: ValName) = TLCreditedIdentityNode()(name) def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name"))) def apply(name: String): TLCreditedIdentityNode = apply(Some(name)) } case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLImp, TLCreditedImp)( dFn = { p => TLCreditedClientPortParameters(delay, p) }, uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName) extends MixedAdapterNode(TLCreditedImp, TLImp)( dFn = { p => p.base.v1copy(minLatency = 1) }, uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut] File ToAXI4.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.amba.{AMBACorrupt, AMBACorruptField, AMBAProt, AMBAProtField} import freechips.rocketchip.amba.axi4.{AXI4BundleARW, AXI4MasterParameters, AXI4MasterPortParameters, AXI4Parameters, AXI4Imp} import freechips.rocketchip.diplomacy.{IdMap, IdMapEntry, IdRange} import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, UIntToOH1} import freechips.rocketchip.util.DataToAugmentedData class AXI4TLStateBundle(val sourceBits: Int) extends Bundle { val size = UInt(4.W) val source = UInt((sourceBits max 1).W) } case object AXI4TLState extends ControlKey[AXI4TLStateBundle]("tl_state") case class AXI4TLStateField(sourceBits: Int) extends BundleField[AXI4TLStateBundle](AXI4TLState, Output(new AXI4TLStateBundle(sourceBits)), x => { x.size := 0.U x.source := 0.U }) /* TLtoAXI4IdMap serves as a record for the translation performed between id spaces. * * Its member [axi4Masters] is used as the new AXI4MasterParameters in diplomacy. * Its member [mapping] is used as the template for the circuit generated in TLToAXI4Node.module. / class TLtoAXI4IdMap(tlPort: TLMasterPortParameters) extends IdMap[TLToAXI4IdMapEntry] { val tlMasters = tlPort.masters.sortBy(_.sourceId).sortWith(TLToAXI4.sortByType) private val axi4IdSize = tlMasters.map { tl => if (tl.requestFifo) 1 else tl.sourceId.size } private val axi4IdStart = axi4IdSize.scanLeft(0)(_+_).init val axi4Masters = axi4IdStart.zip(axi4IdSize).zip(tlMasters).map { case ((start, size), tl) => AXI4MasterParameters( name = tl.name, id = IdRange(start, start+size), aligned = true, maxFlight = Some(if (tl.requestFifo) tl.sourceId.size else 1), nodePath = tl.nodePath) } private val axi4IdEnd = axi4Masters.map(_.id.end).max private val axiDigits = String.valueOf(axi4IdEnd-1).length() private val tlDigits = String.valueOf(tlPort.endSourceId-1).length() protected val fmt = s"\t[%${axiDigits}d, %${axiDigits}d) <= [%${tlDigits}d, %${tlDigits}d) %s%s%s" val mapping: Seq[TLToAXI4IdMapEntry] = tlMasters.zip(axi4Masters).map { case (tl, axi) => TLToAXI4IdMapEntry(axi.id, tl.sourceId, tl.name, tl.supports.probe, tl.requestFifo) } } case class TLToAXI4IdMapEntry(axi4Id: IdRange, tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean) extends IdMapEntry { val from = tlId val to = axi4Id val maxTransactionsInFlight = Some(tlId.size) } case class TLToAXI4Node(wcorrupt: Boolean = true)(implicit valName: ValName) extends MixedAdapterNode(TLImp, AXI4Imp)( dFn = { p => AXI4MasterPortParameters( masters = (new TLtoAXI4IdMap(p)).axi4Masters, requestFields = (if (wcorrupt) Seq(AMBACorruptField()) else Seq()) ++ p.requestFields.filter(!_.isInstanceOf[AMBAProtField]), echoFields = AXI4TLStateField(log2Ceil(p.endSourceId)) +: p.echoFields, responseKeys = p.responseKeys) }, uFn = { p => TLSlavePortParameters.v1( managers = p.slaves.map { case s => TLSlaveParameters.v1( address = s.address, resources = s.resources, regionType = s.regionType, executable = s.executable, nodePath = s.nodePath, supportsGet = s.supportsRead, supportsPutFull = s.supportsWrite, supportsPutPartial = s.supportsWrite, fifoId = Some(0), mayDenyPut = true, mayDenyGet = true)}, beatBytes = p.beatBytes, minLatency = p.minLatency, responseFields = p.responseFields, requestKeys = AMBAProt +: p.requestKeys) }) // wcorrupt alone is not enough; a slave must include AMBACorrupt in the slave port's requestKeys class TLToAXI4(val combinational: Boolean = true, val adapterName: Option[String] = None, val stripBits: Int = 0, val wcorrupt: Boolean = true)(implicit p: Parameters) extends LazyModule { require(stripBits == 0, "stripBits > 0 is no longer supported on TLToAXI4") val node = TLToAXI4Node(wcorrupt) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => val slaves = edgeOut.slave.slaves // All pairs of slaves must promise that they will never interleave data require (slaves(0).interleavedId.isDefined) slaves.foreach { s => require (s.interleavedId == slaves(0).interleavedId) } // Construct the source=>ID mapping table val map = new TLtoAXI4IdMap(edgeIn.client) val sourceStall = WireDefault(VecInit.fill(edgeIn.client.endSourceId)(false.B)) val sourceTable = WireDefault(VecInit.fill(edgeIn.client.endSourceId)(0.U.asTypeOf(out.aw.bits.id))) val idStall = WireDefault(VecInit.fill(edgeOut.master.endId)(false.B)) var idCount = Array.fill(edgeOut.master.endId) { None:Option[Int] } map.mapping.foreach { case TLToAXI4IdMapEntry(axi4Id, tlId, _, _, fifo) => for (i <- 0 until tlId.size) { val id = axi4Id.start + (if (fifo) 0 else i) sourceStall(tlId.start + i) := idStall(id) sourceTable(tlId.start + i) := id.U } if (fifo) { idCount(axi4Id.start) = Some(tlId.size) } } adapterName.foreach { n => println(s"$n AXI4-ID <= TL-Source mapping:\n${map.pretty}\n") ElaborationArtefacts.add(s"$n.axi4.json", s"""{"mapping":[${map.mapping.mkString(",")}]}""") } // We need to keep the following state from A => D: (size, source) // All of those fields could potentially require 0 bits (argh. Chisel.) // We will pack all of that extra information into the echo bits. require (log2Ceil(edgeIn.maxLgSize+1) <= 4) val a_address = edgeIn.address(in.a.bits) val a_source = in.a.bits.source val a_size = edgeIn.size(in.a.bits) val a_isPut = edgeIn.hasData(in.a.bits) val (a_first, a_last, _) = edgeIn.firstlast(in.a) val r_state = out.r.bits.echo(AXI4TLState) val r_source = r_state.source val r_size = r_state.size val b_state = out.b.bits.echo(AXI4TLState) val b_source = b_state.source val b_size = b_state.size // We need these Queues because AXI4 queues are irrevocable val depth = if (combinational) 1 else 2 val out_arw = Wire(Decoupled(new AXI4BundleARW(out.params))) val out_w = Wire(chiselTypeOf(out.w)) out.w :<>= Queue.irrevocable(out_w, entries=depth, flow=combinational) val queue_arw = Queue.irrevocable(out_arw, entries=depth, flow=combinational) // Fan out the ARW channel to AR and AW out.ar.bits := queue_arw.bits out.aw.bits := queue_arw.bits out.ar.valid := queue_arw.valid && !queue_arw.bits.wen out.aw.valid := queue_arw.valid && queue_arw.bits.wen queue_arw.ready := Mux(queue_arw.bits.wen, out.aw.ready, out.ar.ready) val beatBytes = edgeIn.manager.beatBytes val maxSize = log2Ceil(beatBytes).U val doneAW = RegInit(false.B) when (in.a.fire) { doneAW := !a_last } val arw = out_arw.bits arw.wen := a_isPut arw.id := sourceTable(a_source) arw.addr := a_address arw.len := UIntToOH1(a_size, AXI4Parameters.lenBits + log2Ceil(beatBytes)) >> log2Ceil(beatBytes) arw.size := Mux(a_size >= maxSize, maxSize, a_size) arw.burst := AXI4Parameters.BURST_INCR arw.lock := 0.U // not exclusive (LR/SC unsupported b/c no forward progress guarantee) arw.cache := 0.U // do not allow AXI to modify our transactions arw.prot := AXI4Parameters.PROT_PRIVILEGED arw.qos := 0.U // no QoS Connectable.waiveUnmatched(arw.user, in.a.bits.user) match { case (lhs, rhs) => lhs :<= rhs } Connectable.waiveUnmatched(arw.echo, in.a.bits.echo) match { case (lhs, rhs) => lhs :<= rhs } val a_extra = arw.echo(AXI4TLState) a_extra.source := a_source a_extra.size := a_size in.a.bits.user.lift(AMBAProt).foreach { x => val prot = Wire(Vec(3, Bool())) val cache = Wire(Vec(4, Bool())) prot(0) := x.privileged prot(1) := !x.secure prot(2) := x.fetch cache(0) := x.bufferable cache(1) := x.modifiable cache(2) := x.readalloc cache(3) := x.writealloc arw.prot := Cat(prot.reverse) arw.cache := Cat(cache.reverse) } val stall = sourceStall(in.a.bits.source) && a_first in.a.ready := !stall && Mux(a_isPut, (doneAW \|\| out_arw.ready) && out_w.ready, out_arw.ready) out_arw.valid := !stall && in.a.valid && Mux(a_isPut, !doneAW && out_w.ready, true.B) out_w.valid := !stall && in.a.valid && a_isPut && (doneAW \|\| out_arw.ready) out_w.bits.data := in.a.bits.data out_w.bits.strb := in.a.bits.mask out_w.bits.last := a_last out_w.bits.user.lift(AMBACorrupt).foreach { _ := in.a.bits.corrupt } // R and B => D arbitration val r_holds_d = RegInit(false.B) when (out.r.fire) { r_holds_d := !out.r.bits.last } // Give R higher priority than B, unless B has been delayed for 8 cycles val b_delay = Reg(UInt(3.W)) when (out.b.valid && !out.b.ready) { b_delay := b_delay + 1.U } .otherwise { b_delay := 0.U } val r_wins = (out.r.valid && b_delay =/= 7.U) \|\| r_holds_d out.r.ready := in.d.ready && r_wins out.b.ready := in.d.ready && !r_wins in.d.valid := Mux(r_wins, out.r.valid, out.b.valid) // If the first beat of the AXI RRESP is RESP_DECERR, treat this as a denied // request. We must pulse extend this value as AXI is allowed to change the // value of RRESP on every beat, and ChipLink may not. val r_first = RegInit(true.B) when (out.r.fire) { r_first := out.r.bits.last } val r_denied = out.r.bits.resp === AXI4Parameters.RESP_DECERR holdUnless r_first val r_corrupt = out.r.bits.resp =/= AXI4Parameters.RESP_OKAY val b_denied = out.b.bits.resp =/= AXI4Parameters.RESP_OKAY val r_d = edgeIn.AccessAck(r_source, r_size, 0.U, denied = r_denied, corrupt = r_corrupt \|\| r_denied) val b_d = edgeIn.AccessAck(b_source, b_size, denied = b_denied) Connectable.waiveUnmatched(r_d.user, out.r.bits.user) match { case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll } Connectable.waiveUnmatched(r_d.echo, out.r.bits.echo) match { case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll } Connectable.waiveUnmatched(b_d.user, out.b.bits.user) match { case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll } Connectable.waiveUnmatched(b_d.echo, out.b.bits.echo) match { case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll } in.d.bits := Mux(r_wins, r_d, b_d) in.d.bits.data := out.r.bits.data // avoid a costly Mux // We need to track if any reads or writes are inflight for a given ID. // If the opposite type arrives, we must stall until it completes. val a_sel = UIntToOH(arw.id, edgeOut.master.endId).asBools val d_sel = UIntToOH(Mux(r_wins, out.r.bits.id, out.b.bits.id), edgeOut.master.endId).asBools val d_last = Mux(r_wins, out.r.bits.last, true.B) // If FIFO was requested, ensure that R+W ordering is preserved (a_sel zip d_sel zip idStall zip idCount) foreach { case (((as, ds), s), n) => // AXI does not guarantee read vs. write ordering. In particular, if we // are in the middle of receiving a read burst and then issue a write, // the write might affect the read burst. This violates FIFO behaviour. // To solve this, we must wait until the last beat of a burst, but this // means that a TileLink master which performs early source reuse can // have one more transaction inflight than we promised AXI; stall it too. val maxCount = n.getOrElse(1) val count = RegInit(0.U(log2Ceil(maxCount + 1).W)) val write = Reg(Bool()) val idle = count === 0.U val inc = as && out_arw.fire val dec = ds && d_last && in.d.fire count := count + inc.asUInt - dec.asUInt assert (!dec \|\| count =/= 0.U) // underflow assert (!inc \|\| count =/= maxCount.U) // overflow when (inc) { write := arw.wen } // If only one transaction can be inflight, it can't mismatch val mismatch = if (maxCount > 1) { write =/= arw.wen } else { false.B } s := (!idle && mismatch) \|\| (count === maxCount.U) } // Tie off unused channels in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B } } } object TLToAXI4 { def apply(combinational: Boolean = true, adapterName: Option[String] = None, stripBits: Int = 0, wcorrupt: Boolean = true)(implicit p: Parameters) = { val tl2axi4 = LazyModule(new TLToAXI4(combinational, adapterName, stripBits, wcorrupt)) tl2axi4.node } def sortByType(a: TLMasterParameters, b: TLMasterParameters): Boolean = { if ( a.supports.probe && !b.supports.probe) return false if (!a.supports.probe && b.supports.probe) return true if ( a.requestFifo && !b.requestFifo ) return false if (!a.requestFifo && b.requestFifo ) return true return false } } File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLToAXI4( // @[ToAXI4.scala:103:9] input clock, // @[ToAXI4.scala:103:9] input reset, // @[ToAXI4.scala:103:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_aw_ready, // @[LazyModuleImp.scala:107:25] output auto_out_aw_valid, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_aw_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_aw_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_aw_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_aw_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_out_w_ready, // @[LazyModuleImp.scala:107:25] output auto_out_w_valid, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_w_bits_data, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_w_bits_strb, // @[LazyModuleImp.scala:107:25] output auto_out_w_bits_last, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [5:0] auto_out_b_bits_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_resp, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_out_b_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_out_ar_ready, // @[LazyModuleImp.scala:107:25] output auto_out_ar_valid, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_ar_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_ar_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_ar_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] output [5:0] auto_out_ar_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] output auto_out_r_ready, // @[LazyModuleImp.scala:107:25] input auto_out_r_valid, // @[LazyModuleImp.scala:107:25] input [5:0] auto_out_r_bits_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_r_bits_data, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_r_bits_resp, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_r_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25] input [5:0] auto_out_r_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25] input auto_out_r_bits_last // @[LazyModuleImp.scala:107:25] ); reg count_57; // @[ToAXI4.scala:272:28] reg count_56; // @[ToAXI4.scala:272:28] reg count_55; // @[ToAXI4.scala:272:28] reg count_54; // @[ToAXI4.scala:272:28] reg count_53; // @[ToAXI4.scala:272:28] reg count_52; // @[ToAXI4.scala:272:28] reg count_51; // @[ToAXI4.scala:272:28] reg count_50; // @[ToAXI4.scala:272:28] reg count_49; // @[ToAXI4.scala:272:28] reg count_48; // @[ToAXI4.scala:272:28] reg count_47; // @[ToAXI4.scala:272:28] reg count_46; // @[ToAXI4.scala:272:28] reg count_45; // @[ToAXI4.scala:272:28] reg count_44; // @[ToAXI4.scala:272:28] reg count_43; // @[ToAXI4.scala:272:28] reg count_42; // @[ToAXI4.scala:272:28] reg count_41; // @[ToAXI4.scala:272:28] reg count_40; // @[ToAXI4.scala:272:28] reg count_39; // @[ToAXI4.scala:272:28] reg count_38; // @[ToAXI4.scala:272:28] reg count_37; // @[ToAXI4.scala:272:28] reg count_36; // @[ToAXI4.scala:272:28] reg count_35; // @[ToAXI4.scala:272:28] reg count_34; // @[ToAXI4.scala:272:28] reg count_33; // @[ToAXI4.scala:272:28] reg count_32; // @[ToAXI4.scala:272:28] reg count_31; // @[ToAXI4.scala:272:28] reg count_30; // @[ToAXI4.scala:272:28] reg count_29; // @[ToAXI4.scala:272:28] reg count_28; // @[ToAXI4.scala:272:28] reg count_27; // @[ToAXI4.scala:272:28] reg count_26; // @[ToAXI4.scala:272:28] reg count_25; // @[ToAXI4.scala:272:28] reg count_24; // @[ToAXI4.scala:272:28] reg count_23; // @[ToAXI4.scala:272:28] reg count_22; // @[ToAXI4.scala:272:28] reg count_21; // @[ToAXI4.scala:272:28] reg count_20; // @[ToAXI4.scala:272:28] reg count_19; // @[ToAXI4.scala:272:28] reg count_18; // @[ToAXI4.scala:272:28] reg count_17; // @[ToAXI4.scala:272:28] reg count_16; // @[ToAXI4.scala:272:28] reg count_15; // @[ToAXI4.scala:272:28] reg count_14; // @[ToAXI4.scala:272:28] reg count_13; // @[ToAXI4.scala:272:28] reg count_12; // @[ToAXI4.scala:272:28] reg count_11; // @[ToAXI4.scala:272:28] reg count_10; // @[ToAXI4.scala:272:28] reg count_9; // @[ToAXI4.scala:272:28] reg count_8; // @[ToAXI4.scala:272:28] reg count_7; // @[ToAXI4.scala:272:28] reg count_6; // @[ToAXI4.scala:272:28] reg count_5; // @[ToAXI4.scala:272:28] reg count_4; // @[ToAXI4.scala:272:28] reg count_3; // @[ToAXI4.scala:272:28] reg count_2; // @[ToAXI4.scala:272:28] reg count_1; // @[ToAXI4.scala:272:28] reg count; // @[ToAXI4.scala:272:28] wire _queue_arw_deq_q_io_enq_ready; // @[Decoupled.scala:362:21] wire _queue_arw_deq_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [5:0] _queue_arw_deq_q_io_deq_bits_id; // @[Decoupled.scala:362:21] wire [31:0] _queue_arw_deq_q_io_deq_bits_addr; // @[Decoupled.scala:362:21] wire [7:0] _queue_arw_deq_q_io_deq_bits_len; // @[Decoupled.scala:362:21] wire [2:0] _queue_arw_deq_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [1:0] _queue_arw_deq_q_io_deq_bits_burst; // @[Decoupled.scala:362:21] wire _queue_arw_deq_q_io_deq_bits_lock; // @[Decoupled.scala:362:21] wire [3:0] _queue_arw_deq_q_io_deq_bits_cache; // @[Decoupled.scala:362:21] wire [2:0] _queue_arw_deq_q_io_deq_bits_prot; // @[Decoupled.scala:362:21] wire [3:0] _queue_arw_deq_q_io_deq_bits_qos; // @[Decoupled.scala:362:21] wire [3:0] _queue_arw_deq_q_io_deq_bits_echo_tl_state_size; // @[Decoupled.scala:362:21] wire [5:0] _queue_arw_deq_q_io_deq_bits_echo_tl_state_source; // @[Decoupled.scala:362:21] wire _queue_arw_deq_q_io_deq_bits_wen; // @[Decoupled.scala:362:21] wire _nodeOut_w_deq_q_io_enq_ready; // @[Decoupled.scala:362:21] wire [63:0][5:0] _GEN = '{6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h39, 6'h38, 6'h37, 6'h36, 6'h35, 6'h34, 6'h33, 6'h32, 6'h31, 6'h30, 6'h2F, 6'h2E, 6'h2D, 6'h2C, 6'h2B, 6'h2A, 6'h29, 6'h28, 6'h27, 6'h26, 6'h25, 6'h24, 6'h23, 6'h22, 6'h21, 6'h20, 6'h1F, 6'h1E, 6'h1D, 6'h1C, 6'h1B, 6'h1A, 6'h19, 6'h18, 6'h17, 6'h16, 6'h15, 6'h14, 6'h13, 6'h12, 6'h11, 6'h10, 6'hF, 6'hE, 6'hD, 6'hC, 6'hB, 6'hA, 6'h9, 6'h8, 6'h7, 6'h6, 6'h5, 6'h4, 6'h3, 6'h2, 6'h1, 6'h0}; wire [12:0] _r_beats1_decode_T = 13'h3F << auto_in_a_bits_size; // @[package.scala:243:71] wire [2:0] r_beats1 = auto_in_a_bits_opcode[2] ? 3'h0 : ~(_r_beats1_decode_T[5:3]); // @[package.scala:243:{46,71,76}] reg [2:0] r_counter; // @[Edges.scala:229:27] wire a_first = r_counter == 3'h0; // @[ToAXI4.scala:103:9] wire a_last = r_counter == 3'h1 \| r_beats1 == 3'h0; // @[ToAXI4.scala:103:9] reg doneAW; // @[ToAXI4.scala:167:30] wire [17:0] _out_arw_bits_len_T = 18'h7FF << auto_in_a_bits_size; // @[package.scala:243:71] wire [63:0] _GEN_0 = {{count}, {count}, {count}, {count}, {count}, {count}, {count_57}, {count_56}, {count_55}, {count_54}, {count_53}, {count_52}, {count_51}, {count_50}, {count_49}, {count_48}, {count_47}, {count_46}, {count_45}, {count_44}, {count_43}, {count_42}, {count_41}, {count_40}, {count_39}, {count_38}, {count_37}, {count_36}, {count_35}, {count_34}, {count_33}, {count_32}, {count_31}, {count_30}, {count_29}, {count_28}, {count_27}, {count_26}, {count_25}, {count_24}, {count_23}, {count_22}, {count_21}, {count_20}, {count_19}, {count_18}, {count_17}, {count_16}, {count_15}, {count_14}, {count_13}, {count_12}, {count_11}, {count_10}, {count_9}, {count_8}, {count_7}, {count_6}, {count_5}, {count_4}, {count_3}, {count_2}, {count_1}, {count}}; // @[ToAXI4.scala:205:49, :272:28] wire stall = _GEN_0[auto_in_a_bits_source] & a_first; // @[ToAXI4.scala:205:49] wire _out_w_valid_T_3 = doneAW \| _queue_arw_deq_q_io_enq_ready; // @[Decoupled.scala:362:21] wire nodeIn_a_ready = ~stall & (auto_in_a_bits_opcode[2] ? _queue_arw_deq_q_io_enq_ready : _out_w_valid_T_3 & _nodeOut_w_deq_q_io_enq_ready); // @[Decoupled.scala:362:21] wire out_arw_valid = ~stall & auto_in_a_valid & (auto_in_a_bits_opcode[2] \| ~doneAW & _nodeOut_w_deq_q_io_enq_ready); // @[Decoupled.scala:362:21] reg r_holds_d; // @[ToAXI4.scala:216:30] reg [2:0] b_delay; // @[ToAXI4.scala:219:24] wire r_wins = auto_out_r_valid & b_delay != 3'h7 \| r_holds_d; // @[ToAXI4.scala:216:30, :219:24, :225:{33,44,53}] wire nodeOut_r_ready = auto_in_d_ready & r_wins; // @[ToAXI4.scala:225:53, :227:33] wire nodeOut_b_ready = auto_in_d_ready & ~r_wins; // @[ToAXI4.scala:225:53, :228:{33,36}] wire nodeIn_d_valid = r_wins ? auto_out_r_valid : auto_out_b_valid; // @[ToAXI4.scala:225:53, :229:24] reg r_first; // @[ToAXI4.scala:234:28] reg r_denied_r; // @[package.scala:88:63] wire r_denied = r_first ? (&auto_out_r_bits_resp) : r_denied_r; // @[package.scala:88:{42,63}] wire [2:0] nodeIn_d_bits_opcode = {2'h0, r_wins}; // @[ToAXI4.scala:103:9, :225:53, :255:23] wire [2:0] nodeIn_d_bits_size = r_wins ? auto_out_r_bits_echo_tl_state_size[2:0] : auto_out_b_bits_echo_tl_state_size[2:0]; // @[ToAXI4.scala:225:53, :255:23] wire [5:0] nodeIn_d_bits_source = r_wins ? auto_out_r_bits_echo_tl_state_source : auto_out_b_bits_echo_tl_state_source; // @[ToAXI4.scala:225:53, :255:23] wire nodeIn_d_bits_denied = r_wins ? r_denied : (\|auto_out_b_bits_resp); // @[package.scala:88:42] wire nodeIn_d_bits_corrupt = r_wins & ((\|auto_out_r_bits_resp) \| r_denied); // @[package.scala:88:42] wire [5:0] d_sel_shiftAmount = r_wins ? auto_out_r_bits_id : auto_out_b_bits_id; // @[ToAXI4.scala:225:53, :261:31] wire d_last = ~r_wins \| auto_out_r_bits_last; // @[ToAXI4.scala:225:53, :262:23] wire _inc_T_57 = _queue_arw_deq_q_io_enq_ready & out_arw_valid; // @[Decoupled.scala:51:35, :362:21] wire inc = _GEN[auto_in_a_bits_source] == 6'h0 & _inc_T_57; // @[OneHot.scala:65:27] wire _dec_T_115 = auto_in_d_ready & nodeIn_d_valid; // @[Decoupled.scala:51:35] wire dec = d_sel_shiftAmount == 6'h0 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_1 = _GEN[auto_in_a_bits_source] == 6'h1 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_1 = d_sel_shiftAmount == 6'h1 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_2 = _GEN[auto_in_a_bits_source] == 6'h2 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_2 = d_sel_shiftAmount == 6'h2 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_3 = _GEN[auto_in_a_bits_source] == 6'h3 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_3 = d_sel_shiftAmount == 6'h3 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_4 = _GEN[auto_in_a_bits_source] == 6'h4 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_4 = d_sel_shiftAmount == 6'h4 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_5 = _GEN[auto_in_a_bits_source] == 6'h5 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_5 = d_sel_shiftAmount == 6'h5 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_6 = _GEN[auto_in_a_bits_source] == 6'h6 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_6 = d_sel_shiftAmount == 6'h6 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_7 = _GEN[auto_in_a_bits_source] == 6'h7 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_7 = d_sel_shiftAmount == 6'h7 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_8 = _GEN[auto_in_a_bits_source] == 6'h8 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_8 = d_sel_shiftAmount == 6'h8 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_9 = _GEN[auto_in_a_bits_source] == 6'h9 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_9 = d_sel_shiftAmount == 6'h9 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_10 = _GEN[auto_in_a_bits_source] == 6'hA & _inc_T_57; // @[OneHot.scala:65:27] wire dec_10 = d_sel_shiftAmount == 6'hA & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_11 = _GEN[auto_in_a_bits_source] == 6'hB & _inc_T_57; // @[OneHot.scala:65:27] wire dec_11 = d_sel_shiftAmount == 6'hB & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_12 = _GEN[auto_in_a_bits_source] == 6'hC & _inc_T_57; // @[OneHot.scala:65:27] wire dec_12 = d_sel_shiftAmount == 6'hC & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_13 = _GEN[auto_in_a_bits_source] == 6'hD & _inc_T_57; // @[OneHot.scala:65:27] wire dec_13 = d_sel_shiftAmount == 6'hD & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_14 = _GEN[auto_in_a_bits_source] == 6'hE & _inc_T_57; // @[OneHot.scala:65:27] wire dec_14 = d_sel_shiftAmount == 6'hE & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_15 = _GEN[auto_in_a_bits_source] == 6'hF & _inc_T_57; // @[OneHot.scala:65:27] wire dec_15 = d_sel_shiftAmount == 6'hF & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_16 = _GEN[auto_in_a_bits_source] == 6'h10 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_16 = d_sel_shiftAmount == 6'h10 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_17 = _GEN[auto_in_a_bits_source] == 6'h11 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_17 = d_sel_shiftAmount == 6'h11 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_18 = _GEN[auto_in_a_bits_source] == 6'h12 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_18 = d_sel_shiftAmount == 6'h12 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_19 = _GEN[auto_in_a_bits_source] == 6'h13 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_19 = d_sel_shiftAmount == 6'h13 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_20 = _GEN[auto_in_a_bits_source] == 6'h14 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_20 = d_sel_shiftAmount == 6'h14 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_21 = _GEN[auto_in_a_bits_source] == 6'h15 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_21 = d_sel_shiftAmount == 6'h15 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_22 = _GEN[auto_in_a_bits_source] == 6'h16 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_22 = d_sel_shiftAmount == 6'h16 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_23 = _GEN[auto_in_a_bits_source] == 6'h17 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_23 = d_sel_shiftAmount == 6'h17 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_24 = _GEN[auto_in_a_bits_source] == 6'h18 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_24 = d_sel_shiftAmount == 6'h18 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_25 = _GEN[auto_in_a_bits_source] == 6'h19 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_25 = d_sel_shiftAmount == 6'h19 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_26 = _GEN[auto_in_a_bits_source] == 6'h1A & _inc_T_57; // @[OneHot.scala:65:27] wire dec_26 = d_sel_shiftAmount == 6'h1A & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_27 = _GEN[auto_in_a_bits_source] == 6'h1B & _inc_T_57; // @[OneHot.scala:65:27] wire dec_27 = d_sel_shiftAmount == 6'h1B & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_28 = _GEN[auto_in_a_bits_source] == 6'h1C & _inc_T_57; // @[OneHot.scala:65:27] wire dec_28 = d_sel_shiftAmount == 6'h1C & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_29 = _GEN[auto_in_a_bits_source] == 6'h1D & _inc_T_57; // @[OneHot.scala:65:27] wire dec_29 = d_sel_shiftAmount == 6'h1D & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_30 = _GEN[auto_in_a_bits_source] == 6'h1E & _inc_T_57; // @[OneHot.scala:65:27] wire dec_30 = d_sel_shiftAmount == 6'h1E & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_31 = _GEN[auto_in_a_bits_source] == 6'h1F & _inc_T_57; // @[OneHot.scala:65:27] wire dec_31 = d_sel_shiftAmount == 6'h1F & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_32 = _GEN[auto_in_a_bits_source] == 6'h20 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_32 = d_sel_shiftAmount == 6'h20 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_33 = _GEN[auto_in_a_bits_source] == 6'h21 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_33 = d_sel_shiftAmount == 6'h21 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_34 = _GEN[auto_in_a_bits_source] == 6'h22 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_34 = d_sel_shiftAmount == 6'h22 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_35 = _GEN[auto_in_a_bits_source] == 6'h23 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_35 = d_sel_shiftAmount == 6'h23 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_36 = _GEN[auto_in_a_bits_source] == 6'h24 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_36 = d_sel_shiftAmount == 6'h24 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_37 = _GEN[auto_in_a_bits_source] == 6'h25 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_37 = d_sel_shiftAmount == 6'h25 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_38 = _GEN[auto_in_a_bits_source] == 6'h26 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_38 = d_sel_shiftAmount == 6'h26 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_39 = _GEN[auto_in_a_bits_source] == 6'h27 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_39 = d_sel_shiftAmount == 6'h27 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_40 = _GEN[auto_in_a_bits_source] == 6'h28 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_40 = d_sel_shiftAmount == 6'h28 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_41 = _GEN[auto_in_a_bits_source] == 6'h29 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_41 = d_sel_shiftAmount == 6'h29 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_42 = _GEN[auto_in_a_bits_source] == 6'h2A & _inc_T_57; // @[OneHot.scala:65:27] wire dec_42 = d_sel_shiftAmount == 6'h2A & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_43 = _GEN[auto_in_a_bits_source] == 6'h2B & _inc_T_57; // @[OneHot.scala:65:27] wire dec_43 = d_sel_shiftAmount == 6'h2B & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_44 = _GEN[auto_in_a_bits_source] == 6'h2C & _inc_T_57; // @[OneHot.scala:65:27] wire dec_44 = d_sel_shiftAmount == 6'h2C & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_45 = _GEN[auto_in_a_bits_source] == 6'h2D & _inc_T_57; // @[OneHot.scala:65:27] wire dec_45 = d_sel_shiftAmount == 6'h2D & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_46 = _GEN[auto_in_a_bits_source] == 6'h2E & _inc_T_57; // @[OneHot.scala:65:27] wire dec_46 = d_sel_shiftAmount == 6'h2E & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_47 = _GEN[auto_in_a_bits_source] == 6'h2F & _inc_T_57; // @[OneHot.scala:65:27] wire dec_47 = d_sel_shiftAmount == 6'h2F & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_48 = _GEN[auto_in_a_bits_source] == 6'h30 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_48 = d_sel_shiftAmount == 6'h30 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_49 = _GEN[auto_in_a_bits_source] == 6'h31 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_49 = d_sel_shiftAmount == 6'h31 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_50 = _GEN[auto_in_a_bits_source] == 6'h32 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_50 = d_sel_shiftAmount == 6'h32 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_51 = _GEN[auto_in_a_bits_source] == 6'h33 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_51 = d_sel_shiftAmount == 6'h33 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_52 = _GEN[auto_in_a_bits_source] == 6'h34 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_52 = d_sel_shiftAmount == 6'h34 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_53 = _GEN[auto_in_a_bits_source] == 6'h35 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_53 = d_sel_shiftAmount == 6'h35 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_54 = _GEN[auto_in_a_bits_source] == 6'h36 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_54 = d_sel_shiftAmount == 6'h36 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_55 = _GEN[auto_in_a_bits_source] == 6'h37 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_55 = d_sel_shiftAmount == 6'h37 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_56 = _GEN[auto_in_a_bits_source] == 6'h38 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_56 = d_sel_shiftAmount == 6'h38 & d_last & _dec_T_115; // @[OneHot.scala:65:27] wire inc_57 = _GEN[auto_in_a_bits_source] == 6'h39 & _inc_T_57; // @[OneHot.scala:65:27] wire dec_57 = d_sel_shiftAmount == 6'h39 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
Generate the Verilog code corresponding to the following Chisel files. File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File FPU.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import chisel3.util._ import chisel3.{DontCare, WireInit, withClock, withReset} import chisel3.experimental.SourceInfo import chisel3.experimental.dataview._ import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.rocket._ import freechips.rocketchip.rocket.Instructions._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property case class FPUParams( minFLen: Int = 32, fLen: Int = 64, divSqrt: Boolean = true, sfmaLatency: Int = 3, dfmaLatency: Int = 4, fpmuLatency: Int = 2, ifpuLatency: Int = 2 ) object FPConstants { val RM_SZ = 3 val FLAGS_SZ = 5 } trait HasFPUCtrlSigs { val ldst = Bool() val wen = Bool() val ren1 = Bool() val ren2 = Bool() val ren3 = Bool() val swap12 = Bool() val swap23 = Bool() val typeTagIn = UInt(2.W) val typeTagOut = UInt(2.W) val fromint = Bool() val toint = Bool() val fastpipe = Bool() val fma = Bool() val div = Bool() val sqrt = Bool() val wflags = Bool() val vec = Bool() } class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new Bundle { val inst = Input(Bits(32.W)) val sigs = Output(new FPUCtrlSigs()) }) private val X2 = BitPat.dontCare(2) val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N) val h: Array[(BitPat, List[BitPat])] = Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N), FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N), FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N), FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N), FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N), FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N), FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N), FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N), FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N), FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N), FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N), FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N), FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N), FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N), FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N), FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N)) val f: Array[(BitPat, List[BitPat])] = Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N), FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N), FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N), FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N), FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N), FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N), FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N), FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N), FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N), FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N), FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N), FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N), FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N), FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N)) val d: Array[(BitPat, List[BitPat])] = Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N), FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N), FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N), FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N), FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N), FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N), FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N), FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N), FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N), FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N), FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N), FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N), FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N), FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N), FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N), FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N), FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N)) val fcvt_hd: Array[(BitPat, List[BitPat])] = Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N), FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N)) val vfmv_f_s: Array[(BitPat, List[BitPat])] = Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y)) val insns = ((minFLen, fLen) match { case (32, 32) => f case (16, 32) => h ++ f case (32, 64) => f ++ d case (16, 64) => h ++ f ++ d ++ fcvt_hd case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration") }) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]()) val decoder = DecodeLogic(io.inst, default, insns) val s = io.sigs val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint, s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec) sigs zip decoder map {case(s,d) => s := d} } class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val time = Input(UInt(xLen.W)) val inst = Input(Bits(32.W)) val fromint_data = Input(Bits(xLen.W)) val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W)) val v_sew = Input(UInt(3.W)) val store_data = Output(Bits(fLen.W)) val toint_data = Output(Bits(xLen.W)) val ll_resp_val = Input(Bool()) val ll_resp_type = Input(Bits(3.W)) val ll_resp_tag = Input(UInt(5.W)) val ll_resp_data = Input(Bits(fLen.W)) val valid = Input(Bool()) val fcsr_rdy = Output(Bool()) val nack_mem = Output(Bool()) val illegal_rm = Output(Bool()) val killx = Input(Bool()) val killm = Input(Bool()) val dec = Output(new FPUCtrlSigs()) val sboard_set = Output(Bool()) val sboard_clr = Output(Bool()) val sboard_clra = Output(UInt(5.W)) val keep_clock_enabled = Input(Bool()) } class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) { val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs val cp_resp = Decoupled(new FPResult()) } class FPResult(implicit p: Parameters) extends CoreBundle()(p) { val data = Bits((fLen+1).W) val exc = Bits(FPConstants.FLAGS_SZ.W) } class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val typ = Bits(2.W) val in1 = Bits(xLen.W) } class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs { val rm = Bits(FPConstants.RM_SZ.W) val fmaCmd = Bits(2.W) val typ = Bits(2.W) val fmt = Bits(2.W) val in1 = Bits((fLen+1).W) val in2 = Bits((fLen+1).W) val in3 = Bits((fLen+1).W) } case class FType(exp: Int, sig: Int) { def ieeeWidth = exp + sig def recodedWidth = ieeeWidth + 1 def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W) def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W) def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2) def classify(x: UInt) = { val sign = x(sig + exp) val code = x(exp + sig - 1, exp + sig - 3) val codeHi = code(2, 1) val isSpecial = codeHi === 3.U val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U val isSubnormal = code === 1.U \|\| codeHi === 1.U && isHighSubnormalIn val isNormal = codeHi === 1.U && !isHighSubnormalIn \|\| codeHi === 2.U val isZero = code === 0.U val isInf = isSpecial && !code(0) val isNaN = code.andR val isSNaN = isNaN && !x(sig-2) val isQNaN = isNaN && x(sig-2) Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign, isSubnormal && !sign, isZero && !sign, isZero && sign, isSubnormal && sign, isNormal && sign, isInf && sign) } // convert between formats, ignoring rounding, range, NaN def unsafeConvert(x: UInt, to: FType) = if (this == to) x else { val sign = x(sig + exp) val fractIn = x(sig - 2, 0) val expIn = x(sig + exp - 1, sig - 1) val fractOut = fractIn << to.sig >> sig val expOut = { val expCode = expIn(exp, exp - 2) val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U Mux(expCode === 0.U \|\| expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0)) } Cat(sign, expOut, fractOut) } private def ieeeBundle = { val expWidth = exp class IEEEBundle extends Bundle { val sign = Bool() val exp = UInt(expWidth.W) val sig = UInt((ieeeWidth-expWidth-1).W) } new IEEEBundle } def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle) def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x) def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x) } object FType { val H = new FType(5, 11) val S = new FType(8, 24) val D = new FType(11, 53) val all = List(H, S, D) } trait HasFPUParameters { require(fLen == 0 \|\| FType.all.exists(_.ieeeWidth == fLen)) val minFLen: Int val fLen: Int def xLen: Int val minXLen = 32 val nIntTypes = log2Ceil(xLen/minXLen) + 1 def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen) def minType = floatTypes.head def maxType = floatTypes.last def prevType(t: FType) = floatTypes(typeTag(t) - 1) def maxExpWidth = maxType.exp def maxSigWidth = maxType.sig def typeTag(t: FType) = floatTypes.indexOf(t) def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U // typeTag def H = typeTagGroup(FType.H) def S = typeTagGroup(FType.S) def D = typeTagGroup(FType.D) def I = typeTag(maxType).U private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = { require(xt.ieeeWidth == 2 yt.ieeeWidth) val swizzledNaN = Cat( x(xt.sig + xt.exp, xt.sig + xt.exp - 3), x(xt.sig - 2, yt.recodedWidth - 1).andR, x(xt.sig + xt.exp - 5, xt.sig), y(yt.recodedWidth - 2), x(xt.sig - 2, yt.recodedWidth - 1), y(yt.recodedWidth - 1), y(yt.recodedWidth - 3, 0)) Mux(xt.isNaN(x), swizzledNaN, x) } // implement NaN unboxing for FU inputs def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = { val outType = exactType.getOrElse(maxType) def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = { val prev = if (t == minType) { Seq() } else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prev = helper(unswizzled, prevT) val isbox = isBox(x, t) prev.map(p => (isbox && p._1, p._2)) } prev :+ (true.B, t.unsafeConvert(x, outType)) } val (oks, floats) = helper(x, maxType).unzip if (exactType.isEmpty \|\| floatTypes.size == 1) { Mux(oks(tag), floats(tag), maxType.qNaN) } else { val t = exactType.get floats(typeTag(t)) \| Mux(oks(typeTag(t)), 0.U, t.qNaN) } } // make sure that the redundant bits in the NaN-boxed encoding are consistent def consistent(x: UInt): Bool = { def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else { val prevT = prevType(t) val unswizzled = Cat( x(prevT.sig + prevT.exp - 1), x(t.sig - 1), x(prevT.sig + prevT.exp - 2, 0)) val prevOK = !isBox(x, t) \|\| helper(unswizzled, prevT) val curOK = !t.isNaN(x) \|\| x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR prevOK && curOK } helper(x, maxType) } // generate a NaN box from an FU result def box(x: UInt, t: FType): UInt = { if (t == maxType) { x } else { val nt = floatTypes(typeTag(t) + 1) val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t) bigger \| ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U } } // generate a NaN box from an FU result def box(x: UInt, tag: UInt): UInt = { val opts = floatTypes.map(t => box(x, t)) opts(tag) } // zap bits that hardfloat thinks are don't-cares, but we do care about def sanitizeNaN(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { x } else { val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) \| (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W) Mux(t.isNaN(x), maskedNaN, x) } } // implement NaN boxing and recoding for FL/fmv..x def recode(x: UInt, tag: UInt): UInt = { def helper(x: UInt, t: FType): UInt = { if (typeTag(t) == 0) { t.recode(x) } else { val prevT = prevType(t) box(t.recode(x), t, helper(x, prevT), prevT) } } // fill MSBs of subword loads to emulate a wider load of a NaN-boxed value val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U) helper(boxes(tag) \| x, maxType) } // implement NaN unboxing and un-recoding for FS/fmv.x. def ieee(x: UInt, t: FType = maxType): UInt = { if (typeTag(t) == 0) { t.ieee(x) } else { val unrecoded = t.ieee(x) val prevT = prevType(t) val prevRecoded = Cat( x(prevT.recodedWidth-2), x(t.sig-1), x(prevT.recodedWidth-3, 0)) val prevUnrecoded = ieee(prevRecoded, prevT) Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0))) } } } abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { class Output extends Bundle { val in = new FPInput val lt = Bool() val store = Bits(fLen.W) val toint = Bits(xLen.W) val exc = Bits(FPConstants.FLAGS_SZ.W) } val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new Output) }) val in = RegEnable(io.in.bits, io.in.valid) val valid = RegNext(io.in.valid) val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth)) dcmp.io.a := in.in1 dcmp.io.b := in.in2 dcmp.io.signaling := !in.rm(1) val tag = in.typeTagOut val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen)) else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) val toint = WireDefault(toint_ieee) val intType = WireDefault(in.fmt(0)) io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag) io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType) io.out.bits.exc := 0.U when (in.rm(0)) { val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag) toint := classify_out \| (toint_ieee >> minXLen << minXLen) intType := false.B } when (in.wflags) { // feq/flt/fle, fcvt toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR \| (toint_ieee >> minXLen << minXLen) io.out.bits.exc := dcmp.io.exceptionFlags intType := false.B when (!in.ren2) { // fcvt val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1) intType := cvtType val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen)) conv.io.in := in.in1 conv.io.roundingMode := in.rm conv.io.signedOut := ~in.typ(0) toint := conv.io.out io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0)) for (i <- 0 until nIntTypes-1) { val w = minXLen << i when (cvtType === i.U) { val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w)) narrow.io.in := in.in1 narrow.io.roundingMode := in.rm narrow.io.signedOut := ~in.typ(0) val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1) val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign)) val invalid = conv.io.intExceptionFlags(2) \|\| narrow.io.intExceptionFlags(1) when (invalid) { toint := Cat(conv.io.out >> w, excOut) } io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0)) } } } } io.out.valid := valid io.out.bits.lt := dcmp.io.lt \|\| (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S) io.out.bits.in := in } class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new IntToFPInput)) val out = Valid(new FPResult) }) val in = Pipe(io.in) val tag = in.bits.typeTagIn val mux = Wire(new FPResult) mux.exc := 0.U mux.data := recode(in.bits.in1, tag) val intValue = { val res = WireDefault(in.bits.in1.asSInt) for (i <- 0 until nIntTypes-1) { val smallInt = in.bits.in1((minXLen << i) - 1, 0) when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) { res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt) } } res.asUInt } when (in.bits.wflags) { // fcvt // could be improved for RVD/RVQ with a single variable-position rounding // unit, rather than N fixed-position ones val i2fResults = for (t <- floatTypes) yield { val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig)) i2f.io.signedIn := ~in.bits.typ(0) i2f.io.in := intValue i2f.io.roundingMode := in.bits.rm i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding (sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags) } val (data, exc) = i2fResults.unzip val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last mux.data := dataPadded(tag) mux.exc := exc(tag) } io.out <> Pipe(in.valid, mux, latency-1) } class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) val lt = Input(Bool()) // from FPToInt }) val in = Pipe(io.in) val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2)) val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0)) val fsgnjMux = Wire(new FPResult) fsgnjMux.exc := 0.U fsgnjMux.data := fsgnj when (in.bits.wflags) { // fmin/fmax val isnan1 = maxType.isNaN(in.bits.in1) val isnan2 = maxType.isNaN(in.bits.in2) val isInvalid = maxType.isSNaN(in.bits.in1) \|\| maxType.isSNaN(in.bits.in2) val isNaNOut = isnan1 && isnan2 val isLHS = isnan2 \|\| in.bits.rm(0) =/= io.lt && !isnan1 fsgnjMux.exc := isInvalid << 4 fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2)) } val inTag = in.bits.typeTagIn val outTag = in.bits.typeTagOut val mux = WireDefault(fsgnjMux) for (t <- floatTypes.init) { when (outTag === typeTag(t).U) { mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t)) } } when (in.bits.wflags && !in.bits.ren2) { // fcvt if (floatTypes.size > 1) { // widening conversions simply canonicalize NaN operands val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1) fsgnjMux.data := widened fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4 // narrowing conversions require rounding (for RVQ, this could be // optimized to use a single variable-position rounding unit, rather // than two fixed-position ones) for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B \|\| outTag < inTag)) { val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig)) narrower.io.in := in.bits.in1 narrower.io.roundingMode := in.bits.rm narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding val narrowed = sanitizeNaN(narrower.io.out, outType) mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed) mux.exc := narrower.io.exceptionFlags } } } io.out <> Pipe(in.valid, mux, latency-1) } class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module { override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}" require(latency<=2) val io = IO(new Bundle { val validin = Input(Bool()) val op = Input(Bits(2.W)) val a = Input(Bits((expWidth + sigWidth + 1).W)) val b = Input(Bits((expWidth + sigWidth + 1).W)) val c = Input(Bits((expWidth + sigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((expWidth + sigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) val validout = Output(Bool()) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth)) val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth)) mulAddRecFNToRaw_preMul.io.op := io.op mulAddRecFNToRaw_preMul.io.a := io.a mulAddRecFNToRaw_preMul.io.b := io.b mulAddRecFNToRaw_preMul.io.c := io.c val mulAddResult = (mulAddRecFNToRaw_preMul.io.mulAddA * mulAddRecFNToRaw_preMul.io.mulAddB) +& mulAddRecFNToRaw_preMul.io.mulAddC val valid_stage0 = Wire(Bool()) val roundingMode_stage0 = Wire(UInt(3.W)) val detectTininess_stage0 = Wire(UInt(1.W)) val postmul_regs = if(latency>0) 1 else 0 mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid //------------------------------------------------------------------------ //------------------------------------------------------------------------ val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0)) val round_regs = if(latency==2) 1 else 0 roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits io.validout := Pipe(valid_stage0, false.B, round_regs).valid roundRawFNToRecFN.io.infiniteExc := false.B io.out := roundRawFNToRecFN.io.out io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags } class FPUFMAPipe(val latency: Int, val t: FType) (implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed { override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}" require(latency>0) val io = IO(new Bundle { val in = Flipped(Valid(new FPInput)) val out = Valid(new FPResult) }) val valid = RegNext(io.in.valid) val in = Reg(new FPInput) when (io.in.valid) { val one = 1.U << (t.sig + t.exp - 1) val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp)) val cmd_fma = io.in.bits.ren3 val cmd_addsub = io.in.bits.swap23 in := io.in.bits when (cmd_addsub) { in.in2 := one } when (!(cmd_fma \|\| cmd_addsub)) { in.in3 := zero } } val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig)) fma.io.validin := valid fma.io.op := in.fmaCmd fma.io.roundingMode := in.rm fma.io.detectTininess := hardfloat.consts.tininess_afterRounding fma.io.a := in.in1 fma.io.b := in.in2 fma.io.c := in.in3 val res = Wire(new FPResult) res.data := sanitizeNaN(fma.io.out, t) res.exc := fma.io.exceptionFlags io.out := Pipe(fma.io.validout, res, (latency-3) max 0) } class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) { val io = IO(new FPUIO) val (useClockGating, useDebugROB) = coreParams match { case r: RocketCoreParams => val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1 (r.clockGate, sz < 1) case _ => (false, false) } val clock_en_reg = Reg(Bool()) val clock_en = clock_en_reg \|\| io.cp_req.valid val gated_clock = if (!useClockGating) clock else ClockGate(clock, clock_en, "fpu_clock_gate") val fp_decoder = Module(new FPUDecoder) fp_decoder.io.inst := io.inst val id_ctrl = WireInit(fp_decoder.io.sigs) coreParams match { case r: RocketCoreParams => r.vector.map(v => { val v_decode = v.decoder(p) // Only need to get ren1 v_decode.io.inst := io.inst v_decode.io.vconfig := DontCare // core deals with this when (v_decode.io.legal && v_decode.io.read_frs1) { id_ctrl.ren1 := true.B id_ctrl.swap12 := false.B id_ctrl.toint := true.B id_ctrl.typeTagIn := I id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S) } when (v_decode.io.write_frd) { id_ctrl.wen := true.B } })} val ex_reg_valid = RegNext(io.valid, false.B) val ex_reg_inst = RegEnable(io.inst, io.valid) val ex_reg_ctrl = RegEnable(id_ctrl, io.valid) val ex_ra = List.fill(3)(Reg(UInt())) // load/vector response val load_wb = RegNext(io.ll_resp_val) val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val) val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val) val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val) class FPUImpl { // entering gated-clock domain val req_valid = ex_reg_valid \|\| io.cp_req.valid val ex_cp_valid = io.cp_req.fire val mem_cp_valid = RegNext(ex_cp_valid, false.B) val wb_cp_valid = RegNext(mem_cp_valid, false.B) val mem_reg_valid = RegInit(false.B) val killm = (io.killm \|\| io.nack_mem) && !mem_cp_valid // Kill X-stage instruction if M-stage is killed. This prevents it from // speculatively being sent to the div-sqrt unit, which can cause priority // inversion for two back-to-back divides, the first of which is killed. val killx = io.killx \|\| mem_reg_valid && killm mem_reg_valid := ex_reg_valid && !killx \|\| ex_cp_valid val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid) val wb_reg_valid = RegNext(mem_reg_valid && (!killm \|\| mem_cp_valid), false.B) val cp_ctrl = Wire(new FPUCtrlSigs) cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs) io.cp_resp.valid := false.B io.cp_resp.bits.data := 0.U io.cp_resp.bits.exc := DontCare val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl) val mem_ctrl = RegEnable(ex_ctrl, req_valid) val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid) // CoreMonitorBundle to monitor fp register file writes val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare)) frfWriteBundle.foreach { i => i.clock := clock i.reset := reset i.hartid := io.hartid i.timer := io.time(31,0) i.valid := false.B i.wrenx := false.B i.wrenf := false.B i.excpt := false.B } // regfile val regfile = Mem(32, Bits((fLen+1).W)) when (load_wb) { val wdata = recode(load_wb_data, load_wb_typeTag) regfile(load_wb_tag) := wdata assert(consistent(wdata)) if (enableCommitLog) printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata)) if (useDebugROB) DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata)) frfWriteBundle(0).wrdst := load_wb_tag frfWriteBundle(0).wrenf := true.B frfWriteBundle(0).wrdata := ieee(wdata) } val ex_rs = ex_ra.map(a => regfile(a)) when (io.valid) { when (id_ctrl.ren1) { when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) } when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) } } when (id_ctrl.ren2) { when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) } when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) } when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) } } when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) } } val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12)) def fuInput(minT: Option[FType]): FPInput = { val req = Wire(new FPInput) val tag = ex_ctrl.typeTagIn req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs) req.rm := ex_rm req.in1 := unbox(ex_rs(0), tag, minT) req.in2 := unbox(ex_rs(1), tag, minT) req.in3 := unbox(ex_rs(2), tag, minT) req.typ := ex_reg_inst(21,20) req.fmt := ex_reg_inst(26,25) req.fmaCmd := ex_reg_inst(3,2) \| (!ex_ctrl.ren3 && ex_reg_inst(27)) when (ex_cp_valid) { req := io.cp_req.bits when (io.cp_req.bits.swap12) { req.in1 := io.cp_req.bits.in2 req.in2 := io.cp_req.bits.in1 } when (io.cp_req.bits.swap23) { req.in2 := io.cp_req.bits.in3 req.in3 := io.cp_req.bits.in2 } } req } val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S)) sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S sfma.io.in.bits := fuInput(Some(sfma.t)) val fpiu = Module(new FPToInt) fpiu.io.in.valid := req_valid && (ex_ctrl.toint \|\| ex_ctrl.div \|\| ex_ctrl.sqrt \|\| (ex_ctrl.fastpipe && ex_ctrl.wflags)) fpiu.io.in.bits := fuInput(None) io.store_data := fpiu.io.out.bits.store io.toint_data := fpiu.io.out.bits.toint when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){ io.cp_resp.bits.data := fpiu.io.out.bits.toint io.cp_resp.valid := true.B } val ifpu = Module(new IntToFP(cfg.ifpuLatency)) ifpu.io.in.valid := req_valid && ex_ctrl.fromint ifpu.io.in.bits := fpiu.io.in.bits ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) val fpmu = Module(new FPToFP(cfg.fpmuLatency)) fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe fpmu.io.in.bits := fpiu.io.in.bits fpmu.io.lt := fpiu.io.out.bits.lt val divSqrt_wen = WireDefault(false.B) val divSqrt_inFlight = WireDefault(false.B) val divSqrt_waddr = Reg(UInt(5.W)) val divSqrt_cp = Reg(Bool()) val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W)) val divSqrt_wdata = Wire(UInt((fLen+1).W)) val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W)) divSqrt_typeTag := DontCare divSqrt_wdata := DontCare divSqrt_flags := DontCare // writeback arbitration case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult) val pipes = List( Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits), Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits), Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++ (fLen > 32).option({ val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D)) dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D dfma.io.in.bits := fuInput(Some(dfma.t)) Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits) }) ++ (minFLen == 16).option({ val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H)) hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H hfma.io.in.bits := fuInput(Some(hfma.t)) Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits) }) def latencyMask(c: FPUCtrlSigs, offset: Int) = { require(pipes.forall(_.lat >= offset)) pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_\|_) } def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_\|_) val maxLatency = pipes.map(_.lat).max val memLatencyMask = latencyMask(mem_ctrl, 2) class WBInfo extends Bundle { val rd = UInt(5.W) val typeTag = UInt(log2Up(floatTypes.size).W) val cp = Bool() val pipeid = UInt(log2Ceil(pipes.size).W) } val wen = RegInit(0.U((maxLatency-1).W)) val wbInfo = Reg(Vec(maxLatency-1, new WBInfo)) val mem_wen = mem_reg_valid && (mem_ctrl.fma \|\| mem_ctrl.fastpipe \|\| mem_ctrl.fromint) val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR \|\| (wen & latencyMask(ex_ctrl, 0)).orR, req_valid) ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback") for (i <- 0 until maxLatency-2) { when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) } } wen := wen >> 1 when (mem_wen) { when (!killm) { wen := wen >> 1 \| memLatencyMask } for (i <- 0 until maxLatency-1) { when (!write_port_busy && memLatencyMask(i)) { wbInfo(i).cp := mem_cp_valid wbInfo(i).typeTag := mem_ctrl.typeTagOut wbInfo(i).pipeid := pipeid(mem_ctrl) wbInfo(i).rd := mem_reg_inst(11,7) } } } val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd) val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp) val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag) val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag) val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid) when ((!wbInfo(0).cp && wen(0)) \|\| divSqrt_wen) { assert(consistent(wdata)) regfile(waddr) := wdata if (enableCommitLog) { printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata)) } frfWriteBundle(1).wrdst := waddr frfWriteBundle(1).wrenf := true.B frfWriteBundle(1).wrdata := ieee(wdata) } if (useDebugROB) { DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) \|\| divSqrt_wen, waddr + 32.U, ieee(wdata)) } when (wb_cp && (wen(0) \|\| divSqrt_wen)) { io.cp_resp.bits.data := wdata io.cp_resp.valid := true.B } assert(!io.cp_req.valid \|\| pipes.forall(_.lat == pipes.head.lat).B, s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}") // Avoid structural hazards and nacking of external requests // toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight val wb_toint_valid = wb_reg_valid && wb_ctrl.toint val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint) io.fcsr_flags.valid := wb_toint_valid \|\| divSqrt_wen \|\| wen(0) io.fcsr_flags.bits := Mux(wb_toint_valid, wb_toint_exc, 0.U) \| Mux(divSqrt_wen, divSqrt_flags, 0.U) \| Mux(wen(0), wexc, 0.U) val divSqrt_write_port_busy = (mem_ctrl.div \|\| mem_ctrl.sqrt) && wen.orR io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags \|\| mem_reg_valid && mem_ctrl.wflags \|\| wb_reg_valid && wb_ctrl.toint \|\| wen.orR \|\| divSqrt_inFlight) io.nack_mem := (write_port_busy \|\| divSqrt_write_port_busy \|\| divSqrt_inFlight) && !mem_cp_valid io.dec <> id_ctrl def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_\|\|_) io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) \|\| mem_ctrl.div \|\| mem_ctrl.sqrt \|\| mem_ctrl.vec) io.sboard_clr := !wb_cp_valid && (divSqrt_wen \|\| (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U))) io.sboard_clra := waddr ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle") // we don't currently support round-max-magnitude (rm=4) io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) \|\| io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U if (cfg.divSqrt) { val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div \|\| mem_ctrl.sqrt) && !divSqrt_inFlight val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B) when (divSqrt_inValid) { divSqrt_waddr := mem_reg_inst(11,7) divSqrt_cp := mem_cp_valid } ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider") ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div \|\| mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard") ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback") for (t <- floatTypes) { val tag = mem_ctrl.typeTagOut val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) } divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U divSqrt.io.sqrtOp := mem_ctrl.sqrt divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t) divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t) divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight when (divSqrt.io.outValid_div \|\| divSqrt.io.outValid_sqrt) { divSqrt_wen := !divSqrt_killed divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t) divSqrt_flags := divSqrt.io.exceptionFlags divSqrt_typeTag := typeTag(t).U } } when (divSqrt_killed) { divSqrt_inFlight := false.B } } else { when (id_ctrl.div \|\| id_ctrl.sqrt) { io.illegal_rm := true.B } } // gate the clock clock_en_reg := !useClockGating.B \|\| io.keep_clock_enabled \|\| // chicken bit io.valid \|\| // ID stage req_valid \|\| // EX stage mem_reg_valid \|\| mem_cp_valid \|\| // MEM stage wb_reg_valid \|\| wb_cp_valid \|\| // WB stage wen.orR \|\| divSqrt_inFlight \|\| // post-WB stage io.ll_resp_val // load writeback } // leaving gated-clock domain val fpuImpl = withClock (gated_clock) { new FPUImpl } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = property.cover(cond, s"FPU_$label", "Core;;" + desc) } File fNFromRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ object fNFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits) = { val minNormExp = (BigInt(1)<<(expWidth - 1)) + 2 val rawIn = rawFloatFromRecFN(expWidth, sigWidth, in) val isSubnormal = rawIn.sExp < minNormExp.S val denormShiftDist = 1.U - rawIn.sExp(log2Up(sigWidth - 1) - 1, 0) val denormFract = ((rawIn.sig>>1)>>denormShiftDist)(sigWidth - 2, 0) val expOut = Mux(isSubnormal, 0.U, rawIn.sExp(expWidth - 1, 0) - ((BigInt(1)<<(expWidth - 1)) + 1).U ) \| Fill(expWidth, rawIn.isNaN \|\| rawIn.isInf) val fractOut = Mux(isSubnormal, denormFract, Mux(rawIn.isInf, 0.U, rawIn.sig(sigWidth - 2, 0)) ) Cat(rawIn.sign, expOut, fractOut) } } File rawFloatFromRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ /---------------------------------------------------------------------------- \| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be \| set. ----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }	module FPToInt_1( // @[FPU.scala:453:7] input clock, // @[FPU.scala:453:7] input reset, // @[FPU.scala:453:7] input io_in_valid, // @[FPU.scala:461:14] input io_in_bits_ldst, // @[FPU.scala:461:14] input io_in_bits_wen, // @[FPU.scala:461:14] input io_in_bits_ren1, // @[FPU.scala:461:14] input io_in_bits_ren2, // @[FPU.scala:461:14] input io_in_bits_ren3, // @[FPU.scala:461:14] input io_in_bits_swap12, // @[FPU.scala:461:14] input io_in_bits_swap23, // @[FPU.scala:461:14] input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:461:14] input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:461:14] input io_in_bits_fromint, // @[FPU.scala:461:14] input io_in_bits_toint, // @[FPU.scala:461:14] input io_in_bits_fastpipe, // @[FPU.scala:461:14] input io_in_bits_fma, // @[FPU.scala:461:14] input io_in_bits_div, // @[FPU.scala:461:14] input io_in_bits_sqrt, // @[FPU.scala:461:14] input io_in_bits_wflags, // @[FPU.scala:461:14] input io_in_bits_vec, // @[FPU.scala:461:14] input [2:0] io_in_bits_rm, // @[FPU.scala:461:14] input [1:0] io_in_bits_typ, // @[FPU.scala:461:14] input [64:0] io_in_bits_in1, // @[FPU.scala:461:14] input [64:0] io_in_bits_in2, // @[FPU.scala:461:14] output [2:0] io_out_bits_in_rm, // @[FPU.scala:461:14] output [64:0] io_out_bits_in_in1, // @[FPU.scala:461:14] output [64:0] io_out_bits_in_in2 // @[FPU.scala:461:14] ); wire [2:0] _narrow_io_intExceptionFlags; // @[FPU.scala:508:30] wire [63:0] _conv_io_out; // @[FPU.scala:498:24] wire [2:0] _conv_io_intExceptionFlags; // @[FPU.scala:498:24] wire _dcmp_io_lt; // @[FPU.scala:469:20] wire _dcmp_io_eq; // @[FPU.scala:469:20] wire [4:0] _dcmp_io_exceptionFlags; // @[FPU.scala:469:20] wire io_in_valid_0 = io_in_valid; // @[FPU.scala:453:7] wire io_in_bits_ldst_0 = io_in_bits_ldst; // @[FPU.scala:453:7] wire io_in_bits_wen_0 = io_in_bits_wen; // @[FPU.scala:453:7] wire io_in_bits_ren1_0 = io_in_bits_ren1; // @[FPU.scala:453:7] wire io_in_bits_ren2_0 = io_in_bits_ren2; // @[FPU.scala:453:7] wire io_in_bits_ren3_0 = io_in_bits_ren3; // @[FPU.scala:453:7] wire io_in_bits_swap12_0 = io_in_bits_swap12; // @[FPU.scala:453:7] wire io_in_bits_swap23_0 = io_in_bits_swap23; // @[FPU.scala:453:7] wire [1:0] io_in_bits_typeTagIn_0 = io_in_bits_typeTagIn; // @[FPU.scala:453:7] wire [1:0] io_in_bits_typeTagOut_0 = io_in_bits_typeTagOut; // @[FPU.scala:453:7] wire io_in_bits_fromint_0 = io_in_bits_fromint; // @[FPU.scala:453:7] wire io_in_bits_toint_0 = io_in_bits_toint; // @[FPU.scala:453:7] wire io_in_bits_fastpipe_0 = io_in_bits_fastpipe; // @[FPU.scala:453:7] wire io_in_bits_fma_0 = io_in_bits_fma; // @[FPU.scala:453:7] wire io_in_bits_div_0 = io_in_bits_div; // @[FPU.scala:453:7] wire io_in_bits_sqrt_0 = io_in_bits_sqrt; // @[FPU.scala:453:7] wire io_in_bits_wflags_0 = io_in_bits_wflags; // @[FPU.scala:453:7] wire io_in_bits_vec_0 = io_in_bits_vec; // @[FPU.scala:453:7] wire [2:0] io_in_bits_rm_0 = io_in_bits_rm; // @[FPU.scala:453:7] wire [1:0] io_in_bits_typ_0 = io_in_bits_typ; // @[FPU.scala:453:7] wire [64:0] io_in_bits_in1_0 = io_in_bits_in1; // @[FPU.scala:453:7] wire [64:0] io_in_bits_in2_0 = io_in_bits_in2; // @[FPU.scala:453:7] wire [1:0] io_in_bits_fmaCmd = 2'h0; // @[FPU.scala:453:7] wire [1:0] io_in_bits_fmt = 2'h0; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_fmaCmd = 2'h0; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_fmt = 2'h0; // @[FPU.scala:453:7] wire [64:0] io_in_bits_in3 = 65'h0; // @[FPU.scala:453:7, :524:53] wire [64:0] io_out_bits_in_in3 = 65'h0; // @[FPU.scala:453:7, :524:53] wire _intType_T = 1'h0; // @[FPU.scala:479:35] wire _io_out_bits_lt_T_5; // @[FPU.scala:524:32] wire [63:0] _io_out_bits_store_T_16; // @[package.scala:39:76] wire [63:0] _io_out_bits_toint_T_6; // @[package.scala:39:76] wire io_out_bits_in_ldst; // @[FPU.scala:453:7] wire io_out_bits_in_wen; // @[FPU.scala:453:7] wire io_out_bits_in_ren1; // @[FPU.scala:453:7] wire io_out_bits_in_ren2; // @[FPU.scala:453:7] wire io_out_bits_in_ren3; // @[FPU.scala:453:7] wire io_out_bits_in_swap12; // @[FPU.scala:453:7] wire io_out_bits_in_swap23; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_typeTagIn; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_typeTagOut; // @[FPU.scala:453:7] wire io_out_bits_in_fromint; // @[FPU.scala:453:7] wire io_out_bits_in_toint; // @[FPU.scala:453:7] wire io_out_bits_in_fastpipe; // @[FPU.scala:453:7] wire io_out_bits_in_fma; // @[FPU.scala:453:7] wire io_out_bits_in_div; // @[FPU.scala:453:7] wire io_out_bits_in_sqrt; // @[FPU.scala:453:7] wire io_out_bits_in_wflags; // @[FPU.scala:453:7] wire io_out_bits_in_vec; // @[FPU.scala:453:7] wire [2:0] io_out_bits_in_rm_0; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_typ; // @[FPU.scala:453:7] wire [64:0] io_out_bits_in_in1_0; // @[FPU.scala:453:7] wire [64:0] io_out_bits_in_in2_0; // @[FPU.scala:453:7] wire io_out_bits_lt; // @[FPU.scala:453:7] wire [63:0] io_out_bits_store; // @[FPU.scala:453:7] wire [63:0] io_out_bits_toint; // @[FPU.scala:453:7] wire [4:0] io_out_bits_exc; // @[FPU.scala:453:7] wire io_out_valid; // @[FPU.scala:453:7] reg in_ldst; // @[FPU.scala:466:21] assign io_out_bits_in_ldst = in_ldst; // @[FPU.scala:453:7, :466:21] reg in_wen; // @[FPU.scala:466:21] assign io_out_bits_in_wen = in_wen; // @[FPU.scala:453:7, :466:21] reg in_ren1; // @[FPU.scala:466:21] assign io_out_bits_in_ren1 = in_ren1; // @[FPU.scala:453:7, :466:21] reg in_ren2; // @[FPU.scala:466:21] assign io_out_bits_in_ren2 = in_ren2; // @[FPU.scala:453:7, :466:21] reg in_ren3; // @[FPU.scala:466:21] assign io_out_bits_in_ren3 = in_ren3; // @[FPU.scala:453:7, :466:21] reg in_swap12; // @[FPU.scala:466:21] assign io_out_bits_in_swap12 = in_swap12; // @[FPU.scala:453:7, :466:21] reg in_swap23; // @[FPU.scala:466:21] assign io_out_bits_in_swap23 = in_swap23; // @[FPU.scala:453:7, :466:21] reg [1:0] in_typeTagIn; // @[FPU.scala:466:21] assign io_out_bits_in_typeTagIn = in_typeTagIn; // @[FPU.scala:453:7, :466:21] reg [1:0] in_typeTagOut; // @[FPU.scala:466:21] assign io_out_bits_in_typeTagOut = in_typeTagOut; // @[FPU.scala:453:7, :466:21] wire [1:0] _toint_ieee_truncIdx_T = in_typeTagOut; // @[package.scala:38:21] wire [1:0] _io_out_bits_store_truncIdx_T = in_typeTagOut; // @[package.scala:38:21] wire [1:0] _classify_out_truncIdx_T = in_typeTagOut; // @[package.scala:38:21] reg in_fromint; // @[FPU.scala:466:21] assign io_out_bits_in_fromint = in_fromint; // @[FPU.scala:453:7, :466:21] reg in_toint; // @[FPU.scala:466:21] assign io_out_bits_in_toint = in_toint; // @[FPU.scala:453:7, :466:21] reg in_fastpipe; // @[FPU.scala:466:21] assign io_out_bits_in_fastpipe = in_fastpipe; // @[FPU.scala:453:7, :466:21] reg in_fma; // @[FPU.scala:466:21] assign io_out_bits_in_fma = in_fma; // @[FPU.scala:453:7, :466:21] reg in_div; // @[FPU.scala:466:21] assign io_out_bits_in_div = in_div; // @[FPU.scala:453:7, :466:21] reg in_sqrt; // @[FPU.scala:466:21] assign io_out_bits_in_sqrt = in_sqrt; // @[FPU.scala:453:7, :466:21] reg in_wflags; // @[FPU.scala:466:21] assign io_out_bits_in_wflags = in_wflags; // @[FPU.scala:453:7, :466:21] reg in_vec; // @[FPU.scala:466:21] assign io_out_bits_in_vec = in_vec; // @[FPU.scala:453:7, :466:21] reg [2:0] in_rm; // @[FPU.scala:466:21] assign io_out_bits_in_rm_0 = in_rm; // @[FPU.scala:453:7, :466:21] reg [1:0] in_typ; // @[FPU.scala:466:21] assign io_out_bits_in_typ = in_typ; // @[FPU.scala:453:7, :466:21] reg [64:0] in_in1; // @[FPU.scala:466:21] assign io_out_bits_in_in1_0 = in_in1; // @[FPU.scala:453:7, :466:21] wire [64:0] _io_out_bits_lt_T = in_in1; // @[FPU.scala:466:21, :524:46] reg [64:0] in_in2; // @[FPU.scala:466:21] assign io_out_bits_in_in2_0 = in_in2; // @[FPU.scala:453:7, :466:21] wire [64:0] _io_out_bits_lt_T_2 = in_in2; // @[FPU.scala:466:21, :524:72] reg valid; // @[FPU.scala:467:22] assign io_out_valid = valid; // @[FPU.scala:453:7, :467:22] wire _dcmp_io_signaling_T = in_rm[1]; // @[FPU.scala:466:21, :472:30] wire _dcmp_io_signaling_T_1 = ~_dcmp_io_signaling_T; // @[FPU.scala:472:{24,30}] wire [11:0] toint_ieee_unrecoded_rawIn_exp = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] toint_ieee_unrecoded_rawIn_exp_1 = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] io_out_bits_store_unrecoded_rawIn_exp = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] io_out_bits_store_unrecoded_rawIn_exp_1 = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] classify_out_expIn = in_in1[63:52]; // @[FPU.scala:276:18, :466:21] wire [2:0] _toint_ieee_unrecoded_rawIn_isZero_T = toint_ieee_unrecoded_rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_unrecoded_rawIn_isZero = _toint_ieee_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_unrecoded_rawIn_isZero_0 = toint_ieee_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_unrecoded_rawIn_isSpecial_T = toint_ieee_unrecoded_rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_unrecoded_rawIn_isSpecial = &_toint_ieee_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _toint_ieee_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _toint_ieee_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] toint_ieee_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] toint_ieee_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T = toint_ieee_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_unrecoded_rawIn_out_isInf_T = toint_ieee_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_unrecoded_rawIn_out_isNaN_T_1 = toint_ieee_unrecoded_rawIn_isSpecial & _toint_ieee_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_unrecoded_rawIn_isNaN = _toint_ieee_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_1 = ~_toint_ieee_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_unrecoded_rawIn_out_isInf_T_2 = toint_ieee_unrecoded_rawIn_isSpecial & _toint_ieee_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_unrecoded_rawIn_isInf = _toint_ieee_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_unrecoded_rawIn_out_sign_T = in_in1[64]; // @[FPU.scala:466:21] wire _toint_ieee_unrecoded_rawIn_out_sign_T_1 = in_in1[64]; // @[FPU.scala:466:21] wire _io_out_bits_store_unrecoded_rawIn_out_sign_T = in_in1[64]; // @[FPU.scala:466:21] wire _io_out_bits_store_unrecoded_rawIn_out_sign_T_1 = in_in1[64]; // @[FPU.scala:466:21] wire classify_out_sign = in_in1[64]; // @[FPU.scala:274:17, :466:21] wire classify_out_sign_2 = in_in1[64]; // @[FPU.scala:253:17, :466:21] wire _excSign_T = in_in1[64]; // @[FPU.scala:466:21, :513:31] assign toint_ieee_unrecoded_rawIn_sign = _toint_ieee_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_unrecoded_rawIn_out_sExp_T = {1'h0, toint_ieee_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_unrecoded_rawIn_sExp = _toint_ieee_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_unrecoded_rawIn_out_sig_T = ~toint_ieee_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_unrecoded_rawIn_out_sig_T_1 = {1'h0, _toint_ieee_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _toint_ieee_unrecoded_rawIn_out_sig_T_2 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] _toint_ieee_unrecoded_rawIn_out_sig_T_6 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_2 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_6 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] classify_out_fractIn = in_in1[51:0]; // @[FPU.scala:275:20, :466:21] assign _toint_ieee_unrecoded_rawIn_out_sig_T_3 = {_toint_ieee_unrecoded_rawIn_out_sig_T_1, _toint_ieee_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_unrecoded_rawIn_sig = _toint_ieee_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_unrecoded_isSubnormal = $signed(toint_ieee_unrecoded_rawIn_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_unrecoded_denormShiftDist_T = toint_ieee_unrecoded_rawIn_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _toint_ieee_unrecoded_denormShiftDist_T_1 = 7'h1 - {1'h0, _toint_ieee_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] toint_ieee_unrecoded_denormShiftDist = _toint_ieee_unrecoded_denormShiftDist_T_1[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _toint_ieee_unrecoded_denormFract_T = toint_ieee_unrecoded_rawIn_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _toint_ieee_unrecoded_denormFract_T_1 = _toint_ieee_unrecoded_denormFract_T >> toint_ieee_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] toint_ieee_unrecoded_denormFract = _toint_ieee_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _toint_ieee_unrecoded_expOut_T = toint_ieee_unrecoded_rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _toint_ieee_unrecoded_expOut_T_1 = {1'h0, _toint_ieee_unrecoded_expOut_T} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _toint_ieee_unrecoded_expOut_T_2 = _toint_ieee_unrecoded_expOut_T_1[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _toint_ieee_unrecoded_expOut_T_3 = toint_ieee_unrecoded_isSubnormal ? 11'h0 : _toint_ieee_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_unrecoded_expOut_T_4 = toint_ieee_unrecoded_rawIn_isNaN \| toint_ieee_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_unrecoded_expOut_T_5 = {11{_toint_ieee_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] toint_ieee_unrecoded_expOut = _toint_ieee_unrecoded_expOut_T_3 \| _toint_ieee_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _toint_ieee_unrecoded_fractOut_T = toint_ieee_unrecoded_rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _toint_ieee_unrecoded_fractOut_T_1 = toint_ieee_unrecoded_rawIn_isInf ? 52'h0 : _toint_ieee_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] toint_ieee_unrecoded_fractOut = toint_ieee_unrecoded_isSubnormal ? toint_ieee_unrecoded_denormFract : _toint_ieee_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] toint_ieee_unrecoded_hi = {toint_ieee_unrecoded_rawIn_sign, toint_ieee_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] toint_ieee_unrecoded = {toint_ieee_unrecoded_hi, toint_ieee_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire _toint_ieee_prevRecoded_T = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _toint_ieee_prevRecoded_T_3 = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _io_out_bits_store_prevRecoded_T = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _io_out_bits_store_prevRecoded_T_3 = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _toint_ieee_prevRecoded_T_1 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire _toint_ieee_prevRecoded_T_4 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire _io_out_bits_store_prevRecoded_T_1 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire _io_out_bits_store_prevRecoded_T_4 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire [30:0] _toint_ieee_prevRecoded_T_2 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [30:0] _toint_ieee_prevRecoded_T_5 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [30:0] _io_out_bits_store_prevRecoded_T_2 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [30:0] _io_out_bits_store_prevRecoded_T_5 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [1:0] toint_ieee_prevRecoded_hi = {_toint_ieee_prevRecoded_T, _toint_ieee_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] toint_ieee_prevRecoded = {toint_ieee_prevRecoded_hi, _toint_ieee_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [8:0] toint_ieee_prevUnrecoded_rawIn_exp = toint_ieee_prevRecoded[31:23]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_rawIn_isZero_T = toint_ieee_prevUnrecoded_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_rawIn_isZero = _toint_ieee_prevUnrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_rawIn_isZero_0 = toint_ieee_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_rawIn_isSpecial_T = toint_ieee_prevUnrecoded_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_rawIn_isSpecial = &_toint_ieee_prevUnrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _toint_ieee_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _toint_ieee_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] toint_ieee_prevUnrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_rawIn_out_isNaN_T = toint_ieee_prevUnrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_rawIn_out_isInf_T = toint_ieee_prevUnrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_rawIn_out_isNaN_T_1 = toint_ieee_prevUnrecoded_rawIn_isSpecial & _toint_ieee_prevUnrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_rawIn_isNaN = _toint_ieee_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_rawIn_out_isInf_T_1 = ~_toint_ieee_prevUnrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_rawIn_out_isInf_T_2 = toint_ieee_prevUnrecoded_rawIn_isSpecial & _toint_ieee_prevUnrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_rawIn_isInf = _toint_ieee_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_rawIn_out_sign_T = toint_ieee_prevRecoded[32]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_rawIn_sign = _toint_ieee_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_rawIn_out_sExp_T = {1'h0, toint_ieee_prevUnrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_rawIn_sExp = _toint_ieee_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_rawIn_out_sig_T = ~toint_ieee_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_rawIn_out_sig_T_1 = {1'h0, _toint_ieee_prevUnrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _toint_ieee_prevUnrecoded_rawIn_out_sig_T_2 = toint_ieee_prevRecoded[22:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_rawIn_out_sig_T_3 = {_toint_ieee_prevUnrecoded_rawIn_out_sig_T_1, _toint_ieee_prevUnrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_rawIn_sig = _toint_ieee_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_isSubnormal = $signed(toint_ieee_prevUnrecoded_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_denormShiftDist_T = toint_ieee_prevUnrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_denormShiftDist_T_1 = 6'h1 - {1'h0, _toint_ieee_prevUnrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] toint_ieee_prevUnrecoded_denormShiftDist = _toint_ieee_prevUnrecoded_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _toint_ieee_prevUnrecoded_denormFract_T = toint_ieee_prevUnrecoded_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _toint_ieee_prevUnrecoded_denormFract_T_1 = _toint_ieee_prevUnrecoded_denormFract_T >> toint_ieee_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] toint_ieee_prevUnrecoded_denormFract = _toint_ieee_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _toint_ieee_prevUnrecoded_expOut_T = toint_ieee_prevUnrecoded_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _toint_ieee_prevUnrecoded_expOut_T_1 = {1'h0, _toint_ieee_prevUnrecoded_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _toint_ieee_prevUnrecoded_expOut_T_2 = _toint_ieee_prevUnrecoded_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _toint_ieee_prevUnrecoded_expOut_T_3 = toint_ieee_prevUnrecoded_isSubnormal ? 8'h0 : _toint_ieee_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_expOut_T_4 = toint_ieee_prevUnrecoded_rawIn_isNaN \| toint_ieee_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _toint_ieee_prevUnrecoded_expOut_T_5 = {8{_toint_ieee_prevUnrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] toint_ieee_prevUnrecoded_expOut = _toint_ieee_prevUnrecoded_expOut_T_3 \| _toint_ieee_prevUnrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _toint_ieee_prevUnrecoded_fractOut_T = toint_ieee_prevUnrecoded_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _toint_ieee_prevUnrecoded_fractOut_T_1 = toint_ieee_prevUnrecoded_rawIn_isInf ? 23'h0 : _toint_ieee_prevUnrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] toint_ieee_prevUnrecoded_fractOut = toint_ieee_prevUnrecoded_isSubnormal ? toint_ieee_prevUnrecoded_denormFract : _toint_ieee_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] toint_ieee_prevUnrecoded_hi = {toint_ieee_prevUnrecoded_rawIn_sign, toint_ieee_prevUnrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] toint_ieee_prevUnrecoded = {toint_ieee_prevUnrecoded_hi, toint_ieee_prevUnrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire [31:0] _toint_ieee_T = toint_ieee_unrecoded[63:32]; // @[FPU.scala:446:21] wire [2:0] _toint_ieee_T_1 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] _toint_ieee_T_9 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] _io_out_bits_store_T_1 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] _io_out_bits_store_T_9 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] classify_out_code_1 = in_in1[63:61]; // @[FPU.scala:249:25, :254:17, :466:21] wire [2:0] _excSign_T_1 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire _toint_ieee_T_2 = &_toint_ieee_T_1; // @[FPU.scala:249:{25,56}] wire [31:0] _toint_ieee_T_3 = toint_ieee_unrecoded[31:0]; // @[FPU.scala:446:81] wire [31:0] _toint_ieee_T_4 = _toint_ieee_T_2 ? toint_ieee_prevUnrecoded : _toint_ieee_T_3; // @[FPU.scala:249:56, :446:{44,81}] wire [63:0] _toint_ieee_T_5 = {_toint_ieee_T, _toint_ieee_T_4}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _toint_ieee_T_6 = _toint_ieee_T_5[31:0]; // @[FPU.scala:446:10, :476:109] wire [63:0] _toint_ieee_T_7 = {2{_toint_ieee_T_6}}; // @[FPU.scala:476:{63,109}] wire [2:0] _toint_ieee_unrecoded_rawIn_isZero_T_1 = toint_ieee_unrecoded_rawIn_exp_1[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_unrecoded_rawIn_isZero_1 = _toint_ieee_unrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_unrecoded_rawIn_1_isZero = toint_ieee_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_unrecoded_rawIn_isSpecial_T_1 = toint_ieee_unrecoded_rawIn_exp_1[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_unrecoded_rawIn_isSpecial_1 = &_toint_ieee_unrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire [12:0] _toint_ieee_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _toint_ieee_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_unrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] toint_ieee_unrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] toint_ieee_unrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_2 = toint_ieee_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_3 = toint_ieee_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_unrecoded_rawIn_out_isNaN_T_3 = toint_ieee_unrecoded_rawIn_isSpecial_1 & _toint_ieee_unrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_unrecoded_rawIn_1_isNaN = _toint_ieee_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_4 = ~_toint_ieee_unrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_unrecoded_rawIn_out_isInf_T_5 = toint_ieee_unrecoded_rawIn_isSpecial_1 & _toint_ieee_unrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_unrecoded_rawIn_1_isInf = _toint_ieee_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign toint_ieee_unrecoded_rawIn_1_sign = _toint_ieee_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_unrecoded_rawIn_out_sExp_T_1 = {1'h0, toint_ieee_unrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_unrecoded_rawIn_1_sExp = _toint_ieee_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_unrecoded_rawIn_out_sig_T_4 = ~toint_ieee_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_unrecoded_rawIn_out_sig_T_5 = {1'h0, _toint_ieee_unrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] assign _toint_ieee_unrecoded_rawIn_out_sig_T_7 = {_toint_ieee_unrecoded_rawIn_out_sig_T_5, _toint_ieee_unrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_unrecoded_rawIn_1_sig = _toint_ieee_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_unrecoded_isSubnormal_1 = $signed(toint_ieee_unrecoded_rawIn_1_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_unrecoded_denormShiftDist_T_2 = toint_ieee_unrecoded_rawIn_1_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _toint_ieee_unrecoded_denormShiftDist_T_3 = 7'h1 - {1'h0, _toint_ieee_unrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] toint_ieee_unrecoded_denormShiftDist_1 = _toint_ieee_unrecoded_denormShiftDist_T_3[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _toint_ieee_unrecoded_denormFract_T_2 = toint_ieee_unrecoded_rawIn_1_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _toint_ieee_unrecoded_denormFract_T_3 = _toint_ieee_unrecoded_denormFract_T_2 >> toint_ieee_unrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] toint_ieee_unrecoded_denormFract_1 = _toint_ieee_unrecoded_denormFract_T_3[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _toint_ieee_unrecoded_expOut_T_6 = toint_ieee_unrecoded_rawIn_1_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _toint_ieee_unrecoded_expOut_T_7 = {1'h0, _toint_ieee_unrecoded_expOut_T_6} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _toint_ieee_unrecoded_expOut_T_8 = _toint_ieee_unrecoded_expOut_T_7[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _toint_ieee_unrecoded_expOut_T_9 = toint_ieee_unrecoded_isSubnormal_1 ? 11'h0 : _toint_ieee_unrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_unrecoded_expOut_T_10 = toint_ieee_unrecoded_rawIn_1_isNaN \| toint_ieee_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_unrecoded_expOut_T_11 = {11{_toint_ieee_unrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] toint_ieee_unrecoded_expOut_1 = _toint_ieee_unrecoded_expOut_T_9 \| _toint_ieee_unrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _toint_ieee_unrecoded_fractOut_T_2 = toint_ieee_unrecoded_rawIn_1_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _toint_ieee_unrecoded_fractOut_T_3 = toint_ieee_unrecoded_rawIn_1_isInf ? 52'h0 : _toint_ieee_unrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] toint_ieee_unrecoded_fractOut_1 = toint_ieee_unrecoded_isSubnormal_1 ? toint_ieee_unrecoded_denormFract_1 : _toint_ieee_unrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] toint_ieee_unrecoded_hi_1 = {toint_ieee_unrecoded_rawIn_1_sign, toint_ieee_unrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] toint_ieee_unrecoded_1 = {toint_ieee_unrecoded_hi_1, toint_ieee_unrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] toint_ieee_prevRecoded_hi_1 = {_toint_ieee_prevRecoded_T_3, _toint_ieee_prevRecoded_T_4}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] toint_ieee_prevRecoded_1 = {toint_ieee_prevRecoded_hi_1, _toint_ieee_prevRecoded_T_5}; // @[FPU.scala:441:28, :444:10] wire [8:0] toint_ieee_prevUnrecoded_rawIn_exp_1 = toint_ieee_prevRecoded_1[31:23]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_rawIn_isZero_T_1 = toint_ieee_prevUnrecoded_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_rawIn_isZero_1 = _toint_ieee_prevUnrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_rawIn_1_isZero = toint_ieee_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_rawIn_isSpecial_T_1 = toint_ieee_prevUnrecoded_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_rawIn_isSpecial_1 = &_toint_ieee_prevUnrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _toint_ieee_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _toint_ieee_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] toint_ieee_prevUnrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_rawIn_out_isNaN_T_2 = toint_ieee_prevUnrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_rawIn_out_isInf_T_3 = toint_ieee_prevUnrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_rawIn_out_isNaN_T_3 = toint_ieee_prevUnrecoded_rawIn_isSpecial_1 & _toint_ieee_prevUnrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_rawIn_1_isNaN = _toint_ieee_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_rawIn_out_isInf_T_4 = ~_toint_ieee_prevUnrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_rawIn_out_isInf_T_5 = toint_ieee_prevUnrecoded_rawIn_isSpecial_1 & _toint_ieee_prevUnrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_rawIn_1_isInf = _toint_ieee_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_rawIn_out_sign_T_1 = toint_ieee_prevRecoded_1[32]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_rawIn_1_sign = _toint_ieee_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_rawIn_out_sExp_T_1 = {1'h0, toint_ieee_prevUnrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_rawIn_1_sExp = _toint_ieee_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_rawIn_out_sig_T_4 = ~toint_ieee_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_rawIn_out_sig_T_5 = {1'h0, _toint_ieee_prevUnrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _toint_ieee_prevUnrecoded_rawIn_out_sig_T_6 = toint_ieee_prevRecoded_1[22:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_rawIn_out_sig_T_7 = {_toint_ieee_prevUnrecoded_rawIn_out_sig_T_5, _toint_ieee_prevUnrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_rawIn_1_sig = _toint_ieee_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_isSubnormal_1 = $signed(toint_ieee_prevUnrecoded_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_denormShiftDist_T_2 = toint_ieee_prevUnrecoded_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_denormShiftDist_T_3 = 6'h1 - {1'h0, _toint_ieee_prevUnrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] toint_ieee_prevUnrecoded_denormShiftDist_1 = _toint_ieee_prevUnrecoded_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _toint_ieee_prevUnrecoded_denormFract_T_2 = toint_ieee_prevUnrecoded_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _toint_ieee_prevUnrecoded_denormFract_T_3 = _toint_ieee_prevUnrecoded_denormFract_T_2 >> toint_ieee_prevUnrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] toint_ieee_prevUnrecoded_denormFract_1 = _toint_ieee_prevUnrecoded_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _toint_ieee_prevUnrecoded_expOut_T_6 = toint_ieee_prevUnrecoded_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _toint_ieee_prevUnrecoded_expOut_T_7 = {1'h0, _toint_ieee_prevUnrecoded_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _toint_ieee_prevUnrecoded_expOut_T_8 = _toint_ieee_prevUnrecoded_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _toint_ieee_prevUnrecoded_expOut_T_9 = toint_ieee_prevUnrecoded_isSubnormal_1 ? 8'h0 : _toint_ieee_prevUnrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_expOut_T_10 = toint_ieee_prevUnrecoded_rawIn_1_isNaN \| toint_ieee_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _toint_ieee_prevUnrecoded_expOut_T_11 = {8{_toint_ieee_prevUnrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] toint_ieee_prevUnrecoded_expOut_1 = _toint_ieee_prevUnrecoded_expOut_T_9 \| _toint_ieee_prevUnrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _toint_ieee_prevUnrecoded_fractOut_T_2 = toint_ieee_prevUnrecoded_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _toint_ieee_prevUnrecoded_fractOut_T_3 = toint_ieee_prevUnrecoded_rawIn_1_isInf ? 23'h0 : _toint_ieee_prevUnrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] toint_ieee_prevUnrecoded_fractOut_1 = toint_ieee_prevUnrecoded_isSubnormal_1 ? toint_ieee_prevUnrecoded_denormFract_1 : _toint_ieee_prevUnrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] toint_ieee_prevUnrecoded_hi_1 = {toint_ieee_prevUnrecoded_rawIn_1_sign, toint_ieee_prevUnrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] toint_ieee_prevUnrecoded_1 = {toint_ieee_prevUnrecoded_hi_1, toint_ieee_prevUnrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire [31:0] _toint_ieee_T_8 = toint_ieee_unrecoded_1[63:32]; // @[FPU.scala:446:21] wire _toint_ieee_T_10 = &_toint_ieee_T_9; // @[FPU.scala:249:{25,56}] wire [31:0] _toint_ieee_T_11 = toint_ieee_unrecoded_1[31:0]; // @[FPU.scala:446:81] wire [31:0] _toint_ieee_T_12 = _toint_ieee_T_10 ? toint_ieee_prevUnrecoded_1 : _toint_ieee_T_11; // @[FPU.scala:249:56, :446:{44,81}] wire [63:0] _toint_ieee_T_13 = {_toint_ieee_T_8, _toint_ieee_T_12}; // @[FPU.scala:446:{10,21,44}] wire [63:0] _toint_ieee_T_14 = _toint_ieee_T_13; // @[FPU.scala:446:10, :476:109] wire toint_ieee_truncIdx = _toint_ieee_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _toint_ieee_T_15 = toint_ieee_truncIdx; // @[package.scala:38:47, :39:86] wire [63:0] toint_ieee = _toint_ieee_T_15 ? _toint_ieee_T_14 : _toint_ieee_T_7; // @[package.scala:39:{76,86}] wire [63:0] toint; // @[FPU.scala:478:26] wire [63:0] _io_out_bits_toint_T_4 = toint; // @[FPU.scala:478:26, :481:59] wire intType; // @[FPU.scala:479:28] wire _io_out_bits_toint_T_5 = intType; // @[package.scala:39:86] wire [2:0] _io_out_bits_store_unrecoded_rawIn_isZero_T = io_out_bits_store_unrecoded_rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_unrecoded_rawIn_isZero = _io_out_bits_store_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_unrecoded_rawIn_isZero_0 = io_out_bits_store_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_unrecoded_rawIn_isSpecial_T = io_out_bits_store_unrecoded_rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_unrecoded_rawIn_isSpecial = &_io_out_bits_store_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire [12:0] _io_out_bits_store_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] io_out_bits_store_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] io_out_bits_store_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T = io_out_bits_store_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T = io_out_bits_store_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1 = io_out_bits_store_unrecoded_rawIn_isSpecial & _io_out_bits_store_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_unrecoded_rawIn_isNaN = _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1 = ~_io_out_bits_store_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2 = io_out_bits_store_unrecoded_rawIn_isSpecial & _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_unrecoded_rawIn_isInf = _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign io_out_bits_store_unrecoded_rawIn_sign = _io_out_bits_store_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_unrecoded_rawIn_out_sExp_T = {1'h0, io_out_bits_store_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_unrecoded_rawIn_sExp = _io_out_bits_store_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_unrecoded_rawIn_out_sig_T = ~io_out_bits_store_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_1 = {1'h0, _io_out_bits_store_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] assign _io_out_bits_store_unrecoded_rawIn_out_sig_T_3 = {_io_out_bits_store_unrecoded_rawIn_out_sig_T_1, _io_out_bits_store_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_unrecoded_rawIn_sig = _io_out_bits_store_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_unrecoded_isSubnormal = $signed(io_out_bits_store_unrecoded_rawIn_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_unrecoded_denormShiftDist_T = io_out_bits_store_unrecoded_rawIn_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _io_out_bits_store_unrecoded_denormShiftDist_T_1 = 7'h1 - {1'h0, _io_out_bits_store_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] io_out_bits_store_unrecoded_denormShiftDist = _io_out_bits_store_unrecoded_denormShiftDist_T_1[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T = io_out_bits_store_unrecoded_rawIn_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_1 = _io_out_bits_store_unrecoded_denormFract_T >> io_out_bits_store_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] io_out_bits_store_unrecoded_denormFract = _io_out_bits_store_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T = io_out_bits_store_unrecoded_rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _io_out_bits_store_unrecoded_expOut_T_1 = {1'h0, _io_out_bits_store_unrecoded_expOut_T} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_2 = _io_out_bits_store_unrecoded_expOut_T_1[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_3 = io_out_bits_store_unrecoded_isSubnormal ? 11'h0 : _io_out_bits_store_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_unrecoded_expOut_T_4 = io_out_bits_store_unrecoded_rawIn_isNaN \| io_out_bits_store_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_5 = {11{_io_out_bits_store_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] io_out_bits_store_unrecoded_expOut = _io_out_bits_store_unrecoded_expOut_T_3 \| _io_out_bits_store_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T = io_out_bits_store_unrecoded_rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_1 = io_out_bits_store_unrecoded_rawIn_isInf ? 52'h0 : _io_out_bits_store_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] io_out_bits_store_unrecoded_fractOut = io_out_bits_store_unrecoded_isSubnormal ? io_out_bits_store_unrecoded_denormFract : _io_out_bits_store_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] io_out_bits_store_unrecoded_hi = {io_out_bits_store_unrecoded_rawIn_sign, io_out_bits_store_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] io_out_bits_store_unrecoded = {io_out_bits_store_unrecoded_hi, io_out_bits_store_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] io_out_bits_store_prevRecoded_hi = {_io_out_bits_store_prevRecoded_T, _io_out_bits_store_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] io_out_bits_store_prevRecoded = {io_out_bits_store_prevRecoded_hi, _io_out_bits_store_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [8:0] io_out_bits_store_prevUnrecoded_rawIn_exp = io_out_bits_store_prevRecoded[31:23]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_rawIn_isZero_T = io_out_bits_store_prevUnrecoded_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_rawIn_isZero = _io_out_bits_store_prevUnrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_rawIn_isZero_0 = io_out_bits_store_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_rawIn_isSpecial_T = io_out_bits_store_prevUnrecoded_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_rawIn_isSpecial = &_io_out_bits_store_prevUnrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_bits_store_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_bits_store_prevUnrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_rawIn_out_isNaN_T = io_out_bits_store_prevUnrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T = io_out_bits_store_prevUnrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_rawIn_out_isNaN_T_1 = io_out_bits_store_prevUnrecoded_rawIn_isSpecial & _io_out_bits_store_prevUnrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_rawIn_isNaN = _io_out_bits_store_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_1 = ~_io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_2 = io_out_bits_store_prevUnrecoded_rawIn_isSpecial & _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_rawIn_isInf = _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_rawIn_out_sign_T = io_out_bits_store_prevRecoded[32]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_rawIn_sign = _io_out_bits_store_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_rawIn_out_sExp_T = {1'h0, io_out_bits_store_prevUnrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_rawIn_sExp = _io_out_bits_store_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T = ~io_out_bits_store_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_1 = {1'h0, _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_2 = io_out_bits_store_prevRecoded[22:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_3 = {_io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_1, _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_rawIn_sig = _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_isSubnormal = $signed(io_out_bits_store_prevUnrecoded_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_denormShiftDist_T = io_out_bits_store_prevUnrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_denormShiftDist_T_1 = 6'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_bits_store_prevUnrecoded_denormShiftDist = _io_out_bits_store_prevUnrecoded_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_bits_store_prevUnrecoded_denormFract_T = io_out_bits_store_prevUnrecoded_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_bits_store_prevUnrecoded_denormFract_T_1 = _io_out_bits_store_prevUnrecoded_denormFract_T >> io_out_bits_store_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_bits_store_prevUnrecoded_denormFract = _io_out_bits_store_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_bits_store_prevUnrecoded_expOut_T = io_out_bits_store_prevUnrecoded_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_bits_store_prevUnrecoded_expOut_T_1 = {1'h0, _io_out_bits_store_prevUnrecoded_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_bits_store_prevUnrecoded_expOut_T_2 = _io_out_bits_store_prevUnrecoded_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_bits_store_prevUnrecoded_expOut_T_3 = io_out_bits_store_prevUnrecoded_isSubnormal ? 8'h0 : _io_out_bits_store_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_expOut_T_4 = io_out_bits_store_prevUnrecoded_rawIn_isNaN \| io_out_bits_store_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_bits_store_prevUnrecoded_expOut_T_5 = {8{_io_out_bits_store_prevUnrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_bits_store_prevUnrecoded_expOut = _io_out_bits_store_prevUnrecoded_expOut_T_3 \| _io_out_bits_store_prevUnrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_bits_store_prevUnrecoded_fractOut_T = io_out_bits_store_prevUnrecoded_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_bits_store_prevUnrecoded_fractOut_T_1 = io_out_bits_store_prevUnrecoded_rawIn_isInf ? 23'h0 : _io_out_bits_store_prevUnrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_bits_store_prevUnrecoded_fractOut = io_out_bits_store_prevUnrecoded_isSubnormal ? io_out_bits_store_prevUnrecoded_denormFract : _io_out_bits_store_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_bits_store_prevUnrecoded_hi = {io_out_bits_store_prevUnrecoded_rawIn_sign, io_out_bits_store_prevUnrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] io_out_bits_store_prevUnrecoded = {io_out_bits_store_prevUnrecoded_hi, io_out_bits_store_prevUnrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire [31:0] _io_out_bits_store_T = io_out_bits_store_unrecoded[63:32]; // @[FPU.scala:446:21] wire _io_out_bits_store_T_2 = &_io_out_bits_store_T_1; // @[FPU.scala:249:{25,56}] wire [31:0] _io_out_bits_store_T_3 = io_out_bits_store_unrecoded[31:0]; // @[FPU.scala:446:81] wire [31:0] _io_out_bits_store_T_4 = _io_out_bits_store_T_2 ? io_out_bits_store_prevUnrecoded : _io_out_bits_store_T_3; // @[FPU.scala:249:56, :446:{44,81}] wire [63:0] _io_out_bits_store_T_5 = {_io_out_bits_store_T, _io_out_bits_store_T_4}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _io_out_bits_store_T_6 = _io_out_bits_store_T_5[31:0]; // @[FPU.scala:446:10, :480:82] wire [63:0] _io_out_bits_store_T_7 = {2{_io_out_bits_store_T_6}}; // @[FPU.scala:480:{49,82}] wire [2:0] _io_out_bits_store_unrecoded_rawIn_isZero_T_1 = io_out_bits_store_unrecoded_rawIn_exp_1[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_unrecoded_rawIn_isZero_1 = _io_out_bits_store_unrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_unrecoded_rawIn_1_isZero = io_out_bits_store_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_unrecoded_rawIn_isSpecial_T_1 = io_out_bits_store_unrecoded_rawIn_exp_1[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_unrecoded_rawIn_isSpecial_1 = &_io_out_bits_store_unrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire [12:0] _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_unrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] io_out_bits_store_unrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] io_out_bits_store_unrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2 = io_out_bits_store_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_3 = io_out_bits_store_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3 = io_out_bits_store_unrecoded_rawIn_isSpecial_1 & _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_unrecoded_rawIn_1_isNaN = _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4 = ~_io_out_bits_store_unrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5 = io_out_bits_store_unrecoded_rawIn_isSpecial_1 & _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_unrecoded_rawIn_1_isInf = _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign io_out_bits_store_unrecoded_rawIn_1_sign = _io_out_bits_store_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1 = {1'h0, io_out_bits_store_unrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_unrecoded_rawIn_1_sExp = _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_unrecoded_rawIn_out_sig_T_4 = ~io_out_bits_store_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_5 = {1'h0, _io_out_bits_store_unrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] assign _io_out_bits_store_unrecoded_rawIn_out_sig_T_7 = {_io_out_bits_store_unrecoded_rawIn_out_sig_T_5, _io_out_bits_store_unrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_unrecoded_rawIn_1_sig = _io_out_bits_store_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_unrecoded_isSubnormal_1 = $signed(io_out_bits_store_unrecoded_rawIn_1_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_unrecoded_denormShiftDist_T_2 = io_out_bits_store_unrecoded_rawIn_1_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _io_out_bits_store_unrecoded_denormShiftDist_T_3 = 7'h1 - {1'h0, _io_out_bits_store_unrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] io_out_bits_store_unrecoded_denormShiftDist_1 = _io_out_bits_store_unrecoded_denormShiftDist_T_3[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_2 = io_out_bits_store_unrecoded_rawIn_1_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_3 = _io_out_bits_store_unrecoded_denormFract_T_2 >> io_out_bits_store_unrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] io_out_bits_store_unrecoded_denormFract_1 = _io_out_bits_store_unrecoded_denormFract_T_3[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_6 = io_out_bits_store_unrecoded_rawIn_1_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _io_out_bits_store_unrecoded_expOut_T_7 = {1'h0, _io_out_bits_store_unrecoded_expOut_T_6} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_8 = _io_out_bits_store_unrecoded_expOut_T_7[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_9 = io_out_bits_store_unrecoded_isSubnormal_1 ? 11'h0 : _io_out_bits_store_unrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_unrecoded_expOut_T_10 = io_out_bits_store_unrecoded_rawIn_1_isNaN \| io_out_bits_store_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_11 = {11{_io_out_bits_store_unrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] io_out_bits_store_unrecoded_expOut_1 = _io_out_bits_store_unrecoded_expOut_T_9 \| _io_out_bits_store_unrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_2 = io_out_bits_store_unrecoded_rawIn_1_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_3 = io_out_bits_store_unrecoded_rawIn_1_isInf ? 52'h0 : _io_out_bits_store_unrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] io_out_bits_store_unrecoded_fractOut_1 = io_out_bits_store_unrecoded_isSubnormal_1 ? io_out_bits_store_unrecoded_denormFract_1 : _io_out_bits_store_unrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] io_out_bits_store_unrecoded_hi_1 = {io_out_bits_store_unrecoded_rawIn_1_sign, io_out_bits_store_unrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] io_out_bits_store_unrecoded_1 = {io_out_bits_store_unrecoded_hi_1, io_out_bits_store_unrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] io_out_bits_store_prevRecoded_hi_1 = {_io_out_bits_store_prevRecoded_T_3, _io_out_bits_store_prevRecoded_T_4}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] io_out_bits_store_prevRecoded_1 = {io_out_bits_store_prevRecoded_hi_1, _io_out_bits_store_prevRecoded_T_5}; // @[FPU.scala:441:28, :444:10] wire [8:0] io_out_bits_store_prevUnrecoded_rawIn_exp_1 = io_out_bits_store_prevRecoded_1[31:23]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_rawIn_isZero_T_1 = io_out_bits_store_prevUnrecoded_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_rawIn_isZero_1 = _io_out_bits_store_prevUnrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_rawIn_1_isZero = io_out_bits_store_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_rawIn_isSpecial_T_1 = io_out_bits_store_prevUnrecoded_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_rawIn_isSpecial_1 = &_io_out_bits_store_prevUnrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_bits_store_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_bits_store_prevUnrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_rawIn_out_isNaN_T_2 = io_out_bits_store_prevUnrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_3 = io_out_bits_store_prevUnrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_rawIn_out_isNaN_T_3 = io_out_bits_store_prevUnrecoded_rawIn_isSpecial_1 & _io_out_bits_store_prevUnrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_rawIn_1_isNaN = _io_out_bits_store_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_4 = ~_io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_5 = io_out_bits_store_prevUnrecoded_rawIn_isSpecial_1 & _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_rawIn_1_isInf = _io_out_bits_store_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_rawIn_out_sign_T_1 = io_out_bits_store_prevRecoded_1[32]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_rawIn_1_sign = _io_out_bits_store_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_rawIn_out_sExp_T_1 = {1'h0, io_out_bits_store_prevUnrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_rawIn_1_sExp = _io_out_bits_store_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_4 = ~io_out_bits_store_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_5 = {1'h0, _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_6 = io_out_bits_store_prevRecoded_1[22:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_7 = {_io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_5, _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_rawIn_1_sig = _io_out_bits_store_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_isSubnormal_1 = $signed(io_out_bits_store_prevUnrecoded_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_denormShiftDist_T_2 = io_out_bits_store_prevUnrecoded_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_denormShiftDist_T_3 = 6'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_bits_store_prevUnrecoded_denormShiftDist_1 = _io_out_bits_store_prevUnrecoded_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_bits_store_prevUnrecoded_denormFract_T_2 = io_out_bits_store_prevUnrecoded_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_bits_store_prevUnrecoded_denormFract_T_3 = _io_out_bits_store_prevUnrecoded_denormFract_T_2 >> io_out_bits_store_prevUnrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_bits_store_prevUnrecoded_denormFract_1 = _io_out_bits_store_prevUnrecoded_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_bits_store_prevUnrecoded_expOut_T_6 = io_out_bits_store_prevUnrecoded_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_bits_store_prevUnrecoded_expOut_T_7 = {1'h0, _io_out_bits_store_prevUnrecoded_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_bits_store_prevUnrecoded_expOut_T_8 = _io_out_bits_store_prevUnrecoded_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_bits_store_prevUnrecoded_expOut_T_9 = io_out_bits_store_prevUnrecoded_isSubnormal_1 ? 8'h0 : _io_out_bits_store_prevUnrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_expOut_T_10 = io_out_bits_store_prevUnrecoded_rawIn_1_isNaN \| io_out_bits_store_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_bits_store_prevUnrecoded_expOut_T_11 = {8{_io_out_bits_store_prevUnrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_bits_store_prevUnrecoded_expOut_1 = _io_out_bits_store_prevUnrecoded_expOut_T_9 \| _io_out_bits_store_prevUnrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_bits_store_prevUnrecoded_fractOut_T_2 = io_out_bits_store_prevUnrecoded_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_bits_store_prevUnrecoded_fractOut_T_3 = io_out_bits_store_prevUnrecoded_rawIn_1_isInf ? 23'h0 : _io_out_bits_store_prevUnrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_bits_store_prevUnrecoded_fractOut_1 = io_out_bits_store_prevUnrecoded_isSubnormal_1 ? io_out_bits_store_prevUnrecoded_denormFract_1 : _io_out_bits_store_prevUnrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_bits_store_prevUnrecoded_hi_1 = {io_out_bits_store_prevUnrecoded_rawIn_1_sign, io_out_bits_store_prevUnrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] io_out_bits_store_prevUnrecoded_1 = {io_out_bits_store_prevUnrecoded_hi_1, io_out_bits_store_prevUnrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire [31:0] _io_out_bits_store_T_8 = io_out_bits_store_unrecoded_1[63:32]; // @[FPU.scala:446:21] wire _io_out_bits_store_T_10 = &_io_out_bits_store_T_9; // @[FPU.scala:249:{25,56}] wire [31:0] _io_out_bits_store_T_11 = io_out_bits_store_unrecoded_1[31:0]; // @[FPU.scala:446:81] wire [31:0] _io_out_bits_store_T_12 = _io_out_bits_store_T_10 ? io_out_bits_store_prevUnrecoded_1 : _io_out_bits_store_T_11; // @[FPU.scala:249:56, :446:{44,81}] wire [63:0] _io_out_bits_store_T_13 = {_io_out_bits_store_T_8, _io_out_bits_store_T_12}; // @[FPU.scala:446:{10,21,44}] wire [63:0] _io_out_bits_store_T_14 = _io_out_bits_store_T_13; // @[FPU.scala:446:10, :480:82] wire io_out_bits_store_truncIdx = _io_out_bits_store_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_out_bits_store_T_15 = io_out_bits_store_truncIdx; // @[package.scala:38:47, :39:86] assign _io_out_bits_store_T_16 = _io_out_bits_store_T_15 ? _io_out_bits_store_T_14 : _io_out_bits_store_T_7; // @[package.scala:39:{76,86}] assign io_out_bits_store = _io_out_bits_store_T_16; // @[package.scala:39:76] wire [31:0] _io_out_bits_toint_T = toint[31:0]; // @[FPU.scala:478:26, :481:59] wire _io_out_bits_toint_T_1 = _io_out_bits_toint_T[31]; // @[package.scala:132:38] wire [31:0] _io_out_bits_toint_T_2 = {32{_io_out_bits_toint_T_1}}; // @[package.scala:132:{20,38}] wire [63:0] _io_out_bits_toint_T_3 = {_io_out_bits_toint_T_2, _io_out_bits_toint_T}; // @[package.scala:132:{15,20}] assign _io_out_bits_toint_T_6 = _io_out_bits_toint_T_5 ? _io_out_bits_toint_T_4 : _io_out_bits_toint_T_3; // @[package.scala:39:{76,86}, :132:15] assign io_out_bits_toint = _io_out_bits_toint_T_6; // @[package.scala:39:76] wire [75:0] _classify_out_fractOut_T = {classify_out_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] classify_out_fractOut = _classify_out_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] classify_out_expOut_expCode = classify_out_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _classify_out_expOut_commonCase_T = {1'h0, classify_out_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _classify_out_expOut_commonCase_T_1 = _classify_out_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _classify_out_expOut_commonCase_T_2 = {1'h0, _classify_out_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] classify_out_expOut_commonCase = _classify_out_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _classify_out_expOut_T = classify_out_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _classify_out_expOut_T_1 = classify_out_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _classify_out_expOut_T_2 = _classify_out_expOut_T \| _classify_out_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [5:0] _classify_out_expOut_T_3 = classify_out_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _classify_out_expOut_T_4 = {classify_out_expOut_expCode, _classify_out_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _classify_out_expOut_T_5 = classify_out_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] classify_out_expOut = _classify_out_expOut_T_2 ? _classify_out_expOut_T_4 : _classify_out_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] classify_out_hi = {classify_out_sign, classify_out_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] _classify_out_T = {classify_out_hi, classify_out_fractOut}; // @[FPU.scala:277:38, :283:8] wire classify_out_sign_1 = _classify_out_T[32]; // @[FPU.scala:253:17, :283:8] wire [2:0] classify_out_code = _classify_out_T[31:29]; // @[FPU.scala:254:17, :283:8] wire [1:0] classify_out_codeHi = classify_out_code[2:1]; // @[FPU.scala:254:17, :255:22] wire classify_out_isSpecial = &classify_out_codeHi; // @[FPU.scala:255:22, :256:28] wire [6:0] _classify_out_isHighSubnormalIn_T = _classify_out_T[29:23]; // @[FPU.scala:258:30, :283:8] wire classify_out_isHighSubnormalIn = _classify_out_isHighSubnormalIn_T < 7'h2; // @[FPU.scala:258:{30,55}] wire _classify_out_isSubnormal_T = classify_out_code == 3'h1; // @[FPU.scala:254:17, :259:28] wire _GEN = classify_out_codeHi == 2'h1; // @[FPU.scala:255:22, :259:46] wire _classify_out_isSubnormal_T_1; // @[FPU.scala:259:46] assign _classify_out_isSubnormal_T_1 = _GEN; // @[FPU.scala:259:46] wire _classify_out_isNormal_T; // @[FPU.scala:260:27] assign _classify_out_isNormal_T = _GEN; // @[FPU.scala:259:46, :260:27] wire _classify_out_isSubnormal_T_2 = _classify_out_isSubnormal_T_1 & classify_out_isHighSubnormalIn; // @[FPU.scala:258:55, :259:{46,54}] wire classify_out_isSubnormal = _classify_out_isSubnormal_T \| _classify_out_isSubnormal_T_2; // @[FPU.scala:259:{28,36,54}] wire _classify_out_isNormal_T_1 = ~classify_out_isHighSubnormalIn; // @[FPU.scala:258:55, :260:38] wire _classify_out_isNormal_T_2 = _classify_out_isNormal_T & _classify_out_isNormal_T_1; // @[FPU.scala:260:{27,35,38}] wire _classify_out_isNormal_T_3 = classify_out_codeHi == 2'h2; // @[FPU.scala:255:22, :260:67] wire classify_out_isNormal = _classify_out_isNormal_T_2 \| _classify_out_isNormal_T_3; // @[FPU.scala:260:{35,57,67}] wire classify_out_isZero = classify_out_code == 3'h0; // @[FPU.scala:254:17, :261:23] wire _classify_out_isInf_T = classify_out_code[0]; // @[FPU.scala:254:17, :262:35] wire _classify_out_isInf_T_1 = ~_classify_out_isInf_T; // @[FPU.scala:262:{30,35}] wire classify_out_isInf = classify_out_isSpecial & _classify_out_isInf_T_1; // @[FPU.scala:256:28, :262:{27,30}] wire classify_out_isNaN = &classify_out_code; // @[FPU.scala:254:17, :263:22] wire _classify_out_isSNaN_T = _classify_out_T[22]; // @[FPU.scala:264:29, :283:8] wire _classify_out_isQNaN_T = _classify_out_T[22]; // @[FPU.scala:264:29, :265:28, :283:8] wire _classify_out_isSNaN_T_1 = ~_classify_out_isSNaN_T; // @[FPU.scala:264:{27,29}] wire classify_out_isSNaN = classify_out_isNaN & _classify_out_isSNaN_T_1; // @[FPU.scala:263:22, :264:{24,27}] wire classify_out_isQNaN = classify_out_isNaN & _classify_out_isQNaN_T; // @[FPU.scala:263:22, :265:{24,28}] wire _classify_out_T_1 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:34] wire _classify_out_T_2 = classify_out_isInf & _classify_out_T_1; // @[FPU.scala:262:27, :267:{31,34}] wire _classify_out_T_3 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:{34,53}] wire _classify_out_T_4 = classify_out_isNormal & _classify_out_T_3; // @[FPU.scala:260:57, :267:{50,53}] wire _classify_out_T_5 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:34, :268:24] wire _classify_out_T_6 = classify_out_isSubnormal & _classify_out_T_5; // @[FPU.scala:259:36, :268:{21,24}] wire _classify_out_T_7 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:34, :268:41] wire _classify_out_T_8 = classify_out_isZero & _classify_out_T_7; // @[FPU.scala:261:23, :268:{38,41}] wire _classify_out_T_9 = classify_out_isZero & classify_out_sign_1; // @[FPU.scala:253:17, :261:23, :268:55] wire _classify_out_T_10 = classify_out_isSubnormal & classify_out_sign_1; // @[FPU.scala:253:17, :259:36, :269:21] wire _classify_out_T_11 = classify_out_isNormal & classify_out_sign_1; // @[FPU.scala:253:17, :260:57, :269:39] wire _classify_out_T_12 = classify_out_isInf & classify_out_sign_1; // @[FPU.scala:253:17, :262:27, :269:54] wire [1:0] classify_out_lo_lo = {_classify_out_T_11, _classify_out_T_12}; // @[FPU.scala:267:8, :269:{39,54}] wire [1:0] classify_out_lo_hi_hi = {_classify_out_T_8, _classify_out_T_9}; // @[FPU.scala:267:8, :268:{38,55}] wire [2:0] classify_out_lo_hi = {classify_out_lo_hi_hi, _classify_out_T_10}; // @[FPU.scala:267:8, :269:21] wire [4:0] classify_out_lo = {classify_out_lo_hi, classify_out_lo_lo}; // @[FPU.scala:267:8] wire [1:0] classify_out_hi_lo = {_classify_out_T_4, _classify_out_T_6}; // @[FPU.scala:267:{8,50}, :268:21] wire [1:0] classify_out_hi_hi_hi = {classify_out_isQNaN, classify_out_isSNaN}; // @[FPU.scala:264:24, :265:24, :267:8] wire [2:0] classify_out_hi_hi = {classify_out_hi_hi_hi, _classify_out_T_2}; // @[FPU.scala:267:{8,31}] wire [4:0] classify_out_hi_1 = {classify_out_hi_hi, classify_out_hi_lo}; // @[FPU.scala:267:8] wire [9:0] _classify_out_T_13 = {classify_out_hi_1, classify_out_lo}; // @[FPU.scala:267:8] wire [1:0] classify_out_codeHi_1 = classify_out_code_1[2:1]; // @[FPU.scala:254:17, :255:22] wire classify_out_isSpecial_1 = &classify_out_codeHi_1; // @[FPU.scala:255:22, :256:28] wire [9:0] _classify_out_isHighSubnormalIn_T_1 = in_in1[61:52]; // @[FPU.scala:258:30, :466:21] wire classify_out_isHighSubnormalIn_1 = _classify_out_isHighSubnormalIn_T_1 < 10'h2; // @[FPU.scala:258:{30,55}] wire _classify_out_isSubnormal_T_3 = classify_out_code_1 == 3'h1; // @[FPU.scala:254:17, :259:28] wire _GEN_0 = classify_out_codeHi_1 == 2'h1; // @[FPU.scala:255:22, :259:46] wire _classify_out_isSubnormal_T_4; // @[FPU.scala:259:46] assign _classify_out_isSubnormal_T_4 = _GEN_0; // @[FPU.scala:259:46] wire _classify_out_isNormal_T_4; // @[FPU.scala:260:27] assign _classify_out_isNormal_T_4 = _GEN_0; // @[FPU.scala:259:46, :260:27] wire _classify_out_isSubnormal_T_5 = _classify_out_isSubnormal_T_4 & classify_out_isHighSubnormalIn_1; // @[FPU.scala:258:55, :259:{46,54}] wire classify_out_isSubnormal_1 = _classify_out_isSubnormal_T_3 \| _classify_out_isSubnormal_T_5; // @[FPU.scala:259:{28,36,54}] wire _classify_out_isNormal_T_5 = ~classify_out_isHighSubnormalIn_1; // @[FPU.scala:258:55, :260:38] wire _classify_out_isNormal_T_6 = _classify_out_isNormal_T_4 & _classify_out_isNormal_T_5; // @[FPU.scala:260:{27,35,38}] wire _classify_out_isNormal_T_7 = classify_out_codeHi_1 == 2'h2; // @[FPU.scala:255:22, :260:67] wire classify_out_isNormal_1 = _classify_out_isNormal_T_6 \| _classify_out_isNormal_T_7; // @[FPU.scala:260:{35,57,67}] wire classify_out_isZero_1 = classify_out_code_1 == 3'h0; // @[FPU.scala:254:17, :261:23] wire _classify_out_isInf_T_2 = classify_out_code_1[0]; // @[FPU.scala:254:17, :262:35] wire _classify_out_isInf_T_3 = ~_classify_out_isInf_T_2; // @[FPU.scala:262:{30,35}] wire classify_out_isInf_1 = classify_out_isSpecial_1 & _classify_out_isInf_T_3; // @[FPU.scala:256:28, :262:{27,30}] wire classify_out_isNaN_1 = &classify_out_code_1; // @[FPU.scala:254:17, :263:22] wire _classify_out_isSNaN_T_2 = in_in1[51]; // @[FPU.scala:264:29, :466:21] wire _classify_out_isQNaN_T_1 = in_in1[51]; // @[FPU.scala:264:29, :265:28, :466:21] wire _classify_out_isSNaN_T_3 = ~_classify_out_isSNaN_T_2; // @[FPU.scala:264:{27,29}] wire classify_out_isSNaN_1 = classify_out_isNaN_1 & _classify_out_isSNaN_T_3; // @[FPU.scala:263:22, :264:{24,27}] wire classify_out_isQNaN_1 = classify_out_isNaN_1 & _classify_out_isQNaN_T_1; // @[FPU.scala:263:22, :265:{24,28}] wire _classify_out_T_14 = ~classify_out_sign_2; // @[FPU.scala:253:17, :267:34] wire _classify_out_T_15 = classify_out_isInf_1 & _classify_out_T_14; // @[FPU.scala:262:27, :267:{31,34}] wire _classify_out_T_16 = ~classify_out_sign_2; // @[FPU.scala:253:17, :267:{34,53}] wire _classify_out_T_17 = classify_out_isNormal_1 & _classify_out_T_16; // @[FPU.scala:260:57, :267:{50,53}] wire _classify_out_T_18 = ~classify_out_sign_2; // @[FPU.scala:253:17, :267:34, :268:24] wire _classify_out_T_19 = classify_out_isSubnormal_1 & _classify_out_T_18; // @[FPU.scala:259:36, :268:{21,24}] wire _classify_out_T_20 = ~classify_out_sign_2; // @[FPU.scala:253:17, :267:34, :268:41] wire _classify_out_T_21 = classify_out_isZero_1 & _classify_out_T_20; // @[FPU.scala:261:23, :268:{38,41}] wire _classify_out_T_22 = classify_out_isZero_1 & classify_out_sign_2; // @[FPU.scala:253:17, :261:23, :268:55] wire _classify_out_T_23 = classify_out_isSubnormal_1 & classify_out_sign_2; // @[FPU.scala:253:17, :259:36, :269:21] wire _classify_out_T_24 = classify_out_isNormal_1 & classify_out_sign_2; // @[FPU.scala:253:17, :260:57, :269:39] wire _classify_out_T_25 = classify_out_isInf_1 & classify_out_sign_2; // @[FPU.scala:253:17, :262:27, :269:54] wire [1:0] classify_out_lo_lo_1 = {_classify_out_T_24, _classify_out_T_25}; // @[FPU.scala:267:8, :269:{39,54}] wire [1:0] classify_out_lo_hi_hi_1 = {_classify_out_T_21, _classify_out_T_22}; // @[FPU.scala:267:8, :268:{38,55}] wire [2:0] classify_out_lo_hi_1 = {classify_out_lo_hi_hi_1, _classify_out_T_23}; // @[FPU.scala:267:8, :269:21] wire [4:0] classify_out_lo_1 = {classify_out_lo_hi_1, classify_out_lo_lo_1}; // @[FPU.scala:267:8] wire [1:0] classify_out_hi_lo_1 = {_classify_out_T_17, _classify_out_T_19}; // @[FPU.scala:267:{8,50}, :268:21] wire [1:0] classify_out_hi_hi_hi_1 = {classify_out_isQNaN_1, classify_out_isSNaN_1}; // @[FPU.scala:264:24, :265:24, :267:8] wire [2:0] classify_out_hi_hi_1 = {classify_out_hi_hi_hi_1, _classify_out_T_15}; // @[FPU.scala:267:{8,31}] wire [4:0] classify_out_hi_2 = {classify_out_hi_hi_1, classify_out_hi_lo_1}; // @[FPU.scala:267:8] wire [9:0] _classify_out_T_26 = {classify_out_hi_2, classify_out_lo_1}; // @[FPU.scala:267:8] wire classify_out_truncIdx = _classify_out_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _classify_out_T_27 = classify_out_truncIdx; // @[package.scala:38:47, :39:86] wire [9:0] classify_out = _classify_out_T_27 ? _classify_out_T_26 : _classify_out_T_13; // @[package.scala:39:{76,86}] wire [31:0] _toint_T = toint_ieee[63:32]; // @[package.scala:39:76] wire [31:0] _toint_T_7 = toint_ieee[63:32]; // @[package.scala:39:76] wire [63:0] _toint_T_1 = {_toint_T, 32'h0}; // @[FPU.scala:486:{41,52}] wire [63:0] _toint_T_2 = {54'h0, classify_out} \| _toint_T_1; // @[package.scala:39:76] wire [2:0] _toint_T_3 = ~in_rm; // @[FPU.scala:466:21, :491:15] wire [1:0] _toint_T_4 = {_dcmp_io_lt, _dcmp_io_eq}; // @[FPU.scala:469:20, :491:27] wire [2:0] _toint_T_5 = {1'h0, _toint_T_3[1:0] & _toint_T_4}; // @[FPU.scala:491:{15,22,27}] wire _toint_T_6 = \|_toint_T_5; // @[FPU.scala:491:{22,53}] wire [63:0] _toint_T_8 = {_toint_T_7, 32'h0}; // @[FPU.scala:491:{71,82}] wire [63:0] _toint_T_9 = {63'h0, _toint_T_6} \| _toint_T_8; // @[FPU.scala:491:{53,57,82}] wire cvtType = in_typ[1]; // @[package.scala:163:13] assign intType = in_wflags & ~in_ren2 & cvtType; // @[package.scala:163:13] wire _conv_io_signedOut_T = in_typ[0]; // @[FPU.scala:466:21, :501:35] wire _narrow_io_signedOut_T = in_typ[0]; // @[FPU.scala:466:21, :501:35, :511:41] wire _conv_io_signedOut_T_1 = ~_conv_io_signedOut_T; // @[FPU.scala:501:{28,35}] wire [1:0] _io_out_bits_exc_T = _conv_io_intExceptionFlags[2:1]; // @[FPU.scala:498:24, :503:55] wire _io_out_bits_exc_T_1 = \|_io_out_bits_exc_T; // @[FPU.scala:503:{55,62}] wire _io_out_bits_exc_T_2 = _conv_io_intExceptionFlags[0]; // @[FPU.scala:498:24, :503:102] wire _io_out_bits_exc_T_5 = _conv_io_intExceptionFlags[0]; // @[FPU.scala:498:24, :503:102, :517:90] wire [3:0] io_out_bits_exc_hi = {_io_out_bits_exc_T_1, 3'h0}; // @[FPU.scala:503:{29,62}] wire [4:0] _io_out_bits_exc_T_3 = {io_out_bits_exc_hi, _io_out_bits_exc_T_2}; // @[FPU.scala:503:{29,102}] wire _narrow_io_signedOut_T_1 = ~_narrow_io_signedOut_T; // @[FPU.scala:511:{34,41}] wire _excSign_T_2 = &_excSign_T_1; // @[FPU.scala:249:{25,56}] wire _excSign_T_3 = ~_excSign_T_2; // @[FPU.scala:249:56, :513:62] wire excSign = _excSign_T & _excSign_T_3; // @[FPU.scala:513:{31,59,62}] wire _excOut_T = _conv_io_signedOut_T_1 == excSign; // @[FPU.scala:501:28, :513:59, :514:46] wire _excOut_T_1 = ~excSign; // @[FPU.scala:513:59, :514:69] wire [30:0] _excOut_T_2 = {31{_excOut_T_1}}; // @[FPU.scala:514:{63,69}] wire [31:0] excOut = {_excOut_T, _excOut_T_2}; // @[FPU.scala:514:{27,46,63}] wire _invalid_T = _conv_io_intExceptionFlags[2]; // @[FPU.scala:498:24, :515:50] wire _invalid_T_1 = _narrow_io_intExceptionFlags[1]; // @[FPU.scala:508:30, :515:84] wire invalid = _invalid_T \| _invalid_T_1; // @[FPU.scala:515:{50,54,84}] wire [31:0] _toint_T_10 = _conv_io_out[63:32]; // @[FPU.scala:498:24, :516:53] wire [63:0] _toint_T_11 = {_toint_T_10, excOut}; // @[FPU.scala:514:27, :516:{40,53}] assign toint = in_wflags ? (in_ren2 ? _toint_T_9 : ~cvtType & invalid ? _toint_T_11 : _conv_io_out) : in_rm[0] ? _toint_T_2 : toint_ieee; // @[package.scala:39:76, :163:13] wire _io_out_bits_exc_T_4 = ~invalid; // @[FPU.scala:515:54, :517:53] wire _io_out_bits_exc_T_6 = _io_out_bits_exc_T_4 & _io_out_bits_exc_T_5; // @[FPU.scala:517:{53,62,90}] wire [3:0] io_out_bits_exc_hi_1 = {invalid, 3'h0}; // @[FPU.scala:515:54, :517:33] wire [4:0] _io_out_bits_exc_T_7 = {io_out_bits_exc_hi_1, _io_out_bits_exc_T_6}; // @[FPU.scala:517:{33,62}] assign io_out_bits_exc = in_wflags ? (in_ren2 ? _dcmp_io_exceptionFlags : cvtType ? _io_out_bits_exc_T_3 : _io_out_bits_exc_T_7) : 5'h0; // @[package.scala:163:13] wire _io_out_bits_lt_T_1 = $signed(_io_out_bits_lt_T) < 65'sh0; // @[FPU.scala:524:{46,53}] wire _io_out_bits_lt_T_3 = $signed(_io_out_bits_lt_T_2) > -65'sh1; // @[FPU.scala:524:{72,79}] wire _io_out_bits_lt_T_4 = _io_out_bits_lt_T_1 & _io_out_bits_lt_T_3; // @[FPU.scala:524:{53,59,79}] assign _io_out_bits_lt_T_5 = _dcmp_io_lt \| _io_out_bits_lt_T_4; // @[FPU.scala:469:20, :524:{32,59}] assign io_out_bits_lt = _io_out_bits_lt_T_5; // @[FPU.scala:453:7, :524:32] always @(posedge clock) begin // @[FPU.scala:453:7] if (io_in_valid_0) begin // @[FPU.scala:453:7] in_ldst <= io_in_bits_ldst_0; // @[FPU.scala:453:7, :466:21] in_wen <= io_in_bits_wen_0; // @[FPU.scala:453:7, :466:21] in_ren1 <= io_in_bits_ren1_0; // @[FPU.scala:453:7, :466:21] in_ren2 <= io_in_bits_ren2_0; // @[FPU.scala:453:7, :466:21] in_ren3 <= io_in_bits_ren3_0; // @[FPU.scala:453:7, :466:21] in_swap12 <= io_in_bits_swap12_0; // @[FPU.scala:453:7, :466:21] in_swap23 <= io_in_bits_swap23_0; // @[FPU.scala:453:7, :466:21] in_typeTagIn <= io_in_bits_typeTagIn_0; // @[FPU.scala:453:7, :466:21] in_typeTagOut <= io_in_bits_typeTagOut_0; // @[FPU.scala:453:7, :466:21] in_fromint <= io_in_bits_fromint_0; // @[FPU.scala:453:7, :466:21] in_toint <= io_in_bits_toint_0; // @[FPU.scala:453:7, :466:21] in_fastpipe <= io_in_bits_fastpipe_0; // @[FPU.scala:453:7, :466:21] in_fma <= io_in_bits_fma_0; // @[FPU.scala:453:7, :466:21] in_div <= io_in_bits_div_0; // @[FPU.scala:453:7, :466:21] in_sqrt <= io_in_bits_sqrt_0; // @[FPU.scala:453:7, :466:21] in_wflags <= io_in_bits_wflags_0; // @[FPU.scala:453:7, :466:21] in_vec <= io_in_bits_vec_0; // @[FPU.scala:453:7, :466:21] in_rm <= io_in_bits_rm_0; // @[FPU.scala:453:7, :466:21] in_typ <= io_in_bits_typ_0; // @[FPU.scala:453:7, :466:21] in_in1 <= io_in_bits_in1_0; // @[FPU.scala:453:7, :466:21] in_in2 <= io_in_bits_in2_0; // @[FPU.scala:453:7, :466:21] end valid <= io_in_valid_0; // @[FPU.scala:453:7, :467:22] always @(posedge) CompareRecFN_1 dcmp ( // @[FPU.scala:469:20] .io_a (in_in1), // @[FPU.scala:466:21] .io_b (in_in2), // @[FPU.scala:466:21] .io_signaling (_dcmp_io_signaling_T_1), // @[FPU.scala:472:24] .io_lt (_dcmp_io_lt), .io_eq (_dcmp_io_eq), .io_exceptionFlags (_dcmp_io_exceptionFlags) ); // @[FPU.scala:469:20] RecFNToIN_e11_s53_i64_1 conv ( // @[FPU.scala:498:24] .clock (clock), .reset (reset), .io_in (in_in1), // @[FPU.scala:466:21] .io_roundingMode (in_rm), // @[FPU.scala:466:21] .io_signedOut (_conv_io_signedOut_T_1), // @[FPU.scala:501:28] .io_out (_conv_io_out), .io_intExceptionFlags (_conv_io_intExceptionFlags) ); // @[FPU.scala:498:24] RecFNToIN_e11_s53_i32_1 narrow ( // @[FPU.scala:508:30] .clock (clock), .reset (reset), .io_in (in_in1), // @[FPU.scala:466:21] .io_roundingMode (in_rm), // @[FPU.scala:466:21] .io_signedOut (_narrow_io_signedOut_T_1), // @[FPU.scala:511:34] .io_intExceptionFlags (_narrow_io_intExceptionFlags) ); // @[FPU.scala:508:30] assign io_out_bits_in_rm = io_out_bits_in_rm_0; // @[FPU.scala:453:7] assign io_out_bits_in_in1 = io_out_bits_in_in1_0; // @[FPU.scala:453:7] assign io_out_bits_in_in2 = io_out_bits_in_in2_0; // @[FPU.scala:453:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File Decode.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.BitPat import chisel3.util.experimental.decode._ object DecodeLogic { // TODO This should be a method on BitPat private def hasDontCare(bp: BitPat): Boolean = bp.mask.bitCount != bp.width // Pads BitPats that are safe to pad (no don't cares), errors otherwise private def padBP(bp: BitPat, width: Int): BitPat = { if (bp.width == width) bp else { require(!hasDontCare(bp), s"Cannot pad '$bp' to '$width' bits because it has don't cares") val diff = width - bp.width require(diff > 0, s"Cannot pad '$bp' to '$width' because it is already '${bp.width}' bits wide!") BitPat(0.U(diff.W)) ## bp } } def apply(addr: UInt, default: BitPat, mapping: Iterable[(BitPat, BitPat)]): UInt = chisel3.util.experimental.decode.decoder(QMCMinimizer, addr, TruthTable(mapping, default)) def apply(addr: UInt, default: Seq[BitPat], mappingIn: Iterable[(BitPat, Seq[BitPat])]): Seq[UInt] = { val nElts = default.size require(mappingIn.forall(_._2.size == nElts), s"All Seq[BitPat] must be of the same length, got $nElts vs. ${mappingIn.find(_._2.size != nElts).get}" ) val elementsGrouped = mappingIn.map(_._2).transpose val elementWidths = elementsGrouped.zip(default).map { case (elts, default) => (default :: elts.toList).map(_.getWidth).max } val resultWidth = elementWidths.sum val elementIndices = elementWidths.scan(resultWidth - 1) { case (l, r) => l - r } // All BitPats that correspond to a given element in the result must have the same width in the // chisel3 decoder. We will zero pad any BitPats that are too small so long as they dont have // any don't cares. If there are don't cares, it is an error and the user needs to pad the // BitPat themselves val defaultsPadded = default.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } val mappingInPadded = mappingIn.map { case (in, elts) => in -> elts.zip(elementWidths).map { case (bp, w) => padBP(bp, w) } } val decoded = apply(addr, defaultsPadded.reduce(_ ## _), mappingInPadded.map { case (in, out) => (in, out.reduce(_ ## _)) }) elementIndices.zip(elementIndices.tail).map { case (msb, lsb) => decoded(msb, lsb + 1) }.toList } def apply(addr: UInt, default: Seq[BitPat], mappingIn: List[(UInt, Seq[BitPat])]): Seq[UInt] = apply(addr, default, mappingIn.map(m => (BitPat(m._1), m._2)).asInstanceOf[Iterable[(BitPat, Seq[BitPat])]]) def apply(addr: UInt, trues: Iterable[UInt], falses: Iterable[UInt]): Bool = apply(addr, BitPat.dontCare(1), trues.map(BitPat(_) -> BitPat("b1")) ++ falses.map(BitPat(_) -> BitPat("b0"))).asBool } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File CustomCSRs.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tile import chisel3._ import org.chipsalliance.cde.config.Parameters case class CustomCSR(id: Int, mask: BigInt, init: Option[BigInt]) object CustomCSR { def constant(id: Int, value: BigInt): CustomCSR = CustomCSR(id, BigInt(0), Some(value)) } class CustomCSRIO(implicit p: Parameters) extends CoreBundle { val ren = Output(Bool()) // set by CSRFile, indicates an instruction is reading the CSR val wen = Output(Bool()) // set by CSRFile, indicates an instruction is writing the CSR val wdata = Output(UInt(xLen.W)) // wdata provided by instruction writing CSR val value = Output(UInt(xLen.W)) // current value of CSR in CSRFile val stall = Input(Bool()) // reads and writes to this CSR should stall (must be bounded) val set = Input(Bool()) // set/sdata enables external agents to set the value of this CSR val sdata = Input(UInt(xLen.W)) } class CustomCSRs(implicit p: Parameters) extends CoreBundle { // Not all cores have these CSRs, but those that do should follow the same // numbering conventions. So we list them here but default them to None. protected def bpmCSRId = 0x7c0 protected def bpmCSR: Option[CustomCSR] = None protected def chickenCSRId = 0x7c1 protected def chickenCSR: Option[CustomCSR] = None // If you override this, you'll want to concatenate super.decls def decls: Seq[CustomCSR] = bpmCSR.toSeq ++ chickenCSR val csrs = Vec(decls.size, new CustomCSRIO) def flushBTB = getOrElse(bpmCSR, _.wen, false.B) def bpmStatic = getOrElse(bpmCSR, _.value(0), false.B) def disableDCacheClockGate = getOrElse(chickenCSR, _.value(0), false.B) def disableICacheClockGate = getOrElse(chickenCSR, _.value(1), false.B) def disableCoreClockGate = getOrElse(chickenCSR, _.value(2), false.B) def disableSpeculativeICacheRefill = getOrElse(chickenCSR, _.value(3), false.B) def suppressCorruptOnGrantData = getOrElse(chickenCSR, _.value(9), false.B) protected def getByIdOrElse[T](id: Int, f: CustomCSRIO => T, alt: T): T = { val idx = decls.indexWhere(_.id == id) if (idx < 0) alt else f(csrs(idx)) } protected def getOrElse[T](csr: Option[CustomCSR], f: CustomCSRIO => T, alt: T): T = csr.map(c => getByIdOrElse(c.id, f, alt)).getOrElse(alt) } File Consts.scala: // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket.constants import chisel3._ import chisel3.util._ import freechips.rocketchip.util._ trait ScalarOpConstants { val SZ_BR = 3 def BR_X = BitPat("b???") def BR_EQ = 0.U(3.W) def BR_NE = 1.U(3.W) def BR_J = 2.U(3.W) def BR_N = 3.U(3.W) def BR_LT = 4.U(3.W) def BR_GE = 5.U(3.W) def BR_LTU = 6.U(3.W) def BR_GEU = 7.U(3.W) def A1_X = BitPat("b??") def A1_ZERO = 0.U(2.W) def A1_RS1 = 1.U(2.W) def A1_PC = 2.U(2.W) def A1_RS1SHL = 3.U(2.W) def IMM_X = BitPat("b???") def IMM_S = 0.U(3.W) def IMM_SB = 1.U(3.W) def IMM_U = 2.U(3.W) def IMM_UJ = 3.U(3.W) def IMM_I = 4.U(3.W) def IMM_Z = 5.U(3.W) def A2_X = BitPat("b???") def A2_ZERO = 0.U(3.W) def A2_SIZE = 1.U(3.W) def A2_RS2 = 2.U(3.W) def A2_IMM = 3.U(3.W) def A2_RS2OH = 4.U(3.W) def A2_IMMOH = 5.U(3.W) def X = BitPat("b?") def N = BitPat("b0") def Y = BitPat("b1") val SZ_DW = 1 def DW_X = X def DW_32 = false.B def DW_64 = true.B def DW_XPR = DW_64 } trait MemoryOpConstants { val NUM_XA_OPS = 9 val M_SZ = 5 def M_X = BitPat("b?????"); def M_XRD = "b00000".U; // int load def M_XWR = "b00001".U; // int store def M_PFR = "b00010".U; // prefetch with intent to read def M_PFW = "b00011".U; // prefetch with intent to write def M_XA_SWAP = "b00100".U def M_FLUSH_ALL = "b00101".U // flush all lines def M_XLR = "b00110".U def M_XSC = "b00111".U def M_XA_ADD = "b01000".U def M_XA_XOR = "b01001".U def M_XA_OR = "b01010".U def M_XA_AND = "b01011".U def M_XA_MIN = "b01100".U def M_XA_MAX = "b01101".U def M_XA_MINU = "b01110".U def M_XA_MAXU = "b01111".U def M_FLUSH = "b10000".U // write back dirty data and cede R/W permissions def M_PWR = "b10001".U // partial (masked) store def M_PRODUCE = "b10010".U // write back dirty data and cede W permissions def M_CLEAN = "b10011".U // write back dirty data and retain R/W permissions def M_SFENCE = "b10100".U // SFENCE.VMA def M_HFENCEV = "b10101".U // HFENCE.VVMA def M_HFENCEG = "b10110".U // HFENCE.GVMA def M_WOK = "b10111".U // check write permissions but don't perform a write def M_HLVX = "b10000".U // HLVX instruction def isAMOLogical(cmd: UInt) = cmd.isOneOf(M_XA_SWAP, M_XA_XOR, M_XA_OR, M_XA_AND) def isAMOArithmetic(cmd: UInt) = cmd.isOneOf(M_XA_ADD, M_XA_MIN, M_XA_MAX, M_XA_MINU, M_XA_MAXU) def isAMO(cmd: UInt) = isAMOLogical(cmd) \|\| isAMOArithmetic(cmd) def isPrefetch(cmd: UInt) = cmd === M_PFR \|\| cmd === M_PFW def isRead(cmd: UInt) = cmd.isOneOf(M_XRD, M_HLVX, M_XLR, M_XSC) \|\| isAMO(cmd) def isWrite(cmd: UInt) = cmd === M_XWR \|\| cmd === M_PWR \|\| cmd === M_XSC \|\| isAMO(cmd) def isWriteIntent(cmd: UInt) = isWrite(cmd) \|\| cmd === M_PFW \|\| cmd === M_XLR } File Events.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.log2Ceil import freechips.rocketchip.util._ import freechips.rocketchip.util.property class EventSet(val gate: (UInt, UInt) => Bool, val events: Seq[(String, () => Bool)]) { def size = events.size val hits = WireDefault(VecInit(Seq.fill(size)(false.B))) def check(mask: UInt) = { hits := events.map(_._2()) gate(mask, hits.asUInt) } def dump(): Unit = { for (((name, _), i) <- events.zipWithIndex) when (check(1.U << i)) { printf(s"Event $name\n") } } def withCovers: Unit = { events.zipWithIndex.foreach { case ((name, func), i) => property.cover(gate((1.U << i), (func() << i)), name) } } } class EventSets(val eventSets: Seq[EventSet]) { def maskEventSelector(eventSel: UInt): UInt = { // allow full associativity between counters and event sets (for now?) val setMask = (BigInt(1) << eventSetIdBits) - 1 val maskMask = ((BigInt(1) << eventSets.map(_.size).max) - 1) << maxEventSetIdBits eventSel & (setMask \| maskMask).U } private def decode(counter: UInt): (UInt, UInt) = { require(eventSets.size <= (1 << maxEventSetIdBits)) require(eventSetIdBits > 0) (counter(eventSetIdBits-1, 0), counter >> maxEventSetIdBits) } def evaluate(eventSel: UInt): Bool = { val (set, mask) = decode(eventSel) val sets = for (e <- eventSets) yield { require(e.hits.getWidth <= mask.getWidth, s"too many events ${e.hits.getWidth} wider than mask ${mask.getWidth}") e check mask } sets(set) } def cover() = eventSets.foreach { _.withCovers } private def eventSetIdBits = log2Ceil(eventSets.size) private def maxEventSetIdBits = 8 require(eventSetIdBits <= maxEventSetIdBits) } class SuperscalarEventSets(val eventSets: Seq[(Seq[EventSet], (UInt, UInt) => UInt)]) { def evaluate(eventSel: UInt): UInt = { val (set, mask) = decode(eventSel) val sets = for ((sets, reducer) <- eventSets) yield { sets.map { set => require(set.hits.getWidth <= mask.getWidth, s"too many events ${set.hits.getWidth} wider than mask ${mask.getWidth}") set.check(mask) }.reduce(reducer) } val zeroPadded = sets.padTo(1 << eventSetIdBits, 0.U) zeroPadded(set) } def toScalarEventSets: EventSets = new EventSets(eventSets.map(_._1.head)) def cover(): Unit = { eventSets.foreach(_._1.foreach(_.withCovers)) } private def decode(counter: UInt): (UInt, UInt) = { require(eventSets.size <= (1 << maxEventSetIdBits)) require(eventSetIdBits > 0) (counter(eventSetIdBits-1, 0), counter >> maxEventSetIdBits) } private def eventSetIdBits = log2Ceil(eventSets.size) private def maxEventSetIdBits = 8 require(eventSets.forall(s => s._1.forall(_.size == s._1.head.size))) require(eventSetIdBits <= maxEventSetIdBits) } File RocketCore.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import chisel3.withClock import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.ArrayBuffer case class RocketCoreParams( xLen: Int = 64, pgLevels: Int = 3, // sv39 default bootFreqHz: BigInt = 0, useVM: Boolean = true, useUser: Boolean = false, useSupervisor: Boolean = false, useHypervisor: Boolean = false, useDebug: Boolean = true, useAtomics: Boolean = true, useAtomicsOnlyForIO: Boolean = false, useCompressed: Boolean = true, useRVE: Boolean = false, useConditionalZero: Boolean = false, useZba: Boolean = false, useZbb: Boolean = false, useZbs: Boolean = false, nLocalInterrupts: Int = 0, useNMI: Boolean = false, nBreakpoints: Int = 1, useBPWatch: Boolean = false, mcontextWidth: Int = 0, scontextWidth: Int = 0, nPMPs: Int = 8, nPerfCounters: Int = 0, haveBasicCounters: Boolean = true, haveCFlush: Boolean = false, misaWritable: Boolean = true, nL2TLBEntries: Int = 0, nL2TLBWays: Int = 1, nPTECacheEntries: Int = 8, mtvecInit: Option[BigInt] = Some(BigInt(0)), mtvecWritable: Boolean = true, fastLoadWord: Boolean = true, fastLoadByte: Boolean = false, branchPredictionModeCSR: Boolean = false, clockGate: Boolean = false, mvendorid: Int = 0, // 0 means non-commercial implementation mimpid: Int = 0x20181004, // release date in BCD mulDiv: Option[MulDivParams] = Some(MulDivParams()), fpu: Option[FPUParams] = Some(FPUParams()), debugROB: Option[DebugROBParams] = None, // if size < 1, SW ROB, else HW ROB haveCease: Boolean = true, // non-standard CEASE instruction haveSimTimeout: Boolean = true, // add plusarg for simulation timeout vector: Option[RocketCoreVectorParams] = None ) extends CoreParams { val lgPauseCycles = 5 val haveFSDirty = false val pmpGranularity: Int = if (useHypervisor) 4096 else 4 val fetchWidth: Int = if (useCompressed) 2 else 1 // fetchWidth doubled, but coreInstBytes halved, for RVC: val decodeWidth: Int = fetchWidth / (if (useCompressed) 2 else 1) val retireWidth: Int = 1 val instBits: Int = if (useCompressed) 16 else 32 val lrscCycles: Int = 80 // worst case is 14 mispredicted branches + slop val traceHasWdata: Boolean = debugROB.isDefined // ooo wb, so no wdata in trace override val useVector = vector.isDefined override val vectorUseDCache = vector.map(_.useDCache).getOrElse(false) override def vLen = vector.map(_.vLen).getOrElse(0) override def eLen = vector.map(_.eLen).getOrElse(0) override def vfLen = vector.map(_.vfLen).getOrElse(0) override def vfh = vector.map(_.vfh).getOrElse(false) override def vExts = vector.map(_.vExts).getOrElse(Nil) override def vMemDataBits = vector.map(_.vMemDataBits).getOrElse(0) override val customIsaExt = Option.when(haveCease)("xrocket") // CEASE instruction override def minFLen: Int = fpu.map(_.minFLen).getOrElse(32) override def customCSRs(implicit p: Parameters) = new RocketCustomCSRs } trait HasRocketCoreParameters extends HasCoreParameters { lazy val rocketParams: RocketCoreParams = tileParams.core.asInstanceOf[RocketCoreParams] val fastLoadWord = rocketParams.fastLoadWord val fastLoadByte = rocketParams.fastLoadByte val mulDivParams = rocketParams.mulDiv.getOrElse(MulDivParams()) // TODO ask andrew about this require(!fastLoadByte \|\| fastLoadWord) require(!rocketParams.haveFSDirty, "rocket doesn't support setting fs dirty from outside, please disable haveFSDirty") } class RocketCustomCSRs(implicit p: Parameters) extends CustomCSRs with HasRocketCoreParameters { override def bpmCSR = { rocketParams.branchPredictionModeCSR.option(CustomCSR(bpmCSRId, BigInt(1), Some(BigInt(0)))) } private def haveDCache = tileParams.dcache.get.scratch.isEmpty override def chickenCSR = { val mask = BigInt( tileParams.dcache.get.clockGate.toInt << 0 \| rocketParams.clockGate.toInt << 1 \| rocketParams.clockGate.toInt << 2 \| 1 << 3 \| // disableSpeculativeICacheRefill haveDCache.toInt << 9 \| // suppressCorruptOnGrantData tileParams.icache.get.prefetch.toInt << 17 ) Some(CustomCSR(chickenCSRId, mask, Some(mask))) } def disableICachePrefetch = getOrElse(chickenCSR, _.value(17), true.B) def marchid = CustomCSR.constant(CSRs.marchid, BigInt(1)) def mvendorid = CustomCSR.constant(CSRs.mvendorid, BigInt(rocketParams.mvendorid)) // mimpid encodes a release version in the form of a BCD-encoded datestamp. def mimpid = CustomCSR.constant(CSRs.mimpid, BigInt(rocketParams.mimpid)) override def decls = super.decls :+ marchid :+ mvendorid :+ mimpid } class CoreInterrupts(val hasBeu: Boolean)(implicit p: Parameters) extends TileInterrupts()(p) { val buserror = Option.when(hasBeu)(Bool()) } trait HasRocketCoreIO extends HasRocketCoreParameters { implicit val p: Parameters def nTotalRoCCCSRs: Int val io = IO(new CoreBundle()(p) { val hartid = Input(UInt(hartIdLen.W)) val reset_vector = Input(UInt(resetVectorLen.W)) val interrupts = Input(new CoreInterrupts(tileParams.asInstanceOf[RocketTileParams].beuAddr.isDefined)) val imem = new FrontendIO val dmem = new HellaCacheIO val ptw = Flipped(new DatapathPTWIO()) val fpu = Flipped(new FPUCoreIO()) val rocc = Flipped(new RoCCCoreIO(nTotalRoCCCSRs)) val trace = Output(new TraceBundle) val bpwatch = Output(Vec(coreParams.nBreakpoints, new BPWatch(coreParams.retireWidth))) val cease = Output(Bool()) val wfi = Output(Bool()) val traceStall = Input(Bool()) val vector = if (usingVector) Some(Flipped(new VectorCoreIO)) else None }) } class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p) with HasRocketCoreParameters with HasRocketCoreIO { def nTotalRoCCCSRs = tile.roccCSRs.flatten.size import ALU._ val clock_en_reg = RegInit(true.B) val long_latency_stall = Reg(Bool()) val id_reg_pause = Reg(Bool()) val imem_might_request_reg = Reg(Bool()) val clock_en = WireDefault(true.B) val gated_clock = if (!rocketParams.clockGate) clock else ClockGate(clock, clock_en, "rocket_clock_gate") class RocketImpl { // entering gated-clock domain // performance counters def pipelineIDToWB[T <: Data](x: T): T = RegEnable(RegEnable(RegEnable(x, !ctrl_killd), ex_pc_valid), mem_pc_valid) val perfEvents = new EventSets(Seq( new EventSet((mask, hits) => Mux(wb_xcpt, mask(0), wb_valid && pipelineIDToWB((mask & hits).orR)), Seq( ("exception", () => false.B), ("load", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XRD && !id_ctrl.fp), ("store", () => id_ctrl.mem && id_ctrl.mem_cmd === M_XWR && !id_ctrl.fp), ("amo", () => usingAtomics.B && id_ctrl.mem && (isAMO(id_ctrl.mem_cmd) \|\| id_ctrl.mem_cmd.isOneOf(M_XLR, M_XSC))), ("system", () => id_ctrl.csr =/= CSR.N), ("arith", () => id_ctrl.wxd && !(id_ctrl.jal \|\| id_ctrl.jalr \|\| id_ctrl.mem \|\| id_ctrl.fp \|\| id_ctrl.mul \|\| id_ctrl.div \|\| id_ctrl.csr =/= CSR.N)), ("branch", () => id_ctrl.branch), ("jal", () => id_ctrl.jal), ("jalr", () => id_ctrl.jalr)) ++ (if (!usingMulDiv) Seq() else Seq( ("mul", () => if (pipelinedMul) id_ctrl.mul else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) =/= FN_DIV), ("div", () => if (pipelinedMul) id_ctrl.div else id_ctrl.div && (id_ctrl.alu_fn & FN_DIV) === FN_DIV))) ++ (if (!usingFPU) Seq() else Seq( ("fp load", () => id_ctrl.fp && io.fpu.dec.ldst && io.fpu.dec.wen), ("fp store", () => id_ctrl.fp && io.fpu.dec.ldst && !io.fpu.dec.wen), ("fp add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.swap23), ("fp mul", () => id_ctrl.fp && io.fpu.dec.fma && !io.fpu.dec.swap23 && !io.fpu.dec.ren3), ("fp mul-add", () => id_ctrl.fp && io.fpu.dec.fma && io.fpu.dec.ren3), ("fp div/sqrt", () => id_ctrl.fp && (io.fpu.dec.div \|\| io.fpu.dec.sqrt)), ("fp other", () => id_ctrl.fp && !(io.fpu.dec.ldst \|\| io.fpu.dec.fma \|\| io.fpu.dec.div \|\| io.fpu.dec.sqrt))))), new EventSet((mask, hits) => (mask & hits).orR, Seq( ("load-use interlock", () => id_ex_hazard && ex_ctrl.mem \|\| id_mem_hazard && mem_ctrl.mem \|\| id_wb_hazard && wb_ctrl.mem), ("long-latency interlock", () => id_sboard_hazard), ("csr interlock", () => id_ex_hazard && ex_ctrl.csr =/= CSR.N \|\| id_mem_hazard && mem_ctrl.csr =/= CSR.N \|\| id_wb_hazard && wb_ctrl.csr =/= CSR.N), ("I$ blocked", () => icache_blocked), ("D$ blocked", () => id_ctrl.mem && dcache_blocked), ("branch misprediction", () => take_pc_mem && mem_direction_misprediction), ("control-flow target misprediction", () => take_pc_mem && mem_misprediction && mem_cfi && !mem_direction_misprediction && !icache_blocked), ("flush", () => wb_reg_flush_pipe), ("replay", () => replay_wb)) ++ (if (!usingMulDiv) Seq() else Seq( ("mul/div interlock", () => id_ex_hazard && (ex_ctrl.mul \|\| ex_ctrl.div) \|\| id_mem_hazard && (mem_ctrl.mul \|\| mem_ctrl.div) \|\| id_wb_hazard && wb_ctrl.div))) ++ (if (!usingFPU) Seq() else Seq( ("fp interlock", () => id_ex_hazard && ex_ctrl.fp \|\| id_mem_hazard && mem_ctrl.fp \|\| id_wb_hazard && wb_ctrl.fp \|\| id_ctrl.fp && id_stall_fpu)))), new EventSet((mask, hits) => (mask & hits).orR, Seq( ("I$ miss", () => io.imem.perf.acquire), ("D$ miss", () => io.dmem.perf.acquire), ("D$ release", () => io.dmem.perf.release), ("ITLB miss", () => io.imem.perf.tlbMiss), ("DTLB miss", () => io.dmem.perf.tlbMiss), ("L2 TLB miss", () => io.ptw.perf.l2miss))))) val pipelinedMul = usingMulDiv && mulDivParams.mulUnroll == xLen val decode_table = { (if (usingMulDiv) new MDecode(pipelinedMul) +: (xLen > 32).option(new M64Decode(pipelinedMul)).toSeq else Nil) ++: (if (usingAtomics) new ADecode +: (xLen > 32).option(new A64Decode).toSeq else Nil) ++: (if (fLen >= 32) new FDecode +: (xLen > 32).option(new F64Decode).toSeq else Nil) ++: (if (fLen >= 64) new DDecode +: (xLen > 32).option(new D64Decode).toSeq else Nil) ++: (if (minFLen == 16) new HDecode +: (xLen > 32).option(new H64Decode).toSeq ++: (fLen >= 64).option(new HDDecode).toSeq else Nil) ++: (usingRoCC.option(new RoCCDecode)) ++: (if (xLen == 32) new I32Decode else new I64Decode) +: (usingVM.option(new SVMDecode)) ++: (usingSupervisor.option(new SDecode)) ++: (usingHypervisor.option(new HypervisorDecode)) ++: ((usingHypervisor && (xLen == 64)).option(new Hypervisor64Decode)) ++: (usingDebug.option(new DebugDecode)) ++: (usingNMI.option(new NMIDecode)) ++: (usingConditionalZero.option(new ConditionalZeroDecode)) ++: Seq(new FenceIDecode(tile.dcache.flushOnFenceI)) ++: coreParams.haveCFlush.option(new CFlushDecode(tile.dcache.canSupportCFlushLine)) ++: rocketParams.haveCease.option(new CeaseDecode) ++: usingVector.option(new VCFGDecode) ++: (if (coreParams.useZba) new ZbaDecode +: (xLen > 32).option(new Zba64Decode).toSeq else Nil) ++: (if (coreParams.useZbb) Seq(new ZbbDecode, if (xLen == 32) new Zbb32Decode else new Zbb64Decode) else Nil) ++: coreParams.useZbs.option(new ZbsDecode) ++: Seq(new IDecode) } flatMap(_.table) val ex_ctrl = Reg(new IntCtrlSigs) val mem_ctrl = Reg(new IntCtrlSigs) val wb_ctrl = Reg(new IntCtrlSigs) val ex_reg_xcpt_interrupt = Reg(Bool()) val ex_reg_valid = Reg(Bool()) val ex_reg_rvc = Reg(Bool()) val ex_reg_btb_resp = Reg(new BTBResp) val ex_reg_xcpt = Reg(Bool()) val ex_reg_flush_pipe = Reg(Bool()) val ex_reg_load_use = Reg(Bool()) val ex_reg_cause = Reg(UInt()) val ex_reg_replay = Reg(Bool()) val ex_reg_pc = Reg(UInt()) val ex_reg_mem_size = Reg(UInt()) val ex_reg_hls = Reg(Bool()) val ex_reg_inst = Reg(Bits()) val ex_reg_raw_inst = Reg(UInt()) val ex_reg_wphit = Reg(Vec(nBreakpoints, Bool())) val ex_reg_set_vconfig = Reg(Bool()) val mem_reg_xcpt_interrupt = Reg(Bool()) val mem_reg_valid = Reg(Bool()) val mem_reg_rvc = Reg(Bool()) val mem_reg_btb_resp = Reg(new BTBResp) val mem_reg_xcpt = Reg(Bool()) val mem_reg_replay = Reg(Bool()) val mem_reg_flush_pipe = Reg(Bool()) val mem_reg_cause = Reg(UInt()) val mem_reg_slow_bypass = Reg(Bool()) val mem_reg_load = Reg(Bool()) val mem_reg_store = Reg(Bool()) val mem_reg_set_vconfig = Reg(Bool()) val mem_reg_sfence = Reg(Bool()) val mem_reg_pc = Reg(UInt()) val mem_reg_inst = Reg(Bits()) val mem_reg_mem_size = Reg(UInt()) val mem_reg_hls_or_dv = Reg(Bool()) val mem_reg_raw_inst = Reg(UInt()) val mem_reg_wdata = Reg(Bits()) val mem_reg_rs2 = Reg(Bits()) val mem_br_taken = Reg(Bool()) val take_pc_mem = Wire(Bool()) val mem_reg_wphit = Reg(Vec(nBreakpoints, Bool())) val wb_reg_valid = Reg(Bool()) val wb_reg_xcpt = Reg(Bool()) val wb_reg_replay = Reg(Bool()) val wb_reg_flush_pipe = Reg(Bool()) val wb_reg_cause = Reg(UInt()) val wb_reg_set_vconfig = Reg(Bool()) val wb_reg_sfence = Reg(Bool()) val wb_reg_pc = Reg(UInt()) val wb_reg_mem_size = Reg(UInt()) val wb_reg_hls_or_dv = Reg(Bool()) val wb_reg_hfence_v = Reg(Bool()) val wb_reg_hfence_g = Reg(Bool()) val wb_reg_inst = Reg(Bits()) val wb_reg_raw_inst = Reg(UInt()) val wb_reg_wdata = Reg(Bits()) val wb_reg_rs2 = Reg(Bits()) val take_pc_wb = Wire(Bool()) val wb_reg_wphit = Reg(Vec(nBreakpoints, Bool())) val take_pc_mem_wb = take_pc_wb \|\| take_pc_mem val take_pc = take_pc_mem_wb // decode stage val ibuf = Module(new IBuf) val id_expanded_inst = ibuf.io.inst.map(_.bits.inst) val id_raw_inst = ibuf.io.inst.map(_.bits.raw) val id_inst = id_expanded_inst.map(_.bits) ibuf.io.imem <> io.imem.resp ibuf.io.kill := take_pc require(decodeWidth == 1 / TODO / && retireWidth == decodeWidth) require(!(coreParams.useRVE && coreParams.fpu.nonEmpty), "Can't select both RVE and floating-point") require(!(coreParams.useRVE && coreParams.useHypervisor), "Can't select both RVE and Hypervisor") val id_ctrl = Wire(new IntCtrlSigs).decode(id_inst(0), decode_table) val lgNXRegs = if (coreParams.useRVE) 4 else 5 val regAddrMask = (1 << lgNXRegs) - 1 def decodeReg(x: UInt) = (x.extract(x.getWidth-1, lgNXRegs).asBool, x(lgNXRegs-1, 0)) val (id_raddr3_illegal, id_raddr3) = decodeReg(id_expanded_inst(0).rs3) val (id_raddr2_illegal, id_raddr2) = decodeReg(id_expanded_inst(0).rs2) val (id_raddr1_illegal, id_raddr1) = decodeReg(id_expanded_inst(0).rs1) val (id_waddr_illegal, id_waddr) = decodeReg(id_expanded_inst(0).rd) val id_load_use = Wire(Bool()) val id_reg_fence = RegInit(false.B) val id_ren = IndexedSeq(id_ctrl.rxs1, id_ctrl.rxs2) val id_raddr = IndexedSeq(id_raddr1, id_raddr2) val rf = new RegFile(regAddrMask, xLen) val id_rs = id_raddr.map(rf.read _) val ctrl_killd = Wire(Bool()) val id_npc = (ibuf.io.pc.asSInt + ImmGen(IMM_UJ, id_inst(0))).asUInt val csr = Module(new CSRFile(perfEvents, coreParams.customCSRs.decls, tile.roccCSRs.flatten, tile.rocketParams.beuAddr.isDefined)) val id_csr_en = id_ctrl.csr.isOneOf(CSR.S, CSR.C, CSR.W) val id_system_insn = id_ctrl.csr === CSR.I val id_csr_ren = id_ctrl.csr.isOneOf(CSR.S, CSR.C) && id_expanded_inst(0).rs1 === 0.U val id_csr = Mux(id_system_insn && id_ctrl.mem, CSR.N, Mux(id_csr_ren, CSR.R, id_ctrl.csr)) val id_csr_flush = id_system_insn \|\| (id_csr_en && !id_csr_ren && csr.io.decode(0).write_flush) val id_set_vconfig = Seq(Instructions.VSETVLI, Instructions.VSETIVLI, Instructions.VSETVL).map(_ === id_inst(0)).orR && usingVector.B id_ctrl.vec := false.B if (usingVector) { val v_decode = rocketParams.vector.get.decoder(p) v_decode.io.inst := id_inst(0) v_decode.io.vconfig := csr.io.vector.get.vconfig when (v_decode.io.legal) { id_ctrl.legal := !csr.io.vector.get.vconfig.vtype.vill id_ctrl.fp := v_decode.io.fp id_ctrl.rocc := false.B id_ctrl.branch := false.B id_ctrl.jal := false.B id_ctrl.jalr := false.B id_ctrl.rxs2 := v_decode.io.read_rs2 id_ctrl.rxs1 := v_decode.io.read_rs1 id_ctrl.mem := false.B id_ctrl.rfs1 := v_decode.io.read_frs1 id_ctrl.rfs2 := false.B id_ctrl.rfs3 := false.B id_ctrl.wfd := v_decode.io.write_frd id_ctrl.mul := false.B id_ctrl.div := false.B id_ctrl.wxd := v_decode.io.write_rd id_ctrl.csr := CSR.N id_ctrl.fence_i := false.B id_ctrl.fence := false.B id_ctrl.amo := false.B id_ctrl.dp := false.B id_ctrl.vec := true.B } } val id_illegal_insn = !id_ctrl.legal \|\| (id_ctrl.mul \|\| id_ctrl.div) && !csr.io.status.isa('m'-'a') \|\| id_ctrl.amo && !csr.io.status.isa('a'-'a') \|\| id_ctrl.fp && (csr.io.decode(0).fp_illegal \|\| (io.fpu.illegal_rm && !id_ctrl.vec)) \|\| (id_ctrl.vec) && (csr.io.decode(0).vector_illegal \|\| csr.io.vector.map(_.vconfig.vtype.vill).getOrElse(false.B)) \|\| id_ctrl.dp && !csr.io.status.isa('d'-'a') \|\| ibuf.io.inst(0).bits.rvc && !csr.io.status.isa('c'-'a') \|\| id_raddr2_illegal && id_ctrl.rxs2 \|\| id_raddr1_illegal && id_ctrl.rxs1 \|\| id_waddr_illegal && id_ctrl.wxd \|\| id_ctrl.rocc && csr.io.decode(0).rocc_illegal \|\| id_csr_en && (csr.io.decode(0).read_illegal \|\| !id_csr_ren && csr.io.decode(0).write_illegal) \|\| !ibuf.io.inst(0).bits.rvc && (id_system_insn && csr.io.decode(0).system_illegal) val id_virtual_insn = id_ctrl.legal && ((id_csr_en && !(!id_csr_ren && csr.io.decode(0).write_illegal) && csr.io.decode(0).virtual_access_illegal) \|\| (!ibuf.io.inst(0).bits.rvc && id_system_insn && csr.io.decode(0).virtual_system_illegal)) // stall decode for fences (now, for AMO.rl; later, for AMO.aq and FENCE) val id_amo_aq = id_inst(0)(26) val id_amo_rl = id_inst(0)(25) val id_fence_pred = id_inst(0)(27,24) val id_fence_succ = id_inst(0)(23,20) val id_fence_next = id_ctrl.fence \|\| id_ctrl.amo && id_amo_aq val id_mem_busy = !io.dmem.ordered \|\| io.dmem.req.valid when (!id_mem_busy) { id_reg_fence := false.B } val id_rocc_busy = usingRoCC.B && (io.rocc.busy \|\| ex_reg_valid && ex_ctrl.rocc \|\| mem_reg_valid && mem_ctrl.rocc \|\| wb_reg_valid && wb_ctrl.rocc) val id_csr_rocc_write = tile.roccCSRs.flatten.map(_.id.U === id_inst(0)(31,20)).orR && id_csr_en && !id_csr_ren val id_vec_busy = io.vector.map(v => v.backend_busy \|\| v.trap_check_busy).getOrElse(false.B) val id_do_fence = WireDefault(id_rocc_busy && (id_ctrl.fence \|\| id_csr_rocc_write) \|\| id_vec_busy && id_ctrl.fence \|\| id_mem_busy && (id_ctrl.amo && id_amo_rl \|\| id_ctrl.fence_i \|\| id_reg_fence && (id_ctrl.mem \|\| id_ctrl.rocc))) val bpu = Module(new BreakpointUnit(nBreakpoints)) bpu.io.status := csr.io.status bpu.io.bp := csr.io.bp bpu.io.pc := ibuf.io.pc bpu.io.ea := mem_reg_wdata bpu.io.mcontext := csr.io.mcontext bpu.io.scontext := csr.io.scontext val id_xcpt0 = ibuf.io.inst(0).bits.xcpt0 val id_xcpt1 = ibuf.io.inst(0).bits.xcpt1 val (id_xcpt, id_cause) = checkExceptions(List( (csr.io.interrupt, csr.io.interrupt_cause), (bpu.io.debug_if, CSR.debugTriggerCause.U), (bpu.io.xcpt_if, Causes.breakpoint.U), (id_xcpt0.pf.inst, Causes.fetch_page_fault.U), (id_xcpt0.gf.inst, Causes.fetch_guest_page_fault.U), (id_xcpt0.ae.inst, Causes.fetch_access.U), (id_xcpt1.pf.inst, Causes.fetch_page_fault.U), (id_xcpt1.gf.inst, Causes.fetch_guest_page_fault.U), (id_xcpt1.ae.inst, Causes.fetch_access.U), (id_virtual_insn, Causes.virtual_instruction.U), (id_illegal_insn, Causes.illegal_instruction.U))) val idCoverCauses = List( (CSR.debugTriggerCause, "DEBUG_TRIGGER"), (Causes.breakpoint, "BREAKPOINT"), (Causes.fetch_access, "FETCH_ACCESS"), (Causes.illegal_instruction, "ILLEGAL_INSTRUCTION") ) ++ (if (usingVM) List( (Causes.fetch_page_fault, "FETCH_PAGE_FAULT") ) else Nil) coverExceptions(id_xcpt, id_cause, "DECODE", idCoverCauses) val dcache_bypass_data = if (fastLoadByte) io.dmem.resp.bits.data(xLen-1, 0) else if (fastLoadWord) io.dmem.resp.bits.data_word_bypass(xLen-1, 0) else wb_reg_wdata // detect bypass opportunities val ex_waddr = ex_reg_inst(11,7) & regAddrMask.U val mem_waddr = mem_reg_inst(11,7) & regAddrMask.U val wb_waddr = wb_reg_inst(11,7) & regAddrMask.U val bypass_sources = IndexedSeq( (true.B, 0.U, 0.U), // treat reading x0 as a bypass (ex_reg_valid && ex_ctrl.wxd, ex_waddr, mem_reg_wdata), (mem_reg_valid && mem_ctrl.wxd && !mem_ctrl.mem, mem_waddr, wb_reg_wdata), (mem_reg_valid && mem_ctrl.wxd, mem_waddr, dcache_bypass_data)) val id_bypass_src = id_raddr.map(raddr => bypass_sources.map(s => s._1 && s._2 === raddr)) // execute stage val bypass_mux = bypass_sources.map(_._3) val ex_reg_rs_bypass = Reg(Vec(id_raddr.size, Bool())) val ex_reg_rs_lsb = Reg(Vec(id_raddr.size, UInt(log2Ceil(bypass_sources.size).W))) val ex_reg_rs_msb = Reg(Vec(id_raddr.size, UInt())) val ex_rs = for (i <- 0 until id_raddr.size) yield Mux(ex_reg_rs_bypass(i), bypass_mux(ex_reg_rs_lsb(i)), Cat(ex_reg_rs_msb(i), ex_reg_rs_lsb(i))) val ex_imm = ImmGen(ex_ctrl.sel_imm, ex_reg_inst) val ex_rs1shl = Mux(ex_reg_inst(3), ex_rs(0)(31,0), ex_rs(0)) << ex_reg_inst(14,13) val ex_op1 = MuxLookup(ex_ctrl.sel_alu1, 0.S)(Seq( A1_RS1 -> ex_rs(0).asSInt, A1_PC -> ex_reg_pc.asSInt, A1_RS1SHL -> (if (rocketParams.useZba) ex_rs1shl.asSInt else 0.S) )) val ex_op2_oh = UIntToOH(Mux(ex_ctrl.sel_alu2(0), (ex_reg_inst >> 20).asUInt, ex_rs(1))(log2Ceil(xLen)-1,0)).asSInt val ex_op2 = MuxLookup(ex_ctrl.sel_alu2, 0.S)(Seq( A2_RS2 -> ex_rs(1).asSInt, A2_IMM -> ex_imm, A2_SIZE -> Mux(ex_reg_rvc, 2.S, 4.S), ) ++ (if (coreParams.useZbs) Seq( A2_RS2OH -> ex_op2_oh, A2_IMMOH -> ex_op2_oh, ) else Nil)) val (ex_new_vl, ex_new_vconfig) = if (usingVector) { val ex_new_vtype = VType.fromUInt(MuxCase(ex_rs(1), Seq( ex_reg_inst(31,30).andR -> ex_reg_inst(29,20), !ex_reg_inst(31) -> ex_reg_inst(30,20)))) val ex_avl = Mux(ex_ctrl.rxs1, Mux(ex_reg_inst(19,15) === 0.U, Mux(ex_reg_inst(11,7) === 0.U, csr.io.vector.get.vconfig.vl, ex_new_vtype.vlMax), ex_rs(0) ), ex_reg_inst(19,15)) val ex_new_vl = ex_new_vtype.vl(ex_avl, csr.io.vector.get.vconfig.vl, false.B, false.B, false.B) val ex_new_vconfig = Wire(new VConfig) ex_new_vconfig.vtype := ex_new_vtype ex_new_vconfig.vl := ex_new_vl (Some(ex_new_vl), Some(ex_new_vconfig)) } else { (None, None) } val alu = Module(new ALU) alu.io.dw := ex_ctrl.alu_dw alu.io.fn := ex_ctrl.alu_fn alu.io.in2 := ex_op2.asUInt alu.io.in1 := ex_op1.asUInt // multiplier and divider val div = Module(new MulDiv(if (pipelinedMul) mulDivParams.copy(mulUnroll = 0) else mulDivParams, width = xLen)) div.io.req.valid := ex_reg_valid && ex_ctrl.div div.io.req.bits.dw := ex_ctrl.alu_dw div.io.req.bits.fn := ex_ctrl.alu_fn div.io.req.bits.in1 := ex_rs(0) div.io.req.bits.in2 := ex_rs(1) div.io.req.bits.tag := ex_waddr val mul = pipelinedMul.option { val m = Module(new PipelinedMultiplier(xLen, 2)) m.io.req.valid := ex_reg_valid && ex_ctrl.mul m.io.req.bits := div.io.req.bits m } ex_reg_valid := !ctrl_killd ex_reg_replay := !take_pc && ibuf.io.inst(0).valid && ibuf.io.inst(0).bits.replay ex_reg_xcpt := !ctrl_killd && id_xcpt ex_reg_xcpt_interrupt := !take_pc && ibuf.io.inst(0).valid && csr.io.interrupt when (!ctrl_killd) { ex_ctrl := id_ctrl ex_reg_rvc := ibuf.io.inst(0).bits.rvc ex_ctrl.csr := id_csr when (id_ctrl.fence && id_fence_succ === 0.U) { id_reg_pause := true.B } when (id_fence_next) { id_reg_fence := true.B } when (id_xcpt) { // pass PC down ALU writeback pipeline for badaddr ex_ctrl.alu_fn := FN_ADD ex_ctrl.alu_dw := DW_XPR ex_ctrl.sel_alu1 := A1_RS1 // badaddr := instruction ex_ctrl.sel_alu2 := A2_ZERO when (id_xcpt1.asUInt.orR) { // badaddr := PC+2 ex_ctrl.sel_alu1 := A1_PC ex_ctrl.sel_alu2 := A2_SIZE ex_reg_rvc := true.B } when (bpu.io.xcpt_if \|\| id_xcpt0.asUInt.orR) { // badaddr := PC ex_ctrl.sel_alu1 := A1_PC ex_ctrl.sel_alu2 := A2_ZERO } } ex_reg_flush_pipe := id_ctrl.fence_i \|\| id_csr_flush ex_reg_load_use := id_load_use ex_reg_hls := usingHypervisor.B && id_system_insn && id_ctrl.mem_cmd.isOneOf(M_XRD, M_XWR, M_HLVX) ex_reg_mem_size := Mux(usingHypervisor.B && id_system_insn, id_inst(0)(27, 26), id_inst(0)(13, 12)) when (id_ctrl.mem_cmd.isOneOf(M_SFENCE, M_HFENCEV, M_HFENCEG, M_FLUSH_ALL)) { ex_reg_mem_size := Cat(id_raddr2 =/= 0.U, id_raddr1 =/= 0.U) } when (id_ctrl.mem_cmd === M_SFENCE && csr.io.status.v) { ex_ctrl.mem_cmd := M_HFENCEV } if (tile.dcache.flushOnFenceI) { when (id_ctrl.fence_i) { ex_reg_mem_size := 0.U } } for (i <- 0 until id_raddr.size) { val do_bypass = id_bypass_src(i).reduce(_\|\|_) val bypass_src = PriorityEncoder(id_bypass_src(i)) ex_reg_rs_bypass(i) := do_bypass ex_reg_rs_lsb(i) := bypass_src when (id_ren(i) && !do_bypass) { ex_reg_rs_lsb(i) := id_rs(i)(log2Ceil(bypass_sources.size)-1, 0) ex_reg_rs_msb(i) := id_rs(i) >> log2Ceil(bypass_sources.size) } } when (id_illegal_insn \|\| id_virtual_insn) { val inst = Mux(ibuf.io.inst(0).bits.rvc, id_raw_inst(0)(15, 0), id_raw_inst(0)) ex_reg_rs_bypass(0) := false.B ex_reg_rs_lsb(0) := inst(log2Ceil(bypass_sources.size)-1, 0) ex_reg_rs_msb(0) := inst >> log2Ceil(bypass_sources.size) } } when (!ctrl_killd \|\| csr.io.interrupt \|\| ibuf.io.inst(0).bits.replay) { ex_reg_cause := id_cause ex_reg_inst := id_inst(0) ex_reg_raw_inst := id_raw_inst(0) ex_reg_pc := ibuf.io.pc ex_reg_btb_resp := ibuf.io.btb_resp ex_reg_wphit := bpu.io.bpwatch.map { bpw => bpw.ivalid(0) } ex_reg_set_vconfig := id_set_vconfig && !id_xcpt } // replay inst in ex stage? val ex_pc_valid = ex_reg_valid \|\| ex_reg_replay \|\| ex_reg_xcpt_interrupt val wb_dcache_miss = wb_ctrl.mem && !io.dmem.resp.valid val replay_ex_structural = ex_ctrl.mem && !io.dmem.req.ready \|\| ex_ctrl.div && !div.io.req.ready \|\| ex_ctrl.vec && !io.vector.map(_.ex.ready).getOrElse(true.B) val replay_ex_load_use = wb_dcache_miss && ex_reg_load_use val replay_ex = ex_reg_replay \|\| (ex_reg_valid && (replay_ex_structural \|\| replay_ex_load_use)) val ctrl_killx = take_pc_mem_wb \|\| replay_ex \|\| !ex_reg_valid // detect 2-cycle load-use delay for LB/LH/SC val ex_slow_bypass = ex_ctrl.mem_cmd === M_XSC \|\| ex_reg_mem_size < 2.U val ex_sfence = usingVM.B && ex_ctrl.mem && (ex_ctrl.mem_cmd === M_SFENCE \|\| ex_ctrl.mem_cmd === M_HFENCEV \|\| ex_ctrl.mem_cmd === M_HFENCEG) val (ex_xcpt, ex_cause) = checkExceptions(List( (ex_reg_xcpt_interrupt \|\| ex_reg_xcpt, ex_reg_cause))) val exCoverCauses = idCoverCauses coverExceptions(ex_xcpt, ex_cause, "EXECUTE", exCoverCauses) // memory stage val mem_pc_valid = mem_reg_valid \|\| mem_reg_replay \|\| mem_reg_xcpt_interrupt val mem_br_target = mem_reg_pc.asSInt + Mux(mem_ctrl.branch && mem_br_taken, ImmGen(IMM_SB, mem_reg_inst), Mux(mem_ctrl.jal, ImmGen(IMM_UJ, mem_reg_inst), Mux(mem_reg_rvc, 2.S, 4.S))) val mem_npc = (Mux(mem_ctrl.jalr \|\| mem_reg_sfence, encodeVirtualAddress(mem_reg_wdata, mem_reg_wdata).asSInt, mem_br_target) & (-2).S).asUInt val mem_wrong_npc = Mux(ex_pc_valid, mem_npc =/= ex_reg_pc, Mux(ibuf.io.inst(0).valid \|\| ibuf.io.imem.valid, mem_npc =/= ibuf.io.pc, true.B)) val mem_npc_misaligned = !csr.io.status.isa('c'-'a') && mem_npc(1) && !mem_reg_sfence val mem_int_wdata = Mux(!mem_reg_xcpt && (mem_ctrl.jalr ^ mem_npc_misaligned), mem_br_target, mem_reg_wdata.asSInt).asUInt val mem_cfi = mem_ctrl.branch \|\| mem_ctrl.jalr \|\| mem_ctrl.jal val mem_cfi_taken = (mem_ctrl.branch && mem_br_taken) \|\| mem_ctrl.jalr \|\| mem_ctrl.jal val mem_direction_misprediction = mem_ctrl.branch && mem_br_taken =/= (usingBTB.B && mem_reg_btb_resp.taken) val mem_misprediction = if (usingBTB) mem_wrong_npc else mem_cfi_taken take_pc_mem := mem_reg_valid && !mem_reg_xcpt && (mem_misprediction \|\| mem_reg_sfence) mem_reg_valid := !ctrl_killx mem_reg_replay := !take_pc_mem_wb && replay_ex mem_reg_xcpt := !ctrl_killx && ex_xcpt mem_reg_xcpt_interrupt := !take_pc_mem_wb && ex_reg_xcpt_interrupt // on pipeline flushes, cause mem_npc to hold the sequential npc, which // will drive the W-stage npc mux when (mem_reg_valid && mem_reg_flush_pipe) { mem_reg_sfence := false.B }.elsewhen (ex_pc_valid) { mem_ctrl := ex_ctrl mem_reg_rvc := ex_reg_rvc mem_reg_load := ex_ctrl.mem && isRead(ex_ctrl.mem_cmd) mem_reg_store := ex_ctrl.mem && isWrite(ex_ctrl.mem_cmd) mem_reg_sfence := ex_sfence mem_reg_btb_resp := ex_reg_btb_resp mem_reg_flush_pipe := ex_reg_flush_pipe mem_reg_slow_bypass := ex_slow_bypass mem_reg_wphit := ex_reg_wphit mem_reg_set_vconfig := ex_reg_set_vconfig mem_reg_cause := ex_cause mem_reg_inst := ex_reg_inst mem_reg_raw_inst := ex_reg_raw_inst mem_reg_mem_size := ex_reg_mem_size mem_reg_hls_or_dv := io.dmem.req.bits.dv mem_reg_pc := ex_reg_pc // IDecode ensured they are 1H mem_reg_wdata := Mux(ex_reg_set_vconfig, ex_new_vl.getOrElse(alu.io.out), alu.io.out) mem_br_taken := alu.io.cmp_out when (ex_ctrl.rxs2 && (ex_ctrl.mem \|\| ex_ctrl.rocc \|\| ex_sfence)) { val size = Mux(ex_ctrl.rocc, log2Ceil(xLen/8).U, ex_reg_mem_size) mem_reg_rs2 := new StoreGen(size, 0.U, ex_rs(1), coreDataBytes).data } if (usingVector) { when (ex_reg_set_vconfig) { mem_reg_rs2 := ex_new_vconfig.get.asUInt } } when (ex_ctrl.jalr && csr.io.status.debug) { // flush I$ on D-mode JALR to effect uncached fetch without D$ flush mem_ctrl.fence_i := true.B mem_reg_flush_pipe := true.B } } val mem_breakpoint = (mem_reg_load && bpu.io.xcpt_ld) \|\| (mem_reg_store && bpu.io.xcpt_st) val mem_debug_breakpoint = (mem_reg_load && bpu.io.debug_ld) \|\| (mem_reg_store && bpu.io.debug_st) val (mem_ldst_xcpt, mem_ldst_cause) = checkExceptions(List( (mem_debug_breakpoint, CSR.debugTriggerCause.U), (mem_breakpoint, Causes.breakpoint.U))) val (mem_xcpt, mem_cause) = checkExceptions(List( (mem_reg_xcpt_interrupt \|\| mem_reg_xcpt, mem_reg_cause), (mem_reg_valid && mem_npc_misaligned, Causes.misaligned_fetch.U), (mem_reg_valid && mem_ldst_xcpt, mem_ldst_cause))) val memCoverCauses = (exCoverCauses ++ List( (CSR.debugTriggerCause, "DEBUG_TRIGGER"), (Causes.breakpoint, "BREAKPOINT"), (Causes.misaligned_fetch, "MISALIGNED_FETCH") )).distinct coverExceptions(mem_xcpt, mem_cause, "MEMORY", memCoverCauses) val dcache_kill_mem = mem_reg_valid && mem_ctrl.wxd && io.dmem.replay_next // structural hazard on writeback port val fpu_kill_mem = mem_reg_valid && mem_ctrl.fp && io.fpu.nack_mem val vec_kill_mem = mem_reg_valid && mem_ctrl.mem && io.vector.map(_.mem.block_mem).getOrElse(false.B) val vec_kill_all = mem_reg_valid && io.vector.map(_.mem.block_all).getOrElse(false.B) val replay_mem = dcache_kill_mem \|\| mem_reg_replay \|\| fpu_kill_mem \|\| vec_kill_mem \|\| vec_kill_all val killm_common = dcache_kill_mem \|\| take_pc_wb \|\| mem_reg_xcpt \|\| !mem_reg_valid div.io.kill := killm_common && RegNext(div.io.req.fire) val ctrl_killm = killm_common \|\| mem_xcpt \|\| fpu_kill_mem \|\| vec_kill_mem // writeback stage wb_reg_valid := !ctrl_killm wb_reg_replay := replay_mem && !take_pc_wb wb_reg_xcpt := mem_xcpt && !take_pc_wb && !io.vector.map(_.mem.block_all).getOrElse(false.B) wb_reg_flush_pipe := !ctrl_killm && mem_reg_flush_pipe when (mem_pc_valid) { wb_ctrl := mem_ctrl wb_reg_sfence := mem_reg_sfence wb_reg_wdata := Mux(!mem_reg_xcpt && mem_ctrl.fp && mem_ctrl.wxd, io.fpu.toint_data, mem_int_wdata) when (mem_ctrl.rocc \|\| mem_reg_sfence \|\| mem_reg_set_vconfig) { wb_reg_rs2 := mem_reg_rs2 } wb_reg_cause := mem_cause wb_reg_inst := mem_reg_inst wb_reg_raw_inst := mem_reg_raw_inst wb_reg_mem_size := mem_reg_mem_size wb_reg_hls_or_dv := mem_reg_hls_or_dv wb_reg_hfence_v := mem_ctrl.mem_cmd === M_HFENCEV wb_reg_hfence_g := mem_ctrl.mem_cmd === M_HFENCEG wb_reg_pc := mem_reg_pc wb_reg_wphit := mem_reg_wphit \| bpu.io.bpwatch.map { bpw => (bpw.rvalid(0) && mem_reg_load) \|\| (bpw.wvalid(0) && mem_reg_store) } wb_reg_set_vconfig := mem_reg_set_vconfig } val (wb_xcpt, wb_cause) = checkExceptions(List( (wb_reg_xcpt, wb_reg_cause), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.st, Causes.store_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.pf.ld, Causes.load_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.st, Causes.store_guest_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.gf.ld, Causes.load_guest_page_fault.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.st, Causes.store_access.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ae.ld, Causes.load_access.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.st, Causes.misaligned_store.U), (wb_reg_valid && wb_ctrl.mem && io.dmem.s2_xcpt.ma.ld, Causes.misaligned_load.U) )) val wbCoverCauses = List( (Causes.misaligned_store, "MISALIGNED_STORE"), (Causes.misaligned_load, "MISALIGNED_LOAD"), (Causes.store_access, "STORE_ACCESS"), (Causes.load_access, "LOAD_ACCESS") ) ++ (if(usingVM) List( (Causes.store_page_fault, "STORE_PAGE_FAULT"), (Causes.load_page_fault, "LOAD_PAGE_FAULT") ) else Nil) ++ (if (usingHypervisor) List( (Causes.store_guest_page_fault, "STORE_GUEST_PAGE_FAULT"), (Causes.load_guest_page_fault, "LOAD_GUEST_PAGE_FAULT"), ) else Nil) coverExceptions(wb_xcpt, wb_cause, "WRITEBACK", wbCoverCauses) val wb_pc_valid = wb_reg_valid \|\| wb_reg_replay \|\| wb_reg_xcpt val wb_wxd = wb_reg_valid && wb_ctrl.wxd val wb_set_sboard = wb_ctrl.div \|\| wb_dcache_miss \|\| wb_ctrl.rocc \|\| wb_ctrl.vec val replay_wb_common = io.dmem.s2_nack \|\| wb_reg_replay val replay_wb_rocc = wb_reg_valid && wb_ctrl.rocc && !io.rocc.cmd.ready val replay_wb_csr: Bool = wb_reg_valid && csr.io.rw_stall val replay_wb_vec = wb_reg_valid && io.vector.map(_.wb.replay).getOrElse(false.B) val replay_wb = replay_wb_common \|\| replay_wb_rocc \|\| replay_wb_csr \|\| replay_wb_vec take_pc_wb := replay_wb \|\| wb_xcpt \|\| csr.io.eret \|\| wb_reg_flush_pipe // writeback arbitration val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).asBool val dmem_resp_fpu = io.dmem.resp.bits.tag(0).asBool val dmem_resp_waddr = io.dmem.resp.bits.tag(5, 1) val dmem_resp_valid = io.dmem.resp.valid && io.dmem.resp.bits.has_data val dmem_resp_replay = dmem_resp_valid && io.dmem.resp.bits.replay class LLWB extends Bundle { val data = UInt(xLen.W) val tag = UInt(5.W) } val ll_arb = Module(new Arbiter(new LLWB, 3)) // div, rocc, vec ll_arb.io.in.foreach(_.valid := false.B) ll_arb.io.in.foreach(_.bits := DontCare) val ll_wdata = WireInit(ll_arb.io.out.bits.data) val ll_waddr = WireInit(ll_arb.io.out.bits.tag) val ll_wen = WireInit(ll_arb.io.out.fire) ll_arb.io.out.ready := !wb_wxd div.io.resp.ready := ll_arb.io.in(0).ready ll_arb.io.in(0).valid := div.io.resp.valid ll_arb.io.in(0).bits.data := div.io.resp.bits.data ll_arb.io.in(0).bits.tag := div.io.resp.bits.tag if (usingRoCC) { io.rocc.resp.ready := ll_arb.io.in(1).ready ll_arb.io.in(1).valid := io.rocc.resp.valid ll_arb.io.in(1).bits.data := io.rocc.resp.bits.data ll_arb.io.in(1).bits.tag := io.rocc.resp.bits.rd } else { // tie off RoCC io.rocc.resp.ready := false.B io.rocc.mem.req.ready := false.B } io.vector.map { v => v.resp.ready := Mux(v.resp.bits.fp, !(dmem_resp_valid && dmem_resp_fpu), ll_arb.io.in(2).ready) ll_arb.io.in(2).valid := v.resp.valid && !v.resp.bits.fp ll_arb.io.in(2).bits.data := v.resp.bits.data ll_arb.io.in(2).bits.tag := v.resp.bits.rd } // Dont care mem since not all RoCC need accessing memory io.rocc.mem := DontCare when (dmem_resp_replay && dmem_resp_xpu) { ll_arb.io.out.ready := false.B ll_waddr := dmem_resp_waddr ll_wen := true.B } val wb_valid = wb_reg_valid && !replay_wb && !wb_xcpt val wb_wen = wb_valid && wb_ctrl.wxd val rf_wen = wb_wen \|\| ll_wen val rf_waddr = Mux(ll_wen, ll_waddr, wb_waddr) val rf_wdata = Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data(xLen-1, 0), Mux(ll_wen, ll_wdata, Mux(wb_ctrl.csr =/= CSR.N, csr.io.rw.rdata, Mux(wb_ctrl.mul, mul.map(_.io.resp.bits.data).getOrElse(wb_reg_wdata), wb_reg_wdata)))) when (rf_wen) { rf.write(rf_waddr, rf_wdata) } // hook up control/status regfile csr.io.ungated_clock := clock csr.io.decode(0).inst := id_inst(0) csr.io.exception := wb_xcpt csr.io.cause := wb_cause csr.io.retire := wb_valid csr.io.inst(0) := (if (usingCompressed) Cat(Mux(wb_reg_raw_inst(1, 0).andR, wb_reg_inst >> 16, 0.U), wb_reg_raw_inst(15, 0)) else wb_reg_inst) csr.io.interrupts := io.interrupts csr.io.hartid := io.hartid io.fpu.fcsr_rm := csr.io.fcsr_rm val vector_fcsr_flags = io.vector.map(_.set_fflags.bits).getOrElse(0.U(5.W)) val vector_fcsr_flags_valid = io.vector.map(_.set_fflags.valid).getOrElse(false.B) csr.io.fcsr_flags.valid := io.fpu.fcsr_flags.valid \| vector_fcsr_flags_valid csr.io.fcsr_flags.bits := (io.fpu.fcsr_flags.bits & Fill(5, io.fpu.fcsr_flags.valid)) \| (vector_fcsr_flags & Fill(5, vector_fcsr_flags_valid)) io.fpu.time := csr.io.time(31,0) io.fpu.hartid := io.hartid csr.io.rocc_interrupt := io.rocc.interrupt csr.io.pc := wb_reg_pc val tval_dmem_addr = !wb_reg_xcpt val tval_any_addr = tval_dmem_addr \|\| wb_reg_cause.isOneOf(Causes.breakpoint.U, Causes.fetch_access.U, Causes.fetch_page_fault.U, Causes.fetch_guest_page_fault.U) val tval_inst = wb_reg_cause === Causes.illegal_instruction.U val tval_valid = wb_xcpt && (tval_any_addr \|\| tval_inst) csr.io.gva := wb_xcpt && (tval_any_addr && csr.io.status.v \|\| tval_dmem_addr && wb_reg_hls_or_dv) csr.io.tval := Mux(tval_valid, encodeVirtualAddress(wb_reg_wdata, wb_reg_wdata), 0.U) val (htval, mhtinst_read_pseudo) = { val htval_valid_imem = wb_reg_xcpt && wb_reg_cause === Causes.fetch_guest_page_fault.U val htval_imem = Mux(htval_valid_imem, io.imem.gpa.bits, 0.U) assert(!htval_valid_imem \|\| io.imem.gpa.valid) val htval_valid_dmem = wb_xcpt && tval_dmem_addr && io.dmem.s2_xcpt.gf.asUInt.orR && !io.dmem.s2_xcpt.pf.asUInt.orR val htval_dmem = Mux(htval_valid_dmem, io.dmem.s2_gpa, 0.U) val htval = (htval_dmem \| htval_imem) >> hypervisorExtraAddrBits // read pseudoinstruction if a guest-page fault is caused by an implicit memory access for VS-stage address translation val mhtinst_read_pseudo = (io.imem.gpa_is_pte && htval_valid_imem) \|\| (io.dmem.s2_gpa_is_pte && htval_valid_dmem) (htval, mhtinst_read_pseudo) } csr.io.vector.foreach { v => v.set_vconfig.valid := wb_reg_set_vconfig && wb_reg_valid v.set_vconfig.bits := wb_reg_rs2.asTypeOf(new VConfig) v.set_vs_dirty := wb_valid && wb_ctrl.vec v.set_vstart.valid := wb_valid && wb_reg_set_vconfig v.set_vstart.bits := 0.U } io.vector.foreach { v => when (v.wb.retire \|\| v.wb.xcpt \|\| wb_ctrl.vec) { csr.io.pc := v.wb.pc csr.io.retire := v.wb.retire csr.io.inst(0) := v.wb.inst when (v.wb.xcpt && !wb_reg_xcpt) { wb_xcpt := true.B wb_cause := v.wb.cause csr.io.tval := v.wb.tval } } v.wb.store_pending := io.dmem.store_pending v.wb.vxrm := csr.io.vector.get.vxrm v.wb.frm := csr.io.fcsr_rm csr.io.vector.get.set_vxsat := v.set_vxsat when (v.set_vconfig.valid) { csr.io.vector.get.set_vconfig.valid := true.B csr.io.vector.get.set_vconfig.bits := v.set_vconfig.bits } when (v.set_vstart.valid) { csr.io.vector.get.set_vstart.valid := true.B csr.io.vector.get.set_vstart.bits := v.set_vstart.bits } } csr.io.htval := htval csr.io.mhtinst_read_pseudo := mhtinst_read_pseudo io.ptw.ptbr := csr.io.ptbr io.ptw.hgatp := csr.io.hgatp io.ptw.vsatp := csr.io.vsatp (io.ptw.customCSRs.csrs zip csr.io.customCSRs).map { case (lhs, rhs) => lhs <> rhs } io.ptw.status := csr.io.status io.ptw.hstatus := csr.io.hstatus io.ptw.gstatus := csr.io.gstatus io.ptw.pmp := csr.io.pmp csr.io.rw.addr := wb_reg_inst(31,20) csr.io.rw.cmd := CSR.maskCmd(wb_reg_valid, wb_ctrl.csr) csr.io.rw.wdata := wb_reg_wdata io.rocc.csrs <> csr.io.roccCSRs io.trace.time := csr.io.time io.trace.insns := csr.io.trace if (rocketParams.debugROB.isDefined) { val sz = rocketParams.debugROB.get.size if (sz < 1) { // use unsynthesizable ROB val csr_trace_with_wdata = WireInit(csr.io.trace(0)) csr_trace_with_wdata.wdata.get := rf_wdata val should_wb = WireInit((wb_ctrl.wfd \|\| (wb_ctrl.wxd && wb_waddr =/= 0.U)) && !csr.io.trace(0).exception) val has_wb = WireInit(wb_ctrl.wxd && wb_wen && !wb_set_sboard) val wb_addr = WireInit(wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U)) io.vector.foreach { v => when (v.wb.retire) { should_wb := v.wb.rob_should_wb has_wb := false.B wb_addr := Cat(v.wb.rob_should_wb_fp, csr_trace_with_wdata.insn(11,7)) }} DebugROB.pushTrace(clock, reset, io.hartid, csr_trace_with_wdata, should_wb, has_wb, wb_addr) io.trace.insns(0) := DebugROB.popTrace(clock, reset, io.hartid) DebugROB.pushWb(clock, reset, io.hartid, ll_wen, rf_waddr, rf_wdata) } else { // synthesizable ROB (no FPRs) require(!usingVector, "Synthesizable ROB does not support vector implementations") val csr_trace_with_wdata = WireInit(csr.io.trace(0)) csr_trace_with_wdata.wdata.get := rf_wdata val debug_rob = Module(new HardDebugROB(sz, 32)) debug_rob.io.i_insn := csr_trace_with_wdata debug_rob.io.should_wb := (wb_ctrl.wfd \|\| (wb_ctrl.wxd && wb_waddr =/= 0.U)) && !csr.io.trace(0).exception debug_rob.io.has_wb := wb_ctrl.wxd && wb_wen && !wb_set_sboard debug_rob.io.tag := wb_waddr + Mux(wb_ctrl.wfd, 32.U, 0.U) debug_rob.io.wb_val := ll_wen debug_rob.io.wb_tag := rf_waddr debug_rob.io.wb_data := rf_wdata io.trace.insns(0) := debug_rob.io.o_insn } } else { io.trace.insns := csr.io.trace } for (((iobpw, wphit), bp) <- io.bpwatch zip wb_reg_wphit zip csr.io.bp) { iobpw.valid(0) := wphit iobpw.action := bp.control.action // tie off bpwatch valids iobpw.rvalid.foreach(_ := false.B) iobpw.wvalid.foreach(_ := false.B) iobpw.ivalid.foreach(_ := false.B) } val hazard_targets = Seq((id_ctrl.rxs1 && id_raddr1 =/= 0.U, id_raddr1), (id_ctrl.rxs2 && id_raddr2 =/= 0.U, id_raddr2), (id_ctrl.wxd && id_waddr =/= 0.U, id_waddr)) val fp_hazard_targets = Seq((io.fpu.dec.ren1, id_raddr1), (io.fpu.dec.ren2, id_raddr2), (io.fpu.dec.ren3, id_raddr3), (io.fpu.dec.wen, id_waddr)) val sboard = new Scoreboard(32, true) sboard.clear(ll_wen, ll_waddr) def id_sboard_clear_bypass(r: UInt) = { // ll_waddr arrives late when D$ has ECC, so reshuffle the hazard check if (!tileParams.dcache.get.dataECC.isDefined) ll_wen && ll_waddr === r else div.io.resp.fire && div.io.resp.bits.tag === r \|\| dmem_resp_replay && dmem_resp_xpu && dmem_resp_waddr === r } val id_sboard_hazard = checkHazards(hazard_targets, rd => sboard.read(rd) && !id_sboard_clear_bypass(rd)) sboard.set(wb_set_sboard && wb_wen, wb_waddr) // stall for RAW/WAW hazards on CSRs, loads, AMOs, and mul/div in execute stage. val ex_cannot_bypass = ex_ctrl.csr =/= CSR.N \|\| ex_ctrl.jalr \|\| ex_ctrl.mem \|\| ex_ctrl.mul \|\| ex_ctrl.div \|\| ex_ctrl.fp \|\| ex_ctrl.rocc \|\| ex_ctrl.vec val data_hazard_ex = ex_ctrl.wxd && checkHazards(hazard_targets, _ === ex_waddr) val fp_data_hazard_ex = id_ctrl.fp && ex_ctrl.wfd && checkHazards(fp_hazard_targets, _ === ex_waddr) val id_ex_hazard = ex_reg_valid && (data_hazard_ex && ex_cannot_bypass \|\| fp_data_hazard_ex) // stall for RAW/WAW hazards on CSRs, LB/LH, and mul/div in memory stage. val mem_mem_cmd_bh = if (fastLoadWord) (!fastLoadByte).B && mem_reg_slow_bypass else true.B val mem_cannot_bypass = mem_ctrl.csr =/= CSR.N \|\| mem_ctrl.mem && mem_mem_cmd_bh \|\| mem_ctrl.mul \|\| mem_ctrl.div \|\| mem_ctrl.fp \|\| mem_ctrl.rocc \|\| mem_ctrl.vec val data_hazard_mem = mem_ctrl.wxd && checkHazards(hazard_targets, _ === mem_waddr) val fp_data_hazard_mem = id_ctrl.fp && mem_ctrl.wfd && checkHazards(fp_hazard_targets, _ === mem_waddr) val id_mem_hazard = mem_reg_valid && (data_hazard_mem && mem_cannot_bypass \|\| fp_data_hazard_mem) id_load_use := mem_reg_valid && data_hazard_mem && mem_ctrl.mem val id_vconfig_hazard = id_ctrl.vec && ( (ex_reg_valid && ex_reg_set_vconfig) \|\| (mem_reg_valid && mem_reg_set_vconfig) \|\| (wb_reg_valid && wb_reg_set_vconfig)) // stall for RAW/WAW hazards on load/AMO misses and mul/div in writeback. val data_hazard_wb = wb_ctrl.wxd && checkHazards(hazard_targets, _ === wb_waddr) val fp_data_hazard_wb = id_ctrl.fp && wb_ctrl.wfd && checkHazards(fp_hazard_targets, _ === wb_waddr) val id_wb_hazard = wb_reg_valid && (data_hazard_wb && wb_set_sboard \|\| fp_data_hazard_wb) val id_stall_fpu = if (usingFPU) { val fp_sboard = new Scoreboard(32) fp_sboard.set(((wb_dcache_miss \|\| wb_ctrl.vec) && wb_ctrl.wfd \|\| io.fpu.sboard_set) && wb_valid, wb_waddr) val v_ll = io.vector.map(v => v.resp.fire && v.resp.bits.fp).getOrElse(false.B) fp_sboard.clear((dmem_resp_replay && dmem_resp_fpu) \|\| v_ll, io.fpu.ll_resp_tag) fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra) checkHazards(fp_hazard_targets, fp_sboard.read _) } else false.B val dcache_blocked = { // speculate that a blocked D$ will unblock the cycle after a Grant val blocked = Reg(Bool()) blocked := !io.dmem.req.ready && io.dmem.clock_enabled && !io.dmem.perf.grant && (blocked \|\| io.dmem.req.valid \|\| io.dmem.s2_nack) blocked && !io.dmem.perf.grant } val rocc_blocked = Reg(Bool()) rocc_blocked := !wb_xcpt && !io.rocc.cmd.ready && (io.rocc.cmd.valid \|\| rocc_blocked) val ctrl_stalld = id_ex_hazard \|\| id_mem_hazard \|\| id_wb_hazard \|\| id_sboard_hazard \|\| id_vconfig_hazard \|\| csr.io.singleStep && (ex_reg_valid \|\| mem_reg_valid \|\| wb_reg_valid) \|\| id_csr_en && csr.io.decode(0).fp_csr && !io.fpu.fcsr_rdy \|\| id_csr_en && csr.io.decode(0).vector_csr && id_vec_busy \|\| id_ctrl.fp && id_stall_fpu \|\| id_ctrl.mem && dcache_blocked \|\| // reduce activity during D$ misses id_ctrl.rocc && rocc_blocked \|\| // reduce activity while RoCC is busy id_ctrl.div && (!(div.io.req.ready \|\| (div.io.resp.valid && !wb_wxd)) \|\| div.io.req.valid) \|\| // reduce odds of replay !clock_en \|\| id_do_fence \|\| csr.io.csr_stall \|\| id_reg_pause \|\| io.traceStall ctrl_killd := !ibuf.io.inst(0).valid \|\| ibuf.io.inst(0).bits.replay \|\| take_pc_mem_wb \|\| ctrl_stalld \|\| csr.io.interrupt io.imem.req.valid := take_pc io.imem.req.bits.speculative := !take_pc_wb io.imem.req.bits.pc := Mux(wb_xcpt \|\| csr.io.eret, csr.io.evec, // exception or [m\|s]ret Mux(replay_wb, wb_reg_pc, // replay mem_npc)) // flush or branch misprediction io.imem.flush_icache := wb_reg_valid && wb_ctrl.fence_i && !io.dmem.s2_nack io.imem.might_request := { imem_might_request_reg := ex_pc_valid \|\| mem_pc_valid \|\| io.ptw.customCSRs.disableICacheClockGate \|\| io.vector.map(_.trap_check_busy).getOrElse(false.B) imem_might_request_reg } io.imem.progress := RegNext(wb_reg_valid && !replay_wb_common) io.imem.sfence.valid := wb_reg_valid && wb_reg_sfence io.imem.sfence.bits.rs1 := wb_reg_mem_size(0) io.imem.sfence.bits.rs2 := wb_reg_mem_size(1) io.imem.sfence.bits.addr := wb_reg_wdata io.imem.sfence.bits.asid := wb_reg_rs2 io.imem.sfence.bits.hv := wb_reg_hfence_v io.imem.sfence.bits.hg := wb_reg_hfence_g io.ptw.sfence := io.imem.sfence ibuf.io.inst(0).ready := !ctrl_stalld io.imem.btb_update.valid := mem_reg_valid && !take_pc_wb && mem_wrong_npc && (!mem_cfi \|\| mem_cfi_taken) io.imem.btb_update.bits.isValid := mem_cfi io.imem.btb_update.bits.cfiType := Mux((mem_ctrl.jal \|\| mem_ctrl.jalr) && mem_waddr(0), CFIType.call, Mux(mem_ctrl.jalr && (mem_reg_inst(19,15) & regAddrMask.U) === BitPat("b00?01"), CFIType.ret, Mux(mem_ctrl.jal \|\| mem_ctrl.jalr, CFIType.jump, CFIType.branch))) io.imem.btb_update.bits.target := io.imem.req.bits.pc io.imem.btb_update.bits.br_pc := (if (usingCompressed) mem_reg_pc + Mux(mem_reg_rvc, 0.U, 2.U) else mem_reg_pc) io.imem.btb_update.bits.pc := ~(~io.imem.btb_update.bits.br_pc \| (coreInstBytesfetchWidth-1).U) io.imem.btb_update.bits.prediction := mem_reg_btb_resp io.imem.btb_update.bits.taken := DontCare io.imem.bht_update.valid := mem_reg_valid && !take_pc_wb io.imem.bht_update.bits.pc := io.imem.btb_update.bits.pc io.imem.bht_update.bits.taken := mem_br_taken io.imem.bht_update.bits.mispredict := mem_wrong_npc io.imem.bht_update.bits.branch := mem_ctrl.branch io.imem.bht_update.bits.prediction := mem_reg_btb_resp.bht // Connect RAS in Frontend io.imem.ras_update := DontCare io.fpu.valid := !ctrl_killd && id_ctrl.fp io.fpu.killx := ctrl_killx io.fpu.killm := killm_common io.fpu.inst := id_inst(0) io.fpu.fromint_data := ex_rs(0) io.fpu.ll_resp_val := dmem_resp_valid && dmem_resp_fpu io.fpu.ll_resp_data := (if (minFLen == 32) io.dmem.resp.bits.data_word_bypass else io.dmem.resp.bits.data) io.fpu.ll_resp_type := io.dmem.resp.bits.size io.fpu.ll_resp_tag := dmem_resp_waddr io.fpu.keep_clock_enabled := io.ptw.customCSRs.disableCoreClockGate io.fpu.v_sew := csr.io.vector.map(_.vconfig.vtype.vsew).getOrElse(0.U) io.vector.map { v => when (!(dmem_resp_valid && dmem_resp_fpu)) { io.fpu.ll_resp_val := v.resp.valid && v.resp.bits.fp io.fpu.ll_resp_data := v.resp.bits.data io.fpu.ll_resp_type := v.resp.bits.size io.fpu.ll_resp_tag := v.resp.bits.rd } } io.vector.foreach { v => v.ex.valid := ex_reg_valid && (ex_ctrl.vec \|\| rocketParams.vector.get.issueVConfig.B && ex_reg_set_vconfig) && !ctrl_killx v.ex.inst := ex_reg_inst v.ex.vconfig := csr.io.vector.get.vconfig v.ex.vstart := Mux(mem_reg_valid && mem_ctrl.vec \|\| wb_reg_valid && wb_ctrl.vec, 0.U, csr.io.vector.get.vstart) v.ex.rs1 := ex_rs(0) v.ex.rs2 := ex_rs(1) v.ex.pc := ex_reg_pc v.mem.frs1 := io.fpu.store_data v.killm := killm_common v.status := csr.io.status } io.dmem.req.valid := ex_reg_valid && ex_ctrl.mem val ex_dcache_tag = Cat(ex_waddr, ex_ctrl.fp) require(coreParams.dcacheReqTagBits >= ex_dcache_tag.getWidth) io.dmem.req.bits.tag := ex_dcache_tag io.dmem.req.bits.cmd := ex_ctrl.mem_cmd io.dmem.req.bits.size := ex_reg_mem_size io.dmem.req.bits.signed := !Mux(ex_reg_hls, ex_reg_inst(20), ex_reg_inst(14)) io.dmem.req.bits.phys := false.B io.dmem.req.bits.addr := encodeVirtualAddress(ex_rs(0), alu.io.adder_out) io.dmem.req.bits.idx.foreach(_ := io.dmem.req.bits.addr) io.dmem.req.bits.dprv := Mux(ex_reg_hls, csr.io.hstatus.spvp, csr.io.status.dprv) io.dmem.req.bits.dv := ex_reg_hls \|\| csr.io.status.dv io.dmem.req.bits.no_resp := !isRead(ex_ctrl.mem_cmd) \|\| (!ex_ctrl.fp && ex_waddr === 0.U) io.dmem.req.bits.no_alloc := DontCare io.dmem.req.bits.no_xcpt := DontCare io.dmem.req.bits.data := DontCare io.dmem.req.bits.mask := DontCare io.dmem.s1_data.data := (if (fLen == 0) mem_reg_rs2 else Mux(mem_ctrl.fp, Fill(coreDataBits / fLen, io.fpu.store_data), mem_reg_rs2)) io.dmem.s1_data.mask := DontCare io.dmem.s1_kill := killm_common \|\| mem_ldst_xcpt \|\| fpu_kill_mem \|\| vec_kill_mem io.dmem.s2_kill := false.B // don't let D$ go to sleep if we're probably going to use it soon io.dmem.keep_clock_enabled := ibuf.io.inst(0).valid && id_ctrl.mem && !csr.io.csr_stall io.rocc.cmd.valid := wb_reg_valid && wb_ctrl.rocc && !replay_wb_common io.rocc.exception := wb_xcpt && csr.io.status.xs.orR io.rocc.cmd.bits.status := csr.io.status io.rocc.cmd.bits.inst := wb_reg_inst.asTypeOf(new RoCCInstruction()) io.rocc.cmd.bits.rs1 := wb_reg_wdata io.rocc.cmd.bits.rs2 := wb_reg_rs2 // gate the clock val unpause = csr.io.time(rocketParams.lgPauseCycles-1, 0) === 0.U \|\| csr.io.inhibit_cycle \|\| io.dmem.perf.release \|\| take_pc when (unpause) { id_reg_pause := false.B } io.cease := csr.io.status.cease && !clock_en_reg io.wfi := csr.io.status.wfi if (rocketParams.clockGate) { long_latency_stall := csr.io.csr_stall \|\| io.dmem.perf.blocked \|\| id_reg_pause && !unpause clock_en := clock_en_reg \|\| ex_pc_valid \|\| (!long_latency_stall && io.imem.resp.valid) clock_en_reg := ex_pc_valid \|\| mem_pc_valid \|\| wb_pc_valid \|\| // instruction in flight io.ptw.customCSRs.disableCoreClockGate \|\| // chicken bit !div.io.req.ready \|\| // mul/div in flight usingFPU.B && !io.fpu.fcsr_rdy \|\| // long-latency FPU in flight io.dmem.replay_next \|\| // long-latency load replaying (!long_latency_stall && (ibuf.io.inst(0).valid \|\| io.imem.resp.valid)) // instruction pending assert(!(ex_pc_valid \|\| mem_pc_valid \|\| wb_pc_valid) \|\| clock_en) } // evaluate performance counters val icache_blocked = !(io.imem.resp.valid \|\| RegNext(io.imem.resp.valid)) csr.io.counters foreach { c => c.inc := RegNext(perfEvents.evaluate(c.eventSel)) } val coreMonitorBundle = Wire(new CoreMonitorBundle(xLen, fLen)) coreMonitorBundle.clock := clock coreMonitorBundle.reset := reset coreMonitorBundle.hartid := io.hartid coreMonitorBundle.timer := csr.io.time(31,0) coreMonitorBundle.valid := csr.io.trace(0).valid && !csr.io.trace(0).exception coreMonitorBundle.pc := csr.io.trace(0).iaddr(vaddrBitsExtended-1, 0).sextTo(xLen) coreMonitorBundle.wrenx := wb_wen && !wb_set_sboard coreMonitorBundle.wrenf := false.B coreMonitorBundle.wrdst := wb_waddr coreMonitorBundle.wrdata := rf_wdata coreMonitorBundle.rd0src := wb_reg_inst(19,15) coreMonitorBundle.rd0val := RegNext(RegNext(ex_rs(0))) coreMonitorBundle.rd1src := wb_reg_inst(24,20) coreMonitorBundle.rd1val := RegNext(RegNext(ex_rs(1))) coreMonitorBundle.inst := csr.io.trace(0).insn coreMonitorBundle.excpt := csr.io.trace(0).exception coreMonitorBundle.priv_mode := csr.io.trace(0).priv if (enableCommitLog) { val t = csr.io.trace(0) val rd = wb_waddr val wfd = wb_ctrl.wfd val wxd = wb_ctrl.wxd val has_data = wb_wen && !wb_set_sboard when (t.valid && !t.exception) { when (wfd) { printf ("%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd+32.U) } .elsewhen (wxd && rd =/= 0.U && has_data) { printf ("%d 0x%x (0x%x) x%d 0x%x\n", t.priv, t.iaddr, t.insn, rd, rf_wdata) } .elsewhen (wxd && rd =/= 0.U && !has_data) { printf ("%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd) } .otherwise { printf ("%d 0x%x (0x%x)\n", t.priv, t.iaddr, t.insn) } } when (ll_wen && rf_waddr =/= 0.U) { printf ("x%d p%d 0x%x\n", rf_waddr, rf_waddr, rf_wdata) } } else { when (csr.io.trace(0).valid) { printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", io.hartid, coreMonitorBundle.timer, coreMonitorBundle.valid, coreMonitorBundle.pc, Mux(wb_ctrl.wxd \|\| wb_ctrl.wfd, coreMonitorBundle.wrdst, 0.U), Mux(coreMonitorBundle.wrenx, coreMonitorBundle.wrdata, 0.U), coreMonitorBundle.wrenx, Mux(wb_ctrl.rxs1 \|\| wb_ctrl.rfs1, coreMonitorBundle.rd0src, 0.U), Mux(wb_ctrl.rxs1 \|\| wb_ctrl.rfs1, coreMonitorBundle.rd0val, 0.U), Mux(wb_ctrl.rxs2 \|\| wb_ctrl.rfs2, coreMonitorBundle.rd1src, 0.U), Mux(wb_ctrl.rxs2 \|\| wb_ctrl.rfs2, coreMonitorBundle.rd1val, 0.U), coreMonitorBundle.inst, coreMonitorBundle.inst) } } // CoreMonitorBundle for late latency writes val xrfWriteBundle = Wire(new CoreMonitorBundle(xLen, fLen)) xrfWriteBundle.clock := clock xrfWriteBundle.reset := reset xrfWriteBundle.hartid := io.hartid xrfWriteBundle.timer := csr.io.time(31,0) xrfWriteBundle.valid := false.B xrfWriteBundle.pc := 0.U xrfWriteBundle.wrdst := rf_waddr xrfWriteBundle.wrenx := rf_wen && !(csr.io.trace(0).valid && wb_wen && (wb_waddr === rf_waddr)) xrfWriteBundle.wrenf := false.B xrfWriteBundle.wrdata := rf_wdata xrfWriteBundle.rd0src := 0.U xrfWriteBundle.rd0val := 0.U xrfWriteBundle.rd1src := 0.U xrfWriteBundle.rd1val := 0.U xrfWriteBundle.inst := 0.U xrfWriteBundle.excpt := false.B xrfWriteBundle.priv_mode := csr.io.trace(0).priv if (rocketParams.haveSimTimeout) PlusArg.timeout( name = "max_core_cycles", docstring = "Kill the emulation after INT rdtime cycles. Off if 0." )(csr.io.time) } // leaving gated-clock domain val rocketImpl = withClock (gated_clock) { new RocketImpl } def checkExceptions(x: Seq[(Bool, UInt)]) = (WireInit(x.map(_._1).reduce(_\|\|_)), WireInit(PriorityMux(x))) def coverExceptions(exceptionValid: Bool, cause: UInt, labelPrefix: String, coverCausesLabels: Seq[(Int, String)]): Unit = { for ((coverCause, label) <- coverCausesLabels) { property.cover(exceptionValid && (cause === coverCause.U), s"${labelPrefix}_${label}") } } def checkHazards(targets: Seq[(Bool, UInt)], cond: UInt => Bool) = targets.map(h => h._1 && cond(h._2)).reduce(_\|\|_) def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) ea else { // efficient means to compress 64-bit VA into vaddrBits+1 bits // (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)) val b = vaddrBitsExtended-1 val a = (a0 >> b).asSInt val msb = Mux(a === 0.S \|\| a === -1.S, ea(b), !ea(b-1)) Cat(msb, ea(b-1, 0)) } class Scoreboard(n: Int, zero: Boolean = false) { def set(en: Bool, addr: UInt): Unit = update(en, _next \| mask(en, addr)) def clear(en: Bool, addr: UInt): Unit = update(en, _next & ~mask(en, addr)) def read(addr: UInt): Bool = r(addr) def readBypassed(addr: UInt): Bool = _next(addr) private val _r = RegInit(0.U(n.W)) private val r = if (zero) (_r >> 1 << 1) else _r private var _next = r private var ens = false.B private def mask(en: Bool, addr: UInt) = Mux(en, 1.U << addr, 0.U) private def update(en: Bool, update: UInt) = { _next = update ens = ens \|\| en when (ens) { _r := _next } } } } class RegFile(n: Int, w: Int, zero: Boolean = false) { val rf = Mem(n, UInt(w.W)) private def access(addr: UInt) = rf(~addr(log2Up(n)-1,0)) private val reads = ArrayBuffer[(UInt,UInt)]() private var canRead = true def read(addr: UInt) = { require(canRead) reads += addr -> Wire(UInt()) reads.last._2 := Mux(zero.B && addr === 0.U, 0.U, access(addr)) reads.last._2 } def write(addr: UInt, data: UInt) = { canRead = false when (addr =/= 0.U) { access(addr) := data for ((raddr, rdata) <- reads) when (addr === raddr) { rdata := data } } } } object ImmGen { def apply(sel: UInt, inst: UInt) = { val sign = Mux(sel === IMM_Z, 0.S, inst(31).asSInt) val b30_20 = Mux(sel === IMM_U, inst(30,20).asSInt, sign) val b19_12 = Mux(sel =/= IMM_U && sel =/= IMM_UJ, sign, inst(19,12).asSInt) val b11 = Mux(sel === IMM_U \|\| sel === IMM_Z, 0.S, Mux(sel === IMM_UJ, inst(20).asSInt, Mux(sel === IMM_SB, inst(7).asSInt, sign))) val b10_5 = Mux(sel === IMM_U \|\| sel === IMM_Z, 0.U, inst(30,25)) val b4_1 = Mux(sel === IMM_U, 0.U, Mux(sel === IMM_S \|\| sel === IMM_SB, inst(11,8), Mux(sel === IMM_Z, inst(19,16), inst(24,21)))) val b0 = Mux(sel === IMM_S, inst(7), Mux(sel === IMM_I, inst(20), Mux(sel === IMM_Z, inst(15), 0.U))) Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0).asSInt } } File AMOALU.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.Parameters class StoreGen(typ: UInt, addr: UInt, dat: UInt, maxSize: Int) { val size = Wire(UInt(log2Up(log2Up(maxSize)+1).W)) size := typ val dat_padded = dat.pad(maxSize8) def misaligned: Bool = (addr & ((1.U << size) - 1.U)(log2Up(maxSize)-1,0)).orR def mask = { var res = 1.U for (i <- 0 until log2Up(maxSize)) { val upper = Mux(addr(i), res, 0.U) \| Mux(size >= (i+1).U, ((BigInt(1) << (1 << i))-1).U, 0.U) val lower = Mux(addr(i), 0.U, res) res = Cat(upper, lower) } res } protected def genData(i: Int): UInt = if (i >= log2Up(maxSize)) dat_padded else Mux(size === i.U, Fill(1 << (log2Up(maxSize)-i), dat_padded((8 << i)-1,0)), genData(i+1)) def data = genData(0) def wordData = genData(2) } class LoadGen(typ: UInt, signed: Bool, addr: UInt, dat: UInt, zero: Bool, maxSize: Int) { private val size = new StoreGen(typ, addr, dat, maxSize).size private def genData(logMinSize: Int): UInt = { var res = dat for (i <- log2Up(maxSize)-1 to logMinSize by -1) { val pos = 8 << i val shifted = Mux(addr(i), res(2pos-1,pos), res(pos-1,0)) val doZero = (i == 0).B && zero val zeroed = Mux(doZero, 0.U, shifted) res = Cat(Mux(size === i.U \|\| doZero, Fill(8maxSize-pos, signed && zeroed(pos-1)), res(8maxSize-1,pos)), zeroed) } res } def wordData = genData(2) def data = genData(0) } class AMOALU(operandBits: Int)(implicit p: Parameters) extends Module { val minXLen = 32 val widths = (0 to log2Ceil(operandBits / minXLen)).map(minXLen << _) val io = IO(new Bundle { val mask = Input(UInt((operandBits / 8).W)) val cmd = Input(UInt(M_SZ.W)) val lhs = Input(UInt(operandBits.W)) val rhs = Input(UInt(operandBits.W)) val out = Output(UInt(operandBits.W)) val out_unmasked = Output(UInt(operandBits.W)) }) val max = io.cmd === M_XA_MAX \|\| io.cmd === M_XA_MAXU val min = io.cmd === M_XA_MIN \|\| io.cmd === M_XA_MINU val add = io.cmd === M_XA_ADD val logic_and = io.cmd === M_XA_OR \|\| io.cmd === M_XA_AND val logic_xor = io.cmd === M_XA_XOR \|\| io.cmd === M_XA_OR val adder_out = { // partition the carry chain to support sub-xLen addition val mask = ~(0.U(operandBits.W) +: widths.init.map(w => !io.mask(w/8-1) << (w-1))).reduce(_\|_) (io.lhs & mask) + (io.rhs & mask) } val less = { // break up the comparator so the lower parts will be CSE'd def isLessUnsigned(x: UInt, y: UInt, n: Int): Bool = { if (n == minXLen) x(n-1, 0) < y(n-1, 0) else x(n-1, n/2) < y(n-1, n/2) \|\| x(n-1, n/2) === y(n-1, n/2) && isLessUnsigned(x, y, n/2) } def isLess(x: UInt, y: UInt, n: Int): Bool = { val signed = { val mask = M_XA_MIN ^ M_XA_MINU (io.cmd & mask) === (M_XA_MIN & mask) } Mux(x(n-1) === y(n-1), isLessUnsigned(x, y, n), Mux(signed, x(n-1), y(n-1))) } PriorityMux(widths.reverse.map(w => (io.mask(w/8/2), isLess(io.lhs, io.rhs, w)))) } val minmax = Mux(Mux(less, min, max), io.lhs, io.rhs) val logic = Mux(logic_and, io.lhs & io.rhs, 0.U) \| Mux(logic_xor, io.lhs ^ io.rhs, 0.U) val out = Mux(add, adder_out, Mux(logic_and \|\| logic_xor, logic, minmax)) val wmask = FillInterleaved(8, io.mask) io.out := wmask & out \| ~wmask & io.lhs io.out_unmasked := out } File CSR.scala: // See LICENSE.SiFive for license details. // See LICENSE.Berkeley for license details. package freechips.rocketchip.rocket import chisel3._ import chisel3.util.{BitPat, Cat, Fill, Mux1H, PopCount, PriorityMux, RegEnable, UIntToOH, Valid, log2Ceil, log2Up} import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.devices.debug.DebugModuleKey import freechips.rocketchip.tile._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property import scala.collection.mutable.LinkedHashMap import Instructions._ import CustomInstructions._ class MStatus extends Bundle { // not truly part of mstatus, but convenient val debug = Bool() val cease = Bool() val wfi = Bool() val isa = UInt(32.W) val dprv = UInt(PRV.SZ.W) // effective prv for data accesses val dv = Bool() // effective v for data accesses val prv = UInt(PRV.SZ.W) val v = Bool() val sd = Bool() val zero2 = UInt(23.W) val mpv = Bool() val gva = Bool() val mbe = Bool() val sbe = Bool() val sxl = UInt(2.W) val uxl = UInt(2.W) val sd_rv32 = Bool() val zero1 = UInt(8.W) val tsr = Bool() val tw = Bool() val tvm = Bool() val mxr = Bool() val sum = Bool() val mprv = Bool() val xs = UInt(2.W) val fs = UInt(2.W) val mpp = UInt(2.W) val vs = UInt(2.W) val spp = UInt(1.W) val mpie = Bool() val ube = Bool() val spie = Bool() val upie = Bool() val mie = Bool() val hie = Bool() val sie = Bool() val uie = Bool() } class MNStatus extends Bundle { val mpp = UInt(2.W) val zero3 = UInt(3.W) val mpv = Bool() val zero2 = UInt(3.W) val mie = Bool() val zero1 = UInt(3.W) } class HStatus extends Bundle { val zero6 = UInt(30.W) val vsxl = UInt(2.W) val zero5 = UInt(9.W) val vtsr = Bool() val vtw = Bool() val vtvm = Bool() val zero3 = UInt(2.W) val vgein = UInt(6.W) val zero2 = UInt(2.W) val hu = Bool() val spvp = Bool() val spv = Bool() val gva = Bool() val vsbe = Bool() val zero1 = UInt(5.W) } class DCSR extends Bundle { val xdebugver = UInt(2.W) val zero4 = UInt(2.W) val zero3 = UInt(12.W) val ebreakm = Bool() val ebreakh = Bool() val ebreaks = Bool() val ebreaku = Bool() val zero2 = Bool() val stopcycle = Bool() val stoptime = Bool() val cause = UInt(3.W) val v = Bool() val zero1 = UInt(2.W) val step = Bool() val prv = UInt(PRV.SZ.W) } class MIP(implicit p: Parameters) extends CoreBundle()(p) with HasCoreParameters { val lip = Vec(coreParams.nLocalInterrupts, Bool()) val zero1 = Bool() val debug = Bool() // keep in sync with CSR.debugIntCause val rocc = Bool() val sgeip = Bool() val meip = Bool() val vseip = Bool() val seip = Bool() val ueip = Bool() val mtip = Bool() val vstip = Bool() val stip = Bool() val utip = Bool() val msip = Bool() val vssip = Bool() val ssip = Bool() val usip = Bool() } class Envcfg extends Bundle { val stce = Bool() // only for menvcfg/henvcfg val pbmte = Bool() // only for menvcfg/henvcfg val zero54 = UInt(54.W) val cbze = Bool() val cbcfe = Bool() val cbie = UInt(2.W) val zero3 = UInt(3.W) val fiom = Bool() def write(wdata: UInt) { val new_envcfg = wdata.asTypeOf(new Envcfg) fiom := new_envcfg.fiom // only FIOM is writable currently } } class PTBR(implicit p: Parameters) extends CoreBundle()(p) { def additionalPgLevels = mode.extract(log2Ceil(pgLevels-minPgLevels+1)-1, 0) def pgLevelsToMode(i: Int) = (xLen, i) match { case (32, 2) => 1 case (64, x) if x >= 3 && x <= 6 => x + 5 } val (modeBits, maxASIdBits) = xLen match { case 32 => (1, 9) case 64 => (4, 16) } require(modeBits + maxASIdBits + maxPAddrBits - pgIdxBits == xLen) val mode = UInt(modeBits.W) val asid = UInt(maxASIdBits.W) val ppn = UInt((maxPAddrBits - pgIdxBits).W) } object PRV { val SZ = 2 val U = 0 val S = 1 val H = 2 val M = 3 } object CSR { // commands val SZ = 3 def X = BitPat.dontCare(SZ) def N = 0.U(SZ.W) def R = 2.U(SZ.W) def I = 4.U(SZ.W) def W = 5.U(SZ.W) def S = 6.U(SZ.W) def C = 7.U(SZ.W) // mask a CSR cmd with a valid bit def maskCmd(valid: Bool, cmd: UInt): UInt = { // all commands less than CSR.I are treated by CSRFile as NOPs cmd & ~Mux(valid, 0.U, CSR.I) } val ADDRSZ = 12 def modeLSB: Int = 8 def mode(addr: Int): Int = (addr >> modeLSB) % (1 << PRV.SZ) def mode(addr: UInt): UInt = addr(modeLSB + PRV.SZ - 1, modeLSB) def busErrorIntCause = 128 def debugIntCause = 14 // keep in sync with MIP.debug def debugTriggerCause = { val res = debugIntCause require(!(Causes.all contains res)) res } def rnmiIntCause = 13 // NMI: Higher numbers = higher priority, must not reuse debugIntCause def rnmiBEUCause = 12 val firstCtr = CSRs.cycle val firstCtrH = CSRs.cycleh val firstHPC = CSRs.hpmcounter3 val firstHPCH = CSRs.hpmcounter3h val firstHPE = CSRs.mhpmevent3 val firstMHPC = CSRs.mhpmcounter3 val firstMHPCH = CSRs.mhpmcounter3h val firstHPM = 3 val nCtr = 32 val nHPM = nCtr - firstHPM val hpmWidth = 40 val maxPMPs = 16 } class PerfCounterIO(implicit p: Parameters) extends CoreBundle with HasCoreParameters { val eventSel = Output(UInt(xLen.W)) val inc = Input(UInt(log2Ceil(1+retireWidth).W)) } class TracedInstruction(implicit p: Parameters) extends CoreBundle { val valid = Bool() val iaddr = UInt(coreMaxAddrBits.W) val insn = UInt(iLen.W) val priv = UInt(3.W) val exception = Bool() val interrupt = Bool() val cause = UInt(xLen.W) val tval = UInt((coreMaxAddrBits max iLen).W) val wdata = Option.when(traceHasWdata)(UInt((vLen max xLen).W)) } class TraceAux extends Bundle { val enable = Bool() val stall = Bool() } class CSRDecodeIO(implicit p: Parameters) extends CoreBundle { val inst = Input(UInt(iLen.W)) def csr_addr = (inst >> 20)(CSR.ADDRSZ-1, 0) val fp_illegal = Output(Bool()) val vector_illegal = Output(Bool()) val fp_csr = Output(Bool()) val vector_csr = Output(Bool()) val rocc_illegal = Output(Bool()) val read_illegal = Output(Bool()) val write_illegal = Output(Bool()) val write_flush = Output(Bool()) val system_illegal = Output(Bool()) val virtual_access_illegal = Output(Bool()) val virtual_system_illegal = Output(Bool()) } class CSRFileIO(hasBeu: Boolean)(implicit p: Parameters) extends CoreBundle with HasCoreParameters { val ungated_clock = Input(Clock()) val interrupts = Input(new CoreInterrupts(hasBeu)) val hartid = Input(UInt(hartIdLen.W)) val rw = new Bundle { val addr = Input(UInt(CSR.ADDRSZ.W)) val cmd = Input(Bits(CSR.SZ.W)) val rdata = Output(Bits(xLen.W)) val wdata = Input(Bits(xLen.W)) } val decode = Vec(decodeWidth, new CSRDecodeIO) val csr_stall = Output(Bool()) // stall retire for wfi val rw_stall = Output(Bool()) // stall rw, rw will have no effect while rw_stall val eret = Output(Bool()) val singleStep = Output(Bool()) val status = Output(new MStatus()) val hstatus = Output(new HStatus()) val gstatus = Output(new MStatus()) val ptbr = Output(new PTBR()) val hgatp = Output(new PTBR()) val vsatp = Output(new PTBR()) val evec = Output(UInt(vaddrBitsExtended.W)) val exception = Input(Bool()) val retire = Input(UInt(log2Up(1+retireWidth).W)) val cause = Input(UInt(xLen.W)) val pc = Input(UInt(vaddrBitsExtended.W)) val tval = Input(UInt(vaddrBitsExtended.W)) val htval = Input(UInt(((maxSVAddrBits + 1) min xLen).W)) val mhtinst_read_pseudo = Input(Bool()) val gva = Input(Bool()) val time = Output(UInt(xLen.W)) val fcsr_rm = Output(Bits(FPConstants.RM_SZ.W)) val fcsr_flags = Flipped(Valid(Bits(FPConstants.FLAGS_SZ.W))) val set_fs_dirty = coreParams.haveFSDirty.option(Input(Bool())) val rocc_interrupt = Input(Bool()) val interrupt = Output(Bool()) val interrupt_cause = Output(UInt(xLen.W)) val bp = Output(Vec(nBreakpoints, new BP)) val pmp = Output(Vec(nPMPs, new PMP)) val counters = Vec(nPerfCounters, new PerfCounterIO) val csrw_counter = Output(UInt(CSR.nCtr.W)) val inhibit_cycle = Output(Bool()) val inst = Input(Vec(retireWidth, UInt(iLen.W))) val trace = Output(Vec(retireWidth, new TracedInstruction)) val mcontext = Output(UInt(coreParams.mcontextWidth.W)) val scontext = Output(UInt(coreParams.scontextWidth.W)) val fiom = Output(Bool()) val vector = usingVector.option(new Bundle { val vconfig = Output(new VConfig()) val vstart = Output(UInt(maxVLMax.log2.W)) val vxrm = Output(UInt(2.W)) val set_vs_dirty = Input(Bool()) val set_vconfig = Flipped(Valid(new VConfig)) val set_vstart = Flipped(Valid(vstart)) val set_vxsat = Input(Bool()) }) } class VConfig(implicit p: Parameters) extends CoreBundle { val vl = UInt((maxVLMax.log2 + 1).W) val vtype = new VType } object VType { def fromUInt(that: UInt, ignore_vill: Boolean = false)(implicit p: Parameters): VType = { val res = 0.U.asTypeOf(new VType) val in = that.asTypeOf(res) val vill = (in.max_vsew.U < in.vsew) \|\| !in.lmul_ok \|\| in.reserved =/= 0.U \|\| in.vill when (!vill \|\| ignore_vill.B) { res := in res.vsew := in.vsew(log2Ceil(1 + in.max_vsew) - 1, 0) } res.reserved := 0.U res.vill := vill res } def computeVL(avl: UInt, vtype: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool)(implicit p: Parameters): UInt = VType.fromUInt(vtype, true).vl(avl, currentVL, useCurrentVL, useMax, useZero) } class VType(implicit p: Parameters) extends CoreBundle { val vill = Bool() val reserved = UInt((xLen - 9).W) val vma = Bool() val vta = Bool() val vsew = UInt(3.W) val vlmul_sign = Bool() val vlmul_mag = UInt(2.W) def vlmul_signed: SInt = Cat(vlmul_sign, vlmul_mag).asSInt @deprecated("use vlmul_sign, vlmul_mag, or vlmul_signed", "RVV 0.9") def vlmul: UInt = vlmul_mag def max_vsew = log2Ceil(eLen/8) def max_vlmul = (1 << vlmul_mag.getWidth) - 1 def lmul_ok: Bool = Mux(this.vlmul_sign, this.vlmul_mag =/= 0.U && ~this.vlmul_mag < max_vsew.U - this.vsew, true.B) def minVLMax: Int = ((maxVLMax / eLen) >> ((1 << vlmul_mag.getWidth) - 1)) max 1 def vlMax: UInt = (maxVLMax.U >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).andNot((minVLMax-1).U) def vl(avl: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool): UInt = { val atLeastMaxVLMax = useMax \|\| Mux(useCurrentVL, currentVL >= maxVLMax.U, avl >= maxVLMax.U) val avl_lsbs = Mux(useCurrentVL, currentVL, avl)(maxVLMax.log2 - 1, 0) val atLeastVLMax = atLeastMaxVLMax \|\| (avl_lsbs & (-maxVLMax.S >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).asUInt.andNot((minVLMax-1).U)).orR val isZero = vill \|\| useZero Mux(!isZero && atLeastVLMax, vlMax, 0.U) \| Mux(!isZero && !atLeastVLMax, avl_lsbs, 0.U) } } class CSRFile( perfEventSets: EventSets = new EventSets(Seq()), customCSRs: Seq[CustomCSR] = Nil, roccCSRs: Seq[CustomCSR] = Nil, hasBeu: Boolean = false)(implicit p: Parameters) extends CoreModule()(p) with HasCoreParameters { val io = IO(new CSRFileIO(hasBeu) { val customCSRs = Vec(CSRFile.this.customCSRs.size, new CustomCSRIO) val roccCSRs = Vec(CSRFile.this.roccCSRs.size, new CustomCSRIO) }) io.rw_stall := false.B val reset_mstatus = WireDefault(0.U.asTypeOf(new MStatus())) reset_mstatus.mpp := PRV.M.U reset_mstatus.prv := PRV.M.U reset_mstatus.xs := (if (usingRoCC) 3.U else 0.U) val reg_mstatus = RegInit(reset_mstatus) val new_prv = WireDefault(reg_mstatus.prv) reg_mstatus.prv := legalizePrivilege(new_prv) val reset_dcsr = WireDefault(0.U.asTypeOf(new DCSR())) reset_dcsr.xdebugver := 1.U reset_dcsr.prv := PRV.M.U val reg_dcsr = RegInit(reset_dcsr) val (supported_interrupts, delegable_interrupts) = { val sup = Wire(new MIP) sup.usip := false.B sup.ssip := usingSupervisor.B sup.vssip := usingHypervisor.B sup.msip := true.B sup.utip := false.B sup.stip := usingSupervisor.B sup.vstip := usingHypervisor.B sup.mtip := true.B sup.ueip := false.B sup.seip := usingSupervisor.B sup.vseip := usingHypervisor.B sup.meip := true.B sup.sgeip := false.B sup.rocc := usingRoCC.B sup.debug := false.B sup.zero1 := false.B sup.lip foreach { _ := true.B } val supported_high_interrupts = if (io.interrupts.buserror.nonEmpty && !usingNMI) (BigInt(1) << CSR.busErrorIntCause).U else 0.U val del = WireDefault(sup) del.msip := false.B del.mtip := false.B del.meip := false.B (sup.asUInt \| supported_high_interrupts, del.asUInt) } val delegable_base_exceptions = Seq( Causes.misaligned_fetch, Causes.fetch_page_fault, Causes.breakpoint, Causes.load_page_fault, Causes.store_page_fault, Causes.misaligned_load, Causes.misaligned_store, Causes.illegal_instruction, Causes.user_ecall, ) val delegable_hypervisor_exceptions = Seq( Causes.virtual_supervisor_ecall, Causes.fetch_guest_page_fault, Causes.load_guest_page_fault, Causes.virtual_instruction, Causes.store_guest_page_fault, ) val delegable_exceptions = ( delegable_base_exceptions ++ (if (usingHypervisor) delegable_hypervisor_exceptions else Seq()) ).map(1 << _).sum.U val hs_delegable_exceptions = Seq( Causes.misaligned_fetch, Causes.fetch_access, Causes.illegal_instruction, Causes.breakpoint, Causes.misaligned_load, Causes.load_access, Causes.misaligned_store, Causes.store_access, Causes.user_ecall, Causes.fetch_page_fault, Causes.load_page_fault, Causes.store_page_fault).map(1 << _).sum.U val (hs_delegable_interrupts, mideleg_always_hs) = { val always = WireDefault(0.U.asTypeOf(new MIP())) always.vssip := usingHypervisor.B always.vstip := usingHypervisor.B always.vseip := usingHypervisor.B val deleg = WireDefault(always) deleg.lip.foreach { _ := usingHypervisor.B } (deleg.asUInt, always.asUInt) } val reg_debug = RegInit(false.B) val reg_dpc = Reg(UInt(vaddrBitsExtended.W)) val reg_dscratch0 = Reg(UInt(xLen.W)) val reg_dscratch1 = (p(DebugModuleKey).map(_.nDscratch).getOrElse(1) > 1).option(Reg(UInt(xLen.W))) val reg_singleStepped = Reg(Bool()) val reg_mcontext = (coreParams.mcontextWidth > 0).option(RegInit(0.U(coreParams.mcontextWidth.W))) val reg_scontext = (coreParams.scontextWidth > 0).option(RegInit(0.U(coreParams.scontextWidth.W))) val reg_tselect = Reg(UInt(log2Up(nBreakpoints).W)) val reg_bp = Reg(Vec(1 << log2Up(nBreakpoints), new BP)) val reg_pmp = Reg(Vec(nPMPs, new PMPReg)) val reg_mie = Reg(UInt(xLen.W)) val (reg_mideleg, read_mideleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingSupervisor.B, reg & delegable_interrupts \| mideleg_always_hs, 0.U)) } val (reg_medeleg, read_medeleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingSupervisor.B, reg & delegable_exceptions, 0.U)) } val reg_mip = Reg(new MIP) val reg_mepc = Reg(UInt(vaddrBitsExtended.W)) val reg_mcause = RegInit(0.U(xLen.W)) val reg_mtval = Reg(UInt(vaddrBitsExtended.W)) val reg_mtval2 = Reg(UInt(((maxSVAddrBits + 1) min xLen).W)) val reg_mscratch = Reg(Bits(xLen.W)) val mtvecWidth = paddrBits min xLen val reg_mtvec = mtvecInit match { case Some(addr) => RegInit(addr.U(mtvecWidth.W)) case None => Reg(UInt(mtvecWidth.W)) } val reset_mnstatus = WireDefault(0.U.asTypeOf(new MNStatus())) reset_mnstatus.mpp := PRV.M.U val reg_mnscratch = Reg(Bits(xLen.W)) val reg_mnepc = Reg(UInt(vaddrBitsExtended.W)) val reg_mncause = RegInit(0.U(xLen.W)) val reg_mnstatus = RegInit(reset_mnstatus) val reg_rnmie = RegInit(true.B) val nmie = reg_rnmie val reg_menvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val reg_senvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val reg_henvcfg = RegInit(0.U.asTypeOf(new Envcfg)) val delegable_counters = ((BigInt(1) << (nPerfCounters + CSR.firstHPM)) - 1).U val (reg_mcounteren, read_mcounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingUser.B, reg & delegable_counters, 0.U)) } val (reg_scounteren, read_scounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingSupervisor.B, reg & delegable_counters, 0.U)) } val (reg_hideleg, read_hideleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_interrupts, 0.U)) } val (reg_hedeleg, read_hedeleg) = { val reg = Reg(UInt(xLen.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_exceptions, 0.U)) } val hs_delegable_counters = delegable_counters val (reg_hcounteren, read_hcounteren) = { val reg = Reg(UInt(32.W)) (reg, Mux(usingHypervisor.B, reg & hs_delegable_counters, 0.U)) } val reg_hstatus = RegInit(0.U.asTypeOf(new HStatus)) val reg_hgatp = Reg(new PTBR) val reg_htval = Reg(reg_mtval2.cloneType) val read_hvip = reg_mip.asUInt & hs_delegable_interrupts val read_hie = reg_mie & hs_delegable_interrupts val (reg_vstvec, read_vstvec) = { val reg = Reg(UInt(vaddrBitsExtended.W)) (reg, formTVec(reg).sextTo(xLen)) } val reg_vsstatus = Reg(new MStatus) val reg_vsscratch = Reg(Bits(xLen.W)) val reg_vsepc = Reg(UInt(vaddrBitsExtended.W)) val reg_vscause = Reg(Bits(xLen.W)) val reg_vstval = Reg(UInt(vaddrBitsExtended.W)) val reg_vsatp = Reg(new PTBR) val reg_sepc = Reg(UInt(vaddrBitsExtended.W)) val reg_scause = Reg(Bits(xLen.W)) val reg_stval = Reg(UInt(vaddrBitsExtended.W)) val reg_sscratch = Reg(Bits(xLen.W)) val reg_stvec = Reg(UInt((if (usingHypervisor) vaddrBitsExtended else vaddrBits).W)) val reg_satp = Reg(new PTBR) val reg_wfi = withClock(io.ungated_clock) { RegInit(false.B) } val reg_fflags = Reg(UInt(5.W)) val reg_frm = Reg(UInt(3.W)) val reg_vconfig = usingVector.option(Reg(new VConfig)) val reg_vstart = usingVector.option(Reg(UInt(maxVLMax.log2.W))) val reg_vxsat = usingVector.option(Reg(Bool())) val reg_vxrm = usingVector.option(Reg(UInt(io.vector.get.vxrm.getWidth.W))) val reg_mtinst_read_pseudo = Reg(Bool()) val reg_htinst_read_pseudo = Reg(Bool()) // XLEN=32: 0x00002000 // XLEN=64: 0x00003000 val Seq(read_mtinst, read_htinst) = Seq(reg_mtinst_read_pseudo, reg_htinst_read_pseudo).map(r => Cat(r, (xLen == 32).option(0.U).getOrElse(r), 0.U(12.W))) val reg_mcountinhibit = RegInit(0.U((CSR.firstHPM + nPerfCounters).W)) io.inhibit_cycle := reg_mcountinhibit(0) val reg_instret = WideCounter(64, io.retire, inhibit = reg_mcountinhibit(2)) val reg_cycle = if (enableCommitLog) WideCounter(64, io.retire, inhibit = reg_mcountinhibit(0)) else withClock(io.ungated_clock) { WideCounter(64, !io.csr_stall, inhibit = reg_mcountinhibit(0)) } val reg_hpmevent = io.counters.map(c => RegInit(0.U(xLen.W))) (io.counters zip reg_hpmevent) foreach { case (c, e) => c.eventSel := e } val reg_hpmcounter = io.counters.zipWithIndex.map { case (c, i) => WideCounter(CSR.hpmWidth, c.inc, reset = false, inhibit = reg_mcountinhibit(CSR.firstHPM+i)) } val mip = WireDefault(reg_mip) mip.lip := (io.interrupts.lip: Seq[Bool]) mip.mtip := io.interrupts.mtip mip.msip := io.interrupts.msip mip.meip := io.interrupts.meip // seip is the OR of reg_mip.seip and the actual line from the PLIC io.interrupts.seip.foreach { mip.seip := reg_mip.seip \|\| _ } // Simimlar sort of thing would apply if the PLIC had a VSEIP line: //io.interrupts.vseip.foreach { mip.vseip := reg_mip.vseip \|\| _ } mip.rocc := io.rocc_interrupt val read_mip = mip.asUInt & supported_interrupts val read_hip = read_mip & hs_delegable_interrupts val high_interrupts = (if (usingNMI) 0.U else io.interrupts.buserror.map(_ << CSR.busErrorIntCause).getOrElse(0.U)) val pending_interrupts = high_interrupts \| (read_mip & reg_mie) val d_interrupts = io.interrupts.debug << CSR.debugIntCause val (nmi_interrupts, nmiFlag) = io.interrupts.nmi.map(nmi => (((nmi.rnmi && reg_rnmie) << CSR.rnmiIntCause) \| io.interrupts.buserror.map(_ << CSR.rnmiBEUCause).getOrElse(0.U), !io.interrupts.debug && nmi.rnmi && reg_rnmie)).getOrElse(0.U, false.B) val m_interrupts = Mux(nmie && (reg_mstatus.prv <= PRV.S.U \|\| reg_mstatus.mie), ~(~pending_interrupts \| read_mideleg), 0.U) val s_interrupts = Mux(nmie && (reg_mstatus.v \|\| reg_mstatus.prv < PRV.S.U \|\| (reg_mstatus.prv === PRV.S.U && reg_mstatus.sie)), pending_interrupts & read_mideleg & ~read_hideleg, 0.U) val vs_interrupts = Mux(nmie && (reg_mstatus.v && (reg_mstatus.prv < PRV.S.U \|\| reg_mstatus.prv === PRV.S.U && reg_vsstatus.sie)), pending_interrupts & read_hideleg, 0.U) val (anyInterrupt, whichInterrupt) = chooseInterrupt(Seq(vs_interrupts, s_interrupts, m_interrupts, nmi_interrupts, d_interrupts)) val interruptMSB = BigInt(1) << (xLen-1) val interruptCause = interruptMSB.U + (nmiFlag << (xLen-2)) + whichInterrupt io.interrupt := (anyInterrupt && !io.singleStep \|\| reg_singleStepped) && !(reg_debug \|\| io.status.cease) io.interrupt_cause := interruptCause io.bp := reg_bp take nBreakpoints io.mcontext := reg_mcontext.getOrElse(0.U) io.scontext := reg_scontext.getOrElse(0.U) io.fiom := (reg_mstatus.prv < PRV.M.U && reg_menvcfg.fiom) \|\| (reg_mstatus.prv < PRV.S.U && reg_senvcfg.fiom) \|\| (reg_mstatus.v && reg_henvcfg.fiom) io.pmp := reg_pmp.map(PMP(_)) val isaMaskString = (if (usingMulDiv) "M" else "") + (if (usingAtomics) "A" else "") + (if (fLen >= 32) "F" else "") + (if (fLen >= 64) "D" else "") + (if (coreParams.hasV) "V" else "") + (if (usingCompressed) "C" else "") val isaString = (if (coreParams.useRVE) "E" else "I") + isaMaskString + (if (customIsaExt.isDefined \|\| usingRoCC) "X" else "") + (if (usingSupervisor) "S" else "") + (if (usingHypervisor) "H" else "") + (if (usingUser) "U" else "") val isaMax = (BigInt(log2Ceil(xLen) - 4) << (xLen-2)) \| isaStringToMask(isaString) val reg_misa = RegInit(isaMax.U) val read_mstatus = io.status.asUInt.extract(xLen-1,0) val read_mtvec = formTVec(reg_mtvec).padTo(xLen) val read_stvec = formTVec(reg_stvec).sextTo(xLen) val read_mapping = LinkedHashMap[Int,Bits]( CSRs.tselect -> reg_tselect, CSRs.tdata1 -> reg_bp(reg_tselect).control.asUInt, CSRs.tdata2 -> reg_bp(reg_tselect).address.sextTo(xLen), CSRs.tdata3 -> reg_bp(reg_tselect).textra.asUInt, CSRs.misa -> reg_misa, CSRs.mstatus -> read_mstatus, CSRs.mtvec -> read_mtvec, CSRs.mip -> read_mip, CSRs.mie -> reg_mie, CSRs.mscratch -> reg_mscratch, CSRs.mepc -> readEPC(reg_mepc).sextTo(xLen), CSRs.mtval -> reg_mtval.sextTo(xLen), CSRs.mcause -> reg_mcause, CSRs.mhartid -> io.hartid) val debug_csrs = if (!usingDebug) LinkedHashMap() else LinkedHashMap[Int,Bits]( CSRs.dcsr -> reg_dcsr.asUInt, CSRs.dpc -> readEPC(reg_dpc).sextTo(xLen), CSRs.dscratch0 -> reg_dscratch0.asUInt) ++ reg_dscratch1.map(r => CSRs.dscratch1 -> r) val read_mnstatus = WireInit(0.U.asTypeOf(new MNStatus())) read_mnstatus.mpp := reg_mnstatus.mpp read_mnstatus.mpv := reg_mnstatus.mpv read_mnstatus.mie := reg_rnmie val nmi_csrs = if (!usingNMI) LinkedHashMap() else LinkedHashMap[Int,Bits]( CustomCSRs.mnscratch -> reg_mnscratch, CustomCSRs.mnepc -> readEPC(reg_mnepc).sextTo(xLen), CustomCSRs.mncause -> reg_mncause, CustomCSRs.mnstatus -> read_mnstatus.asUInt) val context_csrs = LinkedHashMap[Int,Bits]() ++ reg_mcontext.map(r => CSRs.mcontext -> r) ++ reg_scontext.map(r => CSRs.scontext -> r) val read_fcsr = Cat(reg_frm, reg_fflags) val fp_csrs = LinkedHashMap[Int,Bits]() ++ usingFPU.option(CSRs.fflags -> reg_fflags) ++ usingFPU.option(CSRs.frm -> reg_frm) ++ (usingFPU \|\| usingVector).option(CSRs.fcsr -> read_fcsr) val read_vcsr = Cat(reg_vxrm.getOrElse(0.U), reg_vxsat.getOrElse(0.U)) val vector_csrs = if (!usingVector) LinkedHashMap() else LinkedHashMap[Int,Bits]( CSRs.vxsat -> reg_vxsat.get, CSRs.vxrm -> reg_vxrm.get, CSRs.vcsr -> read_vcsr, CSRs.vstart -> reg_vstart.get, CSRs.vtype -> reg_vconfig.get.vtype.asUInt, CSRs.vl -> reg_vconfig.get.vl, CSRs.vlenb -> (vLen / 8).U) read_mapping ++= debug_csrs read_mapping ++= nmi_csrs read_mapping ++= context_csrs read_mapping ++= fp_csrs read_mapping ++= vector_csrs if (coreParams.haveBasicCounters) { read_mapping += CSRs.mcountinhibit -> reg_mcountinhibit read_mapping += CSRs.mcycle -> reg_cycle read_mapping += CSRs.minstret -> reg_instret for (((e, c), i) <- (reg_hpmevent.padTo(CSR.nHPM, 0.U) zip reg_hpmcounter.map(x => x: UInt).padTo(CSR.nHPM, 0.U)).zipWithIndex) { read_mapping += (i + CSR.firstHPE) -> e // mhpmeventN read_mapping += (i + CSR.firstMHPC) -> c // mhpmcounterN read_mapping += (i + CSR.firstHPC) -> c // hpmcounterN if (xLen == 32) { read_mapping += (i + CSR.firstMHPCH) -> (c >> 32) // mhpmcounterNh read_mapping += (i + CSR.firstHPCH) -> (c >> 32) // hpmcounterNh } } if (usingUser) { read_mapping += CSRs.mcounteren -> read_mcounteren } read_mapping += CSRs.cycle -> reg_cycle read_mapping += CSRs.instret -> reg_instret if (xLen == 32) { read_mapping += CSRs.mcycleh -> (reg_cycle >> 32) read_mapping += CSRs.minstreth -> (reg_instret >> 32) read_mapping += CSRs.cycleh -> (reg_cycle >> 32) read_mapping += CSRs.instreth -> (reg_instret >> 32) } } if (usingUser) { read_mapping += CSRs.menvcfg -> reg_menvcfg.asUInt if (xLen == 32) read_mapping += CSRs.menvcfgh -> (reg_menvcfg.asUInt >> 32) } val sie_mask = { val sgeip_mask = WireInit(0.U.asTypeOf(new MIP)) sgeip_mask.sgeip := true.B read_mideleg & ~(hs_delegable_interrupts \| sgeip_mask.asUInt) } if (usingSupervisor) { val read_sie = reg_mie & sie_mask val read_sip = read_mip & sie_mask val read_sstatus = WireDefault(0.U.asTypeOf(new MStatus)) read_sstatus.sd := io.status.sd read_sstatus.uxl := io.status.uxl read_sstatus.sd_rv32 := io.status.sd_rv32 read_sstatus.mxr := io.status.mxr read_sstatus.sum := io.status.sum read_sstatus.xs := io.status.xs read_sstatus.fs := io.status.fs read_sstatus.vs := io.status.vs read_sstatus.spp := io.status.spp read_sstatus.spie := io.status.spie read_sstatus.sie := io.status.sie read_mapping += CSRs.sstatus -> (read_sstatus.asUInt)(xLen-1,0) read_mapping += CSRs.sip -> read_sip.asUInt read_mapping += CSRs.sie -> read_sie.asUInt read_mapping += CSRs.sscratch -> reg_sscratch read_mapping += CSRs.scause -> reg_scause read_mapping += CSRs.stval -> reg_stval.sextTo(xLen) read_mapping += CSRs.satp -> reg_satp.asUInt read_mapping += CSRs.sepc -> readEPC(reg_sepc).sextTo(xLen) read_mapping += CSRs.stvec -> read_stvec read_mapping += CSRs.scounteren -> read_scounteren read_mapping += CSRs.mideleg -> read_mideleg read_mapping += CSRs.medeleg -> read_medeleg read_mapping += CSRs.senvcfg -> reg_senvcfg.asUInt } val pmpCfgPerCSR = xLen / new PMPConfig().getWidth def pmpCfgIndex(i: Int) = (xLen / 32) * (i / pmpCfgPerCSR) if (reg_pmp.nonEmpty) { require(reg_pmp.size <= CSR.maxPMPs) val read_pmp = reg_pmp.padTo(CSR.maxPMPs, 0.U.asTypeOf(new PMP)) for (i <- 0 until read_pmp.size by pmpCfgPerCSR) read_mapping += (CSRs.pmpcfg0 + pmpCfgIndex(i)) -> read_pmp.map(_.cfg).slice(i, i + pmpCfgPerCSR).asUInt for ((pmp, i) <- read_pmp.zipWithIndex) read_mapping += (CSRs.pmpaddr0 + i) -> pmp.readAddr } // implementation-defined CSRs def generateCustomCSR(csr: CustomCSR, csr_io: CustomCSRIO) = { require(csr.mask >= 0 && csr.mask.bitLength <= xLen) require(!read_mapping.contains(csr.id)) val reg = csr.init.map(init => RegInit(init.U(xLen.W))).getOrElse(Reg(UInt(xLen.W))) val read = io.rw.cmd =/= CSR.N && io.rw.addr === csr.id.U csr_io.ren := read when (read && csr_io.stall) { io.rw_stall := true.B } read_mapping += csr.id -> reg reg } val reg_custom = customCSRs.zip(io.customCSRs).map(t => generateCustomCSR(t._1, t._2)) val reg_rocc = roccCSRs.zip(io.roccCSRs).map(t => generateCustomCSR(t._1, t._2)) if (usingHypervisor) { read_mapping += CSRs.mtinst -> read_mtinst read_mapping += CSRs.mtval2 -> reg_mtval2 val read_hstatus = io.hstatus.asUInt.extract(xLen-1,0) read_mapping += CSRs.hstatus -> read_hstatus read_mapping += CSRs.hedeleg -> read_hedeleg read_mapping += CSRs.hideleg -> read_hideleg read_mapping += CSRs.hcounteren-> read_hcounteren read_mapping += CSRs.hgatp -> reg_hgatp.asUInt read_mapping += CSRs.hip -> read_hip read_mapping += CSRs.hie -> read_hie read_mapping += CSRs.hvip -> read_hvip read_mapping += CSRs.hgeie -> 0.U read_mapping += CSRs.hgeip -> 0.U read_mapping += CSRs.htval -> reg_htval read_mapping += CSRs.htinst -> read_htinst read_mapping += CSRs.henvcfg -> reg_henvcfg.asUInt if (xLen == 32) read_mapping += CSRs.henvcfgh -> (reg_henvcfg.asUInt >> 32) val read_vsie = (read_hie & read_hideleg) >> 1 val read_vsip = (read_hip & read_hideleg) >> 1 val read_vsepc = readEPC(reg_vsepc).sextTo(xLen) val read_vstval = reg_vstval.sextTo(xLen) val read_vsstatus = io.gstatus.asUInt.extract(xLen-1,0) read_mapping += CSRs.vsstatus -> read_vsstatus read_mapping += CSRs.vsip -> read_vsip read_mapping += CSRs.vsie -> read_vsie read_mapping += CSRs.vsscratch -> reg_vsscratch read_mapping += CSRs.vscause -> reg_vscause read_mapping += CSRs.vstval -> read_vstval read_mapping += CSRs.vsatp -> reg_vsatp.asUInt read_mapping += CSRs.vsepc -> read_vsepc read_mapping += CSRs.vstvec -> read_vstvec } // mimpid, marchid, mvendorid, and mconfigptr are 0 unless overridden by customCSRs Seq(CSRs.mimpid, CSRs.marchid, CSRs.mvendorid, CSRs.mconfigptr).foreach(id => read_mapping.getOrElseUpdate(id, 0.U)) val decoded_addr = { val addr = Cat(io.status.v, io.rw.addr) val pats = for (((k, _), i) <- read_mapping.zipWithIndex) yield (BitPat(k.U), (0 until read_mapping.size).map(j => BitPat((i == j).B))) val decoded = DecodeLogic(addr, Seq.fill(read_mapping.size)(X), pats) val unvirtualized_mapping = (for (((k, _), v) <- read_mapping zip decoded) yield k -> v.asBool).toMap for ((k, v) <- unvirtualized_mapping) yield k -> { val alt: Option[Bool] = CSR.mode(k) match { // hcontext was assigned an unfortunate address; it lives where a // hypothetical vscontext will live. Exclude them from the S/VS remapping. // (on separate lines so scala-lint doesnt do something stupid) case _ if k == CSRs.scontext => None case _ if k == CSRs.hcontext => None // When V=1, if a corresponding VS CSR exists, access it instead... case PRV.H => unvirtualized_mapping.lift(k - (1 << CSR.modeLSB)) // ...and don't access the original S-mode version. case PRV.S => unvirtualized_mapping.contains(k + (1 << CSR.modeLSB)).option(false.B) case _ => None } alt.map(Mux(reg_mstatus.v, _, v)).getOrElse(v) } } val wdata = readModifyWriteCSR(io.rw.cmd, io.rw.rdata, io.rw.wdata) val system_insn = io.rw.cmd === CSR.I val hlsv = Seq(HLV_B, HLV_BU, HLV_H, HLV_HU, HLV_W, HLV_WU, HLV_D, HSV_B, HSV_H, HSV_W, HSV_D, HLVX_HU, HLVX_WU) val decode_table = Seq( ECALL-> List(Y,N,N,N,N,N,N,N,N), EBREAK-> List(N,Y,N,N,N,N,N,N,N), MRET-> List(N,N,Y,N,N,N,N,N,N), CEASE-> List(N,N,N,Y,N,N,N,N,N), WFI-> List(N,N,N,N,Y,N,N,N,N)) ++ usingDebug.option( DRET-> List(N,N,Y,N,N,N,N,N,N)) ++ usingNMI.option( MNRET-> List(N,N,Y,N,N,N,N,N,N)) ++ coreParams.haveCFlush.option(CFLUSH_D_L1-> List(N,N,N,N,N,N,N,N,N)) ++ usingSupervisor.option( SRET-> List(N,N,Y,N,N,N,N,N,N)) ++ usingVM.option( SFENCE_VMA-> List(N,N,N,N,N,Y,N,N,N)) ++ usingHypervisor.option( HFENCE_VVMA-> List(N,N,N,N,N,N,Y,N,N)) ++ usingHypervisor.option( HFENCE_GVMA-> List(N,N,N,N,N,N,N,Y,N)) ++ (if (usingHypervisor) hlsv.map(_-> List(N,N,N,N,N,N,N,N,Y)) else Seq()) val insn_call :: insn_break :: insn_ret :: insn_cease :: insn_wfi :: _ :: _ :: _ :: _ :: Nil = { val insn = ECALL.value.U \| (io.rw.addr << 20) DecodeLogic(insn, decode_table(0)._2.map(x=>X), decode_table).map(system_insn && _.asBool) } for (io_dec <- io.decode) { val addr = io_dec.inst(31, 20) def decodeAny(m: LinkedHashMap[Int,Bits]): Bool = m.map { case(k: Int, _: Bits) => addr === k.U }.reduce(_\|\|_) def decodeFast(s: Seq[Int]): Bool = DecodeLogic(addr, s.map(_.U), (read_mapping -- s).keys.toList.map(_.U)) val _ :: is_break :: is_ret :: _ :: is_wfi :: is_sfence :: is_hfence_vvma :: is_hfence_gvma :: is_hlsv :: Nil = DecodeLogic(io_dec.inst, decode_table(0)._2.map(x=>X), decode_table).map(_.asBool) val is_counter = (addr.inRange(CSR.firstCtr.U, (CSR.firstCtr + CSR.nCtr).U) \|\| addr.inRange(CSR.firstCtrH.U, (CSR.firstCtrH + CSR.nCtr).U)) val allow_wfi = (!usingSupervisor).B \|\| reg_mstatus.prv > PRV.S.U \|\| !reg_mstatus.tw && (!reg_mstatus.v \|\| !reg_hstatus.vtw) val allow_sfence_vma = (!usingVM).B \|\| reg_mstatus.prv > PRV.S.U \|\| !Mux(reg_mstatus.v, reg_hstatus.vtvm, reg_mstatus.tvm) val allow_hfence_vvma = (!usingHypervisor).B \|\| !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U) val allow_hlsv = (!usingHypervisor).B \|\| !reg_mstatus.v && (reg_mstatus.prv >= PRV.S.U \|\| reg_hstatus.hu) val allow_sret = (!usingSupervisor).B \|\| reg_mstatus.prv > PRV.S.U \|\| !Mux(reg_mstatus.v, reg_hstatus.vtsr, reg_mstatus.tsr) val counter_addr = addr(log2Ceil(read_mcounteren.getWidth)-1, 0) val allow_counter = (reg_mstatus.prv > PRV.S.U \|\| read_mcounteren(counter_addr)) && (!usingSupervisor.B \|\| reg_mstatus.prv >= PRV.S.U \|\| read_scounteren(counter_addr)) && (!usingHypervisor.B \|\| !reg_mstatus.v \|\| read_hcounteren(counter_addr)) io_dec.fp_illegal := io.status.fs === 0.U \|\| reg_mstatus.v && reg_vsstatus.fs === 0.U \|\| !reg_misa('f'-'a') io_dec.vector_illegal := io.status.vs === 0.U \|\| reg_mstatus.v && reg_vsstatus.vs === 0.U \|\| !reg_misa('v'-'a') io_dec.fp_csr := decodeFast(fp_csrs.keys.toList) io_dec.vector_csr := decodeFast(vector_csrs.keys.toList) io_dec.rocc_illegal := io.status.xs === 0.U \|\| reg_mstatus.v && reg_vsstatus.xs === 0.U \|\| !reg_misa('x'-'a') val csr_addr_legal = reg_mstatus.prv >= CSR.mode(addr) \|\| usingHypervisor.B && !reg_mstatus.v && reg_mstatus.prv === PRV.S.U && CSR.mode(addr) === PRV.H.U val csr_exists = decodeAny(read_mapping) io_dec.read_illegal := !csr_addr_legal \|\| !csr_exists \|\| ((addr === CSRs.satp.U \|\| addr === CSRs.hgatp.U) && !allow_sfence_vma) \|\| is_counter && !allow_counter \|\| decodeFast(debug_csrs.keys.toList) && !reg_debug \|\| decodeFast(vector_csrs.keys.toList) && io_dec.vector_illegal \|\| io_dec.fp_csr && io_dec.fp_illegal io_dec.write_illegal := addr(11,10).andR io_dec.write_flush := { val addr_m = addr \| (PRV.M.U << CSR.modeLSB) !(addr_m >= CSRs.mscratch.U && addr_m <= CSRs.mtval.U) } io_dec.system_illegal := !csr_addr_legal && !is_hlsv \|\| is_wfi && !allow_wfi \|\| is_ret && !allow_sret \|\| is_ret && addr(10) && addr(7) && !reg_debug \|\| (is_sfence \|\| is_hfence_gvma) && !allow_sfence_vma \|\| is_hfence_vvma && !allow_hfence_vvma \|\| is_hlsv && !allow_hlsv io_dec.virtual_access_illegal := reg_mstatus.v && csr_exists && ( CSR.mode(addr) === PRV.H.U \|\| is_counter && read_mcounteren(counter_addr) && (!read_hcounteren(counter_addr) \|\| !reg_mstatus.prv(0) && !read_scounteren(counter_addr)) \|\| CSR.mode(addr) === PRV.S.U && !reg_mstatus.prv(0) \|\| addr === CSRs.satp.U && reg_mstatus.prv(0) && reg_hstatus.vtvm) io_dec.virtual_system_illegal := reg_mstatus.v && ( is_hfence_vvma \|\| is_hfence_gvma \|\| is_hlsv \|\| is_wfi && (!reg_mstatus.prv(0) \|\| !reg_mstatus.tw && reg_hstatus.vtw) \|\| is_ret && CSR.mode(addr) === PRV.S.U && (!reg_mstatus.prv(0) \|\| reg_hstatus.vtsr) \|\| is_sfence && (!reg_mstatus.prv(0) \|\| reg_hstatus.vtvm)) } val cause = Mux(insn_call, Causes.user_ecall.U + Mux(reg_mstatus.prv(0) && reg_mstatus.v, PRV.H.U, reg_mstatus.prv), Mux[UInt](insn_break, Causes.breakpoint.U, io.cause)) val cause_lsbs = cause(log2Ceil(1 + CSR.busErrorIntCause)-1, 0) val cause_deleg_lsbs = cause(log2Ceil(xLen)-1,0) val causeIsDebugInt = cause(xLen-1) && cause_lsbs === CSR.debugIntCause.U val causeIsDebugTrigger = !cause(xLen-1) && cause_lsbs === CSR.debugTriggerCause.U val causeIsDebugBreak = !cause(xLen-1) && insn_break && Cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh, reg_dcsr.ebreaks, reg_dcsr.ebreaku)(reg_mstatus.prv) val trapToDebug = usingDebug.B && (reg_singleStepped \|\| causeIsDebugInt \|\| causeIsDebugTrigger \|\| causeIsDebugBreak \|\| reg_debug) val debugEntry = p(DebugModuleKey).map(_.debugEntry).getOrElse(BigInt(0x800)) val debugException = p(DebugModuleKey).map(_.debugException).getOrElse(BigInt(0x808)) val debugTVec = Mux(reg_debug, Mux(insn_break, debugEntry.U, debugException.U), debugEntry.U) val delegate = usingSupervisor.B && reg_mstatus.prv <= PRV.S.U && Mux(cause(xLen-1), read_mideleg(cause_deleg_lsbs), read_medeleg(cause_deleg_lsbs)) val delegateVS = reg_mstatus.v && delegate && Mux(cause(xLen-1), read_hideleg(cause_deleg_lsbs), read_hedeleg(cause_deleg_lsbs)) def mtvecBaseAlign = 2 def mtvecInterruptAlign = { require(reg_mip.getWidth <= xLen) log2Ceil(xLen) } val notDebugTVec = { val base = Mux(delegate, Mux(delegateVS, read_vstvec, read_stvec), read_mtvec) val interruptOffset = cause(mtvecInterruptAlign-1, 0) << mtvecBaseAlign val interruptVec = Cat(base >> (mtvecInterruptAlign + mtvecBaseAlign), interruptOffset) val doVector = base(0) && cause(cause.getWidth-1) && (cause_lsbs >> mtvecInterruptAlign) === 0.U Mux(doVector, interruptVec, base >> mtvecBaseAlign << mtvecBaseAlign) } val causeIsRnmiInt = cause(xLen-1) && cause(xLen-2) && (cause_lsbs === CSR.rnmiIntCause.U \|\| cause_lsbs === CSR.rnmiBEUCause.U) val causeIsRnmiBEU = cause(xLen-1) && cause(xLen-2) && cause_lsbs === CSR.rnmiBEUCause.U val causeIsNmi = causeIsRnmiInt val nmiTVecInt = io.interrupts.nmi.map(nmi => nmi.rnmi_interrupt_vector).getOrElse(0.U) val nmiTVecXcpt = io.interrupts.nmi.map(nmi => nmi.rnmi_exception_vector).getOrElse(0.U) val trapToNmiInt = usingNMI.B && causeIsNmi val trapToNmiXcpt = usingNMI.B && !nmie val trapToNmi = trapToNmiInt \|\| trapToNmiXcpt val nmiTVec = (Mux(causeIsNmi, nmiTVecInt, nmiTVecXcpt)>>1)<<1 val tvec = Mux(trapToDebug, debugTVec, Mux(trapToNmi, nmiTVec, notDebugTVec)) io.evec := tvec io.ptbr := reg_satp io.hgatp := reg_hgatp io.vsatp := reg_vsatp io.eret := insn_call \|\| insn_break \|\| insn_ret io.singleStep := reg_dcsr.step && !reg_debug io.status := reg_mstatus io.status.sd := io.status.fs.andR \|\| io.status.xs.andR \|\| io.status.vs.andR io.status.debug := reg_debug io.status.isa := reg_misa io.status.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U io.status.sxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U io.status.dprv := Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpp, reg_mstatus.prv) io.status.dv := reg_mstatus.v \|\| Mux(reg_mstatus.mprv && !reg_debug, reg_mstatus.mpv, false.B) io.status.sd_rv32 := (xLen == 32).B && io.status.sd io.status.mpv := reg_mstatus.mpv io.status.gva := reg_mstatus.gva io.hstatus := reg_hstatus io.hstatus.vsxl := (if (usingSupervisor) log2Ceil(xLen) - 4 else 0).U io.gstatus := reg_vsstatus io.gstatus.sd := io.gstatus.fs.andR \|\| io.gstatus.xs.andR \|\| io.gstatus.vs.andR io.gstatus.uxl := (if (usingUser) log2Ceil(xLen) - 4 else 0).U io.gstatus.sd_rv32 := (xLen == 32).B && io.gstatus.sd val exception = insn_call \|\| insn_break \|\| io.exception assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1.U, "these conditions must be mutually exclusive") when (insn_wfi && !io.singleStep && !reg_debug) { reg_wfi := true.B } when (pending_interrupts.orR \|\| io.interrupts.debug \|\| exception) { reg_wfi := false.B } io.interrupts.nmi.map(nmi => when (nmi.rnmi) { reg_wfi := false.B } ) when (io.retire(0) \|\| exception) { reg_singleStepped := true.B } when (!io.singleStep) { reg_singleStepped := false.B } assert(!io.singleStep \|\| io.retire <= 1.U) assert(!reg_singleStepped \|\| io.retire === 0.U) val epc = formEPC(io.pc) val tval = Mux(insn_break, epc, io.tval) when (exception) { when (trapToDebug) { when (!reg_debug) { reg_mstatus.v := false.B reg_debug := true.B reg_dpc := epc reg_dcsr.cause := Mux(reg_singleStepped, 4.U, Mux(causeIsDebugInt, 3.U, Mux[UInt](causeIsDebugTrigger, 2.U, 1.U))) reg_dcsr.prv := trimPrivilege(reg_mstatus.prv) reg_dcsr.v := reg_mstatus.v new_prv := PRV.M.U } }.elsewhen (trapToNmiInt) { when (reg_rnmie) { reg_mstatus.v := false.B reg_mnstatus.mpv := reg_mstatus.v reg_rnmie := false.B reg_mnepc := epc reg_mncause := (BigInt(1) << (xLen-1)).U \| Mux(causeIsRnmiBEU, 3.U, 2.U) reg_mnstatus.mpp := trimPrivilege(reg_mstatus.prv) new_prv := PRV.M.U } }.elsewhen (delegateVS && nmie) { reg_mstatus.v := true.B reg_vsstatus.spp := reg_mstatus.prv reg_vsepc := epc reg_vscause := Mux(cause(xLen-1), Cat(cause(xLen-1, 2), 1.U(2.W)), cause) reg_vstval := tval reg_vsstatus.spie := reg_vsstatus.sie reg_vsstatus.sie := false.B new_prv := PRV.S.U }.elsewhen (delegate && nmie) { reg_mstatus.v := false.B reg_hstatus.spvp := Mux(reg_mstatus.v, reg_mstatus.prv(0),reg_hstatus.spvp) reg_hstatus.gva := io.gva reg_hstatus.spv := reg_mstatus.v reg_sepc := epc reg_scause := cause reg_stval := tval reg_htval := io.htval reg_htinst_read_pseudo := io.mhtinst_read_pseudo reg_mstatus.spie := reg_mstatus.sie reg_mstatus.spp := reg_mstatus.prv reg_mstatus.sie := false.B new_prv := PRV.S.U }.otherwise { reg_mstatus.v := false.B reg_mstatus.mpv := reg_mstatus.v reg_mstatus.gva := io.gva reg_mepc := epc reg_mcause := cause reg_mtval := tval reg_mtval2 := io.htval reg_mtinst_read_pseudo := io.mhtinst_read_pseudo reg_mstatus.mpie := reg_mstatus.mie reg_mstatus.mpp := trimPrivilege(reg_mstatus.prv) reg_mstatus.mie := false.B new_prv := PRV.M.U } } for (i <- 0 until supported_interrupts.getWidth) { val en = exception && (supported_interrupts & (BigInt(1) << i).U) =/= 0.U && cause === (BigInt(1) << (xLen - 1)).U + i.U val delegable = (delegable_interrupts & (BigInt(1) << i).U) =/= 0.U property.cover(en && !delegate, s"INTERRUPT_M_$i") property.cover(en && delegable && delegate, s"INTERRUPT_S_$i") } for (i <- 0 until xLen) { val supported_exceptions: BigInt = 0x8fe \| (if (usingCompressed && !coreParams.misaWritable) 0 else 1) \| (if (usingUser) 0x100 else 0) \| (if (usingSupervisor) 0x200 else 0) \| (if (usingVM) 0xb000 else 0) if (((supported_exceptions >> i) & 1) != 0) { val en = exception && cause === i.U val delegable = (delegable_exceptions & (BigInt(1) << i).U) =/= 0.U property.cover(en && !delegate, s"EXCEPTION_M_$i") property.cover(en && delegable && delegate, s"EXCEPTION_S_$i") } } when (insn_ret) { val ret_prv = WireInit(UInt(), DontCare) when (usingSupervisor.B && !io.rw.addr(9)) { when (!reg_mstatus.v) { reg_mstatus.sie := reg_mstatus.spie reg_mstatus.spie := true.B reg_mstatus.spp := PRV.U.U ret_prv := reg_mstatus.spp reg_mstatus.v := usingHypervisor.B && reg_hstatus.spv io.evec := readEPC(reg_sepc) reg_hstatus.spv := false.B }.otherwise { reg_vsstatus.sie := reg_vsstatus.spie reg_vsstatus.spie := true.B reg_vsstatus.spp := PRV.U.U ret_prv := reg_vsstatus.spp reg_mstatus.v := usingHypervisor.B io.evec := readEPC(reg_vsepc) } }.elsewhen (usingDebug.B && io.rw.addr(10) && io.rw.addr(7)) { ret_prv := reg_dcsr.prv reg_mstatus.v := usingHypervisor.B && reg_dcsr.v && reg_dcsr.prv <= PRV.S.U reg_debug := false.B io.evec := readEPC(reg_dpc) }.elsewhen (usingNMI.B && io.rw.addr(10) && !io.rw.addr(7)) { ret_prv := reg_mnstatus.mpp reg_mstatus.v := usingHypervisor.B && reg_mnstatus.mpv && reg_mnstatus.mpp <= PRV.S.U reg_rnmie := true.B io.evec := readEPC(reg_mnepc) }.otherwise { reg_mstatus.mie := reg_mstatus.mpie reg_mstatus.mpie := true.B reg_mstatus.mpp := legalizePrivilege(PRV.U.U) reg_mstatus.mpv := false.B ret_prv := reg_mstatus.mpp reg_mstatus.v := usingHypervisor.B && reg_mstatus.mpv && reg_mstatus.mpp <= PRV.S.U io.evec := readEPC(reg_mepc) } new_prv := ret_prv when (usingUser.B && ret_prv <= PRV.S.U) { reg_mstatus.mprv := false.B } } io.time := reg_cycle io.csr_stall := reg_wfi \|\| io.status.cease io.status.cease := RegEnable(true.B, false.B, insn_cease) io.status.wfi := reg_wfi for ((io, reg) <- io.customCSRs zip reg_custom) { io.wen := false.B io.wdata := wdata io.value := reg } for ((io, reg) <- io.roccCSRs zip reg_rocc) { io.wen := false.B io.wdata := wdata io.value := reg } io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v) // cover access to register val coverable_counters = read_mapping.filterNot { case (k, _) => k >= CSR.firstHPC + nPerfCounters && k < CSR.firstHPC + CSR.nHPM } coverable_counters.foreach( {case (k, v) => { when (!k.U(11,10).andR) { // Cover points for RW CSR registers property.cover(io.rw.cmd.isOneOf(CSR.W, CSR.S, CSR.C) && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field") } .otherwise { // Cover points for RO CSR registers property.cover(io.rw.cmd===CSR.R && io.rw.addr===k.U, "CSR_access_"+k.toString, "Cover Accessing Core CSR field") } }}) val set_vs_dirty = WireDefault(io.vector.map(_.set_vs_dirty).getOrElse(false.B)) io.vector.foreach { vio => when (set_vs_dirty) { assert(reg_mstatus.vs > 0.U) when (reg_mstatus.v) { reg_vsstatus.vs := 3.U } reg_mstatus.vs := 3.U } } val set_fs_dirty = WireDefault(io.set_fs_dirty.getOrElse(false.B)) if (coreParams.haveFSDirty) { when (set_fs_dirty) { assert(reg_mstatus.fs > 0.U) when (reg_mstatus.v) { reg_vsstatus.fs := 3.U } reg_mstatus.fs := 3.U } } io.fcsr_rm := reg_frm when (io.fcsr_flags.valid) { reg_fflags := reg_fflags \| io.fcsr_flags.bits set_fs_dirty := true.B } io.vector.foreach { vio => when (vio.set_vxsat) { reg_vxsat.get := true.B set_vs_dirty := true.B } } val csr_wen = io.rw.cmd.isOneOf(CSR.S, CSR.C, CSR.W) && !io.rw_stall io.csrw_counter := Mux(coreParams.haveBasicCounters.B && csr_wen && (io.rw.addr.inRange(CSRs.mcycle.U, (CSRs.mcycle + CSR.nCtr).U) \|\| io.rw.addr.inRange(CSRs.mcycleh.U, (CSRs.mcycleh + CSR.nCtr).U)), UIntToOH(io.rw.addr(log2Ceil(CSR.nCtr+nPerfCounters)-1, 0)), 0.U) when (csr_wen) { val scause_mask = ((BigInt(1) << (xLen-1)) + 31).U /* only implement 5 LSBs and MSB / val satp_valid_modes = 0 +: (minPgLevels to pgLevels).map(new PTBR().pgLevelsToMode(_)) when (decoded_addr(CSRs.mstatus)) { val new_mstatus = wdata.asTypeOf(new MStatus()) reg_mstatus.mie := new_mstatus.mie reg_mstatus.mpie := new_mstatus.mpie if (usingUser) { reg_mstatus.mprv := new_mstatus.mprv reg_mstatus.mpp := legalizePrivilege(new_mstatus.mpp) if (usingSupervisor) { reg_mstatus.spp := new_mstatus.spp reg_mstatus.spie := new_mstatus.spie reg_mstatus.sie := new_mstatus.sie reg_mstatus.tw := new_mstatus.tw reg_mstatus.tsr := new_mstatus.tsr } if (usingVM) { reg_mstatus.mxr := new_mstatus.mxr reg_mstatus.sum := new_mstatus.sum reg_mstatus.tvm := new_mstatus.tvm } if (usingHypervisor) { reg_mstatus.mpv := new_mstatus.mpv reg_mstatus.gva := new_mstatus.gva } } if (usingSupervisor \|\| usingFPU) reg_mstatus.fs := formFS(new_mstatus.fs) reg_mstatus.vs := formVS(new_mstatus.vs) } when (decoded_addr(CSRs.misa)) { val mask = isaStringToMask(isaMaskString).U(xLen.W) val f = wdata('f' - 'a') // suppress write if it would cause the next fetch to be misaligned when (!usingCompressed.B \|\| !io.pc(1) \|\| wdata('c' - 'a')) { if (coreParams.misaWritable) reg_misa := ~(~wdata \| (!f << ('d' - 'a'))) & mask \| reg_misa & ~mask } } when (decoded_addr(CSRs.mip)) { // MIP should be modified based on the value in reg_mip, not the value // in read_mip, since read_mip.seip is the OR of reg_mip.seip and // io.interrupts.seip. We don't want the value on the PLIC line to // inadvertently be OR'd into read_mip.seip. val new_mip = readModifyWriteCSR(io.rw.cmd, reg_mip.asUInt, io.rw.wdata).asTypeOf(new MIP) if (usingSupervisor) { reg_mip.ssip := new_mip.ssip reg_mip.stip := new_mip.stip reg_mip.seip := new_mip.seip } if (usingHypervisor) { reg_mip.vssip := new_mip.vssip } } when (decoded_addr(CSRs.mie)) { reg_mie := wdata & supported_interrupts } when (decoded_addr(CSRs.mepc)) { reg_mepc := formEPC(wdata) } when (decoded_addr(CSRs.mscratch)) { reg_mscratch := wdata } if (mtvecWritable) when (decoded_addr(CSRs.mtvec)) { reg_mtvec := wdata } when (decoded_addr(CSRs.mcause)) { reg_mcause := wdata & ((BigInt(1) << (xLen-1)) + (BigInt(1) << whichInterrupt.getWidth) - 1).U } when (decoded_addr(CSRs.mtval)) { reg_mtval := wdata } if (usingNMI) { val new_mnstatus = wdata.asTypeOf(new MNStatus()) when (decoded_addr(CustomCSRs.mnscratch)) { reg_mnscratch := wdata } when (decoded_addr(CustomCSRs.mnepc)) { reg_mnepc := formEPC(wdata) } when (decoded_addr(CustomCSRs.mncause)) { reg_mncause := wdata & ((BigInt(1) << (xLen-1)) + BigInt(3)).U } when (decoded_addr(CustomCSRs.mnstatus)) { reg_mnstatus.mpp := legalizePrivilege(new_mnstatus.mpp) reg_mnstatus.mpv := usingHypervisor.B && new_mnstatus.mpv reg_rnmie := reg_rnmie \| new_mnstatus.mie // mnie bit settable but not clearable from software } } for (((e, c), i) <- (reg_hpmevent zip reg_hpmcounter).zipWithIndex) { writeCounter(i + CSR.firstMHPC, c, wdata) when (decoded_addr(i + CSR.firstHPE)) { e := perfEventSets.maskEventSelector(wdata) } } if (coreParams.haveBasicCounters) { when (decoded_addr(CSRs.mcountinhibit)) { reg_mcountinhibit := wdata & ~2.U(xLen.W) } // mcountinhibit bit [1] is tied zero writeCounter(CSRs.mcycle, reg_cycle, wdata) writeCounter(CSRs.minstret, reg_instret, wdata) } if (usingFPU) { when (decoded_addr(CSRs.fflags)) { set_fs_dirty := true.B; reg_fflags := wdata } when (decoded_addr(CSRs.frm)) { set_fs_dirty := true.B; reg_frm := wdata } when (decoded_addr(CSRs.fcsr)) { set_fs_dirty := true.B reg_fflags := wdata reg_frm := wdata >> reg_fflags.getWidth } } if (usingDebug) { when (decoded_addr(CSRs.dcsr)) { val new_dcsr = wdata.asTypeOf(new DCSR()) reg_dcsr.step := new_dcsr.step reg_dcsr.ebreakm := new_dcsr.ebreakm if (usingSupervisor) reg_dcsr.ebreaks := new_dcsr.ebreaks if (usingUser) reg_dcsr.ebreaku := new_dcsr.ebreaku if (usingUser) reg_dcsr.prv := legalizePrivilege(new_dcsr.prv) if (usingHypervisor) reg_dcsr.v := new_dcsr.v } when (decoded_addr(CSRs.dpc)) { reg_dpc := formEPC(wdata) } when (decoded_addr(CSRs.dscratch0)) { reg_dscratch0 := wdata } reg_dscratch1.foreach { r => when (decoded_addr(CSRs.dscratch1)) { r := wdata } } } if (usingSupervisor) { when (decoded_addr(CSRs.sstatus)) { val new_sstatus = wdata.asTypeOf(new MStatus()) reg_mstatus.sie := new_sstatus.sie reg_mstatus.spie := new_sstatus.spie reg_mstatus.spp := new_sstatus.spp reg_mstatus.fs := formFS(new_sstatus.fs) reg_mstatus.vs := formVS(new_sstatus.vs) if (usingVM) { reg_mstatus.mxr := new_sstatus.mxr reg_mstatus.sum := new_sstatus.sum } } when (decoded_addr(CSRs.sip)) { val new_sip = ((read_mip & ~read_mideleg) \| (wdata & read_mideleg)).asTypeOf(new MIP()) reg_mip.ssip := new_sip.ssip } when (decoded_addr(CSRs.satp)) { if (usingVM) { val new_satp = wdata.asTypeOf(new PTBR()) when (new_satp.mode.isOneOf(satp_valid_modes.map(_.U))) { reg_satp.mode := new_satp.mode & satp_valid_modes.reduce(_\|_).U reg_satp.ppn := new_satp.ppn(ppnBits-1,0) if (asIdBits > 0) reg_satp.asid := new_satp.asid(asIdBits-1,0) } } } when (decoded_addr(CSRs.sie)) { reg_mie := (reg_mie & ~sie_mask) \| (wdata & sie_mask) } when (decoded_addr(CSRs.sscratch)) { reg_sscratch := wdata } when (decoded_addr(CSRs.sepc)) { reg_sepc := formEPC(wdata) } when (decoded_addr(CSRs.stvec)) { reg_stvec := wdata } when (decoded_addr(CSRs.scause)) { reg_scause := wdata & scause_mask } when (decoded_addr(CSRs.stval)) { reg_stval := wdata } when (decoded_addr(CSRs.mideleg)) { reg_mideleg := wdata } when (decoded_addr(CSRs.medeleg)) { reg_medeleg := wdata } when (decoded_addr(CSRs.scounteren)) { reg_scounteren := wdata } when (decoded_addr(CSRs.senvcfg)) { reg_senvcfg.write(wdata) } } if (usingHypervisor) { when (decoded_addr(CSRs.hstatus)) { val new_hstatus = wdata.asTypeOf(new HStatus()) reg_hstatus.gva := new_hstatus.gva reg_hstatus.spv := new_hstatus.spv reg_hstatus.spvp := new_hstatus.spvp reg_hstatus.hu := new_hstatus.hu reg_hstatus.vtvm := new_hstatus.vtvm reg_hstatus.vtw := new_hstatus.vtw reg_hstatus.vtsr := new_hstatus.vtsr reg_hstatus.vsxl := new_hstatus.vsxl } when (decoded_addr(CSRs.hideleg)) { reg_hideleg := wdata } when (decoded_addr(CSRs.hedeleg)) { reg_hedeleg := wdata } when (decoded_addr(CSRs.hgatp)) { val new_hgatp = wdata.asTypeOf(new PTBR()) val valid_modes = 0 +: (minPgLevels to pgLevels).map(new_hgatp.pgLevelsToMode(_)) when (new_hgatp.mode.isOneOf(valid_modes.map(_.U))) { reg_hgatp.mode := new_hgatp.mode & valid_modes.reduce(_\|_).U } reg_hgatp.ppn := Cat(new_hgatp.ppn(ppnBits-1,2), 0.U(2.W)) if (vmIdBits > 0) reg_hgatp.asid := new_hgatp.asid(vmIdBits-1,0) } when (decoded_addr(CSRs.hip)) { val new_hip = ((read_mip & ~hs_delegable_interrupts) \| (wdata & hs_delegable_interrupts)).asTypeOf(new MIP()) reg_mip.vssip := new_hip.vssip } when (decoded_addr(CSRs.hie)) { reg_mie := (reg_mie & ~hs_delegable_interrupts) \| (wdata & hs_delegable_interrupts) } when (decoded_addr(CSRs.hvip)) { val new_sip = ((read_mip & ~hs_delegable_interrupts) \| (wdata & hs_delegable_interrupts)).asTypeOf(new MIP()) reg_mip.vssip := new_sip.vssip reg_mip.vstip := new_sip.vstip reg_mip.vseip := new_sip.vseip } when (decoded_addr(CSRs.hcounteren)) { reg_hcounteren := wdata } when (decoded_addr(CSRs.htval)) { reg_htval := wdata } when (decoded_addr(CSRs.mtval2)) { reg_mtval2 := wdata } val write_mhtinst_read_pseudo = wdata(13) && (xLen == 32).option(true.B).getOrElse(wdata(12)) when(decoded_addr(CSRs.mtinst)) { reg_mtinst_read_pseudo := write_mhtinst_read_pseudo } when(decoded_addr(CSRs.htinst)) { reg_htinst_read_pseudo := write_mhtinst_read_pseudo } when (decoded_addr(CSRs.vsstatus)) { val new_vsstatus = wdata.asTypeOf(new MStatus()) reg_vsstatus.sie := new_vsstatus.sie reg_vsstatus.spie := new_vsstatus.spie reg_vsstatus.spp := new_vsstatus.spp reg_vsstatus.mxr := new_vsstatus.mxr reg_vsstatus.sum := new_vsstatus.sum reg_vsstatus.fs := formFS(new_vsstatus.fs) reg_vsstatus.vs := formVS(new_vsstatus.vs) } when (decoded_addr(CSRs.vsip)) { val new_vsip = ((read_hip & ~read_hideleg) \| ((wdata << 1) & read_hideleg)).asTypeOf(new MIP()) reg_mip.vssip := new_vsip.vssip } when (decoded_addr(CSRs.vsatp)) { val new_vsatp = wdata.asTypeOf(new PTBR()) val mode_ok = new_vsatp.mode.isOneOf(satp_valid_modes.map(_.U)) when (mode_ok) { reg_vsatp.mode := new_vsatp.mode & satp_valid_modes.reduce(_\|_).U } when (mode_ok \|\| !reg_mstatus.v) { reg_vsatp.ppn := new_vsatp.ppn(vpnBits.min(new_vsatp.ppn.getWidth)-1,0) if (asIdBits > 0) reg_vsatp.asid := new_vsatp.asid(asIdBits-1,0) } } when (decoded_addr(CSRs.vsie)) { reg_mie := (reg_mie & ~read_hideleg) \| ((wdata << 1) & read_hideleg) } when (decoded_addr(CSRs.vsscratch)) { reg_vsscratch := wdata } when (decoded_addr(CSRs.vsepc)) { reg_vsepc := formEPC(wdata) } when (decoded_addr(CSRs.vstvec)) { reg_vstvec := wdata } when (decoded_addr(CSRs.vscause)) { reg_vscause := wdata & scause_mask } when (decoded_addr(CSRs.vstval)) { reg_vstval := wdata } when (decoded_addr(CSRs.henvcfg)) { reg_henvcfg.write(wdata) } } if (usingUser) { when (decoded_addr(CSRs.mcounteren)) { reg_mcounteren := wdata } when (decoded_addr(CSRs.menvcfg)) { reg_menvcfg.write(wdata) } } if (nBreakpoints > 0) { when (decoded_addr(CSRs.tselect)) { reg_tselect := wdata } for ((bp, i) <- reg_bp.zipWithIndex) { when (i.U === reg_tselect && (!bp.control.dmode \|\| reg_debug)) { when (decoded_addr(CSRs.tdata2)) { bp.address := wdata } when (decoded_addr(CSRs.tdata3)) { if (coreParams.mcontextWidth > 0) { bp.textra.mselect := wdata(bp.textra.mselectPos) bp.textra.mvalue := wdata >> bp.textra.mvaluePos } if (coreParams.scontextWidth > 0) { bp.textra.sselect := wdata(bp.textra.sselectPos) bp.textra.svalue := wdata >> bp.textra.svaluePos } } when (decoded_addr(CSRs.tdata1)) { bp.control := wdata.asTypeOf(bp.control) val prevChain = if (i == 0) false.B else reg_bp(i-1).control.chain val prevDMode = if (i == 0) false.B else reg_bp(i-1).control.dmode val nextChain = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.chain val nextDMode = if (i >= nBreakpoints-1) true.B else reg_bp(i+1).control.dmode val newBPC = readModifyWriteCSR(io.rw.cmd, bp.control.asUInt, io.rw.wdata).asTypeOf(bp.control) val dMode = newBPC.dmode && reg_debug && (prevDMode \|\| !prevChain) bp.control.dmode := dMode when (dMode \|\| (newBPC.action > 1.U)) { bp.control.action := newBPC.action }.otherwise { bp.control.action := 0.U } bp.control.chain := newBPC.chain && !(prevChain \|\| nextChain) && (dMode \|\| !nextDMode) } } } } reg_mcontext.foreach { r => when (decoded_addr(CSRs.mcontext)) { r := wdata }} reg_scontext.foreach { r => when (decoded_addr(CSRs.scontext)) { r := wdata }} if (reg_pmp.nonEmpty) for (((pmp, next), i) <- (reg_pmp zip (reg_pmp.tail :+ reg_pmp.last)).zipWithIndex) { require(xLen % pmp.cfg.getWidth == 0) when (decoded_addr(CSRs.pmpcfg0 + pmpCfgIndex(i)) && !pmp.cfgLocked) { val newCfg = (wdata >> ((i pmp.cfg.getWidth) % xLen)).asTypeOf(new PMPConfig()) pmp.cfg := newCfg // disallow unreadable but writable PMPs pmp.cfg.w := newCfg.w && newCfg.r // can't select a=NA4 with coarse-grained PMPs if (pmpGranularity.log2 > PMP.lgAlign) pmp.cfg.a := Cat(newCfg.a(1), newCfg.a.orR) } when (decoded_addr(CSRs.pmpaddr0 + i) && !pmp.addrLocked(next)) { pmp.addr := wdata } } def writeCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = { val mask = csr.mask.U(xLen.W) when (decoded_addr(csr.id)) { reg := (wdata & mask) \| (reg & ~mask) io.wen := true.B } } for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) { writeCustomCSR(io, csr, reg) } for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) { writeCustomCSR(io, csr, reg) } if (usingVector) { when (decoded_addr(CSRs.vstart)) { set_vs_dirty := true.B; reg_vstart.get := wdata } when (decoded_addr(CSRs.vxrm)) { set_vs_dirty := true.B; reg_vxrm.get := wdata } when (decoded_addr(CSRs.vxsat)) { set_vs_dirty := true.B; reg_vxsat.get := wdata } when (decoded_addr(CSRs.vcsr)) { set_vs_dirty := true.B reg_vxsat.get := wdata reg_vxrm.get := wdata >> 1 } } } def setCustomCSR(io: CustomCSRIO, csr: CustomCSR, reg: UInt) = { val mask = csr.mask.U(xLen.W) when (io.set) { reg := (io.sdata & mask) \| (reg & ~mask) } } for ((io, csr, reg) <- (io.customCSRs, customCSRs, reg_custom).zipped) { setCustomCSR(io, csr, reg) } for ((io, csr, reg) <- (io.roccCSRs, roccCSRs, reg_rocc).zipped) { setCustomCSR(io, csr, reg) } io.vector.map { vio => when (vio.set_vconfig.valid) { // user of CSRFile is responsible for set_vs_dirty in this case assert(vio.set_vconfig.bits.vl <= vio.set_vconfig.bits.vtype.vlMax) reg_vconfig.get := vio.set_vconfig.bits } when (vio.set_vstart.valid) { set_vs_dirty := true.B reg_vstart.get := vio.set_vstart.bits } vio.vstart := reg_vstart.get vio.vconfig := reg_vconfig.get vio.vxrm := reg_vxrm.get when (reset.asBool) { reg_vconfig.get.vl := 0.U reg_vconfig.get.vtype := 0.U.asTypeOf(new VType) reg_vconfig.get.vtype.vill := true.B } } when(reset.asBool) { reg_satp.mode := 0.U reg_vsatp.mode := 0.U reg_hgatp.mode := 0.U } if (!usingVM) { reg_satp.mode := 0.U reg_satp.ppn := 0.U reg_satp.asid := 0.U } if (!usingHypervisor) { reg_vsatp.mode := 0.U reg_vsatp.ppn := 0.U reg_vsatp.asid := 0.U reg_hgatp.mode := 0.U reg_hgatp.ppn := 0.U reg_hgatp.asid := 0.U } if (!(asIdBits > 0)) { reg_satp.asid := 0.U reg_vsatp.asid := 0.U } if (!(vmIdBits > 0)) { reg_hgatp.asid := 0.U } reg_vsstatus.xs := (if (usingRoCC) 3.U else 0.U) if (nBreakpoints <= 1) reg_tselect := 0.U for (bpc <- reg_bp map {_.control}) { bpc.ttype := bpc.tType.U bpc.maskmax := bpc.maskMax.U bpc.reserved := 0.U bpc.zero := 0.U bpc.h := false.B if (!usingSupervisor) bpc.s := false.B if (!usingUser) bpc.u := false.B if (!usingSupervisor && !usingUser) bpc.m := true.B when (reset.asBool) { bpc.action := 0.U bpc.dmode := false.B bpc.chain := false.B bpc.r := false.B bpc.w := false.B bpc.x := false.B } } for (bpx <- reg_bp map {_.textra}) { if (coreParams.mcontextWidth == 0) bpx.mselect := false.B if (coreParams.scontextWidth == 0) bpx.sselect := false.B } for (bp <- reg_bp drop nBreakpoints) bp := 0.U.asTypeOf(new BP()) for (pmp <- reg_pmp) { pmp.cfg.res := 0.U when (reset.asBool) { pmp.reset() } } for (((t, insn), i) <- (io.trace zip io.inst).zipWithIndex) { t.exception := io.retire >= i.U && exception t.valid := io.retire > i.U \|\| t.exception t.insn := insn t.iaddr := io.pc t.priv := Cat(reg_debug, reg_mstatus.prv) t.cause := cause t.interrupt := cause(xLen-1) t.tval := io.tval t.wdata.foreach(_ := DontCare) } def chooseInterrupt(masksIn: Seq[UInt]): (Bool, UInt) = { val nonstandard = supported_interrupts.getWidth-1 to 12 by -1 // MEI, MSI, MTI, SEI, SSI, STI, VSEI, VSSI, VSTI, UEI, USI, UTI val standard = Seq(11, 3, 7, 9, 1, 5, 10, 2, 6, 8, 0, 4) val priority = nonstandard ++ standard val masks = masksIn.reverse val any = masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => m(i))).reduce(_\|\|_) val which = PriorityMux(masks.flatMap(m => priority.filter(_ < m.getWidth).map(i => (m(i), i.U)))) (any, which) } def readModifyWriteCSR(cmd: UInt, rdata: UInt, wdata: UInt) = { (Mux(cmd(1), rdata, 0.U) \| wdata) & ~Mux(cmd(1,0).andR, wdata, 0.U) } def legalizePrivilege(priv: UInt): UInt = if (usingSupervisor) Mux(priv === PRV.H.U, PRV.U.U, priv) else if (usingUser) Fill(2, priv(0)) else PRV.M.U def trimPrivilege(priv: UInt): UInt = if (usingSupervisor) priv else legalizePrivilege(priv) def writeCounter(lo: Int, ctr: WideCounter, wdata: UInt) = { if (xLen == 32) { val hi = lo + CSRs.mcycleh - CSRs.mcycle when (decoded_addr(lo)) { ctr := Cat(ctr(ctr.getWidth-1, 32), wdata) } when (decoded_addr(hi)) { ctr := Cat(wdata(ctr.getWidth-33, 0), ctr(31, 0)) } } else { when (decoded_addr(lo)) { ctr := wdata(ctr.getWidth-1, 0) } } } def formEPC(x: UInt) = ~(~x \| (if (usingCompressed) 1.U else 3.U)) def readEPC(x: UInt) = ~(~x \| Mux(reg_misa('c' - 'a'), 1.U, 3.U)) def formTVec(x: UInt) = x andNot Mux(x(0), ((((BigInt(1) << mtvecInterruptAlign) - 1) << mtvecBaseAlign) \| 2).U, 2.U) def isaStringToMask(s: String) = s.map(x => 1 << (x - 'A')).foldLeft(0)(_\|_) def formFS(fs: UInt) = if (coreParams.haveFSDirty) fs else Fill(2, fs.orR) def formVS(vs: UInt) = if (usingVector) vs else 0.U }	module Rocket_7( // @[RocketCore.scala:153:7] input clock, // @[RocketCore.scala:153:7] input reset, // @[RocketCore.scala:153:7] input [2:0] io_hartid, // @[RocketCore.scala:134:14] input io_interrupts_debug, // @[RocketCore.scala:134:14] input io_interrupts_mtip, // @[RocketCore.scala:134:14] input io_interrupts_msip, // @[RocketCore.scala:134:14] input io_interrupts_meip, // @[RocketCore.scala:134:14] input io_interrupts_seip, // @[RocketCore.scala:134:14] output io_imem_might_request, // @[RocketCore.scala:134:14] output io_imem_req_valid, // @[RocketCore.scala:134:14] output [39:0] io_imem_req_bits_pc, // @[RocketCore.scala:134:14] output io_imem_req_bits_speculative, // @[RocketCore.scala:134:14] output io_imem_sfence_valid, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_rs1, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_rs2, // @[RocketCore.scala:134:14] output [38:0] io_imem_sfence_bits_addr, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_asid, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_hv, // @[RocketCore.scala:134:14] output io_imem_sfence_bits_hg, // @[RocketCore.scala:134:14] output io_imem_resp_ready, // @[RocketCore.scala:134:14] input io_imem_resp_valid, // @[RocketCore.scala:134:14] input [1:0] io_imem_resp_bits_btb_cfiType, // @[RocketCore.scala:134:14] input io_imem_resp_bits_btb_taken, // @[RocketCore.scala:134:14] input [1:0] io_imem_resp_bits_btb_mask, // @[RocketCore.scala:134:14] input io_imem_resp_bits_btb_bridx, // @[RocketCore.scala:134:14] input [38:0] io_imem_resp_bits_btb_target, // @[RocketCore.scala:134:14] input [4:0] io_imem_resp_bits_btb_entry, // @[RocketCore.scala:134:14] input [7:0] io_imem_resp_bits_btb_bht_history, // @[RocketCore.scala:134:14] input io_imem_resp_bits_btb_bht_value, // @[RocketCore.scala:134:14] input [39:0] io_imem_resp_bits_pc, // @[RocketCore.scala:134:14] input [31:0] io_imem_resp_bits_data, // @[RocketCore.scala:134:14] input [1:0] io_imem_resp_bits_mask, // @[RocketCore.scala:134:14] input io_imem_resp_bits_xcpt_pf_inst, // @[RocketCore.scala:134:14] input io_imem_resp_bits_xcpt_gf_inst, // @[RocketCore.scala:134:14] input io_imem_resp_bits_xcpt_ae_inst, // @[RocketCore.scala:134:14] input io_imem_resp_bits_replay, // @[RocketCore.scala:134:14] input io_imem_gpa_valid, // @[RocketCore.scala:134:14] input [39:0] io_imem_gpa_bits, // @[RocketCore.scala:134:14] input io_imem_gpa_is_pte, // @[RocketCore.scala:134:14] output io_imem_btb_update_valid, // @[RocketCore.scala:134:14] output [1:0] io_imem_btb_update_bits_prediction_cfiType, // @[RocketCore.scala:134:14] output io_imem_btb_update_bits_prediction_taken, // @[RocketCore.scala:134:14] output [1:0] io_imem_btb_update_bits_prediction_mask, // @[RocketCore.scala:134:14] output io_imem_btb_update_bits_prediction_bridx, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_prediction_target, // @[RocketCore.scala:134:14] output [4:0] io_imem_btb_update_bits_prediction_entry, // @[RocketCore.scala:134:14] output [7:0] io_imem_btb_update_bits_prediction_bht_history, // @[RocketCore.scala:134:14] output io_imem_btb_update_bits_prediction_bht_value, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_pc, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_target, // @[RocketCore.scala:134:14] output io_imem_btb_update_bits_isValid, // @[RocketCore.scala:134:14] output [38:0] io_imem_btb_update_bits_br_pc, // @[RocketCore.scala:134:14] output [1:0] io_imem_btb_update_bits_cfiType, // @[RocketCore.scala:134:14] output io_imem_bht_update_valid, // @[RocketCore.scala:134:14] output [7:0] io_imem_bht_update_bits_prediction_history, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_prediction_value, // @[RocketCore.scala:134:14] output [38:0] io_imem_bht_update_bits_pc, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_branch, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_taken, // @[RocketCore.scala:134:14] output io_imem_bht_update_bits_mispredict, // @[RocketCore.scala:134:14] output io_imem_flush_icache, // @[RocketCore.scala:134:14] input [39:0] io_imem_npc, // @[RocketCore.scala:134:14] input io_imem_perf_acquire, // @[RocketCore.scala:134:14] input io_imem_perf_tlbMiss, // @[RocketCore.scala:134:14] output io_imem_progress, // @[RocketCore.scala:134:14] input io_dmem_req_ready, // @[RocketCore.scala:134:14] output io_dmem_req_valid, // @[RocketCore.scala:134:14] output [39:0] io_dmem_req_bits_addr, // @[RocketCore.scala:134:14] output [6:0] io_dmem_req_bits_tag, // @[RocketCore.scala:134:14] output [4:0] io_dmem_req_bits_cmd, // @[RocketCore.scala:134:14] output [1:0] io_dmem_req_bits_size, // @[RocketCore.scala:134:14] output io_dmem_req_bits_signed, // @[RocketCore.scala:134:14] output [1:0] io_dmem_req_bits_dprv, // @[RocketCore.scala:134:14] output io_dmem_req_bits_dv, // @[RocketCore.scala:134:14] output io_dmem_req_bits_no_resp, // @[RocketCore.scala:134:14] output io_dmem_s1_kill, // @[RocketCore.scala:134:14] output [63:0] io_dmem_s1_data_data, // @[RocketCore.scala:134:14] input io_dmem_s2_nack, // @[RocketCore.scala:134:14] input io_dmem_s2_nack_cause_raw, // @[RocketCore.scala:134:14] input io_dmem_s2_uncached, // @[RocketCore.scala:134:14] input [31:0] io_dmem_s2_paddr, // @[RocketCore.scala:134:14] input io_dmem_resp_valid, // @[RocketCore.scala:134:14] input [39:0] io_dmem_resp_bits_addr, // @[RocketCore.scala:134:14] input [6:0] io_dmem_resp_bits_tag, // @[RocketCore.scala:134:14] input [4:0] io_dmem_resp_bits_cmd, // @[RocketCore.scala:134:14] input [1:0] io_dmem_resp_bits_size, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_signed, // @[RocketCore.scala:134:14] input [1:0] io_dmem_resp_bits_dprv, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_dv, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_data, // @[RocketCore.scala:134:14] input [7:0] io_dmem_resp_bits_mask, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_replay, // @[RocketCore.scala:134:14] input io_dmem_resp_bits_has_data, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_data_word_bypass, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_data_raw, // @[RocketCore.scala:134:14] input [63:0] io_dmem_resp_bits_store_data, // @[RocketCore.scala:134:14] input io_dmem_replay_next, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ma_ld, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ma_st, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_pf_ld, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_pf_st, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ae_ld, // @[RocketCore.scala:134:14] input io_dmem_s2_xcpt_ae_st, // @[RocketCore.scala:134:14] input [39:0] io_dmem_s2_gpa, // @[RocketCore.scala:134:14] input io_dmem_ordered, // @[RocketCore.scala:134:14] input io_dmem_store_pending, // @[RocketCore.scala:134:14] input io_dmem_perf_acquire, // @[RocketCore.scala:134:14] input io_dmem_perf_release, // @[RocketCore.scala:134:14] input io_dmem_perf_grant, // @[RocketCore.scala:134:14] input io_dmem_perf_tlbMiss, // @[RocketCore.scala:134:14] input io_dmem_perf_blocked, // @[RocketCore.scala:134:14] input io_dmem_perf_canAcceptStoreThenLoad, // @[RocketCore.scala:134:14] input io_dmem_perf_canAcceptStoreThenRMW, // @[RocketCore.scala:134:14] input io_dmem_perf_canAcceptLoadThenLoad, // @[RocketCore.scala:134:14] input io_dmem_perf_storeBufferEmptyAfterLoad, // @[RocketCore.scala:134:14] input io_dmem_perf_storeBufferEmptyAfterStore, // @[RocketCore.scala:134:14] output io_dmem_keep_clock_enabled, // @[RocketCore.scala:134:14] output [3:0] io_ptw_ptbr_mode, // @[RocketCore.scala:134:14] output [43:0] io_ptw_ptbr_ppn, // @[RocketCore.scala:134:14] output io_ptw_sfence_valid, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_rs1, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_rs2, // @[RocketCore.scala:134:14] output [38:0] io_ptw_sfence_bits_addr, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_asid, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_hv, // @[RocketCore.scala:134:14] output io_ptw_sfence_bits_hg, // @[RocketCore.scala:134:14] output io_ptw_status_debug, // @[RocketCore.scala:134:14] output io_ptw_status_cease, // @[RocketCore.scala:134:14] output io_ptw_status_wfi, // @[RocketCore.scala:134:14] output [31:0] io_ptw_status_isa, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_dprv, // @[RocketCore.scala:134:14] output io_ptw_status_dv, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_prv, // @[RocketCore.scala:134:14] output io_ptw_status_v, // @[RocketCore.scala:134:14] output io_ptw_status_sd, // @[RocketCore.scala:134:14] output io_ptw_status_mpv, // @[RocketCore.scala:134:14] output io_ptw_status_gva, // @[RocketCore.scala:134:14] output io_ptw_status_tsr, // @[RocketCore.scala:134:14] output io_ptw_status_tw, // @[RocketCore.scala:134:14] output io_ptw_status_tvm, // @[RocketCore.scala:134:14] output io_ptw_status_mxr, // @[RocketCore.scala:134:14] output io_ptw_status_sum, // @[RocketCore.scala:134:14] output io_ptw_status_mprv, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_fs, // @[RocketCore.scala:134:14] output [1:0] io_ptw_status_mpp, // @[RocketCore.scala:134:14] output io_ptw_status_spp, // @[RocketCore.scala:134:14] output io_ptw_status_mpie, // @[RocketCore.scala:134:14] output io_ptw_status_spie, // @[RocketCore.scala:134:14] output io_ptw_status_mie, // @[RocketCore.scala:134:14] output io_ptw_status_sie, // @[RocketCore.scala:134:14] output io_ptw_hstatus_spvp, // @[RocketCore.scala:134:14] output io_ptw_hstatus_spv, // @[RocketCore.scala:134:14] output io_ptw_hstatus_gva, // @[RocketCore.scala:134:14] output io_ptw_gstatus_debug, // @[RocketCore.scala:134:14] output io_ptw_gstatus_cease, // @[RocketCore.scala:134:14] output io_ptw_gstatus_wfi, // @[RocketCore.scala:134:14] output [31:0] io_ptw_gstatus_isa, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_dprv, // @[RocketCore.scala:134:14] output io_ptw_gstatus_dv, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_prv, // @[RocketCore.scala:134:14] output io_ptw_gstatus_v, // @[RocketCore.scala:134:14] output io_ptw_gstatus_sd, // @[RocketCore.scala:134:14] output [22:0] io_ptw_gstatus_zero2, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mpv, // @[RocketCore.scala:134:14] output io_ptw_gstatus_gva, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mbe, // @[RocketCore.scala:134:14] output io_ptw_gstatus_sbe, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_sxl, // @[RocketCore.scala:134:14] output [7:0] io_ptw_gstatus_zero1, // @[RocketCore.scala:134:14] output io_ptw_gstatus_tsr, // @[RocketCore.scala:134:14] output io_ptw_gstatus_tw, // @[RocketCore.scala:134:14] output io_ptw_gstatus_tvm, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mxr, // @[RocketCore.scala:134:14] output io_ptw_gstatus_sum, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mprv, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_fs, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_mpp, // @[RocketCore.scala:134:14] output [1:0] io_ptw_gstatus_vs, // @[RocketCore.scala:134:14] output io_ptw_gstatus_spp, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mpie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_ube, // @[RocketCore.scala:134:14] output io_ptw_gstatus_spie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_upie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_mie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_hie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_sie, // @[RocketCore.scala:134:14] output io_ptw_gstatus_uie, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_0_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_0_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_0_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_0_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_1_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_1_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_1_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_1_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_2_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_2_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_2_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_2_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_3_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_3_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_3_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_3_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_4_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_4_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_4_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_4_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_5_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_5_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_5_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_5_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_6_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_6_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_6_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_6_mask, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_l, // @[RocketCore.scala:134:14] output [1:0] io_ptw_pmp_7_cfg_a, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_x, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_w, // @[RocketCore.scala:134:14] output io_ptw_pmp_7_cfg_r, // @[RocketCore.scala:134:14] output [29:0] io_ptw_pmp_7_addr, // @[RocketCore.scala:134:14] output [31:0] io_ptw_pmp_7_mask, // @[RocketCore.scala:134:14] input io_ptw_perf_pte_miss, // @[RocketCore.scala:134:14] input io_ptw_perf_pte_hit, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_0_ren, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_0_wen, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_0_value, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_1_ren, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_1_wen, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_1_value, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_2_ren, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_2_wen, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_2_value, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_3_ren, // @[RocketCore.scala:134:14] output io_ptw_customCSRs_csrs_3_wen, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[RocketCore.scala:134:14] output [63:0] io_ptw_customCSRs_csrs_3_value, // @[RocketCore.scala:134:14] input io_ptw_clock_enabled, // @[RocketCore.scala:134:14] output [2:0] io_fpu_hartid, // @[RocketCore.scala:134:14] output [63:0] io_fpu_time, // @[RocketCore.scala:134:14] output [31:0] io_fpu_inst, // @[RocketCore.scala:134:14] output [63:0] io_fpu_fromint_data, // @[RocketCore.scala:134:14] output [2:0] io_fpu_fcsr_rm, // @[RocketCore.scala:134:14] input io_fpu_fcsr_flags_valid, // @[RocketCore.scala:134:14] input [4:0] io_fpu_fcsr_flags_bits, // @[RocketCore.scala:134:14] input [63:0] io_fpu_store_data, // @[RocketCore.scala:134:14] input [63:0] io_fpu_toint_data, // @[RocketCore.scala:134:14] output io_fpu_ll_resp_val, // @[RocketCore.scala:134:14] output [2:0] io_fpu_ll_resp_type, // @[RocketCore.scala:134:14] output [4:0] io_fpu_ll_resp_tag, // @[RocketCore.scala:134:14] output [63:0] io_fpu_ll_resp_data, // @[RocketCore.scala:134:14] output io_fpu_valid, // @[RocketCore.scala:134:14] input io_fpu_fcsr_rdy, // @[RocketCore.scala:134:14] input io_fpu_nack_mem, // @[RocketCore.scala:134:14] input io_fpu_illegal_rm, // @[RocketCore.scala:134:14] output io_fpu_killx, // @[RocketCore.scala:134:14] output io_fpu_killm, // @[RocketCore.scala:134:14] input io_fpu_dec_ldst, // @[RocketCore.scala:134:14] input io_fpu_dec_wen, // @[RocketCore.scala:134:14] input io_fpu_dec_ren1, // @[RocketCore.scala:134:14] input io_fpu_dec_ren2, // @[RocketCore.scala:134:14] input io_fpu_dec_ren3, // @[RocketCore.scala:134:14] input io_fpu_dec_swap12, // @[RocketCore.scala:134:14] input io_fpu_dec_swap23, // @[RocketCore.scala:134:14] input [1:0] io_fpu_dec_typeTagIn, // @[RocketCore.scala:134:14] input [1:0] io_fpu_dec_typeTagOut, // @[RocketCore.scala:134:14] input io_fpu_dec_fromint, // @[RocketCore.scala:134:14] input io_fpu_dec_toint, // @[RocketCore.scala:134:14] input io_fpu_dec_fastpipe, // @[RocketCore.scala:134:14] input io_fpu_dec_fma, // @[RocketCore.scala:134:14] input io_fpu_dec_div, // @[RocketCore.scala:134:14] input io_fpu_dec_sqrt, // @[RocketCore.scala:134:14] input io_fpu_dec_wflags, // @[RocketCore.scala:134:14] input io_fpu_dec_vec, // @[RocketCore.scala:134:14] input io_fpu_sboard_set, // @[RocketCore.scala:134:14] input io_fpu_sboard_clr, // @[RocketCore.scala:134:14] input [4:0] io_fpu_sboard_clra, // @[RocketCore.scala:134:14] output io_fpu_keep_clock_enabled, // @[RocketCore.scala:134:14] output io_trace_insns_0_valid, // @[RocketCore.scala:134:14] output [39:0] io_trace_insns_0_iaddr, // @[RocketCore.scala:134:14] output [31:0] io_trace_insns_0_insn, // @[RocketCore.scala:134:14] output [2:0] io_trace_insns_0_priv, // @[RocketCore.scala:134:14] output io_trace_insns_0_exception, // @[RocketCore.scala:134:14] output io_trace_insns_0_interrupt, // @[RocketCore.scala:134:14] output [63:0] io_trace_insns_0_cause, // @[RocketCore.scala:134:14] output [39:0] io_trace_insns_0_tval, // @[RocketCore.scala:134:14] output [63:0] io_trace_time, // @[RocketCore.scala:134:14] output io_bpwatch_0_valid_0, // @[RocketCore.scala:134:14] output [2:0] io_bpwatch_0_action, // @[RocketCore.scala:134:14] output io_wfi // @[RocketCore.scala:134:14] ); wire ll_arb_io_out_ready; // @[RocketCore.scala:782:23, :809:44, :810:25] wire id_ctrl_fence; // @[RocketCore.scala:321:21] wire id_ctrl_rocc; // @[RocketCore.scala:321:21] wire io_imem_sfence_bits_hg_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_bits_hv_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_bits_asid_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_sfence_bits_addr_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_bits_rs2_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_bits_rs1_0; // @[RocketCore.scala:153:7] wire io_imem_sfence_valid_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_btb_update_bits_pc_0; // @[RocketCore.scala:153:7] wire _ll_arb_io_in_0_ready; // @[RocketCore.scala:776:22] wire _ll_arb_io_out_valid; // @[RocketCore.scala:776:22] wire [4:0] _ll_arb_io_out_bits_tag; // @[RocketCore.scala:776:22] wire _div_io_req_ready; // @[RocketCore.scala:511:19] wire _div_io_resp_valid; // @[RocketCore.scala:511:19] wire [63:0] _div_io_resp_bits_data; // @[RocketCore.scala:511:19] wire [4:0] _div_io_resp_bits_tag; // @[RocketCore.scala:511:19] wire [63:0] _alu_io_adder_out; // @[RocketCore.scala:504:19] wire _alu_io_cmp_out; // @[RocketCore.scala:504:19] wire _bpu_io_xcpt_if; // @[RocketCore.scala:414:19] wire _bpu_io_xcpt_ld; // @[RocketCore.scala:414:19] wire _bpu_io_xcpt_st; // @[RocketCore.scala:414:19] wire _bpu_io_debug_if; // @[RocketCore.scala:414:19] wire _bpu_io_debug_ld; // @[RocketCore.scala:414:19] wire _bpu_io_debug_st; // @[RocketCore.scala:414:19] wire _bpu_io_bpwatch_0_rvalid_0; // @[RocketCore.scala:414:19] wire _bpu_io_bpwatch_0_wvalid_0; // @[RocketCore.scala:414:19] wire _bpu_io_bpwatch_0_ivalid_0; // @[RocketCore.scala:414:19] wire [63:0] _csr_io_rw_rdata; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_fp_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_fp_csr; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_read_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_write_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_write_flush; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_system_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_virtual_access_illegal; // @[RocketCore.scala:341:19] wire _csr_io_decode_0_virtual_system_illegal; // @[RocketCore.scala:341:19] wire _csr_io_csr_stall; // @[RocketCore.scala:341:19] wire _csr_io_eret; // @[RocketCore.scala:341:19] wire _csr_io_singleStep; // @[RocketCore.scala:341:19] wire _csr_io_status_debug; // @[RocketCore.scala:341:19] wire _csr_io_status_cease; // @[RocketCore.scala:341:19] wire _csr_io_status_wfi; // @[RocketCore.scala:341:19] wire [31:0] _csr_io_status_isa; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_dprv; // @[RocketCore.scala:341:19] wire _csr_io_status_dv; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_prv; // @[RocketCore.scala:341:19] wire _csr_io_status_v; // @[RocketCore.scala:341:19] wire _csr_io_status_sd; // @[RocketCore.scala:341:19] wire _csr_io_status_mpv; // @[RocketCore.scala:341:19] wire _csr_io_status_gva; // @[RocketCore.scala:341:19] wire _csr_io_status_tsr; // @[RocketCore.scala:341:19] wire _csr_io_status_tw; // @[RocketCore.scala:341:19] wire _csr_io_status_tvm; // @[RocketCore.scala:341:19] wire _csr_io_status_mxr; // @[RocketCore.scala:341:19] wire _csr_io_status_sum; // @[RocketCore.scala:341:19] wire _csr_io_status_mprv; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_fs; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_status_mpp; // @[RocketCore.scala:341:19] wire _csr_io_status_spp; // @[RocketCore.scala:341:19] wire _csr_io_status_mpie; // @[RocketCore.scala:341:19] wire _csr_io_status_spie; // @[RocketCore.scala:341:19] wire _csr_io_status_mie; // @[RocketCore.scala:341:19] wire _csr_io_status_sie; // @[RocketCore.scala:341:19] wire [39:0] _csr_io_evec; // @[RocketCore.scala:341:19] wire [63:0] _csr_io_time; // @[RocketCore.scala:341:19] wire _csr_io_interrupt; // @[RocketCore.scala:341:19] wire [63:0] _csr_io_interrupt_cause; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_dmode; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_action; // @[RocketCore.scala:341:19] wire [1:0] _csr_io_bp_0_control_tmatch; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_m; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_s; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_u; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_x; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_w; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_control_r; // @[RocketCore.scala:341:19] wire [38:0] _csr_io_bp_0_address; // @[RocketCore.scala:341:19] wire [47:0] _csr_io_bp_0_textra_pad2; // @[RocketCore.scala:341:19] wire _csr_io_bp_0_textra_pad1; // @[RocketCore.scala:341:19] wire _csr_io_inhibit_cycle; // @[RocketCore.scala:341:19] wire _csr_io_trace_0_valid; // @[RocketCore.scala:341:19] wire [39:0] _csr_io_trace_0_iaddr; // @[RocketCore.scala:341:19] wire [31:0] _csr_io_trace_0_insn; // @[RocketCore.scala:341:19] wire [2:0] _csr_io_trace_0_priv; // @[RocketCore.scala:341:19] wire _csr_io_trace_0_exception; // @[RocketCore.scala:341:19] wire [39:0] _ibuf_io_pc; // @[RocketCore.scala:311:20] wire [1:0] _ibuf_io_btb_resp_cfiType; // @[RocketCore.scala:311:20] wire _ibuf_io_btb_resp_taken; // @[RocketCore.scala:311:20] wire [1:0] _ibuf_io_btb_resp_mask; // @[RocketCore.scala:311:20] wire _ibuf_io_btb_resp_bridx; // @[RocketCore.scala:311:20] wire [38:0] _ibuf_io_btb_resp_target; // @[RocketCore.scala:311:20] wire [4:0] _ibuf_io_btb_resp_entry; // @[RocketCore.scala:311:20] wire [7:0] _ibuf_io_btb_resp_bht_history; // @[RocketCore.scala:311:20] wire _ibuf_io_btb_resp_bht_value; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt0_pf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt0_gf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt0_ae_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt1_pf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt1_gf_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_xcpt1_ae_inst; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_replay; // @[RocketCore.scala:311:20] wire _ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala:311:20] wire [31:0] _ibuf_io_inst_0_bits_inst_bits; // @[RocketCore.scala:311:20] wire [4:0] _ibuf_io_inst_0_bits_inst_rs1; // @[RocketCore.scala:311:20] wire [31:0] _ibuf_io_inst_0_bits_raw; // @[RocketCore.scala:311:20] wire [2:0] io_hartid_0 = io_hartid; // @[RocketCore.scala:153:7] wire io_interrupts_debug_0 = io_interrupts_debug; // @[RocketCore.scala:153:7] wire io_interrupts_mtip_0 = io_interrupts_mtip; // @[RocketCore.scala:153:7] wire io_interrupts_msip_0 = io_interrupts_msip; // @[RocketCore.scala:153:7] wire io_interrupts_meip_0 = io_interrupts_meip; // @[RocketCore.scala:153:7] wire io_interrupts_seip_0 = io_interrupts_seip; // @[RocketCore.scala:153:7] wire io_imem_resp_valid_0 = io_imem_resp_valid; // @[RocketCore.scala:153:7] wire [1:0] io_imem_resp_bits_btb_cfiType_0 = io_imem_resp_bits_btb_cfiType; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_btb_taken_0 = io_imem_resp_bits_btb_taken; // @[RocketCore.scala:153:7] wire [1:0] io_imem_resp_bits_btb_mask_0 = io_imem_resp_bits_btb_mask; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_btb_bridx_0 = io_imem_resp_bits_btb_bridx; // @[RocketCore.scala:153:7] wire [38:0] io_imem_resp_bits_btb_target_0 = io_imem_resp_bits_btb_target; // @[RocketCore.scala:153:7] wire [4:0] io_imem_resp_bits_btb_entry_0 = io_imem_resp_bits_btb_entry; // @[RocketCore.scala:153:7] wire [7:0] io_imem_resp_bits_btb_bht_history_0 = io_imem_resp_bits_btb_bht_history; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_btb_bht_value_0 = io_imem_resp_bits_btb_bht_value; // @[RocketCore.scala:153:7] wire [39:0] io_imem_resp_bits_pc_0 = io_imem_resp_bits_pc; // @[RocketCore.scala:153:7] wire [31:0] io_imem_resp_bits_data_0 = io_imem_resp_bits_data; // @[RocketCore.scala:153:7] wire [1:0] io_imem_resp_bits_mask_0 = io_imem_resp_bits_mask; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_xcpt_pf_inst_0 = io_imem_resp_bits_xcpt_pf_inst; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_xcpt_gf_inst_0 = io_imem_resp_bits_xcpt_gf_inst; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_xcpt_ae_inst_0 = io_imem_resp_bits_xcpt_ae_inst; // @[RocketCore.scala:153:7] wire io_imem_resp_bits_replay_0 = io_imem_resp_bits_replay; // @[RocketCore.scala:153:7] wire io_imem_gpa_valid_0 = io_imem_gpa_valid; // @[RocketCore.scala:153:7] wire [39:0] io_imem_gpa_bits_0 = io_imem_gpa_bits; // @[RocketCore.scala:153:7] wire io_imem_gpa_is_pte_0 = io_imem_gpa_is_pte; // @[RocketCore.scala:153:7] wire [39:0] io_imem_npc_0 = io_imem_npc; // @[RocketCore.scala:153:7] wire io_imem_perf_acquire_0 = io_imem_perf_acquire; // @[RocketCore.scala:153:7] wire io_imem_perf_tlbMiss_0 = io_imem_perf_tlbMiss; // @[RocketCore.scala:153:7] wire io_dmem_req_ready_0 = io_dmem_req_ready; // @[RocketCore.scala:153:7] wire io_dmem_s2_nack_0 = io_dmem_s2_nack; // @[RocketCore.scala:153:7] wire io_dmem_s2_nack_cause_raw_0 = io_dmem_s2_nack_cause_raw; // @[RocketCore.scala:153:7] wire io_dmem_s2_uncached_0 = io_dmem_s2_uncached; // @[RocketCore.scala:153:7] wire [31:0] io_dmem_s2_paddr_0 = io_dmem_s2_paddr; // @[RocketCore.scala:153:7] wire io_dmem_resp_valid_0 = io_dmem_resp_valid; // @[RocketCore.scala:153:7] wire [39:0] io_dmem_resp_bits_addr_0 = io_dmem_resp_bits_addr; // @[RocketCore.scala:153:7] wire [6:0] io_dmem_resp_bits_tag_0 = io_dmem_resp_bits_tag; // @[RocketCore.scala:153:7] wire [4:0] io_dmem_resp_bits_cmd_0 = io_dmem_resp_bits_cmd; // @[RocketCore.scala:153:7] wire [1:0] io_dmem_resp_bits_size_0 = io_dmem_resp_bits_size; // @[RocketCore.scala:153:7] wire io_dmem_resp_bits_signed_0 = io_dmem_resp_bits_signed; // @[RocketCore.scala:153:7] wire [1:0] io_dmem_resp_bits_dprv_0 = io_dmem_resp_bits_dprv; // @[RocketCore.scala:153:7] wire io_dmem_resp_bits_dv_0 = io_dmem_resp_bits_dv; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_resp_bits_data_0 = io_dmem_resp_bits_data; // @[RocketCore.scala:153:7] wire [7:0] io_dmem_resp_bits_mask_0 = io_dmem_resp_bits_mask; // @[RocketCore.scala:153:7] wire io_dmem_resp_bits_replay_0 = io_dmem_resp_bits_replay; // @[RocketCore.scala:153:7] wire io_dmem_resp_bits_has_data_0 = io_dmem_resp_bits_has_data; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_resp_bits_data_word_bypass_0 = io_dmem_resp_bits_data_word_bypass; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_resp_bits_data_raw_0 = io_dmem_resp_bits_data_raw; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_resp_bits_store_data_0 = io_dmem_resp_bits_store_data; // @[RocketCore.scala:153:7] wire io_dmem_replay_next_0 = io_dmem_replay_next; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_ma_ld_0 = io_dmem_s2_xcpt_ma_ld; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_ma_st_0 = io_dmem_s2_xcpt_ma_st; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_pf_ld_0 = io_dmem_s2_xcpt_pf_ld; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_pf_st_0 = io_dmem_s2_xcpt_pf_st; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_ae_ld_0 = io_dmem_s2_xcpt_ae_ld; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_ae_st_0 = io_dmem_s2_xcpt_ae_st; // @[RocketCore.scala:153:7] wire [39:0] io_dmem_s2_gpa_0 = io_dmem_s2_gpa; // @[RocketCore.scala:153:7] wire io_dmem_ordered_0 = io_dmem_ordered; // @[RocketCore.scala:153:7] wire io_dmem_store_pending_0 = io_dmem_store_pending; // @[RocketCore.scala:153:7] wire io_dmem_perf_acquire_0 = io_dmem_perf_acquire; // @[RocketCore.scala:153:7] wire io_dmem_perf_release_0 = io_dmem_perf_release; // @[RocketCore.scala:153:7] wire io_dmem_perf_grant_0 = io_dmem_perf_grant; // @[RocketCore.scala:153:7] wire io_dmem_perf_tlbMiss_0 = io_dmem_perf_tlbMiss; // @[RocketCore.scala:153:7] wire io_dmem_perf_blocked_0 = io_dmem_perf_blocked; // @[RocketCore.scala:153:7] wire io_dmem_perf_canAcceptStoreThenLoad_0 = io_dmem_perf_canAcceptStoreThenLoad; // @[RocketCore.scala:153:7] wire io_dmem_perf_canAcceptStoreThenRMW_0 = io_dmem_perf_canAcceptStoreThenRMW; // @[RocketCore.scala:153:7] wire io_dmem_perf_canAcceptLoadThenLoad_0 = io_dmem_perf_canAcceptLoadThenLoad; // @[RocketCore.scala:153:7] wire io_dmem_perf_storeBufferEmptyAfterLoad_0 = io_dmem_perf_storeBufferEmptyAfterLoad; // @[RocketCore.scala:153:7] wire io_dmem_perf_storeBufferEmptyAfterStore_0 = io_dmem_perf_storeBufferEmptyAfterStore; // @[RocketCore.scala:153:7] wire io_ptw_perf_pte_miss_0 = io_ptw_perf_pte_miss; // @[RocketCore.scala:153:7] wire io_ptw_perf_pte_hit_0 = io_ptw_perf_pte_hit; // @[RocketCore.scala:153:7] wire io_ptw_clock_enabled_0 = io_ptw_clock_enabled; // @[RocketCore.scala:153:7] wire io_fpu_fcsr_flags_valid_0 = io_fpu_fcsr_flags_valid; // @[RocketCore.scala:153:7] wire [4:0] io_fpu_fcsr_flags_bits_0 = io_fpu_fcsr_flags_bits; // @[RocketCore.scala:153:7] wire [63:0] io_fpu_store_data_0 = io_fpu_store_data; // @[RocketCore.scala:153:7] wire [63:0] io_fpu_toint_data_0 = io_fpu_toint_data; // @[RocketCore.scala:153:7] wire io_fpu_fcsr_rdy_0 = io_fpu_fcsr_rdy; // @[RocketCore.scala:153:7] wire io_fpu_nack_mem_0 = io_fpu_nack_mem; // @[RocketCore.scala:153:7] wire io_fpu_illegal_rm_0 = io_fpu_illegal_rm; // @[RocketCore.scala:153:7] wire io_fpu_dec_ldst_0 = io_fpu_dec_ldst; // @[RocketCore.scala:153:7] wire io_fpu_dec_wen_0 = io_fpu_dec_wen; // @[RocketCore.scala:153:7] wire io_fpu_dec_ren1_0 = io_fpu_dec_ren1; // @[RocketCore.scala:153:7] wire io_fpu_dec_ren2_0 = io_fpu_dec_ren2; // @[RocketCore.scala:153:7] wire io_fpu_dec_ren3_0 = io_fpu_dec_ren3; // @[RocketCore.scala:153:7] wire io_fpu_dec_swap12_0 = io_fpu_dec_swap12; // @[RocketCore.scala:153:7] wire io_fpu_dec_swap23_0 = io_fpu_dec_swap23; // @[RocketCore.scala:153:7] wire [1:0] io_fpu_dec_typeTagIn_0 = io_fpu_dec_typeTagIn; // @[RocketCore.scala:153:7] wire [1:0] io_fpu_dec_typeTagOut_0 = io_fpu_dec_typeTagOut; // @[RocketCore.scala:153:7] wire io_fpu_dec_fromint_0 = io_fpu_dec_fromint; // @[RocketCore.scala:153:7] wire io_fpu_dec_toint_0 = io_fpu_dec_toint; // @[RocketCore.scala:153:7] wire io_fpu_dec_fastpipe_0 = io_fpu_dec_fastpipe; // @[RocketCore.scala:153:7] wire io_fpu_dec_fma_0 = io_fpu_dec_fma; // @[RocketCore.scala:153:7] wire io_fpu_dec_div_0 = io_fpu_dec_div; // @[RocketCore.scala:153:7] wire io_fpu_dec_sqrt_0 = io_fpu_dec_sqrt; // @[RocketCore.scala:153:7] wire io_fpu_dec_wflags_0 = io_fpu_dec_wflags; // @[RocketCore.scala:153:7] wire io_fpu_dec_vec_0 = io_fpu_dec_vec; // @[RocketCore.scala:153:7] wire io_fpu_sboard_set_0 = io_fpu_sboard_set; // @[RocketCore.scala:153:7] wire io_fpu_sboard_clr_0 = io_fpu_sboard_clr; // @[RocketCore.scala:153:7] wire [4:0] io_fpu_sboard_clra_0 = io_fpu_sboard_clra; // @[RocketCore.scala:153:7] wire coreMonitorBundle_clock = clock; // @[RocketCore.scala:1186:31] wire coreMonitorBundle_reset = reset; // @[RocketCore.scala:1186:31] wire xrfWriteBundle_clock = clock; // @[RocketCore.scala:1249:28] wire xrfWriteBundle_reset = reset; // @[RocketCore.scala:1249:28] wire io_imem_clock_enabled = 1'h1; // @[RocketCore.scala:153:7] wire io_dmem_clock_enabled = 1'h1; // @[RocketCore.scala:153:7] wire clock_en = 1'h1; // @[RocketCore.scala:153:7, :163:29] wire _id_npc_b19_12_T = 1'h1; // @[RocketCore.scala:153:7, :1343:26] wire _id_npc_b11_T_3 = 1'h1; // @[RocketCore.scala:153:7, :1345:23] wire _id_illegal_insn_T_10 = 1'h1; // @[RocketCore.scala:153:7, :384:73] wire _id_illegal_insn_T_15 = 1'h1; // @[RocketCore.scala:153:7, :385:55] wire _mem_br_target_b19_12_T = 1'h1; // @[RocketCore.scala:153:7, :1343:26] wire _mem_br_target_b19_12_T_1 = 1'h1; // @[RocketCore.scala:153:7, :1343:43] wire _mem_br_target_b19_12_T_2 = 1'h1; // @[RocketCore.scala:153:7, :1343:36] wire _mem_br_target_b11_T_6 = 1'h1; // @[RocketCore.scala:153:7, :1346:23] wire _mem_br_target_b4_1_T_2 = 1'h1; // @[RocketCore.scala:153:7, :1349:41] wire _mem_br_target_b4_1_T_3 = 1'h1; // @[RocketCore.scala:153:7, :1349:34] wire _mem_br_target_b19_12_T_5 = 1'h1; // @[RocketCore.scala:153:7, :1343:26] wire _mem_br_target_b11_T_14 = 1'h1; // @[RocketCore.scala:153:7, :1345:23] wire _wb_reg_xcpt_T_2 = 1'h1; // @[RocketCore.scala:153:7, :707:45] wire _replay_wb_rocc_T_1 = 1'h1; // @[RocketCore.scala:153:7, :758:56] wire _rocc_blocked_T_1 = 1'h1; // @[RocketCore.scala:153:7, :1029:31] wire io_imem_btb_update_bits_taken = 1'h0; // @[RocketCore.scala:153:7] wire io_imem_ras_update_valid = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_phys = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_no_alloc = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_no_xcpt = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_s2_kill = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_gf_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_s2_xcpt_gf_st = 1'h0; // @[RocketCore.scala:153:7] wire io_dmem_s2_gpa_is_pte = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_mbe = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_sbe = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_ube = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_upie = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_hie = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_status_uie = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_vtw = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_hu = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_perf_l2miss = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_perf_l2hit = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_ready = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mbe = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sbe = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sd_rv32 = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_ube = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_upie = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_hie = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_uie = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_resp_ready = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_resp_valid = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_ready = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_valid = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_signed = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_dv = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_phys = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_no_resp = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_no_alloc = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_req_bits_no_xcpt = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s1_kill = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_nack = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_nack_cause_raw = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_kill = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_uncached = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_valid = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_bits_signed = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_bits_dv = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_bits_replay = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_resp_bits_has_data = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_replay_next = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_ma_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_ma_st = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_pf_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_pf_st = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_gf_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_gf_st = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_ae_ld = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_xcpt_ae_st = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_s2_gpa_is_pte = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_ordered = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_store_pending = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_acquire = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_release = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_grant = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_tlbMiss = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_blocked = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_keep_clock_enabled = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_mem_clock_enabled = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_busy = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_interrupt = 1'h0; // @[RocketCore.scala:153:7] wire io_rocc_exception = 1'h0; // @[RocketCore.scala:153:7] wire io_bpwatch_0_rvalid_0 = 1'h0; // @[RocketCore.scala:153:7] wire io_bpwatch_0_wvalid_0 = 1'h0; // @[RocketCore.scala:153:7] wire io_bpwatch_0_ivalid_0 = 1'h0; // @[RocketCore.scala:153:7] wire io_cease = 1'h0; // @[RocketCore.scala:153:7] wire io_traceStall = 1'h0; // @[RocketCore.scala:153:7] wire _hits_WIRE_0 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_3 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_4 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_5 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_6 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_7 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_8 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_9 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_10 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_11 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_12 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_13 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_14 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_15 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_16 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_17 = 1'h0; // @[Events.scala:13:33] wire hits_0 = 1'h0; // @[Events.scala:13:25] wire hits_1 = 1'h0; // @[Events.scala:13:25] wire hits_2 = 1'h0; // @[Events.scala:13:25] wire hits_3 = 1'h0; // @[Events.scala:13:25] wire hits_4 = 1'h0; // @[Events.scala:13:25] wire hits_5 = 1'h0; // @[Events.scala:13:25] wire hits_6 = 1'h0; // @[Events.scala:13:25] wire hits_7 = 1'h0; // @[Events.scala:13:25] wire hits_8 = 1'h0; // @[Events.scala:13:25] wire hits_9 = 1'h0; // @[Events.scala:13:25] wire hits_10 = 1'h0; // @[Events.scala:13:25] wire hits_11 = 1'h0; // @[Events.scala:13:25] wire hits_12 = 1'h0; // @[Events.scala:13:25] wire hits_13 = 1'h0; // @[Events.scala:13:25] wire hits_14 = 1'h0; // @[Events.scala:13:25] wire hits_15 = 1'h0; // @[Events.scala:13:25] wire hits_16 = 1'h0; // @[Events.scala:13:25] wire hits_17 = 1'h0; // @[Events.scala:13:25] wire _hits_WIRE_1_0 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_1 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_2 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_3 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_4 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_5 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_6 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_7 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_8 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_9 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_10 = 1'h0; // @[Events.scala:13:33] wire hits_1_0 = 1'h0; // @[Events.scala:13:25] wire hits_1_1 = 1'h0; // @[Events.scala:13:25] wire hits_1_2 = 1'h0; // @[Events.scala:13:25] wire hits_1_3 = 1'h0; // @[Events.scala:13:25] wire hits_1_4 = 1'h0; // @[Events.scala:13:25] wire hits_1_5 = 1'h0; // @[Events.scala:13:25] wire hits_1_6 = 1'h0; // @[Events.scala:13:25] wire hits_1_7 = 1'h0; // @[Events.scala:13:25] wire hits_1_8 = 1'h0; // @[Events.scala:13:25] wire hits_1_9 = 1'h0; // @[Events.scala:13:25] wire hits_1_10 = 1'h0; // @[Events.scala:13:25] wire _hits_WIRE_2_0 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_1 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_2 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_3 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_4 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_5 = 1'h0; // @[Events.scala:13:33] wire hits_2_0 = 1'h0; // @[Events.scala:13:25] wire hits_2_1 = 1'h0; // @[Events.scala:13:25] wire hits_2_2 = 1'h0; // @[Events.scala:13:25] wire hits_2_3 = 1'h0; // @[Events.scala:13:25] wire hits_2_4 = 1'h0; // @[Events.scala:13:25] wire hits_2_5 = 1'h0; // @[Events.scala:13:25] wire id_ctrl_vec = 1'h0; // @[RocketCore.scala:321:21] wire _id_rs_T_1 = 1'h0; // @[RocketCore.scala:1326:33] wire _id_rs_T_6 = 1'h0; // @[RocketCore.scala:1326:33] wire _id_npc_sign_T = 1'h0; // @[RocketCore.scala:1341:24] wire _id_npc_b30_20_T = 1'h0; // @[RocketCore.scala:1342:26] wire _id_npc_b19_12_T_1 = 1'h0; // @[RocketCore.scala:1343:43] wire _id_npc_b19_12_T_2 = 1'h0; // @[RocketCore.scala:1343:36] wire _id_npc_b11_T = 1'h0; // @[RocketCore.scala:1344:23] wire _id_npc_b11_T_1 = 1'h0; // @[RocketCore.scala:1344:40] wire _id_npc_b11_T_2 = 1'h0; // @[RocketCore.scala:1344:33] wire _id_npc_b11_T_6 = 1'h0; // @[RocketCore.scala:1346:23] wire _id_npc_b10_5_T = 1'h0; // @[RocketCore.scala:1347:25] wire _id_npc_b10_5_T_1 = 1'h0; // @[RocketCore.scala:1347:42] wire _id_npc_b10_5_T_2 = 1'h0; // @[RocketCore.scala:1347:35] wire _id_npc_b4_1_T = 1'h0; // @[RocketCore.scala:1348:24] wire _id_npc_b4_1_T_1 = 1'h0; // @[RocketCore.scala:1349:24] wire _id_npc_b4_1_T_2 = 1'h0; // @[RocketCore.scala:1349:41] wire _id_npc_b4_1_T_3 = 1'h0; // @[RocketCore.scala:1349:34] wire _id_npc_b4_1_T_5 = 1'h0; // @[RocketCore.scala:1350:24] wire _id_npc_b0_T = 1'h0; // @[RocketCore.scala:1351:22] wire _id_npc_b0_T_2 = 1'h0; // @[RocketCore.scala:1352:22] wire _id_npc_b0_T_4 = 1'h0; // @[RocketCore.scala:1353:22] wire _id_npc_b0_T_6 = 1'h0; // @[RocketCore.scala:1353:17] wire _id_npc_b0_T_7 = 1'h0; // @[RocketCore.scala:1352:17] wire id_npc_b0 = 1'h0; // @[RocketCore.scala:1351:17] wire id_set_vconfig = 1'h0; // @[RocketCore.scala:347:120] wire _id_illegal_insn_T_16 = 1'h0; // @[RocketCore.scala:385:19] wire _id_illegal_insn_T_26 = 1'h0; // @[RocketCore.scala:388:23] wire _id_illegal_insn_T_28 = 1'h0; // @[RocketCore.scala:389:23] wire _id_illegal_insn_T_30 = 1'h0; // @[RocketCore.scala:390:22] wire id_rocc_busy = 1'h0; // @[RocketCore.scala:405:34] wire _id_csr_rocc_write_T = 1'h0; // @[RocketCore.scala:408:87] wire id_csr_rocc_write = 1'h0; // @[RocketCore.scala:408:100] wire _id_do_fence_T_1 = 1'h0; // @[RocketCore.scala:410:46] wire _id_do_fence_T_2 = 1'h0; // @[RocketCore.scala:411:17] wire _id_do_fence_T_3 = 1'h0; // @[RocketCore.scala:410:86] wire _ex_reg_hls_T = 1'h0; // @[RocketCore.scala:553:37] wire _ex_reg_hls_T_6 = 1'h0; // @[RocketCore.scala:553:55] wire _ex_reg_mem_size_T = 1'h0; // @[RocketCore.scala:554:46] wire _ex_reg_set_vconfig_T_1 = 1'h0; // @[RocketCore.scala:591:42] wire _replay_ex_structural_T_5 = 1'h0; // @[RocketCore.scala:599:45] wire _replay_ex_structural_T_6 = 1'h0; // @[RocketCore.scala:599:42] wire _mem_br_target_sign_T = 1'h0; // @[RocketCore.scala:1341:24] wire _mem_br_target_b30_20_T = 1'h0; // @[RocketCore.scala:1342:26] wire _mem_br_target_b11_T = 1'h0; // @[RocketCore.scala:1344:23] wire _mem_br_target_b11_T_1 = 1'h0; // @[RocketCore.scala:1344:40] wire _mem_br_target_b11_T_2 = 1'h0; // @[RocketCore.scala:1344:33] wire _mem_br_target_b11_T_3 = 1'h0; // @[RocketCore.scala:1345:23] wire _mem_br_target_b10_5_T = 1'h0; // @[RocketCore.scala:1347:25] wire _mem_br_target_b10_5_T_1 = 1'h0; // @[RocketCore.scala:1347:42] wire _mem_br_target_b10_5_T_2 = 1'h0; // @[RocketCore.scala:1347:35] wire _mem_br_target_b4_1_T = 1'h0; // @[RocketCore.scala:1348:24] wire _mem_br_target_b4_1_T_1 = 1'h0; // @[RocketCore.scala:1349:24] wire _mem_br_target_b4_1_T_5 = 1'h0; // @[RocketCore.scala:1350:24] wire _mem_br_target_b0_T = 1'h0; // @[RocketCore.scala:1351:22] wire _mem_br_target_b0_T_2 = 1'h0; // @[RocketCore.scala:1352:22] wire _mem_br_target_b0_T_4 = 1'h0; // @[RocketCore.scala:1353:22] wire _mem_br_target_b0_T_6 = 1'h0; // @[RocketCore.scala:1353:17] wire _mem_br_target_b0_T_7 = 1'h0; // @[RocketCore.scala:1352:17] wire mem_br_target_b0 = 1'h0; // @[RocketCore.scala:1351:17] wire _mem_br_target_sign_T_3 = 1'h0; // @[RocketCore.scala:1341:24] wire _mem_br_target_b30_20_T_3 = 1'h0; // @[RocketCore.scala:1342:26] wire _mem_br_target_b19_12_T_6 = 1'h0; // @[RocketCore.scala:1343:43] wire _mem_br_target_b19_12_T_7 = 1'h0; // @[RocketCore.scala:1343:36] wire _mem_br_target_b11_T_11 = 1'h0; // @[RocketCore.scala:1344:23] wire _mem_br_target_b11_T_12 = 1'h0; // @[RocketCore.scala:1344:40] wire _mem_br_target_b11_T_13 = 1'h0; // @[RocketCore.scala:1344:33] wire _mem_br_target_b11_T_17 = 1'h0; // @[RocketCore.scala:1346:23] wire _mem_br_target_b10_5_T_4 = 1'h0; // @[RocketCore.scala:1347:25] wire _mem_br_target_b10_5_T_5 = 1'h0; // @[RocketCore.scala:1347:42] wire _mem_br_target_b10_5_T_6 = 1'h0; // @[RocketCore.scala:1347:35] wire _mem_br_target_b4_1_T_10 = 1'h0; // @[RocketCore.scala:1348:24] wire _mem_br_target_b4_1_T_11 = 1'h0; // @[RocketCore.scala:1349:24] wire _mem_br_target_b4_1_T_12 = 1'h0; // @[RocketCore.scala:1349:41] wire _mem_br_target_b4_1_T_13 = 1'h0; // @[RocketCore.scala:1349:34] wire _mem_br_target_b4_1_T_15 = 1'h0; // @[RocketCore.scala:1350:24] wire _mem_br_target_b0_T_8 = 1'h0; // @[RocketCore.scala:1351:22] wire _mem_br_target_b0_T_10 = 1'h0; // @[RocketCore.scala:1352:22] wire _mem_br_target_b0_T_12 = 1'h0; // @[RocketCore.scala:1353:22] wire _mem_br_target_b0_T_14 = 1'h0; // @[RocketCore.scala:1353:17] wire _mem_br_target_b0_T_15 = 1'h0; // @[RocketCore.scala:1352:17] wire mem_br_target_b0_1 = 1'h0; // @[RocketCore.scala:1351:17] wire vec_kill_mem = 1'h0; // @[RocketCore.scala:697:52] wire vec_kill_all = 1'h0; // @[RocketCore.scala:698:36] wire replay_wb_csr = 1'h0; // @[RocketCore.scala:759:42] wire replay_wb_vec = 1'h0; // @[RocketCore.scala:760:36] wire _htval_valid_dmem_T_2 = 1'h0; // @[RocketCore.scala:857:83] wire _htval_valid_dmem_T_3 = 1'h0; // @[RocketCore.scala:857:54] wire htval_valid_dmem = 1'h0; // @[RocketCore.scala:857:87] wire _mhtinst_read_pseudo_T_1 = 1'h0; // @[RocketCore.scala:862:98] wire _id_vconfig_hazard_T = 1'h0; // @[RocketCore.scala:1003:19] wire id_vconfig_hazard = 1'h0; // @[RocketCore.scala:1002:39] wire _ctrl_stalld_T_12 = 1'h0; // @[RocketCore.scala:1036:15] wire _ctrl_stalld_T_13 = 1'h0; // @[RocketCore.scala:1036:46] wire _ctrl_stalld_T_28 = 1'h0; // @[RocketCore.scala:1041:5] wire _io_rocc_exception_T = 1'h0; // @[RocketCore.scala:1157:52] wire _io_rocc_exception_T_1 = 1'h0; // @[RocketCore.scala:1157:32] wire _io_cease_T = 1'h0; // @[RocketCore.scala:1166:38] wire _io_cease_T_1 = 1'h0; // @[RocketCore.scala:1166:35] wire coreMonitorBundle_wrenf = 1'h0; // @[RocketCore.scala:1186:31] wire xrfWriteBundle_excpt = 1'h0; // @[RocketCore.scala:1249:28] wire xrfWriteBundle_valid = 1'h0; // @[RocketCore.scala:1249:28] wire xrfWriteBundle_wrenf = 1'h0; // @[RocketCore.scala:1249:28] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[RocketCore.scala:153:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[RocketCore.scala:153:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[RocketCore.scala:153:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[RocketCore.scala:153:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[RocketCore.scala:153:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[RocketCore.scala:153:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[RocketCore.scala:153:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[RocketCore.scala:153:7] wire [22:0] io_rocc_cmd_bits_status_zero2 = 23'h0; // @[RocketCore.scala:153:7] wire [7:0] io_dmem_req_bits_mask = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_dmem_s1_data_mask = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_rocc_cmd_bits_status_zero1 = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_rocc_mem_req_bits_mask = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_rocc_mem_s1_data_mask = 8'h0; // @[RocketCore.scala:153:7] wire [7:0] io_rocc_mem_resp_bits_mask = 8'h0; // @[RocketCore.scala:153:7] wire [1:0] io_imem_ras_update_bits_cfiType = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_xs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_xs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_vs = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_mem_req_bits_size = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_mem_req_bits_dprv = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_mem_resp_bits_size = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_mem_resp_bits_dprv = 2'h0; // @[RocketCore.scala:153:7] wire [1:0] _htval_valid_dmem_T_1 = 2'h0; // @[RocketCore.scala:857:76] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[RocketCore.scala:153:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[RocketCore.scala:153:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[RocketCore.scala:153:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_resp_bits_rd = 5'h0; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_mem_req_bits_cmd = 5'h0; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_mem_resp_bits_cmd = 5'h0; // @[RocketCore.scala:153:7] wire [4:0] _csr_io_fcsr_flags_bits_T_2 = 5'h0; // @[RocketCore.scala:839:116] wire [4:0] _csr_io_fcsr_flags_bits_T_3 = 5'h0; // @[RocketCore.scala:839:110] wire [4:0] xrfWriteBundle_rd0src = 5'h0; // @[RocketCore.scala:1249:28] wire [4:0] xrfWriteBundle_rd1src = 5'h0; // @[RocketCore.scala:1249:28] wire [39:0] io_rocc_mem_req_bits_addr = 40'h0; // @[RocketCore.scala:153:7] wire [39:0] io_rocc_mem_resp_bits_addr = 40'h0; // @[RocketCore.scala:153:7] wire [39:0] io_rocc_mem_s2_gpa = 40'h0; // @[RocketCore.scala:153:7] wire [39:0] htval_dmem = 40'h0; // @[RocketCore.scala:858:25] wire [31:0] io_reset_vector = 32'h0; // @[RocketCore.scala:153:7] wire [31:0] io_rocc_mem_s2_paddr = 32'h0; // @[RocketCore.scala:153:7] wire [31:0] xrfWriteBundle_inst = 32'h0; // @[RocketCore.scala:1249:28] wire [38:0] io_imem_ras_update_bits_returnAddr = 39'h0; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_req_bits_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_resp_bits_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_req_bits_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_s1_data_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_resp_bits_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_resp_bits_data_word_bypass = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_resp_bits_data_raw = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_mem_resp_bits_store_data = 64'h0; // @[RocketCore.scala:153:7] wire [63:0] xrfWriteBundle_pc = 64'h0; // @[RocketCore.scala:1249:28] wire [63:0] xrfWriteBundle_rd0val = 64'h0; // @[RocketCore.scala:1249:28] wire [63:0] xrfWriteBundle_rd1val = 64'h0; // @[RocketCore.scala:1249:28] wire [1:0] io_ptw_status_sxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_sxl = 2'h2; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_uxl = 2'h2; // @[RocketCore.scala:153:7] wire [2:0] io_fpu_v_sew = 3'h0; // @[RocketCore.scala:153:7] wire [6:0] io_rocc_mem_req_bits_tag = 7'h0; // @[RocketCore.scala:153:7] wire [6:0] io_rocc_mem_resp_bits_tag = 7'h0; // @[RocketCore.scala:153:7] wire [2:0] io_fpu_hartid_0 = io_hartid_0; // @[RocketCore.scala:153:7] wire take_pc_mem_wb; // @[RocketCore.scala:307:35] wire [39:0] _io_imem_req_bits_pc_T_2; // @[RocketCore.scala:1051:8] wire _io_imem_req_bits_speculative_T; // @[RocketCore.scala:1049:35] wire _io_imem_sfence_valid_T; // @[RocketCore.scala:1060:40] wire io_ptw_sfence_valid_0 = io_imem_sfence_valid_0; // @[RocketCore.scala:153:7] wire _io_imem_sfence_bits_rs1_T; // @[RocketCore.scala:1061:45] wire io_ptw_sfence_bits_rs1_0 = io_imem_sfence_bits_rs1_0; // @[RocketCore.scala:153:7] wire _io_imem_sfence_bits_rs2_T; // @[RocketCore.scala:1062:45] wire io_ptw_sfence_bits_rs2_0 = io_imem_sfence_bits_rs2_0; // @[RocketCore.scala:153:7] wire [38:0] io_ptw_sfence_bits_addr_0 = io_imem_sfence_bits_addr_0; // @[RocketCore.scala:153:7] wire io_ptw_sfence_bits_asid_0 = io_imem_sfence_bits_asid_0; // @[RocketCore.scala:153:7] wire io_ptw_sfence_bits_hv_0 = io_imem_sfence_bits_hv_0; // @[RocketCore.scala:153:7] wire io_ptw_sfence_bits_hg_0 = io_imem_sfence_bits_hg_0; // @[RocketCore.scala:153:7] wire _io_imem_btb_update_valid_T_5; // @[RocketCore.scala:1071:77] wire [38:0] _io_imem_btb_update_bits_pc_T_2; // @[RocketCore.scala:1080:33] wire [38:0] io_imem_bht_update_bits_pc_0 = io_imem_btb_update_bits_pc_0; // @[RocketCore.scala:153:7] wire mem_cfi; // @[RocketCore.scala:625:50] wire [1:0] _io_imem_btb_update_bits_cfiType_T_11; // @[RocketCore.scala:1074:8] wire _io_imem_bht_update_valid_T_1; // @[RocketCore.scala:1084:45] wire mem_wrong_npc; // @[RocketCore.scala:621:8] wire _io_imem_flush_icache_T_2; // @[RocketCore.scala:1054:59] wire _io_dmem_req_valid_T; // @[RocketCore.scala:1130:41] wire [39:0] _io_dmem_req_bits_addr_T_1; // @[RocketCore.scala:1295:8] wire _io_dmem_req_bits_signed_T_3; // @[RocketCore.scala:1136:30] wire [1:0] _io_dmem_req_bits_dprv_T; // @[RocketCore.scala:1140:31] wire _io_dmem_req_bits_dv_T; // @[RocketCore.scala:1141:37] wire _io_dmem_req_bits_no_resp_T_29; // @[RocketCore.scala:1142:56] wire _io_dmem_s1_kill_T_2; // @[RocketCore.scala:1151:68] wire [63:0] _io_dmem_s1_data_data_T; // @[RocketCore.scala:1148:63] wire [63:0] io_fpu_ll_resp_data_0 = io_dmem_resp_bits_data_0; // @[RocketCore.scala:153:7] wire [63:0] _rf_wdata_T_1 = io_dmem_resp_bits_data_0; // @[RocketCore.scala:153:7, :819:78] wire [63:0] dcache_bypass_data = io_dmem_resp_bits_data_word_bypass_0; // @[RocketCore.scala:153:7, :449:62] wire _io_dmem_keep_clock_enabled_T_2; // @[RocketCore.scala:1154:70] wire [63:0] ex_rs_0; // @[RocketCore.scala:469:14] wire _csr_io_fcsr_flags_valid_T = io_fpu_fcsr_flags_valid_0; // @[RocketCore.scala:153:7, :838:54] wire _io_fpu_ll_resp_val_T; // @[RocketCore.scala:1099:41] wire [4:0] dmem_resp_waddr; // @[RocketCore.scala:767:46] wire _io_fpu_valid_T_1; // @[RocketCore.scala:1094:31] wire _id_illegal_insn_T_11 = io_fpu_illegal_rm_0; // @[RocketCore.scala:153:7, :384:70] wire ctrl_killx; // @[RocketCore.scala:602:48] wire killm_common; // @[RocketCore.scala:700:68] wire _io_fpu_keep_clock_enabled_T; // @[CustomCSRs.scala:45:59] wire _io_rocc_cmd_valid_T_2; // @[RocketCore.scala:1156:53] wire [6:0] _io_rocc_cmd_bits_inst_WIRE_funct; // @[RocketCore.scala:1159:48] wire [4:0] _io_rocc_cmd_bits_inst_WIRE_rs2; // @[RocketCore.scala:1159:48] wire [4:0] _io_rocc_cmd_bits_inst_WIRE_rs1; // @[RocketCore.scala:1159:48] wire _io_rocc_cmd_bits_inst_WIRE_xd; // @[RocketCore.scala:1159:48] wire _io_rocc_cmd_bits_inst_WIRE_xs1; // @[RocketCore.scala:1159:48] wire _io_rocc_cmd_bits_inst_WIRE_xs2; // @[RocketCore.scala:1159:48] wire [4:0] _io_rocc_cmd_bits_inst_WIRE_rd; // @[RocketCore.scala:1159:48] wire [6:0] _io_rocc_cmd_bits_inst_WIRE_opcode; // @[RocketCore.scala:1159:48] wire [39:0] io_imem_req_bits_pc_0; // @[RocketCore.scala:153:7] wire io_imem_req_bits_speculative_0; // @[RocketCore.scala:153:7] wire io_imem_req_valid_0; // @[RocketCore.scala:153:7] wire io_imem_resp_ready_0; // @[RocketCore.scala:153:7] wire [7:0] io_imem_btb_update_bits_prediction_bht_history_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_bits_prediction_bht_value_0; // @[RocketCore.scala:153:7] wire [1:0] io_imem_btb_update_bits_prediction_cfiType_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_bits_prediction_taken_0; // @[RocketCore.scala:153:7] wire [1:0] io_imem_btb_update_bits_prediction_mask_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_bits_prediction_bridx_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_btb_update_bits_prediction_target_0; // @[RocketCore.scala:153:7] wire [4:0] io_imem_btb_update_bits_prediction_entry_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_btb_update_bits_target_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_bits_isValid_0; // @[RocketCore.scala:153:7] wire [38:0] io_imem_btb_update_bits_br_pc_0; // @[RocketCore.scala:153:7] wire [1:0] io_imem_btb_update_bits_cfiType_0; // @[RocketCore.scala:153:7] wire io_imem_btb_update_valid_0; // @[RocketCore.scala:153:7] wire [7:0] io_imem_bht_update_bits_prediction_history_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_bits_prediction_value_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_bits_branch_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_bits_taken_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_bits_mispredict_0; // @[RocketCore.scala:153:7] wire io_imem_bht_update_valid_0; // @[RocketCore.scala:153:7] wire io_imem_might_request_0; // @[RocketCore.scala:153:7] wire io_imem_flush_icache_0; // @[RocketCore.scala:153:7] wire io_imem_progress_0; // @[RocketCore.scala:153:7] wire [39:0] io_dmem_req_bits_addr_0; // @[RocketCore.scala:153:7] wire [6:0] io_dmem_req_bits_tag_0; // @[RocketCore.scala:153:7] wire [4:0] io_dmem_req_bits_cmd_0; // @[RocketCore.scala:153:7] wire [1:0] io_dmem_req_bits_size_0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_signed_0; // @[RocketCore.scala:153:7] wire [1:0] io_dmem_req_bits_dprv_0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_dv_0; // @[RocketCore.scala:153:7] wire io_dmem_req_bits_no_resp_0; // @[RocketCore.scala:153:7] wire io_dmem_req_valid_0; // @[RocketCore.scala:153:7] wire [63:0] io_dmem_s1_data_data_0; // @[RocketCore.scala:153:7] wire io_dmem_s1_kill_0; // @[RocketCore.scala:153:7] wire io_dmem_keep_clock_enabled_0; // @[RocketCore.scala:153:7] wire [3:0] io_ptw_ptbr_mode_0; // @[RocketCore.scala:153:7] wire [43:0] io_ptw_ptbr_ppn_0; // @[RocketCore.scala:153:7] wire io_ptw_status_debug_0; // @[RocketCore.scala:153:7] wire io_ptw_status_cease_0; // @[RocketCore.scala:153:7] wire io_ptw_status_wfi_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_status_isa_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_dprv_0; // @[RocketCore.scala:153:7] wire io_ptw_status_dv_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_prv_0; // @[RocketCore.scala:153:7] wire io_ptw_status_v_0; // @[RocketCore.scala:153:7] wire io_ptw_status_sd_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mpv_0; // @[RocketCore.scala:153:7] wire io_ptw_status_gva_0; // @[RocketCore.scala:153:7] wire io_ptw_status_tsr_0; // @[RocketCore.scala:153:7] wire io_ptw_status_tw_0; // @[RocketCore.scala:153:7] wire io_ptw_status_tvm_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mxr_0; // @[RocketCore.scala:153:7] wire io_ptw_status_sum_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mprv_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_fs_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_status_mpp_0; // @[RocketCore.scala:153:7] wire io_ptw_status_spp_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mpie_0; // @[RocketCore.scala:153:7] wire io_ptw_status_spie_0; // @[RocketCore.scala:153:7] wire io_ptw_status_mie_0; // @[RocketCore.scala:153:7] wire io_ptw_status_sie_0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_spvp_0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_spv_0; // @[RocketCore.scala:153:7] wire io_ptw_hstatus_gva_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_debug_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_cease_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_wfi_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_gstatus_isa_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_dprv_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_dv_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_prv_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_v_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sd_0; // @[RocketCore.scala:153:7] wire [22:0] io_ptw_gstatus_zero2_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mpv_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_gva_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mbe_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sbe_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_sxl_0; // @[RocketCore.scala:153:7] wire [7:0] io_ptw_gstatus_zero1_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_tsr_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_tw_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_tvm_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mxr_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sum_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mprv_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_fs_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_mpp_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_gstatus_vs_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_spp_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mpie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_ube_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_spie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_upie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_mie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_hie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_sie_0; // @[RocketCore.scala:153:7] wire io_ptw_gstatus_uie_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_0_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_0_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_0_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_0_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_0_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_0_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_0_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_1_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_1_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_1_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_1_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_1_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_1_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_1_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_2_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_2_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_2_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_2_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_2_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_2_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_2_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_3_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_3_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_3_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_3_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_3_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_3_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_3_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_4_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_4_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_4_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_4_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_4_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_4_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_4_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_5_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_5_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_5_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_5_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_5_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_5_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_5_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_6_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_6_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_6_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_6_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_6_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_6_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_6_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_7_cfg_l_0; // @[RocketCore.scala:153:7] wire [1:0] io_ptw_pmp_7_cfg_a_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_7_cfg_x_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_7_cfg_w_0; // @[RocketCore.scala:153:7] wire io_ptw_pmp_7_cfg_r_0; // @[RocketCore.scala:153:7] wire [29:0] io_ptw_pmp_7_addr_0; // @[RocketCore.scala:153:7] wire [31:0] io_ptw_pmp_7_mask_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_0_ren_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_0_wen_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_1_ren_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_1_wen_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_2_ren_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_2_wen_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_3_ren_0; // @[RocketCore.scala:153:7] wire io_ptw_customCSRs_csrs_3_wen_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0; // @[RocketCore.scala:153:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0; // @[RocketCore.scala:153:7] wire [63:0] io_fpu_time_0; // @[RocketCore.scala:153:7] wire [31:0] io_fpu_inst_0; // @[RocketCore.scala:153:7] wire [63:0] io_fpu_fromint_data_0; // @[RocketCore.scala:153:7] wire [2:0] io_fpu_fcsr_rm_0; // @[RocketCore.scala:153:7] wire io_fpu_ll_resp_val_0; // @[RocketCore.scala:153:7] wire [2:0] io_fpu_ll_resp_type_0; // @[RocketCore.scala:153:7] wire [4:0] io_fpu_ll_resp_tag_0; // @[RocketCore.scala:153:7] wire io_fpu_valid_0; // @[RocketCore.scala:153:7] wire io_fpu_killx_0; // @[RocketCore.scala:153:7] wire io_fpu_killm_0; // @[RocketCore.scala:153:7] wire io_fpu_keep_clock_enabled_0; // @[RocketCore.scala:153:7] wire [6:0] io_rocc_cmd_bits_inst_funct; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_cmd_bits_inst_rs2; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_cmd_bits_inst_rs1; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_inst_xd; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_inst_xs1; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_inst_xs2; // @[RocketCore.scala:153:7] wire [4:0] io_rocc_cmd_bits_inst_rd; // @[RocketCore.scala:153:7] wire [6:0] io_rocc_cmd_bits_inst_opcode; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_debug; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_cease; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_wfi; // @[RocketCore.scala:153:7] wire [31:0] io_rocc_cmd_bits_status_isa; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_dprv; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_dv; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_prv; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_v; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sd; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mpv; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_gva; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_tsr; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_tw; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_tvm; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mxr; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sum; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mprv; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_fs; // @[RocketCore.scala:153:7] wire [1:0] io_rocc_cmd_bits_status_mpp; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_spp; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mpie; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_spie; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_mie; // @[RocketCore.scala:153:7] wire io_rocc_cmd_bits_status_sie; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_cmd_bits_rs1; // @[RocketCore.scala:153:7] wire [63:0] io_rocc_cmd_bits_rs2; // @[RocketCore.scala:153:7] wire io_rocc_cmd_valid; // @[RocketCore.scala:153:7] wire io_trace_insns_0_valid_0; // @[RocketCore.scala:153:7] wire [39:0] io_trace_insns_0_iaddr_0; // @[RocketCore.scala:153:7] wire [31:0] io_trace_insns_0_insn_0; // @[RocketCore.scala:153:7] wire [2:0] io_trace_insns_0_priv_0; // @[RocketCore.scala:153:7] wire io_trace_insns_0_exception_0; // @[RocketCore.scala:153:7] wire io_trace_insns_0_interrupt_0; // @[RocketCore.scala:153:7] wire [63:0] io_trace_insns_0_cause_0; // @[RocketCore.scala:153:7] wire [39:0] io_trace_insns_0_tval_0; // @[RocketCore.scala:153:7] wire [63:0] io_trace_time_0; // @[RocketCore.scala:153:7] wire io_bpwatch_0_valid_0_0; // @[RocketCore.scala:153:7] wire [2:0] io_bpwatch_0_action_0; // @[RocketCore.scala:153:7] wire io_wfi_0; // @[RocketCore.scala:153:7] reg id_reg_pause; // @[RocketCore.scala:161:25] reg imem_might_request_reg; // @[RocketCore.scala:162:35] assign io_imem_might_request_0 = imem_might_request_reg; // @[RocketCore.scala:153:7, :162:35] reg ex_ctrl_legal; // @[RocketCore.scala:243:20] reg ex_ctrl_fp; // @[RocketCore.scala:243:20] reg ex_ctrl_rocc; // @[RocketCore.scala:243:20] reg ex_ctrl_branch; // @[RocketCore.scala:243:20] reg ex_ctrl_jal; // @[RocketCore.scala:243:20] reg ex_ctrl_jalr; // @[RocketCore.scala:243:20] reg ex_ctrl_rxs2; // @[RocketCore.scala:243:20] reg ex_ctrl_rxs1; // @[RocketCore.scala:243:20] reg [2:0] ex_ctrl_sel_alu2; // @[RocketCore.scala:243:20] reg [1:0] ex_ctrl_sel_alu1; // @[RocketCore.scala:243:20] reg [2:0] ex_ctrl_sel_imm; // @[RocketCore.scala:243:20] reg ex_ctrl_alu_dw; // @[RocketCore.scala:243:20] reg [4:0] ex_ctrl_alu_fn; // @[RocketCore.scala:243:20] reg ex_ctrl_mem; // @[RocketCore.scala:243:20] wire _ex_sfence_T = ex_ctrl_mem; // @[RocketCore.scala:243:20, :605:29] reg [4:0] ex_ctrl_mem_cmd; // @[RocketCore.scala:243:20] assign io_dmem_req_bits_cmd_0 = ex_ctrl_mem_cmd; // @[RocketCore.scala:153:7, :243:20] reg ex_ctrl_rfs1; // @[RocketCore.scala:243:20] reg ex_ctrl_rfs2; // @[RocketCore.scala:243:20] reg ex_ctrl_rfs3; // @[RocketCore.scala:243:20] reg ex_ctrl_wfd; // @[RocketCore.scala:243:20] reg ex_ctrl_mul; // @[RocketCore.scala:243:20] reg ex_ctrl_div; // @[RocketCore.scala:243:20] reg ex_ctrl_wxd; // @[RocketCore.scala:243:20] reg [2:0] ex_ctrl_csr; // @[RocketCore.scala:243:20] reg ex_ctrl_fence_i; // @[RocketCore.scala:243:20] reg ex_ctrl_fence; // @[RocketCore.scala:243:20] reg ex_ctrl_amo; // @[RocketCore.scala:243:20] reg ex_ctrl_dp; // @[RocketCore.scala:243:20] reg mem_ctrl_legal; // @[RocketCore.scala:244:21] reg mem_ctrl_fp; // @[RocketCore.scala:244:21] reg mem_ctrl_rocc; // @[RocketCore.scala:244:21] reg mem_ctrl_branch; // @[RocketCore.scala:244:21] assign io_imem_bht_update_bits_branch_0 = mem_ctrl_branch; // @[RocketCore.scala:153:7, :244:21] reg mem_ctrl_jal; // @[RocketCore.scala:244:21] reg mem_ctrl_jalr; // @[RocketCore.scala:244:21] reg mem_ctrl_rxs2; // @[RocketCore.scala:244:21] reg mem_ctrl_rxs1; // @[RocketCore.scala:244:21] reg [2:0] mem_ctrl_sel_alu2; // @[RocketCore.scala:244:21] reg [1:0] mem_ctrl_sel_alu1; // @[RocketCore.scala:244:21] reg [2:0] mem_ctrl_sel_imm; // @[RocketCore.scala:244:21] reg mem_ctrl_alu_dw; // @[RocketCore.scala:244:21] reg [4:0] mem_ctrl_alu_fn; // @[RocketCore.scala:244:21] reg mem_ctrl_mem; // @[RocketCore.scala:244:21] reg [4:0] mem_ctrl_mem_cmd; // @[RocketCore.scala:244:21] reg mem_ctrl_rfs1; // @[RocketCore.scala:244:21] reg mem_ctrl_rfs2; // @[RocketCore.scala:244:21] reg mem_ctrl_rfs3; // @[RocketCore.scala:244:21] reg mem_ctrl_wfd; // @[RocketCore.scala:244:21] reg mem_ctrl_mul; // @[RocketCore.scala:244:21] reg mem_ctrl_div; // @[RocketCore.scala:244:21] reg mem_ctrl_wxd; // @[RocketCore.scala:244:21] reg [2:0] mem_ctrl_csr; // @[RocketCore.scala:244:21] reg mem_ctrl_fence_i; // @[RocketCore.scala:244:21] reg mem_ctrl_fence; // @[RocketCore.scala:244:21] reg mem_ctrl_amo; // @[RocketCore.scala:244:21] reg mem_ctrl_dp; // @[RocketCore.scala:244:21] reg mem_ctrl_vec; // @[RocketCore.scala:244:21] reg wb_ctrl_legal; // @[RocketCore.scala:245:20] reg wb_ctrl_fp; // @[RocketCore.scala:245:20] reg wb_ctrl_rocc; // @[RocketCore.scala:245:20] reg wb_ctrl_branch; // @[RocketCore.scala:245:20] reg wb_ctrl_jal; // @[RocketCore.scala:245:20] reg wb_ctrl_jalr; // @[RocketCore.scala:245:20] reg wb_ctrl_rxs2; // @[RocketCore.scala:245:20] reg wb_ctrl_rxs1; // @[RocketCore.scala:245:20] reg [2:0] wb_ctrl_sel_alu2; // @[RocketCore.scala:245:20] reg [1:0] wb_ctrl_sel_alu1; // @[RocketCore.scala:245:20] reg [2:0] wb_ctrl_sel_imm; // @[RocketCore.scala:245:20] reg wb_ctrl_alu_dw; // @[RocketCore.scala:245:20] reg [4:0] wb_ctrl_alu_fn; // @[RocketCore.scala:245:20] reg wb_ctrl_mem; // @[RocketCore.scala:245:20] reg [4:0] wb_ctrl_mem_cmd; // @[RocketCore.scala:245:20] reg wb_ctrl_rfs1; // @[RocketCore.scala:245:20] reg wb_ctrl_rfs2; // @[RocketCore.scala:245:20] reg wb_ctrl_rfs3; // @[RocketCore.scala:245:20] reg wb_ctrl_wfd; // @[RocketCore.scala:245:20] reg wb_ctrl_mul; // @[RocketCore.scala:245:20] reg wb_ctrl_div; // @[RocketCore.scala:245:20] reg wb_ctrl_wxd; // @[RocketCore.scala:245:20] reg [2:0] wb_ctrl_csr; // @[RocketCore.scala:245:20] reg wb_ctrl_fence_i; // @[RocketCore.scala:245:20] reg wb_ctrl_fence; // @[RocketCore.scala:245:20] reg wb_ctrl_amo; // @[RocketCore.scala:245:20] reg wb_ctrl_dp; // @[RocketCore.scala:245:20] reg wb_ctrl_vec; // @[RocketCore.scala:245:20] reg ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35] reg ex_reg_valid; // @[RocketCore.scala:248:35] reg ex_reg_rvc; // @[RocketCore.scala:249:35] reg [1:0] ex_reg_btb_resp_cfiType; // @[RocketCore.scala:250:35] reg ex_reg_btb_resp_taken; // @[RocketCore.scala:250:35] reg [1:0] ex_reg_btb_resp_mask; // @[RocketCore.scala:250:35] reg ex_reg_btb_resp_bridx; // @[RocketCore.scala:250:35] reg [38:0] ex_reg_btb_resp_target; // @[RocketCore.scala:250:35] reg [4:0] ex_reg_btb_resp_entry; // @[RocketCore.scala:250:35] reg [7:0] ex_reg_btb_resp_bht_history; // @[RocketCore.scala:250:35] reg ex_reg_btb_resp_bht_value; // @[RocketCore.scala:250:35] reg ex_reg_xcpt; // @[RocketCore.scala:251:35] reg ex_reg_flush_pipe; // @[RocketCore.scala:252:35] reg ex_reg_load_use; // @[RocketCore.scala:253:35] reg [63:0] ex_reg_cause; // @[RocketCore.scala:254:35] wire [63:0] ex_cause = ex_reg_cause; // @[RocketCore.scala:254:35, :1278:50] reg ex_reg_replay; // @[RocketCore.scala:255:26] reg [39:0] ex_reg_pc; // @[RocketCore.scala:256:22] wire [39:0] _ex_op1_T_1 = ex_reg_pc; // @[RocketCore.scala:256:22, :474:24] reg [1:0] ex_reg_mem_size; // @[RocketCore.scala:257:28] assign io_dmem_req_bits_size_0 = ex_reg_mem_size; // @[RocketCore.scala:153:7, :257:28] reg [31:0] ex_reg_inst; // @[RocketCore.scala:259:24] reg [31:0] ex_reg_raw_inst; // @[RocketCore.scala:260:28] reg ex_reg_wphit_0; // @[RocketCore.scala:261:36] reg mem_reg_xcpt_interrupt; // @[RocketCore.scala:264:36] reg mem_reg_valid; // @[RocketCore.scala:265:36] reg mem_reg_rvc; // @[RocketCore.scala:266:36] reg [1:0] mem_reg_btb_resp_cfiType; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_cfiType_0 = mem_reg_btb_resp_cfiType; // @[RocketCore.scala:153:7, :267:36] reg mem_reg_btb_resp_taken; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_taken_0 = mem_reg_btb_resp_taken; // @[RocketCore.scala:153:7, :267:36] wire _mem_direction_misprediction_T = mem_reg_btb_resp_taken; // @[RocketCore.scala:267:36, :627:85] reg [1:0] mem_reg_btb_resp_mask; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_mask_0 = mem_reg_btb_resp_mask; // @[RocketCore.scala:153:7, :267:36] reg mem_reg_btb_resp_bridx; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_bridx_0 = mem_reg_btb_resp_bridx; // @[RocketCore.scala:153:7, :267:36] reg [38:0] mem_reg_btb_resp_target; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_target_0 = mem_reg_btb_resp_target; // @[RocketCore.scala:153:7, :267:36] reg [4:0] mem_reg_btb_resp_entry; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_entry_0 = mem_reg_btb_resp_entry; // @[RocketCore.scala:153:7, :267:36] reg [7:0] mem_reg_btb_resp_bht_history; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_bht_history_0 = mem_reg_btb_resp_bht_history; // @[RocketCore.scala:153:7, :267:36] assign io_imem_bht_update_bits_prediction_history_0 = mem_reg_btb_resp_bht_history; // @[RocketCore.scala:153:7, :267:36] reg mem_reg_btb_resp_bht_value; // @[RocketCore.scala:267:36] assign io_imem_btb_update_bits_prediction_bht_value_0 = mem_reg_btb_resp_bht_value; // @[RocketCore.scala:153:7, :267:36] assign io_imem_bht_update_bits_prediction_value_0 = mem_reg_btb_resp_bht_value; // @[RocketCore.scala:153:7, :267:36] reg mem_reg_xcpt; // @[RocketCore.scala:268:36] reg mem_reg_replay; // @[RocketCore.scala:269:36] reg mem_reg_flush_pipe; // @[RocketCore.scala:270:36] reg [63:0] mem_reg_cause; // @[RocketCore.scala:271:36] reg mem_reg_slow_bypass; // @[RocketCore.scala:272:36] wire mem_mem_cmd_bh = mem_reg_slow_bypass; // @[RocketCore.scala:272:36, :995:41] reg mem_reg_load; // @[RocketCore.scala:273:36] reg mem_reg_store; // @[RocketCore.scala:274:36] reg mem_reg_set_vconfig; // @[RocketCore.scala:275:36] reg mem_reg_sfence; // @[RocketCore.scala:276:27] reg [39:0] mem_reg_pc; // @[RocketCore.scala:277:23] wire [39:0] _mem_br_target_T = mem_reg_pc; // @[RocketCore.scala:277:23, :615:34] reg [31:0] mem_reg_inst; // @[RocketCore.scala:278:25] reg [1:0] mem_reg_mem_size; // @[RocketCore.scala:279:29] reg mem_reg_hls_or_dv; // @[RocketCore.scala:280:30] reg [31:0] mem_reg_raw_inst; // @[RocketCore.scala:281:29] reg [63:0] mem_reg_wdata; // @[RocketCore.scala:282:26] wire [63:0] _mem_int_wdata_T_3 = mem_reg_wdata; // @[RocketCore.scala:282:26, :624:111] reg [63:0] mem_reg_rs2; // @[RocketCore.scala:283:24] reg mem_br_taken; // @[RocketCore.scala:284:25] assign io_imem_bht_update_bits_taken_0 = mem_br_taken; // @[RocketCore.scala:153:7, :284:25] wire _take_pc_mem_T_3; // @[RocketCore.scala:629:49] wire take_pc_mem; // @[RocketCore.scala:285:25] reg mem_reg_wphit_0; // @[RocketCore.scala:286:35] reg wb_reg_valid; // @[RocketCore.scala:288:35] reg wb_reg_xcpt; // @[RocketCore.scala:289:35] reg wb_reg_replay; // @[RocketCore.scala:290:35] reg wb_reg_flush_pipe; // @[RocketCore.scala:291:35] reg [63:0] wb_reg_cause; // @[RocketCore.scala:292:35] reg wb_reg_set_vconfig; // @[RocketCore.scala:293:35] reg wb_reg_sfence; // @[RocketCore.scala:294:26] reg [39:0] wb_reg_pc; // @[RocketCore.scala:295:22] reg [1:0] wb_reg_mem_size; // @[RocketCore.scala:296:28] reg wb_reg_hls_or_dv; // @[RocketCore.scala:297:29] reg wb_reg_hfence_v; // @[RocketCore.scala:298:28] assign io_imem_sfence_bits_hv_0 = wb_reg_hfence_v; // @[RocketCore.scala:153:7, :298:28] reg wb_reg_hfence_g; // @[RocketCore.scala:299:28] assign io_imem_sfence_bits_hg_0 = wb_reg_hfence_g; // @[RocketCore.scala:153:7, :299:28] reg [31:0] wb_reg_inst; // @[RocketCore.scala:300:24] wire [31:0] _io_rocc_cmd_bits_inst_WIRE_1 = wb_reg_inst; // @[RocketCore.scala:300:24, :1159:48] reg [31:0] wb_reg_raw_inst; // @[RocketCore.scala:301:28] reg [63:0] wb_reg_wdata; // @[RocketCore.scala:302:25] assign io_rocc_cmd_bits_rs1 = wb_reg_wdata; // @[RocketCore.scala:153:7, :302:25] wire [63:0] _rf_wdata_T_3 = wb_reg_wdata; // @[RocketCore.scala:302:25, :822:21] reg [63:0] wb_reg_rs2; // @[RocketCore.scala:303:23] assign io_rocc_cmd_bits_rs2 = wb_reg_rs2; // @[RocketCore.scala:153:7, :303:23] wire _take_pc_wb_T_2; // @[RocketCore.scala:762:53] wire take_pc_wb; // @[RocketCore.scala:304:24] reg wb_reg_wphit_0; // @[RocketCore.scala:305:35] assign io_bpwatch_0_valid_0_0 = wb_reg_wphit_0; // @[RocketCore.scala:153:7, :305:35] assign take_pc_mem_wb = take_pc_wb \| take_pc_mem; // @[RocketCore.scala:285:25, :304:24, :307:35] assign io_imem_req_valid_0 = take_pc_mem_wb; // @[RocketCore.scala:153:7, :307:35] wire id_ctrl_decoder_0; // @[Decode.scala:50:77] wire id_ctrl_decoder_1; // @[Decode.scala:50:77] wire id_ctrl_decoder_2; // @[Decode.scala:50:77] wire id_ctrl_decoder_3; // @[Decode.scala:50:77] wire _id_illegal_insn_T_32 = id_ctrl_rocc; // @[RocketCore.scala:321:21, :391:18] wire id_ctrl_decoder_4; // @[Decode.scala:50:77] wire id_ctrl_decoder_5; // @[Decode.scala:50:77] wire id_ctrl_decoder_6; // @[Decode.scala:50:77] wire id_ctrl_decoder_7; // @[Decode.scala:50:77] wire [2:0] id_ctrl_decoder_8; // @[Decode.scala:50:77] wire [1:0] id_ctrl_decoder_9; // @[Decode.scala:50:77] wire [2:0] id_ctrl_decoder_10; // @[Decode.scala:50:77] wire id_ctrl_decoder_11; // @[Decode.scala:50:77] wire [4:0] id_ctrl_decoder_12; // @[Decode.scala:50:77] wire id_ctrl_decoder_13; // @[Decode.scala:50:77] wire [4:0] id_ctrl_decoder_14; // @[Decode.scala:50:77] wire id_ctrl_decoder_15; // @[Decode.scala:50:77] wire id_ctrl_decoder_16; // @[Decode.scala:50:77] wire id_ctrl_decoder_17; // @[Decode.scala:50:77] wire id_ctrl_decoder_18; // @[Decode.scala:50:77] wire id_ctrl_decoder_19; // @[Decode.scala:50:77] wire id_ctrl_decoder_20; // @[Decode.scala:50:77] wire id_ctrl_decoder_21; // @[Decode.scala:50:77] wire [2:0] id_ctrl_decoder_22; // @[Decode.scala:50:77] wire id_ctrl_decoder_23; // @[Decode.scala:50:77] wire id_ctrl_decoder_24; // @[Decode.scala:50:77] wire id_ctrl_decoder_25; // @[Decode.scala:50:77] wire _id_do_fence_T = id_ctrl_fence; // @[RocketCore.scala:321:21, :410:64] wire id_ctrl_decoder_26; // @[Decode.scala:50:77] wire id_ctrl_legal; // @[RocketCore.scala:321:21] wire id_ctrl_fp; // @[RocketCore.scala:321:21] wire id_ctrl_branch; // @[RocketCore.scala:321:21] wire id_ctrl_jal; // @[RocketCore.scala:321:21] wire id_ctrl_jalr; // @[RocketCore.scala:321:21] wire id_ctrl_rxs2; // @[RocketCore.scala:321:21] wire id_ctrl_rxs1; // @[RocketCore.scala:321:21] wire [2:0] id_ctrl_sel_alu2; // @[RocketCore.scala:321:21] wire [1:0] id_ctrl_sel_alu1; // @[RocketCore.scala:321:21] wire [2:0] id_ctrl_sel_imm; // @[RocketCore.scala:321:21] wire id_ctrl_alu_dw; // @[RocketCore.scala:321:21] wire [4:0] id_ctrl_alu_fn; // @[RocketCore.scala:321:21] wire id_ctrl_mem; // @[RocketCore.scala:321:21] wire [4:0] id_ctrl_mem_cmd; // @[RocketCore.scala:321:21] wire id_ctrl_rfs1; // @[RocketCore.scala:321:21] wire id_ctrl_rfs2; // @[RocketCore.scala:321:21] wire id_ctrl_rfs3; // @[RocketCore.scala:321:21] wire id_ctrl_wfd; // @[RocketCore.scala:321:21] wire id_ctrl_mul; // @[RocketCore.scala:321:21] wire id_ctrl_div; // @[RocketCore.scala:321:21] wire id_ctrl_wxd; // @[RocketCore.scala:321:21] wire [2:0] id_ctrl_csr; // @[RocketCore.scala:321:21] wire id_ctrl_fence_i; // @[RocketCore.scala:321:21] wire id_ctrl_amo; // @[RocketCore.scala:321:21] wire id_ctrl_dp; // @[RocketCore.scala:321:21] wire [31:0] id_ctrl_decoder_decoded_plaInput; // @[pla.scala:77:22] wire [31:0] id_ctrl_decoder_decoded_invInputs = ~id_ctrl_decoder_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [41:0] id_ctrl_decoder_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [41:0] id_ctrl_decoder_decoded; // @[pla.scala:81:23] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_175 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_176 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_177 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_178 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_179 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_180 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_181 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_182 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_183 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_184 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_185 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_186 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_187 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_188 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_189 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_190 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_191 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_192 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_193 = id_ctrl_decoder_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_175 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_176 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_177 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_178 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_179 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_180 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_181 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_182 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_183 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_184 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_185 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_186 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_187 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_188 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_189 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_190 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_191 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_192 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_193 = id_ctrl_decoder_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_175 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_176 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_177 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_178 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_179 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_180 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_181 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_182 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_183 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_184 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_185 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_186 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_187 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_188 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_189 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_190 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_191 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_192 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_193 = id_ctrl_decoder_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_175 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_176 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_177 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_178 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_179 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_180 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_181 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_182 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_183 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_184 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_185 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_186 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_187 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_188 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_189 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_190 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_191 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_192 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_193 = id_ctrl_decoder_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_174 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_175 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_176 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_177 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_178 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_179 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_180 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_181 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_182 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_183 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_184 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_185 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_186 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_187 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_188 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_189 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_190 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_191 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_192 = id_ctrl_decoder_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168 = id_ctrl_decoder_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_164 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_175 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_176 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_179 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_181 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_182 = id_ctrl_decoder_decoded_invInputs[12]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T = {id_ctrl_decoder_decoded_andMatrixOutputs_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_99_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172 = id_ctrl_decoder_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_102_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_163 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_165 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_156 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_157 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_177 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_178 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_160 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_180 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_162 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_163 = id_ctrl_decoder_decoded_invInputs[13]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_9_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_146 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_136 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_137 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_158 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_159 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_140 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_161 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_142 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_143 = id_ctrl_decoder_decoded_invInputs[14]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_29_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_139_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172 = id_ctrl_decoder_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172 = id_ctrl_decoder_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_117_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_4 = id_ctrl_decoder_decoded_andMatrixOutputs_117_2; // @[pla.scala:98:70, :114:36] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_175 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_176 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_177 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_178 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_179 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_180 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_181 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_182 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_183 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_184 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_185 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_186 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_187 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_188 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_189 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_190 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_191 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_192 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_193 = id_ctrl_decoder_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_6}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_96_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:90:45, :98:53] wire [5:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_35_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_182_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171 = id_ctrl_decoder_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_9}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_128_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_67_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_131 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_113 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_76 = id_ctrl_decoder_decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_132 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_71 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_114 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_43 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_75 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_77 = id_ctrl_decoder_decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_123 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_128 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_129 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_72 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_73 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_44 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_45 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_46 = id_ctrl_decoder_decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_122 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31 = id_ctrl_decoder_decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_119 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_120 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_121 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_122 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_123 = id_ctrl_decoder_decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_31 = id_ctrl_decoder_decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_78_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_1}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_190_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114 = id_ctrl_decoder_decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_12}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_13}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [12:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_7_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_2}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_98_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_3}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_4}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_32_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_4}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_71_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_172 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_173 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_174 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_175 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_176 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_177 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_178 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_179 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_180 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_181 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_182 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_183 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_184 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_185 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_186 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_187 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_188 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_189 = id_ctrl_decoder_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_17}; // @[pla.scala:91:29, :98:53] wire [4:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_181_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_16 = id_ctrl_decoder_decoded_andMatrixOutputs_181_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:91:29, :98:53] wire [5:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_145_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_19}; // @[pla.scala:91:29, :98:53] wire [5:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_143_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_8}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_20}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_20_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_9}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_20}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_22_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_22}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_97_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_19}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_39_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_24}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_131_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_21}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_18}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53] wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_191_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_63 = id_ctrl_decoder_decoded_andMatrixOutputs_191_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_22}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_26}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_164_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_64 = id_ctrl_decoder_decoded_andMatrixOutputs_164_2; // @[pla.scala:98:70, :114:36] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160 = id_ctrl_decoder_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141 = id_ctrl_decoder_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121 = id_ctrl_decoder_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118 = id_ctrl_decoder_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115 = id_ctrl_decoder_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62 = id_ctrl_decoder_decoded_invInputs[15]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38 = id_ctrl_decoder_decoded_invInputs[16]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25 = id_ctrl_decoder_decoded_invInputs[17]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18 = id_ctrl_decoder_decoded_invInputs[18]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16 = id_ctrl_decoder_decoded_invInputs[19]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_147 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_148 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_130 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_131 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_135 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_136 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_134 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_138 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_136 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_137 = id_ctrl_decoder_decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_168 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_169 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_170 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_171 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_172 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_173 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_174 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_126 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_127 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_132 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_133 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_130 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_135 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_132 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_133 = id_ctrl_decoder_decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_149 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_150 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_151 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_152 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_153 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_154 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_155 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_124 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_125 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_128 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_129 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_128 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_131 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_130 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_131 = id_ctrl_decoder_decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_133 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_134 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_135 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_111 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_112 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_126 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_127 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_115 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_129 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_117 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_118 = id_ctrl_decoder_decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_6}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_13}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_23}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_27}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53] wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_55_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_1}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:98:53] wire [14:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_6}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_10}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_28}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53] wire [30:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_90_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158 = id_ctrl_decoder_decoded_plaInput[12]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_25}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_29}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_30_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_30}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_26_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_175_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_28}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_32}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_32}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_77_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_29}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_24}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53] wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_21_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_5 = id_ctrl_decoder_decoded_andMatrixOutputs_21_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_8}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_17}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_30}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_34}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_121_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_8}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_9}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_13}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_35}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_61_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_9}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_14}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_105_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_10}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_11}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_15}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_24_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_38}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_165_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_39}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_160_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_39}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_40}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_95_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_37}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_41}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_56_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_38}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_16_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_34}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_42}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_43}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_185_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_6 = id_ctrl_decoder_decoded_andMatrixOutputs_185_2; // @[pla.scala:98:70, :114:36] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161 = id_ctrl_decoder_decoded_plaInput[13]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_40}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_140_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_44}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_45}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_53_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_45}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_193_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_43}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_47}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_47}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_92_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_48}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_17_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_45}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_49}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_129_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_50}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_177_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_51}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_51}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_123_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_27}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_51}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53] wire [10:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_14_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_27 = id_ctrl_decoder_decoded_andMatrixOutputs_14_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_11}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_17}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_53}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_132_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_12}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_18}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_54}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_49_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_55}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_155_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_7 = id_ctrl_decoder_decoded_andMatrixOutputs_155_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_52}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_56}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_184_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_148_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_32}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_54}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_58}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_115_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_13}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_12}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_13}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_58}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_59}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_14}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_162_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119 = id_ctrl_decoder_decoded_plaInput[14]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_56}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_60}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_44_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_15}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_18}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_14}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_60}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_61}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_15}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_126_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_16}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_15}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_19}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_15}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_61}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_58}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_62}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_16}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_150_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_53}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_63}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_161_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_16}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_13}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_17}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_16}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_64}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_17}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_133_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_17}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_17}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_179_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_18}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_19}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_18}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_19}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_5_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_19}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_16}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_19}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_20}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_88_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_20}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_17}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_21}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_20}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_68}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_21}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_94_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_68}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_69}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_66_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_66}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_125_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_43}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_67}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_71}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_91_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_44}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_68}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_72}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_112_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_21}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_18}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_21}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_73}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_22}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_170_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_64}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_73}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_74}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53] wire [7:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_146_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_46}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_71}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_75}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_75}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_168_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_47}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_72}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_76}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53] wire [8:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_2_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_28}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_73}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_67}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_77}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_77}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53] wire [9:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_lo_77}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_15_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_77; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_130 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_74 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_116 = id_ctrl_decoder_decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_23}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_22}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_26}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_22}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_77}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_74}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_78}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_78}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_23}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_78}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_176_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_78; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_23}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_19}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_24}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_23}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_69}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_79}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_24}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_79}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_172_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_79; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_79}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_76}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_80}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_76}; // @[pla.scala:98:53] wire [6:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_80}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_76_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_80; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_28}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_25}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_70}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_51}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_81}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_81}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_77}; // @[pla.scala:98:53] wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_81}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_87_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_81; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_24}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_20}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_24}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_81}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_82}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_82}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_25}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_78}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_82}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_144_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_82; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_25}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_21}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_27}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_25}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_82}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_83}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_83}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_26}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_79}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_83}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_36_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_83; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_27}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_26}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_31}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_54}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_26}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_83}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_84}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_84}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_27}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_80}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_84}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_41_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_84; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_28}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_27}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_32}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_27}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_81}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_85}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_28}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_81}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_85}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_8_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_85; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_28}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_22}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_30}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_28}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_75}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_86}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_29}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_82}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_86}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_104_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_86; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_29}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_23}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_29}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_76}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_87}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_30}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_83}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_87}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_73_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_87; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7 = id_ctrl_decoder_decoded_plaInput[27]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_24}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_35}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_30}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_58}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_88}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_88}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_88}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_31}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_84}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_88}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_189_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_88; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_31}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_39}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_31}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_89}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_32}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_85}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_89}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_28_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_89; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_33}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_40}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_86}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_90}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_90}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_33}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_86}; // @[pla.scala:98:53] wire [12:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_90}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_0_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_90; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_166 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_167 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_133 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_134 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_138 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_139 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_137 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_141 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_139 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_140 = id_ctrl_decoder_decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_2}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_8}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_34}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_32}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_32}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_80}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_61}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_91}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_90}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_91}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_91}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_34}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_87}; // @[pla.scala:98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_91}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_60_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_91; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_33}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_27}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_33}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_91}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_92}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_92}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_35}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_88}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_92}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_48_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_92; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_9}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_34}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_43}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_34}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_82}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_92}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_93}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_93}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_89}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_93}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_167_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_93; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_35}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_44}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_35}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_93}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_94}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_94}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_37}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_90}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_94}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_163_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_94; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_124 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_125 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33 = id_ctrl_decoder_decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_38}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_42}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_36}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_65}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_95}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_95}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_38}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_91}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_95}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_137_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_95; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_31}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_40}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_39}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_37}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_46}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_85}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_96}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_96}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_39}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_92}; // @[pla.scala:98:53] wire [18:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_96}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_74_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_96; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11 = id_ctrl_decoder_decoded_plaInput[21]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_2}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_13}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_38}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_40}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_38}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_67}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_96}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_93}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_97}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_97}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_40}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_93}; // @[pla.scala:98:53] wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_97}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_59_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_97; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_1, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_1}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_3}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_3}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_5}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_39}; // @[pla.scala:98:53] wire [14:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_39}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_42}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_48}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_97}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_98}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_98}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_41}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_94}; // @[pla.scala:98:53] wire [30:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_98}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_152_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_98; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130 = id_ctrl_decoder_decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5 = id_ctrl_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5 = id_ctrl_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66 = id_ctrl_decoder_decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_4}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_4}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_15}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_40}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_42}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_40}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_46}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_69}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_98}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_95}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_99}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_99}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_42}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_95}; // @[pla.scala:98:53] wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_99}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_47_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_99; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_2}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_5}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_5}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_5, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_7}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_41}; // @[pla.scala:98:53] wire [14:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_16}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_41}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_47, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_50}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_99}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_100}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_100}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_43}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_96}; // @[pla.scala:98:53] wire [30:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_100}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_103_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_100; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_10}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_42}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_71}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_97}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_101}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_101}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_44}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_97}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_101}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_83_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_101; // @[pla.scala:98:{53,70}] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_28 = id_ctrl_decoder_decoded_andMatrixOutputs_83_2; // @[pla.scala:98:70, :114:36] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_43}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_49}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_43}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_72}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_98}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_102}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_102}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_45}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_98}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_102}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_31_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_102; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_9}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_47, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_47}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_46}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_44}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_53}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_99}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_92}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_103}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_103}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_46}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_99}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_103}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_13_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_103; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_8}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_48, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_13}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_47}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_45}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_45}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_51}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_74}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_103}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_104}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_104}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_47}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_100}; // @[pla.scala:98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_104}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_111_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_104; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_48}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_46}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_52}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_46}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_101}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_105}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_105}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_48}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_101}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_105}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_65_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_105; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26 = id_ctrl_decoder_decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_47}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_53}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_76}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_47}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_102}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_106}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_106}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_49}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_102}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_106}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_124_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_106; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_48}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_77}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_48}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_103}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_107}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_107}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_50}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_103}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_107}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_50_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_107; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_49}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_55}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_78}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_49}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_104}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_108}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_108}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_51}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_104}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_108}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_6_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_108; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_50}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_56}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_79}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_50}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_105}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_109}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_109}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_52}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_105}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_109}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_134_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_109; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_54, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_51}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_80}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_51}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_106}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_110}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_110}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_53}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_106}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_110}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_153_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_110; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_52}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_58}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_81}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_52}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_107}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_111}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_111}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_54}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_107}; // @[pla.scala:98:53] wire [13:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_111}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_109_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_111; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_40}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_56}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_62}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_53}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_112}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_112}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_55}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_108}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_112}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_187_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_112; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_56, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_41}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_63}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_54}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_113}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_113}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_56}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_109}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_113}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_45_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_113; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_61}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_58}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_84}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_113}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_114}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_114}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_110}; // @[pla.scala:98:53] wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_114}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_79_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_114; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_57, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_42}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_59}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_65}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_55}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_115}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_57}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_111}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_115}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_159_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_115; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_43}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_60}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_66}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_56}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_116}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_58}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_112}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_116}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_34_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_116; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_59, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_44}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_61}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_87, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_57}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_117}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_117}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_59}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_113}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_117}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_86_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_117; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_45}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_65, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_62}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_58}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_118}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_118}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_60}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_114}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_118}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_10_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_118; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_46}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_66, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_63}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_59}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_119}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_119}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_61}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_115}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_119}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_93_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_119; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_62, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_47}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_70}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_60}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_120}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_120}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_62}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_116}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_120}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_180_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_120; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_21}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_65, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_71}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_61}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_121}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_121}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_63}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_117}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_121}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_43_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_121; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_66, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_66}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_72}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_62}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_121}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_122}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_122}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_64}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_118}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_122}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_135_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_122; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_14}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_67, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_70}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_63}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_123}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_123}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_65}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_119}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_123}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_3_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_123; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_8}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_9}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_68, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_24}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_15}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_66}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_64}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_64}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_71}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_94}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_123}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_124}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_124}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_66}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_120}; // @[pla.scala:98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_124}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_188_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_124; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_118 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_108 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_109 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_110 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24 = id_ctrl_decoder_decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_65}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_69, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_69}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_75}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_65}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_114}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_124}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_125}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_125}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_67}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_121}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_125}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_4_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_125; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_68, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_66}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_70, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_70}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_76}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_66}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_115}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_126}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_68}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_122}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_126}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_25_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_126; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_74}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_71}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_97}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_126}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_127}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_127}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_123}; // @[pla.scala:98:53] wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_127}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_58_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_127; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_54}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_72}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_78}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_67}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_127}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_128}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_128}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_69}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_124}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_128}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_147_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_128; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_68}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_73, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_73}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_68}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_118}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_128}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_129}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_129}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_70}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_125}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_129}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_27_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_129; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_56}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_74}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_69}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_119}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_130}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_130}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_71}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_126}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_130}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_52_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_130; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_57}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_75}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_70}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_120}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_131}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_131}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_72}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_127}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_131}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_138_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_131; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_58, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_71}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_76, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_76}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_71}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_121}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_132}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_132}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_73}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_128}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_132}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_178_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_132; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_74, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_59}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_77}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_72}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_122}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_133}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_74}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_129}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_133}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_173_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_133; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_60, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_75, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_73}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_78, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_78}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_73}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_123}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_134}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_75}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_130}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_134}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_120_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_134; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_61, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_74}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_79, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_79}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_74}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_124}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_135}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_76}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_131}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_135}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_19_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_135; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_62}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_75}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_125}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_136}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_77}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_132}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_136}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_64_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_136; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_63, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_76}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_81, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_81}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_76}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_126}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_136}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_137}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_137}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_78}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_133}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_137}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_142_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_137; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_64, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_77}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_82, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_82}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_77}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_127}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_137}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_138}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_138}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_79}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_134}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_138}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_11_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_138; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_65}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_83, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_78}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_128}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_139}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_139}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_80}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_135}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_139}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_46_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_139; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_79, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_66}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_84, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_81}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_87}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_79}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_129}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_139, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_140}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_140}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_81}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_136}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_140}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_141_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_140; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_67, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_35}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_85, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_82, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_80}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_88}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_85}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_80}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_130}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_141}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_141}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_82}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_137}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_141}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_114_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_141; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_68}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_86, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_83}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_89}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_81}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_131}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_142}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_142}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_83}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_138}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_142}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_70_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_142; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_69, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_37}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_87, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_84, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_82}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_90}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_87}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_82}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_132}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_143}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_143}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_84}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_139}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_143}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_72_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_143; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_83, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_70}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_88, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_91}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_83}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_133}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_114}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_144}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_144}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_144}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_85}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_140}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_lo_144}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_174_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_144; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_39}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_89, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_86, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_84}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_92}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_89}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_84}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_134}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_115}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_145}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_145}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_86}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_141}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_lo_145}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_81_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_145; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87 = id_ctrl_decoder_decoded_plaInput[26]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88 = id_ctrl_decoder_decoded_plaInput[26]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_85, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_72}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_90, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_93}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_85}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_135}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_116}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_146}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_146}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_87}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_142}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_lo_146}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_130_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_146; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_41}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_91, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_94}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_91}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_86}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_136}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_117}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_147}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_147}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_88}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_143}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_lo_147}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_157_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_147; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_89, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_74}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_98}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_87}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_137}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_148}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_148}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_89}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_144}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_lo_148}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_68_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_148; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_90, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_75}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_99}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_88}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_138}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_149}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_149}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_90}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_145}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_lo_149}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_42_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_149; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_76, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_89}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_94, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_100}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_89}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_139}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_150}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_150}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_91}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_146}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_lo_150}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_54_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_150; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_77, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_95, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_95}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_101}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_90}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_140}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_150}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_151}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_151}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_92}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_147}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_lo_151}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_63_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_151; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_78, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_91}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_96, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_102}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_91}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_141}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_78 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_151}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_152}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_152}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_93}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_148}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_lo_152}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_69_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_152; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_79}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_97, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_100}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_92}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_142}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_79 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_153}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_153}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_153}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_94}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_149}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_lo_153}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_183_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_153; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_80, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_98, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_104, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_101}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_98}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_93}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_143}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_80 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_124}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_150}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_154}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_154}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_154}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_95}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_150}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_lo_154}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_51_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_154; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_47 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_81, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_99, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_102}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_99}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_94}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_144}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_81 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_125}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_155}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_155}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_96}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_151}; // @[pla.scala:98:53] wire [17:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_lo_155}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_136_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_155; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_48 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_48, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_100, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_100}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_97}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_95}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_145}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_82 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_106}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_152}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_145}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_156}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_156}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_156}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_97}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_152}; // @[pla.scala:98:53] wire [18:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_lo_156}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_127_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_156; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_49 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_49, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_101, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_101, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_98}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_104}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_96}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_146}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_83 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_127}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_153}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_157}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_157}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_98}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_153}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_lo_157}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_151_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_157; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_50 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_50, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_102, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_99}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_105}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_97}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_147}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_84 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_128}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_154}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_158}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_158}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_99}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_154}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_lo_158}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_1_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_158; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_51 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_51, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_98, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_103, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_100}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_106}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_98}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_148}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_85 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_129}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_155}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_159}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_159}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_159}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_100}; // @[pla.scala:98:53] wire [8:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_155}; // @[pla.scala:98:53] wire [16:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_lo_159}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_100_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_159; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_52 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_52, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_32}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_19}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_104, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_99, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_86}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_104}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_101}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_99}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_149}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_86 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_110}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_156}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_149}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_160}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_160}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_160}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_101}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_156}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_lo_160}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_106_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_160; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_53 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_53, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_33}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_20}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_105, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_100, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_87}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_105}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_102}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_100}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_150}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_87 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_111}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_150}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_161}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_161}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_161}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_102}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_157}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_lo_161}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_186_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_161; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_54 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_21}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_14}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_106, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_88, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_54}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_103}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_101}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_101}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_151}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_88 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_109}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_132}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_162}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_161}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_162}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_34, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_162}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_103}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_158}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_lo_162}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_18_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_162; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_55 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_55, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_35}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_22}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_107, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_89}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_107}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_104}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_102}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_152}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_89 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_113}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_159}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_152}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_163}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_163}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_35, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_163}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_104}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_159}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_lo_163}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_108_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_163; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_105, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_103}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_90}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_111, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_108}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_114}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_103}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_153}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_90 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_160, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_153}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_163}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_164}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_164}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_105}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_160}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_lo_164}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_89_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_164; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_56 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_91, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_109, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_109}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_115}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_104}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_164, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_154}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_91 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_161, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_154}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_164}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_165}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_165}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_106}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_161}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_lo_165}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_62_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_165; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_57 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_92, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_110, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_110}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_116}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_105}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_165, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_155}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_92 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_162, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_165}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_166}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_166, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_166}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_107}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_162}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_lo_166}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_149_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_166; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_58 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_93, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_111, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_111}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_106}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_166, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_156}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_93 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_163, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_156}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_166}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_167}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_167}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_108}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_163}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_lo_167}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_171_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_167; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_59 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_94, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_112, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_112}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_138, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_107}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_167, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_157}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_94 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_164, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_167}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_168}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_168}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_109}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_164}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_lo_168}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_37_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_168; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108 = id_ctrl_decoder_decoded_plaInput[23]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95 = id_ctrl_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11 = id_ctrl_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7 = id_ctrl_decoder_decoded_plaInput[24]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_60 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_14}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_113, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_95, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_60}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_36}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_110}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_108}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_108}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_168, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_158}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_95 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_165, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_139}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_169}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_168}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_169}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_36, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_169}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_110}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_165}; // @[pla.scala:98:53] wire [21:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_lo_169}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_122_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_169; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_6}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_61 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_6}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_6}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_114, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_15}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_11}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_37, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_96, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_61}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_109}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_169, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_159}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_111}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_96 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_109}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_117}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_140}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_169}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_166}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_170}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_170}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_37, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_111}; // @[pla.scala:98:53] wire [13:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_166}; // @[pla.scala:98:53] wire [27:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_lo_170}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_82_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_170; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_30_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_28_3, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_29_3}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_62 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_26_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_27_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_24_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_25_7}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_115, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_22_7, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_23_7}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_12, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_21_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_16}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_38, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_25}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_110}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_170, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_160}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_97, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_62}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_112, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_110}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_97 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_115}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_121}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_167, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_160}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_170}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_12, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_171}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_171}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_38, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_112}; // @[pla.scala:98:53] wire [15:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_167}; // @[pla.scala:98:53] wire [31:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_lo_171}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_119_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_171; // @[pla.scala:98:{53,70}] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16 = id_ctrl_decoder_decoded_plaInput[31]; // @[pla.scala:77:22, :90:45] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_119}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_116}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_168, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_161}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_142}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_171, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_161}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_172}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_171}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_172}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_172}; // @[pla.scala:90:45, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_168}; // @[pla.scala:98:53] wire [11:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_lo_172}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_169_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_172; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_113, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_98}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_117}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_123}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_111}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_172, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_162}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_98 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_169, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_162}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_172}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_173}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_173}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_113}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_169}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_lo_173}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_57_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_173; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_114, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_99}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_118}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_144, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_124}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_112}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_173, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_163}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_99 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_170, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_163}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_173}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_174}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_144 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_174}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_144, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_114}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_170}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_lo_174}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_80_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_174; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_164 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_100}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_119}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_145, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_125}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_113}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_174, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_164}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_100 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_171, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_164}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_174}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_175}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_145 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_175}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_145, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_115}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_171}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_lo_175}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_166_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_175; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_165 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_101}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_120}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_146, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_126}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_114}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_175, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_165}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_101 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_172, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_165}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_175}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_176}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_146 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_176}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_146, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_116}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_172}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_lo_176}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_154_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_176; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_63 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_102, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_63}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_115}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_166 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_121, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_121}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_147, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_127}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_115}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_176, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_166}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_102 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_173, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_166}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_176}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_177}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_147 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_177}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_147, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_117}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_173}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_lo_177}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_192_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_177; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_64 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_103, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_64}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_116}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_167 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_122, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_122}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_148, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_128}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_116}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_177, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_167}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_103 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_174, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_167}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_177}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_178}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_148 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_178}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_148, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_118}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_174}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_lo_178}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_38_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_178; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_119, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_168 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_104}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_123}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_149, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_129}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_117}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_178, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_168}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_104 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_175, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_168}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_178}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_179}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_149 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_179}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_149, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_119}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_175}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_lo_179}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_158_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_179; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_120, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_169 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_105}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_124}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_150, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_130}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_118}; // @[pla.scala:98:53] wire [6:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_179, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_169}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_105 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_176, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_169}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_179}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_180}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_150 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_180}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_150, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_120}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_176}; // @[pla.scala:98:53] wire [14:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_lo_180}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_110_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_180; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_106, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_65}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_121, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_119}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_170 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_125, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_119 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_128, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_125}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_151, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_131}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_119}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_180, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_170}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_106 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_177, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_170}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_180}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_181}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_151 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_181}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_151, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_121}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_177}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_lo_181}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_23_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_181; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_66 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_107, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_66}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_122, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_120}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_171 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_126, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_120 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_129, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_126}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_152, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_132}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_120}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_181, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_171}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_107 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_178, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_171}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_181}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_182}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_152 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_182, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_182}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_152, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_122}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_178}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_lo_182}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_101_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_182; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_67 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_108, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_67}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_123, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_121}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_172 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_127, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_121 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_130, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_153, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_133}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_121}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_182, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_172}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_108 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_179, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_172}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_182}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_183}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_153 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_183, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_183}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_153, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_123}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_179}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_lo_183}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_118_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_183; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_68 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_109, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_68}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_173 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_128, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_122 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_131, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_128}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_154, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_134}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_122}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_183, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_173}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_109 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_180, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_173}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_183}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_184}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_154 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_184, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_184}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_154, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_124}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_180}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_lo_184}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_116_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_184; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_69 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_110, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_69}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_174 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_129, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_123 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_132, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_129}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_155, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_135}; // @[pla.scala:91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_123}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_184, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_174}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_110 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_181, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_174}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_184}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_185}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_155 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_185}; // @[pla.scala:90:45, :98:53] wire [3:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_155, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_125}; // @[pla.scala:98:53] wire [7:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_181}; // @[pla.scala:98:53] wire [15:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_lo_185}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_156_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_185; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_70 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_17}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_70, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_39}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_17, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_26}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_175 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_130, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_124 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_124, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_111}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_133, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_130}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_126}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_124}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_185, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_175}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_111 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_156, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_136}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_185, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_182}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_175}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_186}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_186}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_156 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_39, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_186}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_156, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_126}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_182}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_lo_186}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_113_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_186; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_71 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_18}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_71, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_40}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_18, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_27}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_176 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_131, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_125 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_125, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_112}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_131}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_27, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_127}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_125}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_186, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_176}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_112 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_157, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_137}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_183}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_176}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_183 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_187}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_187}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_157 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_40, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_187}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_157, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_127}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_183}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_lo_187}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_107_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_187; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_72 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_19}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_72, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_41}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_19, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_28}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_177 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_132, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_126 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_126, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_113}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_132}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_28, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_128}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_126}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_187, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_177}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_113 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_158, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_138}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_184}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_177}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_184 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_188}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_188}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_158 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_41, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_188}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_158, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_128}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_184}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_lo_188}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_84_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_188; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_73 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_20}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_73, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_42}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_20, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_29}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_178 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_133, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_127 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_127, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_114}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_133}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_29, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_129}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_127}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_188, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_178}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_114 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_159, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_139}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_185}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_178}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_185 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_189}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_189}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_159 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_42, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_189}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_159, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_129}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_185}; // @[pla.scala:98:53] wire [19:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_lo_189}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_33_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_189; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_74 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_13}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_30}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_134 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_21, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_23}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_179 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_134, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_128 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_115, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_134, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_130}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_30, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_128}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_128}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_189, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_179}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_115 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_140, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_137}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_186, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_179}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_160}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_186 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_190, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_190}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_13, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_189}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_43 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_190, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_190}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_160 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_43, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_190}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_160, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_130}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_186}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_lo_190}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_85_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_190; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_75 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_14}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_31}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_135 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_22, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_24}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_180 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_135, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_129 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_116, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_135, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_131}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_141 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_31, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_129}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_190 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_141, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_129}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_190, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_180}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_116 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_141, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_138}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_187, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_180}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_138 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_161}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_187 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_138, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_191, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_191}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_14, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_190}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_44 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_191, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_191}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_161 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_44, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_191}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_161, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_131}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_187}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_lo_191}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_40_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_191; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_76 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_15}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_136 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_23, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_25}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_181 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_136, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_130 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_117, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_76}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_136, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_132}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_142 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_32, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_130}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_191 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_142, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_130}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_191, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_181}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_117 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_142, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_139}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_188, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_181}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_139 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_25, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_162}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_188 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_139, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_192, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_192}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_132 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_191}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_192, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_192}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_162 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_45, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_192}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_162, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_132}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_188}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_lo_192}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_12_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_192; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_77 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_19_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_20_16}; // @[pla.scala:90:45, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_16_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_17_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_137 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_hi_24, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_18_26}; // @[pla.scala:90:45, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_182 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_hi_137, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_131 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_14_118, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_15_77}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_11_137, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_12_133}; // @[pla.scala:91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_143 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_hi_33, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_13_131}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_192 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_hi_143, id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_lo_131}; // @[pla.scala:98:53] wire [9:0] id_ctrl_decoder_decoded_andMatrixOutputs_lo_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_lo_hi_192, id_ctrl_decoder_decoded_andMatrixOutputs_lo_lo_182}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_118 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_9_143, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_10_140}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_6_189, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_7_182}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_140 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_hi_26, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_8_163}; // @[pla.scala:91:29, :98:53] wire [4:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_189 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_hi_140, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_3_193, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_4_193}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_133 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_5_192}; // @[pla.scala:91:29, :98:53] wire [1:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_46 = {id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_0_193, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_1_193}; // @[pla.scala:90:45, :98:53] wire [2:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_163 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_hi_46, id_ctrl_decoder_decoded_andMatrixOutputs_andMatrixInput_2_193}; // @[pla.scala:91:29, :98:53] wire [5:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_hi_163, id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_lo_133}; // @[pla.scala:98:53] wire [10:0] id_ctrl_decoder_decoded_andMatrixOutputs_hi_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_hi_193, id_ctrl_decoder_decoded_andMatrixOutputs_hi_lo_189}; // @[pla.scala:98:53] wire [20:0] _id_ctrl_decoder_decoded_andMatrixOutputs_T_193 = {id_ctrl_decoder_decoded_andMatrixOutputs_hi_193, id_ctrl_decoder_decoded_andMatrixOutputs_lo_193}; // @[pla.scala:98:53] wire id_ctrl_decoder_decoded_andMatrixOutputs_75_2 = &_id_ctrl_decoder_decoded_andMatrixOutputs_T_193; // @[pla.scala:98:{53,70}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_118_2, id_ctrl_decoder_decoded_andMatrixOutputs_85_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_40_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_114_2, id_ctrl_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_127_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_86_2, id_ctrl_decoder_decoded_andMatrixOutputs_10_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_93_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_148_2, id_ctrl_decoder_decoded_andMatrixOutputs_76_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_87_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:114:19] wire [11:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T = {id_ctrl_decoder_decoded_orMatrixOutputs_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_1 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T; // @[pla.scala:114:{19,36}] wire [1:0] _GEN = {id_ctrl_decoder_decoded_andMatrixOutputs_14_2, id_ctrl_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_1 = _GEN; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6 = _GEN; // @[pla.scala:114:19] wire [2:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_3 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_47_2, id_ctrl_decoder_decoded_andMatrixOutputs_83_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_82_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_155_2, id_ctrl_decoder_decoded_andMatrixOutputs_59_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_55_2, id_ctrl_decoder_decoded_andMatrixOutputs_185_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:114:19] wire [6:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_1}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_9 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_8; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_0 = {id_ctrl_decoder_decoded_andMatrixOutputs_84_2, id_ctrl_decoder_decoded_andMatrixOutputs_33_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo = _GEN_0; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2 = _GEN_0; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = _GEN_0; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_154_2, id_ctrl_decoder_decoded_andMatrixOutputs_23_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_57_2, id_ctrl_decoder_decoded_andMatrixOutputs_80_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_166_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_100_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_69_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_52_2, id_ctrl_decoder_decoded_andMatrixOutputs_173_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = _GEN_1; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2 = _GEN_1; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4 = _GEN_1; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_180_2, id_ctrl_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = _GEN_2; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8 = _GEN_2; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1 = _GEN_2; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_24; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_24 = _GEN_2; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2 = _GEN_2; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3 = _GEN_2; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_137_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:114:19] wire [22:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo = _GEN_3; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2 = _GEN_3; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4 = _GEN_3; // @[pla.scala:114:19] wire [1:0] _GEN_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_41_2, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = _GEN_4; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10 = _GEN_4; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3 = _GEN_4; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_14_2, id_ctrl_decoder_decoded_andMatrixOutputs_155_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = _GEN_5; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3 = _GEN_5; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_105_2, id_ctrl_decoder_decoded_andMatrixOutputs_185_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_191_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_121_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_7_2, id_ctrl_decoder_decoded_andMatrixOutputs_98_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = _GEN_6; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7 = _GEN_6; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = _GEN_6; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] _GEN_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_96_2, id_ctrl_decoder_decoded_andMatrixOutputs_35_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = _GEN_7; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4 = _GEN_7; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, id_ctrl_decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_99_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4 = _GEN_8; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = _GEN_8; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_139_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:114:19] wire [22:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_2}; // @[pla.scala:114:19] wire [45:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_2}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_11 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_176_2, id_ctrl_decoder_decoded_andMatrixOutputs_172_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_13 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_12; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_12_2, id_ctrl_decoder_decoded_andMatrixOutputs_75_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1 = _GEN_9; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2 = _GEN_9; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4 = _GEN_9; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_116_2, id_ctrl_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_51_2, id_ctrl_decoder_decoded_andMatrixOutputs_136_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1 = _GEN_10; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2 = _GEN_10; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = _GEN_10; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_72_2, id_ctrl_decoder_decoded_andMatrixOutputs_81_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_157_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_45_2, id_ctrl_decoder_decoded_andMatrixOutputs_114_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_153_2, id_ctrl_decoder_decoded_andMatrixOutputs_109_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1 = _GEN_11; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_12; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_12 = _GEN_11; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3 = _GEN_11; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_187_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_77_2, id_ctrl_decoder_decoded_andMatrixOutputs_92_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_12 = {id_ctrl_decoder_decoded_andMatrixOutputs_181_2, id_ctrl_decoder_decoded_andMatrixOutputs_20_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1 = _GEN_12; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3 = _GEN_12; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2 = _GEN_12; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11 = _GEN_12; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:114:19] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_3}; // @[pla.scala:114:19] wire [18:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_3}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_15 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_14; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_109_2, id_ctrl_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_136_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_6_2, id_ctrl_decoder_decoded_andMatrixOutputs_134_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3 = _GEN_13; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2 = _GEN_13; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = _GEN_13; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_123_2, id_ctrl_decoder_decoded_andMatrixOutputs_124_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_22_2, id_ctrl_decoder_decoded_andMatrixOutputs_160_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_2}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_4}; // @[pla.scala:114:19] wire [12:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_4}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_18 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_17; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_23_2, id_ctrl_decoder_decoded_andMatrixOutputs_101_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_14 = {id_ctrl_decoder_decoded_andMatrixOutputs_70_2, id_ctrl_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2 = _GEN_14; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = _GEN_14; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_130_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_2}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_109_2, id_ctrl_decoder_decoded_andMatrixOutputs_141_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_153_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_124_2, id_ctrl_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_3}; // @[pla.scala:114:19] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_5}; // @[pla.scala:114:19] wire [18:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_5}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_20 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_19; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_65_2, id_ctrl_decoder_decoded_andMatrixOutputs_79_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_128_2, id_ctrl_decoder_decoded_andMatrixOutputs_165_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_177_2}; // @[pla.scala:98:70, :114:19] wire [4:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_6}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_22 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_21; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_137_2, id_ctrl_decoder_decoded_andMatrixOutputs_65_2}; // @[pla.scala:98:70, :114:19] wire [2:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_58_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_24 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_23; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_83_2, id_ctrl_decoder_decoded_andMatrixOutputs_169_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_0_2, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_10; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_10 = _GEN_15; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7 = _GEN_15; // @[pla.scala:114:19] wire [3:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_25 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_7}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_26 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_25; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_74_2, id_ctrl_decoder_decoded_andMatrixOutputs_111_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_102_2, id_ctrl_decoder_decoded_andMatrixOutputs_9_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_6}; // @[pla.scala:114:19] wire [8:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_29 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_8}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_30 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_29; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_142_2, id_ctrl_decoder_decoded_andMatrixOutputs_46_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_149_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_167_2, id_ctrl_decoder_decoded_andMatrixOutputs_138_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_104_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_3}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_6}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_15_2, id_ctrl_decoder_decoded_andMatrixOutputs_144_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_94_2, id_ctrl_decoder_decoded_andMatrixOutputs_125_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_56_2, id_ctrl_decoder_decoded_andMatrixOutputs_179_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_121_2, id_ctrl_decoder_decoded_andMatrixOutputs_105_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6 = _GEN_16; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3 = _GEN_16; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = _GEN_16; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_4}; // @[pla.scala:114:19] wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_7}; // @[pla.scala:114:19] wire [14:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_31 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_9}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_32 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_31; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_64_2, id_ctrl_decoder_decoded_andMatrixOutputs_142_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_17 = {id_ctrl_decoder_decoded_andMatrixOutputs_138_2, id_ctrl_decoder_decoded_andMatrixOutputs_173_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6 = _GEN_17; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5 = _GEN_17; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_25_2, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_43_2, id_ctrl_decoder_decoded_andMatrixOutputs_3_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_4_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_4}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_73_2, id_ctrl_decoder_decoded_andMatrixOutputs_163_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_168_2, id_ctrl_decoder_decoded_andMatrixOutputs_36_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_112_2, id_ctrl_decoder_decoded_andMatrixOutputs_170_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_39_2, id_ctrl_decoder_decoded_andMatrixOutputs_115_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_162_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_5}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_8}; // @[pla.scala:114:19] wire [17:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_33 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_10}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_34 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_33; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_5_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_150_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_133_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_132_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_44_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_9}; // @[pla.scala:114:19] wire [10:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_35 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_11}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_36 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_35; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_54_2, id_ctrl_decoder_decoded_andMatrixOutputs_183_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_147_2, id_ctrl_decoder_decoded_andMatrixOutputs_178_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_19_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_9}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_48_2, id_ctrl_decoder_decoded_andMatrixOutputs_25_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_129_2, id_ctrl_decoder_decoded_andMatrixOutputs_49_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_10}; // @[pla.scala:114:19] wire [9:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_37 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_12}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_38 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_37; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_171_2, id_ctrl_decoder_decoded_andMatrixOutputs_37_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_108_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_5 = _GEN_18; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = _GEN_18; // @[pla.scala:114:19] wire [1:0] _GEN_19 = {id_ctrl_decoder_decoded_andMatrixOutputs_106_2, id_ctrl_decoder_decoded_andMatrixOutputs_186_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_9; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_9 = _GEN_19; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3 = _GEN_19; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_5}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_10}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_11_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_188_2, id_ctrl_decoder_decoded_andMatrixOutputs_27_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_48_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_6}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_11}; // @[pla.scala:114:19] wire [13:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_39 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_13}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_40 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_39; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_62_2, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_151_2, id_ctrl_decoder_decoded_andMatrixOutputs_18_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_20 = {id_ctrl_decoder_decoded_andMatrixOutputs_42_2, id_ctrl_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1 = _GEN_20; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2 = _GEN_20; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3 = _GEN_20; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_135_2, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_4}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_34_2, id_ctrl_decoder_decoded_andMatrixOutputs_180_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_83_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_189_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_6}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_11}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_161_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_155_2, id_ctrl_decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] _GEN_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_17_2, id_ctrl_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1 = _GEN_21; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1 = _GEN_21; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2 = _GEN_21; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_121_2, id_ctrl_decoder_decoded_andMatrixOutputs_95_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_164_2, id_ctrl_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_7_2, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_1}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_78_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_1}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_7}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_12}; // @[pla.scala:114:19] wire [35:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_41 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_14}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_42 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_41; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_66_2, id_ctrl_decoder_decoded_andMatrixOutputs_146_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_18 = {id_ctrl_decoder_decoded_andMatrixOutputs_97_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_43 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_15}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_44 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_43; // @[pla.scala:114:{19,36}] wire [1:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_45 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_46 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_45; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_100_2, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_42_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_1_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] _GEN_22 = {id_ctrl_decoder_decoded_andMatrixOutputs_188_2, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2 = _GEN_22; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3 = _GEN_22; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = _GEN_22; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_120_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_23 = {id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5 = _GEN_23; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3 = _GEN_23; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_180_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_7}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_12}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_91_2, id_ctrl_decoder_decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_24_2, id_ctrl_decoder_decoded_andMatrixOutputs_53_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_6}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2 = {id_ctrl_decoder_decoded_andMatrixOutputs_191_2, id_ctrl_decoder_decoded_andMatrixOutputs_26_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_61_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_8}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_13}; // @[pla.scala:114:19] wire [21:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_47 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_16}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_48 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_47; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_24 = {id_ctrl_decoder_decoded_andMatrixOutputs_122_2, id_ctrl_decoder_decoded_andMatrixOutputs_116_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1 = _GEN_24; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2 = _GEN_24; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_25 = {id_ctrl_decoder_decoded_andMatrixOutputs_1_2, id_ctrl_decoder_decoded_andMatrixOutputs_100_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1 = _GEN_25; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3 = _GEN_25; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4 = _GEN_25; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2 = _GEN_25; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_6}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_26 = {id_ctrl_decoder_decoded_andMatrixOutputs_31_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1 = _GEN_26; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2 = _GEN_26; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_8}; // @[pla.scala:114:19] wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_13}; // @[pla.scala:114:19] wire [1:0] _GEN_27 = {id_ctrl_decoder_decoded_andMatrixOutputs_8_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2 = _GEN_27; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4 = _GEN_27; // @[pla.scala:114:19] wire [1:0] _GEN_28 = {id_ctrl_decoder_decoded_andMatrixOutputs_126_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1 = _GEN_28; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2 = _GEN_28; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = _GEN_28; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_2, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_2}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_184_2}; // @[pla.scala:98:70, :114:19] wire [1:0] _GEN_29 = {id_ctrl_decoder_decoded_andMatrixOutputs_105_2, id_ctrl_decoder_decoded_andMatrixOutputs_16_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2 = _GEN_29; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4 = _GEN_29; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] _GEN_30 = {id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_121_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2 = _GEN_30; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4 = _GEN_30; // @[pla.scala:114:19] wire [1:0] _GEN_31 = {id_ctrl_decoder_decoded_andMatrixOutputs_98_2, id_ctrl_decoder_decoded_andMatrixOutputs_71_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1 = _GEN_31; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3 = _GEN_31; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2 = _GEN_31; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_2}; // @[pla.scala:114:19] wire [1:0] _GEN_32 = {id_ctrl_decoder_decoded_andMatrixOutputs_96_2, id_ctrl_decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1 = _GEN_32; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2 = _GEN_32; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_1, id_ctrl_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_2}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_9}; // @[pla.scala:114:19] wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_14}; // @[pla.scala:114:19] wire [43:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_49 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_lo_17}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_50 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_49; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_15 = {id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_159_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_15, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_16 = {id_ctrl_decoder_decoded_andMatrixOutputs_182_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_16, id_ctrl_decoder_decoded_andMatrixOutputs_189_2}; // @[pla.scala:98:70, :114:19] wire [5:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_51 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_lo_18}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_52 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_51; // @[pla.scala:114:{19,36}] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_120_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_7}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_180_2, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_52_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7 = {id_ctrl_decoder_decoded_andMatrixOutputs_2_2, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_60_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_9}; // @[pla.scala:114:19] wire [11:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_14}; // @[pla.scala:114:19] wire [1:0] _GEN_33 = {id_ctrl_decoder_decoded_andMatrixOutputs_140_2, id_ctrl_decoder_decoded_andMatrixOutputs_17_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3 = _GEN_33; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4 = _GEN_33; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = _GEN_33; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_91_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6 = {id_ctrl_decoder_decoded_andMatrixOutputs_30_2, id_ctrl_decoder_decoded_andMatrixOutputs_61_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_6, id_ctrl_decoder_decoded_andMatrixOutputs_24_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_191_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_29_2, id_ctrl_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_3}; // @[pla.scala:114:19] wire [6:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_10}; // @[pla.scala:114:19] wire [12:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_15}; // @[pla.scala:114:19] wire [24:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_53 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_lo_19}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_54 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_53; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_89_2, id_ctrl_decoder_decoded_andMatrixOutputs_122_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_142_2, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_3}; // @[pla.scala:114:19] wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_8}; // @[pla.scala:114:19] wire [1:0] _GEN_34 = {id_ctrl_decoder_decoded_andMatrixOutputs_159_2, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5 = _GEN_34; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7 = _GEN_34; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = _GEN_34; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_146_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_8_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_3}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_10}; // @[pla.scala:114:19] wire [16:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_15}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_126_2, id_ctrl_decoder_decoded_andMatrixOutputs_66_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_3}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_97_2, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_3}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_9}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5 = {id_ctrl_decoder_decoded_andMatrixOutputs_190_2, id_ctrl_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_3}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_4}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_11}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_16}; // @[pla.scala:114:19] wire [34:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_55 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_23, id_ctrl_decoder_decoded_orMatrixOutputs_lo_20}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_56 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_55; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_21 = {id_ctrl_decoder_decoded_andMatrixOutputs_68_2, id_ctrl_decoder_decoded_andMatrixOutputs_63_2}; // @[pla.scala:98:70, :114:19] wire [3:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_57 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_24, id_ctrl_decoder_decoded_orMatrixOutputs_lo_21}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_58 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_57; // @[pla.scala:114:{19,36}] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_156_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_3, id_ctrl_decoder_decoded_andMatrixOutputs_151_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_4}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_9}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_188_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_34_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_137_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_4}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_11}; // @[pla.scala:114:19] wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_16}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_41_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_184_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_140_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_4}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_10}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_131_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_4}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_2, id_ctrl_decoder_decoded_andMatrixOutputs_7_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_4, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_5}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_12}; // @[pla.scala:114:19] wire [21:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_25 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_17}; // @[pla.scala:114:19] wire [43:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_59 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_25, id_ctrl_decoder_decoded_orMatrixOutputs_lo_22}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_60 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_59; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_69_2, id_ctrl_decoder_decoded_andMatrixOutputs_89_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_135_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_14, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_10}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_13_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_28_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_12}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_17}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_161_2, id_ctrl_decoder_decoded_andMatrixOutputs_88_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9 = {id_ctrl_decoder_decoded_andMatrixOutputs_71_2, id_ctrl_decoder_decoded_andMatrixOutputs_14_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_9, id_ctrl_decoder_decoded_andMatrixOutputs_126_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_11}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_7, id_ctrl_decoder_decoded_andMatrixOutputs_32_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_128_2, id_ctrl_decoder_decoded_andMatrixOutputs_67_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_13}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_26 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_18}; // @[pla.scala:114:19] wire [21:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_61 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_26, id_ctrl_decoder_decoded_orMatrixOutputs_lo_23}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_62 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_61; // @[pla.scala:114:{19,36}] wire [1:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_65 = {id_ctrl_decoder_decoded_andMatrixOutputs_97_2, id_ctrl_decoder_decoded_andMatrixOutputs_161_2}; // @[pla.scala:98:70, :114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_66 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_65; // @[pla.scala:114:{19,36}] wire [1:0] _GEN_35 = {id_ctrl_decoder_decoded_andMatrixOutputs_158_2, id_ctrl_decoder_decoded_andMatrixOutputs_110_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_11; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_11 = _GEN_35; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo; // @[pla.scala:114:19] assign id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = _GEN_35; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_136_2, id_ctrl_decoder_decoded_andMatrixOutputs_192_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_38_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_15, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_11}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_13 = {id_ctrl_decoder_decoded_andMatrixOutputs_130_2, id_ctrl_decoder_decoded_andMatrixOutputs_51_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11 = {id_ctrl_decoder_decoded_andMatrixOutputs_141_2, id_ctrl_decoder_decoded_andMatrixOutputs_70_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_174_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_13}; // @[pla.scala:114:19] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_24 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_18}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_10 = {id_ctrl_decoder_decoded_andMatrixOutputs_50_2, id_ctrl_decoder_decoded_andMatrixOutputs_6_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_10, id_ctrl_decoder_decoded_andMatrixOutputs_134_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_12}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8 = {id_ctrl_decoder_decoded_andMatrixOutputs_175_2, id_ctrl_decoder_decoded_andMatrixOutputs_193_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_8, id_ctrl_decoder_decoded_andMatrixOutputs_124_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_11, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_14}; // @[pla.scala:114:19] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_27 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_19}; // @[pla.scala:114:19] wire [20:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_67 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_27, id_ctrl_decoder_decoded_orMatrixOutputs_lo_24}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_68 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_67; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_113_2, id_ctrl_decoder_decoded_andMatrixOutputs_107_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_122_2, id_ctrl_decoder_decoded_andMatrixOutputs_119_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_5}; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_130_2, id_ctrl_decoder_decoded_andMatrixOutputs_42_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_4 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_69_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_4, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_5}; // @[pla.scala:114:19] wire [16:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_16, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_12}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_173_2, id_ctrl_decoder_decoded_andMatrixOutputs_141_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_8, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_5}; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_111_2, id_ctrl_decoder_decoded_andMatrixOutputs_124_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_50_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_5}; // @[pla.scala:114:19] wire [16:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_14}; // @[pla.scala:114:19] wire [33:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_25 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_21, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_19}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_152_2, id_ctrl_decoder_decoded_andMatrixOutputs_103_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_60_2, id_ctrl_decoder_decoded_andMatrixOutputs_74_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_28_2, id_ctrl_decoder_decoded_andMatrixOutputs_0_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:114:19] wire [7:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_6, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_5}; // @[pla.scala:114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_95_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_11 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_11, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_5}; // @[pla.scala:114:19] wire [16:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_13}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_90_2, id_ctrl_decoder_decoded_andMatrixOutputs_30_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1 = {id_ctrl_decoder_decoded_andMatrixOutputs_131_2, id_ctrl_decoder_decoded_andMatrixOutputs_164_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_1, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_20_2, id_ctrl_decoder_decoded_andMatrixOutputs_22_2}; // @[pla.scala:98:70, :114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = {id_ctrl_decoder_decoded_andMatrixOutputs_71_2, id_ctrl_decoder_decoded_andMatrixOutputs_145_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_3 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_143_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_5}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_3 = {id_ctrl_decoder_decoded_andMatrixOutputs_35_2, id_ctrl_decoder_decoded_andMatrixOutputs_190_2}; // @[pla.scala:98:70, :114:19] wire [3:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_3, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:114:19] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = {id_ctrl_decoder_decoded_andMatrixOutputs_117_2, id_ctrl_decoder_decoded_andMatrixOutputs_96_2}; // @[pla.scala:98:70, :114:19] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, id_ctrl_decoder_decoded_andMatrixOutputs_29_2}; // @[pla.scala:98:70, :114:19] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_5, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:114:19] wire [8:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_6}; // @[pla.scala:114:19] wire [17:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_15}; // @[pla.scala:114:19] wire [34:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_28 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_20}; // @[pla.scala:114:19] wire [68:0] _id_ctrl_decoder_decoded_orMatrixOutputs_T_69 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_28, id_ctrl_decoder_decoded_orMatrixOutputs_lo_25}; // @[pla.scala:114:19] wire _id_ctrl_decoder_decoded_orMatrixOutputs_T_70 = \|_id_ctrl_decoder_decoded_orMatrixOutputs_T_69; // @[pla.scala:114:{19,36}] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_3, _id_ctrl_decoder_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_9, _id_ctrl_decoder_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_5 = {1'h0, _id_ctrl_decoder_decoded_orMatrixOutputs_T_13}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_5, _id_ctrl_decoder_decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_17 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_lo_6}; // @[pla.scala:102:36] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_hi_17, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_lo_13}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_16, _id_ctrl_decoder_decoded_orMatrixOutputs_T_15}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_22, _id_ctrl_decoder_decoded_orMatrixOutputs_T_20}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_9 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_18}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_15 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_hi_9, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_27, _id_ctrl_decoder_decoded_orMatrixOutputs_T_26}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_24}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_32, _id_ctrl_decoder_decoded_orMatrixOutputs_T_30}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_28}; // @[pla.scala:102:36, :114:36] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_19 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_lo_6}; // @[pla.scala:102:36] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_22 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_hi_19, id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_lo_15}; // @[pla.scala:102:36] wire [20:0] id_ctrl_decoder_decoded_orMatrixOutputs_lo_26 = {id_ctrl_decoder_decoded_orMatrixOutputs_lo_hi_22, id_ctrl_decoder_decoded_orMatrixOutputs_lo_lo_20}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_36, _id_ctrl_decoder_decoded_orMatrixOutputs_T_34}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_42, _id_ctrl_decoder_decoded_orMatrixOutputs_T_40}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_38}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_14 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_hi_7, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_46, _id_ctrl_decoder_decoded_orMatrixOutputs_T_44}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_52, _id_ctrl_decoder_decoded_orMatrixOutputs_T_50}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_12 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_6, _id_ctrl_decoder_decoded_orMatrixOutputs_T_48}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_18 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_hi_12, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_lo_6}; // @[pla.scala:102:36] wire [9:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_21 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_hi_18, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_lo_14}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_56, _id_ctrl_decoder_decoded_orMatrixOutputs_T_54}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_62, _id_ctrl_decoder_decoded_orMatrixOutputs_T_60}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_10 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_58}; // @[pla.scala:102:36, :114:36] wire [4:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_16 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_hi_10, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_lo_6}; // @[pla.scala:102:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_4 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_66, _id_ctrl_decoder_decoded_orMatrixOutputs_T_64}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_4, _id_ctrl_decoder_decoded_orMatrixOutputs_T_63}; // @[pla.scala:102:36, :114:36] wire [1:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_6 = {_id_ctrl_decoder_decoded_orMatrixOutputs_T_70, _id_ctrl_decoder_decoded_orMatrixOutputs_T_68}; // @[pla.scala:102:36, :114:36] wire [2:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_13 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_6, 1'h0}; // @[pla.scala:102:36] wire [5:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_20 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_hi_13, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_lo_7}; // @[pla.scala:102:36] wire [10:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_23 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_hi_20, id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_lo_16}; // @[pla.scala:102:36] wire [20:0] id_ctrl_decoder_decoded_orMatrixOutputs_hi_29 = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_hi_23, id_ctrl_decoder_decoded_orMatrixOutputs_hi_lo_21}; // @[pla.scala:102:36] wire [41:0] id_ctrl_decoder_decoded_orMatrixOutputs = {id_ctrl_decoder_decoded_orMatrixOutputs_hi_29, id_ctrl_decoder_decoded_orMatrixOutputs_lo_26}; // @[pla.scala:102:36] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T = id_ctrl_decoder_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_1 = id_ctrl_decoder_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_2 = id_ctrl_decoder_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_3 = id_ctrl_decoder_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_4 = id_ctrl_decoder_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_5 = id_ctrl_decoder_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_6 = id_ctrl_decoder_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_7 = id_ctrl_decoder_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_8 = id_ctrl_decoder_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_9 = id_ctrl_decoder_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_10 = id_ctrl_decoder_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_11 = id_ctrl_decoder_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_12 = id_ctrl_decoder_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_13 = id_ctrl_decoder_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_14 = id_ctrl_decoder_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_15 = id_ctrl_decoder_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_16 = id_ctrl_decoder_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_17 = id_ctrl_decoder_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_18 = id_ctrl_decoder_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_19 = id_ctrl_decoder_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_20 = id_ctrl_decoder_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_21 = id_ctrl_decoder_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_22 = id_ctrl_decoder_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_23 = id_ctrl_decoder_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_24 = id_ctrl_decoder_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_25 = id_ctrl_decoder_decoded_orMatrixOutputs[25]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_26 = id_ctrl_decoder_decoded_orMatrixOutputs[26]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_27 = id_ctrl_decoder_decoded_orMatrixOutputs[27]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_28 = id_ctrl_decoder_decoded_orMatrixOutputs[28]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_29 = id_ctrl_decoder_decoded_orMatrixOutputs[29]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_30 = id_ctrl_decoder_decoded_orMatrixOutputs[30]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_31 = id_ctrl_decoder_decoded_orMatrixOutputs[31]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_32 = id_ctrl_decoder_decoded_orMatrixOutputs[32]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_33 = id_ctrl_decoder_decoded_orMatrixOutputs[33]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_34 = id_ctrl_decoder_decoded_orMatrixOutputs[34]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_35 = id_ctrl_decoder_decoded_orMatrixOutputs[35]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_36 = id_ctrl_decoder_decoded_orMatrixOutputs[36]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_37 = id_ctrl_decoder_decoded_orMatrixOutputs[37]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_38 = id_ctrl_decoder_decoded_orMatrixOutputs[38]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_39 = id_ctrl_decoder_decoded_orMatrixOutputs[39]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_40 = id_ctrl_decoder_decoded_orMatrixOutputs[40]; // @[pla.scala:102:36, :124:31] wire _id_ctrl_decoder_decoded_invMatrixOutputs_T_41 = id_ctrl_decoder_decoded_orMatrixOutputs[41]; // @[pla.scala:102:36, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_1, _id_ctrl_decoder_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_4, _id_ctrl_decoder_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_6, _id_ctrl_decoder_decoded_invMatrixOutputs_T_5}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_9, _id_ctrl_decoder_decoded_invMatrixOutputs_T_8}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [9:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_11, _id_ctrl_decoder_decoded_invMatrixOutputs_T_10}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_14, _id_ctrl_decoder_decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_12}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_17, _id_ctrl_decoder_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_20, _id_ctrl_decoder_decoded_invMatrixOutputs_T_19}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_18}; // @[pla.scala:120:37, :124:31] wire [5:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [10:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [20:0] id_ctrl_decoder_decoded_invMatrixOutputs_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_22, _id_ctrl_decoder_decoded_invMatrixOutputs_T_21}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_25, _id_ctrl_decoder_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_23}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_27, _id_ctrl_decoder_decoded_invMatrixOutputs_T_26}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_30, _id_ctrl_decoder_decoded_invMatrixOutputs_T_29}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_28}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [9:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_32, _id_ctrl_decoder_decoded_invMatrixOutputs_T_31}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_35, _id_ctrl_decoder_decoded_invMatrixOutputs_T_34}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_33}; // @[pla.scala:120:37, :124:31] wire [4:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_38, _id_ctrl_decoder_decoded_invMatrixOutputs_T_37}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_36}; // @[pla.scala:120:37, :124:31] wire [1:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = {_id_ctrl_decoder_decoded_invMatrixOutputs_T_41, _id_ctrl_decoder_decoded_invMatrixOutputs_T_40}; // @[pla.scala:120:37, :124:31] wire [2:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, _id_ctrl_decoder_decoded_invMatrixOutputs_T_39}; // @[pla.scala:120:37, :124:31] wire [5:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [10:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [20:0] id_ctrl_decoder_decoded_invMatrixOutputs_hi = {id_ctrl_decoder_decoded_invMatrixOutputs_hi_hi, id_ctrl_decoder_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign id_ctrl_decoder_decoded_invMatrixOutputs = {id_ctrl_decoder_decoded_invMatrixOutputs_hi, id_ctrl_decoder_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign id_ctrl_decoder_decoded = id_ctrl_decoder_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign id_ctrl_decoder_0 = id_ctrl_decoder_decoded[41]; // @[pla.scala:81:23] assign id_ctrl_legal = id_ctrl_decoder_0; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_1 = id_ctrl_decoder_decoded[40]; // @[pla.scala:81:23] assign id_ctrl_fp = id_ctrl_decoder_1; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_2 = id_ctrl_decoder_decoded[39]; // @[pla.scala:81:23] assign id_ctrl_rocc = id_ctrl_decoder_2; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_3 = id_ctrl_decoder_decoded[38]; // @[pla.scala:81:23] assign id_ctrl_branch = id_ctrl_decoder_3; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_4 = id_ctrl_decoder_decoded[37]; // @[pla.scala:81:23] assign id_ctrl_jal = id_ctrl_decoder_4; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_5 = id_ctrl_decoder_decoded[36]; // @[pla.scala:81:23] assign id_ctrl_jalr = id_ctrl_decoder_5; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_6 = id_ctrl_decoder_decoded[35]; // @[pla.scala:81:23] assign id_ctrl_rxs2 = id_ctrl_decoder_6; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_7 = id_ctrl_decoder_decoded[34]; // @[pla.scala:81:23] assign id_ctrl_rxs1 = id_ctrl_decoder_7; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_8 = id_ctrl_decoder_decoded[33:31]; // @[pla.scala:81:23] assign id_ctrl_sel_alu2 = id_ctrl_decoder_8; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_9 = id_ctrl_decoder_decoded[30:29]; // @[pla.scala:81:23] assign id_ctrl_sel_alu1 = id_ctrl_decoder_9; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_10 = id_ctrl_decoder_decoded[28:26]; // @[pla.scala:81:23] assign id_ctrl_sel_imm = id_ctrl_decoder_10; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_11 = id_ctrl_decoder_decoded[25]; // @[pla.scala:81:23] assign id_ctrl_alu_dw = id_ctrl_decoder_11; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_12 = id_ctrl_decoder_decoded[24:20]; // @[pla.scala:81:23] assign id_ctrl_alu_fn = id_ctrl_decoder_12; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_13 = id_ctrl_decoder_decoded[19]; // @[pla.scala:81:23] assign id_ctrl_mem = id_ctrl_decoder_13; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_14 = id_ctrl_decoder_decoded[18:14]; // @[pla.scala:81:23] assign id_ctrl_mem_cmd = id_ctrl_decoder_14; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_15 = id_ctrl_decoder_decoded[13]; // @[pla.scala:81:23] assign id_ctrl_rfs1 = id_ctrl_decoder_15; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_16 = id_ctrl_decoder_decoded[12]; // @[pla.scala:81:23] assign id_ctrl_rfs2 = id_ctrl_decoder_16; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_17 = id_ctrl_decoder_decoded[11]; // @[pla.scala:81:23] assign id_ctrl_rfs3 = id_ctrl_decoder_17; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_18 = id_ctrl_decoder_decoded[10]; // @[pla.scala:81:23] assign id_ctrl_wfd = id_ctrl_decoder_18; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_19 = id_ctrl_decoder_decoded[9]; // @[pla.scala:81:23] assign id_ctrl_mul = id_ctrl_decoder_19; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_20 = id_ctrl_decoder_decoded[8]; // @[pla.scala:81:23] assign id_ctrl_div = id_ctrl_decoder_20; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_21 = id_ctrl_decoder_decoded[7]; // @[pla.scala:81:23] assign id_ctrl_wxd = id_ctrl_decoder_21; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_22 = id_ctrl_decoder_decoded[6:4]; // @[pla.scala:81:23] assign id_ctrl_csr = id_ctrl_decoder_22; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_23 = id_ctrl_decoder_decoded[3]; // @[pla.scala:81:23] assign id_ctrl_fence_i = id_ctrl_decoder_23; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_24 = id_ctrl_decoder_decoded[2]; // @[pla.scala:81:23] assign id_ctrl_fence = id_ctrl_decoder_24; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_25 = id_ctrl_decoder_decoded[1]; // @[pla.scala:81:23] assign id_ctrl_amo = id_ctrl_decoder_25; // @[RocketCore.scala:321:21] assign id_ctrl_decoder_26 = id_ctrl_decoder_decoded[0]; // @[pla.scala:81:23] assign id_ctrl_dp = id_ctrl_decoder_26; // @[RocketCore.scala:321:21] wire [4:0] id_raddr3; // @[RocketCore.scala:326:72] wire [4:0] id_raddr2; // @[RocketCore.scala:326:72] wire [4:0] _id_rs_T_7 = id_raddr2; // @[RocketCore.scala:326:72, :1320:44] wire [4:0] id_raddr1; // @[RocketCore.scala:326:72] wire [4:0] _id_rs_T_2 = id_raddr1; // @[RocketCore.scala:326:72, :1320:44] wire [4:0] id_waddr; // @[RocketCore.scala:326:72] wire _id_load_use_T_1; // @[RocketCore.scala:1001:51] wire id_load_use; // @[RocketCore.scala:332:25] reg id_reg_fence; // @[RocketCore.scala:333:29] wire [63:0] id_rs_0; // @[RocketCore.scala:1325:26] wire _id_rs_T = ~(\|id_raddr1); // @[RocketCore.scala:326:72, :1326:41] wire [4:0] _id_rs_T_3 = ~_id_rs_T_2; // @[RocketCore.scala:1320:{39,44}] wire [63:0] id_rs_1; // @[RocketCore.scala:1325:26] wire _id_rs_T_5 = ~(\|id_raddr2); // @[RocketCore.scala:326:72, :1326:41] wire [4:0] _id_rs_T_8 = ~_id_rs_T_7; // @[RocketCore.scala:1320:{39,44}] wire _ctrl_killd_T_4; // @[RocketCore.scala:1046:104] wire ctrl_killd; // @[RocketCore.scala:338:24] wire _id_npc_sign_T_1 = _ibuf_io_inst_0_bits_inst_bits[31]; // @[RocketCore.scala:311:20, :1341:44] wire _id_npc_sign_T_2 = _id_npc_sign_T_1; // @[RocketCore.scala:1341:{44,49}] wire id_npc_sign = _id_npc_sign_T_2; // @[RocketCore.scala:1341:{19,49}] wire _id_npc_b11_T_9 = id_npc_sign; // @[RocketCore.scala:1341:19, :1346:18] wire id_npc_hi_hi_hi = id_npc_sign; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _id_npc_b30_20_T_1 = _ibuf_io_inst_0_bits_inst_bits[30:20]; // @[RocketCore.scala:311:20, :1342:41] wire [10:0] _id_npc_b30_20_T_2 = _id_npc_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}] wire [10:0] id_npc_b30_20 = {11{id_npc_sign}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] id_npc_hi_hi_lo = id_npc_b30_20; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _id_npc_b19_12_T_3 = _ibuf_io_inst_0_bits_inst_bits[19:12]; // @[RocketCore.scala:311:20, :1343:65] wire [7:0] _id_npc_b19_12_T_4 = _id_npc_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}] wire [7:0] id_npc_b19_12 = _id_npc_b19_12_T_4; // @[RocketCore.scala:1343:{21,73}] wire [7:0] id_npc_hi_lo_hi = id_npc_b19_12; // @[RocketCore.scala:1343:21, :1355:8] wire _id_npc_b11_T_4 = _ibuf_io_inst_0_bits_inst_bits[20]; // @[RocketCore.scala:311:20, :1345:39] wire _id_npc_b0_T_3 = _ibuf_io_inst_0_bits_inst_bits[20]; // @[RocketCore.scala:311:20, :1345:39, :1352:37] wire _id_npc_b11_T_5 = _id_npc_b11_T_4; // @[RocketCore.scala:1345:{39,44}] wire _id_npc_b11_T_10 = _id_npc_b11_T_5; // @[RocketCore.scala:1345:{18,44}] wire _id_npc_b11_T_7 = _ibuf_io_inst_0_bits_inst_bits[7]; // @[RocketCore.scala:311:20, :1346:39] wire _id_npc_b0_T_1 = _ibuf_io_inst_0_bits_inst_bits[7]; // @[RocketCore.scala:311:20, :1346:39, :1351:37] wire _id_npc_b11_T_8 = _id_npc_b11_T_7; // @[RocketCore.scala:1346:{39,43}] wire id_npc_b11 = _id_npc_b11_T_10; // @[RocketCore.scala:1344:18, :1345:18] wire id_npc_hi_lo_lo = id_npc_b11; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] _id_npc_b10_5_T_3 = _ibuf_io_inst_0_bits_inst_bits[30:25]; // @[RocketCore.scala:311:20, :1347:62] wire [5:0] id_npc_b10_5 = _id_npc_b10_5_T_3; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _id_npc_b4_1_T_4 = _ibuf_io_inst_0_bits_inst_bits[11:8]; // @[RocketCore.scala:311:20, :1349:57] wire [3:0] _id_npc_b4_1_T_6 = _ibuf_io_inst_0_bits_inst_bits[19:16]; // @[RocketCore.scala:311:20, :1350:39] wire [3:0] _id_npc_b4_1_T_7 = _ibuf_io_inst_0_bits_inst_bits[24:21]; // @[RocketCore.scala:311:20, :1350:52] wire [3:0] _id_npc_b4_1_T_8 = _id_npc_b4_1_T_7; // @[RocketCore.scala:1350:{19,52}] wire [3:0] _id_npc_b4_1_T_9 = _id_npc_b4_1_T_8; // @[RocketCore.scala:1349:19, :1350:19] wire [3:0] id_npc_b4_1 = _id_npc_b4_1_T_9; // @[RocketCore.scala:1348:19, :1349:19] wire _id_npc_b0_T_5 = _ibuf_io_inst_0_bits_inst_bits[15]; // @[RocketCore.scala:311:20, :1353:37] wire [9:0] id_npc_lo_hi = {id_npc_b10_5, id_npc_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] id_npc_lo = {id_npc_lo_hi, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] id_npc_hi_lo = {id_npc_hi_lo_hi, id_npc_hi_lo_lo}; // @[RocketCore.scala:1355:8] wire [11:0] id_npc_hi_hi = {id_npc_hi_hi_hi, id_npc_hi_hi_lo}; // @[RocketCore.scala:1355:8] wire [20:0] id_npc_hi = {id_npc_hi_hi, id_npc_hi_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _id_npc_T_1 = {id_npc_hi, id_npc_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _id_npc_T_2 = _id_npc_T_1; // @[RocketCore.scala:1355:{8,53}] wire [39:0] _id_npc_T; // @[RocketCore.scala:339:28] wire [40:0] _id_npc_T_3 = {_id_npc_T[39], _id_npc_T} + {{9{_id_npc_T_2[31]}}, _id_npc_T_2}; // @[RocketCore.scala:339:{28,35}, :1355:53] wire [39:0] _id_npc_T_4 = _id_npc_T_3[39:0]; // @[RocketCore.scala:339:35] wire [39:0] _id_npc_T_5 = _id_npc_T_4; // @[RocketCore.scala:339:35] wire [39:0] id_npc = _id_npc_T_5; // @[RocketCore.scala:339:{35,65}] wire _GEN_36 = id_ctrl_csr == 3'h6; // @[package.scala:16:47] wire _id_csr_en_T; // @[package.scala:16:47] assign _id_csr_en_T = _GEN_36; // @[package.scala:16:47] wire _id_csr_ren_T; // @[package.scala:16:47] assign _id_csr_ren_T = _GEN_36; // @[package.scala:16:47] wire _id_csr_en_T_1 = &id_ctrl_csr; // @[package.scala:16:47] wire _id_csr_en_T_2 = id_ctrl_csr == 3'h5; // @[package.scala:16:47] wire _id_csr_en_T_3 = _id_csr_en_T \| _id_csr_en_T_1; // @[package.scala:16:47, :81:59] wire id_csr_en = _id_csr_en_T_3 \| _id_csr_en_T_2; // @[package.scala:16:47, :81:59] wire id_system_insn = id_ctrl_csr == 3'h4; // @[RocketCore.scala:321:21, :343:36] wire _id_csr_ren_T_1 = &id_ctrl_csr; // @[package.scala:16:47] wire _id_csr_ren_T_2 = _id_csr_ren_T \| _id_csr_ren_T_1; // @[package.scala:16:47, :81:59] wire _id_csr_ren_T_3 = _ibuf_io_inst_0_bits_inst_rs1 == 5'h0; // @[RocketCore.scala:311:20, :344:81] wire id_csr_ren = _id_csr_ren_T_2 & _id_csr_ren_T_3; // @[package.scala:81:59] wire _id_csr_T = id_system_insn & id_ctrl_mem; // @[RocketCore.scala:321:21, :343:36, :345:35] wire [2:0] _id_csr_T_1 = id_csr_ren ? 3'h2 : id_ctrl_csr; // @[RocketCore.scala:321:21, :344:54, :345:61] wire [2:0] id_csr = _id_csr_T ? 3'h0 : _id_csr_T_1; // @[RocketCore.scala:345:{19,35,61}] wire _id_csr_flush_T = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54] wire _id_csr_flush_T_1 = id_csr_en & _id_csr_flush_T; // @[package.scala:81:59] wire _id_csr_flush_T_2 = _id_csr_flush_T_1 & _csr_io_decode_0_write_flush; // @[RocketCore.scala:341:19, :346:{51,66}] wire id_csr_flush = id_system_insn \| _id_csr_flush_T_2; // @[RocketCore.scala:343:36, :346:{37,66}] wire [31:0] _id_set_vconfig_T = _ibuf_io_inst_0_bits_inst_bits & 32'h8000707F; // @[RocketCore.scala:311:20, :347:100] wire _id_set_vconfig_T_1 = _id_set_vconfig_T == 32'h7057; // @[RocketCore.scala:347:100] wire [31:0] _id_set_vconfig_T_2 = _ibuf_io_inst_0_bits_inst_bits & 32'hC000707F; // @[RocketCore.scala:311:20, :347:100] wire _id_set_vconfig_T_3 = _id_set_vconfig_T_2 == 32'hC0007057; // @[RocketCore.scala:347:100] wire [31:0] _id_set_vconfig_T_4 = _ibuf_io_inst_0_bits_inst_bits & 32'hFE00707F; // @[RocketCore.scala:311:20, :347:100] wire _id_set_vconfig_T_5 = _id_set_vconfig_T_4 == 32'h80007057; // @[RocketCore.scala:347:100] wire _id_set_vconfig_T_6 = _id_set_vconfig_T_1 \| _id_set_vconfig_T_3; // @[package.scala:81:59] wire _id_set_vconfig_T_7 = _id_set_vconfig_T_6 \| _id_set_vconfig_T_5; // @[package.scala:81:59] wire _id_illegal_insn_T = ~id_ctrl_legal; // @[RocketCore.scala:321:21, :381:25] wire _id_illegal_insn_T_1 = id_ctrl_mul \| id_ctrl_div; // @[RocketCore.scala:321:21, :382:18] wire _id_illegal_insn_T_2 = _csr_io_status_isa[12]; // @[RocketCore.scala:341:19, :382:55] wire _id_illegal_insn_T_3 = ~_id_illegal_insn_T_2; // @[RocketCore.scala:382:{37,55}] wire _id_illegal_insn_T_4 = _id_illegal_insn_T_1 & _id_illegal_insn_T_3; // @[RocketCore.scala:382:{18,34,37}] wire _id_illegal_insn_T_5 = _id_illegal_insn_T \| _id_illegal_insn_T_4; // @[RocketCore.scala:381:{25,40}, :382:34] wire _id_illegal_insn_T_6 = _csr_io_status_isa[0]; // @[RocketCore.scala:341:19, :383:38] wire _id_illegal_insn_T_7 = ~_id_illegal_insn_T_6; // @[RocketCore.scala:383:{20,38}] wire _id_illegal_insn_T_8 = id_ctrl_amo & _id_illegal_insn_T_7; // @[RocketCore.scala:321:21, :383:{17,20}] wire _id_illegal_insn_T_9 = _id_illegal_insn_T_5 \| _id_illegal_insn_T_8; // @[RocketCore.scala:381:40, :382:65, :383:17] wire _id_illegal_insn_T_12 = _csr_io_decode_0_fp_illegal \| _id_illegal_insn_T_11; // @[RocketCore.scala:341:19, :384:{48,70}] wire _id_illegal_insn_T_13 = id_ctrl_fp & _id_illegal_insn_T_12; // @[RocketCore.scala:321:21, :384:{16,48}] wire _id_illegal_insn_T_14 = _id_illegal_insn_T_9 \| _id_illegal_insn_T_13; // @[RocketCore.scala:382:65, :383:48, :384:16] wire _id_illegal_insn_T_17 = _id_illegal_insn_T_14; // @[RocketCore.scala:383:48, :384:88] wire _id_illegal_insn_T_18 = _csr_io_status_isa[3]; // @[RocketCore.scala:341:19, :386:37] wire _id_illegal_insn_T_19 = ~_id_illegal_insn_T_18; // @[RocketCore.scala:386:{19,37}] wire _id_illegal_insn_T_20 = id_ctrl_dp & _id_illegal_insn_T_19; // @[RocketCore.scala:321:21, :386:{16,19}] wire _id_illegal_insn_T_21 = _id_illegal_insn_T_17 \| _id_illegal_insn_T_20; // @[RocketCore.scala:384:88, :385:118, :386:16] wire _id_illegal_insn_T_22 = _csr_io_status_isa[2]; // @[RocketCore.scala:341:19, :387:51] wire _mem_npc_misaligned_T = _csr_io_status_isa[2]; // @[RocketCore.scala:341:19, :387:51, :623:46] wire _id_illegal_insn_T_23 = ~_id_illegal_insn_T_22; // @[RocketCore.scala:387:{33,51}] wire _id_illegal_insn_T_24 = _ibuf_io_inst_0_bits_rvc & _id_illegal_insn_T_23; // @[RocketCore.scala:311:20, :387:{30,33}] wire _id_illegal_insn_T_25 = _id_illegal_insn_T_21 \| _id_illegal_insn_T_24; // @[RocketCore.scala:385:118, :386:47, :387:30] wire _id_illegal_insn_T_27 = _id_illegal_insn_T_25; // @[RocketCore.scala:386:47, :387:61] wire _id_illegal_insn_T_29 = _id_illegal_insn_T_27; // @[RocketCore.scala:387:61, :388:39] wire _id_illegal_insn_T_31 = _id_illegal_insn_T_29; // @[RocketCore.scala:388:39, :389:39] wire _id_illegal_insn_T_33 = _id_illegal_insn_T_31 \| _id_illegal_insn_T_32; // @[RocketCore.scala:389:39, :390:37, :391:18] wire _id_illegal_insn_T_34 = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54, :392:52] wire _id_illegal_insn_T_35 = _id_illegal_insn_T_34 & _csr_io_decode_0_write_illegal; // @[RocketCore.scala:341:19, :392:{52,64}] wire _id_illegal_insn_T_36 = _csr_io_decode_0_read_illegal \| _id_illegal_insn_T_35; // @[RocketCore.scala:341:19, :392:{49,64}] wire _id_illegal_insn_T_37 = id_csr_en & _id_illegal_insn_T_36; // @[package.scala:81:59] wire _id_illegal_insn_T_38 = _id_illegal_insn_T_33 \| _id_illegal_insn_T_37; // @[RocketCore.scala:390:37, :391:51, :392:15] wire _id_illegal_insn_T_39 = ~_ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala:311:20, :393:5] wire _id_illegal_insn_T_40 = id_system_insn & _csr_io_decode_0_system_illegal; // @[RocketCore.scala:341:19, :343:36, :393:50] wire _id_illegal_insn_T_41 = _id_illegal_insn_T_39 & _id_illegal_insn_T_40; // @[RocketCore.scala:393:{5,31,50}] wire id_illegal_insn = _id_illegal_insn_T_38 \| _id_illegal_insn_T_41; // @[RocketCore.scala:391:51, :392:99, :393:31] wire _id_virtual_insn_T = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54, :395:22] wire _id_virtual_insn_T_1 = _id_virtual_insn_T & _csr_io_decode_0_write_illegal; // @[RocketCore.scala:341:19, :395:{22,34}] wire _id_virtual_insn_T_2 = ~_id_virtual_insn_T_1; // @[RocketCore.scala:395:{20,34}] wire _id_virtual_insn_T_3 = id_csr_en & _id_virtual_insn_T_2; // @[package.scala:81:59] wire _id_virtual_insn_T_4 = _id_virtual_insn_T_3 & _csr_io_decode_0_virtual_access_illegal; // @[RocketCore.scala:341:19, :395:{17,69}] wire _id_virtual_insn_T_5 = ~_ibuf_io_inst_0_bits_rvc; // @[RocketCore.scala:311:20, :393:5, :396:7] wire _id_virtual_insn_T_6 = _id_virtual_insn_T_5 & id_system_insn; // @[RocketCore.scala:343:36, :396:{7,33}] wire _id_virtual_insn_T_7 = _id_virtual_insn_T_6 & _csr_io_decode_0_virtual_system_illegal; // @[RocketCore.scala:341:19, :396:{33,51}] wire _id_virtual_insn_T_8 = _id_virtual_insn_T_4 \| _id_virtual_insn_T_7; // @[RocketCore.scala:395:{69,113}, :396:51] wire id_virtual_insn = id_ctrl_legal & _id_virtual_insn_T_8; // @[RocketCore.scala:321:21, :394:39, :395:113] wire id_amo_aq = _ibuf_io_inst_0_bits_inst_bits[26]; // @[RocketCore.scala:311:20, :398:29] wire id_amo_rl = _ibuf_io_inst_0_bits_inst_bits[25]; // @[RocketCore.scala:311:20, :399:29] wire [3:0] id_fence_pred = _ibuf_io_inst_0_bits_inst_bits[27:24]; // @[RocketCore.scala:311:20, :400:33] wire [3:0] id_fence_succ = _ibuf_io_inst_0_bits_inst_bits[23:20]; // @[RocketCore.scala:311:20, :401:33] wire _id_fence_next_T = id_ctrl_amo & id_amo_aq; // @[RocketCore.scala:321:21, :398:29, :402:52] wire id_fence_next = id_ctrl_fence \| _id_fence_next_T; // @[RocketCore.scala:321:21, :402:{37,52}] wire _id_mem_busy_T = ~io_dmem_ordered_0; // @[RocketCore.scala:153:7, :403:21] wire id_mem_busy = _id_mem_busy_T \| io_dmem_req_valid_0; // @[RocketCore.scala:153:7, :403:{21,38}] wire _id_rocc_busy_T = ex_reg_valid & ex_ctrl_rocc; // @[RocketCore.scala:243:20, :248:35, :406:35] wire _id_rocc_busy_T_1 = _id_rocc_busy_T; // @[RocketCore.scala:406:{19,35}] wire _id_rocc_busy_T_2 = mem_reg_valid & mem_ctrl_rocc; // @[RocketCore.scala:244:21, :265:36, :407:20] wire _id_rocc_busy_T_3 = _id_rocc_busy_T_1 \| _id_rocc_busy_T_2; // @[RocketCore.scala:406:{19,51}, :407:20] wire _GEN_37 = wb_reg_valid & wb_ctrl_rocc; // @[RocketCore.scala:245:20, :288:35, :407:53] wire _id_rocc_busy_T_4; // @[RocketCore.scala:407:53] assign _id_rocc_busy_T_4 = _GEN_37; // @[RocketCore.scala:407:53] wire _replay_wb_rocc_T; // @[RocketCore.scala:758:37] assign _replay_wb_rocc_T = _GEN_37; // @[RocketCore.scala:407:53, :758:37] wire _io_rocc_cmd_valid_T; // @[RocketCore.scala:1156:37] assign _io_rocc_cmd_valid_T = _GEN_37; // @[RocketCore.scala:407:53, :1156:37] wire _id_rocc_busy_T_5 = _id_rocc_busy_T_3 \| _id_rocc_busy_T_4; // @[RocketCore.scala:406:51, :407:{37,53}] wire _id_csr_rocc_write_T_1 = ~id_csr_ren; // @[RocketCore.scala:344:54, :346:54, :408:103] wire _id_do_fence_T_4 = id_ctrl_amo & id_amo_rl; // @[RocketCore.scala:321:21, :399:29, :412:33] wire _id_do_fence_T_5 = _id_do_fence_T_4 \| id_ctrl_fence_i; // @[RocketCore.scala:321:21, :412:{33,46}] wire _id_do_fence_T_6 = id_ctrl_mem \| id_ctrl_rocc; // @[RocketCore.scala:321:21, :412:97] wire _id_do_fence_T_7 = id_reg_fence & _id_do_fence_T_6; // @[RocketCore.scala:333:29, :412:{81,97}] wire _id_do_fence_T_8 = _id_do_fence_T_5 \| _id_do_fence_T_7; // @[RocketCore.scala:412:{46,65,81}] wire _id_do_fence_T_9 = id_mem_busy & _id_do_fence_T_8; // @[RocketCore.scala:403:38, :412:{17,65}] wire _id_do_fence_T_10 = _id_do_fence_T_9; // @[RocketCore.scala:411:34, :412:17] wire id_do_fence = _id_do_fence_T_10; // @[RocketCore.scala:410:32, :411:34] wire [38:0] _mem_npc_T_1 = mem_reg_wdata[38:0]; // @[RocketCore.scala:282:26, :418:13, :1295:16] wire id_xcpt = _csr_io_interrupt \| _bpu_io_debug_if \| _bpu_io_xcpt_if \| _ibuf_io_inst_0_bits_xcpt0_pf_inst \| _ibuf_io_inst_0_bits_xcpt0_gf_inst \| _ibuf_io_inst_0_bits_xcpt0_ae_inst \| _ibuf_io_inst_0_bits_xcpt1_pf_inst \| _ibuf_io_inst_0_bits_xcpt1_gf_inst \| _ibuf_io_inst_0_bits_xcpt1_ae_inst \| id_virtual_insn \| id_illegal_insn; // @[RocketCore.scala:311:20, :341:19, :392:99, :394:39, :414:19, :1278:{14,35}] wire [63:0] id_cause = _csr_io_interrupt ? _csr_io_interrupt_cause : {59'h0, _bpu_io_debug_if ? 5'hE : _bpu_io_xcpt_if ? 5'h3 : _ibuf_io_inst_0_bits_xcpt0_pf_inst ? 5'hC : _ibuf_io_inst_0_bits_xcpt0_gf_inst ? 5'h14 : _ibuf_io_inst_0_bits_xcpt0_ae_inst ? 5'h1 : _ibuf_io_inst_0_bits_xcpt1_pf_inst ? 5'hC : _ibuf_io_inst_0_bits_xcpt1_gf_inst ? 5'h14 : _ibuf_io_inst_0_bits_xcpt1_ae_inst ? 5'h1 : id_virtual_insn ? 5'h16 : 5'h2}; // @[Mux.scala:50:70] wire [4:0] _ex_waddr_T = ex_reg_inst[11:7]; // @[RocketCore.scala:259:24, :453:29] wire [4:0] ex_waddr = _ex_waddr_T; // @[RocketCore.scala:453:{29,36}] wire [4:0] _mem_waddr_T = mem_reg_inst[11:7]; // @[RocketCore.scala:278:25, :454:31] wire [4:0] mem_waddr = _mem_waddr_T; // @[RocketCore.scala:454:{31,38}] wire [4:0] _wb_waddr_T = wb_reg_inst[11:7]; // @[RocketCore.scala:300:24, :455:29] wire [4:0] wb_waddr = _wb_waddr_T; // @[RocketCore.scala:455:{29,36}] wire [4:0] coreMonitorBundle_wrdst = wb_waddr; // @[RocketCore.scala:455:36, :1186:31] wire bypass_sources_1_1 = ex_reg_valid & ex_ctrl_wxd; // @[RocketCore.scala:243:20, :248:35, :458:19] wire _GEN_38 = mem_reg_valid & mem_ctrl_wxd; // @[RocketCore.scala:244:21, :265:36, :459:20] wire _bypass_sources_T; // @[RocketCore.scala:459:20] assign _bypass_sources_T = _GEN_38; // @[RocketCore.scala:459:20] wire bypass_sources_3_1; // @[RocketCore.scala:460:20] assign bypass_sources_3_1 = _GEN_38; // @[RocketCore.scala:459:20, :460:20] wire _dcache_kill_mem_T; // @[RocketCore.scala:695:39] assign _dcache_kill_mem_T = _GEN_38; // @[RocketCore.scala:459:20, :695:39] wire _bypass_sources_T_1 = ~mem_ctrl_mem; // @[RocketCore.scala:244:21, :459:39] wire bypass_sources_2_1 = _bypass_sources_T & _bypass_sources_T_1; // @[RocketCore.scala:459:{20,36,39}] wire _id_bypass_src_T = ~(\|id_raddr1); // @[RocketCore.scala:326:72, :461:82, :1326:41] wire id_bypass_src_0_0 = _id_bypass_src_T; // @[RocketCore.scala:461:{74,82}] wire _GEN_39 = ex_waddr == id_raddr1; // @[RocketCore.scala:326:72, :453:36, :461:82] wire _id_bypass_src_T_1; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_1 = _GEN_39; // @[RocketCore.scala:461:82] wire _data_hazard_ex_T; // @[RocketCore.scala:989:70] assign _data_hazard_ex_T = _GEN_39; // @[RocketCore.scala:461:82, :989:70] wire _fp_data_hazard_ex_T_1; // @[RocketCore.scala:990:90] assign _fp_data_hazard_ex_T_1 = _GEN_39; // @[RocketCore.scala:461:82, :990:90] wire id_bypass_src_0_1 = bypass_sources_1_1 & _id_bypass_src_T_1; // @[RocketCore.scala:458:19, :461:{74,82}] wire _GEN_40 = mem_waddr == id_raddr1; // @[RocketCore.scala:326:72, :454:38, :461:82] wire _id_bypass_src_T_2; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_2 = _GEN_40; // @[RocketCore.scala:461:82] wire _id_bypass_src_T_3; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_3 = _GEN_40; // @[RocketCore.scala:461:82] wire _data_hazard_mem_T; // @[RocketCore.scala:998:72] assign _data_hazard_mem_T = _GEN_40; // @[RocketCore.scala:461:82, :998:72] wire _fp_data_hazard_mem_T_1; // @[RocketCore.scala:999:92] assign _fp_data_hazard_mem_T_1 = _GEN_40; // @[RocketCore.scala:461:82, :999:92] wire id_bypass_src_0_2 = bypass_sources_2_1 & _id_bypass_src_T_2; // @[RocketCore.scala:459:36, :461:{74,82}] wire id_bypass_src_0_3 = bypass_sources_3_1 & _id_bypass_src_T_3; // @[RocketCore.scala:460:20, :461:{74,82}] wire _id_bypass_src_T_4 = ~(\|id_raddr2); // @[RocketCore.scala:326:72, :461:82, :1326:41] wire id_bypass_src_1_0 = _id_bypass_src_T_4; // @[RocketCore.scala:461:{74,82}] wire _GEN_41 = ex_waddr == id_raddr2; // @[RocketCore.scala:326:72, :453:36, :461:82] wire _id_bypass_src_T_5; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_5 = _GEN_41; // @[RocketCore.scala:461:82] wire _data_hazard_ex_T_2; // @[RocketCore.scala:989:70] assign _data_hazard_ex_T_2 = _GEN_41; // @[RocketCore.scala:461:82, :989:70] wire _fp_data_hazard_ex_T_3; // @[RocketCore.scala:990:90] assign _fp_data_hazard_ex_T_3 = _GEN_41; // @[RocketCore.scala:461:82, :990:90] wire id_bypass_src_1_1 = bypass_sources_1_1 & _id_bypass_src_T_5; // @[RocketCore.scala:458:19, :461:{74,82}] wire _GEN_42 = mem_waddr == id_raddr2; // @[RocketCore.scala:326:72, :454:38, :461:82] wire _id_bypass_src_T_6; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_6 = _GEN_42; // @[RocketCore.scala:461:82] wire _id_bypass_src_T_7; // @[RocketCore.scala:461:82] assign _id_bypass_src_T_7 = _GEN_42; // @[RocketCore.scala:461:82] wire _data_hazard_mem_T_2; // @[RocketCore.scala:998:72] assign _data_hazard_mem_T_2 = _GEN_42; // @[RocketCore.scala:461:82, :998:72] wire _fp_data_hazard_mem_T_3; // @[RocketCore.scala:999:92] assign _fp_data_hazard_mem_T_3 = _GEN_42; // @[RocketCore.scala:461:82, :999:92] wire id_bypass_src_1_2 = bypass_sources_2_1 & _id_bypass_src_T_6; // @[RocketCore.scala:459:36, :461:{74,82}] wire id_bypass_src_1_3 = bypass_sources_3_1 & _id_bypass_src_T_7; // @[RocketCore.scala:460:20, :461:{74,82}] reg ex_reg_rs_bypass_0; // @[RocketCore.scala:465:29] reg ex_reg_rs_bypass_1; // @[RocketCore.scala:465:29] reg [1:0] ex_reg_rs_lsb_0; // @[RocketCore.scala:466:26] reg [1:0] ex_reg_rs_lsb_1; // @[RocketCore.scala:466:26] reg [61:0] ex_reg_rs_msb_0; // @[RocketCore.scala:467:26] reg [61:0] ex_reg_rs_msb_1; // @[RocketCore.scala:467:26] wire _ex_rs_T = ex_reg_rs_lsb_0 == 2'h1; // @[package.scala:39:86] wire [63:0] _ex_rs_T_1 = _ex_rs_T ? mem_reg_wdata : 64'h0; // @[package.scala:39:{76,86}] wire _ex_rs_T_2 = ex_reg_rs_lsb_0 == 2'h2; // @[package.scala:39:86] wire [63:0] _ex_rs_T_3 = _ex_rs_T_2 ? wb_reg_wdata : _ex_rs_T_1; // @[package.scala:39:{76,86}] wire _ex_rs_T_4 = &ex_reg_rs_lsb_0; // @[package.scala:39:86] wire [63:0] _ex_rs_T_5 = _ex_rs_T_4 ? dcache_bypass_data : _ex_rs_T_3; // @[package.scala:39:{76,86}] wire [63:0] _ex_rs_T_6 = {ex_reg_rs_msb_0, ex_reg_rs_lsb_0}; // @[RocketCore.scala:466:26, :467:26, :469:69] assign ex_rs_0 = ex_reg_rs_bypass_0 ? _ex_rs_T_5 : _ex_rs_T_6; // @[package.scala:39:76] assign io_fpu_fromint_data_0 = ex_rs_0; // @[RocketCore.scala:153:7, :469:14] wire [63:0] _ex_op1_T = ex_rs_0; // @[RocketCore.scala:469:14, :473:24] wire _ex_rs_T_7 = ex_reg_rs_lsb_1 == 2'h1; // @[package.scala:39:86] wire [63:0] _ex_rs_T_8 = _ex_rs_T_7 ? mem_reg_wdata : 64'h0; // @[package.scala:39:{76,86}] wire _ex_rs_T_9 = ex_reg_rs_lsb_1 == 2'h2; // @[package.scala:39:86] wire [63:0] _ex_rs_T_10 = _ex_rs_T_9 ? wb_reg_wdata : _ex_rs_T_8; // @[package.scala:39:{76,86}] wire _ex_rs_T_11 = &ex_reg_rs_lsb_1; // @[package.scala:39:86] wire [63:0] _ex_rs_T_12 = _ex_rs_T_11 ? dcache_bypass_data : _ex_rs_T_10; // @[package.scala:39:{76,86}] wire [63:0] _ex_rs_T_13 = {ex_reg_rs_msb_1, ex_reg_rs_lsb_1}; // @[RocketCore.scala:466:26, :467:26, :469:69] wire [63:0] ex_rs_1 = ex_reg_rs_bypass_1 ? _ex_rs_T_12 : _ex_rs_T_13; // @[package.scala:39:76] wire [63:0] _ex_op2_T = ex_rs_1; // @[RocketCore.scala:469:14, :479:24] wire [63:0] mem_reg_rs2_dat_padded = ex_rs_1; // @[RocketCore.scala:469:14] wire _GEN_43 = ex_ctrl_sel_imm == 3'h5; // @[RocketCore.scala:243:20, :1341:24] wire _ex_imm_sign_T; // @[RocketCore.scala:1341:24] assign _ex_imm_sign_T = _GEN_43; // @[RocketCore.scala:1341:24] wire _ex_imm_b11_T_1; // @[RocketCore.scala:1344:40] assign _ex_imm_b11_T_1 = _GEN_43; // @[RocketCore.scala:1341:24, :1344:40] wire _ex_imm_b10_5_T_1; // @[RocketCore.scala:1347:42] assign _ex_imm_b10_5_T_1 = _GEN_43; // @[RocketCore.scala:1341:24, :1347:42] wire _ex_imm_b4_1_T_5; // @[RocketCore.scala:1350:24] assign _ex_imm_b4_1_T_5 = _GEN_43; // @[RocketCore.scala:1341:24, :1350:24] wire _ex_imm_b0_T_4; // @[RocketCore.scala:1353:22] assign _ex_imm_b0_T_4 = _GEN_43; // @[RocketCore.scala:1341:24, :1353:22] wire _ex_imm_sign_T_1 = ex_reg_inst[31]; // @[RocketCore.scala:259:24, :1341:44] wire _ex_imm_sign_T_2 = _ex_imm_sign_T_1; // @[RocketCore.scala:1341:{44,49}] wire ex_imm_sign = ~_ex_imm_sign_T & _ex_imm_sign_T_2; // @[RocketCore.scala:1341:{19,24,49}] wire ex_imm_hi_hi_hi = ex_imm_sign; // @[RocketCore.scala:1341:19, :1355:8] wire _GEN_44 = ex_ctrl_sel_imm == 3'h2; // @[RocketCore.scala:243:20, :1342:26] wire _ex_imm_b30_20_T; // @[RocketCore.scala:1342:26] assign _ex_imm_b30_20_T = _GEN_44; // @[RocketCore.scala:1342:26] wire _ex_imm_b11_T; // @[RocketCore.scala:1344:23] assign _ex_imm_b11_T = _GEN_44; // @[RocketCore.scala:1342:26, :1344:23] wire _ex_imm_b10_5_T; // @[RocketCore.scala:1347:25] assign _ex_imm_b10_5_T = _GEN_44; // @[RocketCore.scala:1342:26, :1347:25] wire _ex_imm_b4_1_T; // @[RocketCore.scala:1348:24] assign _ex_imm_b4_1_T = _GEN_44; // @[RocketCore.scala:1342:26, :1348:24] wire [10:0] _ex_imm_b30_20_T_1 = ex_reg_inst[30:20]; // @[RocketCore.scala:259:24, :1342:41] wire [10:0] _ex_imm_b30_20_T_2 = _ex_imm_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}] wire [10:0] ex_imm_b30_20 = _ex_imm_b30_20_T ? _ex_imm_b30_20_T_2 : {11{ex_imm_sign}}; // @[RocketCore.scala:1341:19, :1342:{21,26,49}] wire [10:0] ex_imm_hi_hi_lo = ex_imm_b30_20; // @[RocketCore.scala:1342:21, :1355:8] wire _ex_imm_b19_12_T = ex_ctrl_sel_imm != 3'h2; // @[RocketCore.scala:243:20, :1343:26] wire _ex_imm_b19_12_T_1 = ex_ctrl_sel_imm != 3'h3; // @[RocketCore.scala:243:20, :1343:43] wire _ex_imm_b19_12_T_2 = _ex_imm_b19_12_T & _ex_imm_b19_12_T_1; // @[RocketCore.scala:1343:{26,36,43}] wire [7:0] _ex_imm_b19_12_T_3 = ex_reg_inst[19:12]; // @[RocketCore.scala:259:24, :1343:65] wire [7:0] _ex_imm_b19_12_T_4 = _ex_imm_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}] wire [7:0] ex_imm_b19_12 = _ex_imm_b19_12_T_2 ? {8{ex_imm_sign}} : _ex_imm_b19_12_T_4; // @[RocketCore.scala:1341:19, :1343:{21,36,73}] wire [7:0] ex_imm_hi_lo_hi = ex_imm_b19_12; // @[RocketCore.scala:1343:21, :1355:8] wire _ex_imm_b11_T_2 = _ex_imm_b11_T \| _ex_imm_b11_T_1; // @[RocketCore.scala:1344:{23,33,40}] wire _ex_imm_b11_T_3 = ex_ctrl_sel_imm == 3'h3; // @[RocketCore.scala:243:20, :1345:23] wire _ex_imm_b11_T_4 = ex_reg_inst[20]; // @[RocketCore.scala:259:24, :1345:39] wire _ex_imm_b0_T_3 = ex_reg_inst[20]; // @[RocketCore.scala:259:24, :1345:39, :1352:37] wire _io_dmem_req_bits_signed_T = ex_reg_inst[20]; // @[RocketCore.scala:259:24, :1136:58, :1345:39] wire _ex_imm_b11_T_5 = _ex_imm_b11_T_4; // @[RocketCore.scala:1345:{39,44}] wire _GEN_45 = ex_ctrl_sel_imm == 3'h1; // @[RocketCore.scala:243:20, :1346:23] wire _ex_imm_b11_T_6; // @[RocketCore.scala:1346:23] assign _ex_imm_b11_T_6 = _GEN_45; // @[RocketCore.scala:1346:23] wire _ex_imm_b4_1_T_2; // @[RocketCore.scala:1349:41] assign _ex_imm_b4_1_T_2 = _GEN_45; // @[RocketCore.scala:1346:23, :1349:41] wire _ex_imm_b11_T_7 = ex_reg_inst[7]; // @[RocketCore.scala:259:24, :1346:39] wire _ex_imm_b0_T_1 = ex_reg_inst[7]; // @[RocketCore.scala:259:24, :1346:39, :1351:37] wire _ex_imm_b11_T_8 = _ex_imm_b11_T_7; // @[RocketCore.scala:1346:{39,43}] wire _ex_imm_b11_T_9 = _ex_imm_b11_T_6 ? _ex_imm_b11_T_8 : ex_imm_sign; // @[RocketCore.scala:1341:19, :1346:{18,23,43}] wire _ex_imm_b11_T_10 = _ex_imm_b11_T_3 ? _ex_imm_b11_T_5 : _ex_imm_b11_T_9; // @[RocketCore.scala:1345:{18,23,44}, :1346:18] wire ex_imm_b11 = ~_ex_imm_b11_T_2 & _ex_imm_b11_T_10; // @[RocketCore.scala:1344:{18,33}, :1345:18] wire ex_imm_hi_lo_lo = ex_imm_b11; // @[RocketCore.scala:1344:18, :1355:8] wire _ex_imm_b10_5_T_2 = _ex_imm_b10_5_T \| _ex_imm_b10_5_T_1; // @[RocketCore.scala:1347:{25,35,42}] wire [5:0] _ex_imm_b10_5_T_3 = ex_reg_inst[30:25]; // @[RocketCore.scala:259:24, :1347:62] wire [5:0] ex_imm_b10_5 = _ex_imm_b10_5_T_2 ? 6'h0 : _ex_imm_b10_5_T_3; // @[RocketCore.scala:1347:{20,35,62}] wire _GEN_46 = ex_ctrl_sel_imm == 3'h0; // @[RocketCore.scala:243:20, :1349:24] wire _ex_imm_b4_1_T_1; // @[RocketCore.scala:1349:24] assign _ex_imm_b4_1_T_1 = _GEN_46; // @[RocketCore.scala:1349:24] wire _ex_imm_b0_T; // @[RocketCore.scala:1351:22] assign _ex_imm_b0_T = _GEN_46; // @[RocketCore.scala:1349:24, :1351:22] wire _ex_imm_b4_1_T_3 = _ex_imm_b4_1_T_1 \| _ex_imm_b4_1_T_2; // @[RocketCore.scala:1349:{24,34,41}] wire [3:0] _ex_imm_b4_1_T_4 = ex_reg_inst[11:8]; // @[RocketCore.scala:259:24, :1349:57] wire [3:0] _ex_imm_b4_1_T_6 = ex_reg_inst[19:16]; // @[RocketCore.scala:259:24, :1350:39] wire [3:0] _ex_imm_b4_1_T_7 = ex_reg_inst[24:21]; // @[RocketCore.scala:259:24, :1350:52] wire [3:0] _ex_imm_b4_1_T_8 = _ex_imm_b4_1_T_5 ? _ex_imm_b4_1_T_6 : _ex_imm_b4_1_T_7; // @[RocketCore.scala:1350:{19,24,39,52}] wire [3:0] _ex_imm_b4_1_T_9 = _ex_imm_b4_1_T_3 ? _ex_imm_b4_1_T_4 : _ex_imm_b4_1_T_8; // @[RocketCore.scala:1349:{19,34,57}, :1350:19] wire [3:0] ex_imm_b4_1 = _ex_imm_b4_1_T ? 4'h0 : _ex_imm_b4_1_T_9; // @[RocketCore.scala:1348:{19,24}, :1349:19] wire _ex_imm_b0_T_2 = ex_ctrl_sel_imm == 3'h4; // @[RocketCore.scala:243:20, :1352:22] wire _ex_imm_b0_T_5 = ex_reg_inst[15]; // @[RocketCore.scala:259:24, :1353:37] wire _ex_imm_b0_T_6 = _ex_imm_b0_T_4 & _ex_imm_b0_T_5; // @[RocketCore.scala:1353:{17,22,37}] wire _ex_imm_b0_T_7 = _ex_imm_b0_T_2 ? _ex_imm_b0_T_3 : _ex_imm_b0_T_6; // @[RocketCore.scala:1352:{17,22,37}, :1353:17] wire ex_imm_b0 = _ex_imm_b0_T ? _ex_imm_b0_T_1 : _ex_imm_b0_T_7; // @[RocketCore.scala:1351:{17,22,37}, :1352:17] wire [9:0] ex_imm_lo_hi = {ex_imm_b10_5, ex_imm_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] ex_imm_lo = {ex_imm_lo_hi, ex_imm_b0}; // @[RocketCore.scala:1351:17, :1355:8] wire [8:0] ex_imm_hi_lo = {ex_imm_hi_lo_hi, ex_imm_hi_lo_lo}; // @[RocketCore.scala:1355:8] wire [11:0] ex_imm_hi_hi = {ex_imm_hi_hi_hi, ex_imm_hi_hi_lo}; // @[RocketCore.scala:1355:8] wire [20:0] ex_imm_hi = {ex_imm_hi_hi, ex_imm_hi_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _ex_imm_T = {ex_imm_hi, ex_imm_lo}; // @[RocketCore.scala:1355:8] wire [31:0] ex_imm = _ex_imm_T; // @[RocketCore.scala:1355:{8,53}] wire _ex_rs1shl_T = ex_reg_inst[3]; // @[RocketCore.scala:259:24, :471:34] wire [31:0] _ex_rs1shl_T_1 = ex_rs_0[31:0]; // @[RocketCore.scala:469:14, :471:47] wire [63:0] _ex_rs1shl_T_2 = _ex_rs1shl_T ? {32'h0, _ex_rs1shl_T_1} : ex_rs_0; // @[RocketCore.scala:469:14, :471:{22,34,47}] wire [1:0] _ex_rs1shl_T_3 = ex_reg_inst[14:13]; // @[RocketCore.scala:259:24, :471:79] wire [66:0] ex_rs1shl = {3'h0, _ex_rs1shl_T_2} << _ex_rs1shl_T_3; // @[RocketCore.scala:471:{22,65,79}] wire [66:0] _ex_op1_T_2 = ex_rs1shl; // @[RocketCore.scala:471:65, :475:54] wire _ex_op1_T_3 = ex_ctrl_sel_alu1 == 2'h1; // @[RocketCore.scala:243:20, :472:48] wire [63:0] _ex_op1_T_4 = _ex_op1_T_3 ? _ex_op1_T : 64'h0; // @[RocketCore.scala:472:48, :473:24] wire _ex_op1_T_5 = ex_ctrl_sel_alu1 == 2'h2; // @[RocketCore.scala:243:20, :472:48] wire [63:0] _ex_op1_T_6 = _ex_op1_T_5 ? {{24{_ex_op1_T_1[39]}}, _ex_op1_T_1} : _ex_op1_T_4; // @[RocketCore.scala:472:48, :474:24] wire _ex_op1_T_7 = &ex_ctrl_sel_alu1; // @[RocketCore.scala:243:20, :472:48] wire [66:0] ex_op1 = _ex_op1_T_7 ? _ex_op1_T_2 : {{3{_ex_op1_T_6[63]}}, _ex_op1_T_6}; // @[RocketCore.scala:472:48, :475:54] wire [66:0] _alu_io_in1_T = ex_op1; // @[RocketCore.scala:472:48, :508:24] wire _ex_op2_oh_T = ex_ctrl_sel_alu2[0]; // @[RocketCore.scala:243:20, :477:48] wire [11:0] _ex_op2_oh_T_1 = ex_reg_inst[31:20]; // @[RocketCore.scala:259:24, :477:66] wire [63:0] _ex_op2_oh_T_2 = _ex_op2_oh_T ? {52'h0, _ex_op2_oh_T_1} : ex_rs_1; // @[RocketCore.scala:469:14, :477:{31,48,66}] wire [5:0] _ex_op2_oh_T_3 = _ex_op2_oh_T_2[5:0]; // @[RocketCore.scala:477:{31,90}] wire [63:0] _ex_op2_oh_T_4 = 64'h1 << _ex_op2_oh_T_3; // @[OneHot.scala:58:35] wire [63:0] ex_op2_oh = _ex_op2_oh_T_4; // @[OneHot.scala:58:35] wire [3:0] _ex_op2_T_1 = ex_reg_rvc ? 4'h2 : 4'h4; // @[RocketCore.scala:249:35, :481:19] wire _ex_op2_T_2 = ex_ctrl_sel_alu2 == 3'h2; // @[RocketCore.scala:243:20, :478:48] wire [63:0] _ex_op2_T_3 = _ex_op2_T_2 ? _ex_op2_T : 64'h0; // @[RocketCore.scala:478:48, :479:24] wire _ex_op2_T_4 = ex_ctrl_sel_alu2 == 3'h3; // @[RocketCore.scala:243:20, :478:48] wire [63:0] _ex_op2_T_5 = _ex_op2_T_4 ? {{32{ex_imm[31]}}, ex_imm} : _ex_op2_T_3; // @[RocketCore.scala:478:48, :1355:53] wire _ex_op2_T_6 = ex_ctrl_sel_alu2 == 3'h1; // @[RocketCore.scala:243:20, :478:48] wire [63:0] _ex_op2_T_7 = _ex_op2_T_6 ? {{60{_ex_op2_T_1[3]}}, _ex_op2_T_1} : _ex_op2_T_5; // @[RocketCore.scala:478:48, :481:19] wire _ex_op2_T_8 = ex_ctrl_sel_alu2 == 3'h4; // @[RocketCore.scala:243:20, :478:48] wire [63:0] _ex_op2_T_9 = _ex_op2_T_8 ? ex_op2_oh : _ex_op2_T_7; // @[RocketCore.scala:477:112, :478:48] wire _ex_op2_T_10 = ex_ctrl_sel_alu2 == 3'h5; // @[RocketCore.scala:243:20, :478:48] wire [63:0] ex_op2 = _ex_op2_T_10 ? ex_op2_oh : _ex_op2_T_9; // @[RocketCore.scala:477:112, :478:48] wire [63:0] _alu_io_in2_T = ex_op2; // @[RocketCore.scala:478:48, :507:24] wire _div_io_req_valid_T = ex_reg_valid & ex_ctrl_div; // @[RocketCore.scala:243:20, :248:35, :512:36] wire _ex_reg_valid_T = ~ctrl_killd; // @[RocketCore.scala:338:24, :525:19] wire _ex_reg_replay_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20] wire _ex_reg_replay_T_1 = _ex_reg_replay_T & _ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20, :526:{20,29}] wire _ex_reg_replay_T_2 = _ex_reg_replay_T_1 & _ibuf_io_inst_0_bits_replay; // @[RocketCore.scala:311:20, :526:{29,54}] wire _ex_reg_xcpt_T = ~ctrl_killd; // @[RocketCore.scala:338:24, :525:19, :527:18] wire _ex_reg_xcpt_T_1 = _ex_reg_xcpt_T & id_xcpt; // @[RocketCore.scala:527:{18,30}, :1278:14] wire _ex_reg_xcpt_interrupt_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20, :528:28] wire _ex_reg_xcpt_interrupt_T_1 = _ex_reg_xcpt_interrupt_T & _ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20, :528:{28,37}] wire _ex_reg_xcpt_interrupt_T_2 = _ex_reg_xcpt_interrupt_T_1 & _csr_io_interrupt; // @[RocketCore.scala:341:19, :528:{37,62}] wire [1:0] hi = {_ibuf_io_inst_0_bits_xcpt1_pf_inst, _ibuf_io_inst_0_bits_xcpt1_gf_inst}; // @[RocketCore.scala:311:20, :541:22] wire [1:0] hi_1 = {_ibuf_io_inst_0_bits_xcpt0_pf_inst, _ibuf_io_inst_0_bits_xcpt0_gf_inst}; // @[RocketCore.scala:311:20, :546:40] wire _ex_reg_flush_pipe_T = id_ctrl_fence_i \| id_csr_flush; // @[RocketCore.scala:321:21, :346:37, :551:42] wire _ex_reg_hls_T_1 = id_ctrl_mem_cmd == 5'h0; // @[package.scala:16:47] wire _ex_reg_hls_T_2 = id_ctrl_mem_cmd == 5'h1; // @[package.scala:16:47] wire _ex_reg_hls_T_3 = id_ctrl_mem_cmd == 5'h10; // @[package.scala:16:47] wire _ex_reg_hls_T_4 = _ex_reg_hls_T_1 \| _ex_reg_hls_T_2; // @[package.scala:16:47, :81:59] wire _ex_reg_hls_T_5 = _ex_reg_hls_T_4 \| _ex_reg_hls_T_3; // @[package.scala:16:47, :81:59] wire [1:0] _ex_reg_mem_size_T_1 = _ibuf_io_inst_0_bits_inst_bits[27:26]; // @[RocketCore.scala:311:20, :554:75] wire [1:0] _ex_reg_mem_size_T_2 = _ibuf_io_inst_0_bits_inst_bits[13:12]; // @[RocketCore.scala:311:20, :554:95] wire [1:0] _ex_reg_mem_size_T_3 = _ex_reg_mem_size_T_2; // @[RocketCore.scala:554:{27,95}] wire _ex_reg_mem_size_T_4 = \|id_raddr2; // @[RocketCore.scala:326:72, :556:40, :1326:41] wire _ex_reg_mem_size_T_5 = \|id_raddr1; // @[RocketCore.scala:326:72, :556:59, :1326:41] wire [1:0] _ex_reg_mem_size_T_6 = {_ex_reg_mem_size_T_4, _ex_reg_mem_size_T_5}; // @[RocketCore.scala:556:{29,40,59}] wire _do_bypass_T = id_bypass_src_0_0 \| id_bypass_src_0_1; // @[RocketCore.scala:461:74, :568:48] wire _do_bypass_T_1 = _do_bypass_T \| id_bypass_src_0_2; // @[RocketCore.scala:461:74, :568:48] wire do_bypass = _do_bypass_T_1 \| id_bypass_src_0_3; // @[RocketCore.scala:461:74, :568:48] wire [1:0] _bypass_src_T = {1'h1, ~id_bypass_src_0_2}; // @[Mux.scala:50:70] wire [1:0] _bypass_src_T_1 = id_bypass_src_0_1 ? 2'h1 : _bypass_src_T; // @[Mux.scala:50:70] wire [1:0] bypass_src = id_bypass_src_0_0 ? 2'h0 : _bypass_src_T_1; // @[Mux.scala:50:70] wire [1:0] _ex_reg_rs_lsb_0_T = id_rs_0[1:0]; // @[RocketCore.scala:573:37, :1325:26] wire [61:0] _ex_reg_rs_msb_0_T = id_rs_0[63:2]; // @[RocketCore.scala:574:38, :1325:26] wire _do_bypass_T_2 = id_bypass_src_1_0 \| id_bypass_src_1_1; // @[RocketCore.scala:461:74, :568:48] wire _do_bypass_T_3 = _do_bypass_T_2 \| id_bypass_src_1_2; // @[RocketCore.scala:461:74, :568:48] wire do_bypass_1 = _do_bypass_T_3 \| id_bypass_src_1_3; // @[RocketCore.scala:461:74, :568:48] wire [1:0] _bypass_src_T_2 = {1'h1, ~id_bypass_src_1_2}; // @[Mux.scala:50:70] wire [1:0] _bypass_src_T_3 = id_bypass_src_1_1 ? 2'h1 : _bypass_src_T_2; // @[Mux.scala:50:70] wire [1:0] bypass_src_1 = id_bypass_src_1_0 ? 2'h0 : _bypass_src_T_3; // @[Mux.scala:50:70] wire [1:0] _ex_reg_rs_lsb_1_T = id_rs_1[1:0]; // @[RocketCore.scala:573:37, :1325:26] wire [61:0] _ex_reg_rs_msb_1_T = id_rs_1[63:2]; // @[RocketCore.scala:574:38, :1325:26] wire [15:0] _inst_T = _ibuf_io_inst_0_bits_raw[15:0]; // @[RocketCore.scala:311:20, :578:62] wire [31:0] inst = _ibuf_io_inst_0_bits_rvc ? {16'h0, _inst_T} : _ibuf_io_inst_0_bits_raw; // @[RocketCore.scala:311:20, :578:{21,62}] wire [1:0] _ex_reg_rs_lsb_0_T_1 = inst[1:0]; // @[RocketCore.scala:578:21, :580:31] wire [29:0] _ex_reg_rs_msb_0_T_1 = inst[31:2]; // @[RocketCore.scala:578:21, :581:32] wire _ex_reg_set_vconfig_T = ~id_xcpt; // @[RocketCore.scala:591:45, :1278:14] wire _ex_pc_valid_T = ex_reg_valid \| ex_reg_replay; // @[RocketCore.scala:248:35, :255:26, :595:34] wire ex_pc_valid = _ex_pc_valid_T \| ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35, :595:{34,51}] wire _wb_dcache_miss_T = ~io_dmem_resp_valid_0; // @[RocketCore.scala:153:7, :596:39] wire wb_dcache_miss = wb_ctrl_mem & _wb_dcache_miss_T; // @[RocketCore.scala:245:20, :596:{36,39}] wire _replay_ex_structural_T = ~io_dmem_req_ready_0; // @[RocketCore.scala:153:7, :597:45] wire _replay_ex_structural_T_1 = ex_ctrl_mem & _replay_ex_structural_T; // @[RocketCore.scala:243:20, :597:{42,45}] wire _replay_ex_structural_T_2 = ~_div_io_req_ready; // @[RocketCore.scala:511:19, :598:45] wire _replay_ex_structural_T_3 = ex_ctrl_div & _replay_ex_structural_T_2; // @[RocketCore.scala:243:20, :598:{42,45}] wire _replay_ex_structural_T_4 = _replay_ex_structural_T_1 \| _replay_ex_structural_T_3; // @[RocketCore.scala:597:{42,64}, :598:42] wire replay_ex_structural = _replay_ex_structural_T_4; // @[RocketCore.scala:597:64, :598:63] wire replay_ex_load_use = wb_dcache_miss & ex_reg_load_use; // @[RocketCore.scala:253:35, :596:36, :600:43] wire _replay_ex_T = replay_ex_structural \| replay_ex_load_use; // @[RocketCore.scala:598:63, :600:43, :601:75] wire _replay_ex_T_1 = ex_reg_valid & _replay_ex_T; // @[RocketCore.scala:248:35, :601:{50,75}] wire replay_ex = ex_reg_replay \| _replay_ex_T_1; // @[RocketCore.scala:255:26, :601:{33,50}] wire _ctrl_killx_T = take_pc_mem_wb \| replay_ex; // @[RocketCore.scala:307:35, :601:33, :602:35] wire _ctrl_killx_T_1 = ~ex_reg_valid; // @[RocketCore.scala:248:35, :602:51] assign ctrl_killx = _ctrl_killx_T \| _ctrl_killx_T_1; // @[RocketCore.scala:602:{35,48,51}] assign io_fpu_killx_0 = ctrl_killx; // @[RocketCore.scala:153:7, :602:48] wire _GEN_47 = ex_ctrl_mem_cmd == 5'h7; // @[RocketCore.scala:243:20, :604:40] wire _ex_slow_bypass_T; // @[RocketCore.scala:604:40] assign _ex_slow_bypass_T = _GEN_47; // @[RocketCore.scala:604:40] wire _mem_reg_load_T_3; // @[package.scala:16:47] assign _mem_reg_load_T_3 = _GEN_47; // @[package.scala:16:47] wire _mem_reg_store_T_3; // @[Consts.scala:90:66] assign _mem_reg_store_T_3 = _GEN_47; // @[RocketCore.scala:604:40] wire _io_dmem_req_bits_no_resp_T_3; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_3 = _GEN_47; // @[package.scala:16:47] wire _ex_slow_bypass_T_1 = ~(ex_reg_mem_size[1]); // @[RocketCore.scala:257:28, :604:69] wire ex_slow_bypass = _ex_slow_bypass_T \| _ex_slow_bypass_T_1; // @[RocketCore.scala:604:{40,50,69}] wire _ex_sfence_T_1 = ex_ctrl_mem_cmd == 5'h14; // @[RocketCore.scala:243:20, :605:64] wire _ex_sfence_T_2 = ex_ctrl_mem_cmd == 5'h15; // @[RocketCore.scala:243:20, :605:96] wire _ex_sfence_T_3 = _ex_sfence_T_1 \| _ex_sfence_T_2; // @[RocketCore.scala:605:{64,77,96}] wire _ex_sfence_T_4 = ex_ctrl_mem_cmd == 5'h16; // @[RocketCore.scala:243:20, :605:129] wire _ex_sfence_T_5 = _ex_sfence_T_3 \| _ex_sfence_T_4; // @[RocketCore.scala:605:{77,110,129}] wire ex_sfence = _ex_sfence_T & _ex_sfence_T_5; // @[RocketCore.scala:605:{29,44,110}] wire ex_xcpt = ex_reg_xcpt_interrupt \| ex_reg_xcpt; // @[RocketCore.scala:247:35, :251:35, :608:28, :1278:14] wire _mem_pc_valid_T = mem_reg_valid \| mem_reg_replay; // @[RocketCore.scala:265:36, :269:36, :614:36] wire mem_pc_valid = _mem_pc_valid_T \| mem_reg_xcpt_interrupt; // @[RocketCore.scala:264:36, :614:{36,54}] wire _GEN_48 = mem_ctrl_branch & mem_br_taken; // @[RocketCore.scala:244:21, :284:25, :616:25] wire _mem_br_target_T_1; // @[RocketCore.scala:616:25] assign _mem_br_target_T_1 = _GEN_48; // @[RocketCore.scala:616:25] wire _mem_cfi_taken_T; // @[RocketCore.scala:626:40] assign _mem_cfi_taken_T = _GEN_48; // @[RocketCore.scala:616:25, :626:40] wire _mem_br_target_sign_T_1 = mem_reg_inst[31]; // @[RocketCore.scala:278:25, :1341:44] wire _mem_br_target_sign_T_4 = mem_reg_inst[31]; // @[RocketCore.scala:278:25, :1341:44] wire _mem_br_target_sign_T_2 = _mem_br_target_sign_T_1; // @[RocketCore.scala:1341:{44,49}] wire mem_br_target_sign = _mem_br_target_sign_T_2; // @[RocketCore.scala:1341:{19,49}] wire mem_br_target_hi_hi_hi = mem_br_target_sign; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _mem_br_target_b30_20_T_1 = mem_reg_inst[30:20]; // @[RocketCore.scala:278:25, :1342:41] wire [10:0] _mem_br_target_b30_20_T_4 = mem_reg_inst[30:20]; // @[RocketCore.scala:278:25, :1342:41] wire [10:0] _mem_br_target_b30_20_T_2 = _mem_br_target_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}] wire [10:0] mem_br_target_b30_20 = {11{mem_br_target_sign}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] mem_br_target_hi_hi_lo = mem_br_target_b30_20; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _mem_br_target_b19_12_T_3 = mem_reg_inst[19:12]; // @[RocketCore.scala:278:25, :1343:65] wire [7:0] _mem_br_target_b19_12_T_8 = mem_reg_inst[19:12]; // @[RocketCore.scala:278:25, :1343:65] wire [7:0] _mem_br_target_b19_12_T_4 = _mem_br_target_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}] wire [7:0] mem_br_target_b19_12 = {8{mem_br_target_sign}}; // @[RocketCore.scala:1341:19, :1343:21] wire [7:0] mem_br_target_hi_lo_hi = mem_br_target_b19_12; // @[RocketCore.scala:1343:21, :1355:8] wire _mem_br_target_b11_T_4 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39] wire _mem_br_target_b0_T_3 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39, :1352:37] wire _mem_br_target_b11_T_15 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39] wire _mem_br_target_b0_T_11 = mem_reg_inst[20]; // @[RocketCore.scala:278:25, :1345:39, :1352:37] wire _mem_br_target_b11_T_5 = _mem_br_target_b11_T_4; // @[RocketCore.scala:1345:{39,44}] wire _mem_br_target_b11_T_7 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39] wire _mem_br_target_b0_T_1 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39, :1351:37] wire _mem_br_target_b11_T_18 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39] wire _mem_br_target_b0_T_9 = mem_reg_inst[7]; // @[RocketCore.scala:278:25, :1346:39, :1351:37] wire _mem_br_target_b11_T_8 = _mem_br_target_b11_T_7; // @[RocketCore.scala:1346:{39,43}] wire _mem_br_target_b11_T_9 = _mem_br_target_b11_T_8; // @[RocketCore.scala:1346:{18,43}] wire _mem_br_target_b11_T_10 = _mem_br_target_b11_T_9; // @[RocketCore.scala:1345:18, :1346:18] wire mem_br_target_b11 = _mem_br_target_b11_T_10; // @[RocketCore.scala:1344:18, :1345:18] wire mem_br_target_hi_lo_lo = mem_br_target_b11; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] _mem_br_target_b10_5_T_3 = mem_reg_inst[30:25]; // @[RocketCore.scala:278:25, :1347:62] wire [5:0] _mem_br_target_b10_5_T_7 = mem_reg_inst[30:25]; // @[RocketCore.scala:278:25, :1347:62] wire [5:0] mem_br_target_b10_5 = _mem_br_target_b10_5_T_3; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _mem_br_target_b4_1_T_4 = mem_reg_inst[11:8]; // @[RocketCore.scala:278:25, :1349:57] wire [3:0] _mem_br_target_b4_1_T_14 = mem_reg_inst[11:8]; // @[RocketCore.scala:278:25, :1349:57] wire [3:0] _mem_br_target_b4_1_T_9 = _mem_br_target_b4_1_T_4; // @[RocketCore.scala:1349:{19,57}] wire [3:0] _mem_br_target_b4_1_T_6 = mem_reg_inst[19:16]; // @[RocketCore.scala:278:25, :1350:39] wire [3:0] _mem_br_target_b4_1_T_16 = mem_reg_inst[19:16]; // @[RocketCore.scala:278:25, :1350:39] wire [3:0] _mem_br_target_b4_1_T_7 = mem_reg_inst[24:21]; // @[RocketCore.scala:278:25, :1350:52] wire [3:0] _mem_br_target_b4_1_T_17 = mem_reg_inst[24:21]; // @[RocketCore.scala:278:25, :1350:52] wire [3:0] _mem_br_target_b4_1_T_8 = _mem_br_target_b4_1_T_7; // @[RocketCore.scala:1350:{19,52}] wire [3:0] mem_br_target_b4_1 = _mem_br_target_b4_1_T_9; // @[RocketCore.scala:1348:19, :1349:19] wire _mem_br_target_b0_T_5 = mem_reg_inst[15]; // @[RocketCore.scala:278:25, :1353:37] wire _mem_br_target_b0_T_13 = mem_reg_inst[15]; // @[RocketCore.scala:278:25, :1353:37] wire [9:0] mem_br_target_lo_hi = {mem_br_target_b10_5, mem_br_target_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] mem_br_target_lo = {mem_br_target_lo_hi, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] mem_br_target_hi_lo = {mem_br_target_hi_lo_hi, mem_br_target_hi_lo_lo}; // @[RocketCore.scala:1355:8] wire [11:0] mem_br_target_hi_hi = {mem_br_target_hi_hi_hi, mem_br_target_hi_hi_lo}; // @[RocketCore.scala:1355:8] wire [20:0] mem_br_target_hi = {mem_br_target_hi_hi, mem_br_target_hi_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_br_target_T_2 = {mem_br_target_hi, mem_br_target_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_br_target_T_3 = _mem_br_target_T_2; // @[RocketCore.scala:1355:{8,53}] wire _mem_br_target_sign_T_5 = _mem_br_target_sign_T_4; // @[RocketCore.scala:1341:{44,49}] wire mem_br_target_sign_1 = _mem_br_target_sign_T_5; // @[RocketCore.scala:1341:{19,49}] wire _mem_br_target_b11_T_20 = mem_br_target_sign_1; // @[RocketCore.scala:1341:19, :1346:18] wire mem_br_target_hi_hi_hi_1 = mem_br_target_sign_1; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _mem_br_target_b30_20_T_5 = _mem_br_target_b30_20_T_4; // @[RocketCore.scala:1342:{41,49}] wire [10:0] mem_br_target_b30_20_1 = {11{mem_br_target_sign_1}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] mem_br_target_hi_hi_lo_1 = mem_br_target_b30_20_1; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _mem_br_target_b19_12_T_9 = _mem_br_target_b19_12_T_8; // @[RocketCore.scala:1343:{65,73}] wire [7:0] mem_br_target_b19_12_1 = _mem_br_target_b19_12_T_9; // @[RocketCore.scala:1343:{21,73}] wire [7:0] mem_br_target_hi_lo_hi_1 = mem_br_target_b19_12_1; // @[RocketCore.scala:1343:21, :1355:8] wire _mem_br_target_b11_T_16 = _mem_br_target_b11_T_15; // @[RocketCore.scala:1345:{39,44}] wire _mem_br_target_b11_T_21 = _mem_br_target_b11_T_16; // @[RocketCore.scala:1345:{18,44}] wire _mem_br_target_b11_T_19 = _mem_br_target_b11_T_18; // @[RocketCore.scala:1346:{39,43}] wire mem_br_target_b11_1 = _mem_br_target_b11_T_21; // @[RocketCore.scala:1344:18, :1345:18] wire mem_br_target_hi_lo_lo_1 = mem_br_target_b11_1; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] mem_br_target_b10_5_1 = _mem_br_target_b10_5_T_7; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _mem_br_target_b4_1_T_18 = _mem_br_target_b4_1_T_17; // @[RocketCore.scala:1350:{19,52}] wire [3:0] _mem_br_target_b4_1_T_19 = _mem_br_target_b4_1_T_18; // @[RocketCore.scala:1349:19, :1350:19] wire [3:0] mem_br_target_b4_1_1 = _mem_br_target_b4_1_T_19; // @[RocketCore.scala:1348:19, :1349:19] wire [9:0] mem_br_target_lo_hi_1 = {mem_br_target_b10_5_1, mem_br_target_b4_1_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] mem_br_target_lo_1 = {mem_br_target_lo_hi_1, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] mem_br_target_hi_lo_1 = {mem_br_target_hi_lo_hi_1, mem_br_target_hi_lo_lo_1}; // @[RocketCore.scala:1355:8] wire [11:0] mem_br_target_hi_hi_1 = {mem_br_target_hi_hi_hi_1, mem_br_target_hi_hi_lo_1}; // @[RocketCore.scala:1355:8] wire [20:0] mem_br_target_hi_1 = {mem_br_target_hi_hi_1, mem_br_target_hi_lo_1}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_br_target_T_4 = {mem_br_target_hi_1, mem_br_target_lo_1}; // @[RocketCore.scala:1355:8] wire [31:0] _mem_br_target_T_5 = _mem_br_target_T_4; // @[RocketCore.scala:1355:{8,53}] wire [3:0] _mem_br_target_T_6 = mem_reg_rvc ? 4'h2 : 4'h4; // @[RocketCore.scala:266:36, :618:8] wire [31:0] _mem_br_target_T_7 = mem_ctrl_jal ? _mem_br_target_T_5 : {{28{_mem_br_target_T_6[3]}}, _mem_br_target_T_6}; // @[RocketCore.scala:244:21, :617:8, :618:8, :1355:53] wire [31:0] _mem_br_target_T_8 = _mem_br_target_T_1 ? _mem_br_target_T_3 : _mem_br_target_T_7; // @[RocketCore.scala:616:{8,25}, :617:8, :1355:53] wire [40:0] _mem_br_target_T_9 = {_mem_br_target_T[39], _mem_br_target_T} + {{9{_mem_br_target_T_8[31]}}, _mem_br_target_T_8}; // @[RocketCore.scala:615:{34,41}, :616:8] wire [39:0] _mem_br_target_T_10 = _mem_br_target_T_9[39:0]; // @[RocketCore.scala:615:41] wire [39:0] mem_br_target = _mem_br_target_T_10; // @[RocketCore.scala:615:41] wire _mem_npc_T = mem_ctrl_jalr \| mem_reg_sfence; // @[RocketCore.scala:244:21, :276:27, :619:36] wire [24:0] _mem_npc_a_T = mem_reg_wdata[63:39]; // @[RocketCore.scala:282:26, :1293:17] wire [24:0] mem_npc_a = _mem_npc_a_T; // @[RocketCore.scala:1293:{17,23}] wire _mem_npc_msb_T = mem_npc_a == 25'h0; // @[RocketCore.scala:1293:23, :1294:21] wire _mem_npc_msb_T_1 = &mem_npc_a; // @[RocketCore.scala:1293:23, :1294:34] wire _mem_npc_msb_T_2 = _mem_npc_msb_T \| _mem_npc_msb_T_1; // @[RocketCore.scala:1294:{21,29,34}] wire _mem_npc_msb_T_3 = mem_reg_wdata[39]; // @[RocketCore.scala:282:26, :1294:46] wire _mem_npc_msb_T_4 = mem_reg_wdata[38]; // @[RocketCore.scala:282:26, :1294:54] wire _mem_npc_msb_T_5 = ~_mem_npc_msb_T_4; // @[RocketCore.scala:1294:{51,54}] wire mem_npc_msb = _mem_npc_msb_T_2 ? _mem_npc_msb_T_3 : _mem_npc_msb_T_5; // @[RocketCore.scala:1294:{18,29,46,51}] wire [39:0] _mem_npc_T_2 = {mem_npc_msb, _mem_npc_T_1}; // @[RocketCore.scala:1294:18, :1295:{8,16}] wire [39:0] _mem_npc_T_3 = _mem_npc_T_2; // @[RocketCore.scala:619:106, :1295:8] wire [39:0] _mem_npc_T_4 = _mem_npc_T ? _mem_npc_T_3 : mem_br_target; // @[RocketCore.scala:615:41, :619:{21,36,106}] wire [39:0] _mem_npc_T_5 = _mem_npc_T_4 & 40'hFFFFFFFFFE; // @[RocketCore.scala:619:{21,129}] wire [39:0] _mem_npc_T_6 = _mem_npc_T_5; // @[RocketCore.scala:619:129] wire [39:0] mem_npc = _mem_npc_T_6; // @[RocketCore.scala:619:{129,139}] wire _mem_wrong_npc_T = mem_npc != ex_reg_pc; // @[RocketCore.scala:256:22, :619:139, :621:30] wire _mem_wrong_npc_T_1 = _ibuf_io_inst_0_valid \| io_imem_resp_valid_0; // @[RocketCore.scala:153:7, :311:20, :622:31] wire _mem_wrong_npc_T_2 = mem_npc != _ibuf_io_pc; // @[RocketCore.scala:311:20, :619:139, :622:62] wire _mem_wrong_npc_T_3 = ~_mem_wrong_npc_T_1 \| _mem_wrong_npc_T_2; // @[RocketCore.scala:622:{8,31,62}] assign mem_wrong_npc = ex_pc_valid ? _mem_wrong_npc_T : _mem_wrong_npc_T_3; // @[RocketCore.scala:595:51, :621:{8,30}, :622:8] assign io_imem_bht_update_bits_mispredict_0 = mem_wrong_npc; // @[RocketCore.scala:153:7, :621:8] wire _mem_npc_misaligned_T_1 = ~_mem_npc_misaligned_T; // @[RocketCore.scala:623:{28,46}] wire _mem_npc_misaligned_T_2 = mem_npc[1]; // @[RocketCore.scala:619:139, :623:66] wire _mem_npc_misaligned_T_3 = _mem_npc_misaligned_T_1 & _mem_npc_misaligned_T_2; // @[RocketCore.scala:623:{28,56,66}] wire _mem_npc_misaligned_T_4 = ~mem_reg_sfence; // @[RocketCore.scala:276:27, :623:73] wire mem_npc_misaligned = _mem_npc_misaligned_T_3 & _mem_npc_misaligned_T_4; // @[RocketCore.scala:623:{56,70,73}] wire _mem_int_wdata_T = ~mem_reg_xcpt; // @[RocketCore.scala:268:36, :624:27] wire _mem_int_wdata_T_1 = mem_ctrl_jalr ^ mem_npc_misaligned; // @[RocketCore.scala:244:21, :623:70, :624:59] wire _mem_int_wdata_T_2 = _mem_int_wdata_T & _mem_int_wdata_T_1; // @[RocketCore.scala:624:{27,41,59}] wire [63:0] _mem_int_wdata_T_4 = _mem_int_wdata_T_2 ? {{24{mem_br_target[39]}}, mem_br_target} : _mem_int_wdata_T_3; // @[RocketCore.scala:615:41, :624:{26,41,111}] wire [63:0] mem_int_wdata = _mem_int_wdata_T_4; // @[RocketCore.scala:624:{26,119}] wire _mem_cfi_T = mem_ctrl_branch \| mem_ctrl_jalr; // @[RocketCore.scala:244:21, :625:33] assign mem_cfi = _mem_cfi_T \| mem_ctrl_jal; // @[RocketCore.scala:244:21, :625:{33,50}] assign io_imem_btb_update_bits_isValid_0 = mem_cfi; // @[RocketCore.scala:153:7, :625:50] wire _mem_cfi_taken_T_1 = _mem_cfi_taken_T \| mem_ctrl_jalr; // @[RocketCore.scala:244:21, :626:{40,57}] wire mem_cfi_taken = _mem_cfi_taken_T_1 \| mem_ctrl_jal; // @[RocketCore.scala:244:21, :626:{57,74}] wire _mem_direction_misprediction_T_1 = mem_br_taken != _mem_direction_misprediction_T; // @[RocketCore.scala:284:25, :627:{69,85}] wire mem_direction_misprediction = mem_ctrl_branch & _mem_direction_misprediction_T_1; // @[RocketCore.scala:244:21, :627:{53,69}] wire _take_pc_mem_T = ~mem_reg_xcpt; // @[RocketCore.scala:268:36, :624:27, :629:35] wire _take_pc_mem_T_1 = mem_reg_valid & _take_pc_mem_T; // @[RocketCore.scala:265:36, :629:{32,35}] wire _take_pc_mem_T_2 = mem_wrong_npc \| mem_reg_sfence; // @[RocketCore.scala:276:27, :621:8, :629:71] assign _take_pc_mem_T_3 = _take_pc_mem_T_1 & _take_pc_mem_T_2; // @[RocketCore.scala:629:{32,49,71}] assign take_pc_mem = _take_pc_mem_T_3; // @[RocketCore.scala:285:25, :629:49] wire _mem_reg_valid_T = ~ctrl_killx; // @[RocketCore.scala:602:48, :631:20] wire _mem_reg_replay_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20, :632:21] wire _mem_reg_replay_T_1 = _mem_reg_replay_T & replay_ex; // @[RocketCore.scala:601:33, :632:{21,37}] wire _mem_reg_xcpt_T = ~ctrl_killx; // @[RocketCore.scala:602:48, :631:20, :633:19] wire _mem_reg_xcpt_T_1 = _mem_reg_xcpt_T & ex_xcpt; // @[RocketCore.scala:633:{19,31}, :1278:14] wire _mem_reg_xcpt_interrupt_T = ~take_pc_mem_wb; // @[RocketCore.scala:307:35, :526:20, :634:29] wire _mem_reg_xcpt_interrupt_T_1 = _mem_reg_xcpt_interrupt_T & ex_reg_xcpt_interrupt; // @[RocketCore.scala:247:35, :634:{29,45}] wire _GEN_49 = ex_ctrl_mem_cmd == 5'h0; // @[package.scala:16:47] wire _mem_reg_load_T; // @[package.scala:16:47] assign _mem_reg_load_T = _GEN_49; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T = _GEN_49; // @[package.scala:16:47] wire _GEN_50 = ex_ctrl_mem_cmd == 5'h10; // @[package.scala:16:47] wire _mem_reg_load_T_1; // @[package.scala:16:47] assign _mem_reg_load_T_1 = _GEN_50; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_1; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_1 = _GEN_50; // @[package.scala:16:47] wire _GEN_51 = ex_ctrl_mem_cmd == 5'h6; // @[package.scala:16:47] wire _mem_reg_load_T_2; // @[package.scala:16:47] assign _mem_reg_load_T_2 = _GEN_51; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_2; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_2 = _GEN_51; // @[package.scala:16:47] wire _mem_reg_load_T_4 = _mem_reg_load_T \| _mem_reg_load_T_1; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_5 = _mem_reg_load_T_4 \| _mem_reg_load_T_2; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_6 = _mem_reg_load_T_5 \| _mem_reg_load_T_3; // @[package.scala:16:47, :81:59] wire _GEN_52 = ex_ctrl_mem_cmd == 5'h4; // @[package.scala:16:47] wire _mem_reg_load_T_7; // @[package.scala:16:47] assign _mem_reg_load_T_7 = _GEN_52; // @[package.scala:16:47] wire _mem_reg_store_T_5; // @[package.scala:16:47] assign _mem_reg_store_T_5 = _GEN_52; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_7; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_7 = _GEN_52; // @[package.scala:16:47] wire _GEN_53 = ex_ctrl_mem_cmd == 5'h9; // @[package.scala:16:47] wire _mem_reg_load_T_8; // @[package.scala:16:47] assign _mem_reg_load_T_8 = _GEN_53; // @[package.scala:16:47] wire _mem_reg_store_T_6; // @[package.scala:16:47] assign _mem_reg_store_T_6 = _GEN_53; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_8; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_8 = _GEN_53; // @[package.scala:16:47] wire _GEN_54 = ex_ctrl_mem_cmd == 5'hA; // @[package.scala:16:47] wire _mem_reg_load_T_9; // @[package.scala:16:47] assign _mem_reg_load_T_9 = _GEN_54; // @[package.scala:16:47] wire _mem_reg_store_T_7; // @[package.scala:16:47] assign _mem_reg_store_T_7 = _GEN_54; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_9; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_9 = _GEN_54; // @[package.scala:16:47] wire _GEN_55 = ex_ctrl_mem_cmd == 5'hB; // @[package.scala:16:47] wire _mem_reg_load_T_10; // @[package.scala:16:47] assign _mem_reg_load_T_10 = _GEN_55; // @[package.scala:16:47] wire _mem_reg_store_T_8; // @[package.scala:16:47] assign _mem_reg_store_T_8 = _GEN_55; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_10; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_10 = _GEN_55; // @[package.scala:16:47] wire _mem_reg_load_T_11 = _mem_reg_load_T_7 \| _mem_reg_load_T_8; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_12 = _mem_reg_load_T_11 \| _mem_reg_load_T_9; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_13 = _mem_reg_load_T_12 \| _mem_reg_load_T_10; // @[package.scala:16:47, :81:59] wire _GEN_56 = ex_ctrl_mem_cmd == 5'h8; // @[package.scala:16:47] wire _mem_reg_load_T_14; // @[package.scala:16:47] assign _mem_reg_load_T_14 = _GEN_56; // @[package.scala:16:47] wire _mem_reg_store_T_12; // @[package.scala:16:47] assign _mem_reg_store_T_12 = _GEN_56; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_14; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_14 = _GEN_56; // @[package.scala:16:47] wire _GEN_57 = ex_ctrl_mem_cmd == 5'hC; // @[package.scala:16:47] wire _mem_reg_load_T_15; // @[package.scala:16:47] assign _mem_reg_load_T_15 = _GEN_57; // @[package.scala:16:47] wire _mem_reg_store_T_13; // @[package.scala:16:47] assign _mem_reg_store_T_13 = _GEN_57; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_15; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_15 = _GEN_57; // @[package.scala:16:47] wire _GEN_58 = ex_ctrl_mem_cmd == 5'hD; // @[package.scala:16:47] wire _mem_reg_load_T_16; // @[package.scala:16:47] assign _mem_reg_load_T_16 = _GEN_58; // @[package.scala:16:47] wire _mem_reg_store_T_14; // @[package.scala:16:47] assign _mem_reg_store_T_14 = _GEN_58; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_16; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_16 = _GEN_58; // @[package.scala:16:47] wire _GEN_59 = ex_ctrl_mem_cmd == 5'hE; // @[package.scala:16:47] wire _mem_reg_load_T_17; // @[package.scala:16:47] assign _mem_reg_load_T_17 = _GEN_59; // @[package.scala:16:47] wire _mem_reg_store_T_15; // @[package.scala:16:47] assign _mem_reg_store_T_15 = _GEN_59; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_17; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_17 = _GEN_59; // @[package.scala:16:47] wire _GEN_60 = ex_ctrl_mem_cmd == 5'hF; // @[package.scala:16:47] wire _mem_reg_load_T_18; // @[package.scala:16:47] assign _mem_reg_load_T_18 = _GEN_60; // @[package.scala:16:47] wire _mem_reg_store_T_16; // @[package.scala:16:47] assign _mem_reg_store_T_16 = _GEN_60; // @[package.scala:16:47] wire _io_dmem_req_bits_no_resp_T_18; // @[package.scala:16:47] assign _io_dmem_req_bits_no_resp_T_18 = _GEN_60; // @[package.scala:16:47] wire _mem_reg_load_T_19 = _mem_reg_load_T_14 \| _mem_reg_load_T_15; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_20 = _mem_reg_load_T_19 \| _mem_reg_load_T_16; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_21 = _mem_reg_load_T_20 \| _mem_reg_load_T_17; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_22 = _mem_reg_load_T_21 \| _mem_reg_load_T_18; // @[package.scala:16:47, :81:59] wire _mem_reg_load_T_23 = _mem_reg_load_T_13 \| _mem_reg_load_T_22; // @[package.scala:81:59] wire _mem_reg_load_T_24 = _mem_reg_load_T_6 \| _mem_reg_load_T_23; // @[package.scala:81:59] wire _mem_reg_load_T_25 = ex_ctrl_mem & _mem_reg_load_T_24; // @[RocketCore.scala:243:20, :643:33] wire _mem_reg_store_T = ex_ctrl_mem_cmd == 5'h1; // @[RocketCore.scala:243:20] wire _mem_reg_store_T_1 = ex_ctrl_mem_cmd == 5'h11; // @[RocketCore.scala:243:20] wire _mem_reg_store_T_2 = _mem_reg_store_T \| _mem_reg_store_T_1; // @[Consts.scala:90:{32,42,49}] wire _mem_reg_store_T_4 = _mem_reg_store_T_2 \| _mem_reg_store_T_3; // @[Consts.scala:90:{42,59,66}] wire _mem_reg_store_T_9 = _mem_reg_store_T_5 \| _mem_reg_store_T_6; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_10 = _mem_reg_store_T_9 \| _mem_reg_store_T_7; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_11 = _mem_reg_store_T_10 \| _mem_reg_store_T_8; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_17 = _mem_reg_store_T_12 \| _mem_reg_store_T_13; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_18 = _mem_reg_store_T_17 \| _mem_reg_store_T_14; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_19 = _mem_reg_store_T_18 \| _mem_reg_store_T_15; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_20 = _mem_reg_store_T_19 \| _mem_reg_store_T_16; // @[package.scala:16:47, :81:59] wire _mem_reg_store_T_21 = _mem_reg_store_T_11 \| _mem_reg_store_T_20; // @[package.scala:81:59] wire _mem_reg_store_T_22 = _mem_reg_store_T_4 \| _mem_reg_store_T_21; // @[Consts.scala:87:44, :90:{59,76}] wire _mem_reg_store_T_23 = ex_ctrl_mem & _mem_reg_store_T_22; // @[RocketCore.scala:243:20, :644:34] wire [1:0] size = ex_ctrl_rocc ? 2'h3 : ex_reg_mem_size; // @[RocketCore.scala:243:20, :257:28, :664:21] wire [1:0] mem_reg_rs2_size = size; // @[RocketCore.scala:664:21] wire _mem_reg_rs2_T = mem_reg_rs2_size == 2'h0; // @[AMOALU.scala:11:18, :29:19] wire [7:0] _mem_reg_rs2_T_1 = mem_reg_rs2_dat_padded[7:0]; // @[AMOALU.scala:13:27, :29:69] wire [15:0] _mem_reg_rs2_T_2 = {2{_mem_reg_rs2_T_1}}; // @[AMOALU.scala:29:{32,69}] wire [31:0] _mem_reg_rs2_T_3 = {2{_mem_reg_rs2_T_2}}; // @[AMOALU.scala:29:32] wire [63:0] _mem_reg_rs2_T_4 = {2{_mem_reg_rs2_T_3}}; // @[AMOALU.scala:29:32] wire _mem_reg_rs2_T_5 = mem_reg_rs2_size == 2'h1; // @[AMOALU.scala:11:18, :29:19] wire [15:0] _mem_reg_rs2_T_6 = mem_reg_rs2_dat_padded[15:0]; // @[AMOALU.scala:13:27, :29:69] wire [31:0] _mem_reg_rs2_T_7 = {2{_mem_reg_rs2_T_6}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _mem_reg_rs2_T_8 = {2{_mem_reg_rs2_T_7}}; // @[AMOALU.scala:29:32] wire _mem_reg_rs2_T_9 = mem_reg_rs2_size == 2'h2; // @[AMOALU.scala:11:18, :29:19] wire [31:0] _mem_reg_rs2_T_10 = mem_reg_rs2_dat_padded[31:0]; // @[AMOALU.scala:13:27, :29:69] wire [63:0] _mem_reg_rs2_T_11 = {2{_mem_reg_rs2_T_10}}; // @[AMOALU.scala:29:{32,69}] wire [63:0] _mem_reg_rs2_T_12 = _mem_reg_rs2_T_9 ? _mem_reg_rs2_T_11 : mem_reg_rs2_dat_padded; // @[AMOALU.scala:13:27, :29:{13,19,32}] wire [63:0] _mem_reg_rs2_T_13 = _mem_reg_rs2_T_5 ? _mem_reg_rs2_T_8 : _mem_reg_rs2_T_12; // @[AMOALU.scala:29:{13,19,32}] wire [63:0] _mem_reg_rs2_T_14 = _mem_reg_rs2_T ? _mem_reg_rs2_T_4 : _mem_reg_rs2_T_13; // @[AMOALU.scala:29:{13,19,32}] wire _mem_breakpoint_T = mem_reg_load & _bpu_io_xcpt_ld; // @[RocketCore.scala:273:36, :414:19, :677:38] wire _mem_breakpoint_T_1 = mem_reg_store & _bpu_io_xcpt_st; // @[RocketCore.scala:274:36, :414:19, :677:75] wire mem_breakpoint = _mem_breakpoint_T \| _mem_breakpoint_T_1; // @[RocketCore.scala:677:{38,57,75}] wire _mem_debug_breakpoint_T = mem_reg_load & _bpu_io_debug_ld; // @[RocketCore.scala:273:36, :414:19, :678:44] wire _mem_debug_breakpoint_T_1 = mem_reg_store & _bpu_io_debug_st; // @[RocketCore.scala:274:36, :414:19, :678:82] wire mem_debug_breakpoint = _mem_debug_breakpoint_T \| _mem_debug_breakpoint_T_1; // @[RocketCore.scala:678:{44,64,82}] wire mem_ldst_xcpt = mem_debug_breakpoint \| mem_breakpoint; // @[RocketCore.scala:677:57, :678:64, :1278:{14,35}] wire [3:0] mem_ldst_cause = mem_debug_breakpoint ? 4'hE : 4'h3; // @[Mux.scala:50:70] wire _T_74 = mem_reg_xcpt_interrupt \| mem_reg_xcpt; // @[RocketCore.scala:264:36, :268:36, :684:29] wire _T_75 = mem_reg_valid & mem_npc_misaligned; // @[RocketCore.scala:265:36, :623:70, :685:20] wire mem_xcpt = _T_74 \| _T_75 \| mem_reg_valid & mem_ldst_xcpt; // @[RocketCore.scala:265:36, :684:29, :685:20, :686:20, :1278:{14,35}] wire [63:0] mem_cause = _T_74 ? mem_reg_cause : {60'h0, _T_75 ? 4'h0 : mem_ldst_cause}; // @[Mux.scala:50:70] wire dcache_kill_mem = _dcache_kill_mem_T & io_dmem_replay_next_0; // @[RocketCore.scala:153:7, :695:{39,55}] wire _fpu_kill_mem_T = mem_reg_valid & mem_ctrl_fp; // @[RocketCore.scala:244:21, :265:36, :696:36] wire fpu_kill_mem = _fpu_kill_mem_T & io_fpu_nack_mem_0; // @[RocketCore.scala:153:7, :696:{36,51}] wire _vec_kill_mem_T = mem_reg_valid & mem_ctrl_mem; // @[RocketCore.scala:244:21, :265:36, :697:36] wire _replay_mem_T = dcache_kill_mem \| mem_reg_replay; // @[RocketCore.scala:269:36, :695:55, :699:37] wire _replay_mem_T_1 = _replay_mem_T \| fpu_kill_mem; // @[RocketCore.scala:696:51, :699:{37,55}] wire _replay_mem_T_2 = _replay_mem_T_1; // @[RocketCore.scala:699:{55,71}] wire replay_mem = _replay_mem_T_2; // @[RocketCore.scala:699:{71,87}] wire _killm_common_T = dcache_kill_mem \| take_pc_wb; // @[RocketCore.scala:304:24, :695:55, :700:38] wire _killm_common_T_1 = _killm_common_T \| mem_reg_xcpt; // @[RocketCore.scala:268:36, :700:{38,52}] wire _killm_common_T_2 = ~mem_reg_valid; // @[RocketCore.scala:265:36, :700:71] assign killm_common = _killm_common_T_1 \| _killm_common_T_2; // @[RocketCore.scala:700:{52,68,71}] assign io_fpu_killm_0 = killm_common; // @[RocketCore.scala:153:7, :700:68] wire _div_io_kill_T = _div_io_req_ready & _div_io_req_valid_T; // @[Decoupled.scala:51:35] reg div_io_kill_REG; // @[RocketCore.scala:701:41] wire _div_io_kill_T_1 = killm_common & div_io_kill_REG; // @[RocketCore.scala:700:68, :701:{31,41}] wire _ctrl_killm_T = killm_common \| mem_xcpt; // @[RocketCore.scala:700:68, :702:33, :1278:14] wire _ctrl_killm_T_1 = _ctrl_killm_T \| fpu_kill_mem; // @[RocketCore.scala:696:51, :702:{33,45}] wire ctrl_killm = _ctrl_killm_T_1; // @[RocketCore.scala:702:{45,61}] wire _wb_reg_valid_T = ~ctrl_killm; // @[RocketCore.scala:702:61, :705:19] wire _wb_reg_replay_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34] wire _wb_reg_replay_T_1 = replay_mem & _wb_reg_replay_T; // @[RocketCore.scala:699:87, :706:{31,34}] wire _wb_reg_xcpt_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :707:30] wire _wb_reg_xcpt_T_1 = mem_xcpt & _wb_reg_xcpt_T; // @[RocketCore.scala:707:{27,30}, :1278:14] wire _wb_reg_xcpt_T_3 = _wb_reg_xcpt_T_1; // @[RocketCore.scala:707:{27,42}] wire _wb_reg_flush_pipe_T = ~ctrl_killm; // @[RocketCore.scala:702:61, :705:19, :708:24] wire _wb_reg_flush_pipe_T_1 = _wb_reg_flush_pipe_T & mem_reg_flush_pipe; // @[RocketCore.scala:270:36, :708:{24,36}] wire _wb_reg_wdata_T = ~mem_reg_xcpt; // @[RocketCore.scala:268:36, :624:27, :712:25] wire _wb_reg_wdata_T_1 = _wb_reg_wdata_T & mem_ctrl_fp; // @[RocketCore.scala:244:21, :712:{25,39}] wire _wb_reg_wdata_T_2 = _wb_reg_wdata_T_1 & mem_ctrl_wxd; // @[RocketCore.scala:244:21, :712:{39,54}] wire [63:0] _wb_reg_wdata_T_3 = _wb_reg_wdata_T_2 ? io_fpu_toint_data_0 : mem_int_wdata; // @[RocketCore.scala:153:7, :624:119, :712:{24,54}] wire _wb_reg_hfence_v_T = mem_ctrl_mem_cmd == 5'h15; // @[RocketCore.scala:244:21, :721:41] wire _wb_reg_hfence_g_T = mem_ctrl_mem_cmd == 5'h16; // @[RocketCore.scala:244:21, :722:41] wire _T_113 = wb_reg_valid & wb_ctrl_mem; // @[RocketCore.scala:245:20, :288:35, :730:19] wire _T_100 = _T_113 & io_dmem_s2_xcpt_pf_st_0; // @[RocketCore.scala:153:7, :730:{19,34}] wire _T_102 = _T_113 & io_dmem_s2_xcpt_pf_ld_0; // @[RocketCore.scala:153:7, :730:19, :731:34] wire _T_108 = _T_113 & io_dmem_s2_xcpt_ae_st_0; // @[RocketCore.scala:153:7, :730:19, :734:34] wire _T_110 = _T_113 & io_dmem_s2_xcpt_ae_ld_0; // @[RocketCore.scala:153:7, :730:19, :735:34] wire _T_112 = _T_113 & io_dmem_s2_xcpt_ma_st_0; // @[RocketCore.scala:153:7, :730:19, :736:34] wire wb_xcpt = wb_reg_xcpt \| _T_100 \| _T_102 \| _T_108 \| _T_110 \| _T_112 \| _T_113 & io_dmem_s2_xcpt_ma_ld_0; // @[RocketCore.scala:153:7, :289:35, :730:{19,34}, :731:34, :734:34, :735:34, :736:34, :737:34, :1278:{14,35}] wire [63:0] wb_cause = wb_reg_xcpt ? wb_reg_cause : {59'h0, _T_100 ? 5'hF : _T_102 ? 5'hD : {2'h0, _T_108 ? 3'h7 : _T_110 ? 3'h5 : {1'h1, _T_112, 1'h0}}}; // @[Mux.scala:50:70] wire _wb_pc_valid_T = wb_reg_valid \| wb_reg_replay; // @[RocketCore.scala:288:35, :290:35, :754:34] wire wb_pc_valid = _wb_pc_valid_T \| wb_reg_xcpt; // @[RocketCore.scala:289:35, :754:{34,51}] wire wb_wxd = wb_reg_valid & wb_ctrl_wxd; // @[RocketCore.scala:245:20, :288:35, :755:29] wire _wb_set_sboard_T = wb_ctrl_div \| wb_dcache_miss; // @[RocketCore.scala:245:20, :596:36, :756:35] wire _wb_set_sboard_T_1 = _wb_set_sboard_T \| wb_ctrl_rocc; // @[RocketCore.scala:245:20, :756:{35,53}] wire wb_set_sboard = _wb_set_sboard_T_1 \| wb_ctrl_vec; // @[RocketCore.scala:245:20, :756:{53,69}] wire replay_wb_common = io_dmem_s2_nack_0 \| wb_reg_replay; // @[RocketCore.scala:153:7, :290:35, :757:42] wire replay_wb_rocc = _replay_wb_rocc_T; // @[RocketCore.scala:758:{37,53}] wire _replay_wb_T = replay_wb_common \| replay_wb_rocc; // @[RocketCore.scala:757:42, :758:53, :761:36] wire _replay_wb_T_1 = _replay_wb_T; // @[RocketCore.scala:761:{36,54}] wire replay_wb = _replay_wb_T_1; // @[RocketCore.scala:761:{54,71}] wire _take_pc_wb_T = replay_wb \| wb_xcpt; // @[RocketCore.scala:761:71, :762:27, :1278:14] wire _take_pc_wb_T_1 = _take_pc_wb_T \| _csr_io_eret; // @[RocketCore.scala:341:19, :762:{27,38}] assign _take_pc_wb_T_2 = _take_pc_wb_T_1 \| wb_reg_flush_pipe; // @[RocketCore.scala:291:35, :762:{38,53}] assign take_pc_wb = _take_pc_wb_T_2; // @[RocketCore.scala:304:24, :762:53] wire _dmem_resp_xpu_T = io_dmem_resp_bits_tag_0[0]; // @[RocketCore.scala:153:7, :765:45] wire dmem_resp_fpu = io_dmem_resp_bits_tag_0[0]; // @[RocketCore.scala:153:7, :765:45, :766:45] wire dmem_resp_xpu = ~_dmem_resp_xpu_T; // @[RocketCore.scala:765:{23,45}] assign dmem_resp_waddr = io_dmem_resp_bits_tag_0[5:1]; // @[RocketCore.scala:153:7, :767:46] assign io_fpu_ll_resp_tag_0 = dmem_resp_waddr; // @[RocketCore.scala:153:7, :767:46] wire dmem_resp_valid = io_dmem_resp_valid_0 & io_dmem_resp_bits_has_data_0; // @[RocketCore.scala:153:7, :768:44] wire dmem_resp_replay = dmem_resp_valid & io_dmem_resp_bits_replay_0; // @[RocketCore.scala:153:7, :768:44, :769:42] wire [63:0] ll_wdata; // @[RocketCore.scala:779:26] wire [4:0] ll_waddr; // @[RocketCore.scala:780:26] wire _ll_wen_T = ll_arb_io_out_ready & _ll_arb_io_out_valid; // @[Decoupled.scala:51:35] wire ll_wen; // @[RocketCore.scala:781:24] wire _ll_arb_io_out_ready_T = ~wb_wxd; // @[RocketCore.scala:755:29, :782:26] wire _T_143 = dmem_resp_replay & dmem_resp_xpu; // @[RocketCore.scala:765:23, :769:42, :809:26] assign ll_arb_io_out_ready = ~_T_143 & _ll_arb_io_out_ready_T; // @[RocketCore.scala:782:{23,26}, :809:{26,44}, :810:25] assign ll_waddr = _T_143 ? dmem_resp_waddr : _ll_arb_io_out_bits_tag; // @[RocketCore.scala:767:46, :776:22, :780:26, :809:{26,44}, :811:14] assign ll_wen = _T_143 \| _ll_wen_T; // @[Decoupled.scala:51:35] wire _wb_valid_T = ~replay_wb; // @[RocketCore.scala:761:71, :815:34] wire _wb_valid_T_1 = wb_reg_valid & _wb_valid_T; // @[RocketCore.scala:288:35, :815:{31,34}] wire _wb_valid_T_2 = ~wb_xcpt; // @[RocketCore.scala:815:48, :1278:14] wire wb_valid = _wb_valid_T_1 & _wb_valid_T_2; // @[RocketCore.scala:815:{31,45,48}] wire wb_wen = wb_valid & wb_ctrl_wxd; // @[RocketCore.scala:245:20, :815:45, :816:25] wire rf_wen = wb_wen \| ll_wen; // @[RocketCore.scala:781:24, :816:25, :817:23] wire [4:0] rf_waddr = ll_wen ? ll_waddr : wb_waddr; // @[RocketCore.scala:455:36, :780:26, :781:24, :818:21] wire [4:0] xrfWriteBundle_wrdst = rf_waddr; // @[RocketCore.scala:818:21, :1249:28] wire _rf_wdata_T = dmem_resp_valid & dmem_resp_xpu; // @[RocketCore.scala:765:23, :768:44, :819:38] wire _rf_wdata_T_2 = \|wb_ctrl_csr; // @[RocketCore.scala:245:20, :821:34] wire [63:0] _rf_wdata_T_4 = _rf_wdata_T_2 ? _csr_io_rw_rdata : _rf_wdata_T_3; // @[RocketCore.scala:341:19, :821:{21,34}, :822:21] wire [63:0] _rf_wdata_T_5 = ll_wen ? ll_wdata : _rf_wdata_T_4; // @[RocketCore.scala:779:26, :781:24, :820:21, :821:21] wire [63:0] rf_wdata = _rf_wdata_T ? _rf_wdata_T_1 : _rf_wdata_T_5; // @[RocketCore.scala:819:{21,38,78}, :820:21] wire [63:0] coreMonitorBundle_wrdata = rf_wdata; // @[RocketCore.scala:819:21, :1186:31] wire [63:0] xrfWriteBundle_wrdata = rf_wdata; // @[RocketCore.scala:819:21, :1249:28] wire [63:0] _id_rs_T_4; // @[RocketCore.scala:1326:25] assign id_rs_0 = rf_wen & (\|rf_waddr) & rf_waddr == id_raddr1 ? rf_wdata : _id_rs_T_4; // @[RocketCore.scala:326:72, :817:23, :818:21, :819:21, :824:17, :1325:26, :1326:{19,25}, :1331:{16,25}, :1334:{20,31,39}] wire [63:0] _id_rs_T_9; // @[RocketCore.scala:1326:25] assign id_rs_1 = rf_wen & (\|rf_waddr) & rf_waddr == id_raddr2 ? rf_wdata : _id_rs_T_9; // @[RocketCore.scala:326:72, :817:23, :818:21, :819:21, :824:17, :1325:26, :1326:{19,25}, :1331:{16,25}, :1334:{20,31,39}] wire [1:0] _csr_io_inst_0_T = wb_reg_raw_inst[1:0]; // @[RocketCore.scala:301:28, :832:66] wire _csr_io_inst_0_T_1 = &_csr_io_inst_0_T; // @[RocketCore.scala:832:{66,73}] wire [15:0] _csr_io_inst_0_T_2 = wb_reg_inst[31:16]; // @[RocketCore.scala:300:24, :832:91] wire [15:0] _csr_io_inst_0_T_3 = _csr_io_inst_0_T_1 ? _csr_io_inst_0_T_2 : 16'h0; // @[RocketCore.scala:832:{50,73,91}] wire [15:0] _csr_io_inst_0_T_4 = wb_reg_raw_inst[15:0]; // @[RocketCore.scala:301:28, :832:119] wire [31:0] _csr_io_inst_0_T_5 = {_csr_io_inst_0_T_3, _csr_io_inst_0_T_4}; // @[RocketCore.scala:832:{46,50,119}] wire [4:0] _csr_io_fcsr_flags_bits_T = {5{io_fpu_fcsr_flags_valid_0}}; // @[RocketCore.scala:153:7, :839:59] wire [4:0] _csr_io_fcsr_flags_bits_T_1 = io_fpu_fcsr_flags_bits_0 & _csr_io_fcsr_flags_bits_T; // @[RocketCore.scala:153:7, :839:{53,59}] wire [4:0] _csr_io_fcsr_flags_bits_T_4 = _csr_io_fcsr_flags_bits_T_1; // @[RocketCore.scala:839:{53,89}] wire [31:0] _io_fpu_time_T = _csr_io_time[31:0]; // @[RocketCore.scala:341:19, :840:29] wire [31:0] _coreMonitorBundle_timer_T = _csr_io_time[31:0]; // @[RocketCore.scala:341:19, :840:29, :1191:41] wire [31:0] _xrfWriteBundle_timer_T = _csr_io_time[31:0]; // @[RocketCore.scala:341:19, :840:29, :1254:38] assign io_fpu_time_0 = {32'h0, _io_fpu_time_T}; // @[RocketCore.scala:153:7, :840:{15,29}] wire tval_dmem_addr = ~wb_reg_xcpt; // @[RocketCore.scala:289:35, :845:24] wire _tval_any_addr_T = wb_reg_cause == 64'h3; // @[package.scala:16:47] wire _tval_any_addr_T_1 = wb_reg_cause == 64'h1; // @[package.scala:16:47] wire _tval_any_addr_T_2 = wb_reg_cause == 64'hC; // @[package.scala:16:47] wire _GEN_61 = wb_reg_cause == 64'h14; // @[package.scala:16:47] wire _tval_any_addr_T_3; // @[package.scala:16:47] assign _tval_any_addr_T_3 = _GEN_61; // @[package.scala:16:47] wire _htval_valid_imem_T; // @[RocketCore.scala:853:56] assign _htval_valid_imem_T = _GEN_61; // @[package.scala:16:47] wire _tval_any_addr_T_4 = _tval_any_addr_T \| _tval_any_addr_T_1; // @[package.scala:16:47, :81:59] wire _tval_any_addr_T_5 = _tval_any_addr_T_4 \| _tval_any_addr_T_2; // @[package.scala:16:47, :81:59] wire _tval_any_addr_T_6 = _tval_any_addr_T_5 \| _tval_any_addr_T_3; // @[package.scala:16:47, :81:59] wire tval_any_addr = tval_dmem_addr \| _tval_any_addr_T_6; // @[package.scala:81:59] wire tval_inst = wb_reg_cause == 64'h2; // @[RocketCore.scala:292:35, :848:32] wire _tval_valid_T = tval_any_addr \| tval_inst; // @[RocketCore.scala:846:38, :848:32, :849:46] wire tval_valid = wb_xcpt & _tval_valid_T; // @[RocketCore.scala:849:{28,46}, :1278:14] wire _csr_io_gva_T = tval_any_addr & _csr_io_status_v; // @[RocketCore.scala:341:19, :846:38, :850:43] wire _csr_io_gva_T_1 = tval_dmem_addr & wb_reg_hls_or_dv; // @[RocketCore.scala:297:29, :845:24, :850:80] wire _csr_io_gva_T_2 = _csr_io_gva_T \| _csr_io_gva_T_1; // @[RocketCore.scala:850:{43,62,80}] wire _csr_io_gva_T_3 = wb_xcpt & _csr_io_gva_T_2; // @[RocketCore.scala:850:{25,62}, :1278:14] wire [24:0] _csr_io_tval_a_T = wb_reg_wdata[63:39]; // @[RocketCore.scala:302:25, :1293:17] wire [24:0] csr_io_tval_a = _csr_io_tval_a_T; // @[RocketCore.scala:1293:{17,23}] wire _csr_io_tval_msb_T = csr_io_tval_a == 25'h0; // @[RocketCore.scala:1293:23, :1294:21] wire _csr_io_tval_msb_T_1 = &csr_io_tval_a; // @[RocketCore.scala:1293:23, :1294:34] wire _csr_io_tval_msb_T_2 = _csr_io_tval_msb_T \| _csr_io_tval_msb_T_1; // @[RocketCore.scala:1294:{21,29,34}] wire _csr_io_tval_msb_T_3 = wb_reg_wdata[39]; // @[RocketCore.scala:302:25, :1294:46] wire _csr_io_tval_msb_T_4 = wb_reg_wdata[38]; // @[RocketCore.scala:302:25, :1294:54] wire _csr_io_tval_msb_T_5 = ~_csr_io_tval_msb_T_4; // @[RocketCore.scala:1294:{51,54}] wire csr_io_tval_msb = _csr_io_tval_msb_T_2 ? _csr_io_tval_msb_T_3 : _csr_io_tval_msb_T_5; // @[RocketCore.scala:1294:{18,29,46,51}] assign io_imem_sfence_bits_addr_0 = wb_reg_wdata[38:0]; // @[RocketCore.scala:153:7, :302:25, :1295:16] wire [38:0] _csr_io_tval_T = wb_reg_wdata[38:0]; // @[RocketCore.scala:302:25, :1295:16] wire [39:0] _csr_io_tval_T_1 = {csr_io_tval_msb, _csr_io_tval_T}; // @[RocketCore.scala:1294:18, :1295:{8,16}] wire [39:0] _csr_io_tval_T_2 = tval_valid ? _csr_io_tval_T_1 : 40'h0; // @[RocketCore.scala:849:28, :851:21, :1295:8] wire htval_valid_imem = wb_reg_xcpt & _htval_valid_imem_T; // @[RocketCore.scala:289:35, :853:{40,56}] wire [39:0] htval_imem = htval_valid_imem ? io_imem_gpa_bits_0 : 40'h0; // @[RocketCore.scala:153:7, :853:40, :854:25] wire [39:0] _htval_T = htval_imem; // @[RocketCore.scala:854:25, :860:29] wire _htval_valid_dmem_T = wb_xcpt & tval_dmem_addr; // @[RocketCore.scala:845:24, :857:36, :1278:14] wire [1:0] _htval_valid_dmem_T_4 = {io_dmem_s2_xcpt_pf_ld_0, io_dmem_s2_xcpt_pf_st_0}; // @[RocketCore.scala:153:7, :857:110] wire _htval_valid_dmem_T_5 = \|_htval_valid_dmem_T_4; // @[RocketCore.scala:857:{110,117}] wire _htval_valid_dmem_T_6 = ~_htval_valid_dmem_T_5; // @[RocketCore.scala:857:{90,117}] wire [39:0] htval = _htval_T; // @[RocketCore.scala:860:{29,43}] wire _mhtinst_read_pseudo_T = io_imem_gpa_is_pte_0 & htval_valid_imem; // @[RocketCore.scala:153:7, :853:40, :862:51] wire mhtinst_read_pseudo = _mhtinst_read_pseudo_T; // @[RocketCore.scala:862:{51,72}] wire [11:0] _csr_io_rw_addr_T = wb_reg_inst[31:20]; // @[RocketCore.scala:300:24, :909:32] wire [2:0] _csr_io_rw_cmd_T = {~wb_reg_valid, 2'h0}; // @[RocketCore.scala:288:35] wire [2:0] _csr_io_rw_cmd_T_1 = ~_csr_io_rw_cmd_T; // @[CSR.scala:183:{11,15}] wire [2:0] _csr_io_rw_cmd_T_2 = wb_ctrl_csr & _csr_io_rw_cmd_T_1; // @[RocketCore.scala:245:20] assign io_bpwatch_0_action_0 = {2'h0, _csr_io_bp_0_control_action}; // @[RocketCore.scala:153:7, :341:19, :962:18] wire _hazard_targets_T = \|id_raddr1; // @[RocketCore.scala:326:72, :969:55, :1326:41] wire hazard_targets_0_1 = id_ctrl_rxs1 & _hazard_targets_T; // @[RocketCore.scala:321:21, :969:{42,55}] wire _hazard_targets_T_1 = \|id_raddr2; // @[RocketCore.scala:326:72, :970:55, :1326:41] wire hazard_targets_1_1 = id_ctrl_rxs2 & _hazard_targets_T_1; // @[RocketCore.scala:321:21, :970:{42,55}] wire _hazard_targets_T_2 = \|id_waddr; // @[RocketCore.scala:326:72, :971:55] wire hazard_targets_2_1 = id_ctrl_wxd & _hazard_targets_T_2; // @[RocketCore.scala:321:21, :971:{42,55}] reg [31:0] _r; // @[RocketCore.scala:1305:29] wire [30:0] _r_T = _r[31:1]; // @[RocketCore.scala:1305:29, :1306:35] wire [31:0] r = {_r_T, 1'h0}; // @[RocketCore.scala:1306:{35,40}] wire [31:0] _GEN_62 = {27'h0, id_raddr1}; // @[RocketCore.scala:326:72, :1302:35, :1309:58] wire [31:0] _id_sboard_hazard_T = r >> _GEN_62; // @[RocketCore.scala:1302:35, :1306:40] wire _id_sboard_hazard_T_1 = _id_sboard_hazard_T[0]; // @[RocketCore.scala:1302:35] wire _id_sboard_hazard_T_2 = ll_waddr == id_raddr1; // @[RocketCore.scala:326:72, :780:26, :981:70] wire _id_sboard_hazard_T_3 = ll_wen & _id_sboard_hazard_T_2; // @[RocketCore.scala:781:24, :981:{58,70}] wire _id_sboard_hazard_T_4 = ~_id_sboard_hazard_T_3; // @[RocketCore.scala:981:58, :984:80] wire _id_sboard_hazard_T_5 = _id_sboard_hazard_T_1 & _id_sboard_hazard_T_4; // @[RocketCore.scala:984:{77,80}, :1302:35] wire _id_sboard_hazard_T_6 = hazard_targets_0_1 & _id_sboard_hazard_T_5; // @[RocketCore.scala:969:42, :984:77, :1287:27] wire [31:0] _GEN_63 = {27'h0, id_raddr2}; // @[RocketCore.scala:326:72, :1302:35, :1309:58] wire [31:0] _id_sboard_hazard_T_7 = r >> _GEN_63; // @[RocketCore.scala:1302:35, :1306:40] wire _id_sboard_hazard_T_8 = _id_sboard_hazard_T_7[0]; // @[RocketCore.scala:1302:35] wire _id_sboard_hazard_T_9 = ll_waddr == id_raddr2; // @[RocketCore.scala:326:72, :780:26, :981:70] wire _id_sboard_hazard_T_10 = ll_wen & _id_sboard_hazard_T_9; // @[RocketCore.scala:781:24, :981:{58,70}] wire _id_sboard_hazard_T_11 = ~_id_sboard_hazard_T_10; // @[RocketCore.scala:981:58, :984:80] wire _id_sboard_hazard_T_12 = _id_sboard_hazard_T_8 & _id_sboard_hazard_T_11; // @[RocketCore.scala:984:{77,80}, :1302:35] wire _id_sboard_hazard_T_13 = hazard_targets_1_1 & _id_sboard_hazard_T_12; // @[RocketCore.scala:970:42, :984:77, :1287:27] wire [31:0] _GEN_64 = {27'h0, id_waddr}; // @[RocketCore.scala:326:72, :1302:35, :1309:58] wire [31:0] _id_sboard_hazard_T_14 = r >> _GEN_64; // @[RocketCore.scala:1302:35, :1306:40] wire _id_sboard_hazard_T_15 = _id_sboard_hazard_T_14[0]; // @[RocketCore.scala:1302:35] wire _id_sboard_hazard_T_16 = ll_waddr == id_waddr; // @[RocketCore.scala:326:72, :780:26, :981:70] wire _id_sboard_hazard_T_17 = ll_wen & _id_sboard_hazard_T_16; // @[RocketCore.scala:781:24, :981:{58,70}] wire _id_sboard_hazard_T_18 = ~_id_sboard_hazard_T_17; // @[RocketCore.scala:981:58, :984:80] wire _id_sboard_hazard_T_19 = _id_sboard_hazard_T_15 & _id_sboard_hazard_T_18; // @[RocketCore.scala:984:{77,80}, :1302:35] wire _id_sboard_hazard_T_20 = hazard_targets_2_1 & _id_sboard_hazard_T_19; // @[RocketCore.scala:971:42, :984:77, :1287:27] wire _id_sboard_hazard_T_21 = _id_sboard_hazard_T_6 \| _id_sboard_hazard_T_13; // @[RocketCore.scala:1287:{27,50}] wire id_sboard_hazard = _id_sboard_hazard_T_21 \| _id_sboard_hazard_T_20; // @[RocketCore.scala:1287:{27,50}] wire [31:0] _id_stall_fpu_T_4 = 32'h1 << wb_waddr; // @[RocketCore.scala:455:36, :1309:58] wire _ex_cannot_bypass_T = \|ex_ctrl_csr; // @[RocketCore.scala:243:20, :988:38] wire _ex_cannot_bypass_T_1 = _ex_cannot_bypass_T \| ex_ctrl_jalr; // @[RocketCore.scala:243:20, :988:{38,48}] wire _ex_cannot_bypass_T_2 = _ex_cannot_bypass_T_1 \| ex_ctrl_mem; // @[RocketCore.scala:243:20, :988:{48,64}] wire _ex_cannot_bypass_T_3 = _ex_cannot_bypass_T_2 \| ex_ctrl_mul; // @[RocketCore.scala:243:20, :988:{64,79}] wire _ex_cannot_bypass_T_4 = _ex_cannot_bypass_T_3 \| ex_ctrl_div; // @[RocketCore.scala:243:20, :988:{79,94}] wire _ex_cannot_bypass_T_5 = _ex_cannot_bypass_T_4 \| ex_ctrl_fp; // @[RocketCore.scala:243:20, :988:{94,109}] wire _ex_cannot_bypass_T_6 = _ex_cannot_bypass_T_5 \| ex_ctrl_rocc; // @[RocketCore.scala:243:20, :988:{109,123}] wire ex_cannot_bypass = _ex_cannot_bypass_T_6; // @[RocketCore.scala:988:{123,139}] wire _data_hazard_ex_T_1 = hazard_targets_0_1 & _data_hazard_ex_T; // @[RocketCore.scala:969:42, :989:70, :1287:27] wire _data_hazard_ex_T_3 = hazard_targets_1_1 & _data_hazard_ex_T_2; // @[RocketCore.scala:970:42, :989:70, :1287:27] wire _GEN_65 = id_waddr == ex_waddr; // @[RocketCore.scala:326:72, :453:36, :989:70] wire _data_hazard_ex_T_4; // @[RocketCore.scala:989:70] assign _data_hazard_ex_T_4 = _GEN_65; // @[RocketCore.scala:989:70] wire _fp_data_hazard_ex_T_7; // @[RocketCore.scala:990:90] assign _fp_data_hazard_ex_T_7 = _GEN_65; // @[RocketCore.scala:989:70, :990:90] wire _data_hazard_ex_T_5 = hazard_targets_2_1 & _data_hazard_ex_T_4; // @[RocketCore.scala:971:42, :989:70, :1287:27] wire _data_hazard_ex_T_6 = _data_hazard_ex_T_1 \| _data_hazard_ex_T_3; // @[RocketCore.scala:1287:{27,50}] wire _data_hazard_ex_T_7 = _data_hazard_ex_T_6 \| _data_hazard_ex_T_5; // @[RocketCore.scala:1287:{27,50}] wire data_hazard_ex = ex_ctrl_wxd & _data_hazard_ex_T_7; // @[RocketCore.scala:243:20, :989:36, :1287:50] wire _fp_data_hazard_ex_T = id_ctrl_fp & ex_ctrl_wfd; // @[RocketCore.scala:243:20, :321:21, :990:38] wire _fp_data_hazard_ex_T_2 = io_fpu_dec_ren1_0 & _fp_data_hazard_ex_T_1; // @[RocketCore.scala:153:7, :990:90, :1287:27] wire _fp_data_hazard_ex_T_4 = io_fpu_dec_ren2_0 & _fp_data_hazard_ex_T_3; // @[RocketCore.scala:153:7, :990:90, :1287:27] wire _fp_data_hazard_ex_T_5 = id_raddr3 == ex_waddr; // @[RocketCore.scala:326:72, :453:36, :990:90] wire _fp_data_hazard_ex_T_6 = io_fpu_dec_ren3_0 & _fp_data_hazard_ex_T_5; // @[RocketCore.scala:153:7, :990:90, :1287:27] wire _fp_data_hazard_ex_T_8 = io_fpu_dec_wen_0 & _fp_data_hazard_ex_T_7; // @[RocketCore.scala:153:7, :990:90, :1287:27] wire _fp_data_hazard_ex_T_9 = _fp_data_hazard_ex_T_2 \| _fp_data_hazard_ex_T_4; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_ex_T_10 = _fp_data_hazard_ex_T_9 \| _fp_data_hazard_ex_T_6; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_ex_T_11 = _fp_data_hazard_ex_T_10 \| _fp_data_hazard_ex_T_8; // @[RocketCore.scala:1287:{27,50}] wire fp_data_hazard_ex = _fp_data_hazard_ex_T & _fp_data_hazard_ex_T_11; // @[RocketCore.scala:990:{38,53}, :1287:50] wire _id_ex_hazard_T = data_hazard_ex & ex_cannot_bypass; // @[RocketCore.scala:988:139, :989:36, :991:54] wire _id_ex_hazard_T_1 = _id_ex_hazard_T \| fp_data_hazard_ex; // @[RocketCore.scala:990:53, :991:{54,74}] wire id_ex_hazard = ex_reg_valid & _id_ex_hazard_T_1; // @[RocketCore.scala:248:35, :991:{35,74}] wire _mem_cannot_bypass_T = \|mem_ctrl_csr; // @[RocketCore.scala:244:21, :997:40] wire _mem_cannot_bypass_T_1 = mem_ctrl_mem & mem_mem_cmd_bh; // @[RocketCore.scala:244:21, :995:41, :997:66] wire _mem_cannot_bypass_T_2 = _mem_cannot_bypass_T \| _mem_cannot_bypass_T_1; // @[RocketCore.scala:997:{40,50,66}] wire _mem_cannot_bypass_T_3 = _mem_cannot_bypass_T_2 \| mem_ctrl_mul; // @[RocketCore.scala:244:21, :997:{50,84}] wire _mem_cannot_bypass_T_4 = _mem_cannot_bypass_T_3 \| mem_ctrl_div; // @[RocketCore.scala:244:21, :997:{84,100}] wire _mem_cannot_bypass_T_5 = _mem_cannot_bypass_T_4 \| mem_ctrl_fp; // @[RocketCore.scala:244:21, :997:{100,116}] wire _mem_cannot_bypass_T_6 = _mem_cannot_bypass_T_5 \| mem_ctrl_rocc; // @[RocketCore.scala:244:21, :997:{116,131}] wire mem_cannot_bypass = _mem_cannot_bypass_T_6 \| mem_ctrl_vec; // @[RocketCore.scala:244:21, :997:{131,148}] wire _data_hazard_mem_T_1 = hazard_targets_0_1 & _data_hazard_mem_T; // @[RocketCore.scala:969:42, :998:72, :1287:27] wire _data_hazard_mem_T_3 = hazard_targets_1_1 & _data_hazard_mem_T_2; // @[RocketCore.scala:970:42, :998:72, :1287:27] wire _GEN_66 = id_waddr == mem_waddr; // @[RocketCore.scala:326:72, :454:38, :998:72] wire _data_hazard_mem_T_4; // @[RocketCore.scala:998:72] assign _data_hazard_mem_T_4 = _GEN_66; // @[RocketCore.scala:998:72] wire _fp_data_hazard_mem_T_7; // @[RocketCore.scala:999:92] assign _fp_data_hazard_mem_T_7 = _GEN_66; // @[RocketCore.scala:998:72, :999:92] wire _data_hazard_mem_T_5 = hazard_targets_2_1 & _data_hazard_mem_T_4; // @[RocketCore.scala:971:42, :998:72, :1287:27] wire _data_hazard_mem_T_6 = _data_hazard_mem_T_1 \| _data_hazard_mem_T_3; // @[RocketCore.scala:1287:{27,50}] wire _data_hazard_mem_T_7 = _data_hazard_mem_T_6 \| _data_hazard_mem_T_5; // @[RocketCore.scala:1287:{27,50}] wire data_hazard_mem = mem_ctrl_wxd & _data_hazard_mem_T_7; // @[RocketCore.scala:244:21, :998:38, :1287:50] wire _fp_data_hazard_mem_T = id_ctrl_fp & mem_ctrl_wfd; // @[RocketCore.scala:244:21, :321:21, :999:39] wire _fp_data_hazard_mem_T_2 = io_fpu_dec_ren1_0 & _fp_data_hazard_mem_T_1; // @[RocketCore.scala:153:7, :999:92, :1287:27] wire _fp_data_hazard_mem_T_4 = io_fpu_dec_ren2_0 & _fp_data_hazard_mem_T_3; // @[RocketCore.scala:153:7, :999:92, :1287:27] wire _fp_data_hazard_mem_T_5 = id_raddr3 == mem_waddr; // @[RocketCore.scala:326:72, :454:38, :999:92] wire _fp_data_hazard_mem_T_6 = io_fpu_dec_ren3_0 & _fp_data_hazard_mem_T_5; // @[RocketCore.scala:153:7, :999:92, :1287:27] wire _fp_data_hazard_mem_T_8 = io_fpu_dec_wen_0 & _fp_data_hazard_mem_T_7; // @[RocketCore.scala:153:7, :999:92, :1287:27] wire _fp_data_hazard_mem_T_9 = _fp_data_hazard_mem_T_2 \| _fp_data_hazard_mem_T_4; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_mem_T_10 = _fp_data_hazard_mem_T_9 \| _fp_data_hazard_mem_T_6; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_mem_T_11 = _fp_data_hazard_mem_T_10 \| _fp_data_hazard_mem_T_8; // @[RocketCore.scala:1287:{27,50}] wire fp_data_hazard_mem = _fp_data_hazard_mem_T & _fp_data_hazard_mem_T_11; // @[RocketCore.scala:999:{39,55}, :1287:50] wire _id_mem_hazard_T = data_hazard_mem & mem_cannot_bypass; // @[RocketCore.scala:997:148, :998:38, :1000:57] wire _id_mem_hazard_T_1 = _id_mem_hazard_T \| fp_data_hazard_mem; // @[RocketCore.scala:999:55, :1000:{57,78}] wire id_mem_hazard = mem_reg_valid & _id_mem_hazard_T_1; // @[RocketCore.scala:265:36, :1000:{37,78}] wire _id_load_use_T = mem_reg_valid & data_hazard_mem; // @[RocketCore.scala:265:36, :998:38, :1001:32] assign _id_load_use_T_1 = _id_load_use_T & mem_ctrl_mem; // @[RocketCore.scala:244:21, :1001:{32,51}] assign id_load_use = _id_load_use_T_1; // @[RocketCore.scala:332:25, :1001:51] wire _id_vconfig_hazard_T_1 = mem_reg_valid & mem_reg_set_vconfig; // @[RocketCore.scala:265:36, :275:36, :1004:20] wire _id_vconfig_hazard_T_2 = _id_vconfig_hazard_T_1; // @[RocketCore.scala:1003:42, :1004:20] wire _id_vconfig_hazard_T_3 = wb_reg_valid & wb_reg_set_vconfig; // @[RocketCore.scala:288:35, :293:35, :1005:19] wire _id_vconfig_hazard_T_4 = _id_vconfig_hazard_T_2 \| _id_vconfig_hazard_T_3; // @[RocketCore.scala:1003:42, :1004:44, :1005:19] wire _GEN_67 = id_raddr1 == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1008:70] wire _data_hazard_wb_T; // @[RocketCore.scala:1008:70] assign _data_hazard_wb_T = _GEN_67; // @[RocketCore.scala:1008:70] wire _fp_data_hazard_wb_T_1; // @[RocketCore.scala:1009:90] assign _fp_data_hazard_wb_T_1 = _GEN_67; // @[RocketCore.scala:1008:70, :1009:90] wire _data_hazard_wb_T_1 = hazard_targets_0_1 & _data_hazard_wb_T; // @[RocketCore.scala:969:42, :1008:70, :1287:27] wire _GEN_68 = id_raddr2 == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1008:70] wire _data_hazard_wb_T_2; // @[RocketCore.scala:1008:70] assign _data_hazard_wb_T_2 = _GEN_68; // @[RocketCore.scala:1008:70] wire _fp_data_hazard_wb_T_3; // @[RocketCore.scala:1009:90] assign _fp_data_hazard_wb_T_3 = _GEN_68; // @[RocketCore.scala:1008:70, :1009:90] wire _data_hazard_wb_T_3 = hazard_targets_1_1 & _data_hazard_wb_T_2; // @[RocketCore.scala:970:42, :1008:70, :1287:27] wire _GEN_69 = id_waddr == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1008:70] wire _data_hazard_wb_T_4; // @[RocketCore.scala:1008:70] assign _data_hazard_wb_T_4 = _GEN_69; // @[RocketCore.scala:1008:70] wire _fp_data_hazard_wb_T_7; // @[RocketCore.scala:1009:90] assign _fp_data_hazard_wb_T_7 = _GEN_69; // @[RocketCore.scala:1008:70, :1009:90] wire _data_hazard_wb_T_5 = hazard_targets_2_1 & _data_hazard_wb_T_4; // @[RocketCore.scala:971:42, :1008:70, :1287:27] wire _data_hazard_wb_T_6 = _data_hazard_wb_T_1 \| _data_hazard_wb_T_3; // @[RocketCore.scala:1287:{27,50}] wire _data_hazard_wb_T_7 = _data_hazard_wb_T_6 \| _data_hazard_wb_T_5; // @[RocketCore.scala:1287:{27,50}] wire data_hazard_wb = wb_ctrl_wxd & _data_hazard_wb_T_7; // @[RocketCore.scala:245:20, :1008:36, :1287:50] wire _fp_data_hazard_wb_T = id_ctrl_fp & wb_ctrl_wfd; // @[RocketCore.scala:245:20, :321:21, :1009:38] wire _fp_data_hazard_wb_T_2 = io_fpu_dec_ren1_0 & _fp_data_hazard_wb_T_1; // @[RocketCore.scala:153:7, :1009:90, :1287:27] wire _fp_data_hazard_wb_T_4 = io_fpu_dec_ren2_0 & _fp_data_hazard_wb_T_3; // @[RocketCore.scala:153:7, :1009:90, :1287:27] wire _fp_data_hazard_wb_T_5 = id_raddr3 == wb_waddr; // @[RocketCore.scala:326:72, :455:36, :1009:90] wire _fp_data_hazard_wb_T_6 = io_fpu_dec_ren3_0 & _fp_data_hazard_wb_T_5; // @[RocketCore.scala:153:7, :1009:90, :1287:27] wire _fp_data_hazard_wb_T_8 = io_fpu_dec_wen_0 & _fp_data_hazard_wb_T_7; // @[RocketCore.scala:153:7, :1009:90, :1287:27] wire _fp_data_hazard_wb_T_9 = _fp_data_hazard_wb_T_2 \| _fp_data_hazard_wb_T_4; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_wb_T_10 = _fp_data_hazard_wb_T_9 \| _fp_data_hazard_wb_T_6; // @[RocketCore.scala:1287:{27,50}] wire _fp_data_hazard_wb_T_11 = _fp_data_hazard_wb_T_10 \| _fp_data_hazard_wb_T_8; // @[RocketCore.scala:1287:{27,50}] wire fp_data_hazard_wb = _fp_data_hazard_wb_T & _fp_data_hazard_wb_T_11; // @[RocketCore.scala:1009:{38,53}, :1287:50] wire _id_wb_hazard_T = data_hazard_wb & wb_set_sboard; // @[RocketCore.scala:756:69, :1008:36, :1010:54] wire _id_wb_hazard_T_1 = _id_wb_hazard_T \| fp_data_hazard_wb; // @[RocketCore.scala:1009:53, :1010:{54,71}] wire id_wb_hazard = wb_reg_valid & _id_wb_hazard_T_1; // @[RocketCore.scala:288:35, :1010:{35,71}] reg [31:0] _id_stall_fpu_r; // @[RocketCore.scala:1305:29] wire _id_stall_fpu_T = wb_dcache_miss \| wb_ctrl_vec; // @[RocketCore.scala:245:20, :596:36, :1014:36] wire _id_stall_fpu_T_1 = _id_stall_fpu_T & wb_ctrl_wfd; // @[RocketCore.scala:245:20, :1014:{36,52}] wire _id_stall_fpu_T_2 = _id_stall_fpu_T_1 \| io_fpu_sboard_set_0; // @[RocketCore.scala:153:7, :1014:{52,67}] wire _id_stall_fpu_T_3 = _id_stall_fpu_T_2 & wb_valid; // @[RocketCore.scala:815:45, :1014:{67,89}] wire _id_stall_fpu_T_7 = _id_stall_fpu_T_3; // @[RocketCore.scala:1014:89, :1312:17] wire [31:0] _id_stall_fpu_T_5 = _id_stall_fpu_T_3 ? _id_stall_fpu_T_4 : 32'h0; // @[RocketCore.scala:1014:89, :1309:{49,58}] wire [31:0] _id_stall_fpu_T_6 = _id_stall_fpu_r \| _id_stall_fpu_T_5; // @[RocketCore.scala:1300:60, :1305:29, :1309:49] wire _id_stall_fpu_T_8 = dmem_resp_replay & dmem_resp_fpu; // @[RocketCore.scala:766:45, :769:42, :1016:39] wire _id_stall_fpu_T_9 = _id_stall_fpu_T_8; // @[RocketCore.scala:1016:{39,57}] wire [31:0] _id_stall_fpu_T_10 = 32'h1 << io_fpu_ll_resp_tag_0; // @[RocketCore.scala:153:7, :1309:58] wire [31:0] _id_stall_fpu_T_11 = _id_stall_fpu_T_9 ? _id_stall_fpu_T_10 : 32'h0; // @[RocketCore.scala:1016:57, :1309:{49,58}] wire [31:0] _id_stall_fpu_T_12 = ~_id_stall_fpu_T_11; // @[RocketCore.scala:1301:64, :1309:49] wire [31:0] _id_stall_fpu_T_13 = _id_stall_fpu_T_6 & _id_stall_fpu_T_12; // @[RocketCore.scala:1300:60, :1301:{62,64}] wire _id_stall_fpu_T_14 = _id_stall_fpu_T_7 \| _id_stall_fpu_T_9; // @[RocketCore.scala:1016:57, :1312:17] wire [31:0] _id_stall_fpu_T_15 = 32'h1 << io_fpu_sboard_clra_0; // @[RocketCore.scala:153:7, :1309:58] wire [31:0] _id_stall_fpu_T_16 = io_fpu_sboard_clr_0 ? _id_stall_fpu_T_15 : 32'h0; // @[RocketCore.scala:153:7, :1309:{49,58}] wire [31:0] _id_stall_fpu_T_17 = ~_id_stall_fpu_T_16; // @[RocketCore.scala:1301:64, :1309:49] wire [31:0] _id_stall_fpu_T_18 = _id_stall_fpu_T_13 & _id_stall_fpu_T_17; // @[RocketCore.scala:1301:{62,64}] wire _id_stall_fpu_T_19 = _id_stall_fpu_T_14 \| io_fpu_sboard_clr_0; // @[RocketCore.scala:153:7, :1312:17] wire [31:0] _id_stall_fpu_T_20 = _id_stall_fpu_r >> _GEN_62; // @[RocketCore.scala:1302:35, :1305:29] wire _id_stall_fpu_T_21 = _id_stall_fpu_T_20[0]; // @[RocketCore.scala:1302:35] wire _id_stall_fpu_T_22 = io_fpu_dec_ren1_0 & _id_stall_fpu_T_21; // @[RocketCore.scala:153:7, :1287:27, :1302:35] wire [31:0] _id_stall_fpu_T_23 = _id_stall_fpu_r >> _GEN_63; // @[RocketCore.scala:1302:35, :1305:29] wire _id_stall_fpu_T_24 = _id_stall_fpu_T_23[0]; // @[RocketCore.scala:1302:35] wire _id_stall_fpu_T_25 = io_fpu_dec_ren2_0 & _id_stall_fpu_T_24; // @[RocketCore.scala:153:7, :1287:27, :1302:35] wire [31:0] _id_stall_fpu_T_26 = _id_stall_fpu_r >> id_raddr3; // @[RocketCore.scala:326:72, :1302:35, :1305:29] wire _id_stall_fpu_T_27 = _id_stall_fpu_T_26[0]; // @[RocketCore.scala:1302:35] wire _id_stall_fpu_T_28 = io_fpu_dec_ren3_0 & _id_stall_fpu_T_27; // @[RocketCore.scala:153:7, :1287:27, :1302:35] wire [31:0] _id_stall_fpu_T_29 = _id_stall_fpu_r >> _GEN_64; // @[RocketCore.scala:1302:35, :1305:29] wire _id_stall_fpu_T_30 = _id_stall_fpu_T_29[0]; // @[RocketCore.scala:1302:35] wire _id_stall_fpu_T_31 = io_fpu_dec_wen_0 & _id_stall_fpu_T_30; // @[RocketCore.scala:153:7, :1287:27, :1302:35] wire _id_stall_fpu_T_32 = _id_stall_fpu_T_22 \| _id_stall_fpu_T_25; // @[RocketCore.scala:1287:{27,50}] wire _id_stall_fpu_T_33 = _id_stall_fpu_T_32 \| _id_stall_fpu_T_28; // @[RocketCore.scala:1287:{27,50}] wire id_stall_fpu = _id_stall_fpu_T_33 \| _id_stall_fpu_T_31; // @[RocketCore.scala:1287:{27,50}] reg dcache_blocked_blocked; // @[RocketCore.scala:1024:22] wire _dcache_blocked_blocked_T = ~io_dmem_req_ready_0; // @[RocketCore.scala:153:7, :597:45, :1025:16] wire _dcache_blocked_blocked_T_1 = _dcache_blocked_blocked_T; // @[RocketCore.scala:1025:{16,35}] wire _dcache_blocked_blocked_T_2 = ~io_dmem_perf_grant_0; // @[RocketCore.scala:153:7, :1025:63] wire _dcache_blocked_blocked_T_3 = _dcache_blocked_blocked_T_1 & _dcache_blocked_blocked_T_2; // @[RocketCore.scala:1025:{35,60,63}] wire _dcache_blocked_blocked_T_4 = dcache_blocked_blocked \| io_dmem_req_valid_0; // @[RocketCore.scala:153:7, :1024:22, :1025:95] wire _dcache_blocked_blocked_T_5 = _dcache_blocked_blocked_T_4 \| io_dmem_s2_nack_0; // @[RocketCore.scala:153:7, :1025:{95,116}] wire _dcache_blocked_blocked_T_6 = _dcache_blocked_blocked_T_3 & _dcache_blocked_blocked_T_5; // @[RocketCore.scala:1025:{60,83,116}] wire _dcache_blocked_T = ~io_dmem_perf_grant_0; // @[RocketCore.scala:153:7, :1025:63, :1026:16] wire dcache_blocked = dcache_blocked_blocked & _dcache_blocked_T; // @[RocketCore.scala:1024:22, :1026:{13,16}] reg rocc_blocked; // @[RocketCore.scala:1028:25] wire _rocc_blocked_T = ~wb_xcpt; // @[RocketCore.scala:815:48, :1029:19, :1278:14] wire _rocc_blocked_T_2 = _rocc_blocked_T; // @[RocketCore.scala:1029:{19,28}] wire _rocc_blocked_T_3 = io_rocc_cmd_valid \| rocc_blocked; // @[RocketCore.scala:153:7, :1028:25, :1029:72] wire _rocc_blocked_T_4 = _rocc_blocked_T_2 & _rocc_blocked_T_3; // @[RocketCore.scala:1029:{28,50,72}] wire _ctrl_stalld_T = id_ex_hazard \| id_mem_hazard; // @[RocketCore.scala:991:35, :1000:37, :1032:18] wire _ctrl_stalld_T_1 = _ctrl_stalld_T \| id_wb_hazard; // @[RocketCore.scala:1010:35, :1032:{18,35}] wire _ctrl_stalld_T_2 = _ctrl_stalld_T_1 \| id_sboard_hazard; // @[RocketCore.scala:1032:{35,51}, :1287:50] wire _ctrl_stalld_T_3 = _ctrl_stalld_T_2; // @[RocketCore.scala:1032:{51,71}] wire _ctrl_stalld_T_4 = ex_reg_valid \| mem_reg_valid; // @[RocketCore.scala:248:35, :265:36, :1034:40] wire _ctrl_stalld_T_5 = _ctrl_stalld_T_4 \| wb_reg_valid; // @[RocketCore.scala:288:35, :1034:{40,57}] wire _ctrl_stalld_T_6 = _csr_io_singleStep & _ctrl_stalld_T_5; // @[RocketCore.scala:341:19, :1034:{23,57}] wire _ctrl_stalld_T_7 = _ctrl_stalld_T_3 \| _ctrl_stalld_T_6; // @[RocketCore.scala:1032:71, :1033:23, :1034:23] wire _ctrl_stalld_T_8 = id_csr_en & _csr_io_decode_0_fp_csr; // @[package.scala:81:59] wire _ctrl_stalld_T_9 = ~io_fpu_fcsr_rdy_0; // @[RocketCore.scala:153:7, :1035:45] wire _ctrl_stalld_T_10 = _ctrl_stalld_T_8 & _ctrl_stalld_T_9; // @[RocketCore.scala:1035:{15,42,45}] wire _ctrl_stalld_T_11 = _ctrl_stalld_T_7 \| _ctrl_stalld_T_10; // @[RocketCore.scala:1033:23, :1034:74, :1035:42] wire _ctrl_stalld_T_14 = _ctrl_stalld_T_11; // @[RocketCore.scala:1034:74, :1035:62] wire _ctrl_stalld_T_15 = id_ctrl_fp & id_stall_fpu; // @[RocketCore.scala:321:21, :1037:16, :1287:50] wire _ctrl_stalld_T_16 = _ctrl_stalld_T_14 \| _ctrl_stalld_T_15; // @[RocketCore.scala:1035:62, :1036:61, :1037:16] wire _ctrl_stalld_T_17 = id_ctrl_mem & dcache_blocked; // @[RocketCore.scala:321:21, :1026:13, :1038:17] wire _ctrl_stalld_T_18 = _ctrl_stalld_T_16 \| _ctrl_stalld_T_17; // @[RocketCore.scala:1036:61, :1037:32, :1038:17] wire _ctrl_stalld_T_19 = id_ctrl_rocc & rocc_blocked; // @[RocketCore.scala:321:21, :1028:25, :1039:18] wire _ctrl_stalld_T_20 = _ctrl_stalld_T_18 \| _ctrl_stalld_T_19; // @[RocketCore.scala:1037:32, :1038:35, :1039:18] wire _ctrl_stalld_T_21 = ~wb_wxd; // @[RocketCore.scala:755:29, :782:26, :1040:65] wire _ctrl_stalld_T_22 = _div_io_resp_valid & _ctrl_stalld_T_21; // @[RocketCore.scala:511:19, :1040:{62,65}] wire _ctrl_stalld_T_23 = _div_io_req_ready \| _ctrl_stalld_T_22; // @[RocketCore.scala:511:19, :1040:{40,62}] wire _ctrl_stalld_T_24 = ~_ctrl_stalld_T_23; // @[RocketCore.scala:1040:{21,40}] wire _ctrl_stalld_T_25 = _ctrl_stalld_T_24 \| _div_io_req_valid_T; // @[RocketCore.scala:512:36, :1040:{21,75}] wire _ctrl_stalld_T_26 = id_ctrl_div & _ctrl_stalld_T_25; // @[RocketCore.scala:321:21, :1040:{17,75}] wire _ctrl_stalld_T_27 = _ctrl_stalld_T_20 \| _ctrl_stalld_T_26; // @[RocketCore.scala:1038:35, :1039:34, :1040:17] wire _ctrl_stalld_T_29 = _ctrl_stalld_T_27; // @[RocketCore.scala:1039:34, :1040:96] wire _ctrl_stalld_T_30 = _ctrl_stalld_T_29 \| id_do_fence; // @[RocketCore.scala:410:32, :1040:96, :1041:15] wire _ctrl_stalld_T_31 = _ctrl_stalld_T_30 \| _csr_io_csr_stall; // @[RocketCore.scala:341:19, :1041:15, :1042:17] wire _ctrl_stalld_T_32 = _ctrl_stalld_T_31 \| id_reg_pause; // @[RocketCore.scala:161:25, :1042:17, :1043:22] wire ctrl_stalld = _ctrl_stalld_T_32; // @[RocketCore.scala:1043:22, :1044:18] wire _ctrl_killd_T = ~_ibuf_io_inst_0_valid; // @[RocketCore.scala:311:20, :1046:17] wire _ctrl_killd_T_1 = _ctrl_killd_T \| _ibuf_io_inst_0_bits_replay; // @[RocketCore.scala:311:20, :1046:{17,40}] wire _ctrl_killd_T_2 = _ctrl_killd_T_1 \| take_pc_mem_wb; // @[RocketCore.scala:307:35, :1046:{40,71}] wire _ctrl_killd_T_3 = _ctrl_killd_T_2 \| ctrl_stalld; // @[RocketCore.scala:1044:18, :1046:{71,89}] assign _ctrl_killd_T_4 = _ctrl_killd_T_3 \| _csr_io_interrupt; // @[RocketCore.scala:341:19, :1046:{89,104}] assign ctrl_killd = _ctrl_killd_T_4; // @[RocketCore.scala:338:24, :1046:104] assign _io_imem_req_bits_speculative_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :1049:35] assign io_imem_req_bits_speculative_0 = _io_imem_req_bits_speculative_T; // @[RocketCore.scala:153:7, :1049:35] wire _io_imem_req_bits_pc_T = wb_xcpt \| _csr_io_eret; // @[RocketCore.scala:341:19, :1051:17, :1278:14] wire [39:0] _io_imem_req_bits_pc_T_1 = replay_wb ? wb_reg_pc : mem_npc; // @[RocketCore.scala:295:22, :619:139, :761:71, :1052:8] assign _io_imem_req_bits_pc_T_2 = _io_imem_req_bits_pc_T ? _csr_io_evec : _io_imem_req_bits_pc_T_1; // @[RocketCore.scala:341:19, :1051:{8,17}, :1052:8] assign io_imem_req_bits_pc_0 = _io_imem_req_bits_pc_T_2; // @[RocketCore.scala:153:7, :1051:8] wire _io_imem_flush_icache_T = wb_reg_valid & wb_ctrl_fence_i; // @[RocketCore.scala:245:20, :288:35, :1054:40] wire _io_imem_flush_icache_T_1 = ~io_dmem_s2_nack_0; // @[RocketCore.scala:153:7, :1054:62] assign _io_imem_flush_icache_T_2 = _io_imem_flush_icache_T & _io_imem_flush_icache_T_1; // @[RocketCore.scala:1054:{40,59,62}] assign io_imem_flush_icache_0 = _io_imem_flush_icache_T_2; // @[RocketCore.scala:153:7, :1054:59] wire _io_imem_might_request_imem_might_request_reg_T = ex_pc_valid \| mem_pc_valid; // @[RocketCore.scala:595:51, :614:54, :1056:43] wire _io_imem_might_request_imem_might_request_reg_T_1 = io_ptw_customCSRs_csrs_0_value_0[1]; // @[CustomCSRs.scala:44:61] wire _io_imem_might_request_imem_might_request_reg_T_2 = _io_imem_might_request_imem_might_request_reg_T \| _io_imem_might_request_imem_might_request_reg_T_1; // @[CustomCSRs.scala:44:61] wire _io_imem_might_request_imem_might_request_reg_T_3 = _io_imem_might_request_imem_might_request_reg_T_2; // @[RocketCore.scala:1056:{59,103}] wire _io_imem_progress_T = ~replay_wb_common; // @[RocketCore.scala:757:42, :1059:47] wire _io_imem_progress_T_1 = wb_reg_valid & _io_imem_progress_T; // @[RocketCore.scala:288:35, :1059:{44,47}] reg io_imem_progress_REG; // @[RocketCore.scala:1059:30] assign io_imem_progress_0 = io_imem_progress_REG; // @[RocketCore.scala:153:7, :1059:30] assign _io_imem_sfence_valid_T = wb_reg_valid & wb_reg_sfence; // @[RocketCore.scala:288:35, :294:26, :1060:40] assign io_imem_sfence_valid_0 = _io_imem_sfence_valid_T; // @[RocketCore.scala:153:7, :1060:40] assign _io_imem_sfence_bits_rs1_T = wb_reg_mem_size[0]; // @[RocketCore.scala:296:28, :1061:45] assign io_imem_sfence_bits_rs1_0 = _io_imem_sfence_bits_rs1_T; // @[RocketCore.scala:153:7, :1061:45] assign _io_imem_sfence_bits_rs2_T = wb_reg_mem_size[1]; // @[RocketCore.scala:296:28, :1062:45] assign io_imem_sfence_bits_rs2_0 = _io_imem_sfence_bits_rs2_T; // @[RocketCore.scala:153:7, :1062:45] assign io_imem_sfence_bits_asid_0 = wb_reg_rs2[0]; // @[RocketCore.scala:153:7, :303:23, :1064:28] wire _ibuf_io_inst_0_ready_T = ~ctrl_stalld; // @[RocketCore.scala:1044:18, :1069:28] wire _io_imem_btb_update_valid_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :1071:48] wire _io_imem_btb_update_valid_T_1 = mem_reg_valid & _io_imem_btb_update_valid_T; // @[RocketCore.scala:265:36, :1071:{45,48}] wire _io_imem_btb_update_valid_T_2 = _io_imem_btb_update_valid_T_1 & mem_wrong_npc; // @[RocketCore.scala:621:8, :1071:{45,60}] wire _io_imem_btb_update_valid_T_3 = ~mem_cfi; // @[RocketCore.scala:625:50, :1071:81] wire _io_imem_btb_update_valid_T_4 = _io_imem_btb_update_valid_T_3 \| mem_cfi_taken; // @[RocketCore.scala:626:74, :1071:{81,90}] assign _io_imem_btb_update_valid_T_5 = _io_imem_btb_update_valid_T_2 & _io_imem_btb_update_valid_T_4; // @[RocketCore.scala:1071:{60,77,90}] assign io_imem_btb_update_valid_0 = _io_imem_btb_update_valid_T_5; // @[RocketCore.scala:153:7, :1071:77] wire _GEN_70 = mem_ctrl_jal \| mem_ctrl_jalr; // @[RocketCore.scala:244:21, :1074:23] wire _io_imem_btb_update_bits_cfiType_T; // @[RocketCore.scala:1074:23] assign _io_imem_btb_update_bits_cfiType_T = _GEN_70; // @[RocketCore.scala:1074:23] wire _io_imem_btb_update_bits_cfiType_T_8; // @[RocketCore.scala:1076:22] assign _io_imem_btb_update_bits_cfiType_T_8 = _GEN_70; // @[RocketCore.scala:1074:23, :1076:22] wire _io_imem_btb_update_bits_cfiType_T_1 = mem_waddr[0]; // @[RocketCore.scala:454:38, :1074:53] wire _io_imem_btb_update_bits_cfiType_T_2 = _io_imem_btb_update_bits_cfiType_T & _io_imem_btb_update_bits_cfiType_T_1; // @[RocketCore.scala:1074:{23,41,53}] wire [4:0] _io_imem_btb_update_bits_cfiType_T_3 = mem_reg_inst[19:15]; // @[RocketCore.scala:278:25, :1075:39] wire [4:0] _io_imem_btb_update_bits_cfiType_T_4 = _io_imem_btb_update_bits_cfiType_T_3; // @[RocketCore.scala:1075:{39,47}] wire [4:0] _io_imem_btb_update_bits_cfiType_T_5 = _io_imem_btb_update_bits_cfiType_T_4 & 5'h1B; // @[RocketCore.scala:1075:{47,64}] wire _io_imem_btb_update_bits_cfiType_T_6 = _io_imem_btb_update_bits_cfiType_T_5 == 5'h1; // @[RocketCore.scala:1075:64] wire _io_imem_btb_update_bits_cfiType_T_7 = mem_ctrl_jalr & _io_imem_btb_update_bits_cfiType_T_6; // @[RocketCore.scala:244:21, :1075:{23,64}] wire _io_imem_btb_update_bits_cfiType_T_9 = _io_imem_btb_update_bits_cfiType_T_8; // @[RocketCore.scala:1076:{8,22}] wire [1:0] _io_imem_btb_update_bits_cfiType_T_10 = _io_imem_btb_update_bits_cfiType_T_7 ? 2'h3 : {1'h0, _io_imem_btb_update_bits_cfiType_T_9}; // @[RocketCore.scala:1075:{8,23}, :1076:8] assign _io_imem_btb_update_bits_cfiType_T_11 = _io_imem_btb_update_bits_cfiType_T_2 ? 2'h2 : _io_imem_btb_update_bits_cfiType_T_10; // @[RocketCore.scala:1074:{8,41}, :1075:8] assign io_imem_btb_update_bits_cfiType_0 = _io_imem_btb_update_bits_cfiType_T_11; // @[RocketCore.scala:153:7, :1074:8] assign io_imem_btb_update_bits_target_0 = io_imem_req_bits_pc_0[38:0]; // @[RocketCore.scala:153:7, :1078:34] wire [1:0] _io_imem_btb_update_bits_br_pc_T = {~mem_reg_rvc, 1'h0}; // @[RocketCore.scala:266:36, :1079:74] wire [40:0] _io_imem_btb_update_bits_br_pc_T_1 = {1'h0, mem_reg_pc} + {39'h0, _io_imem_btb_update_bits_br_pc_T}; // @[RocketCore.scala:277:23, :1079:{69,74}] wire [39:0] _io_imem_btb_update_bits_br_pc_T_2 = _io_imem_btb_update_bits_br_pc_T_1[39:0]; // @[RocketCore.scala:1079:69] assign io_imem_btb_update_bits_br_pc_0 = _io_imem_btb_update_bits_br_pc_T_2[38:0]; // @[RocketCore.scala:153:7, :1079:{33,69}] wire [38:0] _io_imem_btb_update_bits_pc_T = ~io_imem_btb_update_bits_br_pc_0; // @[RocketCore.scala:153:7, :1080:35] wire [38:0] _io_imem_btb_update_bits_pc_T_1 = {_io_imem_btb_update_bits_pc_T[38:2], 2'h3}; // @[RocketCore.scala:1080:{35,66}] assign _io_imem_btb_update_bits_pc_T_2 = ~_io_imem_btb_update_bits_pc_T_1; // @[RocketCore.scala:1080:{33,66}] assign io_imem_btb_update_bits_pc_0 = _io_imem_btb_update_bits_pc_T_2; // @[RocketCore.scala:153:7, :1080:33] wire _io_imem_bht_update_valid_T = ~take_pc_wb; // @[RocketCore.scala:304:24, :706:34, :1084:48] assign _io_imem_bht_update_valid_T_1 = mem_reg_valid & _io_imem_bht_update_valid_T; // @[RocketCore.scala:265:36, :1084:{45,48}] assign io_imem_bht_update_valid_0 = _io_imem_bht_update_valid_T_1; // @[RocketCore.scala:153:7, :1084:45] wire _io_fpu_valid_T = ~ctrl_killd; // @[RocketCore.scala:338:24, :525:19, :1094:19] assign _io_fpu_valid_T_1 = _io_fpu_valid_T & id_ctrl_fp; // @[RocketCore.scala:321:21, :1094:{19,31}] assign io_fpu_valid_0 = _io_fpu_valid_T_1; // @[RocketCore.scala:153:7, :1094:31] assign _io_fpu_ll_resp_val_T = dmem_resp_valid & dmem_resp_fpu; // @[RocketCore.scala:766:45, :768:44, :1099:41] assign io_fpu_ll_resp_val_0 = _io_fpu_ll_resp_val_T; // @[RocketCore.scala:153:7, :1099:41] assign io_fpu_ll_resp_type_0 = {1'h0, io_dmem_resp_bits_size_0}; // @[RocketCore.scala:153:7, :1101:23] assign _io_fpu_keep_clock_enabled_T = io_ptw_customCSRs_csrs_0_value_0[2]; // @[CustomCSRs.scala:45:59] assign io_fpu_keep_clock_enabled_0 = _io_fpu_keep_clock_enabled_T; // @[CustomCSRs.scala:45:59] assign _io_dmem_req_valid_T = ex_reg_valid & ex_ctrl_mem; // @[RocketCore.scala:243:20, :248:35, :1130:41] assign io_dmem_req_valid_0 = _io_dmem_req_valid_T; // @[RocketCore.scala:153:7, :1130:41] wire [5:0] ex_dcache_tag = {ex_waddr, ex_ctrl_fp}; // @[RocketCore.scala:243:20, :453:36, :1131:26] assign io_dmem_req_bits_tag_0 = {1'h0, ex_dcache_tag}; // @[RocketCore.scala:153:7, :1131:26, :1133:25] wire _io_dmem_req_bits_signed_T_1 = ex_reg_inst[14]; // @[RocketCore.scala:259:24, :1136:75] wire _io_dmem_req_bits_signed_T_2 = _io_dmem_req_bits_signed_T_1; // @[RocketCore.scala:1136:{34,75}] assign _io_dmem_req_bits_signed_T_3 = ~_io_dmem_req_bits_signed_T_2; // @[RocketCore.scala:1136:{30,34}] assign io_dmem_req_bits_signed_0 = _io_dmem_req_bits_signed_T_3; // @[RocketCore.scala:153:7, :1136:30] wire [24:0] _io_dmem_req_bits_addr_a_T = ex_rs_0[63:39]; // @[RocketCore.scala:469:14, :1293:17] wire [24:0] io_dmem_req_bits_addr_a = _io_dmem_req_bits_addr_a_T; // @[RocketCore.scala:1293:{17,23}] wire _io_dmem_req_bits_addr_msb_T = io_dmem_req_bits_addr_a == 25'h0; // @[RocketCore.scala:1293:23, :1294:21] wire _io_dmem_req_bits_addr_msb_T_1 = &io_dmem_req_bits_addr_a; // @[RocketCore.scala:1293:23, :1294:34] wire _io_dmem_req_bits_addr_msb_T_2 = _io_dmem_req_bits_addr_msb_T \| _io_dmem_req_bits_addr_msb_T_1; // @[RocketCore.scala:1294:{21,29,34}] wire _io_dmem_req_bits_addr_msb_T_3 = _alu_io_adder_out[39]; // @[RocketCore.scala:504:19, :1294:46] wire _io_dmem_req_bits_addr_msb_T_4 = _alu_io_adder_out[38]; // @[RocketCore.scala:504:19, :1294:54] wire _io_dmem_req_bits_addr_msb_T_5 = ~_io_dmem_req_bits_addr_msb_T_4; // @[RocketCore.scala:1294:{51,54}] wire io_dmem_req_bits_addr_msb = _io_dmem_req_bits_addr_msb_T_2 ? _io_dmem_req_bits_addr_msb_T_3 : _io_dmem_req_bits_addr_msb_T_5; // @[RocketCore.scala:1294:{18,29,46,51}] wire [38:0] _io_dmem_req_bits_addr_T = _alu_io_adder_out[38:0]; // @[RocketCore.scala:504:19, :1295:16] assign _io_dmem_req_bits_addr_T_1 = {io_dmem_req_bits_addr_msb, _io_dmem_req_bits_addr_T}; // @[RocketCore.scala:1294:18, :1295:{8,16}] assign io_dmem_req_bits_addr_0 = _io_dmem_req_bits_addr_T_1; // @[RocketCore.scala:153:7, :1295:8] assign io_dmem_req_bits_dprv_0 = _io_dmem_req_bits_dprv_T; // @[RocketCore.scala:153:7, :1140:31] assign io_dmem_req_bits_dv_0 = _io_dmem_req_bits_dv_T; // @[RocketCore.scala:153:7, :1141:37] wire _io_dmem_req_bits_no_resp_T_4 = _io_dmem_req_bits_no_resp_T \| _io_dmem_req_bits_no_resp_T_1; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_5 = _io_dmem_req_bits_no_resp_T_4 \| _io_dmem_req_bits_no_resp_T_2; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_6 = _io_dmem_req_bits_no_resp_T_5 \| _io_dmem_req_bits_no_resp_T_3; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_11 = _io_dmem_req_bits_no_resp_T_7 \| _io_dmem_req_bits_no_resp_T_8; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_12 = _io_dmem_req_bits_no_resp_T_11 \| _io_dmem_req_bits_no_resp_T_9; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_13 = _io_dmem_req_bits_no_resp_T_12 \| _io_dmem_req_bits_no_resp_T_10; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_19 = _io_dmem_req_bits_no_resp_T_14 \| _io_dmem_req_bits_no_resp_T_15; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_20 = _io_dmem_req_bits_no_resp_T_19 \| _io_dmem_req_bits_no_resp_T_16; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_21 = _io_dmem_req_bits_no_resp_T_20 \| _io_dmem_req_bits_no_resp_T_17; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_22 = _io_dmem_req_bits_no_resp_T_21 \| _io_dmem_req_bits_no_resp_T_18; // @[package.scala:16:47, :81:59] wire _io_dmem_req_bits_no_resp_T_23 = _io_dmem_req_bits_no_resp_T_13 \| _io_dmem_req_bits_no_resp_T_22; // @[package.scala:81:59] wire _io_dmem_req_bits_no_resp_T_24 = _io_dmem_req_bits_no_resp_T_6 \| _io_dmem_req_bits_no_resp_T_23; // @[package.scala:81:59] wire _io_dmem_req_bits_no_resp_T_25 = ~_io_dmem_req_bits_no_resp_T_24; // @[RocketCore.scala:1142:31] wire _io_dmem_req_bits_no_resp_T_26 = ~ex_ctrl_fp; // @[RocketCore.scala:243:20, :1142:60] wire _io_dmem_req_bits_no_resp_T_27 = ex_waddr == 5'h0; // @[RocketCore.scala:453:36, :1142:84] wire _io_dmem_req_bits_no_resp_T_28 = _io_dmem_req_bits_no_resp_T_26 & _io_dmem_req_bits_no_resp_T_27; // @[RocketCore.scala:1142:{60,72,84}] assign _io_dmem_req_bits_no_resp_T_29 = _io_dmem_req_bits_no_resp_T_25 \| _io_dmem_req_bits_no_resp_T_28; // @[RocketCore.scala:1142:{31,56,72}] assign io_dmem_req_bits_no_resp_0 = _io_dmem_req_bits_no_resp_T_29; // @[RocketCore.scala:153:7, :1142:56] assign _io_dmem_s1_data_data_T = mem_ctrl_fp ? io_fpu_store_data_0 : mem_reg_rs2; // @[RocketCore.scala:153:7, :244:21, :283:24, :1148:63] assign io_dmem_s1_data_data_0 = _io_dmem_s1_data_data_T; // @[RocketCore.scala:153:7, :1148:63] wire _io_dmem_s1_kill_T = killm_common \| mem_ldst_xcpt; // @[RocketCore.scala:700:68, :1151:35, :1278:14] wire _io_dmem_s1_kill_T_1 = _io_dmem_s1_kill_T \| fpu_kill_mem; // @[RocketCore.scala:696:51, :1151:{35,52}] assign _io_dmem_s1_kill_T_2 = _io_dmem_s1_kill_T_1; // @[RocketCore.scala:1151:{52,68}] assign io_dmem_s1_kill_0 = _io_dmem_s1_kill_T_2; // @[RocketCore.scala:153:7, :1151:68] wire _io_dmem_keep_clock_enabled_T = _ibuf_io_inst_0_valid & id_ctrl_mem; // @[RocketCore.scala:311:20, :321:21, :1154:55] wire _io_dmem_keep_clock_enabled_T_1 = ~_csr_io_csr_stall; // @[RocketCore.scala:341:19, :1154:73] assign _io_dmem_keep_clock_enabled_T_2 = _io_dmem_keep_clock_enabled_T & _io_dmem_keep_clock_enabled_T_1; // @[RocketCore.scala:1154:{55,70,73}] assign io_dmem_keep_clock_enabled_0 = _io_dmem_keep_clock_enabled_T_2; // @[RocketCore.scala:153:7, :1154:70] wire _io_rocc_cmd_valid_T_1 = ~replay_wb_common; // @[RocketCore.scala:757:42, :1059:47, :1156:56] assign _io_rocc_cmd_valid_T_2 = _io_rocc_cmd_valid_T & _io_rocc_cmd_valid_T_1; // @[RocketCore.scala:1156:{37,53,56}] assign io_rocc_cmd_valid = _io_rocc_cmd_valid_T_2; // @[RocketCore.scala:153:7, :1156:53] wire [6:0] _io_rocc_cmd_bits_inst_T_7; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_funct = _io_rocc_cmd_bits_inst_WIRE_funct; // @[RocketCore.scala:153:7, :1159:48] wire [4:0] _io_rocc_cmd_bits_inst_T_6; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_rs2 = _io_rocc_cmd_bits_inst_WIRE_rs2; // @[RocketCore.scala:153:7, :1159:48] wire [4:0] _io_rocc_cmd_bits_inst_T_5; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_rs1 = _io_rocc_cmd_bits_inst_WIRE_rs1; // @[RocketCore.scala:153:7, :1159:48] wire _io_rocc_cmd_bits_inst_T_4; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_xd = _io_rocc_cmd_bits_inst_WIRE_xd; // @[RocketCore.scala:153:7, :1159:48] wire _io_rocc_cmd_bits_inst_T_3; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_xs1 = _io_rocc_cmd_bits_inst_WIRE_xs1; // @[RocketCore.scala:153:7, :1159:48] wire _io_rocc_cmd_bits_inst_T_2; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_xs2 = _io_rocc_cmd_bits_inst_WIRE_xs2; // @[RocketCore.scala:153:7, :1159:48] wire [4:0] _io_rocc_cmd_bits_inst_T_1; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_rd = _io_rocc_cmd_bits_inst_WIRE_rd; // @[RocketCore.scala:153:7, :1159:48] wire [6:0] _io_rocc_cmd_bits_inst_T; // @[RocketCore.scala:1159:48] assign io_rocc_cmd_bits_inst_opcode = _io_rocc_cmd_bits_inst_WIRE_opcode; // @[RocketCore.scala:153:7, :1159:48] assign _io_rocc_cmd_bits_inst_T = _io_rocc_cmd_bits_inst_WIRE_1[6:0]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_opcode = _io_rocc_cmd_bits_inst_T; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_1 = _io_rocc_cmd_bits_inst_WIRE_1[11:7]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_rd = _io_rocc_cmd_bits_inst_T_1; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_2 = _io_rocc_cmd_bits_inst_WIRE_1[12]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_xs2 = _io_rocc_cmd_bits_inst_T_2; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_3 = _io_rocc_cmd_bits_inst_WIRE_1[13]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_xs1 = _io_rocc_cmd_bits_inst_T_3; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_4 = _io_rocc_cmd_bits_inst_WIRE_1[14]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_xd = _io_rocc_cmd_bits_inst_T_4; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_5 = _io_rocc_cmd_bits_inst_WIRE_1[19:15]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_rs1 = _io_rocc_cmd_bits_inst_T_5; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_6 = _io_rocc_cmd_bits_inst_WIRE_1[24:20]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_rs2 = _io_rocc_cmd_bits_inst_T_6; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_T_7 = _io_rocc_cmd_bits_inst_WIRE_1[31:25]; // @[RocketCore.scala:1159:48] assign _io_rocc_cmd_bits_inst_WIRE_funct = _io_rocc_cmd_bits_inst_T_7; // @[RocketCore.scala:1159:48] wire [4:0] _unpause_T = _csr_io_time[4:0]; // @[RocketCore.scala:341:19, :1164:28] wire _unpause_T_1 = _unpause_T == 5'h0; // @[RocketCore.scala:1164:{28,62}] wire _unpause_T_2 = _unpause_T_1 \| _csr_io_inhibit_cycle; // @[RocketCore.scala:341:19, :1164:{62,70}] wire _unpause_T_3 = _unpause_T_2 \| io_dmem_perf_release_0; // @[RocketCore.scala:153:7, :1164:{70,94}] wire unpause = _unpause_T_3 \| take_pc_mem_wb; // @[RocketCore.scala:307:35, :1164:{94,118}] reg icache_blocked_REG; // @[RocketCore.scala:1183:55] wire _icache_blocked_T = io_imem_resp_valid_0 \| icache_blocked_REG; // @[RocketCore.scala:153:7, :1183:{45,55}] wire icache_blocked = ~_icache_blocked_T; // @[RocketCore.scala:1183:{24,45}] wire _coreMonitorBundle_valid_T_1; // @[RocketCore.scala:1192:52] wire [63:0] _coreMonitorBundle_pc_T_3; // @[package.scala:132:15] wire _coreMonitorBundle_wrenx_T_1; // @[RocketCore.scala:1194:37] wire [4:0] _coreMonitorBundle_rd0src_T; // @[RocketCore.scala:1198:42] wire [4:0] _coreMonitorBundle_rd1src_T; // @[RocketCore.scala:1200:42] wire coreMonitorBundle_excpt; // @[RocketCore.scala:1186:31] wire [2:0] coreMonitorBundle_priv_mode; // @[RocketCore.scala:1186:31] wire [63:0] coreMonitorBundle_hartid; // @[RocketCore.scala:1186:31] wire [31:0] coreMonitorBundle_timer; // @[RocketCore.scala:1186:31] wire coreMonitorBundle_valid; // @[RocketCore.scala:1186:31] wire [63:0] coreMonitorBundle_pc; // @[RocketCore.scala:1186:31] wire coreMonitorBundle_wrenx; // @[RocketCore.scala:1186:31] wire [4:0] coreMonitorBundle_rd0src; // @[RocketCore.scala:1186:31] wire [63:0] coreMonitorBundle_rd0val; // @[RocketCore.scala:1186:31] wire [4:0] coreMonitorBundle_rd1src; // @[RocketCore.scala:1186:31] wire [63:0] coreMonitorBundle_rd1val; // @[RocketCore.scala:1186:31] wire [31:0] coreMonitorBundle_inst; // @[RocketCore.scala:1186:31] wire [63:0] _GEN_71 = {61'h0, io_hartid_0}; // @[RocketCore.scala:153:7, :1190:28] assign coreMonitorBundle_hartid = _GEN_71; // @[RocketCore.scala:1186:31, :1190:28] wire [63:0] xrfWriteBundle_hartid; // @[RocketCore.scala:1249:28] assign xrfWriteBundle_hartid = _GEN_71; // @[RocketCore.scala:1190:28, :1249:28] assign coreMonitorBundle_timer = _coreMonitorBundle_timer_T; // @[RocketCore.scala:1186:31, :1191:41] wire _coreMonitorBundle_valid_T = ~_csr_io_trace_0_exception; // @[RocketCore.scala:341:19, :1192:55] assign _coreMonitorBundle_valid_T_1 = _csr_io_trace_0_valid & _coreMonitorBundle_valid_T; // @[RocketCore.scala:341:19, :1192:{52,55}] assign coreMonitorBundle_valid = _coreMonitorBundle_valid_T_1; // @[RocketCore.scala:1186:31, :1192:52] wire [39:0] _coreMonitorBundle_pc_T; // @[RocketCore.scala:1193:48] wire _coreMonitorBundle_pc_T_1 = _coreMonitorBundle_pc_T[39]; // @[package.scala:132:38] wire [23:0] _coreMonitorBundle_pc_T_2 = {24{_coreMonitorBundle_pc_T_1}}; // @[package.scala:132:{20,38}] assign _coreMonitorBundle_pc_T_3 = {_coreMonitorBundle_pc_T_2, _coreMonitorBundle_pc_T}; // @[package.scala:132:{15,20}] assign coreMonitorBundle_pc = _coreMonitorBundle_pc_T_3; // @[package.scala:132:15] wire _coreMonitorBundle_wrenx_T = ~wb_set_sboard; // @[RocketCore.scala:756:69, :1194:40] assign _coreMonitorBundle_wrenx_T_1 = wb_wen & _coreMonitorBundle_wrenx_T; // @[RocketCore.scala:816:25, :1194:{37,40}] assign coreMonitorBundle_wrenx = _coreMonitorBundle_wrenx_T_1; // @[RocketCore.scala:1186:31, :1194:37] assign _coreMonitorBundle_rd0src_T = wb_reg_inst[19:15]; // @[RocketCore.scala:300:24, :1198:42] assign coreMonitorBundle_rd0src = _coreMonitorBundle_rd0src_T; // @[RocketCore.scala:1186:31, :1198:42] reg [63:0] coreMonitorBundle_rd0val_REG; // @[RocketCore.scala:1199:46] reg [63:0] coreMonitorBundle_rd0val_REG_1; // @[RocketCore.scala:1199:38] assign coreMonitorBundle_rd0val = coreMonitorBundle_rd0val_REG_1; // @[RocketCore.scala:1186:31, :1199:38] assign _coreMonitorBundle_rd1src_T = wb_reg_inst[24:20]; // @[RocketCore.scala:300:24, :1200:42] assign coreMonitorBundle_rd1src = _coreMonitorBundle_rd1src_T; // @[RocketCore.scala:1186:31, :1200:42] reg [63:0] coreMonitorBundle_rd1val_REG; // @[RocketCore.scala:1201:46] reg [63:0] coreMonitorBundle_rd1val_REG_1; // @[RocketCore.scala:1201:38] assign coreMonitorBundle_rd1val = coreMonitorBundle_rd1val_REG_1; // @[RocketCore.scala:1186:31, :1201:38]
Generate the Verilog code corresponding to the following Chisel files. File Monitor.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceLine import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import freechips.rocketchip.diplomacy.EnableMonitors import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode} import freechips.rocketchip.util.PlusArg case class TLMonitorArgs(edge: TLEdge) abstract class TLMonitorBase(args: TLMonitorArgs) extends Module { val io = IO(new Bundle { val in = Input(new TLBundle(args.edge.bundle)) }) def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit legalize(io.in, args.edge, reset) } object TLMonitor { def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = { if (enable) { EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) } } else { node } } } class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args) { require (args.edge.params(TLMonitorStrictMode) \|\| (! args.edge.params(TestplanTestType).formal)) val cover_prop_class = PropertyClass.Default //Like assert but can flip to being an assumption for formal verification def monAssert(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir, cond, message, PropertyClass.Default) } def assume(cond: Bool, message: String): Unit = if (monitorDir == MonitorDirection.Monitor) { assert(cond, message) } else { Property(monitorDir.flip, cond, message, PropertyClass.Default) } def extra = { args.edge.sourceInfo match { case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)" case _ => "" } } def visible(address: UInt, source: UInt, edge: TLEdge) = edge.client.clients.map { c => !c.sourceId.contains(source) \|\| c.visibility.map(_.contains(address)).reduce(_ \|\| _) }.reduce(_ && _) def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = { //switch this flag to turn on diplomacy in error messages def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n" monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra) // Reuse these subexpressions to save some firrtl lines val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility") //The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B //TODO: check for acquireT? when (bundle.opcode === TLMessages.AcquireBlock) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra) } when (bundle.opcode === TLMessages.AcquirePerm) { monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra) monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra) monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra) monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra) monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra) monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra) monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra) monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra) monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra) monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra) } } def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = { monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra) monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility") // Reuse these subexpressions to save some firrtl lines val address_ok = edge.manager.containsSafe(edge.address(bundle)) val is_aligned = edge.isAligned(bundle.address, bundle.size) val mask = edge.full_mask(bundle) val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source when (bundle.opcode === TLMessages.Probe) { assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra) assume (address_ok, "'B' channel Probe carries unmanaged address" + extra) assume (legal_source, "'B' channel Probe carries source that is not first source" + extra) assume (is_aligned, "'B' channel Probe address not aligned to size" + extra) assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra) assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra) assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra) } when (bundle.opcode === TLMessages.Get) { monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra) } when (bundle.opcode === TLMessages.PutFullData) { monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra) monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra) } when (bundle.opcode === TLMessages.PutPartialData) { monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra) monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra) monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra) monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra) } when (bundle.opcode === TLMessages.ArithmeticData) { monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra) monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra) monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra) } when (bundle.opcode === TLMessages.LogicalData) { monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra) monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra) monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra) monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra) } when (bundle.opcode === TLMessages.Hint) { monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra) monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra) monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra) monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra) monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra) monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra) } } def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = { monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val is_aligned = edge.isAligned(bundle.address, bundle.size) val address_ok = edge.manager.containsSafe(edge.address(bundle)) monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility") when (bundle.opcode === TLMessages.ProbeAck) { monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra) } when (bundle.opcode === TLMessages.ProbeAckData) { monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.Release) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra) monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra) monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra) } when (bundle.opcode === TLMessages.ReleaseData) { monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra) monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra) monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra) monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra) monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra) monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra) } when (bundle.opcode === TLMessages.AccessAck) { monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra) monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra) } when (bundle.opcode === TLMessages.HintAck) { monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra) monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra) monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra) monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra) monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra) } } def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = { assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra) val source_ok = edge.client.contains(bundle.source) val sink_ok = bundle.sink < edge.manager.endSinkId.U val deny_put_ok = edge.manager.mayDenyPut.B val deny_get_ok = edge.manager.mayDenyGet.B when (bundle.opcode === TLMessages.ReleaseAck) { assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra) assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra) assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra) } when (bundle.opcode === TLMessages.Grant) { assume (source_ok, "'D' channel Grant carries invalid source ID" + extra) assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra) assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel Grant is denied" + extra) } when (bundle.opcode === TLMessages.GrantData) { assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra) assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra) assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra) assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra) assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel GrantData is denied" + extra) } when (bundle.opcode === TLMessages.AccessAck) { assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel AccessAck is denied" + extra) } when (bundle.opcode === TLMessages.AccessAckData) { assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra) assume (!bundle.denied \|\| bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra) assume (deny_get_ok \|\| !bundle.denied, "'D' channel AccessAckData is denied" + extra) } when (bundle.opcode === TLMessages.HintAck) { assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra) // size is ignored assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra) assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra) assume (deny_put_ok \|\| !bundle.denied, "'D' channel HintAck is denied" + extra) } } def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = { val sink_ok = bundle.sink < edge.manager.endSinkId.U monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra) } def legalizeFormat(bundle: TLBundle, edge: TLEdge) = { when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) } when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) } when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) } when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) } } else { monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra) monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra) monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra) } } def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = { val a_first = edge.first(a.bits, a.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (a.valid && !a_first) { monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra) monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra) monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra) monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra) monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra) } when (a.fire && a_first) { opcode := a.bits.opcode param := a.bits.param size := a.bits.size source := a.bits.source address := a.bits.address } } def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = { val b_first = edge.first(b.bits, b.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (b.valid && !b_first) { monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra) monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra) monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra) monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra) monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra) } when (b.fire && b_first) { opcode := b.bits.opcode param := b.bits.param size := b.bits.size source := b.bits.source address := b.bits.address } } def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = { // Symbolic variable val sym_source = Wire(UInt(edge.client.endSourceId.W)) // TODO: Connect sym_source to a fixed value for simulation and to a // free wire in formal sym_source := 0.U // Type casting Int to UInt val maxSourceId = Wire(UInt(edge.client.endSourceId.W)) maxSourceId := edge.client.endSourceId.U // Delayed verison of sym_source val sym_source_d = Reg(UInt(edge.client.endSourceId.W)) sym_source_d := sym_source // These will be constraints for FV setup Property( MonitorDirection.Monitor, (sym_source === sym_source_d), "sym_source should remain stable", PropertyClass.Default) Property( MonitorDirection.Monitor, (sym_source <= maxSourceId), "sym_source should take legal value", PropertyClass.Default) val my_resp_pend = RegInit(false.B) val my_opcode = Reg(UInt()) val my_size = Reg(UInt()) val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire) val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire) val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source) val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source) val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat) val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend) when (my_set_resp_pend) { my_resp_pend := true.B } .elsewhen (my_clr_resp_pend) { my_resp_pend := false.B } when (my_a_first_beat) { my_opcode := bundle.a.bits.opcode my_size := bundle.a.bits.size } val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size) val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode) val my_resp_opcode_legal = Wire(Bool()) when ((my_resp_opcode === TLMessages.Get) \|\| (my_resp_opcode === TLMessages.ArithmeticData) \|\| (my_resp_opcode === TLMessages.LogicalData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData) } .elsewhen ((my_resp_opcode === TLMessages.PutFullData) \|\| (my_resp_opcode === TLMessages.PutPartialData)) { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck) } .otherwise { my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck) } monAssert (IfThen(my_resp_pend, !my_a_first_beat), "Request message should not be sent with a source ID, for which a response message" + "is already pending (not received until current cycle) for a prior request message" + "with the same source ID" + extra) assume (IfThen(my_clr_resp_pend, (my_set_resp_pend \|\| my_resp_pend)), "Response message should be accepted with a source ID only if a request message with the" + "same source ID has been accepted or is being accepted in the current cycle" + extra) assume (IfThen(my_d_first_beat, (my_a_first_beat \|\| my_resp_pend)), "Response message should be sent with a source ID only if a request message with the" + "same source ID has been accepted or is being sent in the current cycle" + extra) assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)), "If d_valid is 1, then d_size should be same as a_size of the corresponding request" + "message" + extra) assume (IfThen(my_d_first_beat, my_resp_opcode_legal), "If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" + "request message" + extra) } def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = { val c_first = edge.first(c.bits, c.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val address = Reg(UInt()) when (c.valid && !c_first) { monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra) monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra) monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra) monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra) monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra) } when (c.fire && c_first) { opcode := c.bits.opcode param := c.bits.param size := c.bits.size source := c.bits.source address := c.bits.address } } def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = { val d_first = edge.first(d.bits, d.fire) val opcode = Reg(UInt()) val param = Reg(UInt()) val size = Reg(UInt()) val source = Reg(UInt()) val sink = Reg(UInt()) val denied = Reg(Bool()) when (d.valid && !d_first) { assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra) assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra) assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra) assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra) assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra) assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra) } when (d.fire && d_first) { opcode := d.bits.opcode param := d.bits.param size := d.bits.size source := d.bits.source sink := d.bits.sink denied := d.bits.denied } } def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = { legalizeMultibeatA(bundle.a, edge) legalizeMultibeatD(bundle.d, edge) if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { legalizeMultibeatB(bundle.b, edge) legalizeMultibeatC(bundle.c, edge) } } //This is left in for almond which doesn't adhere to the tilelink protocol @deprecated("Use legalizeADSource instead if possible","") def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.client.endSourceId.W)) val a_first = edge.first(bundle.a.bits, bundle.a.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val a_set = WireInit(0.U(edge.client.endSourceId.W)) when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) assume((a_set \| inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra) } if (edge.manager.minLatency > 0) { assume(a_set =/= d_clr \|\| !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") assert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = { val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size) val log_a_size_bus_size = log2Ceil(a_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error inflight.suggestName("inflight") val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) inflight_opcodes.suggestName("inflight_opcodes") val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) inflight_sizes.suggestName("inflight_sizes") val a_first = edge.first(bundle.a.bits, bundle.a.fire) a_first.suggestName("a_first") val d_first = edge.first(bundle.d.bits, bundle.d.fire) d_first.suggestName("d_first") val a_set = WireInit(0.U(edge.client.endSourceId.W)) val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) a_set.suggestName("a_set") a_set_wo_ready.suggestName("a_set_wo_ready") val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) a_opcodes_set.suggestName("a_opcodes_set") val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) a_sizes_set.suggestName("a_sizes_set") val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W)) a_opcode_lookup.suggestName("a_opcode_lookup") a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W)) a_size_lookup.suggestName("a_size_lookup") a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant)) val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant)) val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W)) a_opcodes_set_interm.suggestName("a_opcodes_set_interm") val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W)) a_sizes_set_interm.suggestName("a_sizes_set_interm") when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) { a_set_wo_ready := UIntToOH(bundle.a.bits.source) } when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) { a_set := UIntToOH(bundle.a.bits.source) a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) \| 1.U a_sizes_set_interm := (bundle.a.bits.size << 1.U) \| 1.U a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U) a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U) monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra) } val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W)) d_opcodes_clr.suggestName("d_opcodes_clr") val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W)) d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) { val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra) assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) \|\| (bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra) assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) { assume((!bundle.d.ready) \|\| bundle.a.ready, "ready check") } if (edge.manager.minLatency > 0) { assume(a_set_wo_ready =/= d_clr_wo_ready \|\| !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra) } inflight := (inflight \| a_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| a_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| a_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.a.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = { val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset) val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size) val log_c_size_bus_size = log2Ceil(c_size_bus_size) def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) inflight.suggestName("inflight") inflight_opcodes.suggestName("inflight_opcodes") inflight_sizes.suggestName("inflight_sizes") val c_first = edge.first(bundle.c.bits, bundle.c.fire) val d_first = edge.first(bundle.d.bits, bundle.d.fire) c_first.suggestName("c_first") d_first.suggestName("d_first") val c_set = WireInit(0.U(edge.client.endSourceId.W)) val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) c_set.suggestName("c_set") c_set_wo_ready.suggestName("c_set_wo_ready") c_opcodes_set.suggestName("c_opcodes_set") c_sizes_set.suggestName("c_sizes_set") val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W)) val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W)) c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U c_opcode_lookup.suggestName("c_opcode_lookup") c_size_lookup.suggestName("c_size_lookup") val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W)) val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W)) c_opcodes_set_interm.suggestName("c_opcodes_set_interm") c_sizes_set_interm.suggestName("c_sizes_set_interm") when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) { c_set_wo_ready := UIntToOH(bundle.c.bits.source) } when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) { c_set := UIntToOH(bundle.c.bits.source) c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) \| 1.U c_sizes_set_interm := (bundle.c.bits.size << 1.U) \| 1.U c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U) c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U) monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra) } val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck \|\| bundle.c.bits.opcode === TLMessages.ProbeAckData val d_clr = WireInit(0.U(edge.client.endSourceId.W)) val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W)) val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W)) val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W)) d_clr.suggestName("d_clr") d_clr_wo_ready.suggestName("d_clr_wo_ready") d_opcodes_clr.suggestName("d_opcodes_clr") d_sizes_clr.suggestName("d_sizes_clr") val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr_wo_ready := UIntToOH(bundle.d.bits.source) } when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { d_clr := UIntToOH(bundle.d.bits.source) d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U) d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U) } when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) { val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source) assume(((inflight)(bundle.d.bits.source)) \|\| same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra) when (same_cycle_resp) { assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra) } .otherwise { assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra) } } when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) { assume((!bundle.d.ready) \|\| bundle.c.ready, "ready check") } if (edge.manager.minLatency > 0) { when (c_set_wo_ready.orR) { assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra) } } inflight := (inflight \| c_set) & ~d_clr inflight_opcodes := (inflight_opcodes \| c_opcodes_set) & ~d_opcodes_clr inflight_sizes := (inflight_sizes \| c_sizes_set) & ~d_sizes_clr val watchdog = RegInit(0.U(32.W)) val limit = PlusArg("tilelink_timeout", docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.") monAssert (!inflight.orR \|\| limit === 0.U \|\| watchdog < limit, "TileLink timeout expired" + extra) watchdog := watchdog + 1.U when (bundle.c.fire \|\| bundle.d.fire) { watchdog := 0.U } } def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = { val inflight = RegInit(0.U(edge.manager.endSinkId.W)) val d_first = edge.first(bundle.d.bits, bundle.d.fire) val e_first = true.B val d_set = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) { d_set := UIntToOH(bundle.d.bits.sink) assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra) } val e_clr = WireInit(0.U(edge.manager.endSinkId.W)) when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) { e_clr := UIntToOH(bundle.e.bits.sink) monAssert((d_set \| inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra) } // edge.client.minLatency applies to BC, not DE inflight := (inflight \| d_set) & ~e_clr } def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = { val sourceBits = log2Ceil(edge.client.endSourceId) val tooBig = 14 // >16kB worth of flight information gets to be too much if (sourceBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked") } else { if (args.edge.params(TestplanTestType).simulation) { if (args.edge.params(TLMonitorStrictMode)) { legalizeADSource(bundle, edge) legalizeCDSource(bundle, edge) } else { legalizeADSourceOld(bundle, edge) } } if (args.edge.params(TestplanTestType).formal) { legalizeADSourceFormal(bundle, edge) } } if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) { // legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize... val sinkBits = log2Ceil(edge.manager.endSinkId) if (sinkBits > tooBig) { println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked") } else { legalizeDESink(bundle, edge) } } } def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = { legalizeFormat (bundle, edge) legalizeMultibeat (bundle, edge) legalizeUnique (bundle, edge) } } File Misc.scala: // See LICENSE.Berkeley for license details. // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util._ import chisel3.util.random.LFSR import org.chipsalliance.cde.config.Parameters import scala.math._ class ParameterizedBundle(implicit p: Parameters) extends Bundle trait Clocked extends Bundle { val clock = Clock() val reset = Bool() } object DecoupledHelper { def apply(rvs: Bool) = new DecoupledHelper(rvs) } class DecoupledHelper(val rvs: Seq[Bool]) { def fire(exclude: Bool, includes: Bool) = { require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!") (rvs.filter(_ ne exclude) ++ includes).reduce(_ && _) } def fire() = { rvs.reduce(_ && _) } } object MuxT { def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2)) def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3)) def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) = (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4)) } /** Creates a cascade of n MuxTs to search for a key value. / object MuxTLookup { def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = { var res = default for ((k, v) <- mapping.reverse) res = MuxT(k === key, v, res) res } } object ValidMux { def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]): ValidIO[T] = { apply(v1 +: v2.toSeq) } def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = { val out = Wire(Valid(valids.head.bits.cloneType)) out.valid := valids.map(_.valid).reduce(_ \|\| _) out.bits := MuxCase(valids.head.bits, valids.map(v => (v.valid -> v.bits))) out } } object Str { def apply(s: String): UInt = { var i = BigInt(0) require(s.forall(validChar _)) for (c <- s) i = (i << 8) \| c i.U((s.length8).W) } def apply(x: Char): UInt = { require(validChar(x)) x.U(8.W) } def apply(x: UInt): UInt = apply(x, 10) def apply(x: UInt, radix: Int): UInt = { val rad = radix.U val w = x.getWidth require(w > 0) var q = x var s = digit(q % rad) for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s) } s } def apply(x: SInt): UInt = apply(x, 10) def apply(x: SInt, radix: Int): UInt = { val neg = x < 0.S val abs = x.abs.asUInt if (radix != 10) { Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix)) } else { val rad = radix.U val w = abs.getWidth require(w > 0) var q = abs var s = digit(q % rad) var needSign = neg for (i <- 1 until ceil(log(2)/log(radix)w).toInt) { q = q / rad val placeSpace = q === 0.U val space = Mux(needSign, Str('-'), Str(' ')) needSign = needSign && !placeSpace s = Cat(Mux(placeSpace, space, digit(q % rad)), s) } Cat(Mux(needSign, Str('-'), Str(' ')), s) } } private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0) private def validChar(x: Char) = x == (x & 0xFF) } object Split { def apply(x: UInt, n0: Int) = { val w = x.getWidth (x.extract(w-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } def apply(x: UInt, n2: Int, n1: Int, n0: Int) = { val w = x.getWidth (x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0)) } } object Random { def apply(mod: Int, random: UInt): UInt = { if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0) else PriorityEncoder(partition(apply(1 << log2Up(mod8), random), mod)) } def apply(mod: Int): UInt = apply(mod, randomizer) def oneHot(mod: Int, random: UInt): UInt = { if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0)) else PriorityEncoderOH(partition(apply(1 << log2Up(mod8), random), mod)).asUInt } def oneHot(mod: Int): UInt = oneHot(mod, randomizer) private def randomizer = LFSR(16) private def partition(value: UInt, slices: Int) = Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U) } object Majority { def apply(in: Set[Bool]): Bool = { val n = (in.size >> 1) + 1 val clauses = in.subsets(n).map(_.reduce(_ && _)) clauses.reduce(_ \|\| _) } def apply(in: Seq[Bool]): Bool = apply(in.toSet) def apply(in: UInt): Bool = apply(in.asBools.toSet) } object PopCountAtLeast { private def two(x: UInt): (Bool, Bool) = x.getWidth match { case 1 => (x.asBool, false.B) case n => val half = x.getWidth / 2 val (leftOne, leftTwo) = two(x(half - 1, 0)) val (rightOne, rightTwo) = two(x(x.getWidth - 1, half)) (leftOne \|\| rightOne, leftTwo \|\| rightTwo \|\| (leftOne && rightOne)) } def apply(x: UInt, n: Int): Bool = n match { case 0 => true.B case 1 => x.orR case 2 => two(x)._2 case 3 => PopCount(x) >= n.U } } // This gets used everywhere, so make the smallest circuit possible ... // Given an address and size, create a mask of beatBytes size // eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111 // groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01 object MaskGen { def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = { require (groupBy >= 1 && beatBytes >= groupBy) require (isPow2(beatBytes) && isPow2(groupBy)) val lgBytes = log2Ceil(beatBytes) val sizeOH = UIntToOH(lgSize \| 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) \| (groupBy2 - 1).U def helper(i: Int): Seq[(Bool, Bool)] = { if (i == 0) { Seq((lgSize >= lgBytes.asUInt, true.B)) } else { val sub = helper(i-1) val size = sizeOH(lgBytes - i) val bit = addr_lo(lgBytes - i) val nbit = !bit Seq.tabulate (1 << i) { j => val (sub_acc, sub_eq) = sub(j/2) val eq = sub_eq && (if (j % 2 == 1) bit else nbit) val acc = sub_acc \|\| (size && eq) (acc, eq) } } } if (groupBy == beatBytes) 1.U else Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse) } } File PlusArg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.experimental._ import chisel3.util.HasBlackBoxResource @deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05") case class PlusArgInfo(default: BigInt, docstring: String) /** Case class for PlusArg information * * @tparam A scala type of the PlusArg value * @param default optional default value * @param docstring text to include in the help * @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT) / private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String) /* Typeclass for converting a type to a doctype string * @tparam A some type / trait Doctypeable[A] { /* Return the doctype string for some option / def toDoctype(a: Option[A]): String } /* Object containing implementations of the Doctypeable typeclass / object Doctypes { /* Converts an Int => "INT" / implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" } /* Converts a BigInt => "INT" / implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" } /* Converts a String => "STRING" / implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" } } class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map( "FORMAT" -> StringParam(format), "DEFAULT" -> IntParam(default), "WIDTH" -> IntParam(width) )) with HasBlackBoxResource { val io = IO(new Bundle { val out = Output(UInt(width.W)) }) addResource("/vsrc/plusarg_reader.v") } / This wrapper class has no outputs, making it clear it is a simulation-only construct / class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module { val io = IO(new Bundle { val count = Input(UInt(width.W)) }) val max = Module(new plusarg_reader(format, default, docstring, width)).io.out when (max > 0.U) { assert (io.count < max, s"Timeout exceeded: $docstring") } } import Doctypes._ object PlusArg { /* PlusArg("foo") will return 42.U if the simulation is run with +foo=42 * Do not use this as an initial register value. The value is set in an * initial block and thus accessing it from another initial is racey. * Add a docstring to document the arg, which can be dumped in an elaboration * pass. / def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out } /* PlusArg.timeout(name, default, docstring)(count) will use chisel.assert * to kill the simulation when count exceeds the specified integer argument. * Default 0 will never assert. / def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = { PlusArgArtefacts.append(name, Some(default), docstring) Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count } } object PlusArgArtefacts { private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty / Add a new PlusArg / @deprecated( "Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05" ) def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring) /* Add a new PlusArg * * @tparam A scala type of the PlusArg value * @param name name for the PlusArg * @param default optional default value * @param docstring text to include in the help / def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit = artefacts = artefacts ++ Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default))) / From plus args, generate help text / private def serializeHelp_cHeader(tab: String = ""): String = artefacts .map{ case(arg, info) => s"""\|$tab+$arg=${info.doctype}\\n\\ \|$tab${" "20}${info.docstring}\\n\\ \|""".stripMargin ++ info.default.map{ case default => s"$tab${" "22}(default=${default})\\n\\\n"}.getOrElse("") }.toSeq.mkString("\\n\\\n") ++ "\"" / From plus args, generate a char array of their names / private def serializeArray_cHeader(tab: String = ""): String = { val prettyTab = tab + " " 44 // Length of 'static const ...' s"${tab}static const char * verilog_plusargs [] = {\\\n" ++ artefacts .map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" } .mkString("")++ s"${prettyTab}0};" } /* Generate C code to be included in emulator.cc that helps with * argument parsing based on available Verilog PlusArgs / def serialize_cHeader(): String = s"""\|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\ \|${serializeHelp_cHeader(" "7)} \|${serializeArray_cHeader()} \|""".stripMargin } File package.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip import chisel3._ import chisel3.util._ import scala.math.min import scala.collection.{immutable, mutable} package object util { implicit class UnzippableOption[S, T](val x: Option[(S, T)]) { def unzip = (x.map(_._1), x.map(_._2)) } implicit class UIntIsOneOf(private val x: UInt) extends AnyVal { def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR def isOneOf(u1: UInt, u2: UInt): Bool = isOneOf(u1 +: u2.toSeq) } implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal { /* Like Vec.apply(idx), but tolerates indices of mismatched width / def extract(idx: UInt): T = x((idx \| 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0)) } implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal { def apply(idx: UInt): T = { if (x.size <= 1) { x.head } else if (!isPow2(x.size)) { // For non-power-of-2 seqs, reflect elements to simplify decoder (x ++ x.takeRight(x.size & -x.size)).toSeq(idx) } else { // Ignore MSBs of idx val truncIdx = if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx else (idx \| 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0) x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) } } } def extract(idx: UInt): T = VecInit(x).extract(idx) def asUInt: UInt = Cat(x.map(_.asUInt).reverse) def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n) def rotate(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n) def rotateRight(n: UInt): Seq[T] = { if (x.size <= 1) { x } else { require(isPow2(x.size)) val amt = n.padTo(log2Ceil(x.size)) (0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) }) } } } // allow bitwise ops on Seq[Bool] just like UInt implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal { def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b } def \| (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a \|\| b } def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b } def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x def >> (n: Int): Seq[Bool] = x drop n def unary_~ : Seq[Bool] = x.map(!_) def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_) def orR: Bool = if (x.isEmpty) false.B else x.reduce(_\|\|_) def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_) private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B) } implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal { def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable)) def getElements: Seq[Element] = x match { case e: Element => Seq(e) case a: Aggregate => a.getElements.flatMap(_.getElements) } } /* Any Data subtype that has a Bool member named valid. / type DataCanBeValid = Data { val valid: Bool } implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal { def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable) } implicit class StringToAugmentedString(private val x: String) extends AnyVal { /* converts from camel case to to underscores, also removing all spaces / def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") { case (acc, c) if c.isUpper => acc + "_" + c.toLower case (acc, c) if c == ' ' => acc case (acc, c) => acc + c } /* converts spaces or underscores to hyphens, also lowering case / def kebab: String = x.toLowerCase map { case ' ' => '-' case '_' => '-' case c => c } def named(name: Option[String]): String = { x + name.map("_named_" + _ ).getOrElse("_with_no_name") } def named(name: String): String = named(Some(name)) } implicit def uintToBitPat(x: UInt): BitPat = BitPat(x) implicit def wcToUInt(c: WideCounter): UInt = c.value implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal { def sextTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x) } def padTo(n: Int): UInt = { require(x.getWidth <= n) if (x.getWidth == n) x else Cat(0.U((n - x.getWidth).W), x) } // shifts left by n if n >= 0, or right by -n if n < 0 def << (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << n(w-1, 0) Mux(n(w), shifted >> (1 << w), shifted) } // shifts right by n if n >= 0, or left by -n if n < 0 def >> (n: SInt): UInt = { val w = n.getWidth - 1 require(w <= 30) val shifted = x << (1 << w) >> n(w-1, 0) Mux(n(w), shifted, shifted >> (1 << w)) } // Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts def extract(hi: Int, lo: Int): UInt = { require(hi >= lo-1) if (hi == lo-1) 0.U else x(hi, lo) } // Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts def extractOption(hi: Int, lo: Int): Option[UInt] = { require(hi >= lo-1) if (hi == lo-1) None else Some(x(hi, lo)) } // like x & ~y, but first truncate or zero-extend y to x's width def andNot(y: UInt): UInt = x & ~(y \| (x & 0.U)) def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n) def rotateRight(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r)) } } def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n)) def rotateLeft(n: UInt): UInt = { if (x.getWidth <= 1) { x } else { val amt = n.padTo(log2Ceil(x.getWidth)) (0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r)) } } // compute (this + y) % n, given (this < n) and (y < n) def addWrap(y: UInt, n: Int): UInt = { val z = x +& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0) } // compute (this - y) % n, given (this < n) and (y < n) def subWrap(y: UInt, n: Int): UInt = { val z = x -& y if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0) } def grouped(width: Int): Seq[UInt] = (0 until x.getWidth by width).map(base => x(base + width - 1, base)) def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x) // Like >=, but prevents x-prop for ('x >= 0) def >== (y: UInt): Bool = x >= y \|\| y === 0.U } implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal { def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y) def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y) } implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal { def toInt: Int = if (x) 1 else 0 // this one's snagged from scalaz def option[T](z: => T): Option[T] = if (x) Some(z) else None } implicit class IntToAugmentedInt(private val x: Int) extends AnyVal { // exact log2 def log2: Int = { require(isPow2(x)) log2Ceil(x) } } def OH1ToOH(x: UInt): UInt = (x << 1 \| 1.U) & ~Cat(0.U(1.W), x) def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x)) def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0) def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1) def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None // Fill 1s from low bits to high bits def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth) def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x << s)(width-1,0)) helper(1, x)(width-1, 0) } // Fill 1s form high bits to low bits def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth) def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = { val stop = min(width, cap) def helper(s: Int, x: UInt): UInt = if (s >= stop) x else helper(s+s, x \| (x >> s)) helper(1, x)(width-1, 0) } def OptimizationBarrier[T <: Data](in: T): T = { val barrier = Module(new Module { val io = IO(new Bundle { val x = Input(chiselTypeOf(in)) val y = Output(chiselTypeOf(in)) }) io.y := io.x override def desiredName = s"OptimizationBarrier_${in.typeName}" }) barrier.io.x := in barrier.io.y } /* Similar to Seq.groupBy except this returns a Seq instead of a Map * Useful for deterministic code generation / def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = { val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]] for (x <- xs) { val key = f(x) val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A]) l += x } map.view.map({ case (k, vs) => k -> vs.toList }).toList } def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match { case 1 => List.fill(n)(in.head) case x if x == n => in case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in") } // HeterogeneousBag moved to standalond diplomacy @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts) @deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0") val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag } File Parameters.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.diplomacy import chisel3._ import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor} import freechips.rocketchip.util.ShiftQueue /* Options for describing the attributes of memory regions / object RegionType { // Define the 'more relaxed than' ordering val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS) sealed trait T extends Ordered[T] { def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this) } case object CACHED extends T // an intermediate agent may have cached a copy of the region for you case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively } // A non-empty half-open range; [start, end) case class IdRange(start: Int, end: Int) extends Ordered[IdRange] { require (start >= 0, s"Ids cannot be negative, but got: $start.") require (start <= end, "Id ranges cannot be negative.") def compare(x: IdRange) = { val primary = (this.start - x.start).signum val secondary = (x.end - this.end).signum if (primary != 0) primary else secondary } def overlaps(x: IdRange) = start < x.end && x.start < end def contains(x: IdRange) = start <= x.start && x.end <= end def contains(x: Int) = start <= x && x < end def contains(x: UInt) = if (size == 0) { false.B } else if (size == 1) { // simple comparison x === start.U } else { // find index of largest different bit val largestDeltaBit = log2Floor(start ^ (end-1)) val smallestCommonBit = largestDeltaBit + 1 // may not exist in x val uncommonMask = (1 << smallestCommonBit) - 1 val uncommonBits = (x \| 0.U(smallestCommonBit.W))(largestDeltaBit, 0) // the prefix must match exactly (note: may shift ALL bits away) (x >> smallestCommonBit) === (start >> smallestCommonBit).U && // firrtl constant prop range analysis can eliminate these two: (start & uncommonMask).U <= uncommonBits && uncommonBits <= ((end-1) & uncommonMask).U } def shift(x: Int) = IdRange(start+x, end+x) def size = end - start def isEmpty = end == start def range = start until end } object IdRange { def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else { val ranges = s.sorted (ranges.tail zip ranges.init) find { case (a, b) => a overlaps b } } } // An potentially empty inclusive range of 2-powers [min, max] (in bytes) case class TransferSizes(min: Int, max: Int) { def this(x: Int) = this(x, x) require (min <= max, s"Min transfer $min > max transfer $max") require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)") require (max == 0 \|\| isPow2(max), s"TransferSizes must be a power of 2, got: $max") require (min == 0 \|\| isPow2(min), s"TransferSizes must be a power of 2, got: $min") require (max == 0 \|\| min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)") def none = min == 0 def contains(x: Int) = isPow2(x) && min <= x && x <= max def containsLg(x: Int) = contains(1 << x) def containsLg(x: UInt) = if (none) false.B else if (min == max) { log2Ceil(min).U === x } else { log2Ceil(min).U <= x && x <= log2Ceil(max).U } def contains(x: TransferSizes) = x.none \|\| (min <= x.min && x.max <= max) def intersect(x: TransferSizes) = if (x.max < min \|\| max < x.min) TransferSizes.none else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max)) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { this } else { TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max)) } } override def toString() = "TransferSizes[%d, %d]".format(min, max) } object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none } // AddressSets specify the address space managed by the manager // Base is the base address, and mask are the bits consumed by the manager // e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff // e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ... case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet] { // Forbid misaligned base address (and empty sets) require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}") require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous // We do allow negative mask (=> ignore all high bits) def contains(x: BigInt) = ((x ^ base) & ~mask) == 0 def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S // turn x into an address contained in this set def legalize(x: UInt): UInt = base.U \| (mask.U & x) // overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1) def overlaps(x: AddressSet) = (~(mask \| x.mask) & (base ^ x.base)) == 0 // contains iff bitwise: x.mask => mask && contains(x.base) def contains(x: AddressSet) = ((x.mask \| (base ^ x.base)) & ~mask) == 0 // The number of bytes to which the manager must be aligned def alignment = ((mask + 1) & ~mask) // Is this a contiguous memory range def contiguous = alignment == mask+1 def finite = mask >= 0 def max = { require (finite, "Max cannot be calculated on infinite mask"); base \| mask } // Widen the match function to ignore all bits in imask def widen(imask: BigInt) = AddressSet(base & ~imask, mask \| imask) // Return an AddressSet that only contains the addresses both sets contain def intersect(x: AddressSet): Option[AddressSet] = { if (!overlaps(x)) { None } else { val r_mask = mask & x.mask val r_base = base \| x.base Some(AddressSet(r_base, r_mask)) } } def subtract(x: AddressSet): Seq[AddressSet] = { intersect(x) match { case None => Seq(this) case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit => val nmask = (mask & (bit-1)) \| remove.mask val nbase = (remove.base ^ bit) & ~nmask AddressSet(nbase, nmask) } } } // AddressSets have one natural Ordering (the containment order, if contiguous) def compare(x: AddressSet) = { val primary = (this.base - x.base).signum // smallest address first val secondary = (x.mask - this.mask).signum // largest mask first if (primary != 0) primary else secondary } // We always want to see things in hex override def toString() = { if (mask >= 0) { "AddressSet(0x%x, 0x%x)".format(base, mask) } else { "AddressSet(0x%x, ~0x%x)".format(base, ~mask) } } def toRanges = { require (finite, "Ranges cannot be calculated on infinite mask") val size = alignment val fragments = mask & ~(size-1) val bits = bitIndexes(fragments) (BigInt(0) until (BigInt(1) << bits.size)).map { i => val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) } AddressRange(off, size) } } } object AddressSet { val everything = AddressSet(0, -1) def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = { if (size == 0) tail.reverse else { val maxBaseAlignment = base & (-base) // 0 for infinite (LSB) val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size val step = if (maxBaseAlignment == 0 \|\| maxBaseAlignment > maxSizeAlignment) maxSizeAlignment else maxBaseAlignment misaligned(base+step, size-step, AddressSet(base, step-1) +: tail) } } def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = { // Pair terms up by ignoring 'bit' seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) => if (seq.size == 1) { seq.head // singleton -> unaffected } else { key.copy(mask = key.mask \| bit) // pair - widen mask by bit } }.toList } def unify(seq: Seq[AddressSet]): Seq[AddressSet] = { val bits = seq.map(_.base).foldLeft(BigInt(0))(_ \| _) AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted } def enumerateMask(mask: BigInt): Seq[BigInt] = { def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] = if (id == mask) (id +: tail).reverse else helper(((~mask \| id) + 1) & mask, id +: tail) helper(0, Nil) } def enumerateBits(mask: BigInt): Seq[BigInt] = { def helper(x: BigInt): Seq[BigInt] = { if (x == 0) { Nil } else { val bit = x & (-x) bit +: helper(x & ~bit) } } helper(mask) } } case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean) { require (depth >= 0, "Buffer depth must be >= 0") def isDefined = depth > 0 def latency = if (isDefined && !flow) 1 else 0 def apply[T <: Data](x: DecoupledIO[T]) = if (isDefined) Queue(x, depth, flow=flow, pipe=pipe) else x def irrevocable[T <: Data](x: ReadyValidIO[T]) = if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe) else x def sq[T <: Data](x: DecoupledIO[T]) = if (!isDefined) x else { val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe)) sq.io.enq <> x sq.io.deq } override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "") } object BufferParams { implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false) val default = BufferParams(2) val none = BufferParams(0) val flow = BufferParams(1, true, false) val pipe = BufferParams(1, false, true) } case class TriStateValue(value: Boolean, set: Boolean) { def update(orig: Boolean) = if (set) value else orig } object TriStateValue { implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true) def unset = TriStateValue(false, false) } trait DirectedBuffers[T] { def copyIn(x: BufferParams): T def copyOut(x: BufferParams): T def copyInOut(x: BufferParams): T } trait IdMapEntry { def name: String def from: IdRange def to: IdRange def isCache: Boolean def requestFifo: Boolean def maxTransactionsInFlight: Option[Int] def pretty(fmt: String) = if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5 fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } else { fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "") } } abstract class IdMap[T <: IdMapEntry] { protected val fmt: String val mapping: Seq[T] def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n") } File Edges.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config.Parameters import freechips.rocketchip.util._ class TLEdge( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdgeParameters(client, manager, params, sourceInfo) { def isAligned(address: UInt, lgSize: UInt): Bool = { if (maxLgSize == 0) true.B else { val mask = UIntToOH1(lgSize, maxLgSize) (address & mask) === 0.U } } def mask(address: UInt, lgSize: UInt): UInt = MaskGen(address, lgSize, manager.beatBytes) def staticHasData(bundle: TLChannel): Option[Boolean] = { bundle match { case _:TLBundleA => { // Do there exist A messages with Data? val aDataYes = manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportPutFull \|\| manager.anySupportPutPartial // Do there exist A messages without Data? val aDataNo = manager.anySupportAcquireB \|\| manager.anySupportGet \|\| manager.anySupportHint // Statically optimize the case where hasData is a constant if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None } case _:TLBundleB => { // Do there exist B messages with Data? val bDataYes = client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportPutFull \|\| client.anySupportPutPartial // Do there exist B messages without Data? val bDataNo = client.anySupportProbe \|\| client.anySupportGet \|\| client.anySupportHint // Statically optimize the case where hasData is a constant if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None } case _:TLBundleC => { // Do there eixst C messages with Data? val cDataYes = client.anySupportGet \|\| client.anySupportArithmetic \|\| client.anySupportLogical \|\| client.anySupportProbe // Do there exist C messages without Data? val cDataNo = client.anySupportPutFull \|\| client.anySupportPutPartial \|\| client.anySupportHint \|\| client.anySupportProbe if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None } case _:TLBundleD => { // Do there eixst D messages with Data? val dDataYes = manager.anySupportGet \|\| manager.anySupportArithmetic \|\| manager.anySupportLogical \|\| manager.anySupportAcquireB // Do there exist D messages without Data? val dDataNo = manager.anySupportPutFull \|\| manager.anySupportPutPartial \|\| manager.anySupportHint \|\| manager.anySupportAcquireT if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None } case _:TLBundleE => Some(false) } } def isRequest(x: TLChannel): Bool = { x match { case a: TLBundleA => true.B case b: TLBundleB => true.B case c: TLBundleC => c.opcode(2) && c.opcode(1) // opcode === TLMessages.Release \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(2) && !d.opcode(1) // opcode === TLMessages.Grant \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } } def isResponse(x: TLChannel): Bool = { x match { case a: TLBundleA => false.B case b: TLBundleB => false.B case c: TLBundleC => !c.opcode(2) \|\| !c.opcode(1) // opcode =/= TLMessages.Release && // opcode =/= TLMessages.ReleaseData case d: TLBundleD => true.B // Grant isResponse + isRequest case e: TLBundleE => true.B } } def hasData(x: TLChannel): Bool = { val opdata = x match { case a: TLBundleA => !a.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case b: TLBundleB => !b.opcode(2) // opcode === TLMessages.PutFullData \|\| // opcode === TLMessages.PutPartialData \|\| // opcode === TLMessages.ArithmeticData \|\| // opcode === TLMessages.LogicalData case c: TLBundleC => c.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.ProbeAckData \|\| // opcode === TLMessages.ReleaseData case d: TLBundleD => d.opcode(0) // opcode === TLMessages.AccessAckData \|\| // opcode === TLMessages.GrantData case e: TLBundleE => false.B } staticHasData(x).map(_.B).getOrElse(opdata) } def opcode(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.opcode case b: TLBundleB => b.opcode case c: TLBundleC => c.opcode case d: TLBundleD => d.opcode } } def param(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.param case b: TLBundleB => b.param case c: TLBundleC => c.param case d: TLBundleD => d.param } } def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size case b: TLBundleB => b.size case c: TLBundleC => c.size case d: TLBundleD => d.size } } def data(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.data case b: TLBundleB => b.data case c: TLBundleC => c.data case d: TLBundleD => d.data } } def corrupt(x: TLDataChannel): Bool = { x match { case a: TLBundleA => a.corrupt case b: TLBundleB => b.corrupt case c: TLBundleC => c.corrupt case d: TLBundleD => d.corrupt } } def mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.mask case b: TLBundleB => b.mask case c: TLBundleC => mask(c.address, c.size) } } def full_mask(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => mask(a.address, a.size) case b: TLBundleB => mask(b.address, b.size) case c: TLBundleC => mask(c.address, c.size) } } def address(x: TLAddrChannel): UInt = { x match { case a: TLBundleA => a.address case b: TLBundleB => b.address case c: TLBundleC => c.address } } def source(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.source case b: TLBundleB => b.source case c: TLBundleC => c.source case d: TLBundleD => d.source } } def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes) def addr_lo(x: UInt): UInt = if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0) def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x)) def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x)) def numBeats(x: TLChannel): UInt = { x match { case _: TLBundleE => 1.U case bundle: TLDataChannel => { val hasData = this.hasData(bundle) val size = this.size(bundle) val cutoff = log2Ceil(manager.beatBytes) val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U val decode = UIntToOH(size, maxLgSize+1) >> cutoff Mux(hasData, decode \| small.asUInt, 1.U) } } } def numBeats1(x: TLChannel): UInt = { x match { case _: TLBundleE => 0.U case bundle: TLDataChannel => { if (maxLgSize == 0) { 0.U } else { val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes) Mux(hasData(bundle), decode, 0.U) } } } } def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val beats1 = numBeats1(bits) val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W)) val counter1 = counter - 1.U val first = counter === 0.U val last = counter === 1.U \|\| beats1 === 0.U val done = last && fire val count = (beats1 & ~counter1) when (fire) { counter := Mux(first, beats1, counter1) } (first, last, done, count) } def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1 def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire) def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid) def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2 def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire) def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid) def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3 def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire) def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid) def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3) } def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire) def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid) def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4) } def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire) def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid) def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = { val r = firstlastHelper(bits, fire) (r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes)) } def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire) def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid) // Does the request need T permissions to be executed? def needT(a: TLBundleA): Bool = { val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLPermissions.NtoB -> false.B, TLPermissions.NtoT -> true.B, TLPermissions.BtoT -> true.B)) MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array( TLMessages.PutFullData -> true.B, TLMessages.PutPartialData -> true.B, TLMessages.ArithmeticData -> true.B, TLMessages.LogicalData -> true.B, TLMessages.Get -> false.B, TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array( TLHints.PREFETCH_READ -> false.B, TLHints.PREFETCH_WRITE -> true.B)), TLMessages.AcquireBlock -> acq_needT, TLMessages.AcquirePerm -> acq_needT)) } // This is a very expensive circuit; use only if you really mean it! def inFlight(x: TLBundle): (UInt, UInt) = { val flight = RegInit(0.U(log2Ceil(3client.endSourceId+1).W)) val bce = manager.anySupportAcquireB && client.anySupportProbe val (a_first, a_last, _) = firstlast(x.a) val (b_first, b_last, _) = firstlast(x.b) val (c_first, c_last, _) = firstlast(x.c) val (d_first, d_last, _) = firstlast(x.d) val (e_first, e_last, _) = firstlast(x.e) val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits)) val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits)) val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits)) val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits)) val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits)) val a_inc = x.a.fire && a_first && a_request val b_inc = x.b.fire && b_first && b_request val c_inc = x.c.fire && c_first && c_request val d_inc = x.d.fire && d_first && d_request val e_inc = x.e.fire && e_first && e_request val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil)) val a_dec = x.a.fire && a_last && a_response val b_dec = x.b.fire && b_last && b_response val c_dec = x.c.fire && c_last && c_response val d_dec = x.d.fire && d_last && d_response val e_dec = x.e.fire && e_last && e_response val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil)) val next_flight = flight + PopCount(inc) - PopCount(dec) flight := next_flight (flight, next_flight) } def prettySourceMapping(context: String): String = { s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n" } } class TLEdgeOut( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { // Transfers def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquireBlock a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.AcquirePerm a.param := growPermissions a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.Release c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = { require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsAcquireBFast(toAddress, lgSize) val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ReleaseData c.param := shrinkPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt (legal, c) } def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) = Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B) def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAck c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(b.source, b.address, b.size, reportPermissions, data) def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.ProbeAckData c.param := reportPermissions c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC = ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B) def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink) def GrantAck(toSink: UInt): TLBundleE = { val e = Wire(new TLBundleE(bundle)) e.sink := toSink e } // Accesses def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsGetFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Get a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutFullFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutFullData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) = Put(fromSource, toAddress, lgSize, data, mask, false.B) def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = { require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsPutPartialFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.PutPartialData a.param := 0.U a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask a.data := data a.corrupt := corrupt (legal, a) } def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = { require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsArithmeticFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.ArithmeticData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsLogicalFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.LogicalData a.param := atomic a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := data a.corrupt := corrupt (legal, a) } def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = { require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}") val legal = manager.supportsHintFast(toAddress, lgSize) val a = Wire(new TLBundleA(bundle)) a.opcode := TLMessages.Hint a.param := param a.size := lgSize a.source := fromSource a.address := toAddress a.user := DontCare a.echo := DontCare a.mask := mask(toAddress, lgSize) a.data := DontCare a.corrupt := false.B (legal, a) } def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data) def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B) def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.AccessAckData c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := data c.corrupt := corrupt c } def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size) def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = { val c = Wire(new TLBundleC(bundle)) c.opcode := TLMessages.HintAck c.param := 0.U c.size := lgSize c.source := fromSource c.address := toAddress c.user := DontCare c.echo := DontCare c.data := DontCare c.corrupt := false.B c } } class TLEdgeIn( client: TLClientPortParameters, manager: TLManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends TLEdge(client, manager, params, sourceInfo) { private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = { val todo = x.filter(!_.isEmpty) val heads = todo.map(_.head) val tails = todo.map(_.tail) if (todo.isEmpty) Nil else { heads +: myTranspose(tails) } } // Transfers def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = { require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}") val legal = client.supportsProbe(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Probe b.param := capPermissions b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.Grant d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B) def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.GrantData d.param := capPermissions d.size := lgSize d.source := toSource d.sink := fromSink d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B) def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.ReleaseAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } // Accesses def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = { require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsGet(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Get b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}") val legal = client.supportsPutFull(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutFullData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) = Put(fromAddress, toSource, lgSize, data, mask, false.B) def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = { require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsPutPartial(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.PutPartialData b.param := 0.U b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask b.data := data b.corrupt := corrupt (legal, b) } def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsArithmetic(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.ArithmeticData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = { require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsLogical(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.LogicalData b.param := atomic b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := data b.corrupt := corrupt (legal, b) } def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = { require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}") val legal = client.supportsHint(toSource, lgSize) val b = Wire(new TLBundleB(bundle)) b.opcode := TLMessages.Hint b.param := param b.size := lgSize b.source := toSource b.address := fromAddress b.mask := mask(fromAddress, lgSize) b.data := DontCare b.corrupt := false.B (legal, b) } def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size) def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied) def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B) def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data) def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B) def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.AccessAckData d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := data d.corrupt := corrupt d } def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B) def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied) def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B) def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = { val d = Wire(new TLBundleD(bundle)) d.opcode := TLMessages.HintAck d.param := 0.U d.size := lgSize d.source := toSource d.sink := 0.U d.denied := denied d.user := DontCare d.echo := DontCare d.data := DontCare d.corrupt := false.B d } }	module TLMonitor_50( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [5:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire [12:0] _GEN_0 = {10'h0, io_in_c_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [5:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [5:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [2:0] b_first_counter; // @[Edges.scala:229:27] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [5:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35] reg [2:0] c_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [5:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [62:0] inflight; // @[Monitor.scala:614:27] reg [251:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [251:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire [63:0] _GEN_1 = {58'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35] wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] wire [63:0] _GEN_4 = {58'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [62:0] inflight_1; // @[Monitor.scala:726:35] reg [251:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] c_first_counter_1; // @[Edges.scala:229:27] wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}] wire [63:0] _GEN_6 = {58'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35] wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] reg [6:0] inflight_2; // @[Monitor.scala:828:27] reg [2:0] d_first_counter_3; // @[Edges.scala:229:27] wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35] wire [7:0] _d_set_T = 8'h1 << io_in_d_bits_sink; // @[OneHot.scala:58:35] wire [6:0] d_set = _GEN_8 ? _d_set_T[6:0] : 7'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to the following Chisel files. File RecFNToRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import consts._ class RecFNToRecFN( inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int) extends chisel3.RawModule { val io = IO(new Bundle { val in = Input(Bits((inExpWidth + inSigWidth + 1).W)) val roundingMode = Input(UInt(3.W)) val detectTininess = Input(UInt(1.W)) val out = Output(Bits((outExpWidth + outSigWidth + 1).W)) val exceptionFlags = Output(Bits(5.W)) }) //------------------------------------------------------------------------ //------------------------------------------------------------------------ val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in); if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) { //-------------------------------------------------------------------- //-------------------------------------------------------------------- io.out := io.in<<(outSigWidth - inSigWidth) io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W) } else { //-------------------------------------------------------------------- //-------------------------------------------------------------------- val roundAnyRawFNToRecFN = Module( new RoundAnyRawFNToRecFN( inExpWidth, inSigWidth, outExpWidth, outSigWidth, flRoundOpt_sigMSBitAlwaysZero )) roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn) roundAnyRawFNToRecFN.io.infiniteExc := false.B roundAnyRawFNToRecFN.io.in := rawIn roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess io.out := roundAnyRawFNToRecFN.io.out io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags } } File rawFloatFromRecFN.scala: /============================================================================ This Chisel source file is part of a pre-release version of the HardFloat IEEE Floating-Point Arithmetic Package, by John R. Hauser (with some contributions from Yunsup Lee and Andrew Waterman, mainly concerning testing). Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the University of California. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions, and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions, and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =============================================================================/ package hardfloat import chisel3._ import chisel3.util._ /---------------------------------------------------------------------------- \| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be \| set. ----------------------------------------------------------------------------*/ object rawFloatFromRecFN { def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat = { val exp = in(expWidth + sigWidth - 1, sigWidth - 1) val isZero = exp(expWidth, expWidth - 2) === 0.U val isSpecial = exp(expWidth, expWidth - 1) === 3.U val out = Wire(new RawFloat(expWidth, sigWidth)) out.isNaN := isSpecial && exp(expWidth - 2) out.isInf := isSpecial && ! exp(expWidth - 2) out.isZero := isZero out.sign := in(expWidth + sigWidth) out.sExp := exp.zext out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0) out } }	module RecFNToRecFN_87( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_147( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to the following Chisel files. File Buffer.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.BufferParams class TLBufferNode ( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit valName: ValName) extends TLAdapterNode( clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) }, managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) } ) { override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}" override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none) } class TLBuffer( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters) extends LazyModule { def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace) def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde) def this()(implicit p: Parameters) = this(BufferParams.default) val node = new TLBufferNode(a, b, c, d, e) lazy val module = new Impl class Impl extends LazyModuleImp(this) { def headBundle = node.out.head._2.bundle override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_") (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out.a <> a(in .a) in .d <> d(out.d) if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) { in .b <> b(out.b) out.c <> c(in .c) out.e <> e(in .e) } else { in.b.valid := false.B in.c.ready := true.B in.e.ready := true.B out.b.ready := true.B out.c.valid := false.B out.e.valid := false.B } } } } object TLBuffer { def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default) def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde) def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace) def apply( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams)(implicit p: Parameters): TLNode = { val buffer = LazyModule(new TLBuffer(a, b, c, d, e)) buffer.node } def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = { val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) } name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } } buffers.map(_.node) } def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = { chain(depth, name) .reduceLeftOption(_ := _) .getOrElse(TLNameNode("no_buffer")) } } File MemoryBus.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.subsystem import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.devices.tilelink.{BuiltInDevices, HasBuiltInDeviceParams, BuiltInErrorDeviceParams, BuiltInZeroDeviceParams} import freechips.rocketchip.tilelink.{ ReplicatedRegion, HasTLBusParams, HasRegionReplicatorParams, TLBusWrapper, TLBusWrapperInstantiationLike, RegionReplicator, TLXbar, TLInwardNode, TLOutwardNode, ProbePicker, TLEdge, TLFIFOFixer } import freechips.rocketchip.util.Location /** Parameterization of the memory-side bus created for each memory channel / case class MemoryBusParams( beatBytes: Int, blockBytes: Int, dtsFrequency: Option[BigInt] = None, zeroDevice: Option[BuiltInZeroDeviceParams] = None, errorDevice: Option[BuiltInErrorDeviceParams] = None, replication: Option[ReplicatedRegion] = None) extends HasTLBusParams with HasBuiltInDeviceParams with HasRegionReplicatorParams with TLBusWrapperInstantiationLike { def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): MemoryBus = { val mbus = LazyModule(new MemoryBus(this, loc.name)) mbus.suggestName(loc.name) context.tlBusWrapperLocationMap += (loc -> mbus) mbus } } /* Wrapper for creating TL nodes from a bus connected to the back of each mem channel / class MemoryBus(params: MemoryBusParams, name: String = "memory_bus")(implicit p: Parameters) extends TLBusWrapper(params, name)(p) { private val replicator = params.replication.map(r => LazyModule(new RegionReplicator(r))) val prefixNode = replicator.map { r => r.prefix := addressPrefixNexusNode addressPrefixNexusNode } private val xbar = LazyModule(new TLXbar(nameSuffix = Some(name))).suggestName(busName + "_xbar") val inwardNode: TLInwardNode = replicator.map(xbar.node :=* TLFIFOFixer(TLFIFOFixer.all) := _.node) .getOrElse(xbar.node := TLFIFOFixer(TLFIFOFixer.all)) val outwardNode: TLOutwardNode = ProbePicker() := xbar.node def busView: TLEdge = xbar.node.edges.in.head val builtInDevices: BuiltInDevices = BuiltInDevices.attach(params, outwardNode) } File ClockDomain.scala: package freechips.rocketchip.prci import chisel3._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing { def clockBundle: ClockBundle lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { childClock := clockBundle.clock childReset := clockBundle.reset override def provideImplicitClockToLazyChildren = true // these are just for backwards compatibility with external devices // that were manually wiring themselves to the domain's clock/reset input: val clock = IO(Output(chiselTypeOf(clockBundle.clock))) val reset = IO(Output(chiselTypeOf(clockBundle.reset))) clock := clockBundle.clock reset := clockBundle.reset } } abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain { def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name)) val clockNode = ClockSinkNode(Seq(clockSinkParams)) def clockBundle = clockNode.in.head._1 override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString } class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain { def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name)) val clockNode = ClockSourceNode(Seq(clockSourceParams)) def clockBundle = clockNode.out.head._1 override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString } abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing File ClockGroup.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.prci import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy._ import org.chipsalliance.diplomacy.lazymodule._ import org.chipsalliance.diplomacy.nodes._ import freechips.rocketchip.resources.FixedClockResource case class ClockGroupingNode(groupName: String)(implicit valName: ValName) extends MixedNexusNode(ClockGroupImp, ClockImp)( dFn = { _ => ClockSourceParameters() }, uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq) }) { override def circuitIdentity = outputs.size == 1 } class ClockGroup(groupName: String)(implicit p: Parameters) extends LazyModule { val node = ClockGroupingNode(groupName) lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in(0) val (out, _) = node.out.unzip require (node.in.size == 1) require (in.member.size == out.size) (in.member.data zip out) foreach { case (i, o) => o := i } } } object ClockGroup { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroup(valName.name)).node } case class ClockGroupAggregateNode(groupName: String)(implicit valName: ValName) extends NexusNode(ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, uFn = { seq => ClockGroupSinkParameters(name = groupName, members = seq.flatMap(_.members))}) { override def circuitIdentity = outputs.size == 1 } class ClockGroupAggregator(groupName: String)(implicit p: Parameters) extends LazyModule { val node = ClockGroupAggregateNode(groupName) override lazy val desiredName = s"ClockGroupAggregator_$groupName" lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in.unzip val (out, _) = node.out.unzip val outputs = out.flatMap(_.member.data) require (node.in.size == 1, s"Aggregator for groupName: ${groupName} had ${node.in.size} inward edges instead of 1") require (in.head.member.size == outputs.size) in.head.member.data.zip(outputs).foreach { case (i, o) => o := i } } } object ClockGroupAggregator { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupAggregator(valName.name)).node } class SimpleClockGroupSource(numSources: Int = 1)(implicit p: Parameters) extends LazyModule { val node = ClockGroupSourceNode(List.fill(numSources) { ClockGroupSourceParameters() }) lazy val module = new Impl class Impl extends LazyModuleImp(this) { val (out, _) = node.out.unzip out.map { out: ClockGroupBundle => out.member.data.foreach { o => o.clock := clock; o.reset := reset } } } } object SimpleClockGroupSource { def apply(num: Int = 1)(implicit p: Parameters, valName: ValName) = LazyModule(new SimpleClockGroupSource(num)).node } case class FixedClockBroadcastNode(fixedClockOpt: Option[ClockParameters])(implicit valName: ValName) extends NexusNode(ClockImp)( dFn = { seq => fixedClockOpt.map(_ => ClockSourceParameters(give = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSourceParameters()) }, uFn = { seq => fixedClockOpt.map(_ => ClockSinkParameters(take = fixedClockOpt)).orElse(seq.headOption).getOrElse(ClockSinkParameters()) }, inputRequiresOutput = false) { def fixedClockResources(name: String, prefix: String = "soc/"): Seq[Option[FixedClockResource]] = Seq(fixedClockOpt.map(t => new FixedClockResource(name, t.freqMHz, prefix))) } class FixedClockBroadcast(fixedClockOpt: Option[ClockParameters])(implicit p: Parameters) extends LazyModule { val node = new FixedClockBroadcastNode(fixedClockOpt) { override def circuitIdentity = outputs.size == 1 } lazy val module = new Impl class Impl extends LazyRawModuleImp(this) { val (in, _) = node.in(0) val (out, _) = node.out.unzip override def desiredName = s"FixedClockBroadcast_${out.size}" require (node.in.size == 1, "FixedClockBroadcast can only broadcast a single clock") out.foreach { _ := in } } } object FixedClockBroadcast { def apply(fixedClockOpt: Option[ClockParameters] = None)(implicit p: Parameters, valName: ValName) = LazyModule(new FixedClockBroadcast(fixedClockOpt)).node } case class PRCIClockGroupNode()(implicit valName: ValName) extends NexusNode(ClockGroupImp)( dFn = { _ => ClockGroupSourceParameters() }, uFn = { _ => ClockGroupSinkParameters("prci", Nil) }, outputRequiresInput = false) File LazyModuleImp.scala: package org.chipsalliance.diplomacy.lazymodule import chisel3.{withClockAndReset, Module, RawModule, Reset, _} import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo} import firrtl.passes.InlineAnnotation import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.nodes.Dangle import scala.collection.immutable.SortedMap /* Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]]. * * This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy. / sealed trait LazyModuleImpLike extends RawModule { /* [[LazyModule]] that contains this instance. / val wrapper: LazyModule /* IOs that will be automatically "punched" for this instance. / val auto: AutoBundle /* The metadata that describes the [[HalfEdge]]s which generated [[auto]]. / protected[diplomacy] val dangles: Seq[Dangle] // [[wrapper.module]] had better not be accessed while LazyModules are still being built! require( LazyModule.scope.isEmpty, s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}" ) /* Set module name. Defaults to the containing LazyModule's desiredName. / override def desiredName: String = wrapper.desiredName suggestName(wrapper.suggestedName) /* [[Parameters]] for chisel [[Module]]s. / implicit val p: Parameters = wrapper.p /* instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and * submodules. / protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = { // 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]], // 2. return [[Dangle]]s from each module. val childDangles = wrapper.children.reverse.flatMap { c => implicit val sourceInfo: SourceInfo = c.info c.cloneProto.map { cp => // If the child is a clone, then recursively set cloneProto of its children as well def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = { require(bases.size == clones.size) (bases.zip(clones)).map { case (l, r) => require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}") l.cloneProto = Some(r) assignCloneProtos(l.children, r.children) } } assignCloneProtos(c.children, cp.children) // Clone the child module as a record, and get its [[AutoBundle]] val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName) val clonedAuto = clone("auto").asInstanceOf[AutoBundle] // Get the empty [[Dangle]]'s of the cloned child val rawDangles = c.cloneDangles() require(rawDangles.size == clonedAuto.elements.size) // Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) } dangles }.getOrElse { // For non-clones, instantiate the child module val mod = try { Module(c.module) } catch { case e: ChiselException => { println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}") throw e } } mod.dangles } } // Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]]. // This will result in a sequence of [[Dangle]] from these [[BaseNode]]s. val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate()) // Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]] val allDangles = nodeDangles ++ childDangles // Group [[allDangles]] by their [[source]]. val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _) // For each [[source]] set of [[Dangle]]s of size 2, ensure that these // can be connected as a source-sink pair (have opposite flipped value). // Make the connection and mark them as [[done]]. val done = Set() ++ pairing.values.filter(_.size == 2).map { case Seq(a, b) => require(a.flipped != b.flipped) // @todo <> in chisel3 makes directionless connection. if (a.flipped) { a.data <> b.data } else { b.data <> a.data } a.source case _ => None } // Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module. val forward = allDangles.filter(d => !done(d.source)) // Generate [[AutoBundle]] IO from [[forward]]. val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _)) // Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]] val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) => if (d.flipped) { d.data <> io } else { io <> d.data } d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name) } // Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]]. wrapper.inModuleBody.reverse.foreach { _() } if (wrapper.shouldBeInlined) { chisel3.experimental.annotate(new ChiselAnnotation { def toFirrtl = InlineAnnotation(toNamed) }) } // Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]]. (auto, dangles) } } /* Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike { /* Instantiate hardware of this `Module`. / val (auto, dangles) = instantiate() } /* Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]]. * * @param wrapper * the [[LazyModule]] from which the `.module` call is being made. / class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike { // These wires are the default clock+reset for all LazyModule children. // It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the // [[LazyRawModuleImp]] children. // Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly. /* drive clock explicitly. / val childClock: Clock = Wire(Clock()) /* drive reset explicitly. / val childReset: Reset = Wire(Reset()) // the default is that these are disabled childClock := false.B.asClock childReset := chisel3.DontCare def provideImplicitClockToLazyChildren: Boolean = false val (auto, dangles) = if (provideImplicitClockToLazyChildren) { withClockAndReset(childClock, childReset) { instantiate() } } else { instantiate() } } File ProbePicker.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.tilelink import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config._ import org.chipsalliance.diplomacy.lazymodule._ import freechips.rocketchip.diplomacy.{AddressSet, IdRange} / A ProbePicker is used to unify multiple cache banks into one logical cache / class ProbePicker(implicit p: Parameters) extends LazyModule { val node = TLAdapterNode( clientFn = { p => // The ProbePicker assembles multiple clients based on the assumption they are contiguous in the clients list // This should be true for custers of xbar := BankBinder connections def combine(next: TLMasterParameters, pair: (TLMasterParameters, Seq[TLMasterParameters])) = { val (head, output) = pair if (head.visibility.exists(x => next.visibility.exists(_.overlaps(x)))) { (next, head +: output) // pair is not banked, push head without merging } else { def redact(x: TLMasterParameters) = x.v1copy(sourceId = IdRange(0,1), nodePath = Nil, visibility = Seq(AddressSet(0, ~0))) require (redact(next) == redact(head), s"${redact(next)} != ${redact(head)}") val merge = head.v1copy( sourceId = IdRange( head.sourceId.start min next.sourceId.start, head.sourceId.end max next.sourceId.end), visibility = AddressSet.unify(head.visibility ++ next.visibility)) (merge, output) } } val myNil: Seq[TLMasterParameters] = Nil val (head, output) = p.clients.init.foldRight((p.clients.last, myNil))(combine) p.v1copy(clients = head +: output) }, managerFn = { p => p }) lazy val module = new Impl class Impl extends LazyModuleImp(this) { (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) => out <> in // Based on address, adjust source to route to the correct bank if (edgeIn.client.clients.size != edgeOut.client.clients.size) { in.b.bits.source := Mux1H( edgeOut.client.clients.map(_.sourceId contains out.b.bits.source), edgeOut.client.clients.map { c => val banks = edgeIn.client.clients.filter(c.sourceId contains _.sourceId) if (banks.size == 1) { out.b.bits.source // allow sharing the value between single-bank cases } else { Mux1H( banks.map(_.visibility.map(_ contains out.b.bits.address).reduce(_ \|\| _)), banks.map(_.sourceId.start.U)) } } ) } } } } object ProbePicker { def apply()(implicit p: Parameters): TLNode = { val picker = LazyModule(new ProbePicker) picker.node } } File LazyScope.scala: package org.chipsalliance.diplomacy.lazymodule import org.chipsalliance.cde.config.Parameters import org.chipsalliance.diplomacy.ValName /** Allows dynamic creation of [[Module]] hierarchy and "shoving" logic into a [[LazyModule]]. / trait LazyScope { this: LazyModule => override def toString: String = s"LazyScope named $name" /* Evaluate `body` in the current [[LazyModule.scope]] / def apply[T](body: => T): T = { // Preserve the previous value of the [[LazyModule.scope]], because when calling [[apply]] function, // [[LazyModule.scope]] will be altered. val saved = LazyModule.scope // [[LazyModule.scope]] stack push. LazyModule.scope = Some(this) // Evaluate [[body]] in the current `scope`, saving the result to [[out]]. val out = body // Check that the `scope` after evaluating `body` is the same as when we started. require(LazyModule.scope.isDefined, s"LazyScope $name tried to exit, but scope was empty!") require( LazyModule.scope.get eq this, s"LazyScope $name exited before LazyModule ${LazyModule.scope.get.name} was closed" ) // [[LazyModule.scope]] stack pop. LazyModule.scope = saved out } } /* Used to automatically create a level of module hierarchy (a [[SimpleLazyModule]]) within which [[LazyModule]]s can * be instantiated and connected. * * It will instantiate a [[SimpleLazyModule]] to manage evaluation of `body` and evaluate `body` code snippets in this * scope. / object LazyScope { /* Create a [[LazyScope]] with an implicit instance name. * * @param body * code executed within the generated [[SimpleLazyModule]]. * @param valName * instance name of generated [[SimpleLazyModule]]. * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. / def apply[T]( body: => T )( implicit valName: ValName, p: Parameters ): T = { apply(valName.value, "SimpleLazyModule", None)(body)(p) } /* Create a [[LazyScope]] with an explicitly defined instance name. * * @param name * instance name of generated [[SimpleLazyModule]]. * @param body * code executed within the generated `SimpleLazyModule` * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. / def apply[T]( name: String )(body: => T )( implicit p: Parameters ): T = { apply(name, "SimpleLazyModule", None)(body)(p) } /* Create a [[LazyScope]] with an explicit instance and class name, and control inlining. * * @param name * instance name of generated [[SimpleLazyModule]]. * @param desiredModuleName * class name of generated [[SimpleLazyModule]]. * @param overrideInlining * tell FIRRTL that this [[SimpleLazyModule]]'s module should be inlined. * @param body * code executed within the generated `SimpleLazyModule` * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. / def apply[T]( name: String, desiredModuleName: String, overrideInlining: Option[Boolean] = None )(body: => T )( implicit p: Parameters ): T = { val scope = LazyModule(new SimpleLazyModule with LazyScope { override lazy val desiredName = desiredModuleName override def shouldBeInlined = overrideInlining.getOrElse(super.shouldBeInlined) }).suggestName(name) scope { body } } /* Create a [[LazyScope]] to temporarily group children for some reason, but tell Firrtl to inline it. * * For example, we might want to control a set of children's clocks but then not keep the parent wrapper. * * @param body * code executed within the generated `SimpleLazyModule` * @param p * [[Parameters]] propagated to [[SimpleLazyModule]]. */ def inline[T]( body: => T )( implicit p: Parameters ): T = { apply("noname", "ShouldBeInlined", Some(false))(body)(p) } }	module MemoryBus( // @[ClockDomain.scala:14:9] input auto_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [6:0] auto_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_buffer_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [6:0] auto_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_buffer_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_valid, // @[LazyModuleImp.scala:107:25] output [63:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_data, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_strb, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_last, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id, // @[LazyModuleImp.scala:107:25] output [31:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25] output [7:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25] output [2:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25] output [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25] output auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_ready, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_valid, // @[LazyModuleImp.scala:107:25] input [3:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_id, // @[LazyModuleImp.scala:107:25] input [63:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_data, // @[LazyModuleImp.scala:107:25] input [1:0] auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_resp, // @[LazyModuleImp.scala:107:25] input auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_last, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_1_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_0_clock, // @[LazyModuleImp.scala:107:25] output auto_fixedClockNode_anon_out_0_reset, // @[LazyModuleImp.scala:107:25] input auto_mbus_clock_groups_in_member_mbus_0_clock, // @[LazyModuleImp.scala:107:25] input auto_mbus_clock_groups_in_member_mbus_0_reset, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_3_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_3_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_3_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_3_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_bus_xing_in_3_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_bus_xing_in_3_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_3_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_in_3_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_3_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_3_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bus_xing_in_3_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_3_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_bus_xing_in_3_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_3_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_3_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_in_3_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_2_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_2_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_2_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_2_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_bus_xing_in_2_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_bus_xing_in_2_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_2_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_in_2_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_2_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_2_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bus_xing_in_2_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_2_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_bus_xing_in_2_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_2_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_2_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_in_2_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_bus_xing_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_bus_xing_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bus_xing_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_bus_xing_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_bus_xing_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_bus_xing_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_bus_xing_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_bus_xing_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_bus_xing_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_bus_xing_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_bus_xing_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_bus_xing_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_bus_xing_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_bus_xing_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_bus_xing_in_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _buffer_1_auto_in_a_ready; // @[Buffer.scala:75:28] wire _buffer_1_auto_in_d_valid; // @[Buffer.scala:75:28] wire [2:0] _buffer_1_auto_in_d_bits_opcode; // @[Buffer.scala:75:28] wire [1:0] _buffer_1_auto_in_d_bits_param; // @[Buffer.scala:75:28] wire [2:0] _buffer_1_auto_in_d_bits_size; // @[Buffer.scala:75:28] wire [6:0] _buffer_1_auto_in_d_bits_source; // @[Buffer.scala:75:28] wire _buffer_1_auto_in_d_bits_sink; // @[Buffer.scala:75:28] wire _buffer_1_auto_in_d_bits_denied; // @[Buffer.scala:75:28] wire [63:0] _buffer_1_auto_in_d_bits_data; // @[Buffer.scala:75:28] wire _buffer_1_auto_in_d_bits_corrupt; // @[Buffer.scala:75:28] wire _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_source; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_tl_in_a_ready; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_source; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_denied; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_valid; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_opcode; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_param; // @[LazyScope.scala:98:27] wire [2:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_size; // @[LazyScope.scala:98:27] wire [6:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_source; // @[LazyScope.scala:98:27] wire [31:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_address; // @[LazyScope.scala:98:27] wire [7:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_mask; // @[LazyScope.scala:98:27] wire [63:0] _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_data; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_corrupt; // @[LazyScope.scala:98:27] wire _coupler_to_memory_controller_port_named_axi4_auto_tl_out_d_ready; // @[LazyScope.scala:98:27] wire _picker_auto_in_1_a_ready; // @[ProbePicker.scala:69:28] wire _picker_auto_in_1_d_valid; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_in_1_d_bits_opcode; // @[ProbePicker.scala:69:28] wire [1:0] _picker_auto_in_1_d_bits_param; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_in_1_d_bits_size; // @[ProbePicker.scala:69:28] wire [6:0] _picker_auto_in_1_d_bits_source; // @[ProbePicker.scala:69:28] wire _picker_auto_in_1_d_bits_sink; // @[ProbePicker.scala:69:28] wire _picker_auto_in_1_d_bits_denied; // @[ProbePicker.scala:69:28] wire [63:0] _picker_auto_in_1_d_bits_data; // @[ProbePicker.scala:69:28] wire _picker_auto_in_1_d_bits_corrupt; // @[ProbePicker.scala:69:28] wire _picker_auto_in_0_a_ready; // @[ProbePicker.scala:69:28] wire _picker_auto_in_0_d_valid; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_in_0_d_bits_opcode; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_in_0_d_bits_size; // @[ProbePicker.scala:69:28] wire [6:0] _picker_auto_in_0_d_bits_source; // @[ProbePicker.scala:69:28] wire _picker_auto_in_0_d_bits_denied; // @[ProbePicker.scala:69:28] wire [63:0] _picker_auto_in_0_d_bits_data; // @[ProbePicker.scala:69:28] wire _picker_auto_in_0_d_bits_corrupt; // @[ProbePicker.scala:69:28] wire _picker_auto_out_1_a_valid; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_1_a_bits_opcode; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_1_a_bits_param; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_1_a_bits_size; // @[ProbePicker.scala:69:28] wire [6:0] _picker_auto_out_1_a_bits_source; // @[ProbePicker.scala:69:28] wire [27:0] _picker_auto_out_1_a_bits_address; // @[ProbePicker.scala:69:28] wire [7:0] _picker_auto_out_1_a_bits_mask; // @[ProbePicker.scala:69:28] wire [63:0] _picker_auto_out_1_a_bits_data; // @[ProbePicker.scala:69:28] wire _picker_auto_out_1_a_bits_corrupt; // @[ProbePicker.scala:69:28] wire _picker_auto_out_1_d_ready; // @[ProbePicker.scala:69:28] wire _picker_auto_out_0_a_valid; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_0_a_bits_opcode; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_0_a_bits_param; // @[ProbePicker.scala:69:28] wire [2:0] _picker_auto_out_0_a_bits_size; // @[ProbePicker.scala:69:28] wire [6:0] _picker_auto_out_0_a_bits_source; // @[ProbePicker.scala:69:28] wire [31:0] _picker_auto_out_0_a_bits_address; // @[ProbePicker.scala:69:28] wire [7:0] _picker_auto_out_0_a_bits_mask; // @[ProbePicker.scala:69:28] wire [63:0] _picker_auto_out_0_a_bits_data; // @[ProbePicker.scala:69:28] wire _picker_auto_out_0_a_bits_corrupt; // @[ProbePicker.scala:69:28] wire _picker_auto_out_0_d_ready; // @[ProbePicker.scala:69:28] wire _mbus_xbar_auto_anon_out_1_a_valid; // @[MemoryBus.scala:47:32] wire [2:0] _mbus_xbar_auto_anon_out_1_a_bits_opcode; // @[MemoryBus.scala:47:32] wire [2:0] _mbus_xbar_auto_anon_out_1_a_bits_param; // @[MemoryBus.scala:47:32] wire [2:0] _mbus_xbar_auto_anon_out_1_a_bits_size; // @[MemoryBus.scala:47:32] wire [6:0] _mbus_xbar_auto_anon_out_1_a_bits_source; // @[MemoryBus.scala:47:32] wire [27:0] _mbus_xbar_auto_anon_out_1_a_bits_address; // @[MemoryBus.scala:47:32] wire [7:0] _mbus_xbar_auto_anon_out_1_a_bits_mask; // @[MemoryBus.scala:47:32] wire [63:0] _mbus_xbar_auto_anon_out_1_a_bits_data; // @[MemoryBus.scala:47:32] wire _mbus_xbar_auto_anon_out_1_a_bits_corrupt; // @[MemoryBus.scala:47:32] wire _mbus_xbar_auto_anon_out_1_d_ready; // @[MemoryBus.scala:47:32] wire _mbus_xbar_auto_anon_out_0_a_valid; // @[MemoryBus.scala:47:32] wire [2:0] _mbus_xbar_auto_anon_out_0_a_bits_opcode; // @[MemoryBus.scala:47:32] wire [2:0] _mbus_xbar_auto_anon_out_0_a_bits_param; // @[MemoryBus.scala:47:32] wire [2:0] _mbus_xbar_auto_anon_out_0_a_bits_size; // @[MemoryBus.scala:47:32] wire [6:0] _mbus_xbar_auto_anon_out_0_a_bits_source; // @[MemoryBus.scala:47:32] wire [31:0] _mbus_xbar_auto_anon_out_0_a_bits_address; // @[MemoryBus.scala:47:32] wire [7:0] _mbus_xbar_auto_anon_out_0_a_bits_mask; // @[MemoryBus.scala:47:32] wire [63:0] _mbus_xbar_auto_anon_out_0_a_bits_data; // @[MemoryBus.scala:47:32] wire _mbus_xbar_auto_anon_out_0_a_bits_corrupt; // @[MemoryBus.scala:47:32] wire _mbus_xbar_auto_anon_out_0_d_ready; // @[MemoryBus.scala:47:32] wire _fixedClockNode_auto_anon_out_0_clock; // @[ClockGroup.scala:115:114] wire _fixedClockNode_auto_anon_out_0_reset; // @[ClockGroup.scala:115:114] FixedClockBroadcast_3 fixedClockNode ( // @[ClockGroup.scala:115:114] .auto_anon_in_clock (auto_mbus_clock_groups_in_member_mbus_0_clock), .auto_anon_in_reset (auto_mbus_clock_groups_in_member_mbus_0_reset), .auto_anon_out_2_clock (auto_fixedClockNode_anon_out_1_clock), .auto_anon_out_1_clock (auto_fixedClockNode_anon_out_0_clock), .auto_anon_out_1_reset (auto_fixedClockNode_anon_out_0_reset), .auto_anon_out_0_clock (_fixedClockNode_auto_anon_out_0_clock), .auto_anon_out_0_reset (_fixedClockNode_auto_anon_out_0_reset) ); // @[ClockGroup.scala:115:114] TLXbar_mbus_i4_o2_a32d64s7k1z3u mbus_xbar ( // @[MemoryBus.scala:47:32] .clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114] .reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114] .auto_anon_in_3_a_ready (auto_bus_xing_in_3_a_ready), .auto_anon_in_3_a_valid (auto_bus_xing_in_3_a_valid), .auto_anon_in_3_a_bits_opcode (auto_bus_xing_in_3_a_bits_opcode), .auto_anon_in_3_a_bits_param (auto_bus_xing_in_3_a_bits_param), .auto_anon_in_3_a_bits_size (auto_bus_xing_in_3_a_bits_size), .auto_anon_in_3_a_bits_source (auto_bus_xing_in_3_a_bits_source), .auto_anon_in_3_a_bits_address (auto_bus_xing_in_3_a_bits_address), .auto_anon_in_3_a_bits_mask (auto_bus_xing_in_3_a_bits_mask), .auto_anon_in_3_a_bits_data (auto_bus_xing_in_3_a_bits_data), .auto_anon_in_3_a_bits_corrupt (auto_bus_xing_in_3_a_bits_corrupt), .auto_anon_in_3_d_ready (auto_bus_xing_in_3_d_ready), .auto_anon_in_3_d_valid (auto_bus_xing_in_3_d_valid), .auto_anon_in_3_d_bits_opcode (auto_bus_xing_in_3_d_bits_opcode), .auto_anon_in_3_d_bits_param (auto_bus_xing_in_3_d_bits_param), .auto_anon_in_3_d_bits_size (auto_bus_xing_in_3_d_bits_size), .auto_anon_in_3_d_bits_source (auto_bus_xing_in_3_d_bits_source), .auto_anon_in_3_d_bits_sink (auto_bus_xing_in_3_d_bits_sink), .auto_anon_in_3_d_bits_denied (auto_bus_xing_in_3_d_bits_denied), .auto_anon_in_3_d_bits_data (auto_bus_xing_in_3_d_bits_data), .auto_anon_in_3_d_bits_corrupt (auto_bus_xing_in_3_d_bits_corrupt), .auto_anon_in_2_a_ready (auto_bus_xing_in_2_a_ready), .auto_anon_in_2_a_valid (auto_bus_xing_in_2_a_valid), .auto_anon_in_2_a_bits_opcode (auto_bus_xing_in_2_a_bits_opcode), .auto_anon_in_2_a_bits_param (auto_bus_xing_in_2_a_bits_param), .auto_anon_in_2_a_bits_size (auto_bus_xing_in_2_a_bits_size), .auto_anon_in_2_a_bits_source (auto_bus_xing_in_2_a_bits_source), .auto_anon_in_2_a_bits_address (auto_bus_xing_in_2_a_bits_address), .auto_anon_in_2_a_bits_mask (auto_bus_xing_in_2_a_bits_mask), .auto_anon_in_2_a_bits_data (auto_bus_xing_in_2_a_bits_data), .auto_anon_in_2_a_bits_corrupt (auto_bus_xing_in_2_a_bits_corrupt), .auto_anon_in_2_d_ready (auto_bus_xing_in_2_d_ready), .auto_anon_in_2_d_valid (auto_bus_xing_in_2_d_valid), .auto_anon_in_2_d_bits_opcode (auto_bus_xing_in_2_d_bits_opcode), .auto_anon_in_2_d_bits_param (auto_bus_xing_in_2_d_bits_param), .auto_anon_in_2_d_bits_size (auto_bus_xing_in_2_d_bits_size), .auto_anon_in_2_d_bits_source (auto_bus_xing_in_2_d_bits_source), .auto_anon_in_2_d_bits_sink (auto_bus_xing_in_2_d_bits_sink), .auto_anon_in_2_d_bits_denied (auto_bus_xing_in_2_d_bits_denied), .auto_anon_in_2_d_bits_data (auto_bus_xing_in_2_d_bits_data), .auto_anon_in_2_d_bits_corrupt (auto_bus_xing_in_2_d_bits_corrupt), .auto_anon_in_1_a_ready (auto_bus_xing_in_1_a_ready), .auto_anon_in_1_a_valid (auto_bus_xing_in_1_a_valid), .auto_anon_in_1_a_bits_opcode (auto_bus_xing_in_1_a_bits_opcode), .auto_anon_in_1_a_bits_param (auto_bus_xing_in_1_a_bits_param), .auto_anon_in_1_a_bits_size (auto_bus_xing_in_1_a_bits_size), .auto_anon_in_1_a_bits_source (auto_bus_xing_in_1_a_bits_source), .auto_anon_in_1_a_bits_address (auto_bus_xing_in_1_a_bits_address), .auto_anon_in_1_a_bits_mask (auto_bus_xing_in_1_a_bits_mask), .auto_anon_in_1_a_bits_data (auto_bus_xing_in_1_a_bits_data), .auto_anon_in_1_a_bits_corrupt (auto_bus_xing_in_1_a_bits_corrupt), .auto_anon_in_1_d_ready (auto_bus_xing_in_1_d_ready), .auto_anon_in_1_d_valid (auto_bus_xing_in_1_d_valid), .auto_anon_in_1_d_bits_opcode (auto_bus_xing_in_1_d_bits_opcode), .auto_anon_in_1_d_bits_param (auto_bus_xing_in_1_d_bits_param), .auto_anon_in_1_d_bits_size (auto_bus_xing_in_1_d_bits_size), .auto_anon_in_1_d_bits_source (auto_bus_xing_in_1_d_bits_source), .auto_anon_in_1_d_bits_sink (auto_bus_xing_in_1_d_bits_sink), .auto_anon_in_1_d_bits_denied (auto_bus_xing_in_1_d_bits_denied), .auto_anon_in_1_d_bits_data (auto_bus_xing_in_1_d_bits_data), .auto_anon_in_1_d_bits_corrupt (auto_bus_xing_in_1_d_bits_corrupt), .auto_anon_in_0_a_ready (auto_bus_xing_in_0_a_ready), .auto_anon_in_0_a_valid (auto_bus_xing_in_0_a_valid), .auto_anon_in_0_a_bits_opcode (auto_bus_xing_in_0_a_bits_opcode), .auto_anon_in_0_a_bits_param (auto_bus_xing_in_0_a_bits_param), .auto_anon_in_0_a_bits_size (auto_bus_xing_in_0_a_bits_size), .auto_anon_in_0_a_bits_source (auto_bus_xing_in_0_a_bits_source), .auto_anon_in_0_a_bits_address (auto_bus_xing_in_0_a_bits_address), .auto_anon_in_0_a_bits_mask (auto_bus_xing_in_0_a_bits_mask), .auto_anon_in_0_a_bits_data (auto_bus_xing_in_0_a_bits_data), .auto_anon_in_0_a_bits_corrupt (auto_bus_xing_in_0_a_bits_corrupt), .auto_anon_in_0_d_ready (auto_bus_xing_in_0_d_ready), .auto_anon_in_0_d_valid (auto_bus_xing_in_0_d_valid), .auto_anon_in_0_d_bits_opcode (auto_bus_xing_in_0_d_bits_opcode), .auto_anon_in_0_d_bits_param (auto_bus_xing_in_0_d_bits_param), .auto_anon_in_0_d_bits_size (auto_bus_xing_in_0_d_bits_size), .auto_anon_in_0_d_bits_source (auto_bus_xing_in_0_d_bits_source), .auto_anon_in_0_d_bits_sink (auto_bus_xing_in_0_d_bits_sink), .auto_anon_in_0_d_bits_denied (auto_bus_xing_in_0_d_bits_denied), .auto_anon_in_0_d_bits_data (auto_bus_xing_in_0_d_bits_data), .auto_anon_in_0_d_bits_corrupt (auto_bus_xing_in_0_d_bits_corrupt), .auto_anon_out_1_a_ready (_picker_auto_in_1_a_ready), // @[ProbePicker.scala:69:28] .auto_anon_out_1_a_valid (_mbus_xbar_auto_anon_out_1_a_valid), .auto_anon_out_1_a_bits_opcode (_mbus_xbar_auto_anon_out_1_a_bits_opcode), .auto_anon_out_1_a_bits_param (_mbus_xbar_auto_anon_out_1_a_bits_param), .auto_anon_out_1_a_bits_size (_mbus_xbar_auto_anon_out_1_a_bits_size), .auto_anon_out_1_a_bits_source (_mbus_xbar_auto_anon_out_1_a_bits_source), .auto_anon_out_1_a_bits_address (_mbus_xbar_auto_anon_out_1_a_bits_address), .auto_anon_out_1_a_bits_mask (_mbus_xbar_auto_anon_out_1_a_bits_mask), .auto_anon_out_1_a_bits_data (_mbus_xbar_auto_anon_out_1_a_bits_data), .auto_anon_out_1_a_bits_corrupt (_mbus_xbar_auto_anon_out_1_a_bits_corrupt), .auto_anon_out_1_d_ready (_mbus_xbar_auto_anon_out_1_d_ready), .auto_anon_out_1_d_valid (_picker_auto_in_1_d_valid), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_opcode (_picker_auto_in_1_d_bits_opcode), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_param (_picker_auto_in_1_d_bits_param), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_size (_picker_auto_in_1_d_bits_size), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_source (_picker_auto_in_1_d_bits_source), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_sink (_picker_auto_in_1_d_bits_sink), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_denied (_picker_auto_in_1_d_bits_denied), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_data (_picker_auto_in_1_d_bits_data), // @[ProbePicker.scala:69:28] .auto_anon_out_1_d_bits_corrupt (_picker_auto_in_1_d_bits_corrupt), // @[ProbePicker.scala:69:28] .auto_anon_out_0_a_ready (_picker_auto_in_0_a_ready), // @[ProbePicker.scala:69:28] .auto_anon_out_0_a_valid (_mbus_xbar_auto_anon_out_0_a_valid), .auto_anon_out_0_a_bits_opcode (_mbus_xbar_auto_anon_out_0_a_bits_opcode), .auto_anon_out_0_a_bits_param (_mbus_xbar_auto_anon_out_0_a_bits_param), .auto_anon_out_0_a_bits_size (_mbus_xbar_auto_anon_out_0_a_bits_size), .auto_anon_out_0_a_bits_source (_mbus_xbar_auto_anon_out_0_a_bits_source), .auto_anon_out_0_a_bits_address (_mbus_xbar_auto_anon_out_0_a_bits_address), .auto_anon_out_0_a_bits_mask (_mbus_xbar_auto_anon_out_0_a_bits_mask), .auto_anon_out_0_a_bits_data (_mbus_xbar_auto_anon_out_0_a_bits_data), .auto_anon_out_0_a_bits_corrupt (_mbus_xbar_auto_anon_out_0_a_bits_corrupt), .auto_anon_out_0_d_ready (_mbus_xbar_auto_anon_out_0_d_ready), .auto_anon_out_0_d_valid (_picker_auto_in_0_d_valid), // @[ProbePicker.scala:69:28] .auto_anon_out_0_d_bits_opcode (_picker_auto_in_0_d_bits_opcode), // @[ProbePicker.scala:69:28] .auto_anon_out_0_d_bits_size (_picker_auto_in_0_d_bits_size), // @[ProbePicker.scala:69:28] .auto_anon_out_0_d_bits_source (_picker_auto_in_0_d_bits_source), // @[ProbePicker.scala:69:28] .auto_anon_out_0_d_bits_denied (_picker_auto_in_0_d_bits_denied), // @[ProbePicker.scala:69:28] .auto_anon_out_0_d_bits_data (_picker_auto_in_0_d_bits_data), // @[ProbePicker.scala:69:28] .auto_anon_out_0_d_bits_corrupt (_picker_auto_in_0_d_bits_corrupt) // @[ProbePicker.scala:69:28] ); // @[MemoryBus.scala:47:32] ProbePicker picker ( // @[ProbePicker.scala:69:28] .clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114] .reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114] .auto_in_1_a_ready (_picker_auto_in_1_a_ready), .auto_in_1_a_valid (_mbus_xbar_auto_anon_out_1_a_valid), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_opcode (_mbus_xbar_auto_anon_out_1_a_bits_opcode), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_param (_mbus_xbar_auto_anon_out_1_a_bits_param), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_size (_mbus_xbar_auto_anon_out_1_a_bits_size), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_source (_mbus_xbar_auto_anon_out_1_a_bits_source), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_address (_mbus_xbar_auto_anon_out_1_a_bits_address), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_mask (_mbus_xbar_auto_anon_out_1_a_bits_mask), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_data (_mbus_xbar_auto_anon_out_1_a_bits_data), // @[MemoryBus.scala:47:32] .auto_in_1_a_bits_corrupt (_mbus_xbar_auto_anon_out_1_a_bits_corrupt), // @[MemoryBus.scala:47:32] .auto_in_1_d_ready (_mbus_xbar_auto_anon_out_1_d_ready), // @[MemoryBus.scala:47:32] .auto_in_1_d_valid (_picker_auto_in_1_d_valid), .auto_in_1_d_bits_opcode (_picker_auto_in_1_d_bits_opcode), .auto_in_1_d_bits_param (_picker_auto_in_1_d_bits_param), .auto_in_1_d_bits_size (_picker_auto_in_1_d_bits_size), .auto_in_1_d_bits_source (_picker_auto_in_1_d_bits_source), .auto_in_1_d_bits_sink (_picker_auto_in_1_d_bits_sink), .auto_in_1_d_bits_denied (_picker_auto_in_1_d_bits_denied), .auto_in_1_d_bits_data (_picker_auto_in_1_d_bits_data), .auto_in_1_d_bits_corrupt (_picker_auto_in_1_d_bits_corrupt), .auto_in_0_a_ready (_picker_auto_in_0_a_ready), .auto_in_0_a_valid (_mbus_xbar_auto_anon_out_0_a_valid), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_opcode (_mbus_xbar_auto_anon_out_0_a_bits_opcode), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_param (_mbus_xbar_auto_anon_out_0_a_bits_param), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_size (_mbus_xbar_auto_anon_out_0_a_bits_size), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_source (_mbus_xbar_auto_anon_out_0_a_bits_source), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_address (_mbus_xbar_auto_anon_out_0_a_bits_address), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_mask (_mbus_xbar_auto_anon_out_0_a_bits_mask), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_data (_mbus_xbar_auto_anon_out_0_a_bits_data), // @[MemoryBus.scala:47:32] .auto_in_0_a_bits_corrupt (_mbus_xbar_auto_anon_out_0_a_bits_corrupt), // @[MemoryBus.scala:47:32] .auto_in_0_d_ready (_mbus_xbar_auto_anon_out_0_d_ready), // @[MemoryBus.scala:47:32] .auto_in_0_d_valid (_picker_auto_in_0_d_valid), .auto_in_0_d_bits_opcode (_picker_auto_in_0_d_bits_opcode), .auto_in_0_d_bits_size (_picker_auto_in_0_d_bits_size), .auto_in_0_d_bits_source (_picker_auto_in_0_d_bits_source), .auto_in_0_d_bits_denied (_picker_auto_in_0_d_bits_denied), .auto_in_0_d_bits_data (_picker_auto_in_0_d_bits_data), .auto_in_0_d_bits_corrupt (_picker_auto_in_0_d_bits_corrupt), .auto_out_1_a_ready (_buffer_1_auto_in_a_ready), // @[Buffer.scala:75:28] .auto_out_1_a_valid (_picker_auto_out_1_a_valid), .auto_out_1_a_bits_opcode (_picker_auto_out_1_a_bits_opcode), .auto_out_1_a_bits_param (_picker_auto_out_1_a_bits_param), .auto_out_1_a_bits_size (_picker_auto_out_1_a_bits_size), .auto_out_1_a_bits_source (_picker_auto_out_1_a_bits_source), .auto_out_1_a_bits_address (_picker_auto_out_1_a_bits_address), .auto_out_1_a_bits_mask (_picker_auto_out_1_a_bits_mask), .auto_out_1_a_bits_data (_picker_auto_out_1_a_bits_data), .auto_out_1_a_bits_corrupt (_picker_auto_out_1_a_bits_corrupt), .auto_out_1_d_ready (_picker_auto_out_1_d_ready), .auto_out_1_d_valid (_buffer_1_auto_in_d_valid), // @[Buffer.scala:75:28] .auto_out_1_d_bits_opcode (_buffer_1_auto_in_d_bits_opcode), // @[Buffer.scala:75:28] .auto_out_1_d_bits_param (_buffer_1_auto_in_d_bits_param), // @[Buffer.scala:75:28] .auto_out_1_d_bits_size (_buffer_1_auto_in_d_bits_size), // @[Buffer.scala:75:28] .auto_out_1_d_bits_source (_buffer_1_auto_in_d_bits_source), // @[Buffer.scala:75:28] .auto_out_1_d_bits_sink (_buffer_1_auto_in_d_bits_sink), // @[Buffer.scala:75:28] .auto_out_1_d_bits_denied (_buffer_1_auto_in_d_bits_denied), // @[Buffer.scala:75:28] .auto_out_1_d_bits_data (_buffer_1_auto_in_d_bits_data), // @[Buffer.scala:75:28] .auto_out_1_d_bits_corrupt (_buffer_1_auto_in_d_bits_corrupt), // @[Buffer.scala:75:28] .auto_out_0_a_ready (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_a_ready), // @[LazyScope.scala:98:27] .auto_out_0_a_valid (_picker_auto_out_0_a_valid), .auto_out_0_a_bits_opcode (_picker_auto_out_0_a_bits_opcode), .auto_out_0_a_bits_param (_picker_auto_out_0_a_bits_param), .auto_out_0_a_bits_size (_picker_auto_out_0_a_bits_size), .auto_out_0_a_bits_source (_picker_auto_out_0_a_bits_source), .auto_out_0_a_bits_address (_picker_auto_out_0_a_bits_address), .auto_out_0_a_bits_mask (_picker_auto_out_0_a_bits_mask), .auto_out_0_a_bits_data (_picker_auto_out_0_a_bits_data), .auto_out_0_a_bits_corrupt (_picker_auto_out_0_a_bits_corrupt), .auto_out_0_d_ready (_picker_auto_out_0_d_ready), .auto_out_0_d_valid (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_valid), // @[LazyScope.scala:98:27] .auto_out_0_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_out_0_d_bits_size (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_out_0_d_bits_source (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_out_0_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_denied), // @[LazyScope.scala:98:27] .auto_out_0_d_bits_data (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_out_0_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_corrupt) // @[LazyScope.scala:98:27] ); // @[ProbePicker.scala:69:28] TLInterconnectCoupler_mbus_to_memory_controller_port_named_axi4 coupler_to_memory_controller_port_named_axi4 ( // @[LazyScope.scala:98:27] .clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114] .reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114] .auto_widget_anon_in_a_ready (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_a_ready), .auto_widget_anon_in_a_valid (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_valid), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_opcode (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_opcode), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_param (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_param), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_size (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_size), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_source (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_source), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_address (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_address), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_mask (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_mask), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_data (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_data), // @[LazyScope.scala:98:27] .auto_widget_anon_in_a_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_corrupt), // @[LazyScope.scala:98:27] .auto_widget_anon_in_d_ready (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_d_ready), // @[LazyScope.scala:98:27] .auto_widget_anon_in_d_valid (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_valid), .auto_widget_anon_in_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_opcode), .auto_widget_anon_in_d_bits_size (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_size), .auto_widget_anon_in_d_bits_source (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_source), .auto_widget_anon_in_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_denied), .auto_widget_anon_in_d_bits_data (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_data), .auto_widget_anon_in_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_corrupt), .auto_axi4yank_out_aw_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_ready), .auto_axi4yank_out_aw_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_valid), .auto_axi4yank_out_aw_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_id), .auto_axi4yank_out_aw_bits_addr (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_addr), .auto_axi4yank_out_aw_bits_len (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_len), .auto_axi4yank_out_aw_bits_size (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_size), .auto_axi4yank_out_aw_bits_burst (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_burst), .auto_axi4yank_out_aw_bits_lock (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_lock), .auto_axi4yank_out_aw_bits_cache (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_cache), .auto_axi4yank_out_aw_bits_prot (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_prot), .auto_axi4yank_out_aw_bits_qos (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_aw_bits_qos), .auto_axi4yank_out_w_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_ready), .auto_axi4yank_out_w_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_valid), .auto_axi4yank_out_w_bits_data (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_data), .auto_axi4yank_out_w_bits_strb (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_strb), .auto_axi4yank_out_w_bits_last (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_w_bits_last), .auto_axi4yank_out_b_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_ready), .auto_axi4yank_out_b_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_valid), .auto_axi4yank_out_b_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_id), .auto_axi4yank_out_b_bits_resp (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_b_bits_resp), .auto_axi4yank_out_ar_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_ready), .auto_axi4yank_out_ar_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_valid), .auto_axi4yank_out_ar_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_id), .auto_axi4yank_out_ar_bits_addr (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_addr), .auto_axi4yank_out_ar_bits_len (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_len), .auto_axi4yank_out_ar_bits_size (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_size), .auto_axi4yank_out_ar_bits_burst (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_burst), .auto_axi4yank_out_ar_bits_lock (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_lock), .auto_axi4yank_out_ar_bits_cache (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_cache), .auto_axi4yank_out_ar_bits_prot (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_prot), .auto_axi4yank_out_ar_bits_qos (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_ar_bits_qos), .auto_axi4yank_out_r_ready (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_ready), .auto_axi4yank_out_r_valid (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_valid), .auto_axi4yank_out_r_bits_id (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_id), .auto_axi4yank_out_r_bits_data (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_data), .auto_axi4yank_out_r_bits_resp (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_resp), .auto_axi4yank_out_r_bits_last (auto_coupler_to_memory_controller_port_named_axi4_axi4yank_out_r_bits_last), .auto_tl_in_a_ready (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_a_ready), .auto_tl_in_a_valid (_picker_auto_out_0_a_valid), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_opcode (_picker_auto_out_0_a_bits_opcode), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_param (_picker_auto_out_0_a_bits_param), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_size (_picker_auto_out_0_a_bits_size), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_source (_picker_auto_out_0_a_bits_source), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_address (_picker_auto_out_0_a_bits_address), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_mask (_picker_auto_out_0_a_bits_mask), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_data (_picker_auto_out_0_a_bits_data), // @[ProbePicker.scala:69:28] .auto_tl_in_a_bits_corrupt (_picker_auto_out_0_a_bits_corrupt), // @[ProbePicker.scala:69:28] .auto_tl_in_d_ready (_picker_auto_out_0_d_ready), // @[ProbePicker.scala:69:28] .auto_tl_in_d_valid (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_valid), .auto_tl_in_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_opcode), .auto_tl_in_d_bits_size (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_size), .auto_tl_in_d_bits_source (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_source), .auto_tl_in_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_denied), .auto_tl_in_d_bits_data (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_data), .auto_tl_in_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_auto_tl_in_d_bits_corrupt), .auto_tl_out_a_ready (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_a_ready), // @[LazyScope.scala:98:27] .auto_tl_out_a_valid (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_valid), .auto_tl_out_a_bits_opcode (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_opcode), .auto_tl_out_a_bits_param (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_param), .auto_tl_out_a_bits_size (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_size), .auto_tl_out_a_bits_source (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_source), .auto_tl_out_a_bits_address (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_address), .auto_tl_out_a_bits_mask (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_mask), .auto_tl_out_a_bits_data (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_data), .auto_tl_out_a_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_a_bits_corrupt), .auto_tl_out_d_ready (_coupler_to_memory_controller_port_named_axi4_auto_tl_out_d_ready), .auto_tl_out_d_valid (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_valid), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_opcode (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_opcode), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_size (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_size), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_source (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_source), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_denied (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_denied), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_data (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_data), // @[LazyScope.scala:98:27] .auto_tl_out_d_bits_corrupt (_coupler_to_memory_controller_port_named_axi4_auto_widget_anon_in_d_bits_corrupt) // @[LazyScope.scala:98:27] ); // @[LazyScope.scala:98:27] TLBuffer_a28d64s7k1z3u buffer_1 ( // @[Buffer.scala:75:28] .clock (_fixedClockNode_auto_anon_out_0_clock), // @[ClockGroup.scala:115:114] .reset (_fixedClockNode_auto_anon_out_0_reset), // @[ClockGroup.scala:115:114] .auto_in_a_ready (_buffer_1_auto_in_a_ready), .auto_in_a_valid (_picker_auto_out_1_a_valid), // @[ProbePicker.scala:69:28] .auto_in_a_bits_opcode (_picker_auto_out_1_a_bits_opcode), // @[ProbePicker.scala:69:28] .auto_in_a_bits_param (_picker_auto_out_1_a_bits_param), // @[ProbePicker.scala:69:28] .auto_in_a_bits_size (_picker_auto_out_1_a_bits_size), // @[ProbePicker.scala:69:28] .auto_in_a_bits_source (_picker_auto_out_1_a_bits_source), // @[ProbePicker.scala:69:28] .auto_in_a_bits_address (_picker_auto_out_1_a_bits_address), // @[ProbePicker.scala:69:28] .auto_in_a_bits_mask (_picker_auto_out_1_a_bits_mask), // @[ProbePicker.scala:69:28] .auto_in_a_bits_data (_picker_auto_out_1_a_bits_data), // @[ProbePicker.scala:69:28] .auto_in_a_bits_corrupt (_picker_auto_out_1_a_bits_corrupt), // @[ProbePicker.scala:69:28] .auto_in_d_ready (_picker_auto_out_1_d_ready), // @[ProbePicker.scala:69:28] .auto_in_d_valid (_buffer_1_auto_in_d_valid), .auto_in_d_bits_opcode (_buffer_1_auto_in_d_bits_opcode), .auto_in_d_bits_param (_buffer_1_auto_in_d_bits_param), .auto_in_d_bits_size (_buffer_1_auto_in_d_bits_size), .auto_in_d_bits_source (_buffer_1_auto_in_d_bits_source), .auto_in_d_bits_sink (_buffer_1_auto_in_d_bits_sink), .auto_in_d_bits_denied (_buffer_1_auto_in_d_bits_denied), .auto_in_d_bits_data (_buffer_1_auto_in_d_bits_data), .auto_in_d_bits_corrupt (_buffer_1_auto_in_d_bits_corrupt), .auto_out_a_ready (auto_buffer_out_a_ready), .auto_out_a_valid (auto_buffer_out_a_valid), .auto_out_a_bits_opcode (auto_buffer_out_a_bits_opcode), .auto_out_a_bits_param (auto_buffer_out_a_bits_param), .auto_out_a_bits_size (auto_buffer_out_a_bits_size), .auto_out_a_bits_source (auto_buffer_out_a_bits_source), .auto_out_a_bits_address (auto_buffer_out_a_bits_address), .auto_out_a_bits_mask (auto_buffer_out_a_bits_mask), .auto_out_a_bits_data (auto_buffer_out_a_bits_data), .auto_out_a_bits_corrupt (auto_buffer_out_a_bits_corrupt), .auto_out_d_ready (auto_buffer_out_d_ready), .auto_out_d_valid (auto_buffer_out_d_valid), .auto_out_d_bits_opcode (auto_buffer_out_d_bits_opcode), .auto_out_d_bits_param (auto_buffer_out_d_bits_param), .auto_out_d_bits_size (auto_buffer_out_d_bits_size), .auto_out_d_bits_source (auto_buffer_out_d_bits_source), .auto_out_d_bits_sink (auto_buffer_out_d_bits_sink), .auto_out_d_bits_denied (auto_buffer_out_d_bits_denied), .auto_out_d_bits_data (auto_buffer_out_d_bits_data), .auto_out_d_bits_corrupt (auto_buffer_out_d_bits_corrupt) ); // @[Buffer.scala:75:28] endmodule
Generate the Verilog code corresponding to the following Chisel files. File ShiftReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ // Similar to the Chisel ShiftRegister but allows the user to suggest a // name to the registers that get instantiated, and // to provide a reset value. object ShiftRegInit { def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T = (0 until n).foldRight(in) { case (i, next) => { val r = RegNext(next, init) name.foreach { na => r.suggestName(s"${na}_${i}") } r } } } /** These wrap behavioral * shift registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * The different types vary in their reset behavior: * AsyncResetShiftReg -- Asynchronously reset register array * A W(width) x D(depth) sized array is constructed from D instantiations of a * W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg, * but only used for timing applications / abstract class AbstractPipelineReg(w: Int = 1) extends Module { val io = IO(new Bundle { val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) } ) } object AbstractPipelineReg { def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = { val chain = Module(gen) name.foreach{ chain.suggestName(_) } chain.io.d := in.asUInt chain.io.q.asTypeOf(in) } } class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) { require(depth > 0, "Depth must be greater than 0.") override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}" val chain = List.tabulate(depth) { i => Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}") } chain.last.io.d := io.d chain.last.io.en := true.B (chain.init zip chain.tail).foreach { case (sink, source) => sink.io.d := source.io.q sink.io.en := true.B } io.q := chain.head.io.q } object AsyncResetShiftReg { def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name) def apply [T <: Data](in: T, depth: Int, name: Option[String]): T = apply(in, depth, 0, name) def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T = apply(in, depth, init.litValue.toInt, name) def apply [T <: Data](in: T, depth: Int, init: T): T = apply (in, depth, init.litValue.toInt, None) } File SynchronizerReg.scala: // See LICENSE.SiFive for license details. package freechips.rocketchip.util import chisel3._ import chisel3.util.{RegEnable, Cat} /* These wrap behavioral * shift and next registers into specific modules to allow for * backend flows to replace or constrain * them properly when used for CDC synchronization, * rather than buffering. * * * These are built up of ResetSynchronizerPrimitiveShiftReg, intended to be replaced by the integrator's metastable flops chains or replaced * at this level if they have a multi-bit wide synchronizer primitive. * The different types vary in their reset behavior: * NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin * AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep * 1-bit-wide shift registers. * SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg * * [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference. * * ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross * Clock Domains. */ object SynchronizerResetType extends Enumeration { val NonSync, Inferred, Sync, Async = Value } // Note: this should not be used directly. // Use the companion object to generate this with the correct reset type mixin. private class SynchronizerPrimitiveShiftReg( sync: Int, init: Boolean, resetType: SynchronizerResetType.Value) extends AbstractPipelineReg(1) { val initInt = if (init) 1 else 0 val initPostfix = resetType match { case SynchronizerResetType.NonSync => "" case _ => s"_i${initInt}" } override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}" val chain = List.tabulate(sync) { i => val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B) reg.suggestName(s"sync_$i") } chain.last := io.d.asBool (chain.init zip chain.tail).foreach { case (sink, source) => sink := source } io.q := chain.head.asUInt } private object SynchronizerPrimitiveShiftReg { def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = { val gen: () => SynchronizerPrimitiveShiftReg = resetType match { case SynchronizerResetType.NonSync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) case SynchronizerResetType.Async => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset case SynchronizerResetType.Sync => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset case SynchronizerResetType.Inferred => () => new SynchronizerPrimitiveShiftReg(sync, init, resetType) } AbstractPipelineReg(gen(), in) } } // Note: This module may end up with a non-AsyncReset type reset. // But the Primitives within will always have AsyncReset type. class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asAsyncReset){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async) } } io.q := Cat(output.reverse) } object AsyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } // Note: This module may end up with a non-Bool type reset. // But the Primitives within will always have Bool reset type. @deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2") class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 withReset(reset.asBool){ SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync) } } io.q := Cat(output.reverse) } object SyncResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}" val output = Seq.tabulate(w) { i => val initBit = ((init >> i) & 1) > 0 SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred) } io.q := Cat(output.reverse) } object ResetSynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T = AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name) def apply [T <: Data](in: T, sync: Int, name: Option[String]): T = apply (in, sync, 0, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, 0, None) def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T = apply(in, sync, init.litValue.toInt, name) def apply [T <: Data](in: T, sync: Int, init: T): T = apply (in, sync, init.litValue.toInt, None) } class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) { require(sync > 1, s"Sync must be greater than 1, not ${sync}.") override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}" val output = Seq.tabulate(w) { i => SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync) } io.q := Cat(output.reverse) } object SynchronizerShiftReg { def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T = if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name) def apply [T <: Data](in: T, sync: Int): T = apply (in, sync, None) def apply [T <: Data](in: T): T = apply (in, 3, None) } class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module { override def desiredName = s"ClockCrossingReg_w${w}" val io = IO(new Bundle{ val d = Input(UInt(w.W)) val q = Output(UInt(w.W)) val en = Input(Bool()) }) val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en) io.q := cdc_reg } object ClockCrossingReg { def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = { val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit)) name.foreach{ cdc_reg.suggestName(_) } cdc_reg.io.d := in.asUInt cdc_reg.io.en := en cdc_reg.io.q.asTypeOf(in) } }	module AsyncResetSynchronizerShiftReg_w1_d3_i0_52( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_64 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to the following Chisel files. File InputUnit.scala: package constellation.router import chisel3._ import chisel3.util._ import org.chipsalliance.cde.config.{Field, Parameters} import freechips.rocketchip.util._ import constellation.channel._ import constellation.routing.{FlowRoutingBundle} import constellation.noc.{HasNoCParams} class AbstractInputUnitIO( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams], )(implicit val p: Parameters) extends Bundle with HasRouterOutputParams { val nodeId = cParam.destId val router_req = Decoupled(new RouteComputerReq) val router_resp = Input(new RouteComputerResp(outParams, egressParams)) val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams)) val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams)) val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })) val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams))) val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams))) val debug = Output(new Bundle { val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W) }) val block = Input(Bool()) } abstract class AbstractInputUnit( val cParam: BaseChannelParams, val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams] )(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams { val nodeId = cParam.destId def io: AbstractInputUnitIO } class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module { val nVirtualChannels = cParam.nVirtualChannels val io = IO(new Bundle { val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits)))) val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits))) }) val useOutputQueues = cParam.useOutputQueues val delims = if (useOutputQueues) { cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_) } else { // If no queuing, have to add an additional slot since head == tail implies empty // TODO this should be fixed, should use all slots available cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_) } val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val ends = delims.tail.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) s else 0 } val fullSize = delims.last // Ugly case. Use multiple queues if ((cParam.srcSpeedup > 1 \|\| cParam.destSpeedup > 1 \|\| fullSize <= 1) \|\| !cParam.unifiedBuffer) { require(useOutputQueues) val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize))) qs.zipWithIndex.foreach { case (q,i) => val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U) q.io.enq.valid := sel.orR q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head)) q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail)) q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload)) io.deq(i) <> q.io.deq } } else { val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits)) val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W)))) val empty = (heads zip tails).map(t => t._1 === t._2) val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) } qs.foreach(_.io.enq.valid := false.B) qs.foreach(_.io.enq.bits := DontCare) val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id) val flit = Wire(new BaseFlit(cParam.payloadBits)) val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B flit.head := io.enq(0).bits.head flit.tail := io.enq(0).bits.tail flit.payload := io.enq(0).bits.payload when (io.enq(0).valid && !direct_to_q) { val tail = tails(io.enq(0).bits.virt_channel_id) mem.write(tail, flit) tails(io.enq(0).bits.virt_channel_id) := Mux( tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(vc_sel, starts.map(_.U)), tail + 1.U) } .elsewhen (io.enq(0).valid && direct_to_q) { for (i <- 0 until nVirtualChannels) { when (io.enq(0).bits.virt_channel_id === i.U) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := flit } } } if (useOutputQueues) { val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready } val to_q_oh = PriorityEncoderOH(can_to_q) val to_q = OHToUInt(to_q_oh) when (can_to_q.orR) { val head = Mux1H(to_q_oh, heads) heads(to_q) := Mux( head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(to_q_oh, starts.map(_.U)), head + 1.U) for (i <- 0 until nVirtualChannels) { when (to_q_oh(i)) { qs(i).io.enq.valid := true.B qs(i).io.enq.bits := mem.read(head) } } } for (i <- 0 until nVirtualChannels) { io.deq(i) <> qs(i).io.deq } } else { qs.map(_.io.deq.ready := false.B) val ready_sel = io.deq.map(_.ready) val fire = io.deq.map(_.fire) assert(PopCount(fire) <= 1.U) val head = Mux1H(fire, heads) when (fire.orR) { val fire_idx = OHToUInt(fire) heads(fire_idx) := Mux( head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)), Mux1H(fire, starts.map(_.U)), head + 1.U) } val read_flit = mem.read(head) for (i <- 0 until nVirtualChannels) { io.deq(i).valid := !empty(i) io.deq(i).bits := read_flit } } } } class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams], egressParams: Seq[EgressChannelParams], combineRCVA: Boolean, combineSAST: Boolean ) (implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) { val nVirtualChannels = cParam.nVirtualChannels val virtualChannelParams = cParam.virtualChannelParams class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) { val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams])) } val io = IO(new InputUnitIO) val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5) class InputState extends Bundle { val g = UInt(3.W) val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }) val flow = new FlowRoutingBundle val fifo_deps = UInt(nVirtualChannels.W) } val input_buffer = Module(new InputBuffer(cParam)) for (i <- 0 until cParam.srcSpeedup) { input_buffer.io.enq(i) := io.in.flit(i) } input_buffer.io.deq.foreach(_.ready := false.B) val route_arbiter = Module(new Arbiter( new RouteComputerReq, nVirtualChannels )) io.router_req <> route_arbiter.io.out val states = Reg(Vec(nVirtualChannels, new InputState)) val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_\|\|_) val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_) if (anyFifo) { val idle_mask = VecInit(states.map(_.g === g_i)).asUInt for (s <- states) for (i <- 0 until nVirtualChannels) s.fifo_deps := s.fifo_deps & ~idle_mask } for (i <- 0 until cParam.srcSpeedup) { when (io.in.flit(i).fire && io.in.flit(i).bits.head) { val id = io.in.flit(i).bits.virt_channel_id assert(id < nVirtualChannels.U) assert(states(id).g === g_i) val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U states(id).g := Mux(at_dest, g_v, g_r) states(id).vc_sel.foreach(_.foreach(_ := false.B)) for (o <- 0 until nEgress) { when (o.U === io.in.flit(i).bits.flow.egress_node_id) { states(id).vc_sel(o+nOutputs)(0) := true.B } } states(id).flow := io.in.flit(i).bits.flow if (anyFifo) { val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) => s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id }).asUInt } } } (route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) => if (virtualChannelParams(idx).traversable) { i.valid := s.g === g_r i.bits.flow := s.flow i.bits.src_virt_id := idx.U when (i.fire) { s.g := g_v } } else { i.valid := false.B i.bits := DontCare } } when (io.router_req.fire) { val id = io.router_req.bits.src_virt_id assert(states(id).g === g_r) states(id).g := g_v for (i <- 0 until nVirtualChannels) { when (i.U === id) { states(i).vc_sel := io.router_resp.vc_sel } } } val mask = RegInit(0.U(nVirtualChannels.W)) val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams))) val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool())) val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask)) val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) \| (vcalloc_filter >> nVirtualChannels) // Prioritize incoming packetes when (io.router_req.fire) { mask := (1.U << io.router_req.bits.src_virt_id) - 1.U } .elsewhen (vcalloc_vals.orR) { mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) }) } io.vcalloc_req.valid := vcalloc_vals.orR io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs) states.zipWithIndex.map { case (s,idx) => if (virtualChannelParams(idx).traversable) { vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U vcalloc_reqs(idx).in_vc := idx.U vcalloc_reqs(idx).vc_sel := s.vc_sel vcalloc_reqs(idx).flow := s.flow when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a } if (combineRCVA) { when (route_arbiter.io.in(idx).fire) { vcalloc_vals(idx) := true.B vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel } } } else { vcalloc_vals(idx) := false.B vcalloc_reqs(idx) := DontCare } } io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready when (io.vcalloc_req.fire) { for (i <- 0 until nVirtualChannels) { when (vcalloc_sel(i)) { states(i).vc_sel := io.vcalloc_resp.vc_sel states(i).g := g_a if (!combineRCVA) { assert(states(i).g === g_v) } } } } val salloc_arb = Module(new SwitchArbiter( nVirtualChannels, cParam.destSpeedup, outParams, egressParams )) (states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) => if (virtualChannelParams(i).traversable) { val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid r.bits.vc_sel := s.vc_sel val deq_tail = input_buffer.io.deq(i).bits.tail r.bits.tail := deq_tail when (r.fire && deq_tail) { s.g := g_i } input_buffer.io.deq(i).ready := r.ready } else { r.valid := false.B r.bits := DontCare } } io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready)) io.salloc_req <> salloc_arb.io.out when (io.block) { salloc_arb.io.out.foreach(_.ready := false.B) io.salloc_req.foreach(_.valid := false.B) } class OutBundle extends Bundle { val valid = Bool() val vid = UInt(virtualChannelBits.W) val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W) val flit = new Flit(cParam.payloadBits) } val salloc_outs = if (combineSAST) { Wire(Vec(cParam.destSpeedup, new OutBundle)) } else { Reg(Vec(cParam.destSpeedup, new OutBundle)) } io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) => Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)), salloc_arb.io.chosen_oh(i), 0.U) }.reduce(_\|_) for (i <- 0 until cParam.destSpeedup) { val salloc_out = salloc_outs(i) salloc_out.valid := salloc_arb.io.out(i).fire salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i)) val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel)) val channel_oh = vc_sel.map(_.reduce(_\|\|_)).toSeq val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq) when (salloc_arb.io.out(i).fire) { salloc_out.out_vid := virt_channel salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload)) salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head)) salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)) salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow)) } .otherwise { salloc_out.out_vid := DontCare salloc_out.flit := DontCare } salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch io.out(i).valid := salloc_out.valid io.out(i).bits.flit := salloc_out.flit io.out(i).bits.out_virt_channel := salloc_out.out_vid } def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = { if (virtualChannelParams(srcV).traversable) { outParams.zipWithIndex.map { case (oP, oI) => (0 until oP.nVirtualChannels).map { oV => var allow = false virtualChannelParams(srcV).possibleFlows.foreach { pI => allow = allow \|\| routingRelation( cParam.channelRoutingInfos(srcV), oP.channelRoutingInfos(oV), pI ) } if (!allow) sel(oI)(oV) := false.B } } } } (0 until nVirtualChannels).map { i => if (!virtualChannelParams(i).traversable) states(i) := DontCare filterVCSel(states(i).vc_sel, i) } when (reset.asBool) { states.foreach(_.g := g_i) } }	module InputUnit_17( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [1:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_5_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_5_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_2, // @[InputUnit.scala:170:14] input io_out_credit_available_5_0, // @[InputUnit.scala:170:14] input io_out_credit_available_4_0, // @[InputUnit.scala:170:14] input io_out_credit_available_3_0, // @[InputUnit.scala:170:14] input io_out_credit_available_3_1, // @[InputUnit.scala:170:14] input io_out_credit_available_3_2, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_1, // @[InputUnit.scala:170:14] input io_out_credit_available_1_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_0, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_5_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [144:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [1:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [1:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [144:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [2:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [2:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire _GEN; // @[MixedVec.scala:116:9] wire _GEN_0; // @[MixedVec.scala:116:9] wire vcalloc_reqs_2_vc_sel_3_2; // @[MixedVec.scala:116:9] wire vcalloc_vals_2; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _GEN_1; // @[MixedVec.scala:116:9] wire _GEN_2; // @[MixedVec.scala:116:9] wire vcalloc_reqs_1_vc_sel_3_1; // @[MixedVec.scala:116:9] wire vcalloc_vals_1; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _GEN_3; // @[MixedVec.scala:116:9] wire _GEN_4; // @[MixedVec.scala:116:9] wire vcalloc_reqs_0_vc_sel_3_0; // @[MixedVec.scala:116:9] wire vcalloc_vals_0; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [2:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [1:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_0_g; // @[InputUnit.scala:192:19] reg states_0_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_3_0; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_3_1; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_3_2; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN_5 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:158:7, :192:19, :229:22] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:158:7, :192:19, :229:22] wire _GEN_6 = _route_arbiter_io_in_1_ready & route_arbiter_io_in_1_valid; // @[Decoupled.scala:51:35] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:158:7, :192:19, :229:22] wire _GEN_7 = _route_arbiter_io_in_2_ready & route_arbiter_io_in_2_valid; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to the following Chisel files. File MSHR.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import freechips.rocketchip.tilelink._ import TLPermissions._ import TLMessages._ import MetaData._ import chisel3.PrintableHelper import chisel3.experimental.dataview._ class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val a = Valid(new SourceARequest(params)) val b = Valid(new SourceBRequest(params)) val c = Valid(new SourceCRequest(params)) val d = Valid(new SourceDRequest(params)) val e = Valid(new SourceERequest(params)) val x = Valid(new SourceXRequest(params)) val dir = Valid(new DirectoryWrite(params)) val reload = Bool() // get next request via allocate (if any) } class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val way = UInt(params.wayBits.W) val blockB = Bool() val nestB = Bool() val blockC = Bool() val nestC = Bool() } class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params) { val set = UInt(params.setBits.W) val tag = UInt(params.tagBits.W) val b_toN = Bool() // nested Probes may unhit us val b_toB = Bool() // nested Probes may demote us val b_clr_dirty = Bool() // nested Probes clear dirty val c_set_dirty = Bool() // nested Releases MAY set dirty } sealed trait CacheState { val code = CacheState.index.U CacheState.index = CacheState.index + 1 } object CacheState { var index = 0 } case object S_INVALID extends CacheState case object S_BRANCH extends CacheState case object S_BRANCH_C extends CacheState case object S_TIP extends CacheState case object S_TIP_C extends CacheState case object S_TIP_CD extends CacheState case object S_TIP_D extends CacheState case object S_TRUNK_C extends CacheState case object S_TRUNK_CD extends CacheState class MSHR(params: InclusiveCacheParameters) extends Module { val io = IO(new Bundle { val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup val status = Valid(new MSHRStatus(params)) val schedule = Decoupled(new ScheduleRequest(params)) val sinkc = Flipped(Valid(new SinkCResponse(params))) val sinkd = Flipped(Valid(new SinkDResponse(params))) val sinke = Flipped(Valid(new SinkEResponse(params))) val nestedwb = Flipped(new NestedWriteback(params)) }) val request_valid = RegInit(false.B) val request = Reg(new FullRequest(params)) val meta_valid = RegInit(false.B) val meta = Reg(new DirectoryResult(params)) // Define which states are valid when (meta_valid) { when (meta.state === INVALID) { assert (!meta.clients.orR) assert (!meta.dirty) } when (meta.state === BRANCH) { assert (!meta.dirty) } when (meta.state === TRUNK) { assert (meta.clients.orR) assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one } when (meta.state === TIP) { // noop } } // Completed transitions (s_ = scheduled), (w_ = waiting) val s_rprobe = RegInit(true.B) // B val w_rprobeackfirst = RegInit(true.B) val w_rprobeacklast = RegInit(true.B) val s_release = RegInit(true.B) // CW w_rprobeackfirst val w_releaseack = RegInit(true.B) val s_pprobe = RegInit(true.B) // B val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1] val s_flush = RegInit(true.B) // X w_releaseack val w_grantfirst = RegInit(true.B) val w_grantlast = RegInit(true.B) val w_grant = RegInit(true.B) // first \| last depending on wormhole val w_pprobeackfirst = RegInit(true.B) val w_pprobeacklast = RegInit(true.B) val w_pprobeack = RegInit(true.B) // first \| last depending on wormhole val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_) val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD val s_execute = RegInit(true.B) // D w_pprobeack, w_grant val w_grantack = RegInit(true.B) val s_writeback = RegInit(true.B) // W w_* // [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall) // However, inB and outC are higher priority than outB, so s_release and s_pprobe // may be safely issued while blockB. Thus we must NOT try to schedule the // potentially stuck s_acquire with either of them (scheduler is all or none). // Meta-data that we discover underway val sink = Reg(UInt(params.outer.bundle.sinkBits.W)) val gotT = Reg(Bool()) val bad_grant = Reg(Bool()) val probes_done = Reg(UInt(params.clientBits.W)) val probes_toN = Reg(UInt(params.clientBits.W)) val probes_noT = Reg(Bool()) // When a nested transaction completes, update our meta data when (meta_valid && meta.state =/= INVALID && io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) { when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B } when (io.nestedwb.c_set_dirty) { meta.dirty := true.B } when (io.nestedwb.b_toB) { meta.state := BRANCH } when (io.nestedwb.b_toN) { meta.hit := false.B } } // Scheduler status io.status.valid := request_valid io.status.bits.set := request.set io.status.bits.tag := request.tag io.status.bits.way := meta.way io.status.bits.blockB := !meta_valid \|\| ((!w_releaseack \|\| !w_rprobeacklast \|\| !w_pprobeacklast) && !w_grantfirst) io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst // The above rules ensure we will block and not nest an outer probe while still doing our // own inner probes. Thus every probe wakes exactly one MSHR. io.status.bits.blockC := !meta_valid io.status.bits.nestC := meta_valid && (!w_rprobeackfirst \|\| !w_pprobeackfirst \|\| !w_grantfirst) // The w_grantfirst in nestC is necessary to deal with: // acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock // ... this is possible because the release+probe can be for same set, but different tag // We can only demand: block, nest, or queue assert (!io.status.bits.nestB \|\| !io.status.bits.blockB) assert (!io.status.bits.nestC \|\| !io.status.bits.blockC) // Scheduler requests val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe io.schedule.bits.b.valid := !s_rprobe \|\| !s_pprobe io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) \|\| (!s_probeack && w_pprobeackfirst) io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant io.schedule.bits.e.valid := !s_grantack && w_grantfirst io.schedule.bits.x.valid := !s_flush && w_releaseack io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) \|\| (!s_writeback && no_wait) io.schedule.bits.reload := no_wait io.schedule.valid := io.schedule.bits.a.valid \|\| io.schedule.bits.b.valid \|\| io.schedule.bits.c.valid \|\| io.schedule.bits.d.valid \|\| io.schedule.bits.e.valid \|\| io.schedule.bits.x.valid \|\| io.schedule.bits.dir.valid // Schedule completions when (io.schedule.ready) { s_rprobe := true.B when (w_rprobeackfirst) { s_release := true.B } s_pprobe := true.B when (s_release && s_pprobe) { s_acquire := true.B } when (w_releaseack) { s_flush := true.B } when (w_pprobeackfirst) { s_probeack := true.B } when (w_grantfirst) { s_grantack := true.B } when (w_pprobeack && w_grant) { s_execute := true.B } when (no_wait) { s_writeback := true.B } // Await the next operation when (no_wait) { request_valid := false.B meta_valid := false.B } } // Resulting meta-data val final_meta_writeback = WireInit(meta) val req_clientBit = params.clientBit(request.source) val req_needT = needT(request.opcode, request.param) val req_acquire = request.opcode === AcquireBlock \|\| request.opcode === AcquirePerm val meta_no_clients = !meta.clients.orR val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT) when (request.prio(2) && (!params.firstLevel).B) { // always a hit final_meta_writeback.dirty := meta.dirty \|\| request.opcode(0) final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state) final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U) final_meta_writeback.hit := true.B // chained requests are hits } .elsewhen (request.control && params.control.B) { // request.prio(0) when (meta.hit) { final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := meta.clients & ~probes_toN } final_meta_writeback.hit := false.B } .otherwise { final_meta_writeback.dirty := (meta.hit && meta.dirty) \|\| !request.opcode(2) final_meta_writeback.state := Mux(req_needT, Mux(req_acquire, TRUNK, TIP), Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH), MuxLookup(meta.state, 0.U(2.W))(Seq( INVALID -> BRANCH, BRANCH -> BRANCH, TRUNK -> TIP, TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP))))) final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) \| Mux(req_acquire, req_clientBit, 0.U) final_meta_writeback.tag := request.tag final_meta_writeback.hit := true.B } when (bad_grant) { when (meta.hit) { // upgrade failed (B -> T) assert (!meta_valid \|\| meta.state === BRANCH) final_meta_writeback.hit := true.B final_meta_writeback.dirty := false.B final_meta_writeback.state := BRANCH final_meta_writeback.clients := meta.clients & ~probes_toN } .otherwise { // failed N -> (T or B) final_meta_writeback.hit := false.B final_meta_writeback.dirty := false.B final_meta_writeback.state := INVALID final_meta_writeback.clients := 0.U } } val invalid = Wire(new DirectoryEntry(params)) invalid.dirty := false.B invalid.state := INVALID invalid.clients := 0.U invalid.tag := 0.U // Just because a client says BtoT, by the time we process the request he may be N. // Therefore, we must consult our own meta-data state to confirm he owns the line still. val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR // The client asking us to act is proof they don't have permissions. val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U) io.schedule.bits.a.bits.tag := request.tag io.schedule.bits.a.bits.set := request.set io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB) io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U \|\| !(request.opcode === PutFullData \|\| request.opcode === AcquirePerm) io.schedule.bits.a.bits.source := 0.U io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB))) io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag) io.schedule.bits.b.bits.set := request.set io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release) io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN) io.schedule.bits.c.bits.source := 0.U io.schedule.bits.c.bits.tag := meta.tag io.schedule.bits.c.bits.set := request.set io.schedule.bits.c.bits.way := meta.way io.schedule.bits.c.bits.dirty := meta.dirty io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param, MuxLookup(request.param, request.param)(Seq( NtoB -> Mux(req_promoteT, NtoT, NtoB), BtoT -> Mux(honour_BtoT, BtoT, NtoT), NtoT -> NtoT))) io.schedule.bits.d.bits.sink := 0.U io.schedule.bits.d.bits.way := meta.way io.schedule.bits.d.bits.bad := bad_grant io.schedule.bits.e.bits.sink := sink io.schedule.bits.x.bits.fail := false.B io.schedule.bits.dir.bits.set := request.set io.schedule.bits.dir.bits.way := meta.way io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback)) // Coverage of state transitions def cacheState(entry: DirectoryEntry, hit: Bool) = { val out = WireDefault(0.U) val c = entry.clients.orR val d = entry.dirty switch (entry.state) { is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) } is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) } is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) } is (INVALID) { out := S_INVALID.code } } when (!hit) { out := S_INVALID.code } out } val p = !params.lastLevel // can be probed val c = !params.firstLevel // can be acquired val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read) val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist val f = params.control // flush control register exists val cfg = (p, c, m, r, f) val b = r \|\| p // can reach branch state (via probe downgrade or read-only device) // The cache must be used for something or we would not be here require(c \|\| m) val evict = cacheState(meta, !meta.hit) val before = cacheState(meta, meta.hit) val after = cacheState(final_meta_writeback, true.B) def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}") } else { assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}") } if (cover && f) { params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}") } else { assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}") } } def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}") } else { assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}") } } when ((!s_release && w_rprobeackfirst) && io.schedule.ready) { eviction(S_BRANCH, b) // MMIO read to read-only device eviction(S_BRANCH_C, b && c) // you need children to become C eviction(S_TIP, true) // MMIO read \|\| clean release can lead to this state eviction(S_TIP_C, c) // needs two clients \|\| client + mmio \|\| downgrading client eviction(S_TIP_CD, c) // needs two clients \|\| client + mmio \|\| downgrading client eviction(S_TIP_D, true) // MMIO write \|\| dirty release lead here eviction(S_TRUNK_C, c) // acquire for write eviction(S_TRUNK_CD, c) // dirty release then reacquire } when ((!s_writeback && no_wait) && io.schedule.ready) { transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches transition(S_INVALID, S_TIP, m) // MMIO read transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_INVALID, S_TIP_D, m) // MMIO write transition(S_INVALID, S_TRUNK_C, c) // acquire transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions) transition(S_BRANCH, S_BRANCH_C, b && c) // acquire transition(S_BRANCH, S_TIP, b && m) // prefetch write transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH, S_TIP_D, b && m) // MMIO write transition(S_BRANCH, S_TRUNK_C, b && c) // acquire transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_BRANCH_C, S_INVALID, b && c && p) transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional) transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately transition(S_TIP, S_INVALID, p) transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately transition(S_TIP, S_TRUNK_C, c) // acquire transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately transition(S_TIP_C, S_INVALID, c && p) transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TIP_C, S_TIP, c) // probed while MMIO read \|\| clean release (optional) transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients transition(S_TIP_C, S_TRUNK_C, c) // acquire transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty transition(S_TIP_D, S_INVALID, p) transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared transition(S_TIP_D, S_TIP, p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired transition(S_TIP_D, S_TRUNK_CD, c) // acquire transition(S_TIP_CD, S_INVALID, c && p) transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TIP_CD, S_TIP_D, c) // MMIO write \|\| clean release (optional) transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire transition(S_TIP_CD, S_TRUNK_CD, c) // acquire transition(S_TRUNK_C, S_INVALID, c && p) transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe transition(S_TRUNK_C, S_TIP, c) // MMIO read \|\| clean release (optional) transition(S_TRUNK_C, S_TIP_C, c) // bounce shared transition(S_TRUNK_C, S_TIP_D, c) // dirty release transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce transition(S_TRUNK_CD, S_INVALID, c && p) transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read \|\| outer probe.toT (optional) transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead transition(S_TRUNK_CD, S_TIP_D, c) // dirty release transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire } // Handle response messages val probe_bit = params.clientBit(io.sinkc.bits.source) val last_probe = (probes_done \| probe_bit) === (meta.clients & ~excluded_client) val probe_toN = isToN(io.sinkc.bits.param) if (!params.firstLevel) when (io.sinkc.valid) { params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B") params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B") // Caution: the probe matches us only in set. // We would never allow an outer probe to nest until both w_[rp]probeack complete, so // it is safe to just unguardedly update the probe FSM. probes_done := probes_done \| probe_bit probes_toN := probes_toN \| Mux(probe_toN, probe_bit, 0.U) probes_noT := probes_noT \|\| io.sinkc.bits.param =/= TtoT w_rprobeackfirst := w_rprobeackfirst \|\| last_probe w_rprobeacklast := w_rprobeacklast \|\| (last_probe && io.sinkc.bits.last) w_pprobeackfirst := w_pprobeackfirst \|\| last_probe w_pprobeacklast := w_pprobeacklast \|\| (last_probe && io.sinkc.bits.last) // Allow wormhole routing from sinkC if the first request beat has offset 0 val set_pprobeack = last_probe && (io.sinkc.bits.last \|\| request.offset === 0.U) w_pprobeack := w_pprobeack \|\| set_pprobeack params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data") params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data") // However, meta-data updates need to be done more cautiously when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!! } when (io.sinkd.valid) { when (io.sinkd.bits.opcode === Grant \|\| io.sinkd.bits.opcode === GrantData) { sink := io.sinkd.bits.sink w_grantfirst := true.B w_grantlast := io.sinkd.bits.last // Record if we need to prevent taking ownership bad_grant := io.sinkd.bits.denied // Allow wormhole routing for requests whose first beat has offset 0 w_grant := request.offset === 0.U \|\| io.sinkd.bits.last params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data") params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data") gotT := io.sinkd.bits.param === toT } .elsewhen (io.sinkd.bits.opcode === ReleaseAck) { w_releaseack := true.B } } when (io.sinke.valid) { w_grantack := true.B } // Bootstrap new requests val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits) val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits) val new_request = Mux(io.allocate.valid, allocate_as_full, request) val new_needT = needT(new_request.opcode, new_request.param) val new_clientBit = params.clientBit(new_request.source) val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U) val prior = cacheState(final_meta_writeback, true.B) def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) { if (cover) { params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}") } else { assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}") } } when (io.allocate.valid && io.allocate.bits.repeat) { bypass(S_INVALID, f \|\| p) // Can lose permissions (probe/flush) bypass(S_BRANCH, b) // MMIO read to read-only device bypass(S_BRANCH_C, b && c) // you need children to become C bypass(S_TIP, true) // MMIO read \|\| clean release can lead to this state bypass(S_TIP_C, c) // needs two clients \|\| client + mmio \|\| downgrading client bypass(S_TIP_CD, c) // needs two clients \|\| client + mmio \|\| downgrading client bypass(S_TIP_D, true) // MMIO write \|\| dirty release lead here bypass(S_TRUNK_C, c) // acquire for write bypass(S_TRUNK_CD, c) // dirty release then reacquire } when (io.allocate.valid) { assert (!request_valid \|\| (no_wait && io.schedule.fire)) request_valid := true.B request := io.allocate.bits } // Create execution plan when (io.directory.valid \|\| (io.allocate.valid && io.allocate.bits.repeat)) { meta_valid := true.B meta := new_meta probes_done := 0.U probes_toN := 0.U probes_noT := false.B gotT := false.B bad_grant := false.B // These should already be either true or turning true // We clear them here explicitly to simplify the mux tree s_rprobe := true.B w_rprobeackfirst := true.B w_rprobeacklast := true.B s_release := true.B w_releaseack := true.B s_pprobe := true.B s_acquire := true.B s_flush := true.B w_grantfirst := true.B w_grantlast := true.B w_grant := true.B w_pprobeackfirst := true.B w_pprobeacklast := true.B w_pprobeack := true.B s_probeack := true.B s_grantack := true.B s_execute := true.B w_grantack := true.B s_writeback := true.B // For C channel requests (ie: Release[Data]) when (new_request.prio(2) && (!params.firstLevel).B) { s_execute := false.B // Do we need to go dirty? when (new_request.opcode(0) && !new_meta.dirty) { s_writeback := false.B } // Does our state change? when (isToB(new_request.param) && new_meta.state === TRUNK) { s_writeback := false.B } // Do our clients change? when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) { s_writeback := false.B } assert (new_meta.hit) } // For X channel requests (ie: flush) .elsewhen (new_request.control && params.control.B) { // new_request.prio(0) s_flush := false.B // Do we need to actually do something? when (new_meta.hit) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } } // For A channel requests .otherwise { // new_request.prio(0) && !new_request.control s_execute := false.B // Do we need an eviction? when (!new_meta.hit && new_meta.state =/= INVALID) { s_release := false.B w_releaseack := false.B // Do we need to shoot-down inner caches? when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) { s_rprobe := false.B w_rprobeackfirst := false.B w_rprobeacklast := false.B } } // Do we need an acquire? when (!new_meta.hit \|\| (new_meta.state === BRANCH && new_needT)) { s_acquire := false.B w_grantfirst := false.B w_grantlast := false.B w_grant := false.B s_grantack := false.B s_writeback := false.B } // Do we need a probe? when ((!params.firstLevel).B && (new_meta.hit && (new_needT \|\| new_meta.state === TRUNK) && (new_meta.clients & ~new_skipProbe) =/= 0.U)) { s_pprobe := false.B w_pprobeackfirst := false.B w_pprobeacklast := false.B w_pprobeack := false.B s_writeback := false.B } // Do we need a grantack? when (new_request.opcode === AcquireBlock \|\| new_request.opcode === AcquirePerm) { w_grantack := false.B s_writeback := false.B } // Becomes dirty? when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) { s_writeback := false.B } } } } File Parameters.scala: /* * Copyright 2019 SiFive, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You should have received a copy of LICENSE.Apache2 along with * this software. If not, you may obtain a copy at * * https://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. / package sifive.blocks.inclusivecache import chisel3._ import chisel3.util._ import chisel3.experimental.SourceInfo import org.chipsalliance.cde.config._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.util._ import freechips.rocketchip.util.property.cover import scala.math.{min,max} case class CacheParameters( level: Int, ways: Int, sets: Int, blockBytes: Int, beatBytes: Int, // inner hintsSkipProbe: Boolean) { require (ways > 0) require (sets > 0) require (blockBytes > 0 && isPow2(blockBytes)) require (beatBytes > 0 && isPow2(beatBytes)) require (blockBytes >= beatBytes) val blocks = ways sets val sizeBytes = blocks * blockBytes val blockBeats = blockBytes/beatBytes } case class InclusiveCachePortParameters( a: BufferParams, b: BufferParams, c: BufferParams, d: BufferParams, e: BufferParams) { def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e)) } object InclusiveCachePortParameters { val none = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.none) val full = InclusiveCachePortParameters( a = BufferParams.default, b = BufferParams.default, c = BufferParams.default, d = BufferParams.default, e = BufferParams.default) // This removes feed-through paths from C=>A and A=>C val fullC = InclusiveCachePortParameters( a = BufferParams.none, b = BufferParams.none, c = BufferParams.default, d = BufferParams.none, e = BufferParams.none) val flowAD = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.flow, e = BufferParams.none) val flowAE = InclusiveCachePortParameters( a = BufferParams.flow, b = BufferParams.none, c = BufferParams.none, d = BufferParams.none, e = BufferParams.flow) // For innerBuf: // SinkA: no restrictions, flows into scheduler+putbuffer // SourceB: no restrictions, flows out of scheduler // sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore // SourceD: no restrictions, flows out of bankedStore/regout // SinkE: no restrictions, flows into scheduler // // ... so while none is possible, you probably want at least flowAC to cut ready // from the scheduler delay and flowD to ease SourceD back-pressure // For outerBufer: // SourceA: must not be pipe, flows out of scheduler // SinkB: no restrictions, flows into scheduler // SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored // SinkD: no restrictions, flows into scheduler & bankedStore // SourceE: must not be pipe, flows out of scheduler // // ... AE take the channel ready into the scheduler, so you need at least flowAE } case class InclusiveCacheMicroParameters( writeBytes: Int, // backing store update granularity memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz) portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes dirReg: Boolean = false, innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE { require (writeBytes > 0 && isPow2(writeBytes)) require (memCycles > 0) require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant } case class InclusiveCacheControlParameters( address: BigInt, beatBytes: Int, bankedControl: Boolean) case class InclusiveCacheParameters( cache: CacheParameters, micro: InclusiveCacheMicroParameters, control: Boolean, inner: TLEdgeIn, outer: TLEdgeOut)(implicit val p: Parameters) { require (cache.ways > 1) require (cache.sets > 1 && isPow2(cache.sets)) require (micro.writeBytes <= inner.manager.beatBytes) require (micro.writeBytes <= outer.manager.beatBytes) require (inner.manager.beatBytes <= cache.blockBytes) require (outer.manager.beatBytes <= cache.blockBytes) // Require that all cached address ranges have contiguous blocks outer.manager.managers.flatMap(_.address).foreach { a => require (a.alignment >= cache.blockBytes) } // If we are the first level cache, we do not need to support inner-BCE val firstLevel = !inner.client.clients.exists(_.supports.probe) // If we are the last level cache, we do not need to support outer-B val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED) require (lastLevel) // Provision enough resources to achieve full throughput with missing single-beat accesses val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro) val secondary = max(mshrs, micro.memCycles - mshrs) val putLists = micro.memCycles // allow every request to be single beat val putBeats = max(2cache.blockBeats, micro.memCycles) val relLists = 2 val relBeats = relListscache.blockBeats val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address)) val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_\|_)) def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] = if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail) val addressMapping = bitOffsets(pickMask) val addressBits = addressMapping.size // println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}") val allClients = inner.client.clients.size val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size val clientBits = max(1, clientBitsRaw) val stateBits = 2 val wayBits = log2Ceil(cache.ways) val setBits = log2Ceil(cache.sets) val offsetBits = log2Ceil(cache.blockBytes) val tagBits = addressBits - setBits - offsetBits val putBits = log2Ceil(max(putLists, relLists)) require (tagBits > 0) require (offsetBits > 0) val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1 val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1 val innerMaskBits = inner.manager.beatBytes / micro.writeBytes val outerMaskBits = outer.manager.beatBytes / micro.writeBytes def clientBit(source: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse) } } def clientSource(bit: UInt): UInt = { if (clientBitsRaw == 0) { 0.U } else { Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U)) } } def parseAddress(x: UInt): (UInt, UInt, UInt) = { val offset = Cat(addressMapping.map(o => x(o,o)).reverse) val set = offset >> offsetBits val tag = set >> setBits (tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0)) } def widen(x: UInt, width: Int): UInt = { val y = x \| 0.U(width.W) assert (y >> width === 0.U) y(width-1, 0) } def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = { val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits)) val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) } addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) } Cat(bits.reverse) } def restoreAddress(expanded: UInt): UInt = { val missingBits = flatAddresses .map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match .groupBy(_._1) .view .mapValues(_.map(_._2)) val muxMask = AddressDecoder(missingBits.values.toList) val mux = missingBits.toList.map { case (bits, addrs) => val widen = addrs.map(_.widen(~muxMask)) val matches = AddressSet .unify(widen.distinct) .map(_.contains(expanded)) .reduce(_ \|\| _) (matches, bits.U) } expanded \| Mux1H(mux) } def dirReg[T <: Data](x: T, en: Bool = true.B): T = { if (micro.dirReg) RegEnable(x, en) else x } def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc) } object MetaData { val stateBits = 2 def INVALID: UInt = 0.U(stateBits.W) // way is empty def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch // Does a request need trunk? def needT(opcode: UInt, param: UInt): Bool = { !opcode(2) \|\| (opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) \|\| ((opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB) } // Does a request prove the client need not be probed? def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = { // Acquire(toB) and Get => is N, so no probe // Acquire(toT) => is N or B, but need T, so no probe // Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client // Put => is N or B, so probe IS needed opcode === TLMessages.AcquireBlock \|\| opcode === TLMessages.AcquirePerm \|\| opcode === TLMessages.Get \|\| (opcode === TLMessages.Hint && hintsSkipProbe.B) } def isToN(param: UInt): Bool = { param === TLPermissions.TtoN \|\| param === TLPermissions.BtoN \|\| param === TLPermissions.NtoN } def isToB(param: UInt): Bool = { param === TLPermissions.TtoB \|\| param === TLPermissions.BtoB } } object InclusiveCacheParameters { val lfsrBits = 10 val L2ControlAddress = 0x2010000 val L2ControlSize = 0x1000 def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = { // We need 2-3 normal MSHRs to cover the Directory latency // To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats) } def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = // We need a dedicated MSHR for B+C each 2 + out_mshrs(cache, micro) } class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle	module MSHR_3( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input [5:0] io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire [5:0] final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire [5:0] io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [5:0] invalid_clients = 6'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire [5:0] _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire [5:0] _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg [5:0] meta_clients; // @[MSHR.scala:100:17] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg [5:0] probes_done; // @[MSHR.scala:150:24] reg [5:0] probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 \| _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 \| _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T \| _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T \| _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 \| _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T \| _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 \| _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 \| io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T \| io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 \| io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 \| io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 \| io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 \| io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire [5:0] _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire _req_clientBit_T = request_source == 6'h24; // @[Parameters.scala:46:9] wire _req_clientBit_T_1 = request_source == 6'h2E; // @[Parameters.scala:46:9] wire _req_clientBit_T_2 = request_source == 6'h2C; // @[Parameters.scala:46:9] wire _req_clientBit_T_3 = request_source == 6'h2A; // @[Parameters.scala:46:9] wire _req_clientBit_T_4 = request_source == 6'h28; // @[Parameters.scala:46:9] wire _req_clientBit_T_5 = request_source == 6'h20; // @[Parameters.scala:46:9] wire [1:0] req_clientBit_lo_hi = {_req_clientBit_T_2, _req_clientBit_T_1}; // @[Parameters.scala:46:9] wire [2:0] req_clientBit_lo = {req_clientBit_lo_hi, _req_clientBit_T}; // @[Parameters.scala:46:9] wire [1:0] req_clientBit_hi_hi = {_req_clientBit_T_5, _req_clientBit_T_4}; // @[Parameters.scala:46:9] wire [2:0] req_clientBit_hi = {req_clientBit_hi_hi, _req_clientBit_T_3}; // @[Parameters.scala:46:9] wire [5:0] req_clientBit = {req_clientBit_hi, req_clientBit_lo}; // @[Parameters.scala:201:10] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 \| _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 \| _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = \|request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 \| _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T \| _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire _meta_no_clients_T = \|meta_clients; // @[MSHR.scala:100:17, :220:39] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty \| _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T \| _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 \| _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire [5:0] _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 ? req_clientBit : 6'h0; // @[Parameters.scala:201:10, :282:66] wire [5:0] _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire [5:0] _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire [5:0] _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire [5:0] _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 \| _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire [5:0] _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire [5:0] _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire [5:0] _final_meta_writeback_clients_T_12 = meta_hit ? _final_meta_writeback_clients_T_11 : 6'h0; // @[MSHR.scala:100:17, :245:{40,64}] wire [5:0] _final_meta_writeback_clients_T_13 = req_acquire ? req_clientBit : 6'h0; // @[Parameters.scala:201:10] wire [5:0] _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 \| _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 \| request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire [5:0] _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire [5:0] _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 \| ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? (meta_hit ? _final_meta_writeback_clients_T_16 : 6'h0) : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire [5:0] _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:201:10] wire _honour_BtoT_T_1 = \|_honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 \| _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 \| _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire [5:0] excluded_client = _excluded_client_T_9 ? req_clientBit : 6'h0; // @[Parameters.scala:201:10] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 \| _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T \| _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire [5:0] _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(\|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = _io_schedule_bits_dir_bits_data_T ? 6'h0 : _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire evict_c = \|meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire before_c = \|meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(\|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire after_c = \|final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _probe_bit_T = io_sinkc_bits_source_0 == 6'h24; // @[Parameters.scala:46:9] wire _probe_bit_T_1 = io_sinkc_bits_source_0 == 6'h2E; // @[Parameters.scala:46:9] wire _probe_bit_T_2 = io_sinkc_bits_source_0 == 6'h2C; // @[Parameters.scala:46:9] wire _probe_bit_T_3 = io_sinkc_bits_source_0 == 6'h2A; // @[Parameters.scala:46:9] wire _probe_bit_T_4 = io_sinkc_bits_source_0 == 6'h28; // @[Parameters.scala:46:9] wire _probe_bit_T_5 = io_sinkc_bits_source_0 == 6'h20; // @[Parameters.scala:46:9] wire [1:0] probe_bit_lo_hi = {_probe_bit_T_2, _probe_bit_T_1}; // @[Parameters.scala:46:9] wire [2:0] probe_bit_lo = {probe_bit_lo_hi, _probe_bit_T}; // @[Parameters.scala:46:9] wire [1:0] probe_bit_hi_hi = {_probe_bit_T_5, _probe_bit_T_4}; // @[Parameters.scala:46:9] wire [2:0] probe_bit_hi = {probe_bit_hi_hi, _probe_bit_T_3}; // @[Parameters.scala:46:9] wire [5:0] probe_bit = {probe_bit_hi, probe_bit_lo}; // @[Parameters.scala:201:10] wire [5:0] _GEN_15 = probes_done \| probe_bit; // @[Parameters.scala:201:10] wire [5:0] _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire [5:0] _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire [5:0] _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire [5:0] _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T \| _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 \| _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire [5:0] _probes_toN_T = probe_toN ? probe_bit : 6'h0; // @[Parameters.scala:201:10, :282:66] wire [5:0] _probes_toN_T_1 = probes_toN \| _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT \| _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst \| last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast \| _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst \| last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast \| _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 \| _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack \| set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(\|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T \| io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [5:0] new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 \| _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 \| _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = \|new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 \| _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _new_clientBit_T = new_request_source == 6'h24; // @[Parameters.scala:46:9] wire _new_clientBit_T_1 = new_request_source == 6'h2E; // @[Parameters.scala:46:9] wire _new_clientBit_T_2 = new_request_source == 6'h2C; // @[Parameters.scala:46:9] wire _new_clientBit_T_3 = new_request_source == 6'h2A; // @[Parameters.scala:46:9] wire _new_clientBit_T_4 = new_request_source == 6'h28; // @[Parameters.scala:46:9] wire _new_clientBit_T_5 = new_request_source == 6'h20; // @[Parameters.scala:46:9] wire [1:0] new_clientBit_lo_hi = {_new_clientBit_T_2, _new_clientBit_T_1}; // @[Parameters.scala:46:9] wire [2:0] new_clientBit_lo = {new_clientBit_lo_hi, _new_clientBit_T}; // @[Parameters.scala:46:9] wire [1:0] new_clientBit_hi_hi = {_new_clientBit_T_5, _new_clientBit_T_4}; // @[Parameters.scala:46:9] wire [2:0] new_clientBit_hi = {new_clientBit_hi_hi, _new_clientBit_T_3}; // @[Parameters.scala:46:9] wire [5:0] new_clientBit = {new_clientBit_hi, new_clientBit_lo}; // @[Parameters.scala:201:10] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T \| _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 \| _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire [5:0] new_skipProbe = _new_skipProbe_T_7 ? new_clientBit : 6'h0; // @[Parameters.scala:201:10, :279:106] wire [3:0] prior; // @[MSHR.scala:314:26] wire prior_c = \|final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 \| _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]